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//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// RDY_set_verbosity O 1 const
// v_from_masters_0_awready O 1 reg
// v_from_masters_0_wready O 1 reg
// v_from_masters_0_bvalid O 1 reg
// v_from_masters_0_bid O 16 reg
// v_from_masters_0_bresp O 2 reg
// v_from_masters_0_arready O 1 reg
// v_from_masters_0_rvalid O 1 reg
// v_from_masters_0_rid O 16 reg
// v_from_masters_0_rdata O 64 reg
// v_from_masters_0_rresp O 2 reg
// v_from_masters_0_rlast O 1 reg
// v_to_slaves_0_awvalid O 1 reg
// v_to_slaves_0_awid O 16 reg
// v_to_slaves_0_awaddr O 64 reg
// v_to_slaves_0_awlen O 8 reg
// v_to_slaves_0_awsize O 3 reg
// v_to_slaves_0_awburst O 2 reg
// v_to_slaves_0_awlock O 1 reg
// v_to_slaves_0_awcache O 4 reg
// v_to_slaves_0_awprot O 3 reg
// v_to_slaves_0_awqos O 4 reg
// v_to_slaves_0_awregion O 4 reg
// v_to_slaves_0_wvalid O 1 reg
// v_to_slaves_0_wdata O 64 reg
// v_to_slaves_0_wstrb O 8 reg
// v_to_slaves_0_wlast O 1 reg
// v_to_slaves_0_bready O 1 reg
// v_to_slaves_0_arvalid O 1 reg
// v_to_slaves_0_arid O 16 reg
// v_to_slaves_0_araddr O 64 reg
// v_to_slaves_0_arlen O 8 reg
// v_to_slaves_0_arsize O 3 reg
// v_to_slaves_0_arburst O 2 reg
// v_to_slaves_0_arlock O 1 reg
// v_to_slaves_0_arcache O 4 reg
// v_to_slaves_0_arprot O 3 reg
// v_to_slaves_0_arqos O 4 reg
// v_to_slaves_0_arregion O 4 reg
// v_to_slaves_0_rready O 1 reg
// v_to_slaves_1_awvalid O 1 reg
// v_to_slaves_1_awid O 16 reg
// v_to_slaves_1_awaddr O 64 reg
// v_to_slaves_1_awlen O 8 reg
// v_to_slaves_1_awsize O 3 reg
// v_to_slaves_1_awburst O 2 reg
// v_to_slaves_1_awlock O 1 reg
// v_to_slaves_1_awcache O 4 reg
// v_to_slaves_1_awprot O 3 reg
// v_to_slaves_1_awqos O 4 reg
// v_to_slaves_1_awregion O 4 reg
// v_to_slaves_1_wvalid O 1 reg
// v_to_slaves_1_wdata O 64 reg
// v_to_slaves_1_wstrb O 8 reg
// v_to_slaves_1_wlast O 1 reg
// v_to_slaves_1_bready O 1 reg
// v_to_slaves_1_arvalid O 1 reg
// v_to_slaves_1_arid O 16 reg
// v_to_slaves_1_araddr O 64 reg
// v_to_slaves_1_arlen O 8 reg
// v_to_slaves_1_arsize O 3 reg
// v_to_slaves_1_arburst O 2 reg
// v_to_slaves_1_arlock O 1 reg
// v_to_slaves_1_arcache O 4 reg
// v_to_slaves_1_arprot O 3 reg
// v_to_slaves_1_arqos O 4 reg
// v_to_slaves_1_arregion O 4 reg
// v_to_slaves_1_rready O 1 reg
// v_to_slaves_2_awvalid O 1 reg
// v_to_slaves_2_awid O 16 reg
// v_to_slaves_2_awaddr O 64 reg
// v_to_slaves_2_awlen O 8 reg
// v_to_slaves_2_awsize O 3 reg
// v_to_slaves_2_awburst O 2 reg
// v_to_slaves_2_awlock O 1 reg
// v_to_slaves_2_awcache O 4 reg
// v_to_slaves_2_awprot O 3 reg
// v_to_slaves_2_awqos O 4 reg
// v_to_slaves_2_awregion O 4 reg
// v_to_slaves_2_wvalid O 1 reg
// v_to_slaves_2_wdata O 64 reg
// v_to_slaves_2_wstrb O 8 reg
// v_to_slaves_2_wlast O 1 reg
// v_to_slaves_2_bready O 1 reg
// v_to_slaves_2_arvalid O 1 reg
// v_to_slaves_2_arid O 16 reg
// v_to_slaves_2_araddr O 64 reg
// v_to_slaves_2_arlen O 8 reg
// v_to_slaves_2_arsize O 3 reg
// v_to_slaves_2_arburst O 2 reg
// v_to_slaves_2_arlock O 1 reg
// v_to_slaves_2_arcache O 4 reg
// v_to_slaves_2_arprot O 3 reg
// v_to_slaves_2_arqos O 4 reg
// v_to_slaves_2_arregion O 4 reg
// v_to_slaves_2_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// v_from_masters_0_awvalid I 1
// v_from_masters_0_awid I 16 reg
// v_from_masters_0_awaddr I 64 reg
// v_from_masters_0_awlen I 8 reg
// v_from_masters_0_awsize I 3 reg
// v_from_masters_0_awburst I 2 reg
// v_from_masters_0_awlock I 1 reg
// v_from_masters_0_awcache I 4 reg
// v_from_masters_0_awprot I 3 reg
// v_from_masters_0_awqos I 4 reg
// v_from_masters_0_awregion I 4 reg
// v_from_masters_0_wvalid I 1
// v_from_masters_0_wdata I 64 reg
// v_from_masters_0_wstrb I 8 reg
// v_from_masters_0_wlast I 1 reg
// v_from_masters_0_bready I 1
// v_from_masters_0_arvalid I 1
// v_from_masters_0_arid I 16 reg
// v_from_masters_0_araddr I 64 reg
// v_from_masters_0_arlen I 8 reg
// v_from_masters_0_arsize I 3 reg
// v_from_masters_0_arburst I 2 reg
// v_from_masters_0_arlock I 1 reg
// v_from_masters_0_arcache I 4 reg
// v_from_masters_0_arprot I 3 reg
// v_from_masters_0_arqos I 4 reg
// v_from_masters_0_arregion I 4 reg
// v_from_masters_0_rready I 1
// v_to_slaves_0_awready I 1
// v_to_slaves_0_wready I 1
// v_to_slaves_0_bvalid I 1
// v_to_slaves_0_bid I 16 reg
// v_to_slaves_0_bresp I 2 reg
// v_to_slaves_0_arready I 1
// v_to_slaves_0_rvalid I 1
// v_to_slaves_0_rid I 16 reg
// v_to_slaves_0_rdata I 64 reg
// v_to_slaves_0_rresp I 2 reg
// v_to_slaves_0_rlast I 1 reg
// v_to_slaves_1_awready I 1
// v_to_slaves_1_wready I 1
// v_to_slaves_1_bvalid I 1
// v_to_slaves_1_bid I 16 reg
// v_to_slaves_1_bresp I 2 reg
// v_to_slaves_1_arready I 1
// v_to_slaves_1_rvalid I 1
// v_to_slaves_1_rid I 16 reg
// v_to_slaves_1_rdata I 64 reg
// v_to_slaves_1_rresp I 2 reg
// v_to_slaves_1_rlast I 1 reg
// v_to_slaves_2_awready I 1
// v_to_slaves_2_wready I 1
// v_to_slaves_2_bvalid I 1
// v_to_slaves_2_bid I 16 reg
// v_to_slaves_2_bresp I 2 reg
// v_to_slaves_2_arready I 1
// v_to_slaves_2_rvalid I 1
// v_to_slaves_2_rid I 16 reg
// v_to_slaves_2_rdata I 64 reg
// v_to_slaves_2_rresp I 2 reg
// v_to_slaves_2_rlast I 1 reg
// EN_reset I 1
// EN_set_verbosity I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFabric_1x3(CLK,
RST_N,
EN_reset,
RDY_reset,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
v_from_masters_0_awvalid,
v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion,
v_from_masters_0_awready,
v_from_masters_0_wvalid,
v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast,
v_from_masters_0_wready,
v_from_masters_0_bvalid,
v_from_masters_0_bid,
v_from_masters_0_bresp,
v_from_masters_0_bready,
v_from_masters_0_arvalid,
v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion,
v_from_masters_0_arready,
v_from_masters_0_rvalid,
v_from_masters_0_rid,
v_from_masters_0_rdata,
v_from_masters_0_rresp,
v_from_masters_0_rlast,
v_from_masters_0_rready,
v_to_slaves_0_awvalid,
v_to_slaves_0_awid,
v_to_slaves_0_awaddr,
v_to_slaves_0_awlen,
v_to_slaves_0_awsize,
v_to_slaves_0_awburst,
v_to_slaves_0_awlock,
v_to_slaves_0_awcache,
v_to_slaves_0_awprot,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_0_awready,
v_to_slaves_0_wvalid,
v_to_slaves_0_wdata,
v_to_slaves_0_wstrb,
v_to_slaves_0_wlast,
v_to_slaves_0_wready,
v_to_slaves_0_bvalid,
v_to_slaves_0_bid,
v_to_slaves_0_bresp,
v_to_slaves_0_bready,
v_to_slaves_0_arvalid,
v_to_slaves_0_arid,
v_to_slaves_0_araddr,
v_to_slaves_0_arlen,
v_to_slaves_0_arsize,
v_to_slaves_0_arburst,
v_to_slaves_0_arlock,
v_to_slaves_0_arcache,
v_to_slaves_0_arprot,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_arready,
v_to_slaves_0_rvalid,
v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast,
v_to_slaves_0_rready,
v_to_slaves_1_awvalid,
v_to_slaves_1_awid,
v_to_slaves_1_awaddr,
v_to_slaves_1_awlen,
v_to_slaves_1_awsize,
v_to_slaves_1_awburst,
v_to_slaves_1_awlock,
v_to_slaves_1_awcache,
v_to_slaves_1_awprot,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_1_awready,
v_to_slaves_1_wvalid,
v_to_slaves_1_wdata,
v_to_slaves_1_wstrb,
v_to_slaves_1_wlast,
v_to_slaves_1_wready,
v_to_slaves_1_bvalid,
v_to_slaves_1_bid,
v_to_slaves_1_bresp,
v_to_slaves_1_bready,
v_to_slaves_1_arvalid,
v_to_slaves_1_arid,
v_to_slaves_1_araddr,
v_to_slaves_1_arlen,
v_to_slaves_1_arsize,
v_to_slaves_1_arburst,
v_to_slaves_1_arlock,
v_to_slaves_1_arcache,
v_to_slaves_1_arprot,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_arready,
v_to_slaves_1_rvalid,
v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast,
v_to_slaves_1_rready,
v_to_slaves_2_awvalid,
v_to_slaves_2_awid,
v_to_slaves_2_awaddr,
v_to_slaves_2_awlen,
v_to_slaves_2_awsize,
v_to_slaves_2_awburst,
v_to_slaves_2_awlock,
v_to_slaves_2_awcache,
v_to_slaves_2_awprot,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion,
v_to_slaves_2_awready,
v_to_slaves_2_wvalid,
v_to_slaves_2_wdata,
v_to_slaves_2_wstrb,
v_to_slaves_2_wlast,
v_to_slaves_2_wready,
v_to_slaves_2_bvalid,
v_to_slaves_2_bid,
v_to_slaves_2_bresp,
v_to_slaves_2_bready,
v_to_slaves_2_arvalid,
v_to_slaves_2_arid,
v_to_slaves_2_araddr,
v_to_slaves_2_arlen,
v_to_slaves_2_arsize,
v_to_slaves_2_arburst,
v_to_slaves_2_arlock,
v_to_slaves_2_arcache,
v_to_slaves_2_arprot,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_arready,
v_to_slaves_2_rvalid,
v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast,
v_to_slaves_2_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method v_from_masters_0_m_awvalid
input v_from_masters_0_awvalid;
input [15 : 0] v_from_masters_0_awid;
input [63 : 0] v_from_masters_0_awaddr;
input [7 : 0] v_from_masters_0_awlen;
input [2 : 0] v_from_masters_0_awsize;
input [1 : 0] v_from_masters_0_awburst;
input v_from_masters_0_awlock;
input [3 : 0] v_from_masters_0_awcache;
input [2 : 0] v_from_masters_0_awprot;
input [3 : 0] v_from_masters_0_awqos;
input [3 : 0] v_from_masters_0_awregion;
// value method v_from_masters_0_m_awready
output v_from_masters_0_awready;
// action method v_from_masters_0_m_wvalid
input v_from_masters_0_wvalid;
input [63 : 0] v_from_masters_0_wdata;
input [7 : 0] v_from_masters_0_wstrb;
input v_from_masters_0_wlast;
// value method v_from_masters_0_m_wready
output v_from_masters_0_wready;
// value method v_from_masters_0_m_bvalid
output v_from_masters_0_bvalid;
// value method v_from_masters_0_m_bid
output [15 : 0] v_from_masters_0_bid;
// value method v_from_masters_0_m_bresp
output [1 : 0] v_from_masters_0_bresp;
// value method v_from_masters_0_m_buser
// action method v_from_masters_0_m_bready
input v_from_masters_0_bready;
// action method v_from_masters_0_m_arvalid
input v_from_masters_0_arvalid;
input [15 : 0] v_from_masters_0_arid;
input [63 : 0] v_from_masters_0_araddr;
input [7 : 0] v_from_masters_0_arlen;
input [2 : 0] v_from_masters_0_arsize;
input [1 : 0] v_from_masters_0_arburst;
input v_from_masters_0_arlock;
input [3 : 0] v_from_masters_0_arcache;
input [2 : 0] v_from_masters_0_arprot;
input [3 : 0] v_from_masters_0_arqos;
input [3 : 0] v_from_masters_0_arregion;
// value method v_from_masters_0_m_arready
output v_from_masters_0_arready;
// value method v_from_masters_0_m_rvalid
output v_from_masters_0_rvalid;
// value method v_from_masters_0_m_rid
output [15 : 0] v_from_masters_0_rid;
// value method v_from_masters_0_m_rdata
output [63 : 0] v_from_masters_0_rdata;
// value method v_from_masters_0_m_rresp
output [1 : 0] v_from_masters_0_rresp;
// value method v_from_masters_0_m_rlast
output v_from_masters_0_rlast;
// value method v_from_masters_0_m_ruser
// action method v_from_masters_0_m_rready
input v_from_masters_0_rready;
// value method v_to_slaves_0_m_awvalid
output v_to_slaves_0_awvalid;
// value method v_to_slaves_0_m_awid
output [15 : 0] v_to_slaves_0_awid;
// value method v_to_slaves_0_m_awaddr
output [63 : 0] v_to_slaves_0_awaddr;
// value method v_to_slaves_0_m_awlen
output [7 : 0] v_to_slaves_0_awlen;
// value method v_to_slaves_0_m_awsize
output [2 : 0] v_to_slaves_0_awsize;
// value method v_to_slaves_0_m_awburst
output [1 : 0] v_to_slaves_0_awburst;
// value method v_to_slaves_0_m_awlock
output v_to_slaves_0_awlock;
// value method v_to_slaves_0_m_awcache
output [3 : 0] v_to_slaves_0_awcache;
// value method v_to_slaves_0_m_awprot
output [2 : 0] v_to_slaves_0_awprot;
// value method v_to_slaves_0_m_awqos
output [3 : 0] v_to_slaves_0_awqos;
// value method v_to_slaves_0_m_awregion
output [3 : 0] v_to_slaves_0_awregion;
// value method v_to_slaves_0_m_awuser
// action method v_to_slaves_0_m_awready
input v_to_slaves_0_awready;
// value method v_to_slaves_0_m_wvalid
output v_to_slaves_0_wvalid;
// value method v_to_slaves_0_m_wdata
output [63 : 0] v_to_slaves_0_wdata;
// value method v_to_slaves_0_m_wstrb
output [7 : 0] v_to_slaves_0_wstrb;
// value method v_to_slaves_0_m_wlast
output v_to_slaves_0_wlast;
// value method v_to_slaves_0_m_wuser
// action method v_to_slaves_0_m_wready
input v_to_slaves_0_wready;
// action method v_to_slaves_0_m_bvalid
input v_to_slaves_0_bvalid;
input [15 : 0] v_to_slaves_0_bid;
input [1 : 0] v_to_slaves_0_bresp;
// value method v_to_slaves_0_m_bready
output v_to_slaves_0_bready;
// value method v_to_slaves_0_m_arvalid
output v_to_slaves_0_arvalid;
// value method v_to_slaves_0_m_arid
output [15 : 0] v_to_slaves_0_arid;
// value method v_to_slaves_0_m_araddr
output [63 : 0] v_to_slaves_0_araddr;
// value method v_to_slaves_0_m_arlen
output [7 : 0] v_to_slaves_0_arlen;
// value method v_to_slaves_0_m_arsize
output [2 : 0] v_to_slaves_0_arsize;
// value method v_to_slaves_0_m_arburst
output [1 : 0] v_to_slaves_0_arburst;
// value method v_to_slaves_0_m_arlock
output v_to_slaves_0_arlock;
// value method v_to_slaves_0_m_arcache
output [3 : 0] v_to_slaves_0_arcache;
// value method v_to_slaves_0_m_arprot
output [2 : 0] v_to_slaves_0_arprot;
// value method v_to_slaves_0_m_arqos
output [3 : 0] v_to_slaves_0_arqos;
// value method v_to_slaves_0_m_arregion
output [3 : 0] v_to_slaves_0_arregion;
// value method v_to_slaves_0_m_aruser
// action method v_to_slaves_0_m_arready
input v_to_slaves_0_arready;
// action method v_to_slaves_0_m_rvalid
input v_to_slaves_0_rvalid;
input [15 : 0] v_to_slaves_0_rid;
input [63 : 0] v_to_slaves_0_rdata;
input [1 : 0] v_to_slaves_0_rresp;
input v_to_slaves_0_rlast;
// value method v_to_slaves_0_m_rready
output v_to_slaves_0_rready;
// value method v_to_slaves_1_m_awvalid
output v_to_slaves_1_awvalid;
// value method v_to_slaves_1_m_awid
output [15 : 0] v_to_slaves_1_awid;
// value method v_to_slaves_1_m_awaddr
output [63 : 0] v_to_slaves_1_awaddr;
// value method v_to_slaves_1_m_awlen
output [7 : 0] v_to_slaves_1_awlen;
// value method v_to_slaves_1_m_awsize
output [2 : 0] v_to_slaves_1_awsize;
// value method v_to_slaves_1_m_awburst
output [1 : 0] v_to_slaves_1_awburst;
// value method v_to_slaves_1_m_awlock
output v_to_slaves_1_awlock;
// value method v_to_slaves_1_m_awcache
output [3 : 0] v_to_slaves_1_awcache;
// value method v_to_slaves_1_m_awprot
output [2 : 0] v_to_slaves_1_awprot;
// value method v_to_slaves_1_m_awqos
output [3 : 0] v_to_slaves_1_awqos;
// value method v_to_slaves_1_m_awregion
output [3 : 0] v_to_slaves_1_awregion;
// value method v_to_slaves_1_m_awuser
// action method v_to_slaves_1_m_awready
input v_to_slaves_1_awready;
// value method v_to_slaves_1_m_wvalid
output v_to_slaves_1_wvalid;
// value method v_to_slaves_1_m_wdata
output [63 : 0] v_to_slaves_1_wdata;
// value method v_to_slaves_1_m_wstrb
output [7 : 0] v_to_slaves_1_wstrb;
// value method v_to_slaves_1_m_wlast
output v_to_slaves_1_wlast;
// value method v_to_slaves_1_m_wuser
// action method v_to_slaves_1_m_wready
input v_to_slaves_1_wready;
// action method v_to_slaves_1_m_bvalid
input v_to_slaves_1_bvalid;
input [15 : 0] v_to_slaves_1_bid;
input [1 : 0] v_to_slaves_1_bresp;
// value method v_to_slaves_1_m_bready
output v_to_slaves_1_bready;
// value method v_to_slaves_1_m_arvalid
output v_to_slaves_1_arvalid;
// value method v_to_slaves_1_m_arid
output [15 : 0] v_to_slaves_1_arid;
// value method v_to_slaves_1_m_araddr
output [63 : 0] v_to_slaves_1_araddr;
// value method v_to_slaves_1_m_arlen
output [7 : 0] v_to_slaves_1_arlen;
// value method v_to_slaves_1_m_arsize
output [2 : 0] v_to_slaves_1_arsize;
// value method v_to_slaves_1_m_arburst
output [1 : 0] v_to_slaves_1_arburst;
// value method v_to_slaves_1_m_arlock
output v_to_slaves_1_arlock;
// value method v_to_slaves_1_m_arcache
output [3 : 0] v_to_slaves_1_arcache;
// value method v_to_slaves_1_m_arprot
output [2 : 0] v_to_slaves_1_arprot;
// value method v_to_slaves_1_m_arqos
output [3 : 0] v_to_slaves_1_arqos;
// value method v_to_slaves_1_m_arregion
output [3 : 0] v_to_slaves_1_arregion;
// value method v_to_slaves_1_m_aruser
// action method v_to_slaves_1_m_arready
input v_to_slaves_1_arready;
// action method v_to_slaves_1_m_rvalid
input v_to_slaves_1_rvalid;
input [15 : 0] v_to_slaves_1_rid;
input [63 : 0] v_to_slaves_1_rdata;
input [1 : 0] v_to_slaves_1_rresp;
input v_to_slaves_1_rlast;
// value method v_to_slaves_1_m_rready
output v_to_slaves_1_rready;
// value method v_to_slaves_2_m_awvalid
output v_to_slaves_2_awvalid;
// value method v_to_slaves_2_m_awid
output [15 : 0] v_to_slaves_2_awid;
// value method v_to_slaves_2_m_awaddr
output [63 : 0] v_to_slaves_2_awaddr;
// value method v_to_slaves_2_m_awlen
output [7 : 0] v_to_slaves_2_awlen;
// value method v_to_slaves_2_m_awsize
output [2 : 0] v_to_slaves_2_awsize;
// value method v_to_slaves_2_m_awburst
output [1 : 0] v_to_slaves_2_awburst;
// value method v_to_slaves_2_m_awlock
output v_to_slaves_2_awlock;
// value method v_to_slaves_2_m_awcache
output [3 : 0] v_to_slaves_2_awcache;
// value method v_to_slaves_2_m_awprot
output [2 : 0] v_to_slaves_2_awprot;
// value method v_to_slaves_2_m_awqos
output [3 : 0] v_to_slaves_2_awqos;
// value method v_to_slaves_2_m_awregion
output [3 : 0] v_to_slaves_2_awregion;
// value method v_to_slaves_2_m_awuser
// action method v_to_slaves_2_m_awready
input v_to_slaves_2_awready;
// value method v_to_slaves_2_m_wvalid
output v_to_slaves_2_wvalid;
// value method v_to_slaves_2_m_wdata
output [63 : 0] v_to_slaves_2_wdata;
// value method v_to_slaves_2_m_wstrb
output [7 : 0] v_to_slaves_2_wstrb;
// value method v_to_slaves_2_m_wlast
output v_to_slaves_2_wlast;
// value method v_to_slaves_2_m_wuser
// action method v_to_slaves_2_m_wready
input v_to_slaves_2_wready;
// action method v_to_slaves_2_m_bvalid
input v_to_slaves_2_bvalid;
input [15 : 0] v_to_slaves_2_bid;
input [1 : 0] v_to_slaves_2_bresp;
// value method v_to_slaves_2_m_bready
output v_to_slaves_2_bready;
// value method v_to_slaves_2_m_arvalid
output v_to_slaves_2_arvalid;
// value method v_to_slaves_2_m_arid
output [15 : 0] v_to_slaves_2_arid;
// value method v_to_slaves_2_m_araddr
output [63 : 0] v_to_slaves_2_araddr;
// value method v_to_slaves_2_m_arlen
output [7 : 0] v_to_slaves_2_arlen;
// value method v_to_slaves_2_m_arsize
output [2 : 0] v_to_slaves_2_arsize;
// value method v_to_slaves_2_m_arburst
output [1 : 0] v_to_slaves_2_arburst;
// value method v_to_slaves_2_m_arlock
output v_to_slaves_2_arlock;
// value method v_to_slaves_2_m_arcache
output [3 : 0] v_to_slaves_2_arcache;
// value method v_to_slaves_2_m_arprot
output [2 : 0] v_to_slaves_2_arprot;
// value method v_to_slaves_2_m_arqos
output [3 : 0] v_to_slaves_2_arqos;
// value method v_to_slaves_2_m_arregion
output [3 : 0] v_to_slaves_2_arregion;
// value method v_to_slaves_2_m_aruser
// action method v_to_slaves_2_m_arready
input v_to_slaves_2_arready;
// action method v_to_slaves_2_m_rvalid
input v_to_slaves_2_rvalid;
input [15 : 0] v_to_slaves_2_rid;
input [63 : 0] v_to_slaves_2_rdata;
input [1 : 0] v_to_slaves_2_rresp;
input v_to_slaves_2_rlast;
// value method v_to_slaves_2_m_rready
output v_to_slaves_2_rready;
// signals for module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [15 : 0] v_from_masters_0_bid,
v_from_masters_0_rid,
v_to_slaves_0_arid,
v_to_slaves_0_awid,
v_to_slaves_1_arid,
v_to_slaves_1_awid,
v_to_slaves_2_arid,
v_to_slaves_2_awid;
wire [7 : 0] v_to_slaves_0_arlen,
v_to_slaves_0_awlen,
v_to_slaves_0_wstrb,
v_to_slaves_1_arlen,
v_to_slaves_1_awlen,
v_to_slaves_1_wstrb,
v_to_slaves_2_arlen,
v_to_slaves_2_awlen,
v_to_slaves_2_wstrb;
wire [3 : 0] v_to_slaves_0_arcache,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_awcache,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_1_arcache,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_awcache,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_2_arcache,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_awcache,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion;
wire [2 : 0] v_to_slaves_0_arprot,
v_to_slaves_0_arsize,
v_to_slaves_0_awprot,
v_to_slaves_0_awsize,
v_to_slaves_1_arprot,
v_to_slaves_1_arsize,
v_to_slaves_1_awprot,
v_to_slaves_1_awsize,
v_to_slaves_2_arprot,
v_to_slaves_2_arsize,
v_to_slaves_2_awprot,
v_to_slaves_2_awsize;
wire [1 : 0] v_from_masters_0_bresp,
v_from_masters_0_rresp,
v_to_slaves_0_arburst,
v_to_slaves_0_awburst,
v_to_slaves_1_arburst,
v_to_slaves_1_awburst,
v_to_slaves_2_arburst,
v_to_slaves_2_awburst;
wire RDY_reset,
RDY_set_verbosity,
v_from_masters_0_arready,
v_from_masters_0_awready,
v_from_masters_0_bvalid,
v_from_masters_0_rlast,
v_from_masters_0_rvalid,
v_from_masters_0_wready,
v_to_slaves_0_arlock,
v_to_slaves_0_arvalid,
v_to_slaves_0_awlock,
v_to_slaves_0_awvalid,
v_to_slaves_0_bready,
v_to_slaves_0_rready,
v_to_slaves_0_wlast,
v_to_slaves_0_wvalid,
v_to_slaves_1_arlock,
v_to_slaves_1_arvalid,
v_to_slaves_1_awlock,
v_to_slaves_1_awvalid,
v_to_slaves_1_bready,
v_to_slaves_1_rready,
v_to_slaves_1_wlast,
v_to_slaves_1_wvalid,
v_to_slaves_2_arlock,
v_to_slaves_2_arvalid,
v_to_slaves_2_awlock,
v_to_slaves_2_awvalid,
v_to_slaves_2_bready,
v_to_slaves_2_rready,
v_to_slaves_2_wlast,
v_to_slaves_2_wvalid;
// register fabric_cfg_verbosity
reg [3 : 0] fabric_cfg_verbosity;
wire [3 : 0] fabric_cfg_verbosity$D_IN;
wire fabric_cfg_verbosity$EN;
// register fabric_rg_reset
reg fabric_rg_reset;
wire fabric_rg_reset$D_IN, fabric_rg_reset$EN;
// register fabric_v_rg_r_beat_count_0
reg [7 : 0] fabric_v_rg_r_beat_count_0;
wire [7 : 0] fabric_v_rg_r_beat_count_0$D_IN;
wire fabric_v_rg_r_beat_count_0$EN;
// register fabric_v_rg_r_beat_count_1
reg [7 : 0] fabric_v_rg_r_beat_count_1;
wire [7 : 0] fabric_v_rg_r_beat_count_1$D_IN;
wire fabric_v_rg_r_beat_count_1$EN;
// register fabric_v_rg_r_beat_count_2
reg [7 : 0] fabric_v_rg_r_beat_count_2;
wire [7 : 0] fabric_v_rg_r_beat_count_2$D_IN;
wire fabric_v_rg_r_beat_count_2$EN;
// register fabric_v_rg_r_err_beat_count_0
reg [7 : 0] fabric_v_rg_r_err_beat_count_0;
wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN;
wire fabric_v_rg_r_err_beat_count_0$EN;
// register fabric_v_rg_wd_beat_count_0
reg [7 : 0] fabric_v_rg_wd_beat_count_0;
wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN;
wire fabric_v_rg_wd_beat_count_0$EN;
// ports of submodule fabric_v_f_rd_err_info_0
wire [23 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT;
wire fabric_v_f_rd_err_info_0$CLR,
fabric_v_f_rd_err_info_0$DEQ,
fabric_v_f_rd_err_info_0$EMPTY_N,
fabric_v_f_rd_err_info_0$ENQ;
// ports of submodule fabric_v_f_rd_mis_0
wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT;
wire fabric_v_f_rd_mis_0$CLR,
fabric_v_f_rd_mis_0$DEQ,
fabric_v_f_rd_mis_0$EMPTY_N,
fabric_v_f_rd_mis_0$ENQ,
fabric_v_f_rd_mis_0$FULL_N;
// ports of submodule fabric_v_f_rd_mis_1
wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT;
wire fabric_v_f_rd_mis_1$CLR,
fabric_v_f_rd_mis_1$DEQ,
fabric_v_f_rd_mis_1$EMPTY_N,
fabric_v_f_rd_mis_1$ENQ,
fabric_v_f_rd_mis_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_2
wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT;
wire fabric_v_f_rd_mis_2$CLR,
fabric_v_f_rd_mis_2$DEQ,
fabric_v_f_rd_mis_2$EMPTY_N,
fabric_v_f_rd_mis_2$ENQ,
fabric_v_f_rd_mis_2$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_0
reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT;
wire fabric_v_f_rd_sjs_0$CLR,
fabric_v_f_rd_sjs_0$DEQ,
fabric_v_f_rd_sjs_0$EMPTY_N,
fabric_v_f_rd_sjs_0$ENQ,
fabric_v_f_rd_sjs_0$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_0
reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT;
wire fabric_v_f_wd_tasks_0$CLR,
fabric_v_f_wd_tasks_0$DEQ,
fabric_v_f_wd_tasks_0$EMPTY_N,
fabric_v_f_wd_tasks_0$ENQ,
fabric_v_f_wd_tasks_0$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_0
wire [15 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT;
wire fabric_v_f_wr_err_info_0$CLR,
fabric_v_f_wr_err_info_0$DEQ,
fabric_v_f_wr_err_info_0$EMPTY_N,
fabric_v_f_wr_err_info_0$ENQ;
// ports of submodule fabric_v_f_wr_mis_0
wire fabric_v_f_wr_mis_0$CLR,
fabric_v_f_wr_mis_0$DEQ,
fabric_v_f_wr_mis_0$D_IN,
fabric_v_f_wr_mis_0$D_OUT,
fabric_v_f_wr_mis_0$EMPTY_N,
fabric_v_f_wr_mis_0$ENQ,
fabric_v_f_wr_mis_0$FULL_N;
// ports of submodule fabric_v_f_wr_mis_1
wire fabric_v_f_wr_mis_1$CLR,
fabric_v_f_wr_mis_1$DEQ,
fabric_v_f_wr_mis_1$D_IN,
fabric_v_f_wr_mis_1$D_OUT,
fabric_v_f_wr_mis_1$EMPTY_N,
fabric_v_f_wr_mis_1$ENQ,
fabric_v_f_wr_mis_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_2
wire fabric_v_f_wr_mis_2$CLR,
fabric_v_f_wr_mis_2$DEQ,
fabric_v_f_wr_mis_2$D_IN,
fabric_v_f_wr_mis_2$D_OUT,
fabric_v_f_wr_mis_2$EMPTY_N,
fabric_v_f_wr_mis_2$ENQ,
fabric_v_f_wr_mis_2$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_0
reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT;
wire fabric_v_f_wr_sjs_0$CLR,
fabric_v_f_wr_sjs_0$DEQ,
fabric_v_f_wr_sjs_0$EMPTY_N,
fabric_v_f_wr_sjs_0$ENQ,
fabric_v_f_wr_sjs_0$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_addr
wire [108 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN,
fabric_xactors_from_masters_0_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_addr$CLR,
fabric_xactors_from_masters_0_f_rd_addr$DEQ,
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_addr$ENQ,
fabric_xactors_from_masters_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_data
reg [82 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN;
wire [82 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_data$CLR,
fabric_xactors_from_masters_0_f_rd_data$DEQ,
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_data$ENQ,
fabric_xactors_from_masters_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_addr
wire [108 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN,
fabric_xactors_from_masters_0_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_addr$CLR,
fabric_xactors_from_masters_0_f_wr_addr$DEQ,
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_addr$ENQ,
fabric_xactors_from_masters_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN,
fabric_xactors_from_masters_0_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_data$CLR,
fabric_xactors_from_masters_0_f_wr_data$DEQ,
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_data$ENQ,
fabric_xactors_from_masters_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_resp
reg [17 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN;
wire [17 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_resp$CLR,
fabric_xactors_from_masters_0_f_wr_resp$DEQ,
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_resp$ENQ,
fabric_xactors_from_masters_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN,
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_addr$CLR,
fabric_xactors_to_slaves_0_f_rd_addr$DEQ,
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_addr$ENQ,
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_data$CLR,
fabric_xactors_to_slaves_0_f_rd_data$DEQ,
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_data$ENQ,
fabric_xactors_to_slaves_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN,
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_addr$CLR,
fabric_xactors_to_slaves_0_f_wr_addr$DEQ,
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_addr$ENQ,
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN,
fabric_xactors_to_slaves_0_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_data$CLR,
fabric_xactors_to_slaves_0_f_wr_data$DEQ,
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_data$ENQ,
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN,
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_resp$CLR,
fabric_xactors_to_slaves_0_f_wr_resp$DEQ,
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_resp$ENQ,
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN,
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_addr$CLR,
fabric_xactors_to_slaves_1_f_rd_addr$DEQ,
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_addr$ENQ,
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_data$CLR,
fabric_xactors_to_slaves_1_f_rd_data$DEQ,
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_data$ENQ,
fabric_xactors_to_slaves_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN,
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_addr$CLR,
fabric_xactors_to_slaves_1_f_wr_addr$DEQ,
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_addr$ENQ,
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN,
fabric_xactors_to_slaves_1_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_data$CLR,
fabric_xactors_to_slaves_1_f_wr_data$DEQ,
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_data$ENQ,
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN,
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_resp$CLR,
fabric_xactors_to_slaves_1_f_wr_resp$DEQ,
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_resp$ENQ,
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN,
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_addr$CLR,
fabric_xactors_to_slaves_2_f_rd_addr$DEQ,
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_addr$ENQ,
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_data$CLR,
fabric_xactors_to_slaves_2_f_rd_data$DEQ,
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_data$ENQ,
fabric_xactors_to_slaves_2_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN,
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_addr$CLR,
fabric_xactors_to_slaves_2_f_wr_addr$DEQ,
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_addr$ENQ,
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN,
fabric_xactors_to_slaves_2_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_data$CLR,
fabric_xactors_to_slaves_2_f_wr_data$DEQ,
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_data$ENQ,
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN,
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_resp$CLR,
fabric_xactors_to_slaves_2_f_wr_resp$DEQ,
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_resp$ENQ,
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_near_mem_io_addr_base,
soc_map$m_near_mem_io_addr_lim,
soc_map$m_plic_addr_base,
soc_map$m_plic_addr_lim;
// rule scheduling signals
wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_reset,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
CAN_FIRE_reset,
CAN_FIRE_set_verbosity,
CAN_FIRE_v_from_masters_0_m_arvalid,
CAN_FIRE_v_from_masters_0_m_awvalid,
CAN_FIRE_v_from_masters_0_m_bready,
CAN_FIRE_v_from_masters_0_m_rready,
CAN_FIRE_v_from_masters_0_m_wvalid,
CAN_FIRE_v_to_slaves_0_m_arready,
CAN_FIRE_v_to_slaves_0_m_awready,
CAN_FIRE_v_to_slaves_0_m_bvalid,
CAN_FIRE_v_to_slaves_0_m_rvalid,
CAN_FIRE_v_to_slaves_0_m_wready,
CAN_FIRE_v_to_slaves_1_m_arready,
CAN_FIRE_v_to_slaves_1_m_awready,
CAN_FIRE_v_to_slaves_1_m_bvalid,
CAN_FIRE_v_to_slaves_1_m_rvalid,
CAN_FIRE_v_to_slaves_1_m_wready,
CAN_FIRE_v_to_slaves_2_m_arready,
CAN_FIRE_v_to_slaves_2_m_awready,
CAN_FIRE_v_to_slaves_2_m_bvalid,
CAN_FIRE_v_to_slaves_2_m_rvalid,
CAN_FIRE_v_to_slaves_2_m_wready,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_reset,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
WILL_FIRE_reset,
WILL_FIRE_set_verbosity,
WILL_FIRE_v_from_masters_0_m_arvalid,
WILL_FIRE_v_from_masters_0_m_awvalid,
WILL_FIRE_v_from_masters_0_m_bready,
WILL_FIRE_v_from_masters_0_m_rready,
WILL_FIRE_v_from_masters_0_m_wvalid,
WILL_FIRE_v_to_slaves_0_m_arready,
WILL_FIRE_v_to_slaves_0_m_awready,
WILL_FIRE_v_to_slaves_0_m_bvalid,
WILL_FIRE_v_to_slaves_0_m_rvalid,
WILL_FIRE_v_to_slaves_0_m_wready,
WILL_FIRE_v_to_slaves_1_m_arready,
WILL_FIRE_v_to_slaves_1_m_awready,
WILL_FIRE_v_to_slaves_1_m_bvalid,
WILL_FIRE_v_to_slaves_1_m_rvalid,
WILL_FIRE_v_to_slaves_1_m_wready,
WILL_FIRE_v_to_slaves_2_m_arready,
WILL_FIRE_v_to_slaves_2_m_awready,
WILL_FIRE_v_to_slaves_2_m_bvalid,
WILL_FIRE_v_to_slaves_2_m_rvalid,
WILL_FIRE_v_to_slaves_2_m_wready;
// inputs to muxes for submodule ports
wire [82 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
wire [17 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h7091;
reg [31 : 0] v__h7466;
reg [31 : 0] v__h7841;
reg [31 : 0] v__h8601;
reg [31 : 0] v__h8847;
reg [31 : 0] v__h9224;
reg [31 : 0] v__h9516;
reg [31 : 0] v__h9808;
reg [31 : 0] v__h10072;
reg [31 : 0] v__h10501;
reg [31 : 0] v__h10857;
reg [31 : 0] v__h11213;
reg [31 : 0] v__h11950;
reg [31 : 0] v__h12201;
reg [31 : 0] v__h12576;
reg [31 : 0] v__h12817;
reg [31 : 0] v__h13192;
reg [31 : 0] v__h13433;
reg [31 : 0] v__h13919;
reg [31 : 0] v__h4678;
reg [31 : 0] v__h4672;
reg [31 : 0] v__h7085;
reg [31 : 0] v__h7460;
reg [31 : 0] v__h7835;
reg [31 : 0] v__h8595;
reg [31 : 0] v__h8841;
reg [31 : 0] v__h9218;
reg [31 : 0] v__h9510;
reg [31 : 0] v__h9802;
reg [31 : 0] v__h10066;
reg [31 : 0] v__h10495;
reg [31 : 0] v__h10851;
reg [31 : 0] v__h11207;
reg [31 : 0] v__h11944;
reg [31 : 0] v__h12195;
reg [31 : 0] v__h12570;
reg [31 : 0] v__h12811;
reg [31 : 0] v__h13186;
reg [31 : 0] v__h13427;
reg [31 : 0] v__h13913;
// synopsys translate_on
// remaining internal signals
reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1;
wire [7 : 0] x__h12087, x__h12713, x__h13329, x__h13851, x__h8752;
wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_ETC___d249,
IF_fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_ETC___d288,
IF_fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_ETC___d327,
x1_avValue_rresp__h12065,
x1_avValue_rresp__h12691,
x1_avValue_rresp__h13307;
wire fabric_v_f_wd_tasks_0_i_notEmpty__3_AND_fabric_ETC___d82,
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222,
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262,
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301,
fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342,
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d172,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d177,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d170,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d175,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26;
// action method reset
assign RDY_reset = !fabric_rg_reset ;
assign CAN_FIRE_reset = !fabric_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method v_from_masters_0_m_awvalid
assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
// value method v_from_masters_0_m_awready
assign v_from_masters_0_awready =
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
// action method v_from_masters_0_m_wvalid
assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
// value method v_from_masters_0_m_wready
assign v_from_masters_0_wready =
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
// value method v_from_masters_0_m_bvalid
assign v_from_masters_0_bvalid =
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
// value method v_from_masters_0_m_bid
assign v_from_masters_0_bid =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[17:2] ;
// value method v_from_masters_0_m_bresp
assign v_from_masters_0_bresp =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_0_m_bready
assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ;
// action method v_from_masters_0_m_arvalid
assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
// value method v_from_masters_0_m_arready
assign v_from_masters_0_arready =
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
// value method v_from_masters_0_m_rvalid
assign v_from_masters_0_rvalid =
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
// value method v_from_masters_0_m_rid
assign v_from_masters_0_rid =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[82:67] ;
// value method v_from_masters_0_m_rdata
assign v_from_masters_0_rdata =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_0_m_rresp
assign v_from_masters_0_rresp =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_0_m_rlast
assign v_from_masters_0_rlast =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ;
// action method v_from_masters_0_m_rready
assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ;
// value method v_to_slaves_0_m_awvalid
assign v_to_slaves_0_awvalid =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_0_m_awid
assign v_to_slaves_0_awid =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_0_m_awaddr
assign v_to_slaves_0_awaddr =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_awlen
assign v_to_slaves_0_awlen =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_awsize
assign v_to_slaves_0_awsize =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_awburst
assign v_to_slaves_0_awburst =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_awlock
assign v_to_slaves_0_awlock =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_awcache
assign v_to_slaves_0_awcache =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_awprot
assign v_to_slaves_0_awprot =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_awqos
assign v_to_slaves_0_awqos =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_awregion
assign v_to_slaves_0_awregion =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_awready
assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
// value method v_to_slaves_0_m_wvalid
assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ;
// value method v_to_slaves_0_m_wdata
assign v_to_slaves_0_wdata =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_0_m_wstrb
assign v_to_slaves_0_wstrb =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_0_m_wlast
assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_0_m_wready
assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
// action method v_to_slaves_0_m_bvalid
assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
// value method v_to_slaves_0_m_bready
assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
// value method v_to_slaves_0_m_arvalid
assign v_to_slaves_0_arvalid =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_0_m_arid
assign v_to_slaves_0_arid =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_0_m_araddr
assign v_to_slaves_0_araddr =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_arlen
assign v_to_slaves_0_arlen =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_arsize
assign v_to_slaves_0_arsize =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_arburst
assign v_to_slaves_0_arburst =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_arlock
assign v_to_slaves_0_arlock =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_arcache
assign v_to_slaves_0_arcache =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_arprot
assign v_to_slaves_0_arprot =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_arqos
assign v_to_slaves_0_arqos =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_arregion
assign v_to_slaves_0_arregion =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_arready
assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
// action method v_to_slaves_0_m_rvalid
assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
// value method v_to_slaves_0_m_rready
assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
// value method v_to_slaves_1_m_awvalid
assign v_to_slaves_1_awvalid =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_1_m_awid
assign v_to_slaves_1_awid =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_1_m_awaddr
assign v_to_slaves_1_awaddr =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_awlen
assign v_to_slaves_1_awlen =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_awsize
assign v_to_slaves_1_awsize =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_awburst
assign v_to_slaves_1_awburst =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_awlock
assign v_to_slaves_1_awlock =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_awcache
assign v_to_slaves_1_awcache =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_awprot
assign v_to_slaves_1_awprot =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_awqos
assign v_to_slaves_1_awqos =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_awregion
assign v_to_slaves_1_awregion =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_awready
assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
// value method v_to_slaves_1_m_wvalid
assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ;
// value method v_to_slaves_1_m_wdata
assign v_to_slaves_1_wdata =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_1_m_wstrb
assign v_to_slaves_1_wstrb =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_1_m_wlast
assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_1_m_wready
assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
// action method v_to_slaves_1_m_bvalid
assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
// value method v_to_slaves_1_m_bready
assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
// value method v_to_slaves_1_m_arvalid
assign v_to_slaves_1_arvalid =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_1_m_arid
assign v_to_slaves_1_arid =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_1_m_araddr
assign v_to_slaves_1_araddr =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_arlen
assign v_to_slaves_1_arlen =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_arsize
assign v_to_slaves_1_arsize =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_arburst
assign v_to_slaves_1_arburst =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_arlock
assign v_to_slaves_1_arlock =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_arcache
assign v_to_slaves_1_arcache =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_arprot
assign v_to_slaves_1_arprot =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_arqos
assign v_to_slaves_1_arqos =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_arregion
assign v_to_slaves_1_arregion =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_arready
assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
// action method v_to_slaves_1_m_rvalid
assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
// value method v_to_slaves_1_m_rready
assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
// value method v_to_slaves_2_m_awvalid
assign v_to_slaves_2_awvalid =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_2_m_awid
assign v_to_slaves_2_awid =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_2_m_awaddr
assign v_to_slaves_2_awaddr =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_awlen
assign v_to_slaves_2_awlen =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_awsize
assign v_to_slaves_2_awsize =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_awburst
assign v_to_slaves_2_awburst =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_awlock
assign v_to_slaves_2_awlock =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_awcache
assign v_to_slaves_2_awcache =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_awprot
assign v_to_slaves_2_awprot =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_awqos
assign v_to_slaves_2_awqos =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_awregion
assign v_to_slaves_2_awregion =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_awready
assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
// value method v_to_slaves_2_m_wvalid
assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ;
// value method v_to_slaves_2_m_wdata
assign v_to_slaves_2_wdata =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_2_m_wstrb
assign v_to_slaves_2_wstrb =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_2_m_wlast
assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_2_m_wready
assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
// action method v_to_slaves_2_m_bvalid
assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
// value method v_to_slaves_2_m_bready
assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
// value method v_to_slaves_2_m_arvalid
assign v_to_slaves_2_arvalid =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_2_m_arid
assign v_to_slaves_2_arid =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_2_m_araddr
assign v_to_slaves_2_araddr =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_arlen
assign v_to_slaves_2_arlen =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_arsize
assign v_to_slaves_2_arsize =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_arburst
assign v_to_slaves_2_arburst =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_arlock
assign v_to_slaves_2_arlock =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_arcache
assign v_to_slaves_2_arcache =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_arprot
assign v_to_slaves_2_arprot =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_arqos
assign v_to_slaves_2_arqos =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_arregion
assign v_to_slaves_2_arregion =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_arready
assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
// action method v_to_slaves_2_m_rvalid
assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
// value method v_to_slaves_2_m_rready
assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
// submodule fabric_v_f_rd_err_info_0
SizedFIFO #(.p1width(32'd24),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_0$D_IN),
.ENQ(fabric_v_f_rd_err_info_0$ENQ),
.DEQ(fabric_v_f_rd_err_info_0$DEQ),
.CLR(fabric_v_f_rd_err_info_0$CLR),
.D_OUT(fabric_v_f_rd_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_0
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_0$D_IN),
.ENQ(fabric_v_f_rd_mis_0$ENQ),
.DEQ(fabric_v_f_rd_mis_0$DEQ),
.CLR(fabric_v_f_rd_mis_0$CLR),
.D_OUT(fabric_v_f_rd_mis_0$D_OUT),
.FULL_N(fabric_v_f_rd_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_1
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_1$D_IN),
.ENQ(fabric_v_f_rd_mis_1$ENQ),
.DEQ(fabric_v_f_rd_mis_1$DEQ),
.CLR(fabric_v_f_rd_mis_1$CLR),
.D_OUT(fabric_v_f_rd_mis_1$D_OUT),
.FULL_N(fabric_v_f_rd_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_2
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_2$D_IN),
.ENQ(fabric_v_f_rd_mis_2$ENQ),
.DEQ(fabric_v_f_rd_mis_2$DEQ),
.CLR(fabric_v_f_rd_mis_2$CLR),
.D_OUT(fabric_v_f_rd_mis_2$D_OUT),
.FULL_N(fabric_v_f_rd_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N));
// submodule fabric_v_f_rd_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_0$D_IN),
.ENQ(fabric_v_f_rd_sjs_0$ENQ),
.DEQ(fabric_v_f_rd_sjs_0$DEQ),
.CLR(fabric_v_f_rd_sjs_0$CLR),
.D_OUT(fabric_v_f_rd_sjs_0$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N));
// submodule fabric_v_f_wd_tasks_0
FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_0$D_IN),
.ENQ(fabric_v_f_wd_tasks_0$ENQ),
.DEQ(fabric_v_f_wd_tasks_0$DEQ),
.CLR(fabric_v_f_wd_tasks_0$CLR),
.D_OUT(fabric_v_f_wd_tasks_0$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_0$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N));
// submodule fabric_v_f_wr_err_info_0
SizedFIFO #(.p1width(32'd16),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_0$D_IN),
.ENQ(fabric_v_f_wr_err_info_0$ENQ),
.DEQ(fabric_v_f_wr_err_info_0$DEQ),
.CLR(fabric_v_f_wr_err_info_0$CLR),
.D_OUT(fabric_v_f_wr_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_0
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_0$D_IN),
.ENQ(fabric_v_f_wr_mis_0$ENQ),
.DEQ(fabric_v_f_wr_mis_0$DEQ),
.CLR(fabric_v_f_wr_mis_0$CLR),
.D_OUT(fabric_v_f_wr_mis_0$D_OUT),
.FULL_N(fabric_v_f_wr_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_1
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_1$D_IN),
.ENQ(fabric_v_f_wr_mis_1$ENQ),
.DEQ(fabric_v_f_wr_mis_1$DEQ),
.CLR(fabric_v_f_wr_mis_1$CLR),
.D_OUT(fabric_v_f_wr_mis_1$D_OUT),
.FULL_N(fabric_v_f_wr_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_2
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_2$D_IN),
.ENQ(fabric_v_f_wr_mis_2$ENQ),
.DEQ(fabric_v_f_wr_mis_2$DEQ),
.CLR(fabric_v_f_wr_mis_2$CLR),
.D_OUT(fabric_v_f_wr_mis_2$D_OUT),
.FULL_N(fabric_v_f_wr_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N));
// submodule fabric_v_f_wr_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_0$D_IN),
.ENQ(fabric_v_f_wr_sjs_0$ENQ),
.DEQ(fabric_v_f_wr_sjs_0$DEQ),
.CLR(fabric_v_f_wr_sjs_0$CLR),
.D_OUT(fabric_v_f_wr_sjs_0$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_plic_addr_base(soc_map$m_plic_addr_base),
.m_plic_addr_size(),
.m_plic_addr_lim(soc_map$m_plic_addr_lim),
.m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim),
.m_flash_mem_addr_base(),
.m_flash_mem_addr_size(),
.m_flash_mem_addr_lim(),
.m_ethernet_0_addr_base(),
.m_ethernet_0_addr_size(),
.m_ethernet_0_addr_lim(),
.m_dma_0_addr_base(),
.m_dma_0_addr_size(),
.m_dma_0_addr_lim(),
.m_uart16550_0_addr_base(),
.m_uart16550_0_addr_size(),
.m_uart16550_0_addr_lim(),
.m_gpio_0_addr_base(),
.m_gpio_0_addr_size(),
.m_gpio_0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_ddr4_0_uncached_addr_base(),
.m_ddr4_0_uncached_addr_size(),
.m_ddr4_0_uncached_addr_lim(),
.m_ddr4_0_cached_addr_base(),
.m_ddr4_0_cached_addr_size(),
.m_ddr4_0_cached_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_fabric_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29) ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_0_i_notEmpty__3_AND_fabric_ETC___d82 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
!fabric_v_f_wr_mis_0$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
// rule RL_fabric_rl_wr_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
!fabric_v_f_wr_mis_1$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
!fabric_v_f_wr_mis_2$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
// rule RL_fabric_rl_wr_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_0$EMPTY_N &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
// rule RL_fabric_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d170 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d172) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d175 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d177) ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d170 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d172 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d170 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d172) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d175 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d177 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
(fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_0$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
// rule RL_fabric_rl_rd_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
(fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_1$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
(fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_2$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
// rule RL_fabric_rl_rd_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master =
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_0$EMPTY_N &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// rule RL_fabric_rl_reset
assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 =
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 ?
8'd0 :
x__h12087 ;
assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 =
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 ?
8'd0 :
x__h12713 ;
assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 =
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 ?
8'd0 :
x__h13329 ;
assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 ?
8'd0 :
x__h8752 ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 =
{ fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_ETC___d249,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 =
{ fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_ETC___d288,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 =
{ fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_ETC___d327,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_0$D_OUT[15:0],
66'd3,
fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342 } ;
assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ;
// register fabric_cfg_verbosity
assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign fabric_cfg_verbosity$EN = EN_set_verbosity ;
// register fabric_rg_reset
assign fabric_rg_reset$D_IN = !fabric_rg_reset ;
assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ;
// register fabric_v_rg_r_beat_count_0
assign fabric_v_rg_r_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_r_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_1
assign fabric_v_rg_r_beat_count_1$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 ;
assign fabric_v_rg_r_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_2
assign fabric_v_rg_r_beat_count_2$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 ;
assign fabric_v_rg_r_beat_count_2$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
fabric_rg_reset ;
// register fabric_v_rg_r_err_beat_count_0
assign fabric_v_rg_r_err_beat_count_0$D_IN =
fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342 ?
8'd0 :
x__h13851 ;
assign fabric_v_rg_r_err_beat_count_0$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// register fabric_v_rg_wd_beat_count_0
assign fabric_v_rg_wd_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ||
fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_0
assign fabric_v_f_rd_err_info_0$D_IN = 24'h0 ;
assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_rd_err_info_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342 ;
assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_0
assign fabric_v_f_rd_mis_0$D_IN =
{ 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ;
assign fabric_v_f_rd_mis_0$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_v_f_rd_mis_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 ;
assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_1
assign fabric_v_f_rd_mis_1$D_IN = fabric_v_f_rd_mis_0$D_IN ;
assign fabric_v_f_rd_mis_1$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
assign fabric_v_f_rd_mis_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 ;
assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_2
assign fabric_v_f_rd_mis_2$D_IN = fabric_v_f_rd_mis_0$D_IN ;
assign fabric_v_f_rd_mis_2$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_v_f_rd_mis_2$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 ;
assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_0
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1:
fabric_v_f_rd_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2:
fabric_v_f_rd_sjs_0$D_IN = 2'd2;
default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_v_f_rd_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342 ;
assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
default: fabric_v_f_wd_tasks_0$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wd_tasks_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 ;
assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_0
assign fabric_v_f_wr_err_info_0$D_IN = 16'h0 ;
assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_wr_err_info_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_0
assign fabric_v_f_wr_mis_0$D_IN = 1'd0 ;
assign fabric_v_f_wr_mis_0$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_v_f_wr_mis_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_1
assign fabric_v_f_wr_mis_1$D_IN = 1'd0 ;
assign fabric_v_f_wr_mis_1$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
assign fabric_v_f_wr_mis_1$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_2
assign fabric_v_f_wr_mis_2$D_IN = 1'd0 ;
assign fabric_v_f_wr_mis_2$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_mis_2$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wr_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wr_sjs_0$D_IN = 2'd2;
default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_addr
assign fabric_xactors_from_masters_0_f_rd_addr$D_IN =
{ v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion } ;
assign fabric_xactors_from_masters_0_f_rd_addr$ENQ =
v_from_masters_0_arvalid &&
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_rd_data$D_IN =
83'h2AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_rd_data$DEQ =
v_from_masters_0_rready &&
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_addr
assign fabric_xactors_from_masters_0_f_wr_addr$D_IN =
{ v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion } ;
assign fabric_xactors_from_masters_0_f_wr_addr$ENQ =
v_from_masters_0_awvalid &&
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_data
assign fabric_xactors_from_masters_0_f_wr_data$D_IN =
{ v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast } ;
assign fabric_xactors_from_masters_0_f_wr_data$ENQ =
v_from_masters_0_wvalid &&
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_data$DEQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_wr_resp$D_IN =
18'b101010101010101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_wr_resp$DEQ =
v_from_masters_0_bready &&
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_addr
assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N &&
v_to_slaves_0_arready ;
assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_data
assign fabric_xactors_to_slaves_0_f_rd_data$D_IN =
{ v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast } ;
assign fabric_xactors_to_slaves_0_f_rd_data$ENQ =
v_to_slaves_0_rvalid &&
fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_0_f_rd_data$DEQ =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_addr
assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N &&
v_to_slaves_0_awready ;
assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_data
assign fabric_xactors_to_slaves_0_f_wr_data$D_IN =
fabric_xactors_from_masters_0_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ;
assign fabric_xactors_to_slaves_0_f_wr_data$DEQ =
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N &&
v_to_slaves_0_wready ;
assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_resp
assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN =
{ v_to_slaves_0_bid, v_to_slaves_0_bresp } ;
assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ =
v_to_slaves_0_bvalid &&
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_addr
assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N &&
v_to_slaves_1_arready ;
assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_data
assign fabric_xactors_to_slaves_1_f_rd_data$D_IN =
{ v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast } ;
assign fabric_xactors_to_slaves_1_f_rd_data$ENQ =
v_to_slaves_1_rvalid &&
fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_1_f_rd_data$DEQ =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_addr
assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N &&
v_to_slaves_1_awready ;
assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_data
assign fabric_xactors_to_slaves_1_f_wr_data$D_IN =
fabric_xactors_from_masters_0_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ;
assign fabric_xactors_to_slaves_1_f_wr_data$DEQ =
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N &&
v_to_slaves_1_wready ;
assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_resp
assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN =
{ v_to_slaves_1_bid, v_to_slaves_1_bresp } ;
assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ =
v_to_slaves_1_bvalid &&
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_addr
assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N &&
v_to_slaves_2_arready ;
assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_data
assign fabric_xactors_to_slaves_2_f_rd_data$D_IN =
{ v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast } ;
assign fabric_xactors_to_slaves_2_f_rd_data$ENQ =
v_to_slaves_2_rvalid &&
fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_2_f_rd_data$DEQ =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_addr
assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N &&
v_to_slaves_2_awready ;
assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_data
assign fabric_xactors_to_slaves_2_f_wr_data$D_IN =
fabric_xactors_from_masters_0_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ;
assign fabric_xactors_to_slaves_2_f_wr_data$DEQ =
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N &&
v_to_slaves_2_wready ;
assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_resp
assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN =
{ v_to_slaves_2_bid, v_to_slaves_2_bresp } ;
assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ =
v_to_slaves_2_bvalid &&
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_ETC___d249 =
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 ?
x1_avValue_rresp__h12065 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_ETC___d288 =
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 ?
x1_avValue_rresp__h12691 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_ETC___d327 =
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 ?
x1_avValue_rresp__h13307 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign fabric_v_f_wd_tasks_0_i_notEmpty__3_AND_fabric_ETC___d82 =
fabric_v_f_wd_tasks_0$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ;
assign fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 =
fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 =
fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 =
fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ;
assign fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342 =
fabric_v_rg_r_err_beat_count_0 ==
fabric_v_f_rd_err_info_0$D_OUT[23:16] ;
assign fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 =
fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d172 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d177 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d170 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d175 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign x1_avValue_rresp__h12065 =
(fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h12691 =
(fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h13307 =
(fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign x__h12087 = fabric_v_rg_r_beat_count_0 + 8'd1 ;
assign x__h12713 = fabric_v_rg_r_beat_count_1 + 8'd1 ;
assign x__h13329 = fabric_v_rg_r_beat_count_2 + 8'd1 ;
assign x__h13851 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ;
assign x__h8752 = fabric_v_rg_wd_beat_count_0 + 8'd1 ;
always@(fabric_v_f_wd_tasks_0$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_0$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (fabric_cfg_verbosity$EN)
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
fabric_cfg_verbosity$D_IN;
if (fabric_rg_reset$EN)
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN;
if (fabric_v_rg_r_beat_count_0$EN)
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_0$D_IN;
if (fabric_v_rg_r_beat_count_1$EN)
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_1$D_IN;
if (fabric_v_rg_r_beat_count_2$EN)
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_2$D_IN;
if (fabric_v_rg_r_err_beat_count_0$EN)
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_0$D_IN;
if (fabric_v_rg_wd_beat_count_0$EN)
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_0$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fabric_cfg_verbosity = 4'hA;
fabric_rg_reset = 1'h0;
fabric_v_rg_r_beat_count_0 = 8'hAA;
fabric_v_rg_r_beat_count_1 = 8'hAA;
fabric_v_rg_r_beat_count_2 = 8'hAA;
fabric_v_rg_r_err_beat_count_0 = 8'hAA;
fabric_v_rg_wd_beat_count_0 = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h7091 = $stime;
#0;
end
v__h7085 = v__h7091 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h7085,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h7466 = $stime;
#0;
end
v__h7460 = v__h7466 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h7460,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h7841 = $stime;
#0;
end
v__h7835 = v__h7841 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h7835,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8601 = $stime;
#0;
end
v__h8595 = v__h8601 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h8595,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8],
fabric_v_rg_wd_beat_count_0,
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
begin
v__h8847 = $stime;
#0;
end
v__h8841 = v__h8847 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h8841,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9224 = $stime;
#0;
end
v__h9218 = v__h9224 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h9218,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9516 = $stime;
#0;
end
v__h9510 = v__h9516 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h9510,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9808 = $stime;
#0;
end
v__h9802 = v__h9808 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h9802,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10072 = $stime;
#0;
end
v__h10066 = v__h10072 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h10066,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_0$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10501 = $stime;
#0;
end
v__h10495 = v__h10501 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h10495,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10857 = $stime;
#0;
end
v__h10851 = v__h10857 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h10851,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11213 = $stime;
#0;
end
v__h11207 = v__h11213 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h11207,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h11950 = $stime;
#0;
end
v__h11944 = v__h11950 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h11944,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12201 = $stime;
#0;
end
v__h12195 = v__h12201 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h12195,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_ETC___d249);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h12576 = $stime;
#0;
end
v__h12570 = v__h12576 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h12570,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12817 = $stime;
#0;
end
v__h12811 = v__h12817 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h12811,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_ETC___d288);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h13192 = $stime;
#0;
end
v__h13186 = v__h13192 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h13186,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13433 = $stime;
#0;
end
v__h13427 = v__h13433 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h13427,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_ETC___d327);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13919 = $stime;
#0;
end
v__h13913 = v__h13919 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h13913,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[15:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
begin
v__h4678 = $stime;
#0;
end
v__h4672 = v__h4678 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_reset", v__h4672);
end
// synopsys translate_on
endmodule // mkFabric_1x3
|
//#############################################################################
//# Function: Generic Async FIFO #
//# Based on article by Clifford Cummings, #
// "Simulation and Synthesis Techniques for Asynchronous FIFO Design" #
//# (SNUG2002) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_fifo_generic #(parameter DW = 104, // FIFO width
parameter DEPTH = 32, // FIFO depth (entries)
parameter PROG_FULL = (DEPTH/2),// full threshold
parameter AW = $clog2(DEPTH) // read count width
)
(
input nreset, // asynch active low reset for wr_clk
input wr_clk, // write clock
input wr_en, // write enable
input [DW-1:0] din, // write data
input rd_clk, // read clock
input rd_en, // read enable
output [DW-1:0] dout, // read data
output empty, // fifo is empty
output full, // fifo is full
output prog_full, // fifo is "half empty"
output [AW-1:0] rd_count, // NOT IMPLEMENTED
output [AW-1:0] wr_count // NOT IMPLEMENTED
);
//regs
reg [AW:0] wr_addr; // extra bit for wraparound comparison
reg [AW:0] wr_addr_ahead; // extra bit for wraparound comparison
reg [AW:0] rd_addr;
wire [AW:0] rd_addr_gray;
wire [AW:0] wr_addr_gray;
wire [AW:0] rd_addr_gray_sync;
wire [AW:0] wr_addr_gray_sync;
wire [AW:0] rd_addr_sync;
wire [AW:0] wr_addr_sync;
wire wr_nreset;
wire rd_nreset;
//###########################
//# Full/empty indicators
//###########################
// uses one extra bit for compare to track wraparound pointers
// careful clock synchronization done using gray codes
// could get rid of gray2bin for rd_addr_sync...
// fifo indicators
assign empty = (rd_addr_gray[AW:0] == wr_addr_gray_sync[AW:0]);
// fifo full
assign full = (wr_addr[AW-1:0] == rd_addr_sync[AW-1:0]) &
(wr_addr[AW] != rd_addr_sync[AW]);
// programmable full
assign prog_full = (wr_addr_ahead[AW-1:0] == rd_addr_sync[AW-1:0]) &
(wr_addr_ahead[AW] != rd_addr_sync[AW]);
//###########################
//# Reset synchronizers
//###########################
oh_rsync wr_rsync (.nrst_out (wr_nreset),
.clk (wr_clk),
.nrst_in (nreset));
oh_rsync rd_rsync (.nrst_out (rd_nreset),
.clk (rd_clk),
.nrst_in (nreset));
//###########################
//#write side address counter
//###########################
always @ ( posedge wr_clk or negedge wr_nreset)
if(!wr_nreset)
wr_addr[AW:0] <= 'b0;
else if(wr_en)
wr_addr[AW:0] <= wr_addr[AW:0] + 'd1;
//address lookahead for prog_full indicator
always @ (posedge wr_clk or negedge wr_nreset)
if(!wr_nreset)
wr_addr_ahead[AW:0] <= 'b0;
else if(~prog_full)
wr_addr_ahead[AW:0] <= wr_addr[AW:0] + PROG_FULL;
//###########################
//# Synchronize to read clk
//###########################
// convert to gray code (only one bit can toggle)
oh_bin2gray #(.DW(AW+1))
wr_b2g (.out (wr_addr_gray[AW:0]),
.in (wr_addr[AW:0]));
// synchronize to read clock
oh_dsync wr_sync[AW:0] (.dout (wr_addr_gray_sync[AW:0]),
.clk (rd_clk),
.nreset(rd_nreset),
.din (wr_addr_gray[AW:0]));
//###########################
//#read side address counter
//###########################
always @ ( posedge rd_clk or negedge rd_nreset)
if(!rd_nreset)
rd_addr[AW:0] <= 'd0;
else if(rd_en)
rd_addr[AW:0] <= rd_addr[AW:0] + 'd1;
//###########################
//# Synchronize to write clk
//###########################
//covert to gray (can't have multiple bits toggling)
oh_bin2gray #(.DW(AW+1))
rd_b2g (.out (rd_addr_gray[AW:0]),
.in (rd_addr[AW:0]));
//synchronize to wr clock
oh_dsync rd_sync[AW:0] (.dout (rd_addr_gray_sync[AW:0]),
.clk (wr_clk),
.nreset (wr_nreset),
.din (rd_addr_gray[AW:0]));
//convert back to binary (for ease of use, rd_count)
oh_gray2bin #(.DW(AW+1))
rd_g2b (.out (rd_addr_sync[AW:0]),
.in (rd_addr_gray_sync[AW:0]));
//###########################
//#dual ported memory
//###########################
oh_memory_dp #(.DW(DW),
.DEPTH(DEPTH))
fifo_mem(// Outputs
.rd_dout (dout[DW-1:0]),
// Inputs
.wr_clk (wr_clk),
.wr_en (wr_en),
.wr_wem ({(DW){1'b1}}),
.wr_addr (wr_addr[AW-1:0]),
.wr_din (din[DW-1:0]),
.rd_clk (rd_clk),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]));
endmodule // oh_fifo_generic
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: ikari
//
// Create Date: 17:09:03 01/16/2011
// Design Name:
// Module Name: upd77c25
// Project Name: sd2snes
// Target Devices: xc3s400
// Tool versions: ISE 13.1
// Description: NEC uPD77C25 core (for SNES DSP1-4)
//
// Dependencies:
//
// Revision:
// Revision 0.2 - core fully operational, firmware download
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module upd77c25(
input [7:0] DI,
output [7:0] DO,
input A0,
input enable,
input reg_oe_falling,
input reg_oe_rising,
input reg_we_rising,
input RST,
input CLK,
input PGM_WR,
input [23:0] PGM_DI,
input [10:0] PGM_WR_ADDR,
input DAT_WR,
input [15:0] DAT_DI,
input [10:0] DAT_WR_ADDR,
input DP_enable,
input [10:0] DP_ADDR,
input [15:0] dsp_feat,
// debug
output [15:0] updDR,
output [15:0] updSR,
output [10:0] updPC,
output [15:0] updA,
output [15:0] updB,
output [5:0] updFL_A,
output [5:0] updFL_B
);
parameter STATE_FETCH = 8'b00000001;
parameter STATE_LOAD = 8'b00000010;
parameter STATE_ALU1 = 8'b00000100;
parameter STATE_ALU2 = 8'b00001000;
parameter STATE_STORE = 8'b00010000;
parameter STATE_NEXT = 8'b00100000;
parameter STATE_IDLE1 = 8'b01000000;
parameter STATE_IDLE2 = 8'b10000000;
parameter I_OP = 2'b00;
parameter I_RT = 2'b01;
parameter I_JP = 2'b10;
parameter I_LD = 2'b11;
parameter SR_RQM = 15;
parameter SR_DRS = 12;
parameter SR_DRC = 10;
reg [1:0] flags_ov0;
reg [1:0] flags_ov1;
reg [1:0] flags_z;
reg [1:0] flags_c;
reg [1:0] flags_s0;
reg [1:0] flags_s1;
reg [10:0] pc; // program counter
reg [7:0] insn_state; // execute state
reg [1:0] regs_dpb;
reg [3:0] regs_dph;
reg [3:0] regs_dpl;
reg [10:0] regs_rp;
wire [15:0] ram_dina;
reg [15:0] ram_dina_r;
assign ram_dina = ram_dina_r;
wire [23:0] pgm_doutb;
`ifdef MK2
`ifndef DEBUG
upd77c25_pgmrom pgmrom (
.clka(CLK), // input clka
.wea(PGM_WR), // input [0 : 0] wea
.addra(PGM_WR_ADDR), // input [10 : 0] addra
.dina(PGM_DI), // input [23 : 0] dina
.clkb(CLK), // input clkb
.addrb(pc), // input [10 : 0] addrb
.doutb(pgm_doutb) // output [23 : 0] doutb
);
`endif
`endif
`ifdef MK3
upd77c25_pgmrom pgmrom (
.clock(CLK), // input clka
.wren(PGM_WR), // input [0 : 0] wea
.wraddress(PGM_WR_ADDR), // input [10 : 0] addra
.data(PGM_DI), // input [23 : 0] dina
.rdaddress(pc), // input [10 : 0] addrb
.q(pgm_doutb) // output [23 : 0] doutb
);
`endif
wire [23:0] opcode_w = pgm_doutb;
reg [1:0] op;
reg [1:0] op_pselect;
reg [3:0] op_alu;
reg op_asl;
reg [1:0] op_dpl;
reg [3:0] op_dphm;
reg op_rpdcr;
reg [3:0] op_src;
reg [3:0] op_dst;
wire [15:0] dat_doutb;
`ifdef MK2
`ifndef DEBUG
upd77c25_datrom datrom (
.clka(CLK), // input clka
.wea(DAT_WR), // input [0 : 0] wea
.addra(DAT_WR_ADDR), // input [10 : 0] addra
.dina(DAT_DI), // input [15 : 0] dina
.clkb(CLK), // input clkb
.addrb(regs_rp), // input [10 : 0] addrb
.doutb(dat_doutb) // output [15 : 0] doutb
);
`endif
`endif
`ifdef MK3
upd77c25_datrom datrom (
.clock(CLK), // input clka
.wren(DAT_WR), // input [0 : 0] wea
.wraddress(DAT_WR_ADDR), // input [10 : 0] addra
.data(DAT_DI), // input [15 : 0] dina
.rdaddress(regs_rp), // input [10 : 0] addrb
.q(dat_doutb) // output [15 : 0] doutb
);
`endif
wire [15:0] ram_douta;
wire [9:0] ram_addra;
reg [7:0] DP_DOr;
wire [7:0] DP_DO;
wire [7:0] UPD_DO;
wire ram_web = reg_we_rising & DP_enable;
`ifdef MK2
`ifndef DEBUG
upd77c25_datram datram (
.clka(CLK), // input clka
.wea(ram_wea), // input [0 : 0] wea
.addra(ram_addra), // input [9 : 0] addra
.dina(ram_dina), // input [15 : 0] dina
.douta(ram_douta), // output [15 : 0] douta
.clkb(CLK), // input clkb
.web(ram_web), // input [0 : 0] web
.addrb(DP_ADDR), // input [10 : 0] addrb
.dinb(DI), // input [7 : 0] dinb
.doutb(DP_DO) // output [7 : 0] doutb
);
`endif
`endif
`ifdef MK3
upd77c25_datram datram (
.clock(CLK), // input clka
.wren_a(ram_wea), // input [0 : 0] wea
.address_a(ram_addra), // input [9 : 0] addra
.data_a(ram_dina), // input [15 : 0] dina
.q_a(ram_douta), // output [15 : 0] douta
.wren_b(ram_web), // input [0 : 0] web
.address_b(DP_ADDR), // input [10 : 0] addrb
.data_b(DI), // input [7 : 0] dinb
.q_b(DP_DO) // output [7 : 0] doutb
);
`endif
assign ram_wea = ((op != I_JP) && op_dst == 4'b1111 && insn_state == STATE_NEXT);
assign ram_addra = {regs_dpb,
regs_dph | ((|(insn_state & (STATE_ALU1 | STATE_ALU2)) && op_dst == 4'b1100)
? 4'b0100
: 4'b0000),
regs_dpl};
reg signed [15:0] regs_k;
reg signed [15:0] regs_l;
reg [15:0] regs_trb;
reg [15:0] regs_tr;
reg [15:0] regs_dr;
reg [15:0] regs_sr;
reg [3:0] regs_sp;
reg cond_true;
reg [8:0] jp_brch;
reg [10:0] jp_na;
reg [15:0] ld_id;
reg [3:0] ld_dst;
wire [31:0] mul_result = regs_k * regs_l;
reg [15:0] regs_m;
reg [15:0] regs_n;
reg [15:0] alu_p;
reg [15:0] alu_q;
reg [15:0] alu_r;
reg [1:0] alu_store;
reg [10:0] stack [15:0];
reg [15:0] idb;
reg [15:0] regs_ab [1:0];
reg [3:0] cpu_wait = 0;
assign updDR = regs_dr;
assign updSR = regs_sr;
assign updPC = pc;
assign updA = regs_ab[0];
assign updB = regs_ab[1];
assign updFL_A = {flags_s1[0],flags_s0[0],flags_c[0],flags_z[0],flags_ov1[0],flags_ov0[0]};
assign updFL_B = {flags_s1[1],flags_s0[1],flags_c[1],flags_z[1],flags_ov1[1],flags_ov0[1]};
initial begin
alu_store = 2'b11;
insn_state = STATE_IDLE1;
regs_sp = 4'b0000;
pc = 11'b0;
regs_sr = 16'b0;
regs_rp = 16'h0000;
regs_dpb = 2'b0;
regs_dph = 4'b0;
regs_dpl = 4'b0;
regs_k = 16'b0;
regs_l = 16'b0;
regs_ab[0] = 16'b0;
regs_ab[1] = 16'b0;
flags_ov0 = 2'b0;
flags_ov1 = 2'b0;
flags_z = 2'b0;
flags_c = 2'b0;
flags_s0 = 2'b0;
flags_s1 = 2'b0;
regs_tr = 16'b0;
regs_trb = 16'b0;
regs_dr = 16'b0;
end
always @(posedge CLK) begin
if(RST) begin
if(enable & reg_we_rising & (A0 == 1'b0)) begin
if(!regs_sr[SR_DRC]) begin
if(regs_sr[SR_DRS] == 1'b1) begin
regs_sr[SR_RQM] <= 1'b0;
end
end else begin
regs_sr[SR_RQM] <= 1'b0;
end
end
else if(enable & reg_oe_rising & (A0 == 1'b0)) begin
if(!regs_sr[SR_DRC]) begin
if(regs_sr[SR_DRS] == 1'b1) begin
regs_sr[SR_RQM] <= 1'b0;
end
end else begin
regs_sr[SR_RQM] <= 1'b0;
end
end else if((op_src == 4'b1000 && op[1] == 1'b0 && insn_state == STATE_STORE)
|| (op_dst == 4'b0110 && op != 2'b10 && insn_state == STATE_STORE)) begin
regs_sr[SR_RQM] <= 1'b1;
end
end else begin
regs_sr[SR_RQM] <= 1'b0;
end
end
always @(posedge CLK) begin
if(RST) begin
if(enable & reg_we_rising & (A0 == 1'b0)) begin
if(!regs_sr[SR_DRC]) begin
if(regs_sr[SR_DRS] == 1'b0) begin
regs_sr[SR_DRS] <= 1'b1;
end else begin
regs_sr[SR_DRS] <= 1'b0;
end
end
end else if(enable & reg_oe_rising) begin
case(A0)
1'b0: begin
if(!regs_sr[SR_DRC]) begin
if(regs_sr[SR_DRS] == 1'b0) begin
regs_sr[SR_DRS] <= 1'b1;
end else begin
regs_sr[SR_DRS] <= 1'b0;
end
end
end
endcase
end
end else begin
regs_sr[SR_DRS] <= 1'b0;
end
end
always @(posedge CLK) begin
if(RST) begin
if(enable & reg_we_rising & (A0 == 1'b0)) begin
if(!regs_sr[SR_DRC]) begin
if(regs_sr[SR_DRS] == 1'b0) begin
regs_dr[7:0] <= DI;
end else begin
regs_dr[15:8] <= DI;
end
end else begin
regs_dr[7:0] <= DI;
end
end else if(ld_dst == 4'b0110 && insn_state == STATE_STORE) begin
if (op == I_OP || op == I_RT) regs_dr <= idb;
else if (op == I_LD) regs_dr <= ld_id;
end
end else begin
regs_dr <= 16'h0000;
end
end
assign UPD_DO = (A0 ? regs_sr[15:8] : (regs_sr[SR_DRC] ? regs_dr[7:0] : (regs_sr[SR_DRS] ? regs_dr[15:8] : regs_dr[7:0])));
assign DO = DP_enable ? DP_DO : UPD_DO;
always @(posedge CLK) begin
if(RST) begin
case(insn_state)
STATE_FETCH: begin
insn_state <= STATE_LOAD;
if(op == I_OP || op == I_RT) begin
if(|op_alu) begin
flags_z[op_asl] <= (alu_r == 0);
flags_s0[op_asl] <= alu_r[15];
end
case(op_alu)
4'b0001, 4'b0010, 4'b0011, 4'b1010, 4'b1101, 4'b1110, 4'b1111: begin
flags_c[op_asl] <= 0;
flags_ov0[op_asl] <= 0;
flags_ov1[op_asl] <= 0;
end
4'b0100, 4'b0101, 4'b0110, 4'b0111, 4'b1000, 4'b1001: begin
if(op_alu[0]) begin
flags_c[op_asl] <= (alu_r < alu_q);
flags_ov0[op_asl] <= (alu_q[15] ^ alu_r[15]) & ~(alu_q[15] ^ alu_p[15]);
if((alu_q[15] ^ alu_r[15]) & ~(alu_q[15] ^ alu_p[15])) begin
flags_s1[op_asl] <= flags_ov1[op_asl] ^ ~alu_r[15];
flags_ov1[op_asl] <= ~flags_ov1[op_asl];
end
end else begin
flags_c[op_asl] <= (alu_r > alu_q);
flags_ov0[op_asl] <= (alu_q[15] ^ alu_r[15]) & (alu_q[15] ^ alu_p[15]);
if((alu_q[15] ^ alu_r[15]) & (alu_q[15] ^ alu_p[15])) begin
flags_s1[op_asl] <= flags_ov1[op_asl] ^ ~alu_r[15];
flags_ov1[op_asl] <= ~flags_ov1[op_asl];
end
end
end
4'b1011: begin
flags_c[op_asl] <= alu_q[0];
flags_ov0[op_asl] <= 0;
flags_ov1[op_asl] <= 0;
end
4'b1100: begin
flags_c[op_asl] <= alu_q[15];
flags_ov0[op_asl] <= 0;
flags_ov1[op_asl] <= 0;
end
endcase
end
op <= opcode_w[23:22];
op_pselect <= opcode_w[21:20];
op_alu <= opcode_w[19:16];
op_asl <= opcode_w[15];
op_dpl <= opcode_w[14:13];
op_dphm <= opcode_w[12:9];
op_rpdcr <= opcode_w[8];
op_src <= opcode_w[7:4];
op_dst <= opcode_w[3:0];
jp_brch <= opcode_w[21:13];
jp_na <= opcode_w[12:2];
ld_id <= opcode_w[21:6];
ld_dst <= opcode_w[3:0];
regs_m <= {mul_result[31], mul_result[29:15]};
regs_n <= {mul_result[14:0], 1'b0};
end
STATE_LOAD: begin
insn_state <= STATE_ALU1;
case(op)
I_OP, I_RT: begin
case(op_src)
4'b0000: idb <= regs_trb;
4'b0001: idb <= regs_ab[0];
4'b0010: idb <= regs_ab[1];
4'b0011: idb <= regs_tr;
4'b0100: idb <= {regs_dpb,regs_dph,regs_dpl};
4'b0101: idb <= regs_rp;
4'b0110: idb <= dat_doutb; // Address: [regs_rp]
4'b0111: idb <= flags_s1[0] ? 16'h7fff : 16'h8000;
4'b1000: idb <= regs_dr;
4'b1001: idb <= regs_dr;
4'b1010: idb <= regs_sr;
4'b1101: idb <= regs_k;
4'b1110: idb <= regs_l;
4'b1111: idb <= ram_douta; // Address: [regs_dp]
endcase
end
endcase
end
STATE_ALU1: begin
insn_state <= STATE_ALU2;
case(op)
I_OP, I_RT: begin
alu_q <= regs_ab[op_asl];
if(op_alu[3:1] == 3'b100) begin
alu_p <= 16'h0001;
end else begin
case(op_pselect)
2'b00:
alu_p <= ram_douta;
2'b01:
alu_p <= idb;
2'b10:
alu_p <= regs_m;
2'b11:
alu_p <= regs_n;
endcase
end
end
I_JP: begin
case(jp_brch)
9'b100_000_000: cond_true <= 1;
9'b101_000_000: cond_true <= 1;
9'b010_000_000: cond_true <= (flags_c[0] == 0);
9'b010_000_010: cond_true <= (flags_c[0] == 1);
9'b010_000_100: cond_true <= (flags_c[1] == 0);
9'b010_000_110: cond_true <= (flags_c[1] == 1);
9'b010_001_000: cond_true <= (flags_z[0] == 0);
9'b010_001_010: cond_true <= (flags_z[0] == 1);
9'b010_001_100: cond_true <= (flags_z[1] == 0);
9'b010_001_110: cond_true <= (flags_z[1] == 1);
9'b010_010_000: cond_true <= (flags_ov0[0] == 0);
9'b010_010_010: cond_true <= (flags_ov0[0] == 1);
9'b010_010_100: cond_true <= (flags_ov0[1] == 0);
9'b010_010_110: cond_true <= (flags_ov0[1] == 1);
9'b010_011_000: cond_true <= (flags_ov1[0] == 0);
9'b010_011_010: cond_true <= (flags_ov1[0] == 1);
9'b010_011_100: cond_true <= (flags_ov1[1] == 0);
9'b010_011_110: cond_true <= (flags_ov1[1] == 1);
9'b010_100_000: cond_true <= (flags_s0[0] == 0);
9'b010_100_010: cond_true <= (flags_s0[0] == 1);
9'b010_100_100: cond_true <= (flags_s0[1] == 0);
9'b010_100_110: cond_true <= (flags_s0[1] == 1);
9'b010_101_000: cond_true <= (flags_s1[0] == 0);
9'b010_101_010: cond_true <= (flags_s1[0] == 1);
9'b010_101_100: cond_true <= (flags_s1[1] == 0);
9'b010_101_110: cond_true <= (flags_s1[1] == 1);
9'b010_110_000: cond_true <= (regs_dpl == 0);
9'b010_110_001: cond_true <= (regs_dpl != 0);
9'b010_110_010: cond_true <= (regs_dpl == 4'b1111);
9'b010_110_011: cond_true <= (regs_dpl != 4'b1111);
9'b010_111_100: cond_true <= (regs_sr[SR_RQM] == 0);
9'b010_111_110: cond_true <= (regs_sr[SR_RQM] == 1);
default: cond_true <= 0;
endcase
end
endcase
end
STATE_ALU2: begin
insn_state <= STATE_STORE;
end
STATE_STORE: begin
insn_state <= STATE_NEXT;
if(op[1] == 1'b0) begin
case(op_alu)
4'b0001: alu_r <= alu_q | alu_p;
4'b0010: alu_r <= alu_q & alu_p;
4'b0011: alu_r <= alu_q ^ alu_p;
4'b0100: alu_r <= alu_q - alu_p;
4'b0101: alu_r <= alu_q + alu_p;
4'b0110: alu_r <= alu_q - alu_p - flags_c[~op_asl];
4'b0111: alu_r <= alu_q + alu_p + flags_c[~op_asl];
4'b1000: alu_r <= alu_q - alu_p;
4'b1001: alu_r <= alu_q + alu_p;
4'b1010: alu_r <= ~alu_q;
4'b1011: alu_r <= {alu_q[15], alu_q[15:1]};
4'b1100: alu_r <= {alu_q[14:0], flags_c[~op_asl]};
4'b1101: alu_r <= {alu_q[13:0], 2'b11};
4'b1110: alu_r <= {alu_q[11:0], 4'b1111};
4'b1111: alu_r <= {alu_q[7:0], alu_q[15:8]};
endcase
end
case(op)
I_OP, I_RT: begin
case(op_dst)
4'b0001: begin
regs_ab[0] <= idb;
alu_store <= 2'b10;
end
4'b0010: begin
regs_ab[1] <= idb;
alu_store <= 2'b01;
end
4'b0011: regs_tr <= idb;
4'b0100: {regs_dpb,regs_dph,regs_dpl} <= idb[9:0];
4'b0101: regs_rp <= idb;
// 4'b0110: regs_dr <= idb;
4'b0111: begin
regs_sr[14] <= idb[14];
regs_sr[13] <= idb[13];
regs_sr[11] <= idb[11];
regs_sr[SR_DRC] <= idb[10];
regs_sr[9] <= idb[9];
regs_sr[8] <= idb[8];
regs_sr[7] <= idb[7];
regs_sr[1] <= idb[1];
regs_sr[0] <= idb[0];
end
4'b1010: regs_k <= idb;
4'b1011: begin
regs_k <= idb;
regs_l <= dat_doutb;
end
4'b1100: begin
regs_k <= ram_douta;
regs_l <= idb;
end
4'b1101: regs_l <= idb;
4'b1110: regs_trb <= idb;
4'b1111: ram_dina_r <= idb;
endcase
end
I_LD: begin
case(ld_dst)
4'b0001: regs_ab[0] <= ld_id;
4'b0010: regs_ab[1] <= ld_id;
4'b0011: regs_tr <= ld_id;
4'b0100: {regs_dpb,regs_dph,regs_dpl} <= ld_id[9:0];
4'b0101: regs_rp <= ld_id;
// 4'b0110: regs_dr <= ld_id;
4'b0111: begin
regs_sr[14] <= ld_id[14];
regs_sr[13] <= ld_id[13];
regs_sr[11] <= ld_id[11];
regs_sr[SR_DRC] <= ld_id[10];
regs_sr[9] <= ld_id[9];
regs_sr[8] <= ld_id[8];
regs_sr[7] <= ld_id[7];
regs_sr[1] <= ld_id[1];
regs_sr[0] <= ld_id[0];
end
4'b1010: regs_k <= ld_id;
4'b1011: begin
regs_k <= ld_id;
regs_l <= dat_doutb;
end
4'b1100: begin
regs_k <= ram_douta;
regs_l <= ld_id;
end
4'b1101: regs_l <= ld_id;
4'b1110: regs_trb <= ld_id;
4'b1111: ram_dina_r <= ld_id;
endcase
end
endcase
case(op)
I_OP, I_RT: begin
if(op_rpdcr) regs_rp <= regs_rp - 1;
if(op == I_OP) pc <= pc + 1;
else begin
pc <= stack[regs_sp-1];
regs_sp <= regs_sp - 1;
end
end
I_JP: begin
if(cond_true) begin
pc <= jp_na;
if(jp_brch[8:6] == 3'b101) begin
stack[regs_sp] <= pc + 1;
regs_sp <= regs_sp + 1;
end
end else pc <= pc + 1;
end
I_LD: begin
pc <= pc + 1;
end
endcase
cpu_wait <= dsp_feat[3:0];
end
STATE_NEXT: begin
insn_state <= STATE_NEXT;
if(~|cpu_wait) insn_state <= STATE_IDLE1;
cpu_wait <= cpu_wait - 1;
end
STATE_IDLE1: begin
insn_state <= STATE_FETCH;
case(op)
I_OP, I_RT: begin
case(op_dpl)
2'b01: regs_dpl <= regs_dpl + 1;
2'b10: regs_dpl <= regs_dpl - 1;
2'b11: regs_dpl <= 4'b0000;
endcase
regs_dph <= regs_dph ^ op_dphm;
if(|op_alu && alu_store[op_asl]) regs_ab[op_asl] <= alu_r;
alu_store <= 2'b11;
end
endcase
end
endcase
end else begin
insn_state <= STATE_IDLE1;
pc <= 11'b0;
regs_sp <= 4'b0000;
cond_true <= 0;
regs_sr[14] <= 0;
regs_sr[13] <= 0;
regs_sr[11] <= 0;
regs_sr[SR_DRC] <= 0;
regs_sr[9] <= 0;
regs_sr[8] <= 0;
regs_sr[7] <= 0;
regs_rp <= 16'h0000;
regs_dpb <= 2'b0;
regs_dph <= 4'b0;
regs_dpl <= 4'b0;
regs_k <= 16'b0;
regs_l <= 16'b0;
regs_ab[0] <= 16'b0;
regs_ab[1] <= 16'b0;
flags_ov0 <= 2'b0;
flags_ov1 <= 2'b0;
flags_z <= 2'b0;
flags_c <= 2'b0;
flags_s0 <= 2'b0;
flags_s1 <= 2'b0;
regs_tr <= 16'b0;
regs_trb <= 16'b0;
op_pselect <= 2'b0;
op_alu <= 4'b0;
op_asl <= 1'b0;
op_dpl <= 2'b0;
op_dphm <= 4'b0;
op_rpdcr <= 1'b0;
op_src <= 4'b0;
op_dst <= 4'b0;
jp_brch <= 9'b0;
jp_na <= 11'b0;
ld_id <= 16'b0;
ld_dst <= 4'b0;
regs_m <= 16'b0;
regs_n <= 16'b0;
end
end
endmodule
|
/*
* Copyright (c) 2000 Intrinsity, Inc.
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module test_nmos ();
wire t0, t1, t2, t3, t4, t5, t6, t7,
t8, t9, ta, tb, tc, td, te, tf;
reg gnd, vdd, x, z;
reg failed;
wire StH, StL;
assign (strong1, highz0) StH = 1'bx;
assign (highz1, strong0) StL = 1'bx;
nmos n0 ( t0, gnd, gnd);
nmos n1 ( t1, gnd, vdd);
nmos n2 ( t2, gnd, x);
nmos n3 ( t3, gnd, z);
nmos n4 ( t4, vdd, gnd);
nmos n5 ( t5, vdd, vdd);
nmos n6 ( t6, vdd, x);
nmos n7 ( t7, vdd, z);
nmos n8 ( t8, x, gnd);
nmos n9 ( t9, x, vdd);
nmos na ( ta, x, x);
nmos nb ( tb, x, z);
nmos nc ( tc, z, gnd);
nmos nd ( td, z, vdd);
nmos ne ( te, z, x);
nmos nf ( tf, z, z);
initial begin
assign gnd = 1'b1;
assign vdd = 1'b0;
assign x = 1'b0;
assign z = 1'b0;
#10;
assign gnd = 1'b0;
assign vdd = 1'b1;
assign x = 1'b1;
assign z = 1'b1;
#10;
assign gnd = 1'b0;
assign vdd = 1'b1;
assign x = 1'bx;
assign z = 1'bz;
#10;
failed = 0;
if (t0 !== z)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", gnd, gnd, t0 );
end
if (t1 !== 0)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:0", gnd, vdd, t1 );
end
if (t2 !== StL)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:StL", gnd, x, t2 );
end
if (t3 !== StL)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:StL", gnd, z, t3 );
end
if (t4 !== 1'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", vdd, gnd, t4 );
end
if (t5 !== 1)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:0", vdd, vdd, t5 );
end
if (t6 !== StH)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:StH", vdd, x, t6 );
end
if (t7 !== StH)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:StH", vdd, z, t7 );
end
if (t8 !== 1'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", x, gnd, t8 );
end
if (t9 !== 1'bx)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:x", x, vdd, t9 );
end
if (ta !== 1'bx)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:x", x, x, ta );
end
if (tb !== 1'bx)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:x", x, z, tb );
end
if (tc !== 1'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, gnd, tc );
end
if (td !== 1'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, vdd, td );
end
if (te !== 1'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, x, te );
end
if (tf !== 1'bz)
begin
failed = 1;
$display ("FAILED: nmos s:%d g:%d d:%v expected:z", z, z, tf );
end
if (failed == 0)
$display ("PASSED");
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1507 USA
module quad(clk, A, B, Z, zr, out);
parameter W=14;
input clk, A, B, Z, zr;
reg [(W-1):0] c, i; reg zl;
output [2*W:0] out = { zl, i, c };
// reg [(W-1):0] c, i; reg zl;
reg [2:0] Ad, Bd;
reg [2:0] Zc;
always @(posedge clk) Ad <= {Ad[1:0], A};
always @(posedge clk) Bd <= {Bd[1:0], B};
wire good_one = &Zc;
wire good_zero = ~|Zc;
reg last_good;
wire index_pulse = good_one && ! last_good;
wire count_enable = Ad[1] ^ Ad[2] ^ Bd[1] ^ Bd[2];
wire count_direction = Ad[1] ^ Bd[2];
always @(posedge clk)
begin
if(Z && !good_one) Zc <= Zc + 2'b1;
else if(!good_zero) Zc <= Zc - 2'b1;
if(good_one) last_good <= 1;
else if(good_zero) last_good <= 0;
if(count_enable)
begin
if(count_direction) c <= c + 1'd1;
else c <= c - 1'd1;
end
if(index_pulse) begin
i <= c;
zl <= 1;
end else if(zr) begin
zl <= 0;
end
end
endmodule
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
module channel_ram
( // System
input txclk, input reset,
// USB side
input [31:0] datain, input WR, input WR_done, output have_space,
// Reader side
output [31:0] dataout, input RD, input RD_done, output packet_waiting);
reg [6:0] wr_addr, rd_addr;
reg [1:0] which_ram_wr, which_ram_rd;
reg [2:0] nb_packets;
reg [31:0] ram0 [0:127];
reg [31:0] ram1 [0:127];
reg [31:0] ram2 [0:127];
reg [31:0] ram3 [0:127];
reg [31:0] dataout0;
reg [31:0] dataout1;
reg [31:0] dataout2;
reg [31:0] dataout3;
wire wr_done_int;
wire rd_done_int;
wire [6:0] rd_addr_final;
wire [1:0] which_ram_rd_final;
// USB side
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
always @(posedge txclk)
if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
always @(posedge txclk)
if(reset)
wr_addr <= 0;
else if (WR_done)
wr_addr <= 0;
else if (WR)
wr_addr <= wr_addr + 7'd1;
always @(posedge txclk)
if(reset)
which_ram_wr <= 0;
else if (wr_done_int)
which_ram_wr <= which_ram_wr + 2'd1;
assign have_space = (nb_packets < 3'd3);
// Reader side
// short hand fifo
// rd_addr_final is what rd_addr is going to be next clock cycle
// which_ram_rd_final is what which_ram_rd is going to be next clock cycle
always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
assign dataout = (which_ram_rd_final[1]) ?
(which_ram_rd_final[0] ? dataout3 : dataout2) :
(which_ram_rd_final[0] ? dataout1 : dataout0);
//RD_done is the only way to signal the end of one packet
assign rd_done_int = RD_done;
always @(posedge txclk)
if (reset)
rd_addr <= 0;
else if (RD_done)
rd_addr <= 0;
else if (RD)
rd_addr <= rd_addr + 7'd1;
assign rd_addr_final = (reset|RD_done) ? (6'd0) :
((RD)?(rd_addr+7'd1):rd_addr);
always @(posedge txclk)
if (reset)
which_ram_rd <= 0;
else if (rd_done_int)
which_ram_rd <= which_ram_rd + 2'd1;
assign which_ram_rd_final = (reset) ? (2'd0):
((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
//packet_waiting is set to zero if rd_done_int is high
//because there is no guarantee that nb_packets will be pos.
assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
always @(posedge txclk)
if (reset)
nb_packets <= 0;
else if (wr_done_int & ~rd_done_int)
nb_packets <= nb_packets + 3'd1;
else if (rd_done_int & ~wr_done_int)
nb_packets <= nb_packets - 3'd1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRBP_SYMBOL_V
`define SKY130_FD_SC_MS__DLRBP_SYMBOL_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRBP_SYMBOL_V
|
module control_div( clk , rst , start , MSB , z , INIT , SH , DEC , LDA , DONE, DV0 );
input clk;
input rst;
input start;
input MSB;
input z;
output reg INIT;
output reg DV0;
output reg SH;
output reg DEC;
output reg LDA;
output reg DONE;
parameter START = 3'b000;
parameter SHIFT_DEC = 3'b001;
parameter CHECK = 3'b010;
parameter ADD = 3'b011;
parameter LOAD = 3'b101; //agregado
parameter END1 = 3'b100;
reg [2:0] state;
initial begin
INIT=1;
DV0=0;
SH=0;
DEC=0;
LDA=0;
DONE=0;
end
reg [3:0] count;
always @(posedge clk) begin
if (rst) begin
state = START;
end else begin
case(state)
START: begin
count=0;
if(start)
state = SHIFT_DEC;
else
state = START;
end
SHIFT_DEC:
state = CHECK;
CHECK:
if(z)
state = END1;
else begin
if (MSB==0)
state = ADD;
else
state = SHIFT_DEC;
end
ADD: state=LOAD;
LOAD:
if(z)
state = END1;
else
state = SHIFT_DEC;
END1:begin
count = count + 1;
state = (count>9) ? START : END1 ; // hace falta de 10 ciclos de reloj, para que lea el done y luego cargue el resultado
end
default: state = START;
endcase
end
end
always @(state) begin
case(state)
START:begin
INIT=1;
DV0=0;
SH=0;
DEC=0;
LDA=0;
DONE=0;
end
SHIFT_DEC:begin
INIT=0;
DV0=DV0;
SH=1;
DEC=1;
LDA=0;
DONE=0;
end
CHECK:begin
INIT=0;
DV0=0;
SH=0;
DEC=0;
LDA=0;
DONE=0;
end
ADD:begin
INIT=0;
DV0=1; // primero suma
SH=0;
DEC=0;
LDA=0;
DONE=0;
end
LOAD:begin
INIT=0;
DV0=0;
SH=0;
DEC=0;
LDA=1; // ahora carga el resultado
DONE=0;
end
END1:begin
INIT=0;
DV0=0;
SH=0;
DEC=0;
LDA=0;
DONE=1;
end
default:begin
INIT=1;
DV0=0;
SH=0;
DEC=0;
LDA=0;
DONE=0;
end
endcase
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_register_slice
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_register_slice_v2_1_axic_register_slice #
(
parameter C_FAMILY = "virtex6",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
// C_REG_CONFIG:
// 0 => BYPASS = The channel is just wired through the module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => RESERVED (all outputs driven to 0).
// 5 => RESERVED (all outputs driven to 0).
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
(* use_clock_enable = "yes" *)
generate
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 0
// Bypass mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000) begin
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 1 (or 8)
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000001) || (C_REG_CONFIG == 32'h00000008)) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg [C_DATA_WIDTH-1:0] skid_buffer;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else begin
s_ready_i <= M_READY | ~m_valid_i | (s_ready_i & ~S_VALID);
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= S_VALID | ~s_ready_i | (m_valid_i & ~M_READY);
end
if (M_READY | ~m_valid_i) begin
m_payload_i <= s_ready_i ? S_PAYLOAD_DATA : skid_buffer;
end
if (s_ready_i) begin
skid_buffer <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 2
// Only FWD mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000002)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
wire s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg aresetn_d = 1'b0; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 1'b0;
end else begin
aresetn_d <= ~ARESET;
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data;
// M_Valid set to high when we have a completed transfer on slave side
// Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK)
begin
if (~aresetn_d)
m_valid_i <= 1'b0;
else
if (S_VALID) // Always set m_valid_i when slave side is valid
m_valid_i <= 1'b1;
else
if (M_READY) // Clear (or keep) when no slave side is valid but master side is ready
m_valid_i <= 1'b0;
end // always @ (posedge ACLK)
// Slave Ready is either when Master side drives M_Ready or we have space in our storage data
assign s_ready_i = (M_READY | ~m_valid_i) & aresetn_d;
end // if (C_REG_CONFIG == 2)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 3
// Only REV mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000003)
begin
reg [C_DATA_WIDTH-1:0] storage_data;
reg s_ready_i; //local signal of output
reg has_valid_storage_i;
reg has_valid_storage;
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK)
begin
if (S_VALID & s_ready_i)
storage_data <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = has_valid_storage?storage_data:S_PAYLOAD_DATA;
// Need to determine when we need to save a payload
// Need a combinatorial signals since it will also effect S_READY
always @ *
begin
// Set the value if we have a slave transaction but master side is not ready
if (S_VALID & s_ready_i & ~M_READY)
has_valid_storage_i = 1'b1;
// Clear the value if it's set and Master side completes the transaction but we don't have a new slave side
// transaction
else if ( (has_valid_storage == 1) && (M_READY == 1) && ( (S_VALID == 0) || (s_ready_i == 0)))
has_valid_storage_i = 1'b0;
else
has_valid_storage_i = has_valid_storage;
end // always @ *
always @(posedge ACLK)
begin
if (~aresetn_d[0])
has_valid_storage <= 1'b0;
else
has_valid_storage <= has_valid_storage_i;
end
// S_READY is either clocked M_READY or that we have room in local storage
always @(posedge ACLK)
begin
if (~aresetn_d[0])
s_ready_i <= 1'b0;
else
s_ready_i <= M_READY | ~has_valid_storage_i;
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
// M_READY is either combinatorial S_READY or that we have valid data in local storage
assign M_VALID = (S_VALID | has_valid_storage) & aresetn_d[1];
end // if (C_REG_CONFIG == 3)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 4 or 5 is NO LONGER SUPPORTED
//
////////////////////////////////////////////////////////////////////
else if ((C_REG_CONFIG == 32'h00000004) || (C_REG_CONFIG == 32'h00000005))
begin
// synthesis translate_off
initial begin
$display ("ERROR: For axi_register_slice, C_REG_CONFIG = 4 or 5 is RESERVED.");
end
// synthesis translate_on
assign M_PAYLOAD_DATA = 0;
assign M_VALID = 1'b0;
assign S_READY = 1'b0;
end
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 6
// INPUTS mode
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000006)
begin
reg [1:0] state;
reg [1:0] next_state;
localparam [1:0]
ZERO = 2'b00,
ONE = 2'b01,
TWO = 2'b11;
reg [C_DATA_WIDTH-1:0] storage_data1;
reg [C_DATA_WIDTH-1:0] storage_data2;
reg s_valid_d;
reg s_ready_d;
reg m_ready_d;
reg m_valid_d;
reg load_s2;
reg sel_s2;
wire new_access;
wire access_done;
wire s_ready_i; //local signal of output
reg s_ready_ii;
reg m_valid_i; //local signal of output
reg [1:0] aresetn_d = 2'b00; // Reset delay register
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign s_ready_i = s_ready_ii & aresetn_d[1];
// Registrate input control signals
always @(posedge ACLK)
begin
if (~aresetn_d[0]) begin
s_valid_d <= 1'b0;
s_ready_d <= 1'b0;
m_ready_d <= 1'b0;
end else begin
s_valid_d <= S_VALID;
s_ready_d <= s_ready_i;
m_ready_d <= M_READY;
end
end // always @ (posedge ACLK)
// Load storage1 with slave side payload data when slave side ready is high
always @(posedge ACLK)
begin
if (s_ready_i)
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with storage data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= storage_data1;
end
always @(posedge ACLK)
begin
if (~aresetn_d[0])
m_valid_d <= 1'b0;
else
m_valid_d <= m_valid_i;
end
// Local help signals
assign new_access = s_ready_d & s_valid_d;
assign access_done = m_ready_d & m_valid_d;
// State Machine for handling output signals
always @*
begin
next_state = state; // Stay in the same state unless we need to move to another state
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 0;
case (state)
// No transaction stored locally
ZERO: begin
load_s2 = 0;
sel_s2 = 0;
m_valid_i = 0;
s_ready_ii = 1;
if (new_access) begin
next_state = ONE; // Got one so move to ONE
load_s2 = 1;
m_valid_i = 0;
end
else begin
next_state = next_state;
load_s2 = load_s2;
m_valid_i = m_valid_i;
end
end // case: ZERO
// One transaction stored locally
ONE: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 1;
if (~new_access & access_done) begin
next_state = ZERO; // Read out one so move to ZERO
m_valid_i = 0;
end
else if (new_access & ~access_done) begin
next_state = TWO; // Got another one so move to TWO
s_ready_ii = 0;
end
else if (new_access & access_done) begin
load_s2 = 1;
sel_s2 = 0;
end
else begin
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: ONE
// TWO transaction stored locally
TWO: begin
load_s2 = 0;
sel_s2 = 1;
m_valid_i = 1;
s_ready_ii = 0;
if (access_done) begin
next_state = ONE; // Read out one so move to ONE
s_ready_ii = 1;
load_s2 = 1;
sel_s2 = 0;
end
else begin
next_state = next_state;
s_ready_ii = s_ready_ii;
load_s2 = load_s2;
sel_s2 = sel_s2;
end
end // case: TWO
endcase // case (state)
end // always @ *
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (~aresetn_d[0])
state <= ZERO;
else
state <= next_state; // Stay in the same state unless we need to move to another state
end
// Master Payload mux
assign M_PAYLOAD_DATA = sel_s2?storage_data2:storage_data1;
end // if (C_REG_CONFIG == 6)
////////////////////////////////////////////////////////////////////
//
// C_REG_CONFIG = 7
// Light-weight mode.
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000007) begin
reg [C_DATA_WIDTH-1:0] m_payload_i;
reg s_ready_i;
reg m_valid_i;
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
assign M_PAYLOAD_DATA = m_payload_i;
reg [1:0] aresetn_d = 2'b00; // Reset delay shifter
always @(posedge ACLK) begin
if (ARESET) begin
aresetn_d <= 2'b00;
end else begin
aresetn_d <= {aresetn_d[0], ~ARESET};
end
end
always @(posedge ACLK) begin
if (~aresetn_d[0]) begin
s_ready_i <= 1'b0;
end else if (~aresetn_d[1]) begin
s_ready_i <= 1'b1;
end else begin
s_ready_i <= m_valid_i ? M_READY : ~S_VALID;
end
if (~aresetn_d[1]) begin
m_valid_i <= 1'b0;
end else begin
m_valid_i <= s_ready_i ? S_VALID : ~M_READY;
end
if (~m_valid_i) begin
m_payload_i <= S_PAYLOAD_DATA;
end
end
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
//////////////////////////////////////////////////////////////////////
//// ////
//// ROM ////
//// ////
//// Author(s): ////
//// - Michael Unneback ([email protected]) ////
//// - Julius Baxter ([email protected]) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
module rom #(
parameter ADDR_WIDTH = 5,
parameter B3_BURST = 0
)
(
input wb_clk,
input wb_rst,
input [(ADDR_WIDTH + 2) - 1:2] wb_adr_i,
input wb_stb_i,
input wb_cyc_i,
input [2:0] wb_cti_i,
input [1:0] wb_bte_i,
output reg [31:0] wb_dat_o,
output reg wb_ack_o
);
reg [ADDR_WIDTH-1:0] adr;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_dat_o <= 32'h15000000;
else
case (adr)
// Zero r0 and jump to 0x00000100
0 : wb_dat_o <= 32'h18000000;
1 : wb_dat_o <= 32'hA8200000;
2 : wb_dat_o <= 32'hA8C00100;
3 : wb_dat_o <= 32'h44003000;
4 : wb_dat_o <= 32'h15000000;
default: wb_dat_o <= 32'h00000000;
endcase // case (wb_adr_i)
generate
if (B3_BURST) begin : gen_B3_BURST
reg wb_stb_i_r;
reg new_access_r;
reg burst_r;
wire burst = wb_cyc_i & (!(wb_cti_i == 3'b000)) & (!(wb_cti_i == 3'b111));
wire new_access = (wb_stb_i & !wb_stb_i_r);
wire new_burst = (burst & !burst_r);
always @(posedge wb_clk) begin
new_access_r <= new_access;
burst_r <= burst;
wb_stb_i_r <= wb_stb_i;
end
always @(posedge wb_clk)
if (wb_rst)
adr <= 0;
else if (new_access)
// New access, register address, ack a cycle later
adr <= wb_adr_i[(ADDR_WIDTH+2)-1:2];
else if (burst) begin
if (wb_cti_i == 3'b010)
case (wb_bte_i)
2'b00: adr <= adr + 1;
2'b01: adr[1:0] <= adr[1:0] + 1;
2'b10: adr[2:0] <= adr[2:0] + 1;
2'b11: adr[3:0] <= adr[3:0] + 1;
endcase // case (wb_bte_i)
else
adr <= wb_adr_i[(ADDR_WIDTH+2)-1:2];
end // if (burst)
always @(posedge wb_clk)
if (wb_rst)
wb_ack_o <= 0;
else if (wb_ack_o & (!burst | (wb_cti_i == 3'b111)))
wb_ack_o <= 0;
else if (wb_stb_i & ((!burst & !new_access & new_access_r) |
(burst & burst_r)))
wb_ack_o <= 1;
else
wb_ack_o <= 0;
end else begin
always @(wb_adr_i)
adr <= wb_adr_i;
always @ (posedge wb_clk or posedge wb_rst)
if (wb_rst)
wb_ack_o <= 1'b0;
else
wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
end
endgenerate
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pad_jbusl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module pad_jbusl(jbi_io_j_ad_en_chunk56 ,jbi_io_config_dtl_chunk0 ,
dtl_l_vref ,bscan_hiz_l_out ,bscan_mode_ctl_out ,
bscan_update_dr_out ,bscan_hiz_l_in ,serial_out ,pad_jbusl_se ,
jbus_arst_l ,jbus_adbginit_l ,jbi_io_config_dtl ,jbus_gclk ,
jbus_grst_l ,clk_jbusl_cken ,jbus_gdbginit_l ,bscan_update_dr_in ,
pad_jbusl_si ,serial_in ,bscan_shift_dr_out ,bscan_clock_dr_out ,
bscan_mode_ctl_in ,bscan_clock_dr_in ,bypass_enable ,ps_select ,
bypass_enable_out ,ps_select_out ,j_ad ,jbi_io_j_ad ,pad_jbusl_bso
,io_jbi_j_ad ,jbusr_jbusl_cbd ,bscan_shift_dr_in ,jbi_io_j_ad_en ,
pad_jbusl_bsi ,por_l ,rst_io_l ,rst_val_up ,pad_jbusl_so ,
rst_val_dn ,vddo ,jbusr_jbusl_cbu ,sel_bypass );
output [127:57] serial_out ;
output [127:57] io_jbi_j_ad ;
input [0:0] jbi_io_config_dtl_chunk0 ;
input [1:0] jbi_io_config_dtl ;
input [127:57] serial_in ;
input [127:57] jbi_io_j_ad ;
input [8:1] jbusr_jbusl_cbd ;
input [3:2] jbi_io_j_ad_en ;
input [8:1] jbusr_jbusl_cbu ;
inout [127:57] j_ad ;
output bscan_hiz_l_out ;
output bscan_mode_ctl_out ;
output bscan_update_dr_out ;
output bscan_shift_dr_out ;
output bscan_clock_dr_out ;
output bypass_enable_out ;
output ps_select_out ;
output pad_jbusl_bso ;
output pad_jbusl_so ;
input jbi_io_j_ad_en_chunk56 ;
input bscan_hiz_l_in ;
input pad_jbusl_se ;
input jbus_arst_l ;
input jbus_adbginit_l ;
input jbus_gclk ;
input jbus_grst_l ;
input clk_jbusl_cken ;
input jbus_gdbginit_l ;
input bscan_update_dr_in ;
input pad_jbusl_si ;
input bscan_mode_ctl_in ;
input bscan_clock_dr_in ;
input bypass_enable ;
input ps_select ;
input bscan_shift_dr_in ;
input pad_jbusl_bsi ;
input por_l ;
input rst_io_l ;
input rst_val_up ;
input rst_val_dn ;
input vddo ;
input sel_bypass ;
inout dtl_l_vref ;
supply1 vdd ;
supply0 vss ;
wire [1:0] net497 ;
wire [1:0] net493 ;
wire [1:0] net453 ;
wire [1:0] net416 ;
wire [1:0] net422 ;
wire [1:0] clock_dr_end ;
wire [7:0] net467 ;
wire [8:1] cbd3 ;
wire [7:0] net465 ;
wire [7:0] net427 ;
wire [1:0] rstl2 ;
wire [7:0] net428 ;
wire [7:0] net466 ;
wire [7:0] net464 ;
wire [7:0] net429 ;
wire [1:0] net667 ;
wire [1:0] net463 ;
wire [1:0] shift_dr_end ;
wire [7:0] net426 ;
wire [8:1] mid2 ;
wire [1:0] net379 ;
wire [1:0] hiz_l_end ;
wire [8:1] mid0 ;
wire [1:0] mid5 ;
wire [8:1] mid1 ;
wire [1:0] net375 ;
wire [5:1] scan ;
wire [1:0] mid9 ;
wire [1:0] net273 ;
wire [8:1] mid3 ;
wire [8:1] cbu3 ;
wire [1:0] mid15 ;
wire [7:0] net682 ;
wire [1:0] net287 ;
wire [7:0] net389 ;
wire [1:0] net500 ;
wire [1:0] mid19 ;
wire [7:0] net388 ;
wire [1:0] net385 ;
wire [7:0] net505 ;
wire [1:0] net487 ;
wire [1:0] net283 ;
wire [7:0] net391 ;
wire [1:0] mode_ctl_end ;
wire [7:0] net503 ;
wire [7:0] net684 ;
wire [7:0] net685 ;
wire [1:0] mid11 ;
wire [7:0] net390 ;
wire [7:0] net683 ;
wire [1:0] net450 ;
wire [1:0] net412 ;
wire [1:0] net458 ;
wire [1:0] rstl4 ;
wire [1:0] net454 ;
wire [1:0] net460 ;
wire [1:0] bypass_en ;
wire [1:0] rstl0 ;
wire [5:1] bscan ;
wire [1:0] net664 ;
wire [1:0] net670 ;
wire [1:0] mid7 ;
wire [1:0] net376 ;
wire [1:0] bypass_en_end ;
wire [1:0] net382 ;
wire [1:0] net576 ;
wire [1:0] net678 ;
wire [1:0] net501 ;
wire [1:0] mid16 ;
wire [1:0] net674 ;
wire [1:0] net386 ;
wire [1:0] net488 ;
wire [1:0] mid12 ;
wire [1:0] net490 ;
wire [1:0] net498 ;
wire [1:0] rstl3 ;
wire [1:0] net417 ;
wire [1:0] net413 ;
wire [1:0] net494 ;
wire [1:0] net0234 ;
wire [1:0] update_dr_end ;
wire [1:0] net423 ;
wire [1:0] mid6 ;
wire [1:0] net451 ;
wire [1:0] net459 ;
wire [1:0] net455 ;
wire [1:0] net461 ;
wire [1:0] net269 ;
wire [1:0] rstl1 ;
wire [1:0] net669 ;
wire [1:0] net271 ;
wire [1:0] net671 ;
wire [1:0] mid4 ;
wire [1:0] net275 ;
wire [1:0] net377 ;
wire [1:0] net281 ;
wire [1:0] net373 ;
wire [1:0] net675 ;
wire [1:0] mid13 ;
wire [1:0] mid17 ;
wire [1:0] net285 ;
wire [1:0] net387 ;
wire [1:0] net489 ;
wire [1:0] net383 ;
wire [1:0] net491 ;
wire [1:0] net499 ;
wire [1:0] net418 ;
wire [1:0] net414 ;
wire [1:0] net420 ;
wire [1:0] net424 ;
wire [1:0] ps_sel ;
wire [1:0] ps_sel_end ;
wire [1:0] net0494 ;
wire [1:0] se_buf_end ;
wire [1:0] net452 ;
wire [1:0] net0503 ;
wire [1:0] net456 ;
wire [1:0] net462 ;
wire [1:0] net378 ;
wire [1:0] net374 ;
wire [1:0] net380 ;
wire [1:0] mid18 ;
wire [1:0] net384 ;
wire [1:0] net492 ;
wire [1:0] net411 ;
wire [1:0] net415 ;
wire [1:0] net496 ;
wire [1:0] net421 ;
wire [1:0] net425 ;
wire [1:0] net449 ;
wire clk ;
wire pad_jbusl_headel_si ;
wire pad_jbusl_headel_so ;
wire dbginit_l ;
wire reset_l ;
wire net241 ;
wire net0236 ;
wire net0237 ;
wire net0239 ;
wire net0242 ;
wire net656 ;
wire net0682 ;
bw_io_dtl_rpt I57 (
.out18 ({net412[0] ,net412[1] } ),
.in7 ({net498[0] ,net498[1] } ),
.in0 ({net505[0] ,net505[1] ,net505[2] ,net505[3] ,
net505[4] ,net505[5] ,net505[6] ,net505[7] } ),
.out16 ({net414[0] ,net414[1] } ),
.in3 ({cbu3 } ),
.in2 ({net503[0] ,net503[1] ,net503[2] ,net503[3] ,
net503[4] ,net503[5] ,net503[6] ,net503[7] } ),
.in6 ({net499[0] ,net499[1] } ),
.out19 ({net411[0] ,net411[1] } ),
.in8 ({net0503[0] ,net0503[1] } ),
.in9 ({net496[0] ,net496[1] } ),
.out15 ({net415[0] ,net415[1] } ),
.out17 ({net413[0] ,net413[1] } ),
.in1 ({cbd3 } ),
.in4 ({net501[0] ,net501[1] } ),
.in5 ({net500[0] ,net500[1] } ),
.out13 ({net416[0] ,net416[1] } ),
.in10 ({rstl0 } ),
.in11 ({net494[0] ,net494[1] } ),
.in12 ({net493[0] ,net493[1] } ),
.in13 ({net492[0] ,net492[1] } ),
.in19 ({net487[0] ,net487[1] } ),
.in18 ({net0494[0] ,net0494[1] } ),
.in17 ({net489[0] ,net489[1] } ),
.in16 ({net490[0] ,net490[1] } ),
.in15 ({net491[0] ,net491[1] } ),
.out6 ({net423[0] ,net423[1] } ),
.out7 ({net422[0] ,net422[1] } ),
.out8 ({net421[0] ,net421[1] } ),
.out9 ({net420[0] ,net420[1] } ),
.out10 ({rstl1 } ),
.out11 ({net418[0] ,net418[1] } ),
.out12 ({net417[0] ,net417[1] } ),
.out0 ({net429[0] ,net429[1] ,net429[2] ,net429[3] ,
net429[4] ,net429[5] ,net429[6] ,net429[7] } ),
.out1 ({net428[0] ,net428[1] ,net428[2] ,net428[3] ,
net428[4] ,net428[5] ,net428[6] ,net428[7] } ),
.out2 ({net427[0] ,net427[1] ,net427[2] ,net427[3] ,
net427[4] ,net427[5] ,net427[6] ,net427[7] } ),
.out3 ({net426[0] ,net426[1] ,net426[2] ,net426[3] ,
net426[4] ,net426[5] ,net426[6] ,net426[7] } ),
.out4 ({net425[0] ,net425[1] } ),
.out5 ({net424[0] ,net424[1] } ) );
bw_io_dtl_rpt I58 (
.out18 ({net664[0] ,net664[1] } ),
.in7 ({net422[0] ,net422[1] } ),
.in0 ({net429[0] ,net429[1] ,net429[2] ,net429[3] ,
net429[4] ,net429[5] ,net429[6] ,net429[7] } ),
.out16 ({net667[0] ,net667[1] } ),
.in3 ({net426[0] ,net426[1] ,net426[2] ,net426[3] ,
net426[4] ,net426[5] ,net426[6] ,net426[7] } ),
.in2 ({net427[0] ,net427[1] ,net427[2] ,net427[3] ,
net427[4] ,net427[5] ,net427[6] ,net427[7] } ),
.in6 ({net423[0] ,net423[1] } ),
.out19 ({update_dr_end } ),
.in8 ({net421[0] ,net421[1] } ),
.in9 ({net420[0] ,net420[1] } ),
.out15 ({se_buf_end } ),
.out17 ({shift_dr_end } ),
.in1 ({net428[0] ,net428[1] ,net428[2] ,net428[3] ,
net428[4] ,net428[5] ,net428[6] ,net428[7] } ),
.in4 ({net425[0] ,net425[1] } ),
.in5 ({net424[0] ,net424[1] } ),
.out13 ({net669[0] ,net669[1] } ),
.in10 ({net0234[0] ,net0234[1] } ),
.in11 ({net418[0] ,net418[1] } ),
.in12 ({net417[0] ,net417[1] } ),
.in13 ({net416[0] ,net416[1] } ),
.in19 ({net411[0] ,net411[1] } ),
.in18 ({net412[0] ,net412[1] } ),
.in17 ({net413[0] ,net413[1] } ),
.in16 ({net414[0] ,net414[1] } ),
.in15 ({net415[0] ,net415[1] } ),
.out6 ({hiz_l_end } ),
.out7 ({mode_ctl_end } ),
.out8 ({net675[0] ,net675[1] } ),
.out9 ({net674[0] ,net674[1] } ),
.out10 ({rstl0 } ),
.out11 ({net671[0] ,net671[1] } ),
.out12 ({net670[0] ,net670[1] } ),
.out0 ({net685[0] ,net685[1] ,net685[2] ,net685[3] ,
net685[4] ,net685[5] ,net685[6] ,net685[7] } ),
.out1 ({net684[0] ,net684[1] ,net684[2] ,net684[3] ,
net684[4] ,net684[5] ,net684[6] ,net684[7] } ),
.out2 ({net683[0] ,net683[1] ,net683[2] ,net683[3] ,
net683[4] ,net683[5] ,net683[6] ,net683[7] } ),
.out3 ({net682[0] ,net682[1] ,net682[2] ,net682[3] ,
net682[4] ,net682[5] ,net682[6] ,net682[7] } ),
.out4 ({clock_dr_end } ),
.out5 ({net678[0] ,net678[1] } ) );
bw_io_dtl_padx12 I61 (
.ps_select_buf ({ps_sel_end } ),
.bypass_en_buf ({bypass_en_end } ),
.serial_out ({serial_out[127:116] } ),
.serial_in ({serial_in[127:116] } ),
.to_core ({io_jbi_j_ad[127:116] } ),
.pad ({j_ad[127:116] } ),
.por_l_buf ({net674[0] ,net674[1] } ),
.oe_buf ({net675[0] ,net675[1] } ),
.reset_l_buf ({net0234[0] ,net0234[1] } ),
.update_dr_buf ({update_dr_end } ),
.cbu1 ({net682[0] ,net682[1] ,net682[2] ,net682[3] ,
net682[4] ,net682[5] ,net682[6] ,net682[7] } ),
.cbd1 ({net684[0] ,net684[1] ,net684[2] ,net684[3] ,
net684[4] ,net684[5] ,net684[6] ,net684[7] } ),
.up_open_buf ({net664[0] ,net664[1] } ),
.mode_ctl_buf ({mode_ctl_end } ),
.se_buf ({se_buf_end } ),
.shift_dr_buf ({shift_dr_end } ),
.hiz_l_buf ({hiz_l_end } ),
.rst_val_dn_buf ({net670[0] ,net670[1] } ),
.down_25_buf ({net678[0] ,net678[1] } ),
.data ({jbi_io_j_ad[127:116] } ),
.clock_dr_buf ({clock_dr_end } ),
.rst_val_up_buf ({net669[0] ,net669[1] } ),
.sel_bypass_buf ({net667[0] ,net667[1] } ),
.cbu0 ({net683[0] ,net683[1] ,net683[2] ,net683[3] ,
net683[4] ,net683[5] ,net683[6] ,net683[7] } ),
.cbd0 ({net685[0] ,net685[1] ,net685[2] ,net685[3] ,
net685[4] ,net685[5] ,net685[6] ,net685[7] } ),
.rst_io_l_buf ({net671[0] ,net671[1] } ),
.bso (bscan[5] ),
.so (scan[5] ),
.bsr_si (pad_jbusl_bsi ),
.si (pad_jbusl_headel_so ),
.clk (clk ),
.vddo (vddo ),
.ref (dtl_l_vref ) );
bw_io_dtl_padx12 I63 (
.ps_select_buf ({net287[0] ,net287[1] } ),
.bypass_en_buf ({net285[0] ,net285[1] } ),
.serial_out ({serial_out[115:104] } ),
.serial_in ({serial_in[115:104] } ),
.to_core ({io_jbi_j_ad[115:104] } ),
.pad ({j_ad[115:104] } ),
.por_l_buf ({net420[0] ,net420[1] } ),
.oe_buf ({net421[0] ,net421[1] } ),
.reset_l_buf ({rstl0 } ),
.update_dr_buf ({net411[0] ,net411[1] } ),
.cbu1 ({net426[0] ,net426[1] ,net426[2] ,net426[3] ,
net426[4] ,net426[5] ,net426[6] ,net426[7] } ),
.cbd1 ({net428[0] ,net428[1] ,net428[2] ,net428[3] ,
net428[4] ,net428[5] ,net428[6] ,net428[7] } ),
.up_open_buf ({net412[0] ,net412[1] } ),
.mode_ctl_buf ({net422[0] ,net422[1] } ),
.se_buf ({net415[0] ,net415[1] } ),
.shift_dr_buf ({net413[0] ,net413[1] } ),
.hiz_l_buf ({net423[0] ,net423[1] } ),
.rst_val_dn_buf ({net417[0] ,net417[1] } ),
.down_25_buf ({net424[0] ,net424[1] } ),
.data ({jbi_io_j_ad[115:104] } ),
.clock_dr_buf ({net425[0] ,net425[1] } ),
.rst_val_up_buf ({net416[0] ,net416[1] } ),
.sel_bypass_buf ({net414[0] ,net414[1] } ),
.cbu0 ({net427[0] ,net427[1] ,net427[2] ,net427[3] ,
net427[4] ,net427[5] ,net427[6] ,net427[7] } ),
.cbd0 ({net429[0] ,net429[1] ,net429[2] ,net429[3] ,
net429[4] ,net429[5] ,net429[6] ,net429[7] } ),
.rst_io_l_buf ({net418[0] ,net418[1] } ),
.bso (bscan[4] ),
.so (scan[4] ),
.bsr_si (bscan[5] ),
.si (scan[5] ),
.clk (clk ),
.vddo (vddo ),
.ref (dtl_l_vref ) );
bw_u1_buf_15x I113_0_ (
.z (bypass_en_end[0] ),
.a (net285[1] ) );
bw_u1_buf_10x I138 (
.z (net241 ),
.a (se_buf_end[0] ) );
bw_io_dtl_rpt I69 (
.out18 ({net374[0] ,net374[1] } ),
.in7 ({{2 {bscan_mode_ctl_in }} } ),
.in0 ({jbusr_jbusl_cbd } ),
.out16 ({net376[0] ,net376[1] } ),
.in3 ({jbusr_jbusl_cbu } ),
.in2 ({jbusr_jbusl_cbu } ),
.in6 ({{2 {bscan_hiz_l_in }} } ),
.out19 ({net373[0] ,net373[1] } ),
.in8 ({jbi_io_j_ad_en[2] ,jbi_io_j_ad_en[2] } ),
.in9 ({{2 {por_l }} } ),
.out15 ({net377[0] ,net377[1] } ),
.out17 ({net375[0] ,net375[1] } ),
.in1 ({jbusr_jbusl_cbd } ),
.in4 ({{2 {bscan_clock_dr_in }} } ),
.in5 ({jbi_io_config_dtl[1] ,jbi_io_config_dtl[1] } ),
.out13 ({net378[0] ,net378[1] } ),
.in10 ({{2 {bypass_enable }} } ),
.in11 ({{2 {rst_io_l }} } ),
.in12 ({{2 {rst_val_dn }} } ),
.in13 ({{2 {rst_val_up }} } ),
.in19 ({{2 {bscan_update_dr_in }} } ),
.in18 ({jbi_io_config_dtl[0] ,jbi_io_config_dtl[0] } ),
.in17 ({{2 {bscan_shift_dr_in }} } ),
.in16 ({{2 {sel_bypass }} } ),
.in15 ({{2 {pad_jbusl_se }} } ),
.out6 ({net385[0] ,net385[1] } ),
.out7 ({net384[0] ,net384[1] } ),
.out8 ({net383[0] ,net383[1] } ),
.out9 ({net382[0] ,net382[1] } ),
.out10 ({net271[0] ,net271[1] } ),
.out11 ({net380[0] ,net380[1] } ),
.out12 ({net379[0] ,net379[1] } ),
.out0 ({net391[0] ,net391[1] ,net391[2] ,net391[3] ,
net391[4] ,net391[5] ,net391[6] ,net391[7] } ),
.out1 ({net390[0] ,net390[1] ,net390[2] ,net390[3] ,
net390[4] ,net390[5] ,net390[6] ,net390[7] } ),
.out2 ({net389[0] ,net389[1] ,net389[2] ,net389[3] ,
net389[4] ,net389[5] ,net389[6] ,net389[7] } ),
.out3 ({net388[0] ,net388[1] ,net388[2] ,net388[3] ,
net388[4] ,net388[5] ,net388[6] ,net388[7] } ),
.out4 ({net387[0] ,net387[1] } ),
.out5 ({net386[0] ,net386[1] } ) );
bw_u1_buf_15x I100_1_ (
.z (net269[0] ),
.a (ps_select ) );
bw_io_dtl_drv I140 (
.cbu ({cbu3 } ),
.cbd ({cbd3 } ),
.pad (dtl_l_vref ),
.sel_data_n (vss ),
.pad_up (vss ),
.pad_dn_l (vdd ),
.pad_dn25_l (vdd ),
.por (vss ),
.bsr_up (vss ),
.bsr_dn_l (vdd ),
.bsr_dn25_l (vdd ),
.vddo (vddo ) );
bw_io_dtl_rpt I70 (
.out18 ({net488[0] ,net488[1] } ),
.in7 ({mid7 } ),
.in0 ({mid0 } ),
.out16 ({net490[0] ,net490[1] } ),
.in3 ({mid3 } ),
.in2 ({mid2 } ),
.in6 ({mid6 } ),
.out19 ({net487[0] ,net487[1] } ),
.in8 ({jbi_io_j_ad_en[3] ,jbi_io_j_ad_en[3] } ),
.in9 ({mid9 } ),
.out15 ({net491[0] ,net491[1] } ),
.out17 ({net489[0] ,net489[1] } ),
.in1 ({mid1 } ),
.in4 ({mid4 } ),
.in5 ({mid5 } ),
.out13 ({net492[0] ,net492[1] } ),
.in10 ({rstl1 } ),
.in11 ({mid11 } ),
.in12 ({mid12 } ),
.in13 ({mid13 } ),
.in19 ({mid19 } ),
.in18 ({mid18 } ),
.in17 ({mid17 } ),
.in16 ({mid16 } ),
.in15 ({mid15 } ),
.out6 ({net499[0] ,net499[1] } ),
.out7 ({net498[0] ,net498[1] } ),
.out8 ({net497[0] ,net497[1] } ),
.out9 ({net496[0] ,net496[1] } ),
.out10 ({rstl2 } ),
.out11 ({net494[0] ,net494[1] } ),
.out12 ({net493[0] ,net493[1] } ),
.out0 ({net505[0] ,net505[1] ,net505[2] ,net505[3] ,
net505[4] ,net505[5] ,net505[6] ,net505[7] } ),
.out1 ({cbd3 } ),
.out2 ({net503[0] ,net503[1] ,net503[2] ,net503[3] ,
net503[4] ,net503[5] ,net503[6] ,net503[7] } ),
.out3 ({cbu3 } ),
.out4 ({net501[0] ,net501[1] } ),
.out5 ({net500[0] ,net500[1] } ) );
bw_u1_buf_15x I104_1_ (
.z (net275[0] ),
.a (net269[0] ) );
bw_u1_buf_15x I108_1_ (
.z (ps_sel[1] ),
.a (net275[0] ) );
bw_u1_buf_15x I110_1_ (
.z (net283[0] ),
.a (ps_sel[1] ) );
bw_u1_buf_30x I144 (
.z (pad_jbusl_bso ),
.a (net0239 ) );
bw_u1_buf_15x I114_1_ (
.z (ps_sel_end[1] ),
.a (net287[0] ) );
bw_u1_buf_15x I147 (
.z (pad_jbusl_headel_si ),
.a (pad_jbusl_si ) );
bw_u1_buf_15x I100_0_ (
.z (net269[1] ),
.a (ps_select ) );
bw_u1_buf_20x I150 (
.z (pad_jbusl_headel_so ),
.a (net0237 ) );
bw_u1_buf_15x I104_0_ (
.z (net275[1] ),
.a (net269[1] ) );
bw_clk_cl_jbusl_jbus I80 (
.cluster_grst_l (reset_l ),
.so (net0237 ),
.dbginit_l (dbginit_l ),
.si (pad_jbusl_headel_si ),
.se (net241 ),
.adbginit_l (jbus_adbginit_l ),
.gdbginit_l (jbus_gdbginit_l ),
.arst_l (jbus_arst_l ),
.grst_l (jbus_grst_l ),
.cluster_cken (clk_jbusl_cken ),
.gclk (jbus_gclk ),
.rclk (clk ) );
bw_u1_buf_15x I108_0_ (
.z (ps_sel[0] ),
.a (net275[1] ) );
bw_u1_buf_10x I148_1_ (
.z (net0503[0] ),
.a (jbi_io_j_ad_en_chunk56 ) );
bw_u1_scanl_2x I152 (
.so (net0242 ),
.sd (net0682 ),
.ck (net0236 ) );
bw_u1_scanl_2x I153 (
.so (net0239 ),
.sd (net656 ),
.ck (bscan_clock_dr_in ) );
bw_u1_buf_15x I110_0_ (
.z (net283[1] ),
.a (ps_sel[0] ) );
bw_u1_ckbuf_1p5x I154 (
.clk (net0236 ),
.rclk (clk ) );
bw_u1_buf_15x I114_0_ (
.z (ps_sel_end[0] ),
.a (net287[1] ) );
bw_u1_buf_30x I155 (
.z (pad_jbusl_so ),
.a (net0242 ) );
bw_u1_buf_15x I88 (
.z (bscan_hiz_l_out ),
.a (hiz_l_end[0] ) );
bw_u1_buf_15x I105_1_ (
.z (net273[0] ),
.a (net271[0] ) );
bw_u1_buf_15x I109_1_ (
.z (net281[0] ),
.a (bypass_en[1] ) );
bw_u1_buf_15x I91 (
.z (bscan_mode_ctl_out ),
.a (mode_ctl_end[0] ) );
bw_u1_buf_10x I148_0_ (
.z (net0503[1] ),
.a (jbi_io_j_ad_en_chunk56 ) );
bw_u1_buf_15x I111_1_ (
.z (net285[0] ),
.a (net281[0] ) );
bw_u1_buf_15x I93 (
.z (bscan_update_dr_out ),
.a (update_dr_end[0] ) );
bw_u1_buf_15x I95 (
.z (bscan_clock_dr_out ),
.a (clock_dr_end[0] ) );
bw_u1_buf_15x I97 (
.z (bscan_shift_dr_out ),
.a (shift_dr_end[0] ) );
bw_u1_buf_15x I105_0_ (
.z (net273[1] ),
.a (net271[1] ) );
bw_u1_buf_15x I109_0_ (
.z (net281[1] ),
.a (bypass_en[0] ) );
bw_u1_buf_10x I149_1_ (
.z (net0494[0] ),
.a (jbi_io_config_dtl_chunk0[0] ) );
bw_u1_buf_15x I111_0_ (
.z (net285[1] ),
.a (net281[1] ) );
bw_u1_buf_20x I151_1_ (
.z (net0234[0] ),
.a (reset_l ) );
bw_u1_buf_15x I106_1_ (
.z (bypass_en[1] ),
.a (net273[0] ) );
bw_u1_buf_10x I149_0_ (
.z (net0494[1] ),
.a (jbi_io_config_dtl_chunk0[0] ) );
bw_u1_buf_15x I112_1_ (
.z (net287[0] ),
.a (net283[0] ) );
bw_u1_buf_20x I151_0_ (
.z (net0234[1] ),
.a (reset_l ) );
bw_zckgatedcap_h I156_2_ (
.ld (net0236 ) );
bw_io_dtl_padx11 I38 (
.serial_in ({serial_in[103:93] } ),
.serial_out ({serial_out[103:93] } ),
.ps_select_buf ({net283[0] ,net283[1] } ),
.bypass_en_buf ({net281[0] ,net281[1] } ),
.oe_buf ({net497[0] ,net497[1] } ),
.cbu0 ({net503[0] ,net503[1] ,net503[2] ,net503[3] ,
net503[4] ,net503[5] ,net503[6] ,net503[7] } ),
.cbd0 ({net505[0] ,net505[1] ,net505[2] ,net505[3] ,
net505[4] ,net505[5] ,net505[6] ,net505[7] } ),
.data ({jbi_io_j_ad[103:93] } ),
.cbd1 ({cbd3 } ),
.cbu1 ({cbu3 } ),
.pad ({j_ad[103:93] } ),
.to_core ({io_jbi_j_ad[103:93] } ),
.rst_val_dn_buf ({net493[0] ,net493[1] } ),
.hiz_l_buf ({net499[0] ,net499[1] } ),
.down_25_buf ({net500[0] ,net500[1] } ),
.up_open_buf ({net488[0] ,net488[1] } ),
.se_buf ({net491[0] ,net491[1] } ),
.rst_val_up_buf ({net492[0] ,net492[1] } ),
.clock_dr_buf ({net501[0] ,net501[1] } ),
.sel_bypass_buf ({net490[0] ,net490[1] } ),
.mode_ctl_buf ({net498[0] ,net498[1] } ),
.reset_l_buf ({rstl1 } ),
.rst_io_l_buf ({net494[0] ,net494[1] } ),
.shift_dr_buf ({net489[0] ,net489[1] } ),
.por_l_buf ({net496[0] ,net496[1] } ),
.update_dr_buf ({net487[0] ,net487[1] } ),
.serial_out11 (serial_out[104] ),
.clk (clk ),
.vddo (vddo ),
.si (scan[4] ),
.bsr_si (bscan[4] ),
.bso (bscan[3] ),
.so (scan[3] ),
.ref (dtl_l_vref ) );
bw_io_dtl_padx12 I39 (
.ps_select_buf ({net269[0] ,net269[1] } ),
.bypass_en_buf ({net271[0] ,net271[1] } ),
.serial_out ({serial_out[68:57] } ),
.serial_in ({serial_in[68:57] } ),
.to_core ({io_jbi_j_ad[68:57] } ),
.pad ({j_ad[68:57] } ),
.por_l_buf ({net382[0] ,net382[1] } ),
.oe_buf ({net383[0] ,net383[1] } ),
.reset_l_buf ({rstl4 } ),
.update_dr_buf ({net373[0] ,net373[1] } ),
.cbu1 ({net388[0] ,net388[1] ,net388[2] ,net388[3] ,
net388[4] ,net388[5] ,net388[6] ,net388[7] } ),
.cbd1 ({net390[0] ,net390[1] ,net390[2] ,net390[3] ,
net390[4] ,net390[5] ,net390[6] ,net390[7] } ),
.up_open_buf ({net374[0] ,net374[1] } ),
.mode_ctl_buf ({net384[0] ,net384[1] } ),
.se_buf ({net377[0] ,net377[1] } ),
.shift_dr_buf ({net375[0] ,net375[1] } ),
.hiz_l_buf ({net385[0] ,net385[1] } ),
.rst_val_dn_buf ({net379[0] ,net379[1] } ),
.down_25_buf ({net386[0] ,net386[1] } ),
.data ({jbi_io_j_ad[68:57] } ),
.clock_dr_buf ({net387[0] ,net387[1] } ),
.rst_val_up_buf ({net378[0] ,net378[1] } ),
.sel_bypass_buf ({net376[0] ,net376[1] } ),
.cbu0 ({net389[0] ,net389[1] ,net389[2] ,net389[3] ,
net389[4] ,net389[5] ,net389[6] ,net389[7] } ),
.cbd0 ({net391[0] ,net391[1] ,net391[2] ,net391[3] ,
net391[4] ,net391[5] ,net391[6] ,net391[7] } ),
.rst_io_l_buf ({net380[0] ,net380[1] } ),
.bso (net656 ),
.so (net0682 ),
.bsr_si (bscan[1] ),
.si (scan[1] ),
.clk (clk ),
.vddo (vddo ),
.ref (dtl_l_vref ) );
bw_u1_buf_15x I106_0_ (
.z (bypass_en[0] ),
.a (net273[1] ) );
bw_u1_buf_15x I115 (
.z (bypass_enable_out ),
.a (bypass_en_end[0] ) );
bw_u1_buf_15x I112_0_ (
.z (net287[1] ),
.a (net283[1] ) );
bw_zckgatedcap_h I156_1_ (
.ld (net0236 ) );
bw_u1_buf_15x I117 (
.z (ps_select_out ),
.a (ps_sel_end[0] ) );
bw_io_dtl_rpt I51 (
.out18 ({net450[0] ,net450[1] } ),
.in7 ({net384[0] ,net384[1] } ),
.in0 ({net391[0] ,net391[1] ,net391[2] ,net391[3] ,
net391[4] ,net391[5] ,net391[6] ,net391[7] } ),
.out16 ({net452[0] ,net452[1] } ),
.in3 ({net388[0] ,net388[1] ,net388[2] ,net388[3] ,
net388[4] ,net388[5] ,net388[6] ,net388[7] } ),
.in2 ({net389[0] ,net389[1] ,net389[2] ,net389[3] ,
net389[4] ,net389[5] ,net389[6] ,net389[7] } ),
.in6 ({net385[0] ,net385[1] } ),
.out19 ({net449[0] ,net449[1] } ),
.in8 ({net383[0] ,net383[1] } ),
.in9 ({net382[0] ,net382[1] } ),
.out15 ({net453[0] ,net453[1] } ),
.out17 ({net451[0] ,net451[1] } ),
.in1 ({net390[0] ,net390[1] ,net390[2] ,net390[3] ,
net390[4] ,net390[5] ,net390[6] ,net390[7] } ),
.in4 ({net387[0] ,net387[1] } ),
.in5 ({net386[0] ,net386[1] } ),
.out13 ({net454[0] ,net454[1] } ),
.in10 ({rstl3 } ),
.in11 ({net380[0] ,net380[1] } ),
.in12 ({net379[0] ,net379[1] } ),
.in13 ({net378[0] ,net378[1] } ),
.in19 ({net373[0] ,net373[1] } ),
.in18 ({net374[0] ,net374[1] } ),
.in17 ({net375[0] ,net375[1] } ),
.in16 ({net376[0] ,net376[1] } ),
.in15 ({net377[0] ,net377[1] } ),
.out6 ({net461[0] ,net461[1] } ),
.out7 ({net460[0] ,net460[1] } ),
.out8 ({net459[0] ,net459[1] } ),
.out9 ({net458[0] ,net458[1] } ),
.out10 ({rstl4 } ),
.out11 ({net456[0] ,net456[1] } ),
.out12 ({net455[0] ,net455[1] } ),
.out0 ({net467[0] ,net467[1] ,net467[2] ,net467[3] ,
net467[4] ,net467[5] ,net467[6] ,net467[7] } ),
.out1 ({net466[0] ,net466[1] ,net466[2] ,net466[3] ,
net466[4] ,net466[5] ,net466[6] ,net466[7] } ),
.out2 ({net465[0] ,net465[1] ,net465[2] ,net465[3] ,
net465[4] ,net465[5] ,net465[6] ,net465[7] } ),
.out3 ({net464[0] ,net464[1] ,net464[2] ,net464[3] ,
net464[4] ,net464[5] ,net464[6] ,net464[7] } ),
.out4 ({net463[0] ,net463[1] } ),
.out5 ({net462[0] ,net462[1] } ) );
bw_io_dtl_padx12 I52 (
.ps_select_buf ({net275[0] ,net275[1] } ),
.bypass_en_buf ({net273[0] ,net273[1] } ),
.serial_out ({serial_out[80:69] } ),
.serial_in ({serial_in[80:69] } ),
.to_core ({io_jbi_j_ad[80:69] } ),
.pad ({j_ad[80:69] } ),
.por_l_buf ({net458[0] ,net458[1] } ),
.oe_buf ({net459[0] ,net459[1] } ),
.reset_l_buf ({rstl3 } ),
.update_dr_buf ({net449[0] ,net449[1] } ),
.cbu1 ({net464[0] ,net464[1] ,net464[2] ,net464[3] ,
net464[4] ,net464[5] ,net464[6] ,net464[7] } ),
.cbd1 ({net466[0] ,net466[1] ,net466[2] ,net466[3] ,
net466[4] ,net466[5] ,net466[6] ,net466[7] } ),
.up_open_buf ({net450[0] ,net450[1] } ),
.mode_ctl_buf ({net460[0] ,net460[1] } ),
.se_buf ({net453[0] ,net453[1] } ),
.shift_dr_buf ({net451[0] ,net451[1] } ),
.hiz_l_buf ({net461[0] ,net461[1] } ),
.rst_val_dn_buf ({net455[0] ,net455[1] } ),
.down_25_buf ({net462[0] ,net462[1] } ),
.data ({jbi_io_j_ad[80:69] } ),
.clock_dr_buf ({net463[0] ,net463[1] } ),
.rst_val_up_buf ({net454[0] ,net454[1] } ),
.sel_bypass_buf ({net452[0] ,net452[1] } ),
.cbu0 ({net465[0] ,net465[1] ,net465[2] ,net465[3] ,
net465[4] ,net465[5] ,net465[6] ,net465[7] } ),
.cbd0 ({net467[0] ,net467[1] ,net467[2] ,net467[3] ,
net467[4] ,net467[5] ,net467[6] ,net467[7] } ),
.rst_io_l_buf ({net456[0] ,net456[1] } ),
.bso (bscan[1] ),
.so (scan[1] ),
.bsr_si (bscan[2] ),
.si (scan[2] ),
.clk (clk ),
.vddo (vddo ),
.ref (dtl_l_vref ) );
bw_io_dtl_rpt I53 (
.out18 ({mid18 } ),
.in7 ({net460[0] ,net460[1] } ),
.in0 ({net467[0] ,net467[1] ,net467[2] ,net467[3] ,
net467[4] ,net467[5] ,net467[6] ,net467[7] } ),
.out16 ({mid16 } ),
.in3 ({net464[0] ,net464[1] ,net464[2] ,net464[3] ,
net464[4] ,net464[5] ,net464[6] ,net464[7] } ),
.in2 ({net465[0] ,net465[1] ,net465[2] ,net465[3] ,
net465[4] ,net465[5] ,net465[6] ,net465[7] } ),
.in6 ({net461[0] ,net461[1] } ),
.out19 ({mid19 } ),
.in8 ({net459[0] ,net459[1] } ),
.in9 ({net458[0] ,net458[1] } ),
.out15 ({mid15 } ),
.out17 ({mid17 } ),
.in1 ({net466[0] ,net466[1] ,net466[2] ,net466[3] ,
net466[4] ,net466[5] ,net466[6] ,net466[7] } ),
.in4 ({net463[0] ,net463[1] } ),
.in5 ({net462[0] ,net462[1] } ),
.out13 ({mid13 } ),
.in10 ({rstl2 } ),
.in11 ({net456[0] ,net456[1] } ),
.in12 ({net455[0] ,net455[1] } ),
.in13 ({net454[0] ,net454[1] } ),
.in19 ({net449[0] ,net449[1] } ),
.in18 ({net450[0] ,net450[1] } ),
.in17 ({net451[0] ,net451[1] } ),
.in16 ({net452[0] ,net452[1] } ),
.in15 ({net453[0] ,net453[1] } ),
.out6 ({mid6 } ),
.out7 ({mid7 } ),
.out8 ({net576[0] ,net576[1] } ),
.out9 ({mid9 } ),
.out10 ({rstl3 } ),
.out11 ({mid11 } ),
.out12 ({mid12 } ),
.out0 ({mid0 } ),
.out1 ({mid1 } ),
.out2 ({mid2 } ),
.out3 ({mid3 } ),
.out4 ({mid4 } ),
.out5 ({mid5 } ) );
bw_u1_buf_15x I113_1_ (
.z (bypass_en_end[1] ),
.a (net285[0] ) );
bw_io_dtl_padx12 I55 (
.ps_select_buf ({ps_sel } ),
.bypass_en_buf ({bypass_en } ),
.serial_out ({serial_out[92:81] } ),
.serial_in ({serial_in[92:81] } ),
.to_core ({io_jbi_j_ad[92:81] } ),
.pad ({j_ad[92:81] } ),
.por_l_buf ({mid9 } ),
.oe_buf ({net576[0] ,net576[1] } ),
.reset_l_buf ({rstl2 } ),
.update_dr_buf ({mid19 } ),
.cbu1 ({mid3 } ),
.cbd1 ({mid1 } ),
.up_open_buf ({mid18 } ),
.mode_ctl_buf ({mid7 } ),
.se_buf ({mid15 } ),
.shift_dr_buf ({mid17 } ),
.hiz_l_buf ({mid6 } ),
.rst_val_dn_buf ({mid12 } ),
.down_25_buf ({mid5 } ),
.data ({jbi_io_j_ad[92:81] } ),
.clock_dr_buf ({mid4 } ),
.rst_val_up_buf ({mid13 } ),
.sel_bypass_buf ({mid16 } ),
.cbu0 ({mid2 } ),
.cbd0 ({mid0 } ),
.rst_io_l_buf ({mid11 } ),
.bso (bscan[2] ),
.so (scan[2] ),
.bsr_si (bscan[3] ),
.si (scan[3] ),
.clk (clk ),
.vddo (vddo ),
.ref (dtl_l_vref ) );
bw_zckgatedcap_h I156_0_ (
.ld (net0236 ) );
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
//
// bug354
typedef logic [5:0] data_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire rst;
data_t iii_in = crc[5:0];
data_t jjj_in = crc[11:6];
data_t iii_out;
data_t jjj_out;
logic [1:0] ctl0 = crc[63:62];
aaa aaa (.*);
// Aggregate outputs into a single result vector
wire [63:0] result = {64'h0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
rst <= 1'b0;
end
else if (cyc<10) begin
sum <= 64'h0;
rst <= 1'b1;
end
else if (cyc<90) begin
rst <= 1'b0;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module bbb
(
output data_t ggg_out[1:0],
input data_t ggg_in [1:0],
input [1:0] [1:0] ctl,
input logic clk,
input logic rst
);
genvar i;
generate
for (i=0; i<2; i++) begin: PPP
always_ff @(posedge clk) begin
if (rst) begin
ggg_out[i] <= 6'b0;
end
else begin
if (ctl[i][0]) begin
if (ctl[i][1]) begin
ggg_out[i] <= ~ggg_in[i];
end else begin
ggg_out[i] <= ggg_in[i];
end
end
end
end
end
endgenerate
endmodule
module aaa
(
input data_t iii_in,
input data_t jjj_in,
input [1:0] ctl0,
output data_t iii_out,
output data_t jjj_out,
input logic clk,
input logic rst
);
// Below is a bug; {} concat isn't used to make arrays
bbb bbb (
.ggg_in ({jjj_in, iii_in}),
.ggg_out ({jjj_out, iii_out}),
.ctl ({{1'b1,ctl0[1]}, {1'b0,ctl0[0]}}),
.*);
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodrp_mcb_controller.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:25:50 $
// \ \ / \ Date Created: Mon Feb 9 2009
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: Xilinx reference design for IODRP controller for v0.9 device
//Reference:
//
// Revision: Date: Comment
// 1.0: 3/19/09: Initial version for IODRP_MCB read operations.
// 1.1: 4/03/09: SLH - Added left shift for certain IOI's
// End Revision
//**********************************************************************************
`timescale 1ps/1ps
`ifdef ALTERNATE_READ
`else
`define ALTERNATE_READ 1'b1
`endif
module iodrp_mcb_controller(
input wire [7:0] memcell_address,
input wire [7:0] write_data,
output reg [7:0] read_data = 0,
input wire rd_not_write,
input wire cmd_valid,
output wire rdy_busy_n,
input wire use_broadcast,
input wire [4:0] drp_ioi_addr,
input wire sync_rst,
input wire DRP_CLK,
output reg DRP_CS,
output wire DRP_SDI, //output to IODRP SDI pin
output reg DRP_ADD,
output reg DRP_BKST,
input wire DRP_SDO, //input from IODRP SDO pin
output reg MCB_UIREAD = 1'b0
);
reg [7:0] memcell_addr_reg; // Register where memcell_address is captured during the READY state
reg [7:0] data_reg; // Register which stores the write data until it is ready to be shifted out
reg [8:0] shift_through_reg; // The shift register which shifts out SDO and shifts in SDI.
// This register is loaded before the address or data phase, but continues to shift for a writeback of read data
reg load_shift_n; // The signal which causes shift_through_reg to load the new value from data_out_mux, or continue to shift data in from DRP_SDO
reg addr_data_sel_n; // The signal which indicates where the shift_through_reg should load from. 0 -> data_reg 1 -> memcell_addr_reg
reg [2:0] bit_cnt= 3'b0; // The counter for which bit is being shifted during address or data phase
reg rd_not_write_reg;
reg AddressPhase; // This is set after the first address phase has executed
reg DRP_CS_pre;
reg extra_cs;
(* FSM_ENCODING="GRAY" *) reg [3:0] state, nextstate;
wire [8:0] data_out;
reg [8:0] data_out_mux; // The mux which selects between data_reg and memcell_addr_reg for sending to shift_through_reg
wire DRP_SDI_pre; //added so that DRP_SDI output is only active when DRP_CS is active
localparam READY = 4'h0;
localparam DECIDE = 4'h1;
localparam ADDR_PHASE = 4'h2;
localparam ADDR_TO_DATA_GAP = 4'h3;
localparam ADDR_TO_DATA_GAP2 = 4'h4;
localparam ADDR_TO_DATA_GAP3 = 4'h5;
localparam DATA_PHASE = 4'h6;
localparam ALMOST_READY = 4'h7;
localparam ALMOST_READY2 = 4'h8;
localparam ALMOST_READY3 = 4'h9;
localparam IOI_DQ0 = 5'h01;
localparam IOI_DQ1 = 5'h00;
localparam IOI_DQ2 = 5'h03;
localparam IOI_DQ3 = 5'h02;
localparam IOI_DQ4 = 5'h05;
localparam IOI_DQ5 = 5'h04;
localparam IOI_DQ6 = 5'h07;
localparam IOI_DQ7 = 5'h06;
localparam IOI_DQ8 = 5'h09;
localparam IOI_DQ9 = 5'h08;
localparam IOI_DQ10 = 5'h0B;
localparam IOI_DQ11 = 5'h0A;
localparam IOI_DQ12 = 5'h0D;
localparam IOI_DQ13 = 5'h0C;
localparam IOI_DQ14 = 5'h0F;
localparam IOI_DQ15 = 5'h0E;
localparam IOI_UDQS_CLK = 5'h1D;
localparam IOI_UDQS_PIN = 5'h1C;
localparam IOI_LDQS_CLK = 5'h1F;
localparam IOI_LDQS_PIN = 5'h1E;
//synthesis translate_off
reg [32*8-1:0] state_ascii;
always @ (state) begin
case (state)
READY :state_ascii<="READY";
DECIDE :state_ascii<="DECIDE";
ADDR_PHASE :state_ascii<="ADDR_PHASE";
ADDR_TO_DATA_GAP :state_ascii<="ADDR_TO_DATA_GAP";
ADDR_TO_DATA_GAP2 :state_ascii<="ADDR_TO_DATA_GAP2";
ADDR_TO_DATA_GAP3 :state_ascii<="ADDR_TO_DATA_GAP3";
DATA_PHASE :state_ascii<="DATA_PHASE";
ALMOST_READY :state_ascii<="ALMOST_READY";
ALMOST_READY2 :state_ascii<="ALMOST_READY2";
ALMOST_READY3 :state_ascii<="ALMOST_READY3";
endcase // case(state)
end
//synthesis translate_on
/*********************************************
* Input Registers
*********************************************/
always @ (posedge DRP_CLK) begin
if(state == READY) begin
memcell_addr_reg <= memcell_address;
data_reg <= write_data;
rd_not_write_reg <= rd_not_write;
end
end
assign rdy_busy_n = (state == READY);
// The changes below are to compensate for an issue with 1.0 silicon.
// It may still be necessary to add a clock cycle to the ADD and CS signals
//`define DRP_v1_0_FIX // Uncomment out this line for synthesis
task shift_n_expand (
input [7:0] data_in,
output [8:0] data_out
);
begin
if (data_in[0])
data_out[1:0] = 2'b11;
else
data_out[1:0] = 2'b00;
if (data_in[1:0] == 2'b10)
data_out[2:1] = 2'b11;
else
data_out[2:1] = {data_in[1], data_out[1]};
if (data_in[2:1] == 2'b10)
data_out[3:2] = 2'b11;
else
data_out[3:2] = {data_in[2], data_out[2]};
if (data_in[3:2] == 2'b10)
data_out[4:3] = 2'b11;
else
data_out[4:3] = {data_in[3], data_out[3]};
if (data_in[4:3] == 2'b10)
data_out[5:4] = 2'b11;
else
data_out[5:4] = {data_in[4], data_out[4]};
if (data_in[5:4] == 2'b10)
data_out[6:5] = 2'b11;
else
data_out[6:5] = {data_in[5], data_out[5]};
if (data_in[6:5] == 2'b10)
data_out[7:6] = 2'b11;
else
data_out[7:6] = {data_in[6], data_out[6]};
if (data_in[7:6] == 2'b10)
data_out[8:7] = 2'b11;
else
data_out[8:7] = {data_in[7], data_out[7]};
end
endtask
always @(*) begin
case(drp_ioi_addr)
`ifdef DRP_v1_0_FIX
IOI_DQ0 : data_out_mux = data_out<<1;
IOI_DQ1 : data_out_mux = data_out;
IOI_DQ2 : data_out_mux = data_out<<1;
// IOI_DQ2 : data_out_mux = data_out;
IOI_DQ3 : data_out_mux = data_out;
IOI_DQ4 : data_out_mux = data_out;
IOI_DQ5 : data_out_mux = data_out;
IOI_DQ6 : shift_n_expand (data_out, data_out_mux);
// IOI_DQ6 : data_out_mux = data_out;
IOI_DQ7 : data_out_mux = data_out;
IOI_DQ8 : data_out_mux = data_out<<1;
IOI_DQ9 : data_out_mux = data_out;
IOI_DQ10 : data_out_mux = data_out<<1;
IOI_DQ11 : data_out_mux = data_out;
IOI_DQ12 : data_out_mux = data_out<<1;
IOI_DQ13 : data_out_mux = data_out;
IOI_DQ14 : data_out_mux = data_out<<1;
IOI_DQ15 : data_out_mux = data_out;
IOI_UDQS_CLK : data_out_mux = data_out<<1;
IOI_UDQS_PIN : data_out_mux = data_out<<1;
IOI_LDQS_CLK : data_out_mux = data_out;
IOI_LDQS_PIN : data_out_mux = data_out;
`else
`endif
IOI_DQ0 : data_out_mux = data_out;
IOI_DQ1 : data_out_mux = data_out;
IOI_DQ2 : data_out_mux = data_out;
IOI_DQ3 : data_out_mux = data_out;
IOI_DQ4 : data_out_mux = data_out;
IOI_DQ5 : data_out_mux = data_out;
IOI_DQ6 : data_out_mux = data_out;
IOI_DQ7 : data_out_mux = data_out;
IOI_DQ8 : data_out_mux = data_out;
IOI_DQ9 : data_out_mux = data_out;
IOI_DQ10 : data_out_mux = data_out;
IOI_DQ11 : data_out_mux = data_out;
IOI_DQ12 : data_out_mux = data_out;
IOI_DQ13 : data_out_mux = data_out;
IOI_DQ14 : data_out_mux = data_out;
IOI_DQ15 : data_out_mux = data_out;
IOI_UDQS_CLK : data_out_mux = data_out;
IOI_UDQS_PIN : data_out_mux = data_out;
IOI_LDQS_CLK : data_out_mux = data_out;
IOI_LDQS_PIN : data_out_mux = data_out;
default : data_out_mux = data_out;
endcase
end
/*********************************************
* Shift Registers / Bit Counter
*********************************************/
assign data_out = (addr_data_sel_n)? {1'b0, memcell_addr_reg} : {1'b0, data_reg};
always @ (posedge DRP_CLK) begin
if(sync_rst)
shift_through_reg <= 9'b0;
else begin
if (load_shift_n) //Assume the shifter is either loading or shifting, bit 0 is shifted out first
shift_through_reg <= data_out_mux;
else
shift_through_reg <= {1'b0, DRP_SDO, shift_through_reg[7:1]};
end
end
always @ (posedge DRP_CLK) begin
if (((state == ADDR_PHASE) | (state == DATA_PHASE)) & !sync_rst)
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 3'b0;
end
always @ (posedge DRP_CLK) begin
if(sync_rst) begin
read_data <= 8'h00;
end
else begin
if(state == ALMOST_READY3)
read_data <= shift_through_reg;
end
end
always @ (posedge DRP_CLK) begin
if(sync_rst) begin
AddressPhase <= 1'b0;
end
else begin
if (AddressPhase) begin
// Keep it set until we finish the cycle
AddressPhase <= AddressPhase && ~(state == ALMOST_READY2);
end
else begin
// set the address phase when ever we finish the address phase
AddressPhase <= (state == ADDR_PHASE) && (bit_cnt == 3'b111);
end
end
end
/*********************************************
* DRP Signals
*********************************************/
always @ (posedge DRP_CLK) begin
DRP_ADD <= (nextstate == ADDR_PHASE);
DRP_CS <= (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
// DRP_CS <= (drp_ioi_addr != IOI_DQ0) ? (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE) : (bit_cnt != 3'b111) && (nextstate == ADDR_PHASE) | (nextstate == DATA_PHASE);
MCB_UIREAD <= (nextstate == DATA_PHASE) && rd_not_write_reg;
if (state == READY)
DRP_BKST <= use_broadcast;
end
assign DRP_SDI_pre = (DRP_CS)? shift_through_reg[0] : 1'b0; //if DRP_CS is inactive, just drive 0 out - this is a possible place to pipeline for increased performance
assign DRP_SDI = (rd_not_write_reg & DRP_CS & !DRP_ADD)? DRP_SDO : DRP_SDI_pre; //If reading, then feed SDI back out SDO - this is a possible place to pipeline for increased performance
/*********************************************
* State Machine
*********************************************/
always @ (*) begin
addr_data_sel_n = 1'b0;
load_shift_n = 1'b0;
case (state)
READY: begin
load_shift_n = 0;
if(cmd_valid)
nextstate = DECIDE;
else
nextstate = READY;
end
DECIDE: begin
load_shift_n = 1;
addr_data_sel_n = 1;
nextstate = ADDR_PHASE;
end
ADDR_PHASE: begin
load_shift_n = 0;
if(&bit_cnt[2:0])
if (`ALTERNATE_READ && rd_not_write_reg)
if (AddressPhase)
// After the second pass go to end of statemachine
nextstate = ALMOST_READY;
else
// execute a second address phase for the alternative access method.
nextstate = DECIDE;
else
nextstate = ADDR_TO_DATA_GAP;
else
nextstate = ADDR_PHASE;
end
ADDR_TO_DATA_GAP: begin
load_shift_n = 1;
nextstate = ADDR_TO_DATA_GAP2;
end
ADDR_TO_DATA_GAP2: begin
load_shift_n = 1;
nextstate = ADDR_TO_DATA_GAP3;
end
ADDR_TO_DATA_GAP3: begin
load_shift_n = 1;
nextstate = DATA_PHASE;
end
DATA_PHASE: begin
load_shift_n = 0;
if(&bit_cnt)
nextstate = ALMOST_READY;
else
nextstate = DATA_PHASE;
end
ALMOST_READY: begin
load_shift_n = 0;
nextstate = ALMOST_READY2;
end
ALMOST_READY2: begin
load_shift_n = 0;
nextstate = ALMOST_READY3;
end
ALMOST_READY3: begin
load_shift_n = 0;
nextstate = READY;
end
default: begin
load_shift_n = 0;
nextstate = READY;
end
endcase
end
always @ (posedge DRP_CLK) begin
if(sync_rst)
state <= READY;
else
state <= nextstate;
end
endmodule
|
// ivl-bugs PR#307
module top;
reg [127:0] in1;
reg [127:0] in2;
wire [128:0] out1;
reg [128:0] out2;
assign out1 = in1 + in2;
task r;
integer errors;
begin
out2 = in1 + in2;
$display("\n %h\n+ %h", in1,in2);
$display("= %h", out1);
$display("= %h", out2);
if (out1 != out2)
begin
$display("MISMATCH");
errors = errors + 1;
end
end
endtask
initial begin
r.errors = 0;
in1 = 128'hffffffffffffffffffffffffffffffff;
in2 = 128'hfffffffffffffffffffffffffffffff7;
r;
in1 = 128'hffffffffffffffffffffffffffffffff;
in2 = 128'h00000000000000000000000000000001;
r;
in1 = 128'h00000000000000000000000000000001;
in2 = 128'hffffffffffffffffffffffffffffffff;
r;
in1 = 128'h00000000000000000000000000000000;
in2 = 128'hffffffffffffffffffffffffffffffff;
r;
in1 = 128'hffffffffffffffffffffffffffffffff;
in2 = 128'hffffffffffffffffffffffffffffffff;
r;
in1 = 128'h00000000000000000000000000000000;
in2 = 128'h00000000000000000000000000000000;
r;
in1 = 128'h80000000000000000000000000000000;
in2 = 128'h80000000000000000000000000000000;
r;
in1 = 128'h08000000000000000000000000000000;
in2 = 128'h08000000000000000000000000000000;
r;
in1 = 128'h00000000000000008000000000000000;
in2 = 128'h00000000000000008000000000000000;
r;
in1 = 128'h55555555555555555555555555555555;
in2 = 128'h55555555555555555555555555555555;
r;
in1 = 128'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa;
in2 = 128'haaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa;
r;
if (r.errors)
$display("FAILED: %d errors", r.errors);
else
$display("PASSED");
end
endmodule
|
package pkg;
typedef logic [1:0] my_type;
endpackage
module top;
import pkg::*;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
pkg::my_type_t a; // From sub_2 of sub_2.v
pkg::my_type_t z; // From sub_1 of sub_1.v
// End of automatics
sub_1 sub_1 (.*,
// Outputs
.z (z), // Implicit .*
// Inputs
.a (a)); // Implicit .*
sub_2 sub_2 (.*,
// Outputs
.a (a), // Implicit .*
// Inputs
.z (z)); // Implicit .*
endmodule
module sub_1
import pkg::*; // bug317
(
input pkg::my_type_t a,
output pkg::my_type_t z
);
endmodule
module sub_2
(
input pkg::my_type_t z,
output pkg::my_type_t a
);
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// verilog-auto-star-save: t
// End:
|
/*
* <file> <desc>
*
* <fulldesc>
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module mmio (
input clk_i,
input reset_i,
input [5:0] addr_i, // 32-bit addresses, so only 6 bits needed to span 256 bytes of mem
input write_i,
input read_i,
input [31:0] data_i,
output reg [31:0] data_o,
output [79:0] keys
);
// Wire definitions ===========================================================================
// Registers ==================================================================================
reg [79:0] keys_r = 80'hffffffffffffffff;
// Assignments ================================================================================
assign keys = keys_r;
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Other logic ================================================================================
always @(negedge clk_i)
if( !reset_i ) begin
if( write_i ) begin
case(addr_i)
0: keys_r[31:0] <= data_i;
1: keys_r[63:32] <= data_i;
2: keys_r[79:64] <= data_i[15:0];
endcase
end
if( read_i ) begin
case(addr_i)
0: data_o <= keys_r[31:0];
1: data_o <= keys_r[63:32];
2: data_o <= {16'hff,keys_r[79:64]};
endcase
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_rxeq_scan.v
// Version : 3.0
//------------------------------------------------------------------------------
// Filename : rxeq_scan.v
// Description : PIPE RX Equalization Eye Scan Module for 7 Series Transceiver
// Version : 18.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- RXEQ Eye Scan Module ----------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_rxeq_scan #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
parameter CONVERGE_MAX = 22'd3125000, // Convergence max count (12ms)
parameter CONVERGE_MAX_BYPASS = 22'd2083333 // Convergence max count for phase2/3 bypass mode (8ms)
)
(
//---------- Input -------------------------------------
input RXEQSCAN_CLK,
input RXEQSCAN_RST_N,
input [ 1:0] RXEQSCAN_CONTROL,
input [ 2:0] RXEQSCAN_PRESET,
input RXEQSCAN_PRESET_VALID,
input [ 3:0] RXEQSCAN_TXPRESET,
input [17:0] RXEQSCAN_TXCOEFF,
input RXEQSCAN_NEW_TXCOEFF_REQ,
input [ 5:0] RXEQSCAN_FS,
input [ 5:0] RXEQSCAN_LF,
//---------- Output ------------------------------------
output RXEQSCAN_PRESET_DONE,
output [17:0] RXEQSCAN_NEW_TXCOEFF,
output RXEQSCAN_NEW_TXCOEFF_DONE,
output RXEQSCAN_LFFS_SEL,
output RXEQSCAN_ADAPT_DONE
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg2;
//---------- Internal Signals --------------------------
reg adapt_done_cnt = 1'd0;
//---------- Output Register ---------------------------
reg preset_done = 1'd0;
reg [21:0] converge_cnt = 22'd0;
reg [17:0] new_txcoeff = 18'd0;
reg new_txcoeff_done = 1'd0;
reg lffs_sel = 1'd0;
reg adapt_done = 1'd0;
reg [ 3:0] fsm = 4'd0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 4'b0001;
localparam FSM_PRESET = 4'b0010;
localparam FSM_CONVERGE = 4'b0100;
localparam FSM_NEW_TXCOEFF_REQ = 4'b1000;
//---------- Simulation Speedup ------------------------
// Gen3: 32 bits / PCLK : 1 million bits / X PCLK
// X =
//------------------------------------------------------
localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX;
localparam converge_max_bypass_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX_BYPASS;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RXEQSCAN_CLK)
begin
if (!RXEQSCAN_RST_N)
begin
//---------- 1st Stage FF --------------------------
preset_reg1 <= 3'd0;
preset_valid_reg1 <= 1'd0;
txpreset_reg1 <= 4'd0;
txcoeff_reg1 <= 18'd0;
new_txcoeff_req_reg1 <= 1'd0;
fs_reg1 <= 6'd0;
lf_reg1 <= 6'd0;
//---------- 2nd Stage FF --------------------------
preset_reg2 <= 3'd0;
preset_valid_reg2 <= 1'd0;
txpreset_reg2 <= 4'd0;
txcoeff_reg2 <= 18'd0;
new_txcoeff_req_reg2 <= 1'd0;
fs_reg2 <= 6'd0;
lf_reg2 <= 6'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
preset_reg1 <= RXEQSCAN_PRESET;
preset_valid_reg1 <= RXEQSCAN_PRESET_VALID;
txpreset_reg1 <= RXEQSCAN_TXPRESET;
txcoeff_reg1 <= RXEQSCAN_TXCOEFF;
new_txcoeff_req_reg1 <= RXEQSCAN_NEW_TXCOEFF_REQ;
fs_reg1 <= RXEQSCAN_FS;
lf_reg1 <= RXEQSCAN_LF;
//---------- 2nd Stage FF --------------------------
preset_reg2 <= preset_reg1;
preset_valid_reg2 <= preset_valid_reg1;
txpreset_reg2 <= txpreset_reg1;
txcoeff_reg2 <= txcoeff_reg1;
new_txcoeff_req_reg2 <= new_txcoeff_req_reg1;
fs_reg2 <= fs_reg1;
lf_reg2 <= lf_reg1;
end
end
//---------- Eye Scan ----------------------------------------------------------
always @ (posedge RXEQSCAN_CLK)
begin
if (!RXEQSCAN_RST_N)
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= 18'd0;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Process RXEQ Preset ---------------
if (preset_valid_reg2)
begin
fsm <= FSM_PRESET;
preset_done <= 1'd1;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Request New TX Coefficient --------
else if (new_txcoeff_req_reg2)
begin
fsm <= FSM_CONVERGE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
//new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : 18'd4; // Default
new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : (PCIE_GT_DEVICE == "GTX") ? 18'd5 : 18'd4; // Optimized for Gen3 RX JTOL
new_txcoeff_done <= 1'd0;
lffs_sel <= (PCIE_RXEQ_MODE_GEN3 == 0) ? 1'd0 : 1'd1;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Default ---------------------------
else
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
end
//---------- Process RXEQ Preset -------------------
FSM_PRESET :
begin
fsm <= (!preset_valid_reg2) ? FSM_IDLE : FSM_PRESET;
preset_done <= 1'd1;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Wait for Convergence ------------------
FSM_CONVERGE :
begin
if ((adapt_done_cnt == 1'd0) && (RXEQSCAN_CONTROL == 2'd2))
begin
fsm <= FSM_NEW_TXCOEFF_REQ;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= lffs_sel;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
else
begin
//---------- Phase2/3 ----------------------
if (RXEQSCAN_CONTROL == 2'd2)
fsm <= (converge_cnt == converge_max_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
//---------- Phase2/3 Bypass ---------------
else
fsm <= (converge_cnt == converge_max_bypass_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
preset_done <= 1'd0;
converge_cnt <= converge_cnt + 1'd1;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= lffs_sel;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
end
//---------- Request New TX Coefficient ------------
FSM_NEW_TXCOEFF_REQ :
begin
if (!new_txcoeff_req_reg2)
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= lffs_sel;
adapt_done <= 1'd0;
adapt_done_cnt <= (RXEQSCAN_CONTROL == 2'd3) ? 1'd0 : adapt_done_cnt + 1'd1;
end
else
begin
fsm <= FSM_NEW_TXCOEFF_REQ;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd1;
lffs_sel <= lffs_sel;
adapt_done <= (adapt_done_cnt == 1'd1) || (RXEQSCAN_CONTROL == 2'd3);
adapt_done_cnt <= adapt_done_cnt;
end
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= 18'd0;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= 1'd0;
end
endcase
end
end
//---------- RXEQ Eye Scan Output ----------------------------------------------
assign RXEQSCAN_PRESET_DONE = preset_done;
assign RXEQSCAN_NEW_TXCOEFF = new_txcoeff;
assign RXEQSCAN_NEW_TXCOEFF_DONE = new_txcoeff_done;
assign RXEQSCAN_LFFS_SEL = lffs_sel;
assign RXEQSCAN_ADAPT_DONE = adapt_done;
endmodule
|
// (c) Copyright 2010-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// AXI Register Slice
// Register selected channels on the forward and/or reverse signal paths.
// 5-channel memory-mapped AXI4 interfaces.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi_register_slice
// axic_register_slice
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_register_slice_v2_1_9_axi_register_slice #
(
parameter C_FAMILY = "virtex6",
parameter C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
// C_REG_CONFIG_*:
// 0 => BYPASS = The channel is just wired through the module.
// 1 => FWD_REV = Both FWD and REV (fully-registered)
// 2 => FWD = The master VALID and payload signals are registrated.
// 3 => REV = The slave ready signal is registrated
// 4 => SLAVE_FWD = All slave side signals and master VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are registrated.
// 7 => LIGHT_WT = 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// 9 => SI/MI_REG = Source side completely registered (including S_VALID input)
parameter integer C_REG_CONFIG_AW = 0,
parameter integer C_REG_CONFIG_W = 0,
parameter integer C_REG_CONFIG_B = 0,
parameter integer C_REG_CONFIG_AR = 0,
parameter integer C_REG_CONFIG_R = 0
)
(
// System Signals
input wire aclk,
input wire aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready
);
wire reset;
localparam C_AXI_SUPPORTS_REGION_SIGNALS = (C_AXI_PROTOCOL == 0) ? 1 : 0;
`include "axi_infrastructure_v1_1_0_header.vh"
wire [G_AXI_AWPAYLOAD_WIDTH-1:0] s_awpayload;
wire [G_AXI_AWPAYLOAD_WIDTH-1:0] m_awpayload;
wire [G_AXI_WPAYLOAD_WIDTH-1:0] s_wpayload;
wire [G_AXI_WPAYLOAD_WIDTH-1:0] m_wpayload;
wire [G_AXI_BPAYLOAD_WIDTH-1:0] s_bpayload;
wire [G_AXI_BPAYLOAD_WIDTH-1:0] m_bpayload;
wire [G_AXI_ARPAYLOAD_WIDTH-1:0] s_arpayload;
wire [G_AXI_ARPAYLOAD_WIDTH-1:0] m_arpayload;
wire [G_AXI_RPAYLOAD_WIDTH-1:0] s_rpayload;
wire [G_AXI_RPAYLOAD_WIDTH-1:0] m_rpayload;
assign reset = ~aresetn;
axi_infrastructure_v1_1_0_axi2vector #(
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( C_AXI_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( C_AXI_AWUSER_WIDTH ) ,
.C_AXI_ARUSER_WIDTH ( C_AXI_ARUSER_WIDTH ) ,
.C_AXI_WUSER_WIDTH ( C_AXI_WUSER_WIDTH ) ,
.C_AXI_RUSER_WIDTH ( C_AXI_RUSER_WIDTH ) ,
.C_AXI_BUSER_WIDTH ( C_AXI_BUSER_WIDTH ) ,
.C_AWPAYLOAD_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_WPAYLOAD_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_BPAYLOAD_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_ARPAYLOAD_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_RPAYLOAD_WIDTH ( G_AXI_RPAYLOAD_WIDTH )
)
axi_infrastructure_v1_1_0_axi2vector_0 (
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( s_axi_awlock ) ,
.s_axi_awcache ( s_axi_awcache ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( s_axi_awqos ) ,
.s_axi_awuser ( s_axi_awuser ) ,
.s_axi_awregion ( s_axi_awregion ) ,
.s_axi_wid ( s_axi_wid ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( s_axi_wuser ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( s_axi_buser ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( s_axi_arlock ) ,
.s_axi_arcache ( s_axi_arcache ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( s_axi_arqos ) ,
.s_axi_aruser ( s_axi_aruser ) ,
.s_axi_arregion ( s_axi_arregion ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( s_axi_ruser ) ,
.s_awpayload ( s_awpayload ) ,
.s_wpayload ( s_wpayload ) ,
.s_bpayload ( s_bpayload ) ,
.s_arpayload ( s_arpayload ) ,
.s_rpayload ( s_rpayload )
);
axi_register_slice_v2_1_9_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_AW )
)
aw_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_awpayload),
.S_VALID(s_axi_awvalid),
.S_READY(s_axi_awready),
// Master side
.M_PAYLOAD_DATA(m_awpayload),
.M_VALID(m_axi_awvalid),
.M_READY(m_axi_awready)
);
axi_register_slice_v2_1_9_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_W )
)
w_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_wpayload),
.S_VALID(s_axi_wvalid),
.S_READY(s_axi_wready),
// Master side
.M_PAYLOAD_DATA(m_wpayload),
.M_VALID(m_axi_wvalid),
.M_READY(m_axi_wready)
);
axi_register_slice_v2_1_9_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_B )
)
b_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(m_bpayload),
.S_VALID(m_axi_bvalid),
.S_READY(m_axi_bready),
// Master side
.M_PAYLOAD_DATA(s_bpayload),
.M_VALID(s_axi_bvalid),
.M_READY(s_axi_bready)
);
axi_register_slice_v2_1_9_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_AR )
)
ar_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(s_arpayload),
.S_VALID(s_axi_arvalid),
.S_READY(s_axi_arready),
// Master side
.M_PAYLOAD_DATA(m_arpayload),
.M_VALID(m_axi_arvalid),
.M_READY(m_axi_arready)
);
axi_register_slice_v2_1_9_axic_register_slice # (
.C_FAMILY ( C_FAMILY ) ,
.C_DATA_WIDTH ( G_AXI_RPAYLOAD_WIDTH ) ,
.C_REG_CONFIG ( C_REG_CONFIG_R )
)
r_pipe (
// System Signals
.ACLK(aclk),
.ARESET(reset),
// Slave side
.S_PAYLOAD_DATA(m_rpayload),
.S_VALID(m_axi_rvalid),
.S_READY(m_axi_rready),
// Master side
.M_PAYLOAD_DATA(s_rpayload),
.M_VALID(s_axi_rvalid),
.M_READY(s_axi_rready)
);
axi_infrastructure_v1_1_0_vector2axi #(
.C_AXI_PROTOCOL ( C_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( C_AXI_SUPPORTS_USER_SIGNALS ) ,
.C_AXI_SUPPORTS_REGION_SIGNALS ( C_AXI_SUPPORTS_REGION_SIGNALS ) ,
.C_AXI_AWUSER_WIDTH ( C_AXI_AWUSER_WIDTH ) ,
.C_AXI_ARUSER_WIDTH ( C_AXI_ARUSER_WIDTH ) ,
.C_AXI_WUSER_WIDTH ( C_AXI_WUSER_WIDTH ) ,
.C_AXI_RUSER_WIDTH ( C_AXI_RUSER_WIDTH ) ,
.C_AXI_BUSER_WIDTH ( C_AXI_BUSER_WIDTH ) ,
.C_AWPAYLOAD_WIDTH ( G_AXI_AWPAYLOAD_WIDTH ) ,
.C_WPAYLOAD_WIDTH ( G_AXI_WPAYLOAD_WIDTH ) ,
.C_BPAYLOAD_WIDTH ( G_AXI_BPAYLOAD_WIDTH ) ,
.C_ARPAYLOAD_WIDTH ( G_AXI_ARPAYLOAD_WIDTH ) ,
.C_RPAYLOAD_WIDTH ( G_AXI_RPAYLOAD_WIDTH )
)
axi_infrastructure_v1_1_0_vector2axi_0 (
.m_awpayload ( m_awpayload ) ,
.m_wpayload ( m_wpayload ) ,
.m_bpayload ( m_bpayload ) ,
.m_arpayload ( m_arpayload ) ,
.m_rpayload ( m_rpayload ) ,
.m_axi_awid ( m_axi_awid ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( m_axi_awlen ) ,
.m_axi_awsize ( m_axi_awsize ) ,
.m_axi_awburst ( m_axi_awburst ) ,
.m_axi_awlock ( m_axi_awlock ) ,
.m_axi_awcache ( m_axi_awcache ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( m_axi_awqos ) ,
.m_axi_awuser ( m_axi_awuser ) ,
.m_axi_awregion ( m_axi_awregion ) ,
.m_axi_wid ( m_axi_wid ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( m_axi_wlast ) ,
.m_axi_wuser ( m_axi_wuser ) ,
.m_axi_bid ( m_axi_bid ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( m_axi_buser ) ,
.m_axi_arid ( m_axi_arid ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( m_axi_arlen ) ,
.m_axi_arsize ( m_axi_arsize ) ,
.m_axi_arburst ( m_axi_arburst ) ,
.m_axi_arlock ( m_axi_arlock ) ,
.m_axi_arcache ( m_axi_arcache ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( m_axi_arqos ) ,
.m_axi_aruser ( m_axi_aruser ) ,
.m_axi_arregion ( m_axi_arregion ) ,
.m_axi_rid ( m_axi_rid ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( m_axi_rlast ) ,
.m_axi_ruser ( m_axi_ruser )
);
endmodule // axi_register_slice
|
/*
* Milkymist SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module softusb_tx(
input usb_clk,
input usb_rst,
input [7:0] tx_data,
input tx_valid,
output reg tx_ready,
output reg txp,
output reg txm,
output reg txoe,
input low_speed,
input generate_eop
);
/* Register outputs */
reg txp_r;
reg txm_r;
reg txoe_r;
always @(posedge usb_clk) begin
txp <= txp_r;
txm <= txm_r;
txoe <= txoe_r;
end
/* Clock 'divider' */
reg gce; /* global clock enable */
reg [5:0] gce_counter;
always @(posedge usb_clk) begin
if(usb_rst) begin
gce <= 1'b0;
gce_counter <= 6'd0;
end else begin
gce <= 1'b0;
gce_counter <= gce_counter + 6'd1;
if((low_speed & gce_counter == 6'd47) | (~low_speed & gce_counter == 6'd5)) begin
gce <= 1'b1;
gce_counter <= 6'd0;
end
end
end
/* Shift register w/bit stuffing */
reg sr_rst;
reg sr_load;
reg sr_done;
reg sr_out;
reg [2:0] bitcount;
reg [2:0] onecount;
reg [6:0] sr;
always @(posedge usb_clk) begin
if(sr_rst) begin
sr_done <= 1'b1;
onecount <= 3'd0;
sr_out <= 1'b1;
end else if(gce) begin
if(sr_load) begin
sr_done <= 1'b0;
sr_out <= tx_data[0];
bitcount <= 3'd0;
if(tx_data[0])
onecount <= onecount + 3'd1;
else
onecount <= 3'd0;
sr <= tx_data[7:1];
end else if(~sr_done) begin
if(onecount == 3'd6) begin
onecount <= 3'd0;
sr_out <= 1'b0;
if(bitcount == 3'd7)
sr_done <= 1'b1;
end else begin
sr_out <= sr[0];
if(sr[0])
onecount <= onecount + 3'd1;
else
onecount <= 3'd0;
bitcount <= bitcount + 3'd1;
if((bitcount == 3'd6) & (~sr[0] | (onecount != 3'd5)))
sr_done <= 1'b1;
sr <= {1'b0, sr[6:1]};
end
end
end
end
/* Output generation */
reg txoe_ctl;
reg generate_se0;
reg generate_j;
always @(posedge usb_clk) begin
if(usb_rst) begin
txoe_r <= 1'b0;
txp_r <= ~low_speed;
txm_r <= low_speed;
end else if(gce) begin
if(~txoe_ctl) begin
txp_r <= ~low_speed; /* return to J */
txm_r <= low_speed;
end else begin
case({generate_se0, generate_j})
2'b00: begin
if(~sr_out) begin
txp_r <= ~txp_r;
txm_r <= ~txm_r;
end
end
2'b10: begin
txp_r <= 1'b0;
txm_r <= 1'b0;
end
2'b01: begin
txp_r <= ~low_speed;
txm_r <= low_speed;
end
default: begin
txp_r <= 1'bx;
txm_r <= 1'bx;
end
endcase
end
txoe_r <= txoe_ctl;
end
end
/* Sequencer */
parameter IDLE = 3'd0;
parameter DATA = 3'd1;
parameter EOP1 = 3'd2;
parameter EOP2 = 3'd3;
parameter J = 3'd4;
parameter GEOP1 = 3'd5;
parameter GEOP2 = 3'd6;
parameter GJ = 3'd7;
reg [2:0] state;
reg [2:0] next_state;
always @(posedge usb_clk) begin
if(usb_rst)
state <= IDLE;
else if(gce)
state <= next_state;
end
reg tx_ready0;
always @(posedge usb_clk)
tx_ready <= tx_ready0 & gce;
reg tx_valid_r;
reg transmission_continue;
reg transmission_end_ack;
always @(posedge usb_clk) begin
if(usb_rst) begin
tx_valid_r <= 1'b0;
transmission_continue <= 1'b1;
end else begin
tx_valid_r <= tx_valid;
if(tx_valid_r & ~tx_valid)
transmission_continue <= 1'b0;
if(transmission_end_ack)
transmission_continue <= 1'b1;
end
end
reg generate_eop_pending;
reg generate_eop_clear;
always @(posedge usb_clk) begin
if(usb_rst)
generate_eop_pending <= 1'b0;
else begin
if(generate_eop)
generate_eop_pending <= 1'b1;
if(generate_eop_clear)
generate_eop_pending <= 1'b0;
end
end
always @(*) begin
txoe_ctl = 1'b0;
sr_rst = 1'b0;
sr_load = 1'b0;
generate_se0 = 1'b0;
generate_j = 1'b0;
tx_ready0 = 1'b0;
transmission_end_ack = 1'b0;
generate_eop_clear = 1'b0;
next_state = state;
case(state)
IDLE: begin
txoe_ctl = 1'b0;
if(generate_eop_pending)
next_state = GEOP1;
else begin
if(tx_valid) begin
sr_load = 1'b1;
tx_ready0 = 1'b1;
next_state = DATA;
end else
sr_rst = 1'b1;
end
end
DATA: begin
txoe_ctl = 1'b1;
if(sr_done) begin
if(transmission_continue) begin
sr_load = 1'b1;
tx_ready0 = 1'b1;
end else
next_state = EOP1;
end
end
EOP1: begin
transmission_end_ack = 1'b1;
sr_rst = 1'b1;
txoe_ctl = 1'b1;
generate_se0 = 1'b1;
next_state = EOP2;
end
EOP2: begin
sr_rst = 1'b1;
txoe_ctl = 1'b1;
generate_se0 = 1'b1;
next_state = J;
end
J: begin
sr_rst = 1'b1;
txoe_ctl = 1'b1;
generate_j = 1'b1;
next_state = IDLE;
end
GEOP1: begin
sr_rst = 1'b1;
txoe_ctl = 1'b1;
generate_se0 = 1'b1;
next_state = GEOP2;
end
GEOP2: begin
sr_rst = 1'b1;
txoe_ctl = 1'b1;
generate_se0 = 1'b1;
next_state = GJ;
end
GJ: begin
generate_eop_clear = 1'b1;
sr_rst = 1'b1;
txoe_ctl = 1'b1;
generate_j = 1'b1;
next_state = IDLE;
end
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSBP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__SDFSBP_BEHAVIORAL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`include "../u_df_p_s_no_pg/sky130_fd_sc_hs__u_df_p_s_no_pg.v"
`celldefine
module sky130_fd_sc_hs__sdfsbp (
CLK ,
D ,
Q ,
Q_N ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND
);
// Module ports
input CLK ;
input D ;
output Q ;
output Q_N ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
// Local signals
wire buf_Q ;
wire SET ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hs__u_df_p_s_no_pg u_df_p_s_no_pg0 (buf_Q , mux_out, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( ( SET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( ( SET_B === 1'b1 ) && awake );
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSBP_BEHAVIORAL_V |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_niosII_core_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
module ID_EX_Seg(
input Clk,
input stall,
input flush,
input [31:0]PC_Add,
input OverflowEn,
input[2:0] condition,
input Branch,
input[2:0] PC_write,//Unknown
input[3:0] Mem_Byte_Write,
input[3:0] Rd_Write_Byte_en,
input MemWBSrc,
input Jump,
input ALUShiftSrc,
input [2:0]MemDataSrc,
input ALUSrcA,ALUSrcB,
input [3:0] ALUOp,
input [1:0] RegDst,
input ShiftAmountSrc,
input [1:0] ShiftOp,
input [31:0] OperandA,OperandB,
input [4:0]Rs,Rt,Rd,
input [31:0] Immediate32,
input [4:0]Shamt,
input BranchSel,
input [1:0] RtRead,
output reg [31:0]PC_Add_out,
output reg OverflowEn_out,
output reg[2:0] condition_out,
output reg Branch_out,
output reg[2:0] PC_write_out,
output reg[3:0] Mem_Byte_Write_out,
output reg[3:0] Rd_Write_Byte_en_out,
output reg MemWBSrc_out,
output reg Jump_out,
output reg ALUShiftSrc_out,
output reg [2:0]MemDataSrc_out,
output reg ALUSrcA_out,ALUSrcB_out,
output reg [3:0] ALUOp_out,
output reg [1:0] RegDst_out,
output reg ShiftAmountSrc_out,
output reg [1:0] ShiftOp_out,
output reg [31:0] OperandA_out,OperandB_out,
output reg [4:0] Rs_out,Rt_out,Rd_out,
output reg [31:0] Immediate32_out,
output reg [4:0]Shamt_out,
output reg BranchSel_out,
output reg [1:0] RtRead_out
);
always@(posedge Clk)
begin
if(flush)begin
PC_Add_out <= 32'h0;
OverflowEn_out <= 1'b0;
condition_out <= 3'b0;
Branch_out <= 1'b0;
PC_write_out <= 3'b0;
Mem_Byte_Write_out <= 4'b0;
Rd_Write_Byte_en_out <= 4'b0;
MemWBSrc_out <= 1'b0;
Jump_out <= 1'b0;
ALUShiftSrc_out <= 1'b0;
MemDataSrc_out <= 3'b0;
ALUSrcA_out <= 1'b0;
ALUSrcB_out <= 1'b0;
ALUOp_out <= 4'b0;
RegDst_out <= 2'b0;
ShiftAmountSrc_out <= 1'b0;
ShiftOp_out <= 2'b0;//
OperandA_out <= 32'b0;
OperandB_out <= 32'b0;
Rs_out <= 5'b0;
Rt_out <= 5'b0;
Rd_out <= 5'b0;
Immediate32_out <= 32'b0;
Shamt_out <= 5'b0;
BranchSel_out <= 1'b0;
RtRead_out <= 1'b0;
end
else if(~stall)
begin
PC_Add_out <= PC_Add;
OverflowEn_out <= OverflowEn;
condition_out <= condition;
Branch_out <= Branch;
PC_write_out <= PC_write;
Mem_Byte_Write_out <= Mem_Byte_Write;
Rd_Write_Byte_en_out <= Rd_Write_Byte_en;
MemWBSrc_out <= MemWBSrc;
Jump_out <= Jump;
ALUShiftSrc_out <= ALUShiftSrc;
MemDataSrc_out <= MemDataSrc;
ALUSrcA_out <= ALUSrcA;
ALUSrcB_out <= ALUSrcB;
ALUOp_out <= ALUOp;
RegDst_out <= RegDst;
ShiftAmountSrc_out <= ShiftAmountSrc;
ShiftOp_out <= ShiftOp;
OperandA_out <= OperandA;
OperandB_out <= OperandB;
Rs_out <= Rs;
Rt_out <= Rt;
Rd_out <= Rd;
Immediate32_out <= Immediate32;
Shamt_out <= Shamt;
BranchSel_out <= BranchSel;
RtRead_out <= RtRead;
end
end
endmodule |
// (c) Copyright 1995-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
(* DowngradeIPIdentifiedWarnings="yes" *)
(* X_CORE_INFO = "ila,Vivado 2015.2" *)
(* CHECK_LICENSE_TYPE = "ila_0,ila,{}" *)
(* CORE_GENERATION_INFO = "ila_0,ila,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=ila,x_ipVersion=5.1,x_ipLanguage=VERILOG,C_XLNX_HW_PROBE_INFO=NUM_OF_PROBES=1_DATA_DEPTH=1024_PROBE0_WIDTH=1_PROBE0_MU_CNT=4_PROBE1_WIDTH=1_PROBE1_MU_CNT=4_PROBE2_WIDTH=1_PROBE2_MU_CNT=4_PROBE3_WIDTH=1_PROBE3_MU_CNT=4_PROBE4_WIDTH=1_PROBE4_MU_CNT=4_PROBE5_WIDTH=1_PROBE5_MU_CNT=4_PROBE6_WIDTH=1_PROBE6_MU_CNT=4_PROBE7_WIDTH=1_PROBE7_MU_CNT=4_PROBE8_WIDTH=1_PROBE8_MU_CNT=4_PROBE9_WIDTH=1_PROBE9_MU_CNT=4_PROBE10_WIDTH=1_PROBE10_MU_CNT=4_PROBE11_WIDTH=1_PROBE11_MU_CNT=4_PROBE12_WIDTH=1_PROBE12_MU_CNT=4_PROBE13_WIDTH=1_PROBE13_MU_CNT=4_PROBE14_WIDTH=1_PROBE14_MU_CNT=4_PROBE15_WIDTH=1_PROBE15_MU_CNT=4_PROBE16_WIDTH=1_PROBE16_MU_CNT=4_PROBE17_WIDTH=1_PROBE17_MU_CNT=4_PROBE18_WIDTH=1_PROBE18_MU_CNT=4_PROBE19_WIDTH=1_PROBE19_MU_CNT=4_PROBE20_WIDTH=1_PROBE20_MU_CNT=4_PROBE21_WIDTH=1_PROBE21_MU_CNT=4_PROBE22_WIDTH=1_PROBE22_MU_CNT=4_PROBE23_WIDTH=1_PROBE23_MU_CNT=4_PROBE24_WIDTH=1_PROBE24_MU_CNT=4_PROBE25_WIDTH=1_PROBE25_MU_CNT=4_PROBE26_WIDTH=1_PROBE26_MU_CNT=4_PROBE27_WIDTH=1_PROBE27_MU_CNT=4_PROBE28_WIDTH=1_PROBE28_MU_CNT=4_PROBE29_WIDTH=1_PROBE29_MU_CNT=4_PROBE30_WIDTH=1_PROBE30_MU_CNT=4_PROBE31_WIDTH=1_PROBE31_MU_CNT=4_PROBE32_WIDTH=1_PROBE32_MU_CNT=4_PROBE33_WIDTH=1_PROBE33_MU_CNT=4_PROBE34_WIDTH=1_PROBE34_MU_CNT=4_PROBE35_WIDTH=1_PROBE35_MU_CNT=4_PROBE36_WIDTH=1_PROBE36_MU_CNT=4_PROBE37_WIDTH=1_PROBE37_MU_CNT=4_PROBE38_WIDTH=1_PROBE38_MU_CNT=4_PROBE39_WIDTH=1_PROBE39_MU_CNT=4_PROBE40_WIDTH=1_PROBE40_MU_CNT=4_PROBE41_WIDTH=1_PROBE41_MU_CNT=4_PROBE42_WIDTH=1_PROBE42_MU_CNT=4_PROBE43_WIDTH=1_PROBE43_MU_CNT=4_PROBE44_WIDTH=1_PROBE44_MU_CNT=4_PROBE45_WIDTH=1_PROBE45_MU_CNT=1_PROBE46_WIDTH=1_PROBE46_MU_CNT=1_PROBE47_WIDTH=1_PROBE47_MU_CNT=1_PROBE48_WIDTH=1_PROBE48_MU_CNT=1_PROBE49_WIDTH=1_PROBE49_MU_CNT=1_PROBE50_WIDTH=1_PROBE50_MU_CNT=1_PROBE51_WIDTH=1_PROBE51_MU_CNT=1_PROBE52_WIDTH=1_PROBE52_MU_CNT=1_PROBE53_WIDTH=1_PROBE53_MU_CNT=1_PROBE54_WIDTH=1_PROBE54_MU_CNT=1_PROBE55_WIDTH=1_PROBE55_MU_CNT=1_PROBE56_WIDTH=1_PROBE56_MU_CNT=1_PROBE57_WIDTH=1_PROBE57_MU_CNT=1_PROBE58_WIDTH=1_PROBE58_MU_CNT=1_PROBE59_WIDTH=1_PROBE59_MU_CNT=1_PROBE60_WIDTH=1_PROBE60_MU_CNT=1_PROBE61_WIDTH=1_PROBE61_MU_CNT=1_PROBE62_WIDTH=1_PROBE62_MU_CNT=1_PROBE63_WIDTH=1_PROBE63_MU_CNT=1_PROBE64_WIDTH=1_PROBE64_MU_CNT=1_PROBE65_WIDTH=1_PROBE65_MU_CNT=1_PROBE66_WIDTH=1_PROBE66_MU_CNT=1_PROBE67_WIDTH=1_PROBE67_MU_CNT=1_PROBE68_WIDTH=1_PROBE68_MU_CNT=1_PROBE69_WIDTH=1_PROBE69_MU_CNT=1_PROBE70_WIDTH=1_PROBE70_MU_CNT=1_PROBE71_WIDTH=1_PROBE71_MU_CNT=1_PROBE72_WIDTH=1_PROBE72_MU_CNT=1_PROBE73_WIDTH=1_PROBE73_MU_CNT=1_PROBE74_WIDTH=1_PROBE74_MU_CNT=1_PROBE75_WIDTH=1_PROBE75_MU_CNT=1_PROBE76_WIDTH=1_PROBE76_MU_CNT=1_PROBE77_WIDTH=1_PROBE77_MU_CNT=1_PROBE78_WIDTH=1_PROBE78_MU_CNT=1_PROBE79_WIDTH=1_PROBE79_MU_CNT=1_PROBE80_WIDTH=1_PROBE80_MU_CNT=1_PROBE81_WIDTH=1_PROBE81_MU_CNT=1_PROBE82_WIDTH=1_PROBE82_MU_CNT=1_PROBE83_WIDTH=1_PROBE83_MU_CNT=1_PROBE84_WIDTH=1_PROBE84_MU_CNT=1_PROBE85_WIDTH=1_PROBE85_MU_CNT=1_PROBE86_WIDTH=1_PROBE86_MU_CNT=1_PROBE87_WIDTH=1_PROBE87_MU_CNT=1_PROBE88_WIDTH=1_PROBE88_MU_CNT=1_PROBE89_WIDTH=1_PROBE89_MU_CNT=1_PROBE90_WIDTH=1_PROBE90_MU_CNT=1_PROBE91_WIDTH=1_PROBE91_MU_CNT=1_PROBE92_WIDTH=1_PROBE92_MU_CNT=1_PROBE93_WIDTH=1_PROBE93_MU_CNT=1_PROBE94_WIDTH=1_PROBE94_MU_CNT=1_PROBE95_WIDTH=1_PROBE95_MU_CNT=1_PROBE96_WIDTH=1_PROBE96_MU_CNT=1_PROBE97_WIDTH=1_PROBE97_MU_CNT=1_PROBE98_WIDTH=1_PROBE98_MU_CNT=1_PROBE99_WIDTH=1_PROBE99_MU_CNT=1_PROBE100_WIDTH=1_PROBE100_MU_CNT=1_PROBE101_WIDTH=1_PROBE101_MU_CNT=1_PROBE102_WIDTH=1_PROBE102_MU_CNT=1_PROBE103_WIDTH=1_PROBE103_MU_CNT=1_PROBE104_WIDTH=1_PROBE104_MU_CNT=1_PROBE105_WIDTH=1_PROBE105_MU_CNT=1_PROBE106_WIDTH=1_PROBE106_MU_CNT=1_PROBE107_WIDTH=1_PROBE107_MU_CNT=1_PROBE108_WIDTH=1_PROBE108_MU_CNT=1_PROBE109_WIDTH=1_PROBE109_MU_CNT=1_PROBE110_WIDTH=1_PROBE110_MU_CNT=1_PROBE111_WIDTH=1_PROBE111_MU_CNT=1_PROBE112_WIDTH=1_PROBE112_MU_CNT=1_PROBE113_WIDTH=1_PROBE113_MU_CNT=1_PROBE114_WIDTH=1_PROBE114_MU_CNT=1_PROBE115_WIDTH=1_PROBE115_MU_CNT=1_PROBE116_WIDTH=1_PROBE116_MU_CNT=1_PROBE117_WIDTH=1_PROBE117_MU_CNT=1_PROBE118_WIDTH=1_PROBE118_MU_CNT=1_PROBE119_WIDTH=1_PROBE119_MU_CNT=1_PROBE120_WIDTH=1_PROBE120_MU_CNT=1_PROBE121_WIDTH=1_PROBE121_MU_CNT=1_PROBE122_WIDTH=1_PROBE122_MU_CNT=1_PROBE123_WIDTH=1_PROBE123_MU_CNT=1_PROBE124_WIDTH=1_PROBE124_MU_CNT=1_PROBE125_WIDTH=1_PROBE125_MU_CNT=1_PROBE126_WIDTH=1_PROBE126_MU_CNT=1_PROBE127_WIDTH=1_PROBE127_MU_CNT=1_PROBE128_WIDTH=1_PROBE128_MU_CNT=1_PROBE129_WIDTH=1_PROBE129_MU_CNT=1_PROBE130_WIDTH=1_PROBE130_MU_CNT=1_PROBE131_WIDTH=1_PROBE131_MU_CNT=1_PROBE132_WIDTH=1_PROBE132_MU_CNT=1_PROBE133_WIDTH=1_PROBE133_MU_CNT=1_PROBE134_WIDTH=1_PROBE134_MU_CNT=1_PROBE135_WIDTH=1_PROBE135_MU_CNT=1_PROBE136_WIDTH=1_PROBE136_MU_CNT=1_PROBE137_WIDTH=1_PROBE137_MU_CNT=1_PROBE138_WIDTH=1_PROBE138_MU_CNT=1_PROBE139_WIDTH=1_PROBE139_MU_CNT=1_PROBE140_WIDTH=1_PROBE140_MU_CNT=1_PROBE141_WIDTH=1_PROBE141_MU_CNT=1_PROBE142_WIDTH=1_PROBE142_MU_CNT=1_PROBE143_WIDTH=1_PROBE143_MU_CNT=1_PROBE144_WIDTH=1_PROBE144_MU_CNT=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OBE986_WIDTH=1,C_PROBE987_WIDTH=1,C_PROBE988_WIDTH=1,C_PROBE989_WIDTH=1,C_PROBE990_WIDTH=1,C_PROBE991_WIDTH=1,C_PROBE992_WIDTH=1,C_PROBE993_WIDTH=1,C_PROBE994_WIDTH=1,C_PROBE995_WIDTH=1,C_PROBE996_WIDTH=1,C_PROBE997_WIDTH=1,C_PROBE998_WIDTH=1,C_PROBE999_WIDTH=1,C_PROBE1000_WIDTH=1,C_PROBE1001_WIDTH=1,C_PROBE1002_WIDTH=1,C_PROBE1003_WIDTH=1,C_PROBE1004_WIDTH=1,C_PROBE1005_WIDTH=1,C_PROBE1006_WIDTH=1,C_PROBE1007_WIDTH=1,C_PROBE1008_WIDTH=1,C_PROBE1009_WIDTH=1,C_PROBE1010_WIDTH=1,C_PROBE1011_WIDTH=1,C_PROBE1012_WIDTH=1,C_PROBE1013_WIDTH=1,C_PROBE1014_WIDTH=1,C_PROBE1015_WIDTH=1,C_PROBE1016_WIDTH=1,C_PROBE1017_WIDTH=1,C_PROBE1018_WIDTH=1,C_PROBE1019_WIDTH=1,C_PROBE1020_WIDTH=1,C_PROBE1021_WIDTH=1,C_PROBE1022_WIDTH=1,C_PROBE1023_WIDTH=1,C_PROBE0_MU_CNT=4,C_PROBE1_MU_CNT=1,C_PROBE2_MU_CNT=1,C_PROBE3_MU_CNT=1,C_PROBE4_MU_CNT=1,C_PROBE5_MU_CNT=1,C_PROBE6_MU_CNT=1,C_PROBE7_MU_CNT=1,C_PROBE8_MU_CNT=1,C_PROBE9_MU_CNT=1,C_PROBE10_MU_CNT=1,C_PROBE11_MU_CNT=1,C_PROBE12_MU_CNT=1,C_PROBE13_MU_CNT=1,C_PROBE14_MU_CNT=1,C_PROBE15_MU_CNT=1,C_PROBE16_MU_CNT=1,C_PROBE17_MU_CNT=1,C_PROBE18_MU_CNT=1,C_PROBE19_MU_CNT=1,C_PROBE20_MU_CNT=1,C_PROBE21_MU_CNT=1,C_PROBE22_MU_CNT=1,C_PROBE23_MU_CNT=1,C_PROBE24_MU_CNT=1,C_PROBE25_MU_CNT=1,C_PROBE26_MU_CNT=1,C_PROBE27_MU_CNT=1,C_PROBE28_MU_CNT=1,C_PROBE29_MU_CNT=1,C_PROBE30_MU_CNT=1,C_PROBE31_MU_CNT=1,C_PROBE32_MU_CNT=1,C_PROBE33_MU_CNT=1,C_PROBE34_MU_CNT=1,C_PROBE35_MU_CNT=1,C_PROBE36_MU_CNT=1,C_PROBE37_MU_CNT=1,C_PROBE38_MU_CNT=1,C_PROBE39_MU_CNT=1,C_PROBE40_MU_CNT=1,C_PROBE41_MU_CNT=1,C_PROBE42_MU_CNT=1,C_PROBE43_MU_CNT=1,C_PROBE44_MU_CNT=1,C_PROBE45_MU_CNT=1,C_PROBE46_MU_CNT=1,C_PROBE47_MU_CNT=1,C_PROBE48_MU_CNT=1,C_PROBE49_MU_CNT=1,C_PROBE50_MU_CNT=1,C_PROBE51_MU_CNT=1,C_PROBE52_MU_CNT=1,C_PROBE53_MU_CNT=1,C_PROBE54_MU_CNT=1,C_PROBE55_MU_CNT=1,C_PROBE56_MU_CNT=1,C_PROBE57_MU_CNT=1,C_PROBE58_MU_CNT=1,C_PROBE59_MU_CNT=1,C_PROBE60_MU_CNT=1,C_PROBE61_MU_CNT=1,C_PROBE62_MU_CNT=1,C_PROBE63_MU_CNT=1,C_PROBE64_MU_CNT=1,C_PROBE65_MU_CNT=1,C_PROBE66_MU_CNT=1,C_PROBE67_MU_CNT=1,C_PROBE68_MU_CNT=1,C_PROBE69_MU_CNT=1,C_PROBE70_MU_CNT=1,C_PROBE71_MU_CNT=1,C_PROBE72_MU_CNT=1,C_PROBE73_MU_CNT=1,C_PROBE74_MU_CNT=1,C_PROBE75_MU_CNT=1,C_PROBE76_MU_CNT=1,C_PROBE77_MU_CNT=1,C_PROBE78_MU_CNT=1,C_PROBE79_MU_CNT=1,C_PROBE80_MU_CNT=1,C_PROBE81_MU_CNT=1,C_PROBE82_MU_CNT=1,C_PROBE83_MU_CNT=1,C_PROBE84_MU_CNT=1,C_PROBE85_MU_CNT=1,C_PROBE86_MU_CNT=1,C_PROBE87_MU_CNT=1,C_PROBE88_MU_CNT=1,C_PROBE89_MU_CNT=1,C_PROBE90_MU_CNT=1,C_PROBE91_MU_CNT=1,C_PROBE92_MU_CNT=1,C_PROBE93_MU_CNT=1,C_PROBE94_MU_CNT=1,C_PROBE95_MU_CNT=1,C_PROBE96_MU_CNT=1,C_PROBE97_MU_CNT=1,C_PROBE98_MU_CNT=1,C_PROBE99_MU_CNT=1,C_PROBE100_MU_CNT=1,C_PROBE101_MU_CNT=1,C_PROBE102_MU_CNT=1,C_PROBE103_MU_CNT=1,C_PROBE104_MU_CNT=1,C_PROBE105_MU_CNT=1,C_PROBE106_MU_CNT=1,C_PROBE107_MU_CNT=1,C_PROBE108_MU_CNT=1,C_PROBE109_MU_CNT=1,C_PROBE110_MU_CNT=1,C_PROBE111_MU_CNT=1,C_PROBE112_MU_CNT=1,C_PROBE113_MU_CNT=1,C_PROBE114_MU_CNT=1,C_PROBE115_MU_CNT=1,C_PROBE116_MU_CNT=1,C_PROBE117_MU_CNT=1,C_PROBE118_MU_CNT=1,C_PROBE119_MU_CNT=1,C_PROBE120_MU_CNT=1,C_PROBE121_MU_CNT=1,C_PROBE122_MU_CNT=1,C_PROBE123_MU_CNT=1,C_PROBE124_MU_CNT=1,C_PROBE125_MU_CNT=1,C_PROBE126_MU_CNT=1,C_PROBE127_MU_CNT=1,C_PROBE128_MU_CNT=1,C_PROBE129_MU_CNT=1,C_PROBE130_MU_CNT=1,C_PROBE131_MU_CNT=1,C_PROBE132_MU_CNT=1,C_PROBE133_MU_CNT=1,C_PROBE134_MU_CNT=1,C_PROBE135_MU_CNT=1,C_PROBE136_MU_CNT=1,C_PROBE137_MU_CNT=1,C_PROBE138_MU_CNT=1,C_PROBE139_MU_CNT=1,C_PROBE140_MU_CNT=1,C_PROBE141_MU_CNT=1,C_PROBE142_MU_CNT=1,C_PROBE143_MU_CNT=1,C_PROBE144_MU_CNT=1,C_PROBE145_MU_CNT=1,C_PROBE146_MU_CNT=1,C_PROBE147_MU_CNT=1,C_PROBE148_MU_CNT=1,C_PROBE149_MU_CNT=1,C_PROBE150_MU_CNT=1,C_PROBE151_MU_CNT=1,C_PROBE152_MU_CNT=1,C_PROBE153_MU_CNT=1,C_PROBE154_MU_CNT=1,C_PROBE155_MU_CNT=1,C_PROBE156_MU_CNT=1,C_PROBE157_MU_CNT=1,C_PROBE158_MU_CNT=1,C_PROBE159_MU_CNT=1,C_PROBE160_MU_CNT=1,C_PROBE161_MU_CNT=1,C_PROBE162_MU_CNT=1,C_PROBE163_MU_CNT=1,C_PROBE164_MU_CNT=1,C_PROBE165_MU_CNT=1,C_PROBE166_MU_CNT=1,C_PROBE167_MU_CNT=1,C_PROBE168_MU_CNT=1,C_PROBE169_MU_CNT=1,C_PROBE170_MU_CNT=1,C_PROBE171_MU_CNT=1,C_PROBE172_MU_CNT=1,C_PROBE173_MU_CNT=1,C_PROBE174_MU_CNT=1,C_PROBE175_MU_CNT=1,C_PROBE176_MU_CNT=1,C_PROBE177_MU_CNT=1,C_PROBE178_MU_CNT=1,C_PROBE179_MU_CNT=1,C_PROBE180_MU_CNT=1,C_PROBE181_MU_CNT=1,C_PROBE182_MU_CNT=1,C_PROBE183_MU_CNT=1,C_PROBE184_MU_CNT=1,C_PROBE185_MU_CNT=1,C_PROBE186_MU_CNT=1,C_PROBE187_MU_CNT=1,C_PROBE188_MU_CNT=1,C_PROBE189_MU_CNT=1,C_PROBE190_MU_CNT=1,C_PROBE191_MU_CNT=1,C_PROBE192_MU_CNT=1,C_PROBE193_MU_CNT=1,C_PROBE194_MU_CNT=1,C_PROBE195_MU_CNT=1,C_PROBE196_MU_CNT=1,C_PROBE197_MU_CNT=1,C_PROBE198_MU_CNT=1,C_PROBE199_MU_CNT=1,C_PROBE200_MU_CNT=1,C_PROBE201_MU_CNT=1,C_PROBE202_MU_CNT=1,C_PROBE203_MU_CNT=1,C_PROBE204_MU_CNT=1,C_PROBE205_MU_CNT=1,C_PROBE206_MU_CNT=1,C_PROBE207_MU_CNT=1,C_PROBE208_MU_CNT=1,C_PROBE209_MU_CNT=1,C_PROBE210_MU_CNT=1,C_PROBE211_MU_CNT=1,C_PROBE212_MU_CNT=1,C_PROBE213_MU_CNT=1,C_PROBE214_MU_CNT=1,C_PROBE215_MU_CNT=1,C_PROBE216_MU_CNT=1,C_PROBE217_MU_CNT=1,C_PROBE218_MU_CNT=1,C_PROBE219_MU_CNT=1,C_PROBE220_MU_CNT=1,C_PROBE221_MU_CNT=1,C_PROBE222_MU_CNT=1,C_PROBE223_MU_CNT=1,C_PROBE224_MU_CNT=1,C_PROBE225_MU_CNT=1,C_PROBE226_MU_CNT=1,C_PROBE227_MU_CNT=1,C_PROBE228_MU_CNT=1,C_PROBE229_MU_CNT=1,C_PROBE230_MU_CNT=1,C_PROBE231_MU_CNT=1,C_PROBE232_MU_CNT=1,C_PROBE233_MU_CNT=1,C_PROBE234_MU_CNT=1,C_PROBE235_MU_CNT=1,C_PROBE236_MU_CNT=1,C_PROBE237_MU_CNT=1,C_PROBE238_MU_CNT=1,C_PROBE239_MU_CNT=1,C_PROBE240_MU_CNT=1,C_PROBE241_MU_CNT=1,C_PROBE242_MU_CNT=1,C_PROBE243_MU_CNT=1,C_PROBE244_MU_CNT=1,C_PROBE245_MU_CNT=1,C_PROBE246_MU_CNT=1,C_PROBE247_MU_CNT=1,C_PROBE248_MU_CNT=1,C_PROBE249_MU_CNT=1,C_PROBE250_MU_CNT=1,C_PROBE251_MU_CNT=1,C_PROBE252_MU_CNT=1,C_PROBE253_MU_CNT=1,C_PROBE254_MU_CNT=1,C_PROBE255_MU_CNT=1,C_PROBE256_MU_CNT=1,C_PROBE257_MU_CNT=1,C_PROBE258_MU_CNT=1,C_PROBE259_MU_CNT=1,C_PROBE260_MU_CNT=1,C_PROBE261_MU_CNT=1,C_PROBE262_MU_CNT=1,C_PROBE263_MU_CNT=1,C_PROBE264_MU_CNT=1,C_PROBE265_MU_CNT=1,C_PROBE266_MU_CNT=1,C_PROBE267_MU_CNT=1,C_PROBE268_MU_CNT=1,C_PROBE269_MU_CNT=1,C_PROBE270_MU_CNT=1,C_PROBE271_MU_CNT=1,C_PROBE272_MU_CNT=1,C_PROBE273_MU_CNT=1,C_PROBE274_MU_CNT=1,C_PROBE275_MU_CNT=1,C_PROBE276_MU_CNT=1,C_PROBE277_MU_CNT=1,C_PROBE278_MU_CNT=1,C_PROBE279_MU_CNT=1,C_PROBE280_MU_CNT=1,C_PROBE281_MU_CNT=1,C_PROBE282_MU_CNT=1,C_PROBE283_MU_CNT=1,C_PROBE284_MU_CNT=1,C_PROBE285_MU_CNT=1,C_PROBE286_MU_CNT=1,C_PROBE287_MU_CNT=1,C_PROBE288_MU_CNT=1,C_PROBE289_MU_CNT=1,C_PROBE290_MU_CNT=1,C_PROBE291_MU_CNT=1,C_PROBE292_MU_CNT=1,C_PROBE293_MU_CNT=1,C_PROBE294_MU_CNT=1,C_PROBE295_MU_CNT=1,C_PROBE296_MU_CNT=1,C_PROBE297_MU_CNT=1,C_PROBE298_MU_CNT=1,C_PROBE299_MU_CNT=1,C_PROBE300_MU_CNT=1,C_PROBE301_MU_CNT=1,C_PROBE302_MU_CNT=1,C_PROBE303_MU_CNT=1,C_PROBE304_MU_CNT=1,C_PROBE305_MU_CNT=1,C_PROBE306_MU_CNT=1,C_PROBE307_MU_CNT=1,C_PROBE308_MU_CNT=1,C_PROBE309_MU_CNT=1,C_PROBE310_MU_CNT=1,C_PROBE311_MU_CNT=1,C_PROBE312_MU_CNT=1,C_PROBE313_MU_CNT=1,C_PROBE314_MU_CNT=1,C_PROBE315_MU_CNT=1,C_PROBE316_MU_CNT=1,C_PROBE317_MU_CNT=1,C_PROBE318_MU_CNT=1,C_PROBE319_MU_CNT=1,C_PROBE320_MU_CNT=1,C_PROBE321_MU_CNT=1,C_PROBE322_MU_CNT=1,C_PROBE323_MU_CNT=1,C_PROBE324_MU_CNT=1,C_PROBE325_MU_CNT=1,C_PROBE326_MU_CNT=1,C_PROBE327_MU_CNT=1,C_PROBE328_MU_CNT=1,C_PROBE329_MU_CNT=1,C_PROBE330_MU_CNT=1,C_PROBE331_MU_CNT=1,C_PROBE332_MU_CNT=1,C_PROBE333_MU_CNT=1,C_PROBE334_MU_CNT=1,C_PROBE335_MU_CNT=1,C_PROBE336_MU_CNT=1,C_PROBE337_MU_CNT=1,C_PROBE338_MU_CNT=1,C_PROBE339_MU_CNT=1,C_PROBE340_MU_CNT=1,C_PROBE341_MU_CNT=1,C_PROBE342_MU_CNT=1,C_PROBE343_MU_CNT=1,C_PROBE344_MU_CNT=1,C_PROBE345_MU_CNT=1,C_PROBE346_MU_CNT=1,C_PROBE347_MU_CNT=1,C_PROBE348_MU_CNT=1,C_PROBE349_MU_CNT=1,C_PROBE350_MU_CNT=1,C_PROBE351_MU_CNT=1,C_PROBE352_MU_CNT=1,C_PROBE353_MU_CNT=1,C_PROBE354_MU_CNT=1,C_PROBE355_MU_CNT=1,C_PROBE356_MU_CNT=1,C_PROBE357_MU_CNT=1,C_PROBE358_MU_CNT=1,C_PROBE359_MU_CNT=1,C_PROBE360_MU_CNT=1,C_PROBE361_MU_CNT=1,C_PROBE362_MU_CNT=1,C_PROBE363_MU_CNT=1,C_PROBE364_MU_CNT=1,C_PROBE365_MU_CNT=1,C_PROBE366_MU_CNT=1,C_PROBE367_MU_CNT=1,C_PROBE368_MU_CNT=1,C_PROBE369_MU_CNT=1,C_PROBE370_MU_CNT=1,C_PROBE371_MU_CNT=1,C_PROBE372_MU_CNT=1,C_PROBE373_MU_CNT=1,C_PROBE374_MU_CNT=1,C_PROBE375_MU_CNT=1,C_PROBE376_MU_CNT=1,C_PROBE377_MU_CNT=1,C_PROBE378_MU_CNT=1,C_PROBE379_MU_CNT=1,C_PROBE380_MU_CNT=1,C_PROBE381_MU_CNT=1,C_PROBE382_MU_CNT=1,C_PROBE383_MU_CNT=1,C_PROBE384_MU_CNT=1,C_PROBE385_MU_CNT=1,C_PROBE386_MU_CNT=1,C_PROBE387_MU_CNT=1,C_PROBE388_MU_CNT=1,C_PROBE389_MU_CNT=1,C_PROBE390_MU_CNT=1,C_PROBE391_MU_CNT=1,C_PROBE392_MU_CNT=1,C_PROBE393_MU_CNT=1,C_PROBE394_MU_CNT=1,C_PROBE395_MU_CNT=1,C_PROBE396_MU_CNT=1,C_PROBE397_MU_CNT=1,C_PROBE398_MU_CNT=1,C_PROBE399_MU_CNT=1,C_PROBE400_MU_CNT=1,C_PROBE401_MU_CNT=1,C_PROBE402_MU_CNT=1,C_PROBE403_MU_CNT=1,C_PROBE404_MU_CNT=1,C_PROBE405_MU_CNT=1,C_PROBE406_MU_CNT=1,C_PROBE407_MU_CNT=1,C_PROBE408_MU_CNT=1,C_PROBE409_MU_CNT=1,C_PROBE410_MU_CNT=1,C_PROBE411_MU_CNT=1,C_PROBE412_MU_CNT=1,C_PROBE413_MU_CNT=1,C_PROBE414_MU_CNT=1,C_PROBE415_MU_CNT=1,C_PROBE416_MU_CNT=1,C_PROBE417_MU_CNT=1,C_PROBE418_MU_CNT=1,C_PROBE419_MU_CNT=1,C_PROBE420_MU_CNT=1,C_PROBE421_MU_CNT=1,C_PROBE422_MU_CNT=1,C_PROBE423_MU_CNT=1,C_PROBE424_MU_CNT=1,C_PROBE425_MU_CNT=1,C_PROBE426_MU_CNT=1,C_PROBE427_MU_CNT=1,C_PROBE428_MU_CNT=1,C_PROBE429_MU_CNT=1,C_PROBE430_MU_CNT=1,C_PROBE431_MU_CNT=1,C_PROBE432_MU_CNT=1,C_PROBE433_MU_CNT=1,C_PROBE434_MU_CNT=1,C_PROBE435_MU_CNT=1,C_PROBE436_MU_CNT=1,C_PROBE437_MU_CNT=1,C_PROBE438_MU_CNT=1,C_PROBE439_MU_CNT=1,C_PROBE440_MU_CNT=1,C_PROBE441_MU_CNT=1,C_PROBE442_MU_CNT=1,C_PROBE443_MU_CNT=1,C_PROBE444_MU_CNT=1,C_PROBE445_MU_CNT=1,C_PROBE446_MU_CNT=1,C_PROBE447_MU_CNT=1,C_PROBE448_MU_CNT=1,C_PROBE449_MU_CNT=1,C_PROBE450_MU_CNT=1,C_PROBE451_MU_CNT=1,C_PROBE452_MU_CNT=1,C_PROBE453_MU_CNT=1,C_PROBE454_MU_CNT=1,C_PROBE455_MU_CNT=1,C_PROBE456_MU_CNT=1,C_PROBE457_MU_CNT=1,C_PROBE458_MU_CNT=1,C_PROBE459_MU_CNT=1,C_PROBE460_MU_CNT=1,C_PROBE461_MU_CNT=1,C_PROBE462_MU_CNT=1,C_PROBE463_MU_CNT=1,C_PROBE464_MU_CNT=1,C_PROBE465_MU_CNT=1,C_PROBE466_MU_CNT=1,C_PROBE467_MU_CNT=1,C_PROBE468_MU_CNT=1,C_PROBE469_MU_CNT=1,C_PROBE470_MU_CNT=1,C_PROBE471_MU_CNT=1,C_PROBE472_MU_CNT=1,C_PROBE473_MU_CNT=1,C_PROBE474_MU_CNT=1,C_PROBE475_MU_CNT=1,C_PROBE476_MU_CNT=1,C_PROBE477_MU_CNT=1,C_PROBE478_MU_CNT=1,C_PROBE479_MU_CNT=1,C_PROBE480_MU_CNT=1,C_PROBE481_MU_CNT=1,C_PROBE482_MU_CNT=1,C_PROBE483_MU_CNT=1,C_PROBE484_MU_CNT=1,C_PROBE485_MU_CNT=1,C_PROBE486_MU_CNT=1,C_PROBE487_MU_CNT=1,C_PROBE488_MU_CNT=1,C_PROBE489_MU_CNT=1,C_PROBE490_MU_CNT=1,C_PROBE491_MU_CNT=1,C_PROBE492_MU_CNT=1,C_PROBE493_MU_CNT=1,C_PROBE494_MU_CNT=1,C_PROBE495_MU_CNT=1,C_PROBE496_MU_CNT=1,C_PROBE497_MU_CNT=1,C_PROBE498_MU_CNT=1,C_PROBE499_MU_CNT=1,C_PROBE500_MU_CNT=1,C_PROBE501_MU_CNT=1,C_PROBE502_MU_CNT=1,C_PROBE503_MU_CNT=1,C_PROBE504_MU_CNT=1,C_PROBE505_MU_CNT=1,C_PROBE506_MU_CNT=1,C_PROBE507_MU_CNT=1,C_PROBE508_MU_CNT=1,C_PROBE509_MU_CNT=1,C_PROBE510_MU_CNT=1,C_PROBE511_MU_CNT=1,C_PROBE512_MU_CNT=1,C_PROBE513_MU_CNT=1,C_PROBE514_MU_CNT=1,C_PROBE515_MU_CNT=1,C_PROBE516_MU_CNT=1,C_PROBE517_MU_CNT=1,C_PROBE518_MU_CNT=1,C_PROBE519_MU_CNT=1,C_PROBE520_MU_CNT=1,C_PROBE521_MU_CNT=1,C_PROBE522_MU_CNT=1,C_PROBE523_MU_CNT=1,C_PROBE524_MU_CNT=1,C_PROBE525_MU_CNT=1,C_PROBE526_MU_CNT=1,C_PROBE527_MU_CNT=1,C_PROBE528_MU_CNT=1,C_PROBE529_MU_CNT=1,C_PROBE530_MU_CNT=1,C_PROBE531_MU_CNT=1,C_PROBE532_MU_CNT=1,C_PROBE533_MU_CNT=1,C_PROBE534_MU_CNT=1,C_PROBE535_MU_CNT=1,C_PROBE536_MU_CNT=1,C_PROBE537_MU_CNT=1,C_PROBE538_MU_CNT=1,C_PROBE539_MU_CNT=1,C_PROBE540_MU_CNT=1,C_PROBE541_MU_CNT=1,C_PROBE542_MU_CNT=1,C_PROBE543_MU_CNT=1,C_PROBE544_MU_CNT=1,C_PROBE545_MU_CNT=1,C_PROBE546_MU_CNT=1,C_PROBE547_MU_CNT=1,C_PROBE548_MU_CNT=1,C_PROBE549_MU_CNT=1,C_PROBE550_MU_CNT=1,C_PROBE551_MU_CNT=1,C_PROBE552_MU_CNT=1,C_PROBE553_MU_CNT=1,C_PROBE554_MU_CNT=1,C_PROBE555_MU_CNT=1,C_PROBE556_MU_CNT=1,C_PROBE557_MU_CNT=1,C_PROBE558_MU_CNT=1,C_PROBE559_MU_CNT=1,C_PROBE560_MU_CNT=1,C_PROBE561_MU_CNT=1,C_PROBE562_MU_CNT=1,C_PROBE563_MU_CNT=1,C_PROBE564_MU_CNT=1,C_PROBE565_MU_CNT=1,C_PROBE566_MU_CNT=1,C_PROBE567_MU_CNT=1,C_PROBE568_MU_CNT=1,C_PROBE569_MU_CNT=1,C_PROBE570_MU_CNT=1,C_PROBE571_MU_CNT=1,C_PROBE572_MU_CNT=1,C_PROBE573_MU_CNT=1,C_PROBE574_MU_CNT=1,C_PROBE575_MU_CNT=1,C_PROBE576_MU_CNT=1,C_PROBE577_MU_CNT=1,C_PROBE578_MU_CNT=1,C_PROBE579_MU_CNT=1,C_PROBE580_MU_CNT=1,C_PROBE581_MU_CNT=1,C_PROBE582_MU_CNT=1,C_PROBE583_MU_CNT=1,C_PROBE584_MU_CNT=1,C_PROBE585_MU_CNT=1,C_PROBE586_MU_CNT=1,C_PROBE587_MU_CNT=1,C_PROBE588_MU_CNT=1,C_PROBE589_MU_CNT=1,C_PROBE590_MU_CNT=1,C_PROBE591_MU_CNT=1,C_PROBE592_MU_CNT=1,C_PROBE593_MU_CNT=1,C_PROBE594_MU_CNT=1,C_PROBE595_MU_CNT=1,C_PROBE596_MU_CNT=1,C_PROBE597_MU_CNT=1,C_PROBE598_MU_CNT=1,C_PROBE599_MU_CNT=1,C_PROBE600_MU_CNT=1,C_PROBE601_MU_CNT=1,C_PROBE602_MU_CNT=1,C_PROBE603_MU_CNT=1,C_PROBE604_MU_CNT=1,C_PROBE605_MU_CNT=1,C_PROBE606_MU_CNT=1,C_PROBE607_MU_CNT=1,C_PROBE608_MU_CNT=1,C_PROBE609_MU_CNT=1,C_PROBE610_MU_CNT=1,C_PROBE611_MU_CNT=1,C_PROBE612_MU_CNT=1,C_PROBE613_MU_CNT=1,C_PROBE614_MU_CNT=1,C_PROBE615_MU_CNT=1,C_PROBE616_MU_CNT=1,C_PROBE617_MU_CNT=1,C_PROBE618_MU_CNT=1,C_PROBE619_MU_CNT=1,C_PROBE620_MU_CNT=1,C_PROBE621_MU_CNT=1,C_PROBE622_MU_CNT=1,C_PROBE623_MU_CNT=1,C_PROBE624_MU_CNT=1,C_PROBE625_MU_CNT=1,C_PROBE626_MU_CNT=1,C_PROBE627_MU_CNT=1,C_PROBE628_MU_CNT=1,C_PROBE629_MU_CNT=1,C_PROBE630_MU_CNT=1,C_PROBE631_MU_CNT=1,C_PROBE632_MU_CNT=1,C_PROBE633_MU_CNT=1,C_PROBE634_MU_CNT=1,C_PROBE635_MU_CNT=1,C_PROBE636_MU_CNT=1,C_PROBE637_MU_CNT=1,C_PROBE638_MU_CNT=1,C_PROBE639_MU_CNT=1,C_PROBE640_MU_CNT=1,C_PROBE641_MU_CNT=1,C_PROBE642_MU_CNT=1,C_PROBE643_MU_CNT=1,C_PROBE644_MU_CNT=1,C_PROBE645_MU_CNT=1,C_PROBE646_MU_CNT=1,C_PROBE647_MU_CNT=1,C_PROBE648_MU_CNT=1,C_PROBE649_MU_CNT=1,C_PROBE650_MU_CNT=1,C_PROBE651_MU_CNT=1,C_PROBE652_MU_CNT=1,C_PROBE653_MU_CNT=1,C_PROBE654_MU_CNT=1,C_PROBE655_MU_CNT=1,C_PROBE656_MU_CNT=1,C_PROBE657_MU_CNT=1,C_PROBE658_MU_CNT=1,C_PROBE659_MU_CNT=1,C_PROBE660_MU_CNT=1,C_PROBE661_MU_CNT=1,C_PROBE662_MU_CNT=1,C_PROBE663_MU_CNT=1,C_PROBE664_MU_CNT=1,C_PROBE665_MU_CNT=1,C_PROBE666_MU_CNT=1,C_PROBE667_MU_CNT=1,C_PROBE668_MU_CNT=1,C_PROBE669_MU_CNT=1,C_PROBE670_MU_CNT=1,C_PROBE671_MU_CNT=1,C_PROBE672_MU_CNT=1,C_PROBE673_MU_CNT=1,C_PROBE674_MU_CNT=1,C_PROBE675_MU_CNT=1,C_PROBE676_MU_CNT=1,C_PROBE677_MU_CNT=1,C_PROBE678_MU_CNT=1,C_PROBE679_MU_CNT=1,C_PROBE680_MU_CNT=1,C_PROBE681_MU_CNT=1,C_PROBE682_MU_CNT=1,C_PROBE683_MU_CNT=1,C_PROBE684_MU_CNT=1,C_PROBE685_MU_CNT=1,C_PROBE686_MU_CNT=1,C_PROBE687_MU_CNT=1,C_PROBE688_MU_CNT=1,C_PROBE689_MU_CNT=1,C_PROBE690_MU_CNT=1,C_PROBE691_MU_CNT=1,C_PROBE692_MU_CNT=1,C_PROBE693_MU_CNT=1,C_PROBE694_MU_CNT=1,C_PROBE695_MU_CNT=1,C_PROBE696_MU_CNT=1,C_PROBE697_MU_CNT=1,C_PROBE698_MU_CNT=1,C_PROBE699_MU_CNT=1,C_PROBE700_MU_CNT=1,C_PROBE701_MU_CNT=1,C_PROBE702_MU_CNT=1,C_PROBE703_MU_CNT=1,C_PROBE704_MU_CNT=1,C_PROBE705_MU_CNT=1,C_PROBE706_MU_CNT=1,C_PROBE707_MU_CNT=1,C_PROBE708_MU_CNT=1,C_PROBE709_MU_CNT=1,C_PROBE710_MU_CNT=1,C_PROBE711_MU_CNT=1,C_PROBE712_MU_CNT=1,C_PROBE713_MU_CNT=1,C_PROBE714_MU_CNT=1,C_PROBE715_MU_CNT=1,C_PROBE716_MU_CNT=1,C_PROBE717_MU_CNT=1,C_PROBE718_MU_CNT=1,C_PROBE719_MU_CNT=1,C_PROBE720_MU_CNT=1,C_PROBE721_MU_CNT=1,C_PROBE722_MU_CNT=1,C_PROBE723_MU_CNT=1,C_PROBE724_MU_CNT=1,C_PROBE725_MU_CNT=1,C_PROBE726_MU_CNT=1,C_PROBE727_MU_CNT=1,C_PROBE728_MU_CNT=1,C_PROBE729_MU_CNT=1,C_PROBE730_MU_CNT=1,C_PROBE731_MU_CNT=1,C_PROBE732_MU_CNT=1,C_PROBE733_MU_CNT=1,C_PROBE734_MU_CNT=1,C_PROBE735_MU_CNT=1,C_PROBE736_MU_CNT=1,C_PROBE737_MU_CNT=1,C_PROBE738_MU_CNT=1,C_PROBE739_MU_CNT=1,C_PROBE740_MU_CNT=1,C_PROBE741_MU_CNT=1,C_PROBE742_MU_CNT=1,C_PROBE743_MU_CNT=1,C_PROBE744_MU_CNT=1,C_PROBE745_MU_CNT=1,C_PROBE746_MU_CNT=1,C_PROBE747_MU_CNT=1,C_PROBE748_MU_CNT=1,C_PROBE749_MU_CNT=1,C_PROBE750_MU_CNT=1,C_PROBE751_MU_CNT=1,C_PROBE752_MU_CNT=1,C_PROBE753_MU_CNT=1,C_PROBE754_MU_CNT=1,C_PROBE755_MU_CNT=1,C_PROBE756_MU_CNT=1,C_PROBE757_MU_CNT=1,C_PROBE758_MU_CNT=1,C_PROBE759_MU_CNT=1,C_PROBE760_MU_CNT=1,C_PROBE761_MU_CNT=1,C_PROBE762_MU_CNT=1,C_PROBE763_MU_CNT=1,C_PROBE764_MU_CNT=1,C_PROBE765_MU_CNT=1,C_PROBE766_MU_CNT=1,C_PROBE767_MU_CNT=1,C_PROBE768_MU_CNT=1,C_PROBE769_MU_CNT=1,C_PROBE770_MU_CNT=1,C_PROBE771_MU_CNT=1,C_PROBE772_MU_CNT=1,C_PROBE773_MU_CNT=1,C_PROBE774_MU_CNT=1,C_PROBE775_MU_CNT=1,C_PROBE776_MU_CNT=1,C_PROBE777_MU_CNT=1,C_PROBE778_MU_CNT=1,C_PROBE779_MU_CNT=1,C_PROBE780_MU_CNT=1,C_PROBE781_MU_CNT=1,C_PROBE782_MU_CNT=1,C_PROBE783_MU_CNT=1,C_PROBE784_MU_CNT=1,C_PROBE785_MU_CNT=1,C_PROBE786_MU_CNT=1,C_PROBE787_MU_CNT=1,C_PROBE788_MU_CNT=1,C_PROBE789_MU_CNT=1,C_PROBE790_MU_CNT=1,C_PROBE791_MU_CNT=1,C_PROBE792_MU_CNT=1,C_PROBE793_MU_CNT=1,C_PROBE794_MU_CNT=1,C_PROBE795_MU_CNT=1,C_PROBE796_MU_CNT=1,C_PROBE797_MU_CNT=1,C_PROBE798_MU_CNT=1,C_PROBE799_MU_CNT=1,C_PROBE800_MU_CNT=1,C_PROBE801_MU_CNT=1,C_PROBE802_MU_CNT=1,C_PROBE803_MU_CNT=1,C_PROBE804_MU_CNT=1,C_PROBE805_MU_CNT=1,C_PROBE806_MU_CNT=1,C_PROBE807_MU_CNT=1,C_PROBE808_MU_CNT=1,C_PROBE809_MU_CNT=1,C_PROBE810_MU_CNT=1,C_PROBE811_MU_CNT=1,C_PROBE812_MU_CNT=1,C_PROBE813_MU_CNT=1,C_PROBE814_MU_CNT=1,C_PROBE815_MU_CNT=1,C_PROBE816_MU_CNT=1,C_PROBE817_MU_CNT=1,C_PROBE818_MU_CNT=1,C_PROBE819_MU_CNT=1,C_PROBE820_MU_CNT=1,C_PROBE821_MU_CNT=1,C_PROBE822_MU_CNT=1,C_PROBE823_MU_CNT=1,C_PROBE824_MU_CNT=1,C_PROBE825_MU_CNT=1,C_PROBE826_MU_CNT=1,C_PROBE827_MU_CNT=1,C_PROBE828_MU_CNT=1,C_PROBE829_MU_CNT=1,C_PROBE830_MU_CNT=1,C_PROBE831_MU_CNT=1,C_PROBE832_MU_CNT=1,C_PROBE833_MU_CNT=1,C_PROBE834_MU_CNT=1,C_PROBE835_MU_CNT=1,C_PROBE836_MU_CNT=1,C_PROBE837_MU_CNT=1,C_PROBE838_MU_CNT=1,C_PROBE839_MU_CNT=1,C_PROBE840_MU_CNT=1,C_PROBE841_MU_CNT=1,C_PROBE842_MU_CNT=1,C_PROBE843_MU_CNT=1,C_PROBE844_MU_CNT=1,C_PROBE845_MU_CNT=1,C_PROBE846_MU_CNT=1,C_PROBE847_MU_CNT=1,C_PROBE848_MU_CNT=1,C_PROBE849_MU_CNT=1,C_PROBE850_MU_CNT=1,C_PROBE851_MU_CNT=1,C_PROBE852_MU_CNT=1,C_PROBE853_MU_CNT=1,C_PROBE854_MU_CNT=1,C_PROBE855_MU_CNT=1,C_PROBE856_MU_CNT=1,C_PROBE857_MU_CNT=1,C_PROBE858_MU_CNT=1,C_PROBE859_MU_CNT=1,C_PROBE860_MU_CNT=1,C_PROBE861_MU_CNT=1,C_PROBE862_MU_CNT=1,C_PROBE863_MU_CNT=1,C_PROBE864_MU_CNT=1,C_PROBE865_MU_CNT=1,C_PROBE866_MU_CNT=1,C_PROBE867_MU_CNT=1,C_PROBE868_MU_CNT=1,C_PROBE869_MU_CNT=1,C_PROBE870_MU_CNT=1,C_PROBE871_MU_CNT=1,C_PROBE872_MU_CNT=1,C_PROBE873_MU_CNT=1,C_PROBE874_MU_CNT=1,C_PROBE875_MU_CNT=1,C_PROBE876_MU_CNT=1,C_PROBE877_MU_CNT=1,C_PROBE878_MU_CNT=1,C_PROBE879_MU_CNT=1,C_PROBE880_MU_CNT=1,C_PROBE881_MU_CNT=1,C_PROBE882_MU_CNT=1,C_PROBE883_MU_CNT=1,C_PROBE884_MU_CNT=1,C_PROBE885_MU_CNT=1,C_PROBE886_MU_CNT=1,C_PROBE887_MU_CNT=1,C_PROBE888_MU_CNT=1,C_PROBE889_MU_CNT=1,C_PROBE890_MU_CNT=1,C_PROBE891_MU_CNT=1,C_PROBE892_MU_CNT=1,C_PROBE893_MU_CNT=1,C_PROBE894_MU_CNT=1,C_PROBE895_MU_CNT=1,C_PROBE896_MU_CNT=1,C_PROBE897_MU_CNT=1,C_PROBE898_MU_CNT=1,C_PROBE899_MU_CNT=1,C_PROBE900_MU_CNT=1,C_PROBE901_MU_CNT=1,C_PROBE902_MU_CNT=1,C_PROBE903_MU_CNT=1,C_PROBE904_MU_CNT=1,C_PROBE905_MU_CNT=1,C_PROBE906_MU_CNT=1,C_PROBE907_MU_CNT=1,C_PROBE908_MU_CNT=1,C_PROBE909_MU_CNT=1,C_PROBE910_MU_CNT=1,C_PROBE911_MU_CNT=1,C_PROBE912_MU_CNT=1,C_PROBE913_MU_CNT=1,C_PROBE914_MU_CNT=1,C_PROBE915_MU_CNT=1,C_PROBE916_MU_CNT=1,C_PROBE917_MU_CNT=1,C_PROBE918_MU_CNT=1,C_PROBE919_MU_CNT=1,C_PROBE920_MU_CNT=1,C_PROBE921_MU_CNT=1,C_PROBE922_MU_CNT=1,C_PROBE923_MU_CNT=1,C_PROBE924_MU_CNT=1,C_PROBE925_MU_CNT=1,C_PROBE926_MU_CNT=1,C_PROBE927_MU_CNT=1,C_PROBE928_MU_CNT=1,C_PROBE929_MU_CNT=1,C_PROBE930_MU_CNT=1,C_PROBE931_MU_CNT=1,C_PROBE932_MU_CNT=1,C_PROBE933_MU_CNT=1,C_PROBE934_MU_CNT=1,C_PROBE935_MU_CNT=1,C_PROBE936_MU_CNT=1,C_PROBE937_MU_CNT=1,C_PROBE938_MU_CNT=1,C_PROBE939_MU_CNT=1,C_PROBE940_MU_CNT=1,C_PROBE941_MU_CNT=1,C_PROBE942_MU_CNT=1,C_PROBE943_MU_CNT=1,C_PROBE944_MU_CNT=1,C_PROBE945_MU_CNT=1,C_PROBE946_MU_CNT=1,C_PROBE947_MU_CNT=1,C_PROBE948_MU_CNT=1,C_PROBE949_MU_CNT=1,C_PROBE950_MU_CNT=1,C_PROBE951_MU_CNT=1,C_PROBE952_MU_CNT=1,C_PROBE953_MU_CNT=1,C_PROBE954_MU_CNT=1,C_PROBE955_MU_CNT=1,C_PROBE956_MU_CNT=1,C_PROBE957_MU_CNT=1,C_PROBE958_MU_CNT=1,C_PROBE959_MU_CNT=1,C_PROBE960_MU_CNT=1,C_PROBE961_MU_CNT=1,C_PROBE962_MU_CNT=1,C_PROBE963_MU_CNT=1,C_PROBE964_MU_CNT=1,C_PROBE965_MU_CNT=1,C_PROBE966_MU_CNT=1,C_PROBE967_MU_CNT=1,C_PROBE968_MU_CNT=1,C_PROBE969_MU_CNT=1,C_PROBE970_MU_CNT=1,C_PROBE971_MU_CNT=1,C_PROBE972_MU_CNT=1,C_PROBE973_MU_CNT=1,C_PROBE974_MU_CNT=1,C_PROBE975_MU_CNT=1,C_PROBE976_MU_CNT=1,C_PROBE977_MU_CNT=1,C_PROBE978_MU_CNT=1,C_PROBE979_MU_CNT=1,C_PROBE980_MU_CNT=1,C_PROBE981_MU_CNT=1,C_PROBE982_MU_CNT=1,C_PROBE983_MU_CNT=1,C_PROBE984_MU_CNT=1,C_PROBE985_MU_CNT=1,C_PROBE986_MU_CNT=1,C_PROBE987_MU_CNT=1,C_PROBE988_MU_CNT=1,C_PROBE989_MU_CNT=1,C_PROBE990_MU_CNT=1,C_PROBE991_MU_CNT=1,C_PROBE992_MU_CNT=1,C_PROBE993_MU_CNT=1,C_PROBE994_MU_CNT=1,C_PROBE995_MU_CNT=1,C_PROBE996_MU_CNT=1,C_PROBE997_MU_CNT=1,C_PROBE998_MU_CNT=1,C_PROBE999_MU_CNT=1,C_PROBE1000_MU_CNT=1,C_PROBE1001_MU_CNT=1,C_PROBE1002_MU_CNT=1,C_PROBE1003_MU_CNT=1,C_PROBE1004_MU_CNT=1,C_PROBE1005_MU_CNT=1,C_PROBE1006_MU_CNT=1,C_PROBE1007_MU_CNT=1,C_PROBE1008_MU_CNT=1,C_PROBE1009_MU_CNT=1,C_PROBE1010_MU_CNT=1,C_PROBE1011_MU_CNT=1,C_PROBE1012_MU_CNT=1,C_PROBE1013_MU_CNT=1,C_PROBE1014_MU_CNT=1,C_PROBE1015_MU_CNT=1,C_PROBE1016_MU_CNT=1,C_PROBE1017_MU_CNT=1,C_PROBE1018_MU_CNT=1,C_PROBE1019_MU_CNT=1,C_PROBE1020_MU_CNT=1,C_PROBE1021_MU_CNT=1,C_PROBE1022_MU_CNT=1,C_PROBE1023_MU_CNT=1}" *)
module ila_0 (
clk,
trig_out,
trig_out_ack,
trig_in,
trig_in_ack,
probe0
);
input clk;
output trig_out;
input trig_out_ack;
input trig_in;
output trig_in_ack;
input [0 : 0] probe0;
wire [16:0] sl_oport0;
wire [36:0] sl_iport0;
ila_v5_1_ila #(
.C_XLNX_HW_PROBE_INFO("NUM_OF_PROBES=1,DATA_DEPTH=1024,PROBE0_WIDTH=1,PROBE0_MU_CNT=4,PROBE1_WIDTH=1,PROBE1_MU_CNT=4,PROBE2_WIDTH=1,PROBE2_MU_CNT=4,PROBE3_WIDTH=1,PROBE3_MU_CNT=4,PROBE4_WIDTH=1,PROBE4_MU_CNT=4,PROBE5_WIDTH=1,PROBE5_MU_CNT=4,PROBE6_WIDTH=1,PROBE6_MU_CNT=4,PROBE7_WIDTH=1,PROBE7_MU_CNT=4,PROBE8_WIDTH=1,PROBE8_MU_CNT=4,PROBE9_WIDTH=1,PROBE9_MU_CNT=4,PROBE10_WIDTH=1,PROBE10_MU_CNT=4,PROBE11_WIDTH=1,PROBE11_MU_CNT=4,PROBE12_WIDTH=1,PROBE12_MU_CNT=4,PROBE13_WIDTH=1,PROBE13_MU_CNT=4,PROBE14_WIDTH=1,PROBE14_MU_CNT=4,PROBE15_WIDTH=1,PROBE15_MU_CNT=4,PROBE16_WIDTH=1,PROBE16_MU_CNT=4,PROBE17_WIDTH=1,PROBE17_MU_CNT=4,PROBE18_WIDTH=1,PROBE18_MU_CNT=4,PROBE19_WIDTH=1,PROBE19_MU_CNT=4,PROBE20_WIDTH=1,PROBE20_MU_CNT=4,PROBE21_WIDTH=1,PROBE21_MU_CNT=4,PROBE22_WIDTH=1,PROBE22_MU_CNT=4,PROBE23_WIDTH=1,PROBE23_MU_CNT=4,PROBE24_WIDTH=1,PROBE24_MU_CNT=4,PROBE25_WIDTH=1,PROBE25_MU_CNT=4,PROBE26_WIDTH=1,PROBE26_MU_CNT=4,PROBE27_WIDTH=1,PROBE27_MU_CNT=4,PROBE28_WIDTH=1,PROBE28_MU_CNT=4,PROBE29_WIDTH=1,PROBE29_MU_CNT=4,PROBE30_WIDTH=1,PROBE30_MU_CNT=4,PROBE31_WIDTH=1,PROBE31_MU_CNT=4,PROBE32_WIDTH=1,PROBE32_MU_CNT=4,PROBE33_WIDTH=1,PROBE33_MU_CNT=4,PROBE34_WIDTH=1,PROBE34_MU_CNT=4,PROBE35_WIDTH=1,PROBE35_MU_CNT=4,PROBE36_WIDTH=1,PROBE36_MU_CNT=4,PROBE37_WIDTH=1,PROBE37_MU_CNT=4,PROBE38_WIDTH=1,PROBE38_MU_CNT=4,PROBE39_WIDTH=1,PROBE39_MU_CNT=4,PROBE40_WIDTH=1,PROBE40_MU_CNT=4,PROBE41_WIDTH=1,PROBE41_MU_CNT=4,PROBE42_WIDTH=1,PROBE42_MU_CNT=4,PROBE43_WIDTH=1,PROBE43_MU_CNT=4,PROBE44_WIDTH=1,PROBE44_MU_CNT=4,PROBE45_WIDTH=1,PROBE45_MU_CNT=1,PROBE46_WIDTH=1,PROBE46_MU_CNT=1,PROBE47_WIDTH=1,PROBE47_MU_CNT=1,PROBE48_WIDTH=1,PROBE48_MU_CNT=1,PROBE49_WIDTH=1,PROBE49_MU_CNT=1,PROBE50_WIDTH=1,PROBE50_MU_CNT=1,PROBE51_WIDTH=1,PROBE51_MU_CNT=1,PROBE52_WIDTH=1,PROBE52_MU_CNT=1,PROBE53_WIDTH=1,PROBE53_MU_CNT=1,PROBE54_WIDTH=1,PROBE54_MU_CNT=1,PROBE55_WIDTH=1,PROBE55_MU_CNT=1,PROBE56_WIDTH=1,PROBE56_MU_CNT=1,PROBE57_WIDTH=1,PROBE57_MU_CNT=1,PROBE58_WIDTH=1,PROBE58_MU_CNT=1,PROBE59_WIDTH=1,PROBE59_MU_CNT=1,PROBE60_WIDTH=1,PROBE60_MU_CNT=1,PROBE61_WIDTH=1,PROBE61_MU_CNT=1,PROBE62_WIDTH=1,PROBE62_MU_CNT=1,PROBE63_WIDTH=1,PROBE63_MU_CNT=1,PROBE64_WIDTH=1,PROBE64_MU_CNT=1,PROBE65_WIDTH=1,PROBE65_MU_CNT=1,PROBE66_WIDTH=1,PROBE66_MU_CNT=1,PROBE67_WIDTH=1,PROBE67_MU_CNT=1,PROBE68_WIDTH=1,PROBE68_MU_CNT=1,PROBE69_WIDTH=1,PROBE69_MU_CNT=1,PROBE70_WIDTH=1,PROBE70_MU_CNT=1,PROBE71_WIDTH=1,PROBE71_MU_CNT=1,PROBE72_WIDTH=1,PROBE72_MU_CNT=1,PROBE73_WIDTH=1,PROBE73_MU_CNT=1,PROBE74_WIDTH=1,PROBE74_MU_CNT=1,PROBE75_WIDTH=1,PROBE75_MU_CNT=1,PROBE76_WIDTH=1,PROBE76_MU_CNT=1,PROBE77_WIDTH=1,PROBE77_MU_CNT=1,PROBE78_WIDTH=1,PROBE78_MU_CNT=1,PROBE79_WIDTH=1,PROBE79_MU_CNT=1,PROBE80_WIDTH=1,PROBE80_MU_CNT=1,PROBE81_WIDTH=1,PROBE81_MU_CNT=1,PROBE82_WIDTH=1,PROBE82_MU_CNT=1,PROBE83_WIDTH=1,PROBE83_MU_CNT=1,PROBE84_WIDTH=1,PROBE84_MU_CNT=1,PROBE85_WIDTH=1,PROBE85_MU_CNT=1,PROBE86_WIDTH=1,PROBE86_MU_CNT=1,PROBE87_WIDTH=1,PROBE87_MU_CNT=1,PROBE88_WIDTH=1,PROBE88_MU_CNT=1,PROBE89_WIDTH=1,PROBE89_MU_CNT=1,PROBE90_WIDTH=1,PROBE90_MU_CNT=1,PROBE91_WIDTH=1,PROBE91_MU_CNT=1,PROBE92_WIDTH=1,PROBE92_MU_CNT=1,PROBE93_WIDTH=1,PROBE93_MU_CNT=1,PROBE94_WIDTH=1,PROBE94_MU_CNT=1,PROBE95_WIDTH=1,PROBE95_MU_CNT=1,PROBE96_WIDTH=1,PROBE96_MU_CNT=1,PROBE97_WIDTH=1,PROBE97_MU_CNT=1,PROBE98_WIDTH=1,PROBE98_MU_CNT=1,PROBE99_WIDTH=1,PROBE99_MU_CNT=1,PROBE100_WIDTH=1,PROBE100_MU_CNT=1,PROBE101_WIDTH=1,PROBE101_MU_CNT=1,PROBE102_WIDTH=1,PROBE102_MU_CNT=1,PROBE103_WIDTH=1,PROBE103_MU_CNT=1,PROBE104_WIDTH=1,PROBE104_MU_CNT=1,PROBE105_WIDTH=1,PROBE105_MU_CNT=1,PROBE106_WIDTH=1,PROBE106_MU_CNT=1,PROBE107_WIDTH=1,PROBE107_MU_CNT=1,PROBE108_WIDTH=1,PROBE108_MU_CNT=1,PROBE109_WIDTH=1,PROBE109_MU_CNT=1,PROBE110_WIDTH=1,PROBE110_MU_CNT=1,PROBE111_WIDTH=1,PROBE111_MU_CNT=1,PROBE112_WIDTH=1,PROBE112_MU_CNT=1,PROBE113_WIDTH=1,PROBE113_MU_CNT=1,PROBE114_WIDTH=1,PROBE114_MU_CNT=1,PROBE115_WIDTH=1,PROBE115_MU_CNT=1,PROBE116_WIDTH=1,PROBE116_MU_CNT=1,PROBE117_WIDTH=1,PROBE117_MU_CNT=1,PROBE118_WIDTH=1,PROBE118_MU_CNT=1,PROBE119_WIDTH=1,PROBE119_MU_CNT=1,PROBE120_WIDTH=1,PROBE120_MU_CNT=1,PROBE121_WIDTH=1,PROBE121_MU_CNT=1,PROBE122_WIDTH=1,PROBE122_MU_CNT=1,PROBE123_WIDTH=1,PROBE123_MU_CNT=1,PROBE124_WIDTH=1,PROBE124_MU_CNT=1,PROBE125_WIDTH=1,PROBE125_MU_CNT=1,PROBE126_WIDTH=1,PROBE126_MU_CNT=1,PROBE127_WIDTH=1,PROBE127_MU_CNT=1,PROBE128_WIDTH=1,PROBE128_MU_CNT=1,PROBE129_WIDTH=1,PROBE129_MU_CNT=1,PROBE130_WIDTH=1,PROBE130_MU_CNT=1,PROBE131_WIDTH=1,PROBE131_MU_CNT=1,PROBE132_WIDTH=1,PROBE132_MU_CNT=1,PROBE133_WIDTH=1,PROBE133_MU_CNT=1,PROBE134_WIDTH=1,PROBE134_MU_CNT=1,PROBE135_WIDTH=1,PROBE135_MU_CNT=1,PROBE136_WIDTH=1,PROBE136_MU_CNT=1,PROBE137_WIDTH=1,PROBE137_MU_CNT=1,PROBE138_WIDTH=1,PROBE138_MU_CNT=1,PROBE139_WIDTH=1,PROBE139_MU_CNT=1,PROBE140_WIDTH=1,PROBE140_MU_CNT=1,PROBE141_WIDTH=1,PROBE141_MU_CNT=1,PROBE142_WIDTH=1,PROBE142_MU_CNT=1,PROBE143_WIDTH=1,PROBE143_MU_CNT=1,PROBE144_WIDTH=1,PROBE144_MU_CNT=1,PROBE145_WIDTH=1,PROBE145_MU_CNT=1,PROBE146_WIDTH=1,PROBE146_MU_CNT=1,PROBE147_WIDTH=1,PROBE147_MU_CNT=1,PROBE148_WIDTH=1,PROBE148_MU_CNT=1,PROBE149_WIDTH=1,PROBE149_MU_CNT=1,PROBE150_WIDTH=1,PROBE150_MU_CNT=1,PROBE151_WIDTH=1,PROBE151_MU_CNT=1,PROBE152_WIDTH=1,PROBE152_MU_CNT=1,PROBE153_WIDTH=1,PROBE153_MU_CNT=1,PROBE154_WIDTH=1,PROBE154_MU_CNT=1,PROBE155_WIDTH=1,PROBE155_MU_CNT=1,PROBE156_WIDTH=1,PROBE156_MU_CNT=1,PROBE157_WIDTH=1,PROBE157_MU_CNT=1,PROBE158_WIDTH=1,PROBE158_MU_CNT=1,PROBE159_WIDTH=1,PROBE159_MU_CNT=1,PROBE160_WIDTH=1,PROBE160_MU_CNT=1,PROBE161_WIDTH=1,PROBE161_MU_CNT=1,PROBE162_WIDTH=1,PROBE162_MU_CNT=1,PROBE163_WIDTH=1,PROBE163_MU_CNT=1,PROBE164_WIDTH=1,PROBE164_MU_CNT=1,PROBE165_WIDTH=1,PROBE165_MU_CNT=1,PROBE166_WIDTH=1,PROBE166_MU_CNT=1,PROBE167_WIDTH=1,PROBE167_MU_CNT=1,PROBE168_WIDTH=1,PROBE168_MU_CNT=1,PROBE169_WIDTH=1,PROBE169_MU_CNT=1,PROBE170_WIDTH=1,PROBE170_MU_CNT=1,PROBE171_WIDTH=1,PROBE171_MU_CNT=1,PROBE172_WIDTH=1,PROBE172_MU_CNT=1,PROBE173_WIDTH=1,PROBE173_MU_CNT=1,PROBE174_WIDTH=1,PROBE174_MU_CNT=1,PROBE175_WIDTH=1,PROBE175_MU_CNT=1,PROBE176_WIDTH=1,PROBE176_MU_CNT=1,PROBE177_WIDTH=1,PROBE177_MU_CNT=1,PROBE178_WIDTH=1,PROBE178_MU_CNT=1,PROBE179_WIDTH=1,PROBE179_MU_CNT=1,PROBE180_WIDTH=1,PROBE180_MU_CNT=1,PROBE181_WIDTH=1,PROBE181_MU_CNT=1,PROBE182_WIDTH=1,PROBE182_MU_CNT=1,PROBE183_WIDTH=1,PROBE183_MU_CNT=1,PROBE184_WIDTH=1,PROBE184_MU_CNT=1,PROBE185_WIDTH=1,PROBE185_MU_CNT=1,PROBE186_WIDTH=1,PROBE186_MU_CNT=1,PROBE187_WIDTH=1,PROBE187_MU_CNT=1,PROBE188_WIDTH=1,PROBE188_MU_CNT=1,PROBE189_WIDTH=1,PROBE189_MU_CNT=1,PROBE190_WIDTH=1,PROBE190_MU_CNT=1,PROBE191_WIDTH=1,PROBE191_MU_CNT=1,PROBE192_WIDTH=1,PROBE192_MU_CNT=1,PROBE193_WIDTH=1,PROBE193_MU_CNT=1,PROBE194_WIDTH=1,PROBE194_MU_CNT=1,PROBE195_WIDTH=1,PROBE195_MU_CNT=1,PROBE196_WIDTH=1,PROBE196_MU_CNT=1,PROBE197_WIDTH=1,PROBE197_MU_CNT=1,PROBE198_WIDTH=1,PROBE198_MU_CNT=1,PROBE199_WIDTH=1,PROBE199_MU_CNT=1,PROBE200_WIDTH=1,PROBE200_MU_CNT=1,PROBE201_WIDTH=1,PROBE201_MU_CNT=1,PROBE202_WIDTH=1,PROBE202_MU_CNT=1,PROBE203_WIDTH=1,PROBE203_MU_CNT=1,PROBE204_WIDTH=1,PROBE204_MU_CNT=1,PROBE205_WIDTH=1,PROBE205_MU_CNT=1,PROBE206_WIDTH=1,PROBE206_MU_CNT=1,PROBE207_WIDTH=1,PROBE207_MU_CNT=1,PROBE208_WIDTH=1,PROBE208_MU_CNT=1,PROBE209_WIDTH=1,PROBE209_MU_CNT=1,PROBE210_WIDTH=1,PROBE210_MU_CNT=1,PROBE211_WIDTH=1,PROBE211_MU_CNT=1,PROBE212_WIDTH=1,PROBE212_MU_CNT=1,PROBE213_WIDTH=1,PROBE213_MU_CNT=1,PROBE214_WIDTH=1,PROBE214_MU_CNT=1,PROBE215_WIDTH=1,PROBE215_MU_CNT=1,PROBE216_WIDTH=1,PROBE216_MU_CNT=1,PROBE217_WIDTH=1,PROBE217_MU_CNT=1,PROBE218_WIDTH=1,PROBE218_MU_CNT=1,PROBE219_WIDTH=1,PROBE219_MU_CNT=1,PROBE220_WIDTH=1,PROBE220_MU_CNT=1,PROBE221_WIDTH=1,PROBE221_MU_CNT=1,PROBE222_WIDTH=1,PROBE222_MU_CNT=1,PROBE223_WIDTH=1,PROBE223_MU_CNT=1,PROBE224_WIDTH=1,PROBE224_MU_CNT=1,PROBE225_WIDTH=1,PROBE225_MU_CNT=1,PROBE226_WIDTH=1,PROBE226_MU_CNT=1,PROBE227_WIDTH=1,PROBE227_MU_CNT=1,PROBE228_WIDTH=1,PROBE228_MU_CNT=1,PROBE229_WIDTH=1,PROBE229_MU_CNT=1,PROBE230_WIDTH=1,PROBE230_MU_CNT=1,PROBE231_WIDTH=1,PROBE231_MU_CNT=1,PROBE232_WIDTH=1,PROBE232_MU_CNT=1,PROBE233_WIDTH=1,PROBE233_MU_CNT=1,PROBE234_WIDTH=1,PROBE234_MU_CNT=1,PROBE235_WIDTH=1,PROBE235_MU_CNT=1,PROBE236_WIDTH=1,PROBE236_MU_CNT=1,PROBE237_WIDTH=1,PROBE237_MU_CNT=1,PROBE238_WIDTH=1,PROBE238_MU_CNT=1,PROBE239_WIDTH=1,PROBE239_MU_CNT=1,PROBE240_WIDTH=1,PROBE240_MU_CNT=1,PROBE241_WIDTH=1,PROBE241_MU_CNT=1,PROBE242_WIDTH=1,PROBE242_MU_CNT=1,PROBE243_WIDTH=1,PROBE243_MU_CNT=1,PROBE244_WIDTH=1,PROBE244_MU_CNT=1,PROBE245_WIDTH=1,PROBE245_MU_CNT=1,PROBE246_WIDTH=1,PROBE246_MU_CNT=1,PROBE247_WIDTH=1,PROBE247_MU_CNT=1,PROBE248_WIDTH=1,PROBE248_MU_CNT=1,PROBE249_WIDTH=1,PROBE249_MU_CNT=1,PROBE250_WIDTH=1,PROBE250_MU_CNT=1,PROBE251_WIDTH=1,PROBE251_MU_CNT=1,PROBE252_WIDTH=1,PROBE252_MU_CNT=1,PROBE253_WIDTH=1,PROBE253_MU_CNT=1,PROBE254_WIDTH=1,PROBE254_MU_CNT=1,PROBE255_WIDTH=1,PROBE255_MU_CNT=1,PROBE256_WIDTH=1,PROBE256_MU_CNT=1,PROBE257_WIDTH=1,PROBE257_MU_CNT=1,PROBE258_WIDTH=1,PROBE258_MU_CNT=1,PROBE259_WIDTH=1,PROBE259_MU_CNT=1,PROBE260_WIDTH=1,PROBE260_MU_CNT=1,PROBE261_WIDTH=1,PROBE261_MU_CNT=1,PROBE262_WIDTH=1,PROBE262_MU_CNT=1,PROBE263_WIDTH=1,PROBE263_MU_CNT=1,PROBE264_WIDTH=1,PROBE264_MU_CNT=1,PROBE265_WIDTH=1,PROBE265_MU_CNT=1,PROBE266_WIDTH=1,PROBE266_MU_CNT=1,PROBE267_WIDTH=1,PROBE267_MU_CNT=1,PROBE268_WIDTH=1,PROBE268_MU_CNT=1,PROBE269_WIDTH=1,PROBE269_MU_CNT=1,PROBE270_WIDTH=1,PROBE270_MU_CNT=1,PROBE271_WIDTH=1,PROBE271_MU_CNT=1,PROBE272_WIDTH=1,PROBE272_MU_CNT=1,PROBE273_WIDTH=1,PROBE273_MU_CNT=1,PROBE274_WIDTH=1,PROBE274_MU_CNT=1,PROBE275_WIDTH=1,PROBE275_MU_CNT=1,PROBE276_WIDTH=1,PROBE276_MU_CNT=1,PROBE277_WIDTH=1,PROBE277_MU_CNT=1,PROBE278_WIDTH=1,PROBE278_MU_CNT=1,PROBE279_WIDTH=1,PROBE279_MU_CNT=1,PROBE280_WIDTH=1,PROBE280_MU_CNT=1,PROBE281_WIDTH=1,PROBE281_MU_CNT=1,PROBE282_WIDTH=1,PROBE282_MU_CNT=1,PROBE283_WIDTH=1,PROBE283_MU_CNT=1,PROBE284_WIDTH=1,PROBE284_MU_CNT=1,PROBE285_WIDTH=1,PROBE285_MU_CNT=1,PROBE286_WIDTH=1,PROBE286_MU_CNT=1,PROBE287_WIDTH=1,PROBE287_MU_CNT=1,PROBE288_WIDTH=1,PROBE288_MU_CNT=1,PROBE289_WIDTH=1,PROBE289_MU_CNT=1,PROBE290_WIDTH=1,PROBE290_MU_CNT=1,PROBE291_WIDTH=1,PROBE291_MU_CNT=1,PROBE292_WIDTH=1,PROBE292_MU_CNT=1,PROBE293_WIDTH=1,PROBE293_MU_CNT=1,PROBE294_WIDTH=1,PROBE294_MU_CNT=1,PROBE295_WIDTH=1,PROBE295_MU_CNT=1,PROBE296_WIDTH=1,PROBE296_MU_CNT=1,PROBE297_WIDTH=1,PROBE297_MU_CNT=1,PROBE298_WIDTH=1,PROBE298_MU_CNT=1,PROBE299_WIDTH=1,PROBE299_MU_CNT=1,PROBE300_WIDTH=1,PROBE300_MU_CNT=1,PROBE301_WIDTH=1,PROBE301_MU_CNT=1,PROBE302_WIDTH=1,PROBE302_MU_CNT=1,PROBE303_WIDTH=1,PROBE303_MU_CNT=1,PROBE304_WIDTH=1,PROBE304_MU_CNT=1,PROBE305_WIDTH=1,PROBE305_MU_CNT=1,PROBE306_WIDTH=1,PROBE306_MU_CNT=1,PROBE307_WIDTH=1,PROBE307_MU_CNT=1,PROBE308_WIDTH=1,PROBE308_MU_CNT=1,PROBE309_WIDTH=1,PROBE309_MU_CNT=1,PROBE310_WIDTH=1,PROBE310_MU_CNT=1,PROBE311_WIDTH=1,PROBE311_MU_CNT=1,PROBE312_WIDTH=1,PROBE312_MU_CNT=1,PROBE313_WIDTH=1,PROBE313_MU_CNT=1,PROBE314_WIDTH=1,PROBE314_MU_CNT=1,PROBE315_WIDTH=1,PROBE315_MU_CNT=1,PROBE316_WIDTH=1,PROBE316_MU_CNT=1,PROBE317_WIDTH=1,PROBE317_MU_CNT=1,PROBE318_WIDTH=1,PROBE318_MU_CNT=1,PROBE319_WIDTH=1,PROBE319_MU_CNT=1,PROBE320_WIDTH=1,PROBE320_MU_CNT=1,PROBE321_WIDTH=1,PROBE321_MU_CNT=1,PROBE322_WIDTH=1,PROBE322_MU_CNT=1,PROBE323_WIDTH=1,PROBE323_MU_CNT=1,PROBE324_WIDTH=1,PROBE324_MU_CNT=1,PROBE325_WIDTH=1,PROBE325_MU_CNT=1,PROBE326_WIDTH=1,PROBE326_MU_CNT=1,PROBE327_WIDTH=1,PROBE327_MU_CNT=1,PROBE328_WIDTH=1,PROBE328_MU_CNT=1,PROBE329_WIDTH=1,PROBE329_MU_CNT=1,PROBE330_WIDTH=1,PROBE330_MU_CNT=1,PROBE331_WIDTH=1,PROBE331_MU_CNT=1,PROBE332_WIDTH=1,PROBE332_MU_CNT=1,PROBE333_WIDTH=1,PROBE333_MU_CNT=1,PROBE334_WIDTH=1,PROBE334_MU_CNT=1,PROBE335_WIDTH=1,PROBE335_MU_CNT=1,PROBE336_WIDTH=1,PROBE336_MU_CNT=1,PROBE337_WIDTH=1,PROBE337_MU_CNT=1,PROBE338_WIDTH=1,PROBE338_MU_CNT=1,PROBE339_WIDTH=1,PROBE339_MU_CNT=1,PROBE340_WIDTH=1,PROBE340_MU_CNT=1,PROBE341_WIDTH=1,PROBE341_MU_CNT=1,PROBE342_WIDTH=1,PROBE342_MU_CNT=1,PROBE343_WIDTH=1,PROBE343_MU_CNT=1,PROBE344_WIDTH=1,PROBE344_MU_CNT=1,PROBE345_WIDTH=1,PROBE345_MU_CNT=1,PROBE346_WIDTH=1,PROBE346_MU_CNT=1,PROBE347_WIDTH=1,PROBE347_MU_CNT=1,PROBE348_WIDTH=1,PROBE348_MU_CNT=1,PROBE349_WIDTH=1,PROBE349_MU_CNT=1,PROBE350_WIDTH=1,PROBE350_MU_CNT=1,PROBE351_WIDTH=1,PROBE351_MU_CNT=1,PROBE352_WIDTH=1,PROBE352_MU_CNT=1,PROBE353_WIDTH=1,PROBE353_MU_CNT=1,PROBE354_WIDTH=1,PROBE354_MU_CNT=1,PROBE355_WIDTH=1,PROBE355_MU_CNT=1,PROBE356_WIDTH=1,PROBE356_MU_CNT=1,PROBE357_WIDTH=1,PROBE357_MU_CNT=1,PROBE358_WIDTH=1,PROBE358_MU_CNT=1,PROBE359_WIDTH=1,PROBE359_MU_CNT=1,PROBE360_WIDTH=1,PROBE360_MU_CNT=1,PROBE361_WIDTH=1,PROBE361_MU_CNT=1,PROBE362_WIDTH=1,PROBE362_MU_CNT=1,PROBE363_WIDTH=1,PROBE363_MU_CNT=1,PROBE364_WIDTH=1,PROBE364_MU_CNT=1,PROBE365_WIDTH=1,PROBE365_MU_CNT=1,PROBE366_WIDTH=1,PROBE366_MU_CNT=1,PROBE367_WIDTH=1,PROBE367_MU_CNT=1,PROBE368_WIDTH=1,PROBE368_MU_CNT=1,PROBE369_WIDTH=1,PROBE369_MU_CNT=1,PROBE370_WIDTH=1,PROBE370_MU_CNT=1,PROBE371_WIDTH=1,PROBE371_MU_CNT=1,PROBE372_WIDTH=1,PROBE372_MU_CNT=1,PROBE373_WIDTH=1,PROBE373_MU_CNT=1,PROBE374_WIDTH=1,PROBE374_MU_CNT=1,PROBE375_WIDTH=1,PROBE375_MU_CNT=1,PROBE376_WIDTH=1,PROBE376_MU_CNT=1,PROBE377_WIDTH=1,PROBE377_MU_CNT=1,PROBE378_WIDTH=1,PROBE378_MU_CNT=1,PROBE379_WIDTH=1,PROBE379_MU_CNT=1,PROBE380_WIDTH=1,PROBE380_MU_CNT=1,PROBE381_WIDTH=1,PROBE381_MU_CNT=1,PROBE382_WIDTH=1,PROBE382_MU_CNT=1,PROBE383_WIDTH=1,PROBE383_MU_CNT=1,PROBE384_WIDTH=1,PROBE384_MU_CNT=1,PROBE385_WIDTH=1,PROBE385_MU_CNT=1,PROBE386_WIDTH=1,PROBE386_MU_CNT=1,PROBE387_WIDTH=1,PROBE387_MU_CNT=1,PROBE388_WIDTH=1,PROBE388_MU_CNT=1,PROBE389_WIDTH=1,PROBE389_MU_CNT=1,PROBE390_WIDTH=1,PROBE390_MU_CNT=1,PROBE391_WIDTH=1,PROBE391_MU_CNT=1,PROBE392_WIDTH=1,PROBE392_MU_CNT=1,PROBE393_WIDTH=1,PROBE393_MU_CNT=1,PROBE394_WIDTH=1,PROBE394_MU_CNT=1,PROBE395_WIDTH=1,PROBE395_MU_CNT=1,PROBE396_WIDTH=1,PROBE396_MU_CNT=1,PROBE397_WIDTH=1,PROBE397_MU_CNT=1,PROBE398_WIDTH=1,PROBE398_MU_CNT=1,PROBE399_WIDTH=1,PROBE399_MU_CNT=1,PROBE400_WIDTH=1,PROBE400_MU_CNT=1,PROBE401_WIDTH=1,PROBE401_MU_CNT=1,PROBE402_WIDTH=1,PROBE402_MU_CNT=1,PROBE403_WIDTH=1,PROBE403_MU_CNT=1,PROBE404_WIDTH=1,PROBE404_MU_CNT=1,PROBE405_WIDTH=1,PROBE405_MU_CNT=1,PROBE406_WIDTH=1,PROBE406_MU_CNT=1,PROBE407_WIDTH=1,PROBE407_MU_CNT=1,PROBE408_WIDTH=1,PROBE408_MU_CNT=1,PROBE409_WIDTH=1,PROBE409_MU_CNT=1,PROBE410_WIDTH=1,PROBE410_MU_CNT=1,PROBE411_WIDTH=1,PROBE411_MU_CNT=1,PROBE412_WIDTH=1,PROBE412_MU_CNT=1,PROBE413_WIDTH=1,PROBE413_MU_CNT=1,PROBE414_WIDTH=1,PROBE414_MU_CNT=1,PROBE415_WIDTH=1,PROBE415_MU_CNT=1,PROBE416_WIDTH=1,PROBE416_MU_CNT=1,PROBE417_WIDTH=1,PROBE417_MU_CNT=1,PROBE418_WIDTH=1,PROBE418_MU_CNT=1,PROBE419_WIDTH=1,PROBE419_MU_CNT=1,PROBE420_WIDTH=1,PROBE420_MU_CNT=1,PROBE421_WIDTH=1,PROBE421_MU_CNT=1,PROBE422_WIDTH=1,PROBE422_MU_CNT=1,PROBE423_WIDTH=1,PROBE423_MU_CNT=1,PROBE424_WIDTH=1,PROBE424_MU_CNT=1,PROBE425_WIDTH=1,PROBE425_MU_CNT=1,PROBE426_WIDTH=1,PROBE426_MU_CNT=1,PROBE427_WIDTH=1,PROBE427_MU_CNT=1,PROBE428_WIDTH=1,PROBE428_MU_CNT=1,PROBE429_WIDTH=1,PROBE429_MU_CNT=1,PROBE430_WIDTH=1,PROBE430_MU_CNT=1,PROBE431_WIDTH=1,PROBE431_MU_CNT=1,PROBE432_WIDTH=1,PROBE432_MU_CNT=1,PROBE433_WIDTH=1,PROBE433_MU_CNT=1,PROBE434_WIDTH=1,PROBE434_MU_CNT=1,PROBE435_WIDTH=1,PROBE435_MU_CNT=1,PROBE436_WIDTH=1,PROBE436_MU_CNT=1,PROBE437_WIDTH=1,PROBE437_MU_CNT=1,PROBE438_WIDTH=1,PROBE438_MU_CNT=1,PROBE439_WIDTH=1,PROBE439_MU_CNT=1,PROBE440_WIDTH=1,PROBE440_MU_CNT=1,PROBE441_WIDTH=1,PROBE441_MU_CNT=1,PROBE442_WIDTH=1,PROBE442_MU_CNT=1,PROBE443_WIDTH=1,PROBE443_MU_CNT=1,PROBE444_WIDTH=1,PROBE444_MU_CNT=1,PROBE445_WIDTH=1,PROBE445_MU_CNT=1,PROBE446_WIDTH=1,PROBE446_MU_CNT=1,PROBE447_WIDTH=1,PROBE447_MU_CNT=1,PROBE448_WIDTH=1,PROBE448_MU_CNT=1,PROBE449_WIDTH=1,PROBE449_MU_CNT=1,PROBE450_WIDTH=1,PROBE450_MU_CNT=1,PROBE451_WIDTH=1,PROBE451_MU_CNT=1,PROBE452_WIDTH=1,PROBE452_MU_CNT=1,PROBE453_WIDTH=1,PROBE453_MU_CNT=1,PROBE454_WIDTH=1,PROBE454_MU_CNT=1,PROBE455_WIDTH=1,PROBE455_MU_CNT=1,PROBE456_WIDTH=1,PROBE456_MU_CNT=1,PROBE457_WIDTH=1,PROBE457_MU_CNT=1,PROBE458_WIDTH=1,PROBE458_MU_CNT=1,PROBE459_WIDTH=1,PROBE459_MU_CNT=1,PROBE460_WIDTH=1,PROBE460_MU_CNT=1,PROBE461_WIDTH=1,PROBE461_MU_CNT=1,PROBE462_WIDTH=1,PROBE462_MU_CNT=1,PROBE463_WIDTH=1,PROBE463_MU_CNT=1,PROBE464_WIDTH=1,PROBE464_MU_CNT=1,PROBE465_WIDTH=1,PROBE465_MU_CNT=1,PROBE466_WIDTH=1,PROBE466_MU_CNT=1,PROBE467_WIDTH=1,PROBE467_MU_CNT=1,PROBE468_WIDTH=1,PROBE468_MU_CNT=1,PROBE469_WIDTH=1,PROBE469_MU_CNT=1,PROBE470_WIDTH=1,PROBE470_MU_CNT=1,PROBE471_WIDTH=1,PROBE471_MU_CNT=1,PROBE472_WIDTH=1,PROBE472_MU_CNT=1,PROBE473_WIDTH=1,PROBE473_MU_CNT=1,PROBE474_WIDTH=1,PROBE474_MU_CNT=1,PROBE475_WIDTH=1,PROBE475_MU_CNT=1,PROBE476_WIDTH=1,PROBE476_MU_CNT=1,PROBE477_WIDTH=1,PROBE477_MU_CNT=1,PROBE478_WIDTH=1,PROBE478_MU_CNT=1,PROBE479_WIDTH=1,PROBE479_MU_CNT=1,PROBE480_WIDTH=1,PROBE480_MU_CNT=1,PROBE481_WIDTH=1,PROBE481_MU_CNT=1,PROBE482_WIDTH=1,PROBE482_MU_CNT=1,PROBE483_WIDTH=1,PROBE483_MU_CNT=1,PROBE484_WIDTH=1,PROBE484_MU_CNT=1,PROBE485_WIDTH=1,PROBE485_MU_CNT=1,PROBE486_WIDTH=1,PROBE486_MU_CNT=1,PROBE487_WIDTH=1,PROBE487_MU_CNT=1,PROBE488_WIDTH=1,PROBE488_MU_CNT=1,PROBE489_WIDTH=1,PROBE489_MU_CNT=1,PROBE490_WIDTH=1,PROBE490_MU_CNT=1,PROBE491_WIDTH=1,PROBE491_MU_CNT=1,PROBE492_WIDTH=1,PROBE492_MU_CNT=1,PROBE493_WIDTH=1,PROBE493_MU_CNT=1,PROBE494_WIDTH=1,PROBE494_MU_CNT=1,PROBE495_WIDTH=1,PROBE495_MU_CNT=1,PROBE496_WIDTH=1,PROBE496_MU_CNT=1,PROBE497_WIDTH=1,PROBE497_MU_CNT=1,PROBE498_WIDTH=1,PROBE498_MU_CNT=1,PROBE499_WIDTH=1,PROBE499_MU_CNT=1,PROBE500_WIDTH=1,PROBE500_MU_CNT=1,PROBE501_WIDTH=1,PROBE501_MU_CNT=1,PROBE502_WIDTH=1,PROBE502_MU_CNT=1,PROBE503_WIDTH=1,PROBE503_MU_CNT=1,PROBE504_WIDTH=1,PROBE504_MU_CNT=1,PROBE505_WIDTH=1,PROBE505_MU_CNT=1,PROBE506_WIDTH=1,PROBE506_MU_CNT=1,PROBE507_WIDTH=1,PROBE507_MU_CNT=1,PROBE508_WIDTH=1,PROBE508_MU_CNT=1,PROBE509_WIDTH=1,PROBE509_MU_CNT=1,PROBE510_WIDTH=1,PROBE510_MU_CNT=1,PROBE511_WIDTH=1,PROBE511_MU_CNT=1,PROBE512_WIDTH=1,PROBE512_MU_CNT=1,PROBE513_WIDTH=1,PROBE513_MU_CNT=1,PROBE514_WIDTH=1,PROBE514_MU_CNT=1,PROBE515_WIDTH=1,PROBE515_MU_CNT=1,PROBE516_WIDTH=1,PROBE516_MU_CNT=1,PROBE517_WIDTH=1,PROBE517_MU_CNT=1,PROBE518_WIDTH=1,PROBE518_MU_CNT=1,PROBE519_WIDTH=1,PROBE519_MU_CNT=1,PROBE520_WIDTH=1,PROBE520_MU_CNT=1,PROBE521_WIDTH=1,PROBE521_MU_CNT=1,PROBE522_WIDTH=1,PROBE522_MU_CNT=1,PROBE523_WIDTH=1,PROBE523_MU_CNT=1,PROBE524_WIDTH=1,PROBE524_MU_CNT=1,PROBE525_WIDTH=1,PROBE525_MU_CNT=1,PROBE526_WIDTH=1,PROBE526_MU_CNT=1,PROBE527_WIDTH=1,PROBE527_MU_CNT=1,PROBE528_WIDTH=1,PROBE528_MU_CNT=1,PROBE529_WIDTH=1,PROBE529_MU_CNT=1,PROBE530_WIDTH=1,PROBE530_MU_CNT=1,PROBE531_WIDTH=1,PROBE531_MU_CNT=1,PROBE532_WIDTH=1,PROBE532_MU_CNT=1,PROBE533_WIDTH=1,PROBE533_MU_CNT=1,PROBE534_WIDTH=1,PROBE534_MU_CNT=1,PROBE535_WIDTH=1,PROBE535_MU_CNT=1,PROBE536_WIDTH=1,PROBE536_MU_CNT=1,PROBE537_WIDTH=1,PROBE537_MU_CNT=1,PROBE538_WIDTH=1,PROBE538_MU_CNT=1,PROBE539_WIDTH=1,PROBE539_MU_CNT=1,PROBE540_WIDTH=1,PROBE540_MU_CNT=1,PROBE541_WIDTH=1,PROBE541_MU_CNT=1,PROBE542_WIDTH=1,PROBE542_MU_CNT=1,PROBE543_WIDTH=1,PROBE543_MU_CNT=1,PROBE544_WIDTH=1,PROBE544_MU_CNT=1,PROBE545_WIDTH=1,PROBE545_MU_CNT=1,PROBE546_WIDTH=1,PROBE546_MU_CNT=1,PROBE547_WIDTH=1,PROBE547_MU_CNT=1,PROBE548_WIDTH=1,PROBE548_MU_CNT=1,PROBE549_WIDTH=1,PROBE549_MU_CNT=1,PROBE550_WIDTH=1,PROBE550_MU_CNT=1,PROBE551_WIDTH=1,PROBE551_MU_CNT=1,PROBE552_WIDTH=1,PROBE552_MU_CNT=1,PROBE553_WIDTH=1,PROBE553_MU_CNT=1,PROBE554_WIDTH=1,PROBE554_MU_CNT=1,PROBE555_WIDTH=1,PROBE555_MU_CNT=1,PROBE556_WIDTH=1,PROBE556_MU_CNT=1,PROBE557_WIDTH=1,PROBE557_MU_CNT=1,PROBE558_WIDTH=1,PROBE558_MU_CNT=1,PROBE559_WIDTH=1,PROBE559_MU_CNT=1,PROBE560_WIDTH=1,PROBE560_MU_CNT=1,PROBE561_WIDTH=1,PROBE561_MU_CNT=1,PROBE562_WIDTH=1,PROBE562_MU_CNT=1,PROBE563_WIDTH=1,PROBE563_MU_CNT=1,PROBE564_WIDTH=1,PROBE564_MU_CNT=1,PROBE565_WIDTH=1,PROBE565_MU_CNT=1,PROBE566_WIDTH=1,PROBE566_MU_CNT=1,PROBE567_WIDTH=1,PROBE567_MU_CNT=1,PROBE568_WIDTH=1,PROBE568_MU_CNT=1,PROBE569_WIDTH=1,PROBE569_MU_CNT=1,PROBE570_WIDTH=1,PROBE570_MU_CNT=1,PROBE571_WIDTH=1,PROBE571_MU_CNT=1,PROBE572_WIDTH=1,PROBE572_MU_CNT=1,PROBE573_WIDTH=1,PROBE573_MU_CNT=1,PROBE574_WIDTH=1,PROBE574_MU_CNT=1,PROBE575_WIDTH=1,PROBE575_MU_CNT=1,PROBE576_WIDTH=1,PROBE576_MU_CNT=1,PROBE577_WIDTH=1,PROBE577_MU_CNT=1,PROBE578_WIDTH=1,PROBE578_MU_CNT=1,PROBE579_WIDTH=1,PROBE579_MU_CNT=1,PROBE580_WIDTH=1,PROBE580_MU_CNT=1,PROBE581_WIDTH=1,PROBE581_MU_CNT=1,PROBE582_WIDTH=1,PROBE582_MU_CNT=1,PROBE583_WIDTH=1,PROBE583_MU_CNT=1,PROBE584_WIDTH=1,PROBE584_MU_CNT=1,PROBE585_WIDTH=1,PROBE585_MU_CNT=1,PROBE586_WIDTH=1,PROBE586_MU_CNT=1,PROBE587_WIDTH=1,PROBE587_MU_CNT=1,PROBE588_WIDTH=1,PROBE588_MU_CNT=1,PROBE589_WIDTH=1,PROBE589_MU_CNT=1,PROBE590_WIDTH=1,PROBE590_MU_CNT=1,PROBE591_WIDTH=1,PROBE591_MU_CNT=1,PROBE592_WIDTH=1,PROBE592_MU_CNT=1,PROBE593_WIDTH=1,PROBE593_MU_CNT=1,PROBE594_WIDTH=1,PROBE594_MU_CNT=1,PROBE595_WIDTH=1,PROBE595_MU_CNT=1,PROBE596_WIDTH=1,PROBE596_MU_CNT=1,PROBE597_WIDTH=1,PROBE597_MU_CNT=1,PROBE598_WIDTH=1,PROBE598_MU_CNT=1,PROBE599_WIDTH=1,PROBE599_MU_CNT=1,PROBE600_WIDTH=1,PROBE600_MU_CNT=1,PROBE601_WIDTH=1,PROBE601_MU_CNT=1,PROBE602_WIDTH=1,PROBE602_MU_CNT=1,PROBE603_WIDTH=1,PROBE603_MU_CNT=1,PROBE604_WIDTH=1,PROBE604_MU_CNT=1,PROBE605_WIDTH=1,PROBE605_MU_CNT=1,PROBE606_WIDTH=1,PROBE606_MU_CNT=1,PROBE607_WIDTH=1,PROBE607_MU_CNT=1,PROBE608_WIDTH=1,PROBE608_MU_CNT=1,PROBE609_WIDTH=1,PROBE609_MU_CNT=1,PROBE610_WIDTH=1,PROBE610_MU_CNT=1,PROBE611_WIDTH=1,PROBE611_MU_CNT=1,PROBE612_WIDTH=1,PROBE612_MU_CNT=1,PROBE613_WIDTH=1,PROBE613_MU_CNT=1,PROBE614_WIDTH=1,PROBE614_MU_CNT=1,PROBE615_WIDTH=1,PROBE615_MU_CNT=1,PROBE616_WIDTH=1,PROBE616_MU_CNT=1,PROBE617_WIDTH=1,PROBE617_MU_CNT=1,PROBE618_WIDTH=1,PROBE618_MU_CNT=1,PROBE619_WIDTH=1,PROBE619_MU_CNT=1,PROBE620_WIDTH=1,PROBE620_MU_CNT=1,PROBE621_WIDTH=1,PROBE621_MU_CNT=1,PROBE622_WIDTH=1,PROBE622_MU_CNT=1,PROBE623_WIDTH=1,PROBE623_MU_CNT=1,PROBE624_WIDTH=1,PROBE624_MU_CNT=1,PROBE625_WIDTH=1,PROBE625_MU_CNT=1,PROBE626_WIDTH=1,PROBE626_MU_CNT=1,PROBE627_WIDTH=1,PROBE627_MU_CNT=1,PROBE628_WIDTH=1,PROBE628_MU_CNT=1,PROBE629_WIDTH=1,PROBE629_MU_CNT=1,PROBE630_WIDTH=1,PROBE630_MU_CNT=1,PROBE631_WIDTH=1,PROBE631_MU_CNT=1,PROBE632_WIDTH=1,PROBE632_MU_CNT=1,PROBE633_WIDTH=1,PROBE633_MU_CNT=1,PROBE634_WIDTH=1,PROBE634_MU_CNT=1,PROBE635_WIDTH=1,PROBE635_MU_CNT=1,PROBE636_WIDTH=1,PROBE636_MU_CNT=1,PROBE637_WIDTH=1,PROBE637_MU_CNT=1,PROBE638_WIDTH=1,PROBE638_MU_CNT=1,PROBE639_WIDTH=1,PROBE639_MU_CNT=1,PROBE640_WIDTH=1,PROBE640_MU_CNT=1,PROBE641_WIDTH=1,PROBE641_MU_CNT=1,PROBE642_WIDTH=1,PROBE642_MU_CNT=1,PROBE643_WIDTH=1,PROBE643_MU_CNT=1,PROBE644_WIDTH=1,PROBE644_MU_CNT=1,PROBE645_WIDTH=1,PROBE645_MU_CNT=1,PROBE646_WIDTH=1,PROBE646_MU_CNT=1,PROBE647_WIDTH=1,PROBE647_MU_CNT=1,PROBE648_WIDTH=1,PROBE648_MU_CNT=1,PROBE649_WIDTH=1,PROBE649_MU_CNT=1,PROBE650_WIDTH=1,PROBE650_MU_CNT=1,PROBE651_WIDTH=1,PROBE651_MU_CNT=1,PROBE652_WIDTH=1,PROBE652_MU_CNT=1,PROBE653_WIDTH=1,PROBE653_MU_CNT=1,PROBE654_WIDTH=1,PROBE654_MU_CNT=1,PROBE655_WIDTH=1,PROBE655_MU_CNT=1,PROBE656_WIDTH=1,PROBE656_MU_CNT=1,PROBE657_WIDTH=1,PROBE657_MU_CNT=1,PROBE658_WIDTH=1,PROBE658_MU_CNT=1,PROBE659_WIDTH=1,PROBE659_MU_CNT=1,PROBE660_WIDTH=1,PROBE660_MU_CNT=1,PROBE661_WIDTH=1,PROBE661_MU_CNT=1,PROBE662_WIDTH=1,PROBE662_MU_CNT=1,PROBE663_WIDTH=1,PROBE663_MU_CNT=1,PROBE664_WIDTH=1,PROBE664_MU_CNT=1,PROBE665_WIDTH=1,PROBE665_MU_CNT=1,PROBE666_WIDTH=1,PROBE666_MU_CNT=1,PROBE667_WIDTH=1,PROBE667_MU_CNT=1,PROBE668_WIDTH=1,PROBE668_MU_CNT=1,PROBE669_WIDTH=1,PROBE669_MU_CNT=1,PROBE670_WIDTH=1,PROBE670_MU_CNT=1,PROBE671_WIDTH=1,PROBE671_MU_CNT=1,PROBE672_WIDTH=1,PROBE672_MU_CNT=1,PROBE673_WIDTH=1,PROBE673_MU_CNT=1,PROBE674_WIDTH=1,PROBE674_MU_CNT=1,PROBE675_WIDTH=1,PROBE675_MU_CNT=1,PROBE676_WIDTH=1,PROBE676_MU_CNT=1,PROBE677_WIDTH=1,PROBE677_MU_CNT=1,PROBE678_WIDTH=1,PROBE678_MU_CNT=1,PROBE679_WIDTH=1,PROBE679_MU_CNT=1,PROBE680_WIDTH=1,PROBE680_MU_CNT=1,PROBE681_WIDTH=1,PROBE681_MU_CNT=1,PROBE682_WIDTH=1,PROBE682_MU_CNT=1,PROBE683_WIDTH=1,PROBE683_MU_CNT=1,PROBE684_WIDTH=1,PROBE684_MU_CNT=1,PROBE685_WIDTH=1,PROBE685_MU_CNT=1,PROBE686_WIDTH=1,PROBE686_MU_CNT=1,PROBE687_WIDTH=1,PROBE687_MU_CNT=1,PROBE688_WIDTH=1,PROBE688_MU_CNT=1,PROBE689_WIDTH=1,PROBE689_MU_CNT=1,PROBE690_WIDTH=1,PROBE690_MU_CNT=1,PROBE691_WIDTH=1,PROBE691_MU_CNT=1,PROBE692_WIDTH=1,PROBE692_MU_CNT=1,PROBE693_WIDTH=1,PROBE693_MU_CNT=1,PROBE694_WIDTH=1,PROBE694_MU_CNT=1,PROBE695_WIDTH=1,PROBE695_MU_CNT=1,PROBE696_WIDTH=1,PROBE696_MU_CNT=1,PROBE697_WIDTH=1,PROBE697_MU_CNT=1,PROBE698_WIDTH=1,PROBE698_MU_CNT=1,PROBE699_WIDTH=1,PROBE699_MU_CNT=1,PROBE700_WIDTH=1,PROBE700_MU_CNT=1,PROBE701_WIDTH=1,PROBE701_MU_CNT=1,PROBE702_WIDTH=1,PROBE702_MU_CNT=1,PROBE703_WIDTH=1,PROBE703_MU_CNT=1,PROBE704_WIDTH=1,PROBE704_MU_CNT=1,PROBE705_WIDTH=1,PROBE705_MU_CNT=1,PROBE706_WIDTH=1,PROBE706_MU_CNT=1,PROBE707_WIDTH=1,PROBE707_MU_CNT=1,PROBE708_WIDTH=1,PROBE708_MU_CNT=1,PROBE709_WIDTH=1,PROBE709_MU_CNT=1,PROBE710_WIDTH=1,PROBE710_MU_CNT=1,PROBE711_WIDTH=1,PROBE711_MU_CNT=1,PROBE712_WIDTH=1,PROBE712_MU_CNT=1,PROBE713_WIDTH=1,PROBE713_MU_CNT=1,PROBE714_WIDTH=1,PROBE714_MU_CNT=1,PROBE715_WIDTH=1,PROBE715_MU_CNT=1,PROBE716_WIDTH=1,PROBE716_MU_CNT=1,PROBE717_WIDTH=1,PROBE717_MU_CNT=1,PROBE718_WIDTH=1,PROBE718_MU_CNT=1,PROBE719_WIDTH=1,PROBE719_MU_CNT=1,PROBE720_WIDTH=1,PROBE720_MU_CNT=1,PROBE721_WIDTH=1,PROBE721_MU_CNT=1,PROBE722_WIDTH=1,PROBE722_MU_CNT=1,PROBE723_WIDTH=1,PROBE723_MU_CNT=1,PROBE724_WIDTH=1,PROBE724_MU_CNT=1,PROBE725_WIDTH=1,PROBE725_MU_CNT=1,PROBE726_WIDTH=1,PROBE726_MU_CNT=1,PROBE727_WIDTH=1,PROBE727_MU_CNT=1,PROBE728_WIDTH=1,PROBE728_MU_CNT=1,PROBE729_WIDTH=1,PROBE729_MU_CNT=1,PROBE730_WIDTH=1,PROBE730_MU_CNT=1,PROBE731_WIDTH=1,PROBE731_MU_CNT=1,PROBE732_WIDTH=1,PROBE732_MU_CNT=1,PROBE733_WIDTH=1,PROBE733_MU_CNT=1,PROBE734_WIDTH=1,PROBE734_MU_CNT=1,PROBE735_WIDTH=1,PROBE735_MU_CNT=1,PROBE736_WIDTH=1,PROBE736_MU_CNT=1,PROBE737_WIDTH=1,PROBE737_MU_CNT=1,PROBE738_WIDTH=1,PROBE738_MU_CNT=1,PROBE739_WIDTH=1,PROBE739_MU_CNT=1,PROBE740_WIDTH=1,PROBE740_MU_CNT=1,PROBE741_WIDTH=1,PROBE741_MU_CNT=1,PROBE742_WIDTH=1,PROBE742_MU_CNT=1,PROBE743_WIDTH=1,PROBE743_MU_CNT=1,PROBE744_WIDTH=1,PROBE744_MU_CNT=1,PROBE745_WIDTH=1,PROBE745_MU_CNT=1,PROBE746_WIDTH=1,PROBE746_MU_CNT=1,PROBE747_WIDTH=1,PROBE747_MU_CNT=1,PROBE748_WIDTH=1,PROBE748_MU_CNT=1,PROBE749_WIDTH=1,PROBE749_MU_CNT=1,PROBE750_WIDTH=1,PROBE750_MU_CNT=1,PROBE751_WIDTH=1,PROBE751_MU_CNT=1,PROBE752_WIDTH=1,PROBE752_MU_CNT=1,PROBE753_WIDTH=1,PROBE753_MU_CNT=1,PROBE754_WIDTH=1,PROBE754_MU_CNT=1,PROBE755_WIDTH=1,PROBE755_MU_CNT=1,PROBE756_WIDTH=1,PROBE756_MU_CNT=1,PROBE757_WIDTH=1,PROBE757_MU_CNT=1,PROBE758_WIDTH=1,PROBE758_MU_CNT=1,PROBE759_WIDTH=1,PROBE759_MU_CNT=1,PROBE760_WIDTH=1,PROBE760_MU_CNT=1,PROBE761_WIDTH=1,PROBE761_MU_CNT=1,PROBE762_WIDTH=1,PROBE762_MU_CNT=1,PROBE763_WIDTH=1,PROBE763_MU_CNT=1,PROBE764_WIDTH=1,PROBE764_MU_CNT=1,PROBE765_WIDTH=1,PROBE765_MU_CNT=1,PROBE766_WIDTH=1,PROBE766_MU_CNT=1,PROBE767_WIDTH=1,PROBE767_MU_CNT=1,PROBE768_WIDTH=1,PROBE768_MU_CNT=1,PROBE769_WIDTH=1,PROBE769_MU_CNT=1,PROBE770_WIDTH=1,PROBE770_MU_CNT=1,PROBE771_WIDTH=1,PROBE771_MU_CNT=1,PROBE772_WIDTH=1,PROBE772_MU_CNT=1,PROBE773_WIDTH=1,PROBE773_MU_CNT=1,PROBE774_WIDTH=1,PROBE774_MU_CNT=1,PROBE775_WIDTH=1,PROBE775_MU_CNT=1,PROBE776_WIDTH=1,PROBE776_MU_CNT=1,PROBE777_WIDTH=1,PROBE777_MU_CNT=1,PROBE778_WIDTH=1,PROBE778_MU_CNT=1,PROBE779_WIDTH=1,PROBE779_MU_CNT=1,PROBE780_WIDTH=1,PROBE780_MU_CNT=1,PROBE781_WIDTH=1,PROBE781_MU_CNT=1,PROBE782_WIDTH=1,PROBE782_MU_CNT=1,PROBE783_WIDTH=1,PROBE783_MU_CNT=1,PROBE784_WIDTH=1,PROBE784_MU_CNT=1,PROBE785_WIDTH=1,PROBE785_MU_CNT=1,PROBE786_WIDTH=1,PROBE786_MU_CNT=1,PROBE787_WIDTH=1,PROBE787_MU_CNT=1,PROBE788_WIDTH=1,PROBE788_MU_CNT=1,PROBE789_WIDTH=1,PROBE789_MU_CNT=1,PROBE790_WIDTH=1,PROBE790_MU_CNT=1,PROBE791_WIDTH=1,PROBE791_MU_CNT=1,PROBE792_WIDTH=1,PROBE792_MU_CNT=1,PROBE793_WIDTH=1,PROBE793_MU_CNT=1,PROBE794_WIDTH=1,PROBE794_MU_CNT=1,PROBE795_WIDTH=1,PROBE795_MU_CNT=1,PROBE796_WIDTH=1,PROBE796_MU_CNT=1,PROBE797_WIDTH=1,PROBE797_MU_CNT=1,PROBE798_WIDTH=1,PROBE798_MU_CNT=1,PROBE799_WIDTH=1,PROBE799_MU_CNT=1,PROBE800_WIDTH=1,PROBE800_MU_CNT=1,PROBE801_WIDTH=1,PROBE801_MU_CNT=1,PROBE802_WIDTH=1,PROBE802_MU_CNT=1,PROBE803_WIDTH=1,PROBE803_MU_CNT=1,PROBE804_WIDTH=1,PROBE804_MU_CNT=1,PROBE805_WIDTH=1,PROBE805_MU_CNT=1,PROBE806_WIDTH=1,PROBE806_MU_CNT=1,PROBE807_WIDTH=1,PROBE807_MU_CNT=1,PROBE808_WIDTH=1,PROBE808_MU_CNT=1,PROBE809_WIDTH=1,PROBE809_MU_CNT=1,PROBE810_WIDTH=1,PROBE810_MU_CNT=1,PROBE811_WIDTH=1,PROBE811_MU_CNT=1,PROBE812_WIDTH=1,PROBE812_MU_CNT=1,PROBE813_WIDTH=1,PROBE813_MU_CNT=1,PROBE814_WIDTH=1,PROBE814_MU_CNT=1,PROBE815_WIDTH=1,PROBE815_MU_CNT=1,PROBE816_WIDTH=1,PROBE816_MU_CNT=1,PROBE817_WIDTH=1,PROBE817_MU_CNT=1,PROBE818_WIDTH=1,PROBE818_MU_CNT=1,PROBE819_WIDTH=1,PROBE819_MU_CNT=1,PROBE820_WIDTH=1,PROBE820_MU_CNT=1,PROBE821_WIDTH=1,PROBE821_MU_CNT=1,PROBE822_WIDTH=1,PROBE822_MU_CNT=1,PROBE823_WIDTH=1,PROBE823_MU_CNT=1,PROBE824_WIDTH=1,PROBE824_MU_CNT=1,PROBE825_WIDTH=1,PROBE825_MU_CNT=1,PROBE826_WIDTH=1,PROBE826_MU_CNT=1,PROBE827_WIDTH=1,PROBE827_MU_CNT=1,PROBE828_WIDTH=1,PROBE828_MU_CNT=1,PROBE829_WIDTH=1,PROBE829_MU_CNT=1,PROBE830_WIDTH=1,PROBE830_MU_CNT=1,PROBE831_WIDTH=1,PROBE831_MU_CNT=1,PROBE832_WIDTH=1,PROBE832_MU_CNT=1,PROBE833_WIDTH=1,PROBE833_MU_CNT=1,PROBE834_WIDTH=1,PROBE834_MU_CNT=1,PROBE835_WIDTH=1,PROBE835_MU_CNT=1,PROBE836_WIDTH=1,PROBE836_MU_CNT=1,PROBE837_WIDTH=1,PROBE837_MU_CNT=1,PROBE838_WIDTH=1,PROBE838_MU_CNT=1,PROBE839_WIDTH=1,PROBE839_MU_CNT=1,PROBE840_WIDTH=1,PROBE840_MU_CNT=1,PROBE841_WIDTH=1,PROBE841_MU_CNT=1,PROBE842_WIDTH=1,PROBE842_MU_CNT=1,PROBE843_WIDTH=1,PROBE843_MU_CNT=1,PROBE844_WIDTH=1,PROBE844_MU_CNT=1,PROBE845_WIDTH=1,PROBE845_MU_CNT=1,PROBE846_WIDTH=1,PROBE846_MU_CNT=1,PROBE847_WIDTH=1,PROBE847_MU_CNT=1,PROBE848_WIDTH=1,PROBE848_MU_CNT=1,PROBE849_WIDTH=1,PROBE849_MU_CNT=1,PROBE850_WIDTH=1,PROBE850_MU_CNT=1,PROBE851_WIDTH=1,PROBE851_MU_CNT=1,PROBE852_WIDTH=1,PROBE852_MU_CNT=1,PROBE853_WIDTH=1,PROBE853_MU_CNT=1,PROBE854_WIDTH=1,PROBE854_MU_CNT=1,PROBE855_WIDTH=1,PROBE855_MU_CNT=1,PROBE856_WIDTH=1,PROBE856_MU_CNT=1,PROBE857_WIDTH=1,PROBE857_MU_CNT=1,PROBE858_WIDTH=1,PROBE858_MU_CNT=1,PROBE859_WIDTH=1,PROBE859_MU_CNT=1,PROBE860_WIDTH=1,PROBE860_MU_CNT=1,PROBE861_WIDTH=1,PROBE861_MU_CNT=1,PROBE862_WIDTH=1,PROBE862_MU_CNT=1,PROBE863_WIDTH=1,PROBE863_MU_CNT=1,PROBE864_WIDTH=1,PROBE864_MU_CNT=1,PROBE865_WIDTH=1,PROBE865_MU_CNT=1,PROBE866_WIDTH=1,PROBE866_MU_CNT=1,PROBE867_WIDTH=1,PROBE867_MU_CNT=1,PROBE868_WIDTH=1,PROBE868_MU_CNT=1,PROBE869_WIDTH=1,PROBE869_MU_CNT=1,PROBE870_WIDTH=1,PROBE870_MU_CNT=1,PROBE871_WIDTH=1,PROBE871_MU_CNT=1,PROBE872_WIDTH=1,PROBE872_MU_CNT=1,PROBE873_WIDTH=1,PROBE873_MU_CNT=1,PROBE874_WIDTH=1,PROBE874_MU_CNT=1,PROBE875_WIDTH=1,PROBE875_MU_CNT=1,PROBE876_WIDTH=1,PROBE876_MU_CNT=1,PROBE877_WIDTH=1,PROBE877_MU_CNT=1,PROBE878_WIDTH=1,PROBE878_MU_CNT=1,PROBE879_WIDTH=1,PROBE879_MU_CNT=1,PROBE880_WIDTH=1,PROBE880_MU_CNT=1,PROBE881_WIDTH=1,PROBE881_MU_CNT=1,PROBE882_WIDTH=1,PROBE882_MU_CNT=1,PROBE883_WIDTH=1,PROBE883_MU_CNT=1,PROBE884_WIDTH=1,PROBE884_MU_CNT=1,PROBE885_WIDTH=1,PROBE885_MU_CNT=1,PROBE886_WIDTH=1,PROBE886_MU_CNT=1,PROBE887_WIDTH=1,PROBE887_MU_CNT=1,PROBE888_WIDTH=1,PROBE888_MU_CNT=1,PROBE889_WIDTH=1,PROBE889_MU_CNT=1,PROBE890_WIDTH=1,PROBE890_MU_CNT=1,PROBE891_WIDTH=1,PROBE891_MU_CNT=1,PROBE892_WIDTH=1,PROBE892_MU_CNT=1,PROBE893_WIDTH=1,PROBE893_MU_CNT=1,PROBE894_WIDTH=1,PROBE894_MU_CNT=1,PROBE895_WIDTH=1,PROBE895_MU_CNT=1,PROBE896_WIDTH=1,PROBE896_MU_CNT=1,PROBE897_WIDTH=1,PROBE897_MU_CNT=1,PROBE898_WIDTH=1,PROBE898_MU_CNT=1,PROBE899_WIDTH=1,PROBE899_MU_CNT=1,PROBE900_WIDTH=1,PROBE900_MU_CNT=1,PROBE901_WIDTH=1,PROBE901_MU_CNT=1,PROBE902_WIDTH=1,PROBE902_MU_CNT=1,PROBE903_WIDTH=1,PROBE903_MU_CNT=1,PROBE904_WIDTH=1,PROBE904_MU_CNT=1,PROBE905_WIDTH=1,PROBE905_MU_CNT=1,PROBE906_WIDTH=1,PROBE906_MU_CNT=1,PROBE907_WIDTH=1,PROBE907_MU_CNT=1,PROBE908_WIDTH=1,PROBE908_MU_CNT=1,PROBE909_WIDTH=1,PROBE909_MU_CNT=1,PROBE910_WIDTH=1,PROBE910_MU_CNT=1,PROBE911_WIDTH=1,PROBE911_MU_CNT=1,PROBE912_WIDTH=1,PROBE912_MU_CNT=1,PROBE913_WIDTH=1,PROBE913_MU_CNT=1,PROBE914_WIDTH=1,PROBE914_MU_CNT=1,PROBE915_WIDTH=1,PROBE915_MU_CNT=1,PROBE916_WIDTH=1,PROBE916_MU_CNT=1,PROBE917_WIDTH=1,PROBE917_MU_CNT=1,PROBE918_WIDTH=1,PROBE918_MU_CNT=1,PROBE919_WIDTH=1,PROBE919_MU_CNT=1,PROBE920_WIDTH=1,PROBE920_MU_CNT=1,PROBE921_WIDTH=1,PROBE921_MU_CNT=1,PROBE922_WIDTH=1,PROBE922_MU_CNT=1,PROBE923_WIDTH=1,PROBE923_MU_CNT=1,PROBE924_WIDTH=1,PROBE924_MU_CNT=1,PROBE925_WIDTH=1,PROBE925_MU_CNT=1,PROBE926_WIDTH=1,PROBE926_MU_CNT=1,PROBE927_WIDTH=1,PROBE927_MU_CNT=1,PROBE928_WIDTH=1,PROBE928_MU_CNT=1,PROBE929_WIDTH=1,PROBE929_MU_CNT=1,PROBE930_WIDTH=1,PROBE930_MU_CNT=1,PROBE931_WIDTH=1,PROBE931_MU_CNT=1,PROBE932_WIDTH=1,PROBE932_MU_CNT=1,PROBE933_WIDTH=1,PROBE933_MU_CNT=1,PROBE934_WIDTH=1,PROBE934_MU_CNT=1,PROBE935_WIDTH=1,PROBE935_MU_CNT=1,PROBE936_WIDTH=1,PROBE936_MU_CNT=1,PROBE937_WIDTH=1,PROBE937_MU_CNT=1,PROBE938_WIDTH=1,PROBE938_MU_CNT=1,PROBE939_WIDTH=1,PROBE939_MU_CNT=1,PROBE940_WIDTH=1,PROBE940_MU_CNT=1,PROBE941_WIDTH=1,PROBE941_MU_CNT=1,PROBE942_WIDTH=1,PROBE942_MU_CNT=1,PROBE943_WIDTH=1,PROBE943_MU_CNT=1,PROBE944_WIDTH=1,PROBE944_MU_CNT=1,PROBE945_WIDTH=1,PROBE945_MU_CNT=1,PROBE946_WIDTH=1,PROBE946_MU_CNT=1,PROBE947_WIDTH=1,PROBE947_MU_CNT=1,PROBE948_WIDTH=1,PROBE948_MU_CNT=1,PROBE949_WIDTH=1,PROBE949_MU_CNT=1,PROBE950_WIDTH=1,PROBE950_MU_CNT=1,PROBE951_WIDTH=1,PROBE951_MU_CNT=1,PROBE952_WIDTH=1,PROBE952_MU_CNT=1,PROBE953_WIDTH=1,PROBE953_MU_CNT=1,PROBE954_WIDTH=1,PROBE954_MU_CNT=1,PROBE955_WIDTH=1,PROBE955_MU_CNT=1,PROBE956_WIDTH=1,PROBE956_MU_CNT=1,PROBE957_WIDTH=1,PROBE957_MU_CNT=1,PROBE958_WIDTH=1,PROBE958_MU_CNT=1,PROBE959_WIDTH=1,PROBE959_MU_CNT=1,PROBE960_WIDTH=1,PROBE960_MU_CNT=1,PROBE961_WIDTH=1,PROBE961_MU_CNT=1,PROBE962_WIDTH=1,PROBE962_MU_CNT=1,PROBE963_WIDTH=1,PROBE963_MU_CNT=1,PROBE964_WIDTH=1,PROBE964_MU_CNT=1,PROBE965_WIDTH=1,PROBE965_MU_CNT=1,PROBE966_WIDTH=1,PROBE966_MU_CNT=1,PROBE967_WIDTH=1,PROBE967_MU_CNT=1,PROBE968_WIDTH=1,PROBE968_MU_CNT=1,PROBE969_WIDTH=1,PROBE969_MU_CNT=1,PROBE970_WIDTH=1,PROBE970_MU_CNT=1,PROBE971_WIDTH=1,PROBE971_MU_CNT=1,PROBE972_WIDTH=1,PROBE972_MU_CNT=1,PROBE973_WIDTH=1,PROBE973_MU_CNT=1,PROBE974_WIDTH=1,PROBE974_MU_CNT=1,PROBE975_WIDTH=1,PROBE975_MU_CNT=1,PROBE976_WIDTH=1,PROBE976_MU_CNT=1,PROBE977_WIDTH=1,PROBE977_MU_CNT=1,PROBE978_WIDTH=1,PROBE978_MU_CNT=1,PROBE979_WIDTH=1,PROBE979_MU_CNT=1,PROBE980_WIDTH=1,PROBE980_MU_CNT=1,PROBE981_WIDTH=1,PROBE981_MU_CNT=1,PROBE982_WIDTH=1,PROBE982_MU_CNT=1,PROBE983_WIDTH=1,PROBE983_MU_CNT=1,PROBE984_WIDTH=1,PROBE984_MU_CNT=1,PROBE985_WIDTH=1,PROBE985_MU_CNT=1,PROBE986_WIDTH=1,PROBE986_MU_CNT=1,PROBE987_WIDTH=1,PROBE987_MU_CNT=1,PROBE988_WIDTH=1,PROBE988_MU_CNT=1,PROBE989_WIDTH=1,PROBE989_MU_CNT=1,PROBE990_WIDTH=1,PROBE990_MU_CNT=1,PROBE991_WIDTH=1,PROBE991_MU_CNT=1,PROBE992_WIDTH=1,PROBE992_MU_CNT=1,PROBE993_WIDTH=1,PROBE993_MU_CNT=1,PROBE994_WIDTH=1,PROBE994_MU_CNT=1,PROBE995_WIDTH=1,PROBE995_MU_CNT=1,PROBE996_WIDTH=1,PROBE996_MU_CNT=1,PROBE997_WIDTH=1,PROBE997_MU_CNT=1,PROBE998_WIDTH=1,PROBE998_MU_CNT=1,PROBE999_WIDTH=1,PROBE999_MU_CNT=1,PROBE1000_WIDTH=1,PROBE1000_MU_CNT=1,PROBE1001_WIDTH=1,PROBE1001_MU_CNT=1,PROBE1002_WIDTH=1,PROBE1002_MU_CNT=1,PROBE1003_WIDTH=1,PROBE1003_MU_CNT=1,PROBE1004_WIDTH=1,PROBE1004_MU_CNT=1,PROBE1005_WIDTH=1,PROBE1005_MU_CNT=1,PROBE1006_WIDTH=1,PROBE1006_MU_CNT=1,PROBE1007_WIDTH=1,PROBE1007_MU_CNT=1,PROBE1008_WIDTH=1,PROBE1008_MU_CNT=1,PROBE1009_WIDTH=1,PROBE1009_MU_CNT=1,PROBE1010_WIDTH=1,PROBE1010_MU_CNT=1,PROBE1011_WIDTH=1,PROBE1011_MU_CNT=1,PROBE1012_WIDTH=1,PROBE1012_MU_CNT=1,PROBE1013_WIDTH=1,PROBE1013_MU_CNT=1,PROBE1014_WIDTH=1,PROBE1014_MU_CNT=1,PROBE1015_WIDTH=1,PROBE1015_MU_CNT=1,PROBE1016_WIDTH=1,PROBE1016_MU_CNT=1,PROBE1017_WIDTH=1,PROBE1017_MU_CNT=1,PROBE1018_WIDTH=1,PROBE1018_MU_CNT=1,PROBE1019_WIDTH=1,PROBE1019_MU_CNT=1,PROBE1020_WIDTH=1,PROBE1020_MU_CNT=1,PROBE1021_WIDTH=1,PROBE1021_MU_CNT=1,PROBE1022_WIDTH=1,PROBE1022_MU_CNT=1,PROBE1023_WIDTH=1,PROBE1023_MU_CNT=1"),
.C_XDEVICEFAMILY("zynq"),
.C_CORE_TYPE(1),
.C_CORE_INFO1(0),
.C_CORE_INFO2(0),
.C_CAPTURE_TYPE(0),
.C_MU_TYPE(0),
.C_TC_TYPE(0),
.C_NUM_OF_PROBES(1),
.C_DATA_DEPTH(1024),
.C_MAJOR_VERSION(2015),
.C_MINOR_VERSION(2),
.C_BUILD_REVISION(0),
.C_CORE_MAJOR_VER(5),
.C_CORE_MINOR_VER(1),
.C_XSDB_SLAVE_TYPE(17),
.C_NEXT_SLAVE(0),
.C_CSE_DRV_VER(1),
.C_USE_TEST_REG(1),
.C_PIPE_IFACE(1),
.C_RAM_STYLE("SUBCORE"),
.C_TRIGOUT_EN(1),
.C_TRIGIN_EN(1),
.C_ADV_TRIGGER(1),
.C_EN_DDR_ILA(0),
.C_DDR_CLK_GEN(0),
.C_CLK_FREQ(200.00),
.C_CLK_PERIOD(5.0),
.C_CLKFBOUT_MULT_F(10.0),
.C_DIVCLK_DIVIDE(2),
.C_CLKOUT0_DIVIDE_F(10.0),
.C_EN_STRG_QUAL(1),
.C_INPUT_PIPE_STAGES(0),
.C_PROBE0_WIDTH(1),
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.C_PROBE810_WIDTH(1),
.C_PROBE811_WIDTH(1),
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.C_PROBE815_WIDTH(1),
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.C_PROBE818_WIDTH(1),
.C_PROBE819_WIDTH(1),
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.C_PROBE821_WIDTH(1),
.C_PROBE822_WIDTH(1),
.C_PROBE823_WIDTH(1),
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.C_PROBE834_WIDTH(1),
.C_PROBE835_WIDTH(1),
.C_PROBE836_WIDTH(1),
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.C_PROBE877_WIDTH(1),
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.C_PROBE890_WIDTH(1),
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.C_PROBE904_WIDTH(1),
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.C_PROBE913_WIDTH(1),
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.C_PROBE916_WIDTH(1),
.C_PROBE917_WIDTH(1),
.C_PROBE918_WIDTH(1),
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.C_PROBE920_WIDTH(1),
.C_PROBE921_WIDTH(1),
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.C_PROBE929_WIDTH(1),
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.C_PROBE932_WIDTH(1),
.C_PROBE933_WIDTH(1),
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.C_PROBE935_WIDTH(1),
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.C_PROBE937_WIDTH(1),
.C_PROBE938_WIDTH(1),
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.C_PROBE941_WIDTH(1),
.C_PROBE942_WIDTH(1),
.C_PROBE943_WIDTH(1),
.C_PROBE944_WIDTH(1),
.C_PROBE945_WIDTH(1),
.C_PROBE946_WIDTH(1),
.C_PROBE947_WIDTH(1),
.C_PROBE948_WIDTH(1),
.C_PROBE949_WIDTH(1),
.C_PROBE950_WIDTH(1),
.C_PROBE951_WIDTH(1),
.C_PROBE952_WIDTH(1),
.C_PROBE953_WIDTH(1),
.C_PROBE954_WIDTH(1),
.C_PROBE955_WIDTH(1),
.C_PROBE956_WIDTH(1),
.C_PROBE957_WIDTH(1),
.C_PROBE958_WIDTH(1),
.C_PROBE959_WIDTH(1),
.C_PROBE960_WIDTH(1),
.C_PROBE961_WIDTH(1),
.C_PROBE962_WIDTH(1),
.C_PROBE963_WIDTH(1),
.C_PROBE964_WIDTH(1),
.C_PROBE965_WIDTH(1),
.C_PROBE966_WIDTH(1),
.C_PROBE967_WIDTH(1),
.C_PROBE968_WIDTH(1),
.C_PROBE969_WIDTH(1),
.C_PROBE970_WIDTH(1),
.C_PROBE971_WIDTH(1),
.C_PROBE972_WIDTH(1),
.C_PROBE973_WIDTH(1),
.C_PROBE974_WIDTH(1),
.C_PROBE975_WIDTH(1),
.C_PROBE976_WIDTH(1),
.C_PROBE977_WIDTH(1),
.C_PROBE978_WIDTH(1),
.C_PROBE979_WIDTH(1),
.C_PROBE980_WIDTH(1),
.C_PROBE981_WIDTH(1),
.C_PROBE982_WIDTH(1),
.C_PROBE983_WIDTH(1),
.C_PROBE984_WIDTH(1),
.C_PROBE985_WIDTH(1),
.C_PROBE986_WIDTH(1),
.C_PROBE987_WIDTH(1),
.C_PROBE988_WIDTH(1),
.C_PROBE989_WIDTH(1),
.C_PROBE990_WIDTH(1),
.C_PROBE991_WIDTH(1),
.C_PROBE992_WIDTH(1),
.C_PROBE993_WIDTH(1),
.C_PROBE994_WIDTH(1),
.C_PROBE995_WIDTH(1),
.C_PROBE996_WIDTH(1),
.C_PROBE997_WIDTH(1),
.C_PROBE998_WIDTH(1),
.C_PROBE999_WIDTH(1),
.C_PROBE1000_WIDTH(1),
.C_PROBE1001_WIDTH(1),
.C_PROBE1002_WIDTH(1),
.C_PROBE1003_WIDTH(1),
.C_PROBE1004_WIDTH(1),
.C_PROBE1005_WIDTH(1),
.C_PROBE1006_WIDTH(1),
.C_PROBE1007_WIDTH(1),
.C_PROBE1008_WIDTH(1),
.C_PROBE1009_WIDTH(1),
.C_PROBE1010_WIDTH(1),
.C_PROBE1011_WIDTH(1),
.C_PROBE1012_WIDTH(1),
.C_PROBE1013_WIDTH(1),
.C_PROBE1014_WIDTH(1),
.C_PROBE1015_WIDTH(1),
.C_PROBE1016_WIDTH(1),
.C_PROBE1017_WIDTH(1),
.C_PROBE1018_WIDTH(1),
.C_PROBE1019_WIDTH(1),
.C_PROBE1020_WIDTH(1),
.C_PROBE1021_WIDTH(1),
.C_PROBE1022_WIDTH(1),
.C_PROBE1023_WIDTH(1),
.C_PROBE0_MU_CNT(4),
.C_PROBE1_MU_CNT(1),
.C_PROBE2_MU_CNT(1),
.C_PROBE3_MU_CNT(1),
.C_PROBE4_MU_CNT(1),
.C_PROBE5_MU_CNT(1),
.C_PROBE6_MU_CNT(1),
.C_PROBE7_MU_CNT(1),
.C_PROBE8_MU_CNT(1),
.C_PROBE9_MU_CNT(1),
.C_PROBE10_MU_CNT(1),
.C_PROBE11_MU_CNT(1),
.C_PROBE12_MU_CNT(1),
.C_PROBE13_MU_CNT(1),
.C_PROBE14_MU_CNT(1),
.C_PROBE15_MU_CNT(1),
.C_PROBE16_MU_CNT(1),
.C_PROBE17_MU_CNT(1),
.C_PROBE18_MU_CNT(1),
.C_PROBE19_MU_CNT(1),
.C_PROBE20_MU_CNT(1),
.C_PROBE21_MU_CNT(1),
.C_PROBE22_MU_CNT(1),
.C_PROBE23_MU_CNT(1),
.C_PROBE24_MU_CNT(1),
.C_PROBE25_MU_CNT(1),
.C_PROBE26_MU_CNT(1),
.C_PROBE27_MU_CNT(1),
.C_PROBE28_MU_CNT(1),
.C_PROBE29_MU_CNT(1),
.C_PROBE30_MU_CNT(1),
.C_PROBE31_MU_CNT(1),
.C_PROBE32_MU_CNT(1),
.C_PROBE33_MU_CNT(1),
.C_PROBE34_MU_CNT(1),
.C_PROBE35_MU_CNT(1),
.C_PROBE36_MU_CNT(1),
.C_PROBE37_MU_CNT(1),
.C_PROBE38_MU_CNT(1),
.C_PROBE39_MU_CNT(1),
.C_PROBE40_MU_CNT(1),
.C_PROBE41_MU_CNT(1),
.C_PROBE42_MU_CNT(1),
.C_PROBE43_MU_CNT(1),
.C_PROBE44_MU_CNT(1),
.C_PROBE45_MU_CNT(1),
.C_PROBE46_MU_CNT(1),
.C_PROBE47_MU_CNT(1),
.C_PROBE48_MU_CNT(1),
.C_PROBE49_MU_CNT(1),
.C_PROBE50_MU_CNT(1),
.C_PROBE51_MU_CNT(1),
.C_PROBE52_MU_CNT(1),
.C_PROBE53_MU_CNT(1),
.C_PROBE54_MU_CNT(1),
.C_PROBE55_MU_CNT(1),
.C_PROBE56_MU_CNT(1),
.C_PROBE57_MU_CNT(1),
.C_PROBE58_MU_CNT(1),
.C_PROBE59_MU_CNT(1),
.C_PROBE60_MU_CNT(1),
.C_PROBE61_MU_CNT(1),
.C_PROBE62_MU_CNT(1),
.C_PROBE63_MU_CNT(1),
.C_PROBE64_MU_CNT(1),
.C_PROBE65_MU_CNT(1),
.C_PROBE66_MU_CNT(1),
.C_PROBE67_MU_CNT(1),
.C_PROBE68_MU_CNT(1),
.C_PROBE69_MU_CNT(1),
.C_PROBE70_MU_CNT(1),
.C_PROBE71_MU_CNT(1),
.C_PROBE72_MU_CNT(1),
.C_PROBE73_MU_CNT(1),
.C_PROBE74_MU_CNT(1),
.C_PROBE75_MU_CNT(1),
.C_PROBE76_MU_CNT(1),
.C_PROBE77_MU_CNT(1),
.C_PROBE78_MU_CNT(1),
.C_PROBE79_MU_CNT(1),
.C_PROBE80_MU_CNT(1),
.C_PROBE81_MU_CNT(1),
.C_PROBE82_MU_CNT(1),
.C_PROBE83_MU_CNT(1),
.C_PROBE84_MU_CNT(1),
.C_PROBE85_MU_CNT(1),
.C_PROBE86_MU_CNT(1),
.C_PROBE87_MU_CNT(1),
.C_PROBE88_MU_CNT(1),
.C_PROBE89_MU_CNT(1),
.C_PROBE90_MU_CNT(1),
.C_PROBE91_MU_CNT(1),
.C_PROBE92_MU_CNT(1),
.C_PROBE93_MU_CNT(1),
.C_PROBE94_MU_CNT(1),
.C_PROBE95_MU_CNT(1),
.C_PROBE96_MU_CNT(1),
.C_PROBE97_MU_CNT(1),
.C_PROBE98_MU_CNT(1),
.C_PROBE99_MU_CNT(1),
.C_PROBE100_MU_CNT(1),
.C_PROBE101_MU_CNT(1),
.C_PROBE102_MU_CNT(1),
.C_PROBE103_MU_CNT(1),
.C_PROBE104_MU_CNT(1),
.C_PROBE105_MU_CNT(1),
.C_PROBE106_MU_CNT(1),
.C_PROBE107_MU_CNT(1),
.C_PROBE108_MU_CNT(1),
.C_PROBE109_MU_CNT(1),
.C_PROBE110_MU_CNT(1),
.C_PROBE111_MU_CNT(1),
.C_PROBE112_MU_CNT(1),
.C_PROBE113_MU_CNT(1),
.C_PROBE114_MU_CNT(1),
.C_PROBE115_MU_CNT(1),
.C_PROBE116_MU_CNT(1),
.C_PROBE117_MU_CNT(1),
.C_PROBE118_MU_CNT(1),
.C_PROBE119_MU_CNT(1),
.C_PROBE120_MU_CNT(1),
.C_PROBE121_MU_CNT(1),
.C_PROBE122_MU_CNT(1),
.C_PROBE123_MU_CNT(1),
.C_PROBE124_MU_CNT(1),
.C_PROBE125_MU_CNT(1),
.C_PROBE126_MU_CNT(1),
.C_PROBE127_MU_CNT(1),
.C_PROBE128_MU_CNT(1),
.C_PROBE129_MU_CNT(1),
.C_PROBE130_MU_CNT(1),
.C_PROBE131_MU_CNT(1),
.C_PROBE132_MU_CNT(1),
.C_PROBE133_MU_CNT(1),
.C_PROBE134_MU_CNT(1),
.C_PROBE135_MU_CNT(1),
.C_PROBE136_MU_CNT(1),
.C_PROBE137_MU_CNT(1),
.C_PROBE138_MU_CNT(1),
.C_PROBE139_MU_CNT(1),
.C_PROBE140_MU_CNT(1),
.C_PROBE141_MU_CNT(1),
.C_PROBE142_MU_CNT(1),
.C_PROBE143_MU_CNT(1),
.C_PROBE144_MU_CNT(1),
.C_PROBE145_MU_CNT(1),
.C_PROBE146_MU_CNT(1),
.C_PROBE147_MU_CNT(1),
.C_PROBE148_MU_CNT(1),
.C_PROBE149_MU_CNT(1),
.C_PROBE150_MU_CNT(1),
.C_PROBE151_MU_CNT(1),
.C_PROBE152_MU_CNT(1),
.C_PROBE153_MU_CNT(1),
.C_PROBE154_MU_CNT(1),
.C_PROBE155_MU_CNT(1),
.C_PROBE156_MU_CNT(1),
.C_PROBE157_MU_CNT(1),
.C_PROBE158_MU_CNT(1),
.C_PROBE159_MU_CNT(1),
.C_PROBE160_MU_CNT(1),
.C_PROBE161_MU_CNT(1),
.C_PROBE162_MU_CNT(1),
.C_PROBE163_MU_CNT(1),
.C_PROBE164_MU_CNT(1),
.C_PROBE165_MU_CNT(1),
.C_PROBE166_MU_CNT(1),
.C_PROBE167_MU_CNT(1),
.C_PROBE168_MU_CNT(1),
.C_PROBE169_MU_CNT(1),
.C_PROBE170_MU_CNT(1),
.C_PROBE171_MU_CNT(1),
.C_PROBE172_MU_CNT(1),
.C_PROBE173_MU_CNT(1),
.C_PROBE174_MU_CNT(1),
.C_PROBE175_MU_CNT(1),
.C_PROBE176_MU_CNT(1),
.C_PROBE177_MU_CNT(1),
.C_PROBE178_MU_CNT(1),
.C_PROBE179_MU_CNT(1),
.C_PROBE180_MU_CNT(1),
.C_PROBE181_MU_CNT(1),
.C_PROBE182_MU_CNT(1),
.C_PROBE183_MU_CNT(1),
.C_PROBE184_MU_CNT(1),
.C_PROBE185_MU_CNT(1),
.C_PROBE186_MU_CNT(1),
.C_PROBE187_MU_CNT(1),
.C_PROBE188_MU_CNT(1),
.C_PROBE189_MU_CNT(1),
.C_PROBE190_MU_CNT(1),
.C_PROBE191_MU_CNT(1),
.C_PROBE192_MU_CNT(1),
.C_PROBE193_MU_CNT(1),
.C_PROBE194_MU_CNT(1),
.C_PROBE195_MU_CNT(1),
.C_PROBE196_MU_CNT(1),
.C_PROBE197_MU_CNT(1),
.C_PROBE198_MU_CNT(1),
.C_PROBE199_MU_CNT(1),
.C_PROBE200_MU_CNT(1),
.C_PROBE201_MU_CNT(1),
.C_PROBE202_MU_CNT(1),
.C_PROBE203_MU_CNT(1),
.C_PROBE204_MU_CNT(1),
.C_PROBE205_MU_CNT(1),
.C_PROBE206_MU_CNT(1),
.C_PROBE207_MU_CNT(1),
.C_PROBE208_MU_CNT(1),
.C_PROBE209_MU_CNT(1),
.C_PROBE210_MU_CNT(1),
.C_PROBE211_MU_CNT(1),
.C_PROBE212_MU_CNT(1),
.C_PROBE213_MU_CNT(1),
.C_PROBE214_MU_CNT(1),
.C_PROBE215_MU_CNT(1),
.C_PROBE216_MU_CNT(1),
.C_PROBE217_MU_CNT(1),
.C_PROBE218_MU_CNT(1),
.C_PROBE219_MU_CNT(1),
.C_PROBE220_MU_CNT(1),
.C_PROBE221_MU_CNT(1),
.C_PROBE222_MU_CNT(1),
.C_PROBE223_MU_CNT(1),
.C_PROBE224_MU_CNT(1),
.C_PROBE225_MU_CNT(1),
.C_PROBE226_MU_CNT(1),
.C_PROBE227_MU_CNT(1),
.C_PROBE228_MU_CNT(1),
.C_PROBE229_MU_CNT(1),
.C_PROBE230_MU_CNT(1),
.C_PROBE231_MU_CNT(1),
.C_PROBE232_MU_CNT(1),
.C_PROBE233_MU_CNT(1),
.C_PROBE234_MU_CNT(1),
.C_PROBE235_MU_CNT(1),
.C_PROBE236_MU_CNT(1),
.C_PROBE237_MU_CNT(1),
.C_PROBE238_MU_CNT(1),
.C_PROBE239_MU_CNT(1),
.C_PROBE240_MU_CNT(1),
.C_PROBE241_MU_CNT(1),
.C_PROBE242_MU_CNT(1),
.C_PROBE243_MU_CNT(1),
.C_PROBE244_MU_CNT(1),
.C_PROBE245_MU_CNT(1),
.C_PROBE246_MU_CNT(1),
.C_PROBE247_MU_CNT(1),
.C_PROBE248_MU_CNT(1),
.C_PROBE249_MU_CNT(1),
.C_PROBE250_MU_CNT(1),
.C_PROBE251_MU_CNT(1),
.C_PROBE252_MU_CNT(1),
.C_PROBE253_MU_CNT(1),
.C_PROBE254_MU_CNT(1),
.C_PROBE255_MU_CNT(1),
.C_PROBE256_MU_CNT(1),
.C_PROBE257_MU_CNT(1),
.C_PROBE258_MU_CNT(1),
.C_PROBE259_MU_CNT(1),
.C_PROBE260_MU_CNT(1),
.C_PROBE261_MU_CNT(1),
.C_PROBE262_MU_CNT(1),
.C_PROBE263_MU_CNT(1),
.C_PROBE264_MU_CNT(1),
.C_PROBE265_MU_CNT(1),
.C_PROBE266_MU_CNT(1),
.C_PROBE267_MU_CNT(1),
.C_PROBE268_MU_CNT(1),
.C_PROBE269_MU_CNT(1),
.C_PROBE270_MU_CNT(1),
.C_PROBE271_MU_CNT(1),
.C_PROBE272_MU_CNT(1),
.C_PROBE273_MU_CNT(1),
.C_PROBE274_MU_CNT(1),
.C_PROBE275_MU_CNT(1),
.C_PROBE276_MU_CNT(1),
.C_PROBE277_MU_CNT(1),
.C_PROBE278_MU_CNT(1),
.C_PROBE279_MU_CNT(1),
.C_PROBE280_MU_CNT(1),
.C_PROBE281_MU_CNT(1),
.C_PROBE282_MU_CNT(1),
.C_PROBE283_MU_CNT(1),
.C_PROBE284_MU_CNT(1),
.C_PROBE285_MU_CNT(1),
.C_PROBE286_MU_CNT(1),
.C_PROBE287_MU_CNT(1),
.C_PROBE288_MU_CNT(1),
.C_PROBE289_MU_CNT(1),
.C_PROBE290_MU_CNT(1),
.C_PROBE291_MU_CNT(1),
.C_PROBE292_MU_CNT(1),
.C_PROBE293_MU_CNT(1),
.C_PROBE294_MU_CNT(1),
.C_PROBE295_MU_CNT(1),
.C_PROBE296_MU_CNT(1),
.C_PROBE297_MU_CNT(1),
.C_PROBE298_MU_CNT(1),
.C_PROBE299_MU_CNT(1),
.C_PROBE300_MU_CNT(1),
.C_PROBE301_MU_CNT(1),
.C_PROBE302_MU_CNT(1),
.C_PROBE303_MU_CNT(1),
.C_PROBE304_MU_CNT(1),
.C_PROBE305_MU_CNT(1),
.C_PROBE306_MU_CNT(1),
.C_PROBE307_MU_CNT(1),
.C_PROBE308_MU_CNT(1),
.C_PROBE309_MU_CNT(1),
.C_PROBE310_MU_CNT(1),
.C_PROBE311_MU_CNT(1),
.C_PROBE312_MU_CNT(1),
.C_PROBE313_MU_CNT(1),
.C_PROBE314_MU_CNT(1),
.C_PROBE315_MU_CNT(1),
.C_PROBE316_MU_CNT(1),
.C_PROBE317_MU_CNT(1),
.C_PROBE318_MU_CNT(1),
.C_PROBE319_MU_CNT(1),
.C_PROBE320_MU_CNT(1),
.C_PROBE321_MU_CNT(1),
.C_PROBE322_MU_CNT(1),
.C_PROBE323_MU_CNT(1),
.C_PROBE324_MU_CNT(1),
.C_PROBE325_MU_CNT(1),
.C_PROBE326_MU_CNT(1),
.C_PROBE327_MU_CNT(1),
.C_PROBE328_MU_CNT(1),
.C_PROBE329_MU_CNT(1),
.C_PROBE330_MU_CNT(1),
.C_PROBE331_MU_CNT(1),
.C_PROBE332_MU_CNT(1),
.C_PROBE333_MU_CNT(1),
.C_PROBE334_MU_CNT(1),
.C_PROBE335_MU_CNT(1),
.C_PROBE336_MU_CNT(1),
.C_PROBE337_MU_CNT(1),
.C_PROBE338_MU_CNT(1),
.C_PROBE339_MU_CNT(1),
.C_PROBE340_MU_CNT(1),
.C_PROBE341_MU_CNT(1),
.C_PROBE342_MU_CNT(1),
.C_PROBE343_MU_CNT(1),
.C_PROBE344_MU_CNT(1),
.C_PROBE345_MU_CNT(1),
.C_PROBE346_MU_CNT(1),
.C_PROBE347_MU_CNT(1),
.C_PROBE348_MU_CNT(1),
.C_PROBE349_MU_CNT(1),
.C_PROBE350_MU_CNT(1),
.C_PROBE351_MU_CNT(1),
.C_PROBE352_MU_CNT(1),
.C_PROBE353_MU_CNT(1),
.C_PROBE354_MU_CNT(1),
.C_PROBE355_MU_CNT(1),
.C_PROBE356_MU_CNT(1),
.C_PROBE357_MU_CNT(1),
.C_PROBE358_MU_CNT(1),
.C_PROBE359_MU_CNT(1),
.C_PROBE360_MU_CNT(1),
.C_PROBE361_MU_CNT(1),
.C_PROBE362_MU_CNT(1),
.C_PROBE363_MU_CNT(1),
.C_PROBE364_MU_CNT(1),
.C_PROBE365_MU_CNT(1),
.C_PROBE366_MU_CNT(1),
.C_PROBE367_MU_CNT(1),
.C_PROBE368_MU_CNT(1),
.C_PROBE369_MU_CNT(1),
.C_PROBE370_MU_CNT(1),
.C_PROBE371_MU_CNT(1),
.C_PROBE372_MU_CNT(1),
.C_PROBE373_MU_CNT(1),
.C_PROBE374_MU_CNT(1),
.C_PROBE375_MU_CNT(1),
.C_PROBE376_MU_CNT(1),
.C_PROBE377_MU_CNT(1),
.C_PROBE378_MU_CNT(1),
.C_PROBE379_MU_CNT(1),
.C_PROBE380_MU_CNT(1),
.C_PROBE381_MU_CNT(1),
.C_PROBE382_MU_CNT(1),
.C_PROBE383_MU_CNT(1),
.C_PROBE384_MU_CNT(1),
.C_PROBE385_MU_CNT(1),
.C_PROBE386_MU_CNT(1),
.C_PROBE387_MU_CNT(1),
.C_PROBE388_MU_CNT(1),
.C_PROBE389_MU_CNT(1),
.C_PROBE390_MU_CNT(1),
.C_PROBE391_MU_CNT(1),
.C_PROBE392_MU_CNT(1),
.C_PROBE393_MU_CNT(1),
.C_PROBE394_MU_CNT(1),
.C_PROBE395_MU_CNT(1),
.C_PROBE396_MU_CNT(1),
.C_PROBE397_MU_CNT(1),
.C_PROBE398_MU_CNT(1),
.C_PROBE399_MU_CNT(1),
.C_PROBE400_MU_CNT(1),
.C_PROBE401_MU_CNT(1),
.C_PROBE402_MU_CNT(1),
.C_PROBE403_MU_CNT(1),
.C_PROBE404_MU_CNT(1),
.C_PROBE405_MU_CNT(1),
.C_PROBE406_MU_CNT(1),
.C_PROBE407_MU_CNT(1),
.C_PROBE408_MU_CNT(1),
.C_PROBE409_MU_CNT(1),
.C_PROBE410_MU_CNT(1),
.C_PROBE411_MU_CNT(1),
.C_PROBE412_MU_CNT(1),
.C_PROBE413_MU_CNT(1),
.C_PROBE414_MU_CNT(1),
.C_PROBE415_MU_CNT(1),
.C_PROBE416_MU_CNT(1),
.C_PROBE417_MU_CNT(1),
.C_PROBE418_MU_CNT(1),
.C_PROBE419_MU_CNT(1),
.C_PROBE420_MU_CNT(1),
.C_PROBE421_MU_CNT(1),
.C_PROBE422_MU_CNT(1),
.C_PROBE423_MU_CNT(1),
.C_PROBE424_MU_CNT(1),
.C_PROBE425_MU_CNT(1),
.C_PROBE426_MU_CNT(1),
.C_PROBE427_MU_CNT(1),
.C_PROBE428_MU_CNT(1),
.C_PROBE429_MU_CNT(1),
.C_PROBE430_MU_CNT(1),
.C_PROBE431_MU_CNT(1),
.C_PROBE432_MU_CNT(1),
.C_PROBE433_MU_CNT(1),
.C_PROBE434_MU_CNT(1),
.C_PROBE435_MU_CNT(1),
.C_PROBE436_MU_CNT(1),
.C_PROBE437_MU_CNT(1),
.C_PROBE438_MU_CNT(1),
.C_PROBE439_MU_CNT(1),
.C_PROBE440_MU_CNT(1),
.C_PROBE441_MU_CNT(1),
.C_PROBE442_MU_CNT(1),
.C_PROBE443_MU_CNT(1),
.C_PROBE444_MU_CNT(1),
.C_PROBE445_MU_CNT(1),
.C_PROBE446_MU_CNT(1),
.C_PROBE447_MU_CNT(1),
.C_PROBE448_MU_CNT(1),
.C_PROBE449_MU_CNT(1),
.C_PROBE450_MU_CNT(1),
.C_PROBE451_MU_CNT(1),
.C_PROBE452_MU_CNT(1),
.C_PROBE453_MU_CNT(1),
.C_PROBE454_MU_CNT(1),
.C_PROBE455_MU_CNT(1),
.C_PROBE456_MU_CNT(1),
.C_PROBE457_MU_CNT(1),
.C_PROBE458_MU_CNT(1),
.C_PROBE459_MU_CNT(1),
.C_PROBE460_MU_CNT(1),
.C_PROBE461_MU_CNT(1),
.C_PROBE462_MU_CNT(1),
.C_PROBE463_MU_CNT(1),
.C_PROBE464_MU_CNT(1),
.C_PROBE465_MU_CNT(1),
.C_PROBE466_MU_CNT(1),
.C_PROBE467_MU_CNT(1),
.C_PROBE468_MU_CNT(1),
.C_PROBE469_MU_CNT(1),
.C_PROBE470_MU_CNT(1),
.C_PROBE471_MU_CNT(1),
.C_PROBE472_MU_CNT(1),
.C_PROBE473_MU_CNT(1),
.C_PROBE474_MU_CNT(1),
.C_PROBE475_MU_CNT(1),
.C_PROBE476_MU_CNT(1),
.C_PROBE477_MU_CNT(1),
.C_PROBE478_MU_CNT(1),
.C_PROBE479_MU_CNT(1),
.C_PROBE480_MU_CNT(1),
.C_PROBE481_MU_CNT(1),
.C_PROBE482_MU_CNT(1),
.C_PROBE483_MU_CNT(1),
.C_PROBE484_MU_CNT(1),
.C_PROBE485_MU_CNT(1),
.C_PROBE486_MU_CNT(1),
.C_PROBE487_MU_CNT(1),
.C_PROBE488_MU_CNT(1),
.C_PROBE489_MU_CNT(1),
.C_PROBE490_MU_CNT(1),
.C_PROBE491_MU_CNT(1),
.C_PROBE492_MU_CNT(1),
.C_PROBE493_MU_CNT(1),
.C_PROBE494_MU_CNT(1),
.C_PROBE495_MU_CNT(1),
.C_PROBE496_MU_CNT(1),
.C_PROBE497_MU_CNT(1),
.C_PROBE498_MU_CNT(1),
.C_PROBE499_MU_CNT(1),
.C_PROBE500_MU_CNT(1),
.C_PROBE501_MU_CNT(1),
.C_PROBE502_MU_CNT(1),
.C_PROBE503_MU_CNT(1),
.C_PROBE504_MU_CNT(1),
.C_PROBE505_MU_CNT(1),
.C_PROBE506_MU_CNT(1),
.C_PROBE507_MU_CNT(1),
.C_PROBE508_MU_CNT(1),
.C_PROBE509_MU_CNT(1),
.C_PROBE510_MU_CNT(1),
.C_PROBE511_MU_CNT(1),
.C_PROBE512_MU_CNT(1),
.C_PROBE513_MU_CNT(1),
.C_PROBE514_MU_CNT(1),
.C_PROBE515_MU_CNT(1),
.C_PROBE516_MU_CNT(1),
.C_PROBE517_MU_CNT(1),
.C_PROBE518_MU_CNT(1),
.C_PROBE519_MU_CNT(1),
.C_PROBE520_MU_CNT(1),
.C_PROBE521_MU_CNT(1),
.C_PROBE522_MU_CNT(1),
.C_PROBE523_MU_CNT(1),
.C_PROBE524_MU_CNT(1),
.C_PROBE525_MU_CNT(1),
.C_PROBE526_MU_CNT(1),
.C_PROBE527_MU_CNT(1),
.C_PROBE528_MU_CNT(1),
.C_PROBE529_MU_CNT(1),
.C_PROBE530_MU_CNT(1),
.C_PROBE531_MU_CNT(1),
.C_PROBE532_MU_CNT(1),
.C_PROBE533_MU_CNT(1),
.C_PROBE534_MU_CNT(1),
.C_PROBE535_MU_CNT(1),
.C_PROBE536_MU_CNT(1),
.C_PROBE537_MU_CNT(1),
.C_PROBE538_MU_CNT(1),
.C_PROBE539_MU_CNT(1),
.C_PROBE540_MU_CNT(1),
.C_PROBE541_MU_CNT(1),
.C_PROBE542_MU_CNT(1),
.C_PROBE543_MU_CNT(1),
.C_PROBE544_MU_CNT(1),
.C_PROBE545_MU_CNT(1),
.C_PROBE546_MU_CNT(1),
.C_PROBE547_MU_CNT(1),
.C_PROBE548_MU_CNT(1),
.C_PROBE549_MU_CNT(1),
.C_PROBE550_MU_CNT(1),
.C_PROBE551_MU_CNT(1),
.C_PROBE552_MU_CNT(1),
.C_PROBE553_MU_CNT(1),
.C_PROBE554_MU_CNT(1),
.C_PROBE555_MU_CNT(1),
.C_PROBE556_MU_CNT(1),
.C_PROBE557_MU_CNT(1),
.C_PROBE558_MU_CNT(1),
.C_PROBE559_MU_CNT(1),
.C_PROBE560_MU_CNT(1),
.C_PROBE561_MU_CNT(1),
.C_PROBE562_MU_CNT(1),
.C_PROBE563_MU_CNT(1),
.C_PROBE564_MU_CNT(1),
.C_PROBE565_MU_CNT(1),
.C_PROBE566_MU_CNT(1),
.C_PROBE567_MU_CNT(1),
.C_PROBE568_MU_CNT(1),
.C_PROBE569_MU_CNT(1),
.C_PROBE570_MU_CNT(1),
.C_PROBE571_MU_CNT(1),
.C_PROBE572_MU_CNT(1),
.C_PROBE573_MU_CNT(1),
.C_PROBE574_MU_CNT(1),
.C_PROBE575_MU_CNT(1),
.C_PROBE576_MU_CNT(1),
.C_PROBE577_MU_CNT(1),
.C_PROBE578_MU_CNT(1),
.C_PROBE579_MU_CNT(1),
.C_PROBE580_MU_CNT(1),
.C_PROBE581_MU_CNT(1),
.C_PROBE582_MU_CNT(1),
.C_PROBE583_MU_CNT(1),
.C_PROBE584_MU_CNT(1),
.C_PROBE585_MU_CNT(1),
.C_PROBE586_MU_CNT(1),
.C_PROBE587_MU_CNT(1),
.C_PROBE588_MU_CNT(1),
.C_PROBE589_MU_CNT(1),
.C_PROBE590_MU_CNT(1),
.C_PROBE591_MU_CNT(1),
.C_PROBE592_MU_CNT(1),
.C_PROBE593_MU_CNT(1),
.C_PROBE594_MU_CNT(1),
.C_PROBE595_MU_CNT(1),
.C_PROBE596_MU_CNT(1),
.C_PROBE597_MU_CNT(1),
.C_PROBE598_MU_CNT(1),
.C_PROBE599_MU_CNT(1),
.C_PROBE600_MU_CNT(1),
.C_PROBE601_MU_CNT(1),
.C_PROBE602_MU_CNT(1),
.C_PROBE603_MU_CNT(1),
.C_PROBE604_MU_CNT(1),
.C_PROBE605_MU_CNT(1),
.C_PROBE606_MU_CNT(1),
.C_PROBE607_MU_CNT(1),
.C_PROBE608_MU_CNT(1),
.C_PROBE609_MU_CNT(1),
.C_PROBE610_MU_CNT(1),
.C_PROBE611_MU_CNT(1),
.C_PROBE612_MU_CNT(1),
.C_PROBE613_MU_CNT(1),
.C_PROBE614_MU_CNT(1),
.C_PROBE615_MU_CNT(1),
.C_PROBE616_MU_CNT(1),
.C_PROBE617_MU_CNT(1),
.C_PROBE618_MU_CNT(1),
.C_PROBE619_MU_CNT(1),
.C_PROBE620_MU_CNT(1),
.C_PROBE621_MU_CNT(1),
.C_PROBE622_MU_CNT(1),
.C_PROBE623_MU_CNT(1),
.C_PROBE624_MU_CNT(1),
.C_PROBE625_MU_CNT(1),
.C_PROBE626_MU_CNT(1),
.C_PROBE627_MU_CNT(1),
.C_PROBE628_MU_CNT(1),
.C_PROBE629_MU_CNT(1),
.C_PROBE630_MU_CNT(1),
.C_PROBE631_MU_CNT(1),
.C_PROBE632_MU_CNT(1),
.C_PROBE633_MU_CNT(1),
.C_PROBE634_MU_CNT(1),
.C_PROBE635_MU_CNT(1),
.C_PROBE636_MU_CNT(1),
.C_PROBE637_MU_CNT(1),
.C_PROBE638_MU_CNT(1),
.C_PROBE639_MU_CNT(1),
.C_PROBE640_MU_CNT(1),
.C_PROBE641_MU_CNT(1),
.C_PROBE642_MU_CNT(1),
.C_PROBE643_MU_CNT(1),
.C_PROBE644_MU_CNT(1),
.C_PROBE645_MU_CNT(1),
.C_PROBE646_MU_CNT(1),
.C_PROBE647_MU_CNT(1),
.C_PROBE648_MU_CNT(1),
.C_PROBE649_MU_CNT(1),
.C_PROBE650_MU_CNT(1),
.C_PROBE651_MU_CNT(1),
.C_PROBE652_MU_CNT(1),
.C_PROBE653_MU_CNT(1),
.C_PROBE654_MU_CNT(1),
.C_PROBE655_MU_CNT(1),
.C_PROBE656_MU_CNT(1),
.C_PROBE657_MU_CNT(1),
.C_PROBE658_MU_CNT(1),
.C_PROBE659_MU_CNT(1),
.C_PROBE660_MU_CNT(1),
.C_PROBE661_MU_CNT(1),
.C_PROBE662_MU_CNT(1),
.C_PROBE663_MU_CNT(1),
.C_PROBE664_MU_CNT(1),
.C_PROBE665_MU_CNT(1),
.C_PROBE666_MU_CNT(1),
.C_PROBE667_MU_CNT(1),
.C_PROBE668_MU_CNT(1),
.C_PROBE669_MU_CNT(1),
.C_PROBE670_MU_CNT(1),
.C_PROBE671_MU_CNT(1),
.C_PROBE672_MU_CNT(1),
.C_PROBE673_MU_CNT(1),
.C_PROBE674_MU_CNT(1),
.C_PROBE675_MU_CNT(1),
.C_PROBE676_MU_CNT(1),
.C_PROBE677_MU_CNT(1),
.C_PROBE678_MU_CNT(1),
.C_PROBE679_MU_CNT(1),
.C_PROBE680_MU_CNT(1),
.C_PROBE681_MU_CNT(1),
.C_PROBE682_MU_CNT(1),
.C_PROBE683_MU_CNT(1),
.C_PROBE684_MU_CNT(1),
.C_PROBE685_MU_CNT(1),
.C_PROBE686_MU_CNT(1),
.C_PROBE687_MU_CNT(1),
.C_PROBE688_MU_CNT(1),
.C_PROBE689_MU_CNT(1),
.C_PROBE690_MU_CNT(1),
.C_PROBE691_MU_CNT(1),
.C_PROBE692_MU_CNT(1),
.C_PROBE693_MU_CNT(1),
.C_PROBE694_MU_CNT(1),
.C_PROBE695_MU_CNT(1),
.C_PROBE696_MU_CNT(1),
.C_PROBE697_MU_CNT(1),
.C_PROBE698_MU_CNT(1),
.C_PROBE699_MU_CNT(1),
.C_PROBE700_MU_CNT(1),
.C_PROBE701_MU_CNT(1),
.C_PROBE702_MU_CNT(1),
.C_PROBE703_MU_CNT(1),
.C_PROBE704_MU_CNT(1),
.C_PROBE705_MU_CNT(1),
.C_PROBE706_MU_CNT(1),
.C_PROBE707_MU_CNT(1),
.C_PROBE708_MU_CNT(1),
.C_PROBE709_MU_CNT(1),
.C_PROBE710_MU_CNT(1),
.C_PROBE711_MU_CNT(1),
.C_PROBE712_MU_CNT(1),
.C_PROBE713_MU_CNT(1),
.C_PROBE714_MU_CNT(1),
.C_PROBE715_MU_CNT(1),
.C_PROBE716_MU_CNT(1),
.C_PROBE717_MU_CNT(1),
.C_PROBE718_MU_CNT(1),
.C_PROBE719_MU_CNT(1),
.C_PROBE720_MU_CNT(1),
.C_PROBE721_MU_CNT(1),
.C_PROBE722_MU_CNT(1),
.C_PROBE723_MU_CNT(1),
.C_PROBE724_MU_CNT(1),
.C_PROBE725_MU_CNT(1),
.C_PROBE726_MU_CNT(1),
.C_PROBE727_MU_CNT(1),
.C_PROBE728_MU_CNT(1),
.C_PROBE729_MU_CNT(1),
.C_PROBE730_MU_CNT(1),
.C_PROBE731_MU_CNT(1),
.C_PROBE732_MU_CNT(1),
.C_PROBE733_MU_CNT(1),
.C_PROBE734_MU_CNT(1),
.C_PROBE735_MU_CNT(1),
.C_PROBE736_MU_CNT(1),
.C_PROBE737_MU_CNT(1),
.C_PROBE738_MU_CNT(1),
.C_PROBE739_MU_CNT(1),
.C_PROBE740_MU_CNT(1),
.C_PROBE741_MU_CNT(1),
.C_PROBE742_MU_CNT(1),
.C_PROBE743_MU_CNT(1),
.C_PROBE744_MU_CNT(1),
.C_PROBE745_MU_CNT(1),
.C_PROBE746_MU_CNT(1),
.C_PROBE747_MU_CNT(1),
.C_PROBE748_MU_CNT(1),
.C_PROBE749_MU_CNT(1),
.C_PROBE750_MU_CNT(1),
.C_PROBE751_MU_CNT(1),
.C_PROBE752_MU_CNT(1),
.C_PROBE753_MU_CNT(1),
.C_PROBE754_MU_CNT(1),
.C_PROBE755_MU_CNT(1),
.C_PROBE756_MU_CNT(1),
.C_PROBE757_MU_CNT(1),
.C_PROBE758_MU_CNT(1),
.C_PROBE759_MU_CNT(1),
.C_PROBE760_MU_CNT(1),
.C_PROBE761_MU_CNT(1),
.C_PROBE762_MU_CNT(1),
.C_PROBE763_MU_CNT(1),
.C_PROBE764_MU_CNT(1),
.C_PROBE765_MU_CNT(1),
.C_PROBE766_MU_CNT(1),
.C_PROBE767_MU_CNT(1),
.C_PROBE768_MU_CNT(1),
.C_PROBE769_MU_CNT(1),
.C_PROBE770_MU_CNT(1),
.C_PROBE771_MU_CNT(1),
.C_PROBE772_MU_CNT(1),
.C_PROBE773_MU_CNT(1),
.C_PROBE774_MU_CNT(1),
.C_PROBE775_MU_CNT(1),
.C_PROBE776_MU_CNT(1),
.C_PROBE777_MU_CNT(1),
.C_PROBE778_MU_CNT(1),
.C_PROBE779_MU_CNT(1),
.C_PROBE780_MU_CNT(1),
.C_PROBE781_MU_CNT(1),
.C_PROBE782_MU_CNT(1),
.C_PROBE783_MU_CNT(1),
.C_PROBE784_MU_CNT(1),
.C_PROBE785_MU_CNT(1),
.C_PROBE786_MU_CNT(1),
.C_PROBE787_MU_CNT(1),
.C_PROBE788_MU_CNT(1),
.C_PROBE789_MU_CNT(1),
.C_PROBE790_MU_CNT(1),
.C_PROBE791_MU_CNT(1),
.C_PROBE792_MU_CNT(1),
.C_PROBE793_MU_CNT(1),
.C_PROBE794_MU_CNT(1),
.C_PROBE795_MU_CNT(1),
.C_PROBE796_MU_CNT(1),
.C_PROBE797_MU_CNT(1),
.C_PROBE798_MU_CNT(1),
.C_PROBE799_MU_CNT(1),
.C_PROBE800_MU_CNT(1),
.C_PROBE801_MU_CNT(1),
.C_PROBE802_MU_CNT(1),
.C_PROBE803_MU_CNT(1),
.C_PROBE804_MU_CNT(1),
.C_PROBE805_MU_CNT(1),
.C_PROBE806_MU_CNT(1),
.C_PROBE807_MU_CNT(1),
.C_PROBE808_MU_CNT(1),
.C_PROBE809_MU_CNT(1),
.C_PROBE810_MU_CNT(1),
.C_PROBE811_MU_CNT(1),
.C_PROBE812_MU_CNT(1),
.C_PROBE813_MU_CNT(1),
.C_PROBE814_MU_CNT(1),
.C_PROBE815_MU_CNT(1),
.C_PROBE816_MU_CNT(1),
.C_PROBE817_MU_CNT(1),
.C_PROBE818_MU_CNT(1),
.C_PROBE819_MU_CNT(1),
.C_PROBE820_MU_CNT(1),
.C_PROBE821_MU_CNT(1),
.C_PROBE822_MU_CNT(1),
.C_PROBE823_MU_CNT(1),
.C_PROBE824_MU_CNT(1),
.C_PROBE825_MU_CNT(1),
.C_PROBE826_MU_CNT(1),
.C_PROBE827_MU_CNT(1),
.C_PROBE828_MU_CNT(1),
.C_PROBE829_MU_CNT(1),
.C_PROBE830_MU_CNT(1),
.C_PROBE831_MU_CNT(1),
.C_PROBE832_MU_CNT(1),
.C_PROBE833_MU_CNT(1),
.C_PROBE834_MU_CNT(1),
.C_PROBE835_MU_CNT(1),
.C_PROBE836_MU_CNT(1),
.C_PROBE837_MU_CNT(1),
.C_PROBE838_MU_CNT(1),
.C_PROBE839_MU_CNT(1),
.C_PROBE840_MU_CNT(1),
.C_PROBE841_MU_CNT(1),
.C_PROBE842_MU_CNT(1),
.C_PROBE843_MU_CNT(1),
.C_PROBE844_MU_CNT(1),
.C_PROBE845_MU_CNT(1),
.C_PROBE846_MU_CNT(1),
.C_PROBE847_MU_CNT(1),
.C_PROBE848_MU_CNT(1),
.C_PROBE849_MU_CNT(1),
.C_PROBE850_MU_CNT(1),
.C_PROBE851_MU_CNT(1),
.C_PROBE852_MU_CNT(1),
.C_PROBE853_MU_CNT(1),
.C_PROBE854_MU_CNT(1),
.C_PROBE855_MU_CNT(1),
.C_PROBE856_MU_CNT(1),
.C_PROBE857_MU_CNT(1),
.C_PROBE858_MU_CNT(1),
.C_PROBE859_MU_CNT(1),
.C_PROBE860_MU_CNT(1),
.C_PROBE861_MU_CNT(1),
.C_PROBE862_MU_CNT(1),
.C_PROBE863_MU_CNT(1),
.C_PROBE864_MU_CNT(1),
.C_PROBE865_MU_CNT(1),
.C_PROBE866_MU_CNT(1),
.C_PROBE867_MU_CNT(1),
.C_PROBE868_MU_CNT(1),
.C_PROBE869_MU_CNT(1),
.C_PROBE870_MU_CNT(1),
.C_PROBE871_MU_CNT(1),
.C_PROBE872_MU_CNT(1),
.C_PROBE873_MU_CNT(1),
.C_PROBE874_MU_CNT(1),
.C_PROBE875_MU_CNT(1),
.C_PROBE876_MU_CNT(1),
.C_PROBE877_MU_CNT(1),
.C_PROBE878_MU_CNT(1),
.C_PROBE879_MU_CNT(1),
.C_PROBE880_MU_CNT(1),
.C_PROBE881_MU_CNT(1),
.C_PROBE882_MU_CNT(1),
.C_PROBE883_MU_CNT(1),
.C_PROBE884_MU_CNT(1),
.C_PROBE885_MU_CNT(1),
.C_PROBE886_MU_CNT(1),
.C_PROBE887_MU_CNT(1),
.C_PROBE888_MU_CNT(1),
.C_PROBE889_MU_CNT(1),
.C_PROBE890_MU_CNT(1),
.C_PROBE891_MU_CNT(1),
.C_PROBE892_MU_CNT(1),
.C_PROBE893_MU_CNT(1),
.C_PROBE894_MU_CNT(1),
.C_PROBE895_MU_CNT(1),
.C_PROBE896_MU_CNT(1),
.C_PROBE897_MU_CNT(1),
.C_PROBE898_MU_CNT(1),
.C_PROBE899_MU_CNT(1),
.C_PROBE900_MU_CNT(1),
.C_PROBE901_MU_CNT(1),
.C_PROBE902_MU_CNT(1),
.C_PROBE903_MU_CNT(1),
.C_PROBE904_MU_CNT(1),
.C_PROBE905_MU_CNT(1),
.C_PROBE906_MU_CNT(1),
.C_PROBE907_MU_CNT(1),
.C_PROBE908_MU_CNT(1),
.C_PROBE909_MU_CNT(1),
.C_PROBE910_MU_CNT(1),
.C_PROBE911_MU_CNT(1),
.C_PROBE912_MU_CNT(1),
.C_PROBE913_MU_CNT(1),
.C_PROBE914_MU_CNT(1),
.C_PROBE915_MU_CNT(1),
.C_PROBE916_MU_CNT(1),
.C_PROBE917_MU_CNT(1),
.C_PROBE918_MU_CNT(1),
.C_PROBE919_MU_CNT(1),
.C_PROBE920_MU_CNT(1),
.C_PROBE921_MU_CNT(1),
.C_PROBE922_MU_CNT(1),
.C_PROBE923_MU_CNT(1),
.C_PROBE924_MU_CNT(1),
.C_PROBE925_MU_CNT(1),
.C_PROBE926_MU_CNT(1),
.C_PROBE927_MU_CNT(1),
.C_PROBE928_MU_CNT(1),
.C_PROBE929_MU_CNT(1),
.C_PROBE930_MU_CNT(1),
.C_PROBE931_MU_CNT(1),
.C_PROBE932_MU_CNT(1),
.C_PROBE933_MU_CNT(1),
.C_PROBE934_MU_CNT(1),
.C_PROBE935_MU_CNT(1),
.C_PROBE936_MU_CNT(1),
.C_PROBE937_MU_CNT(1),
.C_PROBE938_MU_CNT(1),
.C_PROBE939_MU_CNT(1),
.C_PROBE940_MU_CNT(1),
.C_PROBE941_MU_CNT(1),
.C_PROBE942_MU_CNT(1),
.C_PROBE943_MU_CNT(1),
.C_PROBE944_MU_CNT(1),
.C_PROBE945_MU_CNT(1),
.C_PROBE946_MU_CNT(1),
.C_PROBE947_MU_CNT(1),
.C_PROBE948_MU_CNT(1),
.C_PROBE949_MU_CNT(1),
.C_PROBE950_MU_CNT(1),
.C_PROBE951_MU_CNT(1),
.C_PROBE952_MU_CNT(1),
.C_PROBE953_MU_CNT(1),
.C_PROBE954_MU_CNT(1),
.C_PROBE955_MU_CNT(1),
.C_PROBE956_MU_CNT(1),
.C_PROBE957_MU_CNT(1),
.C_PROBE958_MU_CNT(1),
.C_PROBE959_MU_CNT(1),
.C_PROBE960_MU_CNT(1),
.C_PROBE961_MU_CNT(1),
.C_PROBE962_MU_CNT(1),
.C_PROBE963_MU_CNT(1),
.C_PROBE964_MU_CNT(1),
.C_PROBE965_MU_CNT(1),
.C_PROBE966_MU_CNT(1),
.C_PROBE967_MU_CNT(1),
.C_PROBE968_MU_CNT(1),
.C_PROBE969_MU_CNT(1),
.C_PROBE970_MU_CNT(1),
.C_PROBE971_MU_CNT(1),
.C_PROBE972_MU_CNT(1),
.C_PROBE973_MU_CNT(1),
.C_PROBE974_MU_CNT(1),
.C_PROBE975_MU_CNT(1),
.C_PROBE976_MU_CNT(1),
.C_PROBE977_MU_CNT(1),
.C_PROBE978_MU_CNT(1),
.C_PROBE979_MU_CNT(1),
.C_PROBE980_MU_CNT(1),
.C_PROBE981_MU_CNT(1),
.C_PROBE982_MU_CNT(1),
.C_PROBE983_MU_CNT(1),
.C_PROBE984_MU_CNT(1),
.C_PROBE985_MU_CNT(1),
.C_PROBE986_MU_CNT(1),
.C_PROBE987_MU_CNT(1),
.C_PROBE988_MU_CNT(1),
.C_PROBE989_MU_CNT(1),
.C_PROBE990_MU_CNT(1),
.C_PROBE991_MU_CNT(1),
.C_PROBE992_MU_CNT(1),
.C_PROBE993_MU_CNT(1),
.C_PROBE994_MU_CNT(1),
.C_PROBE995_MU_CNT(1),
.C_PROBE996_MU_CNT(1),
.C_PROBE997_MU_CNT(1),
.C_PROBE998_MU_CNT(1),
.C_PROBE999_MU_CNT(1),
.C_PROBE1000_MU_CNT(1),
.C_PROBE1001_MU_CNT(1),
.C_PROBE1002_MU_CNT(1),
.C_PROBE1003_MU_CNT(1),
.C_PROBE1004_MU_CNT(1),
.C_PROBE1005_MU_CNT(1),
.C_PROBE1006_MU_CNT(1),
.C_PROBE1007_MU_CNT(1),
.C_PROBE1008_MU_CNT(1),
.C_PROBE1009_MU_CNT(1),
.C_PROBE1010_MU_CNT(1),
.C_PROBE1011_MU_CNT(1),
.C_PROBE1012_MU_CNT(1),
.C_PROBE1013_MU_CNT(1),
.C_PROBE1014_MU_CNT(1),
.C_PROBE1015_MU_CNT(1),
.C_PROBE1016_MU_CNT(1),
.C_PROBE1017_MU_CNT(1),
.C_PROBE1018_MU_CNT(1),
.C_PROBE1019_MU_CNT(1),
.C_PROBE1020_MU_CNT(1),
.C_PROBE1021_MU_CNT(1),
.C_PROBE1022_MU_CNT(1),
.C_PROBE1023_MU_CNT(1)
) inst (
.clk(clk),
.sl_iport0(sl_iport0),
.sl_oport0(sl_oport0),
.trig_out(trig_out),
.trig_out_ack(trig_out_ack),
.trig_in(trig_in),
.trig_in_ack(trig_in_ack),
.probe0(probe0),
.probe1(0),
.probe2(0),
.probe3(0),
.probe4(0),
.probe5(0),
.probe6(0),
.probe7(0),
.probe8(0),
.probe9(0),
.probe10(0),
.probe11(0),
.probe12(0),
.probe13(0),
.probe14(0),
.probe15(0),
.probe16(0),
.probe17(0),
.probe18(0),
.probe19(0),
.probe20(0),
.probe21(0),
.probe22(0),
.probe23(0),
.probe24(0),
.probe25(0),
.probe26(0),
.probe27(0),
.probe28(0),
.probe29(0),
.probe30(0),
.probe31(0),
.probe32(0),
.probe33(0),
.probe34(0),
.probe35(0),
.probe36(0),
.probe37(0),
.probe38(0),
.probe39(0),
.probe40(0),
.probe41(0),
.probe42(0),
.probe43(0),
.probe44(0),
.probe45(0),
.probe46(0),
.probe47(0),
.probe48(0),
.probe49(0),
.probe50(0),
.probe51(0),
.probe52(0),
.probe53(0),
.probe54(0),
.probe55(0),
.probe56(0),
.probe57(0),
.probe58(0),
.probe59(0),
.probe60(0),
.probe61(0),
.probe62(0),
.probe63(0),
.probe64(0),
.probe65(0),
.probe66(0),
.probe67(0),
.probe68(0),
.probe69(0),
.probe70(0),
.probe71(0),
.probe72(0),
.probe73(0),
.probe74(0),
.probe75(0),
.probe76(0),
.probe77(0),
.probe78(0),
.probe79(0),
.probe80(0),
.probe81(0),
.probe82(0),
.probe83(0),
.probe84(0),
.probe85(0),
.probe86(0),
.probe87(0),
.probe88(0),
.probe89(0),
.probe90(0),
.probe91(0),
.probe92(0),
.probe93(0),
.probe94(0),
.probe95(0),
.probe96(0),
.probe97(0),
.probe98(0),
.probe99(0),
.probe100(0),
.probe101(0),
.probe102(0),
.probe103(0),
.probe104(0),
.probe105(0),
.probe106(0),
.probe107(0),
.probe108(0),
.probe109(0),
.probe110(0),
.probe111(0),
.probe112(0),
.probe113(0),
.probe114(0),
.probe115(0),
.probe116(0),
.probe117(0),
.probe118(0),
.probe119(0),
.probe120(0),
.probe121(0),
.probe122(0),
.probe123(0),
.probe124(0),
.probe125(0),
.probe126(0),
.probe127(0),
.probe128(0),
.probe129(0),
.probe130(0),
.probe131(0),
.probe132(0),
.probe133(0),
.probe134(0),
.probe135(0),
.probe136(0),
.probe137(0),
.probe138(0),
.probe139(0),
.probe140(0),
.probe141(0),
.probe142(0),
.probe143(0),
.probe144(0),
.probe145(0),
.probe146(0),
.probe147(0),
.probe148(0),
.probe149(0),
.probe150(0),
.probe151(0),
.probe152(0),
.probe153(0),
.probe154(0),
.probe155(0),
.probe156(0),
.probe157(0),
.probe158(0),
.probe159(0),
.probe160(0),
.probe161(0),
.probe162(0),
.probe163(0),
.probe164(0),
.probe165(0),
.probe166(0),
.probe167(0),
.probe168(0),
.probe169(0),
.probe170(0),
.probe171(0),
.probe172(0),
.probe173(0),
.probe174(0),
.probe175(0),
.probe176(0),
.probe177(0),
.probe178(0),
.probe179(0),
.probe180(0),
.probe181(0),
.probe182(0),
.probe183(0),
.probe184(0),
.probe185(0),
.probe186(0),
.probe187(0),
.probe188(0),
.probe189(0),
.probe190(0),
.probe191(0),
.probe192(0),
.probe193(0),
.probe194(0),
.probe195(0),
.probe196(0),
.probe197(0),
.probe198(0),
.probe199(0),
.probe200(0),
.probe201(0),
.probe202(0),
.probe203(0),
.probe204(0),
.probe205(0),
.probe206(0),
.probe207(0),
.probe208(0),
.probe209(0),
.probe210(0),
.probe211(0),
.probe212(0),
.probe213(0),
.probe214(0),
.probe215(0),
.probe216(0),
.probe217(0),
.probe218(0),
.probe219(0),
.probe220(0),
.probe221(0),
.probe222(0),
.probe223(0),
.probe224(0),
.probe225(0),
.probe226(0),
.probe227(0),
.probe228(0),
.probe229(0),
.probe230(0),
.probe231(0),
.probe232(0),
.probe233(0),
.probe234(0),
.probe235(0),
.probe236(0),
.probe237(0),
.probe238(0),
.probe239(0),
.probe240(0),
.probe241(0),
.probe242(0),
.probe243(0),
.probe244(0),
.probe245(0),
.probe246(0),
.probe247(0),
.probe248(0),
.probe249(0),
.probe250(0),
.probe251(0),
.probe252(0),
.probe253(0),
.probe254(0),
.probe255(0),
.probe256(0),
.probe257(0),
.probe258(0),
.probe259(0),
.probe260(0),
.probe261(0),
.probe262(0),
.probe263(0),
.probe264(0),
.probe265(0),
.probe266(0),
.probe267(0),
.probe268(0),
.probe269(0),
.probe270(0),
.probe271(0),
.probe272(0),
.probe273(0),
.probe274(0),
.probe275(0),
.probe276(0),
.probe277(0),
.probe278(0),
.probe279(0),
.probe280(0),
.probe281(0),
.probe282(0),
.probe283(0),
.probe284(0),
.probe285(0),
.probe286(0),
.probe287(0),
.probe288(0),
.probe289(0),
.probe290(0),
.probe291(0),
.probe292(0),
.probe293(0),
.probe294(0),
.probe295(0),
.probe296(0),
.probe297(0),
.probe298(0),
.probe299(0),
.probe300(0),
.probe301(0),
.probe302(0),
.probe303(0),
.probe304(0),
.probe305(0),
.probe306(0),
.probe307(0),
.probe308(0),
.probe309(0),
.probe310(0),
.probe311(0),
.probe312(0),
.probe313(0),
.probe314(0),
.probe315(0),
.probe316(0),
.probe317(0),
.probe318(0),
.probe319(0),
.probe320(0),
.probe321(0),
.probe322(0),
.probe323(0),
.probe324(0),
.probe325(0),
.probe326(0),
.probe327(0),
.probe328(0),
.probe329(0),
.probe330(0),
.probe331(0),
.probe332(0),
.probe333(0),
.probe334(0),
.probe335(0),
.probe336(0),
.probe337(0),
.probe338(0),
.probe339(0),
.probe340(0),
.probe341(0),
.probe342(0),
.probe343(0),
.probe344(0),
.probe345(0),
.probe346(0),
.probe347(0),
.probe348(0),
.probe349(0),
.probe350(0),
.probe351(0),
.probe352(0),
.probe353(0),
.probe354(0),
.probe355(0),
.probe356(0),
.probe357(0),
.probe358(0),
.probe359(0),
.probe360(0),
.probe361(0),
.probe362(0),
.probe363(0),
.probe364(0),
.probe365(0),
.probe366(0),
.probe367(0),
.probe368(0),
.probe369(0),
.probe370(0),
.probe371(0),
.probe372(0),
.probe373(0),
.probe374(0),
.probe375(0),
.probe376(0),
.probe377(0),
.probe378(0),
.probe379(0),
.probe380(0),
.probe381(0),
.probe382(0),
.probe383(0),
.probe384(0),
.probe385(0),
.probe386(0),
.probe387(0),
.probe388(0),
.probe389(0),
.probe390(0),
.probe391(0),
.probe392(0),
.probe393(0),
.probe394(0),
.probe395(0),
.probe396(0),
.probe397(0),
.probe398(0),
.probe399(0),
.probe400(0),
.probe401(0),
.probe402(0),
.probe403(0),
.probe404(0),
.probe405(0),
.probe406(0),
.probe407(0),
.probe408(0),
.probe409(0),
.probe410(0),
.probe411(0),
.probe412(0),
.probe413(0),
.probe414(0),
.probe415(0),
.probe416(0),
.probe417(0),
.probe418(0),
.probe419(0),
.probe420(0),
.probe421(0),
.probe422(0),
.probe423(0),
.probe424(0),
.probe425(0),
.probe426(0),
.probe427(0),
.probe428(0),
.probe429(0),
.probe430(0),
.probe431(0),
.probe432(0),
.probe433(0),
.probe434(0),
.probe435(0),
.probe436(0),
.probe437(0),
.probe438(0),
.probe439(0),
.probe440(0),
.probe441(0),
.probe442(0),
.probe443(0),
.probe444(0),
.probe445(0),
.probe446(0),
.probe447(0),
.probe448(0),
.probe449(0),
.probe450(0),
.probe451(0),
.probe452(0),
.probe453(0),
.probe454(0),
.probe455(0),
.probe456(0),
.probe457(0),
.probe458(0),
.probe459(0),
.probe460(0),
.probe461(0),
.probe462(0),
.probe463(0),
.probe464(0),
.probe465(0),
.probe466(0),
.probe467(0),
.probe468(0),
.probe469(0),
.probe470(0),
.probe471(0),
.probe472(0),
.probe473(0),
.probe474(0),
.probe475(0),
.probe476(0),
.probe477(0),
.probe478(0),
.probe479(0),
.probe480(0),
.probe481(0),
.probe482(0),
.probe483(0),
.probe484(0),
.probe485(0),
.probe486(0),
.probe487(0),
.probe488(0),
.probe489(0),
.probe490(0),
.probe491(0),
.probe492(0),
.probe493(0),
.probe494(0),
.probe495(0),
.probe496(0),
.probe497(0),
.probe498(0),
.probe499(0),
.probe500(0),
.probe501(0),
.probe502(0),
.probe503(0),
.probe504(0),
.probe505(0),
.probe506(0),
.probe507(0),
.probe508(0),
.probe509(0),
.probe510(0),
.probe511(0),
.probe512(0),
.probe513(0),
.probe514(0),
.probe515(0),
.probe516(0),
.probe517(0),
.probe518(0),
.probe519(0),
.probe520(0),
.probe521(0),
.probe522(0),
.probe523(0),
.probe524(0),
.probe525(0),
.probe526(0),
.probe527(0),
.probe528(0),
.probe529(0),
.probe530(0),
.probe531(0),
.probe532(0),
.probe533(0),
.probe534(0),
.probe535(0),
.probe536(0),
.probe537(0),
.probe538(0),
.probe539(0),
.probe540(0),
.probe541(0),
.probe542(0),
.probe543(0),
.probe544(0),
.probe545(0),
.probe546(0),
.probe547(0),
.probe548(0),
.probe549(0),
.probe550(0),
.probe551(0),
.probe552(0),
.probe553(0),
.probe554(0),
.probe555(0),
.probe556(0),
.probe557(0),
.probe558(0),
.probe559(0),
.probe560(0),
.probe561(0),
.probe562(0),
.probe563(0),
.probe564(0),
.probe565(0),
.probe566(0),
.probe567(0),
.probe568(0),
.probe569(0),
.probe570(0),
.probe571(0),
.probe572(0),
.probe573(0),
.probe574(0),
.probe575(0),
.probe576(0),
.probe577(0),
.probe578(0),
.probe579(0),
.probe580(0),
.probe581(0),
.probe582(0),
.probe583(0),
.probe584(0),
.probe585(0),
.probe586(0),
.probe587(0),
.probe588(0),
.probe589(0),
.probe590(0),
.probe591(0),
.probe592(0),
.probe593(0),
.probe594(0),
.probe595(0),
.probe596(0),
.probe597(0),
.probe598(0),
.probe599(0),
.probe600(0),
.probe601(0),
.probe602(0),
.probe603(0),
.probe604(0),
.probe605(0),
.probe606(0),
.probe607(0),
.probe608(0),
.probe609(0),
.probe610(0),
.probe611(0),
.probe612(0),
.probe613(0),
.probe614(0),
.probe615(0),
.probe616(0),
.probe617(0),
.probe618(0),
.probe619(0),
.probe620(0),
.probe621(0),
.probe622(0),
.probe623(0),
.probe624(0),
.probe625(0),
.probe626(0),
.probe627(0),
.probe628(0),
.probe629(0),
.probe630(0),
.probe631(0),
.probe632(0),
.probe633(0),
.probe634(0),
.probe635(0),
.probe636(0),
.probe637(0),
.probe638(0),
.probe639(0),
.probe640(0),
.probe641(0),
.probe642(0),
.probe643(0),
.probe644(0),
.probe645(0),
.probe646(0),
.probe647(0),
.probe648(0),
.probe649(0),
.probe650(0),
.probe651(0),
.probe652(0),
.probe653(0),
.probe654(0),
.probe655(0),
.probe656(0),
.probe657(0),
.probe658(0),
.probe659(0),
.probe660(0),
.probe661(0),
.probe662(0),
.probe663(0),
.probe664(0),
.probe665(0),
.probe666(0),
.probe667(0),
.probe668(0),
.probe669(0),
.probe670(0),
.probe671(0),
.probe672(0),
.probe673(0),
.probe674(0),
.probe675(0),
.probe676(0),
.probe677(0),
.probe678(0),
.probe679(0),
.probe680(0),
.probe681(0),
.probe682(0),
.probe683(0),
.probe684(0),
.probe685(0),
.probe686(0),
.probe687(0),
.probe688(0),
.probe689(0),
.probe690(0),
.probe691(0),
.probe692(0),
.probe693(0),
.probe694(0),
.probe695(0),
.probe696(0),
.probe697(0),
.probe698(0),
.probe699(0),
.probe700(0),
.probe701(0),
.probe702(0),
.probe703(0),
.probe704(0),
.probe705(0),
.probe706(0),
.probe707(0),
.probe708(0),
.probe709(0),
.probe710(0),
.probe711(0),
.probe712(0),
.probe713(0),
.probe714(0),
.probe715(0),
.probe716(0),
.probe717(0),
.probe718(0),
.probe719(0),
.probe720(0),
.probe721(0),
.probe722(0),
.probe723(0),
.probe724(0),
.probe725(0),
.probe726(0),
.probe727(0),
.probe728(0),
.probe729(0),
.probe730(0),
.probe731(0),
.probe732(0),
.probe733(0),
.probe734(0),
.probe735(0),
.probe736(0),
.probe737(0),
.probe738(0),
.probe739(0),
.probe740(0),
.probe741(0),
.probe742(0),
.probe743(0),
.probe744(0),
.probe745(0),
.probe746(0),
.probe747(0),
.probe748(0),
.probe749(0),
.probe750(0),
.probe751(0),
.probe752(0),
.probe753(0),
.probe754(0),
.probe755(0),
.probe756(0),
.probe757(0),
.probe758(0),
.probe759(0),
.probe760(0),
.probe761(0),
.probe762(0),
.probe763(0),
.probe764(0),
.probe765(0),
.probe766(0),
.probe767(0),
.probe768(0),
.probe769(0),
.probe770(0),
.probe771(0),
.probe772(0),
.probe773(0),
.probe774(0),
.probe775(0),
.probe776(0),
.probe777(0),
.probe778(0),
.probe779(0),
.probe780(0),
.probe781(0),
.probe782(0),
.probe783(0),
.probe784(0),
.probe785(0),
.probe786(0),
.probe787(0),
.probe788(0),
.probe789(0),
.probe790(0),
.probe791(0),
.probe792(0),
.probe793(0),
.probe794(0),
.probe795(0),
.probe796(0),
.probe797(0),
.probe798(0),
.probe799(0),
.probe800(0),
.probe801(0),
.probe802(0),
.probe803(0),
.probe804(0),
.probe805(0),
.probe806(0),
.probe807(0),
.probe808(0),
.probe809(0),
.probe810(0),
.probe811(0),
.probe812(0),
.probe813(0),
.probe814(0),
.probe815(0),
.probe816(0),
.probe817(0),
.probe818(0),
.probe819(0),
.probe820(0),
.probe821(0),
.probe822(0),
.probe823(0),
.probe824(0),
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.probe828(0),
.probe829(0),
.probe830(0),
.probe831(0),
.probe832(0),
.probe833(0),
.probe834(0),
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.probe838(0),
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.probe842(0),
.probe843(0),
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.probe845(0),
.probe846(0),
.probe847(0),
.probe848(0),
.probe849(0),
.probe850(0),
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.probe853(0),
.probe854(0),
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.probe856(0),
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.probe863(0),
.probe864(0),
.probe865(0),
.probe866(0),
.probe867(0),
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.probe869(0),
.probe870(0),
.probe871(0),
.probe872(0),
.probe873(0),
.probe874(0),
.probe875(0),
.probe876(0),
.probe877(0),
.probe878(0),
.probe879(0),
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.probe882(0),
.probe883(0),
.probe884(0),
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.probe887(0),
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.probe889(0),
.probe890(0),
.probe891(0),
.probe892(0),
.probe893(0),
.probe894(0),
.probe895(0),
.probe896(0),
.probe897(0),
.probe898(0),
.probe899(0),
.probe900(0),
.probe901(0),
.probe902(0),
.probe903(0),
.probe904(0),
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.probe906(0),
.probe907(0),
.probe908(0),
.probe909(0),
.probe910(0),
.probe911(0),
.probe912(0),
.probe913(0),
.probe914(0),
.probe915(0),
.probe916(0),
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.probe921(0),
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.probe923(0),
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.probe926(0),
.probe927(0),
.probe928(0),
.probe929(0),
.probe930(0),
.probe931(0),
.probe932(0),
.probe933(0),
.probe934(0),
.probe935(0),
.probe936(0),
.probe937(0),
.probe938(0),
.probe939(0),
.probe940(0),
.probe941(0),
.probe942(0),
.probe943(0),
.probe944(0),
.probe945(0),
.probe946(0),
.probe947(0),
.probe948(0),
.probe949(0),
.probe950(0),
.probe951(0),
.probe952(0),
.probe953(0),
.probe954(0),
.probe955(0),
.probe956(0),
.probe957(0),
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.probe961(0),
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.probe964(0),
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.probe966(0),
.probe967(0),
.probe968(0),
.probe969(0),
.probe970(0),
.probe971(0),
.probe972(0),
.probe973(0),
.probe974(0),
.probe975(0),
.probe976(0),
.probe977(0),
.probe978(0),
.probe979(0),
.probe980(0),
.probe981(0),
.probe982(0),
.probe983(0),
.probe984(0),
.probe985(0),
.probe986(0),
.probe987(0),
.probe988(0),
.probe989(0),
.probe990(0),
.probe991(0),
.probe992(0),
.probe993(0),
.probe994(0),
.probe995(0),
.probe996(0),
.probe997(0),
.probe998(0),
.probe999(0),
.probe1000(0),
.probe1001(0),
.probe1002(0),
.probe1003(0),
.probe1004(0),
.probe1005(0),
.probe1006(0),
.probe1007(0),
.probe1008(0),
.probe1009(0),
.probe1010(0),
.probe1011(0),
.probe1012(0),
.probe1013(0),
.probe1014(0),
.probe1015(0),
.probe1016(0),
.probe1017(0),
.probe1018(0),
.probe1019(0),
.probe1020(0),
.probe1021(0),
.probe1022(0),
.probe1023(0)
)/* synthesis syn_noprune=1 */;
endmodule
|
module Computer_Datapath_FunctionUnit(
output reg [WORD_WIDTH-1:0] FU_out,
output [FLAG_WIDTH-1:0] FLAG_bus_out,
input [WORD_WIDTH-1:0] ADDR_bus_in, DATA_bus_in,
input [CNTRL_WIDTH-1:0] CNTRL_bus_in
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter CNTRL_WIDTH = DR_WIDTH+SB_WIDTH+SA_WIDTH+11;
parameter COUNTER_WIDTH = 4;
parameter FS_WIDTH = 4;
parameter FLAG_WIDTH = 4;
wire [FS_WIDTH-1:0] FS = CNTRL_bus_in[9:6];
wire [WORD_WIDTH-2:0] V_temp = ADDR_bus_in[WORD_WIDTH-2:0]+DATA_bus_in[WORD_WIDTH-2:0];
wire V = V_temp[WORD_WIDTH-2:0];
wire N = FU_out[WORD_WIDTH-1];
wire Z = (!FU_out)?1'b1:1'b0;
reg C;
assign FLAG_bus_out = {V, C, N, Z};
always@(*) begin
case(FS)
4'b0000: {C, FU_out} = ADDR_bus_in; // Move A
4'b0001: {C, FU_out} = ADDR_bus_in+1; // Increment
4'b0010: {C, FU_out} = ADDR_bus_in+DATA_bus_in; // Add
4'b0011: {C, FU_out} = ADDR_bus_in+DATA_bus_in+1; //
4'b0100: {C, FU_out} = ADDR_bus_in+(~DATA_bus_in); //
4'b0101: {C, FU_out} = ADDR_bus_in+(~DATA_bus_in)+1; // Subtraction
4'b0110: {C, FU_out} = ADDR_bus_in-1; // Decrement
4'b0111: {C, FU_out} = ADDR_bus_in; // Move A
4'b1000: {C, FU_out} = ADDR_bus_in&DATA_bus_in; // Bitwize and
4'b1001: {C, FU_out} = ADDR_bus_in|DATA_bus_in; // Bitwize or
4'b1010: {C, FU_out} = ADDR_bus_in^DATA_bus_in; // Bitwize xor
4'b1011: {C, FU_out} = (~ADDR_bus_in); // Bitwize Invert
4'b1100: {C, FU_out} = DATA_bus_in; // Move B
4'b1101: {C, FU_out} = (DATA_bus_in>>1); // Shift Right B
4'b1110: {C, FU_out} = (DATA_bus_in<<1); // Shift Left B
4'b1111: {C, FU_out} = (~DATA_bus_in); // Ivert B
endcase
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2010 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t;
integer value = 19;
initial begin
if (value==1) begin end
else if (value==2) begin end
else if (value==3) begin end
else if (value==4) begin end
else if (value==5) begin end
else if (value==6) begin end
else if (value==7) begin end
else if (value==8) begin end
else if (value==9) begin end
else if (value==10) begin end
else if (value==11) begin end // Warn about this one
else if (value==12) begin end
end
initial begin
unique0 if (value==1) begin end
else if (value==2) begin end
else if (value==3) begin end
else if (value==4) begin end
else if (value==5) begin end
else if (value==6) begin end
else if (value==7) begin end
else if (value==8) begin end
else if (value==9) begin end
else if (value==10) begin end
else if (value==11) begin end // Warn about this one
else if (value==12) begin end
end
endmodule
|
/* A alu module*/
module ALU(inputA, inputB, ALUop, result, zero);
input [31:0] inputA, inputB;
input [2:0] ALUop;
output [31:0] result;
reg [31:0] result;
output zero;
reg zero;
/*whenever input or ALUop changes*/
always @(inputA or inputB or ALUop)
begin
/*it supports AND, OR, ADD, SLT with a zero output*/
case(ALUop)
3'b010: result = inputA + inputB;
3'b110: result = inputA - inputB;
3'b001: result = inputA | inputB;
3'b000: result = inputA & inputB;
3'b111:
begin
if(inputA < inputB)
result = 1;
else
result = 0;
end
endcase
if (inputA == inputB)
zero = 1;
else
zero = 0;
end
endmodule
module ALUTestbench;
reg [31:0] inputA, inputB;
reg [2:0] ALUop;
wire [31:0] result;
wire zero;
ALU UUT(inputA, inputB, ALUop, result, zero);
initial begin
#20 inputA = 5;
inputB = 6;
ALUop = 3'b000;
#40 inputA = 5;
inputB = 6;
ALUop = 3'b001;
#40 inputA = 5;
inputB = 6;
ALUop = 3'b010;
#40 inputA = 5;
inputB = 6;
ALUop = 3'b110;
#40 inputA = 5;
inputB = 6;
ALUop = 3'b111;
#40 inputA = 9;
inputB = 3;
ALUop = 3'b111;
#40 inputA = 6;
inputB = 6;
ALUop = 3'b001;
#40 inputA = -8;
inputB = 6;
ALUop = 3'b001;
end
initial
#340 $stop;
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "soc_system_onchip_memory2_0.hex";
output [ 63: 0] readdata;
input [ 12: 0] address;
input [ 7: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 63: 0] writedata;
wire clocken0;
wire [ 63: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 64,
the_altsyncram.width_byteena_a = 8,
the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Wilson Snyder.
//bug591
module t (/*AUTOARG*/);
function real ABS (real num);
ABS = (num < 0) ? -num : num;
endfunction
function logic range_chk;
input real last;
input real period;
input real cmp;
range_chk = 0;
if ( last >= 0 ) begin
if ( ABS(last - period) > cmp ) begin
range_chk = 1;
end
end
endfunction
function integer ceil;
input num;
real num;
if (num > $rtoi(num))
ceil = $rtoi(num) + 1;
else
// verilator lint_off REALCVT
ceil = num;
// verilator lint_on REALCVT
endfunction
initial begin
if (range_chk(-1.1, 2.2, 3.3) != 1'b0) $stop;
if (range_chk(1.1, 2.2, 0.3) != 1'b1) $stop;
if (range_chk(1.1, 2.2, 2.3) != 1'b0) $stop;
if (range_chk(2.2, 1.1, 0.3) != 1'b1) $stop;
if (range_chk(2.2, 1.1, 2.3) != 1'b0) $stop;
if (ceil(-2.1) != -2) $stop;
if (ceil(2.1) != 3) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_pipe_sync.v
// Version : 3.2
//------------------------------------------------------------------------------
// Filename : pipe_sync.v
// Description : PIPE Sync Module for 7 Series Transceiver
// Version : 20.1
//------------------------------------------------------------------------------
// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default).
// : 1 = Auto TX sync.
// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default).
// : 1 = Auto RX sync.
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Sync Module --------------------------------------------------
module PCIeGen2x8If128_pipe_sync #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe TX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_LANE = 1, // PCIe lane
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter BYPASS_TXDELAY_ALIGN = 0, // Bypass TX delay align
parameter BYPASS_RXDELAY_ALIGN = 0 // Bypass RX delay align
)
(
//---------- Input -------------------------------------
input SYNC_CLK,
input SYNC_RST_N,
input SYNC_SLAVE,
input SYNC_GEN3,
input SYNC_RATE_IDLE,
input SYNC_MMCM_LOCK,
input SYNC_RXELECIDLE,
input SYNC_RXCDRLOCK,
input SYNC_ACTIVE_LANE,
input SYNC_TXSYNC_START,
input SYNC_TXPHINITDONE,
input SYNC_TXDLYSRESETDONE,
input SYNC_TXPHALIGNDONE,
input SYNC_TXSYNCDONE,
input SYNC_RXSYNC_START,
input SYNC_RXDLYSRESETDONE,
input SYNC_RXPHALIGNDONE_M,
input SYNC_RXPHALIGNDONE_S,
input SYNC_RXSYNC_DONEM_IN,
input SYNC_RXSYNCDONE,
//---------- Output ------------------------------------
output SYNC_TXPHDLYRESET,
output SYNC_TXPHALIGN,
output SYNC_TXPHALIGNEN,
output SYNC_TXPHINIT,
output SYNC_TXDLYBYPASS,
output SYNC_TXDLYSRESET,
output SYNC_TXDLYEN,
output SYNC_TXSYNC_DONE,
output [ 5:0] SYNC_FSM_TX,
output SYNC_RXPHALIGN,
output SYNC_RXPHALIGNEN,
output SYNC_RXDLYBYPASS,
output SYNC_RXDLYSRESET,
output SYNC_RXDLYEN,
output SYNC_RXDDIEN,
output SYNC_RXSYNC_DONEM_OUT,
output SYNC_RXSYNC_DONE,
output [ 6:0] SYNC_FSM_RX
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxelecidle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsync_start_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphinitdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txdlysresetdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txphaligndone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg txsyncdone_reg3;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxdlysresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_m_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxphaligndone_s_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsync_donem_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxsyncdone_reg2;
//---------- Output Register ---------------------------
reg txdlyen = 1'd0;
reg txsync_done = 1'd0;
reg [ 5:0] fsm_tx = 6'd0;
reg rxdlyen = 1'd0;
reg rxsync_done = 1'd0;
reg [ 6:0] fsm_rx = 7'd0;
//---------- FSM ---------------------------------------
localparam FSM_TXSYNC_IDLE = 6'b000001;
localparam FSM_MMCM_LOCK = 6'b000010;
localparam FSM_TXSYNC_START = 6'b000100;
localparam FSM_TXPHINITDONE = 6'b001000; // Manual TX sync only
localparam FSM_TXSYNC_DONE1 = 6'b010000;
localparam FSM_TXSYNC_DONE2 = 6'b100000;
localparam FSM_RXSYNC_IDLE = 7'b0000001;
localparam FSM_RXCDRLOCK = 7'b0000010;
localparam FSM_RXSYNC_START = 7'b0000100;
localparam FSM_RXSYNC_DONE1 = 7'b0001000;
localparam FSM_RXSYNC_DONE2 = 7'b0010000;
localparam FSM_RXSYNC_DONES = 7'b0100000;
localparam FSM_RXSYNC_DONEM = 7'b1000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= 1'd0;
rate_idle_reg1 <= 1'd0;
mmcm_lock_reg1 <= 1'd0;
rxelecidle_reg1 <= 1'd0;
rxcdrlock_reg1 <= 1'd0;
txsync_start_reg1 <= 1'd0;
txphinitdone_reg1 <= 1'd0;
txdlysresetdone_reg1 <= 1'd0;
txphaligndone_reg1 <= 1'd0;
txsyncdone_reg1 <= 1'd0;
rxsync_start_reg1 <= 1'd0;
rxdlysresetdone_reg1 <= 1'd0;
rxphaligndone_m_reg1 <= 1'd0;
rxphaligndone_s_reg1 <= 1'd0;
rxsync_donem_reg1 <= 1'd0;
rxsyncdone_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= 1'd0;
rate_idle_reg2 <= 1'd0;
mmcm_lock_reg2 <= 1'd0;
rxelecidle_reg2 <= 1'd0;
rxcdrlock_reg2 <= 1'd0;
txsync_start_reg2 <= 1'd0;
txphinitdone_reg2 <= 1'd0;
txdlysresetdone_reg2 <= 1'd0;
txphaligndone_reg2 <= 1'd0;
txsyncdone_reg2 <= 1'd0;
rxsync_start_reg2 <= 1'd0;
rxdlysresetdone_reg2 <= 1'd0;
rxphaligndone_m_reg2 <= 1'd0;
rxphaligndone_s_reg2 <= 1'd0;
rxsync_donem_reg2 <= 1'd0;
rxsyncdone_reg2 <= 1'd0;
//---------- 3rd Stage FF --------------------------
txsync_start_reg3 <= 1'd0;
txphinitdone_reg3 <= 1'd0;
txdlysresetdone_reg3 <= 1'd0;
txphaligndone_reg3 <= 1'd0;
txsyncdone_reg3 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gen3_reg1 <= SYNC_GEN3;
rate_idle_reg1 <= SYNC_RATE_IDLE;
mmcm_lock_reg1 <= SYNC_MMCM_LOCK;
rxelecidle_reg1 <= SYNC_RXELECIDLE;
rxcdrlock_reg1 <= SYNC_RXCDRLOCK;
txsync_start_reg1 <= SYNC_TXSYNC_START;
txphinitdone_reg1 <= SYNC_TXPHINITDONE;
txdlysresetdone_reg1 <= SYNC_TXDLYSRESETDONE;
txphaligndone_reg1 <= SYNC_TXPHALIGNDONE;
txsyncdone_reg1 <= SYNC_TXSYNCDONE;
rxsync_start_reg1 <= SYNC_RXSYNC_START;
rxdlysresetdone_reg1 <= SYNC_RXDLYSRESETDONE;
rxphaligndone_m_reg1 <= SYNC_RXPHALIGNDONE_M;
rxphaligndone_s_reg1 <= SYNC_RXPHALIGNDONE_S;
rxsync_donem_reg1 <= SYNC_RXSYNC_DONEM_IN;
rxsyncdone_reg1 <= SYNC_RXSYNCDONE;
//---------- 2nd Stage FF --------------------------
gen3_reg2 <= gen3_reg1;
rate_idle_reg2 <= rate_idle_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
rxelecidle_reg2 <= rxelecidle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
txsync_start_reg2 <= txsync_start_reg1;
txphinitdone_reg2 <= txphinitdone_reg1;
txdlysresetdone_reg2 <= txdlysresetdone_reg1;
txphaligndone_reg2 <= txphaligndone_reg1;
txsyncdone_reg2 <= txsyncdone_reg1;
rxsync_start_reg2 <= rxsync_start_reg1;
rxdlysresetdone_reg2 <= rxdlysresetdone_reg1;
rxphaligndone_m_reg2 <= rxphaligndone_m_reg1;
rxphaligndone_s_reg2 <= rxphaligndone_s_reg1;
rxsync_donem_reg2 <= rxsync_donem_reg1;
rxsyncdone_reg2 <= rxsyncdone_reg1;
//---------- 3rd Stage FF --------------------------
txsync_start_reg3 <= txsync_start_reg2;
txphinitdone_reg3 <= txphinitdone_reg2;
txdlysresetdone_reg3 <= txdlysresetdone_reg2;
txphaligndone_reg3 <= txphaligndone_reg2;
txsyncdone_reg3 <= txsyncdone_reg2;
end
end
//---------- Generate TX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) || (PCIE_TXBUF_EN == "FALSE"))
begin : txsync_fsm
//---------- PIPE TX Sync FSM ----------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
else
begin
case (fsm_tx)
//---------- Idle State ------------------------
FSM_TXSYNC_IDLE :
begin
//---------- Exiting Reset or Rate Change --
if (txsync_start_reg2)
begin
fsm_tx <= FSM_MMCM_LOCK;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
else
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= txdlyen;
txsync_done <= txsync_done;
end
end
//---------- Check MMCM Lock -------------------
FSM_MMCM_LOCK :
begin
fsm_tx <= (mmcm_lock_reg2 ? FSM_TXSYNC_START : FSM_MMCM_LOCK);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- TX Delay Soft Reset ---------------
FSM_TXSYNC_START :
begin
fsm_tx <= (((!txdlysresetdone_reg3 && txdlysresetdone_reg2) || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE)) ? FSM_TXPHINITDONE : FSM_TXSYNC_START);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for TX Phase Init Done (Manual Mode Only)
FSM_TXPHINITDONE :
begin
fsm_tx <= (((!txphinitdone_reg3 && txphinitdone_reg2) || (PCIE_TXSYNC_MODE == 1) || (!SYNC_ACTIVE_LANE)) ? FSM_TXSYNC_DONE1 : FSM_TXPHINITDONE);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for TX Phase Alignment Done --
FSM_TXSYNC_DONE1 :
begin
if (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && !SYNC_SLAVE)
fsm_tx <= ((!txsyncdone_reg3 && txsyncdone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
else
fsm_tx <= ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) ? FSM_TXSYNC_DONE2 : FSM_TXSYNC_DONE1);
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
//---------- Wait for Master TX Delay Alignment Done
FSM_TXSYNC_DONE2 :
begin
if ((!txphaligndone_reg3 && txphaligndone_reg2) || (!SYNC_ACTIVE_LANE) || SYNC_SLAVE || (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1)) || (BYPASS_TXDELAY_ALIGN == 1))
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= !SYNC_SLAVE;
txsync_done <= 1'd1;
end
else
begin
fsm_tx <= FSM_TXSYNC_DONE2;
txdlyen <= !SYNC_SLAVE;
txsync_done <= 1'd0;
end
end
//---------- Default State ---------------------
default :
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
endcase
end
end
end
//---------- TX Sync FSM Default------------------------------------------------
else
begin : txsync_fsm_disable
//---------- Default -------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
fsm_tx <= FSM_TXSYNC_IDLE;
txdlyen <= 1'd0;
txsync_done <= 1'd0;
end
end
endgenerate
//---------- Generate RX Sync FSM ----------------------------------------------
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_RXBUF_EN == "FALSE"))
begin : rxsync_fsm
//---------- PIPE RX Sync FSM ----------------------------------------------
always @ (posedge SYNC_CLK)
begin
if (!SYNC_RST_N)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
else
begin
case (fsm_rx)
//---------- Idle State ------------------------
FSM_RXSYNC_IDLE :
begin
//---------- Exiting Rate Change -----------
if (rxsync_start_reg2)
begin
fsm_rx <= FSM_RXCDRLOCK;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Exiting Electrical Idle without Rate Change
else if (gen3_reg2 && rate_idle_reg2 && ((rxelecidle_reg2 == 1'd1) && (rxelecidle_reg1 == 1'd0)))
begin
fsm_rx <= FSM_RXCDRLOCK;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Idle --------------------------
else
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= rxelecidle_reg2 ? 1'd0 : rxdlyen;
rxsync_done <= rxelecidle_reg2 ? 1'd0 : rxsync_done;
end
end
//---------- Wait for RX Electrical Idle Exit and RX CDR Lock
FSM_RXCDRLOCK :
begin
fsm_rx <= ((!rxelecidle_reg2 && rxcdrlock_reg2) ? FSM_RXSYNC_START : FSM_RXCDRLOCK);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Start RX Sync with RX Delay Soft Reset
FSM_RXSYNC_START :
begin
fsm_rx <= ((!rxdlysresetdone_reg2 && rxdlysresetdone_reg1) ? FSM_RXSYNC_DONE1 : FSM_RXSYNC_START);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
//---------- Wait for RX Phase Alignment Done --
FSM_RXSYNC_DONE1 :
begin
if (SYNC_SLAVE)
begin
fsm_rx <= ((!rxphaligndone_s_reg2 && rxphaligndone_s_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
else
begin
fsm_rx <= ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) ? FSM_RXSYNC_DONE2 : FSM_RXSYNC_DONE1);
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Master RX Delay Alignment Done
FSM_RXSYNC_DONE2 :
begin
if (SYNC_SLAVE)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd1;
end
else if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
begin
fsm_rx <= ((PCIE_LANE == 1) ? FSM_RXSYNC_IDLE : FSM_RXSYNC_DONES);
rxdlyen <= (PCIE_LANE == 1);
rxsync_done <= (PCIE_LANE == 1);
end
else
begin
fsm_rx <= FSM_RXSYNC_DONE2;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Slave RX Phase Alignment Done
FSM_RXSYNC_DONES :
begin
if (!rxphaligndone_s_reg2 && rxphaligndone_s_reg1)
begin
fsm_rx <= FSM_RXSYNC_DONEM;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
else
begin
fsm_rx <= FSM_RXSYNC_DONES;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
//---------- Wait for Master RX Delay Alignment Done
FSM_RXSYNC_DONEM :
begin
if ((!rxphaligndone_m_reg2 && rxphaligndone_m_reg1) || (BYPASS_RXDELAY_ALIGN == 1))
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd1;
rxsync_done <= 1'd1;
end
else
begin
fsm_rx <= FSM_RXSYNC_DONEM;
rxdlyen <= 1'd1;
rxsync_done <= 1'd0;
end
end
//---------- Default State ---------------------
default :
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
endcase
end
end
end
//---------- RX Sync FSM Default -----------------------------------------------
else
begin : rxsync_fsm_disable
//---------- Default -------------------------------------------------------
always @ (posedge SYNC_CLK)
begin
fsm_rx <= FSM_RXSYNC_IDLE;
rxdlyen <= 1'd0;
rxsync_done <= 1'd0;
end
end
endgenerate
//---------- PIPE Sync Output --------------------------------------------------
assign SYNC_TXPHALIGNEN = ((PCIE_TXSYNC_MODE == 1) || (!gen3_reg2 && (PCIE_TXBUF_EN == "TRUE"))) ? 1'd0 : 1'd1;
assign SYNC_TXDLYBYPASS = 1'd0;
//assign SYNC_TXDLYSRESET = !(((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXDLYSRESET = (fsm_tx == FSM_TXSYNC_START);
assign SYNC_TXPHDLYRESET = (((PCIE_GT_DEVICE == "GTH") || (PCIE_GT_DEVICE == "GTP")) && (PCIE_TXSYNC_MODE == 1) && SYNC_SLAVE) ? (fsm_tx == FSM_TXSYNC_START) : 1'd0;
assign SYNC_TXPHINIT = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXPHINITDONE);
assign SYNC_TXPHALIGN = PCIE_TXSYNC_MODE ? 1'd0 : (fsm_tx == FSM_TXSYNC_DONE1);
assign SYNC_TXDLYEN = PCIE_TXSYNC_MODE ? 1'd0 : txdlyen;
assign SYNC_TXSYNC_DONE = txsync_done;
assign SYNC_FSM_TX = fsm_tx;
assign SYNC_RXPHALIGNEN = ((PCIE_RXSYNC_MODE == 1) || (!gen3_reg2) || (PCIE_RXBUF_EN == "TRUE")) ? 1'd0 : 1'd1;
assign SYNC_RXDLYBYPASS = !gen3_reg2 || (PCIE_RXBUF_EN == "TRUE");
assign SYNC_RXDLYSRESET = (fsm_rx == FSM_RXSYNC_START);
assign SYNC_RXPHALIGN = PCIE_RXSYNC_MODE ? 1'd0 : (!SYNC_SLAVE ? (fsm_rx == FSM_RXSYNC_DONE1) : (rxsync_donem_reg2 && (fsm_rx == FSM_RXSYNC_DONE1)));
assign SYNC_RXDLYEN = PCIE_RXSYNC_MODE ? 1'd0 : rxdlyen;
assign SYNC_RXDDIEN = gen3_reg2 && (PCIE_RXBUF_EN == "FALSE");
assign SYNC_RXSYNC_DONE = rxsync_done;
assign SYNC_RXSYNC_DONEM_OUT = (fsm_rx == FSM_RXSYNC_DONES);
assign SYNC_FSM_RX = fsm_rx;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31O_TB_V
`define SKY130_FD_SC_HDLL__A31O_TB_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a31o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hdll__a31o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31O_TB_V
|
module SimpleRam
#(parameter BUS_WIDTH = 8, parameter SIZE = 512, parameter ADDRESS_WIDTH = 32)
(
input wire clk,
input wire reset,
input wire [ADDRESS_WIDTH-1:0] addrA,
input wire [BUS_WIDTH-1:0] dataIn,
input wire writeEnable,
input wire [ADDRESS_WIDTH-1:0] addrB,
output reg [BUS_WIDTH-1:0] outA,
output reg [BUS_WIDTH-1:0] outB,
output reg busyA,
output reg busyB
);
reg [BUS_WIDTH-1:0] memory[0:SIZE-1];
reg [BUS_WIDTH-1:0] lastAddrA = 0;
reg [BUS_WIDTH-1:0] lastAddrB = 0;
// Counter variable for initialization
integer i;
// For debugging
always @(posedge reset) $writememh("ram.hex", memory);
always @(clk)
begin
if(writeEnable)
begin
outA <= dataIn;
memory[addrA] <= dataIn;
end
if(addrA != lastAddrA)
busyA <= 1;
if(addrB != lastAddrB)
busyA <= 1;
if(~writeEnable)
begin
busyA <= 0;
outA <= memory[addrA];
busyB <= 0;
outB <= memory[addrB];
end
lastAddrA = addrA;
lastAddrB = addrB;
if(reset)
begin
busyA <= 1;
busyB <= 1;
outA <= 0;
outB <= 0;
for(i = 0; i < SIZE; i=i+1)
memory[i] <= 0;
end
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_1kx16.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_1kx16 (
aclr,
clock,
data,
rdreq,
wrreq,
almost_empty,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [15:0] data;
input rdreq;
input wrreq;
output almost_empty;
output empty;
output full;
output [15:0] q;
output [9:0] usedw;
wire [9:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [15:0] sub_wire3;
wire sub_wire4;
wire [9:0] usedw = sub_wire0[9:0];
wire empty = sub_wire1;
wire almost_empty = sub_wire2;
wire [15:0] q = sub_wire3[15:0];
wire full = sub_wire4;
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.almost_empty (sub_wire2),
.q (sub_wire3),
.full (sub_wire4)
// synopsys translate_off
,
.sclr (),
.almost_full ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.almost_empty_value = 504,
scfifo_component.intended_device_family = "Cyclone",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
scfifo_component.lpm_numwords = 1024,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 10,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "504"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: ALMOST_EMPTY_VALUE NUMERIC "504"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: almost_empty 0 0 0 0 OUTPUT NODEFVAL almost_empty
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: CONNECT: almost_empty 0 0 0 0 @almost_empty 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1kx16_wave*.jpg FALSE
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_pipe_wrapper.v
// Version : 3.0
//------------------------------------------------------------------------------
// Filename : pipe_wrapper.v
// Description : PIPE Wrapper for 7 Series Transceiver
// Version : 20.2
//------------------------------------------------------------------------------
//---------- PIPE Wrapper Hierarchy --------------------------------------------
// pipe_wrapper.v
// pipe_clock.v
// pipe_reset.v or gtp_pipe_reset.v
// qpll_reset.v
// * Generate GTXE2_CHANNEL for every lane.
// pipe_user.v
// pipe_rate.v or gtp_pipe_rate.v
// pipe_sync.v
// pipe_drp.v or gtp_pipe_drp.v
// pipe_eq.v
// rxeq_scan.v
// gt_wrapper.v
// GTXE2_CHANNEL or GTHE2_CHANNEL or GTPE2_CHANNEL
// GTXE2_COMMON or GTHE2_COMMON or GTPE2_CHANNEL
// * Generate GTXE2_COMMON for every quad.
// qpll_drp.v
// qpll_wrapper.v
//------------------------------------------------------------------------------
//---------- PIPE Wrapper Parameter Encoding -----------------------------------
// PCIE_SIM_MODE : "FALSE" = Normal mode (default)
// : "TRUE" = Simulation only
// PCIE_SIM_TX_EIDLE_DRIVE_LEVEL : "0", "1" (default), "X" simulation TX electrical idle drive level
// PCIE_GT_DEVICE : "GTX" (default)
// : "GTH"
// : "GTP"
// PCIE_USE_MODE : "1.0" = GTX IES 325T or GTP IES/GES use mode.
// : "1.1" = GTX IES 485T use mode.
// : "2.0" = GTH IES 690T use mode for 1.0 silicon.
// : "2.1" = GTH GES 690T use mode for 1.2 and 2.0 silicon. SW model use "2.0"
// : "3.0" = GTX GES 325T or 485T use mode (default).
// PCIE_PLL_SEL : "CPLL" (default)
// : "QPLL"
// PCIE_AUX_CDR_GEN3_EN : "FALSE" Use Primary CDR for Gen3 only (GTH 2.0)
// : "TRUE" Use AUX CDR for Gen3 only (default) (GTH 2.0)
// PCIE_LPM_DFE : "DFE" for Gen1/Gen2 only (GTX, GTH)
// : "LPM" for Gen1/Gen2 only (default) (GTX, GTH)
// PCIE_LPM_DFE_GEN3 : "DFE" for Gen3 only (GTX, GTH)
// : "LPM" for Gen3 only (default) (GTX, GTH)
// PCIE_EXT_CLK : "FALSE" = Use internal clock module(default)
// : "TRUE" = Use external clock module
// PCIE_POWER_SAVING : "FALSE" = Disable PLL power saving
// : "TRUE" = Enable PLL power saving (default)
// PCIE_ASYNC_EN : "FALSE" = Synchronous mode (default)
// : "TRUE" = Asynchronous mode.
// PCIE_TXBUF_EN : "FALSE" = TX buffer bypass for Gen1/Gen2 only (default)
// : "TRUE" = TX buffer use for Gen1/Gen2 only (for debug only)
// PCIE_RXBUF_EN : "FALSE" = RX buffer bypass for Gen3 only (not supported)
// : "TRUE" = RX buffer use for Gen3 only (default)
// PCIE_TXSYNC_MODE : 0 = Manual TX sync (default) (GTX, GTH)
// : 1 = Auto TX sync (GTH)
// PCIE_RXSYNC_MODE : 0 = Manual RX sync (default) (GTX, GTH)
// : 1 = Auto RX sync (GTH)
// PCIE_CHAN_BOND : 0 = One-Hop (default)
// : 1 = Daisy-Chain
// : 2 = Binary-Tree
// PCIE_CHAN_BOND_EN : "FALSE" = Channel bonding disable for Gen1/Gen2 only
// : "TRUE" = Channel bonding enable for Gen1/Gen2 only
// PCIE_LANE : 1 (default), 2, 4, or 8
// PCIE_LINK_SPEED : 1 = PCIe Gen1 Mode
// : 2 = PCIe Gen1/Gen2 Mode (default)
// : 3 = PCIe Gen1/Gen2/Gen3 Mode
// PCIE_REFCLK_FREQ : 0 = 100 MHz (default)
// : 1 = 125 MHz
// : 2 = 250 MHz
// PCIE_USERCLK[1/2]_FREQ : 0 = Disable user clock
// : 1 = 31.25 MHz
// : 2 = 62.50 MHz (default)
// : 3 = 125.00 MHz
// : 4 = 250.00 MHz
// : 5 = 500.00 MHz
// PCIE_TX_EIDLE_ASSERT_DELAY : 3'd0 to 3'd7 (default = 3'd4)
// PCIE_RXEQ_MODE_GEN3 : 0 = Return same TX coefficients
// : 1 = Return TX preset #5
// PCIE_OOBCLK_MODE : 0 = Reference clock
// : 1 = 62.50 MHz (default)
// : 2 = 50.00 MHz (requires 1 BUFG)
// PCIE_JTAG_MODE : 0 = Normal operation (default)
// : 1 = JTAG mode (for debug only)
// PCIE_DEBUG_MODE : 0 = Normal operation (default)
// : 1 = Debug mode (for debug only)
//------------------------------------------------------------------------------
//---------- Notes -------------------------------------------------------------
// Notes within the PIPE Wrapper RTL files are for internal use only.
// Data Width : This PIPE Wrapper supports a 32-bit [TX/RX]DATA interface.
// In Gen1/Gen2 modes, only 16-bits [15:0] are used.
// In Gen3 mode, all 32-bits are used.
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Wrapper ------------------------------------------------------
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_pipe_wrapper #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_SIM_TX_EIDLE_DRIVE_LEVEL = "1", // PCIe sim TX electrical idle drive level
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 (GTX/GTH) only
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR for Gen3 (GTH 2.0) only
parameter PCIE_LPM_DFE = "LPM", // PCIe LPM or DFE mode for Gen1/Gen2 only
parameter PCIE_LPM_DFE_GEN3 = "DFE", // PCIe LPM or DFE mode for Gen3 only
parameter PCIE_EXT_CLK = "FALSE", // PCIe external clock
parameter PCIE_EXT_GT_COMMON = "FALSE", // PCIe external GT COMMON
parameter EXT_CH_GT_DRP = "FALSE", // PCIe external CH DRP
parameter TX_MARGIN_FULL_0 = 7'b1001111, // 1000 mV
parameter TX_MARGIN_FULL_1 = 7'b1001110, // 950 mV
parameter TX_MARGIN_FULL_2 = 7'b1001101, // 900 mV
parameter TX_MARGIN_FULL_3 = 7'b1001100, // 850 mV
parameter TX_MARGIN_FULL_4 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_0 = 7'b1000101, // 500 mV
parameter TX_MARGIN_LOW_1 = 7'b1000110 , // 450 mV
parameter TX_MARGIN_LOW_2 = 7'b1000011, // 400 mV
parameter TX_MARGIN_LOW_3 = 7'b1000010 , // 350 mV
parameter TX_MARGIN_LOW_4 = 7'b1000000 ,
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter PCIE_CHAN_BOND = 1, // PCIe channel bonding mode
parameter PCIE_CHAN_BOND_EN = "TRUE", // PCIe channel bonding enable for Gen1/Gen2 only
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
parameter PCIE_TX_EIDLE_ASSERT_DELAY = 3'd4, // PCIe TX electrical idle assert delay
parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
parameter PCIE_OOBCLK_MODE = 1, // PCIe OOB clock mode
parameter PCIE_JTAG_MODE = 0, // PCIe JTAG mode
parameter PCIE_DEBUG_MODE = 0 // PCIe debug mode
)
//--------------------------------------
( // Gen1/Gen2 | Gen3
//--------------------------------------
//---------- PIPE Clock & Reset Ports ------------------
input PIPE_CLK, // Reference clock that drives MMCM
input PIPE_RESET_N, // PCLK | PCLK
output PIPE_PCLK, // Drives [TX/RX]USRCLK in Gen1/Gen2
// Drives TXUSRCLK in Gen3
// Drives RXUSRCLK in Gen3 async mode only
//---------- PIPE TX Data Ports ------------------------
input [(PCIE_LANE*32)-1:0]PIPE_TXDATA, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXDATAK, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_TXP, // Serial data
output [PCIE_LANE-1:0] PIPE_TXN, // Serial data
//---------- PIPE RX Data Ports ------------------------
input [PCIE_LANE-1:0] PIPE_RXP, // Serial data
input [PCIE_LANE-1:0] PIPE_RXN, // Serial data
output [(PCIE_LANE*32)-1:0]PIPE_RXDATA, // PCLK | RXUSRCLK
output [(PCIE_LANE*4)-1:0] PIPE_RXDATAK, // PCLK | RXUSRCLK
//---------- PIPE Command Ports ------------------------
input PIPE_TXDETECTRX, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_TXELECIDLE, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_TXCOMPLIANCE, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXPOLARITY, // PCLK | RXUSRCLK
input [(PCIE_LANE*2)-1:0] PIPE_POWERDOWN, // PCLK | PCLK
input [ 1:0] PIPE_RATE, // PCLK | PCLK
//---------- PIPE Electrical Command Ports -------------
input [ 2:0] PIPE_TXMARGIN, // Async | Async
input PIPE_TXSWING, // Async | Async
input [PCIE_LANE-1:0] PIPE_TXDEEMPH, // Async/PCLK | Async/PCLK
input [(PCIE_LANE*2)-1:0] PIPE_TXEQ_CONTROL, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_TXEQ_PRESET_DEFAULT,// PCLK | PCLK
input [(PCIE_LANE*6)-1:0] PIPE_TXEQ_DEEMPH, // PCLK | PCLK
input [(PCIE_LANE*2)-1:0] PIPE_RXEQ_CONTROL, // PCLK | PCLK
input [(PCIE_LANE*3)-1:0] PIPE_RXEQ_PRESET, // PCLK | PCLK
input [(PCIE_LANE*6)-1:0] PIPE_RXEQ_LFFS, // PCLK | PCLK
input [(PCIE_LANE*4)-1:0] PIPE_RXEQ_TXPRESET, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_EN, // PCLK | PCLK
input [(PCIE_LANE*18)-1:0]PIPE_RXEQ_USER_TXCOEFF, // PCLK | PCLK
input [PCIE_LANE-1:0] PIPE_RXEQ_USER_MODE, // PCLK | PCLK
output [ 5:0] PIPE_TXEQ_FS, // Async | Async
output [ 5:0] PIPE_TXEQ_LF, // Async | Async
output [(PCIE_LANE*18)-1:0]PIPE_TXEQ_COEFF, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_TXEQ_DONE, // PCLK | PCLK
output [(PCIE_LANE*18)-1:0]PIPE_RXEQ_NEW_TXCOEFF, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_LFFS_SEL, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_ADAPT_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXEQ_DONE, // PCLK | PCLK
//---------- PIPE Status Ports -------------------------
output [PCIE_LANE-1:0] PIPE_RXVALID, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_PHYSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_PHYSTATUS_RST, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXELECIDLE, // Async | Async
output [PCIE_LANE-1:0] PIPE_EYESCANDATAERROR, // Async | Async
output [(PCIE_LANE*3)-1:0] PIPE_RXSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXPMARESETDONE, // Async | Async
output [(PCIE_LANE*3)-1:0] PIPE_RXBUFSTATUS, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_TXPHALIGNDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_TXPHINITDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_TXDLYSRESETDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXPHALIGNDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXDLYSRESETDONE, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXSYNCDONE, // PCLK | RXUSRCLK
output [(PCIE_LANE*8)-1:0] PIPE_RXDISPERR, // PCLK | RXUSRCLK
output [(PCIE_LANE*8)-1:0] PIPE_RXNOTINTABLE, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXCOMMADET, // PCLK | RXUSRCLK
//---------- PIPE User Ports ---------------------------
input PIPE_MMCM_RST_N, // Async | Async
input [PCIE_LANE-1:0] PIPE_RXSLIDE, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_CPLL_LOCK, // Async | Async
output [(PCIE_LANE-1)>>2:0]PIPE_QPLL_LOCK, // Async | Async
output PIPE_PCLK_LOCK, // Async | Async
output [PCIE_LANE-1:0] PIPE_RXCDRLOCK, // Async | Async
output PIPE_USERCLK1, // Optional user clock
output PIPE_USERCLK2, // Optional user clock
output PIPE_RXUSRCLK, // RXUSRCLK
// Equivalent to PCLK in Gen1/Gen2
// Equivalent to RXOUTCLK[0] in Gen3
output [PCIE_LANE-1:0] PIPE_RXOUTCLK, // RX recovered clock (for debug only)
output [PCIE_LANE-1:0] PIPE_TXSYNC_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXSYNC_DONE, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_GEN3_RDY, // PCLK | RXUSRCLK
output [PCIE_LANE-1:0] PIPE_RXCHANISALIGNED,
output [PCIE_LANE-1:0] PIPE_ACTIVE_LANE,
// Shared Logic Internal
output INT_PCLK_OUT_SLAVE, // PCLK | PCLK
output INT_RXUSRCLK_OUT, // RXUSERCLK
output [PCIE_LANE-1:0 ] INT_RXOUTCLK_OUT, // RX recovered clock
output INT_DCLK_OUT, // DCLK | DCLK
output INT_USERCLK1_OUT, // Optional user clock
output INT_USERCLK2_OUT, // Optional user clock
output INT_OOBCLK_OUT, // OOB | OOB
output INT_MMCM_LOCK_OUT, // Async | Async
output [1:0] INT_QPLLLOCK_OUT,
output [1:0] INT_QPLLOUTCLK_OUT,
output [1:0] INT_QPLLOUTREFCLK_OUT,
input [PCIE_LANE-1:0] INT_PCLK_SEL_SLAVE,
// Shared Logic External
//---------- External Clock Ports ----------------------
input PIPE_PCLK_IN, // PCLK | PCLK
input PIPE_RXUSRCLK_IN, // RXUSERCLK
// Equivalent to PCLK in Gen1/Gen2
// Equivalent to RXOUTCLK[0] in Gen3
input [PCIE_LANE-1:0] PIPE_RXOUTCLK_IN, // RX recovered clock
input PIPE_DCLK_IN, // DCLK | DCLK
input PIPE_USERCLK1_IN, // Optional user clock
input PIPE_USERCLK2_IN, // Optional user clock
input PIPE_OOBCLK_IN, // OOB | OOB
input PIPE_MMCM_LOCK_IN, // Async | Async
output PIPE_TXOUTCLK_OUT, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXOUTCLK_OUT, // RX recovered clock (for debug only)
output [PCIE_LANE-1:0] PIPE_PCLK_SEL_OUT, // PCLK | PCLK
output PIPE_GEN3_OUT, // PCLK | PCLK
//---------- External GT COMMON Ports ----------------------
input [11:0] QPLL_DRP_CRSCODE,
input [17:0] QPLL_DRP_FSM,
input [1:0] QPLL_DRP_DONE,
input [1:0] QPLL_DRP_RESET,
input [1:0] QPLL_QPLLLOCK,
input [1:0] QPLL_QPLLOUTCLK,
input [1:0] QPLL_QPLLOUTREFCLK,
output QPLL_QPLLPD,
output [1:0] QPLL_QPLLRESET,
output QPLL_DRP_CLK,
output QPLL_DRP_RST_N,
output QPLL_DRP_OVRD,
output QPLL_DRP_GEN3,
output QPLL_DRP_START,
//---------- TRANSCEIVER DEBUG -----------------------
input [ 2:0] PIPE_TXPRBSSEL, // PCLK | PCLK
input [ 2:0] PIPE_RXPRBSSEL, // PCLK | PCLK
input PIPE_TXPRBSFORCEERR, // PCLK | PCLK
input PIPE_RXPRBSCNTRESET, // PCLK | PCLK
input [ 2:0] PIPE_LOOPBACK, // PCLK | PCLK
output [PCIE_LANE-1:0] PIPE_RXPRBSERR, // PCLK | PCLK
//---------- FSM Ports ---------------------------------
output [4:0] PIPE_RST_FSM, // PCLK | PCLK
output [11:0] PIPE_QRST_FSM, // PCLK | PCLK
output [(PCIE_LANE*5)-1:0] PIPE_RATE_FSM, // PCLK | PCLK
output [(PCIE_LANE*6)-1:0] PIPE_SYNC_FSM_TX, // PCLK | PCLK
output [(PCIE_LANE*7)-1:0] PIPE_SYNC_FSM_RX, // PCLK | PCLK
output [(PCIE_LANE*7)-1:0] PIPE_DRP_FSM, // DCLK | DCLK
output [(PCIE_LANE*6)-1:0] PIPE_TXEQ_FSM, // PCLK | PCLK
output [(PCIE_LANE*6)-1:0] PIPE_RXEQ_FSM, // PCLK | PCLK
output [((((PCIE_LANE-1)>>2)+1)*9)-1:0]PIPE_QDRP_FSM, // DCLK | DCLK
output PIPE_RST_IDLE, // PCLK | PCLK
output PIPE_QRST_IDLE, // PCLK | PCLK
output PIPE_RATE_IDLE, // PCLK | PCLK
//----------- Channel DRP----------------------------
output EXT_CH_GT_DRPCLK,
input [(PCIE_LANE*9)-1:0] EXT_CH_GT_DRPADDR,
input [PCIE_LANE-1:0] EXT_CH_GT_DRPEN,
input [(PCIE_LANE*16)-1:0]EXT_CH_GT_DRPDI,
input [PCIE_LANE-1:0] EXT_CH_GT_DRPWE,
output [(PCIE_LANE*16)-1:0]EXT_CH_GT_DRPDO,
output [PCIE_LANE-1:0] EXT_CH_GT_DRPRDY,
//---------- JTAG Ports --------------------------------
input PIPE_JTAG_EN, // DCLK | DCLK
output [PCIE_LANE-1:0] PIPE_JTAG_RDY, // DCLK | DCLK
//---------- Debug Ports -------------------------------
output [PCIE_LANE-1:0] PIPE_DEBUG_0, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_1, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_2, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_3, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_4, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_5, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_6, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_7, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_8, // Async | Async
output [PCIE_LANE-1:0] PIPE_DEBUG_9, // Async | Async
output [31:0] PIPE_DEBUG, // Async | Async
output [(PCIE_LANE*15)-1:0] PIPE_DMONITOROUT // DMONITORCLK
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg reset_n_reg2;
//---------- PIPE Clock Module Output ------------------
wire clk_pclk;
wire clk_rxusrclk;
wire [PCIE_LANE-1:0] clk_rxoutclk;
wire clk_dclk;
wire clk_oobclk;
wire clk_mmcm_lock;
//---------- PIPE Reset Module Output ------------------
wire rst_cpllreset;
wire rst_cpllpd;
wire rst_rxusrclk_reset;
wire rst_dclk_reset;
wire rst_gtreset;
wire rst_drp_start;
wire rst_drp_x16x20_mode;
wire rst_drp_x16;
wire rst_userrdy;
wire rst_txsync_start;
wire rst_idle;
wire [4:0] rst_fsm;
//------------------------------------------------------
wire gtp_rst_qpllreset; // GTP
wire gtp_rst_qpllpd; // GTP
//------------------------------------------------------
wire [(PCIE_LANE-1)>>2:0]qpllreset;
wire qpllpd;
//---------- QPLL Reset Module Output ------------------
wire qrst_ovrd;
wire qrst_drp_start;
wire qrst_qpllreset;
wire qrst_qpllpd;
wire qrst_idle;
wire [3:0] qrst_fsm;
//---------- PIPE_JTAG Master Module Output ------------
wire [(PCIE_LANE*37)-1:0] jtag_sl_iport;
wire [(PCIE_LANE*17)-1:0] jtag_sl_oport;
//---------- PIPE User Module Output -------------------
wire [PCIE_LANE-1:0] gt_txpmareset_i;
wire [PCIE_LANE-1:0] gt_rxpmareset_i;
wire [PCIE_LANE-1:0] user_oobclk;
wire [PCIE_LANE-1:0] user_resetovrd;
wire [PCIE_LANE-1:0] user_txpmareset;
wire [PCIE_LANE-1:0] user_rxpmareset;
wire [PCIE_LANE-1:0] user_rxcdrreset;
wire [PCIE_LANE-1:0] user_rxcdrfreqreset;
wire [PCIE_LANE-1:0] user_rxdfelpmreset;
wire [PCIE_LANE-1:0] user_eyescanreset;
wire [PCIE_LANE-1:0] user_txpcsreset;
wire [PCIE_LANE-1:0] user_rxpcsreset;
wire [PCIE_LANE-1:0] user_rxbufreset;
wire [PCIE_LANE-1:0] user_resetovrd_done;
wire [PCIE_LANE-1:0] user_active_lane;
wire [PCIE_LANE-1:0] user_resetdone /* synthesis syn_keep=1 */;
wire [PCIE_LANE-1:0] user_rxcdrlock;
wire [PCIE_LANE-1:0] user_rx_converge;
//---------- PIPE Rate Module Output -------------------
wire [PCIE_LANE-1:0] rate_cpllpd;
wire [PCIE_LANE-1:0] rate_qpllpd;
wire [PCIE_LANE-1:0] rate_cpllreset;
wire [PCIE_LANE-1:0] rate_qpllreset;
wire [PCIE_LANE-1:0] rate_txpmareset;
wire [PCIE_LANE-1:0] rate_rxpmareset;
wire [(PCIE_LANE*2)-1:0] rate_sysclksel;
wire [PCIE_LANE-1:0] rate_pclk_sel;
wire [PCIE_LANE-1:0] rate_drp_start;
wire [PCIE_LANE-1:0] rate_drp_x16x20_mode;
wire [PCIE_LANE-1:0] rate_drp_x16;
wire [PCIE_LANE-1:0] rate_gen3;
wire [(PCIE_LANE*3)-1:0] rate_rate;
wire [PCIE_LANE-1:0] rate_resetovrd_start;
wire [PCIE_LANE-1:0] rate_txsync_start;
wire [PCIE_LANE-1:0] rate_done;
wire [PCIE_LANE-1:0] rate_rxsync_start;
wire [PCIE_LANE-1:0] rate_rxsync;
wire [PCIE_LANE-1:0] rate_idle;
wire [(PCIE_LANE*5)-1:0] rate_fsm;
//---------- PIPE Sync Module Output -------------------
wire [PCIE_LANE-1:0] sync_txphdlyreset;
wire [PCIE_LANE-1:0] sync_txphalign;
wire [PCIE_LANE-1:0] sync_txphalignen;
wire [PCIE_LANE-1:0] sync_txphinit;
wire [PCIE_LANE-1:0] sync_txdlybypass;
wire [PCIE_LANE-1:0] sync_txdlysreset;
wire [PCIE_LANE-1:0] sync_txdlyen;
wire [PCIE_LANE-1:0] sync_txsync_done;
wire [(PCIE_LANE*6)-1:0] sync_fsm_tx;
wire [PCIE_LANE-1:0] sync_rxphalign;
wire [PCIE_LANE-1:0] sync_rxphalignen;
wire [PCIE_LANE-1:0] sync_rxdlybypass;
wire [PCIE_LANE-1:0] sync_rxdlysreset;
wire [PCIE_LANE-1:0] sync_rxdlyen;
wire [PCIE_LANE-1:0] sync_rxddien;
wire [PCIE_LANE-1:0] sync_rxsync_done;
wire [PCIE_LANE-1:0] sync_rxsync_donem;
wire [(PCIE_LANE*7)-1:0] sync_fsm_rx;
wire [PCIE_LANE-1:0] txdlysresetdone;
wire [PCIE_LANE-1:0] txphaligndone;
wire [PCIE_LANE-1:0] rxdlysresetdone;
wire [PCIE_LANE-1:0] rxphaligndone_s;
wire txsyncallin; // GTH
wire rxsyncallin; // GTH
//---------- PIPE DRP Module Output --------------------
wire [(PCIE_LANE*9)-1:0] drp_addr;
wire [PCIE_LANE-1:0] drp_en;
wire [(PCIE_LANE*16)-1:0]drp_di;
wire [PCIE_LANE-1:0] drp_we;
wire [PCIE_LANE-1:0] drp_done;
wire [(PCIE_LANE*3)-1:0] drp_fsm;
//---------- PIPE JTAG Slave Module Output--------------
wire [(PCIE_LANE*17)-1:0]jtag_sl_addr;
wire [PCIE_LANE-1:0] jtag_sl_den;
wire [PCIE_LANE-1:0] jtag_sl_en;
wire [(PCIE_LANE*16)-1:0]jtag_sl_di;
wire [PCIE_LANE-1:0] jtag_sl_we;
//---------- PIPE DRP MUX Output -----------------------
wire [(PCIE_LANE*9)-1:0] drp_mux_addr;
wire [PCIE_LANE-1:0] drp_mux_en;
wire [(PCIE_LANE*16)-1:0]drp_mux_di;
wire [PCIE_LANE-1:0] drp_mux_we;
//---------- PIPE EQ Module Output ---------------------
wire [PCIE_LANE-1:0] eq_txeq_deemph;
wire [(PCIE_LANE*5)-1:0] eq_txeq_precursor;
wire [(PCIE_LANE*7)-1:0] eq_txeq_maincursor;
wire [(PCIE_LANE*5)-1:0] eq_txeq_postcursor;
wire [PCIE_LANE-1:0] eq_rxeq_adapt_done;
//---------- PIPE DRP Module Output --------------------
wire [((((PCIE_LANE-1)>>2)+1)*8)-1:0] qdrp_addr;
wire [(PCIE_LANE-1)>>2:0] qdrp_en;
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qdrp_di;
wire [(PCIE_LANE-1)>>2:0] qdrp_we;
wire [(PCIE_LANE-1)>>2:0] qdrp_done;
wire [(PCIE_LANE-1)>>2:0] qdrp_qpllreset;
wire [((((PCIE_LANE-1)>>2)+1)*6)-1:0] qdrp_crscode;
wire [((((PCIE_LANE-1)>>2)+1)*9)-1:0] qdrp_fsm;
//---------- QPLL Wrapper Output -----------------------
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutclk;
wire [(PCIE_LANE-1)>>2:0] qpll_qplloutrefclk;
wire [(PCIE_LANE-1)>>2:0] qpll_qplllock;
wire [((((PCIE_LANE-1)>>2)+1)*16)-1:0] qpll_do;
wire [(PCIE_LANE-1)>>2:0] qpll_rdy;
//---------- GTX Wrapper Output ------------------------
wire [PCIE_LANE-1:0] gt_txoutclk;
wire [PCIE_LANE-1:0] gt_rxoutclk;
wire [PCIE_LANE-1:0] gt_cplllock;
wire [PCIE_LANE-1:0] gt_rxcdrlock;
wire [PCIE_LANE-1:0] gt_txresetdone;
wire [PCIE_LANE-1:0] gt_rxresetdone;
wire [PCIE_LANE-1:0] gt_eyescandataerror;
wire [PCIE_LANE-1:0] gt_rxpmaresetdone;
wire [(PCIE_LANE*8)-1:0] gt_rxdisperr;
wire [(PCIE_LANE*8)-1:0] gt_rxnotintable;
wire [PCIE_LANE-1:0] gt_rxvalid;
wire [PCIE_LANE-1:0] gt_phystatus;
wire [(PCIE_LANE*3)-1:0] gt_rxstatus;
wire [(PCIE_LANE*3)-1:0] gt_rxbufstatus;
wire [PCIE_LANE-1:0] gt_rxelecidle;
wire [PCIE_LANE-1:0] gt_txratedone;
wire [PCIE_LANE-1:0] gt_rxratedone;
wire [(PCIE_LANE*16)-1:0]gt_do;
wire [PCIE_LANE-1:0] gt_rdy;
wire [PCIE_LANE-1:0] gt_txphinitdone;
wire [PCIE_LANE-1:0] gt_txdlysresetdone;
wire [PCIE_LANE-1:0] gt_txphaligndone;
wire [PCIE_LANE-1:0] gt_rxdlysresetdone;
wire [PCIE_LANE:0] gt_rxphaligndone; // Custom width for calculation
wire [PCIE_LANE-1:0] gt_txsyncout; // GTH
wire [PCIE_LANE-1:0] gt_txsyncdone; // GTH
wire [PCIE_LANE-1:0] gt_rxsyncout; // GTH
wire [PCIE_LANE-1:0] gt_rxsyncdone; // GTH
wire [PCIE_LANE-1:0] gt_rxcommadet;
wire [(PCIE_LANE*4)-1:0] gt_rxchariscomma;
wire [PCIE_LANE-1:0] gt_rxbyteisaligned;
wire [PCIE_LANE-1:0] gt_rxbyterealign;
wire [ 4:0] gt_rxchbondi [PCIE_LANE:0];
wire [(PCIE_LANE*3)-1:0] gt_rxchbondlevel;
wire [ 4:0] gt_rxchbondo [PCIE_LANE:0];
wire [PCIE_LANE-1:0] rxchbonden;
wire [PCIE_LANE-1:0] rxchbondmaster;
wire [PCIE_LANE-1:0] rxchbondslave;
wire [PCIE_LANE-1:0] oobclk;
//---------- TX EQ -------------------------------------
localparam TXEQ_FS = 6'd40; // TX equalization full swing
localparam TXEQ_LF = 6'd15; // TX equalization low frequency
//---------- Select JTAG Slave Type ----------------------------------------
localparam GC_XSDB_SLAVE_TYPE = (PCIE_GT_DEVICE == "GTP") ? 16'h0400 : (PCIE_GT_DEVICE == "GTH") ? 16'h004A : 16'h0046;
//---------- Generate Per-Lane Signals -----------------
genvar i; // Index for per-lane signals
//---------- Assignments -------------------------------------------------------
assign gt_rxchbondo[0] = 5'd0; // Initialize rxchbond for lane 0
assign gt_rxphaligndone[PCIE_LANE] = 1'd1; // Mot used
assign txsyncallin = &(gt_txphaligndone | (~user_active_lane));
assign rxsyncallin = &(gt_rxphaligndone | (~user_active_lane));
//---------- Reset Synchronizer ------------------------------------------------
always @ (posedge clk_pclk or negedge PIPE_RESET_N)
begin
if (!PIPE_RESET_N)
begin
reset_n_reg1 <= 1'd0;
reset_n_reg2 <= 1'd0;
end
else
begin
reset_n_reg1 <= 1'd1;
reset_n_reg2 <= reset_n_reg1;
end
end
//---------- PIPE Clock Module -------------------------------------------------
generate
begin : pipe_clock_int
pcie_7x_0_core_top_pipe_clock #
(
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE), // PCIe number of lanes
.PCIE_LINK_SPEED (PCIE_LINK_SPEED), // PCIe link speed
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
.PCIE_USERCLK1_FREQ (PCIE_USERCLK1_FREQ), // PCIe user clock 1 frequency
.PCIE_USERCLK2_FREQ (PCIE_USERCLK2_FREQ), // PCIe user clock 2 frequency
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
)
pipe_clock_i
(
//---------- Input -------------------------------------
.CLK_CLK (PIPE_CLK),
.CLK_TXOUTCLK (gt_txoutclk[0]), // Reference clock from lane 0
.CLK_RXOUTCLK_IN (gt_rxoutclk),
//.CLK_RST_N (1'b1),
.CLK_RST_N (PIPE_MMCM_RST_N), // Allow system reset for error recovery
.CLK_PCLK_SEL (rate_pclk_sel),
.CLK_PCLK_SEL_SLAVE (INT_PCLK_SEL_SLAVE ),
.CLK_GEN3 (rate_gen3[0]),
//---------- Output ------------------------------------
.CLK_PCLK (clk_pclk),
.CLK_PCLK_SLAVE (INT_PCLK_OUT_SLAVE),
.CLK_RXUSRCLK (clk_rxusrclk),
.CLK_RXOUTCLK_OUT (clk_rxoutclk),
.CLK_DCLK (clk_dclk),
.CLK_USERCLK1 (PIPE_USERCLK1),
.CLK_USERCLK2 (PIPE_USERCLK2),
.CLK_OOBCLK (clk_oobclk),
.CLK_MMCM_LOCK (clk_mmcm_lock)
);
assign INT_RXUSRCLK_OUT = clk_rxusrclk;
assign INT_RXOUTCLK_OUT = clk_rxoutclk;
assign INT_DCLK_OUT = clk_dclk;
assign INT_USERCLK1_OUT = PIPE_USERCLK1;
assign INT_USERCLK2_OUT = PIPE_USERCLK2;
assign INT_OOBCLK_OUT = clk_oobclk;
assign INT_MMCM_LOCK_OUT = clk_mmcm_lock;
end
endgenerate
//---------- PIPE Reset Module -------------------------------------------------
generate
if (PCIE_GT_DEVICE == "GTP")
begin : gtp_pipe_reset
//---------- GTP PIPE Reset Module -------------------------------------
pcie_7x_0_core_top_gtp_pipe_reset #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
gtp_pipe_reset_i
(
//---------- Input -----------------------------
.RST_CLK (clk_pclk),
.RST_RXUSRCLK (clk_rxusrclk),
.RST_DCLK (clk_dclk),
.RST_RST_N (reset_n_reg2),
.RST_DRP_DONE (drp_done),
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
.RST_PLLLOCK (&qpll_qplllock),
//.RST_QPLL_IDLE (qrst_idle), // removed for GTP
.RST_RATE_IDLE (rate_idle),
.RST_RXCDRLOCK (user_rxcdrlock),
.RST_MMCM_LOCK (clk_mmcm_lock),
.RST_RESETDONE (user_resetdone),
.RST_PHYSTATUS (gt_phystatus),
.RST_TXSYNC_DONE (sync_txsync_done),
//---------- Output ----------------------------
.RST_CPLLRESET (rst_cpllreset),
.RST_CPLLPD (rst_cpllpd),
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
.RST_DCLK_RESET (rst_dclk_reset),
.RST_GTRESET (rst_gtreset),
.RST_DRP_START (rst_drp_start),
.RST_DRP_X16 (rst_drp_x16),
.RST_USERRDY (rst_userrdy),
.RST_TXSYNC_START (rst_txsync_start),
.RST_IDLE (rst_idle),
.RST_FSM (rst_fsm)
);
//---------- Default ---------------------------------------------------
assign gtp_rst_qpllreset = rst_cpllreset;
assign gtp_rst_qpllpd = rst_cpllpd;
end
else
begin : pipe_reset
//---------- PIPE Reset Module -----------------------------------------
pcie_7x_0_core_top_pipe_reset #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // PCIe power saving
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
pipe_reset_i
(
//---------- Input -----------------------------
.RST_CLK (clk_pclk),
.RST_RXUSRCLK (clk_rxusrclk),
.RST_DCLK (clk_dclk),
.RST_RST_N (reset_n_reg2),
.RST_DRP_DONE (drp_done),
.RST_RXPMARESETDONE (gt_rxpmaresetdone),
.RST_CPLLLOCK (gt_cplllock),
.RST_QPLL_IDLE (qrst_idle),
.RST_RATE_IDLE (rate_idle),
.RST_RXCDRLOCK (user_rxcdrlock),
.RST_MMCM_LOCK (clk_mmcm_lock),
.RST_RESETDONE (user_resetdone),
.RST_PHYSTATUS (gt_phystatus),
.RST_TXSYNC_DONE (sync_txsync_done),
//---------- Output ----------------------------
.RST_CPLLRESET (rst_cpllreset),
.RST_CPLLPD (rst_cpllpd),
.RST_RXUSRCLK_RESET (rst_rxusrclk_reset),
.RST_DCLK_RESET (rst_dclk_reset),
.RST_GTRESET (rst_gtreset),
.RST_DRP_START (rst_drp_start),
.RST_DRP_X16X20_MODE (rst_drp_x16x20_mode),
.RST_DRP_X16 (rst_drp_x16),
.RST_USERRDY (rst_userrdy),
.RST_TXSYNC_START (rst_txsync_start),
.RST_IDLE (rst_idle),
.RST_FSM (rst_fsm[4:0])
);
//---------- Default ---------------------------------------------------
assign gtp_rst_qpllreset = 1'd0;
assign gtp_rst_qpllpd = 1'd0;
end
endgenerate
//---------- QPLL Reset Module -------------------------------------------------
generate
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL"))
begin : qpll_reset
pcie_7x_0_core_top_qpll_reset #
(
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
.PCIE_LANE (PCIE_LANE) // PCIe number of lanes
)
qpll_reset_i
(
//---------- Input ---------------------------------
.QRST_CLK (clk_pclk),
.QRST_RST_N (reset_n_reg2),
.QRST_MMCM_LOCK (clk_mmcm_lock),
.QRST_CPLLLOCK (gt_cplllock),
.QRST_DRP_DONE (qdrp_done),
.QRST_QPLLLOCK (qpll_qplllock),
.QRST_RATE (PIPE_RATE),
.QRST_QPLLRESET_IN (rate_qpllreset),
.QRST_QPLLPD_IN (rate_qpllpd),
//---------- Output --------------------------------
.QRST_OVRD (qrst_ovrd),
.QRST_DRP_START (qrst_drp_start),
.QRST_QPLLRESET_OUT (qrst_qpllreset),
.QRST_QPLLPD_OUT (qrst_qpllpd),
.QRST_IDLE (qrst_idle),
.QRST_FSM (qrst_fsm)
);
end
else
//---------- QPLL Reset Defaults ---------------------------------------
begin : qpll_reset_disable
assign qrst_ovrd = 1'd0;
assign qrst_drp_start = 1'd0;
assign qrst_qpllreset = 1'd0;
assign qrst_qpllpd = 1'd0;
assign qrst_idle = 1'd0;
assign qrst_fsm = 1;
end
endgenerate
assign jtag_sl_iport = {PCIE_LANE{37'd0}};
//Reference Clock for CPLLPD Fix
wire gt_cpllpdrefclk;
BUFG cpllpd_refclk_inst (.I (PIPE_CLK), .O (gt_cpllpdrefclk));
//---------- Generate PIPE Lane ------------------------------------------------
generate for (i=0; i<PCIE_LANE; i=i+1)
begin : pipe_lane
//---------- PIPE User Module ----------------------------------------------
pcie_7x_0_core_top_pipe_user #
(
.PCIE_USE_MODE (PCIE_USE_MODE),
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE)
)
pipe_user_i
(
//---------- Input ---------------------------------
.USER_TXUSRCLK (clk_pclk),
.USER_RXUSRCLK (clk_rxusrclk),
.USER_OOBCLK_IN (clk_oobclk),
.USER_RST_N (!rst_cpllreset),
.USER_RXUSRCLK_RST_N (!rst_rxusrclk_reset),
.USER_PCLK_SEL (rate_pclk_sel[i]),
.USER_RESETOVRD_START (rate_resetovrd_start[i]),
.USER_TXRESETDONE (gt_txresetdone[i]),
.USER_RXRESETDONE (gt_rxresetdone[i]),
.USER_TXELECIDLE (PIPE_TXELECIDLE[i]),
.USER_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
.USER_RXCDRLOCK_IN (gt_rxcdrlock[i]),
.USER_RXVALID_IN (gt_rxvalid[i]),
.USER_RXSTATUS_IN (gt_rxstatus[(3*i)+2]),
.USER_PHYSTATUS_IN (gt_phystatus[i]),
.USER_RATE_DONE (rate_done[i]),
.USER_RST_IDLE (rst_idle),
.USER_RATE_RXSYNC (rate_rxsync[i]),
.USER_RATE_IDLE (rate_idle[i]),
.USER_RATE_GEN3 (rate_gen3[i]),
.USER_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
//---------- Output --------------------------------
.USER_OOBCLK (user_oobclk[i]),
.USER_RESETOVRD (user_resetovrd[i]),
.USER_TXPMARESET (user_txpmareset[i]),
.USER_RXPMARESET (user_rxpmareset[i]),
.USER_RXCDRRESET (user_rxcdrreset[i]),
.USER_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
.USER_RXDFELPMRESET (user_rxdfelpmreset[i]),
.USER_EYESCANRESET (user_eyescanreset[i]),
.USER_TXPCSRESET (user_txpcsreset[i]),
.USER_RXPCSRESET (user_rxpcsreset[i]),
.USER_RXBUFRESET (user_rxbufreset[i]),
.USER_RESETOVRD_DONE (user_resetovrd_done[i]),
.USER_RESETDONE (user_resetdone[i]),
.USER_ACTIVE_LANE (user_active_lane[i]),
.USER_RXCDRLOCK_OUT (user_rxcdrlock[i]),
.USER_RXVALID_OUT (PIPE_RXVALID[i]),
.USER_PHYSTATUS_OUT (PIPE_PHYSTATUS[i]),
.USER_PHYSTATUS_RST (PIPE_PHYSTATUS_RST[i]),
.USER_GEN3_RDY (PIPE_GEN3_RDY[i]),
.USER_RX_CONVERGE (user_rx_converge[i])
);
//---------- GTP PIPE Rate Module ------------------------------------------
if (PCIE_GT_DEVICE == "GTP")
begin : gtp_pipe_rate
pcie_7x_0_core_top_gtp_pipe_rate #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP) // PCIe sim speedup
//.PCIE_USE_MODE (PCIE_USE_MODE), // removed for GTP
//.PCIE_PLL_SEL (PCIE_PLL_SEL), // removed for GTP
//.PCIE_POWER_SAVING (PCIE_POWER_SAVING), // removed for GTP
//.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // removed for GTP
//.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // removed for GTP
//.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // removed for GTP
)
gtp_pipe_rate_i
(
//---------- Input -----------------------------
.RATE_CLK (clk_pclk),
.RATE_RST_N (!rst_cpllreset),
//.RATE_RST_IDLE (rst_idle), // removed for GTP
//.RATE_ACTIVE_LANE (user_active_lane[i]), // removed for GTP
.RATE_RATE_IN (PIPE_RATE),
//.RATE_CPLLLOCK (gt_cplllock[i]), // removed for GTP
//.RATE_QPLLLOCK (qpll_qplllock[i>>2]) // removed for GTP
//.RATE_MMCM_LOCK (clk_mmcm_lock), // removed for GTP
.RATE_DRP_DONE (drp_done[i]),
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
//.RATE_TXRESETDONE (gt_txresetdone[i]), // removed for GTP
//.RATE_RXRESETDONE (gt_rxresetdone[i]), // removed for GTP
.RATE_TXRATEDONE (gt_txratedone[i]),
.RATE_RXRATEDONE (gt_rxratedone[i]),
.RATE_PHYSTATUS (gt_phystatus[i]),
//.RATE_RESETOVRD_DONE (user_resetovrd_done[i]), // removed for GTP
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
//.RATE_RXSYNC_DONE (sync_rxsync_done[i]), // removed for GTP
//---------- Output ----------------------------
//.RATE_CPLLPD (rate_cpllpd[i]), // removed for GTP
//.RATE_QPLLPD (rate_qpllpd[i]), // removed for GTP
//.RATE_CPLLRESET (rate_cpllreset[i]), // removed for GTP
//.RATE_QPLLRESET (rate_qpllreset[i]), // removed for GTP
//.RATE_TXPMARESET (rate_txpmareset[i]), // removed for GTP
//.RATE_RXPMARESET (rate_rxpmareset[i]), // removed for GTP
//.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]), // removed for GTP
.RATE_DRP_START (rate_drp_start[i]),
.RATE_DRP_X16 (rate_drp_x16[i]),
.RATE_PCLK_SEL (rate_pclk_sel[i]),
//.RATE_GEN3 (rate_gen3[i]), // removed for GTP
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
//.RATE_RESETOVRD_START (rate_resetovrd_start[i]), // removed for GTP
.RATE_TXSYNC_START (rate_txsync_start[i]),
.RATE_DONE (rate_done[i]),
//.RATE_RXSYNC_START (rate_rxsync_start[i]), // removed for GTP
//.RATE_RXSYNC (rate_rxsync[i]), // removed for GTP
.RATE_IDLE (rate_idle[i]),
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
);
//---------- Default for GTP -----------------------
assign rate_cpllpd[i] = 1'd0;
assign rate_qpllpd[i] = 1'd0;
assign rate_cpllreset[i] = 1'd0;
assign rate_qpllreset[i] = 1'd0;
assign rate_txpmareset[i] = 1'd0;
assign rate_rxpmareset[i] = 1'd0;
assign rate_sysclksel[(2*i)+1:(2*i)] = 2'b0;
assign rate_gen3[i] = 1'd0;
assign rate_resetovrd_start[i] = 1'd0;
assign rate_rxsync_start[i] = 1'd0;
assign rate_rxsync[i] = 1'd0;
end
else
begin : pipe_rate
//---------- PIPE Rate Module ----------------------------------------------
pcie_7x_0_core_top_pipe_rate #
(
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_POWER_SAVING (PCIE_POWER_SAVING),// PCIe power saving
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN) // PCIe RX buffer enable for Gen3 only
)
pipe_rate_i
(
//---------- Input ---------------------------------
.RATE_CLK (clk_pclk),
.RATE_RST_N (!rst_cpllreset),
.RATE_RST_IDLE (rst_idle),
.RATE_ACTIVE_LANE (user_active_lane[i]),
.RATE_RATE_IN (PIPE_RATE),
.RATE_CPLLLOCK (gt_cplllock[i]),
.RATE_QPLLLOCK (qpll_qplllock[i>>2]),
.RATE_MMCM_LOCK (clk_mmcm_lock),
.RATE_DRP_DONE (drp_done[i]),
.RATE_RXPMARESETDONE (gt_rxpmaresetdone[i]),
.RATE_TXRESETDONE (gt_txresetdone[i]),
.RATE_RXRESETDONE (gt_rxresetdone[i]),
.RATE_TXRATEDONE (gt_txratedone[i]),
.RATE_RXRATEDONE (gt_rxratedone[i]),
.RATE_PHYSTATUS (gt_phystatus[i]),
.RATE_RESETOVRD_DONE (user_resetovrd_done[i]),
.RATE_TXSYNC_DONE (sync_txsync_done[i]),
.RATE_RXSYNC_DONE (sync_rxsync_done[i]),
//---------- Output --------------------------------
.RATE_CPLLPD (rate_cpllpd[i]),
.RATE_QPLLPD (rate_qpllpd[i]),
.RATE_CPLLRESET (rate_cpllreset[i]),
.RATE_QPLLRESET (rate_qpllreset[i]),
.RATE_TXPMARESET (rate_txpmareset[i]),
.RATE_RXPMARESET (rate_rxpmareset[i]),
.RATE_SYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.RATE_DRP_START (rate_drp_start[i]),
.RATE_DRP_X16X20_MODE (rate_drp_x16x20_mode[i]),
.RATE_DRP_X16 (rate_drp_x16[i]),
.RATE_PCLK_SEL (rate_pclk_sel[i]),
.RATE_GEN3 (rate_gen3[i]),
.RATE_RATE_OUT (rate_rate[(3*i)+2:(3*i)]),
.RATE_RESETOVRD_START (rate_resetovrd_start[i]),
.RATE_TXSYNC_START (rate_txsync_start[i]),
.RATE_DONE (rate_done[i]),
.RATE_RXSYNC_START (rate_rxsync_start[i]),
.RATE_RXSYNC (rate_rxsync[i]),
.RATE_IDLE (rate_idle[i]),
.RATE_FSM (rate_fsm[(5*i)+4:(5*i)])
);
end
//---------- PIPE Sync Module ----------------------------------------------
pcie_7x_0_core_top_pipe_sync #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT Device
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
.PCIE_LANE (PCIE_LANE), // PCIe lane
.PCIE_LINK_SPEED (PCIE_LINK_SPEED) // PCIe link speed
)
pipe_sync_i
(
//---------- Input ---------------------------------
.SYNC_CLK (clk_pclk),
.SYNC_RST_N (!rst_cpllreset),
.SYNC_SLAVE (i > 0),
.SYNC_GEN3 (rate_gen3[i]),
.SYNC_RATE_IDLE (rate_idle[i]),
.SYNC_MMCM_LOCK (clk_mmcm_lock),
.SYNC_RXELECIDLE (gt_rxelecidle[i]),
.SYNC_RXCDRLOCK (user_rxcdrlock[i]),
.SYNC_ACTIVE_LANE (user_active_lane[i]),
.SYNC_TXSYNC_START (rate_txsync_start[i] || rst_txsync_start),
.SYNC_TXPHINITDONE (&(gt_txphinitdone | (~user_active_lane))),
.SYNC_TXDLYSRESETDONE (txdlysresetdone[i]),
.SYNC_TXPHALIGNDONE (txphaligndone[i]),
.SYNC_TXSYNCDONE (gt_txsyncdone[i]), // GTH
.SYNC_RXSYNC_START (rate_rxsync_start[i]),
.SYNC_RXDLYSRESETDONE (rxdlysresetdone[i]),
.SYNC_RXPHALIGNDONE_M (gt_rxphaligndone[0]),
.SYNC_RXPHALIGNDONE_S (rxphaligndone_s[i]),
.SYNC_RXSYNC_DONEM_IN (sync_rxsync_donem[0]),
.SYNC_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
//---------- Output --------------------------------
.SYNC_TXPHDLYRESET (sync_txphdlyreset[i]),
.SYNC_TXPHALIGN (sync_txphalign[i]),
.SYNC_TXPHALIGNEN (sync_txphalignen[i]),
.SYNC_TXPHINIT (sync_txphinit[i]),
.SYNC_TXDLYBYPASS (sync_txdlybypass[i]),
.SYNC_TXDLYSRESET (sync_txdlysreset[i]),
.SYNC_TXDLYEN (sync_txdlyen[i]),
.SYNC_TXSYNC_DONE (sync_txsync_done[i]),
.SYNC_FSM_TX (sync_fsm_tx[(6*i)+5:(6*i)]),
.SYNC_RXPHALIGN (sync_rxphalign[i]),
.SYNC_RXPHALIGNEN (sync_rxphalignen[i]),
.SYNC_RXDLYBYPASS (sync_rxdlybypass[i]),
.SYNC_RXDLYSRESET (sync_rxdlysreset[i]),
.SYNC_RXDLYEN (sync_rxdlyen[i]),
.SYNC_RXDDIEN (sync_rxddien[i]),
.SYNC_RXSYNC_DONEM_OUT (sync_rxsync_donem[i]),
.SYNC_RXSYNC_DONE (sync_rxsync_done[i]),
.SYNC_FSM_RX (sync_fsm_rx[(7*i)+6:(7*i)])
);
//---------- PIPE Sync Assignments -----------------------------------------
assign txdlysresetdone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txdlysresetdone[i] : >_txdlysresetdone;
assign txphaligndone[i] = (PCIE_TXSYNC_MODE == 1) ? gt_txphaligndone[i] : &(gt_txphaligndone | (~user_active_lane));
assign rxdlysresetdone[i] = (PCIE_RXSYNC_MODE == 1) ? gt_rxdlysresetdone[i] : >_rxdlysresetdone;
assign rxphaligndone_s[i] = (PCIE_LANE == 1) ? 1'd0 : >_rxphaligndone[PCIE_LANE:1];
//---------- GTP PIPE DRP Module -------------------------------------------
if (PCIE_GT_DEVICE == "GTP")
begin : gtp_pipe_drp
//---------- GTP PIPE DRP Module ---------------------------------------
pcie_7x_0_core_top_gtp_pipe_drp
gtp_pipe_drp_i
(
//---------- Input ---------------------------------
.DRP_CLK (clk_dclk),
.DRP_RST_N (!rst_dclk_reset),
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
.DRP_START (rst_drp_start || rate_drp_start[i]),
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
.DRP_RDY (gt_rdy[i]),
//---------- Output --------------------------------
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
.DRP_EN (drp_en[i]),
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
.DRP_WE (drp_we[i]),
.DRP_DONE (drp_done[i]),
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
);
end
else
begin : pipe_drp
//---------- PIPE DRP Module -------------------------------------------
pcie_7x_0_core_top_pipe_drp #
(
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_AUX_CDR_GEN3_EN (PCIE_AUX_CDR_GEN3_EN), // PCIe AUX CDR Gen3 enable
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_RXBUF_EN (PCIE_RXBUF_EN), // PCIe RX buffer enable for Gen3 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE) // PCIe RX sync mode
)
pipe_drp_i
(
//---------- Input ---------------------------------
.DRP_CLK (clk_dclk),
.DRP_RST_N (!rst_dclk_reset),
.DRP_GTXRESET (rst_gtreset),
.DRP_RATE (PIPE_RATE),
.DRP_X16X20_MODE (rst_drp_x16x20_mode || rate_drp_x16x20_mode[i]),
.DRP_X16 (rst_drp_x16 || rate_drp_x16[i]),
.DRP_START (rst_drp_start || rate_drp_start[i]),
.DRP_DO (gt_do[(16*i)+15:(16*i)]),
.DRP_RDY (gt_rdy[i]),
//---------- Output --------------------------------
.DRP_ADDR (drp_addr[(9*i)+8:(9*i)]),
.DRP_EN (drp_en[i]),
.DRP_DI (drp_di[(16*i)+15:(16*i)]),
.DRP_WE (drp_we[i]),
.DRP_DONE (drp_done[i]),
.DRP_FSM (drp_fsm[(3*i)+2:(3*i)])
);
end
assign jtag_sl_oport[((i+1)*17)-1 : (i*17)] = 17'd0;
assign jtag_sl_addr[(17*i)+16:(17*i)] = 17'd0;
assign jtag_sl_den[i] = 1'd0;
assign jtag_sl_di[(16*i)+15:(16*i)] = 16'd0;
assign jtag_sl_we[i] = 1'd0;
//---------- Generate DRP MUX ----------------------------------------------
assign PIPE_JTAG_RDY[i] = (drp_fsm[(3*i)+2:(3*i)] == 3'b000);
assign jtag_sl_en[i] = (jtag_sl_addr[(17*i)+16:(17*i)+9] == 8'd0) ? jtag_sl_den[i] : 1'd0;
// Channel DRP
assign drp_mux_en[i] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPEN[i] : drp_en[i];
assign drp_mux_di[(16*i)+15:(16*i)] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPDI[(16*i)+15:(16*i)] : drp_di[(16*i)+15:(16*i)];
assign drp_mux_addr[(9*i)+8:(9*i)] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPADDR[(9*i)+8:(9*i)] : drp_addr[(9*i)+8:(9*i)];
assign drp_mux_we[i] = (PIPE_JTAG_RDY[i] && EXT_CH_GT_DRP) ? EXT_CH_GT_DRPWE[i] : drp_we[i];
//---------- Generate PIPE EQ ----------------------------------------------
if (PCIE_LINK_SPEED == 3)
begin : pipe_eq
//---------- PIPE EQ Module --------------------------------------------
pcie_7x_0_core_top_pipe_eq #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE),
.PCIE_RXEQ_MODE_GEN3 (PCIE_RXEQ_MODE_GEN3) // PCIe RX equalization mode
)
pipe_eq_i
(
//---------- Input -----------------------------
.EQ_CLK (clk_pclk),
.EQ_RST_N (!rst_cpllreset),
.EQ_GEN3 (rate_gen3[i]),
.EQ_TXEQ_CONTROL (PIPE_TXEQ_CONTROL[(2*i)+1:(2*i)]),
.EQ_TXEQ_PRESET (PIPE_TXEQ_PRESET[(4*i)+3:(4*i)]),
.EQ_TXEQ_PRESET_DEFAULT (PIPE_TXEQ_PRESET_DEFAULT[(4*i)+3:(4*i)]),
.EQ_TXEQ_DEEMPH_IN (PIPE_TXEQ_DEEMPH[(6*i)+5:(6*i)]), // renamed
.EQ_RXEQ_CONTROL (PIPE_RXEQ_CONTROL[(2*i)+1:(2*i)]),
.EQ_RXEQ_PRESET (PIPE_RXEQ_PRESET[(3*i)+2:(3*i)]),
.EQ_RXEQ_LFFS (PIPE_RXEQ_LFFS[(6*i)+5:(6*i)]),
.EQ_RXEQ_TXPRESET (PIPE_RXEQ_TXPRESET[(4*i)+3:(4*i)]),
.EQ_RXEQ_USER_EN (PIPE_RXEQ_USER_EN[i]),
.EQ_RXEQ_USER_TXCOEFF (PIPE_RXEQ_USER_TXCOEFF[(18*i)+17:(18*i)]),
.EQ_RXEQ_USER_MODE (PIPE_RXEQ_USER_MODE[i]),
//---------- Output ----------------------------
.EQ_TXEQ_DEEMPH (eq_txeq_deemph[i]),
.EQ_TXEQ_PRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
.EQ_TXEQ_MAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
.EQ_TXEQ_POSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
.EQ_TXEQ_DEEMPH_OUT (PIPE_TXEQ_COEFF[(18*i)+17:(18*i)]),// renamed
.EQ_TXEQ_DONE (PIPE_TXEQ_DONE[i]),
.EQ_TXEQ_FSM (PIPE_TXEQ_FSM[(6*i)+5:(6*i)]),
.EQ_RXEQ_NEW_TXCOEFF (PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)]),
.EQ_RXEQ_LFFS_SEL (PIPE_RXEQ_LFFS_SEL[i]),
.EQ_RXEQ_ADAPT_DONE (eq_rxeq_adapt_done[i]),
.EQ_RXEQ_DONE (PIPE_RXEQ_DONE[i]),
.EQ_RXEQ_FSM (PIPE_RXEQ_FSM[(6*i)+5:(6*i)])
);
end
else
//---------- PIPE EQ Defaults ------------------------------------------
begin : pipe_eq_disable
assign eq_txeq_deemph[i] = 1'd0;
assign eq_txeq_precursor[(5*i)+4:(5*i)] = 5'h00;
assign eq_txeq_maincursor[(7*i)+6:(7*i)] = 7'h00;
assign eq_txeq_postcursor[(5*i)+4:(5*i)] = 5'h00;
assign eq_rxeq_adapt_done[i] = 1'd0;
assign PIPE_TXEQ_COEFF[(18*i)+17:(18*i)] = 18'd0;
assign PIPE_TXEQ_DONE[i] = 1'd0;
assign PIPE_TXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
assign PIPE_RXEQ_NEW_TXCOEFF[(18*i)+17:(18*i)] = 18'd0;
assign PIPE_RXEQ_LFFS_SEL[i] = 1'd0;
assign PIPE_RXEQ_ADAPT_DONE[i] = 1'd0;
assign PIPE_RXEQ_DONE[i] = 1'd0;
assign PIPE_RXEQ_FSM[(6*i)+5:(6*i)] = 6'd0;
end
//---------- Generate PIPE Common Per Quad for Gen3 ------------------------
if ((i%4)==0)
begin : pipe_quad
//---------- Generate QPLL Powerdown and Reset -------------------------
assign qpllpd = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllpd : qrst_qpllpd;
assign qpllreset[i>>2] = (PCIE_GT_DEVICE == "GTP") ? gtp_rst_qpllreset : (qrst_qpllreset || qdrp_qpllreset[i>>2]);
if ((PCIE_LINK_SPEED == 3) || (PCIE_PLL_SEL == "QPLL") || (PCIE_GT_DEVICE == "GTP"))
begin : gt_common_enabled
if (PCIE_EXT_GT_COMMON == "FALSE")
begin : gt_common_int
//---------- GT COMMON INTERNAL Module ---------------------------------------
pcie_7x_0_core_top_gt_common #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ) // PCIe reference clock frequency
)
gt_common_i
(
//---------- Input -------------------------
.CPLLPDREFCLK (gt_cpllpdrefclk),
.PIPE_CLK (PIPE_CLK),
.QPLL_QPLLPD (qpllpd),
.QPLL_QPLLRESET (qpllreset[i>>2]),
.QPLL_DRP_CLK (clk_dclk),
.QPLL_DRP_RST_N (rst_dclk_reset),
.QPLL_DRP_OVRD (qrst_ovrd),
.QPLL_DRP_GEN3 (&rate_gen3),
.QPLL_DRP_START (qrst_drp_start),
.QPLL_DRP_CRSCODE (qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))]),
.QPLL_DRP_FSM (qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))]),
.QPLL_DRP_DONE (qdrp_done[i>>2]),
.QPLL_DRP_RESET (qdrp_qpllreset[i>>2]),
.QPLL_QPLLOUTCLK (qpll_qplloutclk[i>>2]),
.QPLL_QPLLOUTREFCLK (qpll_qplloutrefclk[i>>2]),
.QPLL_QPLLLOCK (qpll_qplllock[i>>2])
);
assign QPLL_QPLLPD = 1'b0;
assign QPLL_QPLLRESET[i>>2] = 1'b0;
assign QPLL_DRP_CLK = 1'b0;
assign QPLL_DRP_RST_N = 1'b0;
assign QPLL_DRP_OVRD = 1'b0;
assign QPLL_DRP_GEN3 = 1'b0;
assign QPLL_DRP_START = 1'b0;
assign INT_QPLLLOCK_OUT[i>>2] = qpll_qplllock[i>>2] ;
assign INT_QPLLOUTREFCLK_OUT[i>>2] = qpll_qplloutrefclk[i>>2];
assign INT_QPLLOUTCLK_OUT[i>>2] = qpll_qplloutclk[i>>2];
end
else
begin : gt_common_ext
assign qdrp_done[i>>2] = QPLL_DRP_DONE[i>>2];
assign qdrp_qpllreset[i>>2] = QPLL_DRP_RESET[i>>2];
assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = QPLL_DRP_CRSCODE[(6*(i>>2))+5:(6*(i>>2))];
assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = QPLL_DRP_FSM[(9*(i>>2))+8:(9*(i>>2))];
assign qpll_qplloutclk[i>>2] = QPLL_QPLLOUTCLK[i>>2];
assign qpll_qplloutrefclk[i>>2] = QPLL_QPLLOUTREFCLK[i>>2];
assign qpll_qplllock[i>>2] = QPLL_QPLLLOCK[i>>2];
assign QPLL_QPLLPD = qpllpd;
assign QPLL_QPLLRESET[i>>2] = qpllreset[i>>2];
assign QPLL_DRP_CLK = clk_dclk;
assign QPLL_DRP_RST_N = rst_dclk_reset;
assign QPLL_DRP_OVRD = qrst_ovrd;
assign QPLL_DRP_GEN3 = &rate_gen3;
assign QPLL_DRP_START = qrst_drp_start;
assign INT_QPLLLOCK_OUT[i>>2] = 1'b0;
assign INT_QPLLOUTCLK_OUT[i>>2] = 1'b0;
assign INT_QPLLOUTREFCLK_OUT[i>>2] = 1'b0;
end
end
else
//---------- PIPE Common Defaults ----------------------------------
begin : gt_common_disabled
assign qdrp_done[i>>2] = 1'd0;
assign qdrp_crscode[(6*(i>>2))+5:(6*(i>>2))] = 6'd0;
assign qdrp_fsm[(9*(i>>2))+8:(9*(i>>2))] = 9'd0;
assign qpll_qplloutclk[i>>2] = 1'd0;
assign qpll_qplloutrefclk[i>>2] = 1'd0;
assign qpll_qplllock[i>>2] = 1'd0;
assign QPLL_QPLLPD = 1'b0;
assign QPLL_QPLLRESET[i>>2] = 1'b0;
assign QPLL_DRP_CLK = 1'b0;
assign QPLL_DRP_RST_N = 1'b0;
assign QPLL_DRP_OVRD = 1'b0;
assign QPLL_DRP_GEN3 = 1'b0;
assign QPLL_DRP_START = 1'b0;
assign INT_QPLLLOCK_OUT[i>>2] = 1'b0;
assign INT_QPLLOUTCLK_OUT[i>>2] = 1'b0;
assign INT_QPLLOUTREFCLK_OUT[i>>2] = 1'b0;
end
end
//---------- GT Wrapper ----------------------------------------------------
assign gt_txpmareset_i[i] = (user_txpmareset[i] || rate_txpmareset[i]);
assign gt_rxpmareset_i[i] = (user_rxpmareset[i] || rate_rxpmareset[i]);
pcie_7x_0_core_top_gt_wrapper #
(
.PCIE_SIM_MODE (PCIE_SIM_MODE), // PCIe sim mode
.PCIE_SIM_SPEEDUP (PCIE_SIM_SPEEDUP), // PCIe sim speedup
.PCIE_SIM_TX_EIDLE_DRIVE_LEVEL (PCIE_SIM_TX_EIDLE_DRIVE_LEVEL), // PCIe sim TX electrical idle drive level
.PCIE_GT_DEVICE (PCIE_GT_DEVICE), // PCIe GT device
.PCIE_USE_MODE (PCIE_USE_MODE), // PCIe use mode
.PCIE_PLL_SEL (PCIE_PLL_SEL), // PCIe PLL select for Gen1/Gen2 only
.PCIE_LPM_DFE (PCIE_LPM_DFE), // PCIe LPM or DFE mode for Gen1/Gen2 only
.PCIE_LPM_DFE_GEN3 (PCIE_LPM_DFE_GEN3), // PCIe LPM or DFE mode for Gen3 only
.PCIE_ASYNC_EN (PCIE_ASYNC_EN), // PCIe async enable
.PCIE_TXBUF_EN (PCIE_TXBUF_EN), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_TXSYNC_MODE (PCIE_TXSYNC_MODE), // PCIe TX sync mode
.PCIE_RXSYNC_MODE (PCIE_RXSYNC_MODE), // PCIe RX sync mode
.PCIE_CHAN_BOND (PCIE_CHAN_BOND), // PCIe Channel bonding mode
.PCIE_CHAN_BOND_EN (PCIE_CHAN_BOND_EN), // PCIe Channel bonding enable for Gen1/Gen2 only
.PCIE_LANE (PCIE_LANE), // PCIe number of lane
.PCIE_REFCLK_FREQ (PCIE_REFCLK_FREQ), // PCIe reference clock frequency
.PCIE_TX_EIDLE_ASSERT_DELAY (PCIE_TX_EIDLE_ASSERT_DELAY), // PCIe TX electrical idle assert delay
.PCIE_OOBCLK_MODE (PCIE_OOBCLK_MODE), // PCIe OOB clock mode
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4),
.PCIE_DEBUG_MODE (PCIE_DEBUG_MODE) // PCIe debug mode
)
gt_wrapper_i
(
//---------- GT User Ports -------------------------
.GT_MASTER (i == 0),
.GT_GEN3 (rate_gen3[i]),
.GT_RX_CONVERGE (&user_rx_converge),
//---------- GT Clock Ports ------------------------
.GT_GTREFCLK0 (PIPE_CLK),
.GT_QPLLCLK (qpll_qplloutclk[i>>2]),
.GT_QPLLREFCLK (qpll_qplloutrefclk[i>>2]),
.GT_TXUSRCLK (clk_pclk),
.GT_RXUSRCLK (clk_rxusrclk),
.GT_TXUSRCLK2 (clk_pclk),
.GT_RXUSRCLK2 (clk_rxusrclk),
.GT_OOBCLK (oobclk[i]),
.GT_TXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.GT_RXSYSCLKSEL (rate_sysclksel[(2*i)+1:(2*i)]),
.GT_CPLLPDREFCLK (gt_cpllpdrefclk),
.GT_TXOUTCLK (gt_txoutclk[i]),
.GT_RXOUTCLK (gt_rxoutclk[i]),
.GT_CPLLLOCK (gt_cplllock[i]),
.GT_RXCDRLOCK (gt_rxcdrlock[i]),
//---------- GT Reset Ports ------------------------
.GT_CPLLPD (rst_cpllpd || rate_cpllpd[i]),
.GT_CPLLRESET (rst_cpllreset || rate_cpllreset[i]),
.GT_TXUSERRDY (rst_userrdy),
.GT_RXUSERRDY (rst_userrdy),
.GT_RESETOVRD (user_resetovrd[i]),
.GT_GTTXRESET (rst_gtreset),
.GT_GTRXRESET (rst_gtreset),
.GT_TXPMARESET (gt_txpmareset_i[i]), // (user_txpmareset[i] || rate_txpmareset[i]),
.GT_RXPMARESET (gt_rxpmareset_i[i]), // (user_rxpmareset[i] || rate_rxpmareset[i]),
.GT_RXCDRRESET (user_rxcdrreset[i]),
.GT_RXCDRFREQRESET (user_rxcdrfreqreset[i]),
.GT_RXDFELPMRESET (user_rxdfelpmreset[i]),
.GT_EYESCANRESET (user_eyescanreset[i]),
.GT_TXPCSRESET (user_txpcsreset[i]),
.GT_RXPCSRESET (user_rxpcsreset[i]),
.GT_RXBUFRESET (user_rxbufreset[i]),
.GT_EYESCANDATAERROR (gt_eyescandataerror[i]),
.GT_TXRESETDONE (gt_txresetdone[i]),
.GT_RXRESETDONE (gt_rxresetdone[i]),
.GT_RXPMARESETDONE (gt_rxpmaresetdone[i]),
//---------- GT TX Data Ports ----------------------
.GT_TXDATA (PIPE_TXDATA[(32*i)+31:(32*i)]),
.GT_TXDATAK (PIPE_TXDATAK[(4*i)+3:(4*i)]),
.GT_TXP (PIPE_TXP[i]),
.GT_TXN (PIPE_TXN[i]),
//---------- GT RX Data Ports ----------------------
.GT_RXP (PIPE_RXP[i]),
.GT_RXN (PIPE_RXN[i]),
.GT_RXDATA (PIPE_RXDATA[(32*i)+31:(32*i)]),
.GT_RXDATAK (PIPE_RXDATAK[(4*i)+3:(4*i)]),
//---------- GT Command Ports ----------------------
.GT_TXDETECTRX (PIPE_TXDETECTRX),
.GT_TXELECIDLE (PIPE_TXELECIDLE[i]),
.GT_TXCOMPLIANCE (PIPE_TXCOMPLIANCE[i]),
.GT_RXPOLARITY (PIPE_RXPOLARITY[i]),
.GT_TXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
.GT_RXPOWERDOWN (PIPE_POWERDOWN[(2*i)+1:(2*i)]),
.GT_TXRATE (rate_rate[(3*i)+2:(3*i)]),
.GT_RXRATE (rate_rate[(3*i)+2:(3*i)]),
//---------- GT Electrical Command Ports -----------
.GT_TXMARGIN (PIPE_TXMARGIN),
.GT_TXSWING (PIPE_TXSWING),
.GT_TXDEEMPH (PIPE_TXDEEMPH[i]),
.GT_TXPRECURSOR (eq_txeq_precursor[(5*i)+4:(5*i)]),
.GT_TXMAINCURSOR (eq_txeq_maincursor[(7*i)+6:(7*i)]),
.GT_TXPOSTCURSOR (eq_txeq_postcursor[(5*i)+4:(5*i)]),
//---------- GT Status Ports -----------------------
.GT_RXVALID (gt_rxvalid[i]),
.GT_PHYSTATUS (gt_phystatus[i]),
.GT_RXELECIDLE (gt_rxelecidle[i]),
.GT_RXSTATUS (gt_rxstatus[(3*i)+2:(3*i)]),
.GT_RXBUFSTATUS (gt_rxbufstatus[(3*i)+2:(3*i)]),
.GT_TXRATEDONE (gt_txratedone[i]),
.GT_RXRATEDONE (gt_rxratedone[i]),
.GT_RXDISPERR (gt_rxdisperr[(8*i)+7:(8*i)]),
.GT_RXNOTINTABLE (gt_rxnotintable[(8*i)+7:(8*i)]),
//---------- GT DRP Ports --------------------------
.GT_DRPCLK (clk_dclk),
.GT_DRPADDR (drp_mux_addr[(9*i)+8:(9*i)]),
.GT_DRPEN (drp_mux_en[i]),
.GT_DRPDI (drp_mux_di[(16*i)+15:(16*i)]),
.GT_DRPWE (drp_mux_we[i]),
.GT_DRPDO (gt_do[(16*i)+15:(16*i)]),
.GT_DRPRDY (gt_rdy[i]),
//---------- GT TX Sync Ports ----------------------
.GT_TXPHALIGN (sync_txphalign[i]),
.GT_TXPHALIGNEN (sync_txphalignen[i]),
.GT_TXPHINIT (sync_txphinit[i]),
.GT_TXDLYBYPASS (sync_txdlybypass[i]),
.GT_TXDLYSRESET (sync_txdlysreset[i]),
.GT_TXDLYEN (sync_txdlyen[i]),
.GT_TXDLYSRESETDONE (gt_txdlysresetdone[i]),
.GT_TXPHINITDONE (gt_txphinitdone[i]),
.GT_TXPHALIGNDONE (gt_txphaligndone[i]),
.GT_TXPHDLYRESET (sync_txphdlyreset[i]),
.GT_TXSYNCMODE (i == 0), // GTH, GTP
.GT_TXSYNCIN (gt_txsyncout[0]), // GTH, GTP
.GT_TXSYNCALLIN (txsyncallin), // GTH, GTP
.GT_TXSYNCOUT (gt_txsyncout[i]), // GTH, GTP
.GT_TXSYNCDONE (gt_txsyncdone[i]), // GTH, GTP
//---------- GT RX Sync Ports ----------------------
.GT_RXPHALIGN (sync_rxphalign[i]),
.GT_RXPHALIGNEN (sync_rxphalignen[i]),
.GT_RXDLYBYPASS (sync_rxdlybypass[i]),
.GT_RXDLYSRESET (sync_rxdlysreset[i]),
.GT_RXDLYEN (sync_rxdlyen[i]),
.GT_RXDDIEN (sync_rxddien[i]),
.GT_RXDLYSRESETDONE (gt_rxdlysresetdone[i]),
.GT_RXPHALIGNDONE (gt_rxphaligndone[i]),
.GT_RXSYNCMODE (i == 0), // GTH
.GT_RXSYNCIN (gt_rxsyncout[0]), // GTH
.GT_RXSYNCALLIN (rxsyncallin), // GTH
.GT_RXSYNCOUT (gt_rxsyncout[i]), // GTH
.GT_RXSYNCDONE (gt_rxsyncdone[i]), // GTH
//---------- GT Comma Alignment Ports --------------
.GT_RXSLIDE (PIPE_RXSLIDE[i]),
.GT_RXCOMMADET (gt_rxcommadet[i]),
.GT_RXCHARISCOMMA (gt_rxchariscomma[(4*i)+3:(4*i)]),
.GT_RXBYTEISALIGNED (gt_rxbyteisaligned[i]),
.GT_RXBYTEREALIGN (gt_rxbyterealign[i]),
//---------- GT Channel Bonding Ports --------------
.GT_RXCHANISALIGNED (PIPE_RXCHANISALIGNED[i]),
.GT_RXCHBONDEN (rxchbonden[i]),
.GT_RXCHBONDI (gt_rxchbondi[i]),
.GT_RXCHBONDLEVEL (gt_rxchbondlevel[(3*i)+2:(3*i)]),
.GT_RXCHBONDMASTER (rxchbondmaster[i]),
.GT_RXCHBONDSLAVE (rxchbondslave[i]),
.GT_RXCHBONDO (gt_rxchbondo[i+1]),
//---------- GT PRBS/Loopback Ports ----------------
.GT_TXPRBSSEL (PIPE_TXPRBSSEL),
.GT_RXPRBSSEL (PIPE_RXPRBSSEL),
.GT_TXPRBSFORCEERR (PIPE_TXPRBSFORCEERR),
.GT_RXPRBSCNTRESET (PIPE_RXPRBSCNTRESET),
.GT_LOOPBACK (PIPE_LOOPBACK),
.GT_RXPRBSERR (PIPE_RXPRBSERR[i]),
//---------- GT Debug Port -------------------------
.GT_DMONITOROUT (PIPE_DMONITOROUT[(15*i)+14:(15*i)])
);
//---------- GT Wrapper Assignments ----------------------------------------
assign oobclk[i] = (PCIE_OOBCLK_MODE == 1) ? user_oobclk[i] : clk_oobclk;
//---------- Channel Bonding Master Slave Enable ---------------------------
if (PCIE_CHAN_BOND_EN == "FALSE")
begin : channel_bonding_ms_disable
assign rxchbonden[i] = 1'd0;
assign rxchbondmaster[i] = 1'd0;
assign rxchbondslave[i] = 1'd0;
end
else
begin : channel_bonding_ms_enable
assign rxchbonden[i] = (PCIE_LANE > 1) && (PCIE_CHAN_BOND_EN == "TRUE") ? !rate_gen3[i] : 1'd0;
assign rxchbondmaster[i] = rate_gen3[i] ? 1'd0 : (i == 0);
assign rxchbondslave[i] = rate_gen3[i] ? 1'd0 : (i > 0);
end
//---------- Channel Bonding Input Connection ------------------------------
if (PCIE_CHAN_BOND_EN == "FALSE")
begin : channel_bonding_in_disable
assign gt_rxchbondi[i] = 5'd0;
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
end
else
begin : channel_bonding_in_enable
//---------- Channel Bonding (2: Binary-Tree) --------------------------
if (PCIE_CHAN_BOND == 2)
begin : channel_bonding_a
case (i)
//---------- Lane 0 --------------------------------
0 :
begin
assign gt_rxchbondi[0] = gt_rxchbondo[0];
assign gt_rxchbondlevel[2:0] = (PCIE_LANE == 4'd8) ? 3'd4 :
(PCIE_LANE > 4'd5) ? 3'd3 :
(PCIE_LANE > 4'd3) ? 3'd2 :
(PCIE_LANE > 4'd1) ? 3'd1 : 3'd0;
end
//---------- Lane 1 --------------------------------
1 :
begin
assign gt_rxchbondi[1] = gt_rxchbondo[1];
assign gt_rxchbondlevel[5:3] = (PCIE_LANE == 4'd8) ? 3'd3 :
(PCIE_LANE > 4'd5) ? 3'd2 :
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
end
//---------- Lane 2 --------------------------------
2 :
begin
assign gt_rxchbondi[2] = gt_rxchbondo[1];
assign gt_rxchbondlevel[8:6] = (PCIE_LANE == 4'd8) ? 3'd3 :
(PCIE_LANE > 4'd5) ? 3'd2 :
(PCIE_LANE > 4'd3) ? 3'd1 : 3'd0;
end
//---------- Lane 3 --------------------------------
3 :
begin
assign gt_rxchbondi[3] = gt_rxchbondo[3];
assign gt_rxchbondlevel[11:9] = (PCIE_LANE == 4'd8) ? 3'd2 :
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
end
//---------- Lane 4 --------------------------------
4 :
begin
assign gt_rxchbondi[4] = gt_rxchbondo[3];
assign gt_rxchbondlevel[14:12] = (PCIE_LANE == 4'd8) ? 3'd2 :
(PCIE_LANE > 4'd5) ? 3'd1 : 3'd0;
end
//---------- Lane 5 --------------------------------
5 :
begin
assign gt_rxchbondi[5] = gt_rxchbondo[5];
assign gt_rxchbondlevel[17:15] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
end
//---------- Lane 6 --------------------------------
6 :
begin
assign gt_rxchbondi[6] = gt_rxchbondo[5];
assign gt_rxchbondlevel[20:18] = (PCIE_LANE == 4'd8) ? 3'd1 : 3'd0;
end
//---------- Lane 7 --------------------------------
7 :
begin
assign gt_rxchbondi[7] = gt_rxchbondo[7];
assign gt_rxchbondlevel[23:21] = 3'd0;
end
//---------- Default -------------------------------
default :
begin
assign gt_rxchbondi[i] = gt_rxchbondo[7];
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = 3'd0;
end
endcase
end
//---------- Channel Bonding (0: One-Hop, 1: Daisy Chain) --------------
else
begin : channel_bonding_b
assign gt_rxchbondi[i] = (PCIE_CHAN_BOND == 1) ? gt_rxchbondo[i] : ((i == 0) ? gt_rxchbondo[0] : gt_rxchbondo[1]);
assign gt_rxchbondlevel[(3*i)+2:(3*i)] = (PCIE_CHAN_BOND == 1) ? (PCIE_LANE-1)-i : ((PCIE_LANE > 1) && (i == 0));
end
end
end
endgenerate
//---------- PIPE Wrapper Output -----------------------------------------------
assign PIPE_TXEQ_FS = 0;//TXEQ_FS;
assign PIPE_TXEQ_LF = 0;//TXEQ_LF;
assign PIPE_RXELECIDLE = gt_rxelecidle;
assign PIPE_RXSTATUS = gt_rxstatus;
assign PIPE_RXDISPERR = gt_rxdisperr;
assign PIPE_RXNOTINTABLE = gt_rxnotintable;
assign PIPE_RXPMARESETDONE = gt_rxpmaresetdone;
assign PIPE_RXBUFSTATUS = gt_rxbufstatus;
assign PIPE_TXPHALIGNDONE = gt_txphaligndone;
assign PIPE_TXPHINITDONE = gt_txphinitdone;
assign PIPE_TXDLYSRESETDONE = gt_txdlysresetdone;
assign PIPE_RXPHALIGNDONE = gt_rxphaligndone;
assign PIPE_RXDLYSRESETDONE = gt_rxdlysresetdone;
assign PIPE_RXSYNCDONE = gt_rxsyncdone;
assign PIPE_RXCOMMADET = gt_rxcommadet;
assign PIPE_QPLL_LOCK = qpll_qplllock;
assign PIPE_CPLL_LOCK = gt_cplllock;
assign PIPE_PCLK = clk_pclk;
assign PIPE_PCLK_LOCK = clk_mmcm_lock;
assign PIPE_RXCDRLOCK = 0;//user_rxcdrlock;
assign PIPE_RXUSRCLK = 0;//clk_rxusrclk;
assign PIPE_RXOUTCLK = 0;//clk_rxoutclk;
assign PIPE_TXSYNC_DONE = 0;//sync_txsync_done;
assign PIPE_RXSYNC_DONE = 0;//sync_rxsync_done;
assign PIPE_ACTIVE_LANE = 0;//user_active_lane;
assign PIPE_TXOUTCLK_OUT = gt_txoutclk[0];
assign PIPE_RXOUTCLK_OUT = gt_rxoutclk;
assign PIPE_PCLK_SEL_OUT = rate_pclk_sel;
assign PIPE_GEN3_OUT = rate_gen3[0];
assign PIPE_RXEQ_CONVERGE = user_rx_converge;
assign PIPE_RXEQ_ADAPT_DONE = (PCIE_GT_DEVICE == "GTP") ? {PCIE_LANE{1'd0}} : eq_rxeq_adapt_done;
assign PIPE_EYESCANDATAERROR = gt_eyescandataerror;
assign PIPE_RST_FSM = rst_fsm;
assign PIPE_QRST_FSM = qrst_fsm;
assign PIPE_RATE_FSM = rate_fsm;
assign PIPE_SYNC_FSM_TX = sync_fsm_tx;
assign PIPE_SYNC_FSM_RX = sync_fsm_rx;
assign PIPE_DRP_FSM = drp_fsm;
assign PIPE_QDRP_FSM = 0;//qdrp_fsm;
assign PIPE_RST_IDLE = &rst_idle;
assign PIPE_QRST_IDLE = &qrst_idle;
assign PIPE_RATE_IDLE = &rate_idle;
assign EXT_CH_GT_DRPDO = gt_do[(PCIE_LANE*16)-1:0];
assign EXT_CH_GT_DRPRDY = gt_rdy[(PCIE_LANE-1):0];
assign EXT_CH_GT_DRPCLK = clk_dclk;
assign PIPE_DEBUG_0 = (PCIE_DEBUG_MODE == 1) ? gt_txresetdone : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_1 = (PCIE_DEBUG_MODE == 1) ? gt_rxresetdone : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_2 = (PCIE_DEBUG_MODE == 1) ? gt_phystatus : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_3 = (PCIE_DEBUG_MODE == 1) ? gt_rxvalid : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_4 = (PCIE_DEBUG_MODE == 1) ? clk_dclk : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_5 = (PCIE_DEBUG_MODE == 1) ? drp_mux_en : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_6 = (PCIE_DEBUG_MODE == 1) ? drp_mux_we : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_7 = (PCIE_DEBUG_MODE == 1) ? gt_rdy : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_8 = (PCIE_DEBUG_MODE == 1) ? user_rx_converge : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG_9 = (PCIE_DEBUG_MODE == 1) ? PIPE_TXELECIDLE : {PCIE_LANE{1'b0}};
assign PIPE_DEBUG[ 1:0] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_CONTROL[1:0] : 2'd0;
assign PIPE_DEBUG[ 5:2] = (PCIE_DEBUG_MODE == 1) ? PIPE_TXEQ_PRESET[3:0] : 4'd0;
assign PIPE_DEBUG[31:6] = 26'd0;
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// d_KES_PE_ELU_MINodr.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH Page Decoder
// Module Name: d_KES_PE_ELU_MINodr
// File Name: d_KES_PE_ELU_MINodr.v
//
// Version: v1.1.1-256B_T14
//
// Description:
// - Processing Element: Error Locator Update module, minimum order
// - for binary version of inversion-less Berlekamp-Massey algorithm (iBM.b)
// - for data area
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.1.1
// - minor modification for releasing
//
// * v1.1.0
// - change state machine: divide states
// - insert additional registers
// - improve frequency characteristic
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`include "d_KES_parameters.vh"
`timescale 1ns / 1ps
module d_KES_PE_ELU_MINodr // error locate update module: minimum order
(
input wire i_clk,
input wire i_RESET_KES,
input wire i_stop_dec,
input wire i_EXECUTE_PE_ELU,
input wire [`D_KES_GF_ORDER-1:0] i_delta_2im2,
output reg [`D_KES_GF_ORDER-1:0] o_v_2i_X,
output reg o_v_2i_X_deg_chk_bit,
output reg [`D_KES_GF_ORDER-1:0] o_k_2i_X
);
parameter [11:0] D_KES_VALUE_ZERO = 12'b0000_0000_0000;
parameter [11:0] D_KES_VALUE_ONE = 12'b0000_0000_0001;
// FSM parameters
parameter PE_ELU_RST = 2'b01; // reset
parameter PE_ELU_OUT = 2'b10; // output buffer update
// variable declaration
reg [1:0] r_cur_state;
reg [1:0] r_nxt_state;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X_term_A;
wire [`D_KES_GF_ORDER-1:0] w_v_2ip2_X;
wire [`D_KES_GF_ORDER-1:0] w_k_2ip2_X;
// update current state to next state
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin
r_cur_state <= PE_ELU_RST;
end else begin
r_cur_state <= r_nxt_state;
end
end
// decide next state
always @ ( * )
begin
case (r_cur_state)
PE_ELU_RST: begin
r_nxt_state <= (i_EXECUTE_PE_ELU)? (PE_ELU_OUT):(PE_ELU_RST);
end
PE_ELU_OUT: begin
r_nxt_state <= PE_ELU_RST;
end
default: begin
r_nxt_state <= PE_ELU_RST;
end
endcase
end
// state behaviour
always @ (posedge i_clk)
begin
if ((i_RESET_KES) || (i_stop_dec)) begin // initializing
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= D_KES_VALUE_ONE[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= 1;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= D_KES_VALUE_ONE[`D_KES_GF_ORDER-1:0];
end
else begin
case (r_nxt_state)
PE_ELU_RST: begin // hold original data
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= o_v_2i_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= o_v_2i_X_deg_chk_bit;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= o_k_2i_X[`D_KES_GF_ORDER-1:0];
end
PE_ELU_OUT: begin // output update only
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= w_v_2ip2_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= |(w_v_2ip2_X[`D_KES_GF_ORDER-1:0]);
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= w_k_2ip2_X[`D_KES_GF_ORDER-1:0];
end
default: begin
o_v_2i_X[`D_KES_GF_ORDER-1:0] <= o_v_2i_X[`D_KES_GF_ORDER-1:0];
o_v_2i_X_deg_chk_bit <= o_v_2i_X_deg_chk_bit;
o_k_2i_X[`D_KES_GF_ORDER-1:0] <= o_k_2i_X[`D_KES_GF_ORDER-1:0];
end
endcase
end
end
d_parallel_FFM_gate_GF12 d_delta_2im2_FFM_v_2i_X (
.i_poly_form_A (i_delta_2im2[`D_KES_GF_ORDER-1:0]),
.i_poly_form_B (o_v_2i_X[`D_KES_GF_ORDER-1:0]),
.o_poly_form_result(w_v_2ip2_X_term_A[`D_KES_GF_ORDER-1:0]));
assign w_v_2ip2_X[`D_KES_GF_ORDER-1:0] = w_v_2ip2_X_term_A[`D_KES_GF_ORDER-1:0];
assign w_k_2ip2_X[`D_KES_GF_ORDER-1:0] = D_KES_VALUE_ZERO[`D_KES_GF_ORDER-1:0];
endmodule
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module ram16_2sum (input clock, input write,
input [3:0] wr_addr, input [15:0] wr_data,
input [3:0] rd_addr1, input [3:0] rd_addr2,
output reg [15:0] sum);
reg signed [15:0] ram_array [0:15];
reg signed [15:0] a,b;
wire signed [16:0] sum_int;
always @(posedge clock)
if(write)
ram_array[wr_addr] <= #1 wr_data;
always @(posedge clock)
begin
a <= #1 ram_array[rd_addr1];
b <= #1 ram_array[rd_addr2];
end
assign sum_int = {a[15],a} + {b[15],b};
always @(posedge clock)
sum <= #1 sum_int[16:1] + (sum_int[16]&sum_int[0]);
endmodule // ram16_2sum
|
module avr_interface #(
parameter CLK_RATE = 50000000,
parameter SERIAL_BAUD_RATE = 500000
)(
input clk,
input rst,
// cclk, or configuration clock is used when the FPGA is begin configured.
// The AVR will hold cclk high when it has finished initializing.
// It is important not to drive the lines connecting to the AVR
// until cclk is high for a short period of time to avoid contention.
input cclk,
// AVR SPI Signals
output spi_miso,
input spi_mosi,
input spi_sck,
input spi_ss,
output [3:0] spi_channel,
// AVR Serial Signals
output tx,
input rx,
// ADC Interface Signals
input [3:0] channel,
output new_sample,
output [9:0] sample,
output [3:0] sample_channel,
// Serial TX User Interface
input [7:0] tx_data,
input new_tx_data,
output tx_busy,
input tx_block,
// Serial Rx User Interface
output [7:0] rx_data,
output new_rx_data
);
wire ready;
wire n_rdy = !ready;
wire spi_done;
wire [7:0] spi_dout;
wire tx_m;
wire spi_miso_m;
reg byte_ct_d, byte_ct_q;
reg [9:0] sample_d, sample_q;
reg new_sample_d, new_sample_q;
reg [3:0] sample_channel_d, sample_channel_q;
// cclk_detector is used to detect when cclk is high signaling when
// the AVR is ready
cclk_detector #(.CLK_RATE(CLK_RATE)) cclk_detector (
.clk(clk),
.rst(rst),
.cclk(cclk),
.ready(ready)
);
spi_slave spi_slave (
.clk(clk),
.rst(n_rdy),
.ss(spi_ss),
.mosi(spi_mosi),
.miso(spi_miso_m),
.sck(spi_sck),
.done(spi_done),
.din(8'hff),
.dout(spi_dout)
);
// CLK_PER_BIT is the number of cycles each 'bit' lasts for
// rtoi converts a 'real' number to an 'integer'
parameter CLK_PER_BIT = $rtoi($ceil(CLK_RATE/SERIAL_BAUD_RATE));
serial_rx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_rx (
.clk(clk),
.rst(n_rdy),
.rx(rx),
.data(rx_data),
.new_data(new_rx_data)
);
serial_tx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_tx (
.clk(clk),
.rst(n_rdy),
.tx(tx_m),
.block(tx_block),
.busy(tx_busy),
.data(tx_data),
.new_data(new_tx_data)
);
// Output declarations
assign new_sample = new_sample_q;
assign sample = sample_q;
assign sample_channel = sample_channel_q;
// these signals connect to the AVR and should be Z when the AVR isn't ready
assign spi_channel = ready ? channel : 4'bZZZZ;
assign spi_miso = ready && !spi_ss ? spi_miso_m : 1'bZ;
assign tx = ready ? tx_m : 1'bZ;
always @(*) begin
byte_ct_d = byte_ct_q;
sample_d = sample_q;
new_sample_d = 1'b0;
sample_channel_d = sample_channel_q;
if (spi_ss) begin // device is not selected
byte_ct_d = 1'b0;
end
if (spi_done) begin // sent/received data from SPI
if (byte_ct_q == 1'b0) begin
sample_d[7:0] = spi_dout; // first byte is the 8 LSB of the sample
byte_ct_d = 1'b1;
end else begin
sample_d[9:8] = spi_dout[1:0]; // second byte is the channel 2 MSB of the sample
sample_channel_d = spi_dout[7:4]; // and the channel that was sampled
byte_ct_d = 1'b1; // slave-select must be brought high before the next transfer
new_sample_d = 1'b1;
end
end
end
always @(posedge clk) begin
if (n_rdy) begin
byte_ct_q <= 1'b0;
sample_q <= 10'b0;
new_sample_q <= 1'b0;
end else begin
byte_ct_q <= byte_ct_d;
sample_q <= sample_d;
new_sample_q <= new_sample_d;
end
sample_channel_q <= sample_channel_d;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/14/2016 06:25:09 AM
// Design Name:
// Module Name: Exp_operation_m
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation_m
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,//underflow
input wire load_b_i,//overflow
input wire load_c_i,//result
input wire [EW:0] Data_A_i,
input wire [EW:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
///////////////////////////////////////////////
wire [EW:0] Data_S;
wire Overflow_A;
wire Overflow_flag_A;
wire underflow_exp_reg;
wire [EW:0] U_Limit;
/////////////////////////////Exponent calculation///
add_sub_carry_out #(.W(EW+1)) exp_add_subt_m(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S ({Overflow_A,Data_S})
);
RegisterMult #(.W(EW+1)) exp_result_m(
.clk (clk),
.rst (rst),
.load (load_c_i),
.D (Data_S),
.Q (Data_Result_o)
);
//Overflow/////////////////////////////////
RegisterMult#(.W(1)) Oflow_A_m (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Overflow_A),
.Q(Overflow_flag_A)
);
assign Overflow_flag_o = Overflow_flag_A | Data_Result_o[EW];
//Underflow//////////////////////////////
Comparator_Less #(.W(EW+1)) Exp_unflow_Comparator_m (
.Data_A(Data_S),
.Data_B(U_Limit),
.less(underflow_exp_reg)
);
RegisterMult #(.W(1)) Underflow_m (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(underflow_exp_reg),
.Q(Underflow_flag_o)
);
//Este valor de upper_limit es definido por la precision del formato
// 127 para simple
//1023 para doble
localparam integer Upper_limit = (2**(EW-1)-1);
assign U_Limit = Upper_limit[EW:0];
//generate
// if (EW == 8)
// assign U_Limit = 9'd127;
// else
// assign U_Limit = 12'd1023;
//endgenerate
endmodule
|
`ifndef PIPELINE_DEF
`include "define.v"
`endif
module regfile(
input clk,
input rst,
// write port
input[`RegAddrWidth-1:0] waddr,
input[`RegDataWidth-1:0] wdata,
input we,
// read port1
input re1,
input[`RegAddrWidth-1:0] raddr_1,
output reg[`RegDataWidth-1:0] rdata_1,
// read port2
input re2,
input[`RegAddrWidth-1:0] raddr_2,
`ifdef DEBUG
output reg[`RegDataWidth-1:0] rdata_2,
output[`RegDataWidth-1:0] reg0,
output[`RegDataWidth-1:0] reg1,
output[`RegDataWidth-1:0] reg2,
output[`RegDataWidth-1:0] reg3,
output[`RegDataWidth-1:0] reg4,
output[`RegDataWidth-1:0] reg5,
output[`RegDataWidth-1:0] reg6,
output[`RegDataWidth-1:0] reg7,
output[`RegDataWidth-1:0] reg8,
output[`RegDataWidth-1:0] reg9,
output[`RegDataWidth-1:0] reg10,
output[`RegDataWidth-1:0] reg11,
output[`RegDataWidth-1:0] reg12,
output[`RegDataWidth-1:0] reg13,
output[`RegDataWidth-1:0] reg14,
output[`RegDataWidth-1:0] reg15,
output[`RegDataWidth-1:0] reg16,
output[`RegDataWidth-1:0] reg17,
output[`RegDataWidth-1:0] reg18,
output[`RegDataWidth-1:0] reg19,
output[`RegDataWidth-1:0] reg20,
output[`RegDataWidth-1:0] reg21,
output[`RegDataWidth-1:0] reg22,
output[`RegDataWidth-1:0] reg23,
output[`RegDataWidth-1:0] reg24,
output[`RegDataWidth-1:0] reg25,
output[`RegDataWidth-1:0] reg26,
output[`RegDataWidth-1:0] reg27,
output[`RegDataWidth-1:0] reg28,
output[`RegDataWidth-1:0] reg29,
output[`RegDataWidth-1:0] reg30,
output[`RegDataWidth-1:0] reg31
`endif
`ifndef DEBUG
output reg[`RegDataWidth-1:0] rdata_2
`endif
);
reg[`RegDataWidth-1:0] regs[`RegNum-1:0];
`ifdef DEBUG
assign reg0 = regs[0];
assign reg1 = regs[1];
assign reg2 = regs[2];
assign reg3 = regs[3];
assign reg4 = regs[4];
assign reg5 = regs[5];
assign reg6 = regs[6];
assign reg7 = regs[7];
assign reg8 = regs[8];
assign reg9 = regs[9];
assign reg10 = regs[10];
assign reg11 = regs[11];
assign reg12 = regs[12];
assign reg13 = regs[13];
assign reg14 = regs[14];
assign reg15 = regs[15];
assign reg16 = regs[16];
assign reg17 = regs[17];
assign reg18 = regs[18];
assign reg19 = regs[19];
assign reg20 = regs[20];
assign reg21 = regs[21];
assign reg22 = regs[22];
assign reg23 = regs[23];
assign reg24 = regs[24];
assign reg25 = regs[25];
assign reg26 = regs[26];
assign reg27 = regs[27];
assign reg28 = regs[28];
assign reg29 = regs[29];
assign reg30 = regs[30];
assign reg31 = regs[31];
`endif
// reset all regs
always @(posedge clk) begin : proc_reset
integer i;
if (rst == `RstEnable) begin
for (i = 0; i < `RegNum; i = i + 1)
regs[i] <= 0;
end
end
// write operation
// Now set the write process finish by the first half of the period
always @(negedge clk) begin : proc_write
if (rst == ~`RstEnable)
if ((we == `WriteEnable) && (waddr != `RegAddrWidth'b0))
regs[waddr] <= wdata;
end
// read port1
always @(*) begin : proc_read1
if (re1 == `ReadEnable && rst == ~`RstEnable)
rdata_1 <= regs[raddr_1];
else
rdata_1 <= `ZeroWord;
end
// read port2
always @(*) begin : proc_read2
if (re2 == `ReadEnable && rst == ~`RstEnable)
rdata_2 <= regs[raddr_2];
else
rdata_2 <= `ZeroWord;
end
endmodule |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ad
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ad.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_ad.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_ad
//
// No user `defines in this module
module ent_ad
//
// Generated Module inst_ad
//
(
port_ad_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ad_2;
// Generated Wires:
wire port_ad_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_ad
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file ROM01.v when simulating
// the core, ROM01. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module ROM01(
clka,
ena,
addra,
douta
);
input clka;
input ena;
input [7 : 0] addra;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("ROM01.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_merge_enc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_ecc_merge_enc
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
mc_wrdata, mc_wrdata_mask,
// Inputs
clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc
);
input clk;
input rst;
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r;
reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r;
always @(posedge clk) wr_data_r <= #TCQ wr_data;
always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask;
always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data;
// Merge new data with memory read data.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data;
genvar h;
genvar i;
generate
for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer
for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner
assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] =
wr_data_mask[h*DATA_WIDTH/8+i]
? rd_merge_data[h*DATA_WIDTH+i*8+:8]
: wr_data[h*PAYLOAD_WIDTH+i*8+:8];
end
if (PAYLOAD_WIDTH > DATA_WIDTH)
assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]=
wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH];
end
endgenerate
// Generate ECC and overlay onto mc_wrdata.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK-1:0] raw_not_ecc;
reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r;
always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc;
output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c;
genvar j;
integer k;
generate
for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word
always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin
mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] =
{{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}},
merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]};
for (k=0; k<ECC_WIDTH; k=k+1)
if (~raw_not_ecc_r[j])
mc_wrdata_c[j*DQ_WIDTH+CODE_WIDTH-k-1] =
^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] &
h_rows[k*CODE_WIDTH+:DATA_WIDTH]);
end
end
endgenerate
always @(posedge clk) mc_wrdata <= mc_wrdata_c;
// Set all DRAM masks to zero.
output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}};
endmodule
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 1532 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w4,
w3,
w384,
w383,
w1532;
assign w1 = i_data0;
assign w1532 = w383 << 2;
assign w3 = w4 - w1;
assign w383 = w384 - w1;
assign w384 = w3 << 7;
assign w4 = w1 << 2;
assign o_data0 = w1532;
//multiplier_block area estimate = 3286.48311563824;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: Packet Generator
-- Description: Este modulo ofrece tasks para la generacion de paquetes
para pruebas de rendimiento y validacion de la red en
chip.
-- Dependencies: -- system.vh
-- packet_type.vh
-- Parameters: -- PORT: Direccion (x+, x-, y+, y-, pe) del
puerto de router para el cual se
generaran paquetes. La direccion limita
los destinos validos de los paquetes
generados.
-- pe_percent:
Porcentaje de paquetes que solicitaran
ingreso al PE del nodo
(witness field = 0).
-- X_LOCAL: Direccion en 'X' del nodo inmediato al
cual esta conectado el inyector de
paquetes (source.v).
-- Y_LOCAL: Direccion en 'Y' del nodo inmediato al
cual esta conectado el inyector de
paquetes (source.v).
-- Original Author: Héctor Cabrera
-- Current Author:
-- Notas:
-- History:
-- 05 de jun 2015: Creacion
-- 12 de dic 2015: Se agrego al generador de paquetes aleatorios la
capacidad de seleccionar una puerta de salida de
la red de manera aleatoria.
-- 26 de dic 2015: Nueva task para generar paquetes recibiendo los
siguientes datos: direccion destino, direccion
de puerta y numero de serie.
(network_directed_packet)
*/
`include "packet_type.vh"
`include "system.vh"
module packet_generator #(
parameter PORT = `X_POS,
parameter PE_RQS = 5,
parameter X_LOCAL = 1,
parameter Y_LOCAL = 1,
parameter X_WIDTH = 2,
parameter Y_WIDTH = 2
)();
/*
-- Lista de tasks:
- Random Packet Router
- Random Performance Packet
- Custom Packet
- Null Packet
-
*/
// -- Variables Globales ----------------------------------------- >>>>>
/*
-- Descripcion:
-- x_dest_addr: Variable aleatoria de direccion
destino en X.
-- y_dest_addr: Variable aleatoria de direccion
destino en Y.
-- packet: Contenedor de paquete a liberar.
-- ascii: Variable para la conversion de
numerosa caracteres ascii
*/
// -- Declaracion de variables publicas ---------------------- >>>>>
reg `PACKET_TYPE packet;
// -- Declaracion de variables privadas ---------------------- >>>>>
reg [2:0] x_dest_addr = 3'b000;
reg [2:0] y_dest_addr = 3'b000;
reg [2:0] x_gate_addr = 3'b000;
reg [2:0] y_gate_addr = 3'b000;
integer random_number = 0;
reg [7:0] ascii;
// -- TASK:: NETWORK_DIRECTED_PACKET ----------------------------- >>>>>
/*
-- Descripcion:
*/
task network_directed_packet;
input [2 :0] x_dest = 0;
input [2 :0] y_dest = 0;
input [2 :0] x_gate = 0;
input [2 :0] y_gate = 0;
input [17:0] extended_serial = 0;
begin: directed_packet
// -- Asignacion de valores a campos de cabecera ----- >>>>>
packet `ID_HEAD = 1'b1;
packet `TESTIGO = 1'b0;
packet `DESTINO = {x_dest, y_dest};
packet `PUERTA = {x_gate, y_gate};
packet `EXTENDED_SERIAL = extended_serial;
// -- Asignacion de contenido a flits de datos ------- >>>>>
if (PORT == `X_POS)
packet `DATA_0 = "x+ ";
else if (PORT == `Y_POS)
packet `DATA_0 = "y+ ";
else if (PORT == `X_NEG)
packet `DATA_0 = "x- ";
else if (PORT == `Y_NEG)
packet `DATA_0 = "y- ";
else if (PORT == `PE)
packet `DATA_0 = "pe ";
bin2ascii(x_gate);
packet `DATA_1 = {"x =",ascii};
bin2ascii(y_gate);
packet `DATA_2 = {"y =",ascii};
packet `DATA_3 = "NTST";
end
endtask
// -- TASK:: RANDOM_PACKET_ROUTER -------------------------------- >>>>>
/*
-- Descripcion: ** NOTA ** Esta rutina esta diseñada para evaluar
routers o nodos de manera independiente.
Utilizar esta rutina con una NoC
completa generara comportamientos
erraticos y posiblemente bloques de la
red por destinos no validos para los
paquetes generados.
El parametro PE_RQS determina si el
paquete generado solicitara ingreso
al PE del nodo (witness_field == 0).
Generacion de paquetes a direcciones aleatorias. El
contenido de los flits de datos generados esta
definido de la siguiente forma:
Flit dato 1: Puerto de ingreso a router (x+, x-,
y+, y-).
Flit dato 2: Direccion en 'X' de destino.
Flit dato 3: Direccion en 'Y' de destino.
Flit dato 4: Testigo de procesamiento (witness
field). Si el paquete pedira
ingreso al PE
Este task requiere 2 parametros para su operacion:
- serial: Numero de 12 bits que se asignara al
campo serial del flit de cabecera. La
intencion de este parametro es la de
utilizarce en conjunto con una variable
indice de un loop para generar id a cada
paquete.
- seed: Semilla para generadores de numeros
aleatoreos de la funcion $random de
verilog.
Un ejemplo de generacion de un numero
de semilla puede ser:
integer seed;
seed = $stime;
random_packet(serial, seed);
*/
task random_packet_router;
input [11:0] serial = 0;
input [31:0] seed = 0;
begin: random_packet
// -- Seleccion de direccion destino --------------------- >>>>>
/*
-- Descripcion
*/
if (PORT == `X_POS)
begin
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
while(x_dest_addr > X_LOCAL)
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
end
else if (PORT == `X_NEG)
begin
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
while(x_dest_addr < X_LOCAL)
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
end
else
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
if (PORT == `Y_POS)
begin
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
while(y_dest_addr > Y_LOCAL)
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else if (PORT == `Y_NEG)
begin
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
while(y_dest_addr < Y_LOCAL)
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
// -- Seleccion de direccion de puerta de salida --------- >>>>>
/*
-- Descripcion
*/
random_number = {$random(seed)} % 4;
if (random_number == `X_POS)
begin
x_gate_addr = X_WIDTH + 1;
y_gate_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else if (random_number == `Y_POS)
begin
x_gate_addr = 1 + ({$random(seed)}%(X_WIDTH));
y_gate_addr = Y_WIDTH + 1;
end
else if (random_number == `X_NEG)
begin
x_gate_addr = 0;
y_gate_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else // random_number == Y_NEG
begin
x_gate_addr = 1 + ({$random(seed)}%(X_WIDTH));
y_gate_addr = 0;
end
// -- Seleccion de valor para el 'Witness Field' --------- >>>>>
packet `ID_HEAD = 1'b1;
if ($unsigned($random(seed))%10 < PE_RQS)
begin
packet `TESTIGO = 1'b0;
packet `DATA_3 = "NTST";
end
else
begin
packet `TESTIGO = 1'b1;
packet `DATA_3 = "TST ";
end
// -- Asignacion de valores a campos de cabecera --------- >>>>>
packet `DESTINO = {x_dest_addr, y_dest_addr};
packet `PUERTA = {x_gate_addr, y_gate_addr};
packet `ORIGEN = {6{1'b0}};
packet `SERIAL = serial;
// -- Asignacion de contenido a flits de datos ----------- >>>>>
if (PORT == `X_POS)
packet `DATA_0 = "x+ ";
else if (PORT == `Y_POS)
packet `DATA_0 = "y+ ";
else if (PORT == `X_NEG)
packet `DATA_0 = "x- ";
else if (PORT == `Y_NEG)
packet `DATA_0 = "y- ";
else if (PORT == `PE)
packet `DATA_0 = "pe ";
bin2ascii(x_dest_addr);
packet `DATA_1 = {"x =",ascii};
bin2ascii(y_dest_addr);
packet `DATA_2 = {"y =",ascii};
end
endtask : random_packet_router
// -- TASK:: RANDOM_PERFORMANCE_PACKET --------------------------- >>>>>
/*
-- Descripcion:
*/
task random_performance_packet;
input [17:0] serial = 0;
input [31:0] seed = 0;
begin: random_dn_packet
// -- Seleccion de direccion destino --------------------- >>>>>
/*
-- Descripcion
*/
if (PORT == `X_POS)
x_dest_addr = 0;
else if (PORT == `X_NEG)
x_dest_addr = X_WIDTH + 1;
else
x_dest_addr = 1 + ({$random(seed)}%(X_WIDTH));
if (PORT == `Y_POS)
y_dest_addr = 0;
else if (PORT == `Y_NEG)
y_dest_addr = Y_WIDTH + 1;
else
y_dest_addr = 1 + ({$random(seed)}%(Y_WIDTH));
// -- Seleccion de direccion de puerta de salida --------- >>>>>
/*
-- Descripcion
*/
random_number = {$random(seed)} % 10;
if (random_number < 6) // Xneg Gate
begin
x_gate_addr = 0;
y_gate_addr = 1 + ({$random(seed)}%(Y_WIDTH));
end
else // Ypos Gate
begin
x_gate_addr = 1 + ({$random(seed)}%(X_WIDTH));
y_gate_addr = Y_WIDTH + 1;
end
// -- Seleccion de valor para el 'Witness Field' --------- >>>>>
packet `ID_HEAD = 1'b1;
packet `TESTIGO = 1'b0;
packet `DATA_3 = "NTST";
// -- Asignacion de valores a campos de cabecera --------- >>>>>
packet `DESTINO = {x_dest_addr, y_dest_addr};
packet `PUERTA = {x_gate_addr, y_gate_addr};
packet `ORIGEN = serial[17:12];
packet `SERIAL = serial[11:0];
// -- Asignacion de contenido a flits de datos ----------- >>>>>
if (PORT == `X_POS)
packet `DATA_0 = "x+ ";
else if (PORT == `Y_POS)
packet `DATA_0 = "y+ ";
else if (PORT == `X_NEG)
packet `DATA_0 = "x- ";
else if (PORT == `Y_NEG)
packet `DATA_0 = "y- ";
else if (PORT == `PE)
packet `DATA_0 = "pe ";
bin2ascii(x_dest_addr);
packet `DATA_1 = {"x =",ascii};
bin2ascii(y_dest_addr);
packet `DATA_2 = {"y =",ascii};
end
endtask : random_performance_packet
// -- TASK:: CUSTOM_PACKET --------------------------------------- >>>>>
/*
-- Descripcion: Paquete generado en su totalidad por datos
proporcionados en la invocacion del task.
*/
task custom_packet;
input testigo;
input [5:0] destino;
input [5:0] puerta;
input [11:0] serial;
input [31:0] dato1;
input [31:0] dato2;
input [31:0] dato3;
input [31:0] dato4;
begin
packet `ID_HEAD = 1'b1;
packet `TESTIGO = testigo;
packet `DESTINO = destino;
packet `PUERTA = puerta;
packet `ORIGEN = {6{1'b0}};
packet `SERIAL = serial;
packet `DATA_0 = dato1;
packet `DATA_1 = dato2;
packet `DATA_2 = dato3;
packet `DATA_3 = dato4;
end
endtask : custom_packet
// -- TASK:: NULL_PACKET ----------------------------------------- >>>>>
/*
-- Descripcion: Generacion de paquete con todos los campos y flits
en zero.
*/
task null_packet;
begin
packet `ID_HEAD = 1'b0;
packet `TESTIGO = 1'b0;
packet `DESTINO = {6{1'b0}};
packet `PUERTA = {6{1'b0}};
packet `ORIGEN = {6{1'b0}};
packet `SERIAL = 11'b000_0000_0000;
packet `DATA_0 = "_NULL";
packet `DATA_1 = "_NULL";
packet `DATA_2 = "_NULL";
packet `DATA_3 = "_NULL";
end
endtask : null_packet
// -- TASK:: BIN2ASCII ------------------------------------------ >>>>>
/*
-- Descripcion: Conversor de binario a ascii en un rango de valores
de 0 a 7.
*/
task bin2ascii;
input [2:0] bin;
begin
if(bin == 3'b000)
ascii = "0";
else if(bin == 3'b001)
ascii = "1";
else if(bin == 3'b010)
ascii = "2";
else if(bin == 3'b011)
ascii = "3";
else if(bin == 3'b100)
ascii = "4";
else if(bin == 3'b101)
ascii = "5";
else if(bin == 3'b110)
ascii = "6";
else
ascii = "7";
end
endtask : bin2ascii
endmodule
/* -- Plantilla de Instancia ------------------------------------- >>>>>
packet_generator
#(
.PORT (PORT),
.pe_percent (pe_percent),
.X_LOCAL (X_LOCAL),
.Y_LOCAL (Y_LOCAL),
.X_WIDTH (X_WIDTH),
.Y_WIDTH (Y_WIDTH)
)
packet_generator
();
*/ |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__EINVP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__EINVP_FUNCTIONAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__EINVP_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/26/2016 09:14:57 AM
// Design Name:
// Module Name: FSM_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FSM_test
(
input wire clk,
input wire rst,
input wire ready_op,
input wire max_tick_address,
input wire max_tick_ch,
input wire TX_DONE,
output reg beg_op,
output reg ack_op,
output reg load_address,
output reg enab_address,
output reg enab_ch,
output reg load_ch,
output reg TX_START
);
//symbolic state declaration
localparam [3:0] est0 = 4'b0000,
est1 = 4'b0001,
est2 = 4'b0010,
est3 = 4'b0011,
est4 = 4'b0100,
est5 = 4'b0101,
est6 = 4'b0110,
est7 = 4'b0111,
est8 = 4'b1000,
est9 = 4'b1001,
est10 = 4'b1010,
est11 = 4'b1011;
//signal declaration
reg [3:0] state_reg, state_next; // Guardan el estado actual y el estado futuro, respectivamente.
//state register
always @( posedge clk, posedge rst)
begin
if(rst) // Si hay reset, el estado actual es el estado inicial.
state_reg <= est0;
else //Si no hay reset el estado actual es igual al estado siguiente.
state_reg <= state_next;
end
//next-state logic and output logic
always @*
begin
state_next = state_reg; // default state : the same
//declaration of default outputs.
beg_op = 1'b0;
ack_op = 1'b0;
load_address = 1'b0;
enab_address = 1'b0;
enab_ch = 1'b0;
load_ch = 1'b0;
TX_START = 1'b0;
case(state_reg)
est0:
begin
state_next = est1;
end
est1:
begin
load_address = 1'b1;
enab_address = 1'b1;
state_next = est2;
end
est2:
begin
beg_op = 1'b1;
state_next=est3;
end
est3:
begin
beg_op = 1'b1;
enab_ch = 1'b1;
load_ch = 1'b1;
state_next=est4;
end
est4:
begin
if(ready_op)
state_next=est5;
else
state_next=est4;
end
est5:
begin
state_next=est6;
end
est6:
begin
TX_START = 1'b1;
state_next=est7;
end
est7:
begin
if(TX_DONE)
if(max_tick_ch)
state_next=est9;
else
begin
state_next=est8;
end
else
state_next=est7;
end
est8:
begin
enab_ch = 1'b1;
state_next=est5;
end
est9:
begin
if(max_tick_address)
state_next=est11;
else
begin
state_next=est10;
end
end
est10:
begin
enab_address = 1'b1;
ack_op = 1'b1;
state_next=est2;
end
est11:
begin
state_next=est11;
end
default:
state_next=est0;
endcase
end
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Cache_DataRAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 232 07/05/2012 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Cache_DataRAM (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [10:0] address_a;
input [10:0] address_b;
input clock;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "36864"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]"
// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]"
// Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]"
// Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]"
// Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0
// Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
// Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:06:01 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_c_addsub_0_0/system_c_addsub_0_0_stub.v
// Design : system_c_addsub_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "c_addsub_v12_0_10,Vivado 2016.4" *)
module system_c_addsub_0_0(A, B, S)
/* synthesis syn_black_box black_box_pad_pin="A[9:0],B[9:0],S[9:0]" */;
input [9:0]A;
input [9:0]B;
output [9:0]S;
endmodule
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Up-Sizer
// Up-Sizer for generic SI- and MI-side data widths. This module instantiates
// Address, Write Data and Read Data Up-Sizer modules, each one taking care
// of the channel specific tasks.
// The Address Up-Sizer can handle both AR and AW channels.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi_upsizer
// a_upsizer
// fifo
// fifo_gen
// fifo_coregen
// w_upsizer
// r_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_7_axi_upsizer #
(
parameter C_FAMILY = "virtex7",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_PROTOCOL = 0,
// Protocol of SI and MI (0=AXI4, 1=AXI3).
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI side of converter.
// Range: 1 - 32.
parameter integer C_SUPPORTS_ID = 0,
// Indicates whether SI-side ID needs to be stored and compared.
// 0 = No, SI is single-threaded, propagate all transactions.
// 1 = Yes, stall any transaction with ID different than outstanding transactions.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range (AXI4, AXI3): 12 - 64.
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 64,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// parameter integer C_FIFO_MODE = 0,
parameter integer C_FIFO_MODE = 1,
// 0=None, 1=Packet_FIFO, 2=Clock_conversion_Packet_FIFO, 3=Simple_FIFO (FUTURE), 4=Clock_conversion_Simple_FIFO (FUTURE)
parameter integer C_S_AXI_ACLK_RATIO = 1, // Clock frequency ratio of SI w.r.t. MI.
// Range = [1..16].
parameter integer C_M_AXI_ACLK_RATIO = 2, // Clock frequency ratio of MI w.r.t. SI.
// Range = [2..16] if C_S_AXI_ACLK_RATIO = 1; else must be 1.
parameter integer C_AXI_IS_ACLK_ASYNC = 0, // Indicates whether S and M clocks are asynchronous.
// FUTURE FEATURE
// Range = [0, 1].
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con. Same size AXI interfaces
// should only be used when always packing)
parameter integer C_SYNCHRONIZER_STAGE = 3
)
(
// Slave Interface
input wire s_axi_aresetn,
input wire s_axi_aclk,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [8-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [2-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [8-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [2-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface
input wire m_axi_aresetn,
input wire m_axi_aclk,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [8-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [2-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [8-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [2-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
// Log2 of number of 32bit word on SI-side.
localparam integer C_S_AXI_BYTES_LOG = log2(C_S_AXI_DATA_WIDTH/8);
// Log2 of number of 32bit word on MI-side.
localparam integer C_M_AXI_BYTES_LOG = log2(C_M_AXI_DATA_WIDTH/8);
// Log2 of Up-Sizing ratio for data.
localparam integer C_RATIO = C_M_AXI_DATA_WIDTH / C_S_AXI_DATA_WIDTH;
localparam integer C_RATIO_LOG = log2(C_RATIO);
localparam P_BYPASS = 32'h0;
localparam P_LIGHTWT = 32'h7;
localparam P_FWD_REV = 32'h1;
localparam integer P_CONV_LIGHT_WT = 0;
localparam integer P_AXI4 = 0;
localparam integer C_FIFO_DEPTH_LOG = 5;
localparam P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);
localparam integer P_ACLK_RATIO = P_SI_LT_MI ? (C_M_AXI_ACLK_RATIO / C_S_AXI_ACLK_RATIO) : (C_S_AXI_ACLK_RATIO / C_M_AXI_ACLK_RATIO);
localparam integer P_NO_FIFO = 0;
localparam integer P_PKTFIFO = 1;
localparam integer P_PKTFIFO_CLK = 2;
localparam integer P_DATAFIFO = 3;
localparam integer P_DATAFIFO_CLK = 4;
localparam P_CLK_CONV = ((C_FIFO_MODE == P_PKTFIFO_CLK) || (C_FIFO_MODE == P_DATAFIFO_CLK));
localparam integer C_M_AXI_AW_REGISTER = 0;
// Simple register AW output.
// Range: 0, 1
localparam integer C_M_AXI_W_REGISTER = 1; // Parameter not used; W reg always implemented.
localparam integer C_M_AXI_AR_REGISTER = 0;
// Simple register AR output.
// Range: 0, 1
localparam integer C_S_AXI_R_REGISTER = 0;
// Simple register R output (SI).
// Range: 0, 1
localparam integer C_M_AXI_R_REGISTER = 1;
// Register slice on R input (MI) side.
// 0 = Bypass (not recommended due to combinatorial M_RVALID -> M_RREADY path)
// 1 = Fully-registered (needed only when upsizer propagates bursts at 1:1 width ratio)
// 7 = Light-weight (safe when upsizer always packs at 1:n width ratio, as in interconnect)
localparam integer P_RID_QUEUE = ((C_SUPPORTS_ID != 0) && !((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK))) ? 1 : 0;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
// Log2.
function integer log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
log2 = acc;
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire aclk;
wire m_aclk;
wire sample_cycle;
wire sample_cycle_early;
wire sm_aresetn;
wire s_aresetn_i;
wire [C_S_AXI_ID_WIDTH-1:0] sr_awid ;
wire [C_AXI_ADDR_WIDTH-1:0] sr_awaddr ;
wire [8-1:0] sr_awlen ;
wire [3-1:0] sr_awsize ;
wire [2-1:0] sr_awburst ;
wire [2-1:0] sr_awlock ;
wire [4-1:0] sr_awcache ;
wire [3-1:0] sr_awprot ;
wire [4-1:0] sr_awregion ;
wire [4-1:0] sr_awqos ;
wire sr_awvalid ;
wire sr_awready ;
wire [C_S_AXI_ID_WIDTH-1:0] sr_arid ;
wire [C_AXI_ADDR_WIDTH-1:0] sr_araddr ;
wire [8-1:0] sr_arlen ;
wire [3-1:0] sr_arsize ;
wire [2-1:0] sr_arburst ;
wire [2-1:0] sr_arlock ;
wire [4-1:0] sr_arcache ;
wire [3-1:0] sr_arprot ;
wire [4-1:0] sr_arregion ;
wire [4-1:0] sr_arqos ;
wire sr_arvalid ;
wire sr_arready ;
wire [C_S_AXI_DATA_WIDTH-1:0] sr_wdata ;
wire [(C_S_AXI_DATA_WIDTH/8)-1:0] sr_wstrb ;
wire sr_wlast ;
wire sr_wvalid ;
wire sr_wready ;
wire [C_M_AXI_DATA_WIDTH-1:0] mr_rdata ;
wire [2-1:0] mr_rresp ;
wire mr_rlast ;
wire mr_rvalid ;
wire mr_rready ;
wire m_axi_rready_i;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_awlen_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_arlen_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_awlock_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_arlock_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_awlen_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_arlen_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_awlock_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_arlock_ii ;
wire [3:0] s_axi_awregion_ii;
wire [3:0] s_axi_arregion_ii;
assign s_axi_awlen_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlen : s_axi_awlen[3:0];
assign s_axi_awlock_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlock[0] : s_axi_awlock;
assign s_axi_arlen_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlen : s_axi_arlen[3:0];
assign s_axi_arlock_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlock[0] : s_axi_arlock;
assign sr_awlen = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlen_ii: {4'b0, s_axi_awlen_ii};
assign sr_awlock = (C_AXI_PROTOCOL == P_AXI4) ? {1'b0, s_axi_awlock_ii} : s_axi_awlock_ii;
assign sr_arlen = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlen_ii: {4'b0, s_axi_arlen_ii};
assign sr_arlock = (C_AXI_PROTOCOL == P_AXI4) ? {1'b0, s_axi_arlock_ii} : s_axi_arlock_ii;
assign sr_awregion = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awregion_ii : 4'b0;
assign sr_arregion = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arregion_ii : 4'b0;
assign aclk = s_axi_aclk;
assign sm_aresetn = s_axi_aresetn & m_axi_aresetn;
generate
if (P_CLK_CONV) begin : gen_clock_conv
if (C_AXI_IS_ACLK_ASYNC) begin : gen_async_conv
assign m_aclk = m_axi_aclk;
assign s_aresetn_i = s_axi_aresetn;
assign sample_cycle_early = 1'b1;
assign sample_cycle = 1'b1;
end else begin : gen_sync_conv
wire fast_aclk;
wire slow_aclk;
reg s_aresetn_r;
if (P_SI_LT_MI) begin : gen_fastclk_mi
assign fast_aclk = m_axi_aclk;
assign slow_aclk = s_axi_aclk;
end else begin : gen_fastclk_si
assign fast_aclk = s_axi_aclk;
assign slow_aclk = m_axi_aclk;
end
assign m_aclk = m_axi_aclk;
assign s_aresetn_i = s_aresetn_r;
always @(negedge sm_aresetn, posedge fast_aclk) begin
if (~sm_aresetn) begin
s_aresetn_r <= 1'b0;
end else if (s_axi_aresetn & m_axi_aresetn & sample_cycle_early) begin
s_aresetn_r <= 1'b1;
end
end
// Sample cycle used to determine when to assert a signal on a fast clock
// to be flopped onto a slow clock.
axi_clock_converter_v2_1_6_axic_sample_cycle_ratio #(
.C_RATIO ( P_ACLK_RATIO )
)
axic_sample_cycle_inst (
.SLOW_ACLK ( slow_aclk ) ,
.FAST_ACLK ( fast_aclk ) ,
.SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,
.SAMPLE_CYCLE ( sample_cycle )
);
end
end else begin : gen_no_clk_conv
assign m_aclk = s_axi_aclk;
assign s_aresetn_i = s_axi_aresetn;
assign sample_cycle_early = 1'b1;
assign sample_cycle = 1'b1;
end // gen_clock_conv
axi_register_slice_v2_1_7_axi_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (0),
.C_REG_CONFIG_AW (C_AXI_SUPPORTS_WRITE ? P_LIGHTWT : P_BYPASS),
.C_REG_CONFIG_AR (C_AXI_SUPPORTS_READ ? P_LIGHTWT : P_BYPASS)
)
si_register_slice_inst
(
.aresetn (s_aresetn_i),
.aclk (aclk),
.s_axi_awid (s_axi_awid ),
.s_axi_awaddr (s_axi_awaddr ),
.s_axi_awlen (s_axi_awlen_i ),
.s_axi_awsize (s_axi_awsize ),
.s_axi_awburst (s_axi_awburst ),
.s_axi_awlock (s_axi_awlock_i ),
.s_axi_awcache (s_axi_awcache ),
.s_axi_awprot (s_axi_awprot ),
.s_axi_awregion (s_axi_awregion ),
.s_axi_awqos (s_axi_awqos ),
.s_axi_awuser (1'b0 ),
.s_axi_awvalid (s_axi_awvalid ),
.s_axi_awready (s_axi_awready ),
.s_axi_wid ( {C_S_AXI_ID_WIDTH{1'b0}}),
.s_axi_wdata ( {C_S_AXI_DATA_WIDTH{1'b0}} ),
.s_axi_wstrb ( {C_S_AXI_DATA_WIDTH/8{1'b0}} ),
.s_axi_wlast ( 1'b0 ),
.s_axi_wuser ( 1'b0 ),
.s_axi_wvalid ( 1'b0 ),
.s_axi_wready ( ),
.s_axi_bid ( ),
.s_axi_bresp ( ),
.s_axi_buser ( ),
.s_axi_bvalid ( ),
.s_axi_bready ( 1'b0 ),
.s_axi_arid (s_axi_arid ),
.s_axi_araddr (s_axi_araddr ),
.s_axi_arlen (s_axi_arlen_i ),
.s_axi_arsize (s_axi_arsize ),
.s_axi_arburst (s_axi_arburst ),
.s_axi_arlock (s_axi_arlock_i ),
.s_axi_arcache (s_axi_arcache ),
.s_axi_arprot (s_axi_arprot ),
.s_axi_arregion (s_axi_arregion ),
.s_axi_arqos (s_axi_arqos ),
.s_axi_aruser (1'b0 ),
.s_axi_arvalid (s_axi_arvalid ),
.s_axi_arready (s_axi_arready ),
.s_axi_rid ( ) ,
.s_axi_rdata ( ) ,
.s_axi_rresp ( ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( ) ,
.s_axi_rready ( 1'b0 ) ,
.m_axi_awid (sr_awid ),
.m_axi_awaddr (sr_awaddr ),
.m_axi_awlen (s_axi_awlen_ii),
.m_axi_awsize (sr_awsize ),
.m_axi_awburst (sr_awburst ),
.m_axi_awlock (s_axi_awlock_ii),
.m_axi_awcache (sr_awcache ),
.m_axi_awprot (sr_awprot ),
.m_axi_awregion (s_axi_awregion_ii ),
.m_axi_awqos (sr_awqos ),
.m_axi_awuser (),
.m_axi_awvalid (sr_awvalid ),
.m_axi_awready (sr_awready ),
.m_axi_wid () ,
.m_axi_wdata (),
.m_axi_wstrb (),
.m_axi_wlast (),
.m_axi_wuser (),
.m_axi_wvalid (),
.m_axi_wready (1'b0),
.m_axi_bid ( {C_S_AXI_ID_WIDTH{1'b0}} ) ,
.m_axi_bresp ( 2'b0 ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( 1'b0 ) ,
.m_axi_bready ( ) ,
.m_axi_arid (sr_arid ),
.m_axi_araddr (sr_araddr ),
.m_axi_arlen (s_axi_arlen_ii),
.m_axi_arsize (sr_arsize ),
.m_axi_arburst (sr_arburst ),
.m_axi_arlock (s_axi_arlock_ii),
.m_axi_arcache (sr_arcache ),
.m_axi_arprot (sr_arprot ),
.m_axi_arregion (s_axi_arregion_ii ),
.m_axi_arqos (sr_arqos ),
.m_axi_aruser (),
.m_axi_arvalid (sr_arvalid ),
.m_axi_arready (sr_arready ),
.m_axi_rid ( {C_S_AXI_ID_WIDTH{1'b0}}),
.m_axi_rdata ( {C_S_AXI_DATA_WIDTH{1'b0}} ),
.m_axi_rresp ( 2'b00 ),
.m_axi_rlast ( 1'b0 ),
.m_axi_ruser ( 1'b0 ),
.m_axi_rvalid ( 1'b0 ),
.m_axi_rready ( )
);
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr_i ;
wire [8-1:0] m_axi_awlen_i ;
wire [3-1:0] m_axi_awsize_i ;
wire [2-1:0] m_axi_awburst_i ;
wire [2-1:0] m_axi_awlock_i ;
wire [4-1:0] m_axi_awcache_i ;
wire [3-1:0] m_axi_awprot_i ;
wire [4-1:0] m_axi_awregion_i ;
wire [4-1:0] m_axi_awqos_i ;
wire m_axi_awvalid_i ;
wire m_axi_awready_i ;
wire s_axi_bvalid_i ;
wire [2-1:0] s_axi_bresp_i ;
wire [C_AXI_ADDR_WIDTH-1:0] wr_cmd_si_addr;
wire [8-1:0] wr_cmd_si_len;
wire [3-1:0] wr_cmd_si_size;
wire [2-1:0] wr_cmd_si_burst;
// Write Channel Signals for Commands Queue Interface.
wire wr_cmd_valid;
wire wr_cmd_fix;
wire wr_cmd_modified;
wire wr_cmd_complete_wrap;
wire wr_cmd_packed_wrap;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_first_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_last_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_offset;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_mask;
wire [C_S_AXI_BYTES_LOG:0] wr_cmd_step;
wire [8-1:0] wr_cmd_length;
wire wr_cmd_ready;
wire wr_cmd_id_ready;
wire [C_S_AXI_ID_WIDTH-1:0] wr_cmd_id;
wire wpush;
wire wpop;
reg [C_FIFO_DEPTH_LOG-1:0] wcnt;
// Write Address Channel.
axi_dwidth_converter_v2_1_7_a_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (C_M_AXI_AW_REGISTER),
.C_AXI_CHANNEL (0),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_FIFO_MODE (C_FIFO_MODE),
.C_ID_QUEUE (C_SUPPORTS_ID),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_fix (wr_cmd_fix),
.cmd_modified (wr_cmd_modified),
.cmd_complete_wrap (wr_cmd_complete_wrap),
.cmd_packed_wrap (wr_cmd_packed_wrap),
.cmd_first_word (wr_cmd_first_word),
.cmd_next_word (wr_cmd_next_word),
.cmd_last_word (wr_cmd_last_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
.cmd_id (wr_cmd_id),
.cmd_id_ready (wr_cmd_id_ready),
.cmd_si_addr (wr_cmd_si_addr ),
.cmd_si_id (),
.cmd_si_len (wr_cmd_si_len ),
.cmd_si_size (wr_cmd_si_size ),
.cmd_si_burst (wr_cmd_si_burst),
// Slave Interface Write Address Ports
.S_AXI_AID (sr_awid),
.S_AXI_AADDR (sr_awaddr),
.S_AXI_ALEN (sr_awlen),
.S_AXI_ASIZE (sr_awsize),
.S_AXI_ABURST (sr_awburst),
.S_AXI_ALOCK (sr_awlock),
.S_AXI_ACACHE (sr_awcache),
.S_AXI_APROT (sr_awprot),
.S_AXI_AREGION (sr_awregion),
.S_AXI_AQOS (sr_awqos),
.S_AXI_AVALID (sr_awvalid),
.S_AXI_AREADY (sr_awready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_awaddr_i ),
.M_AXI_ALEN (m_axi_awlen_i ),
.M_AXI_ASIZE (m_axi_awsize_i ),
.M_AXI_ABURST (m_axi_awburst_i ),
.M_AXI_ALOCK (m_axi_awlock_i ),
.M_AXI_ACACHE (m_axi_awcache_i ),
.M_AXI_APROT (m_axi_awprot_i ),
.M_AXI_AREGION (m_axi_awregion_i ),
.M_AXI_AQOS (m_axi_awqos_i ),
.M_AXI_AVALID (m_axi_awvalid_i ),
.M_AXI_AREADY (m_axi_awready_i )
);
if ((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK)) begin : gen_pktfifo_w_upsizer
// Packet FIFO Write Data channel.
axi_dwidth_converter_v2_1_7_w_upsizer_pktfifo #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG),
.C_CLK_CONV (P_CLK_CONV),
.C_S_AXI_ACLK_RATIO (C_S_AXI_ACLK_RATIO),
.C_M_AXI_ACLK_RATIO (C_M_AXI_ACLK_RATIO),
.C_AXI_IS_ACLK_ASYNC (C_AXI_IS_ACLK_ASYNC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
) pktfifo_write_data_inst
(
.S_AXI_ARESETN ( s_axi_aresetn ) ,
.S_AXI_ACLK ( s_axi_aclk ) ,
.M_AXI_ARESETN ( m_axi_aresetn ) ,
.M_AXI_ACLK ( m_axi_aclk ) ,
// Command Interface
.cmd_si_addr (wr_cmd_si_addr ),
.cmd_si_len (wr_cmd_si_len ),
.cmd_si_size (wr_cmd_si_size ),
.cmd_si_burst (wr_cmd_si_burst),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Address Ports
.S_AXI_AWADDR (m_axi_awaddr_i ),
.S_AXI_AWLEN (m_axi_awlen_i ),
.S_AXI_AWSIZE (m_axi_awsize_i ),
.S_AXI_AWBURST (m_axi_awburst_i ),
.S_AXI_AWLOCK (m_axi_awlock_i ),
.S_AXI_AWCACHE (m_axi_awcache_i ),
.S_AXI_AWPROT (m_axi_awprot_i ),
.S_AXI_AWREGION (m_axi_awregion_i ),
.S_AXI_AWQOS (m_axi_awqos_i ),
.S_AXI_AWVALID (m_axi_awvalid_i ),
.S_AXI_AWREADY (m_axi_awready_i ),
// Master Interface Write Address Port
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWLEN (m_axi_awlen),
.M_AXI_AWSIZE (m_axi_awsize),
.M_AXI_AWBURST (m_axi_awburst),
.M_AXI_AWLOCK (m_axi_awlock),
.M_AXI_AWCACHE (m_axi_awcache),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWREGION (m_axi_awregion),
.M_AXI_AWQOS (m_axi_awqos),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early)
);
end else begin : gen_non_fifo_w_upsizer
// Write Data channel.
axi_dwidth_converter_v2_1_7_w_upsizer #
(
.C_FAMILY ("rtl"),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (1),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG)
) write_data_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_fix (wr_cmd_fix),
.cmd_modified (wr_cmd_modified),
.cmd_complete_wrap (wr_cmd_complete_wrap),
.cmd_packed_wrap (wr_cmd_packed_wrap),
.cmd_first_word (wr_cmd_first_word),
.cmd_next_word (wr_cmd_next_word),
.cmd_last_word (wr_cmd_last_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready)
);
assign m_axi_awaddr = m_axi_awaddr_i ;
assign m_axi_awlen = m_axi_awlen_i ;
assign m_axi_awsize = m_axi_awsize_i ;
assign m_axi_awburst = m_axi_awburst_i ;
assign m_axi_awlock = m_axi_awlock_i ;
assign m_axi_awcache = m_axi_awcache_i ;
assign m_axi_awprot = m_axi_awprot_i ;
assign m_axi_awregion = m_axi_awregion_i ;
assign m_axi_awqos = m_axi_awqos_i ;
assign m_axi_awvalid = m_axi_awvalid_i ;
assign m_axi_awready_i = m_axi_awready ;
end // gen_w_upsizer
// Write Response channel.
assign wr_cmd_id_ready = s_axi_bvalid_i & s_axi_bready;
assign s_axi_bid = wr_cmd_id;
assign s_axi_bresp = s_axi_bresp_i;
assign s_axi_bvalid = s_axi_bvalid_i;
if (P_CLK_CONV) begin : gen_b_clk_conv
if (C_AXI_IS_ACLK_ASYNC == 0) begin : gen_b_sync_conv
axi_clock_converter_v2_1_6_axic_sync_clock_converter #(
.C_FAMILY ( C_FAMILY ) ,
.C_PAYLOAD_WIDTH ( 2 ) ,
.C_M_ACLK_RATIO ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,
.C_S_ACLK_RATIO ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,
.C_MODE(P_CONV_LIGHT_WT)
)
b_sync_clock_converter (
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early),
.S_ACLK ( m_axi_aclk ) ,
.S_ARESETN ( m_axi_aresetn ) ,
.S_PAYLOAD ( m_axi_bresp ) ,
.S_VALID ( m_axi_bvalid ) ,
.S_READY ( m_axi_bready ) ,
.M_ACLK ( s_axi_aclk ) ,
.M_ARESETN ( s_axi_aresetn ) ,
.M_PAYLOAD ( s_axi_bresp_i ) ,
.M_VALID ( s_axi_bvalid_i ) ,
.M_READY ( s_axi_bready )
);
end else begin : gen_b_async_conv
fifo_generator_v13_0_1 #(
.C_COMMON_CLOCK(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE(1),
.C_HAS_AXI_ID(1),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2),
.C_DIN_WIDTH_WACH(63),
.C_DIN_WIDTH_WDCH(38),
.C_DIN_WIDTH_WRCH(3),
.C_DIN_WIDTH_RACH(63),
.C_DIN_WIDTH_RDCH(36),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(2),
.C_WDCH_TYPE(2),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(12),
.C_IMPLEMENTATION_TYPE_WDCH(11),
.C_IMPLEMENTATION_TYPE_WRCH(12),
.C_IMPLEMENTATION_TYPE_RACH(12),
.C_IMPLEMENTATION_TYPE_RDCH(11),
.C_IMPLEMENTATION_TYPE_AXIS(11),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(32),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(5),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(29),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) dw_fifogen_b_async (
.m_aclk(m_axi_aclk),
.s_aclk(s_axi_aclk),
.s_aresetn(sm_aresetn),
.s_axi_awid(1'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(1'b0),
.s_axi_wdata(32'b0),
.s_axi_wstrb(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp_i),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid_i),
.s_axi_bready(s_axi_bready),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(1'b0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.s_axi_arid(1'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(1'b0),
.m_axi_rdata(32'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.rst(1'b0),
.srst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.din(18'b0),
.wr_en(1'b0),
.rd_en(1'b0),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.dout(),
.full(),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(5'b0),
.axi_b_prog_empty_thresh(5'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
end
end else begin : gen_b_passthru
assign m_axi_bready = s_axi_bready;
assign s_axi_bresp_i = m_axi_bresp;
assign s_axi_bvalid_i = m_axi_bvalid;
end // gen_b
end else begin : NO_WRITE
assign sr_awready = 1'b0;
assign s_axi_wready = 1'b0;
assign s_axi_bid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_bresp = 2'b0;
assign s_axi_bvalid = 1'b0;
assign m_axi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_awlen = 8'b0;
assign m_axi_awsize = 3'b0;
assign m_axi_awburst = 2'b0;
assign m_axi_awlock = 2'b0;
assign m_axi_awcache = 4'b0;
assign m_axi_awprot = 3'b0;
assign m_axi_awregion = 4'b0;
assign m_axi_awqos = 4'b0;
assign m_axi_awvalid = 1'b0;
assign m_axi_wdata = {C_M_AXI_DATA_WIDTH{1'b0}};
assign m_axi_wstrb = {C_M_AXI_DATA_WIDTH/8{1'b0}};
assign m_axi_wlast = 1'b0;
assign m_axi_wvalid = 1'b0;
assign m_axi_bready = 1'b0;
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr_i ;
wire [8-1:0] m_axi_arlen_i ;
wire [3-1:0] m_axi_arsize_i ;
wire [2-1:0] m_axi_arburst_i ;
wire [2-1:0] m_axi_arlock_i ;
wire [4-1:0] m_axi_arcache_i ;
wire [3-1:0] m_axi_arprot_i ;
wire [4-1:0] m_axi_arregion_i ;
wire [4-1:0] m_axi_arqos_i ;
wire m_axi_arvalid_i ;
wire m_axi_arready_i ;
// Read Channel Signals for Commands Queue Interface.
wire rd_cmd_valid;
wire rd_cmd_fix;
wire rd_cmd_modified;
wire rd_cmd_complete_wrap;
wire rd_cmd_packed_wrap;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_first_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_last_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_offset;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_mask;
wire [C_S_AXI_BYTES_LOG:0] rd_cmd_step;
wire [8-1:0] rd_cmd_length;
wire rd_cmd_ready;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_id;
wire [C_AXI_ADDR_WIDTH-1:0] rd_cmd_si_addr;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_si_id;
wire [8-1:0] rd_cmd_si_len;
wire [3-1:0] rd_cmd_si_size;
wire [2-1:0] rd_cmd_si_burst;
// Read Address Channel.
axi_dwidth_converter_v2_1_7_a_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (C_M_AXI_AR_REGISTER),
.C_AXI_CHANNEL (1),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
// .C_FIFO_MODE (0),
.C_FIFO_MODE (C_FIFO_MODE),
.C_ID_QUEUE (P_RID_QUEUE),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)
) read_addr_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_fix (rd_cmd_fix),
.cmd_modified (rd_cmd_modified),
.cmd_complete_wrap (rd_cmd_complete_wrap),
.cmd_packed_wrap (rd_cmd_packed_wrap),
.cmd_first_word (rd_cmd_first_word),
.cmd_next_word (rd_cmd_next_word),
.cmd_last_word (rd_cmd_last_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
.cmd_si_addr (rd_cmd_si_addr ),
.cmd_si_id (rd_cmd_si_id ),
.cmd_si_len (rd_cmd_si_len ),
.cmd_si_size (rd_cmd_si_size ),
.cmd_si_burst (rd_cmd_si_burst),
// Slave Interface Write Address Ports
.S_AXI_AID (sr_arid),
.S_AXI_AADDR (sr_araddr),
.S_AXI_ALEN (sr_arlen),
.S_AXI_ASIZE (sr_arsize),
.S_AXI_ABURST (sr_arburst),
.S_AXI_ALOCK (sr_arlock),
.S_AXI_ACACHE (sr_arcache),
.S_AXI_APROT (sr_arprot),
.S_AXI_AREGION (sr_arregion),
.S_AXI_AQOS (sr_arqos),
.S_AXI_AVALID (sr_arvalid),
.S_AXI_AREADY (sr_arready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_araddr_i ),
.M_AXI_ALEN (m_axi_arlen_i ),
.M_AXI_ASIZE (m_axi_arsize_i ),
.M_AXI_ABURST (m_axi_arburst_i ),
.M_AXI_ALOCK (m_axi_arlock_i ),
.M_AXI_ACACHE (m_axi_arcache_i ),
.M_AXI_APROT (m_axi_arprot_i ),
.M_AXI_AREGION (m_axi_arregion_i ),
.M_AXI_AQOS (m_axi_arqos_i ),
.M_AXI_AVALID (m_axi_arvalid_i ),
.M_AXI_AREADY (m_axi_arready_i )
);
if ((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK)) begin : gen_pktfifo_r_upsizer
// Packet FIFO Read Data channel.
axi_dwidth_converter_v2_1_7_r_upsizer_pktfifo #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG),
.C_CLK_CONV (P_CLK_CONV),
.C_S_AXI_ACLK_RATIO (C_S_AXI_ACLK_RATIO),
.C_M_AXI_ACLK_RATIO (C_M_AXI_ACLK_RATIO),
.C_AXI_IS_ACLK_ASYNC (C_AXI_IS_ACLK_ASYNC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
) pktfifo_read_data_inst
(
.S_AXI_ARESETN ( s_axi_aresetn ) ,
.S_AXI_ACLK ( s_axi_aclk ) ,
.M_AXI_ARESETN ( m_axi_aresetn ) ,
.M_AXI_ACLK ( m_axi_aclk ) ,
// Command Interface
.cmd_si_addr (rd_cmd_si_addr ),
.cmd_si_id (rd_cmd_si_id ),
.cmd_si_len (rd_cmd_si_len ),
.cmd_si_size (rd_cmd_si_size ),
.cmd_si_burst (rd_cmd_si_burst),
.cmd_ready (rd_cmd_ready),
// Slave Interface Write Address Ports
.S_AXI_ARADDR (m_axi_araddr_i ),
.S_AXI_ARLEN (m_axi_arlen_i ),
.S_AXI_ARSIZE (m_axi_arsize_i ),
.S_AXI_ARBURST (m_axi_arburst_i ),
.S_AXI_ARLOCK (m_axi_arlock_i ),
.S_AXI_ARCACHE (m_axi_arcache_i ),
.S_AXI_ARPROT (m_axi_arprot_i ),
.S_AXI_ARREGION (m_axi_arregion_i ),
.S_AXI_ARQOS (m_axi_arqos_i ),
.S_AXI_ARVALID (m_axi_arvalid_i ),
.S_AXI_ARREADY (m_axi_arready_i ),
// Master Interface Write Address Port
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARLEN (m_axi_arlen),
.M_AXI_ARSIZE (m_axi_arsize),
.M_AXI_ARBURST (m_axi_arburst),
.M_AXI_ARLOCK (m_axi_arlock),
.M_AXI_ARCACHE (m_axi_arcache),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARREGION (m_axi_arregion),
.M_AXI_ARQOS (m_axi_arqos),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
// Slave Interface Write Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Write Data Ports
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready),
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early)
);
end else begin : gen_non_fifo_r_upsizer
// Read Data channel.
axi_dwidth_converter_v2_1_7_r_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_S_AXI_REGISTER (C_S_AXI_R_REGISTER),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG)
) read_data_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_fix (rd_cmd_fix),
.cmd_modified (rd_cmd_modified),
.cmd_complete_wrap (rd_cmd_complete_wrap),
.cmd_packed_wrap (rd_cmd_packed_wrap),
.cmd_first_word (rd_cmd_first_word),
.cmd_next_word (rd_cmd_next_word),
.cmd_last_word (rd_cmd_last_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
// Slave Interface Read Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Read Data Ports
.M_AXI_RDATA (mr_rdata),
.M_AXI_RRESP (mr_rresp),
.M_AXI_RLAST (mr_rlast),
.M_AXI_RVALID (mr_rvalid),
.M_AXI_RREADY (mr_rready)
);
axi_register_slice_v2_1_7_axi_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (0),
.C_AXI_ID_WIDTH (1),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (0),
.C_REG_CONFIG_R (C_M_AXI_R_REGISTER)
)
mi_register_slice_inst
(
.aresetn (s_aresetn_i),
.aclk (m_aclk),
.s_axi_awid ( 1'b0 ),
.s_axi_awaddr ( {C_AXI_ADDR_WIDTH{1'b0}} ),
.s_axi_awlen ( 8'b0 ),
.s_axi_awsize ( 3'b0 ),
.s_axi_awburst ( 2'b0 ),
.s_axi_awlock ( 1'b0 ),
.s_axi_awcache ( 4'b0 ),
.s_axi_awprot ( 3'b0 ),
.s_axi_awregion ( 4'b0 ),
.s_axi_awqos ( 4'b0 ),
.s_axi_awuser ( 1'b0 ),
.s_axi_awvalid ( 1'b0 ),
.s_axi_awready ( ),
.s_axi_wid ( 1'b0 ),
.s_axi_wdata ( {C_M_AXI_DATA_WIDTH{1'b0}} ),
.s_axi_wstrb ( {C_M_AXI_DATA_WIDTH/8{1'b0}} ),
.s_axi_wlast ( 1'b0 ),
.s_axi_wuser ( 1'b0 ),
.s_axi_wvalid ( 1'b0 ),
.s_axi_wready ( ),
.s_axi_bid ( ),
.s_axi_bresp ( ),
.s_axi_buser ( ),
.s_axi_bvalid ( ),
.s_axi_bready ( 1'b0 ),
.s_axi_arid ( 1'b0 ),
.s_axi_araddr ( {C_AXI_ADDR_WIDTH{1'b0}} ),
.s_axi_arlen ( 8'b0 ),
.s_axi_arsize ( 3'b0 ),
.s_axi_arburst ( 2'b0 ),
.s_axi_arlock ( 1'b0 ),
.s_axi_arcache ( 4'b0 ),
.s_axi_arprot ( 3'b0 ),
.s_axi_arregion ( 4'b0 ),
.s_axi_arqos ( 4'b0 ),
.s_axi_aruser ( 1'b0 ),
.s_axi_arvalid ( 1'b0 ),
.s_axi_arready ( ),
.s_axi_rid (),
.s_axi_rdata (mr_rdata ),
.s_axi_rresp (mr_rresp ),
.s_axi_rlast (mr_rlast ),
.s_axi_ruser (),
.s_axi_rvalid (mr_rvalid ),
.s_axi_rready (mr_rready ),
.m_axi_awid (),
.m_axi_awaddr (),
.m_axi_awlen (),
.m_axi_awsize (),
.m_axi_awburst (),
.m_axi_awlock (),
.m_axi_awcache (),
.m_axi_awprot (),
.m_axi_awregion (),
.m_axi_awqos (),
.m_axi_awuser (),
.m_axi_awvalid (),
.m_axi_awready (1'b0),
.m_axi_wid () ,
.m_axi_wdata (),
.m_axi_wstrb (),
.m_axi_wlast (),
.m_axi_wuser (),
.m_axi_wvalid (),
.m_axi_wready (1'b0),
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( 2'b0 ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( 1'b0 ) ,
.m_axi_bready ( ) ,
.m_axi_arid (),
.m_axi_araddr (),
.m_axi_arlen (),
.m_axi_arsize (),
.m_axi_arburst (),
.m_axi_arlock (),
.m_axi_arcache (),
.m_axi_arprot (),
.m_axi_arregion (),
.m_axi_arqos (),
.m_axi_aruser (),
.m_axi_arvalid (),
.m_axi_arready (1'b0),
.m_axi_rid (1'b0 ),
.m_axi_rdata (m_axi_rdata ),
.m_axi_rresp (m_axi_rresp ),
.m_axi_rlast (m_axi_rlast ),
.m_axi_ruser (1'b0 ),
.m_axi_rvalid (m_axi_rvalid ),
.m_axi_rready (m_axi_rready_i )
);
assign m_axi_araddr = m_axi_araddr_i ;
assign m_axi_arlen = m_axi_arlen_i ;
assign m_axi_arsize = m_axi_arsize_i ;
assign m_axi_arburst = m_axi_arburst_i ;
assign m_axi_arlock = m_axi_arlock_i ;
assign m_axi_arcache = m_axi_arcache_i ;
assign m_axi_arprot = m_axi_arprot_i ;
assign m_axi_arregion = m_axi_arregion_i ;
assign m_axi_arqos = m_axi_arqos_i ;
assign m_axi_arvalid = m_axi_arvalid_i ;
assign m_axi_arready_i = m_axi_arready ;
assign m_axi_rready = m_axi_rready_i;
end // gen_r_upsizer
end else begin : NO_READ
assign sr_arready = 1'b0;
assign s_axi_rid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_rdata = {C_S_AXI_DATA_WIDTH{1'b0}};
assign s_axi_rresp = 2'b0;
assign s_axi_rlast = 1'b0;
assign s_axi_rvalid = 1'b0;
assign m_axi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_arlen = 8'b0;
assign m_axi_arsize = 3'b0;
assign m_axi_arburst = 2'b0;
assign m_axi_arlock = 2'b0;
assign m_axi_arcache = 4'b0;
assign m_axi_arprot = 3'b0;
assign m_axi_arregion = 4'b0;
assign m_axi_arqos = 4'b0;
assign m_axi_arvalid = 1'b0;
assign mr_rready = 1'b0;
end
endgenerate
endmodule
`default_nettype wire
|
/*
* Titor - Barrel Processor - Performs sign extension of halfword integers
* Copyright (C) 2012 Sean Ryan Moore
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`ifdef INC_Sign_Ext_Imm
`else
`define INC_Sign_Ext_Imm
`timescale 1 ns / 100 ps
// Combinational module
// takes a two's complement, WORD/2 bit number and conditionally sign extends to WORD bits
module Sign_Ext_Imm (
result,
operand,
enable
);
`include "definition/Definition.v"
output [WORD-1:0] result;
input [WORD-1:0] operand;
input enable;
Sign_Ext_Return standin(
.result(result),
.operand(operand),
.size(IMM_EXT_CONSTANT),
.signage(enable)
);
endmodule
`endif
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Johan Bjork.
// SPDX-License-Identifier: CC0-1.0
parameter N = 4;
interface a_if #(parameter PARAM = 0) ();
logic long_name;
modport source (output long_name);
modport sink (input long_name);
endinterface
module intf_source
(
input logic [N-1:0] intf_input,
a_if.source i_intf_source[N-1:0]
);
generate
for (genvar i=0; i < N;i++) begin
assign i_intf_source[i].long_name = intf_input[i];
end
endgenerate
endmodule
module intf_sink
(
output [N-1:0] a_out,
a_if.sink i_intf_sink[N-1:0]
);
generate
for (genvar i=0; i < N;i++) begin
assign a_out[i] = i_intf_sink[i].long_name;
end
endgenerate
endmodule
module t
(
clk
);
input clk;
logic [N-1:0] a_in;
logic [N-1:0] a_out;
logic [N-1:0] ack_out;
// verilator lint_off LITENDIAN
a_if #(.PARAM(1)) tl_intf [N] ();
// verilator lint_on LITENDIAN
intf_source source(a_in, tl_intf);
intf_sink sink(a_out, tl_intf);
initial a_in = '0;
always @(posedge clk) begin
a_in <= a_in + { {N-1 {1'b0}}, 1'b1 };
ack_out <= ack_out + { {N-1 {1'b0}}, 1'b1 };
if (ack_out != a_out) begin
$stop;
end
if (& a_in) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.0
// \ \ Application: MIG
// / / Filename: ddr2_chipscope.v
// /___/ /\ Date Last Modified: $Data$
// \ \ / \ Date Created: 9/14/06
// \___\/\___\
//
//Device: Virtex-5
//Purpose:
// Skeleton Chipscope module declarations - for simulation only
//Reference:
//Revision History:
//
//*****************************************************************************
`timescale 1ns/1ps
module icon4
(
control0,
control1,
control2,
control3
)
/* synthesis syn_black_box syn_noprune = 1 */;
output [35:0] control0;
output [35:0] control1;
output [35:0] control2;
output [35:0] control3;
endmodule
module vio_async_in192
(
control,
async_in
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input [191:0] async_in;
endmodule
module vio_async_in96
(
control,
async_in
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input [95:0] async_in;
endmodule
module vio_async_in100
(
control,
async_in
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input [99:0] async_in;
endmodule
module vio_sync_out32
(
control,
clk,
sync_out
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input clk;
output [31:0] sync_out;
endmodule |
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
reg [1:0] out;
reg in;
initial begin
in = 1;
out = in << 1;
if (out !== 2'b10) begin
$display("FAILED (1) -- out == %b", out);
$finish;
end
out <= in << 1;
#1 if (out !== 2'b10) begin
$display("FAILED (2) -- out == %b", out);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:10:50 05/23/2014
// Design Name: CPU_top
// Module Name: E:/3120101980/pipelinecpu/test.v
// Project Name: pipelinecpu
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: CPU_top
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test;
// Inputs
reg clock;
reg memclock;
reg resetn;
// Outputs
wire [31:0] pc;
wire [31:0] inst;
wire [31:0] ealu;
wire [31:0] malu;
wire [31:0] walu;
// Instantiate the Unit Under Test (UUT)
CPU_top uut (
.clock(clock),
.memclock(memclock),
.resetn(resetn),
.pc(pc),
.inst(inst),
.ealu(ealu),
.malu(malu),
.walu(walu)
);
initial begin
// Initialize Inputs
resetn = 1;
clock=0;
memclock=0;
// Wait 100 ns for global reset to finish
#11; resetn= 0;
// Add stimulus here
end
initial forever begin
#1; memclock=~memclock;
#1;memclock=~memclock; clock=~clock;
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_64.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the tx_engine and buffers the input
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module tx_port_64 #(
parameter C_DATA_WIDTH = 9'd64,
parameter C_FIFO_DEPTH = 512,
// Local parameters
parameter C_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
input TXN_DONE_ACK, // Write transaction actual transfer length read
input [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather data
input SG_DATA_EMPTY, // Scatter gather buffer empty
output SG_DATA_REN, // Scatter gather data read enable
output SG_RST, // Scatter gather reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output [C_DATA_WIDTH-1:0] TX_DATA, // Outgoing write data
input TX_DATA_REN, // Outgoing write data read enable
input TX_SENT, // Outgoing write complete
input CHNL_CLK, // Channel write clock
input CHNL_TX, // Channel write receive signal
output CHNL_TX_ACK, // Channel write acknowledgement signal
input CHNL_TX_LAST, // Channel last write
input [31:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [30:0] CHNL_TX_OFF, // Channel write offset
input [C_DATA_WIDTH-1:0] CHNL_TX_DATA, // Channel write data
input CHNL_TX_DATA_VALID, // Channel write data valid
output CHNL_TX_DATA_REN // Channel write data has been recieved
);
`include "functions.vh"
wire wGateRen;
wire wGateEmpty;
wire [C_DATA_WIDTH:0] wGateData;
wire wBufWen;
wire [C_FIFO_DEPTH_WIDTH-1:0] wBufCount;
wire [C_DATA_WIDTH-1:0] wBufData;
wire wTxn;
wire wTxnAck;
wire wTxnLast;
wire [31:0] wTxnLen;
wire [30:0] wTxnOff;
wire [31:0] wTxnWordsRecvd;
wire wTxnDone;
wire wTxnErr;
wire wSgElemRen;
wire wSgElemRdy;
wire wSgElemEmpty;
wire [31:0] wSgElemLen;
wire [63:0] wSgElemAddr;
wire wTxLast;
reg [4:0] rWideRst=0;
reg rRst=0;
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Capture channel transaction open/close events as well as channel data.
tx_port_channel_gate_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.RD_CLK(CLK),
.RD_DATA(wGateData),
.RD_EMPTY(wGateEmpty),
.RD_EN(wGateRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_TX(CHNL_TX),
.CHNL_TX_ACK(CHNL_TX_ACK),
.CHNL_TX_LAST(CHNL_TX_LAST),
.CHNL_TX_LEN(CHNL_TX_LEN),
.CHNL_TX_OFF(CHNL_TX_OFF),
.CHNL_TX_DATA(CHNL_TX_DATA),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN)
);
// Filter transaction events from channel data. Use the events to put only
// the requested amount of data into the port buffer.
tx_port_monitor_64 #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) monitor (
.RST(rRst),
.CLK(CLK),
.EVT_DATA(wGateData),
.EVT_DATA_EMPTY(wGateEmpty),
.EVT_DATA_RD_EN(wGateRen),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount),
.TXN(wTxn),
.ACK(wTxnAck),
.LAST(wTxnLast),
.LEN(wTxnLen),
.OFF(wTxnOff),
.WORDS_RECVD(wTxnWordsRecvd),
.DONE(wTxnDone),
.TX_ERR(SG_ERR)
);
// Buffer the incoming channel data. Also make sure to discard only as
// much data as is needed for a transfer (which may involve non-integral
// packets (i.e. reading only 1 word out of the packet).
tx_port_buffer_64 #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_FIFO_DEPTH)) buffer (
.CLK(CLK),
.RST(rRst | (TXN_DONE & wTxnErr)),
.RD_DATA(TX_DATA),
.RD_EN(TX_DATA_REN),
.LEN_VALID(TX_REQ_ACK),
.LEN_LSB(TX_LEN[0]),
.LEN_LAST(wTxLast),
.WR_DATA(wBufData),
.WR_EN(wBufWen),
.WR_COUNT(wBufCount)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_64 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | SG_RST),
.BUF_DATA(SG_DATA),
.BUF_DATA_EMPTY(SG_DATA_EMPTY),
.BUF_DATA_REN(SG_DATA_REN),
.VALID(wSgElemRdy),
.EMPTY(wSgElemEmpty),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Controls the flow of request to the tx engine for transfers in a transaction.
tx_port_writer writer (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.TXN(TXN),
.TXN_ACK(TXN_ACK),
.TXN_LEN(TXN_LEN),
.TXN_OFF_LAST(TXN_OFF_LAST),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.NEW_TXN(wTxn),
.NEW_TXN_ACK(wTxnAck),
.NEW_TXN_LAST(wTxnLast),
.NEW_TXN_LEN(wTxnLen),
.NEW_TXN_OFF(wTxnOff),
.NEW_TXN_WORDS_RECVD(wTxnWordsRecvd),
.NEW_TXN_DONE(wTxnDone),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_EMPTY(wSgElemEmpty),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(SG_RST),
.SG_ERR(SG_ERR),
.TX_REQ(TX_REQ),
.TX_REQ_ACK(TX_REQ_ACK),
.TX_ADDR(TX_ADDR),
.TX_LEN(TX_LEN),
.TX_LAST(wTxLast),
.TX_SENT(TX_SENT)
);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="image_filter,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=6.666670,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=5.758000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=586,HLS_SYN_LUT=990}" *)
module image_filter (
INPUT_STREAM_TDATA,
INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST,
INPUT_STREAM_TID,
INPUT_STREAM_TDEST,
OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST,
rows,
cols,
ap_clk,
ap_rst_n,
ap_start,
INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY,
OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY,
ap_done,
ap_idle,
ap_ready
);
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_true = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_lv8_0 = 8'b00000000;
parameter ap_const_lv8_1 = 8'b1;
input [31:0] INPUT_STREAM_TDATA;
input [3:0] INPUT_STREAM_TKEEP;
input [3:0] INPUT_STREAM_TSTRB;
input [0:0] INPUT_STREAM_TUSER;
input [0:0] INPUT_STREAM_TLAST;
input [0:0] INPUT_STREAM_TID;
input [0:0] INPUT_STREAM_TDEST;
output [31:0] OUTPUT_STREAM_TDATA;
output [3:0] OUTPUT_STREAM_TKEEP;
output [3:0] OUTPUT_STREAM_TSTRB;
output [0:0] OUTPUT_STREAM_TUSER;
output [0:0] OUTPUT_STREAM_TLAST;
output [0:0] OUTPUT_STREAM_TID;
output [0:0] OUTPUT_STREAM_TDEST;
input [31:0] rows;
input [31:0] cols;
input ap_clk;
input ap_rst_n;
input ap_start;
input INPUT_STREAM_TVALID;
output INPUT_STREAM_TREADY;
output OUTPUT_STREAM_TVALID;
input OUTPUT_STREAM_TREADY;
output ap_done;
output ap_idle;
output ap_ready;
reg ap_idle;
reg ap_rst_n_inv;
wire image_filter_Block_proc_U0_ap_start;
wire image_filter_Block_proc_U0_ap_done;
reg image_filter_Block_proc_U0_ap_continue;
wire image_filter_Block_proc_U0_ap_idle;
wire image_filter_Block_proc_U0_ap_ready;
wire [31:0] image_filter_Block_proc_U0_rows;
wire [31:0] image_filter_Block_proc_U0_cols;
wire [11:0] image_filter_Block_proc_U0_ap_return_0;
wire [11:0] image_filter_Block_proc_U0_ap_return_1;
wire [11:0] image_filter_Block_proc_U0_ap_return_2;
wire [11:0] image_filter_Block_proc_U0_ap_return_3;
reg ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V;
wire img_1_rows_V_full_n;
reg ap_reg_ready_img_1_rows_V_full_n = 1'b0;
reg ap_sig_ready_img_1_rows_V_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel;
wire img_0_rows_V_channel_full_n;
reg ap_reg_ready_img_0_rows_V_channel_full_n = 1'b0;
reg ap_sig_ready_img_0_rows_V_channel_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V;
wire img_1_cols_V_full_n;
reg ap_reg_ready_img_1_cols_V_full_n = 1'b0;
reg ap_sig_ready_img_1_cols_V_full_n;
reg ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel;
wire img_0_cols_V_channel_full_n;
reg ap_reg_ready_img_0_cols_V_channel_full_n = 1'b0;
reg ap_sig_ready_img_0_cols_V_channel_full_n;
wire image_filter_AXIvideo2Mat_U0_ap_start;
wire image_filter_AXIvideo2Mat_U0_ap_done;
wire image_filter_AXIvideo2Mat_U0_ap_continue;
wire image_filter_AXIvideo2Mat_U0_ap_idle;
wire image_filter_AXIvideo2Mat_U0_ap_ready;
wire [31:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA;
wire image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID;
wire image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY;
wire [3:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP;
wire [3:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB;
wire [0:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER;
wire [0:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST;
wire [0:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID;
wire [0:0] image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST;
wire [11:0] image_filter_AXIvideo2Mat_U0_img_rows_V_read;
wire [11:0] image_filter_AXIvideo2Mat_U0_img_cols_V_read;
wire [7:0] image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din;
wire image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n;
wire image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write;
wire [7:0] image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din;
wire image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n;
wire image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write;
wire [7:0] image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din;
wire image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n;
wire image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write;
wire image_filter_Loop_1_proc_U0_ap_start;
wire image_filter_Loop_1_proc_U0_ap_done;
wire image_filter_Loop_1_proc_U0_ap_continue;
wire image_filter_Loop_1_proc_U0_ap_idle;
wire image_filter_Loop_1_proc_U0_ap_ready;
wire [31:0] image_filter_Loop_1_proc_U0_rows;
wire [31:0] image_filter_Loop_1_proc_U0_cols;
wire [7:0] image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din;
wire image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n;
wire image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write;
wire [7:0] image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din;
wire image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n;
wire image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write;
wire [7:0] image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din;
wire image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n;
wire image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write;
wire [7:0] image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout;
wire image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n;
wire image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read;
wire [7:0] image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout;
wire image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n;
wire image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read;
wire [7:0] image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout;
wire image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n;
wire image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read;
wire [1:0] image_filter_Loop_1_proc_U0_buffer_val_0_address0;
wire image_filter_Loop_1_proc_U0_buffer_val_0_ce0;
wire image_filter_Loop_1_proc_U0_buffer_val_0_we0;
wire [7:0] image_filter_Loop_1_proc_U0_buffer_val_0_d0;
wire [7:0] image_filter_Loop_1_proc_U0_buffer_val_0_q0;
wire [1:0] image_filter_Loop_1_proc_U0_buffer_val_0_address1;
wire image_filter_Loop_1_proc_U0_buffer_val_0_ce1;
wire image_filter_Loop_1_proc_U0_buffer_val_0_we1;
wire [7:0] image_filter_Loop_1_proc_U0_buffer_val_0_d1;
wire [7:0] image_filter_Loop_1_proc_U0_buffer_val_0_q1;
wire [1:0] image_filter_Loop_1_proc_U0_buffer_val_1_address0;
wire image_filter_Loop_1_proc_U0_buffer_val_1_ce0;
wire image_filter_Loop_1_proc_U0_buffer_val_1_we0;
wire [7:0] image_filter_Loop_1_proc_U0_buffer_val_1_d0;
wire [7:0] image_filter_Loop_1_proc_U0_buffer_val_1_q0;
wire [1:0] image_filter_Loop_1_proc_U0_buffer_val_1_address1;
wire image_filter_Loop_1_proc_U0_buffer_val_1_ce1;
wire image_filter_Loop_1_proc_U0_buffer_val_1_we1;
wire [7:0] image_filter_Loop_1_proc_U0_buffer_val_1_d1;
wire [7:0] image_filter_Loop_1_proc_U0_buffer_val_1_q1;
wire [1:0] image_filter_Loop_1_proc_U0_buffer_val_2_address0;
wire image_filter_Loop_1_proc_U0_buffer_val_2_ce0;
wire image_filter_Loop_1_proc_U0_buffer_val_2_we0;
wire [7:0] image_filter_Loop_1_proc_U0_buffer_val_2_d0;
wire [7:0] image_filter_Loop_1_proc_U0_buffer_val_2_q0;
wire [1:0] image_filter_Loop_1_proc_U0_buffer_val_2_address1;
wire image_filter_Loop_1_proc_U0_buffer_val_2_ce1;
wire image_filter_Loop_1_proc_U0_buffer_val_2_we1;
wire [7:0] image_filter_Loop_1_proc_U0_buffer_val_2_d1;
wire [7:0] image_filter_Loop_1_proc_U0_buffer_val_2_q1;
wire image_filter_Mat2AXIvideo_U0_ap_start;
wire image_filter_Mat2AXIvideo_U0_ap_done;
wire image_filter_Mat2AXIvideo_U0_ap_continue;
wire image_filter_Mat2AXIvideo_U0_ap_idle;
wire image_filter_Mat2AXIvideo_U0_ap_ready;
wire [11:0] image_filter_Mat2AXIvideo_U0_img_rows_V_read;
wire [11:0] image_filter_Mat2AXIvideo_U0_img_cols_V_read;
wire [7:0] image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout;
wire image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n;
wire image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read;
wire [7:0] image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout;
wire image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n;
wire image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read;
wire [7:0] image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout;
wire image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n;
wire image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read;
wire [31:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA;
wire image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID;
wire image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY;
wire [3:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP;
wire [3:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB;
wire [0:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER;
wire [0:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST;
wire [0:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID;
wire [0:0] image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST;
wire ap_sig_hs_continue;
wire img_0_rows_V_channel_U_ap_dummy_ce;
wire [11:0] img_0_rows_V_channel_din;
wire img_0_rows_V_channel_write;
wire [11:0] img_0_rows_V_channel_dout;
wire img_0_rows_V_channel_empty_n;
wire img_0_rows_V_channel_read;
wire img_0_cols_V_channel_U_ap_dummy_ce;
wire [11:0] img_0_cols_V_channel_din;
wire img_0_cols_V_channel_write;
wire [11:0] img_0_cols_V_channel_dout;
wire img_0_cols_V_channel_empty_n;
wire img_0_cols_V_channel_read;
wire img_1_rows_V_U_ap_dummy_ce;
wire [11:0] img_1_rows_V_din;
wire img_1_rows_V_write;
wire [11:0] img_1_rows_V_dout;
wire img_1_rows_V_empty_n;
wire img_1_rows_V_read;
wire img_1_cols_V_U_ap_dummy_ce;
wire [11:0] img_1_cols_V_din;
wire img_1_cols_V_write;
wire [11:0] img_1_cols_V_dout;
wire img_1_cols_V_empty_n;
wire img_1_cols_V_read;
wire img_0_data_stream_0_V_U_ap_dummy_ce;
wire [7:0] img_0_data_stream_0_V_din;
wire img_0_data_stream_0_V_full_n;
wire img_0_data_stream_0_V_write;
wire [7:0] img_0_data_stream_0_V_dout;
wire img_0_data_stream_0_V_empty_n;
wire img_0_data_stream_0_V_read;
wire img_0_data_stream_1_V_U_ap_dummy_ce;
wire [7:0] img_0_data_stream_1_V_din;
wire img_0_data_stream_1_V_full_n;
wire img_0_data_stream_1_V_write;
wire [7:0] img_0_data_stream_1_V_dout;
wire img_0_data_stream_1_V_empty_n;
wire img_0_data_stream_1_V_read;
wire img_0_data_stream_2_V_U_ap_dummy_ce;
wire [7:0] img_0_data_stream_2_V_din;
wire img_0_data_stream_2_V_full_n;
wire img_0_data_stream_2_V_write;
wire [7:0] img_0_data_stream_2_V_dout;
wire img_0_data_stream_2_V_empty_n;
wire img_0_data_stream_2_V_read;
wire img_1_data_stream_0_V_U_ap_dummy_ce;
wire [7:0] img_1_data_stream_0_V_din;
wire img_1_data_stream_0_V_full_n;
wire img_1_data_stream_0_V_write;
wire [7:0] img_1_data_stream_0_V_dout;
wire img_1_data_stream_0_V_empty_n;
wire img_1_data_stream_0_V_read;
wire img_1_data_stream_1_V_U_ap_dummy_ce;
wire [7:0] img_1_data_stream_1_V_din;
wire img_1_data_stream_1_V_full_n;
wire img_1_data_stream_1_V_write;
wire [7:0] img_1_data_stream_1_V_dout;
wire img_1_data_stream_1_V_empty_n;
wire img_1_data_stream_1_V_read;
wire img_1_data_stream_2_V_U_ap_dummy_ce;
wire [7:0] img_1_data_stream_2_V_din;
wire img_1_data_stream_2_V_full_n;
wire img_1_data_stream_2_V_write;
wire [7:0] img_1_data_stream_2_V_dout;
wire img_1_data_stream_2_V_empty_n;
wire img_1_data_stream_2_V_read;
reg ap_reg_procdone_image_filter_Block_proc_U0 = 1'b0;
reg ap_sig_hs_done;
reg ap_reg_procdone_image_filter_AXIvideo2Mat_U0 = 1'b0;
reg ap_reg_procdone_image_filter_Loop_1_proc_U0 = 1'b0;
reg ap_reg_procdone_image_filter_Mat2AXIvideo_U0 = 1'b0;
reg ap_CS;
wire ap_sig_top_allready;
image_filter_Block_proc image_filter_Block_proc_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst_n_inv ),
.ap_start( image_filter_Block_proc_U0_ap_start ),
.ap_done( image_filter_Block_proc_U0_ap_done ),
.ap_continue( image_filter_Block_proc_U0_ap_continue ),
.ap_idle( image_filter_Block_proc_U0_ap_idle ),
.ap_ready( image_filter_Block_proc_U0_ap_ready ),
.rows( image_filter_Block_proc_U0_rows ),
.cols( image_filter_Block_proc_U0_cols ),
.ap_return_0( image_filter_Block_proc_U0_ap_return_0 ),
.ap_return_1( image_filter_Block_proc_U0_ap_return_1 ),
.ap_return_2( image_filter_Block_proc_U0_ap_return_2 ),
.ap_return_3( image_filter_Block_proc_U0_ap_return_3 )
);
image_filter_AXIvideo2Mat image_filter_AXIvideo2Mat_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst_n_inv ),
.ap_start( image_filter_AXIvideo2Mat_U0_ap_start ),
.ap_done( image_filter_AXIvideo2Mat_U0_ap_done ),
.ap_continue( image_filter_AXIvideo2Mat_U0_ap_continue ),
.ap_idle( image_filter_AXIvideo2Mat_U0_ap_idle ),
.ap_ready( image_filter_AXIvideo2Mat_U0_ap_ready ),
.INPUT_STREAM_TDATA( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA ),
.INPUT_STREAM_TVALID( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID ),
.INPUT_STREAM_TREADY( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY ),
.INPUT_STREAM_TKEEP( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP ),
.INPUT_STREAM_TSTRB( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB ),
.INPUT_STREAM_TUSER( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER ),
.INPUT_STREAM_TLAST( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST ),
.INPUT_STREAM_TID( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID ),
.INPUT_STREAM_TDEST( image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST ),
.img_rows_V_read( image_filter_AXIvideo2Mat_U0_img_rows_V_read ),
.img_cols_V_read( image_filter_AXIvideo2Mat_U0_img_cols_V_read ),
.img_data_stream_0_V_din( image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din ),
.img_data_stream_0_V_full_n( image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n ),
.img_data_stream_0_V_write( image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write ),
.img_data_stream_1_V_din( image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din ),
.img_data_stream_1_V_full_n( image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n ),
.img_data_stream_1_V_write( image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write ),
.img_data_stream_2_V_din( image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din ),
.img_data_stream_2_V_full_n( image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n ),
.img_data_stream_2_V_write( image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write )
);
image_filter_Loop_1_proc image_filter_Loop_1_proc_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst_n_inv ),
.ap_start( image_filter_Loop_1_proc_U0_ap_start ),
.ap_done( image_filter_Loop_1_proc_U0_ap_done ),
.ap_continue( image_filter_Loop_1_proc_U0_ap_continue ),
.ap_idle( image_filter_Loop_1_proc_U0_ap_idle ),
.ap_ready( image_filter_Loop_1_proc_U0_ap_ready ),
.rows( image_filter_Loop_1_proc_U0_rows ),
.cols( image_filter_Loop_1_proc_U0_cols ),
.img_1_data_stream_0_V_din( image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din ),
.img_1_data_stream_0_V_full_n( image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n ),
.img_1_data_stream_0_V_write( image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write ),
.img_1_data_stream_1_V_din( image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din ),
.img_1_data_stream_1_V_full_n( image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n ),
.img_1_data_stream_1_V_write( image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write ),
.img_1_data_stream_2_V_din( image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din ),
.img_1_data_stream_2_V_full_n( image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n ),
.img_1_data_stream_2_V_write( image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write ),
.img_0_data_stream_0_V_dout( image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout ),
.img_0_data_stream_0_V_empty_n( image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n ),
.img_0_data_stream_0_V_read( image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read ),
.img_0_data_stream_1_V_dout( image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout ),
.img_0_data_stream_1_V_empty_n( image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n ),
.img_0_data_stream_1_V_read( image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read ),
.img_0_data_stream_2_V_dout( image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout ),
.img_0_data_stream_2_V_empty_n( image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n ),
.img_0_data_stream_2_V_read( image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read ),
.buffer_val_0_address0( image_filter_Loop_1_proc_U0_buffer_val_0_address0 ),
.buffer_val_0_ce0( image_filter_Loop_1_proc_U0_buffer_val_0_ce0 ),
.buffer_val_0_we0( image_filter_Loop_1_proc_U0_buffer_val_0_we0 ),
.buffer_val_0_d0( image_filter_Loop_1_proc_U0_buffer_val_0_d0 ),
.buffer_val_0_q0( image_filter_Loop_1_proc_U0_buffer_val_0_q0 ),
.buffer_val_0_address1( image_filter_Loop_1_proc_U0_buffer_val_0_address1 ),
.buffer_val_0_ce1( image_filter_Loop_1_proc_U0_buffer_val_0_ce1 ),
.buffer_val_0_we1( image_filter_Loop_1_proc_U0_buffer_val_0_we1 ),
.buffer_val_0_d1( image_filter_Loop_1_proc_U0_buffer_val_0_d1 ),
.buffer_val_0_q1( image_filter_Loop_1_proc_U0_buffer_val_0_q1 ),
.buffer_val_1_address0( image_filter_Loop_1_proc_U0_buffer_val_1_address0 ),
.buffer_val_1_ce0( image_filter_Loop_1_proc_U0_buffer_val_1_ce0 ),
.buffer_val_1_we0( image_filter_Loop_1_proc_U0_buffer_val_1_we0 ),
.buffer_val_1_d0( image_filter_Loop_1_proc_U0_buffer_val_1_d0 ),
.buffer_val_1_q0( image_filter_Loop_1_proc_U0_buffer_val_1_q0 ),
.buffer_val_1_address1( image_filter_Loop_1_proc_U0_buffer_val_1_address1 ),
.buffer_val_1_ce1( image_filter_Loop_1_proc_U0_buffer_val_1_ce1 ),
.buffer_val_1_we1( image_filter_Loop_1_proc_U0_buffer_val_1_we1 ),
.buffer_val_1_d1( image_filter_Loop_1_proc_U0_buffer_val_1_d1 ),
.buffer_val_1_q1( image_filter_Loop_1_proc_U0_buffer_val_1_q1 ),
.buffer_val_2_address0( image_filter_Loop_1_proc_U0_buffer_val_2_address0 ),
.buffer_val_2_ce0( image_filter_Loop_1_proc_U0_buffer_val_2_ce0 ),
.buffer_val_2_we0( image_filter_Loop_1_proc_U0_buffer_val_2_we0 ),
.buffer_val_2_d0( image_filter_Loop_1_proc_U0_buffer_val_2_d0 ),
.buffer_val_2_q0( image_filter_Loop_1_proc_U0_buffer_val_2_q0 ),
.buffer_val_2_address1( image_filter_Loop_1_proc_U0_buffer_val_2_address1 ),
.buffer_val_2_ce1( image_filter_Loop_1_proc_U0_buffer_val_2_ce1 ),
.buffer_val_2_we1( image_filter_Loop_1_proc_U0_buffer_val_2_we1 ),
.buffer_val_2_d1( image_filter_Loop_1_proc_U0_buffer_val_2_d1 ),
.buffer_val_2_q1( image_filter_Loop_1_proc_U0_buffer_val_2_q1 )
);
image_filter_Mat2AXIvideo image_filter_Mat2AXIvideo_U0(
.ap_clk( ap_clk ),
.ap_rst( ap_rst_n_inv ),
.ap_start( image_filter_Mat2AXIvideo_U0_ap_start ),
.ap_done( image_filter_Mat2AXIvideo_U0_ap_done ),
.ap_continue( image_filter_Mat2AXIvideo_U0_ap_continue ),
.ap_idle( image_filter_Mat2AXIvideo_U0_ap_idle ),
.ap_ready( image_filter_Mat2AXIvideo_U0_ap_ready ),
.img_rows_V_read( image_filter_Mat2AXIvideo_U0_img_rows_V_read ),
.img_cols_V_read( image_filter_Mat2AXIvideo_U0_img_cols_V_read ),
.img_data_stream_0_V_dout( image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout ),
.img_data_stream_0_V_empty_n( image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n ),
.img_data_stream_0_V_read( image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read ),
.img_data_stream_1_V_dout( image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout ),
.img_data_stream_1_V_empty_n( image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n ),
.img_data_stream_1_V_read( image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read ),
.img_data_stream_2_V_dout( image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout ),
.img_data_stream_2_V_empty_n( image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n ),
.img_data_stream_2_V_read( image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read ),
.OUTPUT_STREAM_TDATA( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA ),
.OUTPUT_STREAM_TVALID( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID ),
.OUTPUT_STREAM_TREADY( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY ),
.OUTPUT_STREAM_TKEEP( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP ),
.OUTPUT_STREAM_TSTRB( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB ),
.OUTPUT_STREAM_TUSER( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER ),
.OUTPUT_STREAM_TLAST( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST ),
.OUTPUT_STREAM_TID( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID ),
.OUTPUT_STREAM_TDEST( image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST )
);
FIFO_image_filter_img_0_rows_V_channel img_0_rows_V_channel_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_0_rows_V_channel_U_ap_dummy_ce ),
.if_write_ce( img_0_rows_V_channel_U_ap_dummy_ce ),
.if_din( img_0_rows_V_channel_din ),
.if_full_n( img_0_rows_V_channel_full_n ),
.if_write( img_0_rows_V_channel_write ),
.if_dout( img_0_rows_V_channel_dout ),
.if_empty_n( img_0_rows_V_channel_empty_n ),
.if_read( img_0_rows_V_channel_read )
);
FIFO_image_filter_img_0_cols_V_channel img_0_cols_V_channel_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_0_cols_V_channel_U_ap_dummy_ce ),
.if_write_ce( img_0_cols_V_channel_U_ap_dummy_ce ),
.if_din( img_0_cols_V_channel_din ),
.if_full_n( img_0_cols_V_channel_full_n ),
.if_write( img_0_cols_V_channel_write ),
.if_dout( img_0_cols_V_channel_dout ),
.if_empty_n( img_0_cols_V_channel_empty_n ),
.if_read( img_0_cols_V_channel_read )
);
FIFO_image_filter_img_1_rows_V img_1_rows_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_1_rows_V_U_ap_dummy_ce ),
.if_write_ce( img_1_rows_V_U_ap_dummy_ce ),
.if_din( img_1_rows_V_din ),
.if_full_n( img_1_rows_V_full_n ),
.if_write( img_1_rows_V_write ),
.if_dout( img_1_rows_V_dout ),
.if_empty_n( img_1_rows_V_empty_n ),
.if_read( img_1_rows_V_read )
);
FIFO_image_filter_img_1_cols_V img_1_cols_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_1_cols_V_U_ap_dummy_ce ),
.if_write_ce( img_1_cols_V_U_ap_dummy_ce ),
.if_din( img_1_cols_V_din ),
.if_full_n( img_1_cols_V_full_n ),
.if_write( img_1_cols_V_write ),
.if_dout( img_1_cols_V_dout ),
.if_empty_n( img_1_cols_V_empty_n ),
.if_read( img_1_cols_V_read )
);
FIFO_image_filter_img_0_data_stream_0_V img_0_data_stream_0_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_0_data_stream_0_V_U_ap_dummy_ce ),
.if_write_ce( img_0_data_stream_0_V_U_ap_dummy_ce ),
.if_din( img_0_data_stream_0_V_din ),
.if_full_n( img_0_data_stream_0_V_full_n ),
.if_write( img_0_data_stream_0_V_write ),
.if_dout( img_0_data_stream_0_V_dout ),
.if_empty_n( img_0_data_stream_0_V_empty_n ),
.if_read( img_0_data_stream_0_V_read )
);
FIFO_image_filter_img_0_data_stream_1_V img_0_data_stream_1_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_0_data_stream_1_V_U_ap_dummy_ce ),
.if_write_ce( img_0_data_stream_1_V_U_ap_dummy_ce ),
.if_din( img_0_data_stream_1_V_din ),
.if_full_n( img_0_data_stream_1_V_full_n ),
.if_write( img_0_data_stream_1_V_write ),
.if_dout( img_0_data_stream_1_V_dout ),
.if_empty_n( img_0_data_stream_1_V_empty_n ),
.if_read( img_0_data_stream_1_V_read )
);
FIFO_image_filter_img_0_data_stream_2_V img_0_data_stream_2_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_0_data_stream_2_V_U_ap_dummy_ce ),
.if_write_ce( img_0_data_stream_2_V_U_ap_dummy_ce ),
.if_din( img_0_data_stream_2_V_din ),
.if_full_n( img_0_data_stream_2_V_full_n ),
.if_write( img_0_data_stream_2_V_write ),
.if_dout( img_0_data_stream_2_V_dout ),
.if_empty_n( img_0_data_stream_2_V_empty_n ),
.if_read( img_0_data_stream_2_V_read )
);
FIFO_image_filter_img_1_data_stream_0_V img_1_data_stream_0_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_1_data_stream_0_V_U_ap_dummy_ce ),
.if_write_ce( img_1_data_stream_0_V_U_ap_dummy_ce ),
.if_din( img_1_data_stream_0_V_din ),
.if_full_n( img_1_data_stream_0_V_full_n ),
.if_write( img_1_data_stream_0_V_write ),
.if_dout( img_1_data_stream_0_V_dout ),
.if_empty_n( img_1_data_stream_0_V_empty_n ),
.if_read( img_1_data_stream_0_V_read )
);
FIFO_image_filter_img_1_data_stream_1_V img_1_data_stream_1_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_1_data_stream_1_V_U_ap_dummy_ce ),
.if_write_ce( img_1_data_stream_1_V_U_ap_dummy_ce ),
.if_din( img_1_data_stream_1_V_din ),
.if_full_n( img_1_data_stream_1_V_full_n ),
.if_write( img_1_data_stream_1_V_write ),
.if_dout( img_1_data_stream_1_V_dout ),
.if_empty_n( img_1_data_stream_1_V_empty_n ),
.if_read( img_1_data_stream_1_V_read )
);
FIFO_image_filter_img_1_data_stream_2_V img_1_data_stream_2_V_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.if_read_ce( img_1_data_stream_2_V_U_ap_dummy_ce ),
.if_write_ce( img_1_data_stream_2_V_U_ap_dummy_ce ),
.if_din( img_1_data_stream_2_V_din ),
.if_full_n( img_1_data_stream_2_V_full_n ),
.if_write( img_1_data_stream_2_V_write ),
.if_dout( img_1_data_stream_2_V_dout ),
.if_empty_n( img_1_data_stream_2_V_empty_n ),
.if_read( img_1_data_stream_2_V_read )
);
/// ap_reg_procdone_image_filter_AXIvideo2Mat_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_image_filter_AXIvideo2Mat_U0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == image_filter_AXIvideo2Mat_U0_ap_done)) begin
ap_reg_procdone_image_filter_AXIvideo2Mat_U0 <= ap_const_logic_1;
end
end
end
/// ap_reg_procdone_image_filter_Block_proc_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_image_filter_Block_proc_U0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_0;
end else if ((image_filter_Block_proc_U0_ap_done == ap_const_logic_1)) begin
ap_reg_procdone_image_filter_Block_proc_U0 <= ap_const_logic_1;
end
end
end
/// ap_reg_procdone_image_filter_Loop_1_proc_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_image_filter_Loop_1_proc_U0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == image_filter_Loop_1_proc_U0_ap_done)) begin
ap_reg_procdone_image_filter_Loop_1_proc_U0 <= ap_const_logic_1;
end
end
end
/// ap_reg_procdone_image_filter_Mat2AXIvideo_U0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_procdone_image_filter_Mat2AXIvideo_U0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_hs_done)) begin
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_0;
end else if ((ap_const_logic_1 == image_filter_Mat2AXIvideo_U0_ap_done)) begin
ap_reg_procdone_image_filter_Mat2AXIvideo_U0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_0_cols_V_channel_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_0_cols_V_channel_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_0_cols_V_channel_full_n))) begin
ap_reg_ready_img_0_cols_V_channel_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_0_rows_V_channel_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_0_rows_V_channel_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_0_rows_V_channel_full_n))) begin
ap_reg_ready_img_0_rows_V_channel_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_1_cols_V_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_1_cols_V_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (ap_const_logic_1 == img_1_cols_V_full_n))) begin
ap_reg_ready_img_1_cols_V_full_n <= ap_const_logic_1;
end
end
end
/// ap_reg_ready_img_1_rows_V_full_n assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ready_img_1_rows_V_full_n
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_0;
end else begin
if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (image_filter_Block_proc_U0_ap_continue == ap_const_logic_1))) begin
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_0;
end else if (((image_filter_Block_proc_U0_ap_done == ap_const_logic_1) & (img_1_rows_V_full_n == ap_const_logic_1))) begin
ap_reg_ready_img_1_rows_V_full_n <= ap_const_logic_1;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
ap_CS <= ap_const_logic_0;
end
/// ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_0_cols_V_channel_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_0_cols_V_channel_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_0_rows_V_channel_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_0_rows_V_channel_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_1_cols_V_full_n)
begin
if ((ap_const_logic_1 == ap_reg_ready_img_1_cols_V_full_n)) begin
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V assign process. ///
always @ (image_filter_Block_proc_U0_ap_done or ap_reg_ready_img_1_rows_V_full_n)
begin
if ((ap_reg_ready_img_1_rows_V_full_n == ap_const_logic_1)) begin
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V = ap_const_logic_0;
end else begin
ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V = image_filter_Block_proc_U0_ap_done;
end
end
/// ap_idle assign process. ///
always @ (image_filter_Block_proc_U0_ap_idle or image_filter_AXIvideo2Mat_U0_ap_idle or image_filter_Loop_1_proc_U0_ap_idle or image_filter_Mat2AXIvideo_U0_ap_idle or img_0_rows_V_channel_empty_n or img_0_cols_V_channel_empty_n or img_1_rows_V_empty_n or img_1_cols_V_empty_n)
begin
if (((image_filter_Block_proc_U0_ap_idle == ap_const_logic_1) & (ap_const_logic_1 == image_filter_AXIvideo2Mat_U0_ap_idle) & (ap_const_logic_1 == image_filter_Loop_1_proc_U0_ap_idle) & (ap_const_logic_1 == image_filter_Mat2AXIvideo_U0_ap_idle) & (ap_const_logic_0 == img_0_rows_V_channel_empty_n) & (ap_const_logic_0 == img_0_cols_V_channel_empty_n) & (ap_const_logic_0 == img_1_rows_V_empty_n) & (ap_const_logic_0 == img_1_cols_V_empty_n))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_sig_hs_done assign process. ///
always @ (image_filter_Mat2AXIvideo_U0_ap_done)
begin
if ((ap_const_logic_1 == image_filter_Mat2AXIvideo_U0_ap_done)) begin
ap_sig_hs_done = ap_const_logic_1;
end else begin
ap_sig_hs_done = ap_const_logic_0;
end
end
/// ap_sig_ready_img_0_cols_V_channel_full_n assign process. ///
always @ (img_0_cols_V_channel_full_n or ap_reg_ready_img_0_cols_V_channel_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_0_cols_V_channel_full_n)) begin
ap_sig_ready_img_0_cols_V_channel_full_n = img_0_cols_V_channel_full_n;
end else begin
ap_sig_ready_img_0_cols_V_channel_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_0_rows_V_channel_full_n assign process. ///
always @ (img_0_rows_V_channel_full_n or ap_reg_ready_img_0_rows_V_channel_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_0_rows_V_channel_full_n)) begin
ap_sig_ready_img_0_rows_V_channel_full_n = img_0_rows_V_channel_full_n;
end else begin
ap_sig_ready_img_0_rows_V_channel_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_1_cols_V_full_n assign process. ///
always @ (img_1_cols_V_full_n or ap_reg_ready_img_1_cols_V_full_n)
begin
if ((ap_const_logic_0 == ap_reg_ready_img_1_cols_V_full_n)) begin
ap_sig_ready_img_1_cols_V_full_n = img_1_cols_V_full_n;
end else begin
ap_sig_ready_img_1_cols_V_full_n = ap_const_logic_1;
end
end
/// ap_sig_ready_img_1_rows_V_full_n assign process. ///
always @ (img_1_rows_V_full_n or ap_reg_ready_img_1_rows_V_full_n)
begin
if ((ap_reg_ready_img_1_rows_V_full_n == ap_const_logic_0)) begin
ap_sig_ready_img_1_rows_V_full_n = img_1_rows_V_full_n;
end else begin
ap_sig_ready_img_1_rows_V_full_n = ap_const_logic_1;
end
end
/// image_filter_Block_proc_U0_ap_continue assign process. ///
always @ (ap_sig_ready_img_1_rows_V_full_n or ap_sig_ready_img_0_rows_V_channel_full_n or ap_sig_ready_img_1_cols_V_full_n or ap_sig_ready_img_0_cols_V_channel_full_n)
begin
if (((ap_sig_ready_img_1_rows_V_full_n == ap_const_logic_1) & (ap_const_logic_1 == ap_sig_ready_img_0_rows_V_channel_full_n) & (ap_const_logic_1 == ap_sig_ready_img_1_cols_V_full_n) & (ap_const_logic_1 == ap_sig_ready_img_0_cols_V_channel_full_n))) begin
image_filter_Block_proc_U0_ap_continue = ap_const_logic_1;
end else begin
image_filter_Block_proc_U0_ap_continue = ap_const_logic_0;
end
end
assign INPUT_STREAM_TREADY = image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TREADY;
assign OUTPUT_STREAM_TDATA = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDATA;
assign OUTPUT_STREAM_TDEST = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TDEST;
assign OUTPUT_STREAM_TID = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TID;
assign OUTPUT_STREAM_TKEEP = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TKEEP;
assign OUTPUT_STREAM_TLAST = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TLAST;
assign OUTPUT_STREAM_TSTRB = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TSTRB;
assign OUTPUT_STREAM_TUSER = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TUSER;
assign OUTPUT_STREAM_TVALID = image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TVALID;
assign ap_done = ap_sig_hs_done;
assign ap_ready = ap_sig_top_allready;
/// ap_rst_n_inv assign process. ///
always @ (ap_rst_n)
begin
ap_rst_n_inv = ~ap_rst_n;
end
assign ap_sig_hs_continue = ap_const_logic_1;
assign ap_sig_top_allready = image_filter_AXIvideo2Mat_U0_ap_ready;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDATA = INPUT_STREAM_TDATA;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TDEST = INPUT_STREAM_TDEST;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TID = INPUT_STREAM_TID;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TKEEP = INPUT_STREAM_TKEEP;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TLAST = INPUT_STREAM_TLAST;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TSTRB = INPUT_STREAM_TSTRB;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TUSER = INPUT_STREAM_TUSER;
assign image_filter_AXIvideo2Mat_U0_INPUT_STREAM_TVALID = INPUT_STREAM_TVALID;
assign image_filter_AXIvideo2Mat_U0_ap_continue = ap_const_logic_1;
assign image_filter_AXIvideo2Mat_U0_ap_start = (ap_start & img_0_rows_V_channel_empty_n & img_0_cols_V_channel_empty_n);
assign image_filter_AXIvideo2Mat_U0_img_cols_V_read = img_0_cols_V_channel_dout;
assign image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_full_n = img_0_data_stream_0_V_full_n;
assign image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_full_n = img_0_data_stream_1_V_full_n;
assign image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_full_n = img_0_data_stream_2_V_full_n;
assign image_filter_AXIvideo2Mat_U0_img_rows_V_read = img_0_rows_V_channel_dout;
assign image_filter_Block_proc_U0_ap_start = ap_start;
assign image_filter_Block_proc_U0_cols = cols;
assign image_filter_Block_proc_U0_rows = rows;
assign image_filter_Loop_1_proc_U0_ap_continue = ap_const_logic_1;
assign image_filter_Loop_1_proc_U0_ap_start = ap_start;
assign image_filter_Loop_1_proc_U0_buffer_val_0_q0 = ap_const_lv8_0;
assign image_filter_Loop_1_proc_U0_buffer_val_0_q1 = ap_const_lv8_0;
assign image_filter_Loop_1_proc_U0_buffer_val_1_q0 = ap_const_lv8_0;
assign image_filter_Loop_1_proc_U0_buffer_val_1_q1 = ap_const_lv8_0;
assign image_filter_Loop_1_proc_U0_buffer_val_2_q0 = ap_const_lv8_0;
assign image_filter_Loop_1_proc_U0_buffer_val_2_q1 = ap_const_lv8_0;
assign image_filter_Loop_1_proc_U0_cols = cols;
assign image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_dout = img_0_data_stream_0_V_dout;
assign image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_empty_n = img_0_data_stream_0_V_empty_n;
assign image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_dout = img_0_data_stream_1_V_dout;
assign image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_empty_n = img_0_data_stream_1_V_empty_n;
assign image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_dout = img_0_data_stream_2_V_dout;
assign image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_empty_n = img_0_data_stream_2_V_empty_n;
assign image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_full_n = img_1_data_stream_0_V_full_n;
assign image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_full_n = img_1_data_stream_1_V_full_n;
assign image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_full_n = img_1_data_stream_2_V_full_n;
assign image_filter_Loop_1_proc_U0_rows = rows;
assign image_filter_Mat2AXIvideo_U0_OUTPUT_STREAM_TREADY = OUTPUT_STREAM_TREADY;
assign image_filter_Mat2AXIvideo_U0_ap_continue = ap_sig_hs_continue;
assign image_filter_Mat2AXIvideo_U0_ap_start = (img_1_rows_V_empty_n & img_1_cols_V_empty_n);
assign image_filter_Mat2AXIvideo_U0_img_cols_V_read = img_1_cols_V_dout;
assign image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_dout = img_1_data_stream_0_V_dout;
assign image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_empty_n = img_1_data_stream_0_V_empty_n;
assign image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_dout = img_1_data_stream_1_V_dout;
assign image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_empty_n = img_1_data_stream_1_V_empty_n;
assign image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_dout = img_1_data_stream_2_V_dout;
assign image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_empty_n = img_1_data_stream_2_V_empty_n;
assign image_filter_Mat2AXIvideo_U0_img_rows_V_read = img_1_rows_V_dout;
assign img_0_cols_V_channel_U_ap_dummy_ce = ap_const_logic_1;
assign img_0_cols_V_channel_din = image_filter_Block_proc_U0_ap_return_1;
assign img_0_cols_V_channel_read = image_filter_AXIvideo2Mat_U0_ap_ready;
assign img_0_cols_V_channel_write = ap_chn_write_image_filter_Block_proc_U0_img_0_cols_V_channel;
assign img_0_data_stream_0_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_0_data_stream_0_V_din = image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_din;
assign img_0_data_stream_0_V_read = image_filter_Loop_1_proc_U0_img_0_data_stream_0_V_read;
assign img_0_data_stream_0_V_write = image_filter_AXIvideo2Mat_U0_img_data_stream_0_V_write;
assign img_0_data_stream_1_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_0_data_stream_1_V_din = image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_din;
assign img_0_data_stream_1_V_read = image_filter_Loop_1_proc_U0_img_0_data_stream_1_V_read;
assign img_0_data_stream_1_V_write = image_filter_AXIvideo2Mat_U0_img_data_stream_1_V_write;
assign img_0_data_stream_2_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_0_data_stream_2_V_din = image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_din;
assign img_0_data_stream_2_V_read = image_filter_Loop_1_proc_U0_img_0_data_stream_2_V_read;
assign img_0_data_stream_2_V_write = image_filter_AXIvideo2Mat_U0_img_data_stream_2_V_write;
assign img_0_rows_V_channel_U_ap_dummy_ce = ap_const_logic_1;
assign img_0_rows_V_channel_din = image_filter_Block_proc_U0_ap_return_0;
assign img_0_rows_V_channel_read = image_filter_AXIvideo2Mat_U0_ap_ready;
assign img_0_rows_V_channel_write = ap_chn_write_image_filter_Block_proc_U0_img_0_rows_V_channel;
assign img_1_cols_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_1_cols_V_din = image_filter_Block_proc_U0_ap_return_3;
assign img_1_cols_V_read = image_filter_Mat2AXIvideo_U0_ap_ready;
assign img_1_cols_V_write = ap_chn_write_image_filter_Block_proc_U0_img_1_cols_V;
assign img_1_data_stream_0_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_1_data_stream_0_V_din = image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_din;
assign img_1_data_stream_0_V_read = image_filter_Mat2AXIvideo_U0_img_data_stream_0_V_read;
assign img_1_data_stream_0_V_write = image_filter_Loop_1_proc_U0_img_1_data_stream_0_V_write;
assign img_1_data_stream_1_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_1_data_stream_1_V_din = image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_din;
assign img_1_data_stream_1_V_read = image_filter_Mat2AXIvideo_U0_img_data_stream_1_V_read;
assign img_1_data_stream_1_V_write = image_filter_Loop_1_proc_U0_img_1_data_stream_1_V_write;
assign img_1_data_stream_2_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_1_data_stream_2_V_din = image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_din;
assign img_1_data_stream_2_V_read = image_filter_Mat2AXIvideo_U0_img_data_stream_2_V_read;
assign img_1_data_stream_2_V_write = image_filter_Loop_1_proc_U0_img_1_data_stream_2_V_write;
assign img_1_rows_V_U_ap_dummy_ce = ap_const_logic_1;
assign img_1_rows_V_din = image_filter_Block_proc_U0_ap_return_2;
assign img_1_rows_V_read = image_filter_Mat2AXIvideo_U0_ap_ready;
assign img_1_rows_V_write = ap_chn_write_image_filter_Block_proc_U0_img_1_rows_V;
endmodule //image_filter
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:50:06 10/26/2012
// Design Name:
// Module Name: shift
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// 32λÒÆλÆ÷
// ÊäÈëÐźţºd,sa,right,arith
// Êä³öÐźţºsh
// dΪÐèÒªÒÆλµÄÊý¾Ý£¬sa¿ØÖÆÒÆλλÊý£¬¿ÉÑ¡ÔñÒƶ¯0~31λ
// right = 1ʱÓÒÒÆ£¬·ñÔò×óÒÆ£¬arith = 1·ûºÅÀ©Õ¹£¬·ñÔòÁãÀ©Õ¹
// shΪÒÆλ½á¹û
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module shift(d,sa,right,arith,sh
);
input [31:0] d;
input [4:0] sa;
input right,arith;
output [31:0] sh;
wire [31:0] t0,t1,t2,t3,t4,s1,s2,s3,s4;
wire a=d[31]&arith;
wire [15:0] e={16{a}};
parameter z=16'b0;
wire [31:0] sdl4,sdr4,sdl3,sdr3,sdl2,sdr2,sdl1,sdr1,sdl0,sdr0;
assign sdl4={d[15:0],z};
assign sdr4={e,d[31:16]};
mux2x32 m_right4(sdl4,sdr4,right,t4);
mux2x32 m_shift4(d,t4,sa[4],s4);
assign sdl3={s4[23:0],z[7:0]};
assign sdr3={e[7:0],s4[31:8]};
mux2x32 m_right3(sdl3,sdr3,right,t3);
mux2x32 m_shift3(s4,t3,sa[3],s3);
assign sdl2={s3[27:0],z[3:0]};
assign sdr2={e[3:0],s3[31:4]};
mux2x32 m_right2(sdl2,sdr2,right,t2);
mux2x32 m_shift2(s3,t2,sa[2],s2);
assign sdl1={s2[29:0],z[1:0]};
assign sdr1={e[1:0],s2[31:2]};
mux2x32 m_right1(sdl1,sdr1,right,t1);
mux2x32 m_shift1(s2,t1,sa[1],s1);
assign sdl0={s1[30:0],z[0]};
assign sdr0={e[0],s1[31:1]};
mux2x32 m_right0(sdl0,sdr0,right,t0);
mux2x32 m_shift0(s1,t0,sa[0],sh);
endmodule
|
module rd_port_mux_8to1 (
port0_rd_en,
port0_rd_addr,
port1_rd_en,
port1_rd_addr,
port2_rd_en,
port2_rd_addr,
port3_rd_en,
port3_rd_addr,
port4_rd_en,
port4_rd_addr,
port5_rd_en,
port5_rd_addr,
port6_rd_en,
port6_rd_addr,
port7_rd_en,
port7_rd_addr,
rd_data,
muxed_port_rd_addr,
muxed_port_rd_en,
muxed_port_rd_data
);
output [2047:0] rd_data;
output [9:0] muxed_port_rd_addr;
output muxed_port_rd_en;
input port0_rd_en;
input port1_rd_en;
input port2_rd_en;
input port3_rd_en;
input port4_rd_en;
input port5_rd_en;
input port6_rd_en;
input port7_rd_en;
input [9:0] port0_rd_addr;
input [9:0] port1_rd_addr;
input [9:0] port2_rd_addr;
input [9:0] port3_rd_addr;
input [9:0] port4_rd_addr;
input [9:0] port5_rd_addr;
input [9:0] port6_rd_addr;
input [9:0] port7_rd_addr;
input [2047:0] muxed_port_rd_data;
reg [2047:0] port0_rd_data;
reg [2047:0] port1_rd_data;
reg [2047:0] port2_rd_data;
reg [2047:0] port3_rd_data;
reg [2047:0] port4_rd_data;
reg [2047:0] port5_rd_data;
reg [2047:0] port6_rd_data;
reg [2047:0] port7_rd_data;
reg [9:0] muxed_port_rd_addr;
reg muxed_port_rd_en;
always @ (
port0_rd_en or
port1_rd_en or
port2_rd_en or
port3_rd_en or
port4_rd_en or
port5_rd_en or
port6_rd_en or
port7_rd_en or
port0_rd_addr or
port1_rd_addr or
port2_rd_addr or
port3_rd_addr or
port4_rd_addr or
port5_rd_addr or
port6_rd_addr or
port7_rd_addr
) begin
casex({port7_rd_en,port6_rd_en,port5_rd_en,port4_rd_en,port3_rd_en,port2_rd_en,port1_rd_en,port0_rd_en})
8'b0000_0001:
begin
muxed_port_rd_addr <= port0_rd_addr;
muxed_port_rd_en <= 1'b1;
end
8'b0000_0010:
begin
muxed_port_rd_addr <= port1_rd_addr;
muxed_port_rd_en <= 1'b1;
end
8'b0000_0100:
begin
muxed_port_rd_addr <= port2_rd_addr;
muxed_port_rd_en <= 1'b1;
end
8'b0000_1000:
begin
muxed_port_rd_addr <= port3_rd_addr;
muxed_port_rd_en <= 1'b1;
end
8'b0001_0000:
begin
muxed_port_rd_addr <= port4_rd_addr;
muxed_port_rd_en <= 1'b1;
end
8'b0010_0000:
begin
muxed_port_rd_addr <= port5_rd_addr;
muxed_port_rd_en <= 1'b1;
end
8'b0100_0000:
begin
muxed_port_rd_addr <= port6_rd_addr;
muxed_port_rd_en <= 1'b1;
end
8'b1000_0000:
begin
muxed_port_rd_addr <= port7_rd_addr;
muxed_port_rd_en <= 1'b1;
end
8'b0000_0000:
begin
muxed_port_rd_addr <= {10{1'bx}};
muxed_port_rd_en <= 1'b0;
end
default:
begin
muxed_port_rd_addr <= {10{1'bx}};
muxed_port_rd_en <= 1'bx;
end
endcase
end
assign rd_data = muxed_port_rd_data;
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// pfpu32_i2f ////
//// 32-bit integer to floating point converter ////
//// ////
//// Author: Andrey Bacherov ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2014 Andrey Bacherov ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
`include "mor1kx-defines.v"
module pfpu32_i2f
(
input clk,
input rst,
input flush_i, // flush pipe
input adv_i, // advance pipe
input start_i, // start conversion
input [31:0] opa_i,
output reg i2f_rdy_o, // i2f is ready
output reg i2f_sign_o, // i2f signum
output reg [3:0] i2f_shr_o,
output reg [7:0] i2f_exp8shr_o,
output reg [4:0] i2f_shl_o,
output reg [7:0] i2f_exp8shl_o,
output reg [7:0] i2f_exp8sh0_o,
output reg [31:0] i2f_fract32_o
);
/*
Any stage's output is registered.
Definitions:
s??o_name - "S"tage number "??", "O"utput
s??t_name - "S"tage number "??", "T"emporary (internally)
*/
// signum of input
wire s1t_signa = opa_i[31];
// magnitude (tow's complement for negative input)
wire [31:0] s1t_fract32 =
(opa_i ^ {32{s1t_signa}}) + {31'd0,s1t_signa};
// normalization shifts
reg [3:0] s1t_shrx;
reg [4:0] s1t_shlx;
// shift goal:
// 23 22 0
// | | |
// h fffffffffffffffffffffff
// right shift
always @(s1t_fract32[31:24]) begin
casez(s1t_fract32[31:24]) // synopsys full_case parallel_case
8'b1???????: s1t_shrx = 4'd8;
8'b01??????: s1t_shrx = 4'd7;
8'b001?????: s1t_shrx = 4'd6;
8'b0001????: s1t_shrx = 4'd5;
8'b00001???: s1t_shrx = 4'd4;
8'b000001??: s1t_shrx = 4'd3;
8'b0000001?: s1t_shrx = 4'd2;
8'b00000001: s1t_shrx = 4'd1;
8'b00000000: s1t_shrx = 4'd0;
endcase
end
// left shift
always @(s1t_fract32[23:0]) begin
casez(s1t_fract32[23:0]) // synopsys full_case parallel_case
24'b1???????????????????????: s1t_shlx = 5'd0; // hidden '1' is in its plase
24'b01??????????????????????: s1t_shlx = 5'd1;
24'b001?????????????????????: s1t_shlx = 5'd2;
24'b0001????????????????????: s1t_shlx = 5'd3;
24'b00001???????????????????: s1t_shlx = 5'd4;
24'b000001??????????????????: s1t_shlx = 5'd5;
24'b0000001?????????????????: s1t_shlx = 5'd6;
24'b00000001????????????????: s1t_shlx = 5'd7;
24'b000000001???????????????: s1t_shlx = 5'd8;
24'b0000000001??????????????: s1t_shlx = 5'd9;
24'b00000000001?????????????: s1t_shlx = 5'd10;
24'b000000000001????????????: s1t_shlx = 5'd11;
24'b0000000000001???????????: s1t_shlx = 5'd12;
24'b00000000000001??????????: s1t_shlx = 5'd13;
24'b000000000000001?????????: s1t_shlx = 5'd14;
24'b0000000000000001????????: s1t_shlx = 5'd15;
24'b00000000000000001???????: s1t_shlx = 5'd16;
24'b000000000000000001??????: s1t_shlx = 5'd17;
24'b0000000000000000001?????: s1t_shlx = 5'd18;
24'b00000000000000000001????: s1t_shlx = 5'd19;
24'b000000000000000000001???: s1t_shlx = 5'd20;
24'b0000000000000000000001??: s1t_shlx = 5'd21;
24'b00000000000000000000001?: s1t_shlx = 5'd22;
24'b000000000000000000000001: s1t_shlx = 5'd23;
24'b000000000000000000000000: s1t_shlx = 5'd0;
endcase
end
// registering output
always @(posedge clk) begin
if(adv_i) begin
// computation related
i2f_sign_o <= s1t_signa;
i2f_shr_o <= s1t_shrx;
i2f_exp8shr_o <= 8'd150 + {4'd0,s1t_shrx}; // 150=127+23
i2f_shl_o <= s1t_shlx;
i2f_exp8shl_o <= 8'd150 - {3'd0,s1t_shlx};
i2f_exp8sh0_o <= {8{s1t_fract32[23]}} & 8'd150; // "1" is in [23] / zero
i2f_fract32_o <= s1t_fract32;
end // advance
end // posedge clock
// ready is special case
always @(posedge clk `OR_ASYNC_RST) begin
if (rst)
i2f_rdy_o <= 1'b0;
else if(flush_i)
i2f_rdy_o <= 1'b0;
else if(adv_i)
i2f_rdy_o <= start_i;
end // posedge clock
endmodule // pfpu32_i2f
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_9_b2s_rd_cmd_fsm.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s_rd_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire s_arready ,
input wire s_arvalid ,
input wire [7:0] s_arlen ,
output wire m_arvalid ,
input wire m_arready ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
input wire data_ready ,
// status signal for w_channel when command is written.
output wire a_push ,
output wire r_push
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// States
localparam SM_IDLE = 2'b00;
localparam SM_CMD_EN = 2'b01;
localparam SM_CMD_ACCEPTED = 2'b10;
localparam SM_DONE = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [1:0] state;
// synthesis attribute MAX_FANOUT of state is 20;
reg [1:0] state_r1;
reg [1:0] next_state;
reg [7:0] s_arlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// register for timing
always @(posedge clk) begin
if (reset) begin
state <= SM_IDLE;
state_r1 <= SM_IDLE;
s_arlen_r <= 0;
end else begin
state <= next_state;
state_r1 <= state;
s_arlen_r <= s_arlen;
end
end
// Next state transitions.
always @( * ) begin
next_state = state;
case (state)
SM_IDLE:
if (s_arvalid & data_ready) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_CMD_EN:
///////////////////////////////////////////////////////////////////
// Drive m_arvalid downstream in this state
///////////////////////////////////////////////////////////////////
//If there is no fifo space
if (~data_ready & m_arready & next_pending) begin
///////////////////////////////////////////////////////////////////
//There is more to do, wait until data space is available drop valid
next_state = SM_CMD_ACCEPTED;
end else if (m_arready & ~next_pending)begin
next_state = SM_DONE;
end else if (m_arready & next_pending) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_CMD_ACCEPTED:
if (data_ready) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_DONE:
next_state = SM_IDLE;
default:
next_state = SM_IDLE;
endcase
end
// Assign outputs based on current state.
assign m_arvalid = (state == SM_CMD_EN);
assign next = m_arready && (state == SM_CMD_EN);
assign r_push = next;
assign a_push = (state == SM_IDLE);
assign s_arready = ((state == SM_CMD_EN) || (state == SM_DONE)) && (next_state == SM_IDLE);
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized 16/32 word deep FIFO.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_command_fifo #
(
parameter C_FAMILY = "virtex6",
parameter integer C_ENABLE_S_VALID_CARRY = 0,
parameter integer C_ENABLE_REGISTERED_OUTPUT = 0,
parameter integer C_FIFO_DEPTH_LOG = 5, // FIFO depth = 2**C_FIFO_DEPTH_LOG
// Range = [4:5].
parameter integer C_FIFO_WIDTH = 64 // Width of payload [1:512]
)
(
// Global inputs
input wire ACLK, // Clock
input wire ARESET, // Reset
// Information
output wire EMPTY, // FIFO empty (all stages)
// Slave Port
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Payload (may be any set of channel signals)
input wire S_VALID, // FIFO push
output wire S_READY, // FIFO not full
// Master Port
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Payload
output wire M_VALID, // FIFO not empty
input wire M_READY // FIFO pop
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for data vector.
genvar addr_cnt;
genvar bit_cnt;
integer index;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIFO_DEPTH_LOG-1:0] addr;
wire buffer_Full;
wire buffer_Empty;
wire next_Data_Exists;
reg data_Exists_I;
wire valid_Write;
wire new_write;
wire [C_FIFO_DEPTH_LOG-1:0] hsum_A;
wire [C_FIFO_DEPTH_LOG-1:0] sum_A;
wire [C_FIFO_DEPTH_LOG-1:0] addr_cy;
wire buffer_full_early;
wire [C_FIFO_WIDTH-1:0] M_MESG_I; // Payload
wire M_VALID_I; // FIFO not empty
wire M_READY_I; // FIFO pop
/////////////////////////////////////////////////////////////////////////////
// Create Flags
/////////////////////////////////////////////////////////////////////////////
assign buffer_full_early = ( (addr == {{C_FIFO_DEPTH_LOG-1{1'b1}}, 1'b0}) & valid_Write & ~M_READY_I ) |
( buffer_Full & ~M_READY_I );
assign S_READY = ~buffer_Full;
assign buffer_Empty = (addr == {C_FIFO_DEPTH_LOG{1'b0}});
assign next_Data_Exists = (data_Exists_I & ~buffer_Empty) |
(buffer_Empty & S_VALID) |
(data_Exists_I & ~(M_READY_I & data_Exists_I));
always @ (posedge ACLK) begin
if (ARESET) begin
data_Exists_I <= 1'b0;
end else begin
data_Exists_I <= next_Data_Exists;
end
end
assign M_VALID_I = data_Exists_I;
// Select RTL or FPGA optimized instatiations for critical parts.
generate
if ( C_FAMILY == "rtl" || C_ENABLE_S_VALID_CARRY == 0 ) begin : USE_RTL_VALID_WRITE
reg buffer_Full_q;
assign valid_Write = S_VALID & ~buffer_Full;
assign new_write = (S_VALID | ~buffer_Empty);
assign addr_cy[0] = valid_Write;
always @ (posedge ACLK) begin
if (ARESET) begin
buffer_Full_q <= 1'b0;
end else if ( data_Exists_I ) begin
buffer_Full_q <= buffer_full_early;
end
end
assign buffer_Full = buffer_Full_q;
end else begin : USE_FPGA_VALID_WRITE
wire s_valid_dummy1;
wire s_valid_dummy2;
wire sel_s_valid;
wire sel_new_write;
wire valid_Write_dummy1;
wire valid_Write_dummy2;
assign sel_s_valid = ~buffer_Full;
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst1
(
.CIN(S_VALID),
.S(1'b1),
.COUT(s_valid_dummy1)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) s_valid_dummy_inst2
(
.CIN(s_valid_dummy1),
.S(1'b1),
.COUT(s_valid_dummy2)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_inst
(
.CIN(s_valid_dummy2),
.S(sel_s_valid),
.COUT(valid_Write)
);
assign sel_new_write = ~buffer_Empty;
generic_baseblocks_v2_1_0_carry_latch_or #
(
.C_FAMILY(C_FAMILY)
) new_write_inst
(
.CIN(valid_Write),
.I(sel_new_write),
.O(new_write)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst1
(
.CIN(valid_Write),
.S(1'b1),
.COUT(valid_Write_dummy1)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst2
(
.CIN(valid_Write_dummy1),
.S(1'b1),
.COUT(valid_Write_dummy2)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) valid_write_dummy_inst3
(
.CIN(valid_Write_dummy2),
.S(1'b1),
.COUT(addr_cy[0])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_I1 (
.Q(buffer_Full), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(buffer_full_early) // Data input
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Create address pointer
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_ADDR
reg [C_FIFO_DEPTH_LOG-1:0] addr_q;
always @ (posedge ACLK) begin
if (ARESET) begin
addr_q <= {C_FIFO_DEPTH_LOG{1'b0}};
end else if ( data_Exists_I ) begin
if ( valid_Write & ~(M_READY_I & data_Exists_I) ) begin
addr_q <= addr_q + 1'b1;
end else if ( ~valid_Write & (M_READY_I & data_Exists_I) & ~buffer_Empty ) begin
addr_q <= addr_q - 1'b1;
end
else begin
addr_q <= addr_q;
end
end
else begin
addr_q <= addr_q;
end
end
assign addr = addr_q;
end else begin : USE_FPGA_ADDR
for (addr_cnt = 0; addr_cnt < C_FIFO_DEPTH_LOG ; addr_cnt = addr_cnt + 1) begin : ADDR_GEN
assign hsum_A[addr_cnt] = ((M_READY_I & data_Exists_I) ^ addr[addr_cnt]) & new_write;
// Don't need the last muxcy, addr_cy(last) is not used anywhere
if ( addr_cnt < C_FIFO_DEPTH_LOG - 1 ) begin : USE_MUXCY
MUXCY MUXCY_inst (
.DI(addr[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.S(hsum_A[addr_cnt]),
.O(addr_cy[addr_cnt+1])
);
end
else begin : NO_MUXCY
end
XORCY XORCY_inst (
.LI(hsum_A[addr_cnt]),
.CI(addr_cy[addr_cnt]),
.O(sum_A[addr_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(addr[addr_cnt]), // Data output
.C(ACLK), // Clock input
.CE(data_Exists_I), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(sum_A[addr_cnt]) // Data input
);
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Data storage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_FIFO
reg [C_FIFO_WIDTH-1:0] data_srl[2 ** C_FIFO_DEPTH_LOG-1:0];
always @ (posedge ACLK) begin
if ( valid_Write ) begin
for (index = 0; index < 2 ** C_FIFO_DEPTH_LOG-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= S_MESG;
end
end
assign M_MESG_I = data_srl[addr];
end else begin : USE_FPGA_FIFO
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
if ( C_FIFO_DEPTH_LOG == 5 ) begin : USE_32
SRLC32E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC32E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q31(), // SRL cascade output pin
.A(addr), // 5-bit shift depth select input
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end else begin : USE_16
SRLC16E # (
.INIT(32'h00000000) // Initial Value of Shift Register
) SRLC16E_inst (
.Q(M_MESG_I[bit_cnt]), // SRL data output
.Q15(), // SRL cascade output pin
.A0(addr[0]), // 4-bit shift depth select input 0
.A1(addr[1]), // 4-bit shift depth select input 1
.A2(addr[2]), // 4-bit shift depth select input 2
.A3(addr[3]), // 4-bit shift depth select input 3
.CE(valid_Write), // Clock enable input
.CLK(ACLK), // Clock input
.D(S_MESG[bit_cnt]) // SRL data input
);
end // C_FIFO_DEPTH_LOG
end // end for bit_cnt
end // C_FAMILY
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Pipeline stage
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_ENABLE_REGISTERED_OUTPUT != 0 ) begin : USE_FF_OUT
wire [C_FIFO_WIDTH-1:0] M_MESG_FF; // Payload
wire M_VALID_FF; // FIFO not empty
// Select RTL or FPGA optimized instatiations for critical parts.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_Q; // Payload
reg M_VALID_Q; // FIFO not empty
always @ (posedge ACLK) begin
if (ARESET) begin
M_MESG_Q <= {C_FIFO_WIDTH{1'b0}};
M_VALID_Q <= 1'b0;
end else begin
if ( M_READY_I ) begin
M_MESG_Q <= M_MESG_I;
M_VALID_Q <= M_VALID_I;
end
end
end
assign M_MESG_FF = M_MESG_Q;
assign M_VALID_FF = M_VALID_Q;
end else begin : USE_FPGA_OUTPUT_PIPELINE
reg [C_FIFO_WIDTH-1:0] M_MESG_CMB; // Payload
reg M_VALID_CMB; // FIFO not empty
always @ *
begin
if ( M_READY_I ) begin
M_MESG_CMB <= M_MESG_I;
M_VALID_CMB <= M_VALID_I;
end else begin
M_MESG_CMB <= M_MESG_FF;
M_VALID_CMB <= M_VALID_FF;
end
end
for (bit_cnt = 0; bit_cnt < C_FIFO_WIDTH ; bit_cnt = bit_cnt + 1) begin : DATA_GEN
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_MESG_FF[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_MESG_CMB[bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(M_VALID_FF), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_VALID_CMB) // Data input
);
end
assign EMPTY = ~M_VALID_I & ~M_VALID_FF;
assign M_MESG = M_MESG_FF;
assign M_VALID = M_VALID_FF;
assign M_READY_I = ( M_READY & M_VALID_FF ) | ~M_VALID_FF;
end else begin : NO_FF_OUT
assign EMPTY = ~M_VALID_I;
assign M_MESG = M_MESG_I;
assign M_VALID = M_VALID_I;
assign M_READY_I = M_READY;
end
endgenerate
endmodule
|
/*
Line Size : 64byte
Way : 4Way Set Assicatiev
Tag : /2bit LRU Bit(VALID)/20bit Address
Purging : Write Through Algorithm
*/
//`include "processor.h"
`default_nettype none
module l1_data_cache_64entry_4way_line64b_bus_8b(
/********************************
System
********************************/
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Remove
input wire iREMOVE,
/********************************
Search
********************************/
//Search Request
input wire iRD_REQ,
output wire oRD_BUSY,
input wire [31:0] iRD_ADDR, //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
//Search Output Result
output wire oRD_VALID,
output wire oRD_HIT,
input wire iRD_BUSY,
output wire [31:0] oRD_DATA,
output wire [11:0] oRD_MMU_FLAGS,
/********************************
Upload
********************************/
input wire iUP_REQ,
output wire oUP_BUSY,
input wire [1:0] iUP_ORDER,
input wire [3:0] iUP_MASK,
input wire [31:0] iUP_ADDR,
input wire [31:0] iUP_DATA,
/********************************
Write Request
********************************/
input wire iWR_REQ,
output wire oWR_BUSY,
input wire [31:0] iWR_ADDR, //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
input wire [511:0] iWR_DATA,
input wire [255:0] iWR_MMU_FLAGS
);
/**********************************************
Wire and Register
**********************************************/
//Lock Condition
wire this_read_lock;
wire this_write_lock;
//Output Buffer
reg b_rd_hit;
reg [1:0] b_rd_way;
reg [31:0] b_rd_addr;
//Cache Control
wire upload_need;
wire [1:0] upload_way;
wire [3:0] upload_pointer;
wire [3:0] read_pointer;
wire read_hit;
wire [1:0] read_way;
wire [3:0] write_pointer;
wire [1:0] write_way;
//Memory Data Block
wire [511:0] memory_way0_out_data;
wire [511:0] memory_way1_out_data;
wire [511:0] memory_way2_out_data;
wire [511:0] memory_way3_out_data;
wire memory_write_way0_condition;
wire memory_write_way1_condition;
wire memory_write_way2_condition;
wire memory_write_way3_condition;
wire [63:0] memory_write_byte_enable;
wire [511:0] memory_write_data;
//MMU Flag Block
wire [255:0] memory_mmuflag_way0_out_data;
wire [255:0] memory_mmuflag_way1_out_data;
wire [255:0] memory_mmuflag_way2_out_data;
wire [255:0] memory_mmuflag_way3_out_data;
wire [255:0] memory_mmuflag_write_data;
wire [31:0] memory_mmuflag_write_byte_enable;
//Generate
integer i;
//Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
reg [23:0] tag0[0:15]; //LRU_Status:2bit | AddressTag:22bit
reg [23:0] tag1[0:15]; //LRU_Status:2bit | AddressTag:22bit
reg [23:0] tag2[0:15]; //LRU_Status:2bit | AddressTag:22bit
reg [23:0] tag3[0:15]; //LRU_Status:2bit | AddressTag:22bit
reg b_load_req_valid;
/**********************************************
Lock
**********************************************/
assign this_read_lock = iRD_BUSY;
assign this_write_lock = iUP_REQ;
/********************************************
LRU Control - Timer
********************************************/
wire lru_valid;
reg [15:0] b_lru_timer;
assign lru_valid = (b_lru_timer == 16'hFFFF)? 1'b1 : 1'b0;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_lru_timer <= 16'h0;
end
else if(iRESET_SYNC)begin
b_lru_timer <= 16'h0;
end
else if(iREMOVE)begin
b_lru_timer <= 16'h0;
end
else begin
if(!this_read_lock)begin
b_lru_timer <= b_lru_timer + 16'h1;
end
end
end
/********************************************
Control
********************************************/
assign {upload_need, upload_way} = func_upload_check(iUP_ADDR[31:10], tag0[upload_pointer], tag1[upload_pointer], tag2[upload_pointer], tag3[upload_pointer]);
assign upload_pointer = iUP_ADDR[9:6];
assign read_pointer = iRD_ADDR[9:6];
assign {read_hit, read_way} = func_hit_check(iRD_ADDR[31:10], tag0[read_pointer], tag1[read_pointer], tag2[read_pointer], tag3[read_pointer]);
assign write_pointer = iWR_ADDR[9:6];
assign write_way = func_write_way_search(
iWR_ADDR[31:10],
func_get_address_tag(tag0[write_pointer]),
func_get_address_tag(tag1[write_pointer]),
func_get_address_tag(tag2[write_pointer]),
func_get_address_tag(tag3[write_pointer]),
func_get_status_tag(tag0[write_pointer]),
func_get_status_tag(tag1[write_pointer]),
func_get_status_tag(tag2[write_pointer]),
func_get_status_tag(tag3[write_pointer])
);
/********************************************
Data Memory Block
********************************************/
assign memory_write_way0_condition = (!this_write_lock && iWR_REQ && write_way == 2'h0) || (iUP_REQ && upload_need && upload_way == 2'h0);
assign memory_write_way1_condition = (!this_write_lock && iWR_REQ && write_way == 2'h1) || (iUP_REQ && upload_need && upload_way == 2'h1);
assign memory_write_way2_condition = (!this_write_lock && iWR_REQ && write_way == 2'h2) || (iUP_REQ && upload_need && upload_way == 2'h2);
assign memory_write_way3_condition = (!this_write_lock && iWR_REQ && write_way == 2'h3) || (iUP_REQ && upload_need && upload_way == 2'h3);
assign memory_write_byte_enable = (iUP_REQ)? func_up_mask_gen(iUP_ADDR[5:2], iUP_MASK) : {64{1'b1}};
function [63:0] func_up_mask_gen;
input [3:0] func_wordsel;
input [3:0] func_mask;
begin
func_up_mask_gen = {60'h0, func_mask} << (func_wordsel*4);
end
endfunction
assign memory_write_data = (iUP_REQ)? {16{iUP_DATA}} : iWR_DATA;
wire memory_mmuflag_write_way0_condition;
wire memory_mmuflag_write_way1_condition;
wire memory_mmuflag_write_way2_condition;
wire memory_mmuflag_write_way3_condition;
assign memory_mmuflag_write_way0_condition = (!this_write_lock && iWR_REQ && write_way == 2'h0) || (iUP_REQ && upload_need && upload_way == 2'h0);
assign memory_mmuflag_write_way1_condition = (!this_write_lock && iWR_REQ && write_way == 2'h1) || (iUP_REQ && upload_need && upload_way == 2'h1);
assign memory_mmuflag_write_way2_condition = (!this_write_lock && iWR_REQ && write_way == 2'h2) || (iUP_REQ && upload_need && upload_way == 2'h2);
assign memory_mmuflag_write_way3_condition = (!this_write_lock && iWR_REQ && write_way == 2'h3) || (iUP_REQ && upload_need && upload_way == 2'h3);
assign memory_mmuflag_write_byte_enable = (iUP_REQ)? {32{1'b0}} : {32{1'b1}};
assign memory_mmuflag_write_data = iWR_MMU_FLAGS;
/*---------------------------------------
Altera Quartus II MegaWizard
Name : Data RAM
Type : RAM
Port : Dual Port(1Read+1Write)
ReadPort : None Latch
Entry : 16
Data Bit : 512bit
Read Latch : none
Byte Enable : YES(64bit)
Read==Write : Dont care
---------------------------------------*/
/*
`ifdef MIST1032ISA_SIMULATION
damy_memory_16entry_512bit MEMORY_DAMY_BLOCK0(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_write_byte_enable),
//Write
.iWR_ENA(memory_write_way0_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_way0_out_data)
);
damy_memory_16entry_512bit MEMORY_DAMY_BLOCK1(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_write_byte_enable),
//Write
.iWR_ENA(memory_write_way1_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_way1_out_data)
);
damy_memory_16entry_512bit MEMORY_DAMY_BLOCK2(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_write_byte_enable),
//Write
.iWR_ENA(memory_write_way2_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_way2_out_data)
);
damy_memory_16entry_512bit MEMORY_DAMY_BLOCK3(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_write_byte_enable),
//Write
.iWR_ENA(memory_write_way3_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_way3_out_data)
);
*/
//`else
ram_512bit_16word MEMORY_BLOCK0(
.clock(iCLOCK),
.data(memory_write_data), //512bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.byteena_a(memory_write_byte_enable), //64bit
.wren(memory_write_way0_condition),
.q(memory_way0_out_data) //512bit
);
ram_512bit_16word MEMORY_BLOCK1(
.clock(iCLOCK),
.data(memory_write_data), //512bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.byteena_a(memory_write_byte_enable), //64bit
.wren(memory_write_way1_condition),
.q(memory_way1_out_data) //512bit
);
ram_512bit_16word MEMORY_BLOCK2(
.clock(iCLOCK),
.data(memory_write_data), //512bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.byteena_a(memory_write_byte_enable), //64bit
.wren(memory_write_way2_condition),
.q(memory_way2_out_data) //512bit
);
ram_512bit_16word MEMORY_BLOCK3(
.clock(iCLOCK),
.data(memory_write_data), //512bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.byteena_a(memory_write_byte_enable), //64bit
.wren(memory_write_way3_condition),
.q(memory_way3_out_data) //512bit
);
//`endif
/*---------------------------------------
Altera Quartus II MegaWizard
Name : MMU Flag RAM
Type : RAM
Port : Dual Port(1Read+1Write)
ReadPort : None Latch
Memory Word : 128W
Data Bit : 12bit
Read Latch : none
Byte Enable : YES(8bit)
Read==Write : Dont care
---------------------------------------*/
/*`ifdef MIST1032ISA_SIMULATION
damy_memory_16entry_256bit MEMORY_MMUFLAG_DAMY_BLOCK0(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_mmuflag_write_byte_enable),
//Write
.iWR_ENA(memory_mmuflag_write_way0_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_mmuflag_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_mmuflag_way0_out_data)
);
damy_memory_16entry_256bit MEMORY_MMUFLAG_DAMY_BLOCK1(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_mmuflag_write_byte_enable),
//Write
.iWR_ENA(memory_mmuflag_write_way1_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_mmuflag_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_mmuflag_way1_out_data)
);
damy_memory_16entry_256bit MEMORY_MMUFLAG_DAMY_BLOCK2(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_mmuflag_write_byte_enable),
//Write
.iWR_ENA(memory_mmuflag_write_way2_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_mmuflag_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_mmuflag_way2_out_data)
);
damy_memory_16entry_256bit MEMORY_MMUFLAG_DAMY_BLOCK3(
.iCLOCK(iCLOCK),
.iBYTE_ENA(memory_mmuflag_write_byte_enable),
//Write
.iWR_ENA(memory_mmuflag_write_way3_condition),
.iWR_ADDR(write_pointer),
.iWR_DATA(memory_mmuflag_write_data),
//Read
.iRD_ADDR(read_pointer),
.oRD_DATA(memory_mmuflag_way3_out_data)
);
`else*/
ram_256bit_16word MEMORY_MMUFLAG_BLOCK0(
.clock(iCLOCK),
.byteena_a(memory_mmuflag_write_byte_enable),
.data(memory_mmuflag_write_data), //256bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.wren(memory_mmuflag_write_way0_condition),
.q(memory_mmuflag_way0_out_data) //256bit
);
ram_256bit_16word MEMORY_MMUFLAG_BLOCK1(
.clock(iCLOCK),
.byteena_a(memory_mmuflag_write_byte_enable),
.data(memory_mmuflag_write_data), //256bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.wren(memory_mmuflag_write_way1_condition),
.q(memory_mmuflag_way1_out_data) //256bit
);
ram_256bit_16word MEMORY_MMUFLAG_BLOCK2(
.clock(iCLOCK),
.byteena_a(memory_mmuflag_write_byte_enable),
.data(memory_mmuflag_write_data), //256bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.wren(memory_mmuflag_write_way2_condition),
.q(memory_mmuflag_way2_out_data) //256bit
);
ram_256bit_16word MEMORY_MMUFLAG_BLOCK3(
.clock(iCLOCK),
.byteena_a(memory_mmuflag_write_byte_enable),
.data(memory_mmuflag_write_data), //256bit
.rdaddress(read_pointer), //4bit
.wraddress(write_pointer), //4bit
.wren(memory_mmuflag_write_way3_condition),
.q(memory_mmuflag_way3_out_data) //256bit
);
//`endif
/********************************************
Function
********************************************/
//Upload Check
function [2:0] func_upload_check; //[2]:Upload Need Flag | [1:0] Upload Way
input [21:0] func_request_addr;
input [23:0] func_way0;
input [23:0] func_way1;
input [23:0] func_way2;
input [23:0] func_way3;
begin
if(func_request_addr == func_way0[21:0] && func_way0[23:22] != 2'h0)begin
func_upload_check = {1'b1, 2'h0};
end
else if(func_request_addr == func_way1[21:0] && func_way0[23:22] != 2'h0)begin
func_upload_check = {1'b1, 2'h1};
end
else if(func_request_addr == func_way2[21:0] && func_way0[23:22] != 2'h0)begin
func_upload_check = {1'b1, 2'h2};
end
else if(func_request_addr == func_way3[21:0] && func_way0[23:22] != 2'h0)begin
func_upload_check = {1'b1, 2'h3};
end
else begin
func_upload_check = 3'h0;
end
end
endfunction
//Upload Byte Enable Generate
function [63:0] func_upload_enable_byte_gen;
input [5:0] func_addr;
input [1:0] func_order;
begin
case(func_order)
2'h0 : func_upload_enable_byte_gen = 64'h0000000000000001 << func_addr[5:0];
2'h1 : func_upload_enable_byte_gen = 64'h0000000000000003 << (func_addr[5:1]*2);
2'h2 : func_upload_enable_byte_gen = 64'h000000000000000F << (func_addr[5:2]*4);
default : func_upload_enable_byte_gen = 64'h0000000000000000;
endcase
end
endfunction
//Low Pryority Line Search
function [1:0] func_write_way_search;
input [21:0] write_addr;
input [21:0] way0_adder_tag;
input [21:0] way1_adder_tag;
input [21:0] way2_adder_tag;
input [21:0] way3_adder_tag;
input [1:0] way0_status;
input [1:0] way1_status;
input [1:0] way2_status;
input [1:0] way3_status;
begin
//LINE Update
if(write_addr == way0_adder_tag)begin
func_write_way_search = 2'h0;
end
else if(write_addr == way1_adder_tag)begin
func_write_way_search = 2'h1;
end
else if(write_addr == way2_adder_tag)begin
func_write_way_search = 2'h2;
end
else if(write_addr == way3_adder_tag)begin
func_write_way_search = 2'h3;
end
//New Write
else if(way0_status == 2'h0)
func_write_way_search = 2'h0;
else if(way1_status == 2'h0)
func_write_way_search = 2'h1;
else if(way2_status == 2'h0)
func_write_way_search = 2'h2;
else if(way3_status == 2'h0)
func_write_way_search = 2'h3;
else if(way0_status == 2'h1)
func_write_way_search = 2'h0;
else if(way1_status == 2'h1)
func_write_way_search = 2'h1;
else if(way2_status == 2'h1)
func_write_way_search = 2'h2;
else if(way3_status == 2'h1)
func_write_way_search = 2'h3;
else if(way0_status == 2'h2)
func_write_way_search = 2'h0;
else if(way1_status == 2'h2)
func_write_way_search = 2'h1;
else if(way2_status == 2'h2)
func_write_way_search = 2'h2;
else if(way3_status == 2'h2)
func_write_way_search = 2'h3;
else
func_write_way_search = 2'h3;
end
endfunction
function [2:0] func_hit_check; //[2]:Hit | [1:0] Hit Way
input [21:0] func_request_addr;
input [23:0] func_way0;
input [23:0] func_way1;
input [23:0] func_way2;
input [23:0] func_way3;
begin
if(func_request_addr == func_way0[21:0] && func_way0[23:22] != 2'h0)begin
func_hit_check = {1'b1, 2'h0};
end
else if(func_request_addr == func_way1[21:0] && func_way1[23:22] != 2'h0)begin
func_hit_check = {1'b1, 2'h1};
end
else if(func_request_addr == func_way2[21:0] && func_way2[23:22] != 2'h0)begin
func_hit_check = {1'b1, 2'h2};
end
else if(func_request_addr == func_way3[21:0] && func_way3[23:22] != 2'h0)begin
func_hit_check = {1'b1, 2'h3};
end
else begin
//No Hit
func_hit_check = {1'b0, 2'h0};
end
end
endfunction
//Pryority & Valid
function [1:0] func_get_status_tag;
input [23:0] func_tag;
begin
func_get_status_tag = func_tag[23:22];
end
endfunction
//Get Tag Address
function [21:0] func_get_address_tag;
input [23:0] func_tag;
begin
func_get_address_tag = func_tag[21:0];
end
endfunction
function [31:0] func_data_selector;
input [3:0] func_select;
input [511:0] func_data;
begin
case(func_select)
4'h0 : func_data_selector = func_data[31:0];
4'h1 : func_data_selector = func_data[63:32];
4'h2 : func_data_selector = func_data[95:64];
4'h3 : func_data_selector = func_data[127:96];
4'h4 : func_data_selector = func_data[159:128];
4'h5 : func_data_selector = func_data[191:160];
4'h6 : func_data_selector = func_data[223:192];
4'h7 : func_data_selector = func_data[255:224];
4'h8 : func_data_selector = func_data[287:256];
4'h9 : func_data_selector = func_data[319:288];
4'ha : func_data_selector = func_data[351:320];
4'hb : func_data_selector = func_data[383:352];
4'hc : func_data_selector = func_data[415:384];
4'hd : func_data_selector = func_data[447:416];
4'he : func_data_selector = func_data[479:448];
4'hf : func_data_selector = func_data[511:480];
endcase
end
endfunction
function [11:0] func_mmu_flags_selector;
input [3:0] func_select;
input [255:0] func_data;
begin
case(func_select)
4'h0 : func_mmu_flags_selector = func_data[11:0];
4'h1 : func_mmu_flags_selector = func_data[27:16];
4'h2 : func_mmu_flags_selector = func_data[43:32];
4'h3 : func_mmu_flags_selector = func_data[69:48];
4'h4 : func_mmu_flags_selector = func_data[75:64];
4'h5 : func_mmu_flags_selector = func_data[91:80];
4'h6 : func_mmu_flags_selector = func_data[107:96];
4'h7 : func_mmu_flags_selector = func_data[123:112];
4'h8 : func_mmu_flags_selector = func_data[149:128];
4'h9 : func_mmu_flags_selector = func_data[155:144];
4'ha : func_mmu_flags_selector = func_data[171:160];
4'hb : func_mmu_flags_selector = func_data[187:176];
4'hc : func_mmu_flags_selector = func_data[203:192];
4'hd : func_mmu_flags_selector = func_data[219:208];
4'he : func_mmu_flags_selector = func_data[235:224];
4'hf : func_mmu_flags_selector = func_data[251:240];
endcase
end
endfunction
function [23:0] func_lru_control;
input [23:0] func_tag;
begin
if(func_tag[23:22] != 2'h0 && func_tag[23:22] != 2'h1)begin
func_lru_control = {(func_tag[23:22] - 2'h1), func_tag[21:0]};
end
else begin
func_lru_control = func_tag;
end
end
endfunction
/********************************************
Tag Pryority & Tag Control
********************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 16; i = i + 1)begin
/*
if(`PROCESSOR_DATA_RESET_EN)begin
tag0[i] <= tag0[i] & 24'h000000; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h000000; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h000000; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h000000; //Clear LRU_Status bit
end
else begin
tag0[i] <= tag0[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h3FFFFF; //Clear LRU_Status bit
end
*/
tag0[i] <= tag0[i] & 24'h000000; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h000000; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h000000; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h000000; //Clear LRU_Status bit
end
b_load_req_valid <= 1'b0;
end
else if(iRESET_SYNC)begin
for(i = 0; i < 16; i = i + 1)begin
/*
if(`PROCESSOR_DATA_RESET_EN)begin
tag0[i] <= tag0[i] & 24'h000000; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h000000; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h000000; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h000000; //Clear LRU_Status bit
end
else begin
tag0[i] <= tag0[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h3FFFFF; //Clear LRU_Status bit
end
*/
tag0[i] <= tag0[i] & 24'h000000; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h000000; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h000000; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h000000; //Clear LRU_Status bit
end
b_load_req_valid <= 1'b0;
end
else if(iREMOVE)begin
for(i = 0; i < 16; i = i + 1)begin
/*
if(`PROCESSOR_DATA_RESET_EN)begin
tag0[i] <= tag0[i] & 24'h000000; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h000000; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h000000; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h000000; //Clear LRU_Status bit
end
else begin
tag0[i] <= tag0[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h3FFFFF; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h3FFFFF; //Clear LRU_Status bit
end
*/
tag0[i] <= tag0[i] & 24'h000000; //Clear LRU_Status bit
tag1[i] <= tag1[i] & 24'h000000; //Clear LRU_Status bit
tag2[i] <= tag2[i] & 24'h000000; //Clear LRU_Status bit
tag3[i] <= tag3[i] & 24'h000000; //Clear LRU_Status bit
end
b_load_req_valid <= 1'b0;
end
else begin
//Request Valid
if(!this_read_lock)begin
b_load_req_valid <= iRD_REQ;
end
//Upload
if(iUP_REQ)begin
if(upload_need)begin
case(upload_way)
2'h0: tag0[write_pointer] <= {((func_get_status_tag(tag0[upload_pointer]) != 2'b11)? func_get_status_tag(tag0[upload_pointer]) + 2'h1 : func_get_status_tag(tag0[upload_pointer])), func_get_address_tag(tag0[upload_pointer])};
2'h1: tag1[write_pointer] <= {((func_get_status_tag(tag1[upload_pointer]) != 2'b11)? func_get_status_tag(tag1[upload_pointer]) + 2'h1 : func_get_status_tag(tag1[upload_pointer])), func_get_address_tag(tag1[upload_pointer])};
2'h2: tag2[write_pointer] <= {((func_get_status_tag(tag2[upload_pointer]) != 2'b11)? func_get_status_tag(tag2[upload_pointer]) + 2'h1 : func_get_status_tag(tag2[upload_pointer])), func_get_address_tag(tag2[upload_pointer])};
2'h3: tag3[write_pointer] <= {((func_get_status_tag(tag3[upload_pointer]) != 2'b11)? func_get_status_tag(tag3[upload_pointer]) + 2'h1 : func_get_status_tag(tag3[upload_pointer])), func_get_address_tag(tag3[upload_pointer])};
endcase
end
end
//Write
else if(iWR_REQ)begin
case(write_way)
2'h0: tag0[write_pointer] <= {2'b11, iWR_ADDR[31:10]};
2'h1: tag1[write_pointer] <= {2'b11, iWR_ADDR[31:10]};
2'h2: tag2[write_pointer] <= {2'b11, iWR_ADDR[31:10]};
2'h3: tag3[write_pointer] <= {2'b11, iWR_ADDR[31:10]};
endcase
end
else begin
//Read & LRU Controal
if(!this_read_lock)begin
if(iRD_REQ && read_hit && lru_valid)begin
for(i = 0; i < 16; i = i + 1)begin : READ_AND_RLU
//TAG0
if(read_pointer == i[3:0] && read_way == 2'h0)begin
tag0[read_pointer] <= {2'b11, func_get_address_tag(tag0[read_pointer])};
end
else begin
if(func_get_status_tag(tag0[i[3:0]]) != 2'h0 && func_get_status_tag(tag0[i[3:0]]) != 2'h1)begin
tag0[i[3:0]] <= {(func_get_status_tag(tag0[i[3:0]]) - 2'h1), func_get_address_tag(tag0[i[3:0]])};
end
end
//TAG1
if(read_pointer == i[3:0] && read_way == 2'h1)begin
tag1[read_pointer] <= {2'b11, func_get_address_tag(tag1[read_pointer])};
end
else begin
if(func_get_status_tag(tag1[i[3:0]]) != 2'h0 && func_get_status_tag(tag1[i[3:0]]) != 2'h1)begin
tag1[i[3:0]] <= {(func_get_status_tag(tag1[i[3:0]]) - 2'h1), func_get_address_tag(tag1[i[3:0]])};
end
end
//TAG2
if(read_pointer == i[3:0] && read_way == 2'h2)begin
tag2[read_pointer] <= {2'b11, func_get_address_tag(tag2[read_pointer])};
end
else begin
if(func_get_status_tag(tag2[i[3:0]]) != 2'h0 && func_get_status_tag(tag2[i[3:0]]) != 2'h1)begin
tag2[i[3:0]] <= {(func_get_status_tag(tag2[i[3:0]]) - 2'h1), func_get_address_tag(tag2[i[3:0]])};
end
end
//TAG3
if(read_pointer == i[3:0] && read_way == 2'h3)begin
tag3[read_pointer] <= {2'b11, func_get_address_tag(tag3[read_pointer])};
end
else begin
if(func_get_status_tag(tag3[i[3:0]]) != 2'h0 && func_get_status_tag(tag3[i[3:0]]) != 2'h1)begin
tag3[i[3:0]] <= {(func_get_status_tag(tag3[i[3:0]]) - 2'h1), func_get_address_tag(tag3[i[3:0]])};
end
end
end
end
//Read Only
else if(iRD_REQ && read_hit)begin
case(read_way)//synthesis parallel_case full_case
2'h0 :
begin
if(func_get_status_tag(tag0[read_pointer]) != 2'b11)begin
tag0[read_pointer] <= {2'b11/*(func_get_status_tag(tag0[read_pointer]) + 2'h1)*/, func_get_address_tag(tag0[read_pointer])};
end
end
2'h1 :
begin
if(func_get_status_tag(tag1[read_pointer]) != 2'b11)begin
tag1[read_pointer] <= {2'b11, func_get_address_tag(tag1[read_pointer])};
end
end
2'h2 :
begin
if(func_get_status_tag(tag2[read_pointer]) != 2'b11)begin
tag2[read_pointer] <= {2'b11, func_get_address_tag(tag2[read_pointer])};
end
end
2'h3 :
begin
if(func_get_status_tag(tag3[read_pointer]) != 2'b11)begin
tag3[read_pointer] <= {2'b11, func_get_address_tag(tag3[read_pointer])};
end
end
endcase
end
//LRU Controal
else if(lru_valid)begin
for(i = 0; i < 16; i = i + 1)begin
tag0[i] <= func_lru_control(tag0[i]);
tag1[i] <= func_lru_control(tag1[i]);
tag2[i] <= func_lru_control(tag2[i]);
tag3[i] <= func_lru_control(tag3[i]);
end
end
end //End !Lock
end
end
end //always
/********************************************
Output Buffer
********************************************/
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_rd_hit <= 1'h0;
b_rd_way <= 2'h0;
b_rd_addr <= 32'h0;
end
else if(iRESET_SYNC)begin
b_rd_hit <= 1'h0;
b_rd_way <= 2'h0;
b_rd_addr <= 32'h0;
end
else begin
if(!this_read_lock)begin
b_rd_hit <= read_hit;
b_rd_way <= read_way;
b_rd_addr <= iRD_ADDR;
end
end
end
/*****************************************************
Output Assign
*****************************************************/
assign oRD_BUSY = iRD_BUSY || (iRD_REQ && iWR_REQ && iRD_ADDR == iWR_ADDR);
assign oRD_VALID = b_load_req_valid && !this_read_lock;
assign oRD_HIT = b_load_req_valid && !this_read_lock && b_rd_hit;
assign oRD_DATA = (b_load_req_valid && !this_read_lock && b_rd_hit)? (
(b_rd_way == 2'h0)? func_data_selector(b_rd_addr[5:2], memory_way0_out_data) : (
(b_rd_way == 2'h1)? func_data_selector(b_rd_addr[5:2], memory_way1_out_data) : (
(b_rd_way == 2'h2)? func_data_selector(b_rd_addr[5:2], memory_way2_out_data) : func_data_selector(b_rd_addr[5:2], memory_way3_out_data)
)
)
) : 64'h0;
assign oRD_MMU_FLAGS = (b_load_req_valid && !this_read_lock && b_rd_hit)? (
(b_rd_way == 2'h0)? func_mmu_flags_selector(b_rd_addr[5:2], memory_mmuflag_way0_out_data) : (
(b_rd_way == 2'h1)? func_mmu_flags_selector(b_rd_addr[5:2], memory_mmuflag_way1_out_data) : (
(b_rd_way == 2'h2)? func_mmu_flags_selector(b_rd_addr[5:2], memory_mmuflag_way2_out_data) : func_mmu_flags_selector(b_rd_addr[5:2], memory_mmuflag_way3_out_data)
)
)
) : 14'h0;
assign oWR_BUSY = this_write_lock;
assign oUP_BUSY = iWR_REQ;
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__einvp (
Z ,
A ,
TE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_FUNCTIONAL_PP_V |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module p_bsf32_hw (
ap_clk,
ap_rst,
bus_r,
ap_return,
ap_ce
);
input ap_clk;
input ap_rst;
input [31:0] bus_r;
output [4:0] ap_return;
input ap_ce;
wire [0:0] tmp_fu_278_p1;
reg [0:0] tmp_reg_522;
wire [0:0] tmp_1_fu_282_p3;
reg [0:0] tmp_1_reg_526;
wire [0:0] tmp_2_fu_290_p3;
reg [0:0] tmp_2_reg_530;
wire [0:0] tmp_3_fu_298_p3;
reg [0:0] tmp_3_reg_534;
wire [0:0] tmp_4_fu_306_p3;
reg [0:0] tmp_4_reg_538;
wire [0:0] tmp_5_fu_314_p3;
reg [0:0] tmp_5_reg_542;
wire [0:0] tmp_6_fu_322_p3;
reg [0:0] tmp_6_reg_546;
wire [0:0] tmp_7_fu_330_p3;
reg [0:0] tmp_7_reg_550;
wire [0:0] tmp_8_fu_338_p3;
reg [0:0] tmp_8_reg_554;
wire [0:0] tmp_9_fu_346_p3;
reg [0:0] tmp_9_reg_558;
wire [0:0] tmp_10_fu_354_p3;
reg [0:0] tmp_10_reg_562;
wire [0:0] tmp_11_fu_362_p3;
reg [0:0] tmp_11_reg_566;
wire [0:0] tmp_12_fu_370_p3;
reg [0:0] tmp_12_reg_570;
wire [0:0] tmp_13_fu_378_p3;
reg [0:0] tmp_13_reg_574;
wire [0:0] tmp_14_fu_386_p3;
reg [0:0] tmp_14_reg_578;
wire [0:0] tmp_15_fu_394_p3;
reg [0:0] tmp_15_reg_582;
wire [0:0] tmp_16_fu_402_p3;
reg [0:0] tmp_16_reg_586;
wire [0:0] tmp_17_fu_410_p3;
reg [0:0] tmp_17_reg_590;
wire [0:0] tmp_18_fu_418_p3;
reg [0:0] tmp_18_reg_594;
wire [0:0] tmp_19_fu_426_p3;
reg [0:0] tmp_19_reg_598;
wire [0:0] tmp_20_fu_434_p3;
reg [0:0] tmp_20_reg_602;
wire [0:0] tmp_21_fu_442_p3;
reg [0:0] tmp_21_reg_606;
wire [0:0] tmp_22_fu_450_p3;
reg [0:0] tmp_22_reg_610;
wire [0:0] tmp_23_fu_458_p3;
reg [0:0] tmp_23_reg_614;
wire [0:0] tmp_24_fu_466_p3;
reg [0:0] tmp_24_reg_618;
wire [0:0] tmp_25_fu_474_p3;
reg [0:0] tmp_25_reg_622;
wire [0:0] tmp_26_fu_482_p3;
reg [0:0] tmp_26_reg_626;
wire [0:0] tmp_27_fu_490_p3;
reg [0:0] tmp_27_reg_630;
wire [0:0] tmp_28_fu_498_p3;
reg [0:0] tmp_28_reg_634;
wire [0:0] tmp_29_fu_506_p3;
reg [0:0] tmp_29_reg_638;
wire [0:0] tmp_30_fu_514_p3;
reg [0:0] tmp_30_reg_642;
wire [4:0] ap_reg_phiprechg_p_s_reg_136pp0_it0;
reg [4:0] ap_reg_phiprechg_p_s_reg_136pp0_it1;
wire [4:0] ap_reg_phiprechg_merge_reg_265pp0_it0;
reg [4:0] ap_reg_phiprechg_merge_reg_265pp0_it1;
reg [4:0] merge_phi_fu_269_p4;
reg ap_sig_bdd_764;
reg ap_sig_bdd_178;
reg ap_sig_bdd_183;
reg ap_sig_bdd_189;
reg ap_sig_bdd_196;
reg ap_sig_bdd_204;
reg ap_sig_bdd_213;
reg ap_sig_bdd_223;
reg ap_sig_bdd_234;
reg ap_sig_bdd_246;
reg ap_sig_bdd_259;
reg ap_sig_bdd_273;
reg ap_sig_bdd_288;
reg ap_sig_bdd_304;
reg ap_sig_bdd_321;
reg ap_sig_bdd_339;
reg ap_sig_bdd_358;
reg ap_sig_bdd_378;
reg ap_sig_bdd_399;
reg ap_sig_bdd_421;
reg ap_sig_bdd_444;
reg ap_sig_bdd_468;
reg ap_sig_bdd_493;
reg ap_sig_bdd_519;
reg ap_sig_bdd_546;
reg ap_sig_bdd_574;
reg ap_sig_bdd_603;
reg ap_sig_bdd_633;
reg ap_sig_bdd_664;
reg ap_sig_bdd_696;
reg ap_sig_bdd_730;
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv5_1 = 5'b1;
parameter ap_const_lv5_2 = 5'b10;
parameter ap_const_lv5_3 = 5'b11;
parameter ap_const_lv5_4 = 5'b100;
parameter ap_const_lv5_5 = 5'b101;
parameter ap_const_lv5_6 = 5'b110;
parameter ap_const_lv5_7 = 5'b111;
parameter ap_const_lv5_8 = 5'b1000;
parameter ap_const_lv5_9 = 5'b1001;
parameter ap_const_lv5_A = 5'b1010;
parameter ap_const_lv5_B = 5'b1011;
parameter ap_const_lv5_C = 5'b1100;
parameter ap_const_lv5_D = 5'b1101;
parameter ap_const_lv5_E = 5'b1110;
parameter ap_const_lv5_F = 5'b1111;
parameter ap_const_lv5_10 = 5'b10000;
parameter ap_const_lv5_11 = 5'b10001;
parameter ap_const_lv5_12 = 5'b10010;
parameter ap_const_lv5_13 = 5'b10011;
parameter ap_const_lv5_14 = 5'b10100;
parameter ap_const_lv5_15 = 5'b10101;
parameter ap_const_lv5_16 = 5'b10110;
parameter ap_const_lv5_17 = 5'b10111;
parameter ap_const_lv5_18 = 5'b11000;
parameter ap_const_lv5_19 = 5'b11001;
parameter ap_const_lv5_1A = 5'b11010;
parameter ap_const_lv5_1B = 5'b11011;
parameter ap_const_lv5_1C = 5'b11100;
parameter ap_const_lv5_1D = 5'b11101;
parameter ap_const_lv5_1E = 5'b11110;
parameter ap_const_lv5_1F = 5'b11111;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv32_6 = 32'b110;
parameter ap_const_lv32_7 = 32'b111;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv32_9 = 32'b1001;
parameter ap_const_lv32_A = 32'b1010;
parameter ap_const_lv32_B = 32'b1011;
parameter ap_const_lv32_C = 32'b1100;
parameter ap_const_lv32_D = 32'b1101;
parameter ap_const_lv32_E = 32'b1110;
parameter ap_const_lv32_F = 32'b1111;
parameter ap_const_lv32_10 = 32'b10000;
parameter ap_const_lv32_11 = 32'b10001;
parameter ap_const_lv32_12 = 32'b10010;
parameter ap_const_lv32_13 = 32'b10011;
parameter ap_const_lv32_14 = 32'b10100;
parameter ap_const_lv32_15 = 32'b10101;
parameter ap_const_lv32_16 = 32'b10110;
parameter ap_const_lv32_17 = 32'b10111;
parameter ap_const_lv32_18 = 32'b11000;
parameter ap_const_lv32_19 = 32'b11001;
parameter ap_const_lv32_1A = 32'b11010;
parameter ap_const_lv32_1B = 32'b11011;
parameter ap_const_lv32_1C = 32'b11100;
parameter ap_const_lv32_1D = 32'b11101;
parameter ap_const_lv32_1E = 32'b11110;
parameter ap_const_logic_0 = 1'b0;
parameter ap_true = 1'b1;
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_ce)) begin
if (ap_sig_bdd_764) begin
ap_reg_phiprechg_merge_reg_265pp0_it1[1] <= 1'b1;
ap_reg_phiprechg_merge_reg_265pp0_it1[2] <= 1'b1;
ap_reg_phiprechg_merge_reg_265pp0_it1[3] <= 1'b1;
ap_reg_phiprechg_merge_reg_265pp0_it1[4] <= 1'b1;
end else if ((ap_true == ap_true)) begin
ap_reg_phiprechg_merge_reg_265pp0_it1[1] <= ap_reg_phiprechg_merge_reg_265pp0_it0[1];
ap_reg_phiprechg_merge_reg_265pp0_it1[2] <= ap_reg_phiprechg_merge_reg_265pp0_it0[2];
ap_reg_phiprechg_merge_reg_265pp0_it1[3] <= ap_reg_phiprechg_merge_reg_265pp0_it0[3];
ap_reg_phiprechg_merge_reg_265pp0_it1[4] <= ap_reg_phiprechg_merge_reg_265pp0_it0[4];
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_ce)) begin
if (ap_sig_bdd_730) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1E;
end else if (ap_sig_bdd_696) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1D;
end else if (ap_sig_bdd_664) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1C;
end else if (ap_sig_bdd_633) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1B;
end else if (ap_sig_bdd_603) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1A;
end else if (ap_sig_bdd_574) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_19;
end else if (ap_sig_bdd_546) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_18;
end else if (ap_sig_bdd_519) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_17;
end else if (ap_sig_bdd_493) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_16;
end else if (ap_sig_bdd_468) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_15;
end else if (ap_sig_bdd_444) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_14;
end else if (ap_sig_bdd_421) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_13;
end else if (ap_sig_bdd_399) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_12;
end else if (ap_sig_bdd_378) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_11;
end else if (ap_sig_bdd_358) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_10;
end else if (ap_sig_bdd_339) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_F;
end else if (ap_sig_bdd_321) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_E;
end else if (ap_sig_bdd_304) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_D;
end else if (ap_sig_bdd_288) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_C;
end else if (ap_sig_bdd_273) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_B;
end else if (ap_sig_bdd_259) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_A;
end else if (ap_sig_bdd_246) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_9;
end else if (ap_sig_bdd_234) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_8;
end else if (ap_sig_bdd_223) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_7;
end else if (ap_sig_bdd_213) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_6;
end else if (ap_sig_bdd_204) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_5;
end else if (ap_sig_bdd_196) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_4;
end else if (ap_sig_bdd_189) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_3;
end else if (ap_sig_bdd_183) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_2;
end else if (ap_sig_bdd_178) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_1;
end else if (~(tmp_fu_278_p1 == ap_const_lv1_0)) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_const_lv5_0;
end else if ((ap_true == ap_true)) begin
ap_reg_phiprechg_p_s_reg_136pp0_it1 <= ap_reg_phiprechg_p_s_reg_136pp0_it0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3))) begin
tmp_10_reg_562 <= bus_r[ap_const_lv32_A];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3))) begin
tmp_11_reg_566 <= bus_r[ap_const_lv32_B];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3))) begin
tmp_12_reg_570 <= bus_r[ap_const_lv32_C];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3))) begin
tmp_13_reg_574 <= bus_r[ap_const_lv32_D];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3))) begin
tmp_14_reg_578 <= bus_r[ap_const_lv32_E];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3))) begin
tmp_15_reg_582 <= bus_r[ap_const_lv32_F];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3))) begin
tmp_16_reg_586 <= bus_r[ap_const_lv32_10];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3))) begin
tmp_17_reg_590 <= bus_r[ap_const_lv32_11];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3))) begin
tmp_18_reg_594 <= bus_r[ap_const_lv32_12];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3))) begin
tmp_19_reg_598 <= bus_r[ap_const_lv32_13];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0))) begin
tmp_1_reg_526 <= bus_r[ap_const_lv32_1];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3))) begin
tmp_20_reg_602 <= bus_r[ap_const_lv32_14];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3))) begin
tmp_21_reg_606 <= bus_r[ap_const_lv32_15];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3))) begin
tmp_22_reg_610 <= bus_r[ap_const_lv32_16];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3))) begin
tmp_23_reg_614 <= bus_r[ap_const_lv32_17];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3))) begin
tmp_24_reg_618 <= bus_r[ap_const_lv32_18];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3))) begin
tmp_25_reg_622 <= bus_r[ap_const_lv32_19];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3) & (ap_const_lv1_0 == tmp_25_fu_474_p3))) begin
tmp_26_reg_626 <= bus_r[ap_const_lv32_1A];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3) & (ap_const_lv1_0 == tmp_25_fu_474_p3) & (ap_const_lv1_0 == tmp_26_fu_482_p3))) begin
tmp_27_reg_630 <= bus_r[ap_const_lv32_1B];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3) & (ap_const_lv1_0 == tmp_25_fu_474_p3) & (ap_const_lv1_0 == tmp_26_fu_482_p3) & (ap_const_lv1_0 == tmp_27_fu_490_p3))) begin
tmp_28_reg_634 <= bus_r[ap_const_lv32_1C];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3) & (ap_const_lv1_0 == tmp_25_fu_474_p3) & (ap_const_lv1_0 == tmp_26_fu_482_p3) & (ap_const_lv1_0 == tmp_27_fu_490_p3) & (ap_const_lv1_0 == tmp_28_fu_498_p3))) begin
tmp_29_reg_638 <= bus_r[ap_const_lv32_1D];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0))) begin
tmp_2_reg_530 <= bus_r[ap_const_lv32_2];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3) & (ap_const_lv1_0 == tmp_25_fu_474_p3) & (ap_const_lv1_0 == tmp_26_fu_482_p3) & (ap_const_lv1_0 == tmp_27_fu_490_p3) & (ap_const_lv1_0 == tmp_28_fu_498_p3) & (ap_const_lv1_0 == tmp_29_fu_506_p3))) begin
tmp_30_reg_642 <= bus_r[ap_const_lv32_1E];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3))) begin
tmp_3_reg_534 <= bus_r[ap_const_lv32_3];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3))) begin
tmp_4_reg_538 <= bus_r[ap_const_lv32_4];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3))) begin
tmp_5_reg_542 <= bus_r[ap_const_lv32_5];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3))) begin
tmp_6_reg_546 <= bus_r[ap_const_lv32_6];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3))) begin
tmp_7_reg_550 <= bus_r[ap_const_lv32_7];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3))) begin
tmp_8_reg_554 <= bus_r[ap_const_lv32_8];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_ce) & (tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3))) begin
tmp_9_reg_558 <= bus_r[ap_const_lv32_9];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_ce)) begin
tmp_reg_522 <= tmp_fu_278_p1;
end
end
/// merge_phi_fu_269_p4 assign process. ///
always @ (tmp_reg_522 or tmp_1_reg_526 or tmp_2_reg_530 or tmp_3_reg_534 or tmp_4_reg_538 or tmp_5_reg_542 or tmp_6_reg_546 or tmp_7_reg_550 or tmp_8_reg_554 or tmp_9_reg_558 or tmp_10_reg_562 or tmp_11_reg_566 or tmp_12_reg_570 or tmp_13_reg_574 or tmp_14_reg_578 or tmp_15_reg_582 or tmp_16_reg_586 or tmp_17_reg_590 or tmp_18_reg_594 or tmp_19_reg_598 or tmp_20_reg_602 or tmp_21_reg_606 or tmp_22_reg_610 or tmp_23_reg_614 or tmp_24_reg_618 or tmp_25_reg_622 or tmp_26_reg_626 or tmp_27_reg_630 or tmp_28_reg_634 or tmp_29_reg_638 or tmp_30_reg_642 or ap_reg_phiprechg_p_s_reg_136pp0_it1 or ap_reg_phiprechg_merge_reg_265pp0_it1)
begin
if ((~(tmp_reg_522 == ap_const_lv1_0) | ~(tmp_1_reg_526 == ap_const_lv1_0) | ~(ap_const_lv1_0 == tmp_2_reg_530) | ~(ap_const_lv1_0 == tmp_3_reg_534) | ~(ap_const_lv1_0 == tmp_4_reg_538) | ~(ap_const_lv1_0 == tmp_5_reg_542) | ~(ap_const_lv1_0 == tmp_6_reg_546) | ~(ap_const_lv1_0 == tmp_7_reg_550) | ~(ap_const_lv1_0 == tmp_8_reg_554) | ~(ap_const_lv1_0 == tmp_9_reg_558) | ~(ap_const_lv1_0 == tmp_10_reg_562) | ~(ap_const_lv1_0 == tmp_11_reg_566) | ~(ap_const_lv1_0 == tmp_12_reg_570) | ~(ap_const_lv1_0 == tmp_13_reg_574) | ~(ap_const_lv1_0 == tmp_14_reg_578) | ~(ap_const_lv1_0 == tmp_15_reg_582) | ~(ap_const_lv1_0 == tmp_16_reg_586) | ~(ap_const_lv1_0 == tmp_17_reg_590) | ~(ap_const_lv1_0 == tmp_18_reg_594) | ~(ap_const_lv1_0 == tmp_19_reg_598) | ~(ap_const_lv1_0 == tmp_20_reg_602) | ~(ap_const_lv1_0 == tmp_21_reg_606) | ~(ap_const_lv1_0 == tmp_22_reg_610) | ~(ap_const_lv1_0 == tmp_23_reg_614) | ~(ap_const_lv1_0 == tmp_24_reg_618) | ~(ap_const_lv1_0 == tmp_25_reg_622) | ~(ap_const_lv1_0 == tmp_26_reg_626) | ~(ap_const_lv1_0 == tmp_27_reg_630) | ~(ap_const_lv1_0 == tmp_28_reg_634) | ~(ap_const_lv1_0 == tmp_29_reg_638) | ~(ap_const_lv1_0 == tmp_30_reg_642))) begin
merge_phi_fu_269_p4 = ap_reg_phiprechg_p_s_reg_136pp0_it1;
end else begin
merge_phi_fu_269_p4 = ap_reg_phiprechg_merge_reg_265pp0_it1;
end
end
assign ap_reg_phiprechg_merge_reg_265pp0_it0 = ap_const_lv5_1;
assign ap_reg_phiprechg_p_s_reg_136pp0_it0 = ap_const_lv5_1;
assign ap_return = merge_phi_fu_269_p4;
/// ap_sig_bdd_178 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3)
begin
ap_sig_bdd_178 = ((tmp_fu_278_p1 == ap_const_lv1_0) & ~(tmp_1_fu_282_p3 == ap_const_lv1_0));
end
/// ap_sig_bdd_183 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3)
begin
ap_sig_bdd_183 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & ~(ap_const_lv1_0 == tmp_2_fu_290_p3));
end
/// ap_sig_bdd_189 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3)
begin
ap_sig_bdd_189 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & ~(ap_const_lv1_0 == tmp_3_fu_298_p3));
end
/// ap_sig_bdd_196 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3)
begin
ap_sig_bdd_196 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & ~(ap_const_lv1_0 == tmp_4_fu_306_p3));
end
/// ap_sig_bdd_204 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3)
begin
ap_sig_bdd_204 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & ~(ap_const_lv1_0 == tmp_5_fu_314_p3));
end
/// ap_sig_bdd_213 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3)
begin
ap_sig_bdd_213 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & ~(ap_const_lv1_0 == tmp_6_fu_322_p3));
end
/// ap_sig_bdd_223 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3)
begin
ap_sig_bdd_223 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & ~(ap_const_lv1_0 == tmp_7_fu_330_p3));
end
/// ap_sig_bdd_234 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3)
begin
ap_sig_bdd_234 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & ~(ap_const_lv1_0 == tmp_8_fu_338_p3));
end
/// ap_sig_bdd_246 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3)
begin
ap_sig_bdd_246 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & ~(ap_const_lv1_0 == tmp_9_fu_346_p3));
end
/// ap_sig_bdd_259 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3)
begin
ap_sig_bdd_259 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & ~(ap_const_lv1_0 == tmp_10_fu_354_p3));
end
/// ap_sig_bdd_273 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3)
begin
ap_sig_bdd_273 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & ~(ap_const_lv1_0 == tmp_11_fu_362_p3));
end
/// ap_sig_bdd_288 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3)
begin
ap_sig_bdd_288 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & ~(ap_const_lv1_0 == tmp_12_fu_370_p3));
end
/// ap_sig_bdd_304 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3)
begin
ap_sig_bdd_304 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & ~(ap_const_lv1_0 == tmp_13_fu_378_p3));
end
/// ap_sig_bdd_321 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3)
begin
ap_sig_bdd_321 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & ~(ap_const_lv1_0 == tmp_14_fu_386_p3));
end
/// ap_sig_bdd_339 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3)
begin
ap_sig_bdd_339 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & ~(ap_const_lv1_0 == tmp_15_fu_394_p3));
end
/// ap_sig_bdd_358 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3)
begin
ap_sig_bdd_358 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & ~(ap_const_lv1_0 == tmp_16_fu_402_p3));
end
/// ap_sig_bdd_378 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3)
begin
ap_sig_bdd_378 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & ~(ap_const_lv1_0 == tmp_17_fu_410_p3));
end
/// ap_sig_bdd_399 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3)
begin
ap_sig_bdd_399 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & ~(ap_const_lv1_0 == tmp_18_fu_418_p3));
end
/// ap_sig_bdd_421 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3)
begin
ap_sig_bdd_421 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & ~(ap_const_lv1_0 == tmp_19_fu_426_p3));
end
/// ap_sig_bdd_444 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3 or tmp_20_fu_434_p3)
begin
ap_sig_bdd_444 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & ~(ap_const_lv1_0 == tmp_20_fu_434_p3));
end
/// ap_sig_bdd_468 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3 or tmp_20_fu_434_p3 or tmp_21_fu_442_p3)
begin
ap_sig_bdd_468 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & ~(ap_const_lv1_0 == tmp_21_fu_442_p3));
end
/// ap_sig_bdd_493 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3 or tmp_20_fu_434_p3 or tmp_21_fu_442_p3 or tmp_22_fu_450_p3)
begin
ap_sig_bdd_493 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & ~(ap_const_lv1_0 == tmp_22_fu_450_p3));
end
/// ap_sig_bdd_519 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3 or tmp_20_fu_434_p3 or tmp_21_fu_442_p3 or tmp_22_fu_450_p3 or tmp_23_fu_458_p3)
begin
ap_sig_bdd_519 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & ~(ap_const_lv1_0 == tmp_23_fu_458_p3));
end
/// ap_sig_bdd_546 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3 or tmp_20_fu_434_p3 or tmp_21_fu_442_p3 or tmp_22_fu_450_p3 or tmp_23_fu_458_p3 or tmp_24_fu_466_p3)
begin
ap_sig_bdd_546 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & ~(ap_const_lv1_0 == tmp_24_fu_466_p3));
end
/// ap_sig_bdd_574 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3 or tmp_20_fu_434_p3 or tmp_21_fu_442_p3 or tmp_22_fu_450_p3 or tmp_23_fu_458_p3 or tmp_24_fu_466_p3 or tmp_25_fu_474_p3)
begin
ap_sig_bdd_574 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3) & ~(ap_const_lv1_0 == tmp_25_fu_474_p3));
end
/// ap_sig_bdd_603 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3 or tmp_20_fu_434_p3 or tmp_21_fu_442_p3 or tmp_22_fu_450_p3 or tmp_23_fu_458_p3 or tmp_24_fu_466_p3 or tmp_25_fu_474_p3 or tmp_26_fu_482_p3)
begin
ap_sig_bdd_603 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3) & (ap_const_lv1_0 == tmp_25_fu_474_p3) & ~(ap_const_lv1_0 == tmp_26_fu_482_p3));
end
/// ap_sig_bdd_633 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3 or tmp_20_fu_434_p3 or tmp_21_fu_442_p3 or tmp_22_fu_450_p3 or tmp_23_fu_458_p3 or tmp_24_fu_466_p3 or tmp_25_fu_474_p3 or tmp_26_fu_482_p3 or tmp_27_fu_490_p3)
begin
ap_sig_bdd_633 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3) & (ap_const_lv1_0 == tmp_25_fu_474_p3) & (ap_const_lv1_0 == tmp_26_fu_482_p3) & ~(ap_const_lv1_0 == tmp_27_fu_490_p3));
end
/// ap_sig_bdd_664 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3 or tmp_20_fu_434_p3 or tmp_21_fu_442_p3 or tmp_22_fu_450_p3 or tmp_23_fu_458_p3 or tmp_24_fu_466_p3 or tmp_25_fu_474_p3 or tmp_26_fu_482_p3 or tmp_27_fu_490_p3 or tmp_28_fu_498_p3)
begin
ap_sig_bdd_664 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3) & (ap_const_lv1_0 == tmp_25_fu_474_p3) & (ap_const_lv1_0 == tmp_26_fu_482_p3) & (ap_const_lv1_0 == tmp_27_fu_490_p3) & ~(ap_const_lv1_0 == tmp_28_fu_498_p3));
end
/// ap_sig_bdd_696 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3 or tmp_20_fu_434_p3 or tmp_21_fu_442_p3 or tmp_22_fu_450_p3 or tmp_23_fu_458_p3 or tmp_24_fu_466_p3 or tmp_25_fu_474_p3 or tmp_26_fu_482_p3 or tmp_27_fu_490_p3 or tmp_28_fu_498_p3 or tmp_29_fu_506_p3)
begin
ap_sig_bdd_696 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3) & (ap_const_lv1_0 == tmp_25_fu_474_p3) & (ap_const_lv1_0 == tmp_26_fu_482_p3) & (ap_const_lv1_0 == tmp_27_fu_490_p3) & (ap_const_lv1_0 == tmp_28_fu_498_p3) & ~(ap_const_lv1_0 == tmp_29_fu_506_p3));
end
/// ap_sig_bdd_730 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3 or tmp_20_fu_434_p3 or tmp_21_fu_442_p3 or tmp_22_fu_450_p3 or tmp_23_fu_458_p3 or tmp_24_fu_466_p3 or tmp_25_fu_474_p3 or tmp_26_fu_482_p3 or tmp_27_fu_490_p3 or tmp_28_fu_498_p3 or tmp_29_fu_506_p3 or tmp_30_fu_514_p3)
begin
ap_sig_bdd_730 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3) & (ap_const_lv1_0 == tmp_25_fu_474_p3) & (ap_const_lv1_0 == tmp_26_fu_482_p3) & (ap_const_lv1_0 == tmp_27_fu_490_p3) & (ap_const_lv1_0 == tmp_28_fu_498_p3) & (ap_const_lv1_0 == tmp_29_fu_506_p3) & ~(ap_const_lv1_0 == tmp_30_fu_514_p3));
end
/// ap_sig_bdd_764 assign process. ///
always @ (tmp_fu_278_p1 or tmp_1_fu_282_p3 or tmp_2_fu_290_p3 or tmp_3_fu_298_p3 or tmp_4_fu_306_p3 or tmp_5_fu_314_p3 or tmp_6_fu_322_p3 or tmp_7_fu_330_p3 or tmp_8_fu_338_p3 or tmp_9_fu_346_p3 or tmp_10_fu_354_p3 or tmp_11_fu_362_p3 or tmp_12_fu_370_p3 or tmp_13_fu_378_p3 or tmp_14_fu_386_p3 or tmp_15_fu_394_p3 or tmp_16_fu_402_p3 or tmp_17_fu_410_p3 or tmp_18_fu_418_p3 or tmp_19_fu_426_p3 or tmp_20_fu_434_p3 or tmp_21_fu_442_p3 or tmp_22_fu_450_p3 or tmp_23_fu_458_p3 or tmp_24_fu_466_p3 or tmp_25_fu_474_p3 or tmp_26_fu_482_p3 or tmp_27_fu_490_p3 or tmp_28_fu_498_p3 or tmp_29_fu_506_p3 or tmp_30_fu_514_p3)
begin
ap_sig_bdd_764 = ((tmp_fu_278_p1 == ap_const_lv1_0) & (tmp_1_fu_282_p3 == ap_const_lv1_0) & (ap_const_lv1_0 == tmp_2_fu_290_p3) & (ap_const_lv1_0 == tmp_3_fu_298_p3) & (ap_const_lv1_0 == tmp_4_fu_306_p3) & (ap_const_lv1_0 == tmp_5_fu_314_p3) & (ap_const_lv1_0 == tmp_6_fu_322_p3) & (ap_const_lv1_0 == tmp_7_fu_330_p3) & (ap_const_lv1_0 == tmp_8_fu_338_p3) & (ap_const_lv1_0 == tmp_9_fu_346_p3) & (ap_const_lv1_0 == tmp_10_fu_354_p3) & (ap_const_lv1_0 == tmp_11_fu_362_p3) & (ap_const_lv1_0 == tmp_12_fu_370_p3) & (ap_const_lv1_0 == tmp_13_fu_378_p3) & (ap_const_lv1_0 == tmp_14_fu_386_p3) & (ap_const_lv1_0 == tmp_15_fu_394_p3) & (ap_const_lv1_0 == tmp_16_fu_402_p3) & (ap_const_lv1_0 == tmp_17_fu_410_p3) & (ap_const_lv1_0 == tmp_18_fu_418_p3) & (ap_const_lv1_0 == tmp_19_fu_426_p3) & (ap_const_lv1_0 == tmp_20_fu_434_p3) & (ap_const_lv1_0 == tmp_21_fu_442_p3) & (ap_const_lv1_0 == tmp_22_fu_450_p3) & (ap_const_lv1_0 == tmp_23_fu_458_p3) & (ap_const_lv1_0 == tmp_24_fu_466_p3) & (ap_const_lv1_0 == tmp_25_fu_474_p3) & (ap_const_lv1_0 == tmp_26_fu_482_p3) & (ap_const_lv1_0 == tmp_27_fu_490_p3) & (ap_const_lv1_0 == tmp_28_fu_498_p3) & (ap_const_lv1_0 == tmp_29_fu_506_p3) & (ap_const_lv1_0 == tmp_30_fu_514_p3));
end
assign tmp_10_fu_354_p3 = bus_r[ap_const_lv32_A];
assign tmp_11_fu_362_p3 = bus_r[ap_const_lv32_B];
assign tmp_12_fu_370_p3 = bus_r[ap_const_lv32_C];
assign tmp_13_fu_378_p3 = bus_r[ap_const_lv32_D];
assign tmp_14_fu_386_p3 = bus_r[ap_const_lv32_E];
assign tmp_15_fu_394_p3 = bus_r[ap_const_lv32_F];
assign tmp_16_fu_402_p3 = bus_r[ap_const_lv32_10];
assign tmp_17_fu_410_p3 = bus_r[ap_const_lv32_11];
assign tmp_18_fu_418_p3 = bus_r[ap_const_lv32_12];
assign tmp_19_fu_426_p3 = bus_r[ap_const_lv32_13];
assign tmp_1_fu_282_p3 = bus_r[ap_const_lv32_1];
assign tmp_20_fu_434_p3 = bus_r[ap_const_lv32_14];
assign tmp_21_fu_442_p3 = bus_r[ap_const_lv32_15];
assign tmp_22_fu_450_p3 = bus_r[ap_const_lv32_16];
assign tmp_23_fu_458_p3 = bus_r[ap_const_lv32_17];
assign tmp_24_fu_466_p3 = bus_r[ap_const_lv32_18];
assign tmp_25_fu_474_p3 = bus_r[ap_const_lv32_19];
assign tmp_26_fu_482_p3 = bus_r[ap_const_lv32_1A];
assign tmp_27_fu_490_p3 = bus_r[ap_const_lv32_1B];
assign tmp_28_fu_498_p3 = bus_r[ap_const_lv32_1C];
assign tmp_29_fu_506_p3 = bus_r[ap_const_lv32_1D];
assign tmp_2_fu_290_p3 = bus_r[ap_const_lv32_2];
assign tmp_30_fu_514_p3 = bus_r[ap_const_lv32_1E];
assign tmp_3_fu_298_p3 = bus_r[ap_const_lv32_3];
assign tmp_4_fu_306_p3 = bus_r[ap_const_lv32_4];
assign tmp_5_fu_314_p3 = bus_r[ap_const_lv32_5];
assign tmp_6_fu_322_p3 = bus_r[ap_const_lv32_6];
assign tmp_7_fu_330_p3 = bus_r[ap_const_lv32_7];
assign tmp_8_fu_338_p3 = bus_r[ap_const_lv32_8];
assign tmp_9_fu_346_p3 = bus_r[ap_const_lv32_9];
assign tmp_fu_278_p1 = bus_r[0:0];
always @ (posedge ap_clk)
begin
ap_reg_phiprechg_merge_reg_265pp0_it1[0] <= 1'b1;
end
endmodule //p_bsf32_hw
|
/*
* Redistributions of any form whatsoever must retain and/or include the
* following acknowledgment, notices and disclaimer:
*
* This product includes software developed by Carnegie Mellon University.
*
* Copyright (c) 2004 by Babak Falsafi and James Hoe,
* Computer Architecture Lab at Carnegie Mellon (CALCM),
* Carnegie Mellon University.
*
* This source file was written and maintained by Jared Smolens
* as part of the Two-Way In-Order Superscalar project for Carnegie Mellon's
* Introduction to Computer Architecture course, 18-447. The source file
* is in part derived from code originally written by Herman Schmit and
* Diana Marculescu.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* If you modify the software you must place a notice on or within any
* modified version provided or made available to any third party stating
* that you have modified the software. The notice shall include at least
* your name, address, phone number, email address and the date and purpose
* of the modification.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANYWARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
// Top module for the ARM processor core
// NOT synthesizable Verilog!
module testbench;
reg [31:0] i;
reg [29:0] addr;
wire clk, inst_excpt, mem_excpt, halted;
wire [29:0] pc, mem_addr;
wire [31:0] inst, mem_data_in, mem_data_out;
wire [3:0] mem_write_en;
reg rst_b;
// The clock
clock CLK(clk);
// The ARM core
arm_core core(.clk(clk), .inst_addr(pc), .inst(inst),
.mem_addr(mem_addr), .mem_data_in(mem_data_in), .mem_data_out(mem_data_out),
.mem_write_en(mem_write_en),
.halted(halted), .rst_b(rst_b));
// Memory
arm_mem Memory(// Port 1 (instructions)
.addr1(pc), .data_in1(), .data_out1(inst), .we1(4'b0),
.excpt1(), .allow_kernel1(1'b1), .kernel1(),
// Port 2 (data)
.addr2(mem_addr), .data_in2(mem_data_in),
.data_out2(mem_data_out), .we2(mem_write_en),
.excpt2(), .allow_kernel2(1'b1), .kernel2(),
.rst_b(rst_b), .clk(clk));
initial
begin
rst_b = 0;
#75;
rst_b <= 1;
end
always @(halted)
begin
#0;
if(halted === 1'b1)
$finish;
end
endmodule
// Clock module for the ARM core. You may increase the clock period
// if your design requires it.
module clock(clockSignal);
parameter start = 0, halfPeriod = 50;
output clockSignal;
reg clockSignal;
initial
clockSignal = start;
always
#halfPeriod clockSignal = ~clockSignal;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: afifo.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:32 $
// \ \ / \ Date Created: Oct 21 2008
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: A generic synchronous fifo.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module afifo #
(
parameter TCQ = 100,
parameter DSIZE = 32,
parameter FIFO_DEPTH = 16,
parameter ASIZE = 4,
parameter SYNC = 1 // only has always '1' logic.
)
(
input wr_clk,
input rst,
input wr_en,
input [DSIZE-1:0] wr_data,
input rd_en,
input rd_clk,
output [DSIZE-1:0] rd_data,
output reg full,
output reg empty,
output reg almost_full
);
// memory array
reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1];
//Read Capture Logic
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
reg [ASIZE:0] rd_gray_nxt;
reg [ASIZE:0] rd_gray;
reg [ASIZE:0] rd_capture_ptr;
reg [ASIZE:0] pre_rd_capture_gray_ptr;
reg [ASIZE:0] rd_capture_gray_ptr;
reg [ASIZE:0] wr_gray;
reg [ASIZE:0] wr_gray_nxt;
reg [ASIZE:0] wr_capture_ptr;
reg [ASIZE:0] pre_wr_capture_gray_ptr;
reg [ASIZE:0] wr_capture_gray_ptr;
wire [ASIZE:0] buf_avail;
wire [ASIZE:0] buf_filled;
wire [ASIZE-1:0] wr_addr, rd_addr;
reg [ASIZE:0] wr_ptr, rd_ptr;
integer i,j,k;
// for design that use the same clock for both read and write
generate
if (SYNC == 1) begin: RDSYNC
always @ (rd_ptr)
rd_capture_ptr = rd_ptr;
end
endgenerate
//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers
// before do comparison.
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
generate
if (SYNC == 1) begin: WRSYNC
always @ (wr_ptr)
wr_capture_ptr = wr_ptr;
end
endgenerate
// dualport ram
// Memory (RAM) that holds the contents of the FIFO
assign wr_addr = wr_ptr;
assign rd_data = mem[rd_addr];
always @(posedge wr_clk)
begin
if (wr_en && !full)
mem[wr_addr] <= #TCQ wr_data;
end
// Read Side Logic
assign rd_addr = rd_ptr[ASIZE-1:0];
assign rd_strobe = rd_en && !empty;
integer n;
reg [ASIZE:0] rd_ptr_tmp;
// change the binary pointer to gray pointer
always @ (rd_ptr)
begin
// rd_gray_nxt[ASIZE] = rd_ptr_tmp[ASIZE];
// for (n=0; n < ASIZE; n=n+1)
// rd_gray_nxt[n] = rd_ptr_tmp[n] ^ rd_ptr_tmp[n+1];
rd_gray_nxt[ASIZE] = rd_ptr[ASIZE];
for (n=0; n < ASIZE; n=n+1)
rd_gray_nxt[n] = rd_ptr[n] ^ rd_ptr[n+1];
end
always @(posedge rd_clk)
begin
if (rst)
begin
rd_ptr <= #TCQ 'b0;
rd_gray <= #TCQ 'b0;
end
else begin
if (rd_strobe)
rd_ptr <= #TCQ rd_ptr + 1;
rd_ptr_tmp <= #TCQ rd_ptr;
// change the binary pointer to gray pointer
rd_gray <= #TCQ rd_gray_nxt;
end
end
//generate empty signal
assign buf_filled = wr_capture_ptr - rd_ptr;
always @ (posedge rd_clk )
begin
if (rst)
empty <= #TCQ 1'b1;
else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe))
empty <= #TCQ 1'b1;
else
empty <= #TCQ 1'b0;
end
// write side logic;
reg [ASIZE:0] wbin;
wire [ASIZE:0] wgraynext, wbinnext;
always @(posedge rd_clk)
begin
if (rst)
begin
wr_ptr <= #TCQ 'b0;
wr_gray <= #TCQ 'b0;
end
else begin
if (wr_en)
wr_ptr <= #TCQ wr_ptr + 1;
// change the binary pointer to gray pointer
wr_gray <= #TCQ wr_gray_nxt;
end
end
// change the write pointer to gray pointer
always @ (wr_ptr)
begin
wr_gray_nxt[ASIZE] = wr_ptr[ASIZE];
for (n=0; n < ASIZE; n=n+1)
wr_gray_nxt[n] = wr_ptr[n] ^ wr_ptr[n+1];
end
// calculate how many buf still available
assign buf_avail = (rd_capture_ptr + FIFO_DEPTH) - wr_ptr;
always @ (posedge wr_clk )
begin
if (rst)
full <= #TCQ 1'b0;
else if ((buf_avail == 0) || (buf_avail == 1 && wr_en))
full <= #TCQ 1'b1;
else
full <= #TCQ 1'b0;
end
always @ (posedge wr_clk )
begin
if (rst)
almost_full <= #TCQ 1'b0;
else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en))
almost_full <= #TCQ 1'b1;
else
almost_full <= #TCQ 1'b0;
end
endmodule
|
// hub
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
// RR20140816 Remove unscrambling ROM code (now not scrambled)
`include "hub_mem.v"
module hub
(
input clk_cog,
input ena_bus,
input nres,
input [7:0] bus_sel,
input bus_r,
input bus_e,
input bus_w,
input [1:0] bus_s,
input [15:0] bus_a,
input [31:0] bus_d,
output reg [31:0] bus_q,
output bus_c,
output [7:0] bus_ack,
output reg [7:0] cog_ena,
output [7:0] ptr_w,
output [27:0] ptr_d,
output reg [7:0] cfg
);
// latch bus signals from cog[n]
reg rc;
reg ec;
reg wc;
reg [1:0] sc;
reg [15:0] ac;
reg [31:0] dc;
always @(posedge clk_cog)
if (ena_bus)
rc <= bus_r;
always @(posedge clk_cog or negedge nres)
if (!nres)
ec <= 1'b0;
else if (ena_bus)
ec <= bus_e;
always @(posedge clk_cog)
if (ena_bus)
wc <= bus_w;
always @(posedge clk_cog)
if (ena_bus)
sc <= bus_s;
always @(posedge clk_cog)
if (ena_bus)
ac <= bus_a;
always @(posedge clk_cog)
if (ena_bus)
dc <= bus_d;
// connect hub memory to signals from cog[n-1]
wire mem_w = ec && ~&sc && wc;
wire [3:0] mem_wb = sc[1] ? 4'b1111 // wrlong
: sc[0] ? ac[1] ? 4'b1100 : 4'b0011 // wrword
: 4'b0001 << ac[1:0]; // wrbyte
wire [31:0] mem_d = sc[1] ? dc // wrlong
: sc[0] ? {2{dc[15:0]}} // wrword
: {4{dc[7:0]}}; // wrbyte
wire [31:0] mem_q;
hub_mem hub_mem_ ( .clk_cog (clk_cog),
.ena_bus (ena_bus),
.w (mem_w),
.wb (mem_wb),
.a (ac[15:2]),
.d (mem_d),
.q (mem_q) );
// latch bus signals from cog[n-1]
reg rd;
reg ed;
reg [1:0] sd;
reg [1:0] ad;
always @(posedge clk_cog)
if (ena_bus)
rd <= !rc && ac[15];
always @(posedge clk_cog or negedge nres)
if (!nres)
ed <= 1'b0;
else if (ena_bus)
ed <= ec;
always @(posedge clk_cog)
if (ena_bus)
sd <= sc;
always @(posedge clk_cog)
if (ena_bus)
ad <= ac[1:0];
// set bus output according to cog[n-2]
wire [31:0] ramq = mem_q;
always @(posedge clk_cog)
bus_q <= sd[1] ? sd[0] ? {29'b0, sys_q} // cogid/coginit/locknew
: ramq // rdlong
: sd[0] ? ramq >> {ad[1], 4'b0} & 32'h0000FFFF // rdword
: ramq >> {ad[1:0], 3'b0} & 32'h000000FF; // rdbyte
assign bus_c = sys_c;
// generate bus acknowledge for cog[n-2]
assign bus_ack = ed ? {bus_sel[1:0], bus_sel[7:2]} : 8'b0;
// sys common logic
//
// ac in dc in num sys_q sys_c
// -----------------------------------------------------------------------------------------
// 000 CLKSET config(8) - - -
// 001 COGID - - [n-1] -
// 010 COGINIT ptr(28),newx,id(3) id(3)/newx id(3)/newx all
// 011 COGSTOP -,id(3) id(3) id(3) -
// 100 LOCKNEW - newx newx all
// 101 LOCKRET -,id(3) id(3) id(3) -
// 110 LOCKSET -,id(3) id(3) id(3) lock_state[id(3)]
// 111 LOCKCLR -,id(3) id(3) id(3) lock_state[id(3)]
wire sys = ec && (&sc);
wire [7:0] enc = ac[2] ? lock_e : cog_e;
wire all = &enc; // no free cogs/locks
wire [2:0] newx = &enc[3:0] ? &enc[5:4] ? enc[6] ? 3'b111 // x1111111 -> 111
: 3'b110 // x0111111 -> 110
: enc[4] ? 3'b101 // xx011111 -> 101
: 3'b100 // xxx01111 -> 100
: &enc[1:0] ? enc[2] ? 3'b011 // xxxx0111 -> 011
: 3'b010 // xxxxx011 -> 010
: enc[0] ? 3'b001 // xxxxxx01 -> 001
: 3'b000; // xxxxxxx0 -> 000
wire [2:0] num = ac[2:0] == 3'b010 && dc[3] || ac[2:0] == 3'b100 ? newx : dc[2:0];
wire [7:0] num_dcd = 1'b1 << num;
// cfg
always @(posedge clk_cog or negedge nres)
if (!nres)
cfg <= 8'b0;
else if (ena_bus && sys && ac[2:0] == 3'b000)
cfg <= dc[7:0];
// cogs
reg [7:0] cog_e;
wire cog_start = sys && ac[2:0] == 3'b010 && !(dc[3] && all);
always @(posedge clk_cog or negedge nres)
if (!nres)
cog_e <= 8'b00000001;
else if (ena_bus && sys && ac[2:1] == 2'b01)
cog_e <= cog_e & ~num_dcd | {8{!ac[0]}} & num_dcd;
always @(posedge clk_cog or negedge nres)
if (!nres)
cog_ena <= 8'b0;
else if (ena_bus)
cog_ena <= cog_e & ~({8{cog_start}} & num_dcd);
assign ptr_w = {8{cog_start}} & num_dcd;
assign ptr_d = dc[31:4];
// locks
reg [7:0] lock_e;
reg [7:0] lock_state;
always @(posedge clk_cog or negedge nres)
if (!nres)
lock_e <= 8'b0;
else if (ena_bus && sys && ac[2:1] == 2'b10)
lock_e <= lock_e & ~num_dcd | {8{!ac[0]}} & num_dcd;
always @(posedge clk_cog)
if (ena_bus && sys && ac[2:1] == 2'b11)
lock_state <= lock_state & ~num_dcd | {8{!ac[0]}} & num_dcd;
wire lock_mux = lock_state[dc[2:0]];
// output
reg [2:0] sys_q;
reg sys_c;
always @(posedge clk_cog)
if (ena_bus && sys)
sys_q <= ac[2:0] == 3'b001 ? { bus_sel[7] || bus_sel[6] || bus_sel[5] || bus_sel[0], // cogid
bus_sel[7] || bus_sel[4] || bus_sel[3] || bus_sel[0],
bus_sel[6] || bus_sel[4] || bus_sel[2] || bus_sel[0] }
: num; // others
always @(posedge clk_cog)
if (ena_bus && sys)
sys_c <= ac[2:1] == 2'b11 ? lock_mux // lockset/lockclr
: all; // others
endmodule
|
module paj_raygentop_hierarchy_no_mem (rgwant_addr, rgwant_data, rgread_ready, rgaddr_ready, rgdata_ready, rgwant_read, rgdatain, rgdataout, rgaddrin, rgCont, rgStat, rgCfgData, rgwant_CfgData, rgCfgData_ready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, tm3_clk_v0, fbdata, fbdatavalid, fbnextscanline, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, globalreset, rgData, rgAddr, rgWE, rgAddrValid, rgDone, rgResultData, rgResultReady, rgResultSource);
output rgwant_addr;
wire rgwant_addr;
output rgwant_data;
wire rgwant_data;
output rgread_ready;
wire rgread_ready;
input rgaddr_ready;
input rgdata_ready;
input rgwant_read;
input[63:0] rgdatain;
output[63:0] rgdataout;
wire[63:0] rgdataout;
input[17:0] rgaddrin;
input[31:0] rgCont;
output[31:0] rgStat;
wire[31:0] rgStat;
input[31:0] rgCfgData;
output rgwant_CfgData;
wire rgwant_CfgData;
input rgCfgData_ready;
input[63:0] tm3_sram_data_in;
wire[63:0] tm3_sram_data_in;
output[63:0] tm3_sram_data_out;
wire[63:0] tm3_sram_data_out;
wire[63:0] tm3_sram_data_xhdl0;
output[18:0] tm3_sram_addr;
wire[18:0] tm3_sram_addr;
output[7:0] tm3_sram_we;
wire[7:0] tm3_sram_we;
output[1:0] tm3_sram_oe;
wire[1:0] tm3_sram_oe;
output tm3_sram_adsp;
wire tm3_sram_adsp;
input tm3_clk_v0;
output[63:0] fbdata;
wire[63:0] fbdata;
output fbdatavalid;
wire fbdatavalid;
input fbnextscanline;
output[1:0] raygroup01;
wire[1:0] raygroup01;
output raygroupvalid01;
wire raygroupvalid01;
input busy01;
output[1:0] raygroup10;
wire[1:0] raygroup10;
output raygroupvalid10;
wire raygroupvalid10;
input busy10;
input globalreset;
output[31:0] rgData;
wire[31:0] rgData;
output[3:0] rgAddr;
wire[3:0] rgAddr;
output[2:0] rgWE;
wire[2:0] rgWE;
output rgAddrValid;
wire rgAddrValid;
input rgDone;
input[31:0] rgResultData;
input rgResultReady;
input[1:0] rgResultSource;
wire[2:0] statepeek2;
wire as01;
wire ack01;
wire[3:0] addr01;
wire[47:0] dir01;
wire[47:0] dir;
wire[47:0] sramdatal;
wire wantDir;
wire dirReady;
wire dirReadyl;
wire[14:0] address;
wire[30:0] cyclecounter;
wire nas01;
wire nas10;
wire go;
reg page;
wire[2:0] statepeekct;
// result Signals
wire valid01;
wire valid10;
wire[15:0] id01a;
wire[15:0] id01b;
wire[15:0] id01c;
wire[15:0] id10a;
wire[15:0] id10b;
wire[15:0] id10c;
wire hit01a;
wire hit01b;
wire hit01c;
wire hit10a;
wire hit10b;
wire hit10c;
wire[7:0] u01a;
wire[7:0] u01b;
wire[7:0] u01c;
wire[7:0] v01a;
wire[7:0] v01b;
wire[7:0] v01c;
wire[7:0] u10a;
wire[7:0] u10b;
wire[7:0] u10c;
wire[7:0] v10a;
wire[7:0] v10b;
wire[7:0] v10c;
wire wantwriteback;
wire writebackack;
wire[63:0] writebackdata;
wire[17:0] writebackaddr;
wire[17:0] nextaddr01;
// Shading Signals
wire[63:0] shadedata;
wire[15:0] triID;
wire wantshadedata;
wire shadedataready;
// CfgData Signals
wire[27:0] origx;
wire[27:0] origy;
wire[27:0] origz;
wire[15:0] m11;
wire[15:0] m12;
wire[15:0] m13;
wire[15:0] m21;
wire[15:0] m22;
wire[15:0] m23;
wire[15:0] m31;
wire[15:0] m32;
wire[15:0] m33;
wire[20:0] bkcolour;
// Texture signals
wire[20:0] texinfo;
wire[3:0] texaddr;
wire[63:0] texel;
wire[17:0] texeladdr;
wire wanttexel;
wire texelready;
// Frame Buffer Read Signals
wire fbpage;
// debug signals
wire wantcfg;
wire debugglobalreset;
assign rgwant_CfgData = wantcfg ;
onlyonecycle onlyeonecycleinst (rgCont[0], go, globalreset, tm3_clk_v0);
always @(posedge tm3_clk_v0 or posedge globalreset)
begin
if (globalreset == 1'b1)
begin
page <= 1'b1 ; // Reset to 1 such that first flip sets to 0
end
else
begin
page <= ~page ;
end
end
assign fbpage = ~page ;
matmult matmultinst(sramdatal[47:32], sramdatal[31:16], sramdatal[15:0], m11, m12, m13, m21, m22, m23, m31, m32, m33, dir[47:32], dir[31:16], dir[15:0], tm3_clk_v0);
delay1x3 dir01delay(dirReady, dirReadyl, tm3_clk_v0);
rgconfigmemory ConfigMemoryInst (rgCfgData[31:28], rgCfgData[27:0], rgCfgData_ready, wantcfg, origx, origy, origz, m11, m12, m13, m21, m22, m23, m31, m32, m33, bkcolour, texinfo, globalreset, tm3_clk_v0);
rgsramcontroller sramcont (rgwant_addr, rgaddr_ready, rgaddrin, rgwant_data, rgdata_ready, rgdatain, rgwant_read, rgread_ready, rgdataout, dirReady, wantDir, sramdatal, address, wantwriteback, writebackack, writebackdata, writebackaddr, fbdata, fbnextscanline, fbdatavalid, fbpage, shadedata, triID, wantshadedata, shadedataready, texeladdr, texel, wanttexel, texelready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, tm3_clk_v0);
raysend raysendinst (as01, ack01, addr01, dir01, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, tm3_clk_v0, statepeek2);
raygencont raygencontinst(go, rgCont[15:1], rgStat[31], cyclecounter, nextaddr01, nas01, nas10, page, dirReadyl, wantDir, dir, address, as01, addr01, ack01, dir01, raygroup01, raygroupvalid01, busy01, raygroup10, raygroupvalid10, busy10, globalreset, tm3_clk_v0, statepeekct);
resultrecieve resultrecieveinst (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, tm3_clk_v0);
assign debugglobalreset = globalreset | go ;
resultwriter resultwriteinst (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, nextaddr01, nas01, nas10, bkcolour, shadedata, triID, wantshadedata, shadedataready, texinfo, texaddr, texeladdr, texel, wanttexel, texelready, writebackdata, writebackaddr, wantwriteback, writebackack, debugglobalreset, tm3_clk_v0);
assign rgStat[30:0] = cyclecounter ;
endmodule
module delay1x3 (datain, dataout, clk);
input datain;
output dataout;
wire dataout;
input clk;
reg buff0;
reg buff1;
reg buff2;
assign dataout = buff2 ;
always @(posedge clk)
begin
/* PAJ expanded for loop to hard definition the size of `depth */
buff0 <= datain ;
buff1 <= buff0;
buff2 <= buff1;
end
endmodule
// A debugging circuit that allows a single cycle pulse to be
// generated by through the ports package
module onlyonecycle (trigger, output_xhdl0, globalreset, clk);
input trigger;
output output_xhdl0;
reg output_xhdl0;
input globalreset;
input clk;
reg[1:0] state;
reg[1:0] next_state;
reg count;
reg temp_count;
always @(posedge clk or posedge globalreset)
begin
if (globalreset == 1'b1)
begin
state <= 0 ;
count <= 0 ;
end
else
begin
state <= next_state ;
count <= temp_count;
end
end
always @(state or trigger or count)
begin
case (state)
0 :
begin
output_xhdl0 = 1'b0 ;
if (trigger == 1'b1)
begin
next_state = 1 ;
end
else
begin
next_state = 0 ;
end
temp_count = 1 - 1 ;
end
1 :
begin
output_xhdl0 = 1'b1 ;
if (count == 0)
begin
next_state = 2 ;
end
else
begin
next_state = 1 ;
end
temp_count = count - 1 ;
end
2 :
begin
output_xhdl0 = 1'b0 ;
if (trigger == 1'b0)
begin
next_state = 0 ;
end
else
begin
next_state = 2 ;
end
end
endcase
end
endmodule
module matmult (Ax, Ay, Az, m11, m12, m13, m21, m22, m23, m31, m32, m33, Cx, Cy, Cz, clk);
input[16 - 1:0] Ax;
input[16 - 1:0] Ay;
input[16 - 1:0] Az;
input[16 - 1:0] m11;
input[16 - 1:0] m12;
input[16 - 1:0] m13;
input[16 - 1:0] m21;
input[16 - 1:0] m22;
input[16 - 1:0] m23;
input[16 - 1:0] m31;
input[16 - 1:0] m32;
input[16 - 1:0] m33;
output[16 - 1:0] Cx;
reg[16 - 1:0] Cx;
output[16 - 1:0] Cy;
reg[16 - 1:0] Cy;
output[16 - 1:0] Cz;
reg[16 - 1:0] Cz;
input clk;
reg[16 + 16 - 1:0] am11;
reg[16 + 16 - 1:0] am12;
reg[16 + 16 - 1:0] am13;
reg[16 + 16 - 1:0] am21;
reg[16 + 16 - 1:0] am22;
reg[16 + 16 - 1:0] am23;
reg[16 + 16 - 1:0] am31;
reg[16 + 16 - 1:0] am32;
reg[16 + 16 - 1:0] am33;
always @(posedge clk)
begin
am11 <= Ax * m11 ;
am12 <= Ay * m12 ;
am13 <= Az * m13 ;
am21 <= Ax * m21 ;
am22 <= Ay * m22 ;
am23 <= Az * m23 ;
am31 <= Ax * m31 ;
am32 <= Ay * m32 ;
am33 <= Az * m33 ;
// Cx <= (am11 + am12 + am13) (`widthA+`widthB-2 downto `widthB-1);
// Cy <= (am21 + am22 + am23) (`widthA+`widthB-2 downto `widthB-1);
// Cz <= (am31 + am32 + am33) (`widthA+`widthB-2 downto `widthB-1);
Cx <= (am11[16+16-2:16-1] + am12[16+16-2:16-1] + am13[16+16-2:16-1]) ;
Cy <= (am21[16+16-2:16-1] + am22[16+16-2:16-1] + am23[16+16-2:16-1]);
Cz <= (am31[16+16-2:16-1] + am32[16+16-2:16-1] + am33[16+16-2:16-1]) ;
end
endmodule
module rgconfigmemory (CfgAddr, CfgData, CfgData_Ready, want_CfgData, origx, origy, origz, m11, m12, m13, m21, m22, m23, m31, m32, m33, bkcolour, texinfo, globalreset, clk);
input[3:0] CfgAddr;
input[27:0] CfgData;
input CfgData_Ready;
output want_CfgData;
reg want_CfgData;
output[27:0] origx;
reg[27:0] origx;
output[27:0] origy;
reg[27:0] origy;
output[27:0] origz;
reg[27:0] origz;
output[15:0] m11;
reg[15:0] m11;
output[15:0] m12;
reg[15:0] m12;
output[15:0] m13;
reg[15:0] m13;
output[15:0] m21;
reg[15:0] m21;
output[15:0] m22;
reg[15:0] m22;
output[15:0] m23;
reg[15:0] m23;
output[15:0] m31;
reg[15:0] m31;
output[15:0] m32;
reg[15:0] m32;
output[15:0] m33;
reg[15:0] m33;
output[20:0] bkcolour;
reg[20:0] bkcolour;
output[20:0] texinfo;
wire[20:0] texinfo;
input globalreset;
input clk;
reg state;
reg next_state;
wire we;
reg[27:0] temp_origx;
reg[27:0] temp_origy;
reg[27:0] temp_origz;
reg[15:0] temp_m11;
reg[15:0] temp_m12;
reg[15:0] temp_m13;
reg[15:0] temp_m21;
reg[15:0] temp_m22;
reg[15:0] temp_m23;
reg[15:0] temp_m31;
reg[15:0] temp_m32;
reg[15:0] temp_m33;
reg[20:0] temp_bkcolour;
// <<X-HDL>> Can't find translated component 'spram'. Module name may not match
spram21x4 spraminst(we, texinfo, CfgData[20:0], clk);
assign we = ((CfgData_Ready == 1'b1) & (CfgAddr == 4'b1110)) ? 1'b1 : 1'b0 ;
always @(posedge clk or posedge globalreset)
begin
if (globalreset == 1'b1)
begin
state <= 0 ;
origx <= 0;
origy <= 0;
origz <= 0;
m11 <= 1;
m12 <= 0;
m13 <= 0;
m21 <= 0;
m22 <= 1;
m23 <= 0;
m31 <= 0;
m32 <= 0;
m33 <= 1;
bkcolour <= 0;
end
else
begin
state <= next_state ;
origx <= temp_origx;
origy <= temp_origy;
origz <= temp_origz;
m11 <= temp_m11;
m12 <= temp_m12;
m13 <= temp_m13;
m21 <= temp_m21;
m22 <= temp_m22;
m23 <= temp_m23;
m31 <= temp_m31;
m32 <= temp_m32;
m33 <= temp_m33;
bkcolour <= bkcolour;
end
end
always @(state or CfgData_Ready)
begin
case (state)
0 :
begin
want_CfgData = 1'b1 ;
if (CfgData_Ready == 1'b1)
begin
next_state = 1 ;
end
else
begin
next_state = 0 ;
end
if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0001))
begin
temp_origx = CfgData ;
end
else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0010))
begin
temp_origy = CfgData ;
end
else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0011))
begin
temp_origz = CfgData ;
end
else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0100))
begin
temp_m11 = CfgData[15:0] ;
end
else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0101))
begin
temp_m12 = CfgData[15:0] ;
end
else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0110))
begin
temp_m13 = CfgData[15:0] ;
end
else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b0111))
begin
temp_m21 = CfgData[15:0] ;
end
else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1000))
begin
temp_m22 = CfgData[15:0] ;
end
else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1001))
begin
temp_m23 = CfgData[15:0] ;
end
else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1010))
begin
temp_m31 = CfgData[15:0] ;
end
else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1011))
begin
temp_m32 = CfgData[15:0] ;
end
else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1100))
begin
temp_m33 = CfgData[15:0] ;
end
else if ((CfgData_Ready == 1'b1) && (CfgAddr == 4'b1101))
begin
temp_bkcolour = CfgData[20:0] ;
end
end
1 :
begin
want_CfgData = 1'b0 ;
if (CfgData_Ready == 1'b0)
begin
next_state = 0 ;
end
else
begin
next_state = 1 ;
end
end
endcase
end
endmodule
module spram21x4 (we, dataout, datain, clk);
input we;
output[21 - 1:0] dataout;
wire[21 - 1:0] dataout;
input[21 - 1:0] datain;
input clk;
reg[21 - 1:0] mem1;
reg[21 - 1:0] mem2;
assign dataout = mem2 ;
always @(posedge clk or posedge we)
begin
if (we == 1'b1)
begin
mem1 <= datain;
mem2 <= mem1;
end
else
begin
mem1 <= mem1;
mem2 <= mem2;
end
end
endmodule
module rgsramcontroller (want_addr, addr_ready, addrin, want_data, data_ready, datain, want_read, read_ready, dataout, dirReady, wantDir, sramdatal, addr, wantwriteback, writebackack, writebackdata, writebackaddr, fbdata, fbnextscanline, fbdatavalid, fbpage, shadedata, triID, wantshadedata, shadedataready, texeladdr, texel, wanttexel, texelready, tm3_sram_data_in, tm3_sram_data_out, tm3_sram_addr, tm3_sram_we, tm3_sram_oe, tm3_sram_adsp, globalreset, clk);
output want_addr;
reg want_addr;
input addr_ready;
input[17:0] addrin;
output want_data;
reg want_data;
input data_ready;
input[63:0] datain;
input want_read;
output read_ready;
reg read_ready;
output[63:0] dataout;
wire[63:0] dataout;
output dirReady;
reg dirReady;
input wantDir;
output[47:0] sramdatal;
reg[47:0] sramdatal;
output[14:0] addr;
wire[14:0] addr;
input wantwriteback;
output writebackack;
reg writebackack;
input[63:0] writebackdata;
input[17:0] writebackaddr;
output[63:0] fbdata;
reg[63:0] fbdata;
input fbnextscanline;
output fbdatavalid;
reg fbdatavalid;
input fbpage;
output[63:0] shadedata;
wire[63:0] shadedata;
input[15:0] triID;
input wantshadedata;
output shadedataready;
reg shadedataready;
input[17:0] texeladdr;
output[63:0] texel;
wire[63:0] texel;
input wanttexel;
output texelready;
reg texelready;
input[63:0] tm3_sram_data_in;
wire[63:0] tm3_sram_data_in;
output[63:0] tm3_sram_data_out;
wire[63:0] tm3_sram_data_out;
reg[63:0] tm3_sram_data_xhdl0;
output[18:0] tm3_sram_addr;
reg[18:0] tm3_sram_addr;
output[7:0] tm3_sram_we;
reg[7:0] tm3_sram_we;
output[1:0] tm3_sram_oe;
reg[1:0] tm3_sram_oe;
output tm3_sram_adsp;
reg tm3_sram_adsp;
input globalreset;
input clk;
reg[3:0] state;
reg[3:0] next_state;
reg[17:0] waddress;
reg[14:0] faddress;
reg[6:0] fcount;
reg fbdatavalidl;
reg[17:0] temp_waddress;
reg[14:0] temp_faddress;
reg[6:0] temp_fcount;
reg temp_fbdatavalidl;
reg temp_texelready;
reg temp_shadedataready;
assign tm3_sram_data_out = tm3_sram_data_xhdl0;
assign dataout = tm3_sram_data_in ;
assign addr = tm3_sram_data_in[62:48] ;
assign shadedata = tm3_sram_data_in ;
assign texel = tm3_sram_data_in ;
always @(posedge clk or posedge globalreset)
begin
if (globalreset == 1'b1)
begin
state <= 0 ;
waddress <= 0;
faddress <= 0;
fcount <= 7'b1101011 ;
fbdatavalid <= 1'b0 ;
fbdatavalidl <= 1'b0 ;
shadedataready <= 1'b0 ;
texelready <= 1'b0 ;
sramdatal <= 0;
fbdata <= 0;
end
else
begin
state <= next_state ;
sramdatal <= tm3_sram_data_in[47:0] ;
fbdata <= tm3_sram_data_in ;
fbdatavalid <= fbdatavalidl ;
fbdatavalidl <= temp_fbdatavalidl;
texelready <= temp_texelready;
shadedataready <= temp_shadedataready;
fcount <= temp_fcount;
faddress <= temp_faddress;
waddress <= temp_waddress;
end
end
always @(state or addr_ready or data_ready or waddress or datain or wantDir or
want_read or wantwriteback or writebackdata or writebackaddr or
fcount or fbpage or faddress or fbnextscanline or triID or wantshadedata or
wanttexel or texeladdr)
begin
case (state)
0 :
begin
tm3_sram_we = 8'b11111111 ;
tm3_sram_oe = 2'b01 ;
tm3_sram_adsp = 1'b0 ;
tm3_sram_data_xhdl0 = 0;
tm3_sram_addr = {1'b0, waddress} ;
want_addr = 1'b1 ;
want_data = 1'b1 ;
read_ready = 1'b1 ;
dirReady = 1'b0 ;
writebackack = 1'b0 ;
if (addr_ready == 1'b1)
begin
next_state = 1 ;
end
else if (want_read == 1'b1)
begin
next_state = 2 ;
end
else if (data_ready == 1'b1)
begin
next_state = 3 ;
end
else if (wantDir == 1'b1)
begin
next_state = 5 ;
end
else if (wantwriteback == 1'b1)
begin
next_state = 6 ;
end
else if (wantshadedata == 1'b1)
begin
next_state = 9 ;
end
else if (wanttexel == 1'b1)
begin
next_state = 10 ;
end
else if (fcount != 0)
begin
next_state = 7 ;
end
else if (fbnextscanline == 1'b1)
begin
next_state = 8 ;
end
else
begin
next_state = 0 ;
end
temp_fbdatavalidl = 1'b0 ;
temp_shadedataready = 1'b0 ;
temp_texelready = 1'b0 ;
if (addr_ready == 1'b1)
begin
temp_waddress = addrin ;
end
end
1 :
begin
tm3_sram_we = 8'b11111111 ;
tm3_sram_oe = 2'b01 ;
tm3_sram_adsp = 1'b0 ;
tm3_sram_data_xhdl0 = 0;
tm3_sram_addr = {1'b0, waddress} ;
want_data = 1'b1 ;
read_ready = 1'b1 ;
dirReady = 1'b0 ;
writebackack = 1'b0 ;
want_addr = 1'b0 ;
if (addr_ready == 1'b0)
begin
next_state = 0 ;
end
else
begin
next_state = 1 ;
end
end
2 :
begin
tm3_sram_we = 8'b11111111 ;
tm3_sram_oe = 2'b01 ;
tm3_sram_adsp = 1'b0 ;
tm3_sram_data_xhdl0 = 0;
tm3_sram_addr = {1'b0, waddress} ;
want_addr = 1'b1 ;
want_data = 1'b1 ;
dirReady = 1'b0 ;
writebackack = 1'b0 ;
read_ready = 1'b0 ;
if (want_read == 1'b0)
begin
next_state = 0 ;
end
else
begin
next_state = 2 ;
end
temp_fbdatavalidl = 1'b0 ;
temp_shadedataready = 1'b0 ;
temp_texelready = 1'b0 ;
if (want_read == 1'b0)
begin
temp_waddress = waddress + 1 ;
end
end
3 :
begin
tm3_sram_addr = {1'b0, waddress} ;
want_addr = 1'b1 ;
read_ready = 1'b1 ;
dirReady = 1'b0 ;
writebackack = 1'b0 ;
tm3_sram_data_xhdl0 = datain ;
tm3_sram_we = 8'b00000000 ;
tm3_sram_oe = 2'b11 ;
tm3_sram_adsp = 1'b0 ;
want_data = 1'b0 ;
next_state = 4 ;
temp_fbdatavalidl = 1'b0 ;
temp_shadedataready = 1'b0 ;
temp_texelready = 1'b0 ;
temp_waddress = waddress + 1 ;
end
4 :
begin
tm3_sram_we = 8'b11111111 ;
tm3_sram_oe = 2'b01 ;
tm3_sram_adsp = 1'b0 ;
tm3_sram_data_xhdl0 = 0;
tm3_sram_addr = {1'b0, waddress} ;
want_addr = 1'b1 ;
read_ready = 1'b1 ;
dirReady = 1'b0 ;
writebackack = 1'b0 ;
if (data_ready == 1'b0)
begin
next_state = 0 ;
end
else
begin
next_state = 4 ;
end
want_data = 1'b0 ;
end
5 :
begin
tm3_sram_we = 8'b11111111 ;
tm3_sram_oe = 2'b01 ;
tm3_sram_adsp = 1'b0 ;
tm3_sram_data_xhdl0 = 0;
tm3_sram_addr = {1'b0, waddress} ;
want_addr = 1'b1 ;
want_data = 1'b1 ;
read_ready = 1'b1 ;
writebackack = 1'b0 ;
dirReady = 1'b1 ;
if (wantDir == 1'b0)
begin
next_state = 0 ;
end
else
begin
next_state = 5 ;
end
temp_fbdatavalidl = 1'b0 ;
temp_shadedataready = 1'b0 ;
temp_texelready = 1'b0 ;
if (wantDir == 1'b0)
begin
temp_waddress = waddress + 1 ;
end
end
6 :
begin
want_addr = 1'b1 ;
want_data = 1'b1 ;
read_ready = 1'b1 ;
dirReady = 1'b0 ;
tm3_sram_data_xhdl0 = writebackdata ;
tm3_sram_we = 8'b00000000 ;
tm3_sram_oe = 2'b11 ;
tm3_sram_adsp = 1'b0 ;
tm3_sram_addr = {1'b0, writebackaddr} ;
writebackack = 1'b1 ;
next_state = 0 ;
end
7 :
begin
tm3_sram_we = 8'b11111111 ;
tm3_sram_oe = 2'b01 ;
tm3_sram_adsp = 1'b0 ;
tm3_sram_data_xhdl0 = 0;
want_addr = 1'b1 ;
want_data = 1'b1 ;
read_ready = 1'b1 ;
dirReady = 1'b0 ;
writebackack = 1'b0 ;
tm3_sram_addr = {3'b011, fbpage, faddress} ;
if ((fcount == 1) | (addr_ready == 1'b1) | (want_read == 1'b1) | (data_ready == 1'b1) | (wantDir == 1'b1) | (wantwriteback == 1'b1))
begin
next_state = 0 ;
end
else
begin
next_state = 7 ;
end
temp_shadedataready = 1'b0 ;
temp_texelready = 1'b0 ;
temp_fbdatavalidl = 1'b1 ;
if (fcount != 0)
begin
temp_faddress = faddress + 1 ;
temp_fcount = fcount - 1 ;
end
end
8 :
begin
tm3_sram_we = 8'b11111111 ;
tm3_sram_oe = 2'b01 ;
tm3_sram_adsp = 1'b0 ;
tm3_sram_data_xhdl0 = 0;
tm3_sram_addr = {1'b0, waddress} ;
want_addr = 1'b1 ;
want_data = 1'b1 ;
read_ready = 1'b1 ;
dirReady = 1'b0 ;
writebackack = 1'b0 ;
next_state = 7 ;
temp_fbdatavalidl = 1'b0 ;
temp_shadedataready = 1'b0 ;
temp_texelready = 1'b0 ;
temp_fcount = 7'b1101011 ;
if (faddress == 25680)
begin
temp_faddress = 0;
end
end
9 :
begin
tm3_sram_we = 8'b11111111 ;
tm3_sram_oe = 2'b01 ;
tm3_sram_adsp = 1'b0 ;
tm3_sram_data_xhdl0 = 0;
want_addr = 1'b1 ;
want_data = 1'b1 ;
read_ready = 1'b1 ;
dirReady = 1'b0 ;
writebackack = 1'b0 ;
tm3_sram_addr = {3'b010, triID} ;
next_state = 0 ;
temp_fbdatavalidl = 1'b0 ;
temp_texelready = 1'b0 ;
temp_shadedataready = 1'b1 ;
end
10 :
begin
tm3_sram_we = 8'b11111111 ;
tm3_sram_oe = 2'b01 ;
tm3_sram_adsp = 1'b0 ;
tm3_sram_data_xhdl0 = 0;
want_addr = 1'b1 ;
want_data = 1'b1 ;
read_ready = 1'b1 ;
dirReady = 1'b0 ;
writebackack = 1'b0 ;
tm3_sram_addr = {1'b0, texeladdr} ;
next_state = 0 ;
temp_fbdatavalidl = 1'b0 ;
temp_shadedataready = 1'b0 ;
temp_texelready = 1'b1 ;
end
endcase
end
endmodule
module raysend (as, ack, addr, dir, origx, origy, origz, rgData, rgAddr, rgWE, rgAddrValid, rgDone, globalreset, clk, statepeek);
input as;
output ack;
reg ack;
input[3:0] addr;
input[47:0] dir;
input[27:0] origx;
input[27:0] origy;
input[27:0] origz;
output[31:0] rgData;
reg[31:0] rgData;
output[3:0] rgAddr;
reg[3:0] rgAddr;
output[2:0] rgWE;
reg[2:0] rgWE;
output rgAddrValid;
reg rgAddrValid;
input rgDone;
input globalreset;
input clk;
output[2:0] statepeek;
reg[2:0] statepeek;
reg[3:0] state;
reg[3:0] next_state;
reg[31:0] temp_rgData;
reg[2:0] temp_rgWE;
reg temp_rgAddrValid;
reg temp_ack;
reg[3:0] temp_rgAddr;
always @(posedge clk or posedge globalreset)
begin
if (globalreset == 1'b1)
begin
state <= 0 ;
ack <= 1'b0 ;
rgWE <= 3'b000 ;
rgData <= 0;
rgAddrValid <= 1'b0 ;
rgAddr <= 0;
end
else
begin
state <= next_state ;
rgData <= temp_rgData;
rgWE <= temp_rgWE;
rgAddrValid <= temp_rgAddrValid;
ack <= temp_ack;
rgAddr <= temp_rgAddr;
end
end
always @(state or ack or as or rgDone)
begin
case (state)
0 :
begin
if ((as == 1'b1) & (ack == 1'b0))
begin
next_state = 1 ;
end
else
begin
next_state = 0 ;
end
statepeek = 3'b001 ;
if ((as == 1'b1) & (ack == 1'b0))
begin
temp_rgData = {4'b0000, origx} ;
temp_rgWE = 3'b001 ;
temp_rgAddrValid = 1'b1 ;
temp_rgAddr = addr ;
end
if (as == 1'b0 & ack == 1'b1)
begin
temp_ack = 1'b0 ;
end
end
1 :
begin
if (rgDone == 1'b1)
begin
next_state = 6 ;
end
else
begin
next_state = 1 ;
end
statepeek = 3'b010 ;
if (rgDone == 1'b1)
begin
temp_rgAddrValid = 1'b0 ;
end
end
2 :
begin
if (rgDone == 1'b1)
begin
next_state = 7 ;
end
else
begin
next_state = 2 ;
end
statepeek = 3'b011 ;
if (rgDone == 1'b1)
begin
temp_rgAddrValid = 1'b0 ;
end
end
3 :
begin
if (rgDone == 1'b1)
begin
next_state = 8 ;
end
else
begin
next_state = 3 ;
end
statepeek = 3'b100 ;
if (rgDone == 1'b1)
begin
temp_rgAddrValid = 1'b0 ;
end
end
4 :
begin
if (rgDone == 1'b1)
begin
next_state = 9 ;
end
else
begin
next_state = 4 ;
end
statepeek = 3'b101 ;
if (rgDone == 1'b1)
begin
temp_rgAddrValid = 1'b0 ;
end
end
5 :
begin
if (rgDone == 1'b1)
begin
next_state = 0 ;
end
else
begin
next_state = 5 ;
end
statepeek = 3'b110 ;
temp_ack = 1'b1 ;
if (rgDone == 1'b1)
begin
temp_rgAddrValid = 1'b0 ;
end
end
6 :
begin
next_state = 2 ;
temp_rgData = {4'b0000, origy} ;
temp_rgWE = 3'b010 ;
temp_rgAddrValid = 1'b1 ;
end
7 :
begin
next_state = 3 ;
temp_rgData = {4'b0000, origz} ;
temp_rgWE = 3'b011 ;
temp_rgAddrValid = 1'b1 ;
end
8 :
begin
next_state = 4 ;
temp_rgData = {dir[31:16], dir[47:32]} ;
temp_rgWE = 3'b100 ;
temp_rgAddrValid = 1'b1 ;
end
9 :
begin
next_state = 5 ;
temp_rgData = {16'b0000000000000000, dir[15:0]} ;
temp_rgWE = 3'b101 ;
temp_rgAddrValid = 1'b1 ;
end
endcase
end
endmodule
module raygencont (go, initcount, busyout, cycles, nextaddr, nas0, nas1, page, dirReady, wantDir, dirIn, addrIn, as, addr, ack, dir, raygroup0, raygroupvalid0, busy0, raygroup1, raygroupvalid1, busy1, globalreset, clk, statepeek);
input go;
input[14:0] initcount;
output busyout;
wire busyout;
reg temp_busyout;
output[30:0] cycles;
reg[30:0] cycles;
output[17:0] nextaddr;
wire[17:0] nextaddr;
output nas0;
wire nas0;
reg temp_nas0;
output nas1;
wire nas1;
reg temp_nas1;
input page;
input dirReady;
output wantDir;
reg wantDir;
input[47:0] dirIn;
input[14:0] addrIn;
output as;
reg as;
output[3:0] addr;
reg[3:0] addr;
input ack;
output[47:0] dir;
reg[47:0] dir;
output[1:0] raygroup0;
wire[1:0] raygroup0;
output raygroupvalid0;
reg raygroupvalid0;
input busy0;
output[1:0] raygroup1;
wire[1:0] raygroup1;
output raygroupvalid1;
reg raygroupvalid1;
input busy1;
input globalreset;
input clk;
output[2:0] statepeek;
reg[2:0] statepeek;
reg[2:0] state;
reg[2:0] next_state;
reg[14:0] count;
reg first;
reg[17:0] destaddr;
wire[1:0] busy;
reg[1:0] loaded;
reg[1:0] groupID;
reg active;
reg[47:0] temp_dir;
reg[30:0] temp_cycles;
reg[1:0] temp_addr;
reg[1:0] temp_loaded;
reg[1:0] temp_groupID;
reg[14:0] temp_count;
reg temp_active;
reg temp_raygroupvalid1;
reg temp_raygroupvalid0;
assign busy = {busy1, busy0} ;
always @(posedge clk or posedge globalreset)
begin
if (globalreset == 1'b1)
begin
state <= 0 ;
cycles <= 0;
dir <= 0;
addr[1:0] <= 2'b00 ;
groupID <= 2'b00 ;
count <= 0;
first <= 1'b0 ;
destaddr <= 0;
raygroupvalid0 <= 1'b0 ;
raygroupvalid1 <= 1'b0 ;
loaded <= 2'b00 ;
active <= 1'b0 ;
end
else
begin
addr[3:2] <= (active == 1'b0) ? {1'b0, groupID[0]} : {1'b1, groupID[1]} ;
state <= next_state ;
dir <= temp_dir;
cycles <= temp_cycles;
addr <= temp_addr;
loaded <= temp_loaded;
groupID <= temp_groupID;
count <= temp_count;
active <= temp_active;
raygroupvalid0 <= temp_raygroupvalid0;
raygroupvalid1 <= temp_raygroupvalid1;
end
end
assign raygroup0 = {1'b0, groupID[0]} ;
assign raygroup1 = {1'b1, groupID[1]} ;
assign nextaddr = {2'b11, page, addrIn} ;
assign busyout = temp_busyout;
assign nas0 = temp_nas0;
assign nas1 = temp_nas1;
always @(state or go or ack or busy or dirReady or addr or count or loaded)
begin
case (state)
0 :
begin
as = 1'b0 ;
wantDir = 1'b0 ;
if (go == 1'b1)
begin
next_state = 1 ;
end
else
begin
next_state = 0 ;
end
statepeek = 3'b001 ;
temp_busyout = 1'b0;
temp_nas0 = 1'b0;
temp_nas1 = 1'b0;
if (go == 1'b1)
begin
temp_cycles = 0;
end
temp_addr[1:0] = 2'b00 ;
temp_loaded = 2'b00 ;
temp_groupID = 2'b00 ;
temp_count = initcount ;
temp_active = 1'b0 ;
end
1 :
begin
as = dirReady ;
wantDir = 1'b1 ;
if (dirReady == 1'b1)
begin
next_state = 2 ;
end
else
begin
next_state = 1 ;
end
statepeek = 3'b010 ;
temp_busyout = 1'b1;
if (addr[1:0] == 2'b00 & dirReady == 1'b1 & active == 1'b0)
begin
temp_nas0 = 1'b1;
temp_nas1 = 1'b1;
end
temp_dir = dirIn ;
if (dirReady == 1'b1 & addr[1:0] == 2'b10)
begin
if (active == 1'b0)
begin
temp_loaded[0] = 1'b1 ;
end
else
begin
temp_loaded[1] = 1'b1 ;
end
end
temp_cycles = cycles + 1 ;
end
2 :
begin
wantDir = 1'b0 ;
as = 1'b1 ;
if ((ack == 1'b1) & (addr[1:0] != 2'b10))
begin
next_state = 1 ;
end
else if (ack == 1'b1)
begin
if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0)
begin
next_state = 3 ;
end
else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0)
begin
next_state = 4 ;
end
else if (loaded != 2'b11)
begin
next_state = 1 ;
end
else
begin
next_state = 2 ;
end
end
else
begin
next_state = 2 ;
end
statepeek = 3'b011 ;
temp_busyout = 1'b1;
temp_nas0 = 1'b0;
temp_nas1 = 1'b0;
if ((ack == 1'b1) & (addr[1:0] != 2'b10))
begin
temp_addr[1:0] = addr[1:0] + 2'b01 ;
end
else if ((ack == 1'b1) & addr[1:0] == 2'b10)
begin
if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0)
begin
temp_raygroupvalid0 = 1'b1 ;
end
else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0)
begin
temp_raygroupvalid1 = 1'b1 ;
end
else if ((loaded[0]) == 1'b0)
begin
temp_active = 1'b0 ;
temp_addr[1:0] = 2'b00 ;
end
else if ((loaded[1]) == 1'b0)
begin
temp_active = 1'b1 ;
temp_addr[1:0] = 2'b00 ;
end
end
temp_cycles = cycles + 1 ;
end
4 :
begin
if ((busy[1]) == 1'b0)
begin
next_state = 4 ;
end
else if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0)
begin
next_state = 3 ;
end
else if (count > 0)
begin
next_state = 1 ;
end
else
begin
next_state = 0 ;
end
statepeek = 3'b101 ;
temp_busyout = 1'b1;
temp_nas0 = 1'b0;
temp_nas1 = 1'b0;
if ((busy[1]) == 1'b1)
begin
temp_groupID[1] = ~groupID[1] ;
temp_raygroupvalid1 = 1'b0 ;
temp_count = count - 1 ;
if ((loaded[0]) == 1'b1 & (busy[0]) == 1'b0)
begin
temp_raygroupvalid0 = 1'b1 ;
end
else if ((loaded[0]) == 1'b0)
begin
temp_active = 1'b0 ;
end
else
begin
temp_active = 1'b1 ;
end
end
temp_loaded[1] = 1'b0 ;
temp_addr[1:0] = 2'b00 ;
temp_cycles = cycles + 1 ;
end
3 :
begin
if ((busy[0]) == 1'b0)
begin
next_state = 3 ;
end
else if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0)
begin
next_state = 4 ;
end
else if (count > 0)
begin
next_state = 1 ;
end
else
begin
next_state = 0 ;
end
statepeek = 3'b100 ;
temp_busyout = 1'b1;
temp_nas0 = 1'b0;
temp_nas1 = 1'b0;
if ((busy[0]) == 1'b1)
begin
temp_groupID[0] = ~groupID[0] ;
temp_raygroupvalid0 = 1'b0 ;
temp_count = count - 1 ;
if ((loaded[1]) == 1'b1 & (busy[1]) == 1'b0)
begin
temp_raygroupvalid1 = 1'b1 ;
end
else if ((loaded[1]) == 1'b0)
begin
temp_active = 1'b1 ;
end
else
begin
temp_active = 1'b0 ;
end
end
temp_loaded[0] = 1'b0 ;
temp_addr[1:0] = 2'b00 ;
temp_cycles = cycles + 1 ;
end
endcase
end
endmodule
module resultrecieve (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, rgResultData, rgResultReady, rgResultSource, globalreset, clk);
output valid01;
reg valid01;
output valid10;
reg valid10;
output[15:0] id01a;
reg[15:0] id01a;
output[15:0] id01b;
reg[15:0] id01b;
output[15:0] id01c;
reg[15:0] id01c;
output[15:0] id10a;
reg[15:0] id10a;
output[15:0] id10b;
reg[15:0] id10b;
output[15:0] id10c;
reg[15:0] id10c;
output hit01a;
reg hit01a;
output hit01b;
reg hit01b;
output hit01c;
reg hit01c;
output hit10a;
reg hit10a;
output hit10b;
reg hit10b;
output hit10c;
reg hit10c;
output[7:0] u01a;
reg[7:0] u01a;
output[7:0] u01b;
reg[7:0] u01b;
output[7:0] u01c;
reg[7:0] u01c;
output[7:0] v01a;
reg[7:0] v01a;
output[7:0] v01b;
reg[7:0] v01b;
output[7:0] v01c;
reg[7:0] v01c;
output[7:0] u10a;
reg[7:0] u10a;
output[7:0] u10b;
reg[7:0] u10b;
output[7:0] u10c;
reg[7:0] u10c;
output[7:0] v10a;
reg[7:0] v10a;
output[7:0] v10b;
reg[7:0] v10b;
output[7:0] v10c;
reg[7:0] v10c;
input[31:0] rgResultData;
input rgResultReady;
input[1:0] rgResultSource;
input globalreset;
input clk;
reg temp_valid01;
reg temp_valid10;
reg[15:0] temp_id01a;
reg[15:0] temp_id01b;
reg[15:0] temp_id01c;
reg[15:0] temp_id10a;
reg[15:0] temp_id10b;
reg[15:0] temp_id10c;
reg temp_hit01a;
reg temp_hit01b;
reg temp_hit01c;
reg temp_hit10a;
reg temp_hit10b;
reg temp_hit10c;
reg[7:0] temp_u01a;
reg[7:0] temp_u01b;
reg[7:0] temp_u01c;
reg[7:0] temp_v01a;
reg[7:0] temp_v01b;
reg[7:0] temp_v01c;
reg[7:0] temp_u10a;
reg[7:0] temp_u10b;
reg[7:0] temp_u10c;
reg[7:0] temp_v10a;
reg[7:0] temp_v10b;
reg[7:0] temp_v10c;
reg[2:0] state;
reg[2:0] next_state;
always @(posedge clk or posedge globalreset)
begin
if (globalreset == 1'b1)
begin
state <= 0 ;
valid01 <= 1'b0 ;
valid10 <= 1'b0 ;
hit01a <= 1'b0 ;
hit01b <= 1'b0 ;
hit01c <= 1'b0 ;
hit10a <= 1'b0 ;
hit10b <= 1'b0 ;
hit10c <= 1'b0 ;
id01a <= 0;
id01b <= 0;
id01c <= 0;
id10a <= 0;
id10b <= 0;
id10c <= 0;
u01a <= 0;
u01b <= 0;
u01c <= 0;
v01a <= 0;
v01b <= 0;
v01c <= 0;
u10a <= 0;
u10b <= 0;
u10c <= 0;
v10a <= 0;
v10b <= 0;
v10c <= 0;
end
else
begin
state <= next_state ;
valid01 <= temp_valid01;
valid10 <= temp_valid10;
id01a <= temp_id01a;
id01b <= temp_id01b;
id01c <= temp_id01c;
hit01a <= temp_hit01a;
hit01b <= temp_hit01b;
hit01c <= temp_hit01c;
u01a <= temp_u01a;
u01b <= temp_u01b;
u01c <= temp_u01c;
u10a <= temp_u10a;
u10b <= temp_u10b;
u10c <= temp_u10c;
v01a <= temp_v01a;
v01b <= temp_v01b;
v01c <= temp_v01c;
v10a <= temp_v10a;
v10b <= temp_v10b;
v10c <= temp_v10c;
hit10a <= temp_hit10a;
hit10b <= temp_hit10b;
hit10c <= temp_hit10c;
end
end
always @(state or rgResultReady or rgResultSource)
begin
case (state)
0 :
begin
if (rgResultReady == 1'b1 & rgResultSource == 2'b01)
begin
next_state = 1 ;
end
else if (rgResultReady == 1'b1 & rgResultSource == 2'b10)
begin
next_state = 4 ;
end
else
begin
next_state = 0 ;
end
temp_valid01 = 1'b0 ;
temp_valid10 = 1'b0 ;
if (rgResultReady == 1'b1 & rgResultSource == 2'b01)
begin
temp_id01a = rgResultData[31:16] ;
temp_id01b = rgResultData[15:0] ;
end
else if (rgResultReady == 1'b1 & rgResultSource == 2'b10)
begin
temp_id10a = rgResultData[31:16] ;
temp_id10b = rgResultData[15:0] ;
end
end
1 :
begin
next_state = 2 ;
temp_valid01 = 1'b0 ;
temp_valid10 = 1'b0 ;
temp_id01c = rgResultData[15:0] ;
temp_hit01a = rgResultData[18] ;
temp_hit01b = rgResultData[17] ;
temp_hit01c = rgResultData[16] ;
end
2 :
begin
next_state = 3 ;
temp_valid01 = 1'b0 ;
temp_valid10 = 1'b0 ;
temp_u01a = rgResultData[23:16] ;
temp_u01b = rgResultData[15:8] ;
temp_u01c = rgResultData[7:0] ;
end
3 :
begin
next_state = 0 ;
temp_valid10 = 1'b0 ;
temp_v01a = rgResultData[23:16] ;
temp_v01b = rgResultData[15:8] ;
temp_v01c = rgResultData[7:0] ;
temp_valid01 = 1'b1 ;
end
4 :
begin
next_state = 5 ;
temp_valid01 = 1'b0 ;
temp_valid10 = 1'b0 ;
temp_id10c = rgResultData[15:0] ;
temp_hit10a = rgResultData[18] ;
temp_hit10b = rgResultData[17] ;
temp_hit10c = rgResultData[16] ;
end
5 :
begin
next_state = 6 ;
temp_valid01 = 1'b0 ;
temp_valid10 = 1'b0 ;
temp_u10a = rgResultData[23:16] ;
temp_u10b = rgResultData[15:8] ;
temp_u10c = rgResultData[7:0] ;
end
6 :
begin
next_state = 0 ;
temp_valid01 = 1'b0 ;
temp_v10a = rgResultData[23:16] ;
temp_v10b = rgResultData[15:8] ;
temp_v10c = rgResultData[7:0] ;
temp_valid10 = 1'b1 ;
end
endcase
end
endmodule
module resultwriter (valid01, valid10, id01a, id01b, id01c, id10a, id10b, id10c, hit01a, hit01b, hit01c, hit10a, hit10b, hit10c, u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, addr, as01, as10, bkcolour, shadedata, triID, wantshadedata, shadedataready, texinfo, texaddr, texeladdr, texel, wanttexel, texelready, dataout, addrout, write, ack, globalreset, clk);
input valid01;
input valid10;
input[15:0] id01a;
input[15:0] id01b;
input[15:0] id01c;
input[15:0] id10a;
input[15:0] id10b;
input[15:0] id10c;
input hit01a;
input hit01b;
input hit01c;
input hit10a;
input hit10b;
input hit10c;
input[7:0] u01a;
input[7:0] u01b;
input[7:0] u01c;
input[7:0] v01a;
input[7:0] v01b;
input[7:0] v01c;
input[7:0] u10a;
input[7:0] u10b;
input[7:0] u10c;
input[7:0] v10a;
input[7:0] v10b;
input[7:0] v10c;
input[17:0] addr;
input as01;
input as10;
input[20:0] bkcolour;
input[63:0] shadedata;
output[15:0] triID;
reg[15:0] triID;
output wantshadedata;
reg wantshadedata;
input shadedataready;
input[20:0] texinfo;
output[3:0] texaddr;
wire[3:0] texaddr;
output[17:0] texeladdr;
wire[17:0] texeladdr;
input[63:0] texel;
output wanttexel;
reg wanttexel;
input texelready;
output[63:0] dataout;
// PAJ see lower note wire[63:0] dataout;
reg[63:0] dataout;
output[17:0] addrout;
wire[17:0] addrout;
output write;
wire write;
reg temp_write;
input ack;
input globalreset;
input clk;
reg[3:0] state;
reg[3:0] next_state;
reg pending01;
reg pending10;
reg process01;
wire[17:0] addrout01;
wire[17:0] addrout10;
wire shiften01;
wire shiften10;
reg temp_shiften01;
reg temp_shiften10;
reg[20:0] shadedataa;
reg[20:0] shadedatab;
reg[20:0] shadedatac;
wire hita;
wire hitb;
wire hitc;
reg[2:0] selectuv;
wire[6:0] blr;
wire[6:0] blg;
wire[6:0] blb;
reg texmap;
reg lmenable;
wire[1:0] texelselect;
wire[6:0] texelr;
wire[6:0] texelg;
wire[6:0] texelb;
reg[20:0] texinfol;
reg temp_pending01;
reg temp_pending10;
reg temp_process01;
reg temp_texmap;
reg[20:0] temp_texinfol;
reg[20:0] temp_shadedataa;
reg[20:0] temp_shadedatab;
reg[20:0] temp_shadedatac;
col16to21 col16to21inst (texel, texelselect, texelr, texelg, texelb);
linearmap linearmapinst (blb, blg, texinfol[17:0], texeladdr, texelselect, texinfol[20:18], lmenable, clk);
bilinearintrp bilinearimp (u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, selectuv, shadedata[41:35], shadedata[62:56], shadedata[20:14], shadedata[34:28], shadedata[55:49], shadedata[13:7], shadedata[27:21], shadedata[48:42], shadedata[6:0], blr, blg, blb, clk);
fifo3 fifo3insta (addr, as01, addrout01, shiften01, globalreset, clk);
fifo3 fifo3instb (addr, as10, addrout10, shiften10, globalreset, clk);
assign hita = (hit01a & process01) | (hit10a & ~process01) ;
assign hitb = (hit01b & process01) | (hit10b & ~process01) ;
assign hitc = (hit01c & process01) | (hit10c & ~process01) ;
assign texaddr = shadedata[59:56] ;
assign shiften01 = temp_shiften01;
assign shiften10 = temp_shiften10;
assign write = temp_write;
always @(posedge clk or posedge globalreset)
begin
if (globalreset == 1'b1)
begin
state <= 0 ;
pending01 <= 1'b0 ;
pending10 <= 1'b0 ;
shadedataa <= 0;
shadedatab <= 0;
shadedatac <= 0;
process01 <= 1'b0 ;
texmap <= 1'b0 ;
texinfol <= 0;
end
else
begin
state <= next_state ;
process01 <= temp_process01;
pending01 <= temp_pending01;
pending10 <= temp_pending10;
texmap <= temp_texmap;
texinfol <= temp_texinfol;
shadedataa <= temp_shadedataa;
shadedatab <= temp_shadedatab;
shadedatac <= temp_shadedatac;
dataout <= {1'b0,
shadedataa[20],
shadedataa[19],
shadedataa[18],
shadedataa[17],
shadedataa[16],
shadedataa[15],
shadedataa[14],
shadedataa[13],
shadedataa[12],
shadedataa[11],
shadedataa[10],
shadedataa[9],
shadedataa[8],
shadedataa[7],
shadedataa[6],
shadedataa[5],
shadedataa[4],
shadedataa[3],
shadedataa[2],
shadedataa[1],
shadedataa[0],
shadedatab[20],
shadedatab[19],
shadedatab[18],
shadedatab[17],
shadedatab[16],
shadedatab[15],
shadedatab[14],
shadedatab[13],
shadedatab[12],
shadedatab[11],
shadedatab[10],
shadedatab[9],
shadedatab[8],
shadedatab[7],
shadedatab[6],
shadedatab[5],
shadedatab[4],
shadedatab[3],
shadedatab[2],
shadedatab[1],
shadedatab[0],
shadedatac[20],
shadedatac[19],
shadedatac[18],
shadedatac[17],
shadedatac[16],
shadedatac[15],
shadedatac[14],
shadedatac[13],
shadedatac[12],
shadedatac[11],
shadedatac[10],
shadedatac[9],
shadedatac[8],
shadedatac[7],
shadedatac[6],
shadedatac[5],
shadedatac[4],
shadedatac[3],
shadedatac[2],
shadedatac[1],
shadedatac[0]} ;
end
// end
// PAJ used to be assign, but weird error, so added as register assign dataout = {1'b0,
end
assign addrout = (process01 == 1'b1) ? addrout01 : addrout10 ;
always @(state or process01 or pending10 or ack or shadedataready or id01a or
id01b or id01c or id10a or id10b or id10c or selectuv or hita or
hitb or hitc or shadedata or pending01 or texmap or texelready)
begin
case (state)
0 :
begin
wantshadedata = 1'b0 ;
triID = 0;
selectuv = 0;
lmenable = 1'b0 ;
wanttexel = 1'b0 ;
if (pending01 == 1'b1 | pending10 == 1'b1)
begin
next_state = 2 ;
end
else
begin
next_state = 0 ;
end
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
temp_process01 = pending01 ;
temp_shiften01 = 1'b0;
temp_shiften10 = 1'b0;
temp_write = 1'b0;
end
2 :
begin
lmenable = 1'b0 ;
wanttexel = 1'b0 ;
wantshadedata = 1'b1 ;
selectuv[2] = ~process01 ;
selectuv[1:0] = 2'b00 ;
if (process01 == 1'b1)
begin
triID = id01a ;
end
else
begin
triID = id10a ;
end
if (shadedataready == 1'b1)
begin
if (hita == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01))
begin
next_state = 3 ;
end
else
begin
next_state = 4 ;
end
end
else
begin
next_state = 2 ;
end
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
if (hita == 1'b1)
begin
temp_shadedataa = shadedata[20:0] ;
temp_texmap = (~shadedata[63]) & shadedata[62] ;
end
else
begin
temp_shadedataa = bkcolour ;
end
temp_shiften01 = 1'b0;
temp_shiften10 = 1'b0;
temp_write = 1'b0;
end
3 :
begin
wantshadedata = 1'b0 ;
triID = 0;
lmenable = 1'b0 ;
wanttexel = 1'b0 ;
selectuv[2] = ~process01 ;
selectuv[1:0] = 2'b00 ;
next_state = 8 ;
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
temp_texinfol = texinfo ;
temp_shiften01 = 1'b0;
temp_shiften10 = 1'b0;
temp_write = 1'b0;
end
8 :
begin
wantshadedata = 1'b0 ;
triID = 0;
wanttexel = 1'b0 ;
selectuv[2] = ~process01 ;
selectuv[1:0] = 2'b00 ;
lmenable = 1'b1 ;
if (texmap == 1'b1)
begin
next_state = 11 ;
end
else
begin
next_state = 4 ;
end
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
temp_shadedataa[6:0] = blb ;
temp_shadedataa[13:7] = blg ;
temp_shadedataa[20:14] = blr ;
temp_shiften01 = 1'b0;
temp_shiften10 = 1'b0;
temp_write = 1'b0;
end
11 :
begin
wantshadedata = 1'b0 ;
triID = 0;
selectuv = 0;
lmenable = 1'b0 ;
wanttexel = 1'b1 ;
if (texelready == 1'b1)
begin
next_state = 4 ;
end
else
begin
next_state = 11 ;
end
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
temp_shadedataa[6:0] = texelb ;
temp_shadedataa[13:7] = texelg ;
temp_shadedataa[20:14] = texelr ;
temp_shiften01 = 1'b0;
temp_shiften10 = 1'b0;
temp_write = 1'b0;
end
12 :
begin
wantshadedata = 1'b0 ;
triID = 0;
selectuv = 0;
lmenable = 1'b0 ;
wanttexel = 1'b1 ;
if (texelready == 1'b1)
begin
next_state = 5 ;
end
else
begin
next_state = 12 ;
end
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
temp_shadedatab[6:0] = texelb ;
temp_shadedatab[13:7] = texelg ;
temp_shadedatab[20:14] = texelr ;
temp_shiften01 = 1'b0;
temp_shiften10 = 1'b0;
temp_write = 1'b0;
end
13 :
begin
wantshadedata = 1'b0 ;
triID = 0;
selectuv = 0;
lmenable = 1'b0 ;
wanttexel = 1'b1 ;
if (texelready == 1'b1)
begin
next_state = 1 ;
end
else
begin
next_state = 13 ;
end
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
temp_shadedatac[6:0] = texelb ;
temp_shadedatac[13:7] = texelg ;
temp_shadedatac[20:14] = texelr ;
end
6 :
begin
wantshadedata = 1'b0 ;
triID = 0;
lmenable = 1'b0 ;
wanttexel = 1'b0 ;
selectuv[2] = ~process01 ;
selectuv[1:0] = 2'b01 ;
next_state = 9 ;
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
temp_texinfol = texinfo ;
temp_shiften01 = 1'b0;
temp_shiften10 = 1'b0;
temp_write = 1'b0;
end
9 :
begin
wantshadedata = 1'b0 ;
triID = 0;
wanttexel = 1'b0 ;
selectuv[2] = ~process01 ;
selectuv[1:0] = 2'b01 ;
lmenable = 1'b1 ;
if (texmap == 1'b1)
begin
next_state = 12 ;
end
else
begin
next_state = 5 ;
end
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
temp_shadedatab[6:0] = blb ;
temp_shadedatab[13:7] = blg ;
temp_shadedatab[20:14] = blr ;
temp_shiften01 = 1'b0;
temp_shiften10 = 1'b0;
temp_write = 1'b0;
end
7 :
begin
wantshadedata = 1'b0 ;
triID = 0;
lmenable = 1'b0 ;
wanttexel = 1'b0 ;
selectuv[2] = ~process01 ;
selectuv[1:0] = 2'b10 ;
next_state = 10 ;
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
temp_texinfol = texinfo ;
temp_shiften01 = 1'b0;
temp_shiften10 = 1'b0;
temp_write = 1'b0;
end
10 :
begin
wantshadedata = 1'b0 ;
triID = 0;
wanttexel = 1'b0 ;
selectuv[2] = ~process01 ;
selectuv[1:0] = 2'b10 ;
if (texmap == 1'b1)
begin
next_state = 13 ;
end
else
begin
next_state = 1 ;
end
lmenable = 1'b1 ;
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
temp_shadedatac[6:0] = blb ;
temp_shadedatac[13:7] = blg ;
temp_shadedatac[20:14] = blr ;
temp_shiften01 = 1'b0;
temp_shiften10 = 1'b0;
temp_write = 1'b0;
end
4 :
begin
wantshadedata = 1'b0 ;
lmenable = 1'b0 ;
wanttexel = 1'b0 ;
selectuv[2] = ~process01 ;
selectuv[1:0] = 2'b01 ;
if (process01 == 1'b1)
begin
triID = id01b ;
end
else
begin
triID = id10b ;
end
if (shadedataready == 1'b1)
begin
if (hitb == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01))
begin
next_state = 6 ;
end
else
begin
next_state = 5 ;
end
end
else
begin
next_state = 4 ;
end
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
if (hitb == 1'b1)
begin
temp_shadedatab = shadedata[20:0] ;
temp_texmap = (~shadedata[63]) & shadedata[62] ;
end
else
begin
temp_shadedatab = bkcolour ;
end
temp_shiften01 = 1'b0;
temp_shiften10 = 1'b0;
temp_write = 1'b0;
end
5 :
begin
lmenable = 1'b0 ;
wanttexel = 1'b0 ;
wantshadedata = 1'b1 ;
selectuv[2] = ~process01 ;
selectuv[1:0] = 2'b10 ;
if (process01 == 1'b1)
begin
triID = id01c ;
end
else
begin
triID = id10c ;
end
if (shadedataready == 1'b1)
begin
if (hitc == 1'b1 & ((shadedata[63]) == 1'b1 | shadedata[63:62] == 2'b01))
begin
next_state = 7 ;
end
else
begin
next_state = 1 ;
end
end
else
begin
next_state = 5 ;
end
if (valid01 == 1'b1)
begin
temp_pending01 = 1'b1 ;
end
if (valid10 == 1'b1)
begin
temp_pending10 = 1'b1 ;
end
if (hitc == 1'b1)
begin
temp_shadedatac = shadedata[20:0] ;
temp_texmap = (~shadedata[63]) & shadedata[62] ;
end
else
begin
temp_shadedatac = bkcolour ;
end
temp_shiften01 = 1'b0;
temp_shiften10 = 1'b0;
temp_write = 1'b0;
end
1 :
begin
wantshadedata = 1'b0 ;
triID = 0;
selectuv = 0;
lmenable = 1'b0 ;
wanttexel = 1'b0 ;
if (ack == 1'b1)
begin
next_state = 0 ;
end
else
begin
next_state = 1 ;
end
if (ack == 1'b1 & process01 == 1'b1)
begin
temp_pending01 = 1'b0 ;
end
else if (ack == 1'b1 & process01 == 1'b0)
begin
temp_pending10 = 1'b0 ;
end
if (process01 == 1'b1 & ack == 1'b1)
begin
temp_shiften01 = 1'b1;
temp_shiften10 = 1'b1;
end
temp_write = 1'b1;
end
endcase
end
endmodule
//////////////////////////////////////////////////////////////////////////////////////////////
//
// Verilog file generated by X-HDL - Revision 3.2.38 Jan. 9, 2004
// Sun Feb 8 14:14:35 2004
//
// Input file : G:/jamieson/VERILOG_BENCHMARKS/RAYTRACE/col16to21.vhd
// Design name : col16to21
// Author :
// Company :
//
// Description :
//
//
//////////////////////////////////////////////////////////////////////////////////////////////
//
module col16to21 (dataline, texelselect, r, g, b);
input[63:0] dataline;
input[1:0] texelselect;
output[6:0] r;
wire[6:0] r;
output[6:0] g;
wire[6:0] g;
output[6:0] b;
wire[6:0] b;
reg[15:0] col16;
always @(dataline or texelselect)
begin
case (texelselect)
2'b00 :
begin
col16 = dataline[15:0] ;
end
2'b01 :
begin
col16 = dataline[31:16] ;
end
2'b10 :
begin
col16 = dataline[47:32] ;
end
2'b11 :
begin
col16 = dataline[63:48] ;
end
endcase
end
assign r = {col16[15:10], 1'b0} ;
assign g = {col16[9:5], 2'b00} ;
assign b = {col16[4:0], 2'b00} ;
endmodule
module linearmap (u, v, start, addr, texelselect, factor, enable, clk);
input[6:0] u;
input[6:0] v;
input[17:0] start;
output[17:0] addr;
reg[17:0] addr;
output[1:0] texelselect;
wire[1:0] texelselect;
input[2:0] factor;
input enable;
input clk;
reg[6:0] ul;
reg[6:0] vl;
assign texelselect = ul[1:0] ;
always @(posedge clk)
begin
if (enable == 1'b1)
begin
ul <= u ;
vl <= v ;
end
else
begin
ul <= ul ;
vl <= vl ;
end
case (factor)
3'b000 :
begin
addr <= start + ({13'b0000000000000, ul[6:2]}) + ({11'b00000000000, vl}) ;
end
3'b001 :
begin
addr <= start + ({13'b0000000000000, ul[6:2]}) + ({10'b0000000000, vl, 1'b0}) ;
end
3'b010 :
begin
addr <= start + ({13'b0000000000000, ul[6:2]}) + ({9'b000000000, vl, 2'b00}) ;
end
3'b011 :
begin
addr <= start + ({13'b0000000000000, ul[6:2]}) + ({8'b00000000, vl, 3'b000}) ;
end
3'b100 :
begin
addr <= start + ({13'b0000000000000, ul[6:2]}) + ({7'b0000000, vl, 4'b0000}) ;
end
3'b101 :
begin
addr <= start + ({13'b0000000000000, ul[6:2]}) + ({6'b000000, vl, 5'b00000}) ;
end
3'b110 :
begin
addr <= start + ({13'b0000000000000, ul[6:2]}) + ({5'b00000, vl, 6'b000000}) ;
end
3'b111 :
begin
addr <= start + ({13'b0000000000000, ul[6:2]}) + ({4'b0000, vl, 7'b0000000}) ;
end
endcase
end
endmodule
module bilinearintrp (u01a, u01b, u01c, v01a, v01b, v01c, u10a, u10b, u10c, v10a, v10b, v10c, selectuv, ru, rv, rw, gu, gv, gw, bu, bv, bw, r, g, b, clk);
input[7:0] u01a;
input[7:0] u01b;
input[7:0] u01c;
input[7:0] v01a;
input[7:0] v01b;
input[7:0] v01c;
input[7:0] u10a;
input[7:0] u10b;
input[7:0] u10c;
input[7:0] v10a;
input[7:0] v10b;
input[7:0] v10c;
input[2:0] selectuv;
input[6:0] ru;
input[6:0] rv;
input[6:0] rw;
input[6:0] gu;
input[6:0] gv;
input[6:0] gw;
input[6:0] bu;
input[6:0] bv;
input[6:0] bw;
output[6:0] r;
wire[6:0] r;
output[6:0] g;
wire[6:0] g;
output[6:0] b;
wire[6:0] b;
input clk;
reg[7:0] u;
reg[7:0] v;
reg[7:0] ul;
reg[7:0] vl;
reg[7:0] wl;
reg[14:0] i1b;
reg[14:0] i2b;
reg[14:0] i3b;
reg[14:0] i1g;
reg[14:0] i2g;
reg[14:0] i3g;
reg[14:0] i1r;
reg[14:0] i2r;
reg[14:0] i3r;
reg[6:0] rul;
reg[6:0] rvl;
reg[6:0] rwl;
reg[6:0] gul;
reg[6:0] gvl;
reg[6:0] gwl;
reg[6:0] bul;
reg[6:0] bvl;
reg[6:0] bwl;
always @(selectuv or u01a or u01b or u01c or v01a or v01b or v01c or u10a or
u10b or u10c or v10a or v10b or v10c)
begin
case (selectuv)
3'b000 :
begin
u = u01a ;
v = v01a ;
end
3'b001 :
begin
u = u01b ;
v = v01b ;
end
3'b010 :
begin
u = u01c ;
v = v01c ;
end
3'b100 :
begin
u = u10a ;
v = v10a ;
end
3'b101 :
begin
u = u10b ;
v = v10b ;
end
3'b110 :
begin
u = u10c ;
v = v10c ;
end
default :
begin
u = 0;
v = 0;
end
endcase
end
always @(posedge clk)
begin
wl <= 8'b11111111 - u - v ;
ul <= u ;
vl <= v ;
rul <= ru ;
rvl <= rv ;
rwl <= rw ;
gul <= gu ;
gvl <= gv ;
gwl <= gw ;
bul <= bu ;
bvl <= bv ;
bwl <= bw ;
i1r <= ul * rul ;
i2r <= vl * rvl ;
i3r <= wl * rwl ;
i1g <= ul * gul ;
i2g <= vl * gvl ;
i3g <= wl * gwl ;
i1b <= ul * bul ;
i2b <= vl * bvl ;
i3b <= wl * bwl ;
end
assign r = (i1r + i2r + i3r) ;
assign g = (i1g + i2g + i3g) ;
assign b = (i1b + i2b + i3b) ;
endmodule
module fifo3 (datain, writeen, dataout, shiften, globalreset, clk);
input[18 - 1:0] datain;
input writeen;
output[18 - 1:0] dataout;
wire[18 - 1:0] dataout;
input shiften;
input globalreset;
input clk;
reg[18 - 1:0] data0;
reg[18 - 1:0] data1;
reg[18 - 1:0] data2;
reg[1:0] pos;
assign dataout = data0 ;
always @(posedge clk or posedge globalreset)
begin
if (globalreset == 1'b1)
begin
pos <= 2'b00 ;
data0 <= 0 ;
data1 <= 0 ;
data2 <= 0 ;
end
else
begin
if (writeen == 1'b1 & shiften == 1'b1)
begin
case (pos)
2'b00 :
begin
data0 <= 0 ;
data1 <= 0 ;
data2 <= 0 ;
end
2'b01 :
begin
data0 <= datain ;
data1 <= 0 ;
data2 <= 0 ;
end
2'b10 :
begin
data0 <= data1 ;
data1 <= datain ;
data2 <= 0 ;
end
2'b11 :
begin
data0 <= data1 ;
data1 <= data2 ;
data2 <= datain ;
end
endcase
end
else if (shiften == 1'b1)
begin
data0 <= data1 ;
data1 <= data2 ;
pos <= pos - 1 ;
end
else if (writeen == 1'b1)
begin
case (pos)
2'b00 :
begin
data0 <= datain ;
end
2'b01 :
begin
data1 <= datain ;
end
2'b10 :
begin
data2 <= datain ;
end
endcase
pos <= pos + 1 ;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O221A_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O221A_PP_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o221a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O221A_PP_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// verilator lint_off LITENDIAN
wire [10:41] sel2 = crc[31:0];
wire [10:100] sel3 = {crc[26:0],crc};
wire out20 = sel2[{1'b0,crc[3:0]} + 11];
wire [3:0] out21 = sel2[13 : 16];
wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4];
wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4];
wire out30 = sel3[{2'b0,crc[3:0]} + 11];
wire [3:0] out31 = sel3[13 : 16];
wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4];
wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4];
// Aggregate outputs into a single result vector
wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33};
reg [19:50] sel1;
initial begin
// Path clearing
// 122333445
// 826048260
sel1 = 32'h12345678;
if (sel1 != 32'h12345678) $stop;
if (sel1[47 : 50] != 4'h8) $stop;
if (sel1[31 : 34] != 4'h4) $stop;
if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20]
if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24]
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33);
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h28bf65439eb12c00
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
`include "../include/tune.v"
module rom(
input [15:0] addr,
output reg [7:0] data,
input ce_n
);
always @*
begin
if( ce_n )
data <= 8'bZZZZZZZZ;
else
case(addr[13:0])
16'h0000: data<=8'h21;
16'h0001: data<=8'h0e;
16'h0002: data<=8'h00;
16'h0003: data<=8'h11;
16'h0004: data<=8'h00;
16'h0005: data<=8'h60;
16'h0006: data<=8'h01;
16'h0007: data<=8'h1c;
16'h0008: data<=8'h00;
16'h0009: data<=8'hed;
16'h000a: data<=8'hb0;
16'h000b: data<=8'hc3;
16'h000c: data<=8'h00;
16'h000d: data<=8'h60;
16'h000e: data<=8'h21; // ld hl,dcfe
16'h000f: data<=8'hfe;
16'h0010: data<=8'hdc;
16'h0011: data<=8'hf9; // ld sp,hl
16'h0012: data<=8'h11; // ld de,4523
16'h0013: data<=8'h23;
16'h0014: data<=8'h45;
16'h0015: data<=8'he5; // push hl
16'h0016: data<=8'h19; // add hl,de
16'h0017: data<=8'he5;
16'h0018: data<=8'h19;
16'h0019: data<=8'he5;
16'h001a: data<=8'h19;
16'h001b: data<=8'heb; // ex de,hl
16'h001c: data<=8'he1; // pop hl
16'h001d: data<=8'h22; // ld (4444),hl
16'h001e: data<=8'h44;
16'h001f: data<=8'h44;
16'h0020: data<=8'he1;
16'h0021: data<=8'h22;
16'h0022: data<=8'h44;
16'h0023: data<=8'h44;
16'h0024: data<=8'he1;
16'h0025: data<=8'h22;
16'h0026: data<=8'h44;
16'h0027: data<=8'h44;
16'h0028: data<=8'h18; // jr 7
16'h0029: data<=8'heb;
16'h002a: data<=8'h00;
16'h002b: data<=8'hff;
default: data<=8'hFF;
endcase
end
endmodule
|
module mojo_top_0(
// 50MHz clock input
input clk,
// Input from rst button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard leds
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
output [23:0] io_led, // LEDs on IO Shield
output [7:0] io_seg, // 7-segment LEDs on IO Shield
output [3:0] io_sel, // Digit select on IO Shield
input [3:0] pb,
input en,
output pm
);
wire rst = ~rst_n; // make rst active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
assign led[7:0] = {8{slow_clk}};
reg [25:0] slow_clk_d, slow_clk_q;
reg slow_clk;
always @(slow_clk_q) begin
if (pb[0] && ~(slow_clk_q % 8'hFA)) begin
slow_clk_d = slow_clk_q + 8'hFA;
end else if (pb[1] && ~(slow_clk_q % 11'h4E2)) begin
slow_clk_d = slow_clk_q + 11'h4E2;
end else if (pb[2] && ~(slow_clk_q % 13'h186A)) begin
slow_clk_d = slow_clk_q + 13'h186A;
end else begin
slow_clk_d = slow_clk_q + 1'b1;
end
end
always @(posedge clk, posedge rst) begin
if (rst == 1) begin
slow_clk_q <= 25'b0;
slow_clk <= 1'b0;
end else if (slow_clk_q == 25'h17D7840) begin
slow_clk_q <= 25'b0;
slow_clk <= ~slow_clk;
end else begin
slow_clk_q <= slow_clk_d;
end
end
clock_1 real_deal (
.clk(slow_clk),
.fast_clk(slow_clk_q[16]),
.rst(rst),
.en(~en),
.sec(io_led[7:0]),
.pm(io_led[23:8]),
.io_seg(io_seg),
.io_sel(io_sel)
);
endmodule |
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1507 USA
module quad(clk, A, B, Z, zr, out);
parameter W=14;
input clk, A, B, Z, zr;
reg [(W-1):0] c, i; reg zl;
output [2*W:0] out = { zl, i, c };
// reg [(W-1):0] c, i; reg zl;
reg [2:0] Ad, Bd;
reg [2:0] Zc;
always @(posedge clk) Ad <= {Ad[1:0], A};
always @(posedge clk) Bd <= {Bd[1:0], B};
wire good_one = &Zc;
wire good_zero = ~|Zc;
reg last_good;
wire index_pulse = good_one && ! last_good;
wire count_enable = Ad[1] ^ Ad[2] ^ Bd[1] ^ Bd[2];
wire count_direction = Ad[1] ^ Bd[2];
always @(posedge clk)
begin
if(Z && !good_one) Zc <= Zc + 2'b1;
else if(!good_zero) Zc <= Zc - 2'b1;
if(good_one) last_good <= 1;
else if(good_zero) last_good <= 0;
if(count_enable)
begin
if(count_direction) c <= c + 1'd1;
else c <= c - 1'd1;
end
if(index_pulse) begin
i <= c;
zl <= 1;
end else if(zr) begin
zl <= 0;
end
end
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** Base-2 Logarithm *)
Require Import NZAxioms NZMulOrder NZPow.
(** Interface of a log2 function, then its specification on naturals *)
Module Type Log2 (Import A : Typ).
Parameter Inline log2 : t -> t.
End Log2.
Module Type NZLog2Spec (A : NZOrdAxiomsSig')(B : Pow' A)(C : Log2 A).
Import A B C.
Axiom log2_spec : forall a, 0<a -> 2^(log2 a) <= a < 2^(S (log2 a)).
Axiom log2_nonpos : forall a, a<=0 -> log2 a == 0.
End NZLog2Spec.
Module Type NZLog2 (A : NZOrdAxiomsSig)(B : Pow A) := Log2 A <+ NZLog2Spec A B.
(** Derived properties of logarithm *)
Module Type NZLog2Prop
(Import A : NZOrdAxiomsSig')
(Import B : NZPow' A)
(Import C : NZLog2 A B)
(Import D : NZMulOrderProp A)
(Import E : NZPowProp A B D).
(** log2 is always non-negative *)
Lemma log2_nonneg : forall a, 0 <= log2 a.
Proof.
intros a. destruct (le_gt_cases a 0) as [Ha|Ha].
- now rewrite log2_nonpos.
- destruct (log2_spec a Ha) as (_,LT).
apply lt_succ_r, (pow_gt_1 2). + order'.
+ rewrite <- le_succ_l, <- one_succ in Ha. order.
Qed.
(** A tactic for proving positivity and non-negativity *)
Ltac order_pos :=
((apply add_pos_pos || apply add_nonneg_nonneg ||
apply mul_pos_pos || apply mul_nonneg_nonneg ||
apply pow_nonneg || apply pow_pos_nonneg ||
apply log2_nonneg || apply (le_le_succ_r 0));
order_pos) (* in case of success of an apply, we recurse *)
|| order'. (* otherwise *)
(** The spec of log2 indeed determines it *)
Lemma log2_unique : forall a b, 0<=b -> 2^b<=a<2^(S b) -> log2 a == b.
Proof.
intros a b Hb (LEb,LTb).
assert (Ha : 0 < a).
- apply lt_le_trans with (2^b); trivial.
apply pow_pos_nonneg; order'.
- assert (Hc := log2_nonneg a).
destruct (log2_spec a Ha) as (LEc,LTc).
assert (log2 a <= b).
+ apply lt_succ_r, (pow_lt_mono_r_iff 2); try order'.
now apply le_le_succ_r.
+ assert (b <= log2 a).
* apply lt_succ_r, (pow_lt_mono_r_iff 2); try order'.
now apply le_le_succ_r.
* order.
Qed.
(** Hence log2 is a morphism. *)
#[global]
Instance log2_wd : Proper (eq==>eq) log2.
Proof.
intros x x' Hx.
destruct (le_gt_cases x 0).
- rewrite 2 log2_nonpos; trivial. + reflexivity. + now rewrite <- Hx.
- apply log2_unique. + apply log2_nonneg.
+ rewrite Hx in *. now apply log2_spec.
Qed.
(** An alternate specification *)
Lemma log2_spec_alt : forall a, 0<a -> exists r,
a == 2^(log2 a) + r /\ 0 <= r < 2^(log2 a).
Proof.
intros a Ha.
destruct (log2_spec _ Ha) as (LE,LT).
destruct (le_exists_sub _ _ LE) as (r & Hr & Hr').
exists r.
split. - now rewrite add_comm.
- split. + trivial.
+ apply (add_lt_mono_r _ _ (2^log2 a)).
rewrite <- Hr. generalize LT.
rewrite pow_succ_r by order_pos.
rewrite two_succ at 1. now nzsimpl.
Qed.
Lemma log2_unique' : forall a b c, 0<=b -> 0<=c<2^b ->
a == 2^b + c -> log2 a == b.
Proof.
intros a b c Hb (Hc,H) EQ.
apply log2_unique. - trivial.
- rewrite EQ.
split.
+ rewrite <- add_0_r at 1. now apply add_le_mono_l.
+ rewrite pow_succ_r by order.
rewrite two_succ at 2. nzsimpl. now apply add_lt_mono_l.
Qed.
(** log2 is exact on powers of 2 *)
Lemma log2_pow2 : forall a, 0<=a -> log2 (2^a) == a.
Proof.
intros a Ha.
apply log2_unique' with 0; trivial.
- split; order_pos. - now nzsimpl.
Qed.
(** log2 and predecessors of powers of 2 *)
Lemma log2_pred_pow2 : forall a, 0<a -> log2 (P (2^a)) == P a.
Proof.
intros a Ha.
assert (Ha' : S (P a) == a) by (now rewrite lt_succ_pred with 0).
apply log2_unique.
- apply lt_succ_r; order.
- rewrite <-le_succ_l, <-lt_succ_r, Ha'.
rewrite lt_succ_pred with 0.
+ split; try easy. apply pow_lt_mono_r_iff; try order'.
rewrite succ_lt_mono, Ha'. apply lt_succ_diag_r.
+ apply pow_pos_nonneg; order'.
Qed.
(** log2 and basic constants *)
Lemma log2_1 : log2 1 == 0.
Proof.
rewrite <- (pow_0_r 2). now apply log2_pow2.
Qed.
Lemma log2_2 : log2 2 == 1.
Proof.
rewrite <- (pow_1_r 2). apply log2_pow2; order'.
Qed.
(** log2 n is strictly positive for 1<n *)
Lemma log2_pos : forall a, 1<a -> 0 < log2 a.
Proof.
intros a Ha.
assert (Ha' : 0 < a) by order'.
assert (H := log2_nonneg a). le_elim H; trivial.
generalize (log2_spec a Ha'). rewrite <- H in *. nzsimpl; try order.
intros (_,H'). rewrite two_succ in H'. apply lt_succ_r in H'; order.
Qed.
(** Said otherwise, log2 is null only below 1 *)
Lemma log2_null : forall a, log2 a == 0 <-> a <= 1.
Proof.
intros a. split; intros H.
- destruct (le_gt_cases a 1) as [Ha|Ha]; trivial.
generalize (log2_pos a Ha); order.
- le_elim H.
+ apply log2_nonpos. apply lt_succ_r. now rewrite <- one_succ.
+ rewrite H. apply log2_1.
Qed.
(** log2 is a monotone function (but not a strict one) *)
Lemma log2_le_mono : forall a b, a<=b -> log2 a <= log2 b.
Proof.
intros a b H.
destruct (le_gt_cases a 0) as [Ha|Ha].
- rewrite log2_nonpos; order_pos.
- assert (Hb : 0 < b) by order.
destruct (log2_spec a Ha) as (LEa,_).
destruct (log2_spec b Hb) as (_,LTb).
apply lt_succ_r, (pow_lt_mono_r_iff 2); order_pos.
Qed.
(** No reverse result for <=, consider for instance log2 3 <= log2 2 *)
Lemma log2_lt_cancel : forall a b, log2 a < log2 b -> a < b.
Proof.
intros a b H.
destruct (le_gt_cases b 0) as [Hb|Hb].
- rewrite (log2_nonpos b) in H; trivial.
generalize (log2_nonneg a); order.
- destruct (le_gt_cases a 0) as [Ha|Ha]. + order.
+ destruct (log2_spec a Ha) as (_,LTa).
destruct (log2_spec b Hb) as (LEb,_).
apply le_succ_l in H.
apply (pow_le_mono_r_iff 2) in H; order_pos.
Qed.
(** When left side is a power of 2, we have an equivalence for <= *)
Lemma log2_le_pow2 : forall a b, 0<a -> (2^b<=a <-> b <= log2 a).
Proof.
intros a b Ha.
split; intros H.
- destruct (lt_ge_cases b 0) as [Hb|Hb].
+ generalize (log2_nonneg a); order.
+ rewrite <- (log2_pow2 b); trivial. now apply log2_le_mono.
- transitivity (2^(log2 a)).
+ apply pow_le_mono_r; order'.
+ now destruct (log2_spec a Ha).
Qed.
(** When right side is a square, we have an equivalence for < *)
Lemma log2_lt_pow2 : forall a b, 0<a -> (a<2^b <-> log2 a < b).
Proof.
intros a b Ha.
split; intros H.
- destruct (lt_ge_cases b 0) as [Hb|Hb].
+ rewrite pow_neg_r in H; order.
+ apply (pow_lt_mono_r_iff 2); try order_pos.
apply le_lt_trans with a; trivial.
now destruct (log2_spec a Ha).
- destruct (lt_ge_cases b 0) as [Hb|Hb].
+ generalize (log2_nonneg a); order.
+ apply log2_lt_cancel; try order.
now rewrite log2_pow2.
Qed.
(** Comparing log2 and identity *)
Lemma log2_lt_lin : forall a, 0<a -> log2 a < a.
Proof.
intros a Ha.
apply (pow_lt_mono_r_iff 2); try order_pos.
apply le_lt_trans with a.
- now destruct (log2_spec a Ha).
- apply pow_gt_lin_r; order'.
Qed.
Lemma log2_le_lin : forall a, 0<=a -> log2 a <= a.
Proof.
intros a Ha.
le_elim Ha.
- now apply lt_le_incl, log2_lt_lin.
- rewrite <- Ha, log2_nonpos; order.
Qed.
(** Log2 and multiplication. *)
(** Due to rounding error, we don't have the usual
[log2 (a*b) = log2 a + log2 b] but we may be off by 1 at most *)
Lemma log2_mul_below : forall a b, 0<a -> 0<b ->
log2 a + log2 b <= log2 (a*b).
Proof.
intros a b Ha Hb.
apply log2_le_pow2; try order_pos.
rewrite pow_add_r by order_pos.
apply mul_le_mono_nonneg; try apply log2_spec; order_pos.
Qed.
Lemma log2_mul_above : forall a b, 0<=a -> 0<=b ->
log2 (a*b) <= log2 a + log2 b + 1.
Proof.
intros a b Ha Hb.
le_elim Ha.
- le_elim Hb.
+ apply lt_succ_r.
rewrite add_1_r, <- add_succ_r, <- add_succ_l.
apply log2_lt_pow2; try order_pos.
rewrite pow_add_r by order_pos.
apply mul_lt_mono_nonneg; try order; now apply log2_spec.
+ rewrite <- Hb. nzsimpl. rewrite log2_nonpos; order_pos.
- rewrite <- Ha. nzsimpl. rewrite log2_nonpos; order_pos.
Qed.
(** And we can't find better approximations in general.
- The lower bound is exact for powers of 2.
- Concerning the upper bound, for any c>1, take a=b=2^c-1,
then log2 (a*b) = c+c -1 while (log2 a) = (log2 b) = c-1
*)
(** At least, we get back the usual equation when we multiply by 2 (or 2^k) *)
Lemma log2_mul_pow2 : forall a b, 0<a -> 0<=b -> log2 (a*2^b) == b + log2 a.
Proof.
intros a b Ha Hb.
apply log2_unique; try order_pos. split.
- rewrite pow_add_r, mul_comm; try order_pos.
apply mul_le_mono_nonneg_r. + order_pos. + now apply log2_spec.
- rewrite <-add_succ_r, pow_add_r, mul_comm; try order_pos.
apply mul_lt_mono_pos_l. + order_pos. + now apply log2_spec.
Qed.
Lemma log2_double : forall a, 0<a -> log2 (2*a) == S (log2 a).
Proof.
intros a Ha. generalize (log2_mul_pow2 a 1 Ha le_0_1). now nzsimpl'.
Qed.
(** Two numbers with same log2 cannot be far away. *)
Lemma log2_same : forall a b, 0<a -> 0<b -> log2 a == log2 b -> a < 2*b.
Proof.
intros a b Ha Hb H.
apply log2_lt_cancel. rewrite log2_double, H by trivial.
apply lt_succ_diag_r.
Qed.
(** Log2 and successor :
- the log2 function climbs by at most 1 at a time
- otherwise it stays at the same value
- the +1 steps occur for powers of two
*)
Lemma log2_succ_le : forall a, log2 (S a) <= S (log2 a).
Proof.
intros a.
destruct (lt_trichotomy 0 a) as [LT|[EQ|LT]].
- apply (pow_le_mono_r_iff 2); try order_pos.
transitivity (S a).
+ apply log2_spec.
apply lt_succ_r; order.
+ now apply le_succ_l, log2_spec.
- rewrite <- EQ, <- one_succ, log2_1; order_pos.
- rewrite 2 log2_nonpos. + order_pos. + order'. + now rewrite le_succ_l.
Qed.
Lemma log2_succ_or : forall a,
log2 (S a) == S (log2 a) \/ log2 (S a) == log2 a.
Proof.
intros a.
destruct (le_gt_cases (log2 (S a)) (log2 a)) as [H|H].
- right. generalize (log2_le_mono _ _ (le_succ_diag_r a)); order.
- left. apply le_succ_l in H. generalize (log2_succ_le a); order.
Qed.
Lemma log2_eq_succ_is_pow2 : forall a,
log2 (S a) == S (log2 a) -> exists b, S a == 2^b.
Proof.
intros a H.
destruct (le_gt_cases a 0) as [Ha|Ha].
- rewrite 2 (proj2 (log2_null _)) in H. + generalize (lt_succ_diag_r 0); order.
+ order'. + apply le_succ_l. order'.
- assert (Ha' : 0 < S a) by (apply lt_succ_r; order).
exists (log2 (S a)).
generalize (proj1 (log2_spec (S a) Ha')) (proj2 (log2_spec a Ha)).
rewrite <- le_succ_l, <- H. order.
Qed.
Lemma log2_eq_succ_iff_pow2 : forall a, 0<a ->
(log2 (S a) == S (log2 a) <-> exists b, S a == 2^b).
Proof.
intros a Ha.
split. - apply log2_eq_succ_is_pow2.
- intros (b,Hb).
assert (Hb' : 0 < b).
+ apply (pow_gt_1 2); try order'; now rewrite <- Hb, one_succ, <- succ_lt_mono.
+ rewrite Hb, log2_pow2; try order'.
setoid_replace a with (P (2^b)). * rewrite log2_pred_pow2; trivial.
symmetry; now apply lt_succ_pred with 0.
* apply succ_inj. rewrite Hb. symmetry. apply lt_succ_pred with 0.
rewrite <- Hb, lt_succ_r; order.
Qed.
Lemma log2_succ_double : forall a, 0<a -> log2 (2*a+1) == S (log2 a).
Proof.
intros a Ha.
rewrite add_1_r.
destruct (log2_succ_or (2*a)) as [H|H]; [exfalso|now rewrite H, log2_double].
apply log2_eq_succ_is_pow2 in H. destruct H as (b,H).
destruct (lt_trichotomy b 0) as [LT|[EQ|LT]].
- rewrite pow_neg_r in H; trivial.
apply (mul_pos_pos 2), succ_lt_mono in Ha; try order'.
rewrite <- one_succ in Ha. order'.
- rewrite EQ, pow_0_r in H.
apply (mul_pos_pos 2), succ_lt_mono in Ha; try order'.
rewrite <- one_succ in Ha. order'.
- assert (EQ:=lt_succ_pred 0 b LT).
rewrite <- EQ, pow_succ_r in H; [|now rewrite <- lt_succ_r, EQ].
destruct (lt_ge_cases a (2^(P b))) as [LT'|LE'].
+ generalize (mul_2_mono_l _ _ LT'). rewrite add_1_l. order.
+ rewrite (mul_le_mono_pos_l _ _ 2) in LE'; try order'.
rewrite <- H in LE'. apply le_succ_l in LE'. order.
Qed.
(** Log2 and addition *)
Lemma log2_add_le : forall a b, a~=1 -> b~=1 -> log2 (a+b) <= log2 a + log2 b.
Proof.
intros a b Ha Hb.
destruct (lt_trichotomy a 1) as [Ha'|[Ha'|Ha']]; [|order|].
- rewrite one_succ, lt_succ_r in Ha'.
rewrite (log2_nonpos a); trivial. nzsimpl. apply log2_le_mono.
rewrite <- (add_0_l b) at 2. now apply add_le_mono.
- destruct (lt_trichotomy b 1) as [Hb'|[Hb'|Hb']]; [|order|].
+ rewrite one_succ, lt_succ_r in Hb'.
rewrite (log2_nonpos b); trivial. nzsimpl. apply log2_le_mono.
rewrite <- (add_0_r a) at 2. now apply add_le_mono.
+ clear Ha Hb.
apply lt_succ_r.
apply log2_lt_pow2; try order_pos.
rewrite pow_succ_r by order_pos.
rewrite two_succ, one_succ at 1. nzsimpl.
apply add_lt_mono.
* apply lt_le_trans with (2^(S (log2 a))). -- apply log2_spec; order'.
-- apply pow_le_mono_r. ++ order'.
++ rewrite <- add_1_r. apply add_le_mono_l.
rewrite one_succ; now apply le_succ_l, log2_pos.
* apply lt_le_trans with (2^(S (log2 b))).
-- apply log2_spec; order'.
-- apply pow_le_mono_r. ++ order'.
++ rewrite <- add_1_l. apply add_le_mono_r.
rewrite one_succ; now apply le_succ_l, log2_pos.
Qed.
(** The sum of two log2 is less than twice the log2 of the sum.
The large inequality is obvious thanks to monotonicity.
The strict one requires some more work. This is almost
a convexity inequality for points [2a], [2b] and their middle [a+b] :
ideally, we would have [2*log(a+b) >= log(2a)+log(2b) = 2+log a+log b].
Here, we cannot do better: consider for instance a=2 b=4, then 1+2<2*2
*)
Lemma add_log2_lt : forall a b, 0<a -> 0<b ->
log2 a + log2 b < 2 * log2 (a+b).
Proof.
intros a b Ha Hb. nzsimpl'.
assert (H : log2 a <= log2 (a+b)).
- apply log2_le_mono. rewrite <- (add_0_r a) at 1. apply add_le_mono; order.
- assert (H' : log2 b <= log2 (a+b)).
+ apply log2_le_mono. rewrite <- (add_0_l b) at 1. apply add_le_mono; order.
+ le_elim H.
* apply lt_le_trans with (log2 (a+b) + log2 b).
-- now apply add_lt_mono_r. -- now apply add_le_mono_l.
* rewrite <- H at 1. apply add_lt_mono_l.
le_elim H'; trivial.
symmetry in H. apply log2_same in H; try order_pos.
symmetry in H'. apply log2_same in H'; try order_pos.
revert H H'. nzsimpl'. rewrite <- add_lt_mono_l, <- add_lt_mono_r; order.
Qed.
End NZLog2Prop.
Module NZLog2UpProp
(Import A : NZDecOrdAxiomsSig')
(Import B : NZPow' A)
(Import C : NZLog2 A B)
(Import D : NZMulOrderProp A)
(Import E : NZPowProp A B D)
(Import F : NZLog2Prop A B C D E).
(** * [log2_up] : a binary logarithm that rounds up instead of down *)
(** For once, we define instead of axiomatizing, thanks to log2 *)
Definition log2_up a :=
match compare 1 a with
| Lt => S (log2 (P a))
| _ => 0
end.
Lemma log2_up_eqn0 : forall a, a<=1 -> log2_up a == 0.
Proof.
intros a Ha. unfold log2_up. case compare_spec; try order.
Qed.
Lemma log2_up_eqn : forall a, 1<a -> log2_up a == S (log2 (P a)).
Proof.
intros a Ha. unfold log2_up. case compare_spec; try order.
Qed.
Lemma log2_up_spec : forall a, 1<a ->
2^(P (log2_up a)) < a <= 2^(log2_up a).
Proof.
intros a Ha.
rewrite log2_up_eqn; trivial.
rewrite pred_succ.
rewrite <- (lt_succ_pred 1 a Ha) at 2 3.
rewrite lt_succ_r, le_succ_l.
apply log2_spec.
apply succ_lt_mono. now rewrite (lt_succ_pred 1 a Ha), <- one_succ.
Qed.
Lemma log2_up_nonpos : forall a, a<=0 -> log2_up a == 0.
Proof.
intros. apply log2_up_eqn0. order'.
Qed.
#[global]
Instance log2_up_wd : Proper (eq==>eq) log2_up.
Proof.
assert (Proper (eq==>eq==>Logic.eq) compare).
- repeat red; intros; do 2 case compare_spec; trivial; order.
- intros a a' Ha. unfold log2_up. rewrite Ha at 1.
case compare; now rewrite ?Ha.
Qed.
(** [log2_up] is always non-negative *)
Lemma log2_up_nonneg : forall a, 0 <= log2_up a.
Proof.
intros a. unfold log2_up. case compare_spec; try order.
intros. apply le_le_succ_r, log2_nonneg.
Qed.
(** The spec of [log2_up] indeed determines it *)
Lemma log2_up_unique : forall a b, 0<b -> 2^(P b)<a<=2^b -> log2_up a == b.
Proof.
intros a b Hb (LEb,LTb).
assert (Ha : 1 < a).
- apply le_lt_trans with (2^(P b)); trivial.
rewrite one_succ. apply le_succ_l.
apply pow_pos_nonneg. + order'.
+ apply lt_succ_r.
now rewrite (lt_succ_pred 0 b Hb).
- assert (Hc := log2_up_nonneg a).
destruct (log2_up_spec a Ha) as (LTc,LEc).
assert (b <= log2_up a).
+ apply lt_succ_r. rewrite <- (lt_succ_pred 0 b Hb).
rewrite <- succ_lt_mono.
apply (pow_lt_mono_r_iff 2); try order'.
+ assert (Hc' : 0 < log2_up a) by order.
assert (log2_up a <= b).
* apply lt_succ_r. rewrite <- (lt_succ_pred 0 _ Hc').
rewrite <- succ_lt_mono.
apply (pow_lt_mono_r_iff 2); try order'.
* order.
Qed.
(** [log2_up] is exact on powers of 2 *)
Lemma log2_up_pow2 : forall a, 0<=a -> log2_up (2^a) == a.
Proof.
intros a Ha.
le_elim Ha.
- apply log2_up_unique; trivial.
split; try order.
apply pow_lt_mono_r; try order'.
rewrite <- (lt_succ_pred 0 a Ha) at 2.
now apply lt_succ_r.
- now rewrite <- Ha, pow_0_r, log2_up_eqn0.
Qed.
(** [log2_up] and successors of powers of 2 *)
Lemma log2_up_succ_pow2 : forall a, 0<=a -> log2_up (S (2^a)) == S a.
Proof.
intros a Ha.
rewrite log2_up_eqn, pred_succ, log2_pow2; try easy.
rewrite one_succ, <- succ_lt_mono. apply pow_pos_nonneg; order'.
Qed.
(** Basic constants *)
Lemma log2_up_1 : log2_up 1 == 0.
Proof.
now apply log2_up_eqn0.
Qed.
Lemma log2_up_2 : log2_up 2 == 1.
Proof.
rewrite <- (pow_1_r 2). apply log2_up_pow2; order'.
Qed.
(** Links between log2 and [log2_up] *)
Lemma le_log2_log2_up : forall a, log2 a <= log2_up a.
Proof.
intros a. unfold log2_up. case compare_spec; intros H.
- rewrite <- H, log2_1. order.
- rewrite <- (lt_succ_pred 1 a H) at 1. apply log2_succ_le.
- rewrite log2_nonpos. + order. + now rewrite <-lt_succ_r, <-one_succ.
Qed.
Lemma le_log2_up_succ_log2 : forall a, log2_up a <= S (log2 a).
Proof.
intros a. unfold log2_up. case compare_spec; intros H; try order_pos.
rewrite <- succ_le_mono. apply log2_le_mono.
rewrite <- (lt_succ_pred 1 a H) at 2. apply le_succ_diag_r.
Qed.
Lemma log2_log2_up_spec : forall a, 0<a ->
2^log2 a <= a <= 2^log2_up a.
Proof.
intros a H. split.
- now apply log2_spec.
- rewrite <-le_succ_l, <-one_succ in H. le_elim H.
+ now apply log2_up_spec.
+ now rewrite <-H, log2_up_1, pow_0_r.
Qed.
Lemma log2_log2_up_exact :
forall a, 0<a -> (log2 a == log2_up a <-> exists b, a == 2^b).
Proof.
intros a Ha.
split.
- intros H. exists (log2 a).
generalize (log2_log2_up_spec a Ha). rewrite <-H.
destruct 1; order.
- intros (b,Hb). rewrite Hb.
destruct (le_gt_cases 0 b).
+ now rewrite log2_pow2, log2_up_pow2.
+ rewrite pow_neg_r; trivial. now rewrite log2_nonpos, log2_up_nonpos.
Qed.
(** [log2_up] n is strictly positive for 1<n *)
Lemma log2_up_pos : forall a, 1<a -> 0 < log2_up a.
Proof.
intros. rewrite log2_up_eqn; trivial. apply lt_succ_r; order_pos.
Qed.
(** Said otherwise, [log2_up] is null only below 1 *)
Lemma log2_up_null : forall a, log2_up a == 0 <-> a <= 1.
Proof.
intros a. split; intros H.
- destruct (le_gt_cases a 1) as [Ha|Ha]; trivial.
generalize (log2_up_pos a Ha); order.
- now apply log2_up_eqn0.
Qed.
(** [log2_up] is a monotone function (but not a strict one) *)
Lemma log2_up_le_mono : forall a b, a<=b -> log2_up a <= log2_up b.
Proof.
intros a b H.
destruct (le_gt_cases a 1) as [Ha|Ha].
- rewrite log2_up_eqn0; trivial. apply log2_up_nonneg.
- rewrite 2 log2_up_eqn; try order.
rewrite <- succ_le_mono. apply log2_le_mono, succ_le_mono.
rewrite 2 lt_succ_pred with 1; order.
Qed.
(** No reverse result for <=, consider for instance log2_up 4 <= log2_up 3 *)
Lemma log2_up_lt_cancel : forall a b, log2_up a < log2_up b -> a < b.
Proof.
intros a b H.
destruct (le_gt_cases b 1) as [Hb|Hb].
- rewrite (log2_up_eqn0 b) in H; trivial.
generalize (log2_up_nonneg a); order.
- destruct (le_gt_cases a 1) as [Ha|Ha]. + order.
+ rewrite 2 log2_up_eqn in H; try order.
rewrite <- succ_lt_mono in H. apply log2_lt_cancel, succ_lt_mono in H.
rewrite 2 lt_succ_pred with 1 in H; order.
Qed.
(** When left side is a power of 2, we have an equivalence for < *)
Lemma log2_up_lt_pow2 : forall a b, 0<a -> (2^b<a <-> b < log2_up a).
Proof.
intros a b Ha.
split; intros H.
- destruct (lt_ge_cases b 0) as [Hb|Hb].
+ generalize (log2_up_nonneg a); order.
+ apply (pow_lt_mono_r_iff 2). * order'. * apply log2_up_nonneg.
* apply lt_le_trans with a; trivial.
apply (log2_up_spec a).
apply le_lt_trans with (2^b); trivial.
rewrite one_succ, le_succ_l. apply pow_pos_nonneg; order'.
- destruct (lt_ge_cases b 0) as [Hb|Hb].
+ now rewrite pow_neg_r.
+ rewrite <- (log2_up_pow2 b) in H; trivial. now apply log2_up_lt_cancel.
Qed.
(** When right side is a square, we have an equivalence for <= *)
Lemma log2_up_le_pow2 : forall a b, 0<a -> (a<=2^b <-> log2_up a <= b).
Proof.
intros a b Ha.
split; intros H.
- destruct (lt_ge_cases b 0) as [Hb|Hb].
+ rewrite pow_neg_r in H; order.
+ rewrite <- (log2_up_pow2 b); trivial. now apply log2_up_le_mono.
- transitivity (2^(log2_up a)).
+ now apply log2_log2_up_spec.
+ apply pow_le_mono_r; order'.
Qed.
(** Comparing [log2_up] and identity *)
Lemma log2_up_lt_lin : forall a, 0<a -> log2_up a < a.
Proof.
intros a Ha.
assert (H : S (P a) == a) by (now apply lt_succ_pred with 0).
rewrite <- H at 2. apply lt_succ_r. apply log2_up_le_pow2; trivial.
rewrite <- H at 1. apply le_succ_l.
apply pow_gt_lin_r. - order'. - apply lt_succ_r; order.
Qed.
Lemma log2_up_le_lin : forall a, 0<=a -> log2_up a <= a.
Proof.
intros a Ha.
le_elim Ha.
- now apply lt_le_incl, log2_up_lt_lin.
- rewrite <- Ha, log2_up_nonpos; order.
Qed.
(** [log2_up] and multiplication. *)
(** Due to rounding error, we don't have the usual
[log2_up (a*b) = log2_up a + log2_up b] but we may be off by 1 at most *)
Lemma log2_up_mul_above : forall a b, 0<=a -> 0<=b ->
log2_up (a*b) <= log2_up a + log2_up b.
Proof.
intros a b Ha Hb.
assert (Ha':=log2_up_nonneg a).
assert (Hb':=log2_up_nonneg b).
le_elim Ha.
- le_elim Hb.
+ apply log2_up_le_pow2; try order_pos.
rewrite pow_add_r; trivial.
apply mul_le_mono_nonneg; try apply log2_log2_up_spec; order'.
+ rewrite <- Hb. nzsimpl. rewrite log2_up_nonpos; order_pos.
- rewrite <- Ha. nzsimpl. rewrite log2_up_nonpos; order_pos.
Qed.
Lemma log2_up_mul_below : forall a b, 0<a -> 0<b ->
log2_up a + log2_up b <= S (log2_up (a*b)).
Proof.
intros a b Ha Hb.
rewrite <-le_succ_l, <-one_succ in Ha. le_elim Ha.
- rewrite <-le_succ_l, <-one_succ in Hb. le_elim Hb.
+ assert (Ha' : 0 < log2_up a) by (apply log2_up_pos; trivial).
assert (Hb' : 0 < log2_up b) by (apply log2_up_pos; trivial).
rewrite <- (lt_succ_pred 0 (log2_up a)); trivial.
rewrite <- (lt_succ_pred 0 (log2_up b)); trivial.
nzsimpl. rewrite <- succ_le_mono, le_succ_l.
apply (pow_lt_mono_r_iff 2). * order'. * apply log2_up_nonneg.
* rewrite pow_add_r; try (apply lt_succ_r; rewrite (lt_succ_pred 0); trivial).
apply lt_le_trans with (a*b).
-- apply mul_lt_mono_nonneg; try order_pos; try now apply log2_up_spec.
-- apply log2_up_spec.
setoid_replace 1 with (1*1) by now nzsimpl.
apply mul_lt_mono_nonneg; order'.
+ rewrite <- Hb, log2_up_1; nzsimpl. apply le_succ_diag_r.
- rewrite <- Ha, log2_up_1; nzsimpl. apply le_succ_diag_r.
Qed.
(** And we can't find better approximations in general.
- The upper bound is exact for powers of 2.
- Concerning the lower bound, for any c>1, take a=b=2^c+1,
then [log2_up (a*b) = c+c +1] while [(log2_up a) = (log2_up b) = c+1]
*)
(** At least, we get back the usual equation when we multiply by 2 (or 2^k) *)
Lemma log2_up_mul_pow2 : forall a b, 0<a -> 0<=b ->
log2_up (a*2^b) == b + log2_up a.
Proof.
intros a b Ha Hb.
rewrite <- le_succ_l, <- one_succ in Ha; le_elim Ha.
- apply log2_up_unique. + apply add_nonneg_pos; trivial. now apply log2_up_pos.
+ split.
* assert (EQ := lt_succ_pred 0 _ (log2_up_pos _ Ha)).
rewrite <- EQ. nzsimpl. rewrite pow_add_r, mul_comm; trivial.
-- apply mul_lt_mono_pos_r. ++ order_pos. ++ now apply log2_up_spec.
-- rewrite <- lt_succ_r, EQ. now apply log2_up_pos.
* rewrite pow_add_r, mul_comm; trivial.
-- apply mul_le_mono_nonneg_l. ++ order_pos. ++ now apply log2_up_spec.
-- apply log2_up_nonneg.
- now rewrite <- Ha, mul_1_l, log2_up_1, add_0_r, log2_up_pow2.
Qed.
Lemma log2_up_double : forall a, 0<a -> log2_up (2*a) == S (log2_up a).
Proof.
intros a Ha. generalize (log2_up_mul_pow2 a 1 Ha le_0_1). now nzsimpl'.
Qed.
(** Two numbers with same [log2_up] cannot be far away. *)
Lemma log2_up_same : forall a b, 0<a -> 0<b -> log2_up a == log2_up b -> a < 2*b.
Proof.
intros a b Ha Hb H.
apply log2_up_lt_cancel. rewrite log2_up_double, H by trivial.
apply lt_succ_diag_r.
Qed.
(** [log2_up] and successor :
- the [log2_up] function climbs by at most 1 at a time
- otherwise it stays at the same value
- the +1 steps occur after powers of two
*)
Lemma log2_up_succ_le : forall a, log2_up (S a) <= S (log2_up a).
Proof.
intros a.
destruct (lt_trichotomy 1 a) as [LT|[EQ|LT]].
- rewrite 2 log2_up_eqn; trivial.
+ rewrite pred_succ, <- succ_le_mono. rewrite <-(lt_succ_pred 1 a LT) at 1.
apply log2_succ_le.
+ apply lt_succ_r; order.
- rewrite <- EQ, <- two_succ, log2_up_1, log2_up_2. now nzsimpl'.
- rewrite 2 log2_up_eqn0. + order_pos. + order'. + now rewrite le_succ_l.
Qed.
Lemma log2_up_succ_or : forall a,
log2_up (S a) == S (log2_up a) \/ log2_up (S a) == log2_up a.
Proof.
intros a.
destruct (le_gt_cases (log2_up (S a)) (log2_up a)) as [H|H].
- right. generalize (log2_up_le_mono _ _ (le_succ_diag_r a)); order.
- left. apply le_succ_l in H. generalize (log2_up_succ_le a); order.
Qed.
Lemma log2_up_eq_succ_is_pow2 : forall a,
log2_up (S a) == S (log2_up a) -> exists b, a == 2^b.
Proof.
intros a H.
destruct (le_gt_cases a 0) as [Ha|Ha].
- rewrite 2 (proj2 (log2_up_null _)) in H. + generalize (lt_succ_diag_r 0); order.
+ order'. + apply le_succ_l. order'.
- assert (Ha' : 1 < S a) by (now rewrite one_succ, <- succ_lt_mono).
exists (log2_up a).
generalize (proj1 (log2_up_spec (S a) Ha')) (proj2 (log2_log2_up_spec a Ha)).
rewrite H, pred_succ, lt_succ_r. order.
Qed.
Lemma log2_up_eq_succ_iff_pow2 : forall a, 0<a ->
(log2_up (S a) == S (log2_up a) <-> exists b, a == 2^b).
Proof.
intros a Ha.
split. - apply log2_up_eq_succ_is_pow2.
- intros (b,Hb).
destruct (lt_ge_cases b 0) as [Hb'|Hb'].
+ rewrite pow_neg_r in Hb; order.
+ rewrite Hb, log2_up_pow2; try order'.
now rewrite log2_up_succ_pow2.
Qed.
Lemma log2_up_succ_double : forall a, 0<a ->
log2_up (2*a+1) == 2 + log2 a.
Proof.
intros a Ha.
rewrite log2_up_eqn. - rewrite add_1_r, pred_succ, log2_double; now nzsimpl'.
- apply le_lt_trans with (0+1). + now nzsimpl'.
+ apply add_lt_mono_r. order_pos.
Qed.
(** [log2_up] and addition *)
Lemma log2_up_add_le : forall a b, a~=1 -> b~=1 ->
log2_up (a+b) <= log2_up a + log2_up b.
Proof.
intros a b Ha Hb.
destruct (lt_trichotomy a 1) as [Ha'|[Ha'|Ha']]; [|order|].
- rewrite (log2_up_eqn0 a) by order. nzsimpl. apply log2_up_le_mono.
rewrite one_succ, lt_succ_r in Ha'.
rewrite <- (add_0_l b) at 2. now apply add_le_mono.
- destruct (lt_trichotomy b 1) as [Hb'|[Hb'|Hb']]; [|order|].
+ rewrite (log2_up_eqn0 b) by order. nzsimpl. apply log2_up_le_mono.
rewrite one_succ, lt_succ_r in Hb'.
rewrite <- (add_0_r a) at 2. now apply add_le_mono.
+ clear Ha Hb.
transitivity (log2_up (a*b)).
* now apply log2_up_le_mono, add_le_mul.
* apply log2_up_mul_above; order'.
Qed.
(** The sum of two [log2_up] is less than twice the [log2_up] of the sum.
The large inequality is obvious thanks to monotonicity.
The strict one requires some more work. This is almost
a convexity inequality for points [2a], [2b] and their middle [a+b] :
ideally, we would have [2*log(a+b) >= log(2a)+log(2b) = 2+log a+log b].
Here, we cannot do better: consider for instance a=3 b=5, then 2+3<2*3
*)
Lemma add_log2_up_lt : forall a b, 0<a -> 0<b ->
log2_up a + log2_up b < 2 * log2_up (a+b).
Proof.
intros a b Ha Hb. nzsimpl'.
assert (H : log2_up a <= log2_up (a+b)).
- apply log2_up_le_mono. rewrite <- (add_0_r a) at 1. apply add_le_mono; order.
- assert (H' : log2_up b <= log2_up (a+b)).
+ apply log2_up_le_mono. rewrite <- (add_0_l b) at 1. apply add_le_mono; order.
+ le_elim H.
* apply lt_le_trans with (log2_up (a+b) + log2_up b).
-- now apply add_lt_mono_r. -- now apply add_le_mono_l.
* rewrite <- H at 1. apply add_lt_mono_l.
le_elim H'. -- trivial.
-- symmetry in H. apply log2_up_same in H; try order_pos.
symmetry in H'. apply log2_up_same in H'; try order_pos.
revert H H'. nzsimpl'. rewrite <- add_lt_mono_l, <- add_lt_mono_r; order.
Qed.
End NZLog2UpProp.
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 05/11/2009
Version 2.0
This logic recieves registers the byte address of the master when 'start'
is asserted. This block then barrelshifts the write data based on the byte
address to make sure that the input data (from the FIFO) is reformatted to
line up with memory properly.
The only throttling mechanism in this block is the FIFO not empty signal as
well as waitreqeust from the fabric.
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address to determine how
much out of alignment the master begins.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
//included for synthesis
`include "~/ee577b/syn/src/control.h"
/*
*ALU Functions Included (in order coded below):
* mules
* mulos
* muleu
* mulou
*/
module alu_mult(reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
// Input signals
input [0:127] reg_A;
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
input [0:4] alu_op;
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
// Declare "reg" signals:
reg [0:127] result;
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
integer sgn;
integer i;
integer j;
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// !!TROY PART 2 START!!
// ======================================================
// Signed Multiplication - even subfields
`aluwmules:
begin
case(ctrl_ww)
(`w8+2'b1): // aluwmules AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[0:7];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[0:7];
if(reg_B[0]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[0:7];
end
else
begin
p_pdt8a2[8:15]=reg_B[0:7];
end
end
else
begin
p_pdt8a[8:15]=reg_A[0:7];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]<=1+~p_pdt[0:15];
end
else
begin
result[0:15]<=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[16:23];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[16:23];
if(reg_B[16]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[16:23];
end
else
begin
p_pdt8b2[8:15]=reg_B[16:23];
end
end
else
begin
p_pdt8b[8:15]=reg_A[16:23];
end
p_pdt8b[0:7]=8'd0;
$display("p_pdt8b[0:15]",p_pdt8b[0:15]);
$display("p_pdt8b2[0:15]",p_pdt8b2[0:15]);
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
$display("p_pdt[16:31]",p_pdt[16:31]);
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
$display("MINUSp_pdt[16:31]",p_pdt[16:31]);
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
$display("ADDp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
$display("ZEROp_pdt[16:31]",p_pdt[16:31]);
end
end
if(p_pdt8b[8]==1'd1)
begin
result[16:31]<=1+~p_pdt[16:31];
$display("INVp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
result[16:31]<=p_pdt[16:31];
$display("RESp_pdt[16:31]",p_pdt[16:31]);
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[32:39];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[32:39];
if(reg_B[32]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[32:39];
end
else
begin
p_pdt8c2[8:15]=reg_B[32:39];
end
end
else
begin
p_pdt8c[8:15]=reg_A[32:39];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]<=1+~p_pdt[32:47];
end
else
begin
result[32:47]<=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[48:55];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[48:55];
if(reg_B[48]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[48:55];
end
else
begin
p_pdt8d2[8:15]=reg_B[48:55];
end
end
else
begin
p_pdt8d[8:15]=reg_A[48:55];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]<=1+~p_pdt[48:63];
end
else
begin
result[48:63]<=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[64:71];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[64:71];
if(reg_B[64]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[64:71];
end
else
begin
p_pdt8e2[8:15]=reg_B[64:71];
end
end
else
begin
p_pdt8e[8:15]=reg_A[64:71];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]<=1+~p_pdt[64:79];
end
else
begin
result[64:79]<=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[80:87];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[80:87];
if(reg_B[80]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[80:87];
end
else
begin
p_pdt8f2[8:15]=reg_B[80:87];
end
end
else
begin
p_pdt8f[8:15]=reg_A[80:87];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]<=1+~p_pdt[80:95];
end
else
begin
result[80:95]<=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[96:103];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[96:103];
if(reg_B[96]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[96:103];
end
else
begin
p_pdt8g2[8:15]=reg_B[96:103];
end
end
else
begin
p_pdt8g[8:15]=reg_A[96:103];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]<=1+~p_pdt[96:111];
end
else
begin
result[96:111]<=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[112:119];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[112:119];
if(reg_B[112]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[112:119];
end
else
begin
p_pdt8h2[8:15]=reg_B[112:119];
end
end
else
begin
p_pdt8h[8:15]=reg_A[112:119];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]<=1+~p_pdt[112:127];
end
else
begin
result[112:127]<=p_pdt[112:127];
end
// =======================================================
// =======================================================
// =======================================================
end
(`w16+2'b1): // aluwmules AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[0:15];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[0:15];
if(reg_B[0]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[0:15];
end
else
begin
p_pdt16a2[16:31]=reg_B[0:15];
end
end
else
begin
p_pdt16a[16:31]=reg_A[0:15];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]<=1+~p_pdt[0:31];
end
else
begin
result[0:31]<=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[32:47];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[32:47];
if(reg_B[32]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[32:47];
end
else
begin
p_pdt16b2[16:31]=reg_B[32:47];
end
end
else
begin
p_pdt16b[16:31]=reg_A[0:15];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]<=1+~p_pdt[32:63];
end
else
begin
result[32:63]<=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[64:79];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[64:79];
if(reg_B[64]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[64:79];
end
else
begin
p_pdt16c2[16:31]=reg_B[64:79];
end
end
else
begin
p_pdt16c[16:31]=reg_A[64:79];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]<=1+~p_pdt[64:95];
end
else
begin
result[64:95]<=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[96:111];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[96:111];
if(reg_B[96]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[96:111];
end
else
begin
p_pdt16d2[16:31]=reg_B[96:111];
end
end
else
begin
p_pdt16d[16:31]=reg_A[96:111];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]<=1+~p_pdt[96:127];
end
else
begin
result[96:127]<=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// Signed Multiplication - odd subfields
`aluwmulos:
begin
case(ctrl_ww)
(`w8+2'b1): // aluwmulos AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[8:15];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[8]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[8:15];
if(reg_B[8]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[8:15];
end
else
begin
p_pdt8a2[8:15]=reg_B[8:15];
end
end
else
begin
p_pdt8a[8:15]=reg_A[8:15];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]<=1+~p_pdt[0:15];
end
else
begin
result[0:15]<=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[24:31];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[24]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[24:31];
if(reg_B[24]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[24:31];
end
else
begin
p_pdt8b2[8:15]=reg_B[24:31];
end
end
else
begin
p_pdt8b[8:15]=reg_A[24:31];
end
p_pdt8b[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
end
if(p_pdt8b[8]==1'd1)
begin
result[16:31]<=1+~p_pdt[16:31];
end
else
begin
result[16:31]<=p_pdt[16:31];
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[40:47];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[40]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[40:47];
if(reg_B[40]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[40:47];
end
else
begin
p_pdt8c2[8:15]=reg_B[40:47];
end
end
else
begin
p_pdt8c[8:15]=reg_A[40:47];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]<=1+~p_pdt[32:47];
end
else
begin
result[32:47]<=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[56:63];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[56]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[56:63];
if(reg_B[56]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[56:63];
end
else
begin
p_pdt8d2[8:15]=reg_B[56:63];
end
end
else
begin
p_pdt8d[8:15]=reg_A[56:63];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]<=1+~p_pdt[48:63];
end
else
begin
result[48:63]<=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[72:79];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[72]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[72:79];
if(reg_B[72]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[72:79];
end
else
begin
p_pdt8e2[8:15]=reg_B[72:79];
end
end
else
begin
p_pdt8e[8:15]=reg_A[72:79];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]<=1+~p_pdt[64:79];
end
else
begin
result[64:79]<=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[88:95];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[88]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[88:95];
if(reg_B[88]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[88:95];
end
else
begin
p_pdt8f2[8:15]=reg_B[88:95];
end
end
else
begin
p_pdt8f[8:15]=reg_A[88:95];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]<=1+~p_pdt[80:95];
end
else
begin
result[80:95]<=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[104:111];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[104]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[104:111];
if(reg_B[104]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[104:111];
end
else
begin
p_pdt8g2[8:15]=reg_B[104:111];
end
end
else
begin
p_pdt8g[8:15]=reg_A[104:111];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]<=1+~p_pdt[96:111];
end
else
begin
result[96:111]<=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[120:127];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[120]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[120:127];
if(reg_B[120]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[120:127];
end
else
begin
p_pdt8h2[8:15]=reg_B[120:127];
end
end
else
begin
p_pdt8h[8:15]=reg_A[120:127];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]<=1+~p_pdt[112:127];
end
else
begin
result[112:127]<=p_pdt[112:127];
end
// ---------------------------------------
end
(`w16+2'b1): // aluwmulos AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[16:31];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[16:31];
if(reg_B[16]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[16:31];
end
else
begin
p_pdt16a2[16:31]=reg_B[16:31];
end
end
else
begin
p_pdt16a[16:31]=reg_A[16:31];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]<=1+~p_pdt[0:31];
end
else
begin
result[0:31]<=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[48:63];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[48:63];
if(reg_B[48]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[48:63];
end
else
begin
p_pdt16b2[16:31]=reg_B[48:63];
end
end
else
begin
p_pdt16b[16:31]=reg_A[48:63];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]<=1+~p_pdt[32:63];
end
else
begin
result[32:63]<=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[80:95];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[80:95];
if(reg_B[80]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[80:95];
end
else
begin
p_pdt16c2[16:31]=reg_B[80:95];
end
end
else
begin
p_pdt16c[16:31]=reg_A[80:95];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]<=1+~p_pdt[64:95];
end
else
begin
result[64:95]<=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[112:127];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[112:127];
if(reg_B[112]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[112:127];
end
else
begin
p_pdt16d2[16:31]=reg_B[112:127];
end
end
else
begin
p_pdt16d[16:31]=reg_A[112:127];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]<=1+~p_pdt[96:127];
end
else
begin
result[96:127]<=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result<=128'd0;
end
endcase
end
// ===========================================
// Unsigned Multiplication - even subfields
`aluwmuleu:
begin
case(ctrl_ww)
(`w8+2'b1):
begin
// 1st even byte
// extend operand B
p_pdt8a2={{8{1'b0}},reg_B[0+(16*0):7+(16*0)]};
// extend operand A
p_pdt8a={{8{1'b0}},reg_A[0+(16*0):7+(16*0)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*0):15+(16*0)]=p_pdt[0+(16*0):15+(16*0)]
+ (p_pdt8a[i]?(p_pdt8a2<<(8'd15-i)):16'b0);
// 2nd even byte
// extend operand B
p_pdt8b2={{8{1'b0}},reg_B[0+(16*1):7+(16*1)]};
// extend operand A
p_pdt8b={{8{1'b0}},reg_A[0+(16*1):7+(16*1)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*1):15+(16*1)]=p_pdt[0+(16*1):15+(16*1)]
+ (p_pdt8b[i]?(p_pdt8b2<<(8'd15-i)):16'b0);
// 3rd even byte
// extend operand B
p_pdt8c2={{8{1'b0}},reg_B[0+(16*2):7+(16*2)]};
// extend operand A
p_pdt8c={{8{1'b0}},reg_A[0+(16*2):7+(16*2)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*2):15+(16*2)]=p_pdt[0+(16*2):15+(16*2)]
+ (p_pdt8c[i]?(p_pdt8c2<<(8'd15-i)):16'b0);
// 4th even byte
// extend operand B
p_pdt8d2={{8{1'b0}},reg_B[0+(16*3):7+(16*3)]};
// extend operand A
p_pdt8d={{8{1'b0}},reg_A[0+(16*3):7+(16*3)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*3):15+(16*3)]=p_pdt[0+(16*3):15+(16*3)]
+ (p_pdt8d[i]?(p_pdt8d2<<(8'd15-i)):16'b0);
// 5th even byte
// extend operand B
p_pdt8e2={{8{1'b0}},reg_B[0+(16*4):7+(16*4)]};
// extend operand A
p_pdt8e={{8{1'b0}},reg_A[0+(16*4):7+(16*4)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*4):15+(16*4)]=p_pdt[0+(16*4):15+(16*4)]
+ (p_pdt8e[i]?(p_pdt8e2<<(8'd15-i)):16'b0);
// 6th even byte
// extend operand B
p_pdt8f2={{8{1'b0}},reg_B[0+(16*5):7+(16*5)]};
// extend operand A
p_pdt8f={{8{1'b0}},reg_A[0+(16*5):7+(16*5)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*5):15+(16*5)]=p_pdt[0+(16*5):15+(16*5)]
+ (p_pdt8f[i]?(p_pdt8f2<<(8'd15-i)):16'b0);
// 7th even byte
// extend operand B
p_pdt8g2={{8{1'b0}},reg_B[0+(16*6):7+(16*6)]};
// extend operand A
p_pdt8g={{8{1'b0}},reg_A[0+(16*6):7+(16*6)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*6):15+(16*6)]=p_pdt[0+(16*6):15+(16*6)]
+ (p_pdt8g[i]?(p_pdt8g2<<(8'd15-i)):16'b0);
// 8th even byte
// extend operand B
p_pdt8h2={{8{1'b0}},reg_B[0+(16*7):7+(16*7)]};
// extend operand A
p_pdt8h={{8{1'b0}},reg_A[0+(16*7):7+(16*7)]};
// i loops through each bit to compute sum of partial products
for (i=15; i>7; i=i-1)
p_pdt[0+(16*7):15+(16*7)]=p_pdt[0+(16*7):15+(16*7)]
+ (p_pdt8h[i]?(p_pdt8h2<<(8'd15-i)):16'b0);
result<=p_pdt;
end // case (`w8+2'b1)
(`w16+2'b1):
begin
// 1st word
// extend operand B
p_pdt16a2={{16{1'b0}},reg_B[0+(32*0):15+(32*0)]};
// extend operand A
p_pdt16a={{16{1'b0}},reg_A[0+(32*0):15+(32*0)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*0):31+(32*0)]=p_pdt[0+(32*0):31+(32*0)]
+ (p_pdt16a[i]?(p_pdt16a2<<(8'd31-i)):32'b0);
// 2nd word
// extend operand B
p_pdt16b2={{16{1'b0}},reg_B[0+(32*1):15+(32*1)]};
// extend operand A
p_pdt16b={{16{1'b0}},reg_A[0+(32*1):15+(32*1)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*1):31+(32*1)]=p_pdt[0+(32*1):31+(32*1)]
+ (p_pdt16b[i]?(p_pdt16b2<<(8'd31-i)):32'b0);
// 3rd word
// extend operand B
p_pdt16c2={{16{1'b0}},reg_B[0+(32*2):15+(32*2)]};
// extend operand A
p_pdt16c={{16{1'b0}},reg_A[0+(32*2):15+(32*2)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*2):31+(32*2)]=p_pdt[0+(32*2):31+(32*2)]
+ (p_pdt16c[i]?(p_pdt16c2<<(8'd31-i)):32'b0);
// 4th word
// extend operand B
p_pdt16d2={{16{1'b0}},reg_B[0+(32*3):15+(32*3)]};
// extend operand A
p_pdt16d={{16{1'b0}},reg_A[0+(32*3):15+(32*3)]};
// i loops through each bit to compute sum due to partial products
for (i=31; i>15; i=i-1)
p_pdt[0+(32*3):31+(32*3)]=p_pdt[0+(32*3):31+(32*3)]
+ (p_pdt16d[i]?(p_pdt16d2<<(8'd31-i)):32'b0);
result<=p_pdt;
end // case (`w16+2'b1)
default:
begin
result<=128'd0;
end
endcase // case(ctrl_ww)
end
// ===================================
// Unsigned Multiplication - odd subfields
`aluwmulou:
begin
case(ctrl_ww)
(`w8+2'd1): // aluwmulou AND `w8
begin
p_pdt8a[8:15]=reg_A[8:15];
p_pdt8a[0:7]=8'd0;
p_pdt8a2[0:15]={{8{1'b0}},reg_B[8:15]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[0:15]=p_pdt[0:15]+((p_pdt8a[sgn]==1'd1)?(p_pdt8a2<<(8'd15-sgn)):16'b0);
end
p_pdt8b[8:15]=reg_A[24:31];
p_pdt8b[0:7]=8'd0;
p_pdt8b2[0:15]={{8{1'b0}},reg_B[24:31]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[16:31]=p_pdt[16:31]+((p_pdt8b[sgn]==1'd1)?(p_pdt8b2<<(8'd15-sgn)):16'b0);
end
p_pdt8c[8:15]=reg_A[40:47];
p_pdt8c[0:7]=8'd0;
p_pdt8c2[0:15]={{8{1'b0}},reg_B[40:47]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[32:47]=p_pdt[32:47]+((p_pdt8c[sgn]==1'd1)?(p_pdt8c2<<(8'd15-sgn)):16'b0);
end
p_pdt8d[8:15]=reg_A[56:63];
p_pdt8d[0:7]=8'd0;
p_pdt8d2[0:15]={{8{1'b0}},reg_B[56:63]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[48:63]=p_pdt[48:63]+((p_pdt8d[sgn]==1'd1)?(p_pdt8d2<<(8'd15-sgn)):16'b0);
end
p_pdt8e[8:15]=reg_A[72:79];
p_pdt8e[0:7]=8'd0;
p_pdt8e2[0:15]={{8{1'b0}},reg_B[72:79]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[64:79]=p_pdt[64:79]+((p_pdt8e[sgn]==1'd1)?(p_pdt8e2<<(8'd15-sgn)):16'b0);
end
p_pdt8f[8:15]=reg_A[88:95];
p_pdt8f[0:7]=8'd0;
p_pdt8f2[0:15]={{8{1'b0}},reg_B[88:95]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[80:95]=p_pdt[80:95]+((p_pdt8f[sgn]==1'd1)?(p_pdt8f2<<(8'd15-sgn)):16'b0);
end
p_pdt8g[8:15]=reg_A[104:111];
p_pdt8g[0:7]=8'd0;
p_pdt8g2[0:15]={{8{1'b0}},reg_B[104:111]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[96:111]=p_pdt[96:111]+((p_pdt8g[sgn]==1'd1)?(p_pdt8g2<<(8'd15-sgn)):16'b0);
end
p_pdt8h[8:15]=reg_A[120:127];
p_pdt8h[0:7]=8'd0;
p_pdt8h2[0:15]={{8{1'b0}},reg_B[120:127]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[112:127]=p_pdt[112:127]+((p_pdt8h[sgn]==1'd1)?(p_pdt8h2<<(8'd15-sgn)):16'b0);
end
result<=p_pdt;
end
(`w16+2'b01): // aluwmulou AND `w16
begin
p_pdt16a[0:31]={{16{1'b0}},reg_B[16:31]};
p_pdt16a2[0:31]={{16{1'b0}},reg_A[16:31]};
p_pdt16b[0:31]={{16{1'b0}},reg_B[48:63]};
p_pdt16b2[0:31]={{16{1'b0}},reg_A[48:63]};
p_pdt16c[0:31]={{16{1'b0}},reg_B[80:95]};
p_pdt16c2[0:31]={{16{1'b0}},reg_A[80:95]};
p_pdt16d[0:31]={{16{1'b0}},reg_B[112:127]};
p_pdt16d2[0:31]={{16{1'b0}},reg_A[112:127]};
for(sgn=31; sgn>=16; sgn=sgn-1)
begin
p_pdt[0:31]=p_pdt[0:31]+((p_pdt16a[sgn]==1'd1)?(p_pdt16a2<<(16'd31-sgn)):32'd0);
p_pdt[32:63]=p_pdt[32:63]+((p_pdt16b[sgn]==1'd1)?(p_pdt16b2<<(16'd31-sgn)):32'd0);
p_pdt[64:95]=p_pdt[64:95]+((p_pdt16c[sgn]==1'd1)?(p_pdt16c2<<(16'd31-sgn)):32'd0);
p_pdt[96:127]=p_pdt[96:127]+((p_pdt16d[sgn]==1'd1)?(p_pdt16d2<<(16'd31-sgn)):32'd0);
end
result<=p_pdt;
end
default: // aluwmulou AND Default
begin
result<=128'd0;
end
endcase
end
// !!TROY PART 2 END!!
// ==================================================================
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
/*
* VGA top level file
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga (
// Wishbone signals
input wb_clk_i, // 25 Mhz VDU clock
input wb_rst_i,
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
input [16:1] wb_adr_i,
input wb_we_i,
input wb_tga_i,
input [ 1:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
output wb_ack_o,
// VGA pad signals
output [ 3:0] vga_red_o,
output [ 3:0] vga_green_o,
output [ 3:0] vga_blue_o,
output horiz_sync,
output vert_sync,
// CSR SRAM master interface
output [17:1] csrm_adr_o,
output [ 1:0] csrm_sel_o,
output csrm_we_o,
output [15:0] csrm_dat_o,
input [15:0] csrm_dat_i
);
// Registers and nets
//
// csr address
reg [17:1] csr_adr_i;
reg csr_stb_i;
// Config wires
wire [15:0] conf_wb_dat_o;
wire conf_wb_ack_o;
// Mem wires
wire [15:0] mem_wb_dat_o;
wire mem_wb_ack_o;
// LCD wires
wire [17:1] csr_adr_o;
wire [15:0] csr_dat_i;
wire csr_stb_o;
wire v_retrace;
wire vh_retrace;
wire w_vert_sync;
// VGA configuration registers
wire shift_reg1;
wire graphics_alpha;
wire memory_mapping1;
wire [ 1:0] write_mode;
wire [ 1:0] raster_op;
wire read_mode;
wire [ 7:0] bitmask;
wire [ 3:0] set_reset;
wire [ 3:0] enable_set_reset;
wire [ 3:0] map_mask;
wire x_dotclockdiv2;
wire chain_four;
wire [ 1:0] read_map_select;
wire [ 3:0] color_compare;
wire [ 3:0] color_dont_care;
// Wishbone master to SRAM
wire [17:1] wbm_adr_o;
wire [ 1:0] wbm_sel_o;
wire wbm_we_o;
wire [15:0] wbm_dat_o;
wire [15:0] wbm_dat_i;
wire wbm_stb_o;
wire wbm_ack_i;
wire stb;
// CRT wires
wire [ 5:0] cur_start;
wire [ 5:0] cur_end;
wire [15:0] start_addr;
wire [ 4:0] vcursor;
wire [ 6:0] hcursor;
wire [ 6:0] horiz_total;
wire [ 6:0] end_horiz;
wire [ 6:0] st_hor_retr;
wire [ 4:0] end_hor_retr;
wire [ 9:0] vert_total;
wire [ 9:0] end_vert;
wire [ 9:0] st_ver_retr;
wire [ 3:0] end_ver_retr;
// attribute_ctrl wires
wire [3:0] pal_addr;
wire pal_we;
wire [7:0] pal_read;
wire [7:0] pal_write;
// dac_regs wires
wire dac_we;
wire [1:0] dac_read_data_cycle;
wire [7:0] dac_read_data_register;
wire [3:0] dac_read_data;
wire [1:0] dac_write_data_cycle;
wire [7:0] dac_write_data_register;
wire [3:0] dac_write_data;
// Module instances
//
vga_config_iface config_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (conf_wb_dat_o),
.wb_adr_i (wb_adr_i[4:1]),
.wb_we_i (wb_we_i),
.wb_sel_i (wb_sel_i),
.wb_stb_i (stb & wb_tga_i),
.wb_ack_o (conf_wb_ack_o),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.x_dotclockdiv2 (x_dotclockdiv2),
.chain_four (chain_four),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.cur_start (cur_start),
.cur_end (cur_end),
.start_addr (start_addr),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_lcd lcd (
.clk (wb_clk_i),
.rst (wb_rst_i),
.shift_reg1 (shift_reg1),
.graphics_alpha (graphics_alpha),
.pal_addr (pal_addr),
.pal_we (pal_we),
.pal_read (pal_read),
.pal_write (pal_write),
.dac_we (dac_we),
.dac_read_data_cycle (dac_read_data_cycle),
.dac_read_data_register (dac_read_data_register),
.dac_read_data (dac_read_data),
.dac_write_data_cycle (dac_write_data_cycle),
.dac_write_data_register (dac_write_data_register),
.dac_write_data (dac_write_data),
.csr_adr_o (csr_adr_o),
.csr_dat_i (csr_dat_i),
.csr_stb_o (csr_stb_o),
.vga_red_o (vga_red_o),
.vga_green_o (vga_green_o),
.vga_blue_o (vga_blue_o),
.horiz_sync (horiz_sync),
.vert_sync (w_vert_sync),
.cur_start (cur_start),
.cur_end (cur_end),
.vcursor (vcursor),
.hcursor (hcursor),
.horiz_total (horiz_total),
.end_horiz (end_horiz),
.st_hor_retr (st_hor_retr),
.end_hor_retr (end_hor_retr),
.vert_total (vert_total),
.end_vert (end_vert),
.st_ver_retr (st_ver_retr),
.end_ver_retr (end_ver_retr),
.x_dotclockdiv2 (x_dotclockdiv2),
.v_retrace (v_retrace),
.vh_retrace (vh_retrace)
);
vga_cpu_mem_iface cpu_mem_iface (
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.wbs_adr_i (wb_adr_i),
.wbs_sel_i (wb_sel_i),
.wbs_we_i (wb_we_i),
.wbs_dat_i (wb_dat_i),
.wbs_dat_o (mem_wb_dat_o),
.wbs_stb_i (stb & !wb_tga_i),
.wbs_ack_o (mem_wb_ack_o),
.wbm_adr_o (wbm_adr_o),
.wbm_sel_o (wbm_sel_o),
.wbm_we_o (wbm_we_o),
.wbm_dat_o (wbm_dat_o),
.wbm_dat_i (wbm_dat_i),
.wbm_stb_o (wbm_stb_o),
.wbm_ack_i (wbm_ack_i),
.chain_four (chain_four),
.memory_mapping1 (memory_mapping1),
.write_mode (write_mode),
.raster_op (raster_op),
.read_mode (read_mode),
.bitmask (bitmask),
.set_reset (set_reset),
.enable_set_reset (enable_set_reset),
.map_mask (map_mask),
.read_map_select (read_map_select),
.color_compare (color_compare),
.color_dont_care (color_dont_care)
);
vga_mem_arbitrer mem_arbitrer (
.clk_i (wb_clk_i),
.rst_i (wb_rst_i),
.wb_adr_i (wbm_adr_o),
.wb_sel_i (wbm_sel_o),
.wb_we_i (wbm_we_o),
.wb_dat_i (wbm_dat_o),
.wb_dat_o (wbm_dat_i),
.wb_stb_i (wbm_stb_o),
.wb_ack_o (wbm_ack_i),
.csr_adr_i (csr_adr_i),
.csr_dat_o (csr_dat_i),
.csr_stb_i (csr_stb_i),
.csrm_adr_o (csrm_adr_o),
.csrm_sel_o (csrm_sel_o),
.csrm_we_o (csrm_we_o),
.csrm_dat_o (csrm_dat_o),
.csrm_dat_i (csrm_dat_i)
);
// Continous assignments
assign wb_dat_o = wb_tga_i ? conf_wb_dat_o : mem_wb_dat_o;
assign wb_ack_o = wb_tga_i ? conf_wb_ack_o : mem_wb_ack_o;
assign stb = wb_stb_i & wb_cyc_i;
assign vert_sync = ~graphics_alpha ^ w_vert_sync;
// Behaviour
// csr_adr_i
always @(posedge wb_clk_i)
csr_adr_i <= wb_rst_i ? 17'h0 : csr_adr_o + start_addr[15:1];
// csr_stb_i
always @(posedge wb_clk_i)
csr_stb_i <= wb_rst_i ? 1'b0 : csr_stb_o;
endmodule
|
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
parameter ADDR_WIDTH = 4;
parameter N = ADDR_WIDTH-1;
parameter Q1 = 2'b00;
parameter Q2 = 2'b01;
parameter Q3 = 2'b11;
parameter Q4 = 2'b10;
parameter going_empty = 1'b0;
parameter going_full = 1'b1;
input [N:0] wptr, rptr;
output reg fifo_empty, fifo_full;
input wclk, rclk, rst;
reg direction, direction_set, direction_clr;
wire async_empty, async_full;
reg fifo_full2, fifo_empty2;
// direction_set
always @ (wptr[N:N-1] or rptr[N:N-1])
case ({wptr[N:N-1],rptr[N:N-1]})
{Q1,Q2} : direction_set <= 1'b1;
{Q2,Q3} : direction_set <= 1'b1;
{Q3,Q4} : direction_set <= 1'b1;
{Q4,Q1} : direction_set <= 1'b1;
default : direction_set <= 1'b0;
endcase
// direction_clear
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
if (rst)
direction_clr <= 1'b1;
else
case ({wptr[N:N-1],rptr[N:N-1]})
{Q2,Q1} : direction_clr <= 1'b1;
{Q3,Q2} : direction_clr <= 1'b1;
{Q4,Q3} : direction_clr <= 1'b1;
{Q1,Q4} : direction_clr <= 1'b1;
default : direction_clr <= 1'b0;
endcase
always @ (posedge direction_set or posedge direction_clr)
if (direction_clr)
direction <= going_empty;
else
direction <= going_full;
assign async_empty = (wptr == rptr) && (direction==going_empty);
assign async_full = (wptr == rptr) && (direction==going_full);
always @ (posedge wclk or posedge rst or posedge async_full)
if (rst)
{fifo_full, fifo_full2} <= 2'b00;
else if (async_full)
{fifo_full, fifo_full2} <= 2'b11;
else
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
always @ (posedge rclk or posedge async_empty)
if (async_empty)
{fifo_empty, fifo_empty2} <= 2'b11;
else
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty};
endmodule // async_comp
|
/*
* NAME
*
* regr - register of data that can be held or cleared
*
* DESCRIPTION
*
* The regr (register) module can be used to store data in the current
* cylcle so it will be output on the next cycle. Signals are also
* provided to hold the data or clear it. The hold and clear signals
* are both synchronous with the clock.
*
* The first example creates a 8-bit register. The clear and hold
* signals are taken from elsewhere.
*
* wire [7:0] data_s1;
* wire [7:0] data_s2;
*
* regr #(.N(8)) r1(.clk(clk), .clear(clear), .hold(hold),
* .in(data_s1), .out(data_s2))
*
* Multiple signals can be grouped together using array notation.
*
* regr #(.N(8)) r1(.clk(clk), .clear(clear), .hold(hold),
* .in({x1, x2}), .out({y1, y2}))
*/
`ifndef _regr
`define _regr
module regr (
input clk,
input clear,
input hold,
input wire [N-1:0] in,
output reg [N-1:0] out);
parameter N = 1;
always @(posedge clk) begin
if (clear)
out <= {N{1'b0}};
else if (hold)
out <= out;
else
out <= in;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_IO__TOP_REFGEN_NEW_PP_SYMBOL_V
`define SKY130_FD_IO__TOP_REFGEN_NEW_PP_SYMBOL_V
/**
* top_refgen_new: The REFGEN block (sky130_fd_io__top_refgen) is used
* to provide the input trip point (VINREF) for the
* differential input buffer in SIO and also
* the output buffer regulated output level (VOUTREF).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_io__top_refgen_new (
//# {{data|Data Signals}}
input DFT_REFGEN ,
//# {{control|Control Signals}}
inout AMUXBUS_A ,
inout AMUXBUS_B ,
input ENABLE_H ,
input ENABLE_VDDA_H,
input HLD_H_N ,
input IBUF_SEL ,
//# {{power|Power}}
input [2:0] VOH_SEL ,
input [1:0] VREF_SEL ,
input VREG_EN ,
input VTRIP_SEL ,
inout VSWITCH ,
inout REFLEAK_BIAS ,
inout VCCD ,
inout VCCHIB ,
inout VDDA ,
inout VDDIO ,
inout VDDIO_Q ,
output VINREF ,
inout VINREF_DFT ,
input VOHREF ,
output VOUTREF ,
inout VOUTREF_DFT ,
inout VSSA ,
inout VSSD ,
inout VSSIO ,
inout VSSIO_Q
);
endmodule
`default_nettype wire
`endif // SKY130_FD_IO__TOP_REFGEN_NEW_PP_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIeGen2x8If128_axi_basic_rx.v
// Version : 3.2
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module PCIeGen2x8If128_axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [KEEP_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
PCIeGen2x8If128_axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
PCIeGen2x8If128_axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
/*
*
*12bit PWM analog output module.
*Interface bit width is 16bit stereo.
*Input source require dcfifo altera megafunction.
*Clock input 196.608MHz, Output Sampling Frequency 48kHz.
*
*/
module pwm_out(
input wire clk,
input wire reset_n,
output reg fifo_rdreq,
input wire fifo_empty,
input wire [31:0] fifo_data,
output wire pwm_out_l,
output wire pwm_out_r);
reg data_rdy;
reg [11:0] pwm_timer;
reg [31:0] audiodata_32, audiodata_32_p;
always @(posedge clk, negedge reset_n)
begin
if(!reset_n)
begin
pwm_timer <= 0;
fifo_rdreq <= 0;
audiodata_32 <= 0;
audiodata_32_p <= 0;
data_rdy <= 0;
end
else
begin
pwm_timer <= pwm_timer + 1'b1;
if(pwm_timer == 12'h800 && fifo_empty == 0)
begin
fifo_rdreq <= 1'b1;
end
if(pwm_timer == 12'h801 && fifo_rdreq == 1)
begin
fifo_rdreq <= 0;
audiodata_32_p <= fifo_data;
data_rdy <= 1'b1;
end
if(pwm_timer == 12'hfff && data_rdy == 1)
begin
audiodata_32 <= audiodata_32_p;
data_rdy <= 0;
end
end
end
assign pwm_out_l = (pwm_timer <= audiodata_32[15:4]) ? 1'b1 :
(pwm_timer > audiodata_32[15:4]) ? 1'b0 : 1'bx;
assign pwm_out_r = (pwm_timer <= audiodata_32[31:20]) ? 1'b1 :
(pwm_timer > audiodata_32[31:20]) ? 1'b0 : 1'bx;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Primary Global Buffer for Driving Clocks or Long Lines
// /___/ /\ Filename : BUFGP.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:14 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFGP (O, I);
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
output O;
input I;
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
//----------------------------------------------------------------------------
// PLB INTERFACE - Sub Level Module
//-----------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
//----------------------------------------------------------------------------
// Filename: plb_if.v
//
// Description:
//
//
// Design Notes:
//
//-----------------------------------------------------------------------------
// Structure:
//
//-----------------------------------------------------------------------------
// Author: CJN
// History:
// CJN, MM 3/02 -- First Release
// CJN -- Second Release
//
//
//-----------------------------------------------------------------------------
///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 100 ps
module plb_if(
// PLB GLOBAL SIGNALS
clk, // I 100MHz
rst, // I
// REQUEST QUALIFIERS INPUTS
PLB_MnAddrAck, // I
Mn_request, // O
Mn_priority, // O [0:1]
Mn_RNW, // O
Mn_BE, // O [0:7]
Mn_size, // O [0:3]
Mn_type, // O [0:2]
Mn_MSize, // O [0:1]
Mn_ABus, // O [0:31]
// PLB READ DATA BUS
PLB_MnRdDAck, // I
PLB_MnRdWdAddr, // I
PLB_MnRdDBus, // I [0:63]
// PLB_BRAM CONTROL AND DATA
PLB_BRAM_data, // O [0:63]
PLB_BRAM_addr_lsb, // O [0:1]
PLB_BRAM_addr_en, // O
PLB_BRAM_we, // O
// GET_LINE PULSE
get_line, // I
// BASE ADDRESS
tft_base_addr, // I [0:10]
tft_on_reg // I
);
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// PLB GLOBAL SIGNALS
input clk;
input rst;
// REQUEST QUALIFIERS INPUTS
input PLB_MnAddrAck;
output Mn_request;
output [0:1] Mn_priority;
output Mn_RNW;
output [0:7] Mn_BE;
output [0:3] Mn_size;
output [0:2] Mn_type;
output [0:1] Mn_MSize;
output [0:31] Mn_ABus;
// PLB READ DATA BUS
input PLB_MnRdDAck;
input [0:3] PLB_MnRdWdAddr;
input [0:63] PLB_MnRdDBus;
// PLB_BRAM CONTROL AND DATA
output [0:63] PLB_BRAM_data;
output [0:1] PLB_BRAM_addr_lsb;
output PLB_BRAM_addr_en;
output PLB_BRAM_we;
// GET LINE PULSE
input get_line;
input [0:10] tft_base_addr;
input tft_on_reg;
///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////
reg [0:6] trans_cnt;
reg [0:6] trans_cnt_i;
wire trans_cnt_ce;
wire trans_cnt_tc;
reg [0:8] line_cnt;
reg [0:8] line_cnt_i;
wire line_cnt_ce;
wire end_xfer;
wire end_xfer_p1;
reg [0:63] PLB_BRAM_data;
reg [0:1] PLB_BRAM_addr_lsb;
reg PLB_BRAM_we;
reg [0:10] tft_base_addr_i;
wire skip_line;
reg skip_line_d1;
reg skip_plb_xfer;
reg skip_plb_xfer_d1;
reg skip_plb_xfer_d2;
reg skip_plb_xfer_d3;
reg skip_plb_xfer_d4;
reg dummy_rd_ack;
wire mn_request_set;
reg [0:3] data_xfer_shreg;
reg data_xfer_shreg1_d1;
////////////////////////////////////////////////////////////////////////////
// Tie off Constants
////////////////////////////////////////////////////////////////////////////
assign Mn_MSize = 2'b01; // 64 Bit PLB Xfers
assign Mn_priority = 2'b11; // Set priority to 3
assign Mn_size = 4'b0010; // Transfer 8-word line
assign Mn_type = 3'b000; // Memory type transfer
assign Mn_RNW = 1'b1; // Always read
assign Mn_BE = 8'b00000000; // Ignored on Line xfers
assign Mn_ABus[0:10] = tft_base_addr_i; // 11-bits
assign Mn_ABus[11:19] = line_cnt_i;
assign Mn_ABus[20:26] = trans_cnt_i;
assign Mn_ABus[27:31] = 5'b00000;
assign mn_request_set = tft_on_reg & ( (get_line & (trans_cnt == 0))
| (end_xfer & (trans_cnt != 0)));
FDRSE FDRS_MN_REQUEST_DLY (.Q(Mn_request),.CE(1'b0),.C(clk),.D(1'b0),
.R(PLB_MnAddrAck | rst), .S(mn_request_set));
always @(posedge clk)
begin
skip_plb_xfer <= ~tft_on_reg & ( (get_line & (trans_cnt == 0))
| (end_xfer & (trans_cnt != 0)));
skip_plb_xfer_d1 <= skip_plb_xfer;
skip_plb_xfer_d2 <= skip_plb_xfer_d1;
skip_plb_xfer_d3 <= skip_plb_xfer_d2;
skip_plb_xfer_d4 <= skip_plb_xfer_d3;
dummy_rd_ack <= skip_plb_xfer_d4 | skip_plb_xfer_d3 | skip_plb_xfer_d2 | skip_plb_xfer_d1;
end
always @(posedge clk)
if (mn_request_set) begin
tft_base_addr_i <= tft_base_addr;
line_cnt_i <= line_cnt;
trans_cnt_i <= trans_cnt;
end
always @(posedge clk)
begin
PLB_BRAM_data <= PLB_MnRdDBus;
PLB_BRAM_addr_lsb <= PLB_MnRdWdAddr[1:2];
PLB_BRAM_we <= PLB_MnRdDAck | dummy_rd_ack;
end
assign PLB_BRAM_addr_en = end_xfer;
always @(posedge clk)
if (rst | end_xfer)
data_xfer_shreg <= (end_xfer & (PLB_MnRdDAck | dummy_rd_ack))? 4'b0001 : 4'b0000;
else if (PLB_MnRdDAck | dummy_rd_ack)
data_xfer_shreg <= {data_xfer_shreg[1:3], 1'b1};
assign end_xfer = data_xfer_shreg[0];
always @(posedge clk)
data_xfer_shreg1_d1 <= data_xfer_shreg[1];
assign end_xfer_p1 = data_xfer_shreg[1] & ~data_xfer_shreg1_d1;
///////////////////////////////////////////////////////////////////////////////
// Transaction Counter - Counts 0-79 (d)
///////////////////////////////////////////////////////////////////////////////
assign trans_cnt_ce = end_xfer_p1;
assign trans_cnt_tc = (trans_cnt == 7'd79);
always @(posedge clk)
if(rst)
trans_cnt = 7'b0;
else if (trans_cnt_ce) begin
if (trans_cnt_tc)
trans_cnt = 7'b0;
else
trans_cnt = trans_cnt + 1;
end
///////////////////////////////////////////////////////////////////////////////
// Line Counter - Counts 0-479 (d)
///////////////////////////////////////////////////////////////////////////////
// increment line cnt if getline missed because prev plb xfers not complete
assign skip_line = get_line & (trans_cnt != 0);
always @(posedge clk)
skip_line_d1 <= skip_line & line_cnt_ce;
assign line_cnt_ce = end_xfer_p1 & trans_cnt_tc;
always @(posedge clk)
if (rst)
line_cnt = 9'b0;
else if (line_cnt_ce | skip_line | skip_line_d1) begin
if (line_cnt == 9'd479)
line_cnt = 9'b0;
else
line_cnt = line_cnt + 1;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire bit_in = crc[0];
wire [30:0] vec_in = crc[31:1];
wire [123:0] wide_in = {crc[59:0],~crc[63:0]};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire exp_bit_out; // From reference of t_embed1_child.v
wire exp_did_init_out; // From reference of t_embed1_child.v
wire [30:0] exp_vec_out; // From reference of t_embed1_child.v
wire [123:0] exp_wide_out; // From reference of t_embed1_child.v
wire got_bit_out; // From test of t_embed1_wrap.v
wire got_did_init_out; // From test of t_embed1_wrap.v
wire [30:0] got_vec_out; // From test of t_embed1_wrap.v
wire [123:0] got_wide_out; // From test of t_embed1_wrap.v
// End of automatics
// A non-embedded master
/* t_embed1_child AUTO_TEMPLATE(
.\(.*_out\) (exp_\1[]),
.is_ref (1'b1));
*/
t_embed1_child reference
(/*AUTOINST*/
// Outputs
.bit_out (exp_bit_out), // Templated
.vec_out (exp_vec_out[30:0]), // Templated
.wide_out (exp_wide_out[123:0]), // Templated
.did_init_out (exp_did_init_out), // Templated
// Inputs
.clk (clk),
.bit_in (bit_in),
.vec_in (vec_in[30:0]),
.wide_in (wide_in[123:0]),
.is_ref (1'b1)); // Templated
// The embeded comparison
/* t_embed1_wrap AUTO_TEMPLATE(
.\(.*_out\) (got_\1[]),
.is_ref (1'b0));
*/
t_embed1_wrap test
(/*AUTOINST*/
// Outputs
.bit_out (got_bit_out), // Templated
.vec_out (got_vec_out[30:0]), // Templated
.wide_out (got_wide_out[123:0]), // Templated
.did_init_out (got_did_init_out), // Templated
// Inputs
.clk (clk),
.bit_in (bit_in),
.vec_in (vec_in[30:0]),
.wide_in (wide_in[123:0]),
.is_ref (1'b0)); // Templated
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0,
got_wide_out !== exp_wide_out,
got_vec_out !== exp_vec_out,
got_bit_out !== exp_bit_out,
got_did_init_out !== exp_did_init_out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n",$time, cyc, crc, result,
got_vec_out, exp_vec_out);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
end
else if (cyc<90) begin
if (result != 64'h0) begin
$display("Bit mismatch, result=%x\n", result);
$stop;
end
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
//Child prints this: $write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: trellis.vh
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The reset_controller module will safely reset a single stage
// pipeline without using an asychronous reset (bleh). It is intended for use in
// the TX engines, where it will control the output stage of the engine, and
// provide a gracefull end-of-packet reset
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`define S_RC_IDLE 3'b001
`define S_RC_WAIT 3'b010
`define S_RC_ACTIVE 3'b100
`include "trellis.vh"
module reset_controller
#(parameter C_RST_COUNT = 10)
(
input CLK,
input RST_IN,
output DONE_RST,
output WAITING_RESET,
output RST_OUT,
input SIGNAL_RST,
input WAIT_RST,
input NEXT_CYC_RST);
localparam C_CLOG2_RST_COUNT = clog2s(C_RST_COUNT);
localparam C_CEIL2_RST_COUNT = 1 << C_CLOG2_RST_COUNT;
reg [2:0] _rState,rState;
wire [C_CLOG2_RST_COUNT:0] wRstCount;
assign DONE_RST = rState[0];
assign WAITING_RESET = rState[1] & NEXT_CYC_RST;
assign RST_OUT = rState[2];
counter
#(// Parameters
.C_MAX_VALUE (C_CEIL2_RST_COUNT),
.C_SAT_VALUE (C_CEIL2_RST_COUNT),
.C_RST_VALUE (C_CEIL2_RST_COUNT - C_RST_COUNT)
/*AUTOINSTPARAM*/)
rst_counter
(// Outputs
.VALUE (wRstCount),
// Inputs
.ENABLE (1'b1),
.RST_IN (~rState[2] | RST_IN),
/*AUTOINST*/
// Inputs
.CLK (CLK));
always @(posedge CLK) begin
if(RST_IN) begin
rState <= `S_RC_ACTIVE;
end else begin
rState <= _rState;
end
end
always @(*) begin
_rState = rState;
case(rState)
`S_RC_IDLE:begin
if(SIGNAL_RST & WAIT_RST) begin
_rState = `S_RC_WAIT;
end else if(SIGNAL_RST) begin
_rState = `S_RC_ACTIVE;
end
end
`S_RC_WAIT:begin
if(NEXT_CYC_RST) begin
_rState = `S_RC_ACTIVE;
end
end
`S_RC_ACTIVE:begin
if(wRstCount[C_CLOG2_RST_COUNT] & ~SIGNAL_RST) begin
_rState = `S_RC_IDLE;
end
end
default: _rState = rState;
endcase
end
endmodule
|
(** * ImpCEvalFun: Evaluation Function for Imp *)
(* $Date: 2013-07-01 18:48:47 -0400 (Mon, 01 Jul 2013) $ *)
(* #################################### *)
(** ** Evaluation Function *)
Require Import Imp.
(** Here's a first try at an evaluation function for commands,
omitting [WHILE]. *)
Fixpoint ceval_step1 (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step1 st c1 in
ceval_step1 st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step1 st c1
else ceval_step1 st c2
| WHILE b1 DO c1 END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the WHILE case as follows:
<<
| WHILE b1 DO c1 END =>
if (beval st b1)
then ceval_step1 st (c1;; WHILE b1 DO c1 END)
else st
>>
Coq doesn't accept such a definition ([Error: Cannot guess
decreasing argument of fix]) because the function we want to
define is not guaranteed to terminate. Indeed, the changed
[ceval_step1] function applied to the [loop] program from [Imp.v] would
never terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is an
invalid(!) Coq program showing what would go wrong if Coq allowed
non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become
provable (e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_step1] cannot be written in Coq -- at least not
without one additional trick... *)
(** Second try, using an extra numeric argument as a "step index" to
ensure that evaluation always terminates. *)
Fixpoint ceval_step2 (st : state) (c : com) (i : nat) : state :=
match i with
| O => empty_state
| S i' =>
match c with
| SKIP =>
st
| l ::= a1 =>
update st l (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_step2 st c1 i' in
ceval_step2 st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step2 st c1 i'
else ceval_step2 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then let st' := ceval_step2 st c1 i' in
ceval_step2 st' c i'
else st
end
end.
(** _Note_: It is tempting to think that the index [i] here is
counting the "number of steps of evaluation." But if you look
closely you'll see that this is not the case: for example, in the
rule for sequencing, the same [i] is passed to both recursive
calls. Understanding the exact way that [i] is treated will be
important in the proof of [ceval__ceval_step], which is given as
an exercise below. *)
(** Third try, returning an [option state] instead of just a [state]
so that we can distinguish between normal and abnormal
termination. *)
Fixpoint ceval_step3 (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c2 i'
| None => None
end
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step3 st c1 i'
else ceval_step3 st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then match (ceval_step3 st c1 i') with
| Some st' => ceval_step3 st' c i'
| None => None
end
else Some st
end
end.
(** We can improve the readability of this definition by introducing a
bit of auxiliary notation to hide the "plumbing" involved in
repeatedly matching against optional states. *)
Notation "'LETOPT' x <== e1 'IN' e2"
:= (match e1 with
| Some x => e2
| None => None
end)
(right associativity, at level 60).
Fixpoint ceval_step (st : state) (c : com) (i : nat)
: option state :=
match i with
| O => None
| S i' =>
match c with
| SKIP =>
Some st
| l ::= a1 =>
Some (update st l (aeval st a1))
| c1 ;; c2 =>
LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c2 i'
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_step st c1 i'
else ceval_step st c2 i'
| WHILE b1 DO c1 END =>
if (beval st b1)
then LETOPT st' <== ceval_step st c1 i' IN
ceval_step st' c i'
else Some st
end
end.
Definition test_ceval (st:state) (c:com) :=
match ceval_step st c 500 with
| None => None
| Some st => Some (st X, st Y, st Z)
end.
(* Eval compute in
(test_ceval empty_state
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)).
====>
Some (2, 0, 4) *)
(** **** Exercise: 2 stars (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y]. Make sure
your solution satisfies the test that follows. *)
Definition pup_to_n : com :=
(* FILL IN HERE *) admit.
(*
Example pup_to_n_1 :
test_ceval (update empty_state X 5) pup_to_n
= Some (0, 15, 0).
Proof. reflexivity. Qed.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (peven) *)
(** Write a [While] program that sets [Z] to [0] if [X] is even and
sets [Z] to [1] otherwise. Use [ceval_test] to test your
program. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################ *)
(** ** Equivalence of Relational and Step-Indexed Evaluation *)
(** As with arithmetic and boolean expressions, we'd hope that
the two alternative definitions of evaluation actually boil down
to the same thing. This section shows that this is the case.
Make sure you understand the statements of the theorems and can
follow the structure of the proofs. *)
Theorem ceval_step__ceval: forall c st st',
(exists i, ceval_step st c i = Some st') ->
c / st || st'.
Proof.
intros c st st' H.
inversion H as [i E].
clear H.
generalize dependent st'.
generalize dependent st.
generalize dependent c.
induction i as [| i' ].
Case "i = 0 -- contradictory".
intros c st st' H. inversion H.
Case "i = S i'".
intros c st st' H.
com_cases (destruct c) SCase;
simpl in H; inversion H; subst; clear H.
SCase "SKIP". apply E_Skip.
SCase "::=". apply E_Ass. reflexivity.
SCase ";;".
destruct (ceval_step st c1 i') eqn:Heqr1.
SSCase "Evaluation of r1 terminates normally".
apply E_Seq with s.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSCase "Otherwise -- contradiction".
inversion H1.
SCase "IFB".
destruct (beval st b) eqn:Heqr.
SSCase "r = true".
apply E_IfTrue. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SSCase "r = false".
apply E_IfFalse. rewrite Heqr. reflexivity.
apply IHi'. assumption.
SCase "WHILE". destruct (beval st b) eqn :Heqr.
SSCase "r = true".
destruct (ceval_step st c i') eqn:Heqr1.
SSSCase "r1 = Some s".
apply E_WhileLoop with s. rewrite Heqr. reflexivity.
apply IHi'. rewrite Heqr1. reflexivity.
apply IHi'. simpl in H1. assumption.
SSSCase "r1 = None".
inversion H1.
SSCase "r = false".
inversion H1.
apply E_WhileEnd.
rewrite <- Heqr. subst. reflexivity. Qed.
(** **** Exercise: 4 stars (ceval_step__ceval_inf) *)
(** Write an informal proof of [ceval_step__ceval], following the
usual template. (The template for case analysis on an inductively
defined value should look the same as for induction, except that
there is no induction hypothesis.) Make your proof communicate
the main ideas to a human reader; do not simply transcribe the
steps of the formal proof.
(* FILL IN HERE *)
[]
*)
Theorem ceval_step_more: forall i1 i2 st st' c,
i1 <= i2 ->
ceval_step st c i1 = Some st' ->
ceval_step st c i2 = Some st'.
Proof.
induction i1 as [|i1']; intros i2 st st' c Hle Hceval.
Case "i1 = 0".
simpl in Hceval. inversion Hceval.
Case "i1 = S i1'".
destruct i2 as [|i2']. inversion Hle.
assert (Hle': i1' <= i2') by omega.
com_cases (destruct c) SCase.
SCase "SKIP".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase "::=".
simpl in Hceval. inversion Hceval.
reflexivity.
SCase ";;".
simpl in Hceval. simpl.
destruct (ceval_step st c1 i1') eqn:Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "st1'o = None".
inversion Hceval.
SCase "IFB".
simpl in Hceval. simpl.
destruct (beval st b); apply (IHi1' i2') in Hceval; assumption.
SCase "WHILE".
simpl in Hceval. simpl.
destruct (beval st b); try assumption.
destruct (ceval_step st c i1') eqn: Heqst1'o.
SSCase "st1'o = Some".
apply (IHi1' i2') in Heqst1'o; try assumption.
rewrite -> Heqst1'o. simpl. simpl in Hceval.
apply (IHi1' i2') in Hceval; try assumption.
SSCase "i1'o = None".
simpl in Hceval. inversion Hceval. Qed.
(** **** Exercise: 3 stars (ceval__ceval_step) *)
(** Finish the following proof. You'll need [ceval_step_more] in a
few places, as well as some basic facts about [<=] and [plus]. *)
Theorem ceval__ceval_step: forall c st st',
c / st || st' ->
exists i, ceval_step st c i = Some st'.
Proof.
intros c st st' Hce.
ceval_cases (induction Hce) Case.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem ceval_and_ceval_step_coincide: forall c st st',
c / st || st'
<-> exists i, ceval_step st c i = Some st'.
Proof.
intros c st st'.
split. apply ceval__ceval_step. apply ceval_step__ceval.
Qed.
(* ####################################################### *)
(** ** Determinism of Evaluation (Simpler Proof) *)
(** Here's a slicker proof showing that the evaluation relation is
deterministic, using the fact that the relational and step-indexed
definition of evaluation are the same. *)
Theorem ceval_deterministic' : forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 He1 He2.
apply ceval__ceval_step in He1.
apply ceval__ceval_step in He2.
inversion He1 as [i1 E1].
inversion He2 as [i2 E2].
apply ceval_step_more with (i2 := i1 + i2) in E1.
apply ceval_step_more with (i2 := i1 + i2) in E2.
rewrite E1 in E2. inversion E2. reflexivity.
omega. omega. Qed.
|
`include "hi_read_tx.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
shallow_modulation - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_read_tx;
reg pck0;
reg [7:0] adc_d;
reg shallow_modulation;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_read_tx #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.shallow_modulation(shallow_modulation)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
//crank DUT
task crank_dut;
begin
@(posedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
adc_d = 0;
ssp_dout=0;
// shallow modulation off
shallow_modulation=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
shallow_modulation=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog wrapper for lpflow_clkinvkapwr with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_clkinvkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (
Y ,
A ,
KAPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
output Y ;
input A ;
input KAPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
.Y(Y),
.A(A),
.KAPWR(KAPWR),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__lpflow_clkinvkapwr_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__lpflow_clkinvkapwr base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_M_V
`define SKY130_FD_SC_LP__NAND3_M_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_m (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_m (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_M_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg reset;
reg enable;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] out; // From test of Test.v
// End of automatics
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
Test test (/*AUTOINST*/
// Outputs
.out (out[31:0]),
// Inputs
.clk (clk),
.reset (reset),
.enable (enable),
.in (in[31:0]));
wire [63:0] result = {32'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
reset <= (cyc < 5);
enable <= cyc[4] || (cyc < 2);
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
`define EXPECTED_SUM 64'h01e1553da1dcf3af
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, reset, enable, in
);
input clk;
input reset;
input enable;
input [31:0] in;
output [31:0] out;
// No gating
reg [31:0] d10;
always @(posedge clk) begin
d10 <= in;
end
reg displayit;
`ifdef VERILATOR // Harder test
initial displayit = $c1("0"); // Something that won't optimize away
`else
initial displayit = '0;
`endif
// Obvious gating + PLI
reg [31:0] d20;
always @(posedge clk) begin
if (enable) begin
d20 <= d10; // Obvious gating
if (displayit) begin
$display("hello!"); // Must glob with other PLI statements
end
end
end
// Reset means second-level gating
reg [31:0] d30, d31a, d31b, d32;
always @(posedge clk) begin
d32 <= d31b;
if (reset) begin
d30 <= 32'h0;
d31a <= 32'h0;
d31b <= 32'h0;
d32 <= 32'h0; // Overlaps above, just to make things interesting
end
else begin
// Mix two outputs
d30 <= d20;
if (enable) begin
d31a <= d30;
d31b <= d31a;
end
end
end
// Multiple ORs for gater
reg [31:0] d40a,d40b;
always @(posedge clk) begin
if (reset) begin
d40a <= 32'h0;
d40b <= 32'h0;
end
if (enable) begin
d40a <= d32;
d40b <= d40a;
end
end
// Non-optimizable
reg [31:0] d91, d92;
reg [31:0] inverted;
always @(posedge clk) begin
inverted = ~d40b;
if (reset) begin
d91 <= 32'h0;
end
else begin
if (enable) begin
d91 <= inverted;
end
else begin
d92 <= inverted ^ 32'h12341234; // Inverted gating condition
end
end
end
wire [31:0] out = d91 ^ d92;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 16:25:28
// Design Name:
// Module Name: ARINC429
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ARINC429(
input wire [1 : 0] nvel,
input wire [7 : 0] adr,
input wire [22 : 0] dat,
input wire GCLK,
output wire TXD0,
output wire TXD1,
input wire RXD0,
input wire RXD1,
input wire st,
output reg [7:0] sr_adr,
output reg [22:0] sr_dat,
output reg ce_wr,
input wire rec_disp, // reciever dispatcher
input wire reset
);
AR_TXD TX
(
.clk(GCLK),
.Nvel(nvel),
.ADR(adr),
.DAT(dat),
.st(st),
.TXD0(TXD0),
.TXD1(TXD1),
.reset(reset)
);
wire [7:0] sr_adr_1;
wire [22:0] sr_dat_1;
wire ce_wr_1;
AR_RXD RX
(
.clk(GCLK),
.in0(RXD0),
.in1(RXD1),
.sr_dat(sr_dat_1),
.sr_adr(sr_adr_1),
.ce_wr(ce_wr_1)
);
wire [7:0] sr_adr_2;
wire [22:0] sr_dat_2;
wire ce_wr_2;
AR_RXD_2 RX_2
(
.clk(GCLK),
.in0(RXD0),
.in1(RXD1),
.sr_dat(sr_dat_2),
.sr_adr(sr_adr_2),
.ce_wr(ce_wr_2)
);
always @(posedge GCLK)
begin
sr_dat <= rec_disp ? sr_dat_1 : sr_dat_2;
sr_adr <= rec_disp ? sr_adr_1 : sr_adr_2;
ce_wr <= rec_disp ? ce_wr_1 : ce_wr_2;
end
endmodule
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-2-2017
*/
`timescale 1ns / 1ps
module jt12_testdata
#(parameter rand_wait=0)
(
input rst,
input clk,
output reg cs_n,
output reg wr_n,
output reg [1:0] addr,
output reg [7:0] dout,
input [7:0] din,
output reg prog_done
);
// CFG configuration
// { addr[1], reg[7:0], value[7:0] }
reg [16:0] cfg[0:65535];
initial begin
`include "inputs.vh"
end
reg [15:0] data_cnt;
reg [ 3:0] state, next;
reg [15:0] waitcnt;
localparam WAIT_FREE=0, WR_ADDR=1, WR_VAL=2, DONE=3, WRITE=4,
BLANK=5, WAIT_CNT=6;
localparam BUSY_TIMEOUT=500;
integer rnd_count, timeout;
always @(posedge clk or posedge rst) begin
if( rst ) begin
data_cnt <= 0;
prog_done <= 0;
next <= WR_ADDR;
state <= WAIT_FREE;
addr <= 2'b0;
wr_n <= 1'b1;
dout <= 8'h0;
rnd_count <= 0;
waitcnt <= 16'h0;
timeout <= BUSY_TIMEOUT;
end
else begin
case( state )
BLANK: begin
if( rnd_count>0 )
rnd_count <= rnd_count -1;
else begin
state <= WAIT_FREE;
timeout <= BUSY_TIMEOUT;
end
wr_n <= 1'b1;
end
WAIT_FREE: begin
// a0 <= 1'b0;
{ cs_n, wr_n } <= 2'b01;
timeout <= timeout-1;
if(timeout==0) begin
$display("ERROR: timeout while waiting for BUSY\n");
$finish;
end
if( !din[7] ) begin
case( cfg[data_cnt][15:8] )
8'h0: state <= DONE;
8'h1: begin
waitcnt <= { cfg[data_cnt][7:0], 8'h0 };
state <= WAIT_CNT;
end
// Wait for timer flag:
8'h3: if( (din[1:0]&cfg[data_cnt][1:0])!=2'd0 ) state<=next;
default: state <= next;
endcase
end
end
WAIT_CNT: begin
if( waitcnt==16'd0 ) begin
data_cnt <= data_cnt + 1'b1;
timeout <= BUSY_TIMEOUT;
state <= WAIT_FREE;
end
else waitcnt <= waitcnt-1'b1;
end
WRITE: begin
{ cs_n, wr_n } <= 2'b00;
`ifndef VERILATOR
rnd_count <= rand_wait ? ($urandom%100) : 0;
`else
rnd_count <= 0;
`endif
state<= BLANK;
end
WR_ADDR: begin
addr <= { cfg[data_cnt][16], 1'b0 };
dout <= cfg[data_cnt][15:8];
next <= WR_VAL;
state<= WRITE;
end
WR_VAL: begin
addr[0] <= 1'b1;
dout <= cfg[data_cnt][7:0];
state <= WRITE;
if( &data_cnt == 1'b1 ) begin
$display("data_cnt overflow! jt12_testdata.v");
next <= DONE;
end
else begin
data_cnt <= data_cnt + 1'b1;
next <= WR_ADDR;
end
end
DONE: prog_done <= 1'b1;
endcase
end
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_w the_niosii_jtag_uart_0_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
niosii_jtag_uart_0_sim_scfifo_r the_niosii_jtag_uart_0_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module niosii_jtag_uart_0 (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
niosii_jtag_uart_0_scfifo_w the_niosii_jtag_uart_0_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
niosii_jtag_uart_0_scfifo_r the_niosii_jtag_uart_0_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic niosii_jtag_uart_0_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam niosii_jtag_uart_0_alt_jtag_atlantic.INSTANCE_ID = 0,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// niosii_jtag_uart_0_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
`timescale 1ns / 1ps
module CORDIC_FSM_v2_tb;
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//declaration of signals
//Input Signals
reg clk; // Reloj del sitema.
reg reset; // Reset del sitema.
reg beg_FSM_CORDIC; // Señal de inicio de la maquina de estados.
reg ACK_FSM_CORDIC; // Señal proveniente del modulo que recibe el resultado, indicado que el dato ha sido recibido.
reg operation; // Señal que determina si lo que se requiere es realizar un coseno(1´b0) o seno (1'b1).
reg [1:0] shift_region_flag; // Señal que indica si el angulo a calcular se encuentra fuera del rango de calculo del algoritmo CORDIC.
reg [1:0] cont_var; // Señal que indica cual varible se va a calcular. Proveniente del contador de variables.
reg ready_add_subt; // Señal proveniente del módulo de suma/resta, indica que se ha terminado la operacion y que se puede disponer del resultado de dicho modulo.
reg max_tick_iter;
reg min_tick_iter; // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de iteraciones.
reg max_tick_var;
reg min_tick_var; // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de variables.
//Output Signals
wire reset_reg_cordic;
wire ready_CORDIC; // Señal que indica que el calculo CORDIC se ha terminado.
wire beg_add_subt; // Señal que indica al modulo de suma/resta que inicie su operacion.
wire ack_add_subt; // Señal que le indica al modulo de suma/resta que se ha recibido exitosamente el resultado que este entrega.
wire sel_mux_1;
wire sel_mux_3; // Señales de seleccion de mux, la primera escoge el canal 0 si es la primera iteracion, en otro caso escoge el canal 1, y la segunda escoge cual variable (X o Y) debe aparecer a la salida.
wire [1:0] sel_mux_2; // Señal de seleccion de mux, que escoge entre X, Y o Z dependiendo de cual variable se deba calcular en ese momento.
wire mode; // 1'b0 si el modo es rotacion(signo de Y), 1'b1 si el modo es vectorizacion(signo de Z).
wire enab_cont_iter;
wire load_cont_iter; // Señales de habilitacion y carga, respectivamente, en el contador de iteraciones.
wire enab_cont_var;
wire load_cont_var; // Señales de habilitacion y carga, respectivamente, en el contador de variables.
wire enab_RB1;
wire enab_RB2; // Señales de habilitacion para los registros de variables de entrada y para los valores de las variables despues de los primeros mux, respectivamente.
wire enab_d_ff_Xn;
wire enab_d_ff_Yn;
wire enab_d_ff_Zn; // Señales de habilitacion para los registros que guardan los resultados de cada variable en cada iteracion provenientes del modulo de suma/resta.
wire enab_d_ff_out; // Señales de habilitacion para los registros en la salida, el primero antes del cambio de signo y el segundo es el que se encuentra en la salida.
wire enab_dff_shifted_x;
wire enab_dff_shifted_y; // Señales de habilitacion para los registros que guardan el valor de las variables X y Y luego de realizarles los desplazamientos.
wire enab_dff_LUT;
wire enab_dff_sign; // Señales de habilitacion para los registros que guardan los valores provenientes de la look-up table y del signo, respectivamente.
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//Instantiation of the FSM
CORDIC_FSM_v2 cordic_fsm_v2
(
//Input Signals
.clk(clk), // Reloj del sitema.
.reset(reset), // Reset del sitema.
.beg_FSM_CORDIC(beg_FSM_CORDIC), // Señal de inicio de la maquina de estados.
.ACK_FSM_CORDIC(ACK_FSM_CORDIC), // Señal proveniente del modulo que recibe el resultado, indicado que el dato ha sido recibido.
.operation(operation), // Señal que determina si lo que se requiere es realizar un coseno(1´b0) o seno (1'b1).
.shift_region_flag(shift_region_flag), // Señal que indica si el angulo a calcular se encuentra fuera del rango de calculo del algoritmo CORDIC.
.cont_var(cont_var), // Señal que indica cual varible se va a calcular. Proveniente del contador de variables.
.ready_add_subt(ready_add_subt), // Señal proveniente del módulo de suma/resta, indica que se ha terminado la operacion y que se puede disponer del resultado de dicho modulo.
.max_tick_iter(max_tick_iter),
.min_tick_iter(min_tick_iter), // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de iteraciones.
.max_tick_var(max_tick_var),
.min_tick_var(min_tick_var), // Señales que indican la maxima y minima cuenta, respectivamente, en el contador de variables.
//Output Signals
.reset_reg_cordic(reset_reg_cordic),
.ready_CORDIC(ready_CORDIC), // Señal que indica que el calculo CORDIC se ha terminado.
.beg_add_subt(beg_add_subt), // Señal que indica al modulo de suma/resta que inicie su operacion.
.ack_add_subt(ack_add_subt), // Señal que le indica al modulo de suma/resta que se ha recibido exitosamente el resultado que este entrega.
.sel_mux_1(sel_mux_1),
.sel_mux_3(sel_mux_3), // Señales de seleccion de mux, la primera escoge el canal 0 si es la primera iteracion, en otro caso escoge el canal 1, y la segunda escoge cual variable (X o Y) debe aparecer a la salida.
.sel_mux_2(sel_mux_2), // Señal de seleccion de mux, que escoge entre X, Y o Z dependiendo de cual variable se deba calcular en ese momento.
.mode(mode), // 1'b0 si el modo es rotacion(signo de Y), 1'b1 si el modo es vectorizacion(signo de Z).
.enab_cont_iter(enab_cont_iter),
.load_cont_iter(load_cont_iter), // Señales de habilitacion y carga, respectivamente, en el contador de iteraciones.
.enab_cont_var(enab_cont_var),
.load_cont_var(load_cont_var), // Señales de habilitacion y carga, respectivamente, en el contador de variables.
.enab_RB1(enab_RB1),
.enab_RB2(enab_RB2), // Señales de habilitacion para los registros de variables de entrada y para los valores de las variables despues de los primeros mux, respectivamente.
.enab_d_ff_Xn(enab_d_ff_Xn),
.enab_d_ff_Yn(enab_d_ff_Yn),
.enab_d_ff_Zn(enab_d_ff_Zn), // Señales de habilitacion para los registros que guardan los resultados de cada variable en cada iteracion provenientes del modulo de suma/resta.
.enab_d_ff_out(enab_d_ff_out), // Señales de habilitacion para los registros en la salida, el primero antes del cambio de signo y el segundo es el que se encuentra en la salida.
.enab_dff_shifted_x(enab_dff_shifted_x),
.enab_dff_shifted_y(enab_dff_shifted_y), // Señales de habilitacion para los registros que guardan el valor de las variables X y Y luego de realizarles los desplazamientos.
.enab_dff_LUT(enab_dff_LUT),
.enab_dff_sign(enab_dff_sign) // Señales de habilitacion para los registros que guardan los valores provenientes de la look-up table y del signo, respectivamente.
);
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//Generation of the clock
initial
begin
clk = 1;
forever #5 clk = ~clk;
end
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//Stimulus specification
initial
begin
//inicializacion de señales
reset = 0;
beg_FSM_CORDIC = 0;
ACK_FSM_CORDIC = 0;
operation = 0;
shift_region_flag = 2'b10;
cont_var = 2'b00;
ready_add_subt = 0;
max_tick_iter = 0;
min_tick_iter = 0;
max_tick_var = 0;
min_tick_var = 0;
#100
reset = 1;
operation = 0;
shift_region_flag = 2'b00;
#10
reset = 0;
#10
beg_FSM_CORDIC = 1;
min_tick_iter = 1;
min_tick_var = 1;
#10
beg_FSM_CORDIC = 0;
#55
ready_add_subt = 1;
#10
ready_add_subt = 0;
min_tick_var = 0;
cont_var = 2'b01;
#25
ready_add_subt = 1;
#30
ready_add_subt = 0;
cont_var = 2'b10;
max_tick_var = 1;
#35
ready_add_subt = 1;
#10
ready_add_subt = 0;
min_tick_iter = 0;
#25
max_tick_var = 0;
min_tick_var = 0;
max_tick_iter = 1;
#5
max_tick_var = 1;
#30
ready_add_subt = 1;
#10
ready_add_subt = 0;
#40
ACK_FSM_CORDIC = 1'b1;
#100 $stop;
end
endmodule
|
`timescale 1ns / 1ps
`define SIMULATION
module peripheral_bt_TB;
reg clk;
reg rst;
reg reset;
reg start;
reg [15:0]d_in;
reg cs;
reg [1:0]addr;
reg rd;
reg wr;
wire [15:0]d_out;
peripheral_bt uut (.clk(clk) , .rst(reset) , .d_in(d_in) , .cs(cs) , .addr(addr) , .rd(rd) , .wr(wr), .d_out(d_out) );
parameter PERIOD = 20;
parameter real DUTY_CYCLE = 0.5;
parameter OFFSET = 0;
reg [20:0] i;
event reset_trigger;
reg d;
initial begin // Initialize Inputs
clk = 0; reset = 1; start = 0; d_in = 16'd0035; addr = 16'h0000; cs=1; rd=1; wr=0;
end
initial begin // Process for clk
#OFFSET;
forever
begin
clk = 1'b0;
#(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
#(PERIOD*DUTY_CYCLE);
end
end
initial begin // Reset the system, Start the image capture process
forever begin
@ (reset_trigger);
@ (posedge clk);
start = 0;
@ (posedge clk);
start = 1;
for(i=0; i<2; i=i+1) begin
@ (posedge clk);
end
start = 0;
#4 reset=0;
// stimulus here
for(i=0; i<4; i=i+1) begin
@ (posedge clk);
end
d_in = 16'h0001; //envio 1
addr = 16'h0000;
cs=1; rd=0; wr=1;
addr = 16'h0002;
cs=1; rd=1; wr=0;
for(i=0; i<40000; i=i+1) begin
@ (posedge clk);
end
d_in = 16'h0002; //envio 1
addr = 16'h0000;
cs=1; rd=1; wr=0;
end
end
initial begin: TEST_CASE
$dumpfile("peripheral_bt_TB.vcd");
$dumpvars(-1, uut);
#10 -> reset_trigger;
#((PERIOD*DUTY_CYCLE)*200000) $finish;
end
endmodule
|
//wishbone_arbiter.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`timescale 1 ns/1 ps
module arbiter_2_masters (
//control signals
input clk,
input rst,
//wishbone master ports
input i_m0_we,
input i_m0_cyc,
input i_m0_stb,
input [3:0] i_m0_sel,
output o_m0_ack,
input [31:0] i_m0_dat,
output [31:0] o_m0_dat,
input [31:0] i_m0_adr,
output o_m0_int,
input i_m1_we,
input i_m1_cyc,
input i_m1_stb,
input [3:0] i_m1_sel,
output o_m1_ack,
input [31:0] i_m1_dat,
output [31:0] o_m1_dat,
input [31:0] i_m1_adr,
output o_m1_int,
//wishbone slave signals
output o_s_we,
output o_s_stb,
output o_s_cyc,
output [3:0] o_s_sel,
output [31:0] o_s_adr,
output [31:0] o_s_dat,
input [31:0] i_s_dat,
input i_s_ack,
input i_s_int
);
localparam MASTER_COUNT = 2;
//registers/wires
//this should be parameterized
reg [7:0] master_select;
reg [7:0] priority_select;
wire o_master_we [MASTER_COUNT - 1:0];
wire o_master_stb [MASTER_COUNT - 1:0];
wire o_master_cyc [MASTER_COUNT - 1:0];
wire [3:0] o_master_sel [MASTER_COUNT - 1:0];
wire [31:0] o_master_adr [MASTER_COUNT - 1:0];
wire [31:0] o_master_dat [MASTER_COUNT - 1:0];
//master select block
localparam MASTER_NO_SEL = 8'hFF;
localparam MASTER_0 = 0;
localparam MASTER_1 = 1;
always @ (posedge clk) begin
if (rst) begin
master_select <= MASTER_NO_SEL;
end
else begin
case (master_select)
MASTER_0: begin
if (~i_m0_cyc && ~i_s_ack) begin
master_select <= MASTER_NO_SEL;
end
end
MASTER_1: begin
if (~i_m1_cyc && ~i_s_ack) begin
master_select <= MASTER_NO_SEL;
end
end
default: begin
//nothing selected
if (i_m0_cyc) begin
master_select <= MASTER_0;
end
else if (i_m1_cyc) begin
master_select <= MASTER_1;
end
end
endcase
if ((master_select != MASTER_NO_SEL) && (priority_select < master_select) && (!o_s_stb && !i_s_ack))begin
master_select <= MASTER_NO_SEL;
end
end
end
//priority select
always @ (posedge clk) begin
if (rst) begin
priority_select <= MASTER_NO_SEL;
end
else begin
//find the highest priority
if (i_m0_cyc) begin
priority_select <= MASTER_0;
end
else if (i_m1_cyc) begin
priority_select <= MASTER_1;
end
else begin
priority_select <= MASTER_NO_SEL;
end
end
end
//slave assignments
assign o_s_we = (master_select != MASTER_NO_SEL) ? o_master_we[master_select] : 0;
assign o_s_stb = (master_select != MASTER_NO_SEL) ? o_master_stb[master_select] : 0;
assign o_s_cyc = (master_select != MASTER_NO_SEL) ? o_master_cyc[master_select] : 0;
assign o_s_sel = (master_select != MASTER_NO_SEL) ? o_master_sel[master_select] : 0;
assign o_s_adr = (master_select != MASTER_NO_SEL) ? o_master_adr[master_select] : 0;
assign o_s_dat = (master_select != MASTER_NO_SEL) ? o_master_dat[master_select] : 0;
//write select block
assign o_master_we[MASTER_0] = i_m0_we;
assign o_master_we[MASTER_1] = i_m1_we;
//strobe select block
assign o_master_stb[MASTER_0] = i_m0_stb;
assign o_master_stb[MASTER_1] = i_m1_stb;
//cycle select block
assign o_master_cyc[MASTER_0] = i_m0_cyc;
assign o_master_cyc[MASTER_1] = i_m1_cyc;
//select select block
assign o_master_sel[MASTER_0] = i_m0_sel;
assign o_master_sel[MASTER_1] = i_m1_sel;
//address seelct block
assign o_master_adr[MASTER_0] = i_m0_adr;
assign o_master_adr[MASTER_1] = i_m1_adr;
//data select block
assign o_master_dat[MASTER_0] = i_m0_dat;
assign o_master_dat[MASTER_1] = i_m1_dat;
//assign block
assign o_m0_ack = (master_select == MASTER_0) ? i_s_ack : 0;
assign o_m0_dat = i_s_dat;
assign o_m0_int = (master_select == MASTER_0) ? i_s_int : 0;
assign o_m1_ack = (master_select == MASTER_1) ? i_s_ack : 0;
assign o_m1_dat = i_s_dat;
assign o_m1_int = (master_select == MASTER_1) ? i_s_int : 0;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2014 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// bug823
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [6:0] in = crc[6:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] mask; // From test of Test.v
wire [3:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
.mask (mask[3:0]),
// Inputs
.clk (clk),
.in (in[6:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out & mask};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n", $time, cyc, crc, out, mask);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= '0;
end
else if (cyc<10) begin
sum <= '0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4e9d3a74e9d3f656
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out, mask,
// Inputs
clk, in
);
input clk;
input [6:0] in; // Note much wider than any index
output reg [3:0] out;
output reg [3:0] mask;
localparam [15:5] p = 11'h1ac;
always @(posedge clk) begin
// verilator lint_off WIDTH
out <= p[15 + in -: 5];
// verilator lint_on WIDTH
mask[3] <= ((15 + in - 5) < 12);
mask[2] <= ((15 + in - 5) < 13);
mask[1] <= ((15 + in - 5) < 14);
mask[0] <= ((15 + in - 5) < 15);
end
endmodule
|