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//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
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// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_rd_data.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// User interface read buffer. Re orders read data returned from the
// memory controller back to the request order.
//
// Consists of a large buffer for the data, a status RAM and two counters.
//
// The large buffer is implemented with distributed RAM in 6 bit wide,
// 1 read, 1 write mode. The status RAM is implemented with a distributed
// RAM configured as 2 bits wide 1 read/write, 1 read mode.
//
// As read requests are received from the application, the data_buf_addr
// counter supplies the data_buf_addr sent into the memory controller.
// With each read request, the counter is incremented, eventually rolling
// over. This mechanism labels each read request with an incrementing number.
//
// When the memory controller returns read data, it echos the original
// data_buf_addr with the read data.
//
// The status RAM is indexed with the same address as the data buffer
// RAM. Each word of the data buffer RAM has an associated status bit
// and "end" bit. Requests of size 1 return a data burst on two consecutive
// states. Requests of size zero return with a single assertion of rd_data_en.
//
// Upon returning data, the status and end bits are updated for each
// corresponding location in the status RAM indexed by the data_buf_addr
// echoed on the rd_data_addr field.
//
// The other side of the status and data RAMs is indexed by the rd_buf_indx.
// The rd_buf_indx constantly monitors the status bit it is currently
// pointing to. When the status becomes set to the proper state (more on
// this later) read data is returned to the application, and the rd_buf_indx
// is incremented.
//
// At rst the rd_buf_indx is initialized to zero. Data will not have been
// returned from the memory controller yet, so there is nothing to return
// to the application. Evenutally, read requests will be made, and the
// memory controller will return the corresponding data. The memory
// controller may not return this data in the request order. In which
// case, the status bit at location zero, will not indicate
// the data for request zero is ready. Eventually, the memory controller
// will return data for request zero. The data is forwarded on to the
// application, and rd_buf_indx is incremented to point to the next status
// bits and data in the buffers. The status bit will be examined, and if
// data is valid, this data will be returned as well. This process
// continues until the status bit indexed by rd_buf_indx indicates data
// is not ready. This may be because the rd_data_buf
// is empty, or that some data was returned out of order. Since rd_buf_indx
// always increments sequentially, data is always returned to the application
// in request order.
//
// Some further discussion of the status bit is in order. The rd_data_buf
// is a circular buffer. The status bit is a single bit. Distributed RAM
// supports only a single write port. The write port is consumed by
// memory controller read data updates. If a simple '1' were used to
// indicate the status, when rd_data_indx rolled over it would immediately
// encounter a one for a request that may not be ready.
//
// This problem is solved by causing read data returns to flip the
// status bit, and adding hi order bit beyond the size required to
// index the rd_data_buf. Data is considered ready when the status bit
// and this hi order bit are equal.
//
// The status RAM needs to be initialized to zero after reset. This is
// accomplished by cycling through all rd_buf_indx valus and writing a
// zero to the status bits directly following deassertion of reset. This
// mechanism is used for similar purposes
// for the wr_data_buf.
//
// When ORDERING == "STRICT", read data reordering is unnecessary. For thi
// case, most of the logic in the block is not generated.
`timescale 1 ps / 1 ps
// User interface read data.
module mig_7series_v1_9_ui_rd_data #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter ECC = "OFF",
parameter nCK_PER_CLK = 2 ,
parameter ORDERING = "NORM"
)
(/*AUTOARG*/
// Outputs
ram_init_done_r, ram_init_addr, app_rd_data_valid, app_rd_data_end,
app_rd_data, app_ecc_multiple_err, rd_buf_full, rd_data_buf_addr_r,
// Inputs
rst, clk, rd_data_en, rd_data_addr, rd_data_offset, rd_data_end,
rd_data, ecc_multiple, rd_accepted
);
input rst;
input clk;
output wire ram_init_done_r;
output wire [3:0] ram_init_addr;
// rd_buf_indx points to the status and data storage rams for
// reading data out to the app.
reg [5:0] rd_buf_indx_r;
(* keep = "true", max_fanout = 10 *) reg ram_init_done_r_lcl /* synthesis syn_maxfan = 10 */;
assign ram_init_done_r = ram_init_done_r_lcl;
wire app_rd_data_valid_ns;
wire single_data;
reg [5:0] rd_buf_indx_ns;
generate begin : rd_buf_indx
wire upd_rd_buf_indx = ~ram_init_done_r_lcl || app_rd_data_valid_ns;
// Loop through all status write addresses once after rst. Initializes
// the status and pointer RAMs.
wire ram_init_done_ns =
~rst && (ram_init_done_r_lcl || (rd_buf_indx_r[4:0] == 5'h1f));
always @(posedge clk) ram_init_done_r_lcl <= #TCQ ram_init_done_ns;
always @(/*AS*/rd_buf_indx_r or rst or single_data
or upd_rd_buf_indx) begin
rd_buf_indx_ns = rd_buf_indx_r;
if (rst) rd_buf_indx_ns = 6'b0;
else if (upd_rd_buf_indx) rd_buf_indx_ns =
// need to use every slot of RAMB32 if all address bits are used
rd_buf_indx_r + 6'h1 + (DATA_BUF_ADDR_WIDTH == 5 ? 0 : single_data);
end
always @(posedge clk) rd_buf_indx_r <= #TCQ rd_buf_indx_ns;
end
endgenerate
assign ram_init_addr = rd_buf_indx_r[3:0];
input rd_data_en;
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input rd_data_offset;
input rd_data_end;
input [APP_DATA_WIDTH-1:0] rd_data;
(* keep = "true", max_fanout = 10 *) output reg app_rd_data_valid /* synthesis syn_maxfan = 10 */;
output reg app_rd_data_end;
output reg [APP_DATA_WIDTH-1:0] app_rd_data;
input [3:0] ecc_multiple;
reg [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_r = 'b0;
output wire [2*nCK_PER_CLK-1:0] app_ecc_multiple_err;
assign app_ecc_multiple_err = app_ecc_multiple_err_r;
input rd_accepted;
output wire rd_buf_full;
output wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r;
// Compute dimensions of read data buffer. Depending on width of
// DQ bus and DRAM CK
// to fabric ratio, number of RAM32Ms is variable. RAM32Ms are used in
// single write, single read, 6 bit wide mode.
localparam RD_BUF_WIDTH = APP_DATA_WIDTH + (ECC == "OFF" ? 0 : 2*nCK_PER_CLK);
localparam FULL_RAM_CNT = (RD_BUF_WIDTH/6);
localparam REMAINDER = RD_BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
if (ORDERING == "STRICT") begin : strict_mode
assign app_rd_data_valid_ns = 1'b0;
assign single_data = 1'b0;
assign rd_buf_full = 1'b0;
reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns =
rst
? 0
: rd_data_buf_addr_r_lcl + rd_accepted;
always @(posedge clk) rd_data_buf_addr_r_lcl <=
#TCQ rd_data_buf_addr_ns;
assign rd_data_buf_addr_r = rd_data_buf_addr_ns;
// app_* signals required to be registered.
if (ECC == "OFF") begin : ecc_off
always @(/*AS*/rd_data) app_rd_data = rd_data;
always @(/*AS*/rd_data_en) app_rd_data_valid = rd_data_en;
always @(/*AS*/rd_data_end) app_rd_data_end = rd_data_end;
end
else begin : ecc_on
always @(posedge clk) app_rd_data <= #TCQ rd_data;
always @(posedge clk) app_rd_data_valid <= #TCQ rd_data_en;
always @(posedge clk) app_rd_data_end <= #TCQ rd_data_end;
always @(posedge clk) app_ecc_multiple_err_r <= #TCQ ecc_multiple;
end
end
else begin : not_strict_mode
(* keep = "true", max_fanout = 10 *) wire rd_buf_we = ~ram_init_done_r_lcl || rd_data_en /* synthesis syn_maxfan = 10 */;
// In configurations where read data is returned in a single fabric cycle
// the offset is always zero and we can use the bit to get a deeper
// FIFO. The RAMB32 has 5 address bits, so when the DATA_BUF_ADDR_WIDTH
// is set to use them all, discard the offset. Otherwise, include the
// offset.
wire [4:0] rd_buf_wr_addr = DATA_BUF_ADDR_WIDTH == 5 ?
rd_data_addr :
{rd_data_addr, rd_data_offset};
wire [1:0] rd_status;
// Instantiate status RAM. One bit for status and one for "end".
begin : status_ram
// Turns out read to write back status is a timing path. Update
// the status in the ram on the state following the read. Bypass
// the write data into the status read path.
wire [4:0] status_ram_wr_addr_ns = ram_init_done_r_lcl
? rd_buf_wr_addr
: rd_buf_indx_r[4:0];
reg [4:0] status_ram_wr_addr_r;
always @(posedge clk) status_ram_wr_addr_r <=
#TCQ status_ram_wr_addr_ns;
wire [1:0] wr_status;
// Not guaranteed to write second status bit. If it is written, always
// copy in the first status bit.
reg wr_status_r1;
always @(posedge clk) wr_status_r1 <= #TCQ wr_status[0];
wire [1:0] status_ram_wr_data_ns =
ram_init_done_r_lcl
? {rd_data_end, ~(rd_data_offset
? wr_status_r1
: wr_status[0])}
: 2'b0;
reg [1:0] status_ram_wr_data_r;
always @(posedge clk) status_ram_wr_data_r <=
#TCQ status_ram_wr_data_ns;
reg rd_buf_we_r1;
always @(posedge clk) rd_buf_we_r1 <= #TCQ rd_buf_we;
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(rd_status),
.DOB(),
.DOC(wr_status),
.DOD(),
.DIA(status_ram_wr_data_r),
.DIB(2'b0),
.DIC(status_ram_wr_data_r),
.DID(status_ram_wr_data_r),
.ADDRA(rd_buf_indx_r[4:0]),
.ADDRB(5'b0),
.ADDRC(status_ram_wr_addr_ns),
.ADDRD(status_ram_wr_addr_r),
.WE(rd_buf_we_r1),
.WCLK(clk)
);
end // block: status_ram
wire [RAM_WIDTH-1:0] rd_buf_out_data;
begin : rd_buf
wire [RAM_WIDTH-1:0] rd_buf_in_data;
if (REMAINDER == 0)
if (ECC == "OFF")
assign rd_buf_in_data = rd_data;
else
assign rd_buf_in_data = {ecc_multiple, rd_data};
else
if (ECC == "OFF")
assign rd_buf_in_data = {{6-REMAINDER{1'b0}}, rd_data};
else
assign rd_buf_in_data =
{{6-REMAINDER{1'b0}}, ecc_multiple, rd_data};
// Dedicated copy for driving distributed RAM.
(* keep = "true" *) reg [4:0] rd_buf_indx_copy_r /* synthesis syn_keep = 1 */;
always @(posedge clk) rd_buf_indx_copy_r <= #TCQ rd_buf_indx_ns[4:0];
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(rd_buf_out_data[((i*6)+4)+:2]),
.DOB(rd_buf_out_data[((i*6)+2)+:2]),
.DOC(rd_buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(rd_buf_in_data[((i*6)+4)+:2]),
.DIB(rd_buf_in_data[((i*6)+2)+:2]),
.DIC(rd_buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(rd_buf_indx_copy_r[4:0]),
.ADDRB(rd_buf_indx_copy_r[4:0]),
.ADDRC(rd_buf_indx_copy_r[4:0]),
.ADDRD(rd_buf_wr_addr),
.WE(rd_buf_we),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
wire rd_data_rdy = (rd_status[0] == rd_buf_indx_r[5]);
(* keep = "true", max_fanout = 10 *) wire bypass = rd_data_en && (rd_buf_wr_addr[4:0] == rd_buf_indx_r[4:0]) /* synthesis syn_maxfan = 10 */;
assign app_rd_data_valid_ns =
ram_init_done_r_lcl && (bypass || rd_data_rdy);
wire app_rd_data_end_ns = bypass ? rd_data_end : rd_status[1];
always @(posedge clk) app_rd_data_valid <= #TCQ app_rd_data_valid_ns;
always @(posedge clk) app_rd_data_end <= #TCQ app_rd_data_end_ns;
assign single_data =
app_rd_data_valid_ns && app_rd_data_end_ns && ~rd_buf_indx_r[0];
wire [APP_DATA_WIDTH-1:0] app_rd_data_ns =
bypass
? rd_data
: rd_buf_out_data[APP_DATA_WIDTH-1:0];
always @(posedge clk) app_rd_data <= #TCQ app_rd_data_ns;
if (ECC != "OFF") begin : assign_app_ecc_multiple
wire [3:0] app_ecc_multiple_err_ns =
bypass
? ecc_multiple
: rd_buf_out_data[APP_DATA_WIDTH+:4];
always @(posedge clk) app_ecc_multiple_err_r <=
#TCQ app_ecc_multiple_err_ns;
end
//Added to fix timing. The signal app_rd_data_valid has
//a very high fanout. So making a dedicated copy for usage
//with the occ_cnt counter.
(* equivalent_register_removal = "no" *)
reg app_rd_data_valid_copy;
always @(posedge clk) app_rd_data_valid_copy <= #TCQ app_rd_data_valid_ns;
// Keep track of how many entries in the queue hold data.
wire free_rd_buf = app_rd_data_valid_copy && app_rd_data_end; //changed to use registered version
//of the signals in ordered to fix timing
reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_r;
wire [DATA_BUF_ADDR_WIDTH:0] occ_minus_one = occ_cnt_r - 1;
wire [DATA_BUF_ADDR_WIDTH:0] occ_plus_one = occ_cnt_r + 1;
begin : occupied_counter
reg [DATA_BUF_ADDR_WIDTH:0] occ_cnt_ns;
always @(/*AS*/free_rd_buf or occ_cnt_r or rd_accepted or rst or occ_minus_one or occ_plus_one) begin
occ_cnt_ns = occ_cnt_r;
if (rst) occ_cnt_ns = 0;
else case ({rd_accepted, free_rd_buf})
2'b01 : occ_cnt_ns = occ_minus_one;
2'b10 : occ_cnt_ns = occ_plus_one;
endcase // case ({wr_data_end, new_rd_data})
end
always @(posedge clk) occ_cnt_r <= #TCQ occ_cnt_ns;
assign rd_buf_full = occ_cnt_ns[DATA_BUF_ADDR_WIDTH];
`ifdef MC_SVA
rd_data_buffer_full: cover property (@(posedge clk) (~rst && rd_buf_full));
rd_data_buffer_inc_dec_15: cover property (@(posedge clk)
(~rst && rd_accepted && free_rd_buf && (occ_cnt_r == 'hf)));
rd_data_underflow: assert property (@(posedge clk)
(rst || !((occ_cnt_r == 'b0) && (occ_cnt_ns == 'h1f))));
rd_data_overflow: assert property (@(posedge clk)
(rst || !((occ_cnt_r == 'h10) && (occ_cnt_ns == 'h11))));
`endif
end // block: occupied_counter
// Generate the data_buf_address written into the memory controller
// for reads. Increment with each accepted read, and rollover at 0xf.
reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_r_lcl;
assign rd_data_buf_addr_r = rd_data_buf_addr_r_lcl;
begin : data_buf_addr
reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_buf_addr_ns;
always @(/*AS*/rd_accepted or rd_data_buf_addr_r_lcl or rst) begin
rd_data_buf_addr_ns = rd_data_buf_addr_r_lcl;
if (rst) rd_data_buf_addr_ns = 0;
else if (rd_accepted) rd_data_buf_addr_ns =
rd_data_buf_addr_r_lcl + 1;
end
always @(posedge clk) rd_data_buf_addr_r_lcl <=
#TCQ rd_data_buf_addr_ns;
end // block: data_buf_addr
end // block: not_strict_mode
endgenerate
endmodule // ui_rd_data
// Local Variables:
// verilog-library-directories:(".")
// End:
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_dirvec_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: dirvec_dp.v
*/
////////////////////////////////////////////////////////////////////////
module sctag_dirvec_dp( /*AUTOARG*/
// Outputs
dirdp_req_vec_c6, dirdp_way_info_c7, dirdp_inval_pckt_c7, so,
// Inputs
se, si, ic_cam_hit, dc_cam_hit, tagdp_lkup_addr11_c5, sel_mux1_c6,
sel_mux2_c6, sel_mux3_c6, mux_vec_sel_c6, rclk
) ;
input se, si;
input [127:0] ic_cam_hit;
input [127:0] dc_cam_hit;
input tagdp_lkup_addr11_c5;
input [ 3:0] sel_mux1_c6;
input [ 3:0] sel_mux2_c6;
input sel_mux3_c6;
input [ 3:0] mux_vec_sel_c6;
input rclk;
output [ 7:0] dirdp_req_vec_c6;
output [ 2:0] dirdp_way_info_c7;
output [111:0] dirdp_inval_pckt_c7;
output so;
wire [127:0] dc_cam_hit_c6;
wire [127:0] ic_cam_hit_c6;
wire [127:0] dc_cam_hit_c5;
wire [ 63:0] ic_cam_hit_c5;
wire [111:0] dirdp_inval_pckt_c6;
wire [ 2:0] dirvecdp_way_info_c6;
wire [111:0] dirdp_inval_pckt_c7;
wire [ 2:0] dirvecdp_way_info_c7;
//************************************************************************************
// FLOP INVAL PCKT TILL C6
//************************************************************************************
dff_s #(112) ff_dirdp_inval_pckt_c7 (.din(dirdp_inval_pckt_c6[111:0]),
.clk(rclk),
.q(dirdp_inval_pckt_c7[111:0]),
.se(se),
.si(),
.so());
//************************************************************************************
// FLOP way INFO PCKT TILL C6
//************************************************************************************
dff_s #(3) ff_dirvecdp_way_info_c7 (.din(dirvecdp_way_info_c6[2:0]),
.clk(rclk),
.q(dirvecdp_way_info_c7[2:0]),
.se(se),
.si(),
.so());
assign dirdp_way_info_c7 = dirvecdp_way_info_c7 ;
//*****************************************************************************
// PIPELINE FOR DIR VEC GENERATION
// DC cam hit has to be 128 b.
// IC cam hit is 64b and the 128b output of icdir needs to be muxed.
//*****************************************************************************
assign dc_cam_hit_c5 = dc_cam_hit ;
dff_s #(128) ff_dc_cam_hit_c6 ( .din(dc_cam_hit_c5[127:0]),
.clk(rclk),
.q(dc_cam_hit_c6[127:0]),
.se(se),
.si(),
.so());
mux2ds #(32) mux1_cam_hit_c5 ( .dout(ic_cam_hit_c5[31:0]),
.in0(ic_cam_hit[31:0]),
.in1(ic_cam_hit[63:32]),
.sel0(~tagdp_lkup_addr11_c5),
.sel1(tagdp_lkup_addr11_c5));
mux2ds #(32) mux2_cam_hit_c5 ( .dout(ic_cam_hit_c5[63:32]),
.in0(ic_cam_hit[95:64]),
.in1(ic_cam_hit[127:96]),
.sel0(~tagdp_lkup_addr11_c5),
.sel1(tagdp_lkup_addr11_c5));
dff_s #(32) ff_dc1_cam_hit_c6 ( .din(ic_cam_hit_c5[31:0]),
.clk(rclk),
.q(ic_cam_hit_c6[31:0]),
.se(se),
.si(),
.so());
dff_s #(32) ff_dc2_cam_hit_c6 ( .din(ic_cam_hit_c5[63:32]),
.clk(rclk),
.q(ic_cam_hit_c6[95:64]),
.se(se),
.si(),
.so());
//*****************************************************************************
// FORM THE 112b PACKET in C4 ( step 1)
// Get the request vect to be sent to oq_dp
// Get the I$ and D$ invalidation way for L1 load misses.
// DC cam hit has to be 128 b.
// IC cam hit is 64b and the 128b output of icdir needs to be muxed.
//*****************************************************************************
// BITS 0 - 31 CORRESPOND to INDEX <5:4> = 00 for D$
// INDEX <5>=0 for I$
// GENERATED CODE
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec0_c6;
wire ic_dir_vec0_c6;
wire dir_hit_vec0_c6 ;
wire [1:0] enc_dc_vec0_way_c6;
wire [1:0] enc_ic_vec0_way_c6;
wire [1:0] enc_c_vec0_way_c6;
wire [2:0] way_way_vld0_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec4_c6;
wire ic_dir_vec4_c6;
wire dir_hit_vec4_c6 ;
wire [1:0] enc_dc_vec4_way_c6;
wire [1:0] enc_ic_vec4_way_c6;
wire [1:0] enc_c_vec4_way_c6;
wire [2:0] way_way_vld4_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec8_c6;
wire ic_dir_vec8_c6;
wire dir_hit_vec8_c6 ;
wire [1:0] enc_dc_vec8_way_c6;
wire [1:0] enc_ic_vec8_way_c6;
wire [1:0] enc_c_vec8_way_c6;
wire [2:0] way_way_vld8_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec12_c6;
wire ic_dir_vec12_c6;
wire dir_hit_vec12_c6 ;
wire [1:0] enc_dc_vec12_way_c6;
wire [1:0] enc_ic_vec12_way_c6;
wire [1:0] enc_c_vec12_way_c6;
wire [2:0] way_way_vld12_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec16_c6;
wire ic_dir_vec16_c6;
wire dir_hit_vec16_c6 ;
wire [1:0] enc_dc_vec16_way_c6;
wire [1:0] enc_ic_vec16_way_c6;
wire [1:0] enc_c_vec16_way_c6;
wire [2:0] way_way_vld16_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec20_c6;
wire ic_dir_vec20_c6;
wire dir_hit_vec20_c6 ;
wire [1:0] enc_dc_vec20_way_c6;
wire [1:0] enc_ic_vec20_way_c6;
wire [1:0] enc_c_vec20_way_c6;
wire [2:0] way_way_vld20_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec24_c6;
wire ic_dir_vec24_c6;
wire dir_hit_vec24_c6 ;
wire [1:0] enc_dc_vec24_way_c6;
wire [1:0] enc_ic_vec24_way_c6;
wire [1:0] enc_c_vec24_way_c6;
wire [2:0] way_way_vld24_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START wire declarations FOR 0-31 ******************/
// Variables needed for hit Addr<5:4> = 2'b0
wire dc_dir_vec28_c6;
wire ic_dir_vec28_c6;
wire dir_hit_vec28_c6 ;
wire [1:0] enc_dc_vec28_way_c6;
wire [1:0] enc_ic_vec28_way_c6;
wire [1:0] enc_c_vec28_way_c6;
wire [2:0] way_way_vld28_c6 ;
/***************** END wire declarations FOR 0-31 ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec0_c6 = ( dc_cam_hit_c6[0] | dc_cam_hit_c6[1] |
dc_cam_hit_c6[2] | dc_cam_hit_c6[3] ) ;
// indicates whether I
assign ic_dir_vec0_c6 = ( ic_cam_hit_c6[0] | ic_cam_hit_c6[1] |
ic_cam_hit_c6[2] | ic_cam_hit_c6[3] ) ;
// indicates whether hit
assign dir_hit_vec0_c6 = dc_dir_vec0_c6 | ic_dir_vec0_c6 ;
// hit way in D
assign enc_dc_vec0_way_c6[0] = dc_cam_hit_c6[1] | dc_cam_hit_c6[3] ;
assign enc_dc_vec0_way_c6[1] = dc_cam_hit_c6[2] | dc_cam_hit_c6[3] ;
// hit way in I
assign enc_ic_vec0_way_c6[0] = ic_cam_hit_c6[1] | ic_cam_hit_c6[3] ;
assign enc_ic_vec0_way_c6[1] = ic_cam_hit_c6[2] | ic_cam_hit_c6[3] ;
mux2ds #(2) mux2_c_vec0_way ( .dout(enc_c_vec0_way_c6[1:0]),
.in0(enc_dc_vec0_way_c6[1:0]),
.in1(enc_ic_vec0_way_c6[1:0]),
.sel0(~ic_dir_vec0_c6),
.sel1(ic_dir_vec0_c6));
assign way_way_vld0_c6[0] = enc_c_vec0_way_c6[0] ;
assign way_way_vld0_c6[1] = enc_c_vec0_way_c6[1] ;
assign way_way_vld0_c6[2] = dir_hit_vec0_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec4_c6 = ( dc_cam_hit_c6[4] | dc_cam_hit_c6[5] |
dc_cam_hit_c6[6] | dc_cam_hit_c6[7] ) ;
// indicates whether I
assign ic_dir_vec4_c6 = ( ic_cam_hit_c6[4] | ic_cam_hit_c6[5] |
ic_cam_hit_c6[6] | ic_cam_hit_c6[7] ) ;
// indicates whether hit
assign dir_hit_vec4_c6 = dc_dir_vec4_c6 | ic_dir_vec4_c6 ;
// hit way in D
assign enc_dc_vec4_way_c6[0] = dc_cam_hit_c6[5] | dc_cam_hit_c6[7] ;
assign enc_dc_vec4_way_c6[1] = dc_cam_hit_c6[6] | dc_cam_hit_c6[7] ;
// hit way in I
assign enc_ic_vec4_way_c6[0] = ic_cam_hit_c6[5] | ic_cam_hit_c6[7] ;
assign enc_ic_vec4_way_c6[1] = ic_cam_hit_c6[6] | ic_cam_hit_c6[7] ;
mux2ds #(2) mux2_c_vec4_way ( .dout(enc_c_vec4_way_c6[1:0]),
.in0(enc_dc_vec4_way_c6[1:0]),
.in1(enc_ic_vec4_way_c6[1:0]),
.sel0(~ic_dir_vec4_c6),
.sel1(ic_dir_vec4_c6));
assign way_way_vld4_c6[0] = enc_c_vec4_way_c6[0] ;
assign way_way_vld4_c6[1] = enc_c_vec4_way_c6[1] ;
assign way_way_vld4_c6[2] = dir_hit_vec4_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec8_c6 = ( dc_cam_hit_c6[8] | dc_cam_hit_c6[9] |
dc_cam_hit_c6[10] | dc_cam_hit_c6[11] ) ;
// indicates whether I
assign ic_dir_vec8_c6 = ( ic_cam_hit_c6[8] | ic_cam_hit_c6[9] |
ic_cam_hit_c6[10] | ic_cam_hit_c6[11] ) ;
// indicates whether hit
assign dir_hit_vec8_c6 = dc_dir_vec8_c6 | ic_dir_vec8_c6 ;
// hit way in D
assign enc_dc_vec8_way_c6[0] = dc_cam_hit_c6[9] | dc_cam_hit_c6[11] ;
assign enc_dc_vec8_way_c6[1] = dc_cam_hit_c6[10] | dc_cam_hit_c6[11] ;
// hit way in I
assign enc_ic_vec8_way_c6[0] = ic_cam_hit_c6[9] | ic_cam_hit_c6[11] ;
assign enc_ic_vec8_way_c6[1] = ic_cam_hit_c6[10] | ic_cam_hit_c6[11] ;
mux2ds #(2) mux2_c_vec8_way ( .dout(enc_c_vec8_way_c6[1:0]),
.in0(enc_dc_vec8_way_c6[1:0]),
.in1(enc_ic_vec8_way_c6[1:0]),
.sel0(~ic_dir_vec8_c6),
.sel1(ic_dir_vec8_c6));
assign way_way_vld8_c6[0] = enc_c_vec8_way_c6[0] ;
assign way_way_vld8_c6[1] = enc_c_vec8_way_c6[1] ;
assign way_way_vld8_c6[2] = dir_hit_vec8_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec12_c6 = ( dc_cam_hit_c6[12] | dc_cam_hit_c6[13] |
dc_cam_hit_c6[14] | dc_cam_hit_c6[15] ) ;
// indicates whether I
assign ic_dir_vec12_c6 = ( ic_cam_hit_c6[12] | ic_cam_hit_c6[13] |
ic_cam_hit_c6[14] | ic_cam_hit_c6[15] ) ;
// indicates whether hit
assign dir_hit_vec12_c6 = dc_dir_vec12_c6 | ic_dir_vec12_c6 ;
// hit way in D
assign enc_dc_vec12_way_c6[0] = dc_cam_hit_c6[13] | dc_cam_hit_c6[15] ;
assign enc_dc_vec12_way_c6[1] = dc_cam_hit_c6[14] | dc_cam_hit_c6[15] ;
// hit way in I
assign enc_ic_vec12_way_c6[0] = ic_cam_hit_c6[13] | ic_cam_hit_c6[15] ;
assign enc_ic_vec12_way_c6[1] = ic_cam_hit_c6[14] | ic_cam_hit_c6[15] ;
mux2ds #(2) mux2_c_vec12_way ( .dout(enc_c_vec12_way_c6[1:0]),
.in0(enc_dc_vec12_way_c6[1:0]),
.in1(enc_ic_vec12_way_c6[1:0]),
.sel0(~ic_dir_vec12_c6),
.sel1(ic_dir_vec12_c6));
assign way_way_vld12_c6[0] = enc_c_vec12_way_c6[0] ;
assign way_way_vld12_c6[1] = enc_c_vec12_way_c6[1] ;
assign way_way_vld12_c6[2] = dir_hit_vec12_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec16_c6 = ( dc_cam_hit_c6[16] | dc_cam_hit_c6[17] |
dc_cam_hit_c6[18] | dc_cam_hit_c6[19] ) ;
// indicates whether I
assign ic_dir_vec16_c6 = ( ic_cam_hit_c6[16] | ic_cam_hit_c6[17] |
ic_cam_hit_c6[18] | ic_cam_hit_c6[19] ) ;
// indicates whether hit
assign dir_hit_vec16_c6 = dc_dir_vec16_c6 | ic_dir_vec16_c6 ;
// hit way in D
assign enc_dc_vec16_way_c6[0] = dc_cam_hit_c6[17] | dc_cam_hit_c6[19] ;
assign enc_dc_vec16_way_c6[1] = dc_cam_hit_c6[18] | dc_cam_hit_c6[19] ;
// hit way in I
assign enc_ic_vec16_way_c6[0] = ic_cam_hit_c6[17] | ic_cam_hit_c6[19] ;
assign enc_ic_vec16_way_c6[1] = ic_cam_hit_c6[18] | ic_cam_hit_c6[19] ;
mux2ds #(2) mux2_c_vec16_way ( .dout(enc_c_vec16_way_c6[1:0]),
.in0(enc_dc_vec16_way_c6[1:0]),
.in1(enc_ic_vec16_way_c6[1:0]),
.sel0(~ic_dir_vec16_c6),
.sel1(ic_dir_vec16_c6));
assign way_way_vld16_c6[0] = enc_c_vec16_way_c6[0] ;
assign way_way_vld16_c6[1] = enc_c_vec16_way_c6[1] ;
assign way_way_vld16_c6[2] = dir_hit_vec16_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec20_c6 = ( dc_cam_hit_c6[20] | dc_cam_hit_c6[21] |
dc_cam_hit_c6[22] | dc_cam_hit_c6[23] ) ;
// indicates whether I
assign ic_dir_vec20_c6 = ( ic_cam_hit_c6[20] | ic_cam_hit_c6[21] |
ic_cam_hit_c6[22] | ic_cam_hit_c6[23] ) ;
// indicates whether hit
assign dir_hit_vec20_c6 = dc_dir_vec20_c6 | ic_dir_vec20_c6 ;
// hit way in D
assign enc_dc_vec20_way_c6[0] = dc_cam_hit_c6[21] | dc_cam_hit_c6[23] ;
assign enc_dc_vec20_way_c6[1] = dc_cam_hit_c6[22] | dc_cam_hit_c6[23] ;
// hit way in I
assign enc_ic_vec20_way_c6[0] = ic_cam_hit_c6[21] | ic_cam_hit_c6[23] ;
assign enc_ic_vec20_way_c6[1] = ic_cam_hit_c6[22] | ic_cam_hit_c6[23] ;
mux2ds #(2) mux2_c_vec20_way ( .dout(enc_c_vec20_way_c6[1:0]),
.in0(enc_dc_vec20_way_c6[1:0]),
.in1(enc_ic_vec20_way_c6[1:0]),
.sel0(~ic_dir_vec20_c6),
.sel1(ic_dir_vec20_c6));
assign way_way_vld20_c6[0] = enc_c_vec20_way_c6[0] ;
assign way_way_vld20_c6[1] = enc_c_vec20_way_c6[1] ;
assign way_way_vld20_c6[2] = dir_hit_vec20_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec24_c6 = ( dc_cam_hit_c6[24] | dc_cam_hit_c6[25] |
dc_cam_hit_c6[26] | dc_cam_hit_c6[27] ) ;
// indicates whether I
assign ic_dir_vec24_c6 = ( ic_cam_hit_c6[24] | ic_cam_hit_c6[25] |
ic_cam_hit_c6[26] | ic_cam_hit_c6[27] ) ;
// indicates whether hit
assign dir_hit_vec24_c6 = dc_dir_vec24_c6 | ic_dir_vec24_c6 ;
// hit way in D
assign enc_dc_vec24_way_c6[0] = dc_cam_hit_c6[25] | dc_cam_hit_c6[27] ;
assign enc_dc_vec24_way_c6[1] = dc_cam_hit_c6[26] | dc_cam_hit_c6[27] ;
// hit way in I
assign enc_ic_vec24_way_c6[0] = ic_cam_hit_c6[25] | ic_cam_hit_c6[27] ;
assign enc_ic_vec24_way_c6[1] = ic_cam_hit_c6[26] | ic_cam_hit_c6[27] ;
mux2ds #(2) mux2_c_vec24_way ( .dout(enc_c_vec24_way_c6[1:0]),
.in0(enc_dc_vec24_way_c6[1:0]),
.in1(enc_ic_vec24_way_c6[1:0]),
.sel0(~ic_dir_vec24_c6),
.sel1(ic_dir_vec24_c6));
assign way_way_vld24_c6[0] = enc_c_vec24_way_c6[0] ;
assign way_way_vld24_c6[1] = enc_c_vec24_way_c6[1] ;
assign way_way_vld24_c6[2] = dir_hit_vec24_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec28_c6 = ( dc_cam_hit_c6[28] | dc_cam_hit_c6[29] |
dc_cam_hit_c6[30] | dc_cam_hit_c6[31] ) ;
// indicates whether I
assign ic_dir_vec28_c6 = ( ic_cam_hit_c6[28] | ic_cam_hit_c6[29] |
ic_cam_hit_c6[30] | ic_cam_hit_c6[31] ) ;
// indicates whether hit
assign dir_hit_vec28_c6 = dc_dir_vec28_c6 | ic_dir_vec28_c6 ;
// hit way in D
assign enc_dc_vec28_way_c6[0] = dc_cam_hit_c6[29] | dc_cam_hit_c6[31] ;
assign enc_dc_vec28_way_c6[1] = dc_cam_hit_c6[30] | dc_cam_hit_c6[31] ;
// hit way in I
assign enc_ic_vec28_way_c6[0] = ic_cam_hit_c6[29] | ic_cam_hit_c6[31] ;
assign enc_ic_vec28_way_c6[1] = ic_cam_hit_c6[30] | ic_cam_hit_c6[31] ;
mux2ds #(2) mux2_c_vec28_way ( .dout(enc_c_vec28_way_c6[1:0]),
.in0(enc_dc_vec28_way_c6[1:0]),
.in1(enc_ic_vec28_way_c6[1:0]),
.sel0(~ic_dir_vec28_c6),
.sel1(ic_dir_vec28_c6));
assign way_way_vld28_c6[0] = enc_c_vec28_way_c6[0] ;
assign way_way_vld28_c6[1] = enc_c_vec28_way_c6[1] ;
assign way_way_vld28_c6[2] = dir_hit_vec28_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating way wayvld00 ******************/
wire [2:0] way_wayvld00_mux1_c6;
wire [2:0] way_wayvld00_mux2_c6;
wire [2:0] way_wayvld00_mux3_c6;
mux4ds #(3) mux1_way_way_wayvld00_c6 ( .dout(way_wayvld00_mux1_c6[2:0]),
.in0(way_way_vld0_c6[2:0]),
.in1(way_way_vld4_c6[2:0]),
.in2(way_way_vld8_c6[2:0]),
.in3(way_way_vld12_c6[2:0]),
.sel0(sel_mux1_c6[0]),
.sel1(sel_mux1_c6[1]),
.sel2(sel_mux1_c6[2]),
.sel3(sel_mux1_c6[3]));
mux4ds #(3) mux2_way_way_wayvld00_c6 ( .dout(way_wayvld00_mux2_c6[2:0]),
.in0(way_way_vld16_c6[2:0]),
.in1(way_way_vld20_c6[2:0]),
.in2(way_way_vld24_c6[2:0]),
.in3(way_way_vld28_c6[2:0]),
.sel0(sel_mux2_c6[0]),
.sel1(sel_mux2_c6[1]),
.sel2(sel_mux2_c6[2]),
.sel3(sel_mux2_c6[3]));
mux2ds #(3) mux3_way_way_wayvld00_c6 ( .dout(way_wayvld00_mux3_c6[2:0]),
.in0(way_wayvld00_mux1_c6[2:0]),
.in1(way_wayvld00_mux2_c6[2:0]),
.sel0(sel_mux3_c6),
.sel1(~sel_mux3_c6));
/***************** END code for generating way wayvld00 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec32_c6;
wire dir_hit_vec32_c6 ;
wire [1:0] enc_dc_vec32_way_c6;
wire [1:0] enc_c_vec32_way_c6;
wire [2:0] way_way_vld32_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec36_c6;
wire dir_hit_vec36_c6 ;
wire [1:0] enc_dc_vec36_way_c6;
wire [1:0] enc_c_vec36_way_c6;
wire [2:0] way_way_vld36_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec40_c6;
wire dir_hit_vec40_c6 ;
wire [1:0] enc_dc_vec40_way_c6;
wire [1:0] enc_c_vec40_way_c6;
wire [2:0] way_way_vld40_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec44_c6;
wire dir_hit_vec44_c6 ;
wire [1:0] enc_dc_vec44_way_c6;
wire [1:0] enc_c_vec44_way_c6;
wire [2:0] way_way_vld44_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec48_c6;
wire dir_hit_vec48_c6 ;
wire [1:0] enc_dc_vec48_way_c6;
wire [1:0] enc_c_vec48_way_c6;
wire [2:0] way_way_vld48_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec52_c6;
wire dir_hit_vec52_c6 ;
wire [1:0] enc_dc_vec52_way_c6;
wire [1:0] enc_c_vec52_way_c6;
wire [2:0] way_way_vld52_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec56_c6;
wire dir_hit_vec56_c6 ;
wire [1:0] enc_dc_vec56_way_c6;
wire [1:0] enc_c_vec56_way_c6;
wire [2:0] way_way_vld56_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START wire declarations FOR 32-63 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec60_c6;
wire dir_hit_vec60_c6 ;
wire [1:0] enc_dc_vec60_way_c6;
wire [1:0] enc_c_vec60_way_c6;
wire [2:0] way_way_vld60_c6 ;
/***************** START wire declarations FOR 32-63 ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec32_c6 = ( dc_cam_hit_c6[32] | dc_cam_hit_c6[33] |
dc_cam_hit_c6[34] | dc_cam_hit_c6[35] ) ;
// hit way in D
assign enc_dc_vec32_way_c6[0] = dc_cam_hit_c6[33] | dc_cam_hit_c6[35] ;
assign enc_dc_vec32_way_c6[1] = dc_cam_hit_c6[34] | dc_cam_hit_c6[35] ;
assign dir_hit_vec32_c6 = dc_dir_vec32_c6 ;
assign enc_c_vec32_way_c6[1:0] = enc_dc_vec32_way_c6[1:0] ;
assign way_way_vld32_c6[0] = enc_c_vec32_way_c6[0] ;
assign way_way_vld32_c6[1] = enc_c_vec32_way_c6[1] ;
assign way_way_vld32_c6[2] = dir_hit_vec32_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec36_c6 = ( dc_cam_hit_c6[36] | dc_cam_hit_c6[37] |
dc_cam_hit_c6[38] | dc_cam_hit_c6[39] ) ;
// hit way in D
assign enc_dc_vec36_way_c6[0] = dc_cam_hit_c6[37] | dc_cam_hit_c6[39] ;
assign enc_dc_vec36_way_c6[1] = dc_cam_hit_c6[38] | dc_cam_hit_c6[39] ;
assign dir_hit_vec36_c6 = dc_dir_vec36_c6 ;
assign enc_c_vec36_way_c6[1:0] = enc_dc_vec36_way_c6[1:0] ;
assign way_way_vld36_c6[0] = enc_c_vec36_way_c6[0] ;
assign way_way_vld36_c6[1] = enc_c_vec36_way_c6[1] ;
assign way_way_vld36_c6[2] = dir_hit_vec36_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec40_c6 = ( dc_cam_hit_c6[40] | dc_cam_hit_c6[41] |
dc_cam_hit_c6[42] | dc_cam_hit_c6[43] ) ;
// hit way in D
assign enc_dc_vec40_way_c6[0] = dc_cam_hit_c6[41] | dc_cam_hit_c6[43] ;
assign enc_dc_vec40_way_c6[1] = dc_cam_hit_c6[42] | dc_cam_hit_c6[43] ;
assign dir_hit_vec40_c6 = dc_dir_vec40_c6 ;
assign enc_c_vec40_way_c6[1:0] = enc_dc_vec40_way_c6[1:0] ;
assign way_way_vld40_c6[0] = enc_c_vec40_way_c6[0] ;
assign way_way_vld40_c6[1] = enc_c_vec40_way_c6[1] ;
assign way_way_vld40_c6[2] = dir_hit_vec40_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec44_c6 = ( dc_cam_hit_c6[44] | dc_cam_hit_c6[45] |
dc_cam_hit_c6[46] | dc_cam_hit_c6[47] ) ;
// hit way in D
assign enc_dc_vec44_way_c6[0] = dc_cam_hit_c6[45] | dc_cam_hit_c6[47] ;
assign enc_dc_vec44_way_c6[1] = dc_cam_hit_c6[46] | dc_cam_hit_c6[47] ;
assign dir_hit_vec44_c6 = dc_dir_vec44_c6 ;
assign enc_c_vec44_way_c6[1:0] = enc_dc_vec44_way_c6[1:0] ;
assign way_way_vld44_c6[0] = enc_c_vec44_way_c6[0] ;
assign way_way_vld44_c6[1] = enc_c_vec44_way_c6[1] ;
assign way_way_vld44_c6[2] = dir_hit_vec44_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec48_c6 = ( dc_cam_hit_c6[48] | dc_cam_hit_c6[49] |
dc_cam_hit_c6[50] | dc_cam_hit_c6[51] ) ;
// hit way in D
assign enc_dc_vec48_way_c6[0] = dc_cam_hit_c6[49] | dc_cam_hit_c6[51] ;
assign enc_dc_vec48_way_c6[1] = dc_cam_hit_c6[50] | dc_cam_hit_c6[51] ;
assign dir_hit_vec48_c6 = dc_dir_vec48_c6 ;
assign enc_c_vec48_way_c6[1:0] = enc_dc_vec48_way_c6[1:0] ;
assign way_way_vld48_c6[0] = enc_c_vec48_way_c6[0] ;
assign way_way_vld48_c6[1] = enc_c_vec48_way_c6[1] ;
assign way_way_vld48_c6[2] = dir_hit_vec48_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec52_c6 = ( dc_cam_hit_c6[52] | dc_cam_hit_c6[53] |
dc_cam_hit_c6[54] | dc_cam_hit_c6[55] ) ;
// hit way in D
assign enc_dc_vec52_way_c6[0] = dc_cam_hit_c6[53] | dc_cam_hit_c6[55] ;
assign enc_dc_vec52_way_c6[1] = dc_cam_hit_c6[54] | dc_cam_hit_c6[55] ;
assign dir_hit_vec52_c6 = dc_dir_vec52_c6 ;
assign enc_c_vec52_way_c6[1:0] = enc_dc_vec52_way_c6[1:0] ;
assign way_way_vld52_c6[0] = enc_c_vec52_way_c6[0] ;
assign way_way_vld52_c6[1] = enc_c_vec52_way_c6[1] ;
assign way_way_vld52_c6[2] = dir_hit_vec52_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec56_c6 = ( dc_cam_hit_c6[56] | dc_cam_hit_c6[57] |
dc_cam_hit_c6[58] | dc_cam_hit_c6[59] ) ;
// hit way in D
assign enc_dc_vec56_way_c6[0] = dc_cam_hit_c6[57] | dc_cam_hit_c6[59] ;
assign enc_dc_vec56_way_c6[1] = dc_cam_hit_c6[58] | dc_cam_hit_c6[59] ;
assign dir_hit_vec56_c6 = dc_dir_vec56_c6 ;
assign enc_c_vec56_way_c6[1:0] = enc_dc_vec56_way_c6[1:0] ;
assign way_way_vld56_c6[0] = enc_c_vec56_way_c6[0] ;
assign way_way_vld56_c6[1] = enc_c_vec56_way_c6[1] ;
assign way_way_vld56_c6[2] = dir_hit_vec56_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec60_c6 = ( dc_cam_hit_c6[60] | dc_cam_hit_c6[61] |
dc_cam_hit_c6[62] | dc_cam_hit_c6[63] ) ;
// hit way in D
assign enc_dc_vec60_way_c6[0] = dc_cam_hit_c6[61] | dc_cam_hit_c6[63] ;
assign enc_dc_vec60_way_c6[1] = dc_cam_hit_c6[62] | dc_cam_hit_c6[63] ;
assign dir_hit_vec60_c6 = dc_dir_vec60_c6 ;
assign enc_c_vec60_way_c6[1:0] = enc_dc_vec60_way_c6[1:0] ;
assign way_way_vld60_c6[0] = enc_c_vec60_way_c6[0] ;
assign way_way_vld60_c6[1] = enc_c_vec60_way_c6[1] ;
assign way_way_vld60_c6[2] = dir_hit_vec60_c6 ;
/***************** END code for generating return pckt. ******************/
wire [2:0] way_wayvld01_mux1_c6;
wire [2:0] way_wayvld01_mux2_c6;
wire [2:0] way_wayvld01_mux3_c6;
mux4ds #(3) mux1_way_way_wayvld01_c6 ( .dout(way_wayvld01_mux1_c6[2:0]),
.in0(way_way_vld32_c6[2:0]),
.in1(way_way_vld36_c6[2:0]),
.in2(way_way_vld40_c6[2:0]),
.in3(way_way_vld44_c6[2:0]),
.sel0(sel_mux1_c6[0]),
.sel1(sel_mux1_c6[1]),
.sel2(sel_mux1_c6[2]),
.sel3(sel_mux1_c6[3]));
mux4ds #(3) mux2_way_way_wayvld01_c6 ( .dout(way_wayvld01_mux2_c6[2:0]),
.in0(way_way_vld48_c6[2:0]),
.in1(way_way_vld52_c6[2:0]),
.in2(way_way_vld56_c6[2:0]),
.in3(way_way_vld60_c6[2:0]),
.sel0(sel_mux2_c6[0]),
.sel1(sel_mux2_c6[1]),
.sel2(sel_mux2_c6[2]),
.sel3(sel_mux2_c6[3]));
mux2ds #(3) mux3_way_way_wayvld01_c6 ( .dout(way_wayvld01_mux3_c6[2:0]),
.in0(way_wayvld01_mux1_c6[2:0]),
.in1(way_wayvld01_mux2_c6[2:0]),
.sel0(sel_mux3_c6),
.sel1(~sel_mux3_c6));
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec64_c6;
wire ic_dir_vec64_c6;
wire dir_hit_vec64_c6 ;
wire [1:0] enc_dc_vec64_way_c6;
wire [1:0] enc_ic_vec64_way_c6;
wire [1:0] enc_c_vec64_way_c6;
wire [2:0] way_way_vld64_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec68_c6;
wire ic_dir_vec68_c6;
wire dir_hit_vec68_c6 ;
wire [1:0] enc_dc_vec68_way_c6;
wire [1:0] enc_ic_vec68_way_c6;
wire [1:0] enc_c_vec68_way_c6;
wire [2:0] way_way_vld68_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec72_c6;
wire ic_dir_vec72_c6;
wire dir_hit_vec72_c6 ;
wire [1:0] enc_dc_vec72_way_c6;
wire [1:0] enc_ic_vec72_way_c6;
wire [1:0] enc_c_vec72_way_c6;
wire [2:0] way_way_vld72_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec76_c6;
wire ic_dir_vec76_c6;
wire dir_hit_vec76_c6 ;
wire [1:0] enc_dc_vec76_way_c6;
wire [1:0] enc_ic_vec76_way_c6;
wire [1:0] enc_c_vec76_way_c6;
wire [2:0] way_way_vld76_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec80_c6;
wire ic_dir_vec80_c6;
wire dir_hit_vec80_c6 ;
wire [1:0] enc_dc_vec80_way_c6;
wire [1:0] enc_ic_vec80_way_c6;
wire [1:0] enc_c_vec80_way_c6;
wire [2:0] way_way_vld80_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec84_c6;
wire ic_dir_vec84_c6;
wire dir_hit_vec84_c6 ;
wire [1:0] enc_dc_vec84_way_c6;
wire [1:0] enc_ic_vec84_way_c6;
wire [1:0] enc_c_vec84_way_c6;
wire [2:0] way_way_vld84_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec88_c6;
wire ic_dir_vec88_c6;
wire dir_hit_vec88_c6 ;
wire [1:0] enc_dc_vec88_way_c6;
wire [1:0] enc_ic_vec88_way_c6;
wire [1:0] enc_c_vec88_way_c6;
wire [2:0] way_way_vld88_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START wire declarations FOR 64-96 ******************/
// Variables needed for hit Addr<5:4> = 2'b2
wire dc_dir_vec92_c6;
wire ic_dir_vec92_c6;
wire dir_hit_vec92_c6 ;
wire [1:0] enc_dc_vec92_way_c6;
wire [1:0] enc_ic_vec92_way_c6;
wire [1:0] enc_c_vec92_way_c6;
wire [2:0] way_way_vld92_c6 ;
/***************** END wire declarations FOR 64-96 ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec64_c6 = ( dc_cam_hit_c6[64] | dc_cam_hit_c6[65] |
dc_cam_hit_c6[66] | dc_cam_hit_c6[67] ) ;
// indicates whether I hit
assign ic_dir_vec64_c6 = ( ic_cam_hit_c6[64] | ic_cam_hit_c6[65] |
ic_cam_hit_c6[66] | ic_cam_hit_c6[67] ) ;
// indicates whether hit
assign dir_hit_vec64_c6 = dc_dir_vec64_c6 | ic_dir_vec64_c6 ;
// D hit way
assign enc_dc_vec64_way_c6[0] = dc_cam_hit_c6[65] | dc_cam_hit_c6[67] ;
assign enc_dc_vec64_way_c6[1] = dc_cam_hit_c6[66] | dc_cam_hit_c6[67] ;
// I hit way
assign enc_ic_vec64_way_c6[0] = ic_cam_hit_c6[65] | ic_cam_hit_c6[67] ;
assign enc_ic_vec64_way_c6[1] = ic_cam_hit_c6[66] | ic_cam_hit_c6[67] ;
mux2ds #(2) mux2_c_vec64_way ( .dout(enc_c_vec64_way_c6[1:0]),
.in0(enc_dc_vec64_way_c6[1:0]),
.in1(enc_ic_vec64_way_c6[1:0]),
.sel0(~ic_dir_vec64_c6),
.sel1(ic_dir_vec64_c6));
assign way_way_vld64_c6[0] = enc_c_vec64_way_c6[0] ;
assign way_way_vld64_c6[1] = enc_c_vec64_way_c6[1] ;
assign way_way_vld64_c6[2] = dir_hit_vec64_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec68_c6 = ( dc_cam_hit_c6[68] | dc_cam_hit_c6[69] |
dc_cam_hit_c6[70] | dc_cam_hit_c6[71] ) ;
// indicates whether I hit
assign ic_dir_vec68_c6 = ( ic_cam_hit_c6[68] | ic_cam_hit_c6[69] |
ic_cam_hit_c6[70] | ic_cam_hit_c6[71] ) ;
// indicates whether hit
assign dir_hit_vec68_c6 = dc_dir_vec68_c6 | ic_dir_vec68_c6 ;
// D hit way
assign enc_dc_vec68_way_c6[0] = dc_cam_hit_c6[69] | dc_cam_hit_c6[71] ;
assign enc_dc_vec68_way_c6[1] = dc_cam_hit_c6[70] | dc_cam_hit_c6[71] ;
// I hit way
assign enc_ic_vec68_way_c6[0] = ic_cam_hit_c6[69] | ic_cam_hit_c6[71] ;
assign enc_ic_vec68_way_c6[1] = ic_cam_hit_c6[70] | ic_cam_hit_c6[71] ;
mux2ds #(2) mux2_c_vec68_way ( .dout(enc_c_vec68_way_c6[1:0]),
.in0(enc_dc_vec68_way_c6[1:0]),
.in1(enc_ic_vec68_way_c6[1:0]),
.sel0(~ic_dir_vec68_c6),
.sel1(ic_dir_vec68_c6));
assign way_way_vld68_c6[0] = enc_c_vec68_way_c6[0] ;
assign way_way_vld68_c6[1] = enc_c_vec68_way_c6[1] ;
assign way_way_vld68_c6[2] = dir_hit_vec68_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec72_c6 = ( dc_cam_hit_c6[72] | dc_cam_hit_c6[73] |
dc_cam_hit_c6[74] | dc_cam_hit_c6[75] ) ;
// indicates whether I hit
assign ic_dir_vec72_c6 = ( ic_cam_hit_c6[72] | ic_cam_hit_c6[73] |
ic_cam_hit_c6[74] | ic_cam_hit_c6[75] ) ;
// indicates whether hit
assign dir_hit_vec72_c6 = dc_dir_vec72_c6 | ic_dir_vec72_c6 ;
// D hit way
assign enc_dc_vec72_way_c6[0] = dc_cam_hit_c6[73] | dc_cam_hit_c6[75] ;
assign enc_dc_vec72_way_c6[1] = dc_cam_hit_c6[74] | dc_cam_hit_c6[75] ;
// I hit way
assign enc_ic_vec72_way_c6[0] = ic_cam_hit_c6[73] | ic_cam_hit_c6[75] ;
assign enc_ic_vec72_way_c6[1] = ic_cam_hit_c6[74] | ic_cam_hit_c6[75] ;
mux2ds #(2) mux2_c_vec72_way ( .dout(enc_c_vec72_way_c6[1:0]),
.in0(enc_dc_vec72_way_c6[1:0]),
.in1(enc_ic_vec72_way_c6[1:0]),
.sel0(~ic_dir_vec72_c6),
.sel1(ic_dir_vec72_c6));
assign way_way_vld72_c6[0] = enc_c_vec72_way_c6[0] ;
assign way_way_vld72_c6[1] = enc_c_vec72_way_c6[1] ;
assign way_way_vld72_c6[2] = dir_hit_vec72_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec76_c6 = ( dc_cam_hit_c6[76] | dc_cam_hit_c6[77] |
dc_cam_hit_c6[78] | dc_cam_hit_c6[79] ) ;
// indicates whether I hit
assign ic_dir_vec76_c6 = ( ic_cam_hit_c6[76] | ic_cam_hit_c6[77] |
ic_cam_hit_c6[78] | ic_cam_hit_c6[79] ) ;
// indicates whether hit
assign dir_hit_vec76_c6 = dc_dir_vec76_c6 | ic_dir_vec76_c6 ;
// D hit way
assign enc_dc_vec76_way_c6[0] = dc_cam_hit_c6[77] | dc_cam_hit_c6[79] ;
assign enc_dc_vec76_way_c6[1] = dc_cam_hit_c6[78] | dc_cam_hit_c6[79] ;
// I hit way
assign enc_ic_vec76_way_c6[0] = ic_cam_hit_c6[77] | ic_cam_hit_c6[79] ;
assign enc_ic_vec76_way_c6[1] = ic_cam_hit_c6[78] | ic_cam_hit_c6[79] ;
mux2ds #(2) mux2_c_vec76_way ( .dout(enc_c_vec76_way_c6[1:0]),
.in0(enc_dc_vec76_way_c6[1:0]),
.in1(enc_ic_vec76_way_c6[1:0]),
.sel0(~ic_dir_vec76_c6),
.sel1(ic_dir_vec76_c6));
assign way_way_vld76_c6[0] = enc_c_vec76_way_c6[0] ;
assign way_way_vld76_c6[1] = enc_c_vec76_way_c6[1] ;
assign way_way_vld76_c6[2] = dir_hit_vec76_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec80_c6 = ( dc_cam_hit_c6[80] | dc_cam_hit_c6[81] |
dc_cam_hit_c6[82] | dc_cam_hit_c6[83] ) ;
// indicates whether I hit
assign ic_dir_vec80_c6 = ( ic_cam_hit_c6[80] | ic_cam_hit_c6[81] |
ic_cam_hit_c6[82] | ic_cam_hit_c6[83] ) ;
// indicates whether hit
assign dir_hit_vec80_c6 = dc_dir_vec80_c6 | ic_dir_vec80_c6 ;
// D hit way
assign enc_dc_vec80_way_c6[0] = dc_cam_hit_c6[81] | dc_cam_hit_c6[83] ;
assign enc_dc_vec80_way_c6[1] = dc_cam_hit_c6[82] | dc_cam_hit_c6[83] ;
// I hit way
assign enc_ic_vec80_way_c6[0] = ic_cam_hit_c6[81] | ic_cam_hit_c6[83] ;
assign enc_ic_vec80_way_c6[1] = ic_cam_hit_c6[82] | ic_cam_hit_c6[83] ;
mux2ds #(2) mux2_c_vec80_way ( .dout(enc_c_vec80_way_c6[1:0]),
.in0(enc_dc_vec80_way_c6[1:0]),
.in1(enc_ic_vec80_way_c6[1:0]),
.sel0(~ic_dir_vec80_c6),
.sel1(ic_dir_vec80_c6));
assign way_way_vld80_c6[0] = enc_c_vec80_way_c6[0] ;
assign way_way_vld80_c6[1] = enc_c_vec80_way_c6[1] ;
assign way_way_vld80_c6[2] = dir_hit_vec80_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec84_c6 = ( dc_cam_hit_c6[84] | dc_cam_hit_c6[85] |
dc_cam_hit_c6[86] | dc_cam_hit_c6[87] ) ;
// indicates whether I hit
assign ic_dir_vec84_c6 = ( ic_cam_hit_c6[84] | ic_cam_hit_c6[85] |
ic_cam_hit_c6[86] | ic_cam_hit_c6[87] ) ;
// indicates whether hit
assign dir_hit_vec84_c6 = dc_dir_vec84_c6 | ic_dir_vec84_c6 ;
// D hit way
assign enc_dc_vec84_way_c6[0] = dc_cam_hit_c6[85] | dc_cam_hit_c6[87] ;
assign enc_dc_vec84_way_c6[1] = dc_cam_hit_c6[86] | dc_cam_hit_c6[87] ;
// I hit way
assign enc_ic_vec84_way_c6[0] = ic_cam_hit_c6[85] | ic_cam_hit_c6[87] ;
assign enc_ic_vec84_way_c6[1] = ic_cam_hit_c6[86] | ic_cam_hit_c6[87] ;
mux2ds #(2) mux2_c_vec84_way ( .dout(enc_c_vec84_way_c6[1:0]),
.in0(enc_dc_vec84_way_c6[1:0]),
.in1(enc_ic_vec84_way_c6[1:0]),
.sel0(~ic_dir_vec84_c6),
.sel1(ic_dir_vec84_c6));
assign way_way_vld84_c6[0] = enc_c_vec84_way_c6[0] ;
assign way_way_vld84_c6[1] = enc_c_vec84_way_c6[1] ;
assign way_way_vld84_c6[2] = dir_hit_vec84_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec88_c6 = ( dc_cam_hit_c6[88] | dc_cam_hit_c6[89] |
dc_cam_hit_c6[90] | dc_cam_hit_c6[91] ) ;
// indicates whether I hit
assign ic_dir_vec88_c6 = ( ic_cam_hit_c6[88] | ic_cam_hit_c6[89] |
ic_cam_hit_c6[90] | ic_cam_hit_c6[91] ) ;
// indicates whether hit
assign dir_hit_vec88_c6 = dc_dir_vec88_c6 | ic_dir_vec88_c6 ;
// D hit way
assign enc_dc_vec88_way_c6[0] = dc_cam_hit_c6[89] | dc_cam_hit_c6[91] ;
assign enc_dc_vec88_way_c6[1] = dc_cam_hit_c6[90] | dc_cam_hit_c6[91] ;
// I hit way
assign enc_ic_vec88_way_c6[0] = ic_cam_hit_c6[89] | ic_cam_hit_c6[91] ;
assign enc_ic_vec88_way_c6[1] = ic_cam_hit_c6[90] | ic_cam_hit_c6[91] ;
mux2ds #(2) mux2_c_vec88_way ( .dout(enc_c_vec88_way_c6[1:0]),
.in0(enc_dc_vec88_way_c6[1:0]),
.in1(enc_ic_vec88_way_c6[1:0]),
.sel0(~ic_dir_vec88_c6),
.sel1(ic_dir_vec88_c6));
assign way_way_vld88_c6[0] = enc_c_vec88_way_c6[0] ;
assign way_way_vld88_c6[1] = enc_c_vec88_way_c6[1] ;
assign way_way_vld88_c6[2] = dir_hit_vec88_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D
assign dc_dir_vec92_c6 = ( dc_cam_hit_c6[92] | dc_cam_hit_c6[93] |
dc_cam_hit_c6[94] | dc_cam_hit_c6[95] ) ;
// indicates whether I hit
assign ic_dir_vec92_c6 = ( ic_cam_hit_c6[92] | ic_cam_hit_c6[93] |
ic_cam_hit_c6[94] | ic_cam_hit_c6[95] ) ;
// indicates whether hit
assign dir_hit_vec92_c6 = dc_dir_vec92_c6 | ic_dir_vec92_c6 ;
// D hit way
assign enc_dc_vec92_way_c6[0] = dc_cam_hit_c6[93] | dc_cam_hit_c6[95] ;
assign enc_dc_vec92_way_c6[1] = dc_cam_hit_c6[94] | dc_cam_hit_c6[95] ;
// I hit way
assign enc_ic_vec92_way_c6[0] = ic_cam_hit_c6[93] | ic_cam_hit_c6[95] ;
assign enc_ic_vec92_way_c6[1] = ic_cam_hit_c6[94] | ic_cam_hit_c6[95] ;
mux2ds #(2) mux2_c_vec92_way ( .dout(enc_c_vec92_way_c6[1:0]),
.in0(enc_dc_vec92_way_c6[1:0]),
.in1(enc_ic_vec92_way_c6[1:0]),
.sel0(~ic_dir_vec92_c6),
.sel1(ic_dir_vec92_c6));
assign way_way_vld92_c6[0] = enc_c_vec92_way_c6[0] ;
assign way_way_vld92_c6[1] = enc_c_vec92_way_c6[1] ;
assign way_way_vld92_c6[2] = dir_hit_vec92_c6 ;
/***************** END code for generating return pckt. ******************/
wire [2:0] way_wayvld10_mux1_c6;
wire [2:0] way_wayvld10_mux2_c6;
wire [2:0] way_wayvld10_mux3_c6;
mux4ds #(3) mux1_way_way_wayvld10_c6 ( .dout(way_wayvld10_mux1_c6[2:0]),
.in0(way_way_vld64_c6[2:0]),
.in1(way_way_vld68_c6[2:0]),
.in2(way_way_vld72_c6[2:0]),
.in3(way_way_vld76_c6[2:0]),
.sel0(sel_mux1_c6[0]),
.sel1(sel_mux1_c6[1]),
.sel2(sel_mux1_c6[2]),
.sel3(sel_mux1_c6[3]));
mux4ds #(3) mux2_way_way_wayvld10_c6 ( .dout(way_wayvld10_mux2_c6[2:0]),
.in0(way_way_vld80_c6[2:0]),
.in1(way_way_vld84_c6[2:0]),
.in2(way_way_vld88_c6[2:0]),
.in3(way_way_vld92_c6[2:0]),
.sel0(sel_mux2_c6[0]),
.sel1(sel_mux2_c6[1]),
.sel2(sel_mux2_c6[2]),
.sel3(sel_mux2_c6[3]));
mux2ds #(3) mux3_way_way_wayvld10_c6 ( .dout(way_wayvld10_mux3_c6[2:0]),
.in0(way_wayvld10_mux1_c6[2:0]),
.in1(way_wayvld10_mux2_c6[2:0]),
.sel0(sel_mux3_c6),
.sel1(~sel_mux3_c6));
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec96_c6;
wire dir_hit_vec96_c6 ;
wire [1:0] enc_dc_vec96_way_c6;
wire [1:0] enc_c_vec96_way_c6;
wire [2:0] way_way_vld96_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec100_c6;
wire dir_hit_vec100_c6 ;
wire [1:0] enc_dc_vec100_way_c6;
wire [1:0] enc_c_vec100_way_c6;
wire [2:0] way_way_vld100_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec104_c6;
wire dir_hit_vec104_c6 ;
wire [1:0] enc_dc_vec104_way_c6;
wire [1:0] enc_c_vec104_way_c6;
wire [2:0] way_way_vld104_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec108_c6;
wire dir_hit_vec108_c6 ;
wire [1:0] enc_dc_vec108_way_c6;
wire [1:0] enc_c_vec108_way_c6;
wire [2:0] way_way_vld108_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec112_c6;
wire dir_hit_vec112_c6 ;
wire [1:0] enc_dc_vec112_way_c6;
wire [1:0] enc_c_vec112_way_c6;
wire [2:0] way_way_vld112_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec116_c6;
wire dir_hit_vec116_c6 ;
wire [1:0] enc_dc_vec116_way_c6;
wire [1:0] enc_c_vec116_way_c6;
wire [2:0] way_way_vld116_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec120_c6;
wire dir_hit_vec120_c6 ;
wire [1:0] enc_dc_vec120_way_c6;
wire [1:0] enc_c_vec120_way_c6;
wire [2:0] way_way_vld120_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START wire declarations FOR 96-128 ******************/
// Variables needed for hit Addr<5:4> = 2'b1
wire dc_dir_vec124_c6;
wire dir_hit_vec124_c6 ;
wire [1:0] enc_dc_vec124_way_c6;
wire [1:0] enc_c_vec124_way_c6;
wire [2:0] way_way_vld124_c6 ;
/***************** END wire declarations FOR 96-128 ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec96_c6 = ( dc_cam_hit_c6[96] | dc_cam_hit_c6[97] |
dc_cam_hit_c6[98] | dc_cam_hit_c6[99] ) ;
// D hit way
assign dir_hit_vec96_c6 = dc_dir_vec96_c6 ;
// hit way
assign enc_dc_vec96_way_c6[0] = dc_cam_hit_c6[97] | dc_cam_hit_c6[99] ;
assign enc_dc_vec96_way_c6[1] = dc_cam_hit_c6[98] | dc_cam_hit_c6[99] ;
assign enc_c_vec96_way_c6[1:0] = enc_dc_vec96_way_c6[1:0] ;
assign way_way_vld96_c6[0] = enc_c_vec96_way_c6[0] ;
assign way_way_vld96_c6[1] = enc_c_vec96_way_c6[1] ;
assign way_way_vld96_c6[2] = dir_hit_vec96_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec100_c6 = ( dc_cam_hit_c6[100] | dc_cam_hit_c6[101] |
dc_cam_hit_c6[102] | dc_cam_hit_c6[103] ) ;
// D hit way
assign dir_hit_vec100_c6 = dc_dir_vec100_c6 ;
// hit way
assign enc_dc_vec100_way_c6[0] = dc_cam_hit_c6[101] | dc_cam_hit_c6[103] ;
assign enc_dc_vec100_way_c6[1] = dc_cam_hit_c6[102] | dc_cam_hit_c6[103] ;
assign enc_c_vec100_way_c6[1:0] = enc_dc_vec100_way_c6[1:0] ;
assign way_way_vld100_c6[0] = enc_c_vec100_way_c6[0] ;
assign way_way_vld100_c6[1] = enc_c_vec100_way_c6[1] ;
assign way_way_vld100_c6[2] = dir_hit_vec100_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec104_c6 = ( dc_cam_hit_c6[104] | dc_cam_hit_c6[105] |
dc_cam_hit_c6[106] | dc_cam_hit_c6[107] ) ;
// D hit way
assign dir_hit_vec104_c6 = dc_dir_vec104_c6 ;
// hit way
assign enc_dc_vec104_way_c6[0] = dc_cam_hit_c6[105] | dc_cam_hit_c6[107] ;
assign enc_dc_vec104_way_c6[1] = dc_cam_hit_c6[106] | dc_cam_hit_c6[107] ;
assign enc_c_vec104_way_c6[1:0] = enc_dc_vec104_way_c6[1:0] ;
assign way_way_vld104_c6[0] = enc_c_vec104_way_c6[0] ;
assign way_way_vld104_c6[1] = enc_c_vec104_way_c6[1] ;
assign way_way_vld104_c6[2] = dir_hit_vec104_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec108_c6 = ( dc_cam_hit_c6[108] | dc_cam_hit_c6[109] |
dc_cam_hit_c6[110] | dc_cam_hit_c6[111] ) ;
// D hit way
assign dir_hit_vec108_c6 = dc_dir_vec108_c6 ;
// hit way
assign enc_dc_vec108_way_c6[0] = dc_cam_hit_c6[109] | dc_cam_hit_c6[111] ;
assign enc_dc_vec108_way_c6[1] = dc_cam_hit_c6[110] | dc_cam_hit_c6[111] ;
assign enc_c_vec108_way_c6[1:0] = enc_dc_vec108_way_c6[1:0] ;
assign way_way_vld108_c6[0] = enc_c_vec108_way_c6[0] ;
assign way_way_vld108_c6[1] = enc_c_vec108_way_c6[1] ;
assign way_way_vld108_c6[2] = dir_hit_vec108_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec112_c6 = ( dc_cam_hit_c6[112] | dc_cam_hit_c6[113] |
dc_cam_hit_c6[114] | dc_cam_hit_c6[115] ) ;
// D hit way
assign dir_hit_vec112_c6 = dc_dir_vec112_c6 ;
// hit way
assign enc_dc_vec112_way_c6[0] = dc_cam_hit_c6[113] | dc_cam_hit_c6[115] ;
assign enc_dc_vec112_way_c6[1] = dc_cam_hit_c6[114] | dc_cam_hit_c6[115] ;
assign enc_c_vec112_way_c6[1:0] = enc_dc_vec112_way_c6[1:0] ;
assign way_way_vld112_c6[0] = enc_c_vec112_way_c6[0] ;
assign way_way_vld112_c6[1] = enc_c_vec112_way_c6[1] ;
assign way_way_vld112_c6[2] = dir_hit_vec112_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec116_c6 = ( dc_cam_hit_c6[116] | dc_cam_hit_c6[117] |
dc_cam_hit_c6[118] | dc_cam_hit_c6[119] ) ;
// D hit way
assign dir_hit_vec116_c6 = dc_dir_vec116_c6 ;
// hit way
assign enc_dc_vec116_way_c6[0] = dc_cam_hit_c6[117] | dc_cam_hit_c6[119] ;
assign enc_dc_vec116_way_c6[1] = dc_cam_hit_c6[118] | dc_cam_hit_c6[119] ;
assign enc_c_vec116_way_c6[1:0] = enc_dc_vec116_way_c6[1:0] ;
assign way_way_vld116_c6[0] = enc_c_vec116_way_c6[0] ;
assign way_way_vld116_c6[1] = enc_c_vec116_way_c6[1] ;
assign way_way_vld116_c6[2] = dir_hit_vec116_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec120_c6 = ( dc_cam_hit_c6[120] | dc_cam_hit_c6[121] |
dc_cam_hit_c6[122] | dc_cam_hit_c6[123] ) ;
// D hit way
assign dir_hit_vec120_c6 = dc_dir_vec120_c6 ;
// hit way
assign enc_dc_vec120_way_c6[0] = dc_cam_hit_c6[121] | dc_cam_hit_c6[123] ;
assign enc_dc_vec120_way_c6[1] = dc_cam_hit_c6[122] | dc_cam_hit_c6[123] ;
assign enc_c_vec120_way_c6[1:0] = enc_dc_vec120_way_c6[1:0] ;
assign way_way_vld120_c6[0] = enc_c_vec120_way_c6[0] ;
assign way_way_vld120_c6[1] = enc_c_vec120_way_c6[1] ;
assign way_way_vld120_c6[2] = dir_hit_vec120_c6 ;
/***************** END code for generating return pckt. ******************/
/***************** START code for generating return pckt. ******************/
// indicates whether D hit.
assign dc_dir_vec124_c6 = ( dc_cam_hit_c6[124] | dc_cam_hit_c6[125] |
dc_cam_hit_c6[126] | dc_cam_hit_c6[127] ) ;
// D hit way
assign dir_hit_vec124_c6 = dc_dir_vec124_c6 ;
// hit way
assign enc_dc_vec124_way_c6[0] = dc_cam_hit_c6[125] | dc_cam_hit_c6[127] ;
assign enc_dc_vec124_way_c6[1] = dc_cam_hit_c6[126] | dc_cam_hit_c6[127] ;
assign enc_c_vec124_way_c6[1:0] = enc_dc_vec124_way_c6[1:0] ;
assign way_way_vld124_c6[0] = enc_c_vec124_way_c6[0] ;
assign way_way_vld124_c6[1] = enc_c_vec124_way_c6[1] ;
assign way_way_vld124_c6[2] = dir_hit_vec124_c6 ;
/***************** END code for generating return pckt. ******************/
wire [2:0] way_wayvld11_mux1_c6;
wire [2:0] way_wayvld11_mux2_c6;
wire [2:0] way_wayvld11_mux3_c6;
mux4ds #(3) mux1_way_way_wayvld11_c6 ( .dout(way_wayvld11_mux1_c6[2:0]),
.in0(way_way_vld96_c6[2:0]),
.in1(way_way_vld100_c6[2:0]),
.in2(way_way_vld104_c6[2:0]),
.in3(way_way_vld108_c6[2:0]),
.sel0(sel_mux1_c6[0]),
.sel1(sel_mux1_c6[1]),
.sel2(sel_mux1_c6[2]),
.sel3(sel_mux1_c6[3]));
mux4ds #(3) mux2_way_way_wayvld11_c6 ( .dout(way_wayvld11_mux2_c6[2:0]),
.in0(way_way_vld112_c6[2:0]),
.in1(way_way_vld116_c6[2:0]),
.in2(way_way_vld120_c6[2:0]),
.in3(way_way_vld124_c6[2:0]),
.sel0(sel_mux2_c6[0]),
.sel1(sel_mux2_c6[1]),
.sel2(sel_mux2_c6[2]),
.sel3(sel_mux2_c6[3]));
mux2ds #(3) mux3_way_way_wayvld11_c6 ( .dout(way_wayvld11_mux3_c6[2:0]),
.in0(way_wayvld11_mux1_c6[2:0]),
.in1(way_wayvld11_mux2_c6[2:0]),
.sel0(sel_mux3_c6),
.sel1(~sel_mux3_c6));
//*******************************************************************************************
// REQUEST VEC FORMATION
//*******************************************************************************************
assign dirdp_req_vec_c6[0] = dir_hit_vec0_c6 | dir_hit_vec32_c6 | dir_hit_vec64_c6 | dir_hit_vec96_c6 ;
assign dirdp_req_vec_c6[1] = dir_hit_vec4_c6 | dir_hit_vec36_c6 | dir_hit_vec68_c6 | dir_hit_vec100_c6 ;
assign dirdp_req_vec_c6[2] = dir_hit_vec8_c6 | dir_hit_vec40_c6 | dir_hit_vec72_c6 | dir_hit_vec104_c6 ;
assign dirdp_req_vec_c6[3] = dir_hit_vec12_c6 | dir_hit_vec44_c6 | dir_hit_vec76_c6 | dir_hit_vec108_c6 ;
assign dirdp_req_vec_c6[4] = dir_hit_vec16_c6 | dir_hit_vec48_c6 | dir_hit_vec80_c6 | dir_hit_vec112_c6 ;
assign dirdp_req_vec_c6[5] = dir_hit_vec20_c6 | dir_hit_vec52_c6 | dir_hit_vec84_c6 | dir_hit_vec116_c6 ;
assign dirdp_req_vec_c6[6] = dir_hit_vec24_c6 | dir_hit_vec56_c6 | dir_hit_vec88_c6 | dir_hit_vec120_c6 ;
assign dirdp_req_vec_c6[7] = dir_hit_vec28_c6 | dir_hit_vec60_c6 | dir_hit_vec92_c6 | dir_hit_vec124_c6 ;
//*******************************************************************************************
// INVALIDATE PACKET FORMATION
//*******************************************************************************************
// 32 bit dir vec.
assign dirdp_inval_pckt_c6[31:0] = { enc_c_vec28_way_c6, ic_dir_vec28_c6, dc_dir_vec28_c6,
enc_c_vec24_way_c6, ic_dir_vec24_c6, dc_dir_vec24_c6,
enc_c_vec20_way_c6, ic_dir_vec20_c6, dc_dir_vec20_c6,
enc_c_vec16_way_c6, ic_dir_vec16_c6, dc_dir_vec16_c6,
enc_c_vec12_way_c6, ic_dir_vec12_c6, dc_dir_vec12_c6,
enc_c_vec8_way_c6, ic_dir_vec8_c6, dc_dir_vec8_c6,
enc_c_vec4_way_c6, ic_dir_vec4_c6, dc_dir_vec4_c6,
enc_c_vec0_way_c6, ic_dir_vec0_c6, dc_dir_vec0_c6
} ;
// 32 bit dir vec.
assign dirdp_inval_pckt_c6[55:32] = { enc_c_vec60_way_c6, dc_dir_vec60_c6,
enc_c_vec56_way_c6, dc_dir_vec56_c6,
enc_c_vec52_way_c6, dc_dir_vec52_c6,
enc_c_vec48_way_c6, dc_dir_vec48_c6,
enc_c_vec44_way_c6, dc_dir_vec44_c6,
enc_c_vec40_way_c6, dc_dir_vec40_c6,
enc_c_vec36_way_c6, dc_dir_vec36_c6,
enc_c_vec32_way_c6, dc_dir_vec32_c6
} ;
assign dirdp_inval_pckt_c6[87:56] = { enc_c_vec92_way_c6, ic_dir_vec92_c6, dc_dir_vec92_c6,
enc_c_vec88_way_c6, ic_dir_vec88_c6, dc_dir_vec88_c6,
enc_c_vec84_way_c6, ic_dir_vec84_c6, dc_dir_vec84_c6,
enc_c_vec80_way_c6, ic_dir_vec80_c6, dc_dir_vec80_c6,
enc_c_vec76_way_c6, ic_dir_vec76_c6, dc_dir_vec76_c6,
enc_c_vec72_way_c6, ic_dir_vec72_c6, dc_dir_vec72_c6,
enc_c_vec68_way_c6, ic_dir_vec68_c6, dc_dir_vec68_c6,
enc_c_vec64_way_c6, ic_dir_vec64_c6, dc_dir_vec64_c6
} ;
// 32 bit dir vec.
assign dirdp_inval_pckt_c6[111:88] = { enc_c_vec124_way_c6, dc_dir_vec124_c6,
enc_c_vec120_way_c6, dc_dir_vec120_c6,
enc_c_vec116_way_c6, dc_dir_vec116_c6,
enc_c_vec112_way_c6, dc_dir_vec112_c6,
enc_c_vec108_way_c6, dc_dir_vec108_c6,
enc_c_vec104_way_c6, dc_dir_vec104_c6,
enc_c_vec100_way_c6, dc_dir_vec100_c6,
enc_c_vec96_way_c6, dc_dir_vec96_c6
} ;
//*******************************************************************************************
// GENERATION OR WAY AND WAYVLD FOR THE CPX RETURN
//*******************************************************************************************
mux4ds #(3) mux_way_waywayvld_c6 ( .dout(dirvecdp_way_info_c6[2:0]),
.in0(way_wayvld00_mux3_c6[2:0]),
.in1(way_wayvld01_mux3_c6[2:0]),
.in2(way_wayvld10_mux3_c6[2:0]),
.in3(way_wayvld11_mux3_c6[2:0]),
.sel0(mux_vec_sel_c6[0]),
.sel1(mux_vec_sel_c6[1]),
.sel2(mux_vec_sel_c6[2]),
.sel3(mux_vec_sel_c6[3]));
endmodule
|
// Taken from http://www.europa.com/~celiac/fsm_samp.html
// These are the symbolic names for states
parameter [1:0] //synopsys enum state_info
S0 = 2'h0,
S1 = 2'h1,
S2 = 2'h2,
S3 = 2'h3;
// These are the current state and next state variables
reg [1:0] /* synopsys enum state_info */ state;
reg [1:0] /* synopsys enum state_info */ next_state;
// synopsys state_vector state
always @ (state or y or x)
begin
next_state = state;
case (state) // synopsys full_case parallel_case
S0: begin
if (x) begin
next_state = S1;
end
else begin
next_state = S2;
end
end
S1: begin
if (y) begin
next_state = S2;
end
else begin
next_state = S0;
end
end
S2: begin
if (x & y) begin
next_state = S3;
end
else begin
next_state = S0;
end
end
S3: begin
next_state = S0;
end
endcase
end
always @ (posedge clk or posedge reset)
begin
if (reset) begin
state <= S0;
end
else begin
state <= next_state;
end
end
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This example catches the case of a unser defined function that is
* a parameter to a system task.
*/
module main;
function [15:0] sum;
input [15:0] a;
input [15:0] b;
sum = a + b;
endfunction // sum
initial begin
$display("%h = sum(%h, %h)", sum(3,5), 16'd3, 16'd5);
$display("PASSED");
end
endmodule // main
|
`timescale 1 ns / 1 ps
//
// KIA registers
//
`define KQSTAT 0
`define KQDATA 1
// KIA status flag bits
`define KQSF_EMPTY 8'h01
`define KQSF_FULL 8'h02
module TEST_KIA;
// To test the KIA, we need a Wishbone bus.
reg CLK_O;
reg RES_O;
// The KIA will communicate with the microprocessor through
// a typical memory bus interface.
reg [0:0] ADR_O;
reg WE_O;
reg CYC_O;
reg STB_O;
wire ACK_I;
wire [7:0] DAT_I;
// The KIA must also talk to a keyboard.
reg C_O;
reg D_O;
// This register is used to identify a specific test in progress.
// This eases correspondence between waveform traces and their
// corresponding (successful) tests.
reg [15:0] STORY_O;
// The KIA under test.
KIA kia(
.CLK_I(CLK_O),
.RES_I(RES_O),
.ADR_I(ADR_O),
.WE_I(WE_O),
.CYC_I(CYC_O),
.STB_I(STB_O),
.ACK_O(ACK_I),
.DAT_O(DAT_I),
.D_I(D_O),
.C_I(C_O)
);
always begin
#50 CLK_O <= ~CLK_O;
end;
initial begin
RES_O <= 0;
CLK_O <= 0;
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 0;
STB_O <= 0;
D_O <= 1;
C_O <= 1;
wait(CLK_O);
wait(~CLK_O);
// AS A systems programmer
// I WANT the KIA to report an empty queue after reset
// SO THAT I can start the operating system with a clean slate.
STORY_O <= 0;
RES_O <= 1;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != 8'h01) begin
$display("Expected queue to be empty."); $stop;
end
// AS A systems programmer
// I WANT the KIA to report a non-empty queue after receiving a keycode
// SO THAT I can pull the key code from the queue.
STORY_O <= 16'h0010;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != 8'h00) begin
$display("Expected queue to be neither full nor empty."); $stop;
end
// AS A systems programmer
// I WANT the keyboard queue to faithfully record the received scan code
// SO THAT I can respond intelligently to user input.
STORY_O <= 16'h0020;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != 8'h1B) begin
$display("Head of the queue doesn't have the right data byte."); $stop;
end
// AS A systems programmer
// I WANT the queue to capture multiple data bytes while I'm busy
// SO THAT I don't have to have such stringent real-time requirements.
STORY_O <= 16'h0030;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(ACK_I != 1) begin
$display("Single cycle response expected."); $stop;
end
if(DAT_I != 8'hE0) begin
$display("Expected 8'hE0 for first byte."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h1B) begin
$display("Expected 8'h1B for second byte."); $stop;
end
// AS A verilog engineer
// I WANT the KIA to drop excess characters when the queue is full
// SO THAT software engineers don't have to worry about key-code order issues.
STORY_O <= 16'h0040;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE0) begin
$display("Pattern mismatch on byte 0."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE1) begin
$display("Pattern mismatch on byte 1."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE2) begin
$display("Pattern mismatch on byte 2."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE3) begin
$display("Pattern mismatch on byte 3."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE4) begin
$display("Pattern mismatch on byte 4."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE5) begin
$display("Pattern mismatch on byte 5."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE6) begin
$display("Pattern mismatch on byte 6."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE7) begin
$display("Pattern mismatch on byte 7."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE8) begin
$display("Pattern mismatch on byte 8."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hE9) begin
$display("Pattern mismatch on byte 9."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hEA) begin
$display("Pattern mismatch on byte A."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hEB) begin
$display("Pattern mismatch on byte B."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hEC) begin
$display("Pattern mismatch on byte C."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hED) begin
$display("Pattern mismatch on byte D."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hEE) begin
$display("Pattern mismatch on byte E."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hCF) begin
$display("Pattern mismatch on byte F."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQDATA;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'hCF) begin
$display("Should not be able to read beyond the bottom of the queue."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
// AS A software engineer
// I WANT the KIA to indicate the queue is empty after reading the last available byte
// SO THAT my keyboard handling loops have an exit criterion.
STORY_O <= 16'h0050;
RES_O <= 1;
CYC_O <= 0;
STB_O <= 0;
WE_O <= 0;
wait(CLK_O); wait(~CLK_O);
RES_O <= 0;
wait(CLK_O); wait(~CLK_O);
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 0; #32768 C_O <= 0; #32768 C_O <= 1;
D_O <= 1; #32768 C_O <= 0; #32768 C_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != `KQSF_FULL) begin
$display("Before popping first byte, queue must be full."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 1."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 2."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 3."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 4."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 5."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 6."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 7."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 8."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte 9."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte A."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte B."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte C."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte D."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != 8'h00) begin
$display("Queue is neither full nor empty. Byte E."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != `KQSF_EMPTY) begin
$display("After reading 15 bytes, the queue should be empty."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
ADR_O <= `KQSTAT;
WE_O <= 0;
CYC_O <= 1;
STB_O <= 1;
wait(CLK_O); wait(~CLK_O);
if(DAT_I != `KQSF_EMPTY) begin
$display("Popping an empty queue should have no effect."); $stop;
end
ADR_O <= `KQDATA;
WE_O <= 1;
wait(CLK_O); wait(~CLK_O);
// AS A verilog engineer
// I WANT the end of all tests to be delineated on the waveform
// SO THAT I don't have to hunt around for the end of the test sequence.
STORY_O <= -1;
wait(CLK_O); wait(~CLK_O);
$stop;
end;
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_top (
nfa_initials_buckets_NPI_clk,
nfa_initials_buckets_NPI_reset,
nfa_initials_buckets_NPI_Addr,
nfa_initials_buckets_NPI_AddrReq,
nfa_initials_buckets_NPI_AddrAck,
nfa_initials_buckets_NPI_RNW,
nfa_initials_buckets_NPI_Size,
nfa_initials_buckets_NPI_WrFIFO_Data,
nfa_initials_buckets_NPI_WrFIFO_BE,
nfa_initials_buckets_NPI_WrFIFO_Push,
nfa_initials_buckets_NPI_RdFIFO_Data,
nfa_initials_buckets_NPI_RdFIFO_Pop,
nfa_initials_buckets_NPI_RdFIFO_RdWdAddr,
nfa_initials_buckets_NPI_WrFIFO_Empty,
nfa_initials_buckets_NPI_WrFIFO_AlmostFull,
nfa_initials_buckets_NPI_WrFIFO_Flush,
nfa_initials_buckets_NPI_RdFIFO_Empty,
nfa_initials_buckets_NPI_RdFIFO_Flush,
nfa_initials_buckets_NPI_RdFIFO_Latency,
nfa_initials_buckets_NPI_RdModWr,
nfa_initials_buckets_NPI_InitDone,
nfa_finals_buckets_NPI_clk,
nfa_finals_buckets_NPI_reset,
nfa_finals_buckets_NPI_Addr,
nfa_finals_buckets_NPI_AddrReq,
nfa_finals_buckets_NPI_AddrAck,
nfa_finals_buckets_NPI_RNW,
nfa_finals_buckets_NPI_Size,
nfa_finals_buckets_NPI_WrFIFO_Data,
nfa_finals_buckets_NPI_WrFIFO_BE,
nfa_finals_buckets_NPI_WrFIFO_Push,
nfa_finals_buckets_NPI_RdFIFO_Data,
nfa_finals_buckets_NPI_RdFIFO_Pop,
nfa_finals_buckets_NPI_RdFIFO_RdWdAddr,
nfa_finals_buckets_NPI_WrFIFO_Empty,
nfa_finals_buckets_NPI_WrFIFO_AlmostFull,
nfa_finals_buckets_NPI_WrFIFO_Flush,
nfa_finals_buckets_NPI_RdFIFO_Empty,
nfa_finals_buckets_NPI_RdFIFO_Flush,
nfa_finals_buckets_NPI_RdFIFO_Latency,
nfa_finals_buckets_NPI_RdModWr,
nfa_finals_buckets_NPI_InitDone,
nfa_forward_buckets_NPI_clk,
nfa_forward_buckets_NPI_reset,
nfa_forward_buckets_NPI_Addr,
nfa_forward_buckets_NPI_AddrReq,
nfa_forward_buckets_NPI_AddrAck,
nfa_forward_buckets_NPI_RNW,
nfa_forward_buckets_NPI_Size,
nfa_forward_buckets_NPI_WrFIFO_Data,
nfa_forward_buckets_NPI_WrFIFO_BE,
nfa_forward_buckets_NPI_WrFIFO_Push,
nfa_forward_buckets_NPI_RdFIFO_Data,
nfa_forward_buckets_NPI_RdFIFO_Pop,
nfa_forward_buckets_NPI_RdFIFO_RdWdAddr,
nfa_forward_buckets_NPI_WrFIFO_Empty,
nfa_forward_buckets_NPI_WrFIFO_AlmostFull,
nfa_forward_buckets_NPI_WrFIFO_Flush,
nfa_forward_buckets_NPI_RdFIFO_Empty,
nfa_forward_buckets_NPI_RdFIFO_Flush,
nfa_forward_buckets_NPI_RdFIFO_Latency,
nfa_forward_buckets_NPI_RdModWr,
nfa_forward_buckets_NPI_InitDone,
sample_buffer_MPLB_Clk,
sample_buffer_MPLB_Rst,
sample_buffer_M_request,
sample_buffer_M_priority,
sample_buffer_M_busLock,
sample_buffer_M_RNW,
sample_buffer_M_BE,
sample_buffer_M_MSize,
sample_buffer_M_size,
sample_buffer_M_type,
sample_buffer_M_TAttribute,
sample_buffer_M_lockErr,
sample_buffer_M_abort,
sample_buffer_M_UABus,
sample_buffer_M_ABus,
sample_buffer_M_wrDBus,
sample_buffer_M_wrBurst,
sample_buffer_M_rdBurst,
sample_buffer_PLB_MAddrAck,
sample_buffer_PLB_MSSize,
sample_buffer_PLB_MRearbitrate,
sample_buffer_PLB_MTimeout,
sample_buffer_PLB_MBusy,
sample_buffer_PLB_MRdErr,
sample_buffer_PLB_MWrErr,
sample_buffer_PLB_MIRQ,
sample_buffer_PLB_MRdDBus,
sample_buffer_PLB_MRdWdAddr,
sample_buffer_PLB_MRdDAck,
sample_buffer_PLB_MRdBTerm,
sample_buffer_PLB_MWrDAck,
sample_buffer_PLB_MWrBTerm,
indices_MPLB_Clk,
indices_MPLB_Rst,
indices_M_request,
indices_M_priority,
indices_M_busLock,
indices_M_RNW,
indices_M_BE,
indices_M_MSize,
indices_M_size,
indices_M_type,
indices_M_TAttribute,
indices_M_lockErr,
indices_M_abort,
indices_M_UABus,
indices_M_ABus,
indices_M_wrDBus,
indices_M_wrBurst,
indices_M_rdBurst,
indices_PLB_MAddrAck,
indices_PLB_MSSize,
indices_PLB_MRearbitrate,
indices_PLB_MTimeout,
indices_PLB_MBusy,
indices_PLB_MRdErr,
indices_PLB_MWrErr,
indices_PLB_MIRQ,
indices_PLB_MRdDBus,
indices_PLB_MRdWdAddr,
indices_PLB_MRdDAck,
indices_PLB_MRdBTerm,
indices_PLB_MWrDAck,
indices_PLB_MWrBTerm,
splb_slv0_SPLB_Clk,
splb_slv0_SPLB_Rst,
splb_slv0_PLB_ABus,
splb_slv0_PLB_UABus,
splb_slv0_PLB_PAValid,
splb_slv0_PLB_SAValid,
splb_slv0_PLB_rdPrim,
splb_slv0_PLB_wrPrim,
splb_slv0_PLB_masterID,
splb_slv0_PLB_abort,
splb_slv0_PLB_busLock,
splb_slv0_PLB_RNW,
splb_slv0_PLB_BE,
splb_slv0_PLB_MSize,
splb_slv0_PLB_size,
splb_slv0_PLB_type,
splb_slv0_PLB_lockErr,
splb_slv0_PLB_wrDBus,
splb_slv0_PLB_wrBurst,
splb_slv0_PLB_rdBurst,
splb_slv0_PLB_wrPendReq,
splb_slv0_PLB_rdPendReq,
splb_slv0_PLB_wrPendPri,
splb_slv0_PLB_rdPendPri,
splb_slv0_PLB_reqPri,
splb_slv0_PLB_TAttribute,
splb_slv0_Sl_addrAck,
splb_slv0_Sl_SSize,
splb_slv0_Sl_wait,
splb_slv0_Sl_rearbitrate,
splb_slv0_Sl_wrDAck,
splb_slv0_Sl_wrComp,
splb_slv0_Sl_wrBTerm,
splb_slv0_Sl_rdDBus,
splb_slv0_Sl_rdWdAddr,
splb_slv0_Sl_rdDAck,
splb_slv0_Sl_rdComp,
splb_slv0_Sl_rdBTerm,
splb_slv0_Sl_MBusy,
splb_slv0_Sl_MWrErr,
splb_slv0_Sl_MRdErr,
splb_slv0_Sl_MIRQ,
aresetn,
aclk
);
parameter C_nfa_initials_buckets_MPMC_BASE_ADDRESS = 32'h00000000;
parameter C_nfa_finals_buckets_MPMC_BASE_ADDRESS = 32'h00000000;
parameter C_nfa_forward_buckets_MPMC_BASE_ADDRESS = 32'h00000000;
parameter C_sample_buffer_REMOTE_DESTINATION_ADDRESS = 32'h00000000;
parameter C_sample_buffer_AWIDTH = 32;
parameter C_sample_buffer_DWIDTH = 64;
parameter C_sample_buffer_NATIVE_DWIDTH = 64;
parameter C_indices_REMOTE_DESTINATION_ADDRESS = 32'h00000000;
parameter C_indices_AWIDTH = 32;
parameter C_indices_DWIDTH = 64;
parameter C_indices_NATIVE_DWIDTH = 64;
parameter C_SPLB_SLV0_BASEADDR = 32'h00000000;
parameter C_SPLB_SLV0_HIGHADDR = 32'h0000000F;
parameter C_SPLB_SLV0_AWIDTH = 32;
parameter C_SPLB_SLV0_DWIDTH = 32;
parameter C_SPLB_SLV0_NUM_MASTERS = 8;
parameter C_SPLB_SLV0_MID_WIDTH = 3;
parameter C_SPLB_SLV0_NATIVE_DWIDTH = 32;
parameter C_SPLB_SLV0_P2P = 0;
parameter C_SPLB_SLV0_SUPPORT_BURSTS = 0;
parameter C_SPLB_SLV0_SMALLEST_MASTER = 32;
parameter C_SPLB_SLV0_INCLUDE_DPHASE_TIMER = 0;
parameter RESET_ACTIVE_LOW = 1;
input nfa_initials_buckets_NPI_clk ;
input nfa_initials_buckets_NPI_reset ;
output [32 - 1:0] nfa_initials_buckets_NPI_Addr ;
output nfa_initials_buckets_NPI_AddrReq ;
input nfa_initials_buckets_NPI_AddrAck ;
output nfa_initials_buckets_NPI_RNW ;
output [4 - 1:0] nfa_initials_buckets_NPI_Size ;
output [64 - 1:0] nfa_initials_buckets_NPI_WrFIFO_Data ;
output [8 - 1:0] nfa_initials_buckets_NPI_WrFIFO_BE ;
output nfa_initials_buckets_NPI_WrFIFO_Push ;
input [64 - 1:0] nfa_initials_buckets_NPI_RdFIFO_Data ;
output nfa_initials_buckets_NPI_RdFIFO_Pop ;
input [4 - 1:0] nfa_initials_buckets_NPI_RdFIFO_RdWdAddr ;
input nfa_initials_buckets_NPI_WrFIFO_Empty ;
input nfa_initials_buckets_NPI_WrFIFO_AlmostFull ;
output nfa_initials_buckets_NPI_WrFIFO_Flush ;
input nfa_initials_buckets_NPI_RdFIFO_Empty ;
output nfa_initials_buckets_NPI_RdFIFO_Flush ;
input [2 - 1:0] nfa_initials_buckets_NPI_RdFIFO_Latency ;
output nfa_initials_buckets_NPI_RdModWr ;
input nfa_initials_buckets_NPI_InitDone ;
input nfa_finals_buckets_NPI_clk ;
input nfa_finals_buckets_NPI_reset ;
output [32 - 1:0] nfa_finals_buckets_NPI_Addr ;
output nfa_finals_buckets_NPI_AddrReq ;
input nfa_finals_buckets_NPI_AddrAck ;
output nfa_finals_buckets_NPI_RNW ;
output [4 - 1:0] nfa_finals_buckets_NPI_Size ;
output [64 - 1:0] nfa_finals_buckets_NPI_WrFIFO_Data ;
output [8 - 1:0] nfa_finals_buckets_NPI_WrFIFO_BE ;
output nfa_finals_buckets_NPI_WrFIFO_Push ;
input [64 - 1:0] nfa_finals_buckets_NPI_RdFIFO_Data ;
output nfa_finals_buckets_NPI_RdFIFO_Pop ;
input [4 - 1:0] nfa_finals_buckets_NPI_RdFIFO_RdWdAddr ;
input nfa_finals_buckets_NPI_WrFIFO_Empty ;
input nfa_finals_buckets_NPI_WrFIFO_AlmostFull ;
output nfa_finals_buckets_NPI_WrFIFO_Flush ;
input nfa_finals_buckets_NPI_RdFIFO_Empty ;
output nfa_finals_buckets_NPI_RdFIFO_Flush ;
input [2 - 1:0] nfa_finals_buckets_NPI_RdFIFO_Latency ;
output nfa_finals_buckets_NPI_RdModWr ;
input nfa_finals_buckets_NPI_InitDone ;
input nfa_forward_buckets_NPI_clk ;
input nfa_forward_buckets_NPI_reset ;
output [32 - 1:0] nfa_forward_buckets_NPI_Addr ;
output nfa_forward_buckets_NPI_AddrReq ;
input nfa_forward_buckets_NPI_AddrAck ;
output nfa_forward_buckets_NPI_RNW ;
output [4 - 1:0] nfa_forward_buckets_NPI_Size ;
output [64 - 1:0] nfa_forward_buckets_NPI_WrFIFO_Data ;
output [8 - 1:0] nfa_forward_buckets_NPI_WrFIFO_BE ;
output nfa_forward_buckets_NPI_WrFIFO_Push ;
input [64 - 1:0] nfa_forward_buckets_NPI_RdFIFO_Data ;
output nfa_forward_buckets_NPI_RdFIFO_Pop ;
input [4 - 1:0] nfa_forward_buckets_NPI_RdFIFO_RdWdAddr ;
input nfa_forward_buckets_NPI_WrFIFO_Empty ;
input nfa_forward_buckets_NPI_WrFIFO_AlmostFull ;
output nfa_forward_buckets_NPI_WrFIFO_Flush ;
input nfa_forward_buckets_NPI_RdFIFO_Empty ;
output nfa_forward_buckets_NPI_RdFIFO_Flush ;
input [2 - 1:0] nfa_forward_buckets_NPI_RdFIFO_Latency ;
output nfa_forward_buckets_NPI_RdModWr ;
input nfa_forward_buckets_NPI_InitDone ;
input sample_buffer_MPLB_Clk ;
input sample_buffer_MPLB_Rst ;
output sample_buffer_M_request ;
output [2 - 1:0] sample_buffer_M_priority ;
output sample_buffer_M_busLock ;
output sample_buffer_M_RNW ;
output [C_sample_buffer_DWIDTH/8 - 1:0] sample_buffer_M_BE ;
output [2 - 1:0] sample_buffer_M_MSize ;
output [4 - 1:0] sample_buffer_M_size ;
output [3 - 1:0] sample_buffer_M_type ;
output [16 - 1:0] sample_buffer_M_TAttribute ;
output sample_buffer_M_lockErr ;
output sample_buffer_M_abort ;
output [32 - 1:0] sample_buffer_M_UABus ;
output [32 - 1:0] sample_buffer_M_ABus ;
output [C_sample_buffer_DWIDTH - 1:0] sample_buffer_M_wrDBus ;
output sample_buffer_M_wrBurst ;
output sample_buffer_M_rdBurst ;
input sample_buffer_PLB_MAddrAck ;
input [2 - 1:0] sample_buffer_PLB_MSSize ;
input sample_buffer_PLB_MRearbitrate ;
input sample_buffer_PLB_MTimeout ;
input sample_buffer_PLB_MBusy ;
input sample_buffer_PLB_MRdErr ;
input sample_buffer_PLB_MWrErr ;
input sample_buffer_PLB_MIRQ ;
input [C_sample_buffer_DWIDTH - 1:0] sample_buffer_PLB_MRdDBus ;
input [4 - 1:0] sample_buffer_PLB_MRdWdAddr ;
input sample_buffer_PLB_MRdDAck ;
input sample_buffer_PLB_MRdBTerm ;
input sample_buffer_PLB_MWrDAck ;
input sample_buffer_PLB_MWrBTerm ;
input indices_MPLB_Clk ;
input indices_MPLB_Rst ;
output indices_M_request ;
output [2 - 1:0] indices_M_priority ;
output indices_M_busLock ;
output indices_M_RNW ;
output [C_indices_DWIDTH/8 - 1:0] indices_M_BE ;
output [2 - 1:0] indices_M_MSize ;
output [4 - 1:0] indices_M_size ;
output [3 - 1:0] indices_M_type ;
output [16 - 1:0] indices_M_TAttribute ;
output indices_M_lockErr ;
output indices_M_abort ;
output [32 - 1:0] indices_M_UABus ;
output [32 - 1:0] indices_M_ABus ;
output [C_indices_DWIDTH - 1:0] indices_M_wrDBus ;
output indices_M_wrBurst ;
output indices_M_rdBurst ;
input indices_PLB_MAddrAck ;
input [2 - 1:0] indices_PLB_MSSize ;
input indices_PLB_MRearbitrate ;
input indices_PLB_MTimeout ;
input indices_PLB_MBusy ;
input indices_PLB_MRdErr ;
input indices_PLB_MWrErr ;
input indices_PLB_MIRQ ;
input [C_indices_DWIDTH - 1:0] indices_PLB_MRdDBus ;
input [4 - 1:0] indices_PLB_MRdWdAddr ;
input indices_PLB_MRdDAck ;
input indices_PLB_MRdBTerm ;
input indices_PLB_MWrDAck ;
input indices_PLB_MWrBTerm ;
input splb_slv0_SPLB_Clk ;
input splb_slv0_SPLB_Rst ;
input [32 - 1:0] splb_slv0_PLB_ABus ;
input [32 - 1:0] splb_slv0_PLB_UABus ;
input splb_slv0_PLB_PAValid ;
input splb_slv0_PLB_SAValid ;
input splb_slv0_PLB_rdPrim ;
input splb_slv0_PLB_wrPrim ;
input [C_SPLB_SLV0_MID_WIDTH - 1:0] splb_slv0_PLB_masterID ;
input splb_slv0_PLB_abort ;
input splb_slv0_PLB_busLock ;
input splb_slv0_PLB_RNW ;
input [C_SPLB_SLV0_DWIDTH/8 - 1:0] splb_slv0_PLB_BE ;
input [2 - 1:0] splb_slv0_PLB_MSize ;
input [4 - 1:0] splb_slv0_PLB_size ;
input [3 - 1:0] splb_slv0_PLB_type ;
input splb_slv0_PLB_lockErr ;
input [C_SPLB_SLV0_DWIDTH - 1:0] splb_slv0_PLB_wrDBus ;
input splb_slv0_PLB_wrBurst ;
input splb_slv0_PLB_rdBurst ;
input splb_slv0_PLB_wrPendReq ;
input splb_slv0_PLB_rdPendReq ;
input [2 - 1:0] splb_slv0_PLB_wrPendPri ;
input [2 - 1:0] splb_slv0_PLB_rdPendPri ;
input [2 - 1:0] splb_slv0_PLB_reqPri ;
input [16 - 1:0] splb_slv0_PLB_TAttribute ;
output splb_slv0_Sl_addrAck ;
output [2 - 1:0] splb_slv0_Sl_SSize ;
output splb_slv0_Sl_wait ;
output splb_slv0_Sl_rearbitrate ;
output splb_slv0_Sl_wrDAck ;
output splb_slv0_Sl_wrComp ;
output splb_slv0_Sl_wrBTerm ;
output [C_SPLB_SLV0_DWIDTH - 1:0] splb_slv0_Sl_rdDBus ;
output [4 - 1:0] splb_slv0_Sl_rdWdAddr ;
output splb_slv0_Sl_rdDAck ;
output splb_slv0_Sl_rdComp ;
output splb_slv0_Sl_rdBTerm ;
output [C_SPLB_SLV0_NUM_MASTERS - 1:0] splb_slv0_Sl_MBusy ;
output [C_SPLB_SLV0_NUM_MASTERS - 1:0] splb_slv0_Sl_MWrErr ;
output [C_SPLB_SLV0_NUM_MASTERS - 1:0] splb_slv0_Sl_MRdErr ;
output [C_SPLB_SLV0_NUM_MASTERS - 1:0] splb_slv0_Sl_MIRQ ;
input aresetn ;
input aclk ;
wire nfa_initials_buckets_NPI_clk;
wire nfa_initials_buckets_NPI_reset;
wire [32 - 1:0] nfa_initials_buckets_NPI_Addr;
wire nfa_initials_buckets_NPI_AddrReq;
wire nfa_initials_buckets_NPI_AddrAck;
wire nfa_initials_buckets_NPI_RNW;
wire [4 - 1:0] nfa_initials_buckets_NPI_Size;
wire [64 - 1:0] nfa_initials_buckets_NPI_WrFIFO_Data;
wire [8 - 1:0] nfa_initials_buckets_NPI_WrFIFO_BE;
wire nfa_initials_buckets_NPI_WrFIFO_Push;
wire [64 - 1:0] nfa_initials_buckets_NPI_RdFIFO_Data;
wire nfa_initials_buckets_NPI_RdFIFO_Pop;
wire [4 - 1:0] nfa_initials_buckets_NPI_RdFIFO_RdWdAddr;
wire nfa_initials_buckets_NPI_WrFIFO_Empty;
wire nfa_initials_buckets_NPI_WrFIFO_AlmostFull;
wire nfa_initials_buckets_NPI_WrFIFO_Flush;
wire nfa_initials_buckets_NPI_RdFIFO_Empty;
wire nfa_initials_buckets_NPI_RdFIFO_Flush;
wire [2 - 1:0] nfa_initials_buckets_NPI_RdFIFO_Latency;
wire nfa_initials_buckets_NPI_RdModWr;
wire nfa_initials_buckets_NPI_InitDone;
wire nfa_finals_buckets_NPI_clk;
wire nfa_finals_buckets_NPI_reset;
wire [32 - 1:0] nfa_finals_buckets_NPI_Addr;
wire nfa_finals_buckets_NPI_AddrReq;
wire nfa_finals_buckets_NPI_AddrAck;
wire nfa_finals_buckets_NPI_RNW;
wire [4 - 1:0] nfa_finals_buckets_NPI_Size;
wire [64 - 1:0] nfa_finals_buckets_NPI_WrFIFO_Data;
wire [8 - 1:0] nfa_finals_buckets_NPI_WrFIFO_BE;
wire nfa_finals_buckets_NPI_WrFIFO_Push;
wire [64 - 1:0] nfa_finals_buckets_NPI_RdFIFO_Data;
wire nfa_finals_buckets_NPI_RdFIFO_Pop;
wire [4 - 1:0] nfa_finals_buckets_NPI_RdFIFO_RdWdAddr;
wire nfa_finals_buckets_NPI_WrFIFO_Empty;
wire nfa_finals_buckets_NPI_WrFIFO_AlmostFull;
wire nfa_finals_buckets_NPI_WrFIFO_Flush;
wire nfa_finals_buckets_NPI_RdFIFO_Empty;
wire nfa_finals_buckets_NPI_RdFIFO_Flush;
wire [2 - 1:0] nfa_finals_buckets_NPI_RdFIFO_Latency;
wire nfa_finals_buckets_NPI_RdModWr;
wire nfa_finals_buckets_NPI_InitDone;
wire nfa_forward_buckets_NPI_clk;
wire nfa_forward_buckets_NPI_reset;
wire [32 - 1:0] nfa_forward_buckets_NPI_Addr;
wire nfa_forward_buckets_NPI_AddrReq;
wire nfa_forward_buckets_NPI_AddrAck;
wire nfa_forward_buckets_NPI_RNW;
wire [4 - 1:0] nfa_forward_buckets_NPI_Size;
wire [64 - 1:0] nfa_forward_buckets_NPI_WrFIFO_Data;
wire [8 - 1:0] nfa_forward_buckets_NPI_WrFIFO_BE;
wire nfa_forward_buckets_NPI_WrFIFO_Push;
wire [64 - 1:0] nfa_forward_buckets_NPI_RdFIFO_Data;
wire nfa_forward_buckets_NPI_RdFIFO_Pop;
wire [4 - 1:0] nfa_forward_buckets_NPI_RdFIFO_RdWdAddr;
wire nfa_forward_buckets_NPI_WrFIFO_Empty;
wire nfa_forward_buckets_NPI_WrFIFO_AlmostFull;
wire nfa_forward_buckets_NPI_WrFIFO_Flush;
wire nfa_forward_buckets_NPI_RdFIFO_Empty;
wire nfa_forward_buckets_NPI_RdFIFO_Flush;
wire [2 - 1:0] nfa_forward_buckets_NPI_RdFIFO_Latency;
wire nfa_forward_buckets_NPI_RdModWr;
wire nfa_forward_buckets_NPI_InitDone;
wire sample_buffer_MPLB_Clk;
wire sample_buffer_MPLB_Rst;
wire sample_buffer_M_request;
wire [2 - 1:0] sample_buffer_M_priority;
wire sample_buffer_M_busLock;
wire sample_buffer_M_RNW;
wire [C_sample_buffer_DWIDTH/8 - 1:0] sample_buffer_M_BE;
wire [2 - 1:0] sample_buffer_M_MSize;
wire [4 - 1:0] sample_buffer_M_size;
wire [3 - 1:0] sample_buffer_M_type;
wire [16 - 1:0] sample_buffer_M_TAttribute;
wire sample_buffer_M_lockErr;
wire sample_buffer_M_abort;
wire [32 - 1:0] sample_buffer_M_UABus;
wire [32 - 1:0] sample_buffer_M_ABus;
wire [C_sample_buffer_DWIDTH - 1:0] sample_buffer_M_wrDBus;
wire sample_buffer_M_wrBurst;
wire sample_buffer_M_rdBurst;
wire sample_buffer_PLB_MAddrAck;
wire [2 - 1:0] sample_buffer_PLB_MSSize;
wire sample_buffer_PLB_MRearbitrate;
wire sample_buffer_PLB_MTimeout;
wire sample_buffer_PLB_MBusy;
wire sample_buffer_PLB_MRdErr;
wire sample_buffer_PLB_MWrErr;
wire sample_buffer_PLB_MIRQ;
wire [C_sample_buffer_DWIDTH - 1:0] sample_buffer_PLB_MRdDBus;
wire [4 - 1:0] sample_buffer_PLB_MRdWdAddr;
wire sample_buffer_PLB_MRdDAck;
wire sample_buffer_PLB_MRdBTerm;
wire sample_buffer_PLB_MWrDAck;
wire sample_buffer_PLB_MWrBTerm;
wire indices_MPLB_Clk;
wire indices_MPLB_Rst;
wire indices_M_request;
wire [2 - 1:0] indices_M_priority;
wire indices_M_busLock;
wire indices_M_RNW;
wire [C_indices_DWIDTH/8 - 1:0] indices_M_BE;
wire [2 - 1:0] indices_M_MSize;
wire [4 - 1:0] indices_M_size;
wire [3 - 1:0] indices_M_type;
wire [16 - 1:0] indices_M_TAttribute;
wire indices_M_lockErr;
wire indices_M_abort;
wire [32 - 1:0] indices_M_UABus;
wire [32 - 1:0] indices_M_ABus;
wire [C_indices_DWIDTH - 1:0] indices_M_wrDBus;
wire indices_M_wrBurst;
wire indices_M_rdBurst;
wire indices_PLB_MAddrAck;
wire [2 - 1:0] indices_PLB_MSSize;
wire indices_PLB_MRearbitrate;
wire indices_PLB_MTimeout;
wire indices_PLB_MBusy;
wire indices_PLB_MRdErr;
wire indices_PLB_MWrErr;
wire indices_PLB_MIRQ;
wire [C_indices_DWIDTH - 1:0] indices_PLB_MRdDBus;
wire [4 - 1:0] indices_PLB_MRdWdAddr;
wire indices_PLB_MRdDAck;
wire indices_PLB_MRdBTerm;
wire indices_PLB_MWrDAck;
wire indices_PLB_MWrBTerm;
wire splb_slv0_SPLB_Clk;
wire splb_slv0_SPLB_Rst;
wire [32 - 1:0] splb_slv0_PLB_ABus;
wire [32 - 1:0] splb_slv0_PLB_UABus;
wire splb_slv0_PLB_PAValid;
wire splb_slv0_PLB_SAValid;
wire splb_slv0_PLB_rdPrim;
wire splb_slv0_PLB_wrPrim;
wire [C_SPLB_SLV0_MID_WIDTH - 1:0] splb_slv0_PLB_masterID;
wire splb_slv0_PLB_abort;
wire splb_slv0_PLB_busLock;
wire splb_slv0_PLB_RNW;
wire [C_SPLB_SLV0_DWIDTH/8 - 1:0] splb_slv0_PLB_BE;
wire [2 - 1:0] splb_slv0_PLB_MSize;
wire [4 - 1:0] splb_slv0_PLB_size;
wire [3 - 1:0] splb_slv0_PLB_type;
wire splb_slv0_PLB_lockErr;
wire [C_SPLB_SLV0_DWIDTH - 1:0] splb_slv0_PLB_wrDBus;
wire splb_slv0_PLB_wrBurst;
wire splb_slv0_PLB_rdBurst;
wire splb_slv0_PLB_wrPendReq;
wire splb_slv0_PLB_rdPendReq;
wire [2 - 1:0] splb_slv0_PLB_wrPendPri;
wire [2 - 1:0] splb_slv0_PLB_rdPendPri;
wire [2 - 1:0] splb_slv0_PLB_reqPri;
wire [16 - 1:0] splb_slv0_PLB_TAttribute;
wire splb_slv0_Sl_addrAck;
wire [2 - 1:0] splb_slv0_Sl_SSize;
wire splb_slv0_Sl_wait;
wire splb_slv0_Sl_rearbitrate;
wire splb_slv0_Sl_wrDAck;
wire splb_slv0_Sl_wrComp;
wire splb_slv0_Sl_wrBTerm;
wire [C_SPLB_SLV0_DWIDTH - 1:0] splb_slv0_Sl_rdDBus;
wire [4 - 1:0] splb_slv0_Sl_rdWdAddr;
wire splb_slv0_Sl_rdDAck;
wire splb_slv0_Sl_rdComp;
wire splb_slv0_Sl_rdBTerm;
wire [C_SPLB_SLV0_NUM_MASTERS - 1:0] splb_slv0_Sl_MBusy;
wire [C_SPLB_SLV0_NUM_MASTERS - 1:0] splb_slv0_Sl_MWrErr;
wire [C_SPLB_SLV0_NUM_MASTERS - 1:0] splb_slv0_Sl_MRdErr;
wire [C_SPLB_SLV0_NUM_MASTERS - 1:0] splb_slv0_Sl_MIRQ;
wire aresetn;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_datain;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_dataout;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_address;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_size;
wire sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_din;
wire sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_full_n;
wire sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_write;
wire sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_rsp_empty_n;
wire sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_rsp_read;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_datain;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_dataout;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_address;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_size;
wire sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_din;
wire sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_full_n;
wire sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_write;
wire sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_rsp_empty_n;
wire sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_rsp_read;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_datain;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_dataout;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_address;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_size;
wire sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_din;
wire sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_full_n;
wire sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_write;
wire sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_rsp_empty_n;
wire sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_rsp_read;
wire [8 - 1:0] sig_nfa_accept_samples_generic_hw_sample_buffer_datain;
wire [8 - 1:0] sig_nfa_accept_samples_generic_hw_sample_buffer_dataout;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_sample_buffer_address;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_sample_buffer_size;
wire sig_nfa_accept_samples_generic_hw_sample_buffer_req_din;
wire sig_nfa_accept_samples_generic_hw_sample_buffer_req_full_n;
wire sig_nfa_accept_samples_generic_hw_sample_buffer_req_write;
wire sig_nfa_accept_samples_generic_hw_sample_buffer_rsp_empty_n;
wire sig_nfa_accept_samples_generic_hw_sample_buffer_rsp_read;
wire [56 - 1:0] sig_nfa_accept_samples_generic_hw_indices_datain;
wire [56 - 1:0] sig_nfa_accept_samples_generic_hw_indices_dataout;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_indices_address;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_indices_size;
wire sig_nfa_accept_samples_generic_hw_indices_req_din;
wire sig_nfa_accept_samples_generic_hw_indices_req_full_n;
wire sig_nfa_accept_samples_generic_hw_indices_req_write;
wire sig_nfa_accept_samples_generic_hw_indices_rsp_empty_n;
wire sig_nfa_accept_samples_generic_hw_indices_rsp_read;
wire [8 - 1:0] sig_nfa_accept_samples_generic_hw_nfa_symbols;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_sample_buffer_length;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_sample_length;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_i_size;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_begin_index;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_begin_sample;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_end_index;
wire [16 - 1:0] sig_nfa_accept_samples_generic_hw_end_sample;
wire [1 - 1:0] sig_nfa_accept_samples_generic_hw_stop_on_first;
wire [1 - 1:0] sig_nfa_accept_samples_generic_hw_accept;
wire sig_nfa_accept_samples_generic_hw_ap_start;
wire sig_nfa_accept_samples_generic_hw_ap_ready;
wire sig_nfa_accept_samples_generic_hw_ap_done;
wire sig_nfa_accept_samples_generic_hw_ap_idle;
wire [32 - 1:0] sig_nfa_accept_samples_generic_hw_ap_return;
wire sig_nfa_accept_samples_generic_hw_ap_rst;
nfa_accept_samples_generic_hw nfa_accept_samples_generic_hw_U(
.nfa_initials_buckets_datain(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_datain),
.nfa_initials_buckets_dataout(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_dataout),
.nfa_initials_buckets_address(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_address),
.nfa_initials_buckets_size(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_size),
.nfa_initials_buckets_req_din(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_din),
.nfa_initials_buckets_req_full_n(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_full_n),
.nfa_initials_buckets_req_write(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_write),
.nfa_initials_buckets_rsp_empty_n(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_rsp_empty_n),
.nfa_initials_buckets_rsp_read(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_rsp_read),
.nfa_finals_buckets_datain(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_datain),
.nfa_finals_buckets_dataout(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_dataout),
.nfa_finals_buckets_address(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_address),
.nfa_finals_buckets_size(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_size),
.nfa_finals_buckets_req_din(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_din),
.nfa_finals_buckets_req_full_n(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_full_n),
.nfa_finals_buckets_req_write(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_write),
.nfa_finals_buckets_rsp_empty_n(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_rsp_empty_n),
.nfa_finals_buckets_rsp_read(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_rsp_read),
.nfa_forward_buckets_datain(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_datain),
.nfa_forward_buckets_dataout(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_dataout),
.nfa_forward_buckets_address(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_address),
.nfa_forward_buckets_size(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_size),
.nfa_forward_buckets_req_din(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_din),
.nfa_forward_buckets_req_full_n(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_full_n),
.nfa_forward_buckets_req_write(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_write),
.nfa_forward_buckets_rsp_empty_n(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_rsp_empty_n),
.nfa_forward_buckets_rsp_read(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_rsp_read),
.sample_buffer_datain(sig_nfa_accept_samples_generic_hw_sample_buffer_datain),
.sample_buffer_dataout(sig_nfa_accept_samples_generic_hw_sample_buffer_dataout),
.sample_buffer_address(sig_nfa_accept_samples_generic_hw_sample_buffer_address),
.sample_buffer_size(sig_nfa_accept_samples_generic_hw_sample_buffer_size),
.sample_buffer_req_din(sig_nfa_accept_samples_generic_hw_sample_buffer_req_din),
.sample_buffer_req_full_n(sig_nfa_accept_samples_generic_hw_sample_buffer_req_full_n),
.sample_buffer_req_write(sig_nfa_accept_samples_generic_hw_sample_buffer_req_write),
.sample_buffer_rsp_empty_n(sig_nfa_accept_samples_generic_hw_sample_buffer_rsp_empty_n),
.sample_buffer_rsp_read(sig_nfa_accept_samples_generic_hw_sample_buffer_rsp_read),
.indices_datain(sig_nfa_accept_samples_generic_hw_indices_datain),
.indices_dataout(sig_nfa_accept_samples_generic_hw_indices_dataout),
.indices_address(sig_nfa_accept_samples_generic_hw_indices_address),
.indices_size(sig_nfa_accept_samples_generic_hw_indices_size),
.indices_req_din(sig_nfa_accept_samples_generic_hw_indices_req_din),
.indices_req_full_n(sig_nfa_accept_samples_generic_hw_indices_req_full_n),
.indices_req_write(sig_nfa_accept_samples_generic_hw_indices_req_write),
.indices_rsp_empty_n(sig_nfa_accept_samples_generic_hw_indices_rsp_empty_n),
.indices_rsp_read(sig_nfa_accept_samples_generic_hw_indices_rsp_read),
.nfa_symbols(sig_nfa_accept_samples_generic_hw_nfa_symbols),
.sample_buffer_length(sig_nfa_accept_samples_generic_hw_sample_buffer_length),
.sample_length(sig_nfa_accept_samples_generic_hw_sample_length),
.i_size(sig_nfa_accept_samples_generic_hw_i_size),
.begin_index(sig_nfa_accept_samples_generic_hw_begin_index),
.begin_sample(sig_nfa_accept_samples_generic_hw_begin_sample),
.end_index(sig_nfa_accept_samples_generic_hw_end_index),
.end_sample(sig_nfa_accept_samples_generic_hw_end_sample),
.stop_on_first(sig_nfa_accept_samples_generic_hw_stop_on_first),
.accept(sig_nfa_accept_samples_generic_hw_accept),
.ap_start(sig_nfa_accept_samples_generic_hw_ap_start),
.ap_ready(sig_nfa_accept_samples_generic_hw_ap_ready),
.ap_done(sig_nfa_accept_samples_generic_hw_ap_done),
.ap_idle(sig_nfa_accept_samples_generic_hw_ap_idle),
.ap_return(sig_nfa_accept_samples_generic_hw_ap_return),
.ap_rst(sig_nfa_accept_samples_generic_hw_ap_rst),
.ap_clk(aclk)
);
nfa_initials_buckets_if #(
.MPMC_BASE_ADDRESS(C_nfa_initials_buckets_MPMC_BASE_ADDRESS))
nfa_initials_buckets_if_U(
.USER_RdData(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_datain),
.USER_WrData(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_dataout),
.USER_address(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_address),
.USER_size(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_size),
.USER_req_nRW(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_din),
.USER_req_full_n(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_full_n),
.USER_req_push(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_req_write),
.USER_rsp_empty_n(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_rsp_empty_n),
.USER_rsp_pop(sig_nfa_accept_samples_generic_hw_nfa_initials_buckets_rsp_read),
.ap_clk(aclk),
.ap_reset(aresetn),
.NPI_clk(nfa_initials_buckets_NPI_clk),
.NPI_reset(nfa_initials_buckets_NPI_reset),
.NPI_Addr(nfa_initials_buckets_NPI_Addr),
.NPI_AddrReq(nfa_initials_buckets_NPI_AddrReq),
.NPI_AddrAck(nfa_initials_buckets_NPI_AddrAck),
.NPI_RNW(nfa_initials_buckets_NPI_RNW),
.NPI_Size(nfa_initials_buckets_NPI_Size),
.NPI_WrFIFO_Data(nfa_initials_buckets_NPI_WrFIFO_Data),
.NPI_WrFIFO_BE(nfa_initials_buckets_NPI_WrFIFO_BE),
.NPI_WrFIFO_Push(nfa_initials_buckets_NPI_WrFIFO_Push),
.NPI_RdFIFO_Data(nfa_initials_buckets_NPI_RdFIFO_Data),
.NPI_RdFIFO_Pop(nfa_initials_buckets_NPI_RdFIFO_Pop),
.NPI_RdFIFO_RdWdAddr(nfa_initials_buckets_NPI_RdFIFO_RdWdAddr),
.NPI_WrFIFO_Empty(nfa_initials_buckets_NPI_WrFIFO_Empty),
.NPI_WrFIFO_AlmostFull(nfa_initials_buckets_NPI_WrFIFO_AlmostFull),
.NPI_WrFIFO_Flush(nfa_initials_buckets_NPI_WrFIFO_Flush),
.NPI_RdFIFO_Empty(nfa_initials_buckets_NPI_RdFIFO_Empty),
.NPI_RdFIFO_Flush(nfa_initials_buckets_NPI_RdFIFO_Flush),
.NPI_RdFIFO_Latency(nfa_initials_buckets_NPI_RdFIFO_Latency),
.NPI_RdModWr(nfa_initials_buckets_NPI_RdModWr),
.NPI_InitDone(nfa_initials_buckets_NPI_InitDone));
nfa_finals_buckets_if #(
.MPMC_BASE_ADDRESS(C_nfa_finals_buckets_MPMC_BASE_ADDRESS))
nfa_finals_buckets_if_U(
.USER_RdData(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_datain),
.USER_WrData(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_dataout),
.USER_address(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_address),
.USER_size(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_size),
.USER_req_nRW(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_din),
.USER_req_full_n(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_full_n),
.USER_req_push(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_req_write),
.USER_rsp_empty_n(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_rsp_empty_n),
.USER_rsp_pop(sig_nfa_accept_samples_generic_hw_nfa_finals_buckets_rsp_read),
.ap_clk(aclk),
.ap_reset(aresetn),
.NPI_clk(nfa_finals_buckets_NPI_clk),
.NPI_reset(nfa_finals_buckets_NPI_reset),
.NPI_Addr(nfa_finals_buckets_NPI_Addr),
.NPI_AddrReq(nfa_finals_buckets_NPI_AddrReq),
.NPI_AddrAck(nfa_finals_buckets_NPI_AddrAck),
.NPI_RNW(nfa_finals_buckets_NPI_RNW),
.NPI_Size(nfa_finals_buckets_NPI_Size),
.NPI_WrFIFO_Data(nfa_finals_buckets_NPI_WrFIFO_Data),
.NPI_WrFIFO_BE(nfa_finals_buckets_NPI_WrFIFO_BE),
.NPI_WrFIFO_Push(nfa_finals_buckets_NPI_WrFIFO_Push),
.NPI_RdFIFO_Data(nfa_finals_buckets_NPI_RdFIFO_Data),
.NPI_RdFIFO_Pop(nfa_finals_buckets_NPI_RdFIFO_Pop),
.NPI_RdFIFO_RdWdAddr(nfa_finals_buckets_NPI_RdFIFO_RdWdAddr),
.NPI_WrFIFO_Empty(nfa_finals_buckets_NPI_WrFIFO_Empty),
.NPI_WrFIFO_AlmostFull(nfa_finals_buckets_NPI_WrFIFO_AlmostFull),
.NPI_WrFIFO_Flush(nfa_finals_buckets_NPI_WrFIFO_Flush),
.NPI_RdFIFO_Empty(nfa_finals_buckets_NPI_RdFIFO_Empty),
.NPI_RdFIFO_Flush(nfa_finals_buckets_NPI_RdFIFO_Flush),
.NPI_RdFIFO_Latency(nfa_finals_buckets_NPI_RdFIFO_Latency),
.NPI_RdModWr(nfa_finals_buckets_NPI_RdModWr),
.NPI_InitDone(nfa_finals_buckets_NPI_InitDone));
nfa_forward_buckets_if #(
.MPMC_BASE_ADDRESS(C_nfa_forward_buckets_MPMC_BASE_ADDRESS))
nfa_forward_buckets_if_U(
.USER_RdData(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_datain),
.USER_WrData(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_dataout),
.USER_address(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_address),
.USER_size(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_size),
.USER_req_nRW(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_din),
.USER_req_full_n(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_full_n),
.USER_req_push(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_req_write),
.USER_rsp_empty_n(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_rsp_empty_n),
.USER_rsp_pop(sig_nfa_accept_samples_generic_hw_nfa_forward_buckets_rsp_read),
.ap_clk(aclk),
.ap_reset(aresetn),
.NPI_clk(nfa_forward_buckets_NPI_clk),
.NPI_reset(nfa_forward_buckets_NPI_reset),
.NPI_Addr(nfa_forward_buckets_NPI_Addr),
.NPI_AddrReq(nfa_forward_buckets_NPI_AddrReq),
.NPI_AddrAck(nfa_forward_buckets_NPI_AddrAck),
.NPI_RNW(nfa_forward_buckets_NPI_RNW),
.NPI_Size(nfa_forward_buckets_NPI_Size),
.NPI_WrFIFO_Data(nfa_forward_buckets_NPI_WrFIFO_Data),
.NPI_WrFIFO_BE(nfa_forward_buckets_NPI_WrFIFO_BE),
.NPI_WrFIFO_Push(nfa_forward_buckets_NPI_WrFIFO_Push),
.NPI_RdFIFO_Data(nfa_forward_buckets_NPI_RdFIFO_Data),
.NPI_RdFIFO_Pop(nfa_forward_buckets_NPI_RdFIFO_Pop),
.NPI_RdFIFO_RdWdAddr(nfa_forward_buckets_NPI_RdFIFO_RdWdAddr),
.NPI_WrFIFO_Empty(nfa_forward_buckets_NPI_WrFIFO_Empty),
.NPI_WrFIFO_AlmostFull(nfa_forward_buckets_NPI_WrFIFO_AlmostFull),
.NPI_WrFIFO_Flush(nfa_forward_buckets_NPI_WrFIFO_Flush),
.NPI_RdFIFO_Empty(nfa_forward_buckets_NPI_RdFIFO_Empty),
.NPI_RdFIFO_Flush(nfa_forward_buckets_NPI_RdFIFO_Flush),
.NPI_RdFIFO_Latency(nfa_forward_buckets_NPI_RdFIFO_Latency),
.NPI_RdModWr(nfa_forward_buckets_NPI_RdModWr),
.NPI_InitDone(nfa_forward_buckets_NPI_InitDone));
sample_buffer_if #(
.REMOTE_DESTINATION_ADDRESS(C_sample_buffer_REMOTE_DESTINATION_ADDRESS),
.C_PLB_AWIDTH(C_sample_buffer_AWIDTH),
.C_PLB_DWIDTH(C_sample_buffer_DWIDTH))
sample_buffer_if_U(
.USER_RdData(sig_nfa_accept_samples_generic_hw_sample_buffer_datain),
.USER_WrData(sig_nfa_accept_samples_generic_hw_sample_buffer_dataout),
.USER_address(sig_nfa_accept_samples_generic_hw_sample_buffer_address),
.USER_size(sig_nfa_accept_samples_generic_hw_sample_buffer_size),
.USER_req_nRW(sig_nfa_accept_samples_generic_hw_sample_buffer_req_din),
.USER_req_full_n(sig_nfa_accept_samples_generic_hw_sample_buffer_req_full_n),
.USER_req_push(sig_nfa_accept_samples_generic_hw_sample_buffer_req_write),
.USER_rsp_empty_n(sig_nfa_accept_samples_generic_hw_sample_buffer_rsp_empty_n),
.USER_rsp_pop(sig_nfa_accept_samples_generic_hw_sample_buffer_rsp_read),
.MPLB_Clk(sample_buffer_MPLB_Clk),
.MPLB_Rst(sample_buffer_MPLB_Rst),
.M_request(sample_buffer_M_request),
.M_priority(sample_buffer_M_priority),
.M_busLock(sample_buffer_M_busLock),
.M_RNW(sample_buffer_M_RNW),
.M_BE(sample_buffer_M_BE),
.M_MSize(sample_buffer_M_MSize),
.M_size(sample_buffer_M_size),
.M_type(sample_buffer_M_type),
.M_TAttribute(sample_buffer_M_TAttribute),
.M_lockErr(sample_buffer_M_lockErr),
.M_abort(sample_buffer_M_abort),
.M_UABus(sample_buffer_M_UABus),
.M_ABus(sample_buffer_M_ABus),
.M_wrDBus(sample_buffer_M_wrDBus),
.M_wrBurst(sample_buffer_M_wrBurst),
.M_rdBurst(sample_buffer_M_rdBurst),
.PLB_MAddrAck(sample_buffer_PLB_MAddrAck),
.PLB_MSSize(sample_buffer_PLB_MSSize),
.PLB_MRearbitrate(sample_buffer_PLB_MRearbitrate),
.PLB_MTimeout(sample_buffer_PLB_MTimeout),
.PLB_MBusy(sample_buffer_PLB_MBusy),
.PLB_MRdErr(sample_buffer_PLB_MRdErr),
.PLB_MWrErr(sample_buffer_PLB_MWrErr),
.PLB_MIRQ(sample_buffer_PLB_MIRQ),
.PLB_MRdDBus(sample_buffer_PLB_MRdDBus),
.PLB_MRdWdAddr(sample_buffer_PLB_MRdWdAddr),
.PLB_MRdDAck(sample_buffer_PLB_MRdDAck),
.PLB_MRdBTerm(sample_buffer_PLB_MRdBTerm),
.PLB_MWrDAck(sample_buffer_PLB_MWrDAck),
.PLB_MWrBTerm(sample_buffer_PLB_MWrBTerm));
indices_if #(
.REMOTE_DESTINATION_ADDRESS(C_indices_REMOTE_DESTINATION_ADDRESS),
.C_PLB_AWIDTH(C_indices_AWIDTH),
.C_PLB_DWIDTH(C_indices_DWIDTH))
indices_if_U(
.USER_RdData(sig_nfa_accept_samples_generic_hw_indices_datain),
.USER_WrData(sig_nfa_accept_samples_generic_hw_indices_dataout),
.USER_address(sig_nfa_accept_samples_generic_hw_indices_address),
.USER_size(sig_nfa_accept_samples_generic_hw_indices_size),
.USER_req_nRW(sig_nfa_accept_samples_generic_hw_indices_req_din),
.USER_req_full_n(sig_nfa_accept_samples_generic_hw_indices_req_full_n),
.USER_req_push(sig_nfa_accept_samples_generic_hw_indices_req_write),
.USER_rsp_empty_n(sig_nfa_accept_samples_generic_hw_indices_rsp_empty_n),
.USER_rsp_pop(sig_nfa_accept_samples_generic_hw_indices_rsp_read),
.MPLB_Clk(indices_MPLB_Clk),
.MPLB_Rst(indices_MPLB_Rst),
.M_request(indices_M_request),
.M_priority(indices_M_priority),
.M_busLock(indices_M_busLock),
.M_RNW(indices_M_RNW),
.M_BE(indices_M_BE),
.M_MSize(indices_M_MSize),
.M_size(indices_M_size),
.M_type(indices_M_type),
.M_TAttribute(indices_M_TAttribute),
.M_lockErr(indices_M_lockErr),
.M_abort(indices_M_abort),
.M_UABus(indices_M_UABus),
.M_ABus(indices_M_ABus),
.M_wrDBus(indices_M_wrDBus),
.M_wrBurst(indices_M_wrBurst),
.M_rdBurst(indices_M_rdBurst),
.PLB_MAddrAck(indices_PLB_MAddrAck),
.PLB_MSSize(indices_PLB_MSSize),
.PLB_MRearbitrate(indices_PLB_MRearbitrate),
.PLB_MTimeout(indices_PLB_MTimeout),
.PLB_MBusy(indices_PLB_MBusy),
.PLB_MRdErr(indices_PLB_MRdErr),
.PLB_MWrErr(indices_PLB_MWrErr),
.PLB_MIRQ(indices_PLB_MIRQ),
.PLB_MRdDBus(indices_PLB_MRdDBus),
.PLB_MRdWdAddr(indices_PLB_MRdWdAddr),
.PLB_MRdDAck(indices_PLB_MRdDAck),
.PLB_MRdBTerm(indices_PLB_MRdBTerm),
.PLB_MWrDAck(indices_PLB_MWrDAck),
.PLB_MWrBTerm(indices_PLB_MWrBTerm));
slv0_if #(
.C_BASEADDR(C_SPLB_SLV0_BASEADDR),
.C_HIGHADDR(C_SPLB_SLV0_HIGHADDR),
.C_SPLB_AWIDTH(C_SPLB_SLV0_AWIDTH),
.C_SPLB_DWIDTH(C_SPLB_SLV0_DWIDTH),
.C_SPLB_NUM_MASTERS(C_SPLB_SLV0_NUM_MASTERS),
.C_SPLB_MID_WIDTH(C_SPLB_SLV0_MID_WIDTH),
.C_SPLB_NATIVE_DWIDTH(C_SPLB_SLV0_NATIVE_DWIDTH),
.C_SPLB_P2P(C_SPLB_SLV0_P2P),
.C_SPLB_SUPPORT_BURSTS(C_SPLB_SLV0_SUPPORT_BURSTS),
.C_SPLB_SMALLEST_MASTER(C_SPLB_SLV0_SMALLEST_MASTER),
.C_INCLUDE_DPHASE_TIMER(C_SPLB_SLV0_INCLUDE_DPHASE_TIMER))
slv0_if_U(
.DOUT_nfa_symbols(sig_nfa_accept_samples_generic_hw_nfa_symbols),
.DOUT_sample_buffer_length(sig_nfa_accept_samples_generic_hw_sample_buffer_length),
.DOUT_sample_length(sig_nfa_accept_samples_generic_hw_sample_length),
.DOUT_i_size(sig_nfa_accept_samples_generic_hw_i_size),
.DOUT_begin_index(sig_nfa_accept_samples_generic_hw_begin_index),
.DOUT_begin_sample(sig_nfa_accept_samples_generic_hw_begin_sample),
.DOUT_end_index(sig_nfa_accept_samples_generic_hw_end_index),
.DOUT_end_sample(sig_nfa_accept_samples_generic_hw_end_sample),
.DOUT_stop_on_first(sig_nfa_accept_samples_generic_hw_stop_on_first),
.DOUT_accept(sig_nfa_accept_samples_generic_hw_accept),
.DOUT_ap_start(sig_nfa_accept_samples_generic_hw_ap_start),
.DIN_ap_ready(sig_nfa_accept_samples_generic_hw_ap_ready),
.DIN_ap_done(sig_nfa_accept_samples_generic_hw_ap_done),
.DIN_ap_idle(sig_nfa_accept_samples_generic_hw_ap_idle),
.DIN_ap_return(sig_nfa_accept_samples_generic_hw_ap_return),
.SPLB_Clk(splb_slv0_SPLB_Clk),
.SPLB_Rst(splb_slv0_SPLB_Rst),
.PLB_ABus(splb_slv0_PLB_ABus),
.PLB_UABus(splb_slv0_PLB_UABus),
.PLB_PAValid(splb_slv0_PLB_PAValid),
.PLB_SAValid(splb_slv0_PLB_SAValid),
.PLB_rdPrim(splb_slv0_PLB_rdPrim),
.PLB_wrPrim(splb_slv0_PLB_wrPrim),
.PLB_masterID(splb_slv0_PLB_masterID),
.PLB_abort(splb_slv0_PLB_abort),
.PLB_busLock(splb_slv0_PLB_busLock),
.PLB_RNW(splb_slv0_PLB_RNW),
.PLB_BE(splb_slv0_PLB_BE),
.PLB_MSize(splb_slv0_PLB_MSize),
.PLB_size(splb_slv0_PLB_size),
.PLB_type(splb_slv0_PLB_type),
.PLB_lockErr(splb_slv0_PLB_lockErr),
.PLB_wrDBus(splb_slv0_PLB_wrDBus),
.PLB_wrBurst(splb_slv0_PLB_wrBurst),
.PLB_rdBurst(splb_slv0_PLB_rdBurst),
.PLB_wrPendReq(splb_slv0_PLB_wrPendReq),
.PLB_rdPendReq(splb_slv0_PLB_rdPendReq),
.PLB_wrPendPri(splb_slv0_PLB_wrPendPri),
.PLB_rdPendPri(splb_slv0_PLB_rdPendPri),
.PLB_reqPri(splb_slv0_PLB_reqPri),
.PLB_TAttribute(splb_slv0_PLB_TAttribute),
.Sl_addrAck(splb_slv0_Sl_addrAck),
.Sl_SSize(splb_slv0_Sl_SSize),
.Sl_wait(splb_slv0_Sl_wait),
.Sl_rearbitrate(splb_slv0_Sl_rearbitrate),
.Sl_wrDAck(splb_slv0_Sl_wrDAck),
.Sl_wrComp(splb_slv0_Sl_wrComp),
.Sl_wrBTerm(splb_slv0_Sl_wrBTerm),
.Sl_rdDBus(splb_slv0_Sl_rdDBus),
.Sl_rdWdAddr(splb_slv0_Sl_rdWdAddr),
.Sl_rdDAck(splb_slv0_Sl_rdDAck),
.Sl_rdComp(splb_slv0_Sl_rdComp),
.Sl_rdBTerm(splb_slv0_Sl_rdBTerm),
.Sl_MBusy(splb_slv0_Sl_MBusy),
.Sl_MWrErr(splb_slv0_Sl_MWrErr),
.Sl_MRdErr(splb_slv0_Sl_MRdErr),
.Sl_MIRQ(splb_slv0_Sl_MIRQ));
nfa_accept_samples_generic_hw_ap_rst_if #(
.RESET_ACTIVE_LOW(RESET_ACTIVE_LOW))
ap_rst_if_U(
.dout(sig_nfa_accept_samples_generic_hw_ap_rst),
.din(aresetn));
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// one-way bidirectional connection:
// altera message_off 10665
module acl_ic_slave_endpoint
#(
parameter integer DATA_W = 32, // > 0
parameter integer BURSTCOUNT_W = 4, // > 0
parameter integer ADDRESS_W = 32, // > 0
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer ID_W = 1, // > 0
parameter integer NUM_MASTERS = 1, // > 0
parameter integer PIPELINE_RETURN_PATHS = 1, // 0|1
parameter integer WRP_FIFO_DEPTH = 0, // >= 0 (0 disables)
parameter integer RRP_FIFO_DEPTH = 1, // > 0 (don't care if SLAVE_FIXED_LATENCY > 0)
parameter integer RRP_USE_LL_FIFO = 1, // 0|1
parameter integer SLAVE_FIXED_LATENCY = 0, // 0=not fixed latency, >0=# fixed latency cycles
// if >0 effectively RRP_FIFO_DEPTH=SLAVE_FIXED_LATENCY+1
parameter integer SEPARATE_READ_WRITE_STALLS = 0 // 0|1
)
(
input logic clock,
input logic resetn,
// Arbitrated master.
acl_arb_intf m_intf,
// Slave.
acl_arb_intf s_intf,
input logic s_readdatavalid,
input logic [DATA_W-1:0] s_readdata,
input logic s_writeack,
// Write return path.
acl_ic_wrp_intf wrp_intf,
// Read return path.
acl_ic_rrp_intf rrp_intf
);
logic wrp_stall, rrp_stall;
generate
if( SEPARATE_READ_WRITE_STALLS == 0 )
begin
// Need specific sensitivity list instead of always_comb
// otherwise Modelsim will encounter an infinite loop.
always @(s_intf.stall, m_intf.req, rrp_stall, wrp_stall)
begin
// Arbitration request.
s_intf.req = m_intf.req;
if( rrp_stall | wrp_stall )
begin
s_intf.req.read = 1'b0;
s_intf.req.write = 1'b0;
end
// Stall signals.
m_intf.stall = s_intf.stall | rrp_stall | wrp_stall;
end
end
else
begin
// Need specific sensitivity list instead of always_comb
// otherwise Modelsim will encounter an infinite loop.
always @(s_intf.stall, m_intf.req, rrp_stall, wrp_stall)
begin
// Arbitration request.
s_intf.req = m_intf.req;
if( rrp_stall )
s_intf.req.read = 1'b0;
if( wrp_stall )
s_intf.req.write = 1'b0;
// Stall signals.
m_intf.stall = s_intf.stall;
if( m_intf.req.request & m_intf.req.read & rrp_stall )
m_intf.stall = 1'b1;
if( m_intf.req.request & m_intf.req.write & wrp_stall )
m_intf.stall = 1'b1;
end
end
endgenerate
// Write return path.
acl_ic_slave_wrp #(
.DATA_W(DATA_W),
.BURSTCOUNT_W(BURSTCOUNT_W),
.ADDRESS_W(ADDRESS_W),
.BYTEENA_W(BYTEENA_W),
.ID_W(ID_W),
.FIFO_DEPTH(WRP_FIFO_DEPTH),
.NUM_MASTERS(NUM_MASTERS),
.PIPELINE(PIPELINE_RETURN_PATHS)
)
wrp (
.clock( clock ),
.resetn( resetn ),
.m_intf( m_intf ),
.wrp_intf( wrp_intf ),
.s_writeack( s_writeack ),
.stall( wrp_stall )
);
// Read return path.
acl_ic_slave_rrp #(
.DATA_W(DATA_W),
.BURSTCOUNT_W(BURSTCOUNT_W),
.ADDRESS_W(ADDRESS_W),
.BYTEENA_W(BYTEENA_W),
.ID_W(ID_W),
.FIFO_DEPTH(RRP_FIFO_DEPTH),
.USE_LL_FIFO(RRP_USE_LL_FIFO),
.SLAVE_FIXED_LATENCY(SLAVE_FIXED_LATENCY),
.NUM_MASTERS(NUM_MASTERS),
.PIPELINE(PIPELINE_RETURN_PATHS)
)
rrp (
.clock( clock ),
.resetn( resetn ),
.m_intf( m_intf ),
.s_readdatavalid( s_readdatavalid ),
.s_readdata( s_readdata ),
.rrp_intf( rrp_intf ),
.stall( rrp_stall )
);
endmodule
|
`timescale 1ns/100ps
// -----------------------------------------------------------------------------
// One-level up Hierarchical module
// -----------------------------------------------------------------------------
module a_h
// Verilog 2001 style
#(parameter M=5, N=3)
(
// Outputs
output [N-1:0] [M-1:0] a_o1 // From Ia of autoinst_sv_kulkarni_base.v
// End of automatics
// AUTOINPUT*/
);
/*AUTOWIRE*/
autoinst_sv_kulkarni_base
#(/*AUTOINSTPARAM*/
// Parameters
.M (M),
.N (N))
Ia
(/*AUTOINST*/
// Outputs
.a_o1 (a_o1/*[N-1:0][M-1:0]*/),
// Inputs
.a_i1 (a_i1/*[N-1:0][M-1:0]*/)); // <---- BUG?
endmodule
// -----------------------------------------------------------------------------
// Top-level module or Testbench
// -----------------------------------------------------------------------------
module top;
parameter M=4;
parameter N=2;
wire [N-1:0] a_o1;
logic [N-1:0][M-1:0] a_i1;
logic temp;
/*AUTOWIRE*/
// Workaround to fix multi-dimensional port problem
// a) Set "verilog-auto-inst-vector = nil"
// b) ----> a_h AUTO_TEMPLATE ( .\(.*\) (\1), ); */
a_h #(/*AUTOINSTPARAM*/
// Parameters
.M (M),
.N (N))
Ua_h
(/*AUTOINST*/
// Outputs
.a_o1 (a_o1/*[N-1:0][M-1:0]*/)); // <---- BUG?
// Stimulus
initial begin
a_i1 = { 4'h0, 4'h2 };
#5;
$display("Loop Init: a_i1 = { %h, %h } a_o1 = %h\n",
a_i1[1], a_i1[0], a_o1);
#5;
for (int i=0; i<1; i++) begin
for (int j=0; j<N; j++) begin
temp = 1'b0;
for (int k=0; k<M; k++) begin
a_i1[j][k] = temp;
temp = ~temp;
end
end
#5;
$display("Loop %0d: a_i1 = { %h, %h } a_o1 = %h\n",
i, a_i1[1], a_i1[0], a_o1);
#5;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLRTN_FUNCTIONAL_PP_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_pg/sky130_fd_sc_hs__u_dl_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrtn (
VPWR ,
VGND ,
Q ,
RESET_B,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hs__u_dl_p_r_pg `UNIT_DELAY u_dl_p_r_pg0 (buf_Q , D, intgate, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTN_FUNCTIONAL_PP_V |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
///////////////////////////////////////////////////////////////////////////////
// © 2007-2008 Xilinx, Inc. All Rights Reserved.
// Confidential and proprietary information of Xilinx, Inc.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 1.0
// \ \ Filename: egress_fifo_wrapper.v
// / / Date Last Modified: Apr. 1st, 2008
// /___/ /\ Date Created: Apr. 1st, 2008
// \ \ / \
// \___\/\___\
//
// Device: Virtex-5 LXT
// Purpose: This module wraps two fifo36 primitives and pipelines the Read
// data output along with the Empty flag. The interface still
// appears exactly like a regular FIFO36 without a pipeline, except
// there is one extra clock cycle of latency when the fifo goes to
// a non-empty state.
//
// Reference: XAPP859
// Revision History:
// Rev 1.0 - First created, Kraig Lund, Apr. 1 2008.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module egress_fifo_wrapper(
input wire RST,
input wire WRCLK,
input wire WREN,
input wire [127:0] DI,
output wire FULL,
output wire ALMOSTFULL,
input wire RDCLK,
input wire RDEN,
output reg [127:0] DO,
output wire EMPTY,
output wire ALMOSTEMPTY
);
//state machine states
localparam EMPTY_STATE = 2'b00;
localparam DEASSERT_EMPTY = 2'b01;
localparam RDEN_PASS = 2'b10;
localparam WAIT = 2'b11;
wire full_a;
wire almostfull_a;
wire full_b;
wire almostfull_b;
wire almostempty_a;
wire almostempty_b;
wire empty_a;
wire empty_b;
wire empty_or;
reg empty_reg;
wire almostempty_or;
reg almostempty_reg;
reg rden_reg;
wire rden_fifo;
reg [1:0] state;
//if the user wishes to remove the pipeline on the read
//path then define SINGLECYCLE
//This reference design does not define SINGLECYCLE as
//the pipeline is needed for 250 MHz timing
`ifndef SINGLECYCLE
reg rden_d1;
`endif
wire [127:0] do_fifo;
//EGRESS or READ from DDR2 MEMORY FIFO
FIFO36_72 #(
.ALMOST_EMPTY_OFFSET (9'h005),
.ALMOST_FULL_OFFSET (9'h114),
.DO_REG (1),
.EN_ECC_WRITE ("FALSE"),
.EN_ECC_READ ("FALSE"),
.EN_SYN ("FALSE"),
.FIRST_WORD_FALL_THROUGH ("FALSE"))
egress_fifo_a(
.ALMOSTEMPTY (almostempty_a),
.ALMOSTFULL (almostfull_a),
.DBITERR (),
.DO (do_fifo[63:0]),
.DOP (),
.ECCPARITY (),
.EMPTY (empty_a),
.FULL (full_a),
.RDCOUNT (),
.RDERR (),
.SBITERR (),
.WRCOUNT (),
.WRERR (),
.DI (DI[63:0]),
.DIP (),
.RDCLK (RDCLK),
.RDEN (rden_fifo),
.RST (RST),
.WRCLK (WRCLK),
.WREN (WREN)
);
FIFO36_72 #(
.ALMOST_EMPTY_OFFSET (9'h005),
.ALMOST_FULL_OFFSET (9'h114),
.DO_REG (1),
.EN_ECC_WRITE ("FALSE"),
.EN_ECC_READ ("FALSE"),
.EN_SYN ("FALSE"),
.FIRST_WORD_FALL_THROUGH ("FALSE"))
egress_fifo_b(
.ALMOSTEMPTY (almostempty_b),
.ALMOSTFULL (almostfull_b),
.DBITERR (),
.DO (do_fifo[127:64]),
.DOP (),
.ECCPARITY (),
.EMPTY (empty_b),
.FULL (full_b),
.RDCOUNT (),
.RDERR (),
.SBITERR (),
.WRCOUNT (),
.WRERR (),
.DI (DI[127:64]),
.DIP (),
.RDCLK (RDCLK),
.RDEN (rden_fifo),
.RST (RST),
.WRCLK (WRCLK),
.WREN (WREN)
);
//Careful with the fifo status signals when using two fifos in parallel
//Empty flags (and Almost Empty flags) which are synchronous to rdclk
//could deassert on different rdclk cycles due to minute differences in the
//wrclk arrival time (wrclk clock skew). This is because deassertion
//is caused by writing data into an empty fifo i.e. a wrclk domain event
//and this event must cross clock domains.
//Assertion is caused by reading the last piece of data out of the fifo.
//Since rden is a rdclk domain signal/event it is guaranteed that both fifos
//will assert empty on the same rdclk cycle (as long as rden and rdclk are
//are the same signals for both fifos)
//Similarily the Full flags (and almost full flags) which are synchronous to
//wrclk could deassert on different wrclk cycles due to minute differences
//in the rdclk arrival time (rdclk clock skew).
//In both cases the flags should be wire or'ed (since they are positive logic)
//so that the flag doesn't deassert unless both flags are deasserted
assign empty_or = empty_a | empty_b;
assign almostempty_or = almostempty_a | almostempty_b;
assign ALMOSTFULL = almostfull_a | almostfull_b;
assign FULL = full_a | full_b;
assign EMPTY = empty_reg; //empty_reg is output from
//the state machine
`ifdef SINGLECYCLE
assign rden_fifo = (RDEN | rden_reg) & ~empty_or;
`else
//read the fifo if the state machine requests it (rden_reg)
//or if the outside RDEN is asserted (delayed by one - rden_d1)
assign rden_fifo = (rden_d1 | rden_reg) & ~empty_or;
`endif
//pipeline the read path for 250 Mhz timing
//empty flag gets registered in the state machine
always@(posedge RDCLK)begin
almostempty_reg <= almostempty_or;
end
//pipeline the read data path to match the pipelined empty signal
always@(posedge RDCLK)begin
if(RDEN)
DO[127:0] <= do_fifo[127:0];
end
`ifndef SINGLECYCLE
//once the FIFO36 actually go empty, do not pass the RDEN signal to the
//primitives - otherwise pass it to keep the pipeline filled
always@(posedge RDCLK)begin
if(state == RDEN_PASS & (empty_or & RDEN))
rden_d1 <= 1'b0;
else if(state == RDEN_PASS & ~(empty_or & RDEN))
rden_d1 <= RDEN;
end
`endif
//State machine block
//This state machine monitors the empty flags of the FIFO36 primitives and
//controls the assertion/deassertion of pipelined empty flag. It also controls
//whether the RDEN gets passed to the actual FIFO36 or not
always@(posedge RDCLK)begin
if(RST)begin
state <= EMPTY_STATE;
empty_reg <= 1;
rden_reg <= 0;
end else begin
case(state)
EMPTY_STATE:begin
empty_reg <= 1'b1;
if(~empty_or)begin
rden_reg <= 1'b1;
state <= DEASSERT_EMPTY;
end else begin
rden_reg <= 1'b0;
state <= EMPTY_STATE;
end
end
DEASSERT_EMPTY:begin //deassert the empty flag one clock later
empty_reg <= 1'b0;
rden_reg <= 1'b0;
state <= RDEN_PASS;
end
RDEN_PASS:begin //now allow the RDEN signal to pass to the FIFO36
rden_reg <= 1'b0;
if(empty_or & RDEN)begin
empty_reg <= 1'b1;
`ifdef SINGLECYCLE
state <= EMPTY_STATE;
`else
state <= WAIT;
`endif
end else begin
empty_reg <= 1'b0;
state <= RDEN_PASS;
end
end
`ifndef SINGLECYCLE
WAIT:begin
empty_reg <= 1'b1;
rden_reg <= 1'b0;
state <= EMPTY_STATE;
end
`endif
default:begin
state <= EMPTY_STATE;
empty_reg <= 1;
rden_reg <= 0;
end
endcase
end
end
endmodule
|
// -- (c) Copyright 2011 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Register Slice
// Generic single-channel AXI pipeline register on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axic_sample_cycle_ratio
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_clock_converter_v2_1_axic_sample_cycle_ratio # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_RATIO = 2 // Must be > 0
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire SLOW_ACLK,
input wire FAST_ACLK,
output wire SAMPLE_CYCLE_EARLY,
output wire SAMPLE_CYCLE
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_DELAY = C_RATIO > 2 ? C_RATIO-1 : C_RATIO-1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg slow_aclk_div2 = 0;
reg posedge_finder_first;
reg posedge_finder_second;
wire first_edge;
wire second_edge;
reg [P_DELAY-1:0] sample_cycle_d;
(* shreg_extract = "no" *) reg sample_cycle_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_RATIO == 1) begin : gen_always_sample
assign SAMPLE_CYCLE_EARLY = 1'b1;
assign SAMPLE_CYCLE = 1'b1;
end
else begin : gen_sample_cycle
genvar i;
always @(posedge SLOW_ACLK) begin
slow_aclk_div2 <= ~slow_aclk_div2;
end
// Find matching rising edges by clocking slow_aclk_div2 onto faster clock
always @(posedge FAST_ACLK) begin
posedge_finder_first <= slow_aclk_div2;
end
always @(posedge FAST_ACLK) begin
posedge_finder_second <= ~slow_aclk_div2;
end
assign first_edge = slow_aclk_div2 & ~posedge_finder_first;
assign second_edge = ~slow_aclk_div2 & ~posedge_finder_second;
always @(*) begin
sample_cycle_d[P_DELAY-1] = first_edge | second_edge;
end
// delay the posedge alignment by C_RATIO - 1 to set the sample cycle as
// the clock one cycle before the posedge.
for (i = P_DELAY-1; i > 0; i = i - 1) begin : gen_delay
always @(posedge FAST_ACLK) begin
sample_cycle_d[i-1] <= sample_cycle_d[i];
end
end
always @(posedge FAST_ACLK) begin
sample_cycle_r <= sample_cycle_d[0];
end
assign SAMPLE_CYCLE_EARLY = sample_cycle_d[0];
assign SAMPLE_CYCLE = sample_cycle_r;
end
endgenerate
endmodule // axisc_sample_cycle_ratio
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_BEHAVIORAL_PP_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tapvpwrvgnd (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXTP_SYMBOL_V
`define SKY130_FD_SC_LS__DFXTP_SYMBOL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXTP_SYMBOL_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : board.v
// Version : 1.11
// Description: Top level testbench
//
//------------------------------------------------------------------------------
`timescale 1ns/1ns
`include "board_common.v"
`define SIMULATION
module board;
parameter REF_CLK_FREQ = 0; // 0 - 100 MHz, 1 - 125 MHz, 2 - 250 MHz
localparam REF_CLK_HALF_CYCLE = (REF_CLK_FREQ == 0) ? 5000 :
(REF_CLK_FREQ == 1) ? 4000 :
(REF_CLK_FREQ == 2) ? 2000 : 0;
integer i;
// System-level clock and reset
reg sys_rst_n;
wire ep_sys_clk;
wire rp_sys_clk;
//
// PCI-Express Serial Interconnect
//
wire [3:0] ep_pci_exp_txn;
wire [3:0] ep_pci_exp_txp;
wire [3:0] rp_pci_exp_txn;
wire [3:0] rp_pci_exp_txp;
//
// PCI-Express Endpoint Instance
//
xilinx_pcie_2_1_ep_7x # (
.PL_FAST_TRAIN("TRUE")
)
EP (
// SYS Inteface
.sys_clk_n(ep_sys_clk_n),
.sys_clk_p(ep_sys_clk_p),
.sys_rst_n(sys_rst_n),
`ifdef ENABLE_LEDS
// Misc signals
.led_0(),
.led_1(),
.led_2(),
`endif
// PCI-Express Interface
.pci_exp_txn(ep_pci_exp_txn),
.pci_exp_txp(ep_pci_exp_txp),
.pci_exp_rxn(rp_pci_exp_txn),
.pci_exp_rxp(rp_pci_exp_txp)
);
//
// PCI-Express Model Root Port Instance
//
xilinx_pcie_2_1_rport_7x # (
.REF_CLK_FREQ(0),
.PL_FAST_TRAIN("TRUE"),
.ALLOW_X8_GEN2("FALSE"),
.C_DATA_WIDTH(64),
.LINK_CAP_MAX_LINK_WIDTH(6'h04),
.DEVICE_ID(16'h7100),
.LINK_CAP_MAX_LINK_SPEED(4'h2),
.LINK_CTRL2_TARGET_LINK_SPEED(4'h2),
.DEV_CAP_MAX_PAYLOAD_SUPPORTED(3),
.TRN_DW("FALSE"),
.VC0_TX_LASTPACKET(30),
.VC0_RX_RAM_LIMIT(13'hFFF),
.VC0_CPL_INFINITE("TRUE"),
.VC0_TOTAL_CREDITS_PD(949),
.VC0_TOTAL_CREDITS_CD(973),
.USER_CLK_FREQ(3),
.USER_CLK2_DIV2("FALSE")
)
RP (
// SYS Inteface
.sys_clk(rp_sys_clk),
.sys_rst_n(sys_rst_n),
// PCI-Express Interface
.pci_exp_txn(rp_pci_exp_txn),
.pci_exp_txp(rp_pci_exp_txp),
.pci_exp_rxn(ep_pci_exp_txn),
.pci_exp_rxp(ep_pci_exp_txp)
);
sys_clk_gen # (
.halfcycle(REF_CLK_HALF_CYCLE),
.offset(0)
)
CLK_GEN_RP (
.sys_clk(rp_sys_clk)
);
sys_clk_gen_ds # (
.halfcycle(REF_CLK_HALF_CYCLE),
.offset(0)
)
CLK_GEN_EP (
.sys_clk_p(ep_sys_clk_p),
.sys_clk_n(ep_sys_clk_n)
);
initial begin
$display("[%t] : System Reset Asserted...", $realtime);
sys_rst_n = 1'b0;
for (i = 0; i < 500; i = i + 1) begin
@(posedge ep_sys_clk_p);
end
$display("[%t] : System Reset De-asserted...", $realtime);
sys_rst_n = 1'b1;
end
initial begin
if ($test$plusargs ("dump_all")) begin
`ifdef NCV // Cadence TRN dump
$recordsetup("design=board",
"compress",
"wrapsize=100M",
"version=1",
"run=1");
$recordvars();
`elsif VCS //Synopsys VPD dump
$vcdplusfile("board.vpd");
$vcdpluson;
$vcdplusglitchon;
$vcdplusflush;
`else
// Verilog VC dump
$dumpfile("board.vcd");
$dumpvars(0, board);
`endif
end
end
endmodule // BOARD
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: rx_port_32.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Receives data from the rx_engine and buffers the output
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module rx_port_32 #(
parameter C_DATA_WIDTH = 9'd32,
parameter C_MAIN_FIFO_DEPTH = 1024,
parameter C_SG_FIFO_DEPTH = 512,
parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
// Local parameters
parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1),
parameter C_MAIN_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_MAIN_FIFO_DEPTH))+1),
parameter C_SG_FIFO_DEPTH_WIDTH = clog2((2**clog2(C_SG_FIFO_DEPTH))+1)
)
(
input CLK,
input RST,
input [2:0] CONFIG_MAX_READ_REQUEST_SIZE, // Maximum read payload: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B
output SG_RX_BUF_RECVD, // Scatter gather RX buffer completely read (ready for next if applicable)
input [31:0] SG_RX_BUF_DATA, // Scatter gather RX buffer data
input SG_RX_BUF_LEN_VALID, // Scatter gather RX buffer length valid
input SG_RX_BUF_ADDR_HI_VALID, // Scatter gather RX buffer high address valid
input SG_RX_BUF_ADDR_LO_VALID, // Scatter gather RX buffer low address valid
output SG_TX_BUF_RECVD, // Scatter gather TX buffer completely read (ready for next if applicable)
input [31:0] SG_TX_BUF_DATA, // Scatter gather TX buffer data
input SG_TX_BUF_LEN_VALID, // Scatter gather TX buffer length valid
input SG_TX_BUF_ADDR_HI_VALID, // Scatter gather TX buffer high address valid
input SG_TX_BUF_ADDR_LO_VALID, // Scatter gather TX buffer low address valid
output [C_DATA_WIDTH-1:0] SG_DATA, // Scatter gather TX buffer data
output SG_DATA_EMPTY, // Scatter gather TX buffer data empty
input SG_DATA_REN, // Scatter gather TX buffer data read enable
input SG_RST, // Scatter gather TX buffer data reset
output SG_ERR, // Scatter gather TX encountered an error
input [31:0] TXN_DATA, // Read transaction data
input TXN_LEN_VALID, // Read transaction length valid
input TXN_OFF_LAST_VALID, // Read transaction offset/last valid
output [31:0] TXN_DONE_LEN, // Read transaction actual transfer length
output TXN_DONE, // Read transaction done
input TXN_DONE_ACK, // Read transaction actual transfer length read
output RX_REQ, // Read request
input RX_REQ_ACK, // Read request accepted
output [1:0] RX_REQ_TAG, // Read request data tag
output [63:0] RX_REQ_ADDR, // Read request address
output [9:0] RX_REQ_LEN, // Read request length
input [C_DATA_WIDTH-1:0] MAIN_DATA, // Main incoming data
input [C_DATA_WORD_WIDTH-1:0] MAIN_DATA_EN, // Main incoming data enable
input MAIN_DONE, // Main incoming data complete
input MAIN_ERR, // Main incoming data completed with error
input [C_DATA_WIDTH-1:0] SG_RX_DATA, // Scatter gather for RX incoming data
input [C_DATA_WORD_WIDTH-1:0] SG_RX_DATA_EN, // Scatter gather for RX incoming data enable
input SG_RX_DONE, // Scatter gather for RX incoming data complete
input SG_RX_ERR, // Scatter gather for RX incoming data completed with error
input [C_DATA_WIDTH-1:0] SG_TX_DATA, // Scatter gather for TX incoming data
input [C_DATA_WORD_WIDTH-1:0] SG_TX_DATA_EN, // Scatter gather for TX incoming data enable
input SG_TX_DONE, // Scatter gather for TX incoming data complete
input SG_TX_ERR, // Scatter gather for TX incoming data completed with error
input CHNL_CLK, // Channel read clock
output CHNL_RX, // Channel read receive signal
input CHNL_RX_ACK, // Channle read received signal
output CHNL_RX_LAST, // Channel last read
output [31:0] CHNL_RX_LEN, // Channel read length
output [30:0] CHNL_RX_OFF, // Channel read offset
output [C_DATA_WIDTH-1:0] CHNL_RX_DATA, // Channel read data
output CHNL_RX_DATA_VALID, // Channel read data valid
input CHNL_RX_DATA_REN // Channel read data has been recieved
);
`include "functions.vh"
wire [C_DATA_WIDTH-1:0] wPackedMainData;
wire wPackedMainWen;
wire wPackedMainDone;
wire wPackedMainErr;
wire wMainFlush;
wire wMainFlushed;
wire [C_DATA_WIDTH-1:0] wPackedSgRxData;
wire wPackedSgRxWen;
wire wPackedSgRxDone;
wire wPackedSgRxErr;
wire wSgRxFlush;
wire wSgRxFlushed;
wire [C_DATA_WIDTH-1:0] wPackedSgTxData;
wire wPackedSgTxWen;
wire wPackedSgTxDone;
wire wPackedSgTxErr;
wire wSgTxFlush;
wire wSgTxFlushed;
wire wMainDataRen;
wire wMainDataEmpty;
wire [C_DATA_WIDTH-1:0] wMainData;
wire wSgRxRst;
wire wSgRxDataRen;
wire wSgRxDataEmpty;
wire [C_DATA_WIDTH-1:0] wSgRxData;
wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgRxFifoCount;
wire wSgTxRst;
wire [C_SG_FIFO_DEPTH_WIDTH-1:0] wSgTxFifoCount;
wire wSgRxReq;
wire [63:0] wSgRxReqAddr;
wire [9:0] wSgRxReqLen;
wire wSgTxReq;
wire [63:0] wSgTxReqAddr;
wire [9:0] wSgTxReqLen;
wire wSgRxReqProc;
wire wSgTxReqProc;
wire wMainReqProc;
wire wReqAck;
wire wSgElemRdy;
wire wSgElemRen;
wire [63:0] wSgElemAddr;
wire [31:0] wSgElemLen;
wire wSgRst;
wire wMainReq;
wire [63:0] wMainReqAddr;
wire [9:0] wMainReqLen;
wire wTxnErr;
wire wChnlRx;
wire wChnlRxRecvd;
wire wChnlRxAckRecvd;
wire wChnlRxLast;
wire [31:0] wChnlRxLen;
wire [30:0] wChnlRxOff;
wire [31:0] wChnlRxConsumed;
reg [4:0] rWideRst=0;
reg rRst=0;
assign SG_ERR = (wPackedSgTxDone & wPackedSgTxErr);
// Generate a wide reset from the input reset.
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST)
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
// Pack received data tightly into our FIFOs
fifo_packer_32 mainFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(MAIN_DATA),
.DATA_IN_EN(MAIN_DATA_EN),
.DATA_IN_DONE(MAIN_DONE),
.DATA_IN_ERR(MAIN_ERR),
.DATA_IN_FLUSH(wMainFlush),
.PACKED_DATA(wPackedMainData),
.PACKED_WEN(wPackedMainWen),
.PACKED_DATA_DONE(wPackedMainDone),
.PACKED_DATA_ERR(wPackedMainErr),
.PACKED_DATA_FLUSHED(wMainFlushed)
);
fifo_packer_32 sgRxFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(SG_RX_DATA),
.DATA_IN_EN(SG_RX_DATA_EN),
.DATA_IN_DONE(SG_RX_DONE),
.DATA_IN_ERR(SG_RX_ERR),
.DATA_IN_FLUSH(wSgRxFlush),
.PACKED_DATA(wPackedSgRxData),
.PACKED_WEN(wPackedSgRxWen),
.PACKED_DATA_DONE(wPackedSgRxDone),
.PACKED_DATA_ERR(wPackedSgRxErr),
.PACKED_DATA_FLUSHED(wSgRxFlushed)
);
fifo_packer_32 sgTxFifoPacker (
.CLK(CLK),
.RST(rRst),
.DATA_IN(SG_TX_DATA),
.DATA_IN_EN(SG_TX_DATA_EN),
.DATA_IN_DONE(SG_TX_DONE),
.DATA_IN_ERR(SG_TX_ERR),
.DATA_IN_FLUSH(wSgTxFlush),
.PACKED_DATA(wPackedSgTxData),
.PACKED_WEN(wPackedSgTxWen),
.PACKED_DATA_DONE(wPackedSgTxDone),
.PACKED_DATA_ERR(wPackedSgTxErr),
.PACKED_DATA_FLUSHED(wSgTxFlushed)
);
// FIFOs for storing received data for the channel.
(* RAM_STYLE="BLOCK" *)
async_fifo_fwft #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_MAIN_FIFO_DEPTH)) mainFifo (
.WR_CLK(CLK),
.WR_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
.WR_EN(wPackedMainWen),
.WR_DATA(wPackedMainData),
.WR_FULL(),
.RD_CLK(CHNL_CLK),
.RD_RST(rRst | (wTxnErr & TXN_DONE) | wSgRst),
.RD_EN(wMainDataRen),
.RD_DATA(wMainData),
.RD_EMPTY(wMainDataEmpty)
);
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgRxFifo (
.RST(rRst | wSgRxRst),
.CLK(CLK),
.WR_EN(wPackedSgRxWen),
.WR_DATA(wPackedSgRxData),
.FULL(),
.RD_EN(wSgRxDataRen),
.RD_DATA(wSgRxData),
.EMPTY(wSgRxDataEmpty),
.COUNT(wSgRxFifoCount)
);
(* RAM_STYLE="BLOCK" *)
sync_fifo #(.C_WIDTH(C_DATA_WIDTH), .C_DEPTH(C_SG_FIFO_DEPTH), .C_PROVIDE_COUNT(1)) sgTxFifo (
.RST(rRst | wSgTxRst),
.CLK(CLK),
.WR_EN(wPackedSgTxWen),
.WR_DATA(wPackedSgTxData),
.FULL(),
.RD_EN(SG_DATA_REN),
.RD_DATA(SG_DATA),
.EMPTY(SG_DATA_EMPTY),
.COUNT(wSgTxFifoCount)
);
// Manage requesting and acknowledging scatter gather data. Note that
// these modules will share the main requestor's RX channel. They will
// take priority over the main logic's use of the RX channel.
sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgRxReq (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.USER_RST(wSgRst),
.BUF_RECVD(SG_RX_BUF_RECVD),
.BUF_DATA(SG_RX_BUF_DATA),
.BUF_LEN_VALID(SG_RX_BUF_LEN_VALID),
.BUF_ADDR_HI_VALID(SG_RX_BUF_ADDR_HI_VALID),
.BUF_ADDR_LO_VALID(SG_RX_BUF_ADDR_LO_VALID),
.FIFO_COUNT(wSgRxFifoCount),
.FIFO_FLUSH(wSgRxFlush),
.FIFO_FLUSHED(wSgRxFlushed),
.FIFO_RST(wSgRxRst),
.RX_REQ(wSgRxReq),
.RX_ADDR(wSgRxReqAddr),
.RX_LEN(wSgRxReqLen),
.RX_REQ_ACK(wReqAck & wSgRxReqProc),
.RX_DONE(wPackedSgRxDone)
);
sg_list_requester #(.C_FIFO_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_SG_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) sgTxReq (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.USER_RST(SG_RST),
.BUF_RECVD(SG_TX_BUF_RECVD),
.BUF_DATA(SG_TX_BUF_DATA),
.BUF_LEN_VALID(SG_TX_BUF_LEN_VALID),
.BUF_ADDR_HI_VALID(SG_TX_BUF_ADDR_HI_VALID),
.BUF_ADDR_LO_VALID(SG_TX_BUF_ADDR_LO_VALID),
.FIFO_COUNT(wSgTxFifoCount),
.FIFO_FLUSH(wSgTxFlush),
.FIFO_FLUSHED(wSgTxFlushed),
.FIFO_RST(wSgTxRst),
.RX_REQ(wSgTxReq),
.RX_ADDR(wSgTxReqAddr),
.RX_LEN(wSgTxReqLen),
.RX_REQ_ACK(wReqAck & wSgTxReqProc),
.RX_DONE(wPackedSgTxDone)
);
// A read requester for the channel and scatter gather requesters.
rx_port_requester_mux requesterMux (
.RST(rRst),
.CLK(CLK),
.SG_RX_REQ(wSgRxReq),
.SG_RX_LEN(wSgRxReqLen),
.SG_RX_ADDR(wSgRxReqAddr),
.SG_RX_REQ_PROC(wSgRxReqProc),
.SG_TX_REQ(wSgTxReq),
.SG_TX_LEN(wSgTxReqLen),
.SG_TX_ADDR(wSgTxReqAddr),
.SG_TX_REQ_PROC(wSgTxReqProc),
.MAIN_REQ(wMainReq),
.MAIN_LEN(wMainReqLen),
.MAIN_ADDR(wMainReqAddr),
.MAIN_REQ_PROC(wMainReqProc),
.RX_REQ(RX_REQ),
.RX_REQ_ACK(RX_REQ_ACK),
.RX_REQ_TAG(RX_REQ_TAG),
.RX_REQ_ADDR(RX_REQ_ADDR),
.RX_REQ_LEN(RX_REQ_LEN),
.REQ_ACK(wReqAck)
);
// Read the scatter gather buffer address and length, continuously so that
// we have it ready whenever the next buffer is needed.
sg_list_reader_32 #(.C_DATA_WIDTH(C_DATA_WIDTH)) sgListReader (
.CLK(CLK),
.RST(rRst | wSgRst),
.BUF_DATA(wSgRxData),
.BUF_DATA_EMPTY(wSgRxDataEmpty),
.BUF_DATA_REN(wSgRxDataRen),
.VALID(wSgElemRdy),
.EMPTY(),
.REN(wSgElemRen),
.ADDR(wSgElemAddr),
.LEN(wSgElemLen)
);
// Main port reader logic
rx_port_reader #(.C_DATA_WIDTH(C_DATA_WIDTH), .C_FIFO_DEPTH(C_MAIN_FIFO_DEPTH), .C_MAX_READ_REQ(C_MAX_READ_REQ)) reader (
.CLK(CLK),
.RST(rRst),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.TXN_DATA(TXN_DATA),
.TXN_LEN_VALID(TXN_LEN_VALID),
.TXN_OFF_LAST_VALID(TXN_OFF_LAST_VALID),
.TXN_DONE_LEN(TXN_DONE_LEN),
.TXN_DONE(TXN_DONE),
.TXN_ERR(wTxnErr),
.TXN_DONE_ACK(TXN_DONE_ACK),
.TXN_DATA_FLUSH(wMainFlush),
.TXN_DATA_FLUSHED(wMainFlushed),
.RX_REQ(wMainReq),
.RX_ADDR(wMainReqAddr),
.RX_LEN(wMainReqLen),
.RX_REQ_ACK(wReqAck & wMainReqProc),
.RX_DATA_EN(MAIN_DATA_EN),
.RX_DONE(wPackedMainDone),
.RX_ERR(wPackedMainErr),
.SG_DONE(wPackedSgRxDone),
.SG_ERR(wPackedSgRxErr),
.SG_ELEM_ADDR(wSgElemAddr),
.SG_ELEM_LEN(wSgElemLen),
.SG_ELEM_RDY(wSgElemRdy),
.SG_ELEM_REN(wSgElemRen),
.SG_RST(wSgRst),
.CHNL_RX(wChnlRx),
.CHNL_RX_LEN(wChnlRxLen),
.CHNL_RX_LAST(wChnlRxLast),
.CHNL_RX_OFF(wChnlRxOff),
.CHNL_RX_RECVD(wChnlRxRecvd),
.CHNL_RX_ACK_RECVD(wChnlRxAckRecvd),
.CHNL_RX_CONSUMED(wChnlRxConsumed)
);
// Manage the CHNL_RX* signals in the CHNL_CLK domain.
rx_port_channel_gate #(.C_DATA_WIDTH(C_DATA_WIDTH)) gate (
.RST(rRst),
.CLK(CLK),
.RX(wChnlRx),
.RX_RECVD(wChnlRxRecvd),
.RX_ACK_RECVD(wChnlRxAckRecvd),
.RX_LAST(wChnlRxLast),
.RX_LEN(wChnlRxLen),
.RX_OFF(wChnlRxOff),
.RX_CONSUMED(wChnlRxConsumed),
.RD_DATA(wMainData),
.RD_EMPTY(wMainDataEmpty),
.RD_EN(wMainDataRen),
.CHNL_CLK(CHNL_CLK),
.CHNL_RX(CHNL_RX),
.CHNL_RX_ACK(CHNL_RX_ACK),
.CHNL_RX_LAST(CHNL_RX_LAST),
.CHNL_RX_LEN(CHNL_RX_LEN),
.CHNL_RX_OFF(CHNL_RX_OFF),
.CHNL_RX_DATA(CHNL_RX_DATA),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN)
);
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({SG_RX_DATA_EN != 0, wSgElemRen, wMainReq | wSgRxReq | wSgTxReq,
RX_REQ, SG_RX_BUF_ADDR_LO_VALID | SG_RX_BUF_ADDR_HI_VALID | SG_RX_BUF_LEN_VALID,
wSgRst, wTxnErr | wPackedSgRxDone | wSgRxFlush | wSgRxFlushed, TXN_OFF_LAST_VALID | TXN_LEN_VALID}),
.DATA({
wPackedSgRxErr, // 1
wPackedSgRxDone, // 1
wPackedSgRxWen, // 1
wPackedSgRxData, // 64
SG_RX_ERR, // 1
SG_RX_DONE, // 1
SG_RX_DATA_EN, // 2
SG_RX_DATA, // 64
wSgRxDataRen, // 1
wSgRxDataEmpty, // 1
wSgRxData, // 64
wSgRst, // 1
SG_RST, // 1
wPackedSgRxDone, // 1
wSgRxRst, // 1
wSgRxFlushed, // 1
wSgRxFlush, // 1
SG_RX_BUF_ADDR_LO_VALID, // 1
SG_RX_BUF_ADDR_HI_VALID, // 1
SG_RX_BUF_LEN_VALID, // 1
SG_RX_BUF_DATA, // 32
RX_REQ_ADDR, // 64
RX_REQ_TAG, // 2
RX_REQ_ACK, // 1
RX_REQ, // 1
wSgTxReqProc, // 1
wSgTxReqAddr, // 64
wSgTxReq, // 1
wSgRxReqProc, // 1
wSgRxReqAddr, // 64
wSgRxReq, // 1
wMainReqProc, // 1
wMainReqAddr, // 64
wMainReq, // 1
wReqAck, // 1
wTxnErr, // 1
TXN_OFF_LAST_VALID, // 1
TXN_LEN_VALID}) // 1
);
*/
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2015 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file instructionROM.v when simulating
// the core, instructionROM. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module instructionROM(
clka,
addra,
douta
);
input clka;
input [7 : 0] addra;
output [31 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V7_3 #(
.C_ADDRA_WIDTH(8),
.C_ADDRB_WIDTH(8),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(0),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE("BlankString"),
.C_INIT_FILE_NAME("instructionROM.mif"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(1),
.C_MEM_TYPE(3),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(256),
.C_READ_DEPTH_B(256),
.C_READ_WIDTH_A(32),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BRAM_BLOCK(0),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(256),
.C_WRITE_DEPTH_B(256),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ADDRA(addra),
.DOUTA(douta),
.RSTA(),
.ENA(),
.REGCEA(),
.WEA(),
.DINA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module mux(opA,opB,sum,dsp_sel,out);
input [3:0] opA,opB;
input [4:0] sum;
input [1:0] dsp_sel;
output [3:0] out;
reg cout;
always @ (sum)
begin
if (sum[4] == 1)
cout <= 4'b0001;
else
cout <= 4'b0000;
end
reg out;
always @(dsp_sel,sum,cout,opB,opA)
begin
if (dsp_sel == 2'b00)
out <= sum[3:0];
else if (dsp_sel == 2'b01)
out <= cout;
else if (dsp_sel == 2'b10)
out <= opB;
else if (dsp_sel == 2'b11)
out <= opA;
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_convert_with_rounding_8(clock, resetn, dataa, result, valid_in, valid_out, stall_in, stall_out, enable);
// Latency = 4.
parameter UNSIGNED = 1;
parameter ROUNDING_MODE = 0;
parameter HIGH_CAPACITY = 1;
// Rounding mode values are:
// 0 - round to nearest even
// 1 - round to nearest with ties away from zero
// 2 - round towards zero (truncation)
// 3 - round up
// 4 - round down
input clock;
input enable, resetn;
input [31:0] dataa;
output [7:0] result;
input valid_in, stall_in;
output stall_out, valid_out;
// STAGE 0 - extract input data into format we can work with.
wire sign_0;
wire [7:0] exp_0;
wire [22:0] man_0;
wire [23:0] implied_man_0;
assign {sign_0, exp_0, man_0} = dataa;
assign implied_man_0 = (|exp_0) ? {1'b1, man_0} : 24'd0;
// STAGE 1
reg sign_c1;
reg [10:0] man_c1;
reg [8:0] shift_amount_c1;
reg [7:0] exp_c1;
reg valid_c1;
wire stall_c1;
wire enable_c1;
assign stall_out = stall_c1 & valid_c1;
assign enable_c1 = (HIGH_CAPACITY == 1) ? (~stall_c1 | ~valid_c1) : enable;
always @( posedge clock or negedge resetn)
begin
if( ~resetn )
begin
sign_c1 <= 1'bx;
man_c1 <= 11'dx;
shift_amount_c1 <= 9'dx;
exp_c1 <= 8'dx;
valid_c1 <= 1'b0;
end
else if (enable_c1)
begin
sign_c1 <= sign_0;
valid_c1 <= valid_in;
if (UNSIGNED == 1)
begin
man_c1 <= {implied_man_0[23:14], |implied_man_0[13:0]};
shift_amount_c1 <= 9'd134 - exp_0;
end
else
begin
man_c1 <= {1'b0, implied_man_0[23:15], |implied_man_0[14:0]};
shift_amount_c1 <= 9'd133 - exp_0;
end
exp_c1 <= exp_0;
end
end
// STAGE 2
reg sign_c2;
reg [10:0] extended_mantissa_c2;
reg [2:0] shift_amount_c2;
reg valid_c2;
wire stall_c2;
wire enable_c2 = (HIGH_CAPACITY == 1) ? (~stall_c2 | ~valid_c2) : enable;
assign stall_c1 = stall_c2 & valid_c2;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
sign_c2 <= 1'bx;
extended_mantissa_c2 <= 11'dx;
shift_amount_c2 <= 3'dx;
valid_c2 <= 1'b0;
end
else if (enable_c2)
begin
sign_c2 <= sign_c1;
valid_c2 <= valid_c1;
shift_amount_c2 <= (shift_amount_c1[2:0]) & {3{(~(&exp_c1)) & ~shift_amount_c1[8]}};
// Now handle the corner cases of NaN and INF. Make it maximum positive or negative integer depending on the sign.
// Then handle overflow and regular shifting.
if ((UNSIGNED == 1) && (exp_c1 == 8'hff))
extended_mantissa_c2 <= {8'hff, 3'd0};
else if ((UNSIGNED == 0) && (exp_c1 == 8'hff))
extended_mantissa_c2 <= {8'h7f + sign_c1, 3'd0};
else if (shift_amount_c1[8])
extended_mantissa_c2 <= {(UNSIGNED == 0) ? 8'h7f + sign_c1 : 8'hff, 3'd0}; // Overflow/Saturation.
else if (|shift_amount_c1[7:4])
begin
// Shift by more than 16+
sign_c2 <= sign_c1 & (|man_c1);
extended_mantissa_c2 <= {10'd0, |man_c1};
end
else if (|shift_amount_c1[3])
begin
// Shift by 8+
extended_mantissa_c2 <= {8'd0, man_c1[10:9], |man_c1[8:0]};
end
else
extended_mantissa_c2 <= man_c1;
end
end
// STAGE 3
reg [10:0] extended_mantissa_c3;
reg valid_c3;
reg sign_c3;
wire stall_c3;
wire enable_c3 = (HIGH_CAPACITY == 1) ? (~valid_c3 | ~stall_c3) : enable;
assign stall_c2 = valid_c3 & stall_c3;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
extended_mantissa_c3 <= 35'dx;
sign_c3 <= 1'bx;
valid_c3 <= 1'b0;
end
else if (enable_c3)
begin
valid_c3 <= valid_c2;
sign_c3 <= sign_c2;
case (shift_amount_c2)
3'b111: extended_mantissa_c3 <= {7'd0, extended_mantissa_c2[10:8], |extended_mantissa_c2[7:0]};
3'b110: extended_mantissa_c3 <= {6'd0, extended_mantissa_c2[10:7], |extended_mantissa_c2[6:0]};
3'b101: extended_mantissa_c3 <= {5'd0, extended_mantissa_c2[10:6], |extended_mantissa_c2[5:0]};
3'b100: extended_mantissa_c3 <= {4'd0, extended_mantissa_c2[10:5], |extended_mantissa_c2[4:0]};
3'b011: extended_mantissa_c3 <= {3'd0, extended_mantissa_c2[10:4], |extended_mantissa_c2[3:0]};
3'b010: extended_mantissa_c3 <= {2'd0, extended_mantissa_c2[10:3], |extended_mantissa_c2[2:0]};
3'b001: extended_mantissa_c3 <= {1'd0, extended_mantissa_c2[10:2], |extended_mantissa_c2[1:0]};
3'b000: extended_mantissa_c3 <= extended_mantissa_c2;
endcase
end
end
// STAGE 4
reg [8:0] result_c4;
reg valid_c4;
wire stall_c4;
wire enable_c4 = (HIGH_CAPACITY == 1) ? (~valid_c4 | ~stall_c4) : enable;
assign stall_c3 = valid_c4 & stall_c4;
assign stall_c4 = stall_in;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
result_c4 <= 9'dx;
valid_c4 <= 1'b0;
end
else if (enable_c4)
begin
valid_c4 <= valid_c3;
case(ROUNDING_MODE)
2:
begin // 2 is round to zero
if (UNSIGNED == 0)
begin
result_c4 <= ({9{sign_c3}} ^ (extended_mantissa_c3[10:3])) + sign_c3;
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3];
end
end
4:
begin // 4 is round down
if (|extended_mantissa_c3[2:0])
begin
if (UNSIGNED == 0)
begin
result_c4 <= (sign_c3) ? (({9{sign_c3}} ^ (extended_mantissa_c3[10:3] + 1'b1)) + 1'b1) : extended_mantissa_c3[10:3];
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3];
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
3:
begin // 3 is round up
if (|extended_mantissa_c3[2:0])
begin
if (UNSIGNED == 0)
begin
result_c4 <= (sign_c3) ? (({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + 1'b1) : (extended_mantissa_c3[10:3] + 1'b1);
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
1:
begin // 1 is round to nearest with ties rounded away from zero.
if (extended_mantissa_c3[2])
begin
if (UNSIGNED == 0)
begin
result_c4 <= ({9{sign_c3}} ^ (extended_mantissa_c3[10:3] + 1'b1)) + sign_c3;
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
default:
begin // 0 and default are round to nearest even
if ((extended_mantissa_c3[3:0] == 4'hc) | (extended_mantissa_c3[2] & (|extended_mantissa_c3[1:0])))
begin
if (UNSIGNED == 0)
begin
result_c4 <= ({9{sign_c3}} ^ (extended_mantissa_c3[10:3] + 1'b1)) + sign_c3;
end
else
begin
result_c4 <= (sign_c3) ? 8'd0 : extended_mantissa_c3[10:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c4 <= ({9{sign_c3}} ^ extended_mantissa_c3[10:3]) + sign_c3;
else
result_c4 <= {8{~sign_c3}} & extended_mantissa_c3[10:3];
end
end
endcase
end
end
// handle saturation here too, just in case rounding went over the limit of the expected range.
assign result = (UNSIGNED == 1) ? ({8{result_c4[8]}} | result_c4) : ((result_c4[8] ^ result_c4[7]) ? {result_c4[8], {7{~result_c4[8]}}} : result_c4[7:0]);
assign valid_out = valid_c4;
endmodule
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_jtag.v
// Title : JTAG interface
// Dependencies : lm32_include.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// Version : 3.9
// : Support added for 'Fast Download' register in Debugger
// =============================================================================
`include "lm32_include.v"
`ifdef CFG_JTAG_ENABLED
`define LM32_DP 3'b000
`define LM32_TX 3'b001
`define LM32_RX 3'b010
`define LM32_FD 3'b100
// LM32 Debug Protocol commands IDs
`define LM32_DP_RNG 3:0
`define LM32_DP_READ_MEMORY 4'b0001
`define LM32_DP_WRITE_MEMORY 4'b0010
`define LM32_DP_READ_SEQUENTIAL 4'b0011
`define LM32_DP_WRITE_SEQUENTIAL 4'b0100
`define LM32_DP_WRITE_CSR 4'b0101
`define LM32_DP_BREAK 4'b0110
`define LM32_DP_RESET 4'b0111
// States for FSM
`define LM32_JTAG_STATE_RNG 3:0
`define LM32_JTAG_STATE_READ_COMMAND 4'h0
`define LM32_JTAG_STATE_READ_BYTE_0 4'h1
`define LM32_JTAG_STATE_READ_BYTE_1 4'h2
`define LM32_JTAG_STATE_READ_BYTE_2 4'h3
`define LM32_JTAG_STATE_READ_BYTE_3 4'h4
`define LM32_JTAG_STATE_READ_BYTE_4 4'h5
`define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6
`define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7
`define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_jtag
(
// ----- Inputs -------
clk_i,
rst_i,
jtag_clk,
jtag_update,
jtag_reg_q,
jtag_reg_addr_q,
`ifdef CFG_JTAG_UART_ENABLED
csr,
csr_write_enable,
csr_write_data,
stall_x,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
jtag_read_data,
jtag_access_complete,
`endif
`ifdef CFG_DEBUG_ENABLED
exception_q_w,
`endif
// ----- Outputs -------
`ifdef CFG_JTAG_UART_ENABLED
jtx_csr_read_data,
jrx_csr_read_data,
`endif
`ifdef CFG_HW_DEBUG_ENABLED
jtag_csr_write_enable,
jtag_csr_write_data,
jtag_csr,
jtag_read_enable,
jtag_write_enable,
jtag_write_data,
jtag_address,
`endif
`ifdef CFG_DEBUG_ENABLED
jtag_break,
jtag_reset,
`endif
jtag_reg_d,
jtag_reg_addr_d
);
parameter lat_family = `LATTICE_FAMILY;
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
input jtag_clk; // JTAG clock
input jtag_update; // JTAG data register has been updated
`ifdef CFG_FAST_DOWNLOAD_ENABLED
input [`DOWNLOAD_BUFFER_SIZE-1:0] jtag_reg_q; // JTAG data register
`else
input [7:0] jtag_reg_q; // JTAG data register
`endif
input [2:0] jtag_reg_addr_q; // JTAG data register
`ifdef CFG_JTAG_UART_ENABLED
input [`LM32_CSR_RNG] csr; // CSR to write
input csr_write_enable; // CSR write enable
input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
input stall_x; // Stall instruction in X stage
`endif
`ifdef CFG_HW_DEBUG_ENABLED
input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address
input jtag_access_complete; // Memory access if complete
`endif
`ifdef CFG_DEBUG_ENABLED
input exception_q_w; // Indicates an exception has occured in W stage
`endif
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef CFG_JTAG_UART_ENABLED
output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions
wire [`LM32_WORD_RNG] jtx_csr_read_data;
output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions
wire [`LM32_WORD_RNG] jrx_csr_read_data;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
output jtag_csr_write_enable; // CSR write enable
reg jtag_csr_write_enable;
output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
wire [`LM32_WORD_RNG] jtag_csr_write_data;
output [`LM32_CSR_RNG] jtag_csr; // CSR to write
wire [`LM32_CSR_RNG] jtag_csr;
output jtag_read_enable; // Memory read enable
reg jtag_read_enable;
output jtag_write_enable; // Memory write enable
reg jtag_write_enable;
output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address
wire [`LM32_BYTE_RNG] jtag_write_data;
output [`LM32_WORD_RNG] jtag_address; // Memory read/write address
wire [`LM32_WORD_RNG] jtag_address;
`endif
`ifdef CFG_DEBUG_ENABLED
output jtag_break; // Request to raise a breakpoint exception
reg jtag_break;
output jtag_reset; // Request to raise a reset exception
reg jtag_reset;
`endif
output [`LM32_BYTE_RNG] jtag_reg_d;
reg [`LM32_BYTE_RNG] jtag_reg_d;
output [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_d;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg rx_toggle; // Clock-domain crossing registers
reg rx_toggle_r; // Registered version of rx_toggle
reg rx_toggle_r_r; // Registered version of rx_toggle_r
reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r
reg [`LM32_BYTE_RNG] rx_byte;
reg [2:0] rx_addr;
`ifdef CFG_JTAG_UART_ENABLED
reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data
reg uart_tx_valid; // TX data is valid
reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data
reg uart_rx_valid; // RX data is valid
`ifdef CFG_FAST_DOWNLOAD_ENABLED
reg [`DOWNLOAD_BUFFER_SIZE-1:8] uart_rx_fifo;
reg [`DOWNLOAD_BUFFER_SIZE-1:8] rx_fifo;
reg [4:0] uart_rx_fifo_ptr;
reg uart_rx_fifo_transaction;
`endif
`endif
reg [`LM32_DP_RNG] command; // The last received command
`ifdef CFG_HW_DEBUG_ENABLED
reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters
reg [`LM32_BYTE_RNG] jtag_byte_1;
reg [`LM32_BYTE_RNG] jtag_byte_2;
reg [`LM32_BYTE_RNG] jtag_byte_3;
reg [`LM32_BYTE_RNG] jtag_byte_4;
reg processing; // Indicates if we're still processing a memory read/write
`endif
reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
`ifdef CFG_HW_DEBUG_ENABLED
assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
assign jtag_write_data = jtag_byte_4;
`endif
// Generate status flags for reading via the JTAG interface
`ifdef CFG_JTAG_UART_ENABLED
assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
`else
assign jtag_reg_addr_d[1:0] = 2'b00;
`endif
`ifdef CFG_HW_DEBUG_ENABLED
assign jtag_reg_addr_d[2] = processing;
`else
`ifdef CFG_FAST_DOWNLOAD_ENABLED
assign jtag_reg_addr_d[2] = 1'b1;
`else
assign jtag_reg_addr_d[2] = 1'b0;
`endif
`endif
`ifdef CFG_JTAG_UART_ENABLED
assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
`endif
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
// Toggle a flag when a JTAG write occurs
always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
rx_toggle <= #1 1'b0;
else
rx_toggle <= #1 ~rx_toggle;
end
always @(*)
begin
rx_byte = jtag_reg_q[7:0];
`ifdef CFG_FAST_DOWNLOAD_ENABLED
rx_fifo = jtag_reg_q[`DOWNLOAD_BUFFER_SIZE-1:8];
`endif
rx_addr = jtag_reg_addr_q;
end
// Clock domain crossing from JTAG clock domain to CPU clock domain
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
rx_toggle_r <= #1 1'b0;
rx_toggle_r_r <= #1 1'b0;
rx_toggle_r_r_r <= #1 1'b0;
end
else
begin
rx_toggle_r <= #1 rx_toggle;
rx_toggle_r_r <= #1 rx_toggle_r;
rx_toggle_r_r_r <= #1 rx_toggle_r_r;
end
end
// LM32 debug protocol state machine
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
state <= #1 `LM32_JTAG_STATE_READ_COMMAND;
command <= #1 4'b0000;
jtag_reg_d <= #1 8'h00;
`ifdef CFG_HW_DEBUG_ENABLED
processing <= #1 `FALSE;
jtag_csr_write_enable <= #1 `FALSE;
jtag_read_enable <= #1 `FALSE;
jtag_write_enable <= #1 `FALSE;
`endif
`ifdef CFG_DEBUG_ENABLED
jtag_break <= #1 `FALSE;
jtag_reset <= #1 `FALSE;
`endif
`ifdef CFG_JTAG_UART_ENABLED
uart_tx_byte <= #1 8'h00;
uart_tx_valid <= #1 `FALSE;
uart_rx_byte <= #1 8'h00;
uart_rx_valid <= #1 `FALSE;
`ifdef CFG_FAST_DOWNLOAD_ENABLED
uart_rx_fifo <= #1 0;
uart_rx_fifo_ptr <= #1 0;
uart_rx_fifo_transaction <= #1 0;
`endif
`endif
end
else
begin
`ifdef CFG_JTAG_UART_ENABLED
if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
begin
case (csr)
`LM32_CSR_JTX:
begin
// Set flag indicating data is available
uart_tx_byte <= #1 csr_write_data[`LM32_BYTE_0_RNG];
uart_tx_valid <= #1 `TRUE;
end
`LM32_CSR_JRX:
begin
`ifdef CFG_FAST_DOWNLOAD_ENABLED
// Clear flag indidicating data has been received
if (uart_rx_fifo_transaction)
begin
case (uart_rx_fifo_ptr)
// 5'h00: uart_rx_byte <= #1 uart_rx_fifo[ 7: 0];
5'h00: uart_rx_byte <= #1 uart_rx_fifo[ 15: 8];
5'h01: uart_rx_byte <= #1 uart_rx_fifo[ 23: 16];
5'h02: uart_rx_byte <= #1 uart_rx_fifo[ 31: 24];
5'h03: uart_rx_byte <= #1 uart_rx_fifo[ 39: 32];
5'h04: uart_rx_byte <= #1 uart_rx_fifo[ 47: 40];
5'h05: uart_rx_byte <= #1 uart_rx_fifo[ 55: 48];
5'h06: uart_rx_byte <= #1 uart_rx_fifo[ 63: 56];
5'h07: uart_rx_byte <= #1 uart_rx_fifo[ 71: 64];
5'h08: uart_rx_byte <= #1 uart_rx_fifo[ 79: 72];
5'h09: uart_rx_byte <= #1 uart_rx_fifo[ 87: 80];
5'h0A: uart_rx_byte <= #1 uart_rx_fifo[ 95: 88];
5'h0B: uart_rx_byte <= #1 uart_rx_fifo[103: 96];
5'h0C: uart_rx_byte <= #1 uart_rx_fifo[111:104];
5'h0D: uart_rx_byte <= #1 uart_rx_fifo[119:112];
5'h0E: uart_rx_byte <= #1 uart_rx_fifo[127:120];
`ifdef DOWNLOAD_BUFFER_SIZE_256
5'h0F: uart_rx_byte <= #1 uart_rx_fifo[135:128];
5'h10: uart_rx_byte <= #1 uart_rx_fifo[143:136];
5'h11: uart_rx_byte <= #1 uart_rx_fifo[151:144];
5'h12: uart_rx_byte <= #1 uart_rx_fifo[159:152];
5'h13: uart_rx_byte <= #1 uart_rx_fifo[167:160];
5'h14: uart_rx_byte <= #1 uart_rx_fifo[175:168];
5'h15: uart_rx_byte <= #1 uart_rx_fifo[183:176];
5'h16: uart_rx_byte <= #1 uart_rx_fifo[191:184];
5'h17: uart_rx_byte <= #1 uart_rx_fifo[199:192];
5'h18: uart_rx_byte <= #1 uart_rx_fifo[207:200];
5'h19: uart_rx_byte <= #1 uart_rx_fifo[215:208];
5'h1A: uart_rx_byte <= #1 uart_rx_fifo[223:216];
5'h1B: uart_rx_byte <= #1 uart_rx_fifo[231:224];
5'h1C: uart_rx_byte <= #1 uart_rx_fifo[239:232];
5'h1D: uart_rx_byte <= #1 uart_rx_fifo[247:240];
5'h1E: uart_rx_byte <= #1 uart_rx_fifo[255:248];
`endif
default:
uart_rx_byte <= 8'h00;
endcase
uart_rx_fifo_ptr <= #1 uart_rx_fifo_ptr + 1'b1;
`ifdef DOWNLOAD_BUFFER_SIZE_256
if (uart_rx_fifo_ptr == 5'h1F)
`else
if (uart_rx_fifo_ptr == 5'h0F)
`endif
begin
uart_rx_fifo_transaction <= #1 `FALSE;
uart_rx_valid <= #1 `FALSE;
end
end
else
`endif
uart_rx_valid <= #1 `FALSE;
end
endcase
end
`endif
`ifdef CFG_DEBUG_ENABLED
// When an exception has occured, clear the requests
if (exception_q_w == `TRUE)
begin
jtag_break <= #1 `FALSE;
jtag_reset <= #1 `FALSE;
end
`endif
case (state)
`LM32_JTAG_STATE_READ_COMMAND:
begin
// Wait for rx register to toggle which indicates new data is available
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
command <= #1 rx_byte[7:4];
case (rx_addr)
`ifdef CFG_DEBUG_ENABLED
`LM32_DP:
begin
case (rx_byte[7:4])
`ifdef CFG_HW_DEBUG_ENABLED
`LM32_DP_READ_MEMORY:
state <= #1 `LM32_JTAG_STATE_READ_BYTE_0;
`LM32_DP_READ_SEQUENTIAL:
begin
{jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1;
state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND;
end
`LM32_DP_WRITE_MEMORY:
state <= #1 `LM32_JTAG_STATE_READ_BYTE_0;
`LM32_DP_WRITE_SEQUENTIAL:
begin
{jtag_byte_2, jtag_byte_3} <= #1 {jtag_byte_2, jtag_byte_3} + 1'b1;
state <= #1 5;
end
`LM32_DP_WRITE_CSR:
state <= #1 `LM32_JTAG_STATE_READ_BYTE_0;
`endif
`LM32_DP_BREAK:
begin
`ifdef CFG_JTAG_UART_ENABLED
uart_rx_valid <= #1 `FALSE;
uart_tx_valid <= #1 `FALSE;
`endif
jtag_break <= #1 `TRUE;
end
`LM32_DP_RESET:
begin
`ifdef CFG_JTAG_UART_ENABLED
uart_rx_valid <= #1 `FALSE;
uart_tx_valid <= #1 `FALSE;
`endif
jtag_reset <= #1 `TRUE;
end
endcase
end
`endif
`ifdef CFG_JTAG_UART_ENABLED
`LM32_TX:
begin
uart_rx_byte <= #1 rx_byte;
uart_rx_valid <= #1 `TRUE;
end
`LM32_RX:
begin
jtag_reg_d <= #1 uart_tx_byte;
uart_tx_valid <= #1 `FALSE;
end
`ifdef CFG_FAST_DOWNLOAD_ENABLED
`LM32_FD:
begin
uart_rx_byte <= #1 rx_byte;
uart_rx_valid <= #1 `TRUE;
uart_rx_fifo <= #1 rx_fifo;
uart_rx_fifo_ptr <= #1 5'h0;
uart_rx_fifo_transaction <= #1 1'b1;
end
`endif
`endif
default:
;
endcase
end
end
`ifdef CFG_HW_DEBUG_ENABLED
`LM32_JTAG_STATE_READ_BYTE_0:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_0 <= #1 rx_byte;
state <= #1 `LM32_JTAG_STATE_READ_BYTE_1;
end
end
`LM32_JTAG_STATE_READ_BYTE_1:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_1 <= #1 rx_byte;
state <= #1 `LM32_JTAG_STATE_READ_BYTE_2;
end
end
`LM32_JTAG_STATE_READ_BYTE_2:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_2 <= #1 rx_byte;
state <= #1 `LM32_JTAG_STATE_READ_BYTE_3;
end
end
`LM32_JTAG_STATE_READ_BYTE_3:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_3 <= #1 rx_byte;
if (command == `LM32_DP_READ_MEMORY)
state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND;
else
state <= #1 `LM32_JTAG_STATE_READ_BYTE_4;
end
end
`LM32_JTAG_STATE_READ_BYTE_4:
begin
if (rx_toggle_r_r != rx_toggle_r_r_r)
begin
jtag_byte_4 <= #1 rx_byte;
state <= #1 `LM32_JTAG_STATE_PROCESS_COMMAND;
end
end
`LM32_JTAG_STATE_PROCESS_COMMAND:
begin
case (command)
`LM32_DP_READ_MEMORY,
`LM32_DP_READ_SEQUENTIAL:
begin
jtag_read_enable <= #1 `TRUE;
processing <= #1 `TRUE;
state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
end
`LM32_DP_WRITE_MEMORY,
`LM32_DP_WRITE_SEQUENTIAL:
begin
jtag_write_enable <= #1 `TRUE;
processing <= #1 `TRUE;
state <= #1 `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
end
`LM32_DP_WRITE_CSR:
begin
jtag_csr_write_enable <= #1 `TRUE;
processing <= #1 `TRUE;
state <= #1 `LM32_JTAG_STATE_WAIT_FOR_CSR;
end
endcase
end
`LM32_JTAG_STATE_WAIT_FOR_MEMORY:
begin
if (jtag_access_complete == `TRUE)
begin
jtag_read_enable <= #1 `FALSE;
jtag_reg_d <= #1 jtag_read_data;
jtag_write_enable <= #1 `FALSE;
processing <= #1 `FALSE;
state <= #1 `LM32_JTAG_STATE_READ_COMMAND;
end
end
`LM32_JTAG_STATE_WAIT_FOR_CSR:
begin
jtag_csr_write_enable <= #1 `FALSE;
processing <= #1 `FALSE;
state <= #1 `LM32_JTAG_STATE_READ_COMMAND;
end
`endif
endcase
end
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BO_BLACKBOX_V
`define SKY130_FD_SC_MS__A21BO_BLACKBOX_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21bo (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BO_BLACKBOX_V
|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0_header.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
/******************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Data cache implementation
Copyright (C) 2012-2013
Stefan Kristiansson <[email protected]>
Stefan Wallentowitz <[email protected]>
******************************************************************************/
`include "mor1kx-defines.v"
module mor1kx_dcache
#(
parameter OPTION_OPERAND_WIDTH = 32,
parameter OPTION_DCACHE_BLOCK_WIDTH = 5,
parameter OPTION_DCACHE_SET_WIDTH = 9,
parameter OPTION_DCACHE_WAYS = 2,
parameter OPTION_DCACHE_LIMIT_WIDTH = 32,
parameter OPTION_DCACHE_SNOOP = "NONE"
)
(
input clk,
input rst,
input dc_dbus_err_i,
input dc_enable_i,
input dc_access_i,
output refill_o,
output refill_req_o,
output refill_done_o,
// CPU Interface
output cpu_err_o,
output cpu_ack_o,
output reg [OPTION_OPERAND_WIDTH-1:0] cpu_dat_o,
input [OPTION_OPERAND_WIDTH-1:0] cpu_dat_i,
input [OPTION_OPERAND_WIDTH-1:0] cpu_adr_i,
input [OPTION_OPERAND_WIDTH-1:0] cpu_adr_match_i,
input cpu_req_i,
input cpu_we_i,
input [3:0] cpu_bsel_i,
input refill_allowed,
input [OPTION_OPERAND_WIDTH-1:0] wradr_i,
input [OPTION_OPERAND_WIDTH-1:0] wrdat_i,
input we_i,
// Snoop address
input [31:0] snoop_adr_i,
// Snoop event in this cycle
input snoop_valid_i,
// Whether the snoop hit. If so, there will be no tag memory write
// this cycle. The LSU may need to stall the pipeline.
output snoop_hit_o,
// SPR interface
input [15:0] spr_bus_addr_i,
input spr_bus_we_i,
input spr_bus_stb_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i,
output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o,
output spr_bus_ack_o
);
// States
localparam IDLE = 5'b00001;
localparam READ = 5'b00010;
localparam WRITE = 5'b00100;
localparam REFILL = 5'b01000;
localparam INVALIDATE = 5'b10000;
// Address space in bytes for a way
localparam WAY_WIDTH = OPTION_DCACHE_BLOCK_WIDTH + OPTION_DCACHE_SET_WIDTH;
/*
* Tag memory layout
* +---------------------------------------------------------+
* (index) -> | LRU | wayN valid | wayN tag |...| way0 valid | way0 tag |
* +---------------------------------------------------------+
*/
// The tag is the part left of the index
localparam TAG_WIDTH = (OPTION_DCACHE_LIMIT_WIDTH - WAY_WIDTH);
// The tag memory contains entries with OPTION_DCACHE_WAYS parts of
// each TAGMEM_WAY_WIDTH. Each of those is tag and a valid flag.
localparam TAGMEM_WAY_WIDTH = TAG_WIDTH + 1;
localparam TAGMEM_WAY_VALID = TAGMEM_WAY_WIDTH - 1;
// Additionally, the tag memory entry contains an LRU value. The
// width of this is 0 for OPTION_DCACHE_LIMIT_WIDTH==1
localparam TAG_LRU_WIDTH = OPTION_DCACHE_WAYS*(OPTION_DCACHE_WAYS-1) >> 1;
// We have signals for the LRU which are not used for one way
// caches. To avoid signal width [-1:0] this generates [0:0]
// vectors for them, which are removed automatically then.
localparam TAG_LRU_WIDTH_BITS = (OPTION_DCACHE_WAYS >= 2) ? TAG_LRU_WIDTH : 1;
// Compute the total sum of the entry elements
localparam TAGMEM_WIDTH = TAGMEM_WAY_WIDTH * OPTION_DCACHE_WAYS + TAG_LRU_WIDTH;
// For convenience we define the position of the LRU in the tag
// memory entries
localparam TAG_LRU_MSB = TAGMEM_WIDTH - 1;
localparam TAG_LRU_LSB = TAG_LRU_MSB - TAG_LRU_WIDTH + 1;
// FSM state signals
reg [4:0] state;
wire idle;
wire read;
wire write;
wire refill;
reg [WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH] invalidate_adr;
wire [31:0] next_refill_adr;
reg [31:0] way_wr_dat;
wire refill_done;
wire refill_hit;
reg [(1<<(OPTION_DCACHE_BLOCK_WIDTH-2))-1:0] refill_valid;
reg [(1<<(OPTION_DCACHE_BLOCK_WIDTH-2))-1:0] refill_valid_r;
wire invalidate;
// The index we read and write from tag memory
wire [OPTION_DCACHE_SET_WIDTH-1:0] tag_rindex;
reg [OPTION_DCACHE_SET_WIDTH-1:0] tag_windex;
// The data from the tag memory
wire [TAGMEM_WIDTH-1:0] tag_dout;
wire [TAG_LRU_WIDTH_BITS-1:0] tag_lru_out;
wire [TAGMEM_WAY_WIDTH-1:0] tag_way_out [OPTION_DCACHE_WAYS-1:0];
// The data to the tag memory
wire [TAGMEM_WIDTH-1:0] tag_din;
reg [TAG_LRU_WIDTH_BITS-1:0] tag_lru_in;
reg [TAGMEM_WAY_WIDTH-1:0] tag_way_in [OPTION_DCACHE_WAYS-1:0];
reg [TAGMEM_WAY_WIDTH-1:0] tag_way_save[OPTION_DCACHE_WAYS-1:0];
// Whether to write to the tag memory in this cycle
reg tag_we;
// This is the tag we need to write to the tag memory during refill
wire [TAG_WIDTH-1:0] tag_wtag;
// This is the tag we check against
wire [TAG_WIDTH-1:0] tag_tag;
// Access to the way memories
wire [WAY_WIDTH-3:0] way_raddr[OPTION_DCACHE_WAYS-1:0];
wire [WAY_WIDTH-3:0] way_waddr[OPTION_DCACHE_WAYS-1:0];
wire [OPTION_OPERAND_WIDTH-1:0] way_din[OPTION_DCACHE_WAYS-1:0];
wire [OPTION_OPERAND_WIDTH-1:0] way_dout[OPTION_DCACHE_WAYS-1:0];
reg [OPTION_DCACHE_WAYS-1:0] way_we;
// Does any way hit?
wire hit;
wire [OPTION_DCACHE_WAYS-1:0] way_hit;
// This is the least recently used value before access the memory.
// Those are one hot encoded.
wire [OPTION_DCACHE_WAYS-1:0] lru;
// Register that stores the LRU value from lru
reg [OPTION_DCACHE_WAYS-1:0] tag_save_lru;
// The access vector to update the LRU history is the way that has
// a hit or is refilled. It is also one-hot encoded.
reg [OPTION_DCACHE_WAYS-1:0] access;
// The current LRU history as read from tag memory and the update
// value after we accessed it to write back to tag memory.
wire [TAG_LRU_WIDTH_BITS-1:0] current_lru_history;
wire [TAG_LRU_WIDTH_BITS-1:0] next_lru_history;
// Intermediate signals to ease debugging
wire [TAG_WIDTH-1:0] check_way_tag [OPTION_DCACHE_WAYS-1:0];
wire check_way_match [OPTION_DCACHE_WAYS-1:0];
wire check_way_valid [OPTION_DCACHE_WAYS-1:0];
reg write_pending;
// Extract index to read from snooped address
wire [OPTION_DCACHE_SET_WIDTH-1:0] snoop_index;
assign snoop_index = snoop_adr_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH];
// Register that is high one cycle after the actual snoop event to
// drive the comparison
reg snoop_check;
// Register that stores the tag for one cycle
reg [TAG_WIDTH-1:0] snoop_tag;
// Also store the index for one cycle, for the succeeding write access
reg [OPTION_DCACHE_SET_WIDTH-1:0] snoop_windex;
// Snoop tag memory interface
// Data out of tag memory
wire [TAGMEM_WIDTH-1:0] snoop_dout;
// Each ways information in the tag memory
wire [TAGMEM_WAY_WIDTH-1:0] snoop_way_out [OPTION_DCACHE_WAYS-1:0];
// Each ways tag in the tag memory
wire [TAG_WIDTH-1:0] snoop_check_way_tag [OPTION_DCACHE_WAYS-1:0];
// Whether the tag matches the snoop tag
wire snoop_check_way_match [OPTION_DCACHE_WAYS-1:0];
// Whether the tag is valid
wire snoop_check_way_valid [OPTION_DCACHE_WAYS-1:0];
// Whether the way hits
wire [OPTION_DCACHE_WAYS-1:0] snoop_way_hit;
// Whether any way hits
wire snoop_hit;
assign snoop_hit_o = (OPTION_DCACHE_SNOOP != "NONE") ? snoop_hit : 0;
genvar i;
assign cpu_ack_o = ((read | refill) & hit & !write_pending |
refill_hit) & cpu_req_i & !snoop_hit;
assign tag_rindex = cpu_adr_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH];
assign tag_tag = cpu_adr_match_i[OPTION_DCACHE_LIMIT_WIDTH-1:WAY_WIDTH];
assign tag_wtag = wradr_i[OPTION_DCACHE_LIMIT_WIDTH-1:WAY_WIDTH];
generate
if (OPTION_DCACHE_WAYS >= 2) begin
// Multiplex the LRU history from and to tag memory
assign current_lru_history = tag_dout[TAG_LRU_MSB:TAG_LRU_LSB];
assign tag_din[TAG_LRU_MSB:TAG_LRU_LSB] = tag_lru_in;
assign tag_lru_out = tag_dout[TAG_LRU_MSB:TAG_LRU_LSB];
end
for (i = 0; i < OPTION_DCACHE_WAYS; i=i+1) begin : ways
assign way_raddr[i] = cpu_adr_i[WAY_WIDTH-1:2];
assign way_waddr[i] = write ? cpu_adr_match_i[WAY_WIDTH-1:2] :
wradr_i[WAY_WIDTH-1:2];
assign way_din[i] = way_wr_dat;
// compare stored tag with incoming tag and check valid bit
assign check_way_tag[i] = tag_way_out[i][TAG_WIDTH-1:0];
assign check_way_match[i] = (check_way_tag[i] == tag_tag);
assign check_way_valid[i] = tag_way_out[i][TAGMEM_WAY_VALID];
assign way_hit[i] = check_way_valid[i] & check_way_match[i];
// Multiplex the way entries in the tag memory
assign tag_din[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH] = tag_way_in[i];
assign tag_way_out[i] = tag_dout[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH];
if (OPTION_DCACHE_SNOOP != "NONE") begin
// The same for the snoop tag memory
assign snoop_way_out[i] = snoop_dout[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH];
assign snoop_check_way_tag[i] = snoop_way_out[i][TAG_WIDTH-1:0];
assign snoop_check_way_match[i] = (snoop_check_way_tag[i] == snoop_tag);
assign snoop_check_way_valid[i] = snoop_way_out[i][TAGMEM_WAY_VALID];
assign snoop_way_hit[i] = snoop_check_way_valid[i] & snoop_check_way_match[i];
end
end
endgenerate
assign hit = |way_hit;
assign snoop_hit = (OPTION_DCACHE_SNOOP != "NONE") &
|snoop_way_hit & snoop_check;
integer w0;
always @(*) begin
cpu_dat_o = {OPTION_OPERAND_WIDTH{1'bx}};
// Put correct way on the data port
for (w0 = 0; w0 < OPTION_DCACHE_WAYS; w0 = w0 + 1) begin
if (way_hit[w0] | (refill_hit & tag_save_lru[w0])) begin
cpu_dat_o = way_dout[w0];
end
end
end
assign next_refill_adr = (OPTION_DCACHE_BLOCK_WIDTH == 5) ?
{wradr_i[31:5], wradr_i[4:0] + 5'd4} : // 32 byte
{wradr_i[31:4], wradr_i[3:0] + 4'd4}; // 16 byte
assign refill_done_o = refill_done;
assign refill_done = refill_valid[next_refill_adr[OPTION_DCACHE_BLOCK_WIDTH-1:2]];
assign refill_hit = refill_valid_r[cpu_adr_match_i[OPTION_DCACHE_BLOCK_WIDTH-1:2]] &
cpu_adr_match_i[OPTION_DCACHE_LIMIT_WIDTH-1:
OPTION_DCACHE_BLOCK_WIDTH] ==
wradr_i[OPTION_DCACHE_LIMIT_WIDTH-1:
OPTION_DCACHE_BLOCK_WIDTH] &
refill & !write_pending;
assign idle = (state == IDLE);
assign refill = (state == REFILL);
assign read = (state == READ);
assign write = (state == WRITE);
assign refill_o = refill;
assign refill_req_o = read & cpu_req_i & !hit & !write_pending & refill_allowed | refill;
/*
* SPR bus interface
*/
// The SPR interface is used to invalidate the cache blocks. When
// an invalidation is started, the respective entry in the tag
// memory is cleared. When another transfer is in progress, the
// handling is delayed until it is possible to serve it.
//
// The invalidation is acknowledged to the SPR bus, but the cycle
// is terminated by the core. We therefore need to hold the
// invalidate acknowledgement. Meanwhile we continuously write the
// tag memory which is no problem.
// Net that signals an acknowledgement
reg invalidate_ack;
// An invalidate request is either a block flush or a block invalidate
assign invalidate = spr_bus_stb_i & spr_bus_we_i &
(spr_bus_addr_i == `OR1K_SPR_DCBFR_ADDR |
spr_bus_addr_i == `OR1K_SPR_DCBIR_ADDR);
// Acknowledge to the SPR bus.
assign spr_bus_ack_o = invalidate_ack;
/*
* Cache FSM
* Starts in IDLE.
* State changes between READ and WRITE happens cpu_we_i is asserted or not.
* cpu_we_i is in sync with cpu_adr_i, so that means that it's the
* *upcoming* write that it is indicating. It only toggles for one cycle,
* so if we are busy doing something else when this signal comes
* (i.e. refilling) we assert the write_pending signal.
* cpu_req_i is in sync with cpu_adr_match_i, so it can be used to
* determined if a cache hit should cause a refill or if a write should
* really be executed.
*/
integer w1;
always @(posedge clk `OR_ASYNC_RST) begin
if (rst) begin
state <= IDLE;
write_pending <= 0;
end else if(dc_dbus_err_i) begin
state <= IDLE;
write_pending <= 0;
end else begin
if (cpu_we_i)
write_pending <= 1;
else if (!cpu_req_i)
write_pending <= 0;
refill_valid_r <= refill_valid;
if (snoop_valid_i) begin
//
// If there is a snoop event, we need to store this
// information. This happens independent of whether we
// have a snoop tag memory or not.
//
snoop_check <= 1;
snoop_windex <= snoop_index;
snoop_tag <= snoop_adr_i[OPTION_DCACHE_LIMIT_WIDTH-1:WAY_WIDTH];
end else begin
snoop_check <= 0;
end
case (state)
IDLE: begin
if (invalidate) begin
// If there is an invalidation request
//
// Store address in invalidate_adr that is muxed to the tag
// memory write address
invalidate_adr <= spr_bus_dat_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH];
// Change to invalidate state that actually accesses
// the tag memory
state <= INVALIDATE;
end else if (cpu_we_i | write_pending)
state <= WRITE;
else if (cpu_req_i)
state <= READ;
end
READ: begin
if (dc_access_i | cpu_we_i & dc_enable_i) begin
if (!hit & cpu_req_i & !write_pending & refill_allowed) begin
refill_valid <= 0;
refill_valid_r <= 0;
// Store the LRU information for correct replacement
// on refill. Always one when only one way.
tag_save_lru <= (OPTION_DCACHE_WAYS==1) | lru;
for (w1 = 0; w1 < OPTION_DCACHE_WAYS; w1 = w1 + 1) begin
tag_way_save[w1] <= tag_way_out[w1];
end
state <= REFILL;
end else if (cpu_we_i | write_pending) begin
state <= WRITE;
end else if (invalidate) begin
state <= IDLE;
end
end else if (!dc_enable_i | invalidate) begin
state <= IDLE;
end
end
REFILL: begin
if (we_i) begin
refill_valid[wradr_i[OPTION_DCACHE_BLOCK_WIDTH-1:2]] <= 1;
if (refill_done)
state <= IDLE;
end
// Abort refill on snoop-hit
// TODO: only abort on snoop-hits to refill address
if (snoop_hit) begin
refill_valid <= 0;
refill_valid_r <= 0;
state <= IDLE;
end
end
WRITE: begin
if ((!dc_access_i | !cpu_req_i | !cpu_we_i) & !snoop_hit) begin
write_pending <= 0;
state <= READ;
end
end
INVALIDATE: begin
if (invalidate) begin
// Store address in invalidate_adr that is muxed to the tag
// memory write address
invalidate_adr <= spr_bus_dat_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH];
state <= INVALIDATE;
end else begin
state <= IDLE;
end
end
default:
state <= IDLE;
endcase
end
end
//
// This is the combinational part of the state machine that
// interfaces the tag and way memories.
//
integer w2;
always @(*) begin
// Default is to keep data, don't write and don't access
tag_lru_in = tag_lru_out;
for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin
tag_way_in[w2] = tag_way_out[w2];
end
tag_we = 1'b0;
way_we = {(OPTION_DCACHE_WAYS){1'b0}};
access = {(OPTION_DCACHE_WAYS){1'b0}};
way_wr_dat = wrdat_i;
// The default is (of course) not to acknowledge the invalidate
invalidate_ack = 1'b0;
if (snoop_hit) begin
// This is the write access
tag_we = 1'b1;
tag_windex = snoop_windex;
for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin
if (snoop_way_hit[w2]) begin
tag_way_in[w2] = 0;
end else begin
tag_way_in[w2] = snoop_way_out[w2];
end
end
end else begin
//
// The tag mem is written during reads and writes to write
// the lru info and during refill and invalidate.
//
tag_windex = read | write ?
cpu_adr_match_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH] :
(state == INVALIDATE) ? invalidate_adr :
wradr_i[WAY_WIDTH-1:OPTION_DCACHE_BLOCK_WIDTH];
case (state)
IDLE: begin
//
// When idle we can always acknowledge the invalidate as it
// has the highest priority in handling. When something is
// changed on the state machine handling above this needs
// to be changed.
//
invalidate_ack = 1'b1;
end
READ: begin
if (hit) begin
//
// We got a hit. The LRU module gets the access
// information. Depending on this we update the LRU
// history in the tag.
//
access = way_hit;
// This is the updated LRU history after hit
tag_lru_in = next_lru_history;
tag_we = 1'b1;
end
end
WRITE: begin
way_wr_dat = cpu_dat_i;
if (hit & cpu_req_i) begin
/* Mux cache output with write data */
if (!cpu_bsel_i[3])
way_wr_dat[31:24] = cpu_dat_o[31:24];
if (!cpu_bsel_i[2])
way_wr_dat[23:16] = cpu_dat_o[23:16];
if (!cpu_bsel_i[1])
way_wr_dat[15:8] = cpu_dat_o[15:8];
if (!cpu_bsel_i[0])
way_wr_dat[7:0] = cpu_dat_o[7:0];
way_we = way_hit;
tag_lru_in = next_lru_history;
tag_we = 1'b1;
end
end
REFILL: begin
if (we_i) begin
//
// Write the data to the way that is replaced (which is
// the LRU)
//
way_we = tag_save_lru;
// Access pattern
access = tag_save_lru;
/* Invalidate the way on the first write */
if (refill_valid == 0) begin
for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin
if (tag_save_lru[w2]) begin
tag_way_in[w2][TAGMEM_WAY_VALID] = 1'b0;
end
end
tag_we = 1'b1;
end
//
// After refill update the tag memory entry of the
// filled way with the LRU history, the tag and set
// valid to 1.
//
if (refill_done) begin
for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin
tag_way_in[w2] = tag_way_save[w2];
if (tag_save_lru[w2]) begin
tag_way_in[w2] = { 1'b1, tag_wtag };
end
end
tag_lru_in = next_lru_history;
tag_we = 1'b1;
end
end
end
INVALIDATE: begin
invalidate_ack = 1'b1;
// Lazy invalidation, invalidate everything that matches tag address
tag_lru_in = 0;
for (w2 = 0; w2 < OPTION_DCACHE_WAYS; w2 = w2 + 1) begin
tag_way_in[w2] = 0;
end
tag_we = 1'b1;
end
default: begin
end
endcase
end
end
generate
for (i = 0; i < OPTION_DCACHE_WAYS; i=i+1) begin : way_memories
mor1kx_simple_dpram_sclk
#(
.ADDR_WIDTH(WAY_WIDTH-2),
.DATA_WIDTH(OPTION_OPERAND_WIDTH),
.ENABLE_BYPASS(1)
)
way_data_ram
(
// Outputs
.dout (way_dout[i]),
// Inputs
.clk (clk),
.raddr (way_raddr[i][WAY_WIDTH-3:0]),
.re (1'b1),
.waddr (way_waddr[i][WAY_WIDTH-3:0]),
.we (way_we[i]),
.din (way_din[i][31:0]));
end
if (OPTION_DCACHE_WAYS >= 2) begin : gen_u_lru
/* mor1kx_cache_lru AUTO_TEMPLATE(
.current (current_lru_history),
.update (next_lru_history),
.lru_pre (lru),
.lru_post (),
.access (access),
); */
mor1kx_cache_lru
#(.NUMWAYS(OPTION_DCACHE_WAYS))
u_lru(/*AUTOINST*/
// Outputs
.update (next_lru_history), // Templated
.lru_pre (lru), // Templated
.lru_post (), // Templated
// Inputs
.current (current_lru_history), // Templated
.access (access)); // Templated
end // if (OPTION_DCACHE_WAYS >= 2)
endgenerate
mor1kx_simple_dpram_sclk
#(
.ADDR_WIDTH(OPTION_DCACHE_SET_WIDTH),
.DATA_WIDTH(TAGMEM_WIDTH),
.ENABLE_BYPASS(OPTION_DCACHE_SNOOP != "NONE")
)
tag_ram
(
// Outputs
.dout (tag_dout[TAGMEM_WIDTH-1:0]),
// Inputs
.clk (clk),
.raddr (tag_rindex),
.re (1'b1),
.waddr (tag_windex),
.we (tag_we),
.din (tag_din));
generate
if (OPTION_DCACHE_SNOOP != "NONE") begin
mor1kx_simple_dpram_sclk
#(
.ADDR_WIDTH(OPTION_DCACHE_SET_WIDTH),
.DATA_WIDTH(TAGMEM_WIDTH),
.ENABLE_BYPASS(1)
)
snoop_tag_ram
(
// Outputs
.dout (snoop_dout[TAGMEM_WIDTH-1:0]),
// Inputs
.clk (clk),
.raddr (snoop_index),
.re (1'b1),
.waddr (tag_windex),
.we (tag_we),
.din (tag_din));
end
endgenerate
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
`define AUTOTB_DUT hls_macc
`define AUTOTB_DUT_INST AESL_inst_hls_macc
`define AUTOTB_TOP apatb_hls_macc_top
`define AUTOTB_LAT_RESULT_FILE "hls_macc.result.lat.rb"
`define AUTOTB_PER_RESULT_TRANS_FILE "hls_macc.performance.result.transaction.xml"
`define AUTOTB_TOP_INST AESL_inst_apatb_hls_macc_top
`define AUTOTB_MAX_ALLOW_LATENCY 15000000
`define AUTOTB_CLOCK_PERIOD_DIV2 2.00
`define AESL_DEPTH_a 1
`define AESL_DEPTH_b 1
`define AESL_DEPTH_accum 1
`define AESL_DEPTH_accum_clr 1
`define AUTOTB_TVIN_a "../tv/cdatafile/c.hls_macc.autotvin_a.dat"
`define AUTOTB_TVIN_b "../tv/cdatafile/c.hls_macc.autotvin_b.dat"
`define AUTOTB_TVIN_accum_clr "../tv/cdatafile/c.hls_macc.autotvin_accum_clr.dat"
`define AUTOTB_TVIN_a_out_wrapc "../tv/rtldatafile/rtl.hls_macc.autotvin_a.dat"
`define AUTOTB_TVIN_b_out_wrapc "../tv/rtldatafile/rtl.hls_macc.autotvin_b.dat"
`define AUTOTB_TVIN_accum_clr_out_wrapc "../tv/rtldatafile/rtl.hls_macc.autotvin_accum_clr.dat"
`define AUTOTB_TVOUT_accum "../tv/cdatafile/c.hls_macc.autotvout_accum.dat"
`define AUTOTB_TVOUT_accum_out_wrapc "../tv/rtldatafile/rtl.hls_macc.autotvout_accum.dat"
module `AUTOTB_TOP;
parameter AUTOTB_TRANSACTION_NUM = 4383;
parameter PROGRESS_TIMEOUT = 10000000;
parameter LATENCY_ESTIMATION = 8;
parameter LENGTH_a = 1;
parameter LENGTH_b = 1;
parameter LENGTH_accum = 1;
parameter LENGTH_accum_clr = 1;
task read_token;
input integer fp;
output reg [287 : 0] token;
integer ret;
begin
token = "";
ret = 0;
ret = $fscanf(fp,"%s",token);
end
endtask
reg AESL_clock;
reg rst;
reg start;
reg ce;
reg tb_continue;
wire AESL_start;
wire AESL_reset;
wire AESL_ce;
wire AESL_ready;
wire AESL_idle;
wire AESL_continue;
wire AESL_done;
reg AESL_done_delay = 0;
reg AESL_done_delay2 = 0;
reg AESL_ready_delay = 0;
wire ready;
wire ready_wire;
wire [5 : 0] HLS_MACC_PERIPH_BUS_AWADDR;
wire HLS_MACC_PERIPH_BUS_AWVALID;
wire HLS_MACC_PERIPH_BUS_AWREADY;
wire HLS_MACC_PERIPH_BUS_WVALID;
wire HLS_MACC_PERIPH_BUS_WREADY;
wire [31 : 0] HLS_MACC_PERIPH_BUS_WDATA;
wire [3 : 0] HLS_MACC_PERIPH_BUS_WSTRB;
wire [5 : 0] HLS_MACC_PERIPH_BUS_ARADDR;
wire HLS_MACC_PERIPH_BUS_ARVALID;
wire HLS_MACC_PERIPH_BUS_ARREADY;
wire HLS_MACC_PERIPH_BUS_RVALID;
wire HLS_MACC_PERIPH_BUS_RREADY;
wire [31 : 0] HLS_MACC_PERIPH_BUS_RDATA;
wire [1 : 0] HLS_MACC_PERIPH_BUS_RRESP;
wire HLS_MACC_PERIPH_BUS_BVALID;
wire HLS_MACC_PERIPH_BUS_BREADY;
wire [1 : 0] HLS_MACC_PERIPH_BUS_BRESP;
wire HLS_MACC_PERIPH_BUS_INTERRUPT;
integer done_cnt = 0;
integer AESL_ready_cnt = 0;
integer ready_cnt = 0;
reg ready_initial;
reg ready_initial_n;
reg ready_last_n;
reg ready_delay_last_n;
reg done_delay_last_n;
reg interface_done = 0;
wire HLS_MACC_PERIPH_BUS_read_data_finish;
wire HLS_MACC_PERIPH_BUS_write_data_finish;
wire AESL_slave_start;
reg AESL_slave_start_lock = 0;
wire AESL_slave_write_start_in;
wire AESL_slave_write_start_finish;
reg AESL_slave_ready;
wire AESL_slave_output_done;
wire AESL_slave_done;
reg ready_rise = 0;
reg start_rise = 0;
reg slave_start_status = 0;
reg slave_done_status = 0;
reg ap_done_lock = 0;
wire ap_clk;
wire ap_rst_n;
wire ap_rst_n_n;
`AUTOTB_DUT `AUTOTB_DUT_INST(
.s_axi_HLS_MACC_PERIPH_BUS_AWADDR(HLS_MACC_PERIPH_BUS_AWADDR),
.s_axi_HLS_MACC_PERIPH_BUS_AWVALID(HLS_MACC_PERIPH_BUS_AWVALID),
.s_axi_HLS_MACC_PERIPH_BUS_AWREADY(HLS_MACC_PERIPH_BUS_AWREADY),
.s_axi_HLS_MACC_PERIPH_BUS_WVALID(HLS_MACC_PERIPH_BUS_WVALID),
.s_axi_HLS_MACC_PERIPH_BUS_WREADY(HLS_MACC_PERIPH_BUS_WREADY),
.s_axi_HLS_MACC_PERIPH_BUS_WDATA(HLS_MACC_PERIPH_BUS_WDATA),
.s_axi_HLS_MACC_PERIPH_BUS_WSTRB(HLS_MACC_PERIPH_BUS_WSTRB),
.s_axi_HLS_MACC_PERIPH_BUS_ARADDR(HLS_MACC_PERIPH_BUS_ARADDR),
.s_axi_HLS_MACC_PERIPH_BUS_ARVALID(HLS_MACC_PERIPH_BUS_ARVALID),
.s_axi_HLS_MACC_PERIPH_BUS_ARREADY(HLS_MACC_PERIPH_BUS_ARREADY),
.s_axi_HLS_MACC_PERIPH_BUS_RVALID(HLS_MACC_PERIPH_BUS_RVALID),
.s_axi_HLS_MACC_PERIPH_BUS_RREADY(HLS_MACC_PERIPH_BUS_RREADY),
.s_axi_HLS_MACC_PERIPH_BUS_RDATA(HLS_MACC_PERIPH_BUS_RDATA),
.s_axi_HLS_MACC_PERIPH_BUS_RRESP(HLS_MACC_PERIPH_BUS_RRESP),
.s_axi_HLS_MACC_PERIPH_BUS_BVALID(HLS_MACC_PERIPH_BUS_BVALID),
.s_axi_HLS_MACC_PERIPH_BUS_BREADY(HLS_MACC_PERIPH_BUS_BREADY),
.s_axi_HLS_MACC_PERIPH_BUS_BRESP(HLS_MACC_PERIPH_BUS_BRESP),
.interrupt(HLS_MACC_PERIPH_BUS_INTERRUPT),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n));
// Assignment for control signal
assign ap_clk = AESL_clock;
assign ap_rst_n = AESL_reset;
assign ap_rst_n_n = ~AESL_reset;
assign AESL_reset = rst;
assign AESL_start = start;
assign AESL_ce = ce;
assign AESL_continue = tb_continue;
assign AESL_slave_write_start_in = slave_start_status & HLS_MACC_PERIPH_BUS_write_data_finish;
assign AESL_slave_start = AESL_slave_write_start_finish;
assign AESL_done = slave_done_status & HLS_MACC_PERIPH_BUS_read_data_finish;
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
slave_start_status <= 1;
end
else begin
if (AESL_start == 1 ) begin
start_rise = 1;
end
if (start_rise == 1 && AESL_done == 1 ) begin
slave_start_status <= 1;
end
if (AESL_slave_write_start_in == 1 && AESL_done == 0) begin
slave_start_status <= 0;
start_rise = 0;
end
end
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
AESL_slave_ready <= 0;
ready_rise = 0;
end
else begin
if (AESL_ready == 1 ) begin
ready_rise = 1;
end
if (ready_rise == 1 && AESL_done_delay == 1 ) begin
AESL_slave_ready <= 1;
end
if (AESL_slave_ready == 1) begin
AESL_slave_ready <= 0;
ready_rise = 0;
end
end
end
always @ (posedge AESL_clock)
begin
if (AESL_done == 1) begin
slave_done_status <= 0;
end
else if (AESL_slave_output_done == 1 ) begin
slave_done_status <= 1;
end
end
AESL_axi_slave_HLS_MACC_PERIPH_BUS AESL_AXI_SLAVE_HLS_MACC_PERIPH_BUS(
.clk (AESL_clock),
.reset (AESL_reset),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_AWADDR (HLS_MACC_PERIPH_BUS_AWADDR),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_AWVALID (HLS_MACC_PERIPH_BUS_AWVALID),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_AWREADY (HLS_MACC_PERIPH_BUS_AWREADY),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_WVALID (HLS_MACC_PERIPH_BUS_WVALID),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_WREADY (HLS_MACC_PERIPH_BUS_WREADY),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_WDATA (HLS_MACC_PERIPH_BUS_WDATA),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_WSTRB (HLS_MACC_PERIPH_BUS_WSTRB),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_ARADDR (HLS_MACC_PERIPH_BUS_ARADDR),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_ARVALID (HLS_MACC_PERIPH_BUS_ARVALID),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_ARREADY (HLS_MACC_PERIPH_BUS_ARREADY),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_RVALID (HLS_MACC_PERIPH_BUS_RVALID),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_RREADY (HLS_MACC_PERIPH_BUS_RREADY),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_RDATA (HLS_MACC_PERIPH_BUS_RDATA),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_RRESP (HLS_MACC_PERIPH_BUS_RRESP),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_BVALID (HLS_MACC_PERIPH_BUS_BVALID),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_BREADY (HLS_MACC_PERIPH_BUS_BREADY),
.TRAN_s_axi_HLS_MACC_PERIPH_BUS_BRESP (HLS_MACC_PERIPH_BUS_BRESP),
.TRAN_HLS_MACC_PERIPH_BUS_interrupt (HLS_MACC_PERIPH_BUS_INTERRUPT),
.TRAN_HLS_MACC_PERIPH_BUS_read_data_finish(HLS_MACC_PERIPH_BUS_read_data_finish),
.TRAN_HLS_MACC_PERIPH_BUS_write_data_finish(HLS_MACC_PERIPH_BUS_write_data_finish),
.TRAN_HLS_MACC_PERIPH_BUS_ready_out (AESL_ready),
.TRAN_HLS_MACC_PERIPH_BUS_ready_in (AESL_slave_ready),
.TRAN_HLS_MACC_PERIPH_BUS_done_out (AESL_slave_output_done),
.TRAN_HLS_MACC_PERIPH_BUS_idle_out (AESL_idle),
.TRAN_HLS_MACC_PERIPH_BUS_write_start_in (AESL_slave_write_start_in),
.TRAN_HLS_MACC_PERIPH_BUS_write_start_finish (AESL_slave_write_start_finish),
.TRAN_HLS_MACC_PERIPH_BUS_transaction_done_in (AESL_done_delay),
.TRAN_HLS_MACC_PERIPH_BUS_start_in (AESL_slave_start)
);
initial begin : generate_AESL_ready_cnt_proc
AESL_ready_cnt = 0;
wait(AESL_reset === 1);
while(AESL_ready_cnt != AUTOTB_TRANSACTION_NUM) begin
while(AESL_ready !== 1) begin
@(posedge AESL_clock);
# 0.4;
end
@(negedge AESL_clock);
AESL_ready_cnt = AESL_ready_cnt + 1;
@(posedge AESL_clock);
# 0.4;
end
end
event next_trigger_ready_cnt;
initial begin : gen_ready_cnt
ready_cnt = 0;
wait (AESL_reset === 1);
forever begin
@ (posedge AESL_clock);
if (ready == 1) begin
if (ready_cnt < AUTOTB_TRANSACTION_NUM) begin
ready_cnt = ready_cnt + 1;
end
end
-> next_trigger_ready_cnt;
end
end
wire all_finish = (done_cnt == AUTOTB_TRANSACTION_NUM);
// done_cnt
always @ (posedge AESL_clock) begin
if (~AESL_reset) begin
done_cnt <= 0;
end else begin
if (AESL_done == 1) begin
if (done_cnt < AUTOTB_TRANSACTION_NUM) begin
done_cnt <= done_cnt + 1;
end
end
end
end
initial begin : finish_simulation
wait (all_finish == 1);
// last transaction is saved at negedge right after last done
@ (posedge AESL_clock);
@ (posedge AESL_clock);
@ (posedge AESL_clock);
@ (posedge AESL_clock);
$finish;
end
initial begin
AESL_clock = 0;
forever #`AUTOTB_CLOCK_PERIOD_DIV2 AESL_clock = ~AESL_clock;
end
reg end_a;
reg [31:0] size_a;
reg [31:0] size_a_backup;
reg end_b;
reg [31:0] size_b;
reg [31:0] size_b_backup;
reg end_accum_clr;
reg [31:0] size_accum_clr;
reg [31:0] size_accum_clr_backup;
reg end_accum;
reg [31:0] size_accum;
reg [31:0] size_accum_backup;
initial begin : initial_process
integer proc_rand;
rst = 0;
# 100;
repeat(3) @ (posedge AESL_clock);
rst = 1;
end
initial begin : start_process
integer proc_rand;
reg [31:0] start_cnt;
ce = 1;
start = 0;
start_cnt = 0;
wait (AESL_reset === 1);
@ (posedge AESL_clock);
#0 start = 1;
start_cnt = start_cnt + 1;
forever begin
@ (posedge AESL_clock);
if (start_cnt >= AUTOTB_TRANSACTION_NUM) begin
// keep pushing garbage in
#0 start = 1;
end
if (AESL_ready) begin
start_cnt = start_cnt + 1;
end
end
end
always @(AESL_done)
begin
tb_continue = AESL_done;
end
initial begin : ready_initial_process
ready_initial = 0;
wait (AESL_start === 1);
ready_initial = 1;
@(posedge AESL_clock);
ready_initial = 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
AESL_ready_delay = 0;
else
AESL_ready_delay = AESL_ready;
end
initial begin : ready_last_n_process
ready_last_n = 1;
wait(ready_cnt == AUTOTB_TRANSACTION_NUM)
@(posedge AESL_clock);
ready_last_n <= 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
ready_delay_last_n = 0;
else
ready_delay_last_n <= ready_last_n;
end
assign ready = (ready_initial | AESL_ready_delay);
assign ready_wire = ready_initial | AESL_ready_delay;
initial begin : done_delay_last_n_process
done_delay_last_n = 1;
while(done_cnt < AUTOTB_TRANSACTION_NUM)
@(posedge AESL_clock);
# 0.1;
done_delay_last_n = 0;
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
begin
AESL_done_delay <= 0;
AESL_done_delay2 <= 0;
end
else begin
AESL_done_delay <= AESL_done & done_delay_last_n;
AESL_done_delay2 <= AESL_done_delay;
end
end
always @(posedge AESL_clock)
begin
if(AESL_reset === 0)
interface_done = 0;
else begin
# 0.01;
if(ready === 1 && ready_cnt > 0 && ready_cnt < AUTOTB_TRANSACTION_NUM)
interface_done = 1;
else if(AESL_done_delay === 1 && done_cnt == AUTOTB_TRANSACTION_NUM)
interface_done = 1;
else
interface_done = 0;
end
end
reg dump_tvout_finish_accum;
initial begin : dump_tvout_runtime_sign_accum
integer fp;
dump_tvout_finish_accum = 0;
fp = $fopen(`AUTOTB_TVOUT_accum_out_wrapc, "w");
if (fp == 0) begin
$display("Failed to open file \"%s\"!", `AUTOTB_TVOUT_accum_out_wrapc);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
$fdisplay(fp,"[[[runtime]]]");
$fclose(fp);
wait (done_cnt == AUTOTB_TRANSACTION_NUM);
// last transaction is saved at negedge right after last done
@ (posedge AESL_clock);
@ (posedge AESL_clock);
@ (posedge AESL_clock);
fp = $fopen(`AUTOTB_TVOUT_accum_out_wrapc, "a");
if (fp == 0) begin
$display("Failed to open file \"%s\"!", `AUTOTB_TVOUT_accum_out_wrapc);
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
$fdisplay(fp,"[[[/runtime]]]");
$fclose(fp);
dump_tvout_finish_accum = 1;
end
////////////////////////////////////////////
// progress and performance
////////////////////////////////////////////
task wait_start();
while (~AESL_start) begin
@ (posedge AESL_clock);
end
endtask
reg [31:0] clk_cnt = 0;
reg AESL_ready_p1;
reg AESL_start_p1;
always @ (posedge AESL_clock) begin
clk_cnt <= clk_cnt + 1;
AESL_ready_p1 <= AESL_ready;
AESL_start_p1 <= AESL_start;
end
reg [31:0] start_timestamp [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] start_cnt;
reg [31:0] ready_timestamp [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] ap_ready_cnt;
reg [31:0] finish_timestamp [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] finish_cnt;
event report_progress;
initial begin
start_cnt = 0;
finish_cnt = 0;
ap_ready_cnt = 0;
wait (AESL_reset == 1);
wait_start();
start_timestamp[start_cnt] = clk_cnt;
start_cnt = start_cnt + 1;
if (AESL_done) begin
finish_timestamp[finish_cnt] = clk_cnt;
finish_cnt = finish_cnt + 1;
end
-> report_progress;
forever begin
@ (posedge AESL_clock);
if (start_cnt < AUTOTB_TRANSACTION_NUM) begin
if ((AESL_start && AESL_ready_p1)||(AESL_start && ~AESL_start_p1)) begin
start_timestamp[start_cnt] = clk_cnt;
start_cnt = start_cnt + 1;
end
end
if (ap_ready_cnt < AUTOTB_TRANSACTION_NUM) begin
if (AESL_start_p1 && AESL_ready_p1) begin
ready_timestamp[ap_ready_cnt] = clk_cnt;
ap_ready_cnt = ap_ready_cnt + 1;
end
end
if (finish_cnt < AUTOTB_TRANSACTION_NUM) begin
if (AESL_done) begin
finish_timestamp[finish_cnt] = clk_cnt;
finish_cnt = finish_cnt + 1;
end
end
-> report_progress;
end
end
reg [31:0] progress_timeout;
initial begin : simulation_progress
real intra_progress;
wait (AESL_reset == 1);
progress_timeout = PROGRESS_TIMEOUT;
$display("////////////////////////////////////////////////////////////////////////////////////");
$display("// Inter-Transaction Progress: Completed Transaction / Total Transaction");
$display("// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%%");
$display("//");
$display("// RTL Simulation : \"Inter-Transaction Progress\" [\"Intra-Transaction Progress\"] @ \"Simulation Time\"");
$display("////////////////////////////////////////////////////////////////////////////////////");
print_progress();
while (finish_cnt < AUTOTB_TRANSACTION_NUM) begin
@ (report_progress);
if (finish_cnt < AUTOTB_TRANSACTION_NUM) begin
if (AESL_done) begin
print_progress();
progress_timeout = PROGRESS_TIMEOUT;
end else begin
if (progress_timeout == 0) begin
print_progress();
progress_timeout = PROGRESS_TIMEOUT;
end else begin
progress_timeout = progress_timeout - 1;
end
end
end
end
print_progress();
$display("////////////////////////////////////////////////////////////////////////////////////");
calculate_performance();
end
task get_intra_progress(output real intra_progress);
begin
if (start_cnt > finish_cnt) begin
intra_progress = clk_cnt - start_timestamp[finish_cnt];
end else if(finish_cnt > 0) begin
intra_progress = LATENCY_ESTIMATION;
end else begin
intra_progress = 0;
end
intra_progress = intra_progress / LATENCY_ESTIMATION;
end
endtask
task print_progress();
real intra_progress;
begin
if (LATENCY_ESTIMATION > 0) begin
get_intra_progress(intra_progress);
$display("// RTL Simulation : %0d / %0d [%2.2f%%] @ \"%0t\"", finish_cnt, AUTOTB_TRANSACTION_NUM, intra_progress * 100, $time);
end else begin
$display("// RTL Simulation : %0d / %0d [n/a] @ \"%0t\"", finish_cnt, AUTOTB_TRANSACTION_NUM, $time);
end
end
endtask
task calculate_performance();
integer i;
integer fp;
reg [31:0] latency [0:AUTOTB_TRANSACTION_NUM - 1];
reg [31:0] latency_min;
reg [31:0] latency_max;
reg [31:0] latency_total;
reg [31:0] latency_average;
reg [31:0] interval [0:AUTOTB_TRANSACTION_NUM - 2];
reg [31:0] interval_min;
reg [31:0] interval_max;
reg [31:0] interval_total;
reg [31:0] interval_average;
begin
latency_min = -1;
latency_max = 0;
latency_total = 0;
interval_min = -1;
interval_max = 0;
interval_total = 0;
for (i = 0; i < AUTOTB_TRANSACTION_NUM; i = i + 1) begin
// calculate latency
latency[i] = finish_timestamp[i] - start_timestamp[i];
if (latency[i] > latency_max) latency_max = latency[i];
if (latency[i] < latency_min) latency_min = latency[i];
latency_total = latency_total + latency[i];
// calculate interval
if (AUTOTB_TRANSACTION_NUM == 1) begin
interval[i] = 0;
interval_max = 0;
interval_min = 0;
interval_total = 0;
end else if (i < AUTOTB_TRANSACTION_NUM - 1) begin
interval[i] = finish_timestamp[i] - start_timestamp[i]+1;
if (interval[i] > interval_max) interval_max = interval[i];
if (interval[i] < interval_min) interval_min = interval[i];
interval_total = interval_total + interval[i];
end
end
latency_average = latency_total / AUTOTB_TRANSACTION_NUM;
if (AUTOTB_TRANSACTION_NUM == 1) begin
interval_average = 0;
end else begin
interval_average = interval_total / (AUTOTB_TRANSACTION_NUM - 1);
end
fp = $fopen(`AUTOTB_LAT_RESULT_FILE, "w");
$fdisplay(fp, "$MAX_LATENCY = \"%0d\"", latency_max);
$fdisplay(fp, "$MIN_LATENCY = \"%0d\"", latency_min);
$fdisplay(fp, "$AVER_LATENCY = \"%0d\"", latency_average);
$fdisplay(fp, "$MAX_THROUGHPUT = \"%0d\"", interval_max);
$fdisplay(fp, "$MIN_THROUGHPUT = \"%0d\"", interval_min);
$fdisplay(fp, "$AVER_THROUGHPUT = \"%0d\"", interval_average);
$fclose(fp);
fp = $fopen(`AUTOTB_PER_RESULT_TRANS_FILE, "w");
$fdisplay(fp, "%20s%16s%16s", "", "latency", "interval");
if (AUTOTB_TRANSACTION_NUM == 1) begin
i = 0;
$fdisplay(fp, "transaction%8d:%16d%16d", i, latency[i], interval[i]);
end else begin
for (i = 0; i < AUTOTB_TRANSACTION_NUM; i = i + 1) begin
if (i < AUTOTB_TRANSACTION_NUM - 1) begin
$fdisplay(fp, "transaction%8d:%16d%16d", i, latency[i], interval[i]);
end else begin
$fdisplay(fp, "transaction%8d:%16d x", i, latency[i]);
end
end
end
$fclose(fp);
end
endtask
////////////////////////////////////////////
// Dependence Check
////////////////////////////////////////////
`ifndef POST_SYN
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A211OI_LP_V
`define SKY130_FD_SC_LP__A211OI_LP_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211oi with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a211oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_lp (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a211oi_lp (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a211oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A211OI_LP_V
|
module top;
reg pass = 1'b1;
real in, bin;
wire [7:0] out = in;
wire signed [34:0] big = bin;
initial begin
// $monitor(in,, out,, bin,, big);
bin = 8589934592.5; // 2**33+0.5 overflows a 32 bit long.
#1;
if (big !== 35'sd8589934593) begin
$display("Failed: multiword check, expected 8589934593, got %d", big);
pass = 1'b0;
end
if (out !== 'b0) begin
$display("Failed: initial value, expected 8'b0, got %b", out);
pass = 1'b0;
end
in = 0.499999;
bin = -25.5; // This test a different branch (small result -> big vec.).
#1;
if (big !== -26) begin
$display("Failed: small value multiword check, expected -26, got %d", out);
pass = 1'b0;
end
if (out !== 8'b0) begin
$display("Failed: rounding value (down, +), expected 8'b0, got %b", out);
pass = 1'b0;
end
in = -0.499999;
#1;
if (out !== 8'b0) begin
$display("Failed: rounding value (down, -), expected 8'b0, got %b", out);
pass = 1'b0;
end
in = 0.5;
#1;
if (out !== 8'b01) begin
$display("Failed: rounding value (up, +), expected 8'b01, got %b", out);
pass = 1'b0;
end
in = -0.5;
#1;
if (out !== 8'b11111111) begin
$display("Failed: rounding value (up, -), expected 8'b11111111, got %b", out);
pass = 1'b0;
end
in = 256.0;
#1;
if (out !== 8'b0) begin
$display("Failed: overflow expected 8'b0, got %b", out);
pass = 1'b0;
end
in = 511.0;
#1;
if (out !== 8'b11111111) begin
$display("Failed: pruning expected 8'b11111111, got %b", out);
pass = 1'b0;
end
in = 1.0/0.0;
#1;
if (out !== 8'bxxxxxxxx) begin
$display("Failed: +inf expected 8'bxxxxxxxx, got %b", out);
pass = 1'b0;
end
in = -1.0/0.0;
#1;
if (out !== 8'bxxxxxxxx) begin
$display("Failed: -inf expected 8'bxxxxxxxx, got %b", out);
pass = 1'b0;
end
in = $sqrt(-1.0);
#1;
if (out !== 8'bxxxxxxxx) begin
$display("Failed: nan expected 8'bxxxxxxxx, got %b", out);
pass = 1'b0;
end
in = 8589934720.5;
#1;
if (out !== 129) begin
$display("Failed: overflow value expected 129, got %d", out);
pass = 1'b0;
end
if (pass) $display("PASSED");
end
endmodule
|
`timescale 1 ns / 1 ps
module sensor_interface_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 5
)
(
// Users to add ports here
// Register file signals
input wire clk,
input wire mm_en,
input wire mm_wr,
output reg [C_S_AXI_ADDR_WIDTH-1:0] mm_addr,
output reg [C_S_AXI_DATA_WIDTH-1:0] mm_wdata,
input wire [C_S_AXI_DATA_WIDTH-1:0] mm_rdata,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam OPT_MEM_ADDR_BITS = 1;
// Register file signals
reg [C_S_AXI_ADDR_WIDTH-1:0] reg_file [C_S_AXI_DATA_WIDTH-1:0];
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
reg aw_en;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
aw_en <= 1'b1;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
aw_en <= 1'b0;
end
else if (S_AXI_BREADY && axi_bvalid)
begin
aw_en <= 1'b1;
axi_awready <= 1'b0;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK or negedge S_AXI_ARESETN )
begin
if (S_AXI_ARESETN == 1'b1) begin
if (slv_reg_wren)
begin
/*
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
reg_file[axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB]][(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
*/
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
mm_addr <= axi_araddr;
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= {mm_rdata[7:0], mm_rdata[15:8], mm_rdata[23:16], mm_rdata[31:24]}; // register read data
end
end
end
// Add user logic here
// User logic ends
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Implements a fixed-point parameterized pipelined square root
// operation on an unsigned input of any bit length. The number of
// stages in the pipeline is equal to the number of output bits in the
// computation. This pipelien sustains a throughput of one computation
// per clock cycle.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module sqrt_pipelined
(
input clk, // clock
input reset_n, // asynchronous reset
input start, // optional start signal
input [INPUT_BITS-1:0] radicand, // unsigned radicand
output reg data_valid, // optional data valid signal
output reg [OUTPUT_BITS-1:0] root // unsigned root
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
INPUT_BITS = 16; // number of input bits (any integer)
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2; // number of output bits
reg [OUTPUT_BITS-1:0] start_gen; // valid data propagation
reg [OUTPUT_BITS*INPUT_BITS-1:0] root_gen; // root values
reg [OUTPUT_BITS*INPUT_BITS-1:0] radicand_gen; // radicand values
wire [OUTPUT_BITS*INPUT_BITS-1:0] mask_gen; // mask values
// This is the first stage of the pipeline.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
start_gen[0] <= 0;
radicand_gen[INPUT_BITS-1:0] <= 0;
root_gen[INPUT_BITS-1:0] <= 0;
end
else begin
start_gen[0] <= start;
if ( mask_gen[INPUT_BITS-1:0] <= radicand ) begin
radicand_gen[INPUT_BITS-1:0] <= radicand - mask_gen[INPUT_BITS-1:0];
root_gen[INPUT_BITS-1:0] <= mask_gen[INPUT_BITS-1:0];
end
else begin
radicand_gen[INPUT_BITS-1:0] <= radicand;
root_gen[INPUT_BITS-1:0] <= 0;
end
end
end
// Main generate loop to create the masks and pipeline stages.
generate
genvar i;
// Generate all the mask values. These are built up in the
// following fashion:
// LAST MASK: 0x00...001
// 0x00...004 Increasing # OUTPUT_BITS
// 0x00...010 |
// 0x00...040 v
// ...
// FIRST MASK: 0x10...000 # masks == # OUTPUT_BITS
//
// Note that the first mask used can either be of the 0x1... or
// 0x4... variety. This is purely determined by the number of
// computation stages. However, the last mask used will always be
// 0x1 and the second to last mask used will always be 0x4.
for (i = 0; i < OUTPUT_BITS; i = i + 1) begin: mask_4
if (i % 2) // i is odd, this is a 4 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 4 << 4 * (i/2);
else // i is even, this is a 1 mask
assign mask_gen[INPUT_BITS*(OUTPUT_BITS-i)-1:INPUT_BITS*(OUTPUT_BITS-i-1)] = 1 << 4 * (i/2);
end
// Generate all the pipeline stages to compute the square root of
// the input radicand stream. The general approach is to compare
// the current values of the root plus the mask to the
// radicand. If root/mask sum is greater than the radicand,
// subtract the mask and the root from the radicand and store the
// radicand for the next stage. Additionally, the root is
// increased by the value of the mask and stored for the next
// stage. If this test fails, then the radicand and the root
// retain their value through to the next stage. The one weird
// thing is that the mask indices appear to be incremented by one
// additional position. This is not the case, however, because the
// first mask is used in the first stage (always block after the
// generate statement).
for (i = 0; i < OUTPUT_BITS - 1; i = i + 1) begin: pipeline
always @ (posedge clk or negedge reset_n) begin : pipeline_stage
if (!reset_n) begin
start_gen[i+1] <= 0;
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= 0;
end
else begin
start_gen[i+1] <= start_gen[i];
if ((root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)]) <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i]) begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] -
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] -
root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= (root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1) +
mask_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)];
end
else begin
radicand_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= radicand_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i];
root_gen[INPUT_BITS*(i+2)-1:INPUT_BITS*(i+1)] <= root_gen[INPUT_BITS*(i+1)-1:INPUT_BITS*i] >> 1;
end
end
end
end
endgenerate
// This is the final stage which just implements a rounding
// operation. This stage could be tacked on as a combinational logic
// stage, but who cares about latency, anyway? This is NOT a true
// rounding stage. In order to add convergent rounding, you need to
// increase the input bit width by 2 (increase the number of
// pipeline stages by 1) and implement rounding in the module that
// instantiates this one.
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
data_valid <= 0;
root <= 0;
end
else begin
data_valid <= start_gen[OUTPUT_BITS-1];
if (root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] > root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS])
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS] + 1;
else
root <= root_gen[OUTPUT_BITS*INPUT_BITS-1:OUTPUT_BITS*INPUT_BITS-INPUT_BITS];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A21BOI_SYMBOL_V
`define SKY130_FD_SC_HS__A21BOI_SYMBOL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a21boi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A21BOI_SYMBOL_V
|
// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axisc_downsizer
// Convert from SI data width < MI datawidth.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axis_dwidth_converter_v1_1_axisc_upsizer #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex6",
parameter integer C_S_AXIS_TDATA_WIDTH = 32,
parameter integer C_M_AXIS_TDATA_WIDTH = 96,
parameter integer C_AXIS_TID_WIDTH = 1,
parameter integer C_AXIS_TDEST_WIDTH = 1,
parameter integer C_S_AXIS_TUSER_WIDTH = 1,
parameter integer C_M_AXIS_TUSER_WIDTH = 3,
parameter [31:0] C_AXIS_SIGNAL_SET = 32'hFF ,
// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
// [0] => TREADY present
// [1] => TDATA present
// [2] => TSTRB present, TDATA must be present
// [3] => TKEEP present, TDATA must be present
// [4] => TLAST present
// [5] => TID present
// [6] => TDEST present
// [7] => TUSER present
parameter integer C_RATIO = 3 // Should always be 1:C_RATIO (upsizer)
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// System Signals
input wire ACLK,
input wire ARESET,
input wire ACLKEN,
// Slave side
input wire S_AXIS_TVALID,
output wire S_AXIS_TREADY,
input wire [C_S_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA,
input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TSTRB,
input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TKEEP,
input wire S_AXIS_TLAST,
input wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID,
input wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST,
input wire [C_S_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER,
// Master side
output wire M_AXIS_TVALID,
input wire M_AXIS_TREADY,
output wire [C_M_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA,
output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TSTRB,
output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TKEEP,
output wire M_AXIS_TLAST,
output wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID,
output wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST,
output wire [C_M_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axis_infrastructure_v1_1_axis_infrastructure.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_READY_EXIST = C_AXIS_SIGNAL_SET[0];
localparam P_DATA_EXIST = C_AXIS_SIGNAL_SET[1];
localparam P_STRB_EXIST = C_AXIS_SIGNAL_SET[2];
localparam P_KEEP_EXIST = C_AXIS_SIGNAL_SET[3];
localparam P_LAST_EXIST = C_AXIS_SIGNAL_SET[4];
localparam P_ID_EXIST = C_AXIS_SIGNAL_SET[5];
localparam P_DEST_EXIST = C_AXIS_SIGNAL_SET[6];
localparam P_USER_EXIST = C_AXIS_SIGNAL_SET[7];
localparam P_S_AXIS_TSTRB_WIDTH = C_S_AXIS_TDATA_WIDTH/8;
localparam P_M_AXIS_TSTRB_WIDTH = C_M_AXIS_TDATA_WIDTH/8;
// State Machine possible states. Bits 1:0 used to encode output signals.
// /--- M_AXIS_TVALID state
// |/-- S_AXIS_TREADY state
localparam SM_RESET = 3'b000; // De-assert Ready during reset
localparam SM_IDLE = 3'b001; // R0 reg is empty
localparam SM_ACTIVE = 3'b101; // R0 reg is active
localparam SM_END = 3'b011; // R0 reg is empty and ACC reg is active
localparam SM_END_TO_ACTIVE = 3'b010; // R0/ACC reg are both active.
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [2:0] state;
reg [C_M_AXIS_TDATA_WIDTH-1:0] acc_data;
reg [P_M_AXIS_TSTRB_WIDTH-1:0] acc_strb;
reg [P_M_AXIS_TSTRB_WIDTH-1:0] acc_keep;
reg acc_last;
reg [C_AXIS_TID_WIDTH-1:0] acc_id;
reg [C_AXIS_TDEST_WIDTH-1:0] acc_dest;
reg [C_M_AXIS_TUSER_WIDTH-1:0] acc_user;
wire [C_RATIO-1:0] acc_reg_en;
reg [C_RATIO-1:0] r0_reg_sel;
wire next_xfer_is_end;
reg [C_S_AXIS_TDATA_WIDTH-1:0] r0_data;
reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_strb;
reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_keep;
reg r0_last;
reg [C_AXIS_TID_WIDTH-1:0] r0_id;
reg [C_AXIS_TDEST_WIDTH-1:0] r0_dest;
reg [C_S_AXIS_TUSER_WIDTH-1:0] r0_user;
wire id_match;
wire dest_match;
wire id_dest_mismatch;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// S Ready/M Valid outputs are encoded in the current state.
assign S_AXIS_TREADY = state[0];
assign M_AXIS_TVALID = state[1];
// State machine controls M_AXIS_TVALID and S_AXIS_TREADY, and loading
always @(posedge ACLK) begin
if (ARESET) begin
state <= SM_RESET;
end else if (ACLKEN) begin
case (state)
SM_RESET: begin
state <= SM_IDLE;
end
SM_IDLE: begin
if (S_AXIS_TVALID & id_dest_mismatch & ~r0_reg_sel[0]) begin
state <= SM_END_TO_ACTIVE;
end
else if (S_AXIS_TVALID & next_xfer_is_end) begin
state <= SM_END;
end
else if (S_AXIS_TVALID) begin
state <= SM_ACTIVE;
end
else begin
state <= SM_IDLE;
end
end
SM_ACTIVE: begin
if (S_AXIS_TVALID & (id_dest_mismatch | r0_last)) begin
state <= SM_END_TO_ACTIVE;
end
else if ((~S_AXIS_TVALID & r0_last) | (S_AXIS_TVALID & next_xfer_is_end)) begin
state <= SM_END;
end
else if (S_AXIS_TVALID & ~next_xfer_is_end) begin
state <= SM_ACTIVE;
end
else begin
state <= SM_IDLE;
end
end
SM_END: begin
if (M_AXIS_TREADY & S_AXIS_TVALID) begin
state <= SM_ACTIVE;
end
else if ( ~M_AXIS_TREADY & S_AXIS_TVALID) begin
state <= SM_END_TO_ACTIVE;
end
else if ( M_AXIS_TREADY & ~S_AXIS_TVALID) begin
state <= SM_IDLE;
end
else begin
state <= SM_END;
end
end
SM_END_TO_ACTIVE: begin
if (M_AXIS_TREADY) begin
state <= SM_ACTIVE;
end
else begin
state <= SM_END_TO_ACTIVE;
end
end
default: begin
state <= SM_IDLE;
end
endcase // case (state)
end
end
assign M_AXIS_TDATA = acc_data;
assign M_AXIS_TSTRB = acc_strb;
assign M_AXIS_TKEEP = acc_keep;
assign M_AXIS_TUSER = acc_user;
generate
genvar i;
// DATA/USER/STRB/KEEP accumulators
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_data[0*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= acc_reg_en[0] ? r0_data
: acc_data[0*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
acc_user[0*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= acc_reg_en[0] ? r0_user
: acc_user[0*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
acc_strb[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? r0_strb
: acc_strb[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
acc_keep[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? r0_keep
: acc_keep[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
end
end
for (i = 1; i < C_RATIO-1; i = i + 1) begin : gen_data_accumulator
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_data[i*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= acc_reg_en[i] ? r0_data
: acc_data[i*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
acc_user[i*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= acc_reg_en[i] ? r0_user
: acc_user[i*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
acc_strb[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? {P_S_AXIS_TSTRB_WIDTH{1'b0}}
: acc_reg_en[i] ? r0_strb : acc_strb[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
acc_keep[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? {P_S_AXIS_TSTRB_WIDTH{1'b0}}
: acc_reg_en[i] ? r0_keep : acc_keep[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
end
end
end
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_data[(C_RATIO-1)*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= (state == SM_IDLE) | (state == SM_ACTIVE)
? S_AXIS_TDATA : acc_data[(C_RATIO-1)*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
acc_user[(C_RATIO-1)*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= (state == SM_IDLE) | (state == SM_ACTIVE)
? S_AXIS_TUSER : acc_user[(C_RATIO-1)*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
acc_strb[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= (acc_reg_en[0] && C_RATIO > 2) | (state == SM_ACTIVE & r0_last) | (id_dest_mismatch & (state == SM_ACTIVE | state == SM_IDLE))
? {P_S_AXIS_TSTRB_WIDTH{1'b0}} : (state == SM_IDLE) | (state == SM_ACTIVE)
? S_AXIS_TSTRB : acc_strb[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
acc_keep[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= (acc_reg_en[0] && C_RATIO > 2) | (state == SM_ACTIVE & r0_last) | (id_dest_mismatch & (state == SM_ACTIVE| state == SM_IDLE))
? {P_S_AXIS_TSTRB_WIDTH{1'b0}} : (state == SM_IDLE) | (state == SM_ACTIVE)
? S_AXIS_TKEEP : acc_keep[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
end
end
endgenerate
assign acc_reg_en = (state == SM_ACTIVE) ? r0_reg_sel : {C_RATIO{1'b0}};
// Accumulator selector (1 hot left barrel shifter)
always @(posedge ACLK) begin
if (ARESET) begin
r0_reg_sel[0] <= 1'b1;
r0_reg_sel[1+:C_RATIO-1] <= {C_RATIO{1'b0}};
end else if (ACLKEN) begin
r0_reg_sel[0] <= M_AXIS_TVALID & M_AXIS_TREADY ? 1'b1
: (state == SM_ACTIVE) ? 1'b0 : r0_reg_sel[0];
r0_reg_sel[1+:C_RATIO-1] <= M_AXIS_TVALID & M_AXIS_TREADY ? {C_RATIO-1{1'b0}}
: (state == SM_ACTIVE) ? r0_reg_sel[0+:C_RATIO-1] : r0_reg_sel[1+:C_RATIO-1];
end
end
assign next_xfer_is_end = (r0_reg_sel[C_RATIO-2] && (state == SM_ACTIVE)) | r0_reg_sel[C_RATIO-1];
always @(posedge ACLK) begin
if (ACLKEN) begin
r0_data <= S_AXIS_TREADY ? S_AXIS_TDATA : r0_data;
r0_strb <= S_AXIS_TREADY ? S_AXIS_TSTRB : r0_strb;
r0_keep <= S_AXIS_TREADY ? S_AXIS_TKEEP : r0_keep;
r0_last <= (!P_LAST_EXIST) ? 1'b0 : S_AXIS_TREADY ? S_AXIS_TLAST : r0_last;
r0_id <= (S_AXIS_TREADY & S_AXIS_TVALID) ? S_AXIS_TID : r0_id;
r0_dest <= (S_AXIS_TREADY & S_AXIS_TVALID) ? S_AXIS_TDEST : r0_dest;
r0_user <= S_AXIS_TREADY ? S_AXIS_TUSER : r0_user;
end
end
assign M_AXIS_TLAST = acc_last;
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_last <= (state == SM_END | state == SM_END_TO_ACTIVE) ? acc_last :
(state == SM_ACTIVE & r0_last ) ? 1'b1 :
(id_dest_mismatch & (state == SM_IDLE)) ? 1'b0 :
(id_dest_mismatch & (state == SM_ACTIVE)) ? r0_last :
S_AXIS_TLAST;
end
end
assign M_AXIS_TID = acc_id;
assign M_AXIS_TDEST = acc_dest;
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_id <= acc_reg_en[0] ? r0_id : acc_id;
acc_dest <= acc_reg_en[0] ? r0_dest : acc_dest;
end
end
assign id_match = P_ID_EXIST ? (S_AXIS_TID == r0_id) : 1'b1;
assign dest_match = P_DEST_EXIST ? (S_AXIS_TDEST == r0_dest) : 1'b1;
assign id_dest_mismatch = (~id_match | ~dest_match) ? 1'b1 : 1'b0;
endmodule // axisc_upsizer
`default_nettype wire
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_jesd_regmap (
// control interface
up_lanesync_enb,
up_scr_enb,
up_sysref_enb,
up_err_disb,
up_frmcnt,
up_bytecnt,
up_bufdelay,
up_test_mode,
up_gtx_rstn,
up_jesd_rstn,
up_es_mode,
up_es_start,
up_prescale,
up_voffset_step,
up_voffset_max,
up_voffset_min,
up_hoffset_max,
up_hoffset_min,
up_hoffset_step,
up_startaddr,
up_hsize,
up_hmax,
up_hmin,
// eye scan ports
es_drp_en,
es_drp_we,
es_drp_addr,
es_drp_wdata,
es_drp_rdata,
es_drp_ready,
es_state,
// master bus interface
mb_ovf,
mb_unf,
mb_status,
mb_state,
// drp ports
up_drp_en,
up_drp_we,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
// jesd ports
jesd_status,
jesd_bufcnt,
jesd_init_data0,
jesd_init_data1,
jesd_init_data2,
jesd_init_data3,
jesd_test_mfcnt,
jesd_test_ilacnt,
jesd_test_errcnt,
// bus interface
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack);
parameter VERSION = 32'h00010061;
parameter NUM_OF_LANES = 4;
parameter NC = NUM_OF_LANES - 1;
parameter NB = (NUM_OF_LANES* 8) - 1;
parameter NW = (NUM_OF_LANES*16) - 1;
parameter ND = (NUM_OF_LANES*32) - 1;
// control interface
output up_lanesync_enb;
output up_scr_enb;
output up_sysref_enb;
output up_err_disb;
output [ 4:0] up_frmcnt;
output [ 7:0] up_bytecnt;
output [12:0] up_bufdelay;
output [ 1:0] up_test_mode;
output up_gtx_rstn;
output up_jesd_rstn;
output up_es_mode;
output up_es_start;
output [ 4:0] up_prescale;
output [ 7:0] up_voffset_step;
output [ 7:0] up_voffset_max;
output [ 7:0] up_voffset_min;
output [11:0] up_hoffset_max;
output [11:0] up_hoffset_min;
output [11:0] up_hoffset_step;
output [31:0] up_startaddr;
output [15:0] up_hsize;
output [15:0] up_hmax;
output [15:0] up_hmin;
// eye scan ports
input es_drp_en;
input es_drp_we;
input [ 8:0] es_drp_addr;
input [15:0] es_drp_wdata;
output [15:0] es_drp_rdata;
output es_drp_ready;
input es_state;
// master bus interface
input mb_ovf;
input mb_unf;
input [ 1:0] mb_status;
input mb_state;
// drp ports
output [NC:0] up_drp_en;
output up_drp_we;
output [ 8:0] up_drp_addr;
output [15:0] up_drp_wdata;
input [NW:0] up_drp_rdata;
input [NC:0] up_drp_ready;
// jesd ports
input jesd_status;
input [NB:0] jesd_bufcnt;
input [ND:0] jesd_init_data0;
input [ND:0] jesd_init_data1;
input [ND:0] jesd_init_data2;
input [ND:0] jesd_init_data3;
input [ND:0] jesd_test_mfcnt;
input [ND:0] jesd_test_ilacnt;
input [ND:0] jesd_test_errcnt;
// bus interface
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal registers
reg up_lanesync_enb = 'd0;
reg up_scr_enb = 'd0;
reg up_sysref_enb = 'd0;
reg up_err_disb = 'd0;
reg [ 4:0] up_frmcnt = 'd0;
reg [ 7:0] up_bytecnt = 'd0;
reg [12:0] up_bufdelay = 'd0;
reg [ 1:0] up_test_mode = 'd0;
reg up_gtx_rstn = 'd0;
reg up_jesd_rstn = 'd0;
reg [ 7:0] up_lanesel = 'd0;
reg up_es_mode = 'd0;
reg up_es_start = 'd0;
reg [ 4:0] up_prescale = 'd0;
reg [ 7:0] up_voffset_step = 'd0;
reg [ 7:0] up_voffset_max = 'd0;
reg [ 7:0] up_voffset_min = 'd0;
reg [11:0] up_hoffset_max = 'd0;
reg [11:0] up_hoffset_min = 'd0;
reg [11:0] up_hoffset_step = 'd0;
reg [31:0] up_startaddr = 'd0;
reg [15:0] up_hsize = 'd0;
reg [15:0] up_hmax = 'd0;
reg [15:0] up_hmin = 'd0;
reg up_mb_ovf_hold = 'd0;
reg up_mb_unf_hold = 'd0;
reg [ 1:0] up_mb_status_hold = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel_2d = 'd0;
reg up_ack = 'd0;
reg [NC:0] up_drp_en = 'd0;
reg up_drp_we = 'd0;
reg [ 8:0] up_drp_addr = 'd0;
reg [15:0] up_drp_wdata = 'd0;
reg [15:0] es_drp_rdata = 'd0;
reg es_drp_ready = 'd0;
reg up_jesd_status_m1 = 'd0;
reg up_jesd_status = 'd0;
reg [ 7:0] up_jesd_bufcnt = 'd0;
reg [31:0] up_jesd_init_data0 = 'd0;
reg [31:0] up_jesd_init_data1 = 'd0;
reg [31:0] up_jesd_init_data2 = 'd0;
reg [31:0] up_jesd_init_data3 = 'd0;
reg [31:0] up_jesd_test_mfcnt = 'd0;
reg [31:0] up_jesd_test_ilacnt = 'd0;
reg [31:0] up_jesd_test_errcnt = 'd0;
// internal signals
wire up_wr_s;
wire up_ack_s;
wire [NC:0] up_drp_en_s;
wire [15:0] up_drp_rdata_s[0:NC];
wire [ 7:0] jesd_bufcnt_s[0:NC];
wire [31:0] jesd_init_data0_s[0:NC];
wire [31:0] jesd_init_data1_s[0:NC];
wire [31:0] jesd_init_data2_s[0:NC];
wire [31:0] jesd_init_data3_s[0:NC];
wire [31:0] jesd_test_mfcnt_s[0:NC];
wire [31:0] jesd_test_ilacnt_s[0:NC];
wire [31:0] jesd_test_errcnt_s[0:NC];
genvar n;
// processor control signals
assign up_wr_s = up_sel & ~up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_lanesync_enb <= 'd0;
up_scr_enb <= 'd0;
up_sysref_enb <= 'd0;
up_err_disb <= 'd0;
up_frmcnt <= 'd0;
up_bytecnt <= 'd0;
up_bufdelay <= 'd0;
up_test_mode <= 'd0;
up_gtx_rstn <= 'd0;
up_jesd_rstn <= 'd0;
up_lanesel <= 'd0;
up_es_mode <= 'd0;
up_es_start <= 'd0;
up_prescale <= 'd0;
up_voffset_step <= 'd0;
up_voffset_max <= 'd0;
up_voffset_min <= 'd0;
up_hoffset_max <= 'd0;
up_hoffset_min <= 'd0;
up_hoffset_step <= 'd0;
up_startaddr <= 'd0;
up_hsize <= 'd0;
up_hmin <= 'd0;
up_hmax <= 'd0;
up_mb_ovf_hold <= 'd0;
up_mb_unf_hold <= 'd0;
up_mb_status_hold <= 'd0;
end else begin
if ((up_addr == 5'h01) && (up_wr_s == 1'b1)) begin
up_lanesync_enb <= up_wdata[3];
up_scr_enb <= up_wdata[2];
up_sysref_enb <= up_wdata[1];
up_err_disb <= up_wdata[0];
end
if ((up_addr == 5'h03) && (up_wr_s == 1'b1)) begin
up_frmcnt <= up_wdata[12:8];
up_bytecnt <= up_wdata[7:0];
end
if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_bufdelay <= up_wdata[12:0];
end
if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_gtx_rstn <= up_wdata[5];
up_jesd_rstn <= up_wdata[4];
up_test_mode <= 2'd0;
up_lanesel <= {4'd0, up_wdata[3:0]};
end
if ((up_addr == 5'h10) && (up_wr_s == 1'b1)) begin
up_es_mode <= up_wdata[1];
up_es_start <= up_wdata[0];
end
if ((up_addr == 5'h11) && (up_wr_s == 1'b1)) begin
up_prescale <= up_wdata[4:0];
end
if ((up_addr == 5'h12) && (up_wr_s == 1'b1)) begin
up_voffset_step <= up_wdata[23:16];
up_voffset_max <= up_wdata[15:8];
up_voffset_min <= up_wdata[7:0];
end
if ((up_addr == 5'h13) && (up_wr_s == 1'b1)) begin
up_hoffset_max <= up_wdata[27:16];
up_hoffset_min <= up_wdata[11:0];
end
if ((up_addr == 5'h14) && (up_wr_s == 1'b1)) begin
up_hoffset_step <= up_wdata[11:0];
end
if ((up_addr == 5'h15) && (up_wr_s == 1'b1)) begin
up_startaddr <= up_wdata;
end
if ((up_addr == 5'h16) && (up_wr_s == 1'b1)) begin
up_hsize <= up_wdata[15:0];
end
if ((up_addr == 5'h17) && (up_wr_s == 1'b1)) begin
up_hmax <= up_wdata[31:16];
up_hmin <= up_wdata[15:0];
end
if ((up_addr == 5'h18) && (up_wr_s == 1'b1)) begin
up_mb_ovf_hold <= up_mb_ovf_hold & ~up_wdata[5];
up_mb_unf_hold <= up_mb_unf_hold & ~up_wdata[4];
up_mb_status_hold[1] <= up_mb_status_hold[1] & ~up_wdata[3];
up_mb_status_hold[0] <= up_mb_status_hold[0] & ~up_wdata[2];
end else begin
up_mb_ovf_hold <= up_mb_ovf_hold | mb_ovf;
up_mb_unf_hold <= up_mb_unf_hold | mb_unf;
up_mb_status_hold[1] <= up_mb_status_hold[1] | mb_status[1];
up_mb_status_hold[0] <= up_mb_status_hold[0] | mb_status[0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h00: up_rdata <= VERSION;
5'h01: up_rdata <= {28'd0, up_lanesync_enb, up_scr_enb, up_sysref_enb, up_err_disb};
5'h02: up_rdata <= {31'd0, up_jesd_status};
5'h03: up_rdata <= {19'd0, up_frmcnt, up_bytecnt};
5'h04: up_rdata <= {19'd0, up_bufdelay};
5'h05: up_rdata <= {26'd0, up_gtx_rstn, up_jesd_rstn, up_lanesel[3:0]};
5'h06: up_rdata <= up_jesd_bufcnt;
5'h07: up_rdata <= up_jesd_init_data0;
5'h08: up_rdata <= up_jesd_init_data1;
5'h09: up_rdata <= up_jesd_init_data2;
5'h0a: up_rdata <= up_jesd_init_data3;
5'h0b: up_rdata <= up_jesd_test_mfcnt;
5'h0c: up_rdata <= up_jesd_test_ilacnt;
5'h0d: up_rdata <= up_jesd_test_errcnt;
5'h10: up_rdata <= {30'd0, up_es_mode, up_es_start};
5'h11: up_rdata <= {27'd0, up_prescale};
5'h12: up_rdata <= {8'd0, up_voffset_step, up_voffset_max, up_voffset_min};
5'h13: up_rdata <= {4'd0, up_hoffset_max, 4'd0, up_hoffset_min};
5'h14: up_rdata <= {20'd0, up_hoffset_step};
5'h15: up_rdata <= up_startaddr;
5'h16: up_rdata <= {16'd0, up_hsize};
5'h17: up_rdata <= {up_hmax, up_hmin};
5'h18: up_rdata <= {26'd0, up_mb_ovf_hold, up_mb_unf_hold, up_mb_status_hold,
mb_state, es_state};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
// drp mux based on lane select
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_drp_en <= 'd0;
up_drp_we <= 'd0;
up_drp_addr <= 'd0;
up_drp_wdata <= 'd0;
es_drp_rdata <= 'd0;
es_drp_ready <= 'd0;
end else begin
up_drp_en <= up_drp_en_s;
up_drp_we <= es_drp_we;
up_drp_addr <= es_drp_addr;
up_drp_wdata <= es_drp_wdata;
es_drp_rdata <= up_drp_rdata_s[up_lanesel];
es_drp_ready <= up_drp_ready[up_lanesel];
end
end
// multiplexed gtx status/control signals per lane
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_jesd_status_m1 <= 'd0;
up_jesd_status <= 'd0;
up_jesd_bufcnt <= 'd0;
up_jesd_init_data0 <= 'd0;
up_jesd_init_data1 <= 'd0;
up_jesd_init_data2 <= 'd0;
up_jesd_init_data3 <= 'd0;
up_jesd_test_mfcnt <= 'd0;
up_jesd_test_ilacnt <= 'd0;
up_jesd_test_errcnt <= 'd0;
end else begin
up_jesd_status_m1 <= jesd_status;
up_jesd_status <= up_jesd_status_m1;
up_jesd_bufcnt <= jesd_bufcnt_s[up_lanesel];
up_jesd_init_data0 <= jesd_init_data0_s[up_lanesel];
up_jesd_init_data1 <= jesd_init_data1_s[up_lanesel];
up_jesd_init_data2 <= jesd_init_data2_s[up_lanesel];
up_jesd_init_data3 <= jesd_init_data3_s[up_lanesel];
up_jesd_test_mfcnt <= jesd_test_mfcnt_s[up_lanesel];
up_jesd_test_ilacnt <= jesd_test_ilacnt_s[up_lanesel];
up_jesd_test_errcnt <= jesd_test_errcnt_s[up_lanesel];
end
end
// convert 1d signals to 2d signals per lane
generate
for (n = 0; n < NUM_OF_LANES; n = n + 1) begin : g_lanes
assign up_drp_en_s[n] = (up_lanesel == n) ? es_drp_en : 1'b0;
assign up_drp_rdata_s[n] = up_drp_rdata[((n*16)+15):(n*16)];
assign jesd_bufcnt_s[n] = jesd_bufcnt[((n*8)+7):(n*8)];
assign jesd_init_data0_s[n] = jesd_init_data0[((n*32)+31):(n*32)];
assign jesd_init_data1_s[n] = jesd_init_data1[((n*32)+31):(n*32)];
assign jesd_init_data2_s[n] = jesd_init_data2[((n*32)+31):(n*32)];
assign jesd_init_data3_s[n] = jesd_init_data3[((n*32)+31):(n*32)];
assign jesd_test_mfcnt_s[n] = jesd_test_mfcnt[((n*32)+31):(n*32)];
assign jesd_test_ilacnt_s[n] = jesd_test_ilacnt[((n*32)+31):(n*32)];
assign jesd_test_errcnt_s[n] = jesd_test_errcnt[((n*32)+31):(n*32)];
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*WARNING: ONLY SAME EDGE SUPPORTED FOR NOW*/
//D1,D2 sampled on rising edge of C
module ODDR (/*AUTOARG*/
// Outputs
Q,
// Inputs
C, CE, D1, D2, R, S
);
parameter DDR_CLK_EDGE=0; //clock recovery mode
parameter INIT=0; //Q init value
parameter SRTYPE=0;//"SYNC", "ASYNC"
input C; // Clock input
input CE; // Clock enable input
input D1; // Data input1
input D2; // Data input2
input R; // Reset (depends on SRTYPE)
input S; // Active high asynchronous pin
output Q; // Data Output that connects to the IOB pad
reg Q1,Q2;
reg Q2_reg;
//Generate different logic based on parameters
//Only doing same edge and async reset for now
always @ (posedge C or posedge R)
if (R)
Q1 <= 1'b0;
else
Q1 <= D1;
always @ (posedge C or posedge R)
if (R)
Q2 <= 1'b0;
else
Q2 <= D2;
always @ (negedge C or posedge R)
if (R)
Q2_reg <= 1'b0;
else
Q2_reg <= Q2;
assign Q = C ? Q1 : Q2_reg;
endmodule // ODDR
|
`timescale 1 ns / 1 ps
module address_remap_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S_AXI_in
parameter integer C_S_AXI_in_ID_WIDTH = 1,
parameter integer C_S_AXI_in_DATA_WIDTH = 32,
parameter integer C_S_AXI_in_ADDR_WIDTH = 6,
parameter integer C_S_AXI_in_AWUSER_WIDTH = 0,
parameter integer C_S_AXI_in_ARUSER_WIDTH = 0,
parameter integer C_S_AXI_in_WUSER_WIDTH = 0,
parameter integer C_S_AXI_in_RUSER_WIDTH = 0,
parameter integer C_S_AXI_in_BUSER_WIDTH = 0,
// Parameters of Axi Master Bus Interface M_AXI_out
parameter C_M_AXI_out_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
parameter integer C_M_AXI_out_BURST_LEN = 16,
parameter integer C_M_AXI_out_ID_WIDTH = 1,
parameter integer C_M_AXI_out_ADDR_WIDTH = 32,
parameter integer C_M_AXI_out_DATA_WIDTH = 32,
parameter integer C_M_AXI_out_AWUSER_WIDTH = 0,
parameter integer C_M_AXI_out_ARUSER_WIDTH = 0,
parameter integer C_M_AXI_out_WUSER_WIDTH = 0,
parameter integer C_M_AXI_out_RUSER_WIDTH = 0,
parameter integer C_M_AXI_out_BUSER_WIDTH = 0
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S_AXI_in
input wire s_axi_in_aclk,
input wire s_axi_in_aresetn,
input wire [C_S_AXI_in_ID_WIDTH-1 : 0] s_axi_in_awid,
input wire [C_S_AXI_in_ADDR_WIDTH-1 : 0] s_axi_in_awaddr,
input wire [7 : 0] s_axi_in_awlen,
input wire [2 : 0] s_axi_in_awsize,
input wire [1 : 0] s_axi_in_awburst,
input wire s_axi_in_awlock,
input wire [3 : 0] s_axi_in_awcache,
input wire [2 : 0] s_axi_in_awprot,
input wire [3 : 0] s_axi_in_awqos,
input wire [3 : 0] s_axi_in_awregion,
input wire [C_S_AXI_in_AWUSER_WIDTH-1 : 0] s_axi_in_awuser,
input wire s_axi_in_awvalid,
output wire s_axi_in_awready,
input wire [C_S_AXI_in_DATA_WIDTH-1 : 0] s_axi_in_wdata,
input wire [(C_S_AXI_in_DATA_WIDTH/8)-1 : 0] s_axi_in_wstrb,
input wire s_axi_in_wlast,
input wire [C_S_AXI_in_WUSER_WIDTH-1 : 0] s_axi_in_wuser,
input wire s_axi_in_wvalid,
output wire s_axi_in_wready,
output wire [C_S_AXI_in_ID_WIDTH-1 : 0] s_axi_in_bid,
output wire [1 : 0] s_axi_in_bresp,
output wire [C_S_AXI_in_BUSER_WIDTH-1 : 0] s_axi_in_buser,
output wire s_axi_in_bvalid,
input wire s_axi_in_bready,
input wire [C_S_AXI_in_ID_WIDTH-1 : 0] s_axi_in_arid,
input wire [C_S_AXI_in_ADDR_WIDTH-1 : 0] s_axi_in_araddr,
input wire [7 : 0] s_axi_in_arlen,
input wire [2 : 0] s_axi_in_arsize,
input wire [1 : 0] s_axi_in_arburst,
input wire s_axi_in_arlock,
input wire [3 : 0] s_axi_in_arcache,
input wire [2 : 0] s_axi_in_arprot,
input wire [3 : 0] s_axi_in_arqos,
input wire [3 : 0] s_axi_in_arregion,
input wire [C_S_AXI_in_ARUSER_WIDTH-1 : 0] s_axi_in_aruser,
input wire s_axi_in_arvalid,
output wire s_axi_in_arready,
output wire [C_S_AXI_in_ID_WIDTH-1 : 0] s_axi_in_rid,
output wire [C_S_AXI_in_DATA_WIDTH-1 : 0] s_axi_in_rdata,
output wire [1 : 0] s_axi_in_rresp,
output wire s_axi_in_rlast,
output wire [C_S_AXI_in_RUSER_WIDTH-1 : 0] s_axi_in_ruser,
output wire s_axi_in_rvalid,
input wire s_axi_in_rready,
// Ports of Axi Master Bus Interface M_AXI_out
input wire m_axi_out_aclk,
input wire m_axi_out_aresetn,
output wire [C_M_AXI_out_ID_WIDTH-1 : 0] m_axi_out_awid,
output wire [C_M_AXI_out_ADDR_WIDTH-1 : 0] m_axi_out_awaddr,
output wire [7 : 0] m_axi_out_awlen,
output wire [2 : 0] m_axi_out_awsize,
output wire [1 : 0] m_axi_out_awburst,
output wire m_axi_out_awlock,
output wire [3 : 0] m_axi_out_awcache,
output wire [2 : 0] m_axi_out_awprot,
output wire [3 : 0] m_axi_out_awqos,
output wire [C_M_AXI_out_AWUSER_WIDTH-1 : 0] m_axi_out_awuser,
output wire m_axi_out_awvalid,
input wire m_axi_out_awready,
output wire [C_M_AXI_out_DATA_WIDTH-1 : 0] m_axi_out_wdata,
output wire [C_M_AXI_out_DATA_WIDTH/8-1 : 0] m_axi_out_wstrb,
output wire m_axi_out_wlast,
output wire [C_M_AXI_out_WUSER_WIDTH-1 : 0] m_axi_out_wuser,
output wire m_axi_out_wvalid,
input wire m_axi_out_wready,
input wire [C_M_AXI_out_ID_WIDTH-1 : 0] m_axi_out_bid,
input wire [1 : 0] m_axi_out_bresp,
input wire [C_M_AXI_out_BUSER_WIDTH-1 : 0] m_axi_out_buser,
input wire m_axi_out_bvalid,
output wire m_axi_out_bready,
output wire [C_M_AXI_out_ID_WIDTH-1 : 0] m_axi_out_arid,
output wire [C_M_AXI_out_ADDR_WIDTH-1 : 0] m_axi_out_araddr,
output wire [7 : 0] m_axi_out_arlen,
output wire [2 : 0] m_axi_out_arsize,
output wire [1 : 0] m_axi_out_arburst,
output wire m_axi_out_arlock,
output wire [3 : 0] m_axi_out_arcache,
output wire [2 : 0] m_axi_out_arprot,
output wire [3 : 0] m_axi_out_arqos,
output wire [C_M_AXI_out_ARUSER_WIDTH-1 : 0] m_axi_out_aruser,
output wire m_axi_out_arvalid,
input wire m_axi_out_arready,
input wire [C_M_AXI_out_ID_WIDTH-1 : 0] m_axi_out_rid,
input wire [C_M_AXI_out_DATA_WIDTH-1 : 0] m_axi_out_rdata,
input wire [1 : 0] m_axi_out_rresp,
input wire m_axi_out_rlast,
input wire [C_M_AXI_out_RUSER_WIDTH-1 : 0] m_axi_out_ruser,
input wire m_axi_out_rvalid,
output wire m_axi_out_rready
);
// Instantiation of Axi Bus Interface S_AXI_in
assign m_axi_out_awid = s_axi_in_awid;
assign m_axi_out_awaddr = s_axi_in_awaddr;
assign m_axi_out_awlen = s_axi_in_awlen;
assign m_axi_out_awsize = s_axi_in_awsize;
assign m_axi_out_awburst = s_axi_in_awburst;
assign m_axi_out_awlock = s_axi_in_awlock;
assign m_axi_out_awcache = s_axi_in_awcache;
assign m_axi_out_awprot = s_axi_in_awprot;
assign m_axi_out_awqos = s_axi_in_awqos;
assign m_axi_out_awuser = s_axi_in_awuser;
assign m_axi_out_awvalid = s_axi_in_awvalid;
assign s_axi_in_awready = m_axi_out_awready;
assign m_axi_out_wdata = s_axi_in_wdata;
assign m_axi_out_wstrb = s_axi_in_wstrb;
assign m_axi_out_wlast = s_axi_in_wlast;
assign m_axi_out_wuser = s_axi_in_wuser;
assign m_axi_out_wvalid = s_axi_in_wvalid;
assign s_axi_in_wready = m_axi_out_wready;
assign s_axi_in_bid = m_axi_out_bid;
assign s_axi_in_bresp = m_axi_out_bresp;
assign s_axi_in_buser = m_axi_out_buser;
assign s_axi_in_bvalid = m_axi_out_bvalid;
assign m_axi_out_bready = s_axi_in_bready;
assign m_axi_out_arid = s_axi_in_arid;
assign m_axi_out_araddr = s_axi_in_araddr;
assign m_axi_out_arlen = s_axi_in_arlen;
assign m_axi_out_arsize = s_axi_in_arsize;
assign m_axi_out_arburst = s_axi_in_arburst;
assign m_axi_out_arlock = s_axi_in_arlock;
assign m_axi_out_arcache = s_axi_in_arcache;
assign m_axi_out_arprot = s_axi_in_arprot;
assign m_axi_out_arqos = s_axi_in_arqos;
assign m_axi_out_aruser = s_axi_in_aruser;
assign m_axi_out_arvalid = s_axi_in_arvalid;
assign s_axi_in_arready = m_axi_out_arready;
assign s_axi_in_rid = m_axi_out_rid;
assign s_axi_in_rdata = m_axi_out_rdata;
assign s_axi_in_rresp = m_axi_out_rresp;
assign s_axi_in_rlast = m_axi_out_rlast;
assign s_axi_in_ruser = m_axi_out_ruser;
assign s_axi_in_rvalid = m_axi_out_rvalid;
assign m_axi_out_rready = s_axi_in_rready;
// Add user logic here
// Add user logic here
// User logic ends
endmodule
|
// soc_design_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_mm_interconnect_0 (
input wire system_pll_outclk0_clk, // system_pll_outclk0.clk
input wire Test_PipeLine_reset_reset_bridge_in_reset_reset, // Test_PipeLine_reset_reset_bridge_in_reset.reset
input wire [26:0] niosII_core_data_master_address, // niosII_core_data_master.address
output wire niosII_core_data_master_waitrequest, // .waitrequest
input wire [3:0] niosII_core_data_master_burstcount, // .burstcount
input wire [3:0] niosII_core_data_master_byteenable, // .byteenable
input wire niosII_core_data_master_read, // .read
output wire [31:0] niosII_core_data_master_readdata, // .readdata
output wire niosII_core_data_master_readdatavalid, // .readdatavalid
input wire niosII_core_data_master_write, // .write
input wire [31:0] niosII_core_data_master_writedata, // .writedata
input wire niosII_core_data_master_debugaccess, // .debugaccess
input wire [26:0] niosII_core_instruction_master_address, // niosII_core_instruction_master.address
output wire niosII_core_instruction_master_waitrequest, // .waitrequest
input wire [3:0] niosII_core_instruction_master_burstcount, // .burstcount
input wire niosII_core_instruction_master_read, // .read
output wire [31:0] niosII_core_instruction_master_readdata, // .readdata
output wire niosII_core_instruction_master_readdatavalid, // .readdatavalid
input wire [31:0] Test_PipeLine_avm_m0_address, // Test_PipeLine_avm_m0.address
output wire Test_PipeLine_avm_m0_waitrequest, // .waitrequest
input wire [7:0] Test_PipeLine_avm_m0_burstcount, // .burstcount
input wire Test_PipeLine_avm_m0_read, // .read
output wire [31:0] Test_PipeLine_avm_m0_readdata, // .readdata
output wire Test_PipeLine_avm_m0_readdatavalid, // .readdatavalid
input wire Test_PipeLine_avm_m0_write, // .write
input wire [31:0] Test_PipeLine_avm_m0_writedata, // .writedata
output wire [8:0] convolution_slave_avs_s0_address, // convolution_slave_avs_s0.address
output wire convolution_slave_avs_s0_write, // .write
output wire convolution_slave_avs_s0_read, // .read
input wire [31:0] convolution_slave_avs_s0_readdata, // .readdata
output wire [31:0] convolution_slave_avs_s0_writedata, // .writedata
input wire convolution_slave_avs_s0_waitrequest, // .waitrequest
output wire [0:0] JTAG_avalon_jtag_slave_address, // JTAG_avalon_jtag_slave.address
output wire JTAG_avalon_jtag_slave_write, // .write
output wire JTAG_avalon_jtag_slave_read, // .read
input wire [31:0] JTAG_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] JTAG_avalon_jtag_slave_writedata, // .writedata
input wire JTAG_avalon_jtag_slave_waitrequest, // .waitrequest
output wire JTAG_avalon_jtag_slave_chipselect, // .chipselect
output wire [8:0] niosII_core_debug_mem_slave_address, // niosII_core_debug_mem_slave.address
output wire niosII_core_debug_mem_slave_write, // .write
output wire niosII_core_debug_mem_slave_read, // .read
input wire [31:0] niosII_core_debug_mem_slave_readdata, // .readdata
output wire [31:0] niosII_core_debug_mem_slave_writedata, // .writedata
output wire [3:0] niosII_core_debug_mem_slave_byteenable, // .byteenable
input wire niosII_core_debug_mem_slave_waitrequest, // .waitrequest
output wire niosII_core_debug_mem_slave_debugaccess, // .debugaccess
output wire [24:0] SDRAM_s1_address, // SDRAM_s1.address
output wire SDRAM_s1_write, // .write
output wire SDRAM_s1_read, // .read
input wire [15:0] SDRAM_s1_readdata, // .readdata
output wire [15:0] SDRAM_s1_writedata, // .writedata
output wire [1:0] SDRAM_s1_byteenable, // .byteenable
input wire SDRAM_s1_readdatavalid, // .readdatavalid
input wire SDRAM_s1_waitrequest, // .waitrequest
output wire SDRAM_s1_chipselect, // .chipselect
output wire [14:0] SRAM_s1_address, // SRAM_s1.address
output wire SRAM_s1_write, // .write
input wire [31:0] SRAM_s1_readdata, // .readdata
output wire [31:0] SRAM_s1_writedata, // .writedata
output wire [3:0] SRAM_s1_byteenable, // .byteenable
output wire SRAM_s1_chipselect, // .chipselect
output wire SRAM_s1_clken, // .clken
output wire [2:0] Sys_Timer_s1_address, // Sys_Timer_s1.address
output wire Sys_Timer_s1_write, // .write
input wire [15:0] Sys_Timer_s1_readdata, // .readdata
output wire [15:0] Sys_Timer_s1_writedata, // .writedata
output wire Sys_Timer_s1_chipselect, // .chipselect
output wire [0:0] SystemID_control_slave_address, // SystemID_control_slave.address
input wire [31:0] SystemID_control_slave_readdata, // .readdata
output wire [7:0] Test_PipeLine_avs_s0_address, // Test_PipeLine_avs_s0.address
output wire Test_PipeLine_avs_s0_write, // .write
output wire Test_PipeLine_avs_s0_read, // .read
input wire [31:0] Test_PipeLine_avs_s0_readdata, // .readdata
output wire [31:0] Test_PipeLine_avs_s0_writedata, // .writedata
input wire Test_PipeLine_avs_s0_waitrequest, // .waitrequest
output wire [0:0] UART_COM_avalon_rs232_slave_address, // UART_COM_avalon_rs232_slave.address
output wire UART_COM_avalon_rs232_slave_write, // .write
output wire UART_COM_avalon_rs232_slave_read, // .read
input wire [31:0] UART_COM_avalon_rs232_slave_readdata, // .readdata
output wire [31:0] UART_COM_avalon_rs232_slave_writedata, // .writedata
output wire [3:0] UART_COM_avalon_rs232_slave_byteenable, // .byteenable
output wire UART_COM_avalon_rs232_slave_chipselect // .chipselect
);
wire test_pipeline_avm_m0_translator_avalon_universal_master_0_waitrequest; // Test_PipeLine_avm_m0_agent:av_waitrequest -> Test_PipeLine_avm_m0_translator:uav_waitrequest
wire [31:0] test_pipeline_avm_m0_translator_avalon_universal_master_0_readdata; // Test_PipeLine_avm_m0_agent:av_readdata -> Test_PipeLine_avm_m0_translator:uav_readdata
wire test_pipeline_avm_m0_translator_avalon_universal_master_0_debugaccess; // Test_PipeLine_avm_m0_translator:uav_debugaccess -> Test_PipeLine_avm_m0_agent:av_debugaccess
wire [31:0] test_pipeline_avm_m0_translator_avalon_universal_master_0_address; // Test_PipeLine_avm_m0_translator:uav_address -> Test_PipeLine_avm_m0_agent:av_address
wire test_pipeline_avm_m0_translator_avalon_universal_master_0_read; // Test_PipeLine_avm_m0_translator:uav_read -> Test_PipeLine_avm_m0_agent:av_read
wire [3:0] test_pipeline_avm_m0_translator_avalon_universal_master_0_byteenable; // Test_PipeLine_avm_m0_translator:uav_byteenable -> Test_PipeLine_avm_m0_agent:av_byteenable
wire test_pipeline_avm_m0_translator_avalon_universal_master_0_readdatavalid; // Test_PipeLine_avm_m0_agent:av_readdatavalid -> Test_PipeLine_avm_m0_translator:uav_readdatavalid
wire test_pipeline_avm_m0_translator_avalon_universal_master_0_lock; // Test_PipeLine_avm_m0_translator:uav_lock -> Test_PipeLine_avm_m0_agent:av_lock
wire test_pipeline_avm_m0_translator_avalon_universal_master_0_write; // Test_PipeLine_avm_m0_translator:uav_write -> Test_PipeLine_avm_m0_agent:av_write
wire [31:0] test_pipeline_avm_m0_translator_avalon_universal_master_0_writedata; // Test_PipeLine_avm_m0_translator:uav_writedata -> Test_PipeLine_avm_m0_agent:av_writedata
wire [9:0] test_pipeline_avm_m0_translator_avalon_universal_master_0_burstcount; // Test_PipeLine_avm_m0_translator:uav_burstcount -> Test_PipeLine_avm_m0_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> Test_PipeLine_avm_m0_agent:rp_valid
wire [119:0] rsp_mux_src_data; // rsp_mux:src_data -> Test_PipeLine_avm_m0_agent:rp_data
wire rsp_mux_src_ready; // Test_PipeLine_avm_m0_agent:rp_ready -> rsp_mux:src_ready
wire [8:0] rsp_mux_src_channel; // rsp_mux:src_channel -> Test_PipeLine_avm_m0_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> Test_PipeLine_avm_m0_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> Test_PipeLine_avm_m0_agent:rp_endofpacket
wire niosii_core_data_master_translator_avalon_universal_master_0_waitrequest; // niosII_core_data_master_agent:av_waitrequest -> niosII_core_data_master_translator:uav_waitrequest
wire [31:0] niosii_core_data_master_translator_avalon_universal_master_0_readdata; // niosII_core_data_master_agent:av_readdata -> niosII_core_data_master_translator:uav_readdata
wire niosii_core_data_master_translator_avalon_universal_master_0_debugaccess; // niosII_core_data_master_translator:uav_debugaccess -> niosII_core_data_master_agent:av_debugaccess
wire [31:0] niosii_core_data_master_translator_avalon_universal_master_0_address; // niosII_core_data_master_translator:uav_address -> niosII_core_data_master_agent:av_address
wire niosii_core_data_master_translator_avalon_universal_master_0_read; // niosII_core_data_master_translator:uav_read -> niosII_core_data_master_agent:av_read
wire [3:0] niosii_core_data_master_translator_avalon_universal_master_0_byteenable; // niosII_core_data_master_translator:uav_byteenable -> niosII_core_data_master_agent:av_byteenable
wire niosii_core_data_master_translator_avalon_universal_master_0_readdatavalid; // niosII_core_data_master_agent:av_readdatavalid -> niosII_core_data_master_translator:uav_readdatavalid
wire niosii_core_data_master_translator_avalon_universal_master_0_lock; // niosII_core_data_master_translator:uav_lock -> niosII_core_data_master_agent:av_lock
wire niosii_core_data_master_translator_avalon_universal_master_0_write; // niosII_core_data_master_translator:uav_write -> niosII_core_data_master_agent:av_write
wire [31:0] niosii_core_data_master_translator_avalon_universal_master_0_writedata; // niosII_core_data_master_translator:uav_writedata -> niosII_core_data_master_agent:av_writedata
wire [5:0] niosii_core_data_master_translator_avalon_universal_master_0_burstcount; // niosII_core_data_master_translator:uav_burstcount -> niosII_core_data_master_agent:av_burstcount
wire niosii_core_instruction_master_translator_avalon_universal_master_0_waitrequest; // niosII_core_instruction_master_agent:av_waitrequest -> niosII_core_instruction_master_translator:uav_waitrequest
wire [31:0] niosii_core_instruction_master_translator_avalon_universal_master_0_readdata; // niosII_core_instruction_master_agent:av_readdata -> niosII_core_instruction_master_translator:uav_readdata
wire niosii_core_instruction_master_translator_avalon_universal_master_0_debugaccess; // niosII_core_instruction_master_translator:uav_debugaccess -> niosII_core_instruction_master_agent:av_debugaccess
wire [31:0] niosii_core_instruction_master_translator_avalon_universal_master_0_address; // niosII_core_instruction_master_translator:uav_address -> niosII_core_instruction_master_agent:av_address
wire niosii_core_instruction_master_translator_avalon_universal_master_0_read; // niosII_core_instruction_master_translator:uav_read -> niosII_core_instruction_master_agent:av_read
wire [3:0] niosii_core_instruction_master_translator_avalon_universal_master_0_byteenable; // niosII_core_instruction_master_translator:uav_byteenable -> niosII_core_instruction_master_agent:av_byteenable
wire niosii_core_instruction_master_translator_avalon_universal_master_0_readdatavalid; // niosII_core_instruction_master_agent:av_readdatavalid -> niosII_core_instruction_master_translator:uav_readdatavalid
wire niosii_core_instruction_master_translator_avalon_universal_master_0_lock; // niosII_core_instruction_master_translator:uav_lock -> niosII_core_instruction_master_agent:av_lock
wire niosii_core_instruction_master_translator_avalon_universal_master_0_write; // niosII_core_instruction_master_translator:uav_write -> niosII_core_instruction_master_agent:av_write
wire [31:0] niosii_core_instruction_master_translator_avalon_universal_master_0_writedata; // niosII_core_instruction_master_translator:uav_writedata -> niosII_core_instruction_master_agent:av_writedata
wire [5:0] niosii_core_instruction_master_translator_avalon_universal_master_0_burstcount; // niosII_core_instruction_master_translator:uav_burstcount -> niosII_core_instruction_master_agent:av_burstcount
wire [15:0] sdram_s1_agent_m0_readdata; // SDRAM_s1_translator:uav_readdata -> SDRAM_s1_agent:m0_readdata
wire sdram_s1_agent_m0_waitrequest; // SDRAM_s1_translator:uav_waitrequest -> SDRAM_s1_agent:m0_waitrequest
wire sdram_s1_agent_m0_debugaccess; // SDRAM_s1_agent:m0_debugaccess -> SDRAM_s1_translator:uav_debugaccess
wire [31:0] sdram_s1_agent_m0_address; // SDRAM_s1_agent:m0_address -> SDRAM_s1_translator:uav_address
wire [1:0] sdram_s1_agent_m0_byteenable; // SDRAM_s1_agent:m0_byteenable -> SDRAM_s1_translator:uav_byteenable
wire sdram_s1_agent_m0_read; // SDRAM_s1_agent:m0_read -> SDRAM_s1_translator:uav_read
wire sdram_s1_agent_m0_readdatavalid; // SDRAM_s1_translator:uav_readdatavalid -> SDRAM_s1_agent:m0_readdatavalid
wire sdram_s1_agent_m0_lock; // SDRAM_s1_agent:m0_lock -> SDRAM_s1_translator:uav_lock
wire [15:0] sdram_s1_agent_m0_writedata; // SDRAM_s1_agent:m0_writedata -> SDRAM_s1_translator:uav_writedata
wire sdram_s1_agent_m0_write; // SDRAM_s1_agent:m0_write -> SDRAM_s1_translator:uav_write
wire [1:0] sdram_s1_agent_m0_burstcount; // SDRAM_s1_agent:m0_burstcount -> SDRAM_s1_translator:uav_burstcount
wire sdram_s1_agent_rf_source_valid; // SDRAM_s1_agent:rf_source_valid -> SDRAM_s1_agent_rsp_fifo:in_valid
wire [102:0] sdram_s1_agent_rf_source_data; // SDRAM_s1_agent:rf_source_data -> SDRAM_s1_agent_rsp_fifo:in_data
wire sdram_s1_agent_rf_source_ready; // SDRAM_s1_agent_rsp_fifo:in_ready -> SDRAM_s1_agent:rf_source_ready
wire sdram_s1_agent_rf_source_startofpacket; // SDRAM_s1_agent:rf_source_startofpacket -> SDRAM_s1_agent_rsp_fifo:in_startofpacket
wire sdram_s1_agent_rf_source_endofpacket; // SDRAM_s1_agent:rf_source_endofpacket -> SDRAM_s1_agent_rsp_fifo:in_endofpacket
wire sdram_s1_agent_rsp_fifo_out_valid; // SDRAM_s1_agent_rsp_fifo:out_valid -> SDRAM_s1_agent:rf_sink_valid
wire [102:0] sdram_s1_agent_rsp_fifo_out_data; // SDRAM_s1_agent_rsp_fifo:out_data -> SDRAM_s1_agent:rf_sink_data
wire sdram_s1_agent_rsp_fifo_out_ready; // SDRAM_s1_agent:rf_sink_ready -> SDRAM_s1_agent_rsp_fifo:out_ready
wire sdram_s1_agent_rsp_fifo_out_startofpacket; // SDRAM_s1_agent_rsp_fifo:out_startofpacket -> SDRAM_s1_agent:rf_sink_startofpacket
wire sdram_s1_agent_rsp_fifo_out_endofpacket; // SDRAM_s1_agent_rsp_fifo:out_endofpacket -> SDRAM_s1_agent:rf_sink_endofpacket
wire sdram_s1_agent_rdata_fifo_src_valid; // SDRAM_s1_agent:rdata_fifo_src_valid -> SDRAM_s1_agent_rdata_fifo:in_valid
wire [17:0] sdram_s1_agent_rdata_fifo_src_data; // SDRAM_s1_agent:rdata_fifo_src_data -> SDRAM_s1_agent_rdata_fifo:in_data
wire sdram_s1_agent_rdata_fifo_src_ready; // SDRAM_s1_agent_rdata_fifo:in_ready -> SDRAM_s1_agent:rdata_fifo_src_ready
wire [31:0] niosii_core_debug_mem_slave_agent_m0_readdata; // niosII_core_debug_mem_slave_translator:uav_readdata -> niosII_core_debug_mem_slave_agent:m0_readdata
wire niosii_core_debug_mem_slave_agent_m0_waitrequest; // niosII_core_debug_mem_slave_translator:uav_waitrequest -> niosII_core_debug_mem_slave_agent:m0_waitrequest
wire niosii_core_debug_mem_slave_agent_m0_debugaccess; // niosII_core_debug_mem_slave_agent:m0_debugaccess -> niosII_core_debug_mem_slave_translator:uav_debugaccess
wire [31:0] niosii_core_debug_mem_slave_agent_m0_address; // niosII_core_debug_mem_slave_agent:m0_address -> niosII_core_debug_mem_slave_translator:uav_address
wire [3:0] niosii_core_debug_mem_slave_agent_m0_byteenable; // niosII_core_debug_mem_slave_agent:m0_byteenable -> niosII_core_debug_mem_slave_translator:uav_byteenable
wire niosii_core_debug_mem_slave_agent_m0_read; // niosII_core_debug_mem_slave_agent:m0_read -> niosII_core_debug_mem_slave_translator:uav_read
wire niosii_core_debug_mem_slave_agent_m0_readdatavalid; // niosII_core_debug_mem_slave_translator:uav_readdatavalid -> niosII_core_debug_mem_slave_agent:m0_readdatavalid
wire niosii_core_debug_mem_slave_agent_m0_lock; // niosII_core_debug_mem_slave_agent:m0_lock -> niosII_core_debug_mem_slave_translator:uav_lock
wire [31:0] niosii_core_debug_mem_slave_agent_m0_writedata; // niosII_core_debug_mem_slave_agent:m0_writedata -> niosII_core_debug_mem_slave_translator:uav_writedata
wire niosii_core_debug_mem_slave_agent_m0_write; // niosII_core_debug_mem_slave_agent:m0_write -> niosII_core_debug_mem_slave_translator:uav_write
wire [2:0] niosii_core_debug_mem_slave_agent_m0_burstcount; // niosII_core_debug_mem_slave_agent:m0_burstcount -> niosII_core_debug_mem_slave_translator:uav_burstcount
wire niosii_core_debug_mem_slave_agent_rf_source_valid; // niosII_core_debug_mem_slave_agent:rf_source_valid -> niosII_core_debug_mem_slave_agent_rsp_fifo:in_valid
wire [120:0] niosii_core_debug_mem_slave_agent_rf_source_data; // niosII_core_debug_mem_slave_agent:rf_source_data -> niosII_core_debug_mem_slave_agent_rsp_fifo:in_data
wire niosii_core_debug_mem_slave_agent_rf_source_ready; // niosII_core_debug_mem_slave_agent_rsp_fifo:in_ready -> niosII_core_debug_mem_slave_agent:rf_source_ready
wire niosii_core_debug_mem_slave_agent_rf_source_startofpacket; // niosII_core_debug_mem_slave_agent:rf_source_startofpacket -> niosII_core_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire niosii_core_debug_mem_slave_agent_rf_source_endofpacket; // niosII_core_debug_mem_slave_agent:rf_source_endofpacket -> niosII_core_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire niosii_core_debug_mem_slave_agent_rsp_fifo_out_valid; // niosII_core_debug_mem_slave_agent_rsp_fifo:out_valid -> niosII_core_debug_mem_slave_agent:rf_sink_valid
wire [120:0] niosii_core_debug_mem_slave_agent_rsp_fifo_out_data; // niosII_core_debug_mem_slave_agent_rsp_fifo:out_data -> niosII_core_debug_mem_slave_agent:rf_sink_data
wire niosii_core_debug_mem_slave_agent_rsp_fifo_out_ready; // niosII_core_debug_mem_slave_agent:rf_sink_ready -> niosII_core_debug_mem_slave_agent_rsp_fifo:out_ready
wire niosii_core_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // niosII_core_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> niosII_core_debug_mem_slave_agent:rf_sink_startofpacket
wire niosii_core_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // niosII_core_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> niosII_core_debug_mem_slave_agent:rf_sink_endofpacket
wire [31:0] sram_s1_agent_m0_readdata; // SRAM_s1_translator:uav_readdata -> SRAM_s1_agent:m0_readdata
wire sram_s1_agent_m0_waitrequest; // SRAM_s1_translator:uav_waitrequest -> SRAM_s1_agent:m0_waitrequest
wire sram_s1_agent_m0_debugaccess; // SRAM_s1_agent:m0_debugaccess -> SRAM_s1_translator:uav_debugaccess
wire [31:0] sram_s1_agent_m0_address; // SRAM_s1_agent:m0_address -> SRAM_s1_translator:uav_address
wire [3:0] sram_s1_agent_m0_byteenable; // SRAM_s1_agent:m0_byteenable -> SRAM_s1_translator:uav_byteenable
wire sram_s1_agent_m0_read; // SRAM_s1_agent:m0_read -> SRAM_s1_translator:uav_read
wire sram_s1_agent_m0_readdatavalid; // SRAM_s1_translator:uav_readdatavalid -> SRAM_s1_agent:m0_readdatavalid
wire sram_s1_agent_m0_lock; // SRAM_s1_agent:m0_lock -> SRAM_s1_translator:uav_lock
wire [31:0] sram_s1_agent_m0_writedata; // SRAM_s1_agent:m0_writedata -> SRAM_s1_translator:uav_writedata
wire sram_s1_agent_m0_write; // SRAM_s1_agent:m0_write -> SRAM_s1_translator:uav_write
wire [2:0] sram_s1_agent_m0_burstcount; // SRAM_s1_agent:m0_burstcount -> SRAM_s1_translator:uav_burstcount
wire sram_s1_agent_rf_source_valid; // SRAM_s1_agent:rf_source_valid -> SRAM_s1_agent_rsp_fifo:in_valid
wire [120:0] sram_s1_agent_rf_source_data; // SRAM_s1_agent:rf_source_data -> SRAM_s1_agent_rsp_fifo:in_data
wire sram_s1_agent_rf_source_ready; // SRAM_s1_agent_rsp_fifo:in_ready -> SRAM_s1_agent:rf_source_ready
wire sram_s1_agent_rf_source_startofpacket; // SRAM_s1_agent:rf_source_startofpacket -> SRAM_s1_agent_rsp_fifo:in_startofpacket
wire sram_s1_agent_rf_source_endofpacket; // SRAM_s1_agent:rf_source_endofpacket -> SRAM_s1_agent_rsp_fifo:in_endofpacket
wire sram_s1_agent_rsp_fifo_out_valid; // SRAM_s1_agent_rsp_fifo:out_valid -> SRAM_s1_agent:rf_sink_valid
wire [120:0] sram_s1_agent_rsp_fifo_out_data; // SRAM_s1_agent_rsp_fifo:out_data -> SRAM_s1_agent:rf_sink_data
wire sram_s1_agent_rsp_fifo_out_ready; // SRAM_s1_agent:rf_sink_ready -> SRAM_s1_agent_rsp_fifo:out_ready
wire sram_s1_agent_rsp_fifo_out_startofpacket; // SRAM_s1_agent_rsp_fifo:out_startofpacket -> SRAM_s1_agent:rf_sink_startofpacket
wire sram_s1_agent_rsp_fifo_out_endofpacket; // SRAM_s1_agent_rsp_fifo:out_endofpacket -> SRAM_s1_agent:rf_sink_endofpacket
wire [31:0] jtag_avalon_jtag_slave_agent_m0_readdata; // JTAG_avalon_jtag_slave_translator:uav_readdata -> JTAG_avalon_jtag_slave_agent:m0_readdata
wire jtag_avalon_jtag_slave_agent_m0_waitrequest; // JTAG_avalon_jtag_slave_translator:uav_waitrequest -> JTAG_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_avalon_jtag_slave_agent_m0_debugaccess; // JTAG_avalon_jtag_slave_agent:m0_debugaccess -> JTAG_avalon_jtag_slave_translator:uav_debugaccess
wire [31:0] jtag_avalon_jtag_slave_agent_m0_address; // JTAG_avalon_jtag_slave_agent:m0_address -> JTAG_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_avalon_jtag_slave_agent_m0_byteenable; // JTAG_avalon_jtag_slave_agent:m0_byteenable -> JTAG_avalon_jtag_slave_translator:uav_byteenable
wire jtag_avalon_jtag_slave_agent_m0_read; // JTAG_avalon_jtag_slave_agent:m0_read -> JTAG_avalon_jtag_slave_translator:uav_read
wire jtag_avalon_jtag_slave_agent_m0_readdatavalid; // JTAG_avalon_jtag_slave_translator:uav_readdatavalid -> JTAG_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_avalon_jtag_slave_agent_m0_lock; // JTAG_avalon_jtag_slave_agent:m0_lock -> JTAG_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_avalon_jtag_slave_agent_m0_writedata; // JTAG_avalon_jtag_slave_agent:m0_writedata -> JTAG_avalon_jtag_slave_translator:uav_writedata
wire jtag_avalon_jtag_slave_agent_m0_write; // JTAG_avalon_jtag_slave_agent:m0_write -> JTAG_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_avalon_jtag_slave_agent_m0_burstcount; // JTAG_avalon_jtag_slave_agent:m0_burstcount -> JTAG_avalon_jtag_slave_translator:uav_burstcount
wire jtag_avalon_jtag_slave_agent_rf_source_valid; // JTAG_avalon_jtag_slave_agent:rf_source_valid -> JTAG_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [120:0] jtag_avalon_jtag_slave_agent_rf_source_data; // JTAG_avalon_jtag_slave_agent:rf_source_data -> JTAG_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_avalon_jtag_slave_agent_rf_source_ready; // JTAG_avalon_jtag_slave_agent_rsp_fifo:in_ready -> JTAG_avalon_jtag_slave_agent:rf_source_ready
wire jtag_avalon_jtag_slave_agent_rf_source_startofpacket; // JTAG_avalon_jtag_slave_agent:rf_source_startofpacket -> JTAG_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_avalon_jtag_slave_agent_rf_source_endofpacket; // JTAG_avalon_jtag_slave_agent:rf_source_endofpacket -> JTAG_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid; // JTAG_avalon_jtag_slave_agent_rsp_fifo:out_valid -> JTAG_avalon_jtag_slave_agent:rf_sink_valid
wire [120:0] jtag_avalon_jtag_slave_agent_rsp_fifo_out_data; // JTAG_avalon_jtag_slave_agent_rsp_fifo:out_data -> JTAG_avalon_jtag_slave_agent:rf_sink_data
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready; // JTAG_avalon_jtag_slave_agent:rf_sink_ready -> JTAG_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // JTAG_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> JTAG_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // JTAG_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> JTAG_avalon_jtag_slave_agent:rf_sink_endofpacket
wire [31:0] uart_com_avalon_rs232_slave_agent_m0_readdata; // UART_COM_avalon_rs232_slave_translator:uav_readdata -> UART_COM_avalon_rs232_slave_agent:m0_readdata
wire uart_com_avalon_rs232_slave_agent_m0_waitrequest; // UART_COM_avalon_rs232_slave_translator:uav_waitrequest -> UART_COM_avalon_rs232_slave_agent:m0_waitrequest
wire uart_com_avalon_rs232_slave_agent_m0_debugaccess; // UART_COM_avalon_rs232_slave_agent:m0_debugaccess -> UART_COM_avalon_rs232_slave_translator:uav_debugaccess
wire [31:0] uart_com_avalon_rs232_slave_agent_m0_address; // UART_COM_avalon_rs232_slave_agent:m0_address -> UART_COM_avalon_rs232_slave_translator:uav_address
wire [3:0] uart_com_avalon_rs232_slave_agent_m0_byteenable; // UART_COM_avalon_rs232_slave_agent:m0_byteenable -> UART_COM_avalon_rs232_slave_translator:uav_byteenable
wire uart_com_avalon_rs232_slave_agent_m0_read; // UART_COM_avalon_rs232_slave_agent:m0_read -> UART_COM_avalon_rs232_slave_translator:uav_read
wire uart_com_avalon_rs232_slave_agent_m0_readdatavalid; // UART_COM_avalon_rs232_slave_translator:uav_readdatavalid -> UART_COM_avalon_rs232_slave_agent:m0_readdatavalid
wire uart_com_avalon_rs232_slave_agent_m0_lock; // UART_COM_avalon_rs232_slave_agent:m0_lock -> UART_COM_avalon_rs232_slave_translator:uav_lock
wire [31:0] uart_com_avalon_rs232_slave_agent_m0_writedata; // UART_COM_avalon_rs232_slave_agent:m0_writedata -> UART_COM_avalon_rs232_slave_translator:uav_writedata
wire uart_com_avalon_rs232_slave_agent_m0_write; // UART_COM_avalon_rs232_slave_agent:m0_write -> UART_COM_avalon_rs232_slave_translator:uav_write
wire [2:0] uart_com_avalon_rs232_slave_agent_m0_burstcount; // UART_COM_avalon_rs232_slave_agent:m0_burstcount -> UART_COM_avalon_rs232_slave_translator:uav_burstcount
wire uart_com_avalon_rs232_slave_agent_rf_source_valid; // UART_COM_avalon_rs232_slave_agent:rf_source_valid -> UART_COM_avalon_rs232_slave_agent_rsp_fifo:in_valid
wire [120:0] uart_com_avalon_rs232_slave_agent_rf_source_data; // UART_COM_avalon_rs232_slave_agent:rf_source_data -> UART_COM_avalon_rs232_slave_agent_rsp_fifo:in_data
wire uart_com_avalon_rs232_slave_agent_rf_source_ready; // UART_COM_avalon_rs232_slave_agent_rsp_fifo:in_ready -> UART_COM_avalon_rs232_slave_agent:rf_source_ready
wire uart_com_avalon_rs232_slave_agent_rf_source_startofpacket; // UART_COM_avalon_rs232_slave_agent:rf_source_startofpacket -> UART_COM_avalon_rs232_slave_agent_rsp_fifo:in_startofpacket
wire uart_com_avalon_rs232_slave_agent_rf_source_endofpacket; // UART_COM_avalon_rs232_slave_agent:rf_source_endofpacket -> UART_COM_avalon_rs232_slave_agent_rsp_fifo:in_endofpacket
wire uart_com_avalon_rs232_slave_agent_rsp_fifo_out_valid; // UART_COM_avalon_rs232_slave_agent_rsp_fifo:out_valid -> UART_COM_avalon_rs232_slave_agent:rf_sink_valid
wire [120:0] uart_com_avalon_rs232_slave_agent_rsp_fifo_out_data; // UART_COM_avalon_rs232_slave_agent_rsp_fifo:out_data -> UART_COM_avalon_rs232_slave_agent:rf_sink_data
wire uart_com_avalon_rs232_slave_agent_rsp_fifo_out_ready; // UART_COM_avalon_rs232_slave_agent:rf_sink_ready -> UART_COM_avalon_rs232_slave_agent_rsp_fifo:out_ready
wire uart_com_avalon_rs232_slave_agent_rsp_fifo_out_startofpacket; // UART_COM_avalon_rs232_slave_agent_rsp_fifo:out_startofpacket -> UART_COM_avalon_rs232_slave_agent:rf_sink_startofpacket
wire uart_com_avalon_rs232_slave_agent_rsp_fifo_out_endofpacket; // UART_COM_avalon_rs232_slave_agent_rsp_fifo:out_endofpacket -> UART_COM_avalon_rs232_slave_agent:rf_sink_endofpacket
wire [31:0] convolution_slave_avs_s0_agent_m0_readdata; // convolution_slave_avs_s0_translator:uav_readdata -> convolution_slave_avs_s0_agent:m0_readdata
wire convolution_slave_avs_s0_agent_m0_waitrequest; // convolution_slave_avs_s0_translator:uav_waitrequest -> convolution_slave_avs_s0_agent:m0_waitrequest
wire convolution_slave_avs_s0_agent_m0_debugaccess; // convolution_slave_avs_s0_agent:m0_debugaccess -> convolution_slave_avs_s0_translator:uav_debugaccess
wire [31:0] convolution_slave_avs_s0_agent_m0_address; // convolution_slave_avs_s0_agent:m0_address -> convolution_slave_avs_s0_translator:uav_address
wire [3:0] convolution_slave_avs_s0_agent_m0_byteenable; // convolution_slave_avs_s0_agent:m0_byteenable -> convolution_slave_avs_s0_translator:uav_byteenable
wire convolution_slave_avs_s0_agent_m0_read; // convolution_slave_avs_s0_agent:m0_read -> convolution_slave_avs_s0_translator:uav_read
wire convolution_slave_avs_s0_agent_m0_readdatavalid; // convolution_slave_avs_s0_translator:uav_readdatavalid -> convolution_slave_avs_s0_agent:m0_readdatavalid
wire convolution_slave_avs_s0_agent_m0_lock; // convolution_slave_avs_s0_agent:m0_lock -> convolution_slave_avs_s0_translator:uav_lock
wire [31:0] convolution_slave_avs_s0_agent_m0_writedata; // convolution_slave_avs_s0_agent:m0_writedata -> convolution_slave_avs_s0_translator:uav_writedata
wire convolution_slave_avs_s0_agent_m0_write; // convolution_slave_avs_s0_agent:m0_write -> convolution_slave_avs_s0_translator:uav_write
wire [2:0] convolution_slave_avs_s0_agent_m0_burstcount; // convolution_slave_avs_s0_agent:m0_burstcount -> convolution_slave_avs_s0_translator:uav_burstcount
wire convolution_slave_avs_s0_agent_rf_source_valid; // convolution_slave_avs_s0_agent:rf_source_valid -> convolution_slave_avs_s0_agent_rsp_fifo:in_valid
wire [120:0] convolution_slave_avs_s0_agent_rf_source_data; // convolution_slave_avs_s0_agent:rf_source_data -> convolution_slave_avs_s0_agent_rsp_fifo:in_data
wire convolution_slave_avs_s0_agent_rf_source_ready; // convolution_slave_avs_s0_agent_rsp_fifo:in_ready -> convolution_slave_avs_s0_agent:rf_source_ready
wire convolution_slave_avs_s0_agent_rf_source_startofpacket; // convolution_slave_avs_s0_agent:rf_source_startofpacket -> convolution_slave_avs_s0_agent_rsp_fifo:in_startofpacket
wire convolution_slave_avs_s0_agent_rf_source_endofpacket; // convolution_slave_avs_s0_agent:rf_source_endofpacket -> convolution_slave_avs_s0_agent_rsp_fifo:in_endofpacket
wire convolution_slave_avs_s0_agent_rsp_fifo_out_valid; // convolution_slave_avs_s0_agent_rsp_fifo:out_valid -> convolution_slave_avs_s0_agent:rf_sink_valid
wire [120:0] convolution_slave_avs_s0_agent_rsp_fifo_out_data; // convolution_slave_avs_s0_agent_rsp_fifo:out_data -> convolution_slave_avs_s0_agent:rf_sink_data
wire convolution_slave_avs_s0_agent_rsp_fifo_out_ready; // convolution_slave_avs_s0_agent:rf_sink_ready -> convolution_slave_avs_s0_agent_rsp_fifo:out_ready
wire convolution_slave_avs_s0_agent_rsp_fifo_out_startofpacket; // convolution_slave_avs_s0_agent_rsp_fifo:out_startofpacket -> convolution_slave_avs_s0_agent:rf_sink_startofpacket
wire convolution_slave_avs_s0_agent_rsp_fifo_out_endofpacket; // convolution_slave_avs_s0_agent_rsp_fifo:out_endofpacket -> convolution_slave_avs_s0_agent:rf_sink_endofpacket
wire [31:0] test_pipeline_avs_s0_agent_m0_readdata; // Test_PipeLine_avs_s0_translator:uav_readdata -> Test_PipeLine_avs_s0_agent:m0_readdata
wire test_pipeline_avs_s0_agent_m0_waitrequest; // Test_PipeLine_avs_s0_translator:uav_waitrequest -> Test_PipeLine_avs_s0_agent:m0_waitrequest
wire test_pipeline_avs_s0_agent_m0_debugaccess; // Test_PipeLine_avs_s0_agent:m0_debugaccess -> Test_PipeLine_avs_s0_translator:uav_debugaccess
wire [31:0] test_pipeline_avs_s0_agent_m0_address; // Test_PipeLine_avs_s0_agent:m0_address -> Test_PipeLine_avs_s0_translator:uav_address
wire [3:0] test_pipeline_avs_s0_agent_m0_byteenable; // Test_PipeLine_avs_s0_agent:m0_byteenable -> Test_PipeLine_avs_s0_translator:uav_byteenable
wire test_pipeline_avs_s0_agent_m0_read; // Test_PipeLine_avs_s0_agent:m0_read -> Test_PipeLine_avs_s0_translator:uav_read
wire test_pipeline_avs_s0_agent_m0_readdatavalid; // Test_PipeLine_avs_s0_translator:uav_readdatavalid -> Test_PipeLine_avs_s0_agent:m0_readdatavalid
wire test_pipeline_avs_s0_agent_m0_lock; // Test_PipeLine_avs_s0_agent:m0_lock -> Test_PipeLine_avs_s0_translator:uav_lock
wire [31:0] test_pipeline_avs_s0_agent_m0_writedata; // Test_PipeLine_avs_s0_agent:m0_writedata -> Test_PipeLine_avs_s0_translator:uav_writedata
wire test_pipeline_avs_s0_agent_m0_write; // Test_PipeLine_avs_s0_agent:m0_write -> Test_PipeLine_avs_s0_translator:uav_write
wire [2:0] test_pipeline_avs_s0_agent_m0_burstcount; // Test_PipeLine_avs_s0_agent:m0_burstcount -> Test_PipeLine_avs_s0_translator:uav_burstcount
wire test_pipeline_avs_s0_agent_rf_source_valid; // Test_PipeLine_avs_s0_agent:rf_source_valid -> Test_PipeLine_avs_s0_agent_rsp_fifo:in_valid
wire [120:0] test_pipeline_avs_s0_agent_rf_source_data; // Test_PipeLine_avs_s0_agent:rf_source_data -> Test_PipeLine_avs_s0_agent_rsp_fifo:in_data
wire test_pipeline_avs_s0_agent_rf_source_ready; // Test_PipeLine_avs_s0_agent_rsp_fifo:in_ready -> Test_PipeLine_avs_s0_agent:rf_source_ready
wire test_pipeline_avs_s0_agent_rf_source_startofpacket; // Test_PipeLine_avs_s0_agent:rf_source_startofpacket -> Test_PipeLine_avs_s0_agent_rsp_fifo:in_startofpacket
wire test_pipeline_avs_s0_agent_rf_source_endofpacket; // Test_PipeLine_avs_s0_agent:rf_source_endofpacket -> Test_PipeLine_avs_s0_agent_rsp_fifo:in_endofpacket
wire test_pipeline_avs_s0_agent_rsp_fifo_out_valid; // Test_PipeLine_avs_s0_agent_rsp_fifo:out_valid -> Test_PipeLine_avs_s0_agent:rf_sink_valid
wire [120:0] test_pipeline_avs_s0_agent_rsp_fifo_out_data; // Test_PipeLine_avs_s0_agent_rsp_fifo:out_data -> Test_PipeLine_avs_s0_agent:rf_sink_data
wire test_pipeline_avs_s0_agent_rsp_fifo_out_ready; // Test_PipeLine_avs_s0_agent:rf_sink_ready -> Test_PipeLine_avs_s0_agent_rsp_fifo:out_ready
wire test_pipeline_avs_s0_agent_rsp_fifo_out_startofpacket; // Test_PipeLine_avs_s0_agent_rsp_fifo:out_startofpacket -> Test_PipeLine_avs_s0_agent:rf_sink_startofpacket
wire test_pipeline_avs_s0_agent_rsp_fifo_out_endofpacket; // Test_PipeLine_avs_s0_agent_rsp_fifo:out_endofpacket -> Test_PipeLine_avs_s0_agent:rf_sink_endofpacket
wire [31:0] systemid_control_slave_agent_m0_readdata; // SystemID_control_slave_translator:uav_readdata -> SystemID_control_slave_agent:m0_readdata
wire systemid_control_slave_agent_m0_waitrequest; // SystemID_control_slave_translator:uav_waitrequest -> SystemID_control_slave_agent:m0_waitrequest
wire systemid_control_slave_agent_m0_debugaccess; // SystemID_control_slave_agent:m0_debugaccess -> SystemID_control_slave_translator:uav_debugaccess
wire [31:0] systemid_control_slave_agent_m0_address; // SystemID_control_slave_agent:m0_address -> SystemID_control_slave_translator:uav_address
wire [3:0] systemid_control_slave_agent_m0_byteenable; // SystemID_control_slave_agent:m0_byteenable -> SystemID_control_slave_translator:uav_byteenable
wire systemid_control_slave_agent_m0_read; // SystemID_control_slave_agent:m0_read -> SystemID_control_slave_translator:uav_read
wire systemid_control_slave_agent_m0_readdatavalid; // SystemID_control_slave_translator:uav_readdatavalid -> SystemID_control_slave_agent:m0_readdatavalid
wire systemid_control_slave_agent_m0_lock; // SystemID_control_slave_agent:m0_lock -> SystemID_control_slave_translator:uav_lock
wire [31:0] systemid_control_slave_agent_m0_writedata; // SystemID_control_slave_agent:m0_writedata -> SystemID_control_slave_translator:uav_writedata
wire systemid_control_slave_agent_m0_write; // SystemID_control_slave_agent:m0_write -> SystemID_control_slave_translator:uav_write
wire [2:0] systemid_control_slave_agent_m0_burstcount; // SystemID_control_slave_agent:m0_burstcount -> SystemID_control_slave_translator:uav_burstcount
wire systemid_control_slave_agent_rf_source_valid; // SystemID_control_slave_agent:rf_source_valid -> SystemID_control_slave_agent_rsp_fifo:in_valid
wire [120:0] systemid_control_slave_agent_rf_source_data; // SystemID_control_slave_agent:rf_source_data -> SystemID_control_slave_agent_rsp_fifo:in_data
wire systemid_control_slave_agent_rf_source_ready; // SystemID_control_slave_agent_rsp_fifo:in_ready -> SystemID_control_slave_agent:rf_source_ready
wire systemid_control_slave_agent_rf_source_startofpacket; // SystemID_control_slave_agent:rf_source_startofpacket -> SystemID_control_slave_agent_rsp_fifo:in_startofpacket
wire systemid_control_slave_agent_rf_source_endofpacket; // SystemID_control_slave_agent:rf_source_endofpacket -> SystemID_control_slave_agent_rsp_fifo:in_endofpacket
wire systemid_control_slave_agent_rsp_fifo_out_valid; // SystemID_control_slave_agent_rsp_fifo:out_valid -> SystemID_control_slave_agent:rf_sink_valid
wire [120:0] systemid_control_slave_agent_rsp_fifo_out_data; // SystemID_control_slave_agent_rsp_fifo:out_data -> SystemID_control_slave_agent:rf_sink_data
wire systemid_control_slave_agent_rsp_fifo_out_ready; // SystemID_control_slave_agent:rf_sink_ready -> SystemID_control_slave_agent_rsp_fifo:out_ready
wire systemid_control_slave_agent_rsp_fifo_out_startofpacket; // SystemID_control_slave_agent_rsp_fifo:out_startofpacket -> SystemID_control_slave_agent:rf_sink_startofpacket
wire systemid_control_slave_agent_rsp_fifo_out_endofpacket; // SystemID_control_slave_agent_rsp_fifo:out_endofpacket -> SystemID_control_slave_agent:rf_sink_endofpacket
wire [31:0] sys_timer_s1_agent_m0_readdata; // Sys_Timer_s1_translator:uav_readdata -> Sys_Timer_s1_agent:m0_readdata
wire sys_timer_s1_agent_m0_waitrequest; // Sys_Timer_s1_translator:uav_waitrequest -> Sys_Timer_s1_agent:m0_waitrequest
wire sys_timer_s1_agent_m0_debugaccess; // Sys_Timer_s1_agent:m0_debugaccess -> Sys_Timer_s1_translator:uav_debugaccess
wire [31:0] sys_timer_s1_agent_m0_address; // Sys_Timer_s1_agent:m0_address -> Sys_Timer_s1_translator:uav_address
wire [3:0] sys_timer_s1_agent_m0_byteenable; // Sys_Timer_s1_agent:m0_byteenable -> Sys_Timer_s1_translator:uav_byteenable
wire sys_timer_s1_agent_m0_read; // Sys_Timer_s1_agent:m0_read -> Sys_Timer_s1_translator:uav_read
wire sys_timer_s1_agent_m0_readdatavalid; // Sys_Timer_s1_translator:uav_readdatavalid -> Sys_Timer_s1_agent:m0_readdatavalid
wire sys_timer_s1_agent_m0_lock; // Sys_Timer_s1_agent:m0_lock -> Sys_Timer_s1_translator:uav_lock
wire [31:0] sys_timer_s1_agent_m0_writedata; // Sys_Timer_s1_agent:m0_writedata -> Sys_Timer_s1_translator:uav_writedata
wire sys_timer_s1_agent_m0_write; // Sys_Timer_s1_agent:m0_write -> Sys_Timer_s1_translator:uav_write
wire [2:0] sys_timer_s1_agent_m0_burstcount; // Sys_Timer_s1_agent:m0_burstcount -> Sys_Timer_s1_translator:uav_burstcount
wire sys_timer_s1_agent_rf_source_valid; // Sys_Timer_s1_agent:rf_source_valid -> Sys_Timer_s1_agent_rsp_fifo:in_valid
wire [120:0] sys_timer_s1_agent_rf_source_data; // Sys_Timer_s1_agent:rf_source_data -> Sys_Timer_s1_agent_rsp_fifo:in_data
wire sys_timer_s1_agent_rf_source_ready; // Sys_Timer_s1_agent_rsp_fifo:in_ready -> Sys_Timer_s1_agent:rf_source_ready
wire sys_timer_s1_agent_rf_source_startofpacket; // Sys_Timer_s1_agent:rf_source_startofpacket -> Sys_Timer_s1_agent_rsp_fifo:in_startofpacket
wire sys_timer_s1_agent_rf_source_endofpacket; // Sys_Timer_s1_agent:rf_source_endofpacket -> Sys_Timer_s1_agent_rsp_fifo:in_endofpacket
wire sys_timer_s1_agent_rsp_fifo_out_valid; // Sys_Timer_s1_agent_rsp_fifo:out_valid -> Sys_Timer_s1_agent:rf_sink_valid
wire [120:0] sys_timer_s1_agent_rsp_fifo_out_data; // Sys_Timer_s1_agent_rsp_fifo:out_data -> Sys_Timer_s1_agent:rf_sink_data
wire sys_timer_s1_agent_rsp_fifo_out_ready; // Sys_Timer_s1_agent:rf_sink_ready -> Sys_Timer_s1_agent_rsp_fifo:out_ready
wire sys_timer_s1_agent_rsp_fifo_out_startofpacket; // Sys_Timer_s1_agent_rsp_fifo:out_startofpacket -> Sys_Timer_s1_agent:rf_sink_startofpacket
wire sys_timer_s1_agent_rsp_fifo_out_endofpacket; // Sys_Timer_s1_agent_rsp_fifo:out_endofpacket -> Sys_Timer_s1_agent:rf_sink_endofpacket
wire test_pipeline_avm_m0_agent_cp_valid; // Test_PipeLine_avm_m0_agent:cp_valid -> router:sink_valid
wire [119:0] test_pipeline_avm_m0_agent_cp_data; // Test_PipeLine_avm_m0_agent:cp_data -> router:sink_data
wire test_pipeline_avm_m0_agent_cp_ready; // router:sink_ready -> Test_PipeLine_avm_m0_agent:cp_ready
wire test_pipeline_avm_m0_agent_cp_startofpacket; // Test_PipeLine_avm_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire test_pipeline_avm_m0_agent_cp_endofpacket; // Test_PipeLine_avm_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [119:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [8:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire niosii_core_data_master_agent_cp_valid; // niosII_core_data_master_agent:cp_valid -> router_001:sink_valid
wire [119:0] niosii_core_data_master_agent_cp_data; // niosII_core_data_master_agent:cp_data -> router_001:sink_data
wire niosii_core_data_master_agent_cp_ready; // router_001:sink_ready -> niosII_core_data_master_agent:cp_ready
wire niosii_core_data_master_agent_cp_startofpacket; // niosII_core_data_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire niosii_core_data_master_agent_cp_endofpacket; // niosII_core_data_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire niosii_core_instruction_master_agent_cp_valid; // niosII_core_instruction_master_agent:cp_valid -> router_002:sink_valid
wire [119:0] niosii_core_instruction_master_agent_cp_data; // niosII_core_instruction_master_agent:cp_data -> router_002:sink_data
wire niosii_core_instruction_master_agent_cp_ready; // router_002:sink_ready -> niosII_core_instruction_master_agent:cp_ready
wire niosii_core_instruction_master_agent_cp_startofpacket; // niosII_core_instruction_master_agent:cp_startofpacket -> router_002:sink_startofpacket
wire niosii_core_instruction_master_agent_cp_endofpacket; // niosII_core_instruction_master_agent:cp_endofpacket -> router_002:sink_endofpacket
wire sdram_s1_agent_rp_valid; // SDRAM_s1_agent:rp_valid -> router_003:sink_valid
wire [101:0] sdram_s1_agent_rp_data; // SDRAM_s1_agent:rp_data -> router_003:sink_data
wire sdram_s1_agent_rp_ready; // router_003:sink_ready -> SDRAM_s1_agent:rp_ready
wire sdram_s1_agent_rp_startofpacket; // SDRAM_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire sdram_s1_agent_rp_endofpacket; // SDRAM_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire niosii_core_debug_mem_slave_agent_rp_valid; // niosII_core_debug_mem_slave_agent:rp_valid -> router_004:sink_valid
wire [119:0] niosii_core_debug_mem_slave_agent_rp_data; // niosII_core_debug_mem_slave_agent:rp_data -> router_004:sink_data
wire niosii_core_debug_mem_slave_agent_rp_ready; // router_004:sink_ready -> niosII_core_debug_mem_slave_agent:rp_ready
wire niosii_core_debug_mem_slave_agent_rp_startofpacket; // niosII_core_debug_mem_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire niosii_core_debug_mem_slave_agent_rp_endofpacket; // niosII_core_debug_mem_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_001:sink_valid
wire [119:0] router_004_src_data; // router_004:src_data -> rsp_demux_001:sink_data
wire router_004_src_ready; // rsp_demux_001:sink_ready -> router_004:src_ready
wire [8:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_001:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire sram_s1_agent_rp_valid; // SRAM_s1_agent:rp_valid -> router_005:sink_valid
wire [119:0] sram_s1_agent_rp_data; // SRAM_s1_agent:rp_data -> router_005:sink_data
wire sram_s1_agent_rp_ready; // router_005:sink_ready -> SRAM_s1_agent:rp_ready
wire sram_s1_agent_rp_startofpacket; // SRAM_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire sram_s1_agent_rp_endofpacket; // SRAM_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_002:sink_valid
wire [119:0] router_005_src_data; // router_005:src_data -> rsp_demux_002:sink_data
wire router_005_src_ready; // rsp_demux_002:sink_ready -> router_005:src_ready
wire [8:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_002:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire jtag_avalon_jtag_slave_agent_rp_valid; // JTAG_avalon_jtag_slave_agent:rp_valid -> router_006:sink_valid
wire [119:0] jtag_avalon_jtag_slave_agent_rp_data; // JTAG_avalon_jtag_slave_agent:rp_data -> router_006:sink_data
wire jtag_avalon_jtag_slave_agent_rp_ready; // router_006:sink_ready -> JTAG_avalon_jtag_slave_agent:rp_ready
wire jtag_avalon_jtag_slave_agent_rp_startofpacket; // JTAG_avalon_jtag_slave_agent:rp_startofpacket -> router_006:sink_startofpacket
wire jtag_avalon_jtag_slave_agent_rp_endofpacket; // JTAG_avalon_jtag_slave_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_003:sink_valid
wire [119:0] router_006_src_data; // router_006:src_data -> rsp_demux_003:sink_data
wire router_006_src_ready; // rsp_demux_003:sink_ready -> router_006:src_ready
wire [8:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_003:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire uart_com_avalon_rs232_slave_agent_rp_valid; // UART_COM_avalon_rs232_slave_agent:rp_valid -> router_007:sink_valid
wire [119:0] uart_com_avalon_rs232_slave_agent_rp_data; // UART_COM_avalon_rs232_slave_agent:rp_data -> router_007:sink_data
wire uart_com_avalon_rs232_slave_agent_rp_ready; // router_007:sink_ready -> UART_COM_avalon_rs232_slave_agent:rp_ready
wire uart_com_avalon_rs232_slave_agent_rp_startofpacket; // UART_COM_avalon_rs232_slave_agent:rp_startofpacket -> router_007:sink_startofpacket
wire uart_com_avalon_rs232_slave_agent_rp_endofpacket; // UART_COM_avalon_rs232_slave_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_004:sink_valid
wire [119:0] router_007_src_data; // router_007:src_data -> rsp_demux_004:sink_data
wire router_007_src_ready; // rsp_demux_004:sink_ready -> router_007:src_ready
wire [8:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_004:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire convolution_slave_avs_s0_agent_rp_valid; // convolution_slave_avs_s0_agent:rp_valid -> router_008:sink_valid
wire [119:0] convolution_slave_avs_s0_agent_rp_data; // convolution_slave_avs_s0_agent:rp_data -> router_008:sink_data
wire convolution_slave_avs_s0_agent_rp_ready; // router_008:sink_ready -> convolution_slave_avs_s0_agent:rp_ready
wire convolution_slave_avs_s0_agent_rp_startofpacket; // convolution_slave_avs_s0_agent:rp_startofpacket -> router_008:sink_startofpacket
wire convolution_slave_avs_s0_agent_rp_endofpacket; // convolution_slave_avs_s0_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_005:sink_valid
wire [119:0] router_008_src_data; // router_008:src_data -> rsp_demux_005:sink_data
wire router_008_src_ready; // rsp_demux_005:sink_ready -> router_008:src_ready
wire [8:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_005:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire test_pipeline_avs_s0_agent_rp_valid; // Test_PipeLine_avs_s0_agent:rp_valid -> router_009:sink_valid
wire [119:0] test_pipeline_avs_s0_agent_rp_data; // Test_PipeLine_avs_s0_agent:rp_data -> router_009:sink_data
wire test_pipeline_avs_s0_agent_rp_ready; // router_009:sink_ready -> Test_PipeLine_avs_s0_agent:rp_ready
wire test_pipeline_avs_s0_agent_rp_startofpacket; // Test_PipeLine_avs_s0_agent:rp_startofpacket -> router_009:sink_startofpacket
wire test_pipeline_avs_s0_agent_rp_endofpacket; // Test_PipeLine_avs_s0_agent:rp_endofpacket -> router_009:sink_endofpacket
wire router_009_src_valid; // router_009:src_valid -> rsp_demux_006:sink_valid
wire [119:0] router_009_src_data; // router_009:src_data -> rsp_demux_006:sink_data
wire router_009_src_ready; // rsp_demux_006:sink_ready -> router_009:src_ready
wire [8:0] router_009_src_channel; // router_009:src_channel -> rsp_demux_006:sink_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire systemid_control_slave_agent_rp_valid; // SystemID_control_slave_agent:rp_valid -> router_010:sink_valid
wire [119:0] systemid_control_slave_agent_rp_data; // SystemID_control_slave_agent:rp_data -> router_010:sink_data
wire systemid_control_slave_agent_rp_ready; // router_010:sink_ready -> SystemID_control_slave_agent:rp_ready
wire systemid_control_slave_agent_rp_startofpacket; // SystemID_control_slave_agent:rp_startofpacket -> router_010:sink_startofpacket
wire systemid_control_slave_agent_rp_endofpacket; // SystemID_control_slave_agent:rp_endofpacket -> router_010:sink_endofpacket
wire router_010_src_valid; // router_010:src_valid -> rsp_demux_007:sink_valid
wire [119:0] router_010_src_data; // router_010:src_data -> rsp_demux_007:sink_data
wire router_010_src_ready; // rsp_demux_007:sink_ready -> router_010:src_ready
wire [8:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_007:sink_channel
wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_007:sink_startofpacket
wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_007:sink_endofpacket
wire sys_timer_s1_agent_rp_valid; // Sys_Timer_s1_agent:rp_valid -> router_011:sink_valid
wire [119:0] sys_timer_s1_agent_rp_data; // Sys_Timer_s1_agent:rp_data -> router_011:sink_data
wire sys_timer_s1_agent_rp_ready; // router_011:sink_ready -> Sys_Timer_s1_agent:rp_ready
wire sys_timer_s1_agent_rp_startofpacket; // Sys_Timer_s1_agent:rp_startofpacket -> router_011:sink_startofpacket
wire sys_timer_s1_agent_rp_endofpacket; // Sys_Timer_s1_agent:rp_endofpacket -> router_011:sink_endofpacket
wire router_011_src_valid; // router_011:src_valid -> rsp_demux_008:sink_valid
wire [119:0] router_011_src_data; // router_011:src_data -> rsp_demux_008:sink_data
wire router_011_src_ready; // rsp_demux_008:sink_ready -> router_011:src_ready
wire [8:0] router_011_src_channel; // router_011:src_channel -> rsp_demux_008:sink_channel
wire router_011_src_startofpacket; // router_011:src_startofpacket -> rsp_demux_008:sink_startofpacket
wire router_011_src_endofpacket; // router_011:src_endofpacket -> rsp_demux_008:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> niosII_core_data_master_limiter:cmd_sink_valid
wire [119:0] router_001_src_data; // router_001:src_data -> niosII_core_data_master_limiter:cmd_sink_data
wire router_001_src_ready; // niosII_core_data_master_limiter:cmd_sink_ready -> router_001:src_ready
wire [8:0] router_001_src_channel; // router_001:src_channel -> niosII_core_data_master_limiter:cmd_sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> niosII_core_data_master_limiter:cmd_sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> niosII_core_data_master_limiter:cmd_sink_endofpacket
wire [119:0] niosii_core_data_master_limiter_cmd_src_data; // niosII_core_data_master_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire niosii_core_data_master_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> niosII_core_data_master_limiter:cmd_src_ready
wire [8:0] niosii_core_data_master_limiter_cmd_src_channel; // niosII_core_data_master_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire niosii_core_data_master_limiter_cmd_src_startofpacket; // niosII_core_data_master_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire niosii_core_data_master_limiter_cmd_src_endofpacket; // niosII_core_data_master_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> niosII_core_data_master_limiter:rsp_sink_valid
wire [119:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> niosII_core_data_master_limiter:rsp_sink_data
wire rsp_mux_001_src_ready; // niosII_core_data_master_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire [8:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> niosII_core_data_master_limiter:rsp_sink_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> niosII_core_data_master_limiter:rsp_sink_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> niosII_core_data_master_limiter:rsp_sink_endofpacket
wire niosii_core_data_master_limiter_rsp_src_valid; // niosII_core_data_master_limiter:rsp_src_valid -> niosII_core_data_master_agent:rp_valid
wire [119:0] niosii_core_data_master_limiter_rsp_src_data; // niosII_core_data_master_limiter:rsp_src_data -> niosII_core_data_master_agent:rp_data
wire niosii_core_data_master_limiter_rsp_src_ready; // niosII_core_data_master_agent:rp_ready -> niosII_core_data_master_limiter:rsp_src_ready
wire [8:0] niosii_core_data_master_limiter_rsp_src_channel; // niosII_core_data_master_limiter:rsp_src_channel -> niosII_core_data_master_agent:rp_channel
wire niosii_core_data_master_limiter_rsp_src_startofpacket; // niosII_core_data_master_limiter:rsp_src_startofpacket -> niosII_core_data_master_agent:rp_startofpacket
wire niosii_core_data_master_limiter_rsp_src_endofpacket; // niosII_core_data_master_limiter:rsp_src_endofpacket -> niosII_core_data_master_agent:rp_endofpacket
wire router_002_src_valid; // router_002:src_valid -> niosII_core_instruction_master_limiter:cmd_sink_valid
wire [119:0] router_002_src_data; // router_002:src_data -> niosII_core_instruction_master_limiter:cmd_sink_data
wire router_002_src_ready; // niosII_core_instruction_master_limiter:cmd_sink_ready -> router_002:src_ready
wire [8:0] router_002_src_channel; // router_002:src_channel -> niosII_core_instruction_master_limiter:cmd_sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> niosII_core_instruction_master_limiter:cmd_sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> niosII_core_instruction_master_limiter:cmd_sink_endofpacket
wire [119:0] niosii_core_instruction_master_limiter_cmd_src_data; // niosII_core_instruction_master_limiter:cmd_src_data -> cmd_demux_002:sink_data
wire niosii_core_instruction_master_limiter_cmd_src_ready; // cmd_demux_002:sink_ready -> niosII_core_instruction_master_limiter:cmd_src_ready
wire [8:0] niosii_core_instruction_master_limiter_cmd_src_channel; // niosII_core_instruction_master_limiter:cmd_src_channel -> cmd_demux_002:sink_channel
wire niosii_core_instruction_master_limiter_cmd_src_startofpacket; // niosII_core_instruction_master_limiter:cmd_src_startofpacket -> cmd_demux_002:sink_startofpacket
wire niosii_core_instruction_master_limiter_cmd_src_endofpacket; // niosII_core_instruction_master_limiter:cmd_src_endofpacket -> cmd_demux_002:sink_endofpacket
wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> niosII_core_instruction_master_limiter:rsp_sink_valid
wire [119:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> niosII_core_instruction_master_limiter:rsp_sink_data
wire rsp_mux_002_src_ready; // niosII_core_instruction_master_limiter:rsp_sink_ready -> rsp_mux_002:src_ready
wire [8:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> niosII_core_instruction_master_limiter:rsp_sink_channel
wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> niosII_core_instruction_master_limiter:rsp_sink_startofpacket
wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> niosII_core_instruction_master_limiter:rsp_sink_endofpacket
wire niosii_core_instruction_master_limiter_rsp_src_valid; // niosII_core_instruction_master_limiter:rsp_src_valid -> niosII_core_instruction_master_agent:rp_valid
wire [119:0] niosii_core_instruction_master_limiter_rsp_src_data; // niosII_core_instruction_master_limiter:rsp_src_data -> niosII_core_instruction_master_agent:rp_data
wire niosii_core_instruction_master_limiter_rsp_src_ready; // niosII_core_instruction_master_agent:rp_ready -> niosII_core_instruction_master_limiter:rsp_src_ready
wire [8:0] niosii_core_instruction_master_limiter_rsp_src_channel; // niosII_core_instruction_master_limiter:rsp_src_channel -> niosII_core_instruction_master_agent:rp_channel
wire niosii_core_instruction_master_limiter_rsp_src_startofpacket; // niosII_core_instruction_master_limiter:rsp_src_startofpacket -> niosII_core_instruction_master_agent:rp_startofpacket
wire niosii_core_instruction_master_limiter_rsp_src_endofpacket; // niosII_core_instruction_master_limiter:rsp_src_endofpacket -> niosII_core_instruction_master_agent:rp_endofpacket
wire sdram_s1_burst_adapter_source0_valid; // SDRAM_s1_burst_adapter:source0_valid -> SDRAM_s1_agent:cp_valid
wire [101:0] sdram_s1_burst_adapter_source0_data; // SDRAM_s1_burst_adapter:source0_data -> SDRAM_s1_agent:cp_data
wire sdram_s1_burst_adapter_source0_ready; // SDRAM_s1_agent:cp_ready -> SDRAM_s1_burst_adapter:source0_ready
wire [8:0] sdram_s1_burst_adapter_source0_channel; // SDRAM_s1_burst_adapter:source0_channel -> SDRAM_s1_agent:cp_channel
wire sdram_s1_burst_adapter_source0_startofpacket; // SDRAM_s1_burst_adapter:source0_startofpacket -> SDRAM_s1_agent:cp_startofpacket
wire sdram_s1_burst_adapter_source0_endofpacket; // SDRAM_s1_burst_adapter:source0_endofpacket -> SDRAM_s1_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> niosII_core_debug_mem_slave_burst_adapter:sink0_valid
wire [119:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> niosII_core_debug_mem_slave_burst_adapter:sink0_data
wire cmd_mux_001_src_ready; // niosII_core_debug_mem_slave_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
wire [8:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> niosII_core_debug_mem_slave_burst_adapter:sink0_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> niosII_core_debug_mem_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> niosII_core_debug_mem_slave_burst_adapter:sink0_endofpacket
wire niosii_core_debug_mem_slave_burst_adapter_source0_valid; // niosII_core_debug_mem_slave_burst_adapter:source0_valid -> niosII_core_debug_mem_slave_agent:cp_valid
wire [119:0] niosii_core_debug_mem_slave_burst_adapter_source0_data; // niosII_core_debug_mem_slave_burst_adapter:source0_data -> niosII_core_debug_mem_slave_agent:cp_data
wire niosii_core_debug_mem_slave_burst_adapter_source0_ready; // niosII_core_debug_mem_slave_agent:cp_ready -> niosII_core_debug_mem_slave_burst_adapter:source0_ready
wire [8:0] niosii_core_debug_mem_slave_burst_adapter_source0_channel; // niosII_core_debug_mem_slave_burst_adapter:source0_channel -> niosII_core_debug_mem_slave_agent:cp_channel
wire niosii_core_debug_mem_slave_burst_adapter_source0_startofpacket; // niosII_core_debug_mem_slave_burst_adapter:source0_startofpacket -> niosII_core_debug_mem_slave_agent:cp_startofpacket
wire niosii_core_debug_mem_slave_burst_adapter_source0_endofpacket; // niosII_core_debug_mem_slave_burst_adapter:source0_endofpacket -> niosII_core_debug_mem_slave_agent:cp_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> SRAM_s1_burst_adapter:sink0_valid
wire [119:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> SRAM_s1_burst_adapter:sink0_data
wire cmd_mux_002_src_ready; // SRAM_s1_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
wire [8:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> SRAM_s1_burst_adapter:sink0_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> SRAM_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> SRAM_s1_burst_adapter:sink0_endofpacket
wire sram_s1_burst_adapter_source0_valid; // SRAM_s1_burst_adapter:source0_valid -> SRAM_s1_agent:cp_valid
wire [119:0] sram_s1_burst_adapter_source0_data; // SRAM_s1_burst_adapter:source0_data -> SRAM_s1_agent:cp_data
wire sram_s1_burst_adapter_source0_ready; // SRAM_s1_agent:cp_ready -> SRAM_s1_burst_adapter:source0_ready
wire [8:0] sram_s1_burst_adapter_source0_channel; // SRAM_s1_burst_adapter:source0_channel -> SRAM_s1_agent:cp_channel
wire sram_s1_burst_adapter_source0_startofpacket; // SRAM_s1_burst_adapter:source0_startofpacket -> SRAM_s1_agent:cp_startofpacket
wire sram_s1_burst_adapter_source0_endofpacket; // SRAM_s1_burst_adapter:source0_endofpacket -> SRAM_s1_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> JTAG_avalon_jtag_slave_burst_adapter:sink0_valid
wire [119:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> JTAG_avalon_jtag_slave_burst_adapter:sink0_data
wire cmd_mux_003_src_ready; // JTAG_avalon_jtag_slave_burst_adapter:sink0_ready -> cmd_mux_003:src_ready
wire [8:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> JTAG_avalon_jtag_slave_burst_adapter:sink0_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> JTAG_avalon_jtag_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> JTAG_avalon_jtag_slave_burst_adapter:sink0_endofpacket
wire jtag_avalon_jtag_slave_burst_adapter_source0_valid; // JTAG_avalon_jtag_slave_burst_adapter:source0_valid -> JTAG_avalon_jtag_slave_agent:cp_valid
wire [119:0] jtag_avalon_jtag_slave_burst_adapter_source0_data; // JTAG_avalon_jtag_slave_burst_adapter:source0_data -> JTAG_avalon_jtag_slave_agent:cp_data
wire jtag_avalon_jtag_slave_burst_adapter_source0_ready; // JTAG_avalon_jtag_slave_agent:cp_ready -> JTAG_avalon_jtag_slave_burst_adapter:source0_ready
wire [8:0] jtag_avalon_jtag_slave_burst_adapter_source0_channel; // JTAG_avalon_jtag_slave_burst_adapter:source0_channel -> JTAG_avalon_jtag_slave_agent:cp_channel
wire jtag_avalon_jtag_slave_burst_adapter_source0_startofpacket; // JTAG_avalon_jtag_slave_burst_adapter:source0_startofpacket -> JTAG_avalon_jtag_slave_agent:cp_startofpacket
wire jtag_avalon_jtag_slave_burst_adapter_source0_endofpacket; // JTAG_avalon_jtag_slave_burst_adapter:source0_endofpacket -> JTAG_avalon_jtag_slave_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> UART_COM_avalon_rs232_slave_burst_adapter:sink0_valid
wire [119:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> UART_COM_avalon_rs232_slave_burst_adapter:sink0_data
wire cmd_mux_004_src_ready; // UART_COM_avalon_rs232_slave_burst_adapter:sink0_ready -> cmd_mux_004:src_ready
wire [8:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> UART_COM_avalon_rs232_slave_burst_adapter:sink0_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> UART_COM_avalon_rs232_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> UART_COM_avalon_rs232_slave_burst_adapter:sink0_endofpacket
wire uart_com_avalon_rs232_slave_burst_adapter_source0_valid; // UART_COM_avalon_rs232_slave_burst_adapter:source0_valid -> UART_COM_avalon_rs232_slave_agent:cp_valid
wire [119:0] uart_com_avalon_rs232_slave_burst_adapter_source0_data; // UART_COM_avalon_rs232_slave_burst_adapter:source0_data -> UART_COM_avalon_rs232_slave_agent:cp_data
wire uart_com_avalon_rs232_slave_burst_adapter_source0_ready; // UART_COM_avalon_rs232_slave_agent:cp_ready -> UART_COM_avalon_rs232_slave_burst_adapter:source0_ready
wire [8:0] uart_com_avalon_rs232_slave_burst_adapter_source0_channel; // UART_COM_avalon_rs232_slave_burst_adapter:source0_channel -> UART_COM_avalon_rs232_slave_agent:cp_channel
wire uart_com_avalon_rs232_slave_burst_adapter_source0_startofpacket; // UART_COM_avalon_rs232_slave_burst_adapter:source0_startofpacket -> UART_COM_avalon_rs232_slave_agent:cp_startofpacket
wire uart_com_avalon_rs232_slave_burst_adapter_source0_endofpacket; // UART_COM_avalon_rs232_slave_burst_adapter:source0_endofpacket -> UART_COM_avalon_rs232_slave_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> convolution_slave_avs_s0_burst_adapter:sink0_valid
wire [119:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> convolution_slave_avs_s0_burst_adapter:sink0_data
wire cmd_mux_005_src_ready; // convolution_slave_avs_s0_burst_adapter:sink0_ready -> cmd_mux_005:src_ready
wire [8:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> convolution_slave_avs_s0_burst_adapter:sink0_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> convolution_slave_avs_s0_burst_adapter:sink0_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> convolution_slave_avs_s0_burst_adapter:sink0_endofpacket
wire convolution_slave_avs_s0_burst_adapter_source0_valid; // convolution_slave_avs_s0_burst_adapter:source0_valid -> convolution_slave_avs_s0_agent:cp_valid
wire [119:0] convolution_slave_avs_s0_burst_adapter_source0_data; // convolution_slave_avs_s0_burst_adapter:source0_data -> convolution_slave_avs_s0_agent:cp_data
wire convolution_slave_avs_s0_burst_adapter_source0_ready; // convolution_slave_avs_s0_agent:cp_ready -> convolution_slave_avs_s0_burst_adapter:source0_ready
wire [8:0] convolution_slave_avs_s0_burst_adapter_source0_channel; // convolution_slave_avs_s0_burst_adapter:source0_channel -> convolution_slave_avs_s0_agent:cp_channel
wire convolution_slave_avs_s0_burst_adapter_source0_startofpacket; // convolution_slave_avs_s0_burst_adapter:source0_startofpacket -> convolution_slave_avs_s0_agent:cp_startofpacket
wire convolution_slave_avs_s0_burst_adapter_source0_endofpacket; // convolution_slave_avs_s0_burst_adapter:source0_endofpacket -> convolution_slave_avs_s0_agent:cp_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> Test_PipeLine_avs_s0_burst_adapter:sink0_valid
wire [119:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> Test_PipeLine_avs_s0_burst_adapter:sink0_data
wire cmd_mux_006_src_ready; // Test_PipeLine_avs_s0_burst_adapter:sink0_ready -> cmd_mux_006:src_ready
wire [8:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> Test_PipeLine_avs_s0_burst_adapter:sink0_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> Test_PipeLine_avs_s0_burst_adapter:sink0_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> Test_PipeLine_avs_s0_burst_adapter:sink0_endofpacket
wire test_pipeline_avs_s0_burst_adapter_source0_valid; // Test_PipeLine_avs_s0_burst_adapter:source0_valid -> Test_PipeLine_avs_s0_agent:cp_valid
wire [119:0] test_pipeline_avs_s0_burst_adapter_source0_data; // Test_PipeLine_avs_s0_burst_adapter:source0_data -> Test_PipeLine_avs_s0_agent:cp_data
wire test_pipeline_avs_s0_burst_adapter_source0_ready; // Test_PipeLine_avs_s0_agent:cp_ready -> Test_PipeLine_avs_s0_burst_adapter:source0_ready
wire [8:0] test_pipeline_avs_s0_burst_adapter_source0_channel; // Test_PipeLine_avs_s0_burst_adapter:source0_channel -> Test_PipeLine_avs_s0_agent:cp_channel
wire test_pipeline_avs_s0_burst_adapter_source0_startofpacket; // Test_PipeLine_avs_s0_burst_adapter:source0_startofpacket -> Test_PipeLine_avs_s0_agent:cp_startofpacket
wire test_pipeline_avs_s0_burst_adapter_source0_endofpacket; // Test_PipeLine_avs_s0_burst_adapter:source0_endofpacket -> Test_PipeLine_avs_s0_agent:cp_endofpacket
wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> SystemID_control_slave_burst_adapter:sink0_valid
wire [119:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> SystemID_control_slave_burst_adapter:sink0_data
wire cmd_mux_007_src_ready; // SystemID_control_slave_burst_adapter:sink0_ready -> cmd_mux_007:src_ready
wire [8:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> SystemID_control_slave_burst_adapter:sink0_channel
wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> SystemID_control_slave_burst_adapter:sink0_startofpacket
wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> SystemID_control_slave_burst_adapter:sink0_endofpacket
wire systemid_control_slave_burst_adapter_source0_valid; // SystemID_control_slave_burst_adapter:source0_valid -> SystemID_control_slave_agent:cp_valid
wire [119:0] systemid_control_slave_burst_adapter_source0_data; // SystemID_control_slave_burst_adapter:source0_data -> SystemID_control_slave_agent:cp_data
wire systemid_control_slave_burst_adapter_source0_ready; // SystemID_control_slave_agent:cp_ready -> SystemID_control_slave_burst_adapter:source0_ready
wire [8:0] systemid_control_slave_burst_adapter_source0_channel; // SystemID_control_slave_burst_adapter:source0_channel -> SystemID_control_slave_agent:cp_channel
wire systemid_control_slave_burst_adapter_source0_startofpacket; // SystemID_control_slave_burst_adapter:source0_startofpacket -> SystemID_control_slave_agent:cp_startofpacket
wire systemid_control_slave_burst_adapter_source0_endofpacket; // SystemID_control_slave_burst_adapter:source0_endofpacket -> SystemID_control_slave_agent:cp_endofpacket
wire cmd_mux_008_src_valid; // cmd_mux_008:src_valid -> Sys_Timer_s1_burst_adapter:sink0_valid
wire [119:0] cmd_mux_008_src_data; // cmd_mux_008:src_data -> Sys_Timer_s1_burst_adapter:sink0_data
wire cmd_mux_008_src_ready; // Sys_Timer_s1_burst_adapter:sink0_ready -> cmd_mux_008:src_ready
wire [8:0] cmd_mux_008_src_channel; // cmd_mux_008:src_channel -> Sys_Timer_s1_burst_adapter:sink0_channel
wire cmd_mux_008_src_startofpacket; // cmd_mux_008:src_startofpacket -> Sys_Timer_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_008_src_endofpacket; // cmd_mux_008:src_endofpacket -> Sys_Timer_s1_burst_adapter:sink0_endofpacket
wire sys_timer_s1_burst_adapter_source0_valid; // Sys_Timer_s1_burst_adapter:source0_valid -> Sys_Timer_s1_agent:cp_valid
wire [119:0] sys_timer_s1_burst_adapter_source0_data; // Sys_Timer_s1_burst_adapter:source0_data -> Sys_Timer_s1_agent:cp_data
wire sys_timer_s1_burst_adapter_source0_ready; // Sys_Timer_s1_agent:cp_ready -> Sys_Timer_s1_burst_adapter:source0_ready
wire [8:0] sys_timer_s1_burst_adapter_source0_channel; // Sys_Timer_s1_burst_adapter:source0_channel -> Sys_Timer_s1_agent:cp_channel
wire sys_timer_s1_burst_adapter_source0_startofpacket; // Sys_Timer_s1_burst_adapter:source0_startofpacket -> Sys_Timer_s1_agent:cp_startofpacket
wire sys_timer_s1_burst_adapter_source0_endofpacket; // Sys_Timer_s1_burst_adapter:source0_endofpacket -> Sys_Timer_s1_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [119:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [8:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [119:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [8:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink0_valid
wire [119:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux_001:src1_ready
wire [8:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink0_valid
wire [119:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux_001:src2_ready
wire [8:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink0_valid
wire [119:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_001_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux_001:src3_ready
wire [8:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_001_src4_valid; // cmd_demux_001:src4_valid -> cmd_mux_004:sink0_valid
wire [119:0] cmd_demux_001_src4_data; // cmd_demux_001:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_001_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux_001:src4_ready
wire [8:0] cmd_demux_001_src4_channel; // cmd_demux_001:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_001_src4_startofpacket; // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_001_src4_endofpacket; // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_001_src5_valid; // cmd_demux_001:src5_valid -> cmd_mux_005:sink0_valid
wire [119:0] cmd_demux_001_src5_data; // cmd_demux_001:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_001_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux_001:src5_ready
wire [8:0] cmd_demux_001_src5_channel; // cmd_demux_001:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_001_src5_startofpacket; // cmd_demux_001:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_001_src5_endofpacket; // cmd_demux_001:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_001_src6_valid; // cmd_demux_001:src6_valid -> cmd_mux_006:sink0_valid
wire [119:0] cmd_demux_001_src6_data; // cmd_demux_001:src6_data -> cmd_mux_006:sink0_data
wire cmd_demux_001_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux_001:src6_ready
wire [8:0] cmd_demux_001_src6_channel; // cmd_demux_001:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_001_src6_startofpacket; // cmd_demux_001:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire cmd_demux_001_src6_endofpacket; // cmd_demux_001:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_001_src7_valid; // cmd_demux_001:src7_valid -> cmd_mux_007:sink0_valid
wire [119:0] cmd_demux_001_src7_data; // cmd_demux_001:src7_data -> cmd_mux_007:sink0_data
wire cmd_demux_001_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux_001:src7_ready
wire [8:0] cmd_demux_001_src7_channel; // cmd_demux_001:src7_channel -> cmd_mux_007:sink0_channel
wire cmd_demux_001_src7_startofpacket; // cmd_demux_001:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
wire cmd_demux_001_src7_endofpacket; // cmd_demux_001:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
wire cmd_demux_001_src8_valid; // cmd_demux_001:src8_valid -> cmd_mux_008:sink0_valid
wire [119:0] cmd_demux_001_src8_data; // cmd_demux_001:src8_data -> cmd_mux_008:sink0_data
wire cmd_demux_001_src8_ready; // cmd_mux_008:sink0_ready -> cmd_demux_001:src8_ready
wire [8:0] cmd_demux_001_src8_channel; // cmd_demux_001:src8_channel -> cmd_mux_008:sink0_channel
wire cmd_demux_001_src8_startofpacket; // cmd_demux_001:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
wire cmd_demux_001_src8_endofpacket; // cmd_demux_001:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> cmd_mux:sink2_valid
wire [119:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> cmd_mux:sink2_data
wire cmd_demux_002_src0_ready; // cmd_mux:sink2_ready -> cmd_demux_002:src0_ready
wire [8:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> cmd_mux:sink2_channel
wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> cmd_mux:sink2_startofpacket
wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> cmd_mux:sink2_endofpacket
wire cmd_demux_002_src1_valid; // cmd_demux_002:src1_valid -> cmd_mux_001:sink1_valid
wire [119:0] cmd_demux_002_src1_data; // cmd_demux_002:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_002_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_002:src1_ready
wire [8:0] cmd_demux_002_src1_channel; // cmd_demux_002:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_002_src1_startofpacket; // cmd_demux_002:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_002_src1_endofpacket; // cmd_demux_002:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_002_src2_valid; // cmd_demux_002:src2_valid -> cmd_mux_002:sink1_valid
wire [119:0] cmd_demux_002_src2_data; // cmd_demux_002:src2_data -> cmd_mux_002:sink1_data
wire cmd_demux_002_src2_ready; // cmd_mux_002:sink1_ready -> cmd_demux_002:src2_ready
wire [8:0] cmd_demux_002_src2_channel; // cmd_demux_002:src2_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_002_src2_startofpacket; // cmd_demux_002:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_002_src2_endofpacket; // cmd_demux_002:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [119:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [8:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [119:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [8:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_src2_valid; // rsp_demux:src2_valid -> rsp_mux_002:sink0_valid
wire [119:0] rsp_demux_src2_data; // rsp_demux:src2_data -> rsp_mux_002:sink0_data
wire rsp_demux_src2_ready; // rsp_mux_002:sink0_ready -> rsp_demux:src2_ready
wire [8:0] rsp_demux_src2_channel; // rsp_demux:src2_channel -> rsp_mux_002:sink0_channel
wire rsp_demux_src2_startofpacket; // rsp_demux:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
wire rsp_demux_src2_endofpacket; // rsp_demux:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux_001:sink1_valid
wire [119:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux_001:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src0_ready
wire [8:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_002:sink1_valid
wire [119:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_002:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_002:sink1_ready -> rsp_demux_001:src1_ready
wire [8:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_002:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_002:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_002:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux_001:sink2_valid
wire [119:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux_001:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src0_ready
wire [8:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_002:sink2_valid
wire [119:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_002:sink2_data
wire rsp_demux_002_src1_ready; // rsp_mux_002:sink2_ready -> rsp_demux_002:src1_ready
wire [8:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_002:sink2_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_002:sink2_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_002:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux_001:sink3_valid
wire [119:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux_001:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src0_ready
wire [8:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux_001:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux_001:sink4_valid
wire [119:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux_001:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux_001:sink4_ready -> rsp_demux_004:src0_ready
wire [8:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux_001:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux_001:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux_001:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux_001:sink5_valid
wire [119:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux_001:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux_001:sink5_ready -> rsp_demux_005:src0_ready
wire [8:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux_001:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux_001:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux_001:sink5_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux_001:sink6_valid
wire [119:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux_001:sink6_data
wire rsp_demux_006_src0_ready; // rsp_mux_001:sink6_ready -> rsp_demux_006:src0_ready
wire [8:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux_001:sink6_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux_001:sink6_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux_001:sink6_endofpacket
wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux_001:sink7_valid
wire [119:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux_001:sink7_data
wire rsp_demux_007_src0_ready; // rsp_mux_001:sink7_ready -> rsp_demux_007:src0_ready
wire [8:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux_001:sink7_channel
wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux_001:sink7_startofpacket
wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux_001:sink7_endofpacket
wire rsp_demux_008_src0_valid; // rsp_demux_008:src0_valid -> rsp_mux_001:sink8_valid
wire [119:0] rsp_demux_008_src0_data; // rsp_demux_008:src0_data -> rsp_mux_001:sink8_data
wire rsp_demux_008_src0_ready; // rsp_mux_001:sink8_ready -> rsp_demux_008:src0_ready
wire [8:0] rsp_demux_008_src0_channel; // rsp_demux_008:src0_channel -> rsp_mux_001:sink8_channel
wire rsp_demux_008_src0_startofpacket; // rsp_demux_008:src0_startofpacket -> rsp_mux_001:sink8_startofpacket
wire rsp_demux_008_src0_endofpacket; // rsp_demux_008:src0_endofpacket -> rsp_mux_001:sink8_endofpacket
wire router_003_src_valid; // router_003:src_valid -> SDRAM_s1_rsp_width_adapter:in_valid
wire [101:0] router_003_src_data; // router_003:src_data -> SDRAM_s1_rsp_width_adapter:in_data
wire router_003_src_ready; // SDRAM_s1_rsp_width_adapter:in_ready -> router_003:src_ready
wire [8:0] router_003_src_channel; // router_003:src_channel -> SDRAM_s1_rsp_width_adapter:in_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> SDRAM_s1_rsp_width_adapter:in_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> SDRAM_s1_rsp_width_adapter:in_endofpacket
wire sdram_s1_rsp_width_adapter_src_valid; // SDRAM_s1_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire [119:0] sdram_s1_rsp_width_adapter_src_data; // SDRAM_s1_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire sdram_s1_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> SDRAM_s1_rsp_width_adapter:out_ready
wire [8:0] sdram_s1_rsp_width_adapter_src_channel; // SDRAM_s1_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
wire sdram_s1_rsp_width_adapter_src_startofpacket; // SDRAM_s1_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire sdram_s1_rsp_width_adapter_src_endofpacket; // SDRAM_s1_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> SDRAM_s1_cmd_width_adapter:in_valid
wire [119:0] cmd_mux_src_data; // cmd_mux:src_data -> SDRAM_s1_cmd_width_adapter:in_data
wire cmd_mux_src_ready; // SDRAM_s1_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire [8:0] cmd_mux_src_channel; // cmd_mux:src_channel -> SDRAM_s1_cmd_width_adapter:in_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> SDRAM_s1_cmd_width_adapter:in_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> SDRAM_s1_cmd_width_adapter:in_endofpacket
wire sdram_s1_cmd_width_adapter_src_valid; // SDRAM_s1_cmd_width_adapter:out_valid -> SDRAM_s1_burst_adapter:sink0_valid
wire [101:0] sdram_s1_cmd_width_adapter_src_data; // SDRAM_s1_cmd_width_adapter:out_data -> SDRAM_s1_burst_adapter:sink0_data
wire sdram_s1_cmd_width_adapter_src_ready; // SDRAM_s1_burst_adapter:sink0_ready -> SDRAM_s1_cmd_width_adapter:out_ready
wire [8:0] sdram_s1_cmd_width_adapter_src_channel; // SDRAM_s1_cmd_width_adapter:out_channel -> SDRAM_s1_burst_adapter:sink0_channel
wire sdram_s1_cmd_width_adapter_src_startofpacket; // SDRAM_s1_cmd_width_adapter:out_startofpacket -> SDRAM_s1_burst_adapter:sink0_startofpacket
wire sdram_s1_cmd_width_adapter_src_endofpacket; // SDRAM_s1_cmd_width_adapter:out_endofpacket -> SDRAM_s1_burst_adapter:sink0_endofpacket
wire [8:0] niosii_core_data_master_limiter_cmd_valid_data; // niosII_core_data_master_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
wire [8:0] niosii_core_instruction_master_limiter_cmd_valid_data; // niosII_core_instruction_master_limiter:cmd_src_valid -> cmd_demux_002:sink_valid
wire sdram_s1_agent_rdata_fifo_out_valid; // SDRAM_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
wire [17:0] sdram_s1_agent_rdata_fifo_out_data; // SDRAM_s1_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
wire sdram_s1_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> SDRAM_s1_agent_rdata_fifo:out_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> SDRAM_s1_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> SDRAM_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // SDRAM_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> SDRAM_s1_agent:rdata_fifo_sink_error
wire niosii_core_debug_mem_slave_agent_rdata_fifo_src_valid; // niosII_core_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] niosii_core_debug_mem_slave_agent_rdata_fifo_src_data; // niosII_core_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire niosii_core_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> niosII_core_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> niosII_core_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> niosII_core_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // niosII_core_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> niosII_core_debug_mem_slave_agent:rdata_fifo_sink_error
wire sram_s1_agent_rdata_fifo_src_valid; // SRAM_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] sram_s1_agent_rdata_fifo_src_data; // SRAM_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire sram_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> SRAM_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> SRAM_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> SRAM_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // SRAM_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> SRAM_s1_agent:rdata_fifo_sink_error
wire jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid; // JTAG_avalon_jtag_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] jtag_avalon_jtag_slave_agent_rdata_fifo_src_data; // JTAG_avalon_jtag_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> JTAG_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> JTAG_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> JTAG_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // JTAG_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> JTAG_avalon_jtag_slave_agent:rdata_fifo_sink_error
wire uart_com_avalon_rs232_slave_agent_rdata_fifo_src_valid; // UART_COM_avalon_rs232_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] uart_com_avalon_rs232_slave_agent_rdata_fifo_src_data; // UART_COM_avalon_rs232_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire uart_com_avalon_rs232_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> UART_COM_avalon_rs232_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> UART_COM_avalon_rs232_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> UART_COM_avalon_rs232_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // UART_COM_avalon_rs232_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> UART_COM_avalon_rs232_slave_agent:rdata_fifo_sink_error
wire convolution_slave_avs_s0_agent_rdata_fifo_src_valid; // convolution_slave_avs_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
wire [33:0] convolution_slave_avs_s0_agent_rdata_fifo_src_data; // convolution_slave_avs_s0_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
wire convolution_slave_avs_s0_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> convolution_slave_avs_s0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> convolution_slave_avs_s0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> convolution_slave_avs_s0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_005_out_0_ready; // convolution_slave_avs_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> convolution_slave_avs_s0_agent:rdata_fifo_sink_error
wire test_pipeline_avs_s0_agent_rdata_fifo_src_valid; // Test_PipeLine_avs_s0_agent:rdata_fifo_src_valid -> avalon_st_adapter_006:in_0_valid
wire [33:0] test_pipeline_avs_s0_agent_rdata_fifo_src_data; // Test_PipeLine_avs_s0_agent:rdata_fifo_src_data -> avalon_st_adapter_006:in_0_data
wire test_pipeline_avs_s0_agent_rdata_fifo_src_ready; // avalon_st_adapter_006:in_0_ready -> Test_PipeLine_avs_s0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> Test_PipeLine_avs_s0_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> Test_PipeLine_avs_s0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_006_out_0_ready; // Test_PipeLine_avs_s0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> Test_PipeLine_avs_s0_agent:rdata_fifo_sink_error
wire systemid_control_slave_agent_rdata_fifo_src_valid; // SystemID_control_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_007:in_0_valid
wire [33:0] systemid_control_slave_agent_rdata_fifo_src_data; // SystemID_control_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_007:in_0_data
wire systemid_control_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_007:in_0_ready -> SystemID_control_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_007_out_0_valid; // avalon_st_adapter_007:out_0_valid -> SystemID_control_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_007_out_0_data; // avalon_st_adapter_007:out_0_data -> SystemID_control_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_007_out_0_ready; // SystemID_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
wire [0:0] avalon_st_adapter_007_out_0_error; // avalon_st_adapter_007:out_0_error -> SystemID_control_slave_agent:rdata_fifo_sink_error
wire sys_timer_s1_agent_rdata_fifo_src_valid; // Sys_Timer_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_008:in_0_valid
wire [33:0] sys_timer_s1_agent_rdata_fifo_src_data; // Sys_Timer_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_008:in_0_data
wire sys_timer_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_008:in_0_ready -> Sys_Timer_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_008_out_0_valid; // avalon_st_adapter_008:out_0_valid -> Sys_Timer_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_008_out_0_data; // avalon_st_adapter_008:out_0_data -> Sys_Timer_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_008_out_0_ready; // Sys_Timer_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_008:out_0_ready
wire [0:0] avalon_st_adapter_008_out_0_error; // avalon_st_adapter_008:out_0_error -> Sys_Timer_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (32),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (8),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (10),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) test_pipeline_avm_m0_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (test_pipeline_avm_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (test_pipeline_avm_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (test_pipeline_avm_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (test_pipeline_avm_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (test_pipeline_avm_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (test_pipeline_avm_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (test_pipeline_avm_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (test_pipeline_avm_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (test_pipeline_avm_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (test_pipeline_avm_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (test_pipeline_avm_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (Test_PipeLine_avm_m0_address), // avalon_anti_master_0.address
.av_waitrequest (Test_PipeLine_avm_m0_waitrequest), // .waitrequest
.av_burstcount (Test_PipeLine_avm_m0_burstcount), // .burstcount
.av_read (Test_PipeLine_avm_m0_read), // .read
.av_readdata (Test_PipeLine_avm_m0_readdata), // .readdata
.av_readdatavalid (Test_PipeLine_avm_m0_readdatavalid), // .readdatavalid
.av_write (Test_PipeLine_avm_m0_write), // .write
.av_writedata (Test_PipeLine_avm_m0_writedata), // .writedata
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (4),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (6),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) niosii_core_data_master_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (niosii_core_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (niosii_core_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (niosii_core_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (niosii_core_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (niosii_core_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (niosii_core_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (niosii_core_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (niosii_core_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (niosii_core_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (niosii_core_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (niosii_core_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (niosII_core_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (niosII_core_data_master_waitrequest), // .waitrequest
.av_burstcount (niosII_core_data_master_burstcount), // .burstcount
.av_byteenable (niosII_core_data_master_byteenable), // .byteenable
.av_read (niosII_core_data_master_read), // .read
.av_readdata (niosII_core_data_master_readdata), // .readdata
.av_readdatavalid (niosII_core_data_master_readdatavalid), // .readdatavalid
.av_write (niosII_core_data_master_write), // .write
.av_writedata (niosII_core_data_master_writedata), // .writedata
.av_debugaccess (niosII_core_data_master_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (4),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (6),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) niosii_core_instruction_master_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (niosii_core_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (niosii_core_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (niosii_core_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (niosii_core_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (niosii_core_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (niosii_core_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (niosii_core_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (niosii_core_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (niosii_core_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (niosii_core_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (niosii_core_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (niosII_core_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (niosII_core_instruction_master_waitrequest), // .waitrequest
.av_burstcount (niosII_core_instruction_master_burstcount), // .burstcount
.av_read (niosII_core_instruction_master_read), // .read
.av_readdata (niosII_core_instruction_master_readdata), // .readdata
.av_readdatavalid (niosII_core_instruction_master_readdatavalid), // .readdatavalid
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_s1_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.uav_read (sdram_s1_agent_m0_read), // .read
.uav_write (sdram_s1_agent_m0_write), // .write
.uav_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_s1_agent_m0_readdata), // .readdata
.uav_writedata (sdram_s1_agent_m0_writedata), // .writedata
.uav_lock (sdram_s1_agent_m0_lock), // .lock
.uav_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.av_address (SDRAM_s1_address), // avalon_anti_slave_0.address
.av_write (SDRAM_s1_write), // .write
.av_read (SDRAM_s1_read), // .read
.av_readdata (SDRAM_s1_readdata), // .readdata
.av_writedata (SDRAM_s1_writedata), // .writedata
.av_byteenable (SDRAM_s1_byteenable), // .byteenable
.av_readdatavalid (SDRAM_s1_readdatavalid), // .readdatavalid
.av_waitrequest (SDRAM_s1_waitrequest), // .waitrequest
.av_chipselect (SDRAM_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) niosii_core_debug_mem_slave_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (niosii_core_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (niosii_core_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (niosii_core_debug_mem_slave_agent_m0_read), // .read
.uav_write (niosii_core_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (niosii_core_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (niosii_core_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (niosii_core_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (niosii_core_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (niosii_core_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (niosii_core_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (niosii_core_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (niosII_core_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (niosII_core_debug_mem_slave_write), // .write
.av_read (niosII_core_debug_mem_slave_read), // .read
.av_readdata (niosII_core_debug_mem_slave_readdata), // .readdata
.av_writedata (niosII_core_debug_mem_slave_writedata), // .writedata
.av_byteenable (niosII_core_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (niosII_core_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (niosII_core_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (15),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_s1_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_s1_agent_m0_read), // .read
.uav_write (sram_s1_agent_m0_write), // .write
.uav_waitrequest (sram_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_s1_agent_m0_debugaccess), // .debugaccess
.av_address (SRAM_s1_address), // avalon_anti_slave_0.address
.av_write (SRAM_s1_write), // .write
.av_readdata (SRAM_s1_readdata), // .readdata
.av_writedata (SRAM_s1_writedata), // .writedata
.av_byteenable (SRAM_s1_byteenable), // .byteenable
.av_chipselect (SRAM_s1_chipselect), // .chipselect
.av_clken (SRAM_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_avalon_jtag_slave_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (JTAG_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (JTAG_avalon_jtag_slave_write), // .write
.av_read (JTAG_avalon_jtag_slave_read), // .read
.av_readdata (JTAG_avalon_jtag_slave_readdata), // .readdata
.av_writedata (JTAG_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (JTAG_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (JTAG_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_com_avalon_rs232_slave_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_com_avalon_rs232_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_com_avalon_rs232_slave_agent_m0_burstcount), // .burstcount
.uav_read (uart_com_avalon_rs232_slave_agent_m0_read), // .read
.uav_write (uart_com_avalon_rs232_slave_agent_m0_write), // .write
.uav_waitrequest (uart_com_avalon_rs232_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_com_avalon_rs232_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_com_avalon_rs232_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_com_avalon_rs232_slave_agent_m0_readdata), // .readdata
.uav_writedata (uart_com_avalon_rs232_slave_agent_m0_writedata), // .writedata
.uav_lock (uart_com_avalon_rs232_slave_agent_m0_lock), // .lock
.uav_debugaccess (uart_com_avalon_rs232_slave_agent_m0_debugaccess), // .debugaccess
.av_address (UART_COM_avalon_rs232_slave_address), // avalon_anti_slave_0.address
.av_write (UART_COM_avalon_rs232_slave_write), // .write
.av_read (UART_COM_avalon_rs232_slave_read), // .read
.av_readdata (UART_COM_avalon_rs232_slave_readdata), // .readdata
.av_writedata (UART_COM_avalon_rs232_slave_writedata), // .writedata
.av_byteenable (UART_COM_avalon_rs232_slave_byteenable), // .byteenable
.av_chipselect (UART_COM_avalon_rs232_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) convolution_slave_avs_s0_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (convolution_slave_avs_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (convolution_slave_avs_s0_agent_m0_burstcount), // .burstcount
.uav_read (convolution_slave_avs_s0_agent_m0_read), // .read
.uav_write (convolution_slave_avs_s0_agent_m0_write), // .write
.uav_waitrequest (convolution_slave_avs_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (convolution_slave_avs_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (convolution_slave_avs_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (convolution_slave_avs_s0_agent_m0_readdata), // .readdata
.uav_writedata (convolution_slave_avs_s0_agent_m0_writedata), // .writedata
.uav_lock (convolution_slave_avs_s0_agent_m0_lock), // .lock
.uav_debugaccess (convolution_slave_avs_s0_agent_m0_debugaccess), // .debugaccess
.av_address (convolution_slave_avs_s0_address), // avalon_anti_slave_0.address
.av_write (convolution_slave_avs_s0_write), // .write
.av_read (convolution_slave_avs_s0_read), // .read
.av_readdata (convolution_slave_avs_s0_readdata), // .readdata
.av_writedata (convolution_slave_avs_s0_writedata), // .writedata
.av_waitrequest (convolution_slave_avs_s0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) test_pipeline_avs_s0_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (test_pipeline_avs_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (test_pipeline_avs_s0_agent_m0_burstcount), // .burstcount
.uav_read (test_pipeline_avs_s0_agent_m0_read), // .read
.uav_write (test_pipeline_avs_s0_agent_m0_write), // .write
.uav_waitrequest (test_pipeline_avs_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (test_pipeline_avs_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (test_pipeline_avs_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (test_pipeline_avs_s0_agent_m0_readdata), // .readdata
.uav_writedata (test_pipeline_avs_s0_agent_m0_writedata), // .writedata
.uav_lock (test_pipeline_avs_s0_agent_m0_lock), // .lock
.uav_debugaccess (test_pipeline_avs_s0_agent_m0_debugaccess), // .debugaccess
.av_address (Test_PipeLine_avs_s0_address), // avalon_anti_slave_0.address
.av_write (Test_PipeLine_avs_s0_write), // .write
.av_read (Test_PipeLine_avs_s0_read), // .read
.av_readdata (Test_PipeLine_avs_s0_readdata), // .readdata
.av_writedata (Test_PipeLine_avs_s0_writedata), // .writedata
.av_waitrequest (Test_PipeLine_avs_s0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) systemid_control_slave_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (systemid_control_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (systemid_control_slave_agent_m0_burstcount), // .burstcount
.uav_read (systemid_control_slave_agent_m0_read), // .read
.uav_write (systemid_control_slave_agent_m0_write), // .write
.uav_waitrequest (systemid_control_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (systemid_control_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (systemid_control_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (systemid_control_slave_agent_m0_readdata), // .readdata
.uav_writedata (systemid_control_slave_agent_m0_writedata), // .writedata
.uav_lock (systemid_control_slave_agent_m0_lock), // .lock
.uav_debugaccess (systemid_control_slave_agent_m0_debugaccess), // .debugaccess
.av_address (SystemID_control_slave_address), // avalon_anti_slave_0.address
.av_readdata (SystemID_control_slave_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (32),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sys_timer_s1_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sys_timer_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sys_timer_s1_agent_m0_burstcount), // .burstcount
.uav_read (sys_timer_s1_agent_m0_read), // .read
.uav_write (sys_timer_s1_agent_m0_write), // .write
.uav_waitrequest (sys_timer_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sys_timer_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sys_timer_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sys_timer_s1_agent_m0_readdata), // .readdata
.uav_writedata (sys_timer_s1_agent_m0_writedata), // .writedata
.uav_lock (sys_timer_s1_agent_m0_lock), // .lock
.uav_debugaccess (sys_timer_s1_agent_m0_debugaccess), // .debugaccess
.av_address (Sys_Timer_s1_address), // avalon_anti_slave_0.address
.av_write (Sys_Timer_s1_write), // .write
.av_readdata (Sys_Timer_s1_readdata), // .readdata
.av_writedata (Sys_Timer_s1_writedata), // .writedata
.av_chipselect (Sys_Timer_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_QOS_H (98),
.PKT_QOS_L (98),
.PKT_DATA_SIDEBAND_H (96),
.PKT_DATA_SIDEBAND_L (96),
.PKT_ADDR_SIDEBAND_H (95),
.PKT_ADDR_SIDEBAND_L (95),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_CACHE_H (114),
.PKT_CACHE_L (111),
.PKT_THREAD_ID_H (107),
.PKT_THREAD_ID_L (107),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.AV_BURSTCOUNT_W (10),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (63),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) test_pipeline_avm_m0_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (test_pipeline_avm_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (test_pipeline_avm_m0_translator_avalon_universal_master_0_write), // .write
.av_read (test_pipeline_avm_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (test_pipeline_avm_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (test_pipeline_avm_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (test_pipeline_avm_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (test_pipeline_avm_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (test_pipeline_avm_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (test_pipeline_avm_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (test_pipeline_avm_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (test_pipeline_avm_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (test_pipeline_avm_m0_agent_cp_valid), // cp.valid
.cp_data (test_pipeline_avm_m0_agent_cp_data), // .data
.cp_startofpacket (test_pipeline_avm_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (test_pipeline_avm_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (test_pipeline_avm_m0_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_QOS_H (98),
.PKT_QOS_L (98),
.PKT_DATA_SIDEBAND_H (96),
.PKT_DATA_SIDEBAND_L (96),
.PKT_ADDR_SIDEBAND_H (95),
.PKT_ADDR_SIDEBAND_L (95),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_CACHE_H (114),
.PKT_CACHE_L (111),
.PKT_THREAD_ID_H (107),
.PKT_THREAD_ID_L (107),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.AV_BURSTCOUNT_W (6),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (63),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) niosii_core_data_master_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (niosii_core_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (niosii_core_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (niosii_core_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (niosii_core_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (niosii_core_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (niosii_core_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (niosii_core_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (niosii_core_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (niosii_core_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (niosii_core_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (niosii_core_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (niosii_core_data_master_agent_cp_valid), // cp.valid
.cp_data (niosii_core_data_master_agent_cp_data), // .data
.cp_startofpacket (niosii_core_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (niosii_core_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (niosii_core_data_master_agent_cp_ready), // .ready
.rp_valid (niosii_core_data_master_limiter_rsp_src_valid), // rp.valid
.rp_data (niosii_core_data_master_limiter_rsp_src_data), // .data
.rp_channel (niosii_core_data_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (niosii_core_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (niosii_core_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (niosii_core_data_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_QOS_H (98),
.PKT_QOS_L (98),
.PKT_DATA_SIDEBAND_H (96),
.PKT_DATA_SIDEBAND_L (96),
.PKT_ADDR_SIDEBAND_H (95),
.PKT_ADDR_SIDEBAND_L (95),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_CACHE_H (114),
.PKT_CACHE_L (111),
.PKT_THREAD_ID_H (107),
.PKT_THREAD_ID_L (107),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_EXCLUSIVE (73),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.AV_BURSTCOUNT_W (6),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (2),
.BURSTWRAP_VALUE (31),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) niosii_core_instruction_master_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (niosii_core_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (niosii_core_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (niosii_core_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (niosii_core_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (niosii_core_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (niosii_core_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (niosii_core_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (niosii_core_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (niosii_core_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (niosii_core_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (niosii_core_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (niosii_core_instruction_master_agent_cp_valid), // cp.valid
.cp_data (niosii_core_instruction_master_agent_cp_data), // .data
.cp_startofpacket (niosii_core_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (niosii_core_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (niosii_core_instruction_master_agent_cp_ready), // .ready
.rp_valid (niosii_core_instruction_master_limiter_rsp_src_valid), // rp.valid
.rp_data (niosii_core_instruction_master_limiter_rsp_src_data), // .data
.rp_channel (niosii_core_instruction_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (niosii_core_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (niosii_core_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (niosii_core_instruction_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (101),
.PKT_ORI_BURST_SIZE_L (99),
.PKT_RESPONSE_STATUS_H (98),
.PKT_RESPONSE_STATUS_L (97),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_TRANS_LOCK (54),
.PKT_BEGIN_BURST (79),
.PKT_PROTECTION_H (92),
.PKT_PROTECTION_L (90),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (66),
.PKT_BYTE_CNT_H (65),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (84),
.PKT_SRC_ID_L (81),
.PKT_DEST_ID_H (88),
.PKT_DEST_ID_L (85),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (9),
.ST_DATA_W (102),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sdram_s1_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sdram_s1_agent_m0_address), // m0.address
.m0_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_s1_agent_m0_lock), // .lock
.m0_readdata (sdram_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_s1_agent_m0_read), // .read
.m0_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_s1_agent_m0_writedata), // .writedata
.m0_write (sdram_s1_agent_m0_write), // .write
.rp_endofpacket (sdram_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_s1_agent_rp_ready), // .ready
.rp_valid (sdram_s1_agent_rp_valid), // .valid
.rp_data (sdram_s1_agent_rp_data), // .data
.rp_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sdram_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (sdram_s1_burst_adapter_source0_valid), // .valid
.cp_data (sdram_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (sdram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sdram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sdram_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sdram_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (sdram_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (103),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rf_source_data), // in.data
.in_valid (sdram_s1_agent_rf_source_valid), // .valid
.in_ready (sdram_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rdata_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (9),
.ST_DATA_W (120),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) niosii_core_debug_mem_slave_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (niosii_core_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (niosii_core_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (niosii_core_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (niosii_core_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (niosii_core_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (niosii_core_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (niosii_core_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (niosii_core_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (niosii_core_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (niosii_core_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (niosii_core_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (niosii_core_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (niosii_core_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (niosii_core_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (niosii_core_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (niosii_core_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (niosii_core_debug_mem_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (niosii_core_debug_mem_slave_burst_adapter_source0_valid), // .valid
.cp_data (niosii_core_debug_mem_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (niosii_core_debug_mem_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (niosii_core_debug_mem_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (niosii_core_debug_mem_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (niosii_core_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (niosii_core_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (niosii_core_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (niosii_core_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (niosii_core_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (niosii_core_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (niosii_core_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (niosii_core_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (niosii_core_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (niosii_core_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (niosii_core_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (niosii_core_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (niosii_core_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (121),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) niosii_core_debug_mem_slave_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (niosii_core_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (niosii_core_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (niosii_core_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (niosii_core_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (niosii_core_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (niosii_core_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (niosii_core_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (niosii_core_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (niosii_core_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (niosii_core_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (9),
.ST_DATA_W (120),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sram_s1_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_s1_agent_m0_lock), // .lock
.m0_readdata (sram_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_s1_agent_m0_read), // .read
.m0_waitrequest (sram_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_s1_agent_m0_writedata), // .writedata
.m0_write (sram_s1_agent_m0_write), // .write
.rp_endofpacket (sram_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_s1_agent_rp_ready), // .ready
.rp_valid (sram_s1_agent_rp_valid), // .valid
.rp_data (sram_s1_agent_rp_data), // .data
.rp_startofpacket (sram_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sram_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (sram_s1_burst_adapter_source0_valid), // .valid
.cp_data (sram_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (sram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sram_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sram_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (sram_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (121),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_s1_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_s1_agent_rf_source_data), // in.data
.in_valid (sram_s1_agent_rf_source_valid), // .valid
.in_ready (sram_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (9),
.ST_DATA_W (120),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) jtag_avalon_jtag_slave_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (jtag_avalon_jtag_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (jtag_avalon_jtag_slave_burst_adapter_source0_valid), // .valid
.cp_data (jtag_avalon_jtag_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (jtag_avalon_jtag_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (jtag_avalon_jtag_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (jtag_avalon_jtag_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (121),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_avalon_jtag_slave_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (9),
.ST_DATA_W (120),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_com_avalon_rs232_slave_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_com_avalon_rs232_slave_agent_m0_address), // m0.address
.m0_burstcount (uart_com_avalon_rs232_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_com_avalon_rs232_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_com_avalon_rs232_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_com_avalon_rs232_slave_agent_m0_lock), // .lock
.m0_readdata (uart_com_avalon_rs232_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_com_avalon_rs232_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_com_avalon_rs232_slave_agent_m0_read), // .read
.m0_waitrequest (uart_com_avalon_rs232_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_com_avalon_rs232_slave_agent_m0_writedata), // .writedata
.m0_write (uart_com_avalon_rs232_slave_agent_m0_write), // .write
.rp_endofpacket (uart_com_avalon_rs232_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_com_avalon_rs232_slave_agent_rp_ready), // .ready
.rp_valid (uart_com_avalon_rs232_slave_agent_rp_valid), // .valid
.rp_data (uart_com_avalon_rs232_slave_agent_rp_data), // .data
.rp_startofpacket (uart_com_avalon_rs232_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (uart_com_avalon_rs232_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (uart_com_avalon_rs232_slave_burst_adapter_source0_valid), // .valid
.cp_data (uart_com_avalon_rs232_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (uart_com_avalon_rs232_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (uart_com_avalon_rs232_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (uart_com_avalon_rs232_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_com_avalon_rs232_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_com_avalon_rs232_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_com_avalon_rs232_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_com_avalon_rs232_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_com_avalon_rs232_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (uart_com_avalon_rs232_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_com_avalon_rs232_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_com_avalon_rs232_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (121),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_com_avalon_rs232_slave_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_com_avalon_rs232_slave_agent_rf_source_data), // in.data
.in_valid (uart_com_avalon_rs232_slave_agent_rf_source_valid), // .valid
.in_ready (uart_com_avalon_rs232_slave_agent_rf_source_ready), // .ready
.in_startofpacket (uart_com_avalon_rs232_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_com_avalon_rs232_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_com_avalon_rs232_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (9),
.ST_DATA_W (120),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) convolution_slave_avs_s0_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (convolution_slave_avs_s0_agent_m0_address), // m0.address
.m0_burstcount (convolution_slave_avs_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (convolution_slave_avs_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (convolution_slave_avs_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (convolution_slave_avs_s0_agent_m0_lock), // .lock
.m0_readdata (convolution_slave_avs_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (convolution_slave_avs_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (convolution_slave_avs_s0_agent_m0_read), // .read
.m0_waitrequest (convolution_slave_avs_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (convolution_slave_avs_s0_agent_m0_writedata), // .writedata
.m0_write (convolution_slave_avs_s0_agent_m0_write), // .write
.rp_endofpacket (convolution_slave_avs_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (convolution_slave_avs_s0_agent_rp_ready), // .ready
.rp_valid (convolution_slave_avs_s0_agent_rp_valid), // .valid
.rp_data (convolution_slave_avs_s0_agent_rp_data), // .data
.rp_startofpacket (convolution_slave_avs_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (convolution_slave_avs_s0_burst_adapter_source0_ready), // cp.ready
.cp_valid (convolution_slave_avs_s0_burst_adapter_source0_valid), // .valid
.cp_data (convolution_slave_avs_s0_burst_adapter_source0_data), // .data
.cp_startofpacket (convolution_slave_avs_s0_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (convolution_slave_avs_s0_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (convolution_slave_avs_s0_burst_adapter_source0_channel), // .channel
.rf_sink_ready (convolution_slave_avs_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (convolution_slave_avs_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (convolution_slave_avs_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (convolution_slave_avs_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (convolution_slave_avs_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (convolution_slave_avs_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (convolution_slave_avs_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (convolution_slave_avs_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (convolution_slave_avs_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (convolution_slave_avs_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
.rdata_fifo_src_ready (convolution_slave_avs_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (convolution_slave_avs_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (convolution_slave_avs_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (121),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) convolution_slave_avs_s0_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (convolution_slave_avs_s0_agent_rf_source_data), // in.data
.in_valid (convolution_slave_avs_s0_agent_rf_source_valid), // .valid
.in_ready (convolution_slave_avs_s0_agent_rf_source_ready), // .ready
.in_startofpacket (convolution_slave_avs_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (convolution_slave_avs_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (convolution_slave_avs_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (convolution_slave_avs_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (convolution_slave_avs_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (convolution_slave_avs_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (convolution_slave_avs_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (9),
.ST_DATA_W (120),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) test_pipeline_avs_s0_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (test_pipeline_avs_s0_agent_m0_address), // m0.address
.m0_burstcount (test_pipeline_avs_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (test_pipeline_avs_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (test_pipeline_avs_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (test_pipeline_avs_s0_agent_m0_lock), // .lock
.m0_readdata (test_pipeline_avs_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (test_pipeline_avs_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (test_pipeline_avs_s0_agent_m0_read), // .read
.m0_waitrequest (test_pipeline_avs_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (test_pipeline_avs_s0_agent_m0_writedata), // .writedata
.m0_write (test_pipeline_avs_s0_agent_m0_write), // .write
.rp_endofpacket (test_pipeline_avs_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (test_pipeline_avs_s0_agent_rp_ready), // .ready
.rp_valid (test_pipeline_avs_s0_agent_rp_valid), // .valid
.rp_data (test_pipeline_avs_s0_agent_rp_data), // .data
.rp_startofpacket (test_pipeline_avs_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (test_pipeline_avs_s0_burst_adapter_source0_ready), // cp.ready
.cp_valid (test_pipeline_avs_s0_burst_adapter_source0_valid), // .valid
.cp_data (test_pipeline_avs_s0_burst_adapter_source0_data), // .data
.cp_startofpacket (test_pipeline_avs_s0_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (test_pipeline_avs_s0_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (test_pipeline_avs_s0_burst_adapter_source0_channel), // .channel
.rf_sink_ready (test_pipeline_avs_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (test_pipeline_avs_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (test_pipeline_avs_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (test_pipeline_avs_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (test_pipeline_avs_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (test_pipeline_avs_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (test_pipeline_avs_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (test_pipeline_avs_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (test_pipeline_avs_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (test_pipeline_avs_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error
.rdata_fifo_src_ready (test_pipeline_avs_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (test_pipeline_avs_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (test_pipeline_avs_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (121),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) test_pipeline_avs_s0_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (test_pipeline_avs_s0_agent_rf_source_data), // in.data
.in_valid (test_pipeline_avs_s0_agent_rf_source_valid), // .valid
.in_ready (test_pipeline_avs_s0_agent_rf_source_ready), // .ready
.in_startofpacket (test_pipeline_avs_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (test_pipeline_avs_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (test_pipeline_avs_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (test_pipeline_avs_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (test_pipeline_avs_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (test_pipeline_avs_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (test_pipeline_avs_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (9),
.ST_DATA_W (120),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) systemid_control_slave_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (systemid_control_slave_agent_m0_address), // m0.address
.m0_burstcount (systemid_control_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (systemid_control_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (systemid_control_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (systemid_control_slave_agent_m0_lock), // .lock
.m0_readdata (systemid_control_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (systemid_control_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (systemid_control_slave_agent_m0_read), // .read
.m0_waitrequest (systemid_control_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (systemid_control_slave_agent_m0_writedata), // .writedata
.m0_write (systemid_control_slave_agent_m0_write), // .write
.rp_endofpacket (systemid_control_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (systemid_control_slave_agent_rp_ready), // .ready
.rp_valid (systemid_control_slave_agent_rp_valid), // .valid
.rp_data (systemid_control_slave_agent_rp_data), // .data
.rp_startofpacket (systemid_control_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (systemid_control_slave_burst_adapter_source0_ready), // cp.ready
.cp_valid (systemid_control_slave_burst_adapter_source0_valid), // .valid
.cp_data (systemid_control_slave_burst_adapter_source0_data), // .data
.cp_startofpacket (systemid_control_slave_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (systemid_control_slave_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (systemid_control_slave_burst_adapter_source0_channel), // .channel
.rf_sink_ready (systemid_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (systemid_control_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (systemid_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (systemid_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (systemid_control_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (systemid_control_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (systemid_control_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (systemid_control_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (systemid_control_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (systemid_control_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_007_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_007_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_007_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_007_out_0_error), // .error
.rdata_fifo_src_ready (systemid_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (systemid_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (systemid_control_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (121),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) systemid_control_slave_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (systemid_control_slave_agent_rf_source_data), // in.data
.in_valid (systemid_control_slave_agent_rf_source_valid), // .valid
.in_ready (systemid_control_slave_agent_rf_source_ready), // .ready
.in_startofpacket (systemid_control_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (systemid_control_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (systemid_control_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (systemid_control_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (systemid_control_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (systemid_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (systemid_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (119),
.PKT_ORI_BURST_SIZE_L (117),
.PKT_RESPONSE_STATUS_H (116),
.PKT_RESPONSE_STATUS_L (115),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_TRANS_LOCK (72),
.PKT_BEGIN_BURST (97),
.PKT_PROTECTION_H (110),
.PKT_PROTECTION_L (108),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (9),
.ST_DATA_W (120),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sys_timer_s1_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sys_timer_s1_agent_m0_address), // m0.address
.m0_burstcount (sys_timer_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sys_timer_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sys_timer_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sys_timer_s1_agent_m0_lock), // .lock
.m0_readdata (sys_timer_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sys_timer_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sys_timer_s1_agent_m0_read), // .read
.m0_waitrequest (sys_timer_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sys_timer_s1_agent_m0_writedata), // .writedata
.m0_write (sys_timer_s1_agent_m0_write), // .write
.rp_endofpacket (sys_timer_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sys_timer_s1_agent_rp_ready), // .ready
.rp_valid (sys_timer_s1_agent_rp_valid), // .valid
.rp_data (sys_timer_s1_agent_rp_data), // .data
.rp_startofpacket (sys_timer_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sys_timer_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (sys_timer_s1_burst_adapter_source0_valid), // .valid
.cp_data (sys_timer_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (sys_timer_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sys_timer_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sys_timer_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sys_timer_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sys_timer_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sys_timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sys_timer_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sys_timer_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sys_timer_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sys_timer_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sys_timer_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sys_timer_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sys_timer_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_008_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_008_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_008_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_008_out_0_error), // .error
.rdata_fifo_src_ready (sys_timer_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sys_timer_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sys_timer_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (121),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sys_timer_s1_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sys_timer_s1_agent_rf_source_data), // in.data
.in_valid (sys_timer_s1_agent_rf_source_valid), // .valid
.in_ready (sys_timer_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sys_timer_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sys_timer_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sys_timer_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sys_timer_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sys_timer_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sys_timer_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sys_timer_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
soc_design_mm_interconnect_0_router router (
.sink_ready (test_pipeline_avm_m0_agent_cp_ready), // sink.ready
.sink_valid (test_pipeline_avm_m0_agent_cp_valid), // .valid
.sink_data (test_pipeline_avm_m0_agent_cp_data), // .data
.sink_startofpacket (test_pipeline_avm_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (test_pipeline_avm_m0_agent_cp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_001 router_001 (
.sink_ready (niosii_core_data_master_agent_cp_ready), // sink.ready
.sink_valid (niosii_core_data_master_agent_cp_valid), // .valid
.sink_data (niosii_core_data_master_agent_cp_data), // .data
.sink_startofpacket (niosii_core_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (niosii_core_data_master_agent_cp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_002 router_002 (
.sink_ready (niosii_core_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (niosii_core_instruction_master_agent_cp_valid), // .valid
.sink_data (niosii_core_instruction_master_agent_cp_data), // .data
.sink_startofpacket (niosii_core_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (niosii_core_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_003 router_003 (
.sink_ready (sdram_s1_agent_rp_ready), // sink.ready
.sink_valid (sdram_s1_agent_rp_valid), // .valid
.sink_data (sdram_s1_agent_rp_data), // .data
.sink_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_004 router_004 (
.sink_ready (niosii_core_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (niosii_core_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (niosii_core_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (niosii_core_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (niosii_core_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_004 router_005 (
.sink_ready (sram_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_s1_agent_rp_valid), // .valid
.sink_data (sram_s1_agent_rp_data), // .data
.sink_startofpacket (sram_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_s1_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_006 router_006 (
.sink_ready (jtag_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_006 router_007 (
.sink_ready (uart_com_avalon_rs232_slave_agent_rp_ready), // sink.ready
.sink_valid (uart_com_avalon_rs232_slave_agent_rp_valid), // .valid
.sink_data (uart_com_avalon_rs232_slave_agent_rp_data), // .data
.sink_startofpacket (uart_com_avalon_rs232_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_com_avalon_rs232_slave_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_006 router_008 (
.sink_ready (convolution_slave_avs_s0_agent_rp_ready), // sink.ready
.sink_valid (convolution_slave_avs_s0_agent_rp_valid), // .valid
.sink_data (convolution_slave_avs_s0_agent_rp_data), // .data
.sink_startofpacket (convolution_slave_avs_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (convolution_slave_avs_s0_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_006 router_009 (
.sink_ready (test_pipeline_avs_s0_agent_rp_ready), // sink.ready
.sink_valid (test_pipeline_avs_s0_agent_rp_valid), // .valid
.sink_data (test_pipeline_avs_s0_agent_rp_data), // .data
.sink_startofpacket (test_pipeline_avs_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (test_pipeline_avs_s0_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_006 router_010 (
.sink_ready (systemid_control_slave_agent_rp_ready), // sink.ready
.sink_valid (systemid_control_slave_agent_rp_valid), // .valid
.sink_data (systemid_control_slave_agent_rp_data), // .data
.sink_startofpacket (systemid_control_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (systemid_control_slave_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_010_src_ready), // src.ready
.src_valid (router_010_src_valid), // .valid
.src_data (router_010_src_data), // .data
.src_channel (router_010_src_channel), // .channel
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_router_006 router_011 (
.sink_ready (sys_timer_s1_agent_rp_ready), // sink.ready
.sink_valid (sys_timer_s1_agent_rp_valid), // .valid
.sink_data (sys_timer_s1_agent_rp_data), // .data
.sink_startofpacket (sys_timer_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sys_timer_s1_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_011_src_ready), // src.ready
.src_valid (router_011_src_valid), // .valid
.src_data (router_011_src_data), // .data
.src_channel (router_011_src_channel), // .channel
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.VALID_WIDTH (9),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) niosii_core_data_master_limiter (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (niosii_core_data_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (niosii_core_data_master_limiter_cmd_src_data), // .data
.cmd_src_channel (niosii_core_data_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (niosii_core_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (niosii_core_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (niosii_core_data_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (niosii_core_data_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (niosii_core_data_master_limiter_rsp_src_data), // .data
.rsp_src_channel (niosii_core_data_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (niosii_core_data_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (niosii_core_data_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (niosii_core_data_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (106),
.PKT_DEST_ID_L (103),
.PKT_SRC_ID_H (102),
.PKT_SRC_ID_L (99),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (69),
.PKT_TRANS_WRITE (70),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.VALID_WIDTH (9),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) niosii_core_instruction_master_limiter (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_002_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_002_src_valid), // .valid
.cmd_sink_data (router_002_src_data), // .data
.cmd_sink_channel (router_002_src_channel), // .channel
.cmd_sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.cmd_src_ready (niosii_core_instruction_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (niosii_core_instruction_master_limiter_cmd_src_data), // .data
.cmd_src_channel (niosii_core_instruction_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (niosii_core_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (niosii_core_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_002_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_002_src_valid), // .valid
.rsp_sink_channel (rsp_mux_002_src_channel), // .channel
.rsp_sink_data (rsp_mux_002_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.rsp_src_ready (niosii_core_instruction_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (niosii_core_instruction_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (niosii_core_instruction_master_limiter_rsp_src_data), // .data
.rsp_src_channel (niosii_core_instruction_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (niosii_core_instruction_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (niosii_core_instruction_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (niosii_core_instruction_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (49),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (79),
.PKT_BYTE_CNT_H (65),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (74),
.PKT_BURST_SIZE_L (72),
.PKT_BURST_TYPE_H (76),
.PKT_BURST_TYPE_L (75),
.PKT_BURSTWRAP_H (71),
.PKT_BURSTWRAP_L (66),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (102),
.ST_CHANNEL_W (9),
.OUT_BYTE_CNT_H (57),
.OUT_BURSTWRAP_H (71),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (31),
.BURSTWRAP_CONST_VALUE (31),
.ADAPTER_VERSION ("13.1")
) sdram_s1_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (sdram_s1_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (sdram_s1_cmd_width_adapter_src_data), // .data
.sink0_channel (sdram_s1_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (sdram_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (sdram_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (sdram_s1_cmd_width_adapter_src_ready), // .ready
.source0_valid (sdram_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (sdram_s1_burst_adapter_source0_data), // .data
.source0_channel (sdram_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sdram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sdram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sdram_s1_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (31),
.BURSTWRAP_CONST_VALUE (31),
.ADAPTER_VERSION ("13.1")
) niosii_core_debug_mem_slave_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_mux_001_src_data), // .data
.sink0_channel (cmd_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_001_src_ready), // .ready
.source0_valid (niosii_core_debug_mem_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (niosii_core_debug_mem_slave_burst_adapter_source0_data), // .data
.source0_channel (niosii_core_debug_mem_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (niosii_core_debug_mem_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (niosii_core_debug_mem_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (niosii_core_debug_mem_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (31),
.BURSTWRAP_CONST_VALUE (31),
.ADAPTER_VERSION ("13.1")
) sram_s1_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_002_src_valid), // sink0.valid
.sink0_data (cmd_mux_002_src_data), // .data
.sink0_channel (cmd_mux_002_src_channel), // .channel
.sink0_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_002_src_ready), // .ready
.source0_valid (sram_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (sram_s1_burst_adapter_source0_data), // .data
.source0_channel (sram_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sram_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sram_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sram_s1_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (63),
.BURSTWRAP_CONST_VALUE (63),
.ADAPTER_VERSION ("13.1")
) jtag_avalon_jtag_slave_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_003_src_valid), // sink0.valid
.sink0_data (cmd_mux_003_src_data), // .data
.sink0_channel (cmd_mux_003_src_channel), // .channel
.sink0_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_003_src_ready), // .ready
.source0_valid (jtag_avalon_jtag_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (jtag_avalon_jtag_slave_burst_adapter_source0_data), // .data
.source0_channel (jtag_avalon_jtag_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (jtag_avalon_jtag_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (jtag_avalon_jtag_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (jtag_avalon_jtag_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (63),
.BURSTWRAP_CONST_VALUE (63),
.ADAPTER_VERSION ("13.1")
) uart_com_avalon_rs232_slave_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_004_src_valid), // sink0.valid
.sink0_data (cmd_mux_004_src_data), // .data
.sink0_channel (cmd_mux_004_src_channel), // .channel
.sink0_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_004_src_ready), // .ready
.source0_valid (uart_com_avalon_rs232_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (uart_com_avalon_rs232_slave_burst_adapter_source0_data), // .data
.source0_channel (uart_com_avalon_rs232_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (uart_com_avalon_rs232_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (uart_com_avalon_rs232_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (uart_com_avalon_rs232_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (63),
.BURSTWRAP_CONST_VALUE (63),
.ADAPTER_VERSION ("13.1")
) convolution_slave_avs_s0_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_005_src_valid), // sink0.valid
.sink0_data (cmd_mux_005_src_data), // .data
.sink0_channel (cmd_mux_005_src_channel), // .channel
.sink0_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_005_src_ready), // .ready
.source0_valid (convolution_slave_avs_s0_burst_adapter_source0_valid), // source0.valid
.source0_data (convolution_slave_avs_s0_burst_adapter_source0_data), // .data
.source0_channel (convolution_slave_avs_s0_burst_adapter_source0_channel), // .channel
.source0_startofpacket (convolution_slave_avs_s0_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (convolution_slave_avs_s0_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (convolution_slave_avs_s0_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (63),
.BURSTWRAP_CONST_VALUE (63),
.ADAPTER_VERSION ("13.1")
) test_pipeline_avs_s0_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_006_src_valid), // sink0.valid
.sink0_data (cmd_mux_006_src_data), // .data
.sink0_channel (cmd_mux_006_src_channel), // .channel
.sink0_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_006_src_ready), // .ready
.source0_valid (test_pipeline_avs_s0_burst_adapter_source0_valid), // source0.valid
.source0_data (test_pipeline_avs_s0_burst_adapter_source0_data), // .data
.source0_channel (test_pipeline_avs_s0_burst_adapter_source0_channel), // .channel
.source0_startofpacket (test_pipeline_avs_s0_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (test_pipeline_avs_s0_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (test_pipeline_avs_s0_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (63),
.BURSTWRAP_CONST_VALUE (63),
.ADAPTER_VERSION ("13.1")
) systemid_control_slave_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_007_src_valid), // sink0.valid
.sink0_data (cmd_mux_007_src_data), // .data
.sink0_channel (cmd_mux_007_src_channel), // .channel
.sink0_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_007_src_ready), // .ready
.source0_valid (systemid_control_slave_burst_adapter_source0_valid), // source0.valid
.source0_data (systemid_control_slave_burst_adapter_source0_data), // .data
.source0_channel (systemid_control_slave_burst_adapter_source0_channel), // .channel
.source0_startofpacket (systemid_control_slave_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (systemid_control_slave_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (systemid_control_slave_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (67),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (97),
.PKT_BYTE_CNT_H (83),
.PKT_BYTE_CNT_L (74),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (92),
.PKT_BURST_SIZE_L (90),
.PKT_BURST_TYPE_H (94),
.PKT_BURST_TYPE_L (93),
.PKT_BURSTWRAP_H (89),
.PKT_BURSTWRAP_L (84),
.PKT_TRANS_COMPRESSED_READ (68),
.PKT_TRANS_WRITE (70),
.PKT_TRANS_READ (71),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (120),
.ST_CHANNEL_W (9),
.OUT_BYTE_CNT_H (76),
.OUT_BURSTWRAP_H (89),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (63),
.BURSTWRAP_CONST_VALUE (63),
.ADAPTER_VERSION ("13.1")
) sys_timer_s1_burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_008_src_valid), // sink0.valid
.sink0_data (cmd_mux_008_src_data), // .data
.sink0_channel (cmd_mux_008_src_channel), // .channel
.sink0_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_008_src_ready), // .ready
.source0_valid (sys_timer_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (sys_timer_s1_burst_adapter_source0_data), // .data
.source0_channel (sys_timer_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sys_timer_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sys_timer_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sys_timer_s1_burst_adapter_source0_ready) // .ready
);
soc_design_mm_interconnect_0_cmd_demux cmd_demux (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (niosii_core_data_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (niosii_core_data_master_limiter_cmd_src_channel), // .channel
.sink_data (niosii_core_data_master_limiter_cmd_src_data), // .data
.sink_startofpacket (niosii_core_data_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (niosii_core_data_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (niosii_core_data_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_demux_001_src3_valid), // .valid
.src3_data (cmd_demux_001_src3_data), // .data
.src3_channel (cmd_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_demux_001_src4_valid), // .valid
.src4_data (cmd_demux_001_src4_data), // .data
.src4_channel (cmd_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_demux_001_src5_valid), // .valid
.src5_data (cmd_demux_001_src5_data), // .data
.src5_channel (cmd_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_001_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_001_src6_ready), // src6.ready
.src6_valid (cmd_demux_001_src6_valid), // .valid
.src6_data (cmd_demux_001_src6_data), // .data
.src6_channel (cmd_demux_001_src6_channel), // .channel
.src6_startofpacket (cmd_demux_001_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_001_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_001_src7_ready), // src7.ready
.src7_valid (cmd_demux_001_src7_valid), // .valid
.src7_data (cmd_demux_001_src7_data), // .data
.src7_channel (cmd_demux_001_src7_channel), // .channel
.src7_startofpacket (cmd_demux_001_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_001_src7_endofpacket), // .endofpacket
.src8_ready (cmd_demux_001_src8_ready), // src8.ready
.src8_valid (cmd_demux_001_src8_valid), // .valid
.src8_data (cmd_demux_001_src8_data), // .data
.src8_channel (cmd_demux_001_src8_channel), // .channel
.src8_startofpacket (cmd_demux_001_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_demux_001_src8_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (niosii_core_instruction_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (niosii_core_instruction_master_limiter_cmd_src_channel), // .channel
.sink_data (niosii_core_instruction_master_limiter_cmd_src_data), // .data
.sink_startofpacket (niosii_core_instruction_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (niosii_core_instruction_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (niosii_core_instruction_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_demux_002_src0_valid), // .valid
.src0_data (cmd_demux_002_src0_data), // .data
.src0_channel (cmd_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_002_src1_ready), // src1.ready
.src1_valid (cmd_demux_002_src1_valid), // .valid
.src1_data (cmd_demux_002_src1_data), // .data
.src1_channel (cmd_demux_002_src1_channel), // .channel
.src1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_002_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_002_src2_ready), // src2.ready
.src2_valid (cmd_demux_002_src2_valid), // .valid
.src2_data (cmd_demux_002_src2_data), // .data
.src2_channel (cmd_demux_002_src2_channel), // .channel
.src2_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_002_src2_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux cmd_mux (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_002_src0_ready), // sink2.ready
.sink2_valid (cmd_demux_002_src0_valid), // .valid
.sink2_channel (cmd_demux_002_src0_channel), // .channel
.sink2_data (cmd_demux_002_src0_data), // .data
.sink2_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src1_valid), // .valid
.sink0_channel (cmd_demux_001_src1_channel), // .channel
.sink0_data (cmd_demux_001_src1_data), // .data
.sink0_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_002_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_002_src1_valid), // .valid
.sink1_channel (cmd_demux_002_src1_channel), // .channel
.sink1_data (cmd_demux_002_src1_data), // .data
.sink1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_002_src1_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src2_valid), // .valid
.sink0_channel (cmd_demux_001_src2_channel), // .channel
.sink0_data (cmd_demux_001_src2_data), // .data
.sink0_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_002_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_002_src2_valid), // .valid
.sink1_channel (cmd_demux_002_src2_channel), // .channel
.sink1_data (cmd_demux_002_src2_data), // .data
.sink1_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_002_src2_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_003 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src3_valid), // .valid
.sink0_channel (cmd_demux_001_src3_channel), // .channel
.sink0_data (cmd_demux_001_src3_data), // .data
.sink0_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_004 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src4_valid), // .valid
.sink0_channel (cmd_demux_001_src4_channel), // .channel
.sink0_data (cmd_demux_001_src4_data), // .data
.sink0_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src4_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_005 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src5_valid), // .valid
.sink0_channel (cmd_demux_001_src5_channel), // .channel
.sink0_data (cmd_demux_001_src5_data), // .data
.sink0_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src5_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_006 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src6_valid), // .valid
.sink0_channel (cmd_demux_001_src6_channel), // .channel
.sink0_data (cmd_demux_001_src6_data), // .data
.sink0_startofpacket (cmd_demux_001_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src6_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_007 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_007_src_ready), // src.ready
.src_valid (cmd_mux_007_src_valid), // .valid
.src_data (cmd_mux_007_src_data), // .data
.src_channel (cmd_mux_007_src_channel), // .channel
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src7_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src7_valid), // .valid
.sink0_channel (cmd_demux_001_src7_channel), // .channel
.sink0_data (cmd_demux_001_src7_data), // .data
.sink0_startofpacket (cmd_demux_001_src7_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src7_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_mux_003 cmd_mux_008 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_008_src_ready), // src.ready
.src_valid (cmd_mux_008_src_valid), // .valid
.src_data (cmd_mux_008_src_data), // .data
.src_channel (cmd_mux_008_src_channel), // .channel
.src_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src8_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src8_valid), // .valid
.sink0_channel (cmd_demux_001_src8_channel), // .channel
.sink0_data (cmd_demux_001_src8_data), // .data
.sink0_startofpacket (cmd_demux_001_src8_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src8_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_demux rsp_demux (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sdram_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sdram_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sdram_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sdram_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sdram_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_src2_ready), // src2.ready
.src2_valid (rsp_demux_src2_valid), // .valid
.src2_data (rsp_demux_src2_data), // .data
.src2_channel (rsp_demux_src2_channel), // .channel
.src2_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_src2_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_demux_001 rsp_demux_002 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_demux rsp_demux_003 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_demux rsp_demux_004 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_demux rsp_demux_005 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_demux rsp_demux_006 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_009_src_ready), // sink.ready
.sink_channel (router_009_src_channel), // .channel
.sink_data (router_009_src_data), // .data
.sink_startofpacket (router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (router_009_src_endofpacket), // .endofpacket
.sink_valid (router_009_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_demux rsp_demux_007 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_010_src_ready), // sink.ready
.sink_channel (router_010_src_channel), // .channel
.sink_data (router_010_src_data), // .data
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
.sink_valid (router_010_src_valid), // .valid
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_demux_007_src0_valid), // .valid
.src0_data (rsp_demux_007_src0_data), // .data
.src0_channel (rsp_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_007_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_cmd_demux rsp_demux_008 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_011_src_ready), // sink.ready
.sink_channel (router_011_src_channel), // .channel
.sink_data (router_011_src_data), // .data
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
.sink_valid (router_011_src_valid), // .valid
.src0_ready (rsp_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_demux_008_src0_valid), // .valid
.src0_data (rsp_demux_008_src0_data), // .data
.src0_channel (rsp_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_008_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_mux rsp_mux (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src0_valid), // .valid
.sink7_channel (rsp_demux_007_src0_channel), // .channel
.sink7_data (rsp_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.sink8_ready (rsp_demux_008_src0_ready), // sink8.ready
.sink8_valid (rsp_demux_008_src0_valid), // .valid
.sink8_channel (rsp_demux_008_src0_channel), // .channel
.sink8_data (rsp_demux_008_src0_data), // .data
.sink8_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.sink8_endofpacket (rsp_demux_008_src0_endofpacket) // .endofpacket
);
soc_design_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_002_src_ready), // src.ready
.src_valid (rsp_mux_002_src_valid), // .valid
.src_data (rsp_mux_002_src_data), // .data
.src_channel (rsp_mux_002_src_channel), // .channel
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src2_ready), // sink0.ready
.sink0_valid (rsp_demux_src2_valid), // .valid
.sink0_channel (rsp_demux_src2_channel), // .channel
.sink0_data (rsp_demux_src2_data), // .data
.sink0_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src2_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src1_valid), // .valid
.sink2_channel (rsp_demux_002_src1_channel), // .channel
.sink2_data (rsp_demux_002_src1_data), // .data
.sink2_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (65),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_TRANS_WRITE (52),
.IN_PKT_BURSTWRAP_H (71),
.IN_PKT_BURSTWRAP_L (66),
.IN_PKT_BURST_SIZE_H (74),
.IN_PKT_BURST_SIZE_L (72),
.IN_PKT_RESPONSE_STATUS_H (98),
.IN_PKT_RESPONSE_STATUS_L (97),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (76),
.IN_PKT_BURST_TYPE_L (75),
.IN_PKT_ORI_BURST_SIZE_L (99),
.IN_PKT_ORI_BURST_SIZE_H (101),
.IN_ST_DATA_W (102),
.OUT_PKT_ADDR_H (67),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (83),
.OUT_PKT_BYTE_CNT_L (74),
.OUT_PKT_TRANS_COMPRESSED_READ (68),
.OUT_PKT_BURST_SIZE_H (92),
.OUT_PKT_BURST_SIZE_L (90),
.OUT_PKT_RESPONSE_STATUS_H (116),
.OUT_PKT_RESPONSE_STATUS_L (115),
.OUT_PKT_TRANS_EXCLUSIVE (73),
.OUT_PKT_BURST_TYPE_H (94),
.OUT_PKT_BURST_TYPE_L (93),
.OUT_PKT_ORI_BURST_SIZE_L (117),
.OUT_PKT_ORI_BURST_SIZE_H (119),
.OUT_ST_DATA_W (120),
.ST_CHANNEL_W (9),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_s1_rsp_width_adapter (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_003_src_valid), // sink.valid
.in_channel (router_003_src_channel), // .channel
.in_startofpacket (router_003_src_startofpacket), // .startofpacket
.in_endofpacket (router_003_src_endofpacket), // .endofpacket
.in_ready (router_003_src_ready), // .ready
.in_data (router_003_src_data), // .data
.out_endofpacket (sdram_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_s1_rsp_width_adapter_src_data), // .data
.out_channel (sdram_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sdram_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sdram_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (67),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (83),
.IN_PKT_BYTE_CNT_L (74),
.IN_PKT_TRANS_COMPRESSED_READ (68),
.IN_PKT_TRANS_WRITE (70),
.IN_PKT_BURSTWRAP_H (89),
.IN_PKT_BURSTWRAP_L (84),
.IN_PKT_BURST_SIZE_H (92),
.IN_PKT_BURST_SIZE_L (90),
.IN_PKT_RESPONSE_STATUS_H (116),
.IN_PKT_RESPONSE_STATUS_L (115),
.IN_PKT_TRANS_EXCLUSIVE (73),
.IN_PKT_BURST_TYPE_H (94),
.IN_PKT_BURST_TYPE_L (93),
.IN_PKT_ORI_BURST_SIZE_L (117),
.IN_PKT_ORI_BURST_SIZE_H (119),
.IN_ST_DATA_W (120),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (65),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (74),
.OUT_PKT_BURST_SIZE_L (72),
.OUT_PKT_RESPONSE_STATUS_H (98),
.OUT_PKT_RESPONSE_STATUS_L (97),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (76),
.OUT_PKT_BURST_TYPE_L (75),
.OUT_PKT_ORI_BURST_SIZE_L (99),
.OUT_PKT_ORI_BURST_SIZE_H (101),
.OUT_ST_DATA_W (102),
.ST_CHANNEL_W (9),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sdram_s1_cmd_width_adapter (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (sdram_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sdram_s1_cmd_width_adapter_src_data), // .data
.out_channel (sdram_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sdram_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sdram_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sdram_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
soc_design_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sdram_s1_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (sdram_s1_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (niosii_core_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (niosii_core_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (niosii_core_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sram_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sram_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sram_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (jtag_avalon_jtag_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (jtag_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (jtag_avalon_jtag_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_com_avalon_rs232_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_com_avalon_rs232_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_com_avalon_rs232_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_005 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (convolution_slave_avs_s0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (convolution_slave_avs_s0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (convolution_slave_avs_s0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_006 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (test_pipeline_avs_s0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (test_pipeline_avs_s0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (test_pipeline_avs_s0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_006_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_006_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_006_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_006_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_007 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (systemid_control_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (systemid_control_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (systemid_control_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_007_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_007_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_007_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_007_out_0_error) // .error
);
soc_design_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_008 (
.in_clk_0_clk (system_pll_outclk0_clk), // in_clk_0.clk
.in_rst_0_reset (Test_PipeLine_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sys_timer_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sys_timer_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sys_timer_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_008_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_008_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_008_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_008_out_0_error) // .error
);
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NPM_Toggle_DO_tADL_DDR100 for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPM_Toggle_DO_tADL_DDR100
// Module Name: NPM_Toggle_DO_tADL_DDR100
// File Name: NPM_Toggle_DO_tADL_DDR100.v
//
// Version: v1.0.0
//
// Description: NFC PM data out FSM
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPM_Toggle_DO_tADL_DDR100
#
(
// support "serial execution"
// Data Packet Width (DQ): 8 bit
// iOption: set SDR/DDR mode
// 0-SDR(WE#), 1-DDR(DQS)
// NumOfData: 0 means 1
// -> unit: word (32 bit = 4 B)
// _tADL.v
// (original design: tCDQSS = 110 ns, tWPRE = 30 ns)
//
// tCDQSS = 250 ns => 25 cycles
// tWPRE = 50 ns => 5 cycles
// future -> add data buffer?
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
oReady ,
oLastStep ,
iStart ,
iOption ,
iTargetWay ,
iWriteData ,
iWriteLast ,
iWriteValid ,
oWriteReady ,
oPO_DQStrobe ,
oPO_DQ ,
oPO_ChipEnable ,
oPO_WriteEnable ,
oPO_AddressLatchEnable ,
oPO_CommandLatchEnable ,
oDQSOutEnable ,
oDQOutEnable
);
input iSystemClock ;
input iReset ;
output oReady ;
output oLastStep ;
input iStart ;
input iOption ;
input [NumberOfWays - 1:0] iTargetWay ;
input [31:0] iWriteData ;
input iWriteLast ;
input iWriteValid ;
output oWriteReady ;
output [7:0] oPO_DQStrobe ;
output [31:0] oPO_DQ ;
output [2*NumberOfWays - 1:0] oPO_ChipEnable ;
output [3:0] oPO_WriteEnable ;
output [3:0] oPO_AddressLatchEnable ;
output [3:0] oPO_CommandLatchEnable ;
output oDQSOutEnable ;
output oDQOutEnable ;
// FSM Parameters/Wires/Regs
localparam DTO_FSM_BIT = 9; // DaTa Out
localparam DTO_RESET = 9'b000_000_001;
localparam DTO_READY = 9'b000_000_010;
localparam DTO_DQS01 = 9'b000_000_100; // info. capture, wait state for tCDQSS
localparam DTO_DQS02 = 9'b000_001_000; // wait state for tCDQSS
localparam DTO_WPRAM = 9'b000_010_000; // wait state for tWRPE
localparam DTO_DQOUT = 9'b000_100_000; // DQ out: loop
localparam DTO_PAUSE = 9'b001_000_000; // pause DQ out
localparam DTO_DQLST = 9'b010_000_000; // DQ out: last
localparam DTO_WPSAM = 9'b100_000_000; // wait state for tWPST
localparam DTO_WPSA2 = 9'b110_000_000; // temp. state: will be removed
reg [DTO_FSM_BIT-1:0] rDTO_cur_state ;
reg [DTO_FSM_BIT-1:0] rDTO_nxt_state ;
// Internal Wires/Regs
reg rReady ;
reg rLastStep ;
reg rOption ;
reg [4:0] rDTOSubCounter ;
wire [2*NumberOfWays - 1:0] wPO_ChipEnable ;
wire wtCDQSSDone ;
wire wtWPREDone ;
wire wLoopDone ;
wire wtWPSTDone ;
reg [7:0] rPO_DQStrobe ;
reg [31:0] rPO_DQ ;
reg [2*NumberOfWays - 1:0] rPO_ChipEnable ;
reg [3:0] rPO_WriteEnable ;
reg [3:0] rPO_AddressLatchEnable ;
reg [3:0] rPO_CommandLatchEnable ;
reg rDQSOutEnable ;
reg rDQOutEnable ;
reg rStageFlag ;
// Control Signals
// Target Way Decoder
assign wPO_ChipEnable = { iTargetWay[NumberOfWays - 1:0], iTargetWay[NumberOfWays - 1:0] };
// Flow Control
assign wtCDQSSDone = (rDTOSubCounter[4:0] == 5'd25); // 25 => 250 ns
assign wtWPREDone = (rDTOSubCounter[4:0] == 5'd30); // 30 - 25 = 5 => 50 ns
assign wLoopDone = iWriteLast & iWriteValid;
assign wtWPSTDone = (rDTOSubCounter[4:0] == 5'd3); // 3 - 0 = 3 => 30 ns, tWPST = 6.5 ns
// FSM: DaTa Out (DTO)
// update current state to next state
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rDTO_cur_state <= DTO_RESET;
end else begin
rDTO_cur_state <= rDTO_nxt_state;
end
end
// deside next state
always @ ( * ) begin
case (rDTO_cur_state)
DTO_RESET: begin
rDTO_nxt_state <= DTO_READY;
end
DTO_READY: begin
rDTO_nxt_state <= (iStart)? DTO_DQS01:DTO_READY;
end
DTO_DQS01: begin
rDTO_nxt_state <= DTO_DQS02;
end
DTO_DQS02: begin
rDTO_nxt_state <= (wtCDQSSDone)? DTO_WPRAM:DTO_DQS02;
end
DTO_WPRAM: begin
rDTO_nxt_state <= (wtWPREDone)? ((iWriteValid)? DTO_DQOUT:DTO_PAUSE):DTO_WPRAM;
end
DTO_DQOUT: begin
rDTO_nxt_state <= (rStageFlag)? (DTO_DQOUT):((wLoopDone)? DTO_DQLST:((iWriteValid)? DTO_DQOUT:DTO_PAUSE));
end
DTO_PAUSE: begin
rDTO_nxt_state <= (wLoopDone)? DTO_DQLST:((iWriteValid)? DTO_DQOUT:DTO_PAUSE);
end
DTO_DQLST: begin
rDTO_nxt_state <= (rStageFlag)? DTO_DQLST:DTO_WPSAM;
end
DTO_WPSAM: begin
rDTO_nxt_state <= (wtWPSTDone)? DTO_WPSA2:DTO_WPSAM;
end
DTO_WPSA2: begin
rDTO_nxt_state <= (iStart)? DTO_DQS01:DTO_READY;
end
default:
rDTO_nxt_state <= DTO_READY;
endcase
end
// state behaviour
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rReady <= 0;
rLastStep <= 0;
rOption <= 0;
rDTOSubCounter[4:0] <= 0;
rPO_DQStrobe[7:0] <= 8'b1111_1111;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= 0;
rPO_WriteEnable[3:0] <= 0;
rPO_AddressLatchEnable[3:0] <= 0;
rPO_CommandLatchEnable[3:0] <= 0;
rDQSOutEnable <= 0;
rDQOutEnable <= 0;
rStageFlag <= 0;
end else begin
case (rDTO_nxt_state)
DTO_RESET: begin
rReady <= 0;
rLastStep <= 0;
rOption <= 0;
rDTOSubCounter[4:0] <= 0;
rPO_DQStrobe[7:0] <= 8'b1111_1111;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= 0;
rPO_WriteEnable[3:0] <= 0;
rPO_AddressLatchEnable[3:0] <= 0;
rPO_CommandLatchEnable[3:0] <= 0;
rDQSOutEnable <= 0;
rDQOutEnable <= 0;
rStageFlag <= 0;
end
DTO_READY: begin
rReady <= 1;
rLastStep <= 0;
rOption <= 0;
rDTOSubCounter[4:0] <= 0;
rPO_DQStrobe[7:0] <= 8'b1111_1111;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= 0;
rPO_WriteEnable[3:0] <= 0;
rPO_AddressLatchEnable[3:0] <= 0;
rPO_CommandLatchEnable[3:0] <= 0;
rDQSOutEnable <= 0;
rDQOutEnable <= 0;
rStageFlag <= 0;
end
DTO_DQS01: begin
rReady <= 0;
rLastStep <= 0;
rOption <= iOption;
rDTOSubCounter[4:0] <= 0;
rPO_DQStrobe[7:0] <= 8'b1111_1111;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= wPO_ChipEnable;
rPO_WriteEnable[3:0] <= 4'b0000;
rPO_AddressLatchEnable[3:0] <= 4'b1111;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (iOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b1;
rStageFlag <= 0;
end
DTO_DQS02: begin
rReady <= 0;
rLastStep <= 0;
rOption <= rOption;
rDTOSubCounter[4:0] <= rDTOSubCounter[4:0] + 1'b1;
rPO_DQStrobe[7:0] <= 8'b1111_1111;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= 4'b0000;
rPO_AddressLatchEnable[3:0] <= 4'b1111;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b1;
rStageFlag <= 0;
end
DTO_WPRAM: begin
rReady <= 0;
rLastStep <= 0;
rOption <= rOption;
rDTOSubCounter[4:0] <= rDTOSubCounter[4:0] + 1'b1;
rPO_DQStrobe[7:0] <= 8'b0000_0000;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b1111;
rPO_AddressLatchEnable[3:0] <= 4'b0000;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b1;
rStageFlag <= 1'b0;
end
DTO_DQOUT: begin
rReady <= 0;
rLastStep <= 0;
rOption <= rOption;
rDTOSubCounter[4:0] <= rDTOSubCounter[4:0];
rPO_DQStrobe[7:0] <= 8'b0110_0110;
rPO_DQ[31:0] <= (rStageFlag)? ({ rPO_DQ[31:16], rPO_DQ[31:16] }):iWriteData[31:0];
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b1001;
rPO_AddressLatchEnable[3:0] <= 4'b0000;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b1;
rStageFlag <= (rOption)? ((rStageFlag)? 1'b0:1'b1):1'b0;
end
DTO_PAUSE: begin
rReady <= 0;
rLastStep <= 0;
rOption <= rOption;
rDTOSubCounter[4:0] <= rDTOSubCounter[4:0];
rPO_DQStrobe[7:0] <= 8'b0000_0000;
rPO_DQ[31:0] <= { 4{rPO_DQ[31:24]} };
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b1111;
rPO_AddressLatchEnable[3:0] <= 4'b0000;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b1;
rStageFlag <= 1'b0;
end
DTO_DQLST: begin
rReady <= 0;
rLastStep <= 0;
rOption <= rOption;
rDTOSubCounter[4:0] <= 0;
rPO_DQStrobe[7:0] <= 8'b0110_0110;
rPO_DQ[31:0] <= (rStageFlag)? ({ rPO_DQ[31:16], rPO_DQ[31:16] }):iWriteData[31:0];
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= (rOption)? 4'b0000:4'b0001;
rPO_AddressLatchEnable[3:0] <= 4'b0000;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b1;
rStageFlag <= (rOption)? ((rStageFlag)? 1'b0:1'b1):1'b0;
end
DTO_WPSAM: begin
rReady <= 0;
rLastStep <= 0;
rOption <= rOption;
rDTOSubCounter[4:0] <= rDTOSubCounter[4:0] + 1'b1;
rPO_DQStrobe[7:0] <= 8'b0000_0000;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= 4'b0000;
rPO_AddressLatchEnable[3:0] <= 4'b0000;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b0;
rStageFlag <= 1'b0;
end
DTO_WPSA2: begin
rReady <= 1;
rLastStep <= 1;
rOption <= rOption;
rDTOSubCounter[4:0] <= rDTOSubCounter[4:0];
rPO_DQStrobe[7:0] <= 8'b0000_0000;
rPO_DQ[31:0] <= 0;
rPO_ChipEnable <= rPO_ChipEnable;
rPO_WriteEnable[3:0] <= 4'b0000;
rPO_AddressLatchEnable[3:0] <= 4'b0000;
rPO_CommandLatchEnable[3:0] <= 4'b0000;
rDQSOutEnable <= (rOption)? 1'b1:1'b0;
rDQOutEnable <= 1'b0;
rStageFlag <= 1'b0;
end
endcase
end
end
// Output
assign oReady = rReady ;
assign oLastStep = rLastStep ;
assign oWriteReady = wtWPREDone & (~rStageFlag);
assign oPO_DQStrobe = rPO_DQStrobe ;
assign oPO_DQ = rPO_DQ ;
assign oPO_ChipEnable = rPO_ChipEnable ;
assign oPO_WriteEnable = rPO_WriteEnable ;
assign oPO_AddressLatchEnable = rPO_AddressLatchEnable;
assign oPO_CommandLatchEnable = rPO_CommandLatchEnable;
assign oDQSOutEnable = rDQSOutEnable ;
assign oDQOutEnable = rDQOutEnable ;
endmodule
|
// test taken from systemcaes from iwls2005
module subbytes_00(clk, reset, start_i, decrypt_i, data_i, ready_o, data_o, sbox_data_o, sbox_data_i, sbox_decrypt_o);
input clk;
input reset;
input start_i;
input decrypt_i;
input [31:0] data_i;
output ready_o;
output [31:0] data_o;
output [7:0] sbox_data_o;
input [7:0] sbox_data_i;
output sbox_decrypt_o;
reg ready_o;
reg [31:0] data_o;
reg [7:0] sbox_data_o;
reg sbox_decrypt_o;
reg [1:0] state;
reg [1:0] next_state;
reg [31:0] data_reg;
reg [31:0] next_data_reg;
reg next_ready_o;
always @(posedge clk or negedge reset)
begin
if (!reset) begin
data_reg = 0;
state = 0;
ready_o = 0;
end else begin
data_reg = next_data_reg;
state = next_state;
ready_o = next_ready_o;
end
end
reg [31:0] data_i_var, data_reg_128;
reg [7:0] data_array [3:0];
reg [7:0] data_reg_var [3:0];
always @(decrypt_i or start_i or state or data_i or sbox_data_i or data_reg)
begin
data_i_var = data_i;
data_array[0] = data_i_var[ 31: 24];
data_array[1] = data_i_var[ 23: 16];
data_array[2] = data_i_var[ 15: 8];
data_array[3] = data_i_var[ 7: 0];
data_reg_var[0] = data_reg[ 31: 24];
data_reg_var[1] = data_reg[ 23: 16];
data_reg_var[2] = data_reg[ 15: 8];
data_reg_var[3] = data_reg[ 7: 0];
sbox_decrypt_o = decrypt_i;
sbox_data_o = data_array[state];
next_state = state;
next_data_reg = data_reg;
next_ready_o = 0;
data_o = data_reg;
if (state) begin
if (start_i) begin
next_state = 1;
end
end else begin
data_reg_var[state] = sbox_data_i;
data_reg_128[ 31: 24] = data_reg_var[0];
data_reg_128[ 23: 16] = data_reg_var[1];
data_reg_128[ 15: 8] = data_reg_var[2];
data_reg_128[ 7: 0] = data_reg_var[3];
next_data_reg = data_reg_128;
next_state = state + 1;
end
end
endmodule
|
(** * Auto: More Automation *)
Require Export Imp.
(** Up to now, we've continued to use a quite restricted set of
Coq's tactic facilities. In this chapter, we'll learn more about
two very powerful features of Coq's tactic language:
proof search via the [auto] and [eauto] tactics, and
automated forward reasoning via the [Ltac] hypothesis matching
machinery. Using these features together with Ltac's scripting facilities
will enable us to make our proofs startlingly short! Used properly,
they can also make proofs more maintainable and robust in the face
of incremental changes to underlying definitions.
There's a third major source of automation we haven't
fully studied yet, namely built-in decision procedures for specific
kinds of problems: [omega] is one example, but there are others.
This topic will be defered for a while longer.
*)
(** Our motivating example will be this proof, repeated with
just a few small changes from [Imp]. We will try to simplify
this proof in several stages. *)
Ltac inv H := inversion H; subst; clear H.
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2.
Case "E_Skip". reflexivity.
Case "E_Ass". reflexivity.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption.
Case "E_IfTrue".
SCase "b evaluates to true".
apply IHE1. assumption.
SCase "b evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
SCase "b evaluates to false".
apply IHE1. assumption.
Case "E_WhileEnd".
SCase "b evaluates to false".
reflexivity.
SCase "b evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". apply IHE1_1; assumption.
subst st'0.
apply IHE1_2. assumption. Qed.
(** * The [auto] and [eauto] tactics *)
(** Thus far, we have (nearly) always written proof scripts that
apply relevant hypothoses or lemmas by name. In particular, when
a chain of hypothesis applications is needed, we have specified
them explicitly. (The only exceptions introduced so far are using
[assumption] to find a matching unqualified hypothesis
or [(e)constructor] to find a matching constructor.) *)
Example auto_example_1 : forall (P Q R: Prop), (P -> Q) -> (Q -> R) -> P -> R.
Proof.
intros P Q R H1 H2 H3.
apply H2. apply H1. assumption.
Qed.
(** The [auto] tactic frees us from this drudgery by _searching_
for a sequence of applications that will prove the goal *)
Example auto_example_1' : forall (P Q R: Prop), (P -> Q) -> (Q -> R) -> P -> R.
Proof.
intros P Q R H1 H2 H3.
auto.
Qed.
(** The [auto] tactic solves goals that are solvable by any combination of
- [intros],
- [apply] (with a local hypothesis, by default).
The [eauto] tactic works just like [auto], except that it uses
[eapply] instead of [apply]. *)
(** Using [auto] is always "safe" in the sense that it will never fail
and will never change the proof state: either it completely solves
the current goal, or it does nothing.
*)
(** A more complicated example: *)
Example auto_example_2 : forall P Q R S T U : Prop,
(P -> Q) ->
(P -> R) ->
(T -> R) ->
(S -> T -> U) ->
((P->Q) -> (P->S)) ->
T ->
P ->
U.
Proof. auto. Qed.
(** Search can take an arbitrarily long time, so there are limits to
how far [auto] will search by default *)
Example auto_example_3 : forall (P Q R S T U: Prop),
(P -> Q) -> (Q -> R) -> (R -> S) ->
(S -> T) -> (T -> U) -> P -> U.
Proof.
auto. (* When it cannot solve the goal, does nothing! *)
auto 6. (* Optional argument says how deep to search (default depth is 5) *)
Qed.
(** When searching for potential proofs of the current goal, [auto]
and [eauto] consider the hypotheses in the current context
together with a _hint database_ of other lemmas and constructors.
Some of the lemmas and constructors we've already seen -- e.g.,
[eq_refl], [conj], [or_introl], and [or_intror] -- are installed in this hint
database by default. *)
Example auto_example_4 : forall P Q R : Prop,
Q ->
(Q -> R) ->
P \/ (Q /\ R).
Proof.
auto. Qed.
(** If we want to see which facts [auto] is using, we can use [info_auto] instead. *)
Example auto_example_5: 2 = 2.
Proof.
info_auto. (* subsumes reflexivity because eq_refl is in hint database *)
Qed.
(** We can extend the hint database just for the purposes of one
application of [auto] or [eauto] by writing [auto using ...]. *)
Lemma le_antisym : forall n m: nat, (n <= m /\ m <= n) -> n = m.
Proof. intros. omega. Qed.
Example auto_example_6 : forall n m p : nat,
(n<= p -> (n <= m /\ m <= n)) ->
n <= p ->
n = m.
Proof.
intros.
auto. (* does nothing: auto doesn't destruct hypotheses! *)
auto using le_antisym.
Qed.
(** Of course, in any given development there will also be some of our
own specific constructors and lemmas that are used very often in
proofs. We can add these to the global hint database by writing
Hint Resolve T.
at the top level, where [T] is a top-level theorem or a
constructor of an inductively defined proposition (i.e., anything
whose type is an implication). As a shorthand, we can write
Hint Constructors c.
to tell Coq to do a [Hint Resolve] for _all_ of the constructors
from the inductive definition of [c].
It is also sometimes necessary to add
Hint Unfold d.
where [d] is a defined symbol, so that [auto] knows to expand
uses of [d] and enable further possibilities for applying
lemmas that it knows about. *)
Hint Resolve le_antisym.
Example auto_example_6' : forall n m p : nat,
(n<= p -> (n <= m /\ m <= n)) ->
n <= p ->
n = m.
Proof.
intros.
auto. (* picks up hint from database *)
Qed.
Definition is_fortytwo x := x = 42.
Example auto_example_7: forall x, (x <= 42 /\ 42 <= x) -> is_fortytwo x.
Proof.
auto. (* does nothing *)
Abort.
Hint Unfold is_fortytwo.
Example auto_example_7' : forall x, (x <= 42 /\ 42 <= x) -> is_fortytwo x.
Proof.
info_auto.
Qed.
Hint Constructors ceval.
Definition st12 := update (update empty_state X 1) Y 2.
Definition st21 := update (update empty_state X 2) Y 1.
Example auto_example_8 : exists s',
(IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI) / st21 || s'.
Proof.
eexists. info_auto.
Qed.
Example auto_example_8' : exists s',
(IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI) / st12 || s'.
Proof.
eexists. info_auto.
Qed.
(** Now let's take a pass over [ceval_deterministic] using [auto]
to simplify the proof script. We see that all simple sequences of hypothesis
applications and all uses of [reflexivity] can be replaced by [auto],
which we add to the default tactic to be applied to each case.
*)
Theorem ceval_deterministic': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; auto.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". auto.
subst st'0.
auto.
Case "E_IfTrue".
SCase "b evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
Case "E_WhileEnd".
SCase "b evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". auto.
subst st'0.
auto.
Qed.
(** When we are using a particular tactic many times in a proof,
we can use a variant of the [Proof] command to make that tactic
into a default within the proof.
Saying [Proof with t] (where [t] is an arbitrary tactic)
allows us to use [t1...] as a shorthand for [t1;t] within the proof.
As an illustration, here is an alternate version of the previous proof,
using [Proof with auto].
*)
Theorem ceval_deterministic'_alt: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof with auto.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2...
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion"...
subst st'0...
Case "E_IfTrue".
SCase "b evaluates to false (contradiction)".
rewrite H in H5. inversion H5.
Case "E_IfFalse".
SCase "b evaluates to true (contradiction)".
rewrite H in H5. inversion H5.
Case "E_WhileEnd".
SCase "b evaluates to true (contradiction)".
rewrite H in H2. inversion H2.
Case "E_WhileLoop".
SCase "b evaluates to false (contradiction)".
rewrite H in H4. inversion H4.
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion"...
subst st'0...
Qed.
(** * Searching Hypotheses *)
(** The proof has become simpler, but there is still an annoying amount
of repetition. Let's start by tackling the contradiction cases. Each
of them occurs in a situation where we have both
[H1: beval st b = false]
and
[H2: beval st b = true]
as hypotheses. The contradiction is evident, but demonstrating it
is a little complicated: we have to locate the two hypotheses [H1] and [H2]
and do a [rewrite] following by an [inversion]. We'd like to automate
this process.
Note: In fact, Coq has a built-in tactic [congruence] that will do the
job. But we'll ignore the existence of this tactic for now, in order
to demonstrate how to build forward search tactics by hand.
*)
(** As a first step, we can abstract out the piece of script in question by
writing a small amount of paramerized Ltac. *)
Ltac rwinv H1 H2 := rewrite H1 in H2; inv H2.
Theorem ceval_deterministic'': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; auto.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". auto.
subst st'0.
auto.
Case "E_IfTrue".
SCase "b evaluates to false (contradiction)".
rwinv H H5.
Case "E_IfFalse".
SCase "b evaluates to true (contradiction)".
rwinv H H5.
Case "E_WhileEnd".
SCase "b evaluates to true (contradiction)".
rwinv H H2.
Case "E_WhileLoop".
SCase "b evaluates to false (contradiction)".
rwinv H H4.
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". auto.
subst st'0.
auto. Qed.
(** But this is not much better. We really want Coq to discover
the relevant hypotheses for us. We can do this by using the
[match goal with ... end] facility of Ltac. *)
Ltac find_rwinv :=
match goal with
H1: ?E = true, H2: ?E = false |- _ => rwinv H1 H2
end.
(** In words, this [match goal] looks for two (distinct) hypotheses that have
the form of equalities with the same arbitrary expression [E] on the
left and conflicting boolean values on the right; if such hypotheses are
found, it binds [H1] and [H2] to their names, and applies the tactic
after the [=>].
Adding this tactic to our default string handles all the contradiction cases. *)
Theorem ceval_deterministic''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; try find_rwinv; auto.
Case "E_Seq".
assert (st' = st'0) as EQ1.
SCase "Proof of assertion". auto.
subst st'0.
auto.
Case "E_WhileLoop".
SCase "b evaluates to true".
assert (st' = st'0) as EQ1.
SSCase "Proof of assertion". auto.
subst st'0.
auto. Qed.
(** Finally, let's see about the remaining cases. Each of them involves
applying a conditional hypothesis to extract an equality. Currently
we have phrased these as assertions, so that we have to predict what
the resulting equality will be (although we can then use [auto]
to prove it.) An alternative is to pick the relevant
hypotheses to use, and then rewrite with them, as follows:
*)
Theorem ceval_deterministic'''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; try find_rwinv; auto.
Case "E_Seq".
rewrite (IHE1_1 st'0 H1) in *. auto.
Case "E_WhileLoop".
SCase "b evaluates to true".
rewrite (IHE1_1 st'0 H3) in *. auto. Qed.
(** Now we can automate the task of finding the relevant hypotheses to
rewrite with. *)
Ltac find_eqn :=
match goal with
H1: forall x, ?P x -> ?L = ?R, H2: ?P ?X |- _ =>
rewrite (H1 X H2) in *
end.
(** But there are several pairs of hypotheses that have the right
general form, and it seems tricky to pick out the ones we actually need.
A key trick is to realize that we can _try them all_!
Here's how this works:
- [rewrite] will fail given a trivial equation of the form [X = X].
- each execution of [match goal] will keep trying to find a valid pair of
hypotheses until the tactic on the RHS of the match succeeds;
if there are no such pairs, it fails.
- we can wrap the whole thing in a [repeat] which will keep
doing useful rewrites until only trivial ones are left.
*)
Theorem ceval_deterministic''''': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; try find_rwinv; repeat find_eqn; auto.
Qed.
(** The big pay-off in this approach is that our proof script
should be robust in the face of modest changes to our language.
For example, we can add a [REPEAT] command to the language.
(This was an exercise in [Hoare.v].) *)
Module Repeat.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE"
| Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
| E_RepeatEnd : forall st st' b1 c1,
ceval st c1 st' ->
beval st' b1 = true ->
ceval st (CRepeat c1 b1) st'
| E_RepeatLoop : forall st st' st'' b1 c1,
ceval st c1 st' ->
beval st' b1 = false ->
ceval st' (CRepeat c1 b1) st'' ->
ceval st (CRepeat c1 b1) st''
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass"
| Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_RepeatEnd" | Case_aux c "E_RepeatLoop"
].
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; try find_rwinv; repeat find_eqn; auto.
Case "E_RepeatEnd".
SCase "b evaluates to false (contradiction)".
find_rwinv.
(* oops: why didn't [find_rwinv] solve this for us already?
answer: we did things in the wrong order. *)
case "E_RepeatLoop".
SCase "b evaluates to true (contradiction)".
find_rwinv.
Qed.
Theorem ceval_deterministic': forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof.
intros c st st1 st2 E1 E2;
generalize dependent st2;
ceval_cases (induction E1) Case;
intros st2 E2; inv E2; repeat find_eqn; try find_rwinv; auto.
Qed.
End Repeat.
(** These examples just give a flavor of what "hyper-automation" can do...
The details of using [match goal] are tricky, and debugging is
not pleasant at all. But it is well worth adding at least simple
uses to your proofs to avoid tedium and "future proof" your scripts.
*)
(* $Date: 2014-10-27 22:05:24 -0400 (Mon, 27 Oct 2014) $ *)
|
module rc4_tb();
wire control_out;
wire [7:0] streamvalue;
reg clk, rst_n, control_in, write, read;
reg [7:0] keylength, keydata;
rc4 U1(
.control_out(control_out),
.streamvalue(streamvalue),
.clk(clk),
.rst_n(rst_n),
.control_in(control_in),
.keylength(keylength),
.keydata(keydata),
.write(write),
.read(read)
);
initial begin
clk = 0;
rst_n = 1;
control_in = 0; write = 0;
keylength = 8'b0;
keydata = 8'b0;
write = 0;
read = 0;
#1;
keylength = 3;
keydata = 75;
write = 1;
#1 write = 0;
#9;
keydata = 101;
write = 1;
#1 write = 0;
#9;
keydata = 121;
write = 1;
#1 write = 0;
#1525;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
#10;
control_in = 1; write = 1;
#1
control_in = 0; write = 0;
end
always @(posedge clk) begin
/*if (control_out) begin
control_in = 0; write = 0;
end*/
end
always #1 clk = ~clk;
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
// NFC_Toggle_Top_DDR100 for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NFC_Toggle_Top_DDR100
// Module Name: NFC_Toggle_Top_DDR100
// File Name: NFC_Toggle_Top_DDR100.v
//
// Version: v1.0.0
//
// Description: NFC top
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NFC_Toggle_Top_DDR100
#
(
parameter IDelayValue = 13 ,
parameter InputClockBufferType = 0 ,
parameter NumberOfWays = 8
)
(
iSystemClock ,
iDelayRefClock ,
iOutputDrivingClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iAddress ,
iLength ,
iCMDValid ,
oCMDReady ,
iWriteData ,
iWriteLast ,
iWriteValid ,
oWriteReady ,
oReadData ,
oReadLast ,
oReadValid ,
iReadReady ,
oReadyBusy ,
IO_NAND_DQS_P ,
IO_NAND_DQS_N ,
IO_NAND_DQ ,
O_NAND_CE ,
O_NAND_WE ,
O_NAND_RE_P ,
O_NAND_RE_N ,
O_NAND_ALE ,
O_NAND_CLE ,
I_NAND_RB ,
O_NAND_WP
);
input iSystemClock ; // SDR 100MHz
input iDelayRefClock ; // SDR 200Mhz
input iOutputDrivingClock ; // SDR 200Mhz
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input [31:0] iAddress ;
input [15:0] iLength ;
input iCMDValid ;
output oCMDReady ;
input [31:0] iWriteData ;
input iWriteLast ;
input iWriteValid ;
output oWriteReady ;
output [31:0] oReadData ;
output oReadLast ;
output oReadValid ;
input iReadReady ;
output [NumberOfWays - 1:0] oReadyBusy ; // bypass
inout IO_NAND_DQS_P ; // Differential: Positive
inout IO_NAND_DQS_N ; // Differential: Negative
inout [7:0] IO_NAND_DQ ;
output [NumberOfWays - 1:0] O_NAND_CE ;
output O_NAND_WE ;
output O_NAND_RE_P ; // Differential: Positive
output O_NAND_RE_N ; // Differential: Negative
output O_NAND_ALE ;
output O_NAND_CLE ;
input [NumberOfWays - 1:0] I_NAND_RB ;
output O_NAND_WP ;
// Internal Wires/Regs
// Primitive Command Generator (P.C.G.) ~~~ Primitive Machine (P.M.)
wire [7:0] wPM_Ready_PCG_PM ;
wire [7:0] wPM_LastStep_PCG_PM ;
wire [7:0] wPM_PCommand_PCG_PM ;
wire [2:0] wPM_PCommandOption_PCG_PM ;
wire [NumberOfWays - 1:0] wPM_TargetWay_PCG_PM ;
wire [15:0] wPM_NumOfData_PCG_PM ;
wire wPM_CEHold_PCG_PM ;
wire wPM_NANDPowerOnEvent_PCG_PM ;
wire wPM_CASelect_PCG_PM ;
wire [7:0] wPM_CAData_PCG_PM ;
wire [31:0] wPM_WriteData_PCG_PM ;
wire wPM_WriteLast_PCG_PM ;
wire wPM_WriteValid_PCG_PM ;
wire wPM_WriteReady_PCG_PM ;
wire [31:0] wPM_ReadData_PCG_PM ;
wire wPM_ReadLast_PCG_PM ;
wire wPM_ReadValid_PCG_PM ;
wire wPM_ReadReady_PCG_PM ;
wire [NumberOfWays - 1:0] wReadyBusy_PCG_PM ;
// Primitive Machine (P.M.) ~~~ Physical Module (PHY)
wire wPI_Reset_PM_PHY ;
wire wPI_BUFF_Reset_PM_PHY ;
wire wPO_Reset_PM_PHY ;
wire wPI_BUFF_RE_PM_PHY ;
wire wPI_BUFF_WE_PM_PHY ;
wire [2:0] wPI_BUFF_OutSel_PM_PHY ;
wire wPI_BUFF_Empty_PM_PHY ;
wire [31:0] wPI_DQ_PM_PHY ;
wire [3:0] wPI_ValidFlag_PM_PHY ;
wire wPIDelayTapLoad_PM_PHY ;
wire [4:0] wPIDelayTap_PM_PHY ;
wire wPIDelayReady_PM_PHY ;
wire [7:0] wPO_DQStrobe_PM_PHY ;
wire [31:0] wPO_DQ_PM_PHY ;
wire [2*NumberOfWays - 1:0] wPO_ChipEnable_PM_PHY ;
wire [3:0] wPO_ReadEnable_PM_PHY ;
wire [3:0] wPO_WriteEnable_PM_PHY ;
wire [3:0] wPO_AddressLatchEnable_PM_PHY ;
wire [3:0] wPO_CommandLatchEnable_PM_PHY ;
wire [NumberOfWays - 1:0] wReadyBusy_PM_PHY ;
wire wWriteProtect_PM_PHY ;
wire wDQSOutEnable_PM_PHY ;
wire wDQOutEnable_PM_PHY ;
// Primitive Command Generator (P.C.G.)
NPCG_Toggle_Top
#
(
.NumberOfWays (NumberOfWays )
)
Inst_NPCG_Toggle_Top
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
// Dispatcher Interface
// - Command Channel
.iOpcode (iOpcode ),
.iTargetID (iTargetID ),
.iSourceID (iSourceID ),
.iAddress (iAddress ),
.iLength (iLength ),
.iCMDValid (iCMDValid ),
.oCMDReady (oCMDReady ),
// - Data Write Channel
.iWriteData (iWriteData ),
.iWriteLast (iWriteLast ),
.iWriteValid (iWriteValid ),
.oWriteReady (oWriteReady ),
// - Data Read Channel
.oReadData (oReadData ),
.oReadLast (oReadLast ),
.oReadValid (oReadValid ),
.iReadReady (iReadReady ),
// - Miscellaneous Information Channel
.oReadyBusy (oReadyBusy ),
// NPCG_Toggle Interface
.iPM_Ready (wPM_Ready_PCG_PM),
.iPM_LastStep (wPM_LastStep_PCG_PM),
.oPM_PCommand (wPM_PCommand_PCG_PM),
.oPM_PCommandOption (wPM_PCommandOption_PCG_PM),
.oPM_TargetWay (wPM_TargetWay_PCG_PM),
.oPM_NumOfData (wPM_NumOfData_PCG_PM),
.oPM_CEHold (wPM_CEHold_PCG_PM),
.oPM_NANDPowerOnEvent (wPM_NANDPowerOnEvent_PCG_PM),
.oPM_CASelect (wPM_CASelect_PCG_PM),
.oPM_CAData (wPM_CAData_PCG_PM),
.oPM_WriteData (wPM_WriteData_PCG_PM),
.oPM_WriteLast (wPM_WriteLast_PCG_PM),
.oPM_WriteValid (wPM_WriteValid_PCG_PM),
.iPM_WriteReady (wPM_WriteReady_PCG_PM),
.iPM_ReadData (wPM_ReadData_PCG_PM),
.iPM_ReadLast (wPM_ReadLast_PCG_PM),
.iPM_ReadValid (wPM_ReadValid_PCG_PM),
.oPM_ReadReady (wPM_ReadReady_PCG_PM),
.iReadyBusy (wReadyBusy_PCG_PM )
);
// Primitive Machine (P.M.)
NPM_Toggle_Top_DDR100
#
(
.NumberOfWays (NumberOfWays )
)
Inst_NPM_Toggle_Top
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
// NPCG_Toggle Interface
.oPM_Ready (wPM_Ready_PCG_PM),
.oPM_LastStep (wPM_LastStep_PCG_PM),
.iPCommand (wPM_PCommand_PCG_PM),
.iPCommandOption (wPM_PCommandOption_PCG_PM),
.iTargetWay (wPM_TargetWay_PCG_PM),
.iNumOfData (wPM_NumOfData_PCG_PM),
.iCEHold (wPM_CEHold_PCG_PM),
.iNANDPowerOnEvent (wPM_NANDPowerOnEvent_PCG_PM),
.iCASelect (wPM_CASelect_PCG_PM),
.iCAData (wPM_CAData_PCG_PM),
.iWriteData (wPM_WriteData_PCG_PM),
.iWriteLast (wPM_WriteLast_PCG_PM),
.iWriteValid (wPM_WriteValid_PCG_PM),
.oWriteReady (wPM_WriteReady_PCG_PM),
.oReadData (wPM_ReadData_PCG_PM),
.oReadLast (wPM_ReadLast_PCG_PM),
.oReadValid (wPM_ReadValid_PCG_PM),
.iReadReady (wPM_ReadReady_PCG_PM),
.oReadyBusy (wReadyBusy_PCG_PM),
// NPhy_Toggle Interface
// - RESET Interface
.oPI_Reset (wPI_Reset_PM_PHY),
.oPI_BUFF_Reset (wPI_BUFF_Reset_PM_PHY),
.oPO_Reset (wPO_Reset_PM_PHY),
// - PI Interface
.oPI_BUFF_RE (wPI_BUFF_RE_PM_PHY),
.oPI_BUFF_WE (wPI_BUFF_WE_PM_PHY),
.oPI_BUFF_OutSel (wPI_BUFF_OutSel_PM_PHY),
.iPI_BUFF_Empty (wPI_BUFF_Empty_PM_PHY),
.iPI_DQ (wPI_DQ_PM_PHY),
.iPI_ValidFlag (wPI_ValidFlag_PM_PHY),
.oPIDelayTapLoad (wPIDelayTapLoad_PM_PHY),
.oPIDelayTap (wPIDelayTap_PM_PHY),
.iPIDelayReady (wPIDelayReady_PM_PHY),
// - PO Interface
.oPO_DQStrobe (wPO_DQStrobe_PM_PHY),
.oPO_DQ (wPO_DQ_PM_PHY),
.oPO_ChipEnable (wPO_ChipEnable_PM_PHY),
.oPO_ReadEnable (wPO_ReadEnable_PM_PHY),
.oPO_WriteEnable (wPO_WriteEnable_PM_PHY),
.oPO_AddressLatchEnable (wPO_AddressLatchEnable_PM_PHY),
.oPO_CommandLatchEnable (wPO_CommandLatchEnable_PM_PHY),
// - Miscellaneous Physical Interface
.iReadyBusy (wReadyBusy_PM_PHY),
.oWriteProtect (wWriteProtect_PM_PHY),
// - Pad Interface
.oDQSOutEnable (wDQSOutEnable_PM_PHY),
.oDQOutEnable (wDQOutEnable_PM_PHY )
);
// Physical Module (PHY)
NPhy_Toggle_Top_DDR100
#
(
.IDelayValue (IDelayValue ),
.InputClockBufferType (InputClockBufferType ),
.NumberOfWays (NumberOfWays )
)
Inst_NPhy_Toggle_Top
(
.iSystemClock (iSystemClock ),
.iDelayRefClock (iDelayRefClock ),
.iOutputDrivingClock (iOutputDrivingClock ),
// NPhy_Toggle Interface
// - RESET Interface
.iPI_Reset (wPI_Reset_PM_PHY),
.iPI_BUFF_Reset (wPI_BUFF_Reset_PM_PHY),
.iPO_Reset (wPO_Reset_PM_PHY),
// - PI Interface
.iPI_BUFF_RE (wPI_BUFF_RE_PM_PHY),
.iPI_BUFF_WE (wPI_BUFF_WE_PM_PHY),
.iPI_BUFF_OutSel (wPI_BUFF_OutSel_PM_PHY),
.oPI_BUFF_Empty (wPI_BUFF_Empty_PM_PHY),
.oPI_DQ (wPI_DQ_PM_PHY),
.oPI_ValidFlag (wPI_ValidFlag_PM_PHY),
.iPIDelayTapLoad (wPIDelayTapLoad_PM_PHY),
.iPIDelayTap (wPIDelayTap_PM_PHY),
.oPIDelayReady (wPIDelayReady_PM_PHY),
// - PO Interface
.iPO_DQStrobe (wPO_DQStrobe_PM_PHY),
.iPO_DQ (wPO_DQ_PM_PHY),
.iPO_ChipEnable (wPO_ChipEnable_PM_PHY),
.iPO_ReadEnable (wPO_ReadEnable_PM_PHY),
.iPO_WriteEnable (wPO_WriteEnable_PM_PHY),
.iPO_AddressLatchEnable (wPO_AddressLatchEnable_PM_PHY),
.iPO_CommandLatchEnable (wPO_CommandLatchEnable_PM_PHY),
// - Miscellaneous Physical Interface
.oReadyBusy (wReadyBusy_PM_PHY),
.iWriteProtect (wWriteProtect_PM_PHY),
// - Pad Interface
.iDQSOutEnable (wDQSOutEnable_PM_PHY),
.iDQOutEnable (wDQOutEnable_PM_PHY),
// NAND Interface
.IO_NAND_DQS_P (IO_NAND_DQS_P ), // Differential: Positive
.IO_NAND_DQS_N (IO_NAND_DQS_N ), // Differential: Positive
.IO_NAND_DQ (IO_NAND_DQ ),
.O_NAND_CE (O_NAND_CE ),
.O_NAND_WE (O_NAND_WE ),
.O_NAND_RE_P (O_NAND_RE_P ), // Differential: Positive
.O_NAND_RE_N (O_NAND_RE_N ), // Differential: Positive
.O_NAND_ALE (O_NAND_ALE ),
.O_NAND_CLE (O_NAND_CLE ),
.I_NAND_RB (I_NAND_RB ),
.O_NAND_WP (O_NAND_WP )
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: mcb_flow_control.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:21 $
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Virtex 6
//Design Name: DDR2/DDR3
//Purpose: This module is the main flow control between cmd_gen.v,
// write_data_path and read_data_path modules.
//Reference:
//Revision History: 7/29/10 Support V6 Back-to-back commands over user interface.
//
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_memc_flow_vcontrol #
(
parameter TCQ = 100,
parameter nCK_PER_CLK = 4,
parameter NUM_DQ_PINS = 32,
parameter BL_WIDTH = 6,
parameter MEM_BURST_LEN = 4,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3"
)
(
input clk_i,
input [9:0] rst_i,
input [3:0] data_mode_i,
input [5:0] cmds_gap_delay_value,
input mem_pattern_init_done_i,
// interface to cmd_gen, pipeline inserter
output reg cmd_rdy_o,
input cmd_valid_i,
input [2:0] cmd_i,
input [31:0] addr_i,
input [BL_WIDTH - 1:0] bl_i,
// interface to mcb_cmd port
input mcb_cmd_full,
input mcb_wr_full_i,
output reg [2:0] cmd_o,
output [31:0] addr_o,
output reg [BL_WIDTH-1:0] bl_o,
output cmd_en_o, // interface to write data path module
// *** interface to qdr ****
output reg qdr_rd_cmd_o,
// *************************
input mcb_wr_en_i,
input last_word_wr_i,
input wdp_rdy_i,
output reg wdp_valid_o,
output reg wdp_validB_o,
output reg wdp_validC_o,
output [31:0] wr_addr_o,
output [BL_WIDTH-1:0] wr_bl_o,
// interface to read data path module
input rdp_rdy_i,
output reg rdp_valid_o,
output [31:0] rd_addr_o,
output [BL_WIDTH-1:0] rd_bl_o
);
//FSM State Defination
localparam READY = 4'b0001,
READ = 4'b0010,
WRITE = 4'b0100,
CMD_WAIT = 4'b1000;
localparam RD = 3'b001;
localparam RDP = 3'b011;
localparam WR = 3'b000;
localparam WRP = 3'b010;
localparam REFRESH = 3'b100;
localparam NOP = 3'b101;
reg cmd_fifo_rdy;
reg push_cmd;
reg cmd_rdy;
reg [31:0] addr_r;
reg [2:0] cmd_reg;
reg [31:0] addr_reg;
reg [BL_WIDTH-1:0] bl_reg;
reg [BL_WIDTH:0] cmd_counts;
reg rdp_valid;
(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg wdp_valid,wdp_validB,wdp_validC;
reg [3:0] current_state;
reg [3:0] next_state;
reg push_cmd_r;
reg cmd_en_r1;
reg wr_in_progress;
reg wrcmd_in_progress;
reg rdcmd_in_progress;
reg [5:0] commands_delay_counters;
reg goahead;
reg cmd_en_r2;
reg cmd_wr_pending_r1;
reg [3:0] addr_INC;
reg COuta;
wire cmd_rd;
wire cmd_wr;
always @ (posedge clk_i) begin
if (data_mode_i == 4'b1000 || FAMILY == "SPARTAN6")
addr_INC <= #TCQ 0;
else
addr_INC <= #TCQ MEM_BURST_LEN[3:0];
end
// mcb_command bus outputs
always @(posedge clk_i) begin
if (rst_i[0]) begin
commands_delay_counters <= 6'b00000;
goahead <= 1'b1;
end
else if (cmds_gap_delay_value == 5'd0)
goahead <= 1'b1;
else if (wr_in_progress || wrcmd_in_progress ||
rdcmd_in_progress || cmd_rdy_o) begin
commands_delay_counters <= 6'b00000;
goahead <= 1'b0;
end
else if (commands_delay_counters == cmds_gap_delay_value) begin
commands_delay_counters <= commands_delay_counters;
goahead <= 1'b1;
end
else
commands_delay_counters <= commands_delay_counters + 1'b1;
end
assign cmd_en_o = (FAMILY == "VIRTEX6") ? cmd_en_r1 : (~cmd_en_r1 & cmd_en_r2) ;
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ cmd_rdy;
always @ (posedge clk_i) begin
if (rst_i[8])
cmd_en_r1 <= #TCQ 1'b0;
else if (cmd_counts == 1 && (!mcb_cmd_full && cmd_en_r1 || mcb_wr_full_i))
cmd_en_r1 <= #TCQ 1'b0;
else if ((rdcmd_in_progress || wrcmd_in_progress && MEM_TYPE != "QDR2PLUS") ||
(mcb_wr_en_i && MEM_TYPE == "QDR2PLUS"))
cmd_en_r1 <= #TCQ 1'b1;
else if (!mcb_cmd_full)
cmd_en_r1 <= #TCQ 1'b0;
end
always @ (posedge clk_i)
if (rst_i[8])
cmd_en_r2 <= #TCQ 1'b0;
else
cmd_en_r2 <= cmd_en_r1;
// QDR read command generation
always @ (posedge clk_i) begin
if (rst_i[8])
qdr_rd_cmd_o <= #TCQ 1'b0;
else if (cmd_counts == 1 && !mcb_cmd_full && rdcmd_in_progress && cmd_en_r1)
qdr_rd_cmd_o <= #TCQ 1'b0;
else if (rdcmd_in_progress)
qdr_rd_cmd_o <= #TCQ 1'b1;
else if (!mcb_cmd_full)
qdr_rd_cmd_o <= #TCQ 1'b0;
end
always @ (posedge clk_i) begin
if (rst_i[9])
cmd_fifo_rdy <= #TCQ 1'b1;
else if (cmd_en_r1 || mcb_cmd_full)
cmd_fifo_rdy <= #TCQ 1'b0;
else if (!mcb_cmd_full)
cmd_fifo_rdy <= #TCQ 1'b1;
end
always @ (posedge clk_i) begin
if (rst_i[9]) begin
cmd_o <= #TCQ 'b0;
bl_o <= #TCQ 'b0;
end
else if (push_cmd_r && current_state == READ) begin
cmd_o <= #TCQ cmd_i;
bl_o <= #TCQ bl_i - 'b1;
end
else if (push_cmd_r && current_state == WRITE) begin
if (FAMILY == "SPARTAN6")
cmd_o <= #TCQ cmd_reg;
else
cmd_o <= #TCQ {2'b00,cmd_reg[0]};
bl_o <= #TCQ bl_reg;
end
end
always @ (posedge clk_i)
if ((push_cmd && mem_pattern_init_done_i) | rst_i)
addr_reg <= #TCQ addr_i;
else if (push_cmd && !mem_pattern_init_done_i)
addr_reg <= #TCQ addr_r;
always @ (posedge clk_i) begin
if (push_cmd && cmd_rd || rst_i[0])
addr_r <= #TCQ addr_i;
else if (push_cmd_r && current_state != READ)
addr_r <= #TCQ addr_reg;
else if ((wrcmd_in_progress || rdcmd_in_progress) &&
cmd_en_r1 && ~mcb_cmd_full) begin
if (MEM_TYPE == "QDR2PLUS")
{COuta,addr_r[31:0]} <= addr_o + 1;
else
{COuta,addr_r[31:0]} <= addr_o + addr_INC;
end
end
assign addr_o = addr_r;
assign wr_addr_o = addr_i;
assign rd_addr_o = addr_i;
assign rd_bl_o = bl_i;
assign wr_bl_o = bl_i;
always @ (posedge clk_i) begin
wdp_valid_o <= wdp_valid;
wdp_validB_o <= wdp_validB;
wdp_validC_o <= wdp_validC;
end
always @ (posedge clk_i)
rdp_valid_o <= rdp_valid;
always @(posedge clk_i)
push_cmd_r <= #TCQ push_cmd;
always @(posedge clk_i)
if (push_cmd) begin
cmd_reg <= #TCQ cmd_i;
bl_reg <= #TCQ bl_i - 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i[8])
cmd_counts <= #TCQ 'b0;
else if (push_cmd_r) begin
if (bl_i == 0) begin
if (MEM_BURST_LEN == 8) begin
if (nCK_PER_CLK == 4)
cmd_counts <= #TCQ {2'b01, {BL_WIDTH-1{1'b0}}};
else
cmd_counts <= #TCQ {3'b001, {BL_WIDTH-2{1'b0}}};
end
else
cmd_counts <= {1'b0,{BL_WIDTH{1'b1}}} ;//- 2;//63;
end
else begin
if (MEM_BURST_LEN == 8) begin
if (nCK_PER_CLK == 4)
cmd_counts <= {1'b0,bl_i};
else
cmd_counts <= {3'b000,bl_i[BL_WIDTH-2:1]};
end
else
cmd_counts <= {1'b0,bl_i};//- 1 ;// {1'b0,bl_i[5:1]} -2;
end
end
else if ((wrcmd_in_progress || rdcmd_in_progress) && cmd_en_r1 && ~mcb_cmd_full) begin
if (cmd_counts > 0) begin
if (FAMILY == "VIRTEX6")
cmd_counts <= cmd_counts - 1'b1;
else if (wrcmd_in_progress)
cmd_counts <= cmd_counts - 1'b1;
else
cmd_counts <= 0;
end
end
end
//--Command Decodes--
assign cmd_wr = ((cmd_i == WR | cmd_i == WRP) & cmd_valid_i) ? 1'b1 : 1'b0;
assign cmd_rd = ((cmd_i == RD | cmd_i == RDP) & cmd_valid_i) ? 1'b1 : 1'b0;
always @ (posedge clk_i) begin
if (rst_i[0])
cmd_wr_pending_r1 <= #TCQ 1'b0;
else if (last_word_wr_i)
cmd_wr_pending_r1 <= #TCQ 1'b1;
else if (push_cmd & cmd_wr)
cmd_wr_pending_r1 <= #TCQ 1'b0;
end
always @ (posedge clk_i) begin
if (rst_i[0])
wr_in_progress <= #TCQ 1'b0;
else if (last_word_wr_i)
wr_in_progress <= #TCQ 1'b0;
else if (push_cmd && cmd_wr)
wr_in_progress <= #TCQ 1'b1;
end
always @ (posedge clk_i) begin
if (rst_i[0])
wrcmd_in_progress <= #TCQ 1'b0;
else if (cmd_wr && push_cmd_r)
wrcmd_in_progress <= #TCQ 1'b1;
else if (cmd_counts == 0 || (cmd_counts == 1 && ~mcb_cmd_full))
wrcmd_in_progress <= #TCQ 1'b0;
end
always @ (posedge clk_i) begin
if (rst_i[0])
rdcmd_in_progress <= #TCQ 1'b0;
else if (cmd_rd && push_cmd_r)
rdcmd_in_progress <= #TCQ 1'b1;
else if (cmd_counts <= 1)
rdcmd_in_progress <= #TCQ 1'b0;
end
// mcb_flow_control statemachine
always @ (posedge clk_i)
if (rst_i[0])
current_state <= #TCQ 5'b00001;
else
current_state <= #TCQ next_state;
always @ (*) begin
push_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
cmd_rdy = 1'b0;
next_state = current_state;
case(current_state) // next state logic
READY: begin // 5'h01
if (rdp_rdy_i && cmd_rd && ~mcb_cmd_full) begin
next_state = READ;
push_cmd = 1'b1;
rdp_valid = 1'b1;
cmd_rdy = 1'b1;
end
else if (wdp_rdy_i && cmd_wr && ~mcb_cmd_full) begin
next_state = WRITE;
push_cmd = 1'b1;
wdp_valid = 1'b1;
wdp_validB = 1'b1;
wdp_validC = 1'b1;
cmd_rdy = 1'b1;
end
else begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
end
end // READY
READ: begin // 5'h02
if (rdcmd_in_progress) begin
next_state = READ;
push_cmd = 1'b0;
rdp_valid = 1'b0;
wdp_valid = 1'b0;
end
else if (!rdp_rdy_i) begin
next_state = READ;
push_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
rdp_valid = 1'b0;
end
else if (~cmd_fifo_rdy && ~rdcmd_in_progress && goahead) begin
next_state = CMD_WAIT;
end
else if (goahead && ~push_cmd_r) begin
next_state = READY;
cmd_rdy = 1'b0;
end
else
next_state = READ;
end // READ
WRITE: begin // 5'h04
if (wr_in_progress || wrcmd_in_progress || push_cmd_r) begin
next_state = WRITE;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
push_cmd = 1'b0;
end
else if (!cmd_fifo_rdy && last_word_wr_i && goahead) begin
next_state = CMD_WAIT;
push_cmd = 1'b0;
end
else if (goahead) begin
next_state = READY;
end
else
next_state = WRITE;
cmd_rdy = 1'b0;
end // WRITE
CMD_WAIT: begin // 5'h08
if (!cmd_fifo_rdy || wr_in_progress) begin
next_state = CMD_WAIT;
cmd_rdy = 1'b0;
end
else if (cmd_fifo_rdy && rdp_rdy_i && cmd_rd) begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
rdp_valid = 1'b0;
end
else if (cmd_fifo_rdy && cmd_wr && goahead &&
cmd_wr_pending_r1) begin
next_state = READY;
push_cmd = 1'b0;
cmd_rdy = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
end
else begin
next_state = CMD_WAIT;
cmd_rdy = 1'b0;
end
end // CMD_WAIT
default: begin
push_cmd = 1'b0;
wdp_valid = 1'b0;
wdp_validB = 1'b0;
wdp_validC = 1'b0;
next_state = READY;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
/*******************************************************************************
* Engineer: Robin zhang
* Create Date: 2016.09.10
* Module Name: spi_slave
*******************************************************************************/
module spi_slave_freertos(
clk,sck,mosi,miso,ssel,rst_n,recived_status
);
input clk;
input rst_n;
input sck,mosi,ssel;
output miso;
output recived_status;
reg recived_status;
reg[2:0] sckr;
reg[2:0] sselr;
reg[1:0] mosir;
reg[2:0] bitcnt;
reg[7:0] bytecnt;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
reg[7:0] received_memory;
reg [7:0] byte_data_sent;
reg [7:0] cnt;
wire ssel_active;
wire sck_risingedge;
wire sck_fallingedge;
wire ssel_startmessage;
wire ssel_endmessage;
wire mosi_data;
/*******************************************************************************
*detect the rising edge and falling edge of sck
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sckr <= 3'h0;
else
sckr <= {sckr[1:0],sck};
end
assign sck_risingedge = (sckr[2:1] == 2'b01) ? 1'b1 : 1'b0;
assign sck_fallingedge = (sckr[2:1] == 2'b10) ? 1'b1 : 1'b0;
/*******************************************************************************
*detect starts at falling edge and stops at rising edge of ssel
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
sselr <= 3'h0;
else
sselr <= {sselr[1:0],ssel};
end
assign ssel_active = (~sselr[1]) ? 1'b1 : 1'b0; // SSEL is active low
assign ssel_startmessage = (sselr[2:1]==2'b10) ? 1'b1 : 1'b0; // message starts at falling edge
assign ssel_endmessage = (sselr[2:1]==2'b01) ? 1'b1 : 1'b0; // message stops at rising edge
/*******************************************************************************
*read from mosi
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)
mosir <= 2'h0;
else
mosir <={mosir[0],mosi};
end
assign mosi_data = mosir[1];
/*******************************************************************************
*SPI slave reveive in 8-bits format
*******************************************************************************/
always @(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bitcnt <= 3'b000;
byte_data_received <= 8'h0;
end
else begin
if(~ssel_active)
bitcnt <= 3'b000;
else begin
if(sck_risingedge)begin
bitcnt <= bitcnt + 3'b001;
byte_data_received <= {byte_data_received[6:0], mosi_data};
end
else begin
bitcnt <= bitcnt;
byte_data_received <= byte_data_received;
end
end
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_received <= 1'b0;
else
byte_received <= ssel_active && sck_risingedge && (bitcnt==3'b111);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)begin
bytecnt <= 8'h0;
received_memory <= 8'h0;
end
else begin
if(byte_received) begin
bytecnt <= bytecnt + 1'b1;
received_memory <= (byte_data_received == bytecnt) ? (received_memory + 1'b1) : received_memory;
end
else begin
bytecnt <= bytecnt;
received_memory <= received_memory;
end
end
end
/*******************************************************************************
*SPI slave send date
*******************************************************************************/
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
cnt<= 8'hFF;
else begin
if(byte_received)
cnt<=cnt - 8'h1; // count the messages
else
cnt<=cnt;
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
byte_data_sent <= 8'hFF;
else begin
if(ssel_active && sck_fallingedge) begin
if(bitcnt==3'b000)
byte_data_sent <= cnt; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[6:0], 1'b0};
end
else
byte_data_sent <= byte_data_sent;
end
end
assign miso = byte_data_sent[7]; // send MSB first
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
recived_status <= 1'b0;
else
recived_status <= 1'b1;
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// surefire lint_off _NETNM
// surefire lint_off STMINI
input clk;
integer _mode; initial _mode = 0;
wire [2:0] b3; reg [2:0] g3;
wire [5:0] b6; reg [5:0] g6;
t_func_grey2bin #(3) g2b3 (.b(b3), .g(g3));
t_func_grey2bin #(6) g2b6 (.b(b6), .g(g6));
always @ (posedge clk) begin
if (_mode==0) begin
_mode <= 1;
g3 <= 3'b101;
g6 <= 6'b110101;
end
else if (_mode==1) begin
if (b3 !== 3'b110) $stop;
if (b6 !== 6'b100110) $stop;
_mode <= 2;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
// Module gray2bin
// convert an arbitrary width gray coded number to binary. The conversion
// of a 4 bit gray (represented as "g") to binary ("b") would go as follows:
// b[3] = ^g[3] = g[3]
// b[2] = ^g[3:2]
// b[1] = ^g[3:1]
// b[0] = ^g[3:[SZ-1:0] cur0]
module t_func_grey2bin (/*AUTOARG*/
// Outputs
b,
// Inputs
g
);
// surefire lint_off STMFOR
parameter SZ = 5;
output [SZ-1:0] b;
input [SZ-1:0] g;
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [SZ-1:0] b;
// End of automatics
integer i;
always @(/*AUTOSENSE*/g)
for (i=0; i<SZ; i=i+1)
b[i] = ^(g >> i); // surefire lint_off_line LATASS
endmodule
|
// Released under GPL2.0
// (c) 2002 Tom Verbeure
module main;
integer myInt;
reg [39:0] myReg40;
reg [0:39] myReg40r;
reg [0:38] myReg39r;
reg [13:0] myReg14;
reg [7:0] myReg8;
reg [31:0] myReg32;
initial begin
$display("============================ myReg8 = 65");
myReg8 = 65;
$display(">| 65|");
$display("*|%d|", myReg8);
$display("*|",myReg8,"|");
$display("============================ myReg14 = -10");
myReg14 = -10;
$display(">|16374|");
$display("*|%d|", myReg14);
$display("*|",myReg14,"|");
$display("============================ myReg14 = 65");
myReg14 = 65;
$display(">1| 65|");
$display("*1|%d|", myReg14);
$display(">2|65|");
$display("*2|%0d|", myReg14);
$display(">3| 65|");
$display("*3|%10d|", myReg14);
$display(">4| 65|");
$display("*4|%08d|", myReg14);
$display("*4|%8d|", myReg14);
$display(">5| 65|");
$display("*5|%03d|", myReg14);
$display("*5|%3d|", myReg14);
$display("============================ myReg14 = 1000");
myReg14 = 1000;
$display(">|1000|");
$display("*|%03d|", myReg14);
$finish;
$display("*|",myReg14,"|");
$display(">|0041|");
$display("*|%h|", myReg14);
$display(">|00000001000001|");
$display("*|%b|", myReg14);
$display(">|41|");
$display("*|%0h|", myReg14);
$display(">|1000001|");
$display("*|%0b|", myReg14);
$display(">| A|");
$display("*|%s|", myReg14);
$display(">|A|");
$display("*|%0s|", myReg14);
$display("============================ myInt = -10");
myInt = -10;
$display(">| -10|");
$display("*|%d|", myInt);
$display("*|",myInt,"|");
$display(">|fffffff6|");
$display("*|%h|", myInt);
$display("============================ myReg32 = -10");
myReg32 = -10;
$display(">|4294967286|");
$display("*|%d|", myReg32);
$display("*|",myReg32,"|");
$display(">|fffffff6|");
$display("*|%h|", myReg32);
$display("============================ myInt = 65");
myInt = 65;
$display(">| 65|");
$display("*|%d|", myInt);
$display("*|",myInt,"|");
$display("*| A|");
$display(">|%s|", myInt);
$display("*|A|");
$display(">|%0s|", myInt);
$display("============================ myReg32 = 65");
myReg32 = 65;
$display(">| 65|");
$display("*|%d|", myReg32);
$display("*|",myReg32,"|");
$display("*| A|");
$display(">|%s|", myReg32);
$display("*|A|");
$display(">|%0s|", myReg32);
$display("*| A|");
$display(">|%s|", " A");
$display("*| A|");
$display(">|%0s|", " A");
$display("*|0|");
$display(">|%0t|", $time);
$display("*| 0|");
$display(">|%t|", $time);
end
endmodule
|
/* Top level module for keypad + UART demo */
module top (
// input hardware clock (12 MHz)
hwclk,
// all LEDs
led1,
// UART lines
ftdi_tx,
);
/* Clock input */
input hwclk;
/* LED outputs */
output led1;
/* FTDI I/O */
output ftdi_tx;
/* 9600 Hz clock generation (from 12 MHz) */
reg clk_9600 = 0;
reg [31:0] cntr_9600 = 32'b0;
parameter period_9600 = 625;
/* 1 Hz clock generation (from 12 MHz) */
reg clk_1 = 0;
reg [31:0] cntr_1 = 32'b0;
parameter period_1 = 6000000;
// Note: could also use "0" or "9" below, but I wanted to
// be clear about what the actual binary value is.
parameter ASCII_0 = 8'd48;
parameter ASCII_9 = 8'd57;
/* UART registers */
reg [7:0] uart_txbyte = ASCII_0;
reg uart_send = 1'b1;
wire uart_txed;
/* LED register */
reg ledval = 0;
/* UART transmitter module designed for
8 bits, no parity, 1 stop bit.
*/
uart_tx_8n1 transmitter (
// 9600 baud rate clock
.clk (clk_9600),
// byte to be transmitted
.txbyte (uart_txbyte),
// trigger a UART transmit on baud clock
.senddata (uart_send),
// input: tx is finished
.txdone (uart_txed),
// output UART tx pin
.tx (ftdi_tx),
);
/* Wiring */
assign led1=ledval;
/* Low speed clock generation */
always @ (posedge hwclk) begin
/* generate 9600 Hz clock */
cntr_9600 <= cntr_9600 + 1;
if (cntr_9600 == period_9600) begin
clk_9600 <= ~clk_9600;
cntr_9600 <= 32'b0;
end
/* generate 1 Hz clock */
cntr_1 <= cntr_1 + 1;
if (cntr_1 == period_1) begin
clk_1 <= ~clk_1;
cntr_1 <= 32'b0;
end
end
/* Increment ASCII digit and blink LED */
always @ (posedge clk_1 ) begin
ledval <= ~ledval;
if (uart_txbyte == ASCII_9) begin
uart_txbyte <= ASCII_0;
end else begin
uart_txbyte <= uart_txbyte + 1;
end
end
endmodule |
/******************************************************************************/
/* FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
/***** Comparator *****/
/**************************************************************************************************/
module COMPARATOR #(parameter WIDTH = 32)
(input wire [WIDTH-1:0] DIN0,
input wire [WIDTH-1:0] DIN1,
output wire [WIDTH-1:0] DOUT0,
output wire [WIDTH-1:0] DOUT1);
wire comp_rslt = (DIN0 < DIN1);
function [WIDTH-1:0] mux;
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign DOUT0 = mux(DIN1, DIN0, comp_rslt);
assign DOUT1 = mux(DIN0, DIN1, comp_rslt);
endmodule
/***** FIFO of only two entries *****/
/**************************************************************************************************/
module MRE2 #(parameter FIFO_SIZE = 1, // dummy, just for portability
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==2);
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=~head; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=~tail; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=~head; tail<=~tail; end
endcase
end
end
endmodule
/***** Sorter cell emitting multiple values at once *****/
/**************************************************************************************************/
module SCELL #(parameter SORTW = 32,
parameter M_LOG = 2)
(input wire CLK,
input wire RST,
input wire valid1,
input wire valid2,
output wire deq1,
output wire deq2,
input wire [(SORTW<<M_LOG)-1:0] din1,
input wire [(SORTW<<M_LOG)-1:0] din2,
input wire full,
output wire [(SORTW<<M_LOG)-1:0] dout,
output wire enq);
function [(SORTW<<M_LOG)-1:0] mux;
input [(SORTW<<M_LOG)-1:0] a;
input [(SORTW<<M_LOG)-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
wire cmp = (din1[SORTW-1:0] < din2[SORTW-1:0]);
wire [(SORTW<<M_LOG)-1:0] cmp_dout = mux(din2, din1, cmp);
wire F_enq;
wire F_deq;
wire F_emp;
wire F_full;
wire [(SORTW<<M_LOG)-1:0] F_dot;
MRE2 #(1,(SORTW<<M_LOG)) F(.CLK(CLK), .RST(RST), .enq(F_enq), .deq(F_deq),
.din(cmp_dout), .dot(F_dot), .emp(F_emp), .full(F_full));
assign F_enq = &{~F_full,valid1,valid2}; // assign F_enq = (!F_full && valid1 && valid2);
assign F_deq = ~|{full,F_emp}; // assign F_deq = !full && !F_emp;
reg [(SORTW<<M_LOG)-1:0] fbdata;
reg [(SORTW<<M_LOG)-1:0] fbdata_a; // duplicated register
reg [(SORTW<<M_LOG)-1:0] fbdata_b; // duplicated register
reg fbinvoke;
assign enq = (F_deq && fbinvoke);
assign deq1 = (F_enq && cmp);
assign deq2 = (F_enq && !cmp);
localparam P_DATAWIDTH = 32;
wire [P_DATAWIDTH-1:0] a, b, c, d, e, f, g, h;
wire [P_DATAWIDTH-1:0] e_a, f_a, g_a, h_a; // for duplicated register
wire [P_DATAWIDTH-1:0] e_b, f_b, g_b, h_b; // for duplicated register
assign a = F_dot[ 31: 0];
assign b = F_dot[ 63:32];
assign c = F_dot[ 95:64];
assign d = F_dot[127:96];
assign e = fbdata[ 31: 0];
assign f = fbdata[ 63:32];
assign g = fbdata[ 95:64];
assign h = fbdata[127:96];
assign e_a = fbdata_a[ 31: 0];
assign f_a = fbdata_a[ 63:32];
assign g_a = fbdata_a[ 95:64];
assign h_a = fbdata_a[127:96];
assign e_b = fbdata_b[ 31: 0];
assign f_b = fbdata_b[ 63:32];
assign g_b = fbdata_b[ 95:64];
assign h_b = fbdata_b[127:96];
wire t0_c0 = (a < h);
wire t0_c1 = (b < g);
wire t0_c2 = (c < f);
wire t0_c3 = (d < e);
wire t0_x0 = t0_c0 ^ t0_c1;
wire t0_x1 = t0_c2 ^ t0_c3;
wire t0 = t0_x0 ^ t0_x1;
wire s2_c0 = (b < e);
wire s2_c1 = (a < f);
wire s3_c0 = (c < h);
wire s3_c1 = (d < g);
wire s4_c0 = (a < g);
wire s4_c1 = (b < f);
wire s4_c2 = (c < e);
wire s5_c0 = (d < f);
wire s5_c1 = (c < g);
wire s5_c2 = (b < h);
wire s0 = (a < e);
wire s1 = (d < h);
wire [1:0] s2 = {s0, (s2_c0 ^ s2_c1)};
wire [1:0] s3 = {s1, (s3_c0 ^ s3_c1)};
wire [2:0] s4 = {s2, (s4_c0 ^ s4_c1 ^ s4_c2)};
wire [2:0] s5 = {s3, (s5_c0 ^ s5_c1 ^ s5_c2)};
wire [3:0] s6 = {s4, t0};
wire [3:0] s7 = {s5, t0};
wire [P_DATAWIDTH-1:0] m0, m1, m2, m3, m4, m5, m6, m7;
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [32-1:0] mux4in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [1:0] sel;
begin
case (sel)
2'b00: mux4in32 = a;
2'b01: mux4in32 = b;
2'b10: mux4in32 = c;
2'b11: mux4in32 = d;
endcase
end
endfunction
function [32-1:0] mux6in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [32-1:0] e;
input [32-1:0] f;
input [2:0] sel;
begin
casex (sel)
3'b000: mux6in32 = a;
3'b001: mux6in32 = b;
3'b100: mux6in32 = c;
3'b101: mux6in32 = d;
3'bx10: mux6in32 = e;
3'bx11: mux6in32 = f;
endcase
end
endfunction
function [32-1:0] mux12in32;
input [32-1:0] a;
input [32-1:0] b;
input [32-1:0] c;
input [32-1:0] d;
input [32-1:0] e;
input [32-1:0] f;
input [32-1:0] g;
input [32-1:0] h;
input [32-1:0] i;
input [32-1:0] j;
input [32-1:0] k;
input [32-1:0] l;
input [3:0] sel;
begin
casex (sel)
4'b0000: mux12in32 = a;
4'b0001: mux12in32 = b;
4'b0010: mux12in32 = c;
4'b0011: mux12in32 = d;
4'b1000: mux12in32 = e;
4'b1001: mux12in32 = f;
4'b1010: mux12in32 = g;
4'b1011: mux12in32 = h;
4'bx100: mux12in32 = i;
4'bx101: mux12in32 = j;
4'bx110: mux12in32 = k;
4'bx111: mux12in32 = l;
endcase
end
endfunction
assign m0 = mux32(e, a, s0);
assign m1 = mux32(d, h, s1);
assign m2 = mux4in32(f, a, b, e, s2);
assign m3 = mux4in32(c, h, g, d, s3);
assign m4 = mux6in32(g, a, e, c, b, f, s4);
assign m5 = mux6in32(b, h, d, f, g, c, s5);
// using duplicated registers
assign m6 = mux12in32(h_a, a, b, g_a, f_a, c, d, e_a, f_a, c, b, g_a, s6);
assign m7 = mux12in32(a, h_b, g_b, b, c, f_b, e_b, d, c, f_b, g_b, b, s7);
// output and feedback
//////////////////////////////////////////////////////////
assign dout = {m6,m4,m2,m0}; // output
always @(posedge CLK) begin // feedback
if (RST) begin
fbdata <= 0;
fbdata_a <= 0;
fbdata_b <= 0;
fbinvoke <= 0;
end else begin
if (F_deq) begin
fbdata <= {m1,m3,m5,m7};
fbdata_a <= {m1,m3,m5,m7};
fbdata_b <= {m1,m3,m5,m7};
fbinvoke <= 1;
end
end
end
endmodule
/***** general FIFO (BRAM Version) *****/
/**************************************************************************************************/
module BFIFO #(parameter FIFO_SIZE = 2, // size in log scale, 2 for 4 entry, 3 for 8 entry
parameter FIFO_WIDTH = 32) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output reg [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head, tail;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
always @(posedge CLK) dot <= mem[head];
always @(posedge CLK) begin
if (RST) {cnt, head, tail} <= 0;
else begin
case ({enq, deq})
2'b01: begin head<=head+1; cnt<=cnt-1; end
2'b10: begin mem[tail]<=din; tail<=tail+1; cnt<=cnt+1; end
2'b11: begin mem[tail]<=din; head<=head+1; tail<=tail+1; end
endcase
end
end
endmodule
/***** Input Module Pre *****/
/**************************************************************************************************/
module INMOD2(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] din, // input data
input wire den, // input data enable
input wire IB_full, // the next module is full ?
output wire rx_wait,
output wire [`MERGW-1:0] dot, // this module's data output
output wire IB_enq, // the next module's enqueue signal
output reg [1:0] im_req); // DRAM data request
wire req;
reg deq;
wire [`DRAMW-1:0] im_dot;
(* mark_debug = "true" *) wire [`IB_SIZE:0] im_cnt;
wire im_full, im_emp;
wire im_enq = den;
wire im_deq = (req && !im_emp);
assign rx_wait = im_cnt[`IB_SIZE-1];
always @(posedge CLK) im_req <= (im_cnt==0) ? 3 : (im_cnt<`REQ_THRE);
always @(posedge CLK) deq <= im_deq;
BFIFO #(`IB_SIZE, `DRAMW) // note, using BRAM
imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq), .din(din),
.dot(im_dot), .emp(im_emp), .full(im_full), .cnt(im_cnt));
INMOD inmod(.CLK(CLK), .RST(RST), .d_dout(im_dot), .d_douten(deq),
.IB_full(IB_full), .im_dot(dot), .IB_enq(IB_enq), .im_req(req));
endmodule
/***** Input Module *****/
/**************************************************************************************************/ // todo
module INMOD(input wire CLK,
input wire RST,
input wire [`DRAMW-1:0] d_dout, // DRAM output
input wire d_douten, // DRAM output enable
input wire IB_full, // INBUF is full ?
output wire [`MERGW-1:0] im_dot, // this module's data output
output wire IB_enq,
output wire im_req); // DRAM data request
reg [`DRAMW-1:0] dot_t; // shift register to feed 32bit data
reg [1:0] cnte; // the number of enqueued elements in one block
reg cntez; // cnte==0 ?
reg cntef; // cnte==15 ?
wire [`DRAMW-1:0] dot;
wire im_emp, im_full;
wire im_enq = d_douten; // (!im_full && d_douten);
wire im_deq = (IB_enq && cntef); // old version may have a bug here!!
function [`MERGW-1:0] mux;
input [`MERGW-1:0] a;
input [`MERGW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
assign IB_enq = (!IB_full && !im_emp); // enqueue signal for the next module
assign im_req = (im_emp || im_deq); // note!!!
assign im_dot = mux(dot_t[`MERGW-1:0], dot[`MERGW-1:0], cntez);
always @(posedge CLK) begin
if (RST) begin
cnte <= 0;
end else begin
if (IB_enq) cnte <= cnte + 1;
end
end
always @(posedge CLK) begin
if (RST) begin
cntez <= 1;
end else begin
case ({IB_enq, (cnte==3)})
2'b10: cntez <= 0;
2'b11: cntez <= 1;
endcase
end
end
always @(posedge CLK) begin
if (RST) begin
cntef <= 0;
end else begin
case ({IB_enq, (cnte==2)})
2'b10: cntef <= 0;
2'b11: cntef <= 1;
endcase
end
end
always @(posedge CLK) begin
case ({IB_enq, cntez})
2'b10: dot_t <= {`MERGW'b0, dot_t[`DRAMW-1:`MERGW]};
2'b11: dot_t <= {`MERGW'b0, dot[`DRAMW-1:`MERGW]};
endcase
end
MRE2 #(1, `DRAMW) imf(.CLK(CLK), .RST(RST), .enq(im_enq), .deq(im_deq),
.din(d_dout), .dot(dot), .emp(im_emp), .full(im_full));
endmodule
/***** input buffer module *****/
/**************************************************************************************************/
module INBUF(input wire CLK,
input wire RST,
output wire ib_full, // this module is full
input wire full, // next moldule's full
output wire enq, // next module's enqueue
input wire [`MERGW-1:0] din, // data in
output wire [`MERGW-1:0] dot, // data out
input wire ib_enq, // this module's enqueue
input wire [`PHASE_W] phase, // current phase
input wire idone); // iteration done, this module's enqueue
function mux1;
input a;
input b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`MERGW-1:0] mux128;
input [`MERGW-1:0] a;
input [`MERGW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux128 = a;
1'b1: mux128 = b;
endcase
end
endfunction
/*****************************************/
wire [`MERGW-1:0] F_dout;
wire F_deq, F_emp;
reg [31:0] ecnt; // the number of elements in one iteration
reg ecntz; // ecnt==0 ?
wire f_full;
MRE2 #(1,`MERGW) F(.CLK(CLK), .RST(RST), .enq(ib_enq), .deq(F_deq), // input buffer FIFO
.din(din), .dot(F_dout), .emp(F_emp), .full(f_full));
assign ib_full = mux1(f_full, 0, F_deq); // INBUF back_pressure
/*****************************************/
assign enq = !full && (!F_emp || ecntz); // enqueue for the next buffer
assign F_deq = enq && (ecnt!=0); //
assign dot = mux128(F_dout, `MAX_VALUE, ecntz);
always @(posedge CLK) begin
if (RST || idone) begin
ecnt <= (`ELEMS_PER_UNIT << (phase * `WAY_LOG)); /// note
ecntz <= 0;
end else begin
if (ecnt!=0 && enq) ecnt <= ecnt - 4;
if (ecnt==4 && enq) ecntz <= 1; // old version has a bug here!
end
end
endmodule
/**************************************************************************************************/
module STREE(input wire CLK,
input wire RST_in,
input wire irst,
input wire frst,
input wire [`PHASE_W] phase_in,
input wire [`MERGW*`SORT_WAY-1:0] s_din, // sorting-tree input data
input wire [`SORT_WAY-1:0] enq, // enqueue
output wire [`SORT_WAY-1:0] full, // buffer is full ?
input wire deq, // dequeue
output wire [`MERGW-1:0] dot, // output data
output wire emp);
reg RST;
always @(posedge CLK) RST <= RST_in;
reg [`PHASE_W] phase;
always @(posedge CLK) phase <= phase_in;
wire [`MERGW-1:0] d00, d01, d02, d03, d04, d05, d06, d07;
assign {d00, d01, d02, d03, d04, d05, d06, d07} = s_din;
wire F01_enq, F01_deq, F01_emp, F01_full; wire [`MERGW-1:0] F01_din, F01_dot; wire [1:0] F01_cnt;
wire F02_enq, F02_deq, F02_emp, F02_full; wire [`MERGW-1:0] F02_din, F02_dot; wire [1:0] F02_cnt;
wire F03_enq, F03_deq, F03_emp, F03_full; wire [`MERGW-1:0] F03_din, F03_dot; wire [1:0] F03_cnt;
wire F04_enq, F04_deq, F04_emp, F04_full; wire [`MERGW-1:0] F04_din, F04_dot; wire [1:0] F04_cnt;
wire F05_enq, F05_deq, F05_emp, F05_full; wire [`MERGW-1:0] F05_din, F05_dot; wire [1:0] F05_cnt;
wire F06_enq, F06_deq, F06_emp, F06_full; wire [`MERGW-1:0] F06_din, F06_dot; wire [1:0] F06_cnt;
wire F07_enq, F07_deq, F07_emp, F07_full; wire [`MERGW-1:0] F07_din, F07_dot; wire [1:0] F07_cnt;
wire F08_enq, F08_deq, F08_emp, F08_full; wire [`MERGW-1:0] F08_din, F08_dot; wire [1:0] F08_cnt;
wire F09_enq, F09_deq, F09_emp, F09_full; wire [`MERGW-1:0] F09_din, F09_dot; wire [1:0] F09_cnt;
wire F10_enq, F10_deq, F10_emp, F10_full; wire [`MERGW-1:0] F10_din, F10_dot; wire [1:0] F10_cnt;
wire F11_enq, F11_deq, F11_emp, F11_full; wire [`MERGW-1:0] F11_din, F11_dot; wire [1:0] F11_cnt;
wire F12_enq, F12_deq, F12_emp, F12_full; wire [`MERGW-1:0] F12_din, F12_dot; wire [1:0] F12_cnt;
wire F13_enq, F13_deq, F13_emp, F13_full; wire [`MERGW-1:0] F13_din, F13_dot; wire [1:0] F13_cnt;
wire F14_enq, F14_deq, F14_emp, F14_full; wire [`MERGW-1:0] F14_din, F14_dot; wire [1:0] F14_cnt;
wire F15_enq, F15_deq, F15_emp, F15_full; wire [`MERGW-1:0] F15_din, F15_dot; wire [1:0] F15_cnt;
INBUF IN08(CLK, RST, full[0], F08_full, F08_enq, d00, F08_din, enq[0], phase, irst);
INBUF IN09(CLK, RST, full[1], F09_full, F09_enq, d01, F09_din, enq[1], phase, irst);
INBUF IN10(CLK, RST, full[2], F10_full, F10_enq, d02, F10_din, enq[2], phase, irst);
INBUF IN11(CLK, RST, full[3], F11_full, F11_enq, d03, F11_din, enq[3], phase, irst);
INBUF IN12(CLK, RST, full[4], F12_full, F12_enq, d04, F12_din, enq[4], phase, irst);
INBUF IN13(CLK, RST, full[5], F13_full, F13_enq, d05, F13_din, enq[5], phase, irst);
INBUF IN14(CLK, RST, full[6], F14_full, F14_enq, d06, F14_din, enq[6], phase, irst);
INBUF IN15(CLK, RST, full[7], F15_full, F15_enq, d07, F15_din, enq[7], phase, irst);
MRE2 #(1, `MERGW) F01(CLK, frst, F01_enq, F01_deq, F01_din, F01_dot, F01_emp, F01_full, F01_cnt);
MRE2 #(1, `MERGW) F02(CLK, frst, F02_enq, F02_deq, F02_din, F02_dot, F02_emp, F02_full, F02_cnt);
MRE2 #(1, `MERGW) F03(CLK, frst, F03_enq, F03_deq, F03_din, F03_dot, F03_emp, F03_full, F03_cnt);
MRE2 #(1, `MERGW) F04(CLK, frst, F04_enq, F04_deq, F04_din, F04_dot, F04_emp, F04_full, F04_cnt);
MRE2 #(1, `MERGW) F05(CLK, frst, F05_enq, F05_deq, F05_din, F05_dot, F05_emp, F05_full, F05_cnt);
MRE2 #(1, `MERGW) F06(CLK, frst, F06_enq, F06_deq, F06_din, F06_dot, F06_emp, F06_full, F06_cnt);
MRE2 #(1, `MERGW) F07(CLK, frst, F07_enq, F07_deq, F07_din, F07_dot, F07_emp, F07_full, F07_cnt);
MRE2 #(1, `MERGW) F08(CLK, frst, F08_enq, F08_deq, F08_din, F08_dot, F08_emp, F08_full, F08_cnt);
MRE2 #(1, `MERGW) F09(CLK, frst, F09_enq, F09_deq, F09_din, F09_dot, F09_emp, F09_full, F09_cnt);
MRE2 #(1, `MERGW) F10(CLK, frst, F10_enq, F10_deq, F10_din, F10_dot, F10_emp, F10_full, F10_cnt);
MRE2 #(1, `MERGW) F11(CLK, frst, F11_enq, F11_deq, F11_din, F11_dot, F11_emp, F11_full, F11_cnt);
MRE2 #(1, `MERGW) F12(CLK, frst, F12_enq, F12_deq, F12_din, F12_dot, F12_emp, F12_full, F12_cnt);
MRE2 #(1, `MERGW) F13(CLK, frst, F13_enq, F13_deq, F13_din, F13_dot, F13_emp, F13_full, F13_cnt);
MRE2 #(1, `MERGW) F14(CLK, frst, F14_enq, F14_deq, F14_din, F14_dot, F14_emp, F14_full, F14_cnt);
MRE2 #(1, `MERGW) F15(CLK, frst, F15_enq, F15_deq, F15_din, F15_dot, F15_emp, F15_full, F15_cnt);
SCELL #(`SORTW, `M_LOG) S01(CLK, frst, !F02_emp, !F03_emp, F02_deq, F03_deq, F02_dot, F03_dot, F01_full, F01_din, F01_enq);
SCELL #(`SORTW, `M_LOG) S02(CLK, frst, !F04_emp, !F05_emp, F04_deq, F05_deq, F04_dot, F05_dot, F02_full, F02_din, F02_enq);
SCELL #(`SORTW, `M_LOG) S03(CLK, frst, !F06_emp, !F07_emp, F06_deq, F07_deq, F06_dot, F07_dot, F03_full, F03_din, F03_enq);
SCELL #(`SORTW, `M_LOG) S04(CLK, frst, !F08_emp, !F09_emp, F08_deq, F09_deq, F08_dot, F09_dot, F04_full, F04_din, F04_enq);
SCELL #(`SORTW, `M_LOG) S05(CLK, frst, !F10_emp, !F11_emp, F10_deq, F11_deq, F10_dot, F11_dot, F05_full, F05_din, F05_enq);
SCELL #(`SORTW, `M_LOG) S06(CLK, frst, !F12_emp, !F13_emp, F12_deq, F13_deq, F12_dot, F13_dot, F06_full, F06_din, F06_enq);
SCELL #(`SORTW, `M_LOG) S07(CLK, frst, !F14_emp, !F15_emp, F14_deq, F15_deq, F14_dot, F15_dot, F07_full, F07_din, F07_enq);
assign F01_deq = deq;
assign dot = F01_dot;
assign emp = F01_emp;
endmodule
/***** Output Module *****/
/**************************************************************************************************/
module OTMOD(input wire CLK,
input wire RST,
input wire F01_deq,
input wire [`MERGW-1:0] F01_dot,
input wire OB_deq,
output wire [`DRAMW-1:0] OB_dot,
output wire OB_full,
output reg OB_req);
reg [1:0] ob_buf_t_cnt; // counter for temporary register
reg ob_enque;
reg [`DRAMW-1:0] ob_buf_t;
wire [`DRAMW-1:0] OB_din = ob_buf_t;
wire OB_enq = ob_enque;
wire [`OB_SIZE:0] OB_cnt;
always @(posedge CLK) OB_req <= (OB_cnt>=`DRAM_WBLOCKS);
always @(posedge CLK) begin
if (F01_deq) ob_buf_t <= {F01_dot, ob_buf_t[`DRAMW-1:`MERGW]};
end
always @(posedge CLK) begin
if (RST) begin
ob_buf_t_cnt <= 0;
end else begin
if (F01_deq) ob_buf_t_cnt <= ob_buf_t_cnt + 1;
end
end
always @(posedge CLK) ob_enque <= (F01_deq && ob_buf_t_cnt == 3);
BFIFO #(`OB_SIZE, `DRAMW) OB(.CLK(CLK), .RST(RST), .enq(OB_enq), .deq(OB_deq),
.din(OB_din), .dot(OB_dot), .full(OB_full), .cnt(OB_cnt));
endmodule
/***** Sorting Network *****/
/**************************************************************************************************/
module SORTINGNETWORK(input wire CLK,
input wire RST_IN,
input wire DATAEN_IN,
input wire [511:0] DIN_T,
output reg [511:0] DOUT,
output reg DATAEN_OUT);
reg RST;
reg [511:0] DIN;
reg DATAEN;
always @(posedge CLK) RST <= RST_IN;
always @(posedge CLK) DIN <= DIN_T;
always @(posedge CLK) DATAEN <= (RST) ? 0 : DATAEN_IN;
// Stage A
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00; // output
wire [`WW] a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00; // input
assign {a15,a14,a13,a12,a11,a10,a09,a08,a07,a06,a05,a04,a03,a02,a01,a00} = DIN;
COMPARATOR comp00(a00, a01, A00, A01);
COMPARATOR comp01(a02, a03, A02, A03);
COMPARATOR comp02(a04, a05, A04, A05);
COMPARATOR comp03(a06, a07, A06, A07);
COMPARATOR comp04(a08, a09, A08, A09);
COMPARATOR comp05(a10, a11, A10, A11);
COMPARATOR comp06(a12, a13, A12, A13);
COMPARATOR comp07(a14, a15, A14, A15);
reg [511:0] pdA; // pipeline regester A for data
reg pcA; // pipeline regester A for control
always @(posedge CLK) pdA <= {A15,A14,A13,A12,A11,A10,A09,A08,A07,A06,A05,A04,A03,A02,A01,A00};
always @(posedge CLK) pcA <= (RST) ? 0 : DATAEN;
// Stage B
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00; // output
wire [`WW] b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00; // input
assign {b15,b14,b13,b12,b11,b10,b09,b08,b07,b06,b05,b04,b03,b02,b01,b00} = pdA;
COMPARATOR comp10(b00, b02, B00, B02);
COMPARATOR comp11(b04, b06, B04, B06);
COMPARATOR comp12(b08, b10, B08, B10);
COMPARATOR comp13(b12, b14, B12, B14);
COMPARATOR comp14(b01, b03, B01, B03);
COMPARATOR comp15(b05, b07, B05, B07);
COMPARATOR comp16(b09, b11, B09, B11);
COMPARATOR comp17(b13, b15, B13, B15);
reg [511:0] pdB; // pipeline regester B for data
reg pcB; // pipeline regester B for control
always @(posedge CLK) pdB <= {B15,B14,B13,B12,B11,B10,B09,B08,B07,B06,B05,B04,B03,B02,B01,B00};
always @(posedge CLK) pcB <= (RST) ? 0 : pcA;
// Stage C
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00; // output
wire [`WW] c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00; // input
assign {c15,c14,c13,c12,c11,c10,c09,c08,c07,c06,c05,c04,c03,c02,c01,c00} = pdB;
assign {C00,C03,C04,C07,C08,C11,C12,C15} = {c00,c03,c04,c07,c08,c11,c12,c15};
COMPARATOR comp20(c01, c02, C01, C02);
COMPARATOR comp21(c05, c06, C05, C06);
COMPARATOR comp22(c09, c10, C09, C10);
COMPARATOR comp23(c13, c14, C13, C14);
reg [511:0] pdC; // pipeline regester C for data
reg pcC; // pipeline regester C for control
always @(posedge CLK) pdC <= {C15,C14,C13,C12,C11,C10,C09,C08,C07,C06,C05,C04,C03,C02,C01,C00};
always @(posedge CLK) pcC <= (RST) ? 0 : pcB;
// Stage D
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00; // output
wire [`WW] d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00; // input
assign {d15,d14,d13,d12,d11,d10,d09,d08,d07,d06,d05,d04,d03,d02,d01,d00} = pdC;
COMPARATOR comp30(d00, d04, D00, D04);
COMPARATOR comp31(d08, d12, D08, D12);
COMPARATOR comp32(d01, d05, D01, D05);
COMPARATOR comp33(d09, d13, D09, D13);
COMPARATOR comp34(d02, d06, D02, D06);
COMPARATOR comp35(d10, d14, D10, D14);
COMPARATOR comp36(d03, d07, D03, D07);
COMPARATOR comp37(d11, d15, D11, D15);
reg [511:0] pdD; // pipeline regester D for data
reg pcD; // pipeline regester D for control
always @(posedge CLK) pdD <= {D15,D14,D13,D12,D11,D10,D09,D08,D07,D06,D05,D04,D03,D02,D01,D00};
always @(posedge CLK) pcD <= (RST) ? 0 : pcC;
// Stage E
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00; // output
wire [`WW] e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00; // input
assign {e15,e14,e13,e12,e11,e10,e09,e08,e07,e06,e05,e04,e03,e02,e01,e00} = pdD;
assign {E00,E01,E06,E07,E08,E09,E14,E15} = {e00,e01,e06,e07,e08,e09,e14,e15};
COMPARATOR comp40(e02, e04, E02, E04);
COMPARATOR comp41(e10, e12, E10, E12);
COMPARATOR comp42(e03, e05, E03, E05);
COMPARATOR comp43(e11, e13, E11, E13);
reg [511:0] pdE; // pipeline regester E for data
reg pcE; // pipeline regester E for control
always @(posedge CLK) pdE <= {E15,E14,E13,E12,E11,E10,E09,E08,E07,E06,E05,E04,E03,E02,E01,E00};
always @(posedge CLK) pcE <= (RST) ? 0 : pcD;
// Stage F
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00; // output
wire [`WW] f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00; // input
assign {f15,f14,f13,f12,f11,f10,f09,f08,f07,f06,f05,f04,f03,f02,f01,f00} = pdE;
assign {F00,F07,F08,F15} = {f00,f07,f08,f15};
COMPARATOR comp50(f01, f02, F01, F02);
COMPARATOR comp51(f03, f04, F03, F04);
COMPARATOR comp52(f05, f06, F05, F06);
COMPARATOR comp53(f09, f10, F09, F10);
COMPARATOR comp54(f11, f12, F11, F12);
COMPARATOR comp55(f13, f14, F13, F14);
reg [511:0] pdF; // pipeline regester F for data
reg pcF; // pipeline regester F for control
always @(posedge CLK) pdF <= {F15,F14,F13,F12,F11,F10,F09,F08,F07,F06,F05,F04,F03,F02,F01,F00};
always @(posedge CLK) pcF <= (RST) ? 0 : pcE;
// Stage G
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00; // output
wire [`WW] g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00; // input
assign {g15,g14,g13,g12,g11,g10,g09,g08,g07,g06,g05,g04,g03,g02,g01,g00} = pdF;
COMPARATOR comp60(g00, g08, G00, G08);
COMPARATOR comp61(g01, g09, G01, G09);
COMPARATOR comp62(g02, g10, G02, G10);
COMPARATOR comp63(g03, g11, G03, G11);
COMPARATOR comp64(g04, g12, G04, G12);
COMPARATOR comp65(g05, g13, G05, G13);
COMPARATOR comp66(g06, g14, G06, G14);
COMPARATOR comp67(g07, g15, G07, G15);
reg [511:0] pdG; // pipeline regester G for data
reg pcG; // pipeline regester G for control
always @(posedge CLK) pdG <= {G15,G14,G13,G12,G11,G10,G09,G08,G07,G06,G05,G04,G03,G02,G01,G00};
always @(posedge CLK) pcG <= (RST) ? 0 : pcF;
// Stage H
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00; // output
wire [`WW] h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00; // input
assign {h15,h14,h13,h12,h11,h10,h09,h08,h07,h06,h05,h04,h03,h02,h01,h00} = pdG;
assign {H00,H01,H02,H03,H12,H13,H14,H15} = {h00,h01,h02,h03,h12,h13,h14,h15};
COMPARATOR comp70(h04, h08, H04, H08);
COMPARATOR comp71(h05, h09, H05, H09);
COMPARATOR comp72(h06, h10, H06, H10);
COMPARATOR comp73(h07, h11, H07, H11);
reg [511:0] pdH; // pipeline regester H for data
reg pcH; // pipeline regester H for control
always @(posedge CLK) pdH <= {H15,H14,H13,H12,H11,H10,H09,H08,H07,H06,H05,H04,H03,H02,H01,H00};
always @(posedge CLK) pcH <= (RST) ? 0 : pcG;
// Stage I
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00; // output
wire [`WW] i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00; // input
assign {i15,i14,i13,i12,i11,i10,i09,i08,i07,i06,i05,i04,i03,i02,i01,i00} = pdH;
assign {I00,I01,I14,I15} = {i00,i01,i14,i15};
COMPARATOR comp80(i02, i04, I02, I04);
COMPARATOR comp81(i06, i08, I06, I08);
COMPARATOR comp82(i10, i12, I10, I12);
COMPARATOR comp83(i03, i05, I03, I05);
COMPARATOR comp84(i07, i09, I07, I09);
COMPARATOR comp85(i11, i13, I11, I13);
reg [511:0] pdI; // pipeline regester I for data
reg pcI; // pipeline regester I for control
always @(posedge CLK) pdI <= {I15,I14,I13,I12,I11,I10,I09,I08,I07,I06,I05,I04,I03,I02,I01,I00};
always @(posedge CLK) pcI <= (RST) ? 0 : pcH;
// Stage J
////////////////////////////////////////////////////////////////////////////////////////////////
wire [`WW] J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00; // output
wire [`WW] j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00; // input
assign {j15,j14,j13,j12,j11,j10,j09,j08,j07,j06,j05,j04,j03,j02,j01,j00} = pdI;
assign {J00,J15} = {j00,j15};
COMPARATOR comp90(j01, j02, J01, J02);
COMPARATOR comp91(j03, j04, J03, J04);
COMPARATOR comp92(j05, j06, J05, J06);
COMPARATOR comp93(j07, j08, J07, J08);
COMPARATOR comp94(j09, j10, J09, J10);
COMPARATOR comp95(j11, j12, J11, J12);
COMPARATOR comp96(j13, j14, J13, J14);
always @(posedge CLK) DOUT <= {J15,J14,J13,J12,J11,J10,J09,J08,J07,J06,J05,J04,J03,J02,J01,J00};
always @(posedge CLK) DATAEN_OUT <= (RST) ? 0 : pcI;
endmodule
/**************************************************************************************************/
/***** An SRL-based FIFO *****/
/******************************************************************************/
module SRL_FIFO #(parameter FIFO_SIZE = 4, // size in log scale, 4 for 16 entry
parameter FIFO_WIDTH = 64) // fifo width in bit
(input wire CLK,
input wire RST,
input wire enq,
input wire deq,
input wire [FIFO_WIDTH-1:0] din,
output wire [FIFO_WIDTH-1:0] dot,
output wire emp,
output wire full,
output reg [FIFO_SIZE:0] cnt);
reg [FIFO_SIZE-1:0] head;
reg [FIFO_WIDTH-1:0] mem [(1<<FIFO_SIZE)-1:0];
assign emp = (cnt==0);
assign full = (cnt==(1<<FIFO_SIZE));
assign dot = mem[head];
always @(posedge CLK) begin
if (RST) begin
cnt <= 0;
head <= {(FIFO_SIZE){1'b1}};
end else begin
case ({enq, deq})
2'b01: begin cnt <= cnt - 1; head <= head - 1; end
2'b10: begin cnt <= cnt + 1; head <= head + 1; end
endcase
end
end
integer i;
always @(posedge CLK) begin
if (enq) begin
mem[0] <= din;
for (i=1; i<(1<<FIFO_SIZE); i=i+1) mem[i] <= mem[i-1];
end
end
endmodule
/***** Core User Logic *****/
/**************************************************************************************************/
module CORE(input wire CLK, // clock
input wire RST_IN, // reset
input wire d_busy, // DRAM busy
output wire [`DRAMW-1:0] d_din, // DRAM data in
input wire d_w, // DRAM write flag
input wire [`DRAMW-1:0] d_dout, // DRAM data out
input wire d_douten, // DRAM data out enable
output reg [1:0] d_req, // DRAM REQ access request (read/write)
output reg [31:0] d_initadr, // DRAM REQ initial address for the access
output reg [31:0] d_blocks, // DRAM REQ the number of blocks per one access
input wire [`DRAMW-1:0] rx_data,
input wire rx_data_valid,
output wire rx_wait,
input wire chnl_tx_data_ren,
input wire chnl_tx_data_valid,
output wire [`MERGW-1:0] rslt,
output wire rslt_ready);
function [1-1:0] mux1;
input [1-1:0] a;
input [1-1:0] b;
input sel;
begin
case (sel)
1'b0: mux1 = a;
1'b1: mux1 = b;
endcase
end
endfunction
function [`SORT_WAY-1:0] mux_sortway;
input [`SORT_WAY-1:0] a;
input [`SORT_WAY-1:0] b;
input sel;
begin
case (sel)
1'b0: mux_sortway = a;
1'b1: mux_sortway = b;
endcase
end
endfunction
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
function [512-1:0] mux512;
input [512-1:0] a;
input [512-1:0] b;
input sel;
begin
case (sel)
1'b0: mux512 = a;
1'b1: mux512 = b;
endcase
end
endfunction
/**********************************************************************************************/
wire [`DRAMW-1:0] OB_dot_a, OB_dot_b;
wire OB_req_a, OB_req_b;
wire OB_full_a, OB_full_b;
reg OB_granted_a, OB_granted_b;
wire OB_deq_a = d_w && OB_granted_a;
wire OB_deq_b = d_w && OB_granted_b;
assign d_din = mux512(OB_dot_b, OB_dot_a, OB_granted_a);
reg [`DRAMW-1:0] dout_ta;
reg [`DRAMW-1:0] dout_tb;
reg [`DRAMW-1:0] dout_tc;
reg [`DRAMW-1:0] dout_td;
reg [`DRAMW-1:0] dout_te;
reg [`DRAMW-1:0] dout_tf;
reg doen_ta;
reg doen_tb; //
reg doen_tc; //
reg doen_td; //
reg doen_te; //
reg doen_tf; //
reg [`SORT_WAY-1:0] req; // use n-bit for n-way sorting, data read request from ways
reg [`SORT_WAY-1:0] req_a, req_b;
reg [`SORT_WAY-1:0] req_ta;
reg [`SORT_WAY-1:0] req_tb;
reg [`SORT_WAY-1:0] req_taa; //
reg [`SORT_WAY-1:0] req_tab; //
reg [`SORT_WAY-1:0] req_tba; //
reg [`SORT_WAY-1:0] req_tbb; //
reg [`SRTP_WAY-1:0] req_pzero;
wire [`SORT_WAY-1:0] im_req_a;
wire [`SORT_WAY-1:0] im_req_b;
wire [`SRTP_WAY-1:0] rxw;
reg [31:0] elem_a, elem_b; // sorted elements in a phase
reg [`PHASE_W] phase_a, phase_b; //
reg pchange_a, pchange_b; // phase_change to reset some registers
reg iter_done_a, iter_done_b; //
reg [31:0] ecnt_a, ecnt_b; // sorted elements in an iteration
reg irst_a, irst_b; // INBUF reset
reg frst_a, frst_b; // sort-tree FIFO reset
reg plast_a, plast_b;
reg phase_zero;
reg last_phase;
reg RSTa, RSTb;
always @(posedge CLK) RSTa <= RST_IN;
always @(posedge CLK) RSTb <= RST_IN;
/**********************************************************************************************/
wire [`MERGW-1:0] d00_a, d01_a, d02_a, d03_a, d04_a, d05_a, d06_a, d07_a;
wire [1:0] ib00_req_a, ib01_req_a, ib02_req_a, ib03_req_a, ib04_req_a, ib05_req_a, ib06_req_a, ib07_req_a;
wire [`MERGW-1:0] d00_b, d01_b, d02_b, d03_b, d04_b, d05_b, d06_b, d07_b;
wire [1:0] ib00_req_b, ib01_req_b, ib02_req_b, ib03_req_b, ib04_req_b, ib05_req_b, ib06_req_b, ib07_req_b;
(* mark_debug = "true" *) wire rsltbuf_enq;
(* mark_debug = "true" *) wire rsltbuf_deq;
wire rsltbuf_emp;
wire rsltbuf_ful;
(* mark_debug = "true" *) wire [4:0] rsltbuf_cnt;
wire F01_emp_a, F01_emp_b;
wire F01_deq_a = mux1((~|{F01_emp_a,OB_full_a}), (~|{F01_emp_a,rsltbuf_ful}), last_phase);
wire F01_deq_b = (~|{F01_emp_b,OB_full_b});
wire [`MERGW-1:0] F01_dot_a, F01_dot_b;
wire [`MERGW*`SORT_WAY-1:0] s_din_a = {d00_a, d01_a, d02_a, d03_a, d04_a, d05_a, d06_a, d07_a};
wire [`MERGW*`SORT_WAY-1:0] s_din_b = {d00_b, d01_b, d02_b, d03_b, d04_b, d05_b, d06_b, d07_b};
wire [`SORT_WAY-1:0] enq_a, enq_b;
wire [`SORT_WAY-1:0] s_ful_a, s_ful_b;
wire [`DRAMW-1:0] stnet_dout;
wire stnet_douten;
SORTINGNETWORK sortingnetwork(CLK, RSTa, rx_data_valid, rx_data, stnet_dout, stnet_douten);
always @(posedge CLK) begin
if (RSTa) req_pzero <= 1;
else if (doen_tc) req_pzero <= {req_pzero[`SRTP_WAY-2:0],req_pzero[`SRTP_WAY-1]};
end
assign im_req_a = mux_sortway(req_tab, req_pzero[`SORT_WAY-1:0], phase_zero);
assign im_req_b = mux_sortway(req_tbb, req_pzero[`SRTP_WAY-1:`SORT_WAY], phase_zero);
INMOD2 im00_a(CLK, RSTa, dout_tc, doen_tc & im_req_a[0], s_ful_a[0], rxw[0], d00_a, enq_a[0], ib00_req_a);
INMOD2 im01_a(CLK, RSTa, dout_tc, doen_tc & im_req_a[1], s_ful_a[1], rxw[1], d01_a, enq_a[1], ib01_req_a);
INMOD2 im02_a(CLK, RSTa, dout_td, doen_td & im_req_a[2], s_ful_a[2], rxw[2], d02_a, enq_a[2], ib02_req_a);
INMOD2 im03_a(CLK, RSTa, dout_td, doen_td & im_req_a[3], s_ful_a[3], rxw[3], d03_a, enq_a[3], ib03_req_a);
INMOD2 im04_a(CLK, RSTa, dout_te, doen_te & im_req_a[4], s_ful_a[4], rxw[4], d04_a, enq_a[4], ib04_req_a);
INMOD2 im05_a(CLK, RSTa, dout_te, doen_te & im_req_a[5], s_ful_a[5], rxw[5], d05_a, enq_a[5], ib05_req_a);
INMOD2 im06_a(CLK, RSTa, dout_tf, doen_tf & im_req_a[6], s_ful_a[6], rxw[6], d06_a, enq_a[6], ib06_req_a);
INMOD2 im07_a(CLK, RSTa, dout_tf, doen_tf & im_req_a[7], s_ful_a[7], rxw[7], d07_a, enq_a[7], ib07_req_a);
INMOD2 im00_b(CLK, RSTb, dout_tc, doen_tc & im_req_b[0], s_ful_b[0], rxw[8], d00_b, enq_b[0], ib00_req_b);
INMOD2 im01_b(CLK, RSTb, dout_tc, doen_tc & im_req_b[1], s_ful_b[1], rxw[9], d01_b, enq_b[1], ib01_req_b);
INMOD2 im02_b(CLK, RSTb, dout_td, doen_td & im_req_b[2], s_ful_b[2], rxw[10], d02_b, enq_b[2], ib02_req_b);
INMOD2 im03_b(CLK, RSTb, dout_td, doen_td & im_req_b[3], s_ful_b[3], rxw[11], d03_b, enq_b[3], ib03_req_b);
INMOD2 im04_b(CLK, RSTb, dout_te, doen_te & im_req_b[4], s_ful_b[4], rxw[12], d04_b, enq_b[4], ib04_req_b);
INMOD2 im05_b(CLK, RSTb, dout_te, doen_te & im_req_b[5], s_ful_b[5], rxw[13], d05_b, enq_b[5], ib05_req_b);
INMOD2 im06_b(CLK, RSTb, dout_tf, doen_tf & im_req_b[6], s_ful_b[6], rxw[14], d06_b, enq_b[6], ib06_req_b);
INMOD2 im07_b(CLK, RSTb, dout_tf, doen_tf & im_req_b[7], s_ful_b[7], rxw[15], d07_b, enq_b[7], ib07_req_b);
assign rx_wait = |rxw;
STREE stree_a(CLK, RSTa, irst_a, frst_a, phase_a, s_din_a, enq_a, s_ful_a, F01_deq_a, F01_dot_a, F01_emp_a);
STREE stree_b(CLK, RSTb, irst_b, frst_b, phase_b, s_din_b, enq_b, s_ful_b, F01_deq_b, F01_dot_b, F01_emp_b);
OTMOD ob_a(CLK, RSTa, (!last_phase && F01_deq_a), F01_dot_a, OB_deq_a, OB_dot_a, OB_full_a, OB_req_a);
OTMOD ob_b(CLK, RSTb, F01_deq_b, F01_dot_b, OB_deq_b, OB_dot_b, OB_full_b, OB_req_b);
assign rsltbuf_enq = last_phase && F01_deq_a;
assign rsltbuf_deq = chnl_tx_data_ren && chnl_tx_data_valid;
SRL_FIFO #(4, `MERGW) rsltbuf(CLK, RSTa, rsltbuf_enq, rsltbuf_deq, F01_dot_a,
rslt, rsltbuf_emp, rsltbuf_ful, rsltbuf_cnt);
assign rslt_ready = !rsltbuf_emp;
/***** dram READ/WRITE controller *****/
/**********************************************************************************************/
reg [31:0] w_addr; //
reg [31:0] w_addr_pzero; //
reg [31:0] w_addr_a, w_addr_b;
reg [3:0] state; // state
reg [31:0] radr_a, radr_b, radr_c, radr_d, radr_e, radr_f, radr_g, radr_h;
reg [31:0] radr_a_a, radr_b_a, radr_c_a, radr_d_a, radr_e_a, radr_f_a, radr_g_a, radr_h_a;
reg [31:0] radr_a_b, radr_b_b, radr_c_b, radr_d_b, radr_e_b, radr_f_b, radr_g_b, radr_h_b;
reg [27:0] cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h;
reg [27:0] cnt_a_a, cnt_b_a, cnt_c_a, cnt_d_a, cnt_e_a, cnt_f_a, cnt_g_a, cnt_h_a;
reg [27:0] cnt_a_b, cnt_b_b, cnt_c_b, cnt_d_b, cnt_e_b, cnt_f_b, cnt_g_b, cnt_h_b;
reg c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h; // counter is full ?
reg c_a_a, c_b_a, c_c_a, c_d_a, c_e_a, c_f_a, c_g_a, c_h_a;
reg c_a_b, c_b_b, c_c_b, c_d_b, c_e_b, c_f_b, c_g_b, c_h_b;
always @(posedge CLK) begin
if (RSTa || pchange_a || pchange_b) begin
if (RSTa) state <= 0;
if (RSTa) {d_req, d_initadr, d_blocks} <= 0;
if (RSTa) w_addr_pzero <= (`SORT_ELM>>1);
req <= 0;
w_addr <= mux32((`SORT_ELM>>1), 0, phase_a[0]);
radr_a <= ((`SELM_PER_WAY>>3)*0);
radr_b <= ((`SELM_PER_WAY>>3)*1);
radr_c <= ((`SELM_PER_WAY>>3)*2);
radr_d <= ((`SELM_PER_WAY>>3)*3);
radr_e <= ((`SELM_PER_WAY>>3)*4);
radr_f <= ((`SELM_PER_WAY>>3)*5);
radr_g <= ((`SELM_PER_WAY>>3)*6);
radr_h <= ((`SELM_PER_WAY>>3)*7);
{cnt_a, cnt_b, cnt_c, cnt_d, cnt_e, cnt_f, cnt_g, cnt_h} <= 0;
{c_a, c_b, c_c, c_d, c_e, c_f, c_g, c_h} <= 0;
if ((RSTa || pchange_a) && !plast_a) begin
req_a <= 0;
w_addr_a <= mux32((`SORT_ELM>>1), 0, phase_a[0]);
radr_a_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*0);
radr_b_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*1);
radr_c_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*2);
radr_d_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*3);
radr_e_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*4);
radr_f_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*5);
radr_g_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*6);
radr_h_a <= ((`SELM_PER_WAY>>(`P_LOG+3))*7);
{cnt_a_a, cnt_b_a, cnt_c_a, cnt_d_a, cnt_e_a, cnt_f_a, cnt_g_a, cnt_h_a} <= 0;
{c_a_a, c_b_a, c_c_a, c_d_a, c_e_a, c_f_a, c_g_a, c_h_a} <= 0;
OB_granted_a <= 0;
end
if ((RSTa || pchange_b) && !plast_b) begin
req_b <= 0;
w_addr_b <= mux32(((`SORT_ELM>>2) | (`SORT_ELM>>1)), (`SORT_ELM>>2), phase_b[0]);
radr_a_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*0) | (`SORT_ELM>>2);
radr_b_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*1) | (`SORT_ELM>>2);
radr_c_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*2) | (`SORT_ELM>>2);
radr_d_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*3) | (`SORT_ELM>>2);
radr_e_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*4) | (`SORT_ELM>>2);
radr_f_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*5) | (`SORT_ELM>>2);
radr_g_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*6) | (`SORT_ELM>>2);
radr_h_b <= ((`SELM_PER_WAY>>(`P_LOG+3))*7) | (`SORT_ELM>>2);
{cnt_a_b, cnt_b_b, cnt_c_b, cnt_d_b, cnt_e_b, cnt_f_b, cnt_g_b, cnt_h_b} <= 0;
{c_a_b, c_b_b, c_c_b, c_d_b, c_e_b, c_f_b, c_g_b, c_h_b} <= 0;
OB_granted_b <= 0;
end
end else begin
case (state)
////////////////////////////////////////////////////////////////////////////////////////
0: begin ///// Initialize memory, write data to DRAM
if (!phase_zero) state <= 4;
if (d_req != 0) d_req <= 0;
else if (!d_busy) begin
if (OB_req_a || OB_req_b) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= `DRAM_WBLOCKS; //
d_initadr <= w_addr_pzero; //
w_addr_pzero <= w_addr_pzero + (`D_WS); // address for the next write
if (OB_req_a) begin OB_granted_a <= 1; OB_granted_b <= 0; end
else if (OB_req_b) begin OB_granted_a <= 0; OB_granted_b <= 1; end
end
end
end
/////////////////////////////////////////////////////////////////////////////////////
1: begin ///// request arbitration
if (!d_busy) begin
if (ib00_req_a[1] && !c_a) begin req<=8'h01; state<=3; end // first priority
else if (ib01_req_a[1] && !c_b) begin req<=8'h02; state<=3; end //
else if (ib02_req_a[1] && !c_c) begin req<=8'h04; state<=3; end //
else if (ib03_req_a[1] && !c_d) begin req<=8'h08; state<=3; end //
else if (ib04_req_a[1] && !c_e) begin req<=8'h10; state<=3; end //
else if (ib05_req_a[1] && !c_f) begin req<=8'h20; state<=3; end //
else if (ib06_req_a[1] && !c_g) begin req<=8'h40; state<=3; end //
else if (ib07_req_a[1] && !c_h) begin req<=8'h80; state<=3; end //
else state<=2;
end
end
/////////////////////////////////////////////////////////////////////////////////////
2: begin ///// request arbitration
if (!d_busy) begin
if (ib00_req_a[0] && !c_a) begin req<=8'h01; state<=3; end // second priority
else if (ib01_req_a[0] && !c_b) begin req<=8'h02; state<=3; end //
else if (ib02_req_a[0] && !c_c) begin req<=8'h04; state<=3; end //
else if (ib03_req_a[0] && !c_d) begin req<=8'h08; state<=3; end //
else if (ib04_req_a[0] && !c_e) begin req<=8'h10; state<=3; end //
else if (ib05_req_a[0] && !c_f) begin req<=8'h20; state<=3; end //
else if (ib06_req_a[0] && !c_g) begin req<=8'h40; state<=3; end //
else if (ib07_req_a[0] && !c_h) begin req<=8'h80; state<=3; end //
end
end
/////////////////////////////////////////////////////////////////////////////////////
3: begin ///// READ data from DRAM
if (d_req!=0) begin d_req<=0; state<=1; end
else if (!d_busy) begin
case (req)
8'h01: begin
d_initadr <= mux32(radr_a, (radr_a | (`SORT_ELM>>1)), phase_a[0]);
radr_a <= radr_a+(`D_RS);
cnt_a <= cnt_a+1;
c_a <= (cnt_a>=`WAY_CN_);
end
8'h02: begin
d_initadr <= mux32(radr_b, (radr_b | (`SORT_ELM>>1)), phase_a[0]);
radr_b <= radr_b+(`D_RS);
cnt_b <= cnt_b+1;
c_b <= (cnt_b>=`WAY_CN_);
end
8'h04: begin
d_initadr <= mux32(radr_c, (radr_c | (`SORT_ELM>>1)), phase_a[0]);
radr_c <= radr_c+(`D_RS);
cnt_c <= cnt_c+1;
c_c <= (cnt_c>=`WAY_CN_);
end
8'h08: begin
d_initadr <= mux32(radr_d, (radr_d | (`SORT_ELM>>1)), phase_a[0]);
radr_d <= radr_d+(`D_RS);
cnt_d <= cnt_d+1;
c_d <= (cnt_d>=`WAY_CN_);
end
8'h10: begin
d_initadr <= mux32(radr_e, (radr_e | (`SORT_ELM>>1)), phase_a[0]);
radr_e <= radr_e+(`D_RS);
cnt_e <= cnt_e+1;
c_e <= (cnt_e>=`WAY_CN_);
end
8'h20: begin
d_initadr <= mux32(radr_f, (radr_f | (`SORT_ELM>>1)), phase_a[0]);
radr_f <= radr_f+(`D_RS);
cnt_f <= cnt_f+1;
c_f <= (cnt_f>=`WAY_CN_);
end
8'h40: begin
d_initadr <= mux32(radr_g, (radr_g | (`SORT_ELM>>1)), phase_a[0]);
radr_g <= radr_g+(`D_RS);
cnt_g <= cnt_g+1;
c_g <= (cnt_g>=`WAY_CN_);
end
8'h80: begin
d_initadr <= mux32(radr_h, (radr_h | (`SORT_ELM>>1)), phase_a[0]);
radr_h <= radr_h+(`D_RS);
cnt_h <= cnt_h+1;
c_h <= (cnt_h>=`WAY_CN_);
end
endcase
d_req <= `DRAM_REQ_READ;
d_blocks <= `DRAM_RBLOCKS;
req_ta <= req;
req_tb <= 0;
end
end
////////////////////////////////////////////////////////////////////////////////////////
4: begin
if (!d_busy) begin
///////////////// can be parameterized
if (ib00_req_a[1] && !c_a_a) begin req_a<=8'h01; req_b<=0; state<=6; end // first priority
else if (ib01_req_a[1] && !c_b_a) begin req_a<=8'h02; req_b<=0; state<=6; end //
else if (ib02_req_a[1] && !c_c_a) begin req_a<=8'h04; req_b<=0; state<=6; end //
else if (ib03_req_a[1] && !c_d_a) begin req_a<=8'h08; req_b<=0; state<=6; end //
else if (ib04_req_a[1] && !c_e_a) begin req_a<=8'h10; req_b<=0; state<=6; end // first priority
else if (ib05_req_a[1] && !c_f_a) begin req_a<=8'h20; req_b<=0; state<=6; end //
else if (ib06_req_a[1] && !c_g_a) begin req_a<=8'h40; req_b<=0; state<=6; end //
else if (ib07_req_a[1] && !c_h_a) begin req_a<=8'h80; req_b<=0; state<=6; end //
else if (ib00_req_b[1] && !c_a_b) begin req_b<=8'h01; req_a<=0; state<=6; end // first priority
else if (ib01_req_b[1] && !c_b_b) begin req_b<=8'h02; req_a<=0; state<=6; end //
else if (ib02_req_b[1] && !c_c_b) begin req_b<=8'h04; req_a<=0; state<=6; end //
else if (ib03_req_b[1] && !c_d_b) begin req_b<=8'h08; req_a<=0; state<=6; end //
else if (ib04_req_b[1] && !c_e_b) begin req_b<=8'h10; req_a<=0; state<=6; end // first priority
else if (ib05_req_b[1] && !c_f_b) begin req_b<=8'h20; req_a<=0; state<=6; end //
else if (ib06_req_b[1] && !c_g_b) begin req_b<=8'h40; req_a<=0; state<=6; end //
else if (ib07_req_b[1] && !c_h_b) begin req_b<=8'h80; req_a<=0; state<=6; end //
else state<=5;
end
end
5: begin
if (!d_busy) begin
///////////////// can be parameterized
if (ib00_req_a[0] && !c_a_a) begin req_a<=8'h01; req_b<=0; state<=6; end // first priority
else if (ib01_req_a[0] && !c_b_a) begin req_a<=8'h02; req_b<=0; state<=6; end //
else if (ib02_req_a[0] && !c_c_a) begin req_a<=8'h04; req_b<=0; state<=6; end //
else if (ib03_req_a[0] && !c_d_a) begin req_a<=8'h08; req_b<=0; state<=6; end //
else if (ib04_req_a[0] && !c_e_a) begin req_a<=8'h10; req_b<=0; state<=6; end // first priority
else if (ib05_req_a[0] && !c_f_a) begin req_a<=8'h20; req_b<=0; state<=6; end //
else if (ib06_req_a[0] && !c_g_a) begin req_a<=8'h40; req_b<=0; state<=6; end //
else if (ib07_req_a[0] && !c_h_a) begin req_a<=8'h80; req_b<=0; state<=6; end //
else if (ib00_req_b[0] && !c_a_b) begin req_b<=8'h01; req_a<=0; state<=6; end // first priority
else if (ib01_req_b[0] && !c_b_b) begin req_b<=8'h02; req_a<=0; state<=6; end //
else if (ib02_req_b[0] && !c_c_b) begin req_b<=8'h04; req_a<=0; state<=6; end //
else if (ib03_req_b[0] && !c_d_b) begin req_b<=8'h08; req_a<=0; state<=6; end //
else if (ib04_req_b[0] && !c_e_b) begin req_b<=8'h10; req_a<=0; state<=6; end // first priority
else if (ib05_req_b[0] && !c_f_b) begin req_b<=8'h20; req_a<=0; state<=6; end //
else if (ib06_req_b[0] && !c_g_b) begin req_b<=8'h40; req_a<=0; state<=6; end //
else if (ib07_req_b[0] && !c_h_b) begin req_b<=8'h80; req_a<=0; state<=6; end //
else if (OB_req_a) begin OB_granted_a <= 1; OB_granted_b <= 0; state<=7; end
else if (OB_req_b) begin OB_granted_a <= 0; OB_granted_b <= 1; state<=8; end
else if (last_phase) state<=1;
end
end
////////////////////////////////////////////////////////////////////////////////////////
6: begin
if (d_req!=0) begin d_req<=0; state<=4; end
else if (!d_busy) begin
case ({req_b,req_a})
16'h0001: begin
d_initadr <= mux32(radr_a_a, (radr_a_a | (`SORT_ELM>>1)), phase_a[0]);
radr_a_a <= radr_a_a+(`D_RS);
cnt_a_a <= cnt_a_a+1;
c_a_a <= (cnt_a_a>=`WAYP_CN_);
end
16'h0002: begin
d_initadr <= mux32(radr_b_a, (radr_b_a | (`SORT_ELM>>1)), phase_a[0]);
radr_b_a <= radr_b_a+(`D_RS);
cnt_b_a <= cnt_b_a+1;
c_b_a <= (cnt_b_a>=`WAYP_CN_);
end
16'h0004: begin
d_initadr <= mux32(radr_c_a, (radr_c_a | (`SORT_ELM>>1)), phase_a[0]);
radr_c_a <= radr_c_a+(`D_RS);
cnt_c_a <= cnt_c_a+1;
c_c_a <= (cnt_c_a>=`WAYP_CN_);
end
16'h0008: begin
d_initadr <= mux32(radr_d_a, (radr_d_a | (`SORT_ELM>>1)), phase_a[0]);
radr_d_a <= radr_d_a+(`D_RS);
cnt_d_a <= cnt_d_a+1;
c_d_a <= (cnt_d_a>=`WAYP_CN_);
end
16'h0010: begin
d_initadr <= mux32(radr_e_a, (radr_e_a | (`SORT_ELM>>1)), phase_a[0]);
radr_e_a <= radr_e_a+(`D_RS);
cnt_e_a <= cnt_e_a+1;
c_e_a <= (cnt_e_a>=`WAYP_CN_);
end
16'h0020: begin
d_initadr <= mux32(radr_f_a, (radr_f_a | (`SORT_ELM>>1)), phase_a[0]);
radr_f_a <= radr_f_a+(`D_RS);
cnt_f_a <= cnt_f_a+1;
c_f_a <= (cnt_f_a>=`WAYP_CN_);
end
16'h0040: begin
d_initadr <= mux32(radr_g_a, (radr_g_a | (`SORT_ELM>>1)), phase_a[0]);
radr_g_a <= radr_g_a+(`D_RS);
cnt_g_a <= cnt_g_a+1;
c_g_a <= (cnt_g_a>=`WAYP_CN_);
end
16'h0080: begin
d_initadr <= mux32(radr_h_a, (radr_h_a | (`SORT_ELM>>1)), phase_a[0]);
radr_h_a <= radr_h_a+(`D_RS);
cnt_h_a <= cnt_h_a+1;
c_h_a <= (cnt_h_a>=`WAYP_CN_);
end
16'h0100: begin
d_initadr <= mux32(radr_a_b, (radr_a_b | (`SORT_ELM>>1)), phase_b[0]);
radr_a_b <= radr_a_b+(`D_RS);
cnt_a_b <= cnt_a_b+1;
c_a_b <= (cnt_a_b>=`WAYP_CN_);
end
16'h0200: begin
d_initadr <= mux32(radr_b_b, (radr_b_b | (`SORT_ELM>>1)), phase_b[0]);
radr_b_b <= radr_b_b+(`D_RS);
cnt_b_b <= cnt_b_b+1;
c_b_b <= (cnt_b_b>=`WAYP_CN_);
end
16'h0400: begin
d_initadr <= mux32(radr_c_b, (radr_c_b | (`SORT_ELM>>1)), phase_b[0]);
radr_c_b <= radr_c_b+(`D_RS);
cnt_c_b <= cnt_c_b+1;
c_c_b <= (cnt_c_b>=`WAYP_CN_);
end
16'h0800: begin
d_initadr <= mux32(radr_d_b, (radr_d_b | (`SORT_ELM>>1)), phase_b[0]);
radr_d_b <= radr_d_b+(`D_RS);
cnt_d_b <= cnt_d_b+1;
c_d_b <= (cnt_d_b>=`WAYP_CN_);
end
16'h1000: begin
d_initadr <= mux32(radr_e_b, (radr_e_b | (`SORT_ELM>>1)), phase_b[0]);
radr_e_b <= radr_e_b+(`D_RS);
cnt_e_b <= cnt_e_b+1;
c_e_b <= (cnt_e_b>=`WAYP_CN_);
end
16'h2000: begin
d_initadr <= mux32(radr_f_b, (radr_f_b | (`SORT_ELM>>1)), phase_b[0]);
radr_f_b <= radr_f_b+(`D_RS);
cnt_f_b <= cnt_f_b+1;
c_f_b <= (cnt_f_b>=`WAYP_CN_);
end
16'h4000: begin
d_initadr <= mux32(radr_g_b, (radr_g_b | (`SORT_ELM>>1)), phase_b[0]);
radr_g_b <= radr_g_b+(`D_RS);
cnt_g_b <= cnt_g_b+1;
c_g_b <= (cnt_g_b>=`WAYP_CN_);
end
16'h8000: begin
d_initadr <= mux32(radr_h_b, (radr_h_b | (`SORT_ELM>>1)), phase_b[0]);
radr_h_b <= radr_h_b+(`D_RS);
cnt_h_b <= cnt_h_b+1;
c_h_b <= (cnt_h_b>=`WAYP_CN_);
end
endcase
d_req <= `DRAM_REQ_READ;
d_blocks <= `DRAM_RBLOCKS;
req_ta <= req_a;
req_tb <= req_b;
end
end
7: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=4; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= `DRAM_WBLOCKS; //
d_initadr <= w_addr_a; //
w_addr_a <= w_addr_a + (`D_WS); // address for the next write
end
end
8: begin ///// WRITE data to DRAM
if (d_req!=0) begin d_req<=0; state<=4; end
else if (!d_busy) begin
d_req <= `DRAM_REQ_WRITE; //
d_blocks <= `DRAM_WBLOCKS; //
d_initadr <= w_addr_b; //
w_addr_b <= w_addr_b + (`D_WS); // address for the next write
end
end
////////////////////////////////////////////////////////////////////////////////////////
endcase
end
end
/**********************************************************************************************/
always @(posedge CLK) begin
// Stage 0
////////////////////////////////////
dout_ta <= mux512(d_dout, stnet_dout, phase_zero);
dout_tb <= mux512(d_dout, stnet_dout, phase_zero);
doen_ta <= mux1(d_douten, stnet_douten, phase_zero);
doen_tb <= mux1(d_douten, stnet_douten, phase_zero);
req_taa <= req_ta;
req_tba <= req_tb;
// Stage 1
////////////////////////////////////
dout_tc <= dout_ta;
dout_td <= dout_ta;
dout_te <= dout_tb;
dout_tf <= dout_tb;
doen_tc <= doen_ta;
doen_td <= doen_ta;
doen_te <= doen_tb;
doen_tf <= doen_tb;
req_tab <= req_taa;
req_tbb <= req_tba;
end
// for phase
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
phase_a <= 0;
end else begin
if (elem_a==`SRTP_ELM) phase_a <= phase_a+1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
phase_b <= 0;
end else begin
if (elem_b==`SRTP_ELM) phase_b <= phase_b+1;
end
end
// for plast
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
plast_a <= 0;
end else begin
if (phase_a==`LAST_PHASE-1) plast_a <= 1;
end
end
always @(posedge CLK) begin
if (RSTb) begin
plast_b <= 0;
end else begin
if (phase_b==`LAST_PHASE-1) plast_b <= 1;
end
end
// for elem
// ###########################################################################
always @(posedge CLK) begin
if (RSTa) begin
elem_a <= 0;
end else begin
case ({OB_deq_a, (elem_a==`SRTP_ELM)})
2'b01: elem_a <= 0;
2'b10: elem_a <= elem_a + 16;
endcase
end
end
always @(posedge CLK) begin
if (RSTb) begin
elem_b <= 0;
end else begin
case ({OB_deq_b, (elem_b==`SRTP_ELM)})
2'b01: elem_b <= 0;
2'b10: elem_b <= elem_b + 16;
endcase
end
end
// for iter_done
// ###########################################################################
always @(posedge CLK) iter_done_a <= (ecnt_a==8);
always @(posedge CLK) iter_done_b <= (ecnt_b==8);
// for pchange
// ###########################################################################
always @(posedge CLK) pchange_a <= (elem_a==`SRTP_ELM);
always @(posedge CLK) pchange_b <= (elem_b==`SRTP_ELM);
// for irst
// ###########################################################################
always @(posedge CLK) irst_a <= (ecnt_a==8) || pchange_a;
always @(posedge CLK) irst_b <= (ecnt_b==8) || pchange_b;
// for frst
// ###########################################################################
always @(posedge CLK) frst_a <= RSTa || (ecnt_a==8) || (elem_a==`SRTP_ELM);
always @(posedge CLK) frst_b <= RSTb || (ecnt_b==8) || (elem_b==`SRTP_ELM);
// for ecnt
// ###########################################################################
always @(posedge CLK) begin
if (RSTa || iter_done_a || pchange_a) begin
ecnt_a <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_a * `WAY_LOG));
end else begin
if (ecnt_a!=0 && F01_deq_a) ecnt_a <= ecnt_a - 4;
end
end
always @(posedge CLK) begin
if (RSTb || iter_done_b || pchange_b) begin
ecnt_b <= ((`ELEMS_PER_UNIT<<`WAY_LOG) << (phase_b * `WAY_LOG));
end else begin
if (ecnt_b!=0 && F01_deq_b) ecnt_b <= ecnt_b - 4;
end
end
// for phase zero
// ###########################################################################
always @(posedge CLK) phase_zero <= ((phase_a == 0) || (phase_b == 0));
// for last phase
// ###########################################################################
always @(posedge CLK) last_phase <= ((phase_a == `LAST_PHASE) && (phase_b == `LAST_PHASE));
// for debug
// ###########################################################################
// (* mark_debug = "true" *) reg [31:0] dcnt;
// always @(posedge CLK) begin
// if (RST) begin
// dcnt <= 0;
// end else begin
// case ({F01_deq, (dcnt==`SORT_ELM)})
// 2'b01: dcnt <= 0;
// 2'b10: dcnt <= dcnt + 4;
// endcase
// end
// end
endmodule // CORE
/**************************************************************************************************/
`default_nettype wire
|
//////////////////////////////////////////////////////////////////
// //
// Decompiler for Amber 2 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Decompiler for debugging core - not synthesizable //
// Shows instruction in Execute Stage at last clock of //
// the instruction //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
`include "a23_config_defines.v"
module a23_decompile
(
input i_clk,
input i_fetch_stall,
input [31:0] i_instruction,
input i_instruction_valid,
input i_instruction_undefined,
input i_instruction_execute,
input [2:0] i_interrupt, // non-zero value means interrupt triggered
input i_interrupt_state,
input [31:0] i_instruction_address,
input [1:0] i_pc_sel,
input i_pc_wen
);
`include "a23_localparams.v"
`ifdef A23_DECOMPILE
integer i;
wire [31:0] imm32;
wire [7:0] imm8;
wire [11:0] offset12;
wire [7:0] offset8;
wire [3:0] reg_n, reg_d, reg_m, reg_s;
wire [4:0] shift_imm;
wire [3:0] opcode;
wire [3:0] condition;
wire [3:0] type;
wire opcode_compare;
wire opcode_move;
wire no_shift;
wire shift_op_imm;
wire [1:0] mtrans_type;
wire s_bit;
reg [(5*8)-1:0] xINSTRUCTION_EXECUTE;
reg [(5*8)-1:0] xINSTRUCTION_EXECUTE_R = "--- ";
wire [(8*8)-1:0] TYPE_NAME;
reg [3:0] fchars;
reg [31:0] execute_address = 'd0;
reg [2:0] interrupt_d1;
reg [31:0] execute_instruction = 'd0;
reg execute_now = 'd0;
reg execute_valid = 'd0;
reg execute_undefined = 'd0;
// ========================================================
// Delay instruction to Execute stage
// ========================================================
always @( posedge i_clk )
if ( !i_fetch_stall && i_instruction_valid )
begin
execute_instruction <= i_instruction;
execute_address <= i_instruction_address;
execute_undefined <= i_instruction_undefined;
execute_now <= 1'd1;
end
else
execute_now <= 1'd0;
always @ ( posedge i_clk )
if ( !i_fetch_stall )
execute_valid <= i_instruction_valid;
// ========================================================
// Open File
// ========================================================
integer decompile_file;
initial
#1 decompile_file = $fopen(`A23_DECOMPILE_FILE, "w");
// ========================================================
// Fields within the instruction
// ========================================================
assign opcode = execute_instruction[24:21];
assign condition = execute_instruction[31:28];
assign s_bit = execute_instruction[20];
assign reg_n = execute_instruction[19:16];
assign reg_d = execute_instruction[15:12];
assign reg_m = execute_instruction[3:0];
assign reg_s = execute_instruction[11:8];
assign shift_imm = execute_instruction[11:7];
assign offset12 = execute_instruction[11:0];
assign offset8 = {execute_instruction[11:8], execute_instruction[3:0]};
assign imm8 = execute_instruction[7:0];
assign no_shift = execute_instruction[11:4] == 8'h0;
assign mtrans_type = execute_instruction[24:23];
assign opcode_compare =
opcode == CMP ||
opcode == CMN ||
opcode == TEQ ||
opcode == TST ;
assign opcode_move =
opcode == MOV ||
opcode == MVN ;
assign shift_op_imm = type == REGOP && execute_instruction[25] == 1'd1;
assign imm32 = execute_instruction[11:8] == 4'h0 ? { 24'h0, imm8[7:0] } :
execute_instruction[11:8] == 4'h1 ? { imm8[1:0], 24'h0, imm8[7:2] } :
execute_instruction[11:8] == 4'h2 ? { imm8[3:0], 24'h0, imm8[7:4] } :
execute_instruction[11:8] == 4'h3 ? { imm8[5:0], 24'h0, imm8[7:6] } :
execute_instruction[11:8] == 4'h4 ? { imm8[7:0], 24'h0 } :
execute_instruction[11:8] == 4'h5 ? { 2'h0, imm8[7:0], 22'h0 } :
execute_instruction[11:8] == 4'h6 ? { 4'h0, imm8[7:0], 20'h0 } :
execute_instruction[11:8] == 4'h7 ? { 6'h0, imm8[7:0], 18'h0 } :
execute_instruction[11:8] == 4'h8 ? { 8'h0, imm8[7:0], 16'h0 } :
execute_instruction[11:8] == 4'h9 ? { 10'h0, imm8[7:0], 14'h0 } :
execute_instruction[11:8] == 4'ha ? { 12'h0, imm8[7:0], 12'h0 } :
execute_instruction[11:8] == 4'hb ? { 14'h0, imm8[7:0], 10'h0 } :
execute_instruction[11:8] == 4'hc ? { 16'h0, imm8[7:0], 8'h0 } :
execute_instruction[11:8] == 4'hd ? { 18'h0, imm8[7:0], 6'h0 } :
execute_instruction[11:8] == 4'he ? { 20'h0, imm8[7:0], 4'h0 } :
{ 22'h0, imm8[7:0], 2'h0 } ;
// ========================================================
// Instruction decode
// ========================================================
// the order of these matters
assign type =
{execute_instruction[27:23], execute_instruction[21:20], execute_instruction[11:4] } == { 5'b00010, 2'b00, 8'b00001001 } ? SWAP : // Before REGOP
{execute_instruction[27:22], execute_instruction[7:4] } == { 6'b000000, 4'b1001 } ? MULT : // Before REGOP
{execute_instruction[27:26] } == { 2'b00 } ? REGOP :
{execute_instruction[27:26] } == { 2'b01 } ? TRANS :
{execute_instruction[27:25] } == { 3'b100 } ? MTRANS :
{execute_instruction[27:25] } == { 3'b101 } ? BRANCH :
{execute_instruction[27:25] } == { 3'b110 } ? CODTRANS :
{execute_instruction[27:24], execute_instruction[4] } == { 4'b1110, 1'b0 } ? COREGOP :
{execute_instruction[27:24], execute_instruction[4] } == { 4'b1110, 1'b1 } ? CORTRANS :
SWI ;
//
// Convert some important signals to ASCII
// so their values can easily be displayed on a waveform viewer
//
assign TYPE_NAME = type == REGOP ? "REGOP " :
type == MULT ? "MULT " :
type == SWAP ? "SWAP " :
type == TRANS ? "TRANS " :
type == MTRANS ? "MTRANS " :
type == BRANCH ? "BRANCH " :
type == CODTRANS ? "CODTRANS" :
type == COREGOP ? "COREGOP " :
type == CORTRANS ? "CORTRANS" :
type == SWI ? "SWI " :
"UNKNOWN " ;
always @*
begin
if ( !execute_now )
begin
xINSTRUCTION_EXECUTE = xINSTRUCTION_EXECUTE_R;
end // stalled
else if ( type == REGOP && opcode == ADC ) xINSTRUCTION_EXECUTE = "adc ";
else if ( type == REGOP && opcode == ADD ) xINSTRUCTION_EXECUTE = "add ";
else if ( type == REGOP && opcode == AND ) xINSTRUCTION_EXECUTE = "and ";
else if ( type == BRANCH && execute_instruction[24] == 1'b0 ) xINSTRUCTION_EXECUTE = "b ";
else if ( type == REGOP && opcode == BIC ) xINSTRUCTION_EXECUTE = "bic ";
else if ( type == BRANCH && execute_instruction[24] == 1'b1 ) xINSTRUCTION_EXECUTE = "bl ";
else if ( type == COREGOP ) xINSTRUCTION_EXECUTE = "cdp ";
else if ( type == REGOP && opcode == CMN ) xINSTRUCTION_EXECUTE = "cmn ";
else if ( type == REGOP && opcode == CMP ) xINSTRUCTION_EXECUTE = "cmp ";
else if ( type == REGOP && opcode == EOR ) xINSTRUCTION_EXECUTE = "eor ";
else if ( type == CODTRANS && execute_instruction[20] == 1'b1 ) xINSTRUCTION_EXECUTE = "ldc ";
else if ( type == MTRANS && execute_instruction[20] == 1'b1 ) xINSTRUCTION_EXECUTE = "ldm ";
else if ( type == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b0, 1'b1} ) xINSTRUCTION_EXECUTE = "ldr ";
else if ( type == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b1, 1'b1} ) xINSTRUCTION_EXECUTE = "ldrb ";
else if ( type == CORTRANS && execute_instruction[20] == 1'b0 ) xINSTRUCTION_EXECUTE = "mcr ";
else if ( type == MULT && execute_instruction[21] == 1'b1 ) xINSTRUCTION_EXECUTE = "mla ";
else if ( type == REGOP && opcode == MOV ) xINSTRUCTION_EXECUTE = "mov ";
else if ( type == CORTRANS && execute_instruction[20] == 1'b1 ) xINSTRUCTION_EXECUTE = "mrc ";
else if ( type == MULT && execute_instruction[21] == 1'b0 ) xINSTRUCTION_EXECUTE = "mul ";
else if ( type == REGOP && opcode == MVN ) xINSTRUCTION_EXECUTE = "mvn ";
else if ( type == REGOP && opcode == ORR ) xINSTRUCTION_EXECUTE = "orr ";
else if ( type == REGOP && opcode == RSB ) xINSTRUCTION_EXECUTE = "rsb ";
else if ( type == REGOP && opcode == RSC ) xINSTRUCTION_EXECUTE = "rsc ";
else if ( type == REGOP && opcode == SBC ) xINSTRUCTION_EXECUTE = "sbc ";
else if ( type == CODTRANS && execute_instruction[20] == 1'b0 ) xINSTRUCTION_EXECUTE = "stc ";
else if ( type == MTRANS && execute_instruction[20] == 1'b0 ) xINSTRUCTION_EXECUTE = "stm ";
else if ( type == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b0, 1'b0} ) xINSTRUCTION_EXECUTE = "str ";
else if ( type == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b1, 1'b0} ) xINSTRUCTION_EXECUTE = "strb ";
else if ( type == REGOP && opcode == SUB ) xINSTRUCTION_EXECUTE = "sub ";
else if ( type == SWI ) xINSTRUCTION_EXECUTE = "swi ";
else if ( type == SWAP && execute_instruction[22] == 1'b0 ) xINSTRUCTION_EXECUTE = "swp ";
else if ( type == SWAP && execute_instruction[22] == 1'b1 ) xINSTRUCTION_EXECUTE = "swpb ";
else if ( type == REGOP && opcode == TEQ ) xINSTRUCTION_EXECUTE = "teq ";
else if ( type == REGOP && opcode == TST ) xINSTRUCTION_EXECUTE = "tst ";
else xINSTRUCTION_EXECUTE = "unkow";
end
always @ ( posedge i_clk )
xINSTRUCTION_EXECUTE_R <= xINSTRUCTION_EXECUTE;
always @( posedge i_clk )
if ( execute_now )
begin
// Interrupts override instructions that are just starting
if ( interrupt_d1 == 3'd0 || interrupt_d1 == 3'd7 )
begin
$fwrite(decompile_file,"%09d ", `U_TB.clk_count);
// Right justify the address
if ( execute_address < 32'h10) $fwrite(decompile_file," %01x: ", {execute_address[ 3:1], 1'd0});
else if ( execute_address < 32'h100) $fwrite(decompile_file," %02x: ", {execute_address[ 7:1], 1'd0});
else if ( execute_address < 32'h1000) $fwrite(decompile_file," %03x: ", {execute_address[11:1], 1'd0});
else if ( execute_address < 32'h10000) $fwrite(decompile_file," %04x: ", {execute_address[15:1], 1'd0});
else if ( execute_address < 32'h100000) $fwrite(decompile_file," %05x: ", {execute_address[19:1], 1'd0});
else if ( execute_address < 32'h1000000) $fwrite(decompile_file," %06x: ", {execute_address[23:1], 1'd0});
else if ( execute_address < 32'h10000000) $fwrite(decompile_file," %07x: ", {execute_address[27:1], 1'd0});
else $fwrite(decompile_file,"%8x: ", {execute_address[31:1], 1'd0});
// Mark that the instruction is not being executed
// condition field in execute stage allows instruction to execute ?
if (!i_instruction_execute)
begin
$fwrite(decompile_file,"-");
if ( type == SWI )
$display ("Cycle %09d SWI not taken *************", `U_TB.clk_count);
end
else
$fwrite(decompile_file," ");
// ========================================
// print the instruction name
// ========================================
case (numchars( xINSTRUCTION_EXECUTE ))
4'd1: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:32] );
4'd2: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:24] );
4'd3: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:16] );
4'd4: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39: 8] );
default: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39: 0] );
endcase
fchars = 8 - numchars(xINSTRUCTION_EXECUTE);
// Print the Multiple transfer type
if (type == MTRANS )
begin
w_mtrans_type;
fchars = fchars - 2;
end
// Print the s bit
if ( ((type == REGOP && !opcode_compare) || type == MULT ) && s_bit == 1'b1 )
begin
$fwrite(decompile_file,"s");
fchars = fchars - 1;
end
// Print the p bit
if ( type == REGOP && opcode_compare && s_bit == 1'b1 && reg_d == 4'd15 )
begin
$fwrite(decompile_file,"p");
fchars = fchars - 1;
end
// Print the condition code
if ( condition != AL )
begin
wcond;
fchars = fchars - 2;
end
// Align spaces after instruction
case ( fchars )
4'd0: $fwrite(decompile_file,"");
4'd1: $fwrite(decompile_file," ");
4'd2: $fwrite(decompile_file," ");
4'd3: $fwrite(decompile_file," ");
4'd4: $fwrite(decompile_file," ");
4'd5: $fwrite(decompile_file," ");
4'd6: $fwrite(decompile_file," ");
4'd7: $fwrite(decompile_file," ");
4'd8: $fwrite(decompile_file," ");
default: $fwrite(decompile_file," ");
endcase
// ========================================
// print the arguments for the instruction
// ========================================
case ( type )
REGOP: regop_args;
TRANS: trans_args;
MTRANS: mtrans_args;
BRANCH: branch_args;
MULT: mult_args;
SWAP: swap_args;
CODTRANS: codtrans_args;
COREGOP: begin
// `TB_ERROR_MESSAGE
$write("Coregop not implemented in decompiler yet\n");
end
CORTRANS: cortrans_args;
SWI: $fwrite(decompile_file,"#0x%06h", execute_instruction[23:0]);
default: begin
`TB_ERROR_MESSAGE
$write("Unknown Instruction Type ERROR\n");
end
endcase
$fwrite( decompile_file,"\n" );
end
// Undefined Instruction Interrupts
if ( i_instruction_execute && execute_undefined )
begin
$fwrite( decompile_file,"%09d interrupt undefined instruction", `U_TB.clk_count );
$fwrite( decompile_file,", return addr " );
$fwrite( decompile_file,"%08x\n", pcf(get_reg_val(5'd21)-4'd4) );
end
// Software Interrupt
if ( i_instruction_execute && type == SWI )
begin
$fwrite( decompile_file,"%09d interrupt swi", `U_TB.clk_count );
$fwrite( decompile_file,", return addr " );
$fwrite( decompile_file,"%08x\n", pcf(get_reg_val(5'd21)-4'd4) );
end
end
always @( posedge i_clk )
if ( !i_fetch_stall )
begin
interrupt_d1 <= i_interrupt;
// Asynchronous Interrupts
if ( interrupt_d1 != 3'd0 && i_interrupt_state )
begin
$fwrite( decompile_file,"%09d interrupt ", `U_TB.clk_count );
case ( interrupt_d1 )
3'd1: $fwrite( decompile_file,"data abort" );
3'd2: $fwrite( decompile_file,"firq" );
3'd3: $fwrite( decompile_file,"irq" );
3'd4: $fwrite( decompile_file,"address exception" );
3'd5: $fwrite( decompile_file,"instruction abort" );
default: $fwrite( decompile_file,"unknown type" );
endcase
$fwrite( decompile_file,", return addr " );
case ( interrupt_d1 )
3'd1: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd16)));
3'd2: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd17)));
3'd3: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd18)));
3'd4: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd19)));
3'd5: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd19)));
3'd7: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd20)));
default: ;
endcase
end
end
// jump
// Dont print a jump message for interrupts
always @( posedge i_clk )
if (
i_pc_sel != 2'd0 &&
i_pc_wen &&
!i_fetch_stall &&
i_instruction_execute &&
i_interrupt == 3'd0 &&
!execute_undefined &&
type != SWI &&
execute_address != get_32bit_signal(0) // Don't print jump to same address
)
begin
$fwrite(decompile_file,"%09d jump from ", `U_TB.clk_count);
fwrite_hex_drop_zeros(decompile_file, pcf(execute_address));
$fwrite(decompile_file," to ");
fwrite_hex_drop_zeros(decompile_file, pcf(get_32bit_signal(0)) ); // u_execute.pc_nxt
$fwrite(decompile_file,", r0 %08h, ", get_reg_val ( 5'd0 ));
$fwrite(decompile_file,"r1 %08h\n", get_reg_val ( 5'd1 ));
end
// =================================================================================
// Memory Writes - Peek into fetch module
// =================================================================================
reg [31:0] tmp_address;
// Data access
always @( posedge i_clk )
// Data Write
if ( get_1bit_signal(0) && !get_1bit_signal(1) )
begin
$fwrite(decompile_file, "%09d write addr ", `U_TB.clk_count);
tmp_address = get_32bit_signal(2);
fwrite_hex_drop_zeros(decompile_file, {tmp_address [31:2], 2'd0} );
$fwrite(decompile_file, ", data %08h, be %h",
get_32bit_signal(3), // u_cache.i_write_data
get_4bit_signal (0)); // u_cache.i_byte_enable
if ( get_1bit_signal(2) ) // Abort! address translation failed
$fwrite(decompile_file, " aborted!\n");
else
$fwrite(decompile_file, "\n");
end
// Data Read
else if (get_1bit_signal(3) && !get_1bit_signal(0) && !get_1bit_signal(1))
begin
$fwrite(decompile_file, "%09d read addr ", `U_TB.clk_count);
tmp_address = get_32bit_signal(2);
fwrite_hex_drop_zeros(decompile_file, {tmp_address[31:2], 2'd0} );
$fwrite(decompile_file, ", data %08h", get_32bit_signal(4)); // u_decode.i_read_data
if ( get_1bit_signal(2) ) // Abort! address translation failed
$fwrite(decompile_file, " aborted!\n");
else
$fwrite(decompile_file, "\n");
end
// =================================================================================
// Tasks
// =================================================================================
// Write Condition field
task wcond;
begin
case( condition)
4'h0: $fwrite(decompile_file,"eq");
4'h1: $fwrite(decompile_file,"ne");
4'h2: $fwrite(decompile_file,"cs");
4'h3: $fwrite(decompile_file,"cc");
4'h4: $fwrite(decompile_file,"mi");
4'h5: $fwrite(decompile_file,"pl");
4'h6: $fwrite(decompile_file,"vs");
4'h7: $fwrite(decompile_file,"vc");
4'h8: $fwrite(decompile_file,"hi");
4'h9: $fwrite(decompile_file,"ls");
4'ha: $fwrite(decompile_file,"ge");
4'hb: $fwrite(decompile_file,"lt");
4'hc: $fwrite(decompile_file,"gt");
4'hd: $fwrite(decompile_file,"le");
4'he: $fwrite(decompile_file," "); // Always
default: $fwrite(decompile_file,"nv"); // Never
endcase
end
endtask
// ldm and stm types
task w_mtrans_type;
begin
case( mtrans_type )
4'h0: $fwrite(decompile_file,"da");
4'h1: $fwrite(decompile_file,"ia");
4'h2: $fwrite(decompile_file,"db");
4'h3: $fwrite(decompile_file,"ib");
default: $fwrite(decompile_file,"xx");
endcase
end
endtask
// e.g. mrc 15, 0, r9, cr0, cr0, {0}
task cortrans_args;
begin
// Co-Processor Number
$fwrite(decompile_file,"%1d, ", execute_instruction[11:8]);
// opcode1
$fwrite(decompile_file,"%1d, ", execute_instruction[23:21]);
// Rd [15:12]
warmreg(reg_d);
// CRn [19:16]
$fwrite(decompile_file,", cr%1d", execute_instruction[19:16]);
// CRm [3:0]
$fwrite(decompile_file,", cr%1d", execute_instruction[3:0]);
// Opcode2 [7:5]
$fwrite(decompile_file,", {%1d}", execute_instruction[7:5]);
end
endtask
// ldc 15, 0, r9, cr0, cr0, {0}
task codtrans_args;
begin
// Co-Processor Number
$fwrite(decompile_file,"%1d, ", execute_instruction[11:8]);
// CRd [15:12]
$fwrite(decompile_file,"cr%1d, ", execute_instruction[15:12]);
// Rd [19:16]
warmreg(reg_n);
end
endtask
task branch_args;
reg [31:0] shift_amount;
begin
if (execute_instruction[23]) // negative
shift_amount = {~execute_instruction[23:0] + 24'd1, 2'd0};
else
shift_amount = {execute_instruction[23:0], 2'd0};
if (execute_instruction[23]) // negative
fwrite_hex_drop_zeros ( decompile_file, get_reg_val( 5'd21 ) - shift_amount );
else
fwrite_hex_drop_zeros ( decompile_file, get_reg_val( 5'd21 ) + shift_amount );
end
endtask
task mult_args;
begin
warmreg(reg_n); // Rd is in the Rn position for MULT instructions
$fwrite(decompile_file,", ");
warmreg(reg_m);
$fwrite(decompile_file,", ");
warmreg(reg_s);
if (execute_instruction[21]) // MLA
begin
$fwrite(decompile_file,", ");
warmreg(reg_d);
end
end
endtask
task swap_args;
begin
warmreg(reg_d);
$fwrite(decompile_file,", ");
warmreg(reg_m);
$fwrite(decompile_file,", [");
warmreg(reg_n);
$fwrite(decompile_file,"]");
end
endtask
task regop_args;
begin
if (!opcode_compare)
warmreg(reg_d);
if (!opcode_move )
begin
if (!opcode_compare)
begin
$fwrite(decompile_file,", ");
if (reg_d < 4'd10 || reg_d > 4'd12)
$fwrite(decompile_file," ");
end
warmreg(reg_n);
$fwrite(decompile_file,", ");
if (reg_n < 4'd10 || reg_n > 4'd12)
$fwrite(decompile_file," ");
end
else
begin
$fwrite(decompile_file,", ");
if (reg_d < 4'd10 || reg_d > 4'd12)
$fwrite(decompile_file," ");
end
if (shift_op_imm)
begin
if (|imm32[31:15])
$fwrite(decompile_file,"#0x%08h", imm32);
else
$fwrite(decompile_file,"#%1d", imm32);
end
else // Rm
begin
warmreg(reg_m);
if (execute_instruction[4])
// Register Shifts
wshiftreg;
else
// Immediate shifts
wshift;
end
end
endtask
task trans_args;
begin
warmreg(reg_d); // Destination register
casez ({execute_instruction[25:23], execute_instruction[21], no_shift, offset12==12'd0})
6'b0100?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #-%1d]" , offset12); end
6'b0110?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #%1d]" , offset12); end
6'b0100?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0110?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0101?? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #-%1d]!", offset12); end
6'b0111?? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #%1d]!" , offset12); end
6'b0000?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #-%1d", offset12); end
6'b0010?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #%1d" , offset12); end
6'b0001?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #-%1d", offset12); end
6'b0011?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #%1d" , offset12); end
6'b0000?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0010?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0001?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0011?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b11001? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); $fwrite(decompile_file,"]"); end
6'b11101? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); $fwrite(decompile_file,"]"); end
6'b11011? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); $fwrite(decompile_file,"]!"); end
6'b11111? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); $fwrite(decompile_file,"]!"); end
6'b10001? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); end
6'b10101? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); end
6'b10011? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); end
6'b10111? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); end
6'b11000? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); wshift; $fwrite(decompile_file,"]"); end
6'b11100? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); wshift; $fwrite(decompile_file,"]"); end
6'b11010? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); wshift; $fwrite(decompile_file,"]!");end
6'b11110? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); wshift; $fwrite(decompile_file,"]!");end
6'b10000? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); wshift; end
6'b10100? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); wshift; end
6'b10010? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); wshift; end
6'b10110? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); wshift; end
endcase
end
endtask
task mtrans_args;
begin
warmreg(reg_n);
if (execute_instruction[21]) $fwrite(decompile_file,"!");
$fwrite(decompile_file,", {");
for (i=0;i<16;i=i+1)
if (execute_instruction[i])
begin
warmreg(i);
if (more_to_come(execute_instruction[15:0], i))
$fwrite(decompile_file,", ");
end
$fwrite(decompile_file,"}");
// SDM: store the user mode registers, when in priviledged mode
if (execute_instruction[22:20] == 3'b100)
$fwrite(decompile_file,"^");
end
endtask
task wshift;
begin
// Check that its a valid shift operation. LSL by #0 is the null operator
if (execute_instruction[6:5] != LSL || shift_imm != 5'd0)
begin
case(execute_instruction[6:5])
2'd0: $fwrite(decompile_file,", lsl");
2'd1: $fwrite(decompile_file,", lsr");
2'd2: $fwrite(decompile_file,", asr");
2'd3: if (shift_imm == 5'd0) $fwrite(decompile_file,", rrx"); else $fwrite(decompile_file,", ror");
endcase
if (execute_instruction[6:5] != 2'd3 || shift_imm != 5'd0)
$fwrite(decompile_file," #%1d", shift_imm);
end
end
endtask
task wshiftreg;
begin
case(execute_instruction[6:5])
2'd0: $fwrite(decompile_file,", lsl ");
2'd1: $fwrite(decompile_file,", lsr ");
2'd2: $fwrite(decompile_file,", asr ");
2'd3: $fwrite(decompile_file,", ror ");
endcase
warmreg(reg_s);
end
endtask
task warmreg;
input [3:0] regnum;
begin
if (regnum < 4'd12)
$fwrite(decompile_file,"r%1d", regnum);
else
case (regnum)
4'd12 : $fwrite(decompile_file,"ip");
4'd13 : $fwrite(decompile_file,"sp");
4'd14 : $fwrite(decompile_file,"lr");
4'd15 : $fwrite(decompile_file,"pc");
endcase
end
endtask
task fwrite_hex_drop_zeros;
input [31:0] file;
input [31:0] num;
begin
if (num[31:28] != 4'd0)
$fwrite(file, "%x", num);
else if (num[27:24] != 4'd0)
$fwrite(file, "%x", num[27:0]);
else if (num[23:20] != 4'd0)
$fwrite(file, "%x", num[23:0]);
else if (num[19:16] != 4'd0)
$fwrite(file, "%x", num[19:0]);
else if (num[15:12] != 4'd0)
$fwrite(file, "%x", num[15:0]);
else if (num[11:8] != 4'd0)
$fwrite(file, "%x", num[11:0]);
else if (num[7:4] != 4'd0)
$fwrite(file, "%x", num[7:0]);
else
$fwrite(file, "%x", num[3:0]);
end
endtask
// =================================================================================
// Functions
// =================================================================================
// Get current value of register
function [31:0] get_reg_val;
input [4:0] regnum;
begin
case (regnum)
5'd0 : get_reg_val = `U_REGISTER_BANK.r0_out;
5'd1 : get_reg_val = `U_REGISTER_BANK.r1_out;
5'd2 : get_reg_val = `U_REGISTER_BANK.r2_out;
5'd3 : get_reg_val = `U_REGISTER_BANK.r3_out;
5'd4 : get_reg_val = `U_REGISTER_BANK.r4_out;
5'd5 : get_reg_val = `U_REGISTER_BANK.r5_out;
5'd6 : get_reg_val = `U_REGISTER_BANK.r6_out;
5'd7 : get_reg_val = `U_REGISTER_BANK.r7_out;
5'd8 : get_reg_val = `U_REGISTER_BANK.r8_out;
5'd9 : get_reg_val = `U_REGISTER_BANK.r9_out;
5'd10 : get_reg_val = `U_REGISTER_BANK.r10_out;
5'd11 : get_reg_val = `U_REGISTER_BANK.r11_out;
5'd12 : get_reg_val = `U_REGISTER_BANK.r12_out;
5'd13 : get_reg_val = `U_REGISTER_BANK.r13_out;
5'd14 : get_reg_val = `U_REGISTER_BANK.r14_out;
5'd15 : get_reg_val = `U_REGISTER_BANK.r15_out_rm; // the version of pc with status bits
5'd16 : get_reg_val = `U_REGISTER_BANK.r14_svc;
5'd17 : get_reg_val = `U_REGISTER_BANK.r14_firq;
5'd18 : get_reg_val = `U_REGISTER_BANK.r14_irq;
5'd19 : get_reg_val = `U_REGISTER_BANK.r14_svc;
5'd20 : get_reg_val = `U_REGISTER_BANK.r14_svc;
5'd21 : get_reg_val = `U_REGISTER_BANK.r15_out_rn; // the version of pc without status bits
endcase
end
endfunction
function [31:0] get_32bit_signal;
input [2:0] num;
begin
case (num)
3'd0: get_32bit_signal = `U_EXECUTE.pc_nxt;
3'd1: get_32bit_signal = `U_FETCH.i_address;
3'd2: get_32bit_signal = `U_FETCH.i_address;
3'd3: get_32bit_signal = `U_CACHE.i_write_data;
3'd4: get_32bit_signal = `U_DECODE.i_read_data;
endcase
end
endfunction
function get_1bit_signal;
input [2:0] num;
begin
case (num)
3'd0: get_1bit_signal = `U_FETCH.i_write_enable;
3'd1: get_1bit_signal = `U_AMBER.fetch_stall;
3'd2: get_1bit_signal = 1'd0;
3'd3: get_1bit_signal = `U_FETCH.i_data_access;
endcase
end
endfunction
function [3:0] get_4bit_signal;
input [2:0] num;
begin
case (num)
3'd0: get_4bit_signal = `U_CACHE.i_byte_enable;
endcase
end
endfunction
function [3:0] numchars;
input [(5*8)-1:0] xINSTRUCTION_EXECUTE;
begin
if (xINSTRUCTION_EXECUTE[31:0] == " ")
numchars = 4'd1;
else if (xINSTRUCTION_EXECUTE[23:0] == " ")
numchars = 4'd2;
else if (xINSTRUCTION_EXECUTE[15:0] == " ")
numchars = 4'd3;
else if (xINSTRUCTION_EXECUTE[7:0] == " ")
numchars = 4'd4;
else
numchars = 4'd5;
end
endfunction
function more_to_come;
input [15:0] regs;
input [31:0] i;
begin
case (i)
15 : more_to_come = 1'd0;
14 : more_to_come = regs[15] ? 1'd1 : 1'd0;
13 : more_to_come = |regs[15:14] ? 1'd1 : 1'd0;
12 : more_to_come = |regs[15:13] ? 1'd1 : 1'd0;
11 : more_to_come = |regs[15:12] ? 1'd1 : 1'd0;
10 : more_to_come = |regs[15:11] ? 1'd1 : 1'd0;
9 : more_to_come = |regs[15:10] ? 1'd1 : 1'd0;
8 : more_to_come = |regs[15: 9] ? 1'd1 : 1'd0;
7 : more_to_come = |regs[15: 8] ? 1'd1 : 1'd0;
6 : more_to_come = |regs[15: 7] ? 1'd1 : 1'd0;
5 : more_to_come = |regs[15: 6] ? 1'd1 : 1'd0;
4 : more_to_come = |regs[15: 5] ? 1'd1 : 1'd0;
3 : more_to_come = |regs[15: 4] ? 1'd1 : 1'd0;
2 : more_to_come = |regs[15: 3] ? 1'd1 : 1'd0;
1 : more_to_come = |regs[15: 2] ? 1'd1 : 1'd0;
0 : more_to_come = |regs[15: 1] ? 1'd1 : 1'd0;
endcase
end
endfunction
`endif
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Interface to Cypress FX2 bus
// A packet is 512 Bytes. Each fifo line is 2 bytes
// Fifo has 1024 or 2048 lines
module tx_buffer
( input usbclk,
input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
input reset, // standard DSP-side reset
input [15:0] usbdata,
input wire WR,
output wire have_space,
output reg tx_underrun,
input wire [3:0] channels,
output reg [15:0] tx_i_0,
output reg [15:0] tx_q_0,
output reg [15:0] tx_i_1,
output reg [15:0] tx_q_1,
output reg [15:0] tx_i_2,
output reg [15:0] tx_q_2,
output reg [15:0] tx_i_3,
output reg [15:0] tx_q_3,
input txclk,
input txstrobe,
input clear_status,
output wire tx_empty,
output [11:0] debugbus
);
wire [11:0] txfifolevel;
reg [8:0] write_count;
wire tx_full;
wire [15:0] fifodata;
wire rdreq;
reg [3:0] load_next;
// DAC Side of FIFO
assign rdreq = ((load_next != channels) & !tx_empty);
always @(posedge txclk)
if(reset)
begin
{tx_i_0,tx_q_0,tx_i_1,tx_q_1,tx_i_2,tx_q_2,tx_i_3,tx_q_3}
<= #1 128'h0;
load_next <= #1 4'd0;
end
else
if(load_next != channels)
begin
load_next <= #1 load_next + 4'd1;
case(load_next)
4'd0 : tx_i_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd1 : tx_q_0 <= #1 tx_empty ? 16'd0 : fifodata;
4'd2 : tx_i_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd3 : tx_q_1 <= #1 tx_empty ? 16'd0 : fifodata;
4'd4 : tx_i_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd5 : tx_q_2 <= #1 tx_empty ? 16'd0 : fifodata;
4'd6 : tx_i_3 <= #1 tx_empty ? 16'd0 : fifodata;
4'd7 : tx_q_3 <= #1 tx_empty ? 16'd0 : fifodata;
endcase // case(load_next)
end // if (load_next != channels)
else if(txstrobe & (load_next == channels))
begin
load_next <= #1 4'd0;
end
// USB Side of FIFO
assign have_space = (txfifolevel <= (4095-256));
always @(posedge usbclk)
if(bus_reset) // Use bus reset because this is on usbclk
write_count <= #1 0;
else if(WR & ~write_count[8])
write_count <= #1 write_count + 9'd1;
else
write_count <= #1 WR ? write_count : 9'b0;
// Detect Underruns
always @(posedge txclk)
if(reset)
tx_underrun <= 1'b0;
else if(txstrobe & (load_next != channels))
tx_underrun <= 1'b1;
else if(clear_status)
tx_underrun <= 1'b0;
// FIFO
fifo_4k txfifo
( .data ( usbdata ),
.wrreq ( WR & ~write_count[8] ),
.wrclk ( usbclk ),
.q ( fifodata ),
.rdreq ( rdreq ),
.rdclk ( txclk ),
.aclr ( reset ), // asynch, so we can use either
.rdempty ( tx_empty ),
.rdusedw ( ),
.wrfull ( tx_full ),
.wrusedw ( txfifolevel )
);
// Debugging Aids
assign debugbus[0] = WR;
assign debugbus[1] = have_space;
assign debugbus[2] = tx_empty;
assign debugbus[3] = tx_full;
assign debugbus[4] = tx_underrun;
assign debugbus[5] = write_count[8];
assign debugbus[6] = txstrobe;
assign debugbus[7] = rdreq;
assign debugbus[11:8] = load_next;
endmodule // tx_buffer
|
`timescale 1ns/1ps
module snap_action_shim #(
// Parameters of Axi Master Bus Interface AXI_CARD_MEM0 ; to DDR memory
parameter C_M_AXI_CARD_MEM0_ID_WIDTH = 2,
parameter C_M_AXI_CARD_MEM0_ADDR_WIDTH = 33,
parameter C_M_AXI_CARD_MEM0_DATA_WIDTH = 512,
parameter C_M_AXI_CARD_MEM0_AWUSER_WIDTH = 8,
parameter C_M_AXI_CARD_MEM0_ARUSER_WIDTH = 8,
parameter C_M_AXI_CARD_MEM0_WUSER_WIDTH = 1,
parameter C_M_AXI_CARD_MEM0_RUSER_WIDTH = 1,
parameter C_M_AXI_CARD_MEM0_BUSER_WIDTH = 1,
// Parameters of Axi Slave Bus Interface AXI_CTRL_REG
parameter C_S_AXI_CTRL_REG_DATA_WIDTH = 32,
parameter C_S_AXI_CTRL_REG_ADDR_WIDTH = 32,
// Parameters of Axi Master Bus Interface AXI_HOST_MEM ; to Host memory
parameter C_M_AXI_HOST_MEM_ID_WIDTH = 2,
parameter C_M_AXI_HOST_MEM_ADDR_WIDTH = 64,
parameter C_M_AXI_HOST_MEM_DATA_WIDTH = 512,
parameter C_M_AXI_HOST_MEM_AWUSER_WIDTH = 8,
parameter C_M_AXI_HOST_MEM_ARUSER_WIDTH = 8,
parameter C_M_AXI_HOST_MEM_WUSER_WIDTH = 1,
parameter C_M_AXI_HOST_MEM_RUSER_WIDTH = 1,
parameter C_M_AXI_HOST_MEM_BUSER_WIDTH = 1,
parameter C_PATTERN_WIDTH = 1744
)(
input clk ,
input rst_n ,
//---- AXI bus interfaced with SNAP core ----
// AXI write address channel
output [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_awid ,
output [C_M_AXI_HOST_MEM_ADDR_WIDTH - 1:0] m_axi_snap_awaddr ,
output [0007:0] m_axi_snap_awlen ,
output [0002:0] m_axi_snap_awsize ,
output [0001:0] m_axi_snap_awburst ,
output [0003:0] m_axi_snap_awcache ,
output [0001:0] m_axi_snap_awlock ,
output [0002:0] m_axi_snap_awprot ,
output [0003:0] m_axi_snap_awqos ,
output [0003:0] m_axi_snap_awregion ,
output [C_M_AXI_HOST_MEM_AWUSER_WIDTH - 1:0] m_axi_snap_awuser ,
output m_axi_snap_awvalid ,
input m_axi_snap_awready ,
// AXI write data channel
output [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_wid ,
output [C_M_AXI_HOST_MEM_DATA_WIDTH - 1:0] m_axi_snap_wdata ,
output [(C_M_AXI_HOST_MEM_DATA_WIDTH/8) - 1:0] m_axi_snap_wstrb ,
output m_axi_snap_wlast ,
output m_axi_snap_wvalid ,
input m_axi_snap_wready ,
// AXI write response channel
output m_axi_snap_bready ,
input [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_bid ,
input [0001:0] m_axi_snap_bresp ,
input m_axi_snap_bvalid ,
// AXI read address channel
output [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_arid ,
output [C_M_AXI_HOST_MEM_ADDR_WIDTH - 1:0] m_axi_snap_araddr ,
output [0007:0] m_axi_snap_arlen ,
output [0002:0] m_axi_snap_arsize ,
output [0001:0] m_axi_snap_arburst ,
output [C_M_AXI_HOST_MEM_ARUSER_WIDTH - 1:0] m_axi_snap_aruser ,
output [0003:0] m_axi_snap_arcache ,
output [0001:0] m_axi_snap_arlock ,
output [0002:0] m_axi_snap_arprot ,
output [0003:0] m_axi_snap_arqos ,
output [0003:0] m_axi_snap_arregion ,
output m_axi_snap_arvalid ,
input m_axi_snap_arready ,
// AXI ead data channel
output m_axi_snap_rready ,
input [C_M_AXI_HOST_MEM_ID_WIDTH - 1:0] m_axi_snap_rid ,
input [C_M_AXI_HOST_MEM_DATA_WIDTH - 1:0] m_axi_snap_rdata ,
input [0001:0] m_axi_snap_rresp ,
input m_axi_snap_rlast ,
input m_axi_snap_rvalid ,
/*
//---- AXI bus interfaced with DDR ----
// AXI write address channel
output [C_M_AXI_CARD_MEM0_ID_WIDTH - 1:0] m_axi_ddr_awid ,
output [C_M_AXI_CARD_MEM0_ADDR_WIDTH - 1:0] m_axi_ddr_awaddr ,
output [0007:0] m_axi_ddr_awlen ,
output [0002:0] m_axi_ddr_awsize ,
output [0001:0] m_axi_ddr_awburst ,
output [0003:0] m_axi_ddr_awcache ,
output [0001:0] m_axi_ddr_awlock ,
output [0002:0] m_axi_ddr_awprot ,
output [0003:0] m_axi_ddr_awqos ,
output [0003:0] m_axi_ddr_awregion ,
output [C_M_AXI_CARD_MEM0_AWUSER_WIDTH - 1:0] m_axi_ddr_awuser ,
output m_axi_ddr_awvalid ,
input m_axi_ddr_awready ,
// AXI write data channel
output [C_M_AXI_CARD_MEM0_ID_WIDTH - 1:0] m_axi_ddr_wid ,
output [C_M_AXI_CARD_MEM0_DATA_WIDTH - 1:0] m_axi_ddr_wdata ,
output [(C_M_AXI_CARD_MEM0_DATA_WIDTH/8) - 1:0] m_axi_ddr_wstrb ,
output m_axi_ddr_wlast ,
output m_axi_ddr_wvalid ,
input m_axi_ddr_wready ,
// AXI write response channel
output m_axi_ddr_bready ,
input [C_M_AXI_CARD_MEM0_ID_WIDTH - 1:0] m_axi_ddr_bid ,
input [0001:0] m_axi_ddr_bresp ,
input m_axi_ddr_bvalid ,
// AXI read address channel
output [C_M_AXI_CARD_MEM0_ID_WIDTH - 1:0] m_axi_ddr_arid ,
output [C_M_AXI_CARD_MEM0_ADDR_WIDTH - 1:0] m_axi_ddr_araddr ,
output [0007:0] m_axi_ddr_arlen ,
output [0002:0] m_axi_ddr_arsize ,
output [0001:0] m_axi_ddr_arburst ,
output [C_M_AXI_HOST_MEM_ARUSER_WIDTH - 1:0] m_axi_ddr_aruser ,
output [0003:0] m_axi_ddr_arcache ,
output [0001:0] m_axi_ddr_arlock ,
output [0002:0] m_axi_ddr_arprot ,
output [0003:0] m_axi_ddr_arqos ,
output [0003:0] m_axi_ddr_arregion ,
output m_axi_ddr_arvalid ,
input m_axi_ddr_arready ,
// AXI ead data channel
output m_axi_ddr_rready ,
input [C_M_AXI_CARD_MEM0_ID_WIDTH - 1:0] m_axi_ddr_rid ,
input [C_M_AXI_CARD_MEM0_DATA_WIDTH - 1:0] m_axi_ddr_rdata ,
input [0001:0] m_axi_ddr_rresp ,
input m_axi_ddr_rlast ,
input m_axi_ddr_rvalid ,
*/
//---- AXI Lite bus interfaced with SNAP core ----
// AXI write address channel
output s_axi_snap_awready ,
input [C_S_AXI_CTRL_REG_ADDR_WIDTH - 1:0] s_axi_snap_awaddr ,
input [0002:0] s_axi_snap_awprot ,
input s_axi_snap_awvalid ,
// axi write data channel
output s_axi_snap_wready ,
input [C_S_AXI_CTRL_REG_DATA_WIDTH - 1:0] s_axi_snap_wdata ,
input [(C_S_AXI_CTRL_REG_DATA_WIDTH/8) - 1:0] s_axi_snap_wstrb ,
input s_axi_snap_wvalid ,
// AXI response channel
output [0001:0] s_axi_snap_bresp ,
output s_axi_snap_bvalid ,
input s_axi_snap_bready ,
// AXI read address channel
output s_axi_snap_arready ,
input s_axi_snap_arvalid ,
input [C_S_AXI_CTRL_REG_ADDR_WIDTH - 1:0] s_axi_snap_araddr ,
input [0002:0] s_axi_snap_arprot ,
// AXI read data channel
output [C_S_AXI_CTRL_REG_DATA_WIDTH - 1:0] s_axi_snap_rdata ,
output [0001:0] s_axi_snap_rresp ,
input s_axi_snap_rready ,
output s_axi_snap_rvalid ,
// Other signals
input i_app_ready ,
input [31:0] i_action_type ,
input [31:0] i_action_version
);
wire[000:0] lcl_snap_ibusy;
wire[000:0] lcl_snap_obusy;
wire[000:0] lcl_snap_istart;
wire[000:0] lcl_snap_ostart;
wire[063:0] lcl_snap_iaddr;
wire[063:0] lcl_snap_oaddr;
wire[007:0] lcl_snap_inum;
wire[007:0] lcl_snap_onum;
wire[000:0] lcl_snap_irdy;
wire[000:0] lcl_snap_den;
wire[511:0] lcl_snap_din;
wire[000:0] lcl_snap_idone;
wire[000:0] lcl_snap_ordy;
wire[000:0] lcl_snap_rden;
wire[000:0] lcl_snap_dv;
wire[511:0] lcl_snap_dout;
wire[000:0] lcl_snap_odone;
wire[000:0] pattern_memcpy_enable;
wire[063:0] pattern_source_address;
wire[063:0] pattern_target_address;
wire[063:0] pattern_total_number;
wire[000:0] pattern_memcpy_done;
wire[005:0] wstat,rstat;
wire[003:0] werr,rerr;
wire[011:0] axi_snap_status = {wstat,rstat};
wire[011:0] axi_ddr_status;
wire[007:0] axi_snap_error = {werr, rerr};
wire[007:0] axi_ddr_error;
wire[023:0] axi_master_status = {axi_ddr_status,axi_snap_status};
wire[015:0] axi_master_error = {axi_ddr_error,axi_snap_error};
wire[031:0] snap_context;
//---- registers hub for AXI Lite interface ----
axi_lite_slave #(
.DATA_WIDTH (C_S_AXI_CTRL_REG_DATA_WIDTH ),
.ADDR_WIDTH (C_S_AXI_CTRL_REG_ADDR_WIDTH )
) maxi_lite_slave (
.clk (clk ),
.rst_n (rst_n ),
.s_axi_awready (s_axi_snap_awready ),
.s_axi_awaddr (s_axi_snap_awaddr ),//32b
.s_axi_awprot (s_axi_snap_awprot ),//3b
.s_axi_awvalid (s_axi_snap_awvalid ),
.s_axi_wready (s_axi_snap_wready ),
.s_axi_wdata (s_axi_snap_wdata ),//32b
.s_axi_wstrb (s_axi_snap_wstrb ),//4b
.s_axi_wvalid (s_axi_snap_wvalid ),
.s_axi_bresp (s_axi_snap_bresp ),//2b
.s_axi_bvalid (s_axi_snap_bvalid ),
.s_axi_bready (s_axi_snap_bready ),
.s_axi_arready (s_axi_snap_arready ),
.s_axi_arvalid (s_axi_snap_arvalid ),
.s_axi_araddr (s_axi_snap_araddr ),//32b
.s_axi_arprot (s_axi_snap_arprot ),//3b
.s_axi_rdata (s_axi_snap_rdata ),//32b
.s_axi_rresp (s_axi_snap_rresp ),//2b
.s_axi_rready (s_axi_snap_rready ),
.s_axi_rvalid (s_axi_snap_rvalid ),
//---- local control ----
.pattern_memcpy_enable (pattern_memcpy_enable ),
.pattern_source_address(pattern_source_address),//64b
.pattern_target_address(pattern_target_address),//64b
.pattern_total_number (pattern_total_number ),//64b
//---- local status ----
.pattern_memcpy_done (pattern_memcpy_done ),
//---- snap status ----
.i_app_ready (i_app_ready ),
.i_action_type (i_action_type ),
.i_action_version (i_action_version ),
.o_snap_context (snap_context )
);
//---- writing channel of AXI master interface facing SNAP ----
axi_master_wr#(
.ID_WIDTH (C_M_AXI_HOST_MEM_ID_WIDTH ),
.ADDR_WIDTH (C_M_AXI_HOST_MEM_ADDR_WIDTH ),
.DATA_WIDTH (C_M_AXI_HOST_MEM_DATA_WIDTH ),
.AWUSER_WIDTH (C_M_AXI_HOST_MEM_AWUSER_WIDTH ),
.ARUSER_WIDTH (C_M_AXI_HOST_MEM_ARUSER_WIDTH ),
.WUSER_WIDTH (C_M_AXI_HOST_MEM_WUSER_WIDTH ),
.RUSER_WIDTH (C_M_AXI_HOST_MEM_RUSER_WIDTH ),
.BUSER_WIDTH (C_M_AXI_HOST_MEM_BUSER_WIDTH )
) maxi_master_wr(
.clk (clk ),
.rst_n (rst_n),
.clear (1'b0 ),
.m_axi_awid (m_axi_snap_awid ),//20b
.m_axi_awaddr (m_axi_snap_awaddr ),//64b
.m_axi_awlen (m_axi_snap_awlen ),//8b
.m_axi_awsize (m_axi_snap_awsize ),//3b
.m_axi_awburst (m_axi_snap_awburst ),//2b
.m_axi_awcache (m_axi_snap_awcache ),//4b
.m_axi_awlock (m_axi_snap_awlock ),//2b
.m_axi_awprot (m_axi_snap_awprot ),//3b
.m_axi_awqos (m_axi_snap_awqos ),//4b
.m_axi_awregion(m_axi_snap_awregion),//4b
.m_axi_awuser (m_axi_snap_awuser ),
.m_axi_awvalid (m_axi_snap_awvalid ),
.m_axi_awready (m_axi_snap_awready ),
.m_axi_wid (m_axi_snap_wid ),//20b
.m_axi_wdata (m_axi_snap_wdata ),//512b
.m_axi_wstrb (m_axi_snap_wstrb ),//64b
.m_axi_wlast (m_axi_snap_wlast ),
.m_axi_wvalid (m_axi_snap_wvalid ),
.m_axi_wready (m_axi_snap_wready ),
.m_axi_bready (m_axi_snap_bready ),
.m_axi_bid (m_axi_snap_bid ),//20b
.m_axi_bresp (m_axi_snap_bresp ),//2b
.m_axi_bvalid (m_axi_snap_bvalid ),
.lcl_ibusy (lcl_snap_ibusy ),
.lcl_istart (lcl_snap_istart ),
.lcl_iaddr (lcl_snap_iaddr ),//64b
.lcl_inum (lcl_snap_inum ),//8b
.lcl_irdy (lcl_snap_irdy ),
.lcl_den (lcl_snap_den ),
.lcl_din (lcl_snap_din ),//512b
.lcl_idone (lcl_snap_idone ),
.status (wstat ),//6b
.error (werr ),//4b
.i_snap_context(snap_context )
);
//---- writing channel of AXI master interface facing SNAP ----
axi_master_rd#(
.ID_WIDTH (C_M_AXI_HOST_MEM_ID_WIDTH ),
.ADDR_WIDTH (C_M_AXI_HOST_MEM_ADDR_WIDTH ),
.DATA_WIDTH (C_M_AXI_HOST_MEM_DATA_WIDTH ),
.AWUSER_WIDTH (C_M_AXI_HOST_MEM_AWUSER_WIDTH ),
.ARUSER_WIDTH (C_M_AXI_HOST_MEM_ARUSER_WIDTH ),
.WUSER_WIDTH (C_M_AXI_HOST_MEM_WUSER_WIDTH ),
.RUSER_WIDTH (C_M_AXI_HOST_MEM_RUSER_WIDTH ),
.BUSER_WIDTH (C_M_AXI_HOST_MEM_BUSER_WIDTH )
) maxi_master_rd(
.clk (clk ),
.rst_n (rst_n),
.clear (1'b0 ),
.m_axi_arid (m_axi_snap_arid ),//20b
.m_axi_araddr (m_axi_snap_araddr ),//64b
.m_axi_arlen (m_axi_snap_arlen ),//8b
.m_axi_arsize (m_axi_snap_arsize ),//3b
.m_axi_arburst (m_axi_snap_arburst ),//2b
.m_axi_aruser (m_axi_snap_aruser ),
.m_axi_arcache (m_axi_snap_arcache ),//4b
.m_axi_arlock (m_axi_snap_arlock ),//2b
.m_axi_arprot (m_axi_snap_arprot ),//3b
.m_axi_arqos (m_axi_snap_arqos ),//4b
.m_axi_arregion(m_axi_snap_arregion),//4b
.m_axi_arvalid (m_axi_snap_arvalid ),
.m_axi_arready (m_axi_snap_arready ),
.m_axi_rready (m_axi_snap_rready ),
.m_axi_rid (m_axi_snap_rid ),//20b
.m_axi_rdata (m_axi_snap_rdata ),//512b
.m_axi_rresp (m_axi_snap_rresp ),//2b
.m_axi_rlast (m_axi_snap_rlast ),
.m_axi_rvalid (m_axi_snap_rvalid ),
.lcl_obusy (lcl_snap_obusy ),
.lcl_ostart (lcl_snap_ostart ),
.lcl_oaddr (lcl_snap_oaddr ),//64b
.lcl_onum (lcl_snap_onum ),//8b
.lcl_ordy (lcl_snap_ordy ),
.lcl_rden (lcl_snap_rden ),
.lcl_dv (lcl_snap_dv ),
.lcl_dout (lcl_snap_dout ),//512b
.lcl_odone (lcl_snap_odone ),
.status (rstat ),//6b
.error (rerr ),//4b
.i_snap_context(snap_context )
);
//---- memcpy burst management ----
memcpy_engine #(
.ADDR_WIDTH (C_M_AXI_HOST_MEM_ADDR_WIDTH ),
.DATA_WIDTH (C_M_AXI_HOST_MEM_DATA_WIDTH )
) mmemcpy_engine (
.clk (clk ),
.rst_n (rst_n ),
.memcpy_src_addr(pattern_source_address),
.memcpy_tgt_addr(pattern_target_address),
.memcpy_len (pattern_total_number ), // in terms of bytes
.memcpy_start (pattern_memcpy_enable ),
.memcpy_done (pattern_memcpy_done ),
.lcl_ibusy (lcl_snap_ibusy ),
.lcl_istart (lcl_snap_istart ),
.lcl_iaddr (lcl_snap_iaddr ),
.lcl_inum (lcl_snap_inum ),
.lcl_irdy (lcl_snap_irdy ),
.lcl_den (lcl_snap_den ),
.lcl_din (lcl_snap_din ),
.lcl_idone (lcl_snap_idone ),
.lcl_obusy (lcl_snap_obusy ),
.lcl_ostart (lcl_snap_ostart ),
.lcl_oaddr (lcl_snap_oaddr ),
.lcl_onum (lcl_snap_onum ),
.lcl_ordy (lcl_snap_ordy ),
.lcl_rden (lcl_snap_rden ),
.lcl_dv (lcl_snap_dv ),
.lcl_dout (lcl_snap_dout ),
.lcl_odone (lcl_snap_odone )
);
endmodule
|
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
`define DDIFF_BITS 9
`define AOA_BITS 8
`define HALF_DDIFF `DDIFF_BITS'd256
`define MAX_AOA `AOA_BITS'd255
`define BURP_DIVIDER 9'd16
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [`DDIFF_BITS-1:0] DDIFF_B = crc[`DDIFF_BITS-1:0];
wire reset = (cyc<7);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.AOA_B (AOA_B[`AOA_BITS-1:0]),
// Inputs
.DDIFF_B (DDIFF_B[`DDIFF_BITS-1:0]),
.reset (reset),
.clk (clk));
// Aggregate outputs into a single result vector
wire [63:0] result = {56'h0, AOA_B};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h3a74e9d34771ad93
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
AOA_B,
// Inputs
DDIFF_B, reset, clk
);
input [`DDIFF_BITS-1:0] DDIFF_B;
input reset;
input clk;
output reg [`AOA_BITS-1:0] AOA_B;
reg [`AOA_BITS-1:0] AOA_NEXT_B;
reg [`AOA_BITS-1:0] tmp;
always @(posedge clk) begin
if (reset) begin
AOA_B <= 8'h80;
end
else begin
AOA_B <= AOA_NEXT_B;
end
end
always @* begin
// verilator lint_off WIDTH
tmp = ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER);
t_aoa_update(AOA_NEXT_B, AOA_B, ((`HALF_DDIFF-DDIFF_B)/`BURP_DIVIDER));
// verilator lint_on WIDTH
end
task t_aoa_update;
output [`AOA_BITS-1:0] aoa_reg_next;
input [`AOA_BITS-1:0] aoa_reg;
input [`AOA_BITS-1:0] aoa_delta_update;
begin
if ((`MAX_AOA-aoa_reg)<aoa_delta_update) //Overflow protection
aoa_reg_next=`MAX_AOA;
else
aoa_reg_next=aoa_reg+aoa_delta_update;
end
endtask
endmodule
|
/****************************************
MIST1032 - Core-Main Pipeline
[ODCP] Open Design Computer Project
****************************************/
`default_nettype none
module core_pipeline #(
parameter CORE_ID = 32'h0
)(
//System
input wire iCLOCK,
input wire inRESET,
/****************************************
System
****************************************/
output wire oFREE_TLB_FLUSH,
/****************************************
GCI Controll
****************************************/
//Interrupt Controll
output wire oIO_IRQ_CONFIG_TABLE_REQ,
output wire [5:0] oIO_IRQ_CONFIG_TABLE_ENTRY,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_MASK,
output wire oIO_IRQ_CONFIG_TABLE_FLAG_VALID,
output wire [1:0] oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL,
/****************************************
Instrution Memory
****************************************/
//Req
output wire oINST_REQ,
input wire iINST_LOCK,
output wire [1:0] oINST_MMUMOD,
output wire [31:0] oINST_PDT,
output wire [31:0] oINST_ADDR,
//RAM -> This
input wire iINST_VALID,
output wire oINST_BUSY,
input wire iINST_PAGEFAULT,
input wire iINST_QUEUE_FLUSH,
input wire [63:0] iINST_DATA,
input wire [27:0] iINST_MMU_FLAGS,
/****************************************
Load Store Access
****************************************/
//Req
output wire oDATA_REQ,
input wire iDATA_LOCK,
output wire [1:0] oDATA_ORDER,
output wire [3:0] oDATA_MASK,
output wire oDATA_RW, //0=Write 1=Read
output wire [13:0] oDATA_TID,
output wire [1:0] oDATA_MMUMOD,
output wire [31:0] oDATA_PDT,
output wire [31:0] oDATA_ADDR,
//This -> Data RAM
output wire [31:0] oDATA_DATA,
//Data RAM -> This
input wire iDATA_VALID,
input wire iDATA_PAGEFAULT,
input wire [63:0] iDATA_DATA,
input wire [27:0] iDATA_MMU_FLAGS,
/****************************************
IO
****************************************/
//Req
output wire oIO_REQ,
input wire iIO_BUSY,
output wire [1:0] oIO_ORDER,
output wire oIO_RW, //0=Write 1=Read
output wire [31:0] oIO_ADDR,
//Write
output wire [31:0] oIO_DATA,
//Rec
input wire iIO_VALID,
input wire [31:0] iIO_DATA,
/****************************************
Interrupt
****************************************/
input wire iINTERRUPT_VALID,
input wire [5:0] iINTERRUPT_NUM,
output wire oINTERRUPT_ACK,
/****************************************
System Infomation
****************************************/
//IOSR(Input Output Status Register)
input wire iSYSINFO_IOSR_VALID,
input wire [31:0] iSYSINFO_IOSR
);
//Dummy
assign oFREE_TLB_FLUSH = 1'b0;
/****************************************
Core Internal wire
****************************************/
//FreeRegister
wire freereg_renaming2scheduler1_flag0_rd;
wire [3:0] freereg_renaming2scheduler1_flag0_num;
wire freereg_renaming2scheduler1_flag0_empty;
wire freereg_renaming2scheduler1_flag1_rd;
wire [3:0] freereg_renaming2scheduler1_flag1_num;
wire freereg_renaming2scheduler1_flag1_empty;
wire freereg_renaming2scheduler1_other0_rd;
wire [5:0] freereg_renaming2scheduler1_other0_num;
wire freereg_renaming2scheduler1_other0_empty;
wire freereg_renaming2scheduler1_other1_rd;
wire [5:0] freereg_renaming2scheduler1_other1_num;
wire freereg_renaming2scheduler1_other1_empty;
wire freereg_scheduler12scheduler2_flag0_wr;
wire [3:0] freereg_scheduler12scheduler2_flag0_num;
wire freereg_scheduler12scheduler2_flag0_full;
wire [1:0] freereg_scheduler12scheduler2_flag0_count;
wire freereg_scheduler12scheduler2_flag1_wr;
wire [3:0] freereg_scheduler12scheduler2_flag1_num;
wire freereg_scheduler12scheduler2_flag1_full;
wire [1:0] freereg_scheduler12scheduler2_flag1_count;
wire freereg_scheduler12scheduler2_other0_wr;
wire [5:0] freereg_scheduler12scheduler2_other0_num;
wire freereg_scheduler12scheduler2_other0_full;
wire [2:0] freereg_scheduler12scheduler2_other0_count;
wire freereg_scheduler12scheduler2_other1_wr;
wire [5:0] freereg_scheduler12scheduler2_other1_num;
wire freereg_scheduler12scheduler2_other1_full;
wire [2:0] freereg_scheduler12scheduler2_other1_count;
//Jump
wire jump_active;
wire [31:0] jump_addr;
//Free
wire [63:0] free_register;
//Info
wire [5:0] commit_counter;
wire exception_protect;
//Re Order Buffer
wire [63:0] commit_vector;
//Commit
wire [2:0] commit_offset;
//Stage Info
wire stage_info_renaming_0_valid;
wire stage_info_renaming_1_valid;
wire stage_info_scheduler1_0_valid;
wire stage_info_scheduler1_1_valid;
wire [5:0] stage_info_scheduler1_regist_pointer;
wire [5:0] stage_info_scheduler1_commit_pointer;
//Renaming Table
wire scheduler12renaming_rollback_update_info0_valid;
wire [4:0] scheduler12renaming_rollback_update_info0_lregname;
wire [5:0] scheduler12renaming_rollback_update_info0_pregname;
wire scheduler12renaming_rollback_update_info0_sysreg;
wire scheduler12renaming_rollback_update_info1_valid;
wire [4:0] scheduler12renaming_rollback_update_info1_lregname;
wire [5:0] scheduler12renaming_rollback_update_info1_pregname;
wire scheduler12renaming_rollback_update_info1_sysreg;
wire scheduler12renaming_rollback_update_info2_valid;
wire [4:0] scheduler12renaming_rollback_update_info2_lregname;
wire [5:0] scheduler12renaming_rollback_update_info2_pregname;
wire scheduler12renaming_rollback_update_info2_sysreg;
wire scheduler12renaming_rollback_update_info3_valid;
wire [4:0] scheduler12renaming_rollback_update_info3_lregname;
wire [5:0] scheduler12renaming_rollback_update_info3_pregname;
wire scheduler12renaming_rollback_update_info3_sysreg;
wire scheduler12renaming_flags_rollback_update_info0_valid;
wire [3:0] scheduler12renaming_flags_rollback_update_info0_pregname;
wire scheduler12renaming_flags_rollback_update_info1_valid;
wire [3:0] scheduler12renaming_flags_rollback_update_info1_pregname;
wire scheduler12renaming_flags_rollback_update_info2_valid;
wire [3:0] scheduler12renaming_flags_rollback_update_info2_pregname;
wire scheduler12renaming_flags_rollback_update_info3_valid;
wire [3:0] scheduler12renaming_flags_rollback_update_info3_pregname;
//I-cache to Fetch
wire icache2fetch_0_inst_valid;
//wire icache2fetch_0_inst_pagefault;
wire [13:0] icache2fetch_0_inst_mmuflags;
wire [31:0] icache2fetch_0_inst_inst;
wire icache2fetch_1_inst_valid;
//wire icache2fetch_1_inst_pagefault;
wire [13:0] icache2fetch_1_inst_mmuflags;
wire [31:0] icache2fetch_1_inst_inst;
wire fetch2icache_inst_busy;
wire fetch2icache_inst_req;
wire [31:0] fetch2icache_inst_addr;
wire icache2fetch_inst_busy;
//Fetch to Decoder and Decoder to Fetch
wire fetch2decoder_0_inst_valid;
wire [5:0] fetch2decoder_0_mmu_flags;
wire [31:0] fetch2decoder_0_inst;
wire fetch2decoder_1_inst_valid;
wire [5:0] fetch2decoder_1_mmu_flags;
wire [31:0] fetch2decoder_1_inst;
wire [31:0] fetch2decoder_pc;
wire decoder2fetch_lock;
//Decoder to Matching and Matching to Fetch
wire decoder2matching_0_valid;
wire [5:0] decoder2matching_0_mmu_flags;
wire decoder2matching_0_source0_active;
wire decoder2matching_0_source1_active;
wire decoder2matching_0_source0_sysreg;
wire decoder2matching_0_source1_sysreg;
wire decoder2matching_0_source0_sysreg_rename;
wire decoder2matching_0_source1_sysreg_rename;
wire decoder2matching_0_adv_active;
wire [5:0] decoder2matching_0_adv_data;
wire decoder2matching_0_destination_sysreg;
wire decoder2matching_0_dest_rename;
wire decoder2matching_0_writeback;
wire decoder2mathsing_0_flags_writeback;
wire decoder2matching_0_front_commit_wait;
wire [4:0] decoder2matching_0_cmd;
wire [3:0] decoder2matching_0_cc_afe;
wire [4:0] decoder2matching_0_source0;
wire [31:0] decoder2matching_0_source1;
wire decoder2matching_0_source0_flags;
wire decoder2matching_0_source1_imm;
wire [4:0] decoder2matching_0_destination;
wire decoder2matching_0_sys_reg;
wire decoder2matching_0_sys_ldst;
wire decoder2matching_0_logic;
wire decoder2matching_0_shift;
wire decoder2matching_0_adder;
wire decoder2matching_0_mul;
wire decoder2matching_0_sdiv;
wire decoder2matching_0_udiv;
wire decoder2matching_0_ldst;
wire decoder2matching_0_branch;
wire decoder2matching_1_valid;
wire [5:0] decoder2matching_1_mmu_flags;
wire decoder2matching_1_source0_active;
wire decoder2matching_1_source1_active;
wire decoder2matching_1_source0_sysreg;
wire decoder2matching_1_source1_sysreg;
wire decoder2matching_1_source0_sysreg_rename;
wire decoder2matching_1_source1_sysreg_rename;
wire decoder2matching_1_adv_active;
wire [5:0] decoder2matching_1_adv_data;
wire decoder2matching_1_destination_sysreg;
wire decoder2matching_1_dest_rename;
wire decoder2matching_1_writeback;
wire decoder2mathsing_1_flags_writeback;
wire decoder2matching_1_front_commit_wait;
wire [4:0] decoder2matching_1_cmd;
wire [3:0] decoder2matching_1_cc_afe;
wire [4:0] decoder2matching_1_source0;
wire [31:0] decoder2matching_1_source1;
wire decoder2matching_1_source0_flags;
wire decoder2matching_1_source1_imm;
wire [4:0] decoder2matching_1_destination;
wire decoder2matching_1_sys_reg;
wire decoder2matching_1_sys_ldst;
wire decoder2matching_1_logic;
wire decoder2matching_1_shift;
wire decoder2matching_1_adder;
wire decoder2matching_1_mul;
wire decoder2matching_1_sdiv;
wire decoder2matching_1_udiv;
wire decoder2matching_1_ldst;
wire decoder2matching_1_branch;
wire [31:0] decoder2matching_pc;
wire matching2decoder_lock;
//Matching to Fetch
wire matching2fetch_loopbuffer_limit;
//Matching to Renaming and Renaming to Matching
wire matching2renaming_0_valid;
wire matching2renaming_0_source0_active;
wire matching2renaming_0_source1_active;
wire matching2renaming_0_source0_sysreg;
wire matching2renaming_0_source1_sysreg;
wire matching2renaming_0_source0_sysreg_rename;
wire matching2renaming_0_source1_sysreg_rename;
wire matching2renaming_0_adv_active;
wire matching2renaming_0_destination_sysreg;
wire matching2renaming_0_dest_rename;
wire matching2renaming_0_writeback;
wire matching2renaming_0_flags_writeback;
wire [4:0] matching2renaming_0_cmd;
wire [3:0] matching2renaming_0_cc_afe;
wire [4:0] matching2renaming_0_source0;
wire [31:0] matching2renaming_0_source1;
wire [5:0] matching2renaming_0_adv_data;
wire matching2renaming_0_source0_flags;
wire matching2renaming_0_source1_imm;
wire [4:0] matching2renaming_0_destination;
wire matching2renaming_0_sys_adder;
wire matching2renaming_0_sys_ldst;
wire matching2renaming_0_logic;
wire matching2renaming_0_shift;
wire matching2renaming_0_adder;
wire matching2renaming_0_mul;
wire matching2renaming_0_sdiv;
wire matching2renaming_0_udiv;
wire matching2renaming_0_ldst;
wire matching2renaming_0_branch;
wire matching2renaming_1_valid;
wire matching2renaming_1_source0_active;
wire matching2renaming_1_source1_active;
wire matching2renaming_1_source0_sysreg;
wire matching2renaming_1_source1_sysreg;
wire matching2renaming_1_source0_sysreg_rename;
wire matching2renaming_1_source1_sysreg_rename;
wire matching2renaming_1_adv_active;
wire matching2renaming_1_destination_sysreg;
wire matching2renaming_1_dest_rename;
wire matching2renaming_1_writeback;
wire matching2renaming_1_flags_writeback;
wire matching2renaming_1_system_end;
wire [4:0] matching2renaming_1_cmd;
wire [3:0] matching2renaming_1_cc_afe;
wire [4:0] matching2renaming_1_source0;
wire [31:0] matching2renaming_1_source1;
wire [5:0] matching2renaming_1_adv_data;
wire matching2renaming_1_source0_flags;
wire matching2renaming_1_source1_imm;
wire [4:0] matching2renaming_1_destination;
wire matching2renaming_1_sys_adder;
wire matching2renaming_1_sys_ldst;
wire matching2renaming_1_logic;
wire matching2renaming_1_shift;
wire matching2renaming_1_adder;
wire matching2renaming_1_mul;
wire matching2renaming_1_sdiv;
wire matching2renaming_1_udiv;
wire matching2renaming_1_ldst;
wire matching2renaming_1_branch;
wire [31:0] matching2renaming_pc;
wire renaming2matching_lock;
//Renaming to Scheduler1 and Scheduler1 to Renaming
wire renaming2scheduler1_0_valid;
wire renaming2scheduler1_0_source0_active;
wire renaming2scheduler1_0_source1_active;
wire renaming2scheduler1_0_source0_sysreg;
wire renaming2scheduler1_0_source1_sysreg;
wire renaming2scheduler1_0_source0_sysreg_rename;
wire renaming2scheduler1_0_source1_sysreg_rename;
wire renaming2scheduler1_0_adv_active;
wire renaming2scheduler1_0_destination_sysreg;
wire renaming2scheduler1_0_data_writeback;
wire renaming2scheduler1_0_flags_writeback;
wire [4:0] renaming2scheduler1_0_cmd;
wire [3:0] renaming2scheduler1_0_cc_afe;
wire [3:0] renaming2scheduler1_0_flags_regname;
wire [5:0] renaming2scheduler1_0_destination_regname;
wire [4:0] renaming2scheduler1_0_logic_destination;
wire [5:0] renaming2scheduler1_0_source0;
wire [31:0] renaming2scheduler1_0_source1;
wire [5:0] renaming2scheduler1_0_adv_data;
wire renaming2scheduler1_0_source0_flags;
wire renaming2scheduler1_0_source1_imm;
wire renaming2scheduler1_0_sys_adder;
wire renaming2scheduler1_0_sys_ldst;
wire renaming2scheduler1_0_logic;
wire renaming2scheduler1_0_shift;
wire renaming2scheduler1_0_adder;
wire renaming2scheduler1_0_mul;
wire renaming2scheduler1_0_sdiv;
wire renaming2scheduler1_0_udiv;
wire renaming2scheduler1_0_ldst;
wire renaming2scheduler1_0_branch;
wire renaming2scheduler1_1_valid;
wire renaming2scheduler1_1_source0_active;
wire renaming2scheduler1_1_source1_active;
wire renaming2scheduler1_1_source0_sysreg;
wire renaming2scheduler1_1_source1_sysreg;
wire renaming2scheduler1_1_source0_sysreg_rename;
wire renaming2scheduler1_1_source1_sysreg_rename;
wire renaming2scheduler1_1_adv_active;
wire renaming2scheduler1_1_destination_sysreg;
wire renaming2scheduler1_1_data_writeback;
wire renaming2scheduler1_1_flags_writeback;
wire [4:0] renaming2scheduler1_1_cmd;
wire [3:0] renaming2scheduler1_1_cc_afe;
wire [3:0] renaming2scheduler1_1_flags_regname;
wire [5:0] renaming2scheduler1_1_destination_regname;
wire [4:0] renaming2scheduler1_1_logic_destination;
wire [5:0] renaming2scheduler1_1_source0;
wire [31:0] renaming2scheduler1_1_source1;
wire [5:0] renaming2scheduler1_1_adv_data;
wire renaming2scheduler1_1_source0_flags;
wire renaming2scheduler1_1_source_imm;
wire renaming2scheduler1_1_sys_adder;
wire renaming2scheduler1_1_sys_ldst;
wire renaming2scheduler1_1_logic;
wire renaming2scheduler1_1_shift;
wire renaming2scheduler1_1_adder;
wire renaming2scheduler1_1_mul;
wire renaming2scheduler1_1_sdiv;
wire renaming2scheduler1_1_udiv;
wire renaming2scheduler1_1_ldst;
wire renaming2scheduler1_1_branch;
wire [31:0] renaming2scheduler1_pc;
wire scheduler12renaming_lock;
//Scheduler1 to Scheduler2 and Scheduler2 to Scheduler1
wire scheduler12scheduler2_0_valid;
wire scheduler12scheduler2_0_source0_active;
wire scheduler12scheduler2_0_source1_active;
wire scheduler12scheduler2_0_source0_sysreg;
wire scheduler12scheduler2_0_source1_sysreg;
wire scheduler12scheduler2_0_source0_sysreg_rename;
wire scheduler12scheduler2_0_source1_sysreg_rename;
wire scheduler12scheduler2_0_adv_active;
wire scheduler12scheduler2_0_destination_sysreg;
wire scheduler12scheduler2_0_writeback;
wire scheduler12scheduler2_0_flags_writeback;
wire [4:0] scheduler12scheduler2_0_cmd;
wire [5:0] scheduler12scheduler2_0_commit_tag;
wire [3:0] scheduler12scheduler2_0_cc_afe;
wire [3:0] scheduler12scheduler2_0_flags_regname;
wire [5:0] scheduler12scheduler2_0_destination_regname;
wire [4:0] scheduler12scheduler2_0_logic_destination;
wire [5:0] scheduler12scheduler2_0_source0;
wire [31:0] scheduler12scheduler2_0_source1;
wire [5:0] scheduler12scheduler2_0_adv_data;
wire scheduler12scheduler2_0_source0_flags;
wire scheduler12scheduler2_0_source1_imm;
wire scheduler12scheduler2_0_sys_reg;
wire scheduler12scheduler2_0_sys_ldst;
wire scheduler12scheduler2_0_logic;
wire scheduler12scheduler2_0_shift;
wire scheduler12scheduler2_0_adder;
wire scheduler12scheduler2_0_mul;
wire scheduler12scheduler2_0_sdiv;
wire scheduler12scheduler2_0_udiv;
wire scheduler12scheduler2_0_ldst;
wire scheduler12scheduler2_0_branch;
wire scheduler12scheduler2_1_valid;
wire scheduler12scheduler2_1_source0_active;
wire scheduler12scheduler2_1_source1_active;
wire scheduler12scheduler2_1_source0_sysreg;
wire scheduler12scheduler2_1_source1_sysreg;
wire scheduler12scheduler2_1_source0_sysreg_rename;
wire scheduler12scheduler2_1_source1_sysreg_rename;
wire scheduler12scheduler2_1_adv_active;
wire scheduler12scheduler2_1_destination_sysreg;
wire scheduler12scheduler2_1_writeback;
wire scheduler12scheduler2_1_flags_writeback;
wire [4:0] scheduler12scheduler2_1_cmd;
wire [5:0] scheduler12scheduler2_1_commit_tag;
wire [3:0] scheduler12scheduler2_1_cc_afe;
wire [3:0] scheduler12scheduler2_1_flags_regname;
wire [5:0] scheduler12scheduler2_1_destination_regname;
wire [4:0] scheduler12scheduler2_1_logic_destination;
wire [5:0] scheduler12scheduler2_1_source0;
wire [31:0] scheduler12scheduler2_1_source1;
wire [5:0] scheduler12scheduler2_1_adv_data;
wire scheduler12scheduler2_1_source0_flags;
wire scheduler12scheduler2_1_source1_imm;
wire scheduler12scheduler2_1_sys_reg;
wire scheduler12scheduler2_1_sys_ldst;
wire scheduler12scheduler2_1_logic;
wire scheduler12scheduler2_1_shift;
wire scheduler12scheduler2_1_adder;
wire scheduler12scheduler2_1_mul;
wire scheduler12scheduler2_1_sdiv;
wire scheduler12scheduler2_1_udiv;
wire scheduler12scheduler2_1_ldst;
wire scheduler12scheduler2_1_branch;
wire [31:0] scheduler12scheduler2_pc;
wire scheduler22scheduler1_lock;
//Scheduler2 to alu0 and alu0 to Scheduler2
wire scheduler22ex_alu0_valid;
wire [5:0] scheduler22ex_alu0_commit_tag;
wire [4:0] scheduler22ex_alu0_cmd;
wire [3:0] scheduler22ex_alu0_cc;
wire [4:0] scheduler22ex_alu0_flag;
wire [31:0] scheduler22ex_alu0_source;
wire [31:0] scheduler22ex_alu0_pc;
wire ex_alu02scheduler2_lock;
wire ex_alu02scheduler2_branch_valid;
wire [5:0] ex_alu02scheduler2_branch_commit_tag;
//Scheduler2 to alu1
wire scheduler22ex_alu1_valid;
wire scheduler22ex_alu1_writeback;
wire [5:0] scheduler22ex_alu1_commit_tag;
wire [4:0] scheduler22ex_alu1_cmd;
wire [3:0] scheduler22ex_alu1_afe;
wire scheduler22ex_alu1_sys_reg;
wire scheduler22ex_alu1_logic;
wire scheduler22ex_alu1_shift;
wire scheduler22ex_alu1_adder;
wire scheduler22ex_alu1_mul;
wire scheduler22ex_alu1_sdiv;
wire scheduler22ex_alu1_udiv;
wire [31:0] scheduler22ex_alu1_source0;
wire [31:0] scheduler22ex_alu1_source1;
wire scheduler22ex_alu1_destination_sysreg;
wire [4:0] scheduler22ex_alu1_logic_dest;
wire [5:0] scheduler22ex_alu1_destination_regname;
wire scheduler22ex_alu1_flags_writeback;
wire [3:0] scheduler22ex_alu1_flags_regname;
wire [31:0] scheduler22ex_alu1_pcr;
wire ex_alu12scheduler2_lock;
wire ex_alu12scheduler2_valid;
wire [5:0] ex_alu12scheduler2_commit_tag;
wire ex_alu12scheduler2_destination_sysreg;
wire [5:0] ex_alu12scheduler2_destination_regname;
wire ex_alu12scheduler2_writeback;
wire [31:0] ex_alu12scheduler2_data;
wire [4:0] ex_alu12scheduler2_flag;
wire ex_alu12scheduler2_flags_writeback;
wire [3:0] ex_alu12scheduler2_flags_regname;
//Scheduler2 to alu2
wire scheduler22ex_alu2_valid;
wire scheduler22ex_alu2_writeback;
wire [5:0] scheduler22ex_alu2_commit_tag;
wire [4:0] scheduler22ex_alu2_cmd;
wire [3:0] scheduler22ex_alu2_afe;
wire scheduler22ex_alu2_sys_reg;
wire scheduler22ex_alu2_logic;
wire scheduler22ex_alu2_shift;
wire scheduler22ex_alu2_adder;
wire [31:0] scheduler22ex_alu2_source0;
wire [31:0] scheduler22ex_alu2_source1;
wire scheduler22ex_alu2_destination_sysreg;
wire [4:0] scheduler22ex_alu2_logic_dest;
wire [5:0] scheduler22ex_alu2_destination_regname;
wire scheduler22ex_alu2_flags_writeback;
wire [3:0] scheduler22ex_alu2_flags_regname;
wire [31:0] scheduler22ex_alu2_pcr;
wire ex_alu22scheduler2_lock;
wire ex_alu22scheduler2_valid;
wire [5:0] ex_alu22scheduler2_commit_tag;
wire ex_alu22scheduler2_destination_sysreg;
wire [5:0] ex_alu22scheduler2_destination_regname;
wire ex_alu22scheduler2_writeback;
wire [31:0] ex_alu22scheduler2_data;
wire [4:0] ex_alu22scheduler2_flag;
wire ex_alu22scheduler2_flags_writeback;
wire [3:0] ex_alu22scheduler2_flags_regname;
//Scheduler2 to alu3 and alu3 to scheduler2
wire scheduler22ex_alu3_valid;
wire scheduler22ex_alu3_destination_sysreg;
wire [5:0] scheduler22ex_alu3_commit_tag;
wire [4:0] scheduler22ex_alu3_cmd;
wire scheduler22ex_alu3_sys_ldst;
wire scheduler22ex_alu3_ldst;
wire [31:0] scheduler22ex_alu3_source0;
wire [31:0] scheduler22ex_alu3_source1;
wire scheduler22ex_alu3_adv_active;
wire [5:0] scheduler22ex_alu3_adv_data;
wire [4:0] scheduler22ex_alu3_logic_dest;
wire [5:0] scheduler22ex_alu3_destination_regname;
wire [31:0] scheduler22ex_alu3_pc;
wire ex_alu32scheduler2_ldst_lock;
wire ex_alu32scheduler2_ldst_valid;
wire [5:0] ex_alu32scheduler2_ldst_commit_tag;
wire [5:0] ex_alu32scheduler2_ldst_destination_regname;
wire ex_alu32scheduler2_ldst_destination_sysreg;
wire ex_alu32scheduler2_ldst_writeback;
wire [31:0] ex_alu32scheduler2_ldst_data;
//alu0-3 to scheduler1
wire ex_alu02scheduler1_branch_valid;
wire [5:0] ex_alu02scheduler1_branch_commit_tag;
wire ex_alu12scheduler1_valid;
wire [5:0] ex_alu12scheduler1_commit_tag;
wire ex_alu22scheduler1_valid;
wire [5:0] ex_alu22scheduler1_commit_tag;
wire ex_alu32scheduler1_ldst_valid;
wire [5:0] ex_alu32scheduler1_ldst_commit_tag;
//alu0 to IIC
wire ex_alu02iic_swi_active;
wire [10:0] ex_alu02iic_swi_number;
//alu0~3 to CIM
wire ex_alu12cim_valid;
wire [10:0] ex_alu12cim_num;
//SystemRegister
wire [31:0] wire_sysreg_tidr;
wire [31:0] wire_sysreg_ptidr;
wire [31:0] wire_sysreg_psr;
wire [31:0] wire_sysreg_ppsr;
wire [31:0] wire_sysreg_tisr;
wire [31:0] wire_sysreg_pdtr;
wire [31:0] wire_sysreg_idtr;
wire [31:0] wire_sysreg_ppcr;
wire [31:0] wire_sysreg_spr;
//ALU3 to Load Store Selector
wire alu32ldst_ldst_req;
wire ldst2alu3_ldst_busy;
wire [1:0] alu32ldst_ldst_order;
wire [3:0] alu32ldst_ldst_mask;
wire alu32ldst_ldst_rw;
wire [13:0] alu32ldst_ldst_tid;
wire [1:0] alu32ldst_ldst_mmumod;
wire [31:0] alu32ldst_ldst_pdt;
wire [31:0] alu32ldst_ldst_addr;
wire [31:0] alu32ldst_ldst_data;
wire ldst2alu3_ldst_req;
wire [31:0] ldst2alu3_ldst_data;
/****************************************
Internal Interrupt Controlor
****************************************/
wire exception2cim_irq_lock;
wire cim2exception_irq_req;
wire [6:0] cim2exception_irq_num;
wire exception2cim_irq_ack;
wire exception2ldst_ldst_use;
wire exception2ldst_ldst_req;
wire ldst2exception_ldst_busy;
wire [1:0] exception2ldst_ldst_order;
wire exception2ldst_ldst_rw;
wire [13:0] exception2ldst_ldst_tid;
wire [1:0] exception2ldst_ldst_mmumod;
wire [31:0] exception2ldst_ldst_pdt;
wire [31:0] exception2ldst_ldst_addr;
wire [31:0] exception2ldst_ldst_data;
wire ldst2exception_ldst_req;
wire [31:0] ldst2exception_ldst_data;
wire exception2cim_ict_req;
wire [5:0] exception2cim_ict_entry;
wire exception2cim_ict_conf_mask;
wire exception2cim_ict_conf_valid;
wire [1:0] exception2cim_ict_conf_level;
wire exception2alu0_new_spr_valid;
wire [31:0] exception2alu0_new_spr;
wire ex_alu02exception_intr_active;
wire [31:0] ex_alu02exception_intr_addr;
wire ex_alu02exception_idts_active;
wire [31:0] ex_alu02exception_idts_r_addr;
wire [5:0] ex_alu02exception_idts_commit_tag;
wire [31:0] current_execution_pc;
wire exception_inst_discard;
wire exception_event;
wire [5:0] exception_commit_tag;
wire exception_addr_set;
wire [31:0] exception_addr;
wire exception_restart;
wire [31:0] exception_current_pc;
wire exception2scheduler2_irq_reqister_set;
wire exception2scheduler2_irq_reqister_ret;
core_interrupt_manager CORE_INT_M(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Exception
.iFREE_IRQ_SETCONDITION(exception2scheduler2_irq_reqister_set),
//Core Interrupt Configlation Table
.iICT_VALID(exception2cim_ict_req),
.iICT_ENTRY(exception2cim_ict_entry),
.iICT_CONF_MASK(exception2cim_ict_conf_mask),
.iICT_CONF_VALID(exception2cim_ict_conf_valid),
.iICT_CONF_LEVEL(exception2cim_ict_conf_level),
//Sysreg
.iSYSREGINFO_PSR(wire_sysreg_psr),
//Interrupt Input
.iEXT_ACTIVE(iINTERRUPT_VALID),
.iEXT_NUM(iINTERRUPT_NUM),
.oEXT_ACK(oINTERRUPT_ACK),
//Internal IRQ
/*
.iSWI_ACTIVE(ex_alu02iic_swi_active),
.iSWI_NUM(ex_alu02iic_swi_number[6:0]),
//To Exception Manager
.iEXCEPTION_LOCK(exception2cim_irq_lock),
.oEXCEPTION_ACTIVE(cim2exception_irq_req),
.oEXCEPTION_IRQ_NUM(cim2exception_irq_num),
.iEXCEPTION_IRQ_ACK(exception2cim_irq_ack)
*/
.iFAULT_ACTIVE(ex_alu02iic_swi_active),
.iFAULT_NUM(ex_alu02iic_swi_number[6:0]),
.iFAULT_FI0R(32'h0), //dummy
///To Exception Manager
.iEXCEPTION_LOCK(exception2cim_irq_lock),
.oEXCEPTION_ACTIVE(cim2exception_irq_req),
.oEXCEPTION_IRQ_NUM(cim2exception_irq_num),
.oEXCEPTION_IRQ_FI0R(),
.iEXCEPTION_IRQ_ACK(exception2cim_irq_ack)
);
/****************************************
Core Exception Manager
****************************************/
exception_manager EXCEPTION_MANAGER(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
/*********************************
Core
*********************************/
//Commit & Regist Info
.iCOREINFO_COMMIT_COUNTER(commit_counter),
.iCOREINFO_EXCEPTION_PROTECT(exception_protect),
//Scheduler1
.iCOREINFO_CURRENT_PC(current_execution_pc),
//Free
.oCOREINFO_FREE_INST_DISCARD(exception_inst_discard),
.oCOREINFO_FREE_EVENT(exception_event),
.oCOREINFO_FREE_COMMIT_TAG(exception_commit_tag),
.oCOREINFO_FREE_ADDR_SET(exception_addr_set),
.oCOREINFO_FREE_ADDR(exception_addr),
.oCOREINFO_FREE_RESTART(exception_restart),
.oCOREINFO_FREE_CURRENT_PC(exception_current_pc),
.oCOREINFO_FREE_SET_IRQ_MODE(exception2scheduler2_irq_reqister_set),
.oCOREINFO_FREE_CLR_IRQ_MODE(exception2scheduler2_irq_reqister_ret),
.oCOREINFO_FREE_NEW_SPR_VALID(exception2alu0_new_spr_valid),
.oCOREINFO_FREE_NEW_SPR(exception2alu0_new_spr),
//Order
.oCOREINFO_MCODE0_VALID(),
.oCOREINFO_MCODE0(),
.oCOREINFO_MCODE1_VALID(),
.oCOREINFO_MCODE1(),
.iCODEINFO_MCODE_LOCK(1'b0), //damy
//System Register
.iCOREINFO_SYSREG_IDTR(wire_sysreg_idtr),
.iCOREINFO_SYSREG_TISR(wire_sysreg_tisr),
.iCOREINFO_SYSREG_TIDR(wire_sysreg_tidr),
.iCOREINFO_SYSREG_PSR(wire_sysreg_psr),
.iCOREINFO_SYSREG_PPSR(wire_sysreg_ppsr),
.iCOREINFO_SYSREG_PPCR(wire_sysreg_ppcr),
.iCOREINFO_SYSREG_SPR(wire_sysreg_spr),
//Load Store
.oLDST_USE(exception2ldst_ldst_use),
.oLDST_REQ(exception2ldst_ldst_req),
.iLDST_BUSY(ldst2exception_ldst_busy),
.oLDST_ORDER(exception2ldst_ldst_order),
.oLDST_RW(exception2ldst_ldst_rw),
.oLDST_TID(exception2ldst_ldst_tid),
.oLDST_MMUMOD(exception2ldst_ldst_mmumod),
.oLDST_PDT(exception2ldst_ldst_pdt),
.oLDST_ADDR(exception2ldst_ldst_addr),
.oLDST_DATA(exception2ldst_ldst_data),
.iLDST_REQ(ldst2exception_ldst_req),
.iLDST_DATA(ldst2exception_ldst_data),
//GCI Interrupt Configlation Table
.oIO_IRQ_CONFIG_TABLE_REQ(oIO_IRQ_CONFIG_TABLE_REQ),
.oIO_IRQ_CONFIG_TABLE_ENTRY(oIO_IRQ_CONFIG_TABLE_ENTRY),
.oIO_IRQ_CONFIG_TABLE_FLAG_MASK(oIO_IRQ_CONFIG_TABLE_FLAG_MASK),
.oIO_IRQ_CONFIG_TABLE_FLAG_VALID(oIO_IRQ_CONFIG_TABLE_FLAG_VALID),
.oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL(oIO_IRQ_CONFIG_TABLE_FLAG_LEVEL),
//Core Interrupt Configlation Table
.oICT_REQ(exception2cim_ict_req),
.oICT_ENTRY(exception2cim_ict_entry),
.oICT_CONF_MASK(exception2cim_ict_conf_mask),
.oICT_CONF_VALID(exception2cim_ict_conf_valid),
.oICT_CONF_LEVEL(exception2cim_ict_conf_level),
/*********************************
Exeption Source
*********************************/
//ALU Branch
.iALU_BRANCH_REQ(jump_active),
.iALU_BRANCH_ADDR(jump_addr),
.iALU_BRANCH_COMMIT_TAG(ex_alu02scheduler1_branch_commit_tag),
//Int ret
.iALU_INTRET_REQ(ex_alu02exception_intr_active),
.iALU_INTRET_ADDR(ex_alu02exception_intr_addr),
.iALU_INTRET_COMMIT_TAG(ex_alu02scheduler1_branch_commit_tag),
//IDT Set
.iIDT_SET_REQ(ex_alu02exception_idts_active),
.iIDT_SET_R_ADDR(ex_alu02exception_idts_r_addr),
.iIDT_SET_COMMIT_TAG(ex_alu02exception_idts_commit_tag),
.iIDT_SET_IDTR(wire_sysreg_idtr),
//Hardware Task Switch
.iHW_TS_REQ(1'b0),
.iHW_TS_ADDR({32{1'b0}}),
.oHW_TS_BUSY(),
//IRQ Branch
.iIRQ_REQ(cim2exception_irq_req),
.iIRQ_NUM(cim2exception_irq_num),
.oIRQ_ACK(exception2cim_irq_ack),
.oIRQ_BUSY(exception2cim_irq_lock)
);
/****************************************
Stage : 0
Instruction Cache
****************************************/
l1_instruction_cache STAGE0_L1_INST(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Remove
.iREMOVE(exception_event),
.iCACHE_FLASH(1'b0),
/****************************************
Memory Port Memory
****************************************/
//Req
.oINST_REQ(oINST_REQ),
.iINST_LOCK(iINST_LOCK),
.oINST_MMUMOD(oINST_MMUMOD),
.oINST_ADDR(oINST_ADDR),
//Mem
.iINST_VALID(iINST_VALID),
.oINST_BUSY(oINST_BUSY),
.iINST_PAGEFAULT(iINST_PAGEFAULT),
.iINST_DATA(iINST_DATA),
.iINST_MMU_FLAGS(iINST_MMU_FLAGS),
/****************************************
Fetch Module
****************************************/
//From Fetch
.iNEXT_FETCH_REQ(fetch2icache_inst_req),
.oNEXT_FETCH_LOCK(icache2fetch_inst_busy),
.iNEXT_MMUMOD(2'h0),
.iNEXT_FETCH_ADDR(fetch2icache_inst_addr),
//To Fetch
.oNEXT_0_INST_VALID(icache2fetch_0_inst_valid),
.oNEXT_0_PAGEFAULT(/*icache2fetch_0_inst_pagefault*/),
.oNEXT_0_MMU_FLAGS(icache2fetch_0_inst_mmuflags),
.oNEXT_0_INST(icache2fetch_0_inst_inst),
.oNEXT_1_INST_VALID(icache2fetch_1_inst_valid),
.oNEXT_1_PAGEFAULT(/*icache2fetch_1_inst_pagefault*/),
.oNEXT_1_MMU_FLAGS(icache2fetch_1_inst_mmuflags),
.oNEXT_1_INST(icache2fetch_1_inst_inst),
.iNEXT_LOCK(fetch2icache_inst_busy)
);
/****************************************
Stage : 1
Instruction Fetch Unit
****************************************/
fetch STAGE1_FETCH(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Exception
.iEXCEPTION_INST_DISCARD(exception_inst_discard),
.iEXCEPTION_EVENT(exception_event),
.iEXCEPTION_ADDR_SET(exception_addr_set),
.iEXCEPTION_ADDR(exception_addr),
.iEXCEPTION_RESTART(exception_restart),
//Fetch Stop
.iFETCH_STOP_LOOPBUFFER_LIMIT(matching2fetch_loopbuffer_limit),
//Input Instruction
.iPREVIOUS_0_INST_VALID(icache2fetch_0_inst_valid),
.iPREVIOUS_0_MMU_FLAGS(icache2fetch_0_inst_mmuflags),
.iPREVIOUS_0_INST(icache2fetch_0_inst_inst),
.iPREVIOUS_1_INST_VALID(icache2fetch_1_inst_valid),
.iPREVIOUS_1_MMU_FLAGS(icache2fetch_1_inst_mmuflags),
.iPREVIOUS_1_INST(icache2fetch_1_inst_inst),
.oPREVIOUS_LOCK(fetch2icache_inst_busy),
//Req Instruction
.oPREVIOUS_FETCH_REQ(fetch2icache_inst_req),
.oPREVIOUS_FETCH_ADDR(fetch2icache_inst_addr),
.iPREVIOUS_FETCH_LOCK(icache2fetch_inst_busy),
//Next Unit
.oNEXT_0_INST_VALID(fetch2decoder_0_inst_valid),
.oNEXT_0_MMU_FLAGS(fetch2decoder_0_mmu_flags),
.oNEXT_0_INST(fetch2decoder_0_inst),
.oNEXT_1_INST_VALID(fetch2decoder_1_inst_valid),
.oNEXT_1_MMU_FLAGS(fetch2decoder_1_mmu_flags),
.oNEXT_1_INST(fetch2decoder_1_inst),
.oNEXT_PC(fetch2decoder_pc),
.iNEXT_LOCK(decoder2fetch_lock)
);
/****************************************
Stage : 2
Decoder Unit
****************************************/
assign decoder2matching_0_mmu_flags = 6'h0;
assign decoder2matching_1_mmu_flags = 6'h0;
decoder STAGE2_DECODER(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Free
.iRESET_SYNC(exception_event),
//Previous
/*
.iPREVIOUS_0_INST_VALID(fetch2decoder_0_inst_valid),
.iPREVIOUS_0_MMU_FLAGS(fetch2decoder_0_mmu_flags),
.iPREVIOUS_0_INST(fetch2decoder_0_inst),
.iPREVIOUS_1_INST_VALID(fetch2decoder_1_inst_valid),
.iPREVIOUS_1_MMU_FLAGS(fetch2decoder_1_mmu_flags),
.iPREVIOUS_1_INST(fetch2decoder_1_inst),
.iPREVIOUS_PC(fetch2decoder_pc),
.oPREVIOUS_LOCK(decoder2fetch_lock),
*/
.iPREVIOUS_COMMON_VALID(fetch2decoder_0_inst_valid),
.iPREVIOUS_0_INST_VALID(fetch2decoder_0_inst_valid),
.iPREVIOUS_0_PAGEFAULT(1'b0),
.iPREVIOUS_0_PAGING_ENA(1'b0),
.iPREVIOUS_0_KERNEL_ACCESS(1'b1),
.iPREVIOUS_0_BRANCH_PREDICT(1'b0),
.iPREVIOUS_0_BRANCH_PREDICT_ADDR(32'h0),
.iPREVIOUS_0_INST(fetch2decoder_0_inst),
.iPREVIOUS_1_INST_VALID(fetch2decoder_1_inst_valid),
.iPREVIOUS_1_PAGEFAULT(1'b0),
.iPREVIOUS_1_PAGING_ENA(1'b0),
.iPREVIOUS_1_KERNEL_ACCESS(1'b1),
.iPREVIOUS_1_BRANCH_PREDICT(1'b0),
.iPREVIOUS_1_BRANCH_PREDICT_ADDR(32'h0),
.iPREVIOUS_1_INST(fetch2decoder_1_inst),
.iPREVIOUS_PC(fetch2decoder_pc),
.oPREVIOUS_LOCK(decoder2fetch_lock),
//Next
.oNEXT_COMMON_VALID(decoder2matching_0_valid),
.oNEXT_0_VALID(),//(decoder2matching_0_valid),
//.oNEXT_0_MMU_FLAGS(decoder2matching_0_mmu_flags),
.oNEXT_0_SOURCE0_ACTIVE(decoder2matching_0_source0_active),
.oNEXT_0_SOURCE1_ACTIVE(decoder2matching_0_source1_active),
.oNEXT_0_SOURCE0_SYSREG(decoder2matching_0_source0_sysreg),
.oNEXT_0_SOURCE1_SYSREG(decoder2matching_0_source1_sysreg),
.oNEXT_0_SOURCE0_SYSREG_RENAME(decoder2matching_0_source0_sysreg_rename),
.oNEXT_0_SOURCE1_SYSREG_RENAME(decoder2matching_0_source1_sysreg_rename),
.oNEXT_0_ADV_ACTIVE(decoder2matching_0_adv_active), //++
.oNEXT_0_DESTINATION_SYSREG(decoder2matching_0_destination_sysreg),
.oNEXT_0_DEST_RENAME(decoder2matching_0_dest_rename),
.oNEXT_0_WRITEBACK(decoder2matching_0_writeback),
.oNEXT_0_FLAGS_WRITEBACK(decoder2mathsing_0_flags_writeback),
.oNEXT_0_FRONT_COMMIT_WAIT(decoder2matching_0_front_commit_wait),
.oNEXT_0_CMD(decoder2matching_0_cmd),
.oNEXT_0_CC_AFE(decoder2matching_0_cc_afe),
.oNEXT_0_SOURCE0(decoder2matching_0_source0),
.oNEXT_0_SOURCE1(decoder2matching_0_source1),
.oNEXT_0_ADV_DATA(decoder2matching_0_adv_data), //++
.oNEXT_0_SOURCE0_FLAGS(decoder2matching_0_source0_flags),
.oNEXT_0_SOURCE1_IMM(decoder2matching_0_source1_imm),
.oNEXT_0_DESTINATION(decoder2matching_0_destination),
.oNEXT_0_EX_SYS_REG(decoder2matching_0_sys_reg),
.oNEXT_0_EX_SYS_LDST(decoder2matching_0_sys_ldst),
.oNEXT_0_EX_LOGIC(decoder2matching_0_logic),
.oNEXT_0_EX_SHIFT(decoder2matching_0_shift),
.oNEXT_0_EX_ADDER(decoder2matching_0_adder),
.oNEXT_0_EX_MUL(decoder2matching_0_mul),
.oNEXT_0_EX_SDIV(decoder2matching_0_sdiv),
.oNEXT_0_EX_UDIV(decoder2matching_0_udiv),
.oNEXT_0_EX_LDST(decoder2matching_0_ldst),
.oNEXT_0_EX_BRANCH(decoder2matching_0_branch),
.oNEXT_1_VALID(decoder2matching_1_valid),
//.oNEXT_1_MMU_FLAGS(decoder2matching_1_mmu_flags),
.oNEXT_1_SOURCE0_ACTIVE(decoder2matching_1_source0_active),
.oNEXT_1_SOURCE1_ACTIVE(decoder2matching_1_source1_active),
.oNEXT_1_SOURCE0_SYSREG(decoder2matching_1_source0_sysreg),
.oNEXT_1_SOURCE1_SYSREG(decoder2matching_1_source1_sysreg),
.oNEXT_1_SOURCE0_SYSREG_RENAME(decoder2matching_1_source0_sysreg_rename),
.oNEXT_1_SOURCE1_SYSREG_RENAME(decoder2matching_1_source1_sysreg_rename),
.oNEXT_1_ADV_ACTIVE(decoder2matching_1_adv_active), //++
.oNEXT_1_DESTINATION_SYSREG(decoder2matching_1_destination_sysreg),
.oNEXT_1_DEST_RENAME(decoder2matching_1_dest_rename),
.oNEXT_1_WRITEBACK(decoder2matching_1_writeback),
.oNEXT_1_FLAGS_WRITEBACK(decoder2mathsing_1_flags_writeback),
.oNEXT_1_FRONT_COMMIT_WAIT(decoder2matching_1_front_commit_wait),
.oNEXT_1_CMD(decoder2matching_1_cmd),
.oNEXT_1_CC_AFE(decoder2matching_1_cc_afe),
.oNEXT_1_SOURCE0(decoder2matching_1_source0),
.oNEXT_1_SOURCE1(decoder2matching_1_source1),
.oNEXT_1_ADV_DATA(decoder2matching_1_adv_data), //++
.oNEXT_1_SOURCE0_FLAGS(decoder2matching_1_source0_flags),
.oNEXT_1_SOURCE1_IMM(decoder2matching_1_source1_imm),
.oNEXT_1_DESTINATION(decoder2matching_1_destination),
.oNEXT_1_EX_SYS_REG(decoder2matching_1_sys_reg),
.oNEXT_1_EX_SYS_LDST(decoder2matching_1_sys_ldst),
.oNEXT_1_EX_LOGIC(decoder2matching_1_logic),
.oNEXT_1_EX_SHIFT(decoder2matching_1_shift),
.oNEXT_1_EX_ADDER(decoder2matching_1_adder),
.oNEXT_1_EX_MUL(decoder2matching_1_mul),
.oNEXT_1_EX_SDIV(decoder2matching_1_sdiv),
.oNEXT_1_EX_UDIV(decoder2matching_1_udiv),
.oNEXT_1_EX_LDST(decoder2matching_1_ldst),
.oNEXT_1_EX_BRANCH(decoder2matching_1_branch),
.oNEXT_PC(decoder2matching_pc),
.iNEXT_LOCK(matching2decoder_lock)
);
/****************************************
Stage : 3
Matching Unit
****************************************/
matching SATGE3_MATCHING(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Free
.iFREE_DEFAULT(exception_event),
.iFREE_RESTART(exception_restart),
//Commit OFFSET
.iCOMMIT_OFFSET(commit_offset),
//Instruction Fetch Stop
.oLOOPBUFFER_LIMIT(matching2fetch_loopbuffer_limit),
.iOTHER_INFO_RENAME_0_VALID(stage_info_renaming_0_valid),
.iOTHER_INFO_RENAME_1_VALID(stage_info_renaming_1_valid),
.iOTHER_INFO_SCHEDULER1_0_VALID(stage_info_scheduler1_0_valid),
.iOTHER_INFO_SCHEDULER1_1_VALID(stage_info_scheduler1_1_valid),
.iOTHER_INFO_SCHEDULER1_REGIST_POINTER(stage_info_scheduler1_regist_pointer),
.iOTHER_INFO_SCHEDULER1_COMMIT_POINTER(stage_info_scheduler1_commit_pointer),
//Prev
.iPREVIOUS_0_VALID(decoder2matching_0_valid),
.iPREVIOUS_0_MMU_FLAGS(decoder2matching_0_mmu_flags),
.iPREVIOUS_0_SOURCE0_ACTIVE(decoder2matching_0_source0_active),
.iPREVIOUS_0_SOURCE1_ACTIVE(decoder2matching_0_source1_active),
.iPREVIOUS_0_SOURCE0_SYSREG(decoder2matching_0_source0_sysreg),
.iPREVIOUS_0_SOURCE1_SYSREG(decoder2matching_0_source1_sysreg),
.iPREVIOUS_0_SOURCE0_SYSREG_RENAME(decoder2matching_0_source0_sysreg_rename),
.iPREVIOUS_0_SOURCE1_SYSREG_RENAME(decoder2matching_0_source1_sysreg_rename),
.iPREVIOUS_0_ADV_ACTIVE(decoder2matching_0_adv_active), //++
.iPREVIOUS_0_DESTINATION_SYSREG(decoder2matching_0_destination_sysreg),
.iPREVIOUS_0_DEST_RENAME(decoder2matching_0_dest_rename),
.iPREVIOUS_0_WRITEBACK(decoder2matching_0_writeback),
.iPREVIOUS_0_FLAGS_WRITEBACK(decoder2mathsing_0_flags_writeback),
.iPREVIOUS_0_FRONT_COMMIT_WAIT(decoder2matching_0_front_commit_wait),
.iPREVIOUS_0_CMD(decoder2matching_0_cmd),
.iPREVIOUS_0_CC_AFE(decoder2matching_0_cc_afe),
.iPREVIOUS_0_SOURCE0(decoder2matching_0_source0),
.iPREVIOUS_0_SOURCE1(decoder2matching_0_source1),
.iPREVIOUS_0_ADV_DATA(decoder2matching_0_adv_data), //++
.iPREVIOUS_0_SOURCE0_FLAGS(decoder2matching_0_source0_flags),
.iPREVIOUS_0_SOURCE1_IMM(decoder2matching_0_source1_imm),
.iPREVIOUS_0_DESTINATION(decoder2matching_0_destination),
.iPREVIOUS_0_EX_SYS_ADDER(decoder2matching_0_sys_reg),
.iPREVIOUS_0_EX_SYS_LDST(decoder2matching_0_sys_ldst),
.iPREVIOUS_0_EX_LOGIC(decoder2matching_0_logic),
.iPREVIOUS_0_EX_SHIFT(decoder2matching_0_shift),
.iPREVIOUS_0_EX_ADDER(decoder2matching_0_adder),
.iPREVIOUS_0_EX_MUL(decoder2matching_0_mul),
.iPREVIOUS_0_EX_SDIV(decoder2matching_0_sdiv),
.iPREVIOUS_0_EX_UDIV(decoder2matching_0_udiv),
.iPREVIOUS_0_EX_LDST(decoder2matching_0_ldst),
.iPREVIOUS_0_EX_BRANCH(decoder2matching_0_branch),
.iPREVIOUS_1_VALID(decoder2matching_1_valid),
.iPREVIOUS_1_MMU_FLAGS(decoder2matching_1_mmu_flags),
.iPREVIOUS_1_SOURCE0_ACTIVE(decoder2matching_1_source0_active),
.iPREVIOUS_1_SOURCE1_ACTIVE(decoder2matching_1_source1_active),
.iPREVIOUS_1_SOURCE0_SYSREG(decoder2matching_1_source0_sysreg),
.iPREVIOUS_1_SOURCE1_SYSREG(decoder2matching_1_source1_sysreg),
.iPREVIOUS_1_SOURCE0_SYSREG_RENAME(decoder2matching_1_source0_sysreg_rename),
.iPREVIOUS_1_SOURCE1_SYSREG_RENAME(decoder2matching_1_source1_sysreg_rename),
.iPREVIOUS_1_ADV_ACTIVE(decoder2matching_1_adv_active), //++
.iPREVIOUS_1_DESTINATION_SYSREG(decoder2matching_1_destination_sysreg),
.iPREVIOUS_1_DEST_RENAME(decoder2matching_1_dest_rename),
.iPREVIOUS_1_WRITEBACK(decoder2matching_1_writeback),
.iPREVIOUS_1_FLAGS_WRITEBACK(decoder2mathsing_1_flags_writeback),
.iPREVIOUS_1_FRONT_COMMIT_WAIT(decoder2matching_1_front_commit_wait),
.iPREVIOUS_1_CMD(decoder2matching_1_cmd),
.iPREVIOUS_1_CC_AFE(decoder2matching_1_cc_afe),
.iPREVIOUS_1_SOURCE0(decoder2matching_1_source0),
.iPREVIOUS_1_SOURCE1(decoder2matching_1_source1),
.iPREVIOUS_1_ADV_DATA(decoder2matching_1_adv_data), //++
.iPREVIOUS_1_SOURCE0_FLAGS(decoder2matching_1_source0_flags),
.iPREVIOUS_1_SOURCE1_IMM(decoder2matching_1_source1_imm),
.iPREVIOUS_1_DESTINATION(decoder2matching_1_destination),
.iPREVIOUS_1_EX_SYS_ADDER(decoder2matching_1_sys_reg),
.iPREVIOUS_1_EX_SYS_LDST(decoder2matching_1_sys_ldst),
.iPREVIOUS_1_EX_LOGIC(decoder2matching_1_logic),
.iPREVIOUS_1_EX_SHIFT(decoder2matching_1_shift),
.iPREVIOUS_1_EX_ADDER(decoder2matching_1_adder),
.iPREVIOUS_1_EX_MUL(decoder2matching_1_mul),
.iPREVIOUS_1_EX_SDIV(decoder2matching_1_sdiv),
.iPREVIOUS_1_EX_UDIV(decoder2matching_1_udiv),
.iPREVIOUS_1_EX_LDST(decoder2matching_1_ldst),
.iPREVIOUS_1_EX_BRANCH(decoder2matching_1_branch),
.iPREVIOUS_PC(decoder2matching_pc),
.oPREVIOUS_LOCK(matching2decoder_lock),
//Next
.oNEXT_0_VALID(matching2renaming_0_valid),
.oNEXT_0_SOURCE0_ACTIVE(matching2renaming_0_source0_active),
.oNEXT_0_SOURCE1_ACTIVE(matching2renaming_0_source1_active),
.oNEXT_0_SOURCE0_SYSREG(matching2renaming_0_source0_sysreg),
.oNEXT_0_SOURCE1_SYSREG(matching2renaming_0_source1_sysreg),
.oNEXT_0_SOURCE0_SYSREG_RENAME(matching2renaming_0_source0_sysreg_rename),
.oNEXT_0_SOURCE1_SYSREG_RENAME(matching2renaming_0_source1_sysreg_rename),
.oNEXT_0_ADV_ACTIVE(matching2renaming_0_adv_active), //++
.oNEXT_0_DESTINATION_SYSREG(matching2renaming_0_destination_sysreg),
.oNEXT_0_DEST_RENAME(matching2renaming_0_dest_rename),
.oNEXT_0_WRITEBACK(matching2renaming_0_writeback),
.oNEXT_0_FLAGS_WRITEBACK(matching2renaming_0_flags_writeback),
.oNEXT_0_CMD(matching2renaming_0_cmd),
.oNEXT_0_CC_AFE(matching2renaming_0_cc_afe),
.oNEXT_0_SOURCE0(matching2renaming_0_source0),
.oNEXT_0_SOURCE1(matching2renaming_0_source1),
.oNEXT_0_ADV_DATA(matching2renaming_0_adv_data), //++
.oNEXT_0_SOURCE0_FLAGS(matching2renaming_0_source0_flags),
.oNEXT_0_SOURCE1_IMM(matching2renaming_0_source1_imm),
.oNEXT_0_DESTINATION(matching2renaming_0_destination),
.oNEXT_0_EX_SYS_ADDER(matching2renaming_0_sys_adder),
.oNEXT_0_EX_SYS_LDST(matching2renaming_0_sys_ldst),
.oNEXT_0_EX_LOGIC(matching2renaming_0_logic),
.oNEXT_0_EX_SHIFT(matching2renaming_0_shift),
.oNEXT_0_EX_ADDER(matching2renaming_0_adder),
.oNEXT_0_EX_MUL(matching2renaming_0_mul),
.oNEXT_0_EX_SDIV(matching2renaming_0_sdiv),
.oNEXT_0_EX_UDIV(matching2renaming_0_udiv),
.oNEXT_0_EX_LDST(matching2renaming_0_ldst),
.oNEXT_0_EX_BRANCH(matching2renaming_0_branch),
.oNEXT_1_VALID(matching2renaming_1_valid),
.oNEXT_1_SOURCE0_ACTIVE(matching2renaming_1_source0_active),
.oNEXT_1_SOURCE1_ACTIVE(matching2renaming_1_source1_active),
.oNEXT_1_SOURCE0_SYSREG(matching2renaming_1_source0_sysreg),
.oNEXT_1_SOURCE1_SYSREG(matching2renaming_1_source1_sysreg),
.oNEXT_1_SOURCE0_SYSREG_RENAME(matching2renaming_1_source0_sysreg_rename),
.oNEXT_1_SOURCE1_SYSREG_RENAME(matching2renaming_1_source1_sysreg_rename),
.oNEXT_1_ADV_ACTIVE(matching2renaming_1_adv_active), //++
.oNEXT_1_DESTINATION_SYSREG(matching2renaming_1_destination_sysreg),
.oNEXT_1_DEST_RENAME(matching2renaming_1_dest_rename),
.oNEXT_1_WRITEBACK(matching2renaming_1_writeback),
.oNEXT_1_FLAGS_WRITEBACK(matching2renaming_1_flags_writeback),
.oNEXT_1_CMD(matching2renaming_1_cmd),
.oNEXT_1_CC_AFE(matching2renaming_1_cc_afe),
.oNEXT_1_SOURCE0(matching2renaming_1_source0),
.oNEXT_1_SOURCE1(matching2renaming_1_source1),
.oNEXT_1_ADV_DATA(matching2renaming_1_adv_data), //++
.oNEXT_1_SOURCE0_FLAGS(matching2renaming_1_source0_flags),
.oNEXT_1_SOURCE1_IMM(matching2renaming_1_source1_imm),
.oNEXT_1_DESTINATION(matching2renaming_1_destination),
.oNEXT_1_EX_SYS_ADDER(matching2renaming_1_sys_adder),
.oNEXT_1_EX_SYS_LDST(matching2renaming_1_sys_ldst),
.oNEXT_1_EX_LOGIC(matching2renaming_1_logic),
.oNEXT_1_EX_SHIFT(matching2renaming_1_shift),
.oNEXT_1_EX_ADDER(matching2renaming_1_adder),
.oNEXT_1_EX_MUL(matching2renaming_1_mul),
.oNEXT_1_EX_SDIV(matching2renaming_1_sdiv),
.oNEXT_1_EX_UDIV(matching2renaming_1_udiv),
.oNEXT_1_EX_LDST(matching2renaming_1_ldst),
.oNEXT_1_EX_BRANCH(matching2renaming_1_branch),
.oNEXT_PC(matching2renaming_pc),
.iNEXT_LOCK(renaming2matching_lock)
);
/****************************************
Stage : 4
Rename Unit
****************************************/
rename SATGE4_RENAME(
.iCLOCK(iCLOCK), .inRESET(inRESET),
.iFREE_DEFAULT(exception_event), .iFREE_RESTART(exception_restart),
.iROLLBACK_UPDATE_CANDIDATE0_VALID(scheduler12renaming_rollback_update_info0_valid),
.iROLLBACK_UPDATE_CANDIDATE0_LREGNAME(scheduler12renaming_rollback_update_info0_lregname),
.iROLLBACK_UPDATE_CANDIDATE0_PREGNAME(scheduler12renaming_rollback_update_info0_pregname),
.iROLLBACK_UPDATE_CANDIDATE0_SYSREG(scheduler12renaming_rollback_update_info0_sysreg),
.iROLLBACK_UPDATE_CANDIDATE1_VALID(scheduler12renaming_rollback_update_info1_valid),
.iROLLBACK_UPDATE_CANDIDATE1_LREGNAME(scheduler12renaming_rollback_update_info1_lregname),
.iROLLBACK_UPDATE_CANDIDATE1_PREGNAME(scheduler12renaming_rollback_update_info1_pregname),
.iROLLBACK_UPDATE_CANDIDATE1_SYSREG(scheduler12renaming_rollback_update_info1_sysreg),
.iROLLBACK_UPDATE_CANDIDATE2_VALID(scheduler12renaming_rollback_update_info2_valid),
.iROLLBACK_UPDATE_CANDIDATE2_LREGNAME(scheduler12renaming_rollback_update_info2_lregname),
.iROLLBACK_UPDATE_CANDIDATE2_PREGNAME(scheduler12renaming_rollback_update_info2_pregname),
.iROLLBACK_UPDATE_CANDIDATE2_SYSREG(scheduler12renaming_rollback_update_info2_sysreg),
.iROLLBACK_UPDATE_CANDIDATE3_VALID(scheduler12renaming_rollback_update_info3_valid),
.iROLLBACK_UPDATE_CANDIDATE3_LREGNAME(scheduler12renaming_rollback_update_info3_lregname),
.iROLLBACK_UPDATE_CANDIDATE3_PREGNAME(scheduler12renaming_rollback_update_info3_pregname),
.iROLLBACK_UPDATE_CANDIDATE3_SYSREG(scheduler12renaming_rollback_update_info3_sysreg),
.iFLAGR_RENAME_ROLLBACK_UPDATE_INFO0_VALID(scheduler12renaming_flags_rollback_update_info0_valid),
.iFLAGR_RENAME_ROLLBACK_UPDATE_INFO0_PREGNAME(scheduler12renaming_flags_rollback_update_info0_pregname),
.iFLAGR_RENAME_ROLLBACK_UPDATE_INFO1_VALID(scheduler12renaming_flags_rollback_update_info1_valid),
.iFLAGR_RENAME_ROLLBACK_UPDATE_INFO1_PREGNAME(scheduler12renaming_flags_rollback_update_info1_pregname),
.iFLAGR_RENAME_ROLLBACK_UPDATE_INFO2_VALID(scheduler12renaming_flags_rollback_update_info2_valid),
.iFLAGR_RENAME_ROLLBACK_UPDATE_INFO2_PREGNAME(scheduler12renaming_flags_rollback_update_info2_pregname),
.iFLAGR_RENAME_ROLLBACK_UPDATE_INFO3_VALID(scheduler12renaming_flags_rollback_update_info3_valid),
.iFLAGR_RENAME_ROLLBACK_UPDATE_INFO3_PREGNAME(scheduler12renaming_flags_rollback_update_info3_pregname),
.oSTAGE_INFO_0_VALID(stage_info_renaming_0_valid),
.oSTAGE_INFO_1_VALID(stage_info_renaming_1_valid),
.iPREVIOUS_0_VALID(matching2renaming_0_valid),
.iPREVIOUS_0_SOURCE0_ACTIVE(matching2renaming_0_source0_active),
.iPREVIOUS_0_SOURCE1_ACTIVE(matching2renaming_0_source1_active),
.iPREVIOUS_0_SOURCE0_SYSREG(matching2renaming_0_source0_sysreg),
.iPREVIOUS_0_SOURCE1_SYSREG(matching2renaming_0_source1_sysreg),
.iPREVIOUS_0_SOURCE0_SYSREG_RENAME(matching2renaming_0_source0_sysreg_rename),
.iPREVIOUS_0_SOURCE1_SYSREG_RENAME(matching2renaming_0_source1_sysreg_rename),
.iPREVIOUS_0_ADV_ACTIVE(matching2renaming_0_adv_active),
.iPREVIOUS_0_DESTINATION_SYSREG(matching2renaming_0_destination_sysreg),
.iPREVIOUS_0_DEST_RENAME(matching2renaming_0_dest_rename),
.iPREVIOUS_0_WRITEBACK(matching2renaming_0_writeback),
.iPREVIOUS_0_FLAGS_WRITEBACK(matching2renaming_0_flags_writeback),
.iPREVIOUS_0_CMD(matching2renaming_0_cmd),
.iPREVIOUS_0_CC_AFE(matching2renaming_0_cc_afe),
.iPREVIOUS_0_SOURCE1(matching2renaming_0_source1),
.iPREVIOUS_0_SOURCE0(matching2renaming_0_source0),
.iPREVIOUS_0_ADV_DATA(matching2renaming_0_adv_data),
.iPREVIOUS_0_SOURCE0_FLAGS(matching2renaming_0_source0_flags),
.iPREVIOUS_0_SOURCE1_IMM(matching2renaming_0_source1_imm),
.iPREVIOUS_0_DESTINATION(matching2renaming_0_destination),
.iPREVIOUS_0_EX_SYS_ADDER(matching2renaming_0_sys_adder),
.iPREVIOUS_0_EX_SYS_LDST(matching2renaming_0_sys_ldst),
.iPREVIOUS_0_EX_LOGIC(matching2renaming_0_logic),
.iPREVIOUS_0_EX_SHIFT(matching2renaming_0_shift),
.iPREVIOUS_0_EX_ADDER(matching2renaming_0_adder),
.iPREVIOUS_0_EX_MUL(matching2renaming_0_mul),
.iPREVIOUS_0_EX_SDIV(matching2renaming_0_sdiv),
.iPREVIOUS_0_EX_UDIV(matching2renaming_0_udiv),
.iPREVIOUS_0_EX_LDST(matching2renaming_0_ldst),
.iPREVIOUS_0_EX_BRANCH(matching2renaming_0_branch),
.iPREVIOUS_1_VALID(matching2renaming_1_valid),
.iPREVIOUS_1_SOURCE0_ACTIVE(matching2renaming_1_source0_active),
.iPREVIOUS_1_SOURCE1_ACTIVE(matching2renaming_1_source1_active),
.iPREVIOUS_1_SOURCE0_SYSREG(matching2renaming_1_source0_sysreg),
.iPREVIOUS_1_SOURCE1_SYSREG(matching2renaming_1_source1_sysreg),
.iPREVIOUS_1_SOURCE0_SYSREG_RENAME(matching2renaming_1_source0_sysreg_rename),
.iPREVIOUS_1_SOURCE1_SYSREG_RENAME(matching2renaming_1_source1_sysreg_rename),
.iPREVIOUS_1_ADV_ACTIVE(matching2renaming_1_adv_active),
.iPREVIOUS_1_DESTINATION_SYSREG(matching2renaming_1_destination_sysreg),
.iPREVIOUS_1_DEST_RENAME(matching2renaming_1_dest_rename),
.iPREVIOUS_1_WRITEBACK(matching2renaming_1_writeback),
.iPREVIOUS_1_FLAGS_WRITEBACK(matching2renaming_1_flags_writeback),
.iPREVIOUS_1_CMD(matching2renaming_1_cmd),
.iPREVIOUS_1_CC_AFE(matching2renaming_1_cc_afe),
.iPREVIOUS_1_SOURCE0(matching2renaming_1_source0),
.iPREVIOUS_1_SOURCE1(matching2renaming_1_source1),
.iPREVIOUS_1_ADV_DATA(matching2renaming_1_adv_data),
.iPREVIOUS_1_SOURCE0_FLAGS(matching2renaming_1_source0_flags),
.iPREVIOUS_1_SOURCE1_IMM(matching2renaming_1_source1_imm),
.iPREVIOUS_1_DESTINATION(matching2renaming_1_destination),
.iPREVIOUS_1_EX_SYS_ADDER(matching2renaming_1_sys_adder),
.iPREVIOUS_1_EX_SYS_LDST(matching2renaming_1_sys_ldst),
.iPREVIOUS_1_EX_LOGIC(matching2renaming_1_logic),
.iPREVIOUS_1_EX_SHIFT(matching2renaming_1_shift),
.iPREVIOUS_1_EX_ADDER(matching2renaming_1_adder),
.iPREVIOUS_1_EX_MUL(matching2renaming_1_mul),
.iPREVIOUS_1_EX_SDIV(matching2renaming_1_sdiv),
.iPREVIOUS_1_EX_UDIV(matching2renaming_1_udiv),
.iPREVIOUS_1_EX_LDST(matching2renaming_1_ldst),
.iPREVIOUS_1_EX_BRANCH(matching2renaming_1_branch),
.iPREVIOUS_PC(matching2renaming_pc),
.oPREVIOUS_LOCK(renaming2matching_lock),
//Register
.oFLAG_REGISTER_0_RD(freereg_renaming2scheduler1_flag0_rd),
.iFLAG_REGISTER_0_NUM(freereg_renaming2scheduler1_flag0_num),
.iFLAG_REGISTER_0_EMPTY(freereg_renaming2scheduler1_flag0_empty),
.oFLAG_REGISTER_1_RD(freereg_renaming2scheduler1_flag1_rd),
.iFLAG_REGISTER_1_NUM(freereg_renaming2scheduler1_flag1_num),
.iFLAG_REGISTER_1_EMPTY(freereg_renaming2scheduler1_flag1_empty),
.oOTHER_REGISTER_0_RD(freereg_renaming2scheduler1_other0_rd),
.iOTHER_REGISTER_0_NUM(freereg_renaming2scheduler1_other0_num),
.iOTHER_REGISTER_0_EMPTY(freereg_renaming2scheduler1_other0_empty),
.oOTHER_REGISTER_1_RD(freereg_renaming2scheduler1_other1_rd),
.iOTHER_REGISTER_1_NUM(freereg_renaming2scheduler1_other1_num),
.iOTHER_REGISTER_1_EMPTY(freereg_renaming2scheduler1_other1_empty),
.oNEXT_0_VALID(renaming2scheduler1_0_valid),
.oNEXT_0_SOURCE0_ACTIVE(renaming2scheduler1_0_source0_active),
.oNEXT_0_SOURCE1_ACTIVE(renaming2scheduler1_0_source1_active),
.oNEXT_0_SOURCE0_SYSREG(renaming2scheduler1_0_source0_sysreg),
.oNEXT_0_SOURCE1_SYSREG(renaming2scheduler1_0_source1_sysreg),
.oNEXT_0_SOURCE0_SYSREG_RENAME(renaming2scheduler1_0_source0_sysreg_rename),
.oNEXT_0_SOURCE1_SYSREG_RENAME(renaming2scheduler1_0_source1_sysreg_rename),
.oNEXT_0_ADV_ACTIVE(renaming2scheduler1_0_adv_active), //++
.oNEXT_0_DESTINATION_SYSREG(renaming2scheduler1_0_destination_sysreg),
.oNEXT_0_WRITEBACK(renaming2scheduler1_0_data_writeback),
.oNEXT_0_FLAGS_WRITEBACK(renaming2scheduler1_0_flags_writeback),
.oNEXT_0_CMD(renaming2scheduler1_0_cmd),
.oNEXT_0_CC_AFE(renaming2scheduler1_0_cc_afe),
.oNEXT_0_FLAGS_REGNAME(renaming2scheduler1_0_flags_regname),
.oNEXT_0_DESTINATION_REGNAME(renaming2scheduler1_0_destination_regname),
.oNEXT_0_LOGIC_DESTINATION(renaming2scheduler1_0_logic_destination),
.oNEXT_0_SOURCE0(renaming2scheduler1_0_source0),
.oNEXT_0_SOURCE1(renaming2scheduler1_0_source1),
.oNEXT_0_ADV_DATA(renaming2scheduler1_0_adv_data), //++
.oNEXT_0_SOURCE0_FLAGS(renaming2scheduler1_0_source0_flags),
.oNEXT_0_SOURCE1_IMM(renaming2scheduler1_0_source1_imm),
.oNEXT_0_EX_SYS_ADDER(renaming2scheduler1_0_sys_adder),
.oNEXT_0_EX_SYS_LDST(renaming2scheduler1_0_sys_ldst),
.oNEXT_0_EX_LOGIC(renaming2scheduler1_0_logic),
.oNEXT_0_EX_SHIFT(renaming2scheduler1_0_shift),
.oNEXT_0_EX_ADDER(renaming2scheduler1_0_adder),
.oNEXT_0_EX_MUL(renaming2scheduler1_0_mul),
.oNEXT_0_EX_SDIV(renaming2scheduler1_0_sdiv),
.oNEXT_0_EX_UDIV(renaming2scheduler1_0_udiv),
.oNEXT_0_EX_LDST(renaming2scheduler1_0_ldst),
.oNEXT_0_EX_BRANCH(renaming2scheduler1_0_branch),
.oNEXT_1_VALID(renaming2scheduler1_1_valid),
.oNEXT_1_SOURCE0_ACTIVE(renaming2scheduler1_1_source0_active),
.oNEXT_1_SOURCE1_ACTIVE(renaming2scheduler1_1_source1_active),
.oNEXT_1_SOURCE0_SYSREG(renaming2scheduler1_1_source0_sysreg),
.oNEXT_1_SOURCE1_SYSREG(renaming2scheduler1_1_source1_sysreg),
.oNEXT_1_SOURCE0_SYSREG_RENAME(renaming2scheduler1_1_source0_sysreg_rename),
.oNEXT_1_SOURCE1_SYSREG_RENAME(renaming2scheduler1_1_source1_sysreg_rename),
.oNEXT_1_ADV_ACTIVE(renaming2scheduler1_1_adv_active), //++
.oNEXT_1_DESTINATION_SYSREG(renaming2scheduler1_1_destination_sysreg),
.oNEXT_1_WRITEBACK(renaming2scheduler1_1_data_writeback),
.oNEXT_1_FLAGS_WRITEBACK(renaming2scheduler1_1_flags_writeback),
.oNEXT_1_CMD(renaming2scheduler1_1_cmd),
.oNEXT_1_CC_AFE(renaming2scheduler1_1_cc_afe),
.oNEXT_1_FLAGS_REGNAME(renaming2scheduler1_1_flags_regname),
.oNEXT_1_DESTINATION_REGNAME(renaming2scheduler1_1_destination_regname),
.oNEXT_1_LOGIC_DESTINATION(renaming2scheduler1_1_logic_destination),
.oNEXT_1_SOURCE0(renaming2scheduler1_1_source0),
.oNEXT_1_SOURCE1(renaming2scheduler1_1_source1),
.oNEXT_1_ADV_DATA(renaming2scheduler1_1_adv_data), //++
.oNEXT_1_SOURCE0_FLAGS(renaming2scheduler1_1_source0_flags),
.oNEXT_1_SOURCE1_IMM(renaming2scheduler1_1_source_imm),
.oNEXT_1_EX_SYS_ADDER(renaming2scheduler1_1_sys_adder),
.oNEXT_1_EX_SYS_LDST(renaming2scheduler1_1_sys_ldst),
.oNEXT_1_EX_LOGIC(renaming2scheduler1_1_logic),
.oNEXT_1_EX_SHIFT(renaming2scheduler1_1_shift),
.oNEXT_1_EX_ADDER(renaming2scheduler1_1_adder),
.oNEXT_1_EX_MUL(renaming2scheduler1_1_mul),
.oNEXT_1_EX_SDIV(renaming2scheduler1_1_sdiv),
.oNEXT_1_EX_UDIV(renaming2scheduler1_1_udiv),
.oNEXT_1_EX_LDST(renaming2scheduler1_1_ldst),
.oNEXT_1_EX_BRANCH(renaming2scheduler1_1_branch),
.oNEXT_PC(renaming2scheduler1_pc), .iNEXT_LOCK(scheduler12renaming_lock)
);
/****************************************
Stage : 5
Scheduler1 Unit
****************************************/
scheduler1 SATGE5_SCHEDULER1(
.iCLOCK(iCLOCK), .inRESET(inRESET),
//IRQ
.iIRQ_VALID(1'b0),
//FREE
.iEXCEPTION_EVENT(exception_event),
.iEXCEPTION_COMMIT_TAG(exception_commit_tag),
.iEXCEPTION_RESTART(exception_restart),
.oFREE_CURRENT_PC(current_execution_pc),
.oFREE_REGISTER(free_register),
//Commit
.oINFO_COMMIT_COUNTER(commit_counter),
.oINFO_EXCEPTION_PROTECT(exception_protect),
//Rollback
.oRENAME_ROLLBACK_UPDATE_INFO0_VALID(scheduler12renaming_rollback_update_info0_valid),
.oRENAME_ROLLBACK_UPDATE_INFO0_LREGNAME(scheduler12renaming_rollback_update_info0_lregname),
.oRENAME_ROLLBACK_UPDATE_INFO0_PREGNAME(scheduler12renaming_rollback_update_info0_pregname),
.oRENAME_ROLLBACK_UPDATE_INFO0_SYSREG(scheduler12renaming_rollback_update_info0_sysreg),
.oRENAME_ROLLBACK_UPDATE_INFO1_VALID(scheduler12renaming_rollback_update_info1_valid),
.oRENAME_ROLLBACK_UPDATE_INFO1_LREGNAME(scheduler12renaming_rollback_update_info1_lregname),
.oRENAME_ROLLBACK_UPDATE_INFO1_PREGNAME(scheduler12renaming_rollback_update_info1_pregname),
.oRENAME_ROLLBACK_UPDATE_INFO1_SYSREG(scheduler12renaming_rollback_update_info1_sysreg),
.oRENAME_ROLLBACK_UPDATE_INFO2_VALID(scheduler12renaming_rollback_update_info2_valid),
.oRENAME_ROLLBACK_UPDATE_INFO2_LREGNAME(scheduler12renaming_rollback_update_info2_lregname),
.oRENAME_ROLLBACK_UPDATE_INFO2_PREGNAME(scheduler12renaming_rollback_update_info2_pregname),
.oRENAME_ROLLBACK_UPDATE_INFO2_SYSREG(scheduler12renaming_rollback_update_info2_sysreg),
.oRENAME_ROLLBACK_UPDATE_INFO3_VALID(scheduler12renaming_rollback_update_info3_valid),
.oRENAME_ROLLBACK_UPDATE_INFO3_LREGNAME(scheduler12renaming_rollback_update_info3_lregname),
.oRENAME_ROLLBACK_UPDATE_INFO3_PREGNAME(scheduler12renaming_rollback_update_info3_pregname),
.oRENAME_ROLLBACK_UPDATE_INFO3_SYSREG(scheduler12renaming_rollback_update_info3_sysreg),
.oFLAGR_RENAME_ROLLBACK_UPDATE_INFO0_VALID(scheduler12renaming_flags_rollback_update_info0_valid),
.oFLAGR_RENAME_ROLLBACK_UPDATE_INFO0_PREGNAME(scheduler12renaming_flags_rollback_update_info0_pregname),
.oFLAGR_RENAME_ROLLBACK_UPDATE_INFO1_VALID(scheduler12renaming_flags_rollback_update_info1_valid),
.oFLAGR_RENAME_ROLLBACK_UPDATE_INFO1_PREGNAME(scheduler12renaming_flags_rollback_update_info1_pregname),
.oFLAGR_RENAME_ROLLBACK_UPDATE_INFO2_VALID(scheduler12renaming_flags_rollback_update_info2_valid),
.oFLAGR_RENAME_ROLLBACK_UPDATE_INFO2_PREGNAME(scheduler12renaming_flags_rollback_update_info2_pregname),
.oFLAGR_RENAME_ROLLBACK_UPDATE_INFO3_VALID(scheduler12renaming_flags_rollback_update_info3_valid),
.oFLAGR_RENAME_ROLLBACK_UPDATE_INFO3_PREGNAME(scheduler12renaming_flags_rollback_update_info3_pregname),
.oCOMMIT_ENTRY_COMMIT_VECTOR(commit_vector),
.oCOMMIT_OFFSET(commit_offset),
//Write Back
.iSCHE1_EX_BRANCH_VALID(ex_alu02scheduler1_branch_valid), .iSCHE1_EX_BRANCH_COMMIT_TAG(ex_alu02scheduler1_branch_commit_tag),
.iSCHE1_EX_ALU1_VALID(ex_alu12scheduler1_valid), .iSCHE1_EX_ALU1_COMMIT_TAG(ex_alu12scheduler1_commit_tag),
.iSCHE1_EX_ALU2_VALID(ex_alu22scheduler1_valid), .iSCHE1_EX_ALU2_COMMIT_TAG(ex_alu22scheduler1_commit_tag),
.iSCHE1_EX_ALU3_VALID(ex_alu32scheduler1_ldst_valid), .iSCHE1_EX_ALU3_COMMIT_TAG(ex_alu32scheduler1_ldst_commit_tag),
.oSTAGE_INFO_0_VALID(stage_info_scheduler1_0_valid), .oSTAGE_INFO_1_VALID(stage_info_scheduler1_1_valid),
.oSTAGE_INFO_REGIST_POINTER(stage_info_scheduler1_regist_pointer), .oSTAGE_INFO_COMMIT_POINTER(stage_info_scheduler1_commit_pointer),
//Previous
.iPREVIOUS_0_VALID(renaming2scheduler1_0_valid),
.iPREVIOUS_0_SOURCE0_ACTIVE(renaming2scheduler1_0_source0_active),
.iPREVIOUS_0_SOURCE1_ACTIVE(renaming2scheduler1_0_source1_active),
.iPREVIOUS_0_SOURCE0_SYSREG(renaming2scheduler1_0_source0_sysreg),
.iPREVIOUS_0_SOURCE1_SYSREG(renaming2scheduler1_0_source1_sysreg),
.iPREVIOUS_0_SOURCE0_SYSREG_RENAME(renaming2scheduler1_0_source0_sysreg_rename),
.iPREVIOUS_0_SOURCE1_SYSREG_RENAME(renaming2scheduler1_0_source1_sysreg_rename),
.iPREVIOUS_0_ADV_ACTIVE(renaming2scheduler1_0_adv_active),
.iPREVIOUS_0_DESTINATION_SYSREG(renaming2scheduler1_0_destination_sysreg),
.iPREVIOUS_0_WRITEBACK(renaming2scheduler1_0_data_writeback),
.iPREVIOUS_0_FLAGS_WRITEBACK(renaming2scheduler1_0_flags_writeback),
.iPREVIOUS_0_CMD(renaming2scheduler1_0_cmd),
.iPREVIOUS_0_CC_AFE(renaming2scheduler1_0_cc_afe),
.iPREVIOUS_0_FLAGS_REGNAME(renaming2scheduler1_0_flags_regname),
.iPREVIOUS_0_DESTINATION_REGNAME(renaming2scheduler1_0_destination_regname),
.iPREVIOUS_0_LOGIC_DESTINATION(renaming2scheduler1_0_logic_destination),
.iPREVIOUS_0_SOURCE0(renaming2scheduler1_0_source0),
.iPREVIOUS_0_SOURCE1(renaming2scheduler1_0_source1),
.iPREVIOUS_0_ADV_DATA(renaming2scheduler1_0_adv_data),
.iPREVIOUS_0_SOURCE0_FLAGS(renaming2scheduler1_0_source0_flags),
.iPREVIOUS_0_SOURCE1_IMM(renaming2scheduler1_0_source1_imm),
.iPREVIOUS_0_EX_SYS_ADDER(renaming2scheduler1_0_sys_adder),
.iPREVIOUS_0_EX_SYS_LDST(renaming2scheduler1_0_sys_ldst),
.iPREVIOUS_0_EX_LOGIC(renaming2scheduler1_0_logic),
.iPREVIOUS_0_EX_SHIFT(renaming2scheduler1_0_shift),
.iPREVIOUS_0_EX_ADDER(renaming2scheduler1_0_adder),
.iPREVIOUS_0_EX_MUL(renaming2scheduler1_0_mul),
.iPREVIOUS_0_EX_SDIV(renaming2scheduler1_0_sdiv),
.iPREVIOUS_0_EX_UDIV(renaming2scheduler1_0_udiv),
.iPREVIOUS_0_EX_LDST(renaming2scheduler1_0_ldst),
.iPREVIOUS_0_EX_BRANCH(renaming2scheduler1_0_branch),
.iPREVIOUS_1_VALID(renaming2scheduler1_1_valid),
.iPREVIOUS_1_SOURCE0_ACTIVE(renaming2scheduler1_1_source0_active),
.iPREVIOUS_1_SOURCE1_ACTIVE(renaming2scheduler1_1_source1_active),
.iPREVIOUS_1_SOURCE0_SYSREG(renaming2scheduler1_1_source0_sysreg),
.iPREVIOUS_1_SOURCE1_SYSREG(renaming2scheduler1_1_source1_sysreg),
.iPREVIOUS_1_SOURCE0_SYSREG_RENAME(renaming2scheduler1_1_source0_sysreg_rename),
.iPREVIOUS_1_SOURCE1_SYSREG_RENAME(renaming2scheduler1_1_source1_sysreg_rename),
.iPREVIOUS_1_ADV_ACTIVE(renaming2scheduler1_1_adv_active),
.iPREVIOUS_1_DESTINATION_SYSREG(renaming2scheduler1_1_destination_sysreg),
.iPREVIOUS_1_WRITEBACK(renaming2scheduler1_1_data_writeback),
.iPREVIOUS_1_FLAGS_WRITEBACK(renaming2scheduler1_1_flags_writeback),
.iPREVIOUS_1_CMD(renaming2scheduler1_1_cmd),
.iPREVIOUS_1_CC_AFE(renaming2scheduler1_1_cc_afe),
.iPREVIOUS_1_FLAGS_REGNAME(renaming2scheduler1_1_flags_regname),
.iPREVIOUS_1_DESTINATION_REGNAME(renaming2scheduler1_1_destination_regname),
.iPREVIOUS_1_LOGIC_DESTINATION(renaming2scheduler1_1_logic_destination),
.iPREVIOUS_1_SOURCE0(renaming2scheduler1_1_source0),
.iPREVIOUS_1_SOURCE1(renaming2scheduler1_1_source1),
.iPREVIOUS_1_ADV_DATA(renaming2scheduler1_1_adv_data),
.iPREVIOUS_1_SOURCE0_FLAGS(renaming2scheduler1_1_source0_flags),
.iPREVIOUS_1_SOURCE1_IMM(renaming2scheduler1_1_source_imm),
.iPREVIOUS_1_EX_SYS_ADDER(renaming2scheduler1_1_sys_adder),
.iPREVIOUS_1_EX_SYS_LDST(renaming2scheduler1_1_sys_ldst),
.iPREVIOUS_1_EX_LOGIC(renaming2scheduler1_1_logic),
.iPREVIOUS_1_EX_SHIFT(renaming2scheduler1_1_shift),
.iPREVIOUS_1_EX_ADDER(renaming2scheduler1_1_adder),
.iPREVIOUS_1_EX_MUL(renaming2scheduler1_1_mul),
.iPREVIOUS_1_EX_SDIV(renaming2scheduler1_1_sdiv),
.iPREVIOUS_1_EX_UDIV(renaming2scheduler1_1_udiv),
.iPREVIOUS_1_EX_LDST(renaming2scheduler1_1_ldst),
.iPREVIOUS_1_EX_BRANCH(renaming2scheduler1_1_branch),
.iPREVIOUS_PC(renaming2scheduler1_pc),
.oPREVIOUS_LOCK(scheduler12renaming_lock),
//Freelist
.iFLAG_REGISTER_0_RD(freereg_renaming2scheduler1_flag0_rd),
.oFLAG_REGISTER_0_NUM(freereg_renaming2scheduler1_flag0_num),
.oFLAG_REGISTER_0_EMPTY(freereg_renaming2scheduler1_flag0_empty),
.iFLAG_REGISTER_1_RD(freereg_renaming2scheduler1_flag1_rd),
.oFLAG_REGISTER_1_NUM(freereg_renaming2scheduler1_flag1_num),
.oFLAG_REGISTER_1_EMPTY(freereg_renaming2scheduler1_flag1_empty),
.iOTHER_REGISTER_0_RD(freereg_renaming2scheduler1_other0_rd),
.oOTHER_REGISTER_0_NUM(freereg_renaming2scheduler1_other0_num),
.oOTHER_REGISTER_0_EMPTY(freereg_renaming2scheduler1_other0_empty),
.iOTHER_REGISTER_1_RD(freereg_renaming2scheduler1_other1_rd),
.oOTHER_REGISTER_1_NUM(freereg_renaming2scheduler1_other1_num),
.oOTHER_REGISTER_1_EMPTY(freereg_renaming2scheduler1_other1_empty),
.iFLAG_REGISTER_0_WR(freereg_scheduler12scheduler2_flag0_wr),
.iFLAG_REGISTER_0_NUM(freereg_scheduler12scheduler2_flag0_num),
.oFLAG_REGISTER_0_FULL(freereg_scheduler12scheduler2_flag0_full),
.oFLAG_REGISTER_0_COUNT(freereg_scheduler12scheduler2_flag0_count),
.iFLAG_REGISTER_1_WR(freereg_scheduler12scheduler2_flag1_wr),
.iFLAG_REGISTER_1_NUM(freereg_scheduler12scheduler2_flag1_num),
.oFLAG_REGISTER_1_FULL(freereg_scheduler12scheduler2_flag1_full),
.oFLAG_REGISTER_1_COUNT(freereg_scheduler12scheduler2_flag1_count),
.iOTHER_REGISTER_0_WR(freereg_scheduler12scheduler2_other0_wr),
.iOTHER_REGISTER_0_NUM(freereg_scheduler12scheduler2_other0_num),
.oOTHER_REGISTER_0_FULL(freereg_scheduler12scheduler2_other0_full),
.oOTHER_REGISTER_0_COUNT(freereg_scheduler12scheduler2_other0_count),
.iOTHER_REGISTER_1_WR(freereg_scheduler12scheduler2_other1_wr),
.iOTHER_REGISTER_1_NUM(freereg_scheduler12scheduler2_other1_num),
.oOTHER_REGISTER_1_FULL(freereg_scheduler12scheduler2_other1_full),
.oOTHER_REGISTER_1_COUNT(freereg_scheduler12scheduler2_other1_count),
//Next
.oNEXT_0_VALID(scheduler12scheduler2_0_valid),
.oNEXT_0_SOURCE0_ACTIVE(scheduler12scheduler2_0_source0_active),
.oNEXT_0_SOURCE1_ACTIVE(scheduler12scheduler2_0_source1_active),
.oNEXT_0_SOURCE0_SYSREG(scheduler12scheduler2_0_source0_sysreg),
.oNEXT_0_SOURCE1_SYSREG(scheduler12scheduler2_0_source1_sysreg),
.oNEXT_0_SOURCE0_SYSREG_RENAME(scheduler12scheduler2_0_source0_sysreg_rename),
.oNEXT_0_SOURCE1_SYSREG_RENAME(scheduler12scheduler2_0_source1_sysreg_rename),
.oNEXT_0_ADV_ACTIVE(scheduler12scheduler2_0_adv_active),
.oNEXT_0_DESTINATION_SYSREG(scheduler12scheduler2_0_destination_sysreg),
.oNEXT_0_WRITEBACK(scheduler12scheduler2_0_writeback),
.oNEXT_0_FLAGS_WRITEBACK(scheduler12scheduler2_0_flags_writeback),
.oNEXT_0_CMD(scheduler12scheduler2_0_cmd),
.oNEXT_0_COMMIT_TAG(scheduler12scheduler2_0_commit_tag),
.oNEXT_0_CC_AFE(scheduler12scheduler2_0_cc_afe),
.oNEXT_0_FLAGS_REGNAME(scheduler12scheduler2_0_flags_regname),
.oNEXT_0_DESTINATION_REGNAME(scheduler12scheduler2_0_destination_regname),
.oNEXT_0_LOGIC_DESTINATION(scheduler12scheduler2_0_logic_destination),
.oNEXT_0_SOURCE0(scheduler12scheduler2_0_source0),
.oNEXT_0_SOURCE1(scheduler12scheduler2_0_source1),
.oNEXT_0_ADV_DATA(scheduler12scheduler2_0_adv_data),
.oNEXT_0_SOURCE0_FLAGS(scheduler12scheduler2_0_source0_flags),
.oNEXT_0_SOURCE1_IMM(scheduler12scheduler2_0_source1_imm),
.oNEXT_0_EX_SYS_ADDER(scheduler12scheduler2_0_sys_reg),
.oNEXT_0_EX_SYS_LDST(scheduler12scheduler2_0_sys_ldst),
.oNEXT_0_EX_LOGIC(scheduler12scheduler2_0_logic),
.oNEXT_0_EX_SHIFT(scheduler12scheduler2_0_shift),
.oNEXT_0_EX_ADDER(scheduler12scheduler2_0_adder),
.oNEXT_0_EX_MUL(scheduler12scheduler2_0_mul),
.oNEXT_0_EX_SDIV(scheduler12scheduler2_0_sdiv),
.oNEXT_0_EX_UDIV(scheduler12scheduler2_0_udiv),
.oNEXT_0_EX_LDST(scheduler12scheduler2_0_ldst),
.oNEXT_0_EX_BRANCH(scheduler12scheduler2_0_branch),
.oNEXT_1_VALID(scheduler12scheduler2_1_valid),
.oNEXT_1_SOURCE0_ACTIVE(scheduler12scheduler2_1_source0_active),
.oNEXT_1_SOURCE1_ACTIVE(scheduler12scheduler2_1_source1_active),
.oNEXT_1_SOURCE0_SYSREG(scheduler12scheduler2_1_source0_sysreg),
.oNEXT_1_SOURCE1_SYSREG(scheduler12scheduler2_1_source1_sysreg),
.oNEXT_1_SOURCE0_SYSREG_RENAME(scheduler12scheduler2_1_source0_sysreg_rename),
.oNEXT_1_SOURCE1_SYSREG_RENAME(scheduler12scheduler2_1_source1_sysreg_rename),
.oNEXT_1_ADV_ACTIVE(scheduler12scheduler2_1_adv_active),
.oNEXT_1_DESTINATION_SYSREG(scheduler12scheduler2_1_destination_sysreg),
.oNEXT_1_WRITEBACK(scheduler12scheduler2_1_writeback),
.oNEXT_1_FLAGS_WRITEBACK(scheduler12scheduler2_1_flags_writeback),
.oNEXT_1_CMD(scheduler12scheduler2_1_cmd),
.oNEXT_1_COMMIT_TAG(scheduler12scheduler2_1_commit_tag),
.oNEXT_1_CC_AFE(scheduler12scheduler2_1_cc_afe),
.oNEXT_1_FLAGS_REGNAME(scheduler12scheduler2_1_flags_regname),
.oNEXT_1_DESTINATION_REGNAME(scheduler12scheduler2_1_destination_regname),
.oNEXT_1_LOGIC_DESTINATION(scheduler12scheduler2_1_logic_destination),
.oNEXT_1_SOURCE0(scheduler12scheduler2_1_source0),
.oNEXT_1_SOURCE1(scheduler12scheduler2_1_source1),
.oNEXT_1_ADV_DATA(scheduler12scheduler2_1_adv_data),
.oNEXT_1_SOURCE0_FLAGS(scheduler12scheduler2_1_source0_flags),
.oNEXT_1_SOURCE1_IMM(scheduler12scheduler2_1_source1_imm),
.oNEXT_1_EX_SYS_ADDER(scheduler12scheduler2_1_sys_reg),
.oNEXT_1_EX_SYS_LDST(scheduler12scheduler2_1_sys_ldst),
.oNEXT_1_EX_LOGIC(scheduler12scheduler2_1_logic),
.oNEXT_1_EX_SHIFT(scheduler12scheduler2_1_shift),
.oNEXT_1_EX_ADDER(scheduler12scheduler2_1_adder),
.oNEXT_1_EX_MUL(scheduler12scheduler2_1_mul),
.oNEXT_1_EX_SDIV(scheduler12scheduler2_1_sdiv),
.oNEXT_1_EX_UDIV(scheduler12scheduler2_1_udiv),
.oNEXT_1_EX_LDST(scheduler12scheduler2_1_ldst),
.oNEXT_1_EX_BRANCH(scheduler12scheduler2_1_branch),
.oNEXT_PC(scheduler12scheduler2_pc), .iNEXT_LOCK(scheduler22scheduler1_lock)
);
/****************************************
Stage : 6
Scheduler2 Unit
****************************************/
scheduler2 #(32'h0) SATGE6_SCHEDULER2(
//System
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Exception
.iFREE_DEFAULT(exception_event),
.iFREE_RESTART(exception_restart),
.iFREE_RESERVATIONSTATION(exception_restart),
.iFREE_SYSREG_SET_IRQ_MODE(exception2scheduler2_irq_reqister_set),
.iFREE_SYSREG_BACK_PREVIOUS(exception2scheduler2_irq_reqister_ret),
.iFREE_CURRENT_PC(exception_current_pc),
.iFREE_REGISTER(free_register),
.iCOMMIT_ENTRY_COMMIT_VECTOR(commit_vector),
.iSYSREGINFO_IOSR_VALID(iSYSINFO_IOSR_VALID),
.iSYSREGINFO_IOSR(iSYSINFO_IOSR),
.oSYSREGINFO_TIDR(wire_sysreg_tidr),
.oSYSREGINFO_PTIDR(wire_sysreg_ptidr),
.oSYSREGINFO_PSR(wire_sysreg_psr),
.oSYSREGINFO_PPSR(wire_sysreg_ppsr),
.oSYSREGINFO_TISR(wire_sysreg_tisr),
.oSYSREGINFO_PDTR(wire_sysreg_pdtr),
.oSYSREGINFO_IDTR(wire_sysreg_idtr),
.oSYSREGINFO_PPCR(wire_sysreg_ppcr),
.iPREVIOUS_0_VALID(scheduler12scheduler2_0_valid),
.iPREVIOUS_0_SOURCE0_ACTIVE(scheduler12scheduler2_0_source0_active),
.iPREVIOUS_0_SOURCE1_ACTIVE(scheduler12scheduler2_0_source1_active),
.iPREVIOUS_0_SOURCE0_SYSREG(scheduler12scheduler2_0_source0_sysreg),
.iPREVIOUS_0_SOURCE1_SYSREG(scheduler12scheduler2_0_source1_sysreg),
.iPREVIOUS_0_SOURCE0_SYSREG_RENAME(scheduler12scheduler2_0_source0_sysreg_rename),
.iPREVIOUS_0_SOURCE1_SYSREG_RENAME(scheduler12scheduler2_0_source1_sysreg_rename),
.iPREVIOUS_0_ADV_ACTIVE(scheduler12scheduler2_0_adv_active),
.iPREVIOUS_0_DESTINATION_SYSREG(scheduler12scheduler2_0_destination_sysreg),
.iPREVIOUS_0_WRITEBACK(scheduler12scheduler2_0_writeback),
.iPREVIOUS_0_FLAGS_WRITEBACK(scheduler12scheduler2_0_flags_writeback),
.iPREVIOUS_0_CMD(scheduler12scheduler2_0_cmd),
.iPREVIOUS_0_COMMIT_TAG(scheduler12scheduler2_0_commit_tag),
.iPREVIOUS_0_CC_AFE(scheduler12scheduler2_0_cc_afe),
.iPREVIOUS_0_FLAGS_REGNAME(scheduler12scheduler2_0_flags_regname),
.iPREVIOUS_0_DESTINATION_REGNAME(scheduler12scheduler2_0_destination_regname),
.iPREVIOUS_0_LOGIC_DESTINATION(scheduler12scheduler2_0_logic_destination),
.iPREVIOUS_0_SOURCE0(scheduler12scheduler2_0_source0),
.iPREVIOUS_0_SOURCE1(scheduler12scheduler2_0_source1),
.iPREVIOUS_0_ADV_DATA(scheduler12scheduler2_0_adv_data),
.iPREVIOUS_0_SOURCE0_FLAGS(scheduler12scheduler2_0_source0_flags),
.iPREVIOUS_0_SOURCE1_IMM(scheduler12scheduler2_0_source1_imm),
.iPREVIOUS_0_EX_SYS_REG(scheduler12scheduler2_0_sys_reg),
.iPREVIOUS_0_EX_SYS_LDST(scheduler12scheduler2_0_sys_ldst),
.iPREVIOUS_0_EX_LOGIC(scheduler12scheduler2_0_logic),
.iPREVIOUS_0_EX_SHIFT(scheduler12scheduler2_0_shift),
.iPREVIOUS_0_EX_ADDER(scheduler12scheduler2_0_adder),
.iPREVIOUS_0_EX_MUL(scheduler12scheduler2_0_mul),
.iPREVIOUS_0_EX_SDIV(scheduler12scheduler2_0_sdiv),
.iPREVIOUS_0_EX_UDIV(scheduler12scheduler2_0_udiv),
.iPREVIOUS_0_EX_LDST(scheduler12scheduler2_0_ldst),
.iPREVIOUS_0_EX_BRANCH(scheduler12scheduler2_0_branch),
.iPREVIOUS_1_VALID(scheduler12scheduler2_1_valid),
.iPREVIOUS_1_SOURCE0_ACTIVE(scheduler12scheduler2_1_source0_active),
.iPREVIOUS_1_SOURCE1_ACTIVE(scheduler12scheduler2_1_source1_active),
.iPREVIOUS_1_SOURCE0_SYSREG(scheduler12scheduler2_1_source0_sysreg),
.iPREVIOUS_1_SOURCE1_SYSREG(scheduler12scheduler2_1_source1_sysreg),
.iPREVIOUS_1_SOURCE0_SYSREG_RENAME(scheduler12scheduler2_1_source0_sysreg_rename),
.iPREVIOUS_1_SOURCE1_SYSREG_RENAME(scheduler12scheduler2_1_source1_sysreg_rename),
.iPREVIOUS_1_ADV_ACTIVE(scheduler12scheduler2_1_adv_active),
.iPREVIOUS_1_DESTINATION_SYSREG(scheduler12scheduler2_1_destination_sysreg),
.iPREVIOUS_1_WRITEBACK(scheduler12scheduler2_1_writeback),
.iPREVIOUS_1_FLAGS_WRITEBACK(scheduler12scheduler2_1_flags_writeback),
.iPREVIOUS_1_CMD(scheduler12scheduler2_1_cmd),
.iPREVIOUS_1_COMMIT_TAG(scheduler12scheduler2_1_commit_tag),
.iPREVIOUS_1_CC_AFE(scheduler12scheduler2_1_cc_afe),
.iPREVIOUS_1_FLAGS_REGNAME(scheduler12scheduler2_1_flags_regname),
.iPREVIOUS_1_DESTINATION_REGNAME(scheduler12scheduler2_1_destination_regname),
.iPREVIOUS_1_LOGIC_DESTINATION(scheduler12scheduler2_1_logic_destination),
.iPREVIOUS_1_SOURCE0(scheduler12scheduler2_1_source0),
.iPREVIOUS_1_SOURCE1(scheduler12scheduler2_1_source1),
.iPREVIOUS_1_ADV_DATA(scheduler12scheduler2_1_adv_data),
.iPREVIOUS_1_SOURCE0_FLAGS(scheduler12scheduler2_1_source0_flags),
.iPREVIOUS_1_SOURCE1_IMM(scheduler12scheduler2_1_source1_imm),
.iPREVIOUS_1_EX_SYS_REG(scheduler12scheduler2_1_sys_reg),
.iPREVIOUS_1_EX_SYS_LDST(scheduler12scheduler2_1_sys_ldst),
.iPREVIOUS_1_EX_LOGIC(scheduler12scheduler2_1_logic),
.iPREVIOUS_1_EX_SHIFT(scheduler12scheduler2_1_shift),
.iPREVIOUS_1_EX_ADDER(scheduler12scheduler2_1_adder),
.iPREVIOUS_1_EX_MUL(scheduler12scheduler2_1_mul),
.iPREVIOUS_1_EX_SDIV(scheduler12scheduler2_1_sdiv),
.iPREVIOUS_1_EX_UDIV(scheduler12scheduler2_1_udiv),
.iPREVIOUS_1_EX_LDST(scheduler12scheduler2_1_ldst),
.iPREVIOUS_1_EX_BRANCH(scheduler12scheduler2_1_branch),
.iPREVIOUS_PC(scheduler12scheduler2_pc),
.oPREVIOUS_LOCK(scheduler22scheduler1_lock),
.oFLAG_REGISTER_0_WR(freereg_scheduler12scheduler2_flag0_wr),
.oFLAG_REGISTER_0_NUM(freereg_scheduler12scheduler2_flag0_num),
.iFLAG_REGISTER_0_FULL(freereg_scheduler12scheduler2_flag0_full),
.iFLAG_REGISTER_0_COUNT(freereg_scheduler12scheduler2_flag0_count),
.oFLAG_REGISTER_1_WR(freereg_scheduler12scheduler2_flag1_wr),
.oFLAG_REGISTER_1_NUM(freereg_scheduler12scheduler2_flag1_num),
.iFLAG_REGISTER_1_FULL(freereg_scheduler12scheduler2_flag1_full),
.iFLAG_REGISTER_1_COUNT(freereg_scheduler12scheduler2_flag1_count),
.oOTHER_REGISTER_0_WR(freereg_scheduler12scheduler2_other0_wr),
.oOTHER_REGISTER_0_NUM(freereg_scheduler12scheduler2_other0_num),
.iOTHER_REGISTER_0_FULL(freereg_scheduler12scheduler2_other0_full),
.iOTHER_REGISTER_0_COUNT(freereg_scheduler12scheduler2_other0_count),
.oOTHER_REGISTER_1_WR(freereg_scheduler12scheduler2_other1_wr),
.oOTHER_REGISTER_1_NUM(freereg_scheduler12scheduler2_other1_num),
.iOTHER_REGISTER_1_FULL(freereg_scheduler12scheduler2_other1_full),
.iOTHER_REGISTER_1_COUNT(freereg_scheduler12scheduler2_other1_count),
.oNEXT_EX_BRANCH_VALID(scheduler22ex_alu0_valid),
.oNEXT_EX_BRANCH_COMMIT_TAG(scheduler22ex_alu0_commit_tag),
.oNEXT_EX_BRANCH_CMD(scheduler22ex_alu0_cmd),
.oNEXT_EX_BRANCH_CC(scheduler22ex_alu0_cc),
.oNEXT_EX_BRANCH_FLAG(scheduler22ex_alu0_flag),
.oNEXT_EX_BRANCH_SOURCE(scheduler22ex_alu0_source),
.oNEXT_EX_PC(scheduler22ex_alu0_pc),
.iNEXT_EX_BRANCH_LOCK(ex_alu02scheduler2_lock),
.iSCHE2_EX_BRANCH_VALID(ex_alu02scheduler2_branch_valid),
.iSCHE2_EX_BRANCH_COMMIT_TAG(ex_alu02scheduler2_branch_commit_tag),
.oNEXT_EX_ALU1_VALID(scheduler22ex_alu1_valid),
.oNEXT_EX_ALU1_WRITEBACK(scheduler22ex_alu1_writeback),
.oNEXT_EX_ALU1_COMMIT_TAG(scheduler22ex_alu1_commit_tag),
.oNEXT_EX_ALU1_CMD(scheduler22ex_alu1_cmd),
.oNEXT_EX_ALU1_AFE(scheduler22ex_alu1_afe),
.oNEXT_EX_ALU1_SYS_REG(scheduler22ex_alu1_sys_reg),
.oNEXT_EX_ALU1_LOGIC(scheduler22ex_alu1_logic),
.oNEXT_EX_ALU1_SHIFT(scheduler22ex_alu1_shift),
.oNEXT_EX_ALU1_ADDER(scheduler22ex_alu1_adder),
.oNEXT_EX_ALU1_MUL(scheduler22ex_alu1_mul),
.oNEXT_EX_ALU1_SDIV(scheduler22ex_alu1_sdiv),
.oNEXT_EX_ALU1_UDIV(scheduler22ex_alu1_udiv),
.oNEXT_EX_ALU1_SOURCE0(scheduler22ex_alu1_source0),
.oNEXT_EX_ALU1_SOURCE1(scheduler22ex_alu1_source1),
.oNEXT_EX_ALU1_DESTINATION_SYSREG(scheduler22ex_alu1_destination_sysreg),
.oNEXT_EX_ALU1_LOGIC_DEST(scheduler22ex_alu1_logic_dest), //for debug
.oNEXT_EX_ALU1_DESTINATION_REGNAME(scheduler22ex_alu1_destination_regname),
.oNEXT_EX_ALU1_FLAGS_WRITEBACK(scheduler22ex_alu1_flags_writeback),
.oNEXT_EX_ALU1_FLAGS_REGNAME(scheduler22ex_alu1_flags_regname),
.oNEXT_EX_ALU1_PCR(scheduler22ex_alu1_pcr),
.iNEXT_EX_ALU1_LOCK(ex_alu12scheduler2_lock),
.iSCHE2_EX_ALU1_VALID(ex_alu12scheduler2_valid),
.iSCHE2_EX_ALU1_COMMIT_TAG(ex_alu12scheduler2_commit_tag),
.iSCHE2_EX_ALU1_DESTINATION_SYSREG(ex_alu12scheduler2_destination_sysreg),
.iSCHE2_EX_ALU1_DESTINATION_REGNAME(ex_alu12scheduler2_destination_regname),
.iSCHE2_EX_ALU1_WRITEBACK(ex_alu12scheduler2_writeback),
.iSCHE2_EX_ALU1_DATA(ex_alu12scheduler2_data),
.iSCHE2_EX_ALU1_FLAG(ex_alu12scheduler2_flag),
.iSCHE2_EX_ALU1_FLAGS_WRITEBACK(ex_alu12scheduler2_flags_writeback),
.iSCHE2_EX_ALU1_FLAGS_REGNAME(ex_alu12scheduler2_flags_regname),
.oNEXT_EX_ALU2_VALID(scheduler22ex_alu2_valid),
.oNEXT_EX_ALU2_WRITEBACK(scheduler22ex_alu2_writeback),
.oNEXT_EX_ALU2_COMMIT_TAG(scheduler22ex_alu2_commit_tag),
.oNEXT_EX_ALU2_CMD(scheduler22ex_alu2_cmd),
.oNEXT_EX_ALU2_AFE(scheduler22ex_alu2_afe),
.oNEXT_EX_ALU2_SYS_REG(scheduler22ex_alu2_sys_reg),
.oNEXT_EX_ALU2_LOGIC(scheduler22ex_alu2_logic),
.oNEXT_EX_ALU2_SHIFT(scheduler22ex_alu2_shift),
.oNEXT_EX_ALU2_ADDER(scheduler22ex_alu2_adder),
.oNEXT_EX_ALU2_SOURCE0(scheduler22ex_alu2_source0),
.oNEXT_EX_ALU2_SOURCE1(scheduler22ex_alu2_source1),
.oNEXT_EX_ALU2_DESTINATION_SYSREG(scheduler22ex_alu2_destination_sysreg),
.oNEXT_EX_ALU2_LOGIC_DEST(scheduler22ex_alu2_logic_dest), //for debug
.oNEXT_EX_ALU2_DESTINATION_REGNAME(scheduler22ex_alu2_destination_regname),
.oNEXT_EX_ALU2_FLAGS_WRITEBACK(scheduler22ex_alu2_flags_writeback),
.oNEXT_EX_ALU2_FLAGS_REGNAME(scheduler22ex_alu2_flags_regname),
.oNEXT_EX_ALU2_PCR(scheduler22ex_alu2_pcr),
.iNEXT_EX_ALU2_LOCK(ex_alu22scheduler2_lock),
.iSCHE2_EX_ALU2_VALID(ex_alu22scheduler2_valid),
.iSCHE2_EX_ALU2_COMMIT_TAG(ex_alu22scheduler2_commit_tag),
.iSCHE2_EX_ALU2_DESTINATION_SYSREG(ex_alu22scheduler2_destination_sysreg),
.iSCHE2_EX_ALU2_DESTINATION_REGNAME(ex_alu22scheduler2_destination_regname),
.iSCHE2_EX_ALU2_WRITEBACK(ex_alu22scheduler2_writeback),
.iSCHE2_EX_ALU2_DATA(ex_alu22scheduler2_data),
.iSCHE2_EX_ALU2_FLAG(ex_alu22scheduler2_flag),
.iSCHE2_EX_ALU2_FLAGS_WRITEBACK(ex_alu22scheduler2_flags_writeback),
.iSCHE2_EX_ALU2_FLAGS_REGNAME(ex_alu22scheduler2_flags_regname),
.oNEXT_EX_ALU3_VALID(scheduler22ex_alu3_valid),
.oNEXT_EX_ALU3_DESTINATION_SYSREG(scheduler22ex_alu3_destination_sysreg),
.oNEXT_EX_ALU3_COMMIT_TAG(scheduler22ex_alu3_commit_tag),
.oNEXT_EX_ALU3_CMD(scheduler22ex_alu3_cmd),
.oNEXT_EX_ALU3_SYS_LDST(scheduler22ex_alu3_sys_ldst),
.oNEXT_EX_ALU3_LDST(scheduler22ex_alu3_ldst),
.oNEXT_EX_ALU3_SOURCE0(scheduler22ex_alu3_source0),
.oNEXT_EX_ALU3_SOURCE1(scheduler22ex_alu3_source1),
.oNEXT_EX_ALU3_ADV_ACTIVE(scheduler22ex_alu3_adv_active),
.oNEXT_EX_ALU3_ADV_DATA(scheduler22ex_alu3_adv_data),
.oNEXT_EX_ALU3_LOGIC_DEST(scheduler22ex_alu3_logic_dest), //for debug
.oNEXT_EX_ALU3_DESTINATION_REGNAME(scheduler22ex_alu3_destination_regname),
.oNEXT_EX_ALU3_PC(scheduler22ex_alu3_pc),
.iNEXT_EX_ALU3_LOCK(ex_alu32scheduler2_ldst_lock),
.iSCHE2_ALU3_VALID(ex_alu32scheduler2_ldst_valid), .iSCHE2_ALU3_COMMIT_TAG(ex_alu32scheduler2_ldst_commit_tag),
.iSCHE2_ALU3_DESTINATION_REGNAME(ex_alu32scheduler2_ldst_destination_regname),
.iSCHE2_ALU3_DESTINATION_SYSREG(ex_alu32scheduler2_ldst_destination_sysreg),
.iSCHE2_ALU3_WRITEBACK(ex_alu32scheduler2_ldst_writeback),
.iSCHE2_ALU3_DATA(ex_alu32scheduler2_ldst_data)
);
/****************************************
Stage : 7
Execution Unit
****************************************/
//Branch(alu0)
execute_port0 SATGE7_EX_PORT0(
.iCLOCK(iCLOCK), .inRESET(inRESET),
.iFREE_RESTART(exception_restart),
.iPREVIOUS_EX_BRANCH_VALID(scheduler22ex_alu0_valid), .iPREVIOUS_EX_BRANCH_COMMIT_TAG(scheduler22ex_alu0_commit_tag),
.iPREVIOUS_EX_BRANCH_CMD(scheduler22ex_alu0_cmd), .iPREVIOUS_EX_BRANCH_CC(scheduler22ex_alu0_cc),
.iPREVIOUS_EX_BRANCH_FLAG(scheduler22ex_alu0_flag),
.iPREVIOUS_EX_BRANCH_SOURCE(scheduler22ex_alu0_source), .iPREVIOUS_EX_BRANCH_PC(scheduler22ex_alu0_pc),
.oPREVIOUS_EX_BRANCH_LOCK(ex_alu02scheduler2_lock),
//To Exception Unit
.oJUMP_ACTIVE(jump_active),
.oJUMP_ADDR(jump_addr),
//To Internal Interrupt Controller
.oSWI_ACTIVE(ex_alu02iic_swi_active),
.oSWI_NUMBER(ex_alu02iic_swi_number),
//To Exception Manager
.oINTR_ACTIVE(ex_alu02exception_intr_active),
.oINTR_ADDR(ex_alu02exception_intr_addr),
//IDT Write Action Request
.oIDTS_ACTIVE(ex_alu02exception_idts_active),
.oIDTS_R_ADDR(ex_alu02exception_idts_r_addr),
.oIDTR_COMMIT_TAG(ex_alu02exception_idts_commit_tag),
//To Scheduler1
.oSCHE1_EX_BRANCH_VALID(ex_alu02scheduler1_branch_valid),
.oSCHE1_EX_BRANCH_COMMIT_TAG(ex_alu02scheduler1_branch_commit_tag),
//To Scheduler2
.oSCHE2_EX_BRANCH_VALID(ex_alu02scheduler2_branch_valid),
.oSCHE2_EX_BRANCH_COMMIT_TAG(ex_alu02scheduler2_branch_commit_tag)
);
//Complex Adder(alu1)
execute_port1 SATGE7_EX_PORT1(
.iCLOCK(iCLOCK), .inRESET(inRESET),
.iFREE_EX(exception_restart),
.iPREVIOUS_EX_ALU1_VALID(scheduler22ex_alu1_valid),
.iPREVIOUS_EX_ALU1_WRITEBACK(scheduler22ex_alu1_writeback),
.iPREVIOUS_EX_ALU1_COMMIT_TAG(scheduler22ex_alu1_commit_tag),
.iPREVIOUS_EX_ALU1_CMD(scheduler22ex_alu1_cmd),
.iPREVIOUS_EX_ALU1_AFE(scheduler22ex_alu1_afe),
.iPREVIOUS_EX_ALU1_SYS_REG(scheduler22ex_alu1_sys_reg),
.iPREVIOUS_EX_ALU1_LOGIC(scheduler22ex_alu1_logic),
.iPREVIOUS_EX_ALU1_SHIFT(scheduler22ex_alu1_shift),
.iPREVIOUS_EX_ALU1_ADDER(scheduler22ex_alu1_adder),
.iPREVIOUS_EX_ALU1_MUL(scheduler22ex_alu1_mul),
.iPREVIOUS_EX_ALU1_SDIV(scheduler22ex_alu1_sdiv),
.iPREVIOUS_EX_ALU1_UDIV(scheduler22ex_alu1_udiv),
.iPREVIOUS_EX_ALU1_SOURCE0(scheduler22ex_alu1_source0),
.iPREVIOUS_EX_ALU1_SOURCE1(scheduler22ex_alu1_source1),
.iPREVIOUS_EX_ALU1_DESTINATION_SYSREG(scheduler22ex_alu1_destination_sysreg),
.iPREVIOUS_EX_ALU1_LOGIC_DEST(scheduler22ex_alu1_logic_dest),
.iPREVIOUS_EX_ALU1_DESTINATION_REGNAME(scheduler22ex_alu1_destination_regname),
.iPREVIOUS_EX_ALU1_FLAGS_WRITEBACK(scheduler22ex_alu1_flags_writeback),
.iPREVIOUS_EX_ALU1_FLAGS_REGNAME(scheduler22ex_alu1_flags_regname),
.iPREVIOUS_EX_ALU1_PCR(scheduler22ex_alu1_pcr),
.oPREVIOUS_EX_ALU1_LOCK(ex_alu12scheduler2_lock),
//Exception
.oINTERRUPT_ACTIVE(ex_alu12cim_valid),
.oINTERRUPT_NUM(ex_alu12cim_num),
//Scheduler
.oSCHE1_EX_ALU1_VALID(ex_alu12scheduler1_valid),
.oSCHE1_EX_ALU1_COMMIT_TAG(ex_alu12scheduler1_commit_tag),
.oSCHE2_EX_ALU1_VALID(ex_alu12scheduler2_valid),
.oSCHE2_EX_ALU1_COMMIT_TAG(ex_alu12scheduler2_commit_tag),
.oSCHE2_EX_ALU1_SYSREG(ex_alu12scheduler2_destination_sysreg),
.oSCHE2_EX_ALU1_LOGIC_DEST(),
.oSCHE2_EX_ALU1_DESTINATION_REGNAME(ex_alu12scheduler2_destination_regname),
.oSCHE2_EX_ALU1_WRITEBACK(ex_alu12scheduler2_writeback),
.oSCHE2_EX_ALU1_DATA(ex_alu12scheduler2_data),
.oSCHE2_EX_ALU1_FLAG(ex_alu12scheduler2_flag),
.oSCHE2_EX_ALU1_FLAGS_WRITEBACK(ex_alu12scheduler2_flags_writeback),
.oSCHE2_EX_ALU1_FLAGS_REGNAME(ex_alu12scheduler2_flags_regname)
);
//Simple Adder(alu2)
execute_port2 SATGE7_EX_PORT2(
.iCLOCK(iCLOCK), .inRESET(inRESET),
.iFREE_EX(exception_restart),
.iPREVIOUS_EX_ALU2_VALID(scheduler22ex_alu2_valid),
.iPREVIOUS_EX_ALU2_WRITEBACK(scheduler22ex_alu2_writeback),
.iPREVIOUS_EX_ALU2_COMMIT_TAG(scheduler22ex_alu2_commit_tag),
.iPREVIOUS_EX_ALU2_CMD(scheduler22ex_alu2_cmd),
.iPREVIOUS_EX_ALU2_AFE(scheduler22ex_alu2_afe),
.iPREVIOUS_EX_ALU2_SYS_REG(scheduler22ex_alu2_sys_reg),
.iPREVIOUS_EX_ALU2_LOGIC(scheduler22ex_alu2_logic),
.iPREVIOUS_EX_ALU2_SHIFT(scheduler22ex_alu2_shift),
.iPREVIOUS_EX_ALU2_ADDER(scheduler22ex_alu2_adder),
.iPREVIOUS_EX_ALU2_SOURCE0(scheduler22ex_alu2_source0),
.iPREVIOUS_EX_ALU2_SOURCE1(scheduler22ex_alu2_source1),
.iPREVIOUS_EX_ALU2_DESTINATION_SYSREG(scheduler22ex_alu2_destination_sysreg),
.iPREVIOUS_EX_ALU2_LOGIC_DEST(scheduler22ex_alu2_logic_dest),
.iPREVIOUS_EX_ALU2_DESTINATION_REGNAME(scheduler22ex_alu2_destination_regname),
.iPREVIOUS_EX_ALU2_FLAGS_WRITEBACK(scheduler22ex_alu2_flags_writeback),
.iPREVIOUS_EX_ALU2_FLAGS_REGNAME(scheduler22ex_alu2_flags_regname),
.iPREVIOUS_EX_ALU2_PCR(scheduler22ex_alu2_pcr),
.oPREVIOUS_EX_ALU2_LOCK(ex_alu22scheduler2_lock),
//Scheduler
.oSCHE1_EX_ALU2_VALID(ex_alu22scheduler1_valid),
.oSCHE1_EX_ALU2_COMMIT_TAG(ex_alu22scheduler1_commit_tag),
.oSCHE2_EX_ALU2_VALID(ex_alu22scheduler2_valid),
.oSCHE2_EX_ALU2_COMMIT_TAG(ex_alu22scheduler2_commit_tag),
.oSCHE2_EX_ALU2_SYSREG(ex_alu22scheduler2_destination_sysreg),
.oSCHE2_EX_ALU2_LOGIC_DEST(),
.oSCHE2_EX_ALU2_DESTINATION_REGNAME(ex_alu22scheduler2_destination_regname),
.oSCHE2_EX_ALU2_WRITEBACK(ex_alu22scheduler2_writeback),
.oSCHE2_EX_ALU2_DATA(ex_alu22scheduler2_data),
.oSCHE2_EX_ALU2_FLAG(ex_alu22scheduler2_flag),
.oSCHE2_EX_ALU2_FLAGS_WRITEBACK(ex_alu22scheduler2_flags_writeback),
.oSCHE2_EX_ALU2_FLAGS_REGNAME(ex_alu22scheduler2_flags_regname)
);
//Load/Store(alu3)
execute_port3 SATGE7_EX_PORT3(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
.iRESET_SYNC(1'b0),
//Free
.iFREE_EX(exception_restart),
.iFREE_SYSREG_NEW_SPR_VALID(exception2alu0_new_spr_valid),
.iFREE_SYSREG_NEW_SPR(exception2alu0_new_spr),
//Sysreg
.iSYSREG_TIDR(wire_sysreg_tidr),
.iSYSREG_PSR(wire_sysreg_psr),
.iSYSREG_PDTR(wire_sysreg_pdtr),
.oSYSREG_SPR(wire_sysreg_spr),
//Data OI
.oDATAIO_REQ(alu32ldst_ldst_req),
.iDATAIO_BUSY(ldst2alu3_ldst_busy),
.oDATAIO_ORDER(alu32ldst_ldst_order),
.oDATAIO_MASK(alu32ldst_ldst_mask),
.oDATAIO_RW(alu32ldst_ldst_rw),
.oDATAIO_TID(alu32ldst_ldst_tid),
.oDATAIO_MMUMOD(alu32ldst_ldst_mmumod),
.oDATAIO_PDT(alu32ldst_ldst_pdt),
.oDATAIO_ADDR(alu32ldst_ldst_addr),
.oDATAIO_DATA(alu32ldst_ldst_data),
.iDATAIO_REQ(ldst2alu3_ldst_req),
.iDATAIO_DATA(ldst2alu3_ldst_data),
//Scheduler
.iPREVIOUS_EX_ALU3_VALID(scheduler22ex_alu3_valid),
.iPREVIOUS_EX_ALU3_DESTINATION_SYSREG(scheduler22ex_alu3_destination_sysreg),
.iPREVIOUS_EX_ALU3_COMMIT_TAG(scheduler22ex_alu3_commit_tag),
.iPREVIOUS_EX_ALU3_CMD(scheduler22ex_alu3_cmd),
.iPREVIOUS_EX_ALU3_SOURCE0(scheduler22ex_alu3_source0),
.iPREVIOUS_EX_ALU3_SOURCE1(scheduler22ex_alu3_source1),
.iPREVIOUS_EX_ALU3_ADV_ACTIVE(scheduler22ex_alu3_adv_active),
.iPREVIOUS_EX_ALU3_ADV_DATA(scheduler22ex_alu3_adv_data),
.iPREVIOUS_EX_ALU3_LOGIC_DEST(scheduler22ex_alu3_logic_dest),
.iPREVIOUS_EX_ALU3_DESTINATION_REGNAME(scheduler22ex_alu3_destination_regname), .iPREVIOUS_EX_ALU3_PC(scheduler22ex_alu3_pc),
.iPREVIOUS_EX_ALU3_SYS_LDST(scheduler22ex_alu3_sys_ldst),
.iPREVIOUS_EX_ALU3_LDST(scheduler22ex_alu3_ldst),
.oPREVIOUS_EX_ALU3_LOCK(ex_alu32scheduler2_ldst_lock),
.oSCHE1_ALU3_VALID(ex_alu32scheduler1_ldst_valid),
.oSCHE1_ALU3_COMMIT_TAG(ex_alu32scheduler1_ldst_commit_tag),
.oSCHE2_ALU3_VALID(ex_alu32scheduler2_ldst_valid),
.oSCHE2_ALU3_COMMIT_TAG(ex_alu32scheduler2_ldst_commit_tag),
.oSCHE2_ALU3_LOGIC_DEST(),
.oSCHE2_ALU3_DESTINATION_REGNAME(ex_alu32scheduler2_ldst_destination_regname),
.oSCHE2_ALU3_DESTINATION_SYSREG(ex_alu32scheduler2_ldst_destination_sysreg),
.oSCHE2_ALU3_WRITEBACK(ex_alu32scheduler2_ldst_writeback),
.oSCHE2_ALU3_DATA(ex_alu32scheduler2_ldst_data)
);
/****************************************
Stage : 8
Data Cache
****************************************/
wire ldst_arbiter2d_cache_req;
wire d_cache2ldst_arbiter_busy;
wire [1:0] ldst_arbiter2d_cache_order;
wire [3:0] ldst_arbiter2d_cache_mask;
wire ldst_arbiter2d_cache_rw;
wire [31:0] ldst_arbiter2d_cache_tid;
wire [1:0] ldst_arbiter2d_cache_mmumod;
wire [31:0] ldst_arbiter2d_cache_pdt;
wire [31:0] ldst_arbiter2d_cache_addr;
wire [31:0] ldst_arbiter2d_cache_data;
wire d_cache2ldst_arbiter_valid;
wire d_cache2ldst_arbiter_pagefault;
wire [13:0] d_cache2ldst_arbiter_mmu_flags;
wire [31:0] d_cache2ldst_arbiter_data;
l1_data_cache L1_DATA_CACHE(
.iCLOCK(iCLOCK),
.inRESET(inRESET),
//Remove
.iREMOVE(exception_restart),
.iCACHE_FLASH(/*cache_flash || free_cache_flush*/1'b0),
//IOSR
.iSYSINFO_IOSR_VALID(iSYSINFO_IOSR_VALID),
.iSYSINFO_IOSR(iSYSINFO_IOSR),
/****************************************
Load/Store Module
****************************************/
//Load Store -> Cache
.iLDST_REQ(ldst_arbiter2d_cache_req),
.oLDST_BUSY(d_cache2ldst_arbiter_busy),
.iLDST_ORDER(ldst_arbiter2d_cache_order),
.iLDST_MASK(ldst_arbiter2d_cache_mask),
.iLDST_RW(ldst_arbiter2d_cache_rw),
.iLDST_TID(ldst_arbiter2d_cache_tid),
.iLDST_MMUMOD(ldst_arbiter2d_cache_mmumod),
.iLDST_PDT(ldst_arbiter2d_cache_pdt),
.iLDST_ADDR(ldst_arbiter2d_cache_addr),
.iLDST_DATA(ldst_arbiter2d_cache_data),
//Cache -> Load Store
.oLDST_VALID(d_cache2ldst_arbiter_valid),
.oLDST_PAGEFAULT(d_cache2ldst_arbiter_pagefault),////////////////////////////////
.oLDST_MMU_FLAGS(d_cache2ldst_arbiter_mmu_flags),////////////////////////////////
.oLDST_DATA(d_cache2ldst_arbiter_data),
/****************************************
Data Memory
****************************************/
//Req
.oDATA_REQ(oDATA_REQ),
.iDATA_LOCK(iDATA_LOCK),
.oDATA_ORDER(oDATA_ORDER),
.oDATA_MASK(oDATA_MASK),
.oDATA_RW(oDATA_RW), //0=Write 1=Read
.oDATA_TID(oDATA_TID),
.oDATA_MMUMOD(oDATA_MMUMOD),
.oDATA_PDT(oDATA_PDT),
.oDATA_ADDR(oDATA_ADDR),
//This -> Data RAM
.oDATA_DATA(oDATA_DATA),
//Data RAM -> This
.iDATA_VALID(iDATA_VALID),
.iDATA_PAGEFAULT(iDATA_PAGEFAULT),
.iDATA_MMU_FLAGS(iDATA_MMU_FLAGS),
.iDATA_DATA(iDATA_DATA),
/****************************************
IO
****************************************/
//Req
.oIO_REQ(oIO_REQ),
.iIO_BUSY(iIO_BUSY),
.oIO_ORDER(oIO_ORDER),
.oIO_RW(oIO_RW), //0=Write 1=Read
.oIO_ADDR(oIO_ADDR),
//Write
.oIO_DATA(oIO_DATA),
//Rec
.iIO_VALID(iIO_VALID),
.iIO_DATA(iIO_DATA)
);
/****************************************
Load Store Port Selector
****************************************/
/*
//Output Port
assign oLDST_REQ = alu32ldst_ldst_req;
assign oLDST_ORDER = alu32ldst_ldst_order;
assign oLDST_RW = alu32ldst_ldst_rw;
assign oLDST_TID = alu32ldst_ldst_tid;
assign oLDST_MMUMOD = alu32ldst_ldst_mmumod;
assign oLDST_PDT = alu32ldst_ldst_pdt;
assign oLDST_ADDR = alu32ldst_ldst_addr;
assign oLDST_DATA = alu32ldst_ldst_data;
//Exception Unit
assign ldst2exception_ldst_busy = (exception2ldst_ldst_use)? iLDST_BUSY : 1'b1;
assign ldst2exception_ldst_req = (exception2ldst_ldst_use)? iLDST_VALID : 1'b0;
assign ldst2exception_ldst_data = iLDST_DATA;
//ALU-LoadStore Unit
assign ldst2alu3_ldst_busy = (exception2ldst_ldst_use)? 1'b1 : iLDST_BUSY;
assign ldst2alu3_ldst_req = (exception2ldst_ldst_use)? 1'b0 : iLDST_VALID;
assign ldst2alu3_ldst_data = iLDST_DATA;
*/
/*
//Output Port
assign oLDST_REQ = (exception2ldst_ldst_use)? exception2ldst_ldst_req : alu32ldst_ldst_req;
assign oLDST_ORDER = (exception2ldst_ldst_use)? exception2ldst_ldst_order : alu32ldst_ldst_order;
assign oLDST_RW = (exception2ldst_ldst_use)? exception2ldst_ldst_rw : alu32ldst_ldst_rw;
assign oLDST_TID = (exception2ldst_ldst_use)? exception2ldst_ldst_tid : alu32ldst_ldst_tid;
assign oLDST_MMUMOD = (exception2ldst_ldst_use)? exception2ldst_ldst_mmumod : alu32ldst_ldst_mmumod;
assign oLDST_PDT = (exception2ldst_ldst_use)? exception2ldst_ldst_pdt : alu32ldst_ldst_pdt;
assign oLDST_ADDR = (exception2ldst_ldst_use)? exception2ldst_ldst_addr : alu32ldst_ldst_addr;
assign oLDST_DATA = (exception2ldst_ldst_use)? exception2ldst_ldst_data : alu32ldst_ldst_data;
//Exception Unit
assign ldst2exception_ldst_busy = (exception2ldst_ldst_use)? iLDST_BUSY : 1'b1;
assign ldst2exception_ldst_req = (exception2ldst_ldst_use)? iLDST_VALID : 1'b0;
assign ldst2exception_ldst_data = iLDST_DATA;
//ALU-LoadStore Unit
assign ldst2alu3_ldst_busy = (exception2ldst_ldst_use)? 1'b1 : iLDST_BUSY;
assign ldst2alu3_ldst_req = (exception2ldst_ldst_use)? 1'b0 : iLDST_VALID;
assign ldst2alu3_ldst_data = iLDST_DATA;
*/
losd_store_pipe_arbiter LDST_PIPE_ARBITOR(
.oLDST_REQ(ldst_arbiter2d_cache_req),
.iLDST_BUSY(d_cache2ldst_arbiter_busy),
.oLDST_ORDER(ldst_arbiter2d_cache_order), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.oLDST_MASK(ldst_arbiter2d_cache_mask),
.oLDST_RW(ldst_arbiter2d_cache_rw), //0=Read 1=Write
.oLDST_TID(ldst_arbiter2d_cache_tid),
.oLDST_MMUMOD(ldst_arbiter2d_cache_mmumod),
.oLDST_PDT(ldst_arbiter2d_cache_pdt),
.oLDST_ADDR(ldst_arbiter2d_cache_addr),
.oLDST_DATA(ldst_arbiter2d_cache_data),
.iLDST_VALID(d_cache2ldst_arbiter_valid),
.iLDST_PAGEFAULT(d_cache2ldst_arbiter_pagefault),
.iLDST_MMU_FLAGS(d_cache2ldst_arbiter_mmu_flags),
.iLDST_DATA(d_cache2ldst_arbiter_data),
//Selector
.iUSE_SEL(exception2ldst_ldst_use), //0:Execution | 1:Exception
//Execution Module
.iEXE_REQ(alu32ldst_ldst_req),
.oEXE_BUSY(ldst2alu3_ldst_busy),
.iEXE_ORDER(alu32ldst_ldst_order), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.iEXE_MASK(alu32ldst_ldst_mask),
.iEXE_RW(alu32ldst_ldst_rw), //0=Read 1=Write
.iEXE_TID(alu32ldst_ldst_tid),
.iEXE_MMUMOD(alu32ldst_ldst_mmumod),
.iEXE_PDT(alu32ldst_ldst_pdt),
.iEXE_ADDR(alu32ldst_ldst_addr),
.iEXE_DATA(alu32ldst_ldst_data),
.oEXE_REQ(ldst2alu3_ldst_req),
.oEXE_PAGEFAULT(),
.oEXE_MMU_FLAGS(),
.oEXE_DATA(ldst2alu3_ldst_data),
//Exception Module
.iEXCEPT_REQ(exception2ldst_ldst_req),
.oEXCEPT_BUSY(ldst2exception_ldst_busy),
.iEXCEPT_ORDER(exception2ldst_ldst_order), //00=Byte Order 01=2Byte Order 10= Word Order 11= None
.iEXCEPT_RW(exception2ldst_ldst_rw), //0=Read 1=Write
.iEXCEPT_TID(exception2ldst_ldst_tid),
.iEXCEPT_MMUMOD(exception2ldst_ldst_mmumod),
.iEXCEPT_PDT(exception2ldst_ldst_pdt),
.iEXCEPT_ADDR(exception2ldst_ldst_addr),
.iEXCEPT_DATA(exception2ldst_ldst_data),
.oEXCEPT_REQ(ldst2exception_ldst_req),
.oEXCEPT_DATA(ldst2exception_ldst_data)
);
endmodule
`default_nettype wire
|
// -----------------------------------------------------------
// Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Description: Single clock Avalon-ST FIFO.
// -----------------------------------------------------------
`timescale 1 ns / 1 ns
//altera message_off 10036
module altera_avalon_sc_fifo
#(
// --------------------------------------------------
// Parameters
// --------------------------------------------------
parameter SYMBOLS_PER_BEAT = 1,
parameter BITS_PER_SYMBOL = 8,
parameter FIFO_DEPTH = 16,
parameter CHANNEL_WIDTH = 0,
parameter ERROR_WIDTH = 0,
parameter USE_PACKETS = 0,
parameter USE_FILL_LEVEL = 0,
parameter USE_STORE_FORWARD = 0,
parameter USE_ALMOST_FULL_IF = 0,
parameter USE_ALMOST_EMPTY_IF = 0,
// --------------------------------------------------
// Empty latency is defined as the number of cycles
// required for a write to deassert the empty flag.
// For example, a latency of 1 means that the empty
// flag is deasserted on the cycle after a write.
//
// Another way to think of it is the latency for a
// write to propagate to the output.
//
// An empty latency of 0 implies lookahead, which is
// only implemented for the register-based FIFO.
// --------------------------------------------------
parameter EMPTY_LATENCY = 3,
parameter USE_MEMORY_BLOCKS = 1,
// --------------------------------------------------
// Internal Parameters
// --------------------------------------------------
parameter DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL,
parameter EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
// --------------------------------------------------
// Ports
// --------------------------------------------------
input clk,
input reset,
input [DATA_WIDTH-1: 0] in_data,
input in_valid,
input in_startofpacket,
input in_endofpacket,
input [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] in_empty,
input [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] in_error,
input [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] in_channel,
output in_ready,
output [DATA_WIDTH-1 : 0] out_data,
output reg out_valid,
output out_startofpacket,
output out_endofpacket,
output [((EMPTY_WIDTH>0) ? (EMPTY_WIDTH-1):0) : 0] out_empty,
output [((ERROR_WIDTH>0) ? (ERROR_WIDTH-1):0) : 0] out_error,
output [((CHANNEL_WIDTH>0) ? (CHANNEL_WIDTH-1):0): 0] out_channel,
input out_ready,
input [(USE_STORE_FORWARD ? 2 : 1) : 0] csr_address,
input csr_write,
input csr_read,
input [31 : 0] csr_writedata,
output reg [31 : 0] csr_readdata,
output wire almost_full_data,
output wire almost_empty_data
);
// --------------------------------------------------
// Local Parameters
// --------------------------------------------------
localparam ADDR_WIDTH = log2ceil(FIFO_DEPTH);
localparam DEPTH = FIFO_DEPTH;
localparam PKT_SIGNALS_WIDTH = 2 + EMPTY_WIDTH;
localparam PAYLOAD_WIDTH = (USE_PACKETS == 1) ?
2 + EMPTY_WIDTH + DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH:
DATA_WIDTH + ERROR_WIDTH + CHANNEL_WIDTH;
// --------------------------------------------------
// Internal Signals
// --------------------------------------------------
genvar i;
reg [PAYLOAD_WIDTH-1 : 0] mem [DEPTH-1 : 0];
reg [ADDR_WIDTH-1 : 0] wr_ptr;
reg [ADDR_WIDTH-1 : 0] rd_ptr;
reg [DEPTH-1 : 0] mem_used;
wire [ADDR_WIDTH-1 : 0] next_wr_ptr;
wire [ADDR_WIDTH-1 : 0] next_rd_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_wr_ptr;
wire [ADDR_WIDTH-1 : 0] incremented_rd_ptr;
wire [ADDR_WIDTH-1 : 0] mem_rd_ptr;
wire read;
wire write;
reg empty;
reg next_empty;
reg full;
reg next_full;
wire [PKT_SIGNALS_WIDTH-1 : 0] in_packet_signals;
wire [PKT_SIGNALS_WIDTH-1 : 0] out_packet_signals;
wire [PAYLOAD_WIDTH-1 : 0] in_payload;
reg [PAYLOAD_WIDTH-1 : 0] internal_out_payload;
reg [PAYLOAD_WIDTH-1 : 0] out_payload;
reg internal_out_valid;
wire internal_out_ready;
reg [ADDR_WIDTH : 0] fifo_fill_level;
reg [ADDR_WIDTH : 0] fill_level;
reg [ADDR_WIDTH-1 : 0] sop_ptr = 0;
reg [23:0] almost_full_threshold;
reg [23:0] almost_empty_threshold;
reg [23:0] cut_through_threshold;
reg [15:0] pkt_cnt;
reg [15:0] pkt_cnt_r;
reg [15:0] pkt_cnt_plusone;
reg [15:0] pkt_cnt_minusone;
reg drop_on_error_en;
reg error_in_pkt;
reg pkt_has_started;
reg sop_has_left_fifo;
reg fifo_too_small_r;
reg pkt_cnt_eq_zero;
reg pkt_cnt_eq_one;
reg pkt_cnt_changed;
wire wait_for_threshold;
reg pkt_mode;
wire wait_for_pkt;
wire ok_to_forward;
wire in_pkt_eop_arrive;
wire out_pkt_leave;
wire in_pkt_start;
wire in_pkt_error;
wire drop_on_error;
wire fifo_too_small;
wire out_pkt_sop_leave;
wire [31:0] max_fifo_size;
reg fifo_fill_level_lt_cut_through_threshold;
// --------------------------------------------------
// Define Payload
//
// Icky part where we decide which signals form the
// payload to the FIFO with generate blocks.
// --------------------------------------------------
generate
if (EMPTY_WIDTH > 0) begin
assign in_packet_signals = {in_startofpacket, in_endofpacket, in_empty};
assign {out_startofpacket, out_endofpacket, out_empty} = out_packet_signals;
end
else begin
assign out_empty = in_error;
assign in_packet_signals = {in_startofpacket, in_endofpacket};
assign {out_startofpacket, out_endofpacket} = out_packet_signals;
end
endgenerate
generate
if (USE_PACKETS) begin
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_error, in_channel};
assign {out_packet_signals, out_data, out_error, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data, in_error};
assign {out_packet_signals, out_data, out_error} = out_payload;
end
end
else begin
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_packet_signals, in_data, in_channel};
assign {out_packet_signals, out_data, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_packet_signals, in_data};
assign {out_packet_signals, out_data} = out_payload;
end
end
end
else begin
assign out_packet_signals = 0;
if (ERROR_WIDTH > 0) begin
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_error, in_channel};
assign {out_data, out_error, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = {in_data, in_error};
assign {out_data, out_error} = out_payload;
end
end
else begin
assign out_error = in_error;
if (CHANNEL_WIDTH > 0) begin
assign in_payload = {in_data, in_channel};
assign {out_data, out_channel} = out_payload;
end
else begin
assign out_channel = in_channel;
assign in_payload = in_data;
assign out_data = out_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Memory-based FIFO storage
//
// To allow a ready latency of 0, the read index is
// obtained from the next read pointer and memory
// outputs are unregistered.
//
// If the empty latency is 1, we infer bypass logic
// around the memory so writes propagate to the
// outputs on the next cycle.
//
// Do not change the way this is coded: Quartus needs
// a perfect match to the template, and any attempt to
// refactor the two always blocks into one will break
// memory inference.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
if (EMPTY_LATENCY == 1) begin
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] = in_payload;
internal_out_payload = mem[mem_rd_ptr];
end
end else begin
always @(posedge clk) begin
if (in_valid && in_ready)
mem[wr_ptr] <= in_payload;
internal_out_payload <= mem[mem_rd_ptr];
end
end
assign mem_rd_ptr = next_rd_ptr;
end else begin
// --------------------------------------------------
// Register-based FIFO storage
//
// Uses a shift register as the storage element. Each
// shift register slot has a bit which indicates if
// the slot is occupied (credit to Sam H for the idea).
// The occupancy bits are contiguous and start from the
// lsb, so 0000, 0001, 0011, 0111, 1111 for a 4-deep
// FIFO.
//
// Each slot is enabled during a read or when it
// is unoccupied. New data is always written to every
// going-to-be-empty slot (we keep track of which ones
// are actually useful with the occupancy bits). On a
// read we shift occupied slots.
//
// The exception is the last slot, which always gets
// new data when it is unoccupied.
// --------------------------------------------------
for (i = 0; i < DEPTH-1; i = i + 1) begin : shift_reg
always @(posedge clk or posedge reset) begin
if (reset) begin
mem[i] <= 0;
end
else if (read || !mem_used[i]) begin
if (!mem_used[i+1])
mem[i] <= in_payload;
else
mem[i] <= mem[i+1];
end
end
end
always @(posedge clk, posedge reset) begin
if (reset) begin
mem[DEPTH-1] <= 0;
end
else begin
if (!mem_used[DEPTH-1])
mem[DEPTH-1] <= in_payload;
if (DEPTH == 1) begin
if (write)
mem[DEPTH-1] <= in_payload;
end
end
end
end
endgenerate
assign read = internal_out_ready && internal_out_valid && ok_to_forward;
assign write = in_ready && in_valid;
// --------------------------------------------------
// Pointer Management
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
assign incremented_wr_ptr = wr_ptr + 1'b1;
assign incremented_rd_ptr = rd_ptr + 1'b1;
assign next_wr_ptr = drop_on_error ? sop_ptr : write ? incremented_wr_ptr : wr_ptr;
assign next_rd_ptr = (read) ? incremented_rd_ptr : rd_ptr;
always @(posedge clk or posedge reset) begin
if (reset) begin
wr_ptr <= 0;
rd_ptr <= 0;
end
else begin
wr_ptr <= next_wr_ptr;
rd_ptr <= next_rd_ptr;
end
end
end else begin
// --------------------------------------------------
// Shift Register Occupancy Bits
//
// Consider a 4-deep FIFO with 2 entries: 0011
// On a read and write, do not modify the bits.
// On a write, left-shift the bits to get 0111.
// On a read, right-shift the bits to get 0001.
//
// Also, on a write we set bit0 (the head), while
// clearing the tail on a read.
// --------------------------------------------------
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[0] <= 0;
end
else begin
if (write ^ read) begin
if (read) begin
if (DEPTH > 1)
mem_used[0] <= mem_used[1];
else
mem_used[0] <= 0;
end
if (write)
mem_used[0] <= 1;
end
end
end
if (DEPTH > 1) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
mem_used[DEPTH-1] <= 0;
end
else begin
if (write ^ read) begin
mem_used[DEPTH-1] <= 0;
if (write)
mem_used[DEPTH-1] <= mem_used[DEPTH-2];
end
end
end
end
for (i = 1; i < DEPTH-1; i = i + 1) begin : storage_logic
always @(posedge clk, posedge reset) begin
if (reset) begin
mem_used[i] <= 0;
end
else begin
if (write ^ read) begin
if (read)
mem_used[i] <= mem_used[i+1];
if (write)
mem_used[i] <= mem_used[i-1];
end
end
end
end
end
endgenerate
// --------------------------------------------------
// Memory FIFO Status Management
//
// Generates the full and empty signals from the
// pointers. The FIFO is full when the next write
// pointer will be equal to the read pointer after
// a write. Reading from a FIFO clears full.
//
// The FIFO is empty when the next read pointer will
// be equal to the write pointer after a read. Writing
// to a FIFO clears empty.
//
// A simultaneous read and write must not change any of
// the empty or full flags unless there is a drop on error event.
// --------------------------------------------------
generate if (USE_MEMORY_BLOCKS == 1) begin
always @* begin
next_full = full;
next_empty = empty;
if (read && !write) begin
next_full = 1'b0;
if (incremented_rd_ptr == wr_ptr)
next_empty = 1'b1;
end
if (write && !read) begin
if (!drop_on_error)
next_empty = 1'b0;
else if (sop_ptr == rd_ptr) // drop on error and only 1 pkt in fifo
next_empty = 1'b1;
if (incremented_wr_ptr == rd_ptr && !drop_on_error)
next_full = 1'b1;
end
if (write && read && drop_on_error) begin
if (sop_ptr == next_rd_ptr)
next_empty = 1'b1;
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
empty <= 1;
full <= 0;
end
else begin
empty <= next_empty;
full <= next_full;
end
end
end else begin
// --------------------------------------------------
// Register FIFO Status Management
//
// Full when the tail occupancy bit is 1. Empty when
// the head occupancy bit is 0.
// --------------------------------------------------
always @* begin
full = mem_used[DEPTH-1];
empty = !mem_used[0];
// ------------------------------------------
// For a single slot FIFO, reading clears the
// full status immediately.
// ------------------------------------------
if (DEPTH == 1)
full = mem_used[0] && !read;
internal_out_payload = mem[0];
// ------------------------------------------
// Writes clear empty immediately for lookahead modes.
// Note that we use in_valid instead of write to avoid
// combinational loops (in lookahead mode, qualifying
// with in_ready is meaningless).
//
// In a 1-deep FIFO, a possible combinational loop runs
// from write -> out_valid -> out_ready -> write
// ------------------------------------------
if (EMPTY_LATENCY == 0) begin
empty = !mem_used[0] && !in_valid;
if (!mem_used[0] && in_valid)
internal_out_payload = in_payload;
end
end
end
endgenerate
// --------------------------------------------------
// Avalon-ST Signals
//
// The in_ready signal is straightforward.
//
// To match memory latency when empty latency > 1,
// out_valid assertions must be delayed by one clock
// cycle.
//
// Note: out_valid deassertions must not be delayed or
// the FIFO will underflow.
// --------------------------------------------------
assign in_ready = !full;
assign internal_out_ready = out_ready || !out_valid;
generate if (EMPTY_LATENCY > 1) begin
always @(posedge clk or posedge reset) begin
if (reset)
internal_out_valid <= 0;
else begin
internal_out_valid <= !empty & ok_to_forward & ~drop_on_error;
if (read) begin
if (incremented_rd_ptr == wr_ptr)
internal_out_valid <= 1'b0;
end
end
end
end else begin
always @* begin
internal_out_valid = !empty & ok_to_forward;
end
end
endgenerate
// --------------------------------------------------
// Single Output Pipeline Stage
//
// This output pipeline stage is enabled if the FIFO's
// empty latency is set to 3 (default). It is disabled
// for all other allowed latencies.
//
// Reason: The memory outputs are unregistered, so we have to
// register the output or fmax will drop if combinatorial
// logic is present on the output datapath.
//
// Q: The Avalon-ST spec says that I have to register my outputs
// But isn't the memory counted as a register?
// A: The path from the address lookup to the memory output is
// slow. Registering the memory outputs is a good idea.
//
// The registers get packed into the memory by the fitter
// which means minimal resources are consumed (the result
// is a altsyncram with registered outputs, available on
// all modern Altera devices).
//
// This output stage acts as an extra slot in the FIFO,
// and complicates the fill level.
// --------------------------------------------------
generate if (EMPTY_LATENCY == 3) begin
always @(posedge clk or posedge reset) begin
if (reset) begin
out_valid <= 0;
out_payload <= 0;
end
else begin
if (internal_out_ready) begin
out_valid <= internal_out_valid & ok_to_forward;
out_payload <= internal_out_payload;
end
end
end
end
else begin
always @* begin
out_valid = internal_out_valid;
out_payload = internal_out_payload;
end
end
endgenerate
// --------------------------------------------------
// Fill Level
//
// The fill level is calculated from the next write
// and read pointers to avoid unnecessary latency.
//
// If the output pipeline is enabled, the fill level
// must account for it, or we'll always be off by one.
// This may, or may not be important depending on the
// application.
//
// For now, we'll always calculate the exact fill level
// at the cost of an extra adder when the output stage
// is enabled.
// --------------------------------------------------
generate if (USE_FILL_LEVEL) begin
wire [31:0] depth32;
assign depth32 = DEPTH;
always @(posedge clk or posedge reset) begin
if (reset)
fifo_fill_level <= 0;
else if (next_full & !drop_on_error)
fifo_fill_level <= depth32[ADDR_WIDTH:0];
else begin
fifo_fill_level[ADDR_WIDTH] <= 1'b0;
fifo_fill_level[ADDR_WIDTH-1 : 0] <= next_wr_ptr - next_rd_ptr;
end
end
always @* begin
fill_level = fifo_fill_level;
if (EMPTY_LATENCY == 3)
fill_level = fifo_fill_level + {{ADDR_WIDTH{1'b0}}, out_valid};
end
end
else begin
initial fill_level = 0;
end
endgenerate
generate if (USE_ALMOST_FULL_IF) begin
assign almost_full_data = (fill_level >= almost_full_threshold);
end
else
assign almost_full_data = 0;
endgenerate
generate if (USE_ALMOST_EMPTY_IF) begin
assign almost_empty_data = (fill_level <= almost_empty_threshold);
end
else
assign almost_empty_data = 0;
endgenerate
// --------------------------------------------------
// Avalon-MM Status & Control Connection Point
//
// Register map:
//
// | Addr | RW | 31 - 0 |
// | 0 | R | Fill level |
//
// The registering of this connection point means
// that there is a cycle of latency between
// reads/writes and the updating of the fill level.
// --------------------------------------------------
generate if (USE_STORE_FORWARD) begin
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
cut_through_threshold <= 0;
drop_on_error_en <= 0;
csr_readdata <= 0;
pkt_mode <= 1'b1;
end
else begin
if (csr_write) begin
if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
if(csr_address == 3'b100) begin
cut_through_threshold <= csr_writedata[23:0];
pkt_mode <= (csr_writedata[23:0] == 0);
end
if(csr_address == 3'b101)
drop_on_error_en <= csr_writedata[0];
end
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
if (csr_address == 4)
csr_readdata <= {8'b0, cut_through_threshold};
if (csr_address == 5)
csr_readdata <= {31'b0, drop_on_error_en};
end
end
end
end
else if (USE_ALMOST_FULL_IF || USE_ALMOST_EMPTY_IF) begin
assign max_fifo_size = FIFO_DEPTH - 1;
always @(posedge clk or posedge reset) begin
if (reset) begin
almost_full_threshold <= max_fifo_size[23 : 0];
almost_empty_threshold <= 0;
csr_readdata <= 0;
end
else begin
if (csr_write) begin
if(csr_address == 3'b010)
almost_full_threshold <= csr_writedata[23:0];
if(csr_address == 3'b011)
almost_empty_threshold <= csr_writedata[23:0];
end
if (csr_read) begin
csr_readdata <= 32'b0;
if (csr_address == 0)
csr_readdata <= {{(31 - ADDR_WIDTH){1'b0}}, fill_level};
if (csr_address == 2)
csr_readdata <= {8'b0, almost_full_threshold};
if (csr_address == 3)
csr_readdata <= {8'b0, almost_empty_threshold};
end
end
end
end
else begin
always @(posedge clk or posedge reset) begin
if (reset) begin
csr_readdata <= 0;
end
else if (csr_read) begin
csr_readdata <= 0;
if (csr_address == 0)
csr_readdata <= fill_level;
end
end
end
endgenerate
// --------------------------------------------------
// Store and forward logic
// --------------------------------------------------
// if the fifo gets full before the entire packet or the
// cut-threshold condition is met then start sending out
// data in order to avoid dead-lock situation
generate if (USE_STORE_FORWARD) begin
assign wait_for_threshold = (fifo_fill_level_lt_cut_through_threshold) & wait_for_pkt ;
assign wait_for_pkt = pkt_cnt_eq_zero | (pkt_cnt_eq_one & out_pkt_leave);
assign ok_to_forward = (pkt_mode ? (~wait_for_pkt | ~pkt_has_started) :
~wait_for_threshold) | fifo_too_small_r;
assign in_pkt_eop_arrive = in_valid & in_ready & in_endofpacket;
assign in_pkt_start = in_valid & in_ready & in_startofpacket;
assign in_pkt_error = in_valid & in_ready & |in_error;
assign out_pkt_sop_leave = out_valid & out_ready & out_startofpacket;
assign out_pkt_leave = out_valid & out_ready & out_endofpacket;
assign fifo_too_small = (pkt_mode ? wait_for_pkt : wait_for_threshold) & full & out_ready;
// count packets coming and going into the fifo
always @(posedge clk or posedge reset) begin
if (reset) begin
pkt_cnt <= 0;
pkt_cnt_r <= 0;
pkt_cnt_plusone <= 1;
pkt_cnt_minusone <= 0;
pkt_cnt_changed <= 0;
pkt_has_started <= 0;
sop_has_left_fifo <= 0;
fifo_too_small_r <= 0;
pkt_cnt_eq_zero <= 1'b1;
pkt_cnt_eq_one <= 1'b0;
fifo_fill_level_lt_cut_through_threshold <= 1'b1;
end
else begin
fifo_fill_level_lt_cut_through_threshold <= fifo_fill_level < cut_through_threshold;
fifo_too_small_r <= fifo_too_small;
pkt_cnt_plusone <= pkt_cnt + 1'b1;
pkt_cnt_minusone <= pkt_cnt - 1'b1;
pkt_cnt_r <= pkt_cnt;
pkt_cnt_changed <= 1'b0;
if( in_pkt_eop_arrive )
sop_has_left_fifo <= 1'b0;
else if (out_pkt_sop_leave & pkt_cnt_eq_zero )
sop_has_left_fifo <= 1'b1;
if (in_pkt_eop_arrive & ~out_pkt_leave & ~drop_on_error ) begin
pkt_cnt_changed <= 1'b1;
pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_plusone;
pkt_cnt_eq_zero <= 0;
if (pkt_cnt == 0)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
else if((~in_pkt_eop_arrive | drop_on_error) & out_pkt_leave) begin
pkt_cnt_changed <= 1'b1;
pkt_cnt <= pkt_cnt_changed ? pkt_cnt_r : pkt_cnt_minusone;
if (pkt_cnt == 1)
pkt_cnt_eq_zero <= 1'b1;
else
pkt_cnt_eq_zero <= 1'b0;
if (pkt_cnt == 2)
pkt_cnt_eq_one <= 1'b1;
else
pkt_cnt_eq_one <= 1'b0;
end
if (in_pkt_start)
pkt_has_started <= 1'b1;
else if (in_pkt_eop_arrive)
pkt_has_started <= 1'b0;
end
end
// drop on error logic
always @(posedge clk or posedge reset) begin
if (reset) begin
sop_ptr <= 0;
error_in_pkt <= 0;
end
else begin
// save the location of the SOP
if ( in_pkt_start )
sop_ptr <= wr_ptr;
// remember if error in pkt
// log error only if packet has already started
if (in_pkt_eop_arrive)
error_in_pkt <= 1'b0;
else if ( in_pkt_error & (pkt_has_started | in_pkt_start))
error_in_pkt <= 1'b1;
end
end
assign drop_on_error = drop_on_error_en & (error_in_pkt | in_pkt_error) & in_pkt_eop_arrive &
~sop_has_left_fifo & ~(out_pkt_sop_leave & pkt_cnt_eq_zero);
end
else begin
assign ok_to_forward = 1'b1;
assign drop_on_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 10:10:04 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_inverter_0_0_1/system_inverter_0_0_stub.v
// Design : system_inverter_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "inverter,Vivado 2016.4" *)
module system_inverter_0_0(x, x_not)
/* synthesis syn_black_box black_box_pad_pin="x,x_not" */;
input x;
output x_not;
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_jtag_uart_sim_scfifo_w (
// inputs:
clk,
fifo_wdata,
fifo_wr,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input [ 7: 0] fifo_wdata;
input fifo_wr;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(posedge clk)
begin
if (fifo_wr)
$write("%c", fifo_wdata);
end
assign wfifo_used = {6{1'b0}};
assign r_dat = {8{1'b0}};
assign fifo_FF = 1'b0;
assign wfifo_empty = 1'b1;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_jtag_uart_scfifo_w (
// inputs:
clk,
fifo_clear,
fifo_wdata,
fifo_wr,
rd_wfifo,
// outputs:
fifo_FF,
r_dat,
wfifo_empty,
wfifo_used
)
;
output fifo_FF;
output [ 7: 0] r_dat;
output wfifo_empty;
output [ 5: 0] wfifo_used;
input clk;
input fifo_clear;
input [ 7: 0] fifo_wdata;
input fifo_wr;
input rd_wfifo;
wire fifo_FF;
wire [ 7: 0] r_dat;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
soc_system_jtag_uart_sim_scfifo_w the_soc_system_jtag_uart_sim_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo wfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (fifo_wdata),
// .empty (wfifo_empty),
// .full (fifo_FF),
// .q (r_dat),
// .rdreq (rd_wfifo),
// .usedw (wfifo_used),
// .wrreq (fifo_wr)
// );
//
// defparam wfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// wfifo.lpm_numwords = 64,
// wfifo.lpm_showahead = "OFF",
// wfifo.lpm_type = "scfifo",
// wfifo.lpm_width = 8,
// wfifo.lpm_widthu = 6,
// wfifo.overflow_checking = "OFF",
// wfifo.underflow_checking = "OFF",
// wfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_jtag_uart_sim_scfifo_r (
// inputs:
clk,
fifo_rd,
rst_n,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_rd;
input rst_n;
reg [ 31: 0] bytes_left;
wire fifo_EF;
reg fifo_rd_d;
wire [ 7: 0] fifo_rdata;
wire new_rom;
wire [ 31: 0] num_bytes;
wire [ 6: 0] rfifo_entries;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Generate rfifo_entries for simulation
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
bytes_left <= 32'h0;
fifo_rd_d <= 1'b0;
end
else
begin
fifo_rd_d <= fifo_rd;
// decrement on read
if (fifo_rd_d)
bytes_left <= bytes_left - 1'b1;
// catch new contents
if (new_rom)
bytes_left <= num_bytes;
end
end
assign fifo_EF = bytes_left == 32'b0;
assign rfifo_full = bytes_left > 7'h40;
assign rfifo_entries = (rfifo_full) ? 7'h40 : bytes_left;
assign rfifo_used = rfifo_entries[5 : 0];
assign new_rom = 1'b0;
assign num_bytes = 32'b0;
assign fifo_rdata = 8'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_jtag_uart_scfifo_r (
// inputs:
clk,
fifo_clear,
fifo_rd,
rst_n,
t_dat,
wr_rfifo,
// outputs:
fifo_EF,
fifo_rdata,
rfifo_full,
rfifo_used
)
;
output fifo_EF;
output [ 7: 0] fifo_rdata;
output rfifo_full;
output [ 5: 0] rfifo_used;
input clk;
input fifo_clear;
input fifo_rd;
input rst_n;
input [ 7: 0] t_dat;
input wr_rfifo;
wire fifo_EF;
wire [ 7: 0] fifo_rdata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
soc_system_jtag_uart_sim_scfifo_r the_soc_system_jtag_uart_sim_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n)
);
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// scfifo rfifo
// (
// .aclr (fifo_clear),
// .clock (clk),
// .data (t_dat),
// .empty (fifo_EF),
// .full (rfifo_full),
// .q (fifo_rdata),
// .rdreq (fifo_rd),
// .usedw (rfifo_used),
// .wrreq (wr_rfifo)
// );
//
// defparam rfifo.lpm_hint = "RAM_BLOCK_TYPE=AUTO",
// rfifo.lpm_numwords = 64,
// rfifo.lpm_showahead = "OFF",
// rfifo.lpm_type = "scfifo",
// rfifo.lpm_width = 8,
// rfifo.lpm_widthu = 6,
// rfifo.overflow_checking = "OFF",
// rfifo.underflow_checking = "OFF",
// rfifo.use_eab = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_system_jtag_uart (
// inputs:
av_address,
av_chipselect,
av_read_n,
av_write_n,
av_writedata,
clk,
rst_n,
// outputs:
av_irq,
av_readdata,
av_waitrequest,
dataavailable,
readyfordata
)
/* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R101,C106,D101,D103\"" */ ;
output av_irq;
output [ 31: 0] av_readdata;
output av_waitrequest;
output dataavailable;
output readyfordata;
input av_address;
input av_chipselect;
input av_read_n;
input av_write_n;
input [ 31: 0] av_writedata;
input clk;
input rst_n;
reg ac;
wire activity;
wire av_irq;
wire [ 31: 0] av_readdata;
reg av_waitrequest;
reg dataavailable;
reg fifo_AE;
reg fifo_AF;
wire fifo_EF;
wire fifo_FF;
wire fifo_clear;
wire fifo_rd;
wire [ 7: 0] fifo_rdata;
wire [ 7: 0] fifo_wdata;
reg fifo_wr;
reg ien_AE;
reg ien_AF;
wire ipen_AE;
wire ipen_AF;
reg pause_irq;
wire [ 7: 0] r_dat;
wire r_ena;
reg r_val;
wire rd_wfifo;
reg read_0;
reg readyfordata;
wire rfifo_full;
wire [ 5: 0] rfifo_used;
reg rvalid;
reg sim_r_ena;
reg sim_t_dat;
reg sim_t_ena;
reg sim_t_pause;
wire [ 7: 0] t_dat;
reg t_dav;
wire t_ena;
wire t_pause;
wire wfifo_empty;
wire [ 5: 0] wfifo_used;
reg woverflow;
wire wr_rfifo;
//avalon_jtag_slave, which is an e_avalon_slave
assign rd_wfifo = r_ena & ~wfifo_empty;
assign wr_rfifo = t_ena & ~rfifo_full;
assign fifo_clear = ~rst_n;
soc_system_jtag_uart_scfifo_w the_soc_system_jtag_uart_scfifo_w
(
.clk (clk),
.fifo_FF (fifo_FF),
.fifo_clear (fifo_clear),
.fifo_wdata (fifo_wdata),
.fifo_wr (fifo_wr),
.r_dat (r_dat),
.rd_wfifo (rd_wfifo),
.wfifo_empty (wfifo_empty),
.wfifo_used (wfifo_used)
);
soc_system_jtag_uart_scfifo_r the_soc_system_jtag_uart_scfifo_r
(
.clk (clk),
.fifo_EF (fifo_EF),
.fifo_clear (fifo_clear),
.fifo_rd (fifo_rd),
.fifo_rdata (fifo_rdata),
.rfifo_full (rfifo_full),
.rfifo_used (rfifo_used),
.rst_n (rst_n),
.t_dat (t_dat),
.wr_rfifo (wr_rfifo)
);
assign ipen_AE = ien_AE & fifo_AE;
assign ipen_AF = ien_AF & (pause_irq | fifo_AF);
assign av_irq = ipen_AE | ipen_AF;
assign activity = t_pause | t_ena;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
pause_irq <= 1'b0;
else // only if fifo is not empty...
if (t_pause & ~fifo_EF)
pause_irq <= 1'b1;
else if (read_0)
pause_irq <= 1'b0;
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
r_val <= 1'b0;
t_dav <= 1'b1;
end
else
begin
r_val <= r_ena & ~wfifo_empty;
t_dav <= ~rfifo_full;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
begin
fifo_AE <= 1'b0;
fifo_AF <= 1'b0;
fifo_wr <= 1'b0;
rvalid <= 1'b0;
read_0 <= 1'b0;
ien_AE <= 1'b0;
ien_AF <= 1'b0;
ac <= 1'b0;
woverflow <= 1'b0;
av_waitrequest <= 1'b1;
end
else
begin
fifo_AE <= {fifo_FF,wfifo_used} <= 8;
fifo_AF <= (7'h40 - {rfifo_full,rfifo_used}) <= 8;
fifo_wr <= 1'b0;
read_0 <= 1'b0;
av_waitrequest <= ~(av_chipselect & (~av_write_n | ~av_read_n) & av_waitrequest);
if (activity)
ac <= 1'b1;
// write
if (av_chipselect & ~av_write_n & av_waitrequest)
// addr 1 is control; addr 0 is data
if (av_address)
begin
ien_AF <= av_writedata[0];
ien_AE <= av_writedata[1];
if (av_writedata[10] & ~activity)
ac <= 1'b0;
end
else
begin
fifo_wr <= ~fifo_FF;
woverflow <= fifo_FF;
end
// read
if (av_chipselect & ~av_read_n & av_waitrequest)
begin
// addr 1 is interrupt; addr 0 is data
if (~av_address)
rvalid <= ~fifo_EF;
read_0 <= ~av_address;
end
end
end
assign fifo_wdata = av_writedata[7 : 0];
assign fifo_rd = (av_chipselect & ~av_read_n & av_waitrequest & ~av_address) ? ~fifo_EF : 1'b0;
assign av_readdata = read_0 ? { {9{1'b0}},rfifo_full,rfifo_used,rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,fifo_rdata } : { {9{1'b0}},(7'h40 - {fifo_FF,wfifo_used}),rvalid,woverflow,~fifo_FF,~fifo_EF,1'b0,ac,ipen_AE,ipen_AF,{6{1'b0}},ien_AE,ien_AF };
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
readyfordata <= 0;
else
readyfordata <= ~fifo_FF;
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
// Tie off Atlantic Interface signals not used for simulation
always @(posedge clk)
begin
sim_t_pause <= 1'b0;
sim_t_ena <= 1'b0;
sim_t_dat <= t_dav ? r_dat : {8{r_val}};
sim_r_ena <= 1'b0;
end
assign r_ena = sim_r_ena;
assign t_ena = sim_t_ena;
assign t_dat = sim_t_dat;
assign t_pause = sim_t_pause;
always @(fifo_EF)
begin
dataavailable = ~fifo_EF;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// alt_jtag_atlantic soc_system_jtag_uart_alt_jtag_atlantic
// (
// .clk (clk),
// .r_dat (r_dat),
// .r_ena (r_ena),
// .r_val (r_val),
// .rst_n (rst_n),
// .t_dat (t_dat),
// .t_dav (t_dav),
// .t_ena (t_ena),
// .t_pause (t_pause)
// );
//
// defparam soc_system_jtag_uart_alt_jtag_atlantic.INSTANCE_ID = 0,
// soc_system_jtag_uart_alt_jtag_atlantic.LOG2_RXFIFO_DEPTH = 6,
// soc_system_jtag_uart_alt_jtag_atlantic.LOG2_TXFIFO_DEPTH = 6,
// soc_system_jtag_uart_alt_jtag_atlantic.SLD_AUTO_INSTANCE_INDEX = "YES";
//
// always @(posedge clk or negedge rst_n)
// begin
// if (rst_n == 0)
// dataavailable <= 0;
// else
// dataavailable <= ~fifo_EF;
// end
//
//
//synthesis read_comments_as_HDL off
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
//*******************************************************************************************
//Author: ZhiYoong Foo ([email protected])
//Last Modified: Feb 25 2014
//Description: MBUS Reset Detector (Active Low)
// Custom Block
//Update History: Feb 25 2014 - First commit
//*******************************************************************************************
module rstdtctr
(
//Power Domain
//Always On
//Input
//Output
RESETn
);
output reg RESETn; //Active Low
initial begin
RESETn <= 1'b0;
`RESET_TIME;
RESETn <= 1'b1;
end
endmodule // rstdtctr
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 07/01/2009
This optional block is used for two purposes:
1) Relay response information back to the host typically in ST->MM mode.
This information is 'actual bytes transferred', 'error', and 'early termination'.
2) Relay response and interrupt information back to a prefetching master block
that will write the contents back to memory. Interrupt information is also passed
since the interrupt needs to occur when the prefetching master block overwrites
the descriptor in main memory and not when the event occurs. The host needs to read
the interrupt condition out of memory so it could potentially get out of sync if
the interrupt information wasn't buffered and delayed.
This block has three response port options: MM slave, ST source, and disabled.
When you don't need access to response information (MM->MM or MM->ST) or interrupts in
the case of a prefetching descriptor master then you can safely disable the port.
By disabling the port you will not consume any logic resources or on-chip memory blocks.
When the source port is enabled bit 52 of the data stream represents the "descriptor full"
condition. The descriptor prefetching master can use this signal to perform pipelined reads
without having to worry about flow control (since there is room for an entire descriptor to be
written). This is benefical as apposed to performing descriptor reads, buffering the data, then
writting it out to the descriptor buffer block.
Version 1.0
1.0 - If you attempt to use the wrong response port type you will be issued a warning
but allowed to generate. This is because in some cases you may not need the typical
behavior. For example if you perform MM->MM transfers with some streaming IP between
the read and write masters you still might need access to error bits. Likewise
if you don't enable the streaming sink port while using a descriptor pre-fetching block
you may not care if you get interrupted early and want to use the CSR block for interrupts
instead.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module response_block (
clk,
reset,
mm_response_readdata,
mm_response_read,
mm_response_address,
mm_response_byteenable,
mm_response_waitrequest,
src_response_data,
src_response_valid,
src_response_ready,
sw_reset,
response_watermark,
response_fifo_full,
response_fifo_empty,
done_strobe,
actual_bytes_transferred,
error,
early_termination,
transfer_complete_IRQ_mask,
error_IRQ_mask,
early_termination_IRQ_mask,
descriptor_buffer_full
);
parameter RESPONSE_PORT = 0; // when disabled all the outputs will be disconnected by the component wrapper
parameter FIFO_DEPTH = 256; // needs to be double the descriptor FIFO depth
parameter FIFO_DEPTH_LOG2 = 8;
localparam FIFO_WIDTH = (RESPONSE_PORT == 0)? 41 : 51; // when 'RESPONSE_PORT' is 1 then the response port is set to streaming and must pass the interrupt masks as well
input clk;
input reset;
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address; // only have 2 addresses
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
output wire [255:0] src_response_data; // not going to use all these bits, the remainder will be grounded
output wire src_response_valid;
input src_response_ready;
input sw_reset;
output wire [15:0] response_watermark;
output wire response_fifo_full;
output wire response_fifo_empty;
input done_strobe;
input [31:0] actual_bytes_transferred;
input [7:0] error;
input early_termination;
// all of these signals are only used the ST source response port since the pre-fetching master component will handle the interrupt generation as apposed to the CSR block
input transfer_complete_IRQ_mask;
input [7:0] error_IRQ_mask;
input early_termination_IRQ_mask;
input descriptor_buffer_full; // handy signal for the prefetching master to use so that it known when to blast a new descriptor into the dispatcher
/* internal signals and registers */
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_full;
wire fifo_empty;
wire fifo_read;
wire [FIFO_WIDTH-1:0] fifo_input;
wire [FIFO_WIDTH-1:0] fifo_output;
generate
if (RESPONSE_PORT == 0) // slave port used for response data
begin
assign fifo_input = {early_termination, error, actual_bytes_transferred};
assign fifo_read = (mm_response_read == 1) & (fifo_empty == 0) & (mm_response_address == 1) & (mm_response_byteenable[3] == 1); // reading from the upper byte (byte offset 7) pops the fifo
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset),
.sclr (sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
// either actual bytes transfered when address == 0 or {zero padding, early_termination, error[7:0]} when address = 1
assign mm_response_readdata = (mm_response_address == 0)? fifo_output[31:0] : {{23{1'b0}}, fifo_output[40:32]};
assign mm_response_waitrequest = fifo_empty;
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no streaming port so ground all of its outputs
assign src_response_data = 0;
assign src_response_valid = 0;
end
else if (RESPONSE_PORT == 1) // streaming source port used for response data (prefetcher will catch this data)
begin
assign fifo_input = {early_termination_IRQ_mask, error_IRQ_mask, transfer_complete_IRQ_mask, early_termination, error, actual_bytes_transferred};
assign fifo_read = (fifo_empty == 0) & (src_response_ready == 1);
scfifo the_response_FIFO (
.clock (clk),
.aclr (reset | sw_reset),
.data (fifo_input),
.wrreq (done_strobe),
.rdreq (fifo_read),
.q (fifo_output),
.full (fifo_full),
.empty (fifo_empty),
.usedw (fifo_used)
);
defparam the_response_FIFO.lpm_width = FIFO_WIDTH;
defparam the_response_FIFO.lpm_numwords = FIFO_DEPTH;
defparam the_response_FIFO.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_response_FIFO.lpm_showahead = "ON";
defparam the_response_FIFO.use_eab = "ON";
defparam the_response_FIFO.overflow_checking = "OFF";
defparam the_response_FIFO.underflow_checking = "OFF";
defparam the_response_FIFO.add_ram_output_register = "ON";
defparam the_response_FIFO.lpm_type = "scfifo";
assign src_response_data = {{204{1'b0}}, descriptor_buffer_full, fifo_output}; // zero padding the upper bits, also sending out the descriptor buffer full signal to simplify the throttling in the prefetching master (bit 52)
assign src_response_valid = (fifo_empty == 0);
assign response_watermark = {{(16-(FIFO_DEPTH_LOG2+1)){1'b0}}, fifo_full, fifo_used}; // zero padding plus the 'true used' FIFO amount;
assign response_fifo_full = fifo_full;
assign response_fifo_empty = fifo_empty;
// no slave port so ground all of its outputs
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
end
else // no response port so grounding all outputs
begin
assign fifo_input = 0;
assign fifo_output = 0;
assign mm_response_readdata = 0;
assign mm_response_waitrequest = 0;
assign src_response_data = 0;
assign src_response_valid = 0;
assign response_watermark = 0;
assign response_fifo_full = 0;
assign response_fifo_empty = 0;
end
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Wrapper for Xilinx Spartan-6 DSP48 Block //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// DSP block configured as an N-bit adder and substractor //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module xs6_addsub_n #(
parameter WIDTH=32
)(
input [WIDTH-1:0] i_a,
input [WIDTH-1:0] i_b,
input i_cin,
input i_sub,
output [WIDTH-1:0] o_sum,
output o_co
);
wire [7:0] opmode;
wire [47:0] in_a, in_b;
wire [47:0] out;
assign opmode = {i_sub, 1'd0, i_cin, 1'd0, 2'd3, 2'd3 };
assign in_a = {{48-WIDTH{1'd0}}, i_a};
assign in_b = {{48-WIDTH{1'd0}}, i_b};
assign o_sum = out[WIDTH-1:0];
assign o_co = out[WIDTH];
DSP48A1 #(
// Enable registers
.A1REG ( 0 ),
.B0REG ( 0 ),
.B1REG ( 0 ),
.CARRYINREG ( 0 ),
.CARRYOUTREG ( 0 ),
.CREG ( 0 ),
.DREG ( 0 ),
.MREG ( 0 ),
.OPMODEREG ( 0 ),
.PREG ( 0 ),
.CARRYINSEL ("OPMODE5" ),
.RSTTYPE ( "SYNC" )
)
u_dsp48 (
// Outputs
.BCOUT ( ),
.CARRYOUT ( ),
.CARRYOUTF ( ),
.M ( ),
.P ( out ),
.PCOUT ( ),
// Inputs
.CLK ( 1'd0 ),
.A ( in_b[35:18] ),
.B ( in_b[17:00] ),
.C ( in_a ),
.D ( {6'd0, in_b[47:36]} ),
.CARRYIN ( 1'd0 ), // uses opmode bit 5 for carry in
.OPMODE ( opmode ),
.PCIN ( 48'd0 ),
// Clock enables
.CEA ( 1'd1 ),
.CEB ( 1'd1 ),
.CEC ( 1'd1 ),
.CED ( 1'd1 ),
.CEM ( 1'd1 ),
.CEP ( 1'd1 ),
.CECARRYIN ( 1'd1 ),
.CEOPMODE ( 1'd1 ),
// Register Resets
.RSTA ( 1'd0 ),
.RSTB ( 1'd0 ),
.RSTC ( 1'd0 ),
.RSTCARRYIN ( 1'd0 ),
.RSTD ( 1'd0 ),
.RSTM ( 1'd0 ),
.RSTOPMODE ( 1'd0 ),
.RSTP ( 1'd0 )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFINV_8_V
`define SKY130_FD_SC_MS__BUFINV_8_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__bufinv_8 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__bufinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFINV_8_V
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_dynamic_align( clock, resetn,
dataa, datab, result,
valid_in, valid_out, stall_in, stall_out,
enable);
// This module performs dynamic alignment of inputs for adder trees only. Dynamic means that both inputs can be shifted to their
// appropriate position, the larger one is shifted left, the smaller one is shifted right.
// To do this correctly, both the left and the right inputs are compared using both the exponent and the mantissa.
// Leading zeroes in the mantissa affect the exponent.
//
// Another difference from regular alignment module is that the input mantissa is 28 bits. This is to deal with the fact that the
// input may be in overflow as a result of addition that preceeded this module.
//
// Note that this module is not IEEE754 compliant because:
// - it removes sticky bits
// - works only on finite math (no infinities or nans are supported)
// - may flush denorms to zero
//
parameter HIGH_CAPACITY = 0;
parameter HIGH_LATENCY = 0;
input clock, resetn;
input [37:0] dataa;
input [37:0] datab;
output [37:0] result;
input enable, valid_in, stall_in;
output valid_out, stall_out;
wire [27:0] input_a_mantissa = dataa[27:0];
wire [8:0] input_a_exponent = dataa[36:28];
wire input_a_sign = dataa[37];
wire [27:0] input_b_mantissa = datab[27:0];
wire [8:0] input_b_exponent = datab[36:28];
wire input_b_sign = datab[37];
// This module aligns two floating point input values such that their exponents are equal,
// permitting a proper addition of the two numbers.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c4_valid;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c5_valid;
wire c1_enable;
wire c2_enable;
wire c3_enable;
wire c4_enable;
wire c5_enable;
wire c1_stall;
wire c2_stall;
wire c3_stall;
wire c4_stall;
wire c5_stall;
// Cycle 1 - compare input values by looking at their exponents and mantissas. To do this, first adjust the
// exponents by counting leading zeroes.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c1_mantissa_left;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c1_mantissa_right;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c1_exponent_left;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c1_exponent_right;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c1_exp_difference;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [4:0] c1_lead_zeroes;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_sign_left;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_sign_right;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_direction;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_left_clear;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_right_clear;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c1_increment_left, c1_increment_right;
assign c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
wire [4:0] left_count;
wire [4:0] right_count;
wire left_clear, right_clear;
acl_fp_custom_clz left(.mantissa(input_a_mantissa[26:0]), .result(left_count), .all_zero(left_clear));
acl_fp_custom_clz right(.mantissa(input_b_mantissa[26:0]), .result(right_count), .all_zero(right_clear));
wire [8:0] diff_a_b = {1'b0, input_a_exponent} - {1'b0, input_b_exponent} +
{{8{~input_a_mantissa[27] & input_b_mantissa[27]}}, input_a_mantissa[27] ^ input_b_mantissa[27]};
wire [8:0] diff_b_a = {1'b0, input_b_exponent} - {1'b0, input_a_exponent} +
{{8{~input_b_mantissa[27] & input_a_mantissa[27]}}, input_a_mantissa[27] ^ input_b_mantissa[27]};
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_valid <= 1'b0;
c1_mantissa_left <= 27'dx;
c1_mantissa_right <= 27'dx;
c1_exponent_left <= 9'dx;
c1_exponent_right <= 9'dx;
c1_sign_left <= 1'bx;
c1_sign_right <= 1'bx;
c1_exp_difference <= 9'dx;
c1_direction <= 1'bx;
c1_left_clear <= 1'bx;
c1_right_clear <= 1'bx;
c1_increment_left <= 1'bx;
c1_increment_right <= 1'bx;
c1_lead_zeroes <= 5'dx;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
// Adjust exponents for overflow.
c1_increment_left <= input_a_mantissa[27];
c1_increment_right <= input_b_mantissa[27];
// Delay this computation by 2 cycles.
// c1_exponent_left <= input_a_exponent + {1'b0, input_a_mantissa[27]};
// c1_exponent_right <= input_b_exponent + {1'b0, input_b_mantissa[27]};
c1_exponent_left <= input_a_exponent;
c1_exponent_right <= input_b_exponent;
if (diff_a_b[8])
begin
// Adjust mantissas for overflow.
c1_mantissa_right <= input_a_mantissa[27] ? input_a_mantissa[27:1] : input_a_mantissa[26:0];
c1_mantissa_left <= input_b_mantissa[27] ? input_b_mantissa[27:1] : input_b_mantissa[26:0];
// Copy signs over
c1_sign_right <= input_a_sign;
c1_sign_left <= input_b_sign;
end
else
begin
// Adjust mantissas for overflow.
c1_mantissa_left <= input_a_mantissa[27] ? input_a_mantissa[27:1] : input_a_mantissa[26:0];
c1_mantissa_right <= input_b_mantissa[27] ? input_b_mantissa[27:1] : input_b_mantissa[26:0];
// Copy signs over
c1_sign_left <= input_a_sign;
c1_sign_right <= input_b_sign;
end
// Count leading zeroes.
c1_lead_zeroes <= diff_a_b[8] ? ({5{~input_b_mantissa[27]}} & right_count) : ({5{~input_a_mantissa[27]}} & left_count);
c1_left_clear <= left_clear & ~input_a_mantissa[27];
c1_right_clear <= right_clear & ~input_b_mantissa[27];
// Exponent difference.
c1_exp_difference <= diff_a_b[8] ? diff_b_a : diff_a_b;
c1_direction <= diff_a_b[8];
end
end
// Cycle 2 - In this stage we have to decide by how much to shift each number.
// one will be shifted to the left, the other to the right.
// The first level of comparisons is the exponent difference combined with the number of leading zeroes.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c2_mantissa_left;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c2_mantissa_right;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c2_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_sign_left;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_sign_right;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c2_increment_exp;
assign c2_enable = (HIGH_CAPACITY == 1) ? (~c2_valid | ~c2_stall) : enable;
assign c1_stall = c2_valid & c2_stall;
reg [4:0] c2_exp_shift_left; // left will be the greater value
reg [4:0] c2_exp_shift_right; // right will be the smaller value
//wire c2_comp_lz_to_diff = c1_lead_zeroes >= c1_exp_difference;
//wire [8:0] c2_v = c2_comp_lz_to_diff ? c1_exp_difference : {3'd0, c1_lead_zeroes};
//wire [8:0] c2_v_minus_diff = c1_exp_difference - c2_v;
wire [8:0] c2_compare = c1_exp_difference - {1'b0, c1_lead_zeroes};
wire [8:0] c2_v = c2_compare[8] ? c1_exp_difference : {3'd0, c1_lead_zeroes};
wire [4:0] c2_v_minus_diff = (c2_compare[4:0] | {5{|c2_compare[7:5]}}) & {5{~c2_compare[8]}};
wire c2_left_is_zero = c1_left_clear;
wire c2_right_is_zero = c1_right_clear;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c2_mantissa_left <= 27'dx;
c2_mantissa_right <= 27'dx;
c2_exponent <= 9'dx;
c2_sign_left <= 1'bx;
c2_sign_right <= 1'bx;
c2_exp_shift_left <= 5'dx;
c2_exp_shift_right <= 5'dx;
c2_increment_exp <= 1'bx;
c2_valid <= 1'b0;
end
else if (c2_enable)
begin
// To determine which way to shift which input, we must compare the values. To do this, we must first shift both values to
// have the same exponent, accounting for the leading zeroes in each number.
// Now, in order to do this efficiently, we must carefully pick which number to shift left and which to shift right.
c2_valid <= c1_valid;
// To keep things clean, the right number will be shifted right, the left number will be shifed left.
// So, pick them carefully now for shifting in the following stages.
// The most accurate solution here is to shift the value with the bigger exponent to the left as much as possible, no exceeding the
// exponent difference. Then, if the difference is not large enough, shift the value with the smaller exponent to the right,
// bringing its exponent value up.
// c1_direction = 1 means exponent of B is greater than exponent of A, so B is shifted left, A is shifted right.
// Otherwise A is shifted left and B is shifted right.
c2_mantissa_left <= c1_mantissa_left;
c2_mantissa_right <= c1_mantissa_right;
c2_sign_left <= c1_sign_left;
c2_sign_right <= c1_sign_right;
if ((c2_left_is_zero) || (c2_right_is_zero))
begin
// both mantissas are clear, so zero the exponent.
c2_exponent <= ({9{~c2_left_is_zero}} & c1_exponent_left) | ({9{~c2_right_is_zero}} & c1_exponent_right);
c2_increment_exp <= (~c2_left_is_zero & c1_increment_left) | (~c2_right_is_zero & c1_increment_right);
c2_exp_shift_left <= 5'd0;
c2_exp_shift_right <= 5'd0;
end
else
begin
c2_exp_shift_left <= c2_v[4:0];
c2_exp_shift_right <= c2_v_minus_diff;//{5{|c2_v_minus_diff[8:5]}} | c2_v_minus_diff[4:0];
if (c1_direction)
begin
// input B had a greater exponent than the input A, so shift it left. Also, swap inputs A and B (B=> left, A=>right)
c2_exponent <= c1_exponent_right;
c2_increment_exp <= c1_increment_right;
end
else
begin
// input A had a greater exponent than the input B, so shift it left. (A=> left, B=>right)
c2_exponent <= c1_exponent_left;
c2_increment_exp <= c1_increment_left;
end
end
end
end
// Cycle 3 - shift inputs as needed. Reduce the exponent by the c2_exp_shift_left value.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c3_mantissa_left;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c3_mantissa_right;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c3_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_sign_left;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c3_sign_right;
assign c3_enable = (HIGH_CAPACITY == 1) ? (~c3_valid | ~c3_stall) : enable;
assign c2_stall = c3_valid & c3_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c3_mantissa_left <= 27'dx;
c3_mantissa_right <= 27'dx;
c3_exponent <= 9'dx;
c3_sign_left <= 1'bx;
c3_sign_right <= 1'bx;
c3_valid <= 1'b0;
end
else if (c3_enable)
begin
c3_mantissa_left <= c2_mantissa_left << c2_exp_shift_left;
c3_mantissa_right <= c2_mantissa_right >> c2_exp_shift_right;
c3_exponent <= c2_exponent - {1'b0, c2_exp_shift_left} + c2_increment_exp;
c3_sign_left <= c2_sign_left;
c3_sign_right <= c2_sign_right;
c3_valid <= c2_valid;
end
end
// Cycle 4 - final shift of inputs.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c4_mantissa_left;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [26:0] c4_mantissa_right;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c4_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c4_sign_left;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c4_sign_right;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c4_do_subtraction;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c4_swap_inputs;
assign c4_enable = (HIGH_CAPACITY == 1) ? (~c4_valid | ~c4_stall) : enable;
assign c3_stall = c4_valid & c4_stall;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c4_mantissa_left <= 27'dx;
c4_mantissa_right <= 27'dx;
c4_exponent <= 9'dx;
c4_sign_left <= 1'bx;
c4_sign_right <= 1'bx;
c4_do_subtraction <= 1'bx;
c4_swap_inputs <= 1'bx;
c4_valid <= 1'b0;
end
else if (c4_enable)
begin
c4_mantissa_left <= c3_mantissa_left;
c4_mantissa_right <= c3_mantissa_right;
c4_exponent <= c3_exponent;
c4_sign_left <= c3_sign_left;
c4_sign_right <= c3_sign_right;
c4_valid <= c3_valid;
c4_do_subtraction <= c3_sign_left ^ c3_sign_right;
c4_swap_inputs <= (c3_mantissa_right > c3_mantissa_left);
end
end
// Cycle 5 - Perform addition/subtraction.
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [27:0] c5_mantissa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [8:0] c5_exponent;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg c5_sign;
assign c5_enable = (HIGH_CAPACITY == 1) ? (~c5_valid | ~c5_stall) : enable;
assign c4_stall = c5_valid & c5_stall;
wire [27:0] c5_op_ab = ({28{c4_do_subtraction & c4_swap_inputs}} ^ {1'b0,c4_mantissa_left}) + ({28{c4_do_subtraction & ~c4_swap_inputs}} ^ {1'b0, c4_mantissa_right}) + c4_do_subtraction;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c5_mantissa <= 28'dx;
c5_exponent <= 9'dx;
c5_sign <= 1'bx;
c5_valid <= 1'b0;
end
else if (c5_enable)
begin
c5_mantissa <= c5_op_ab;
c5_sign <= c4_swap_inputs ? c4_sign_right : c4_sign_left;
c5_exponent <= c4_exponent;
c5_valid <= c4_valid;
end
end
assign valid_out = c5_valid;
assign c5_stall = stall_in;
assign result = {c5_sign, c5_exponent, c5_mantissa};
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2005,2006 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
`include "../../firmware/include/fpga_regs_common.v"
`include "../../firmware/include/fpga_regs_standard.v"
module io_pins
( inout wire [15:0] io_0, inout wire [15:0] io_1,
input wire [15:0] reg_0, input wire [15:0] reg_1,
input clock, input rx_reset, input tx_reset,
input [6:0] serial_addr, input [31:0] serial_data, input serial_strobe);
reg [15:0] io_0_oe,io_1_oe;
bidir_reg bidir_reg_0 (.tristate(io_0),.oe(io_0_oe),.reg_val(reg_0));
bidir_reg bidir_reg_1 (.tristate(io_1),.oe(io_1_oe),.reg_val(reg_1));
// Upper 16 bits are mask for lower 16
always @(posedge clock)
if(serial_strobe)
case(serial_addr)
`FR_OE_0 : io_0_oe
<= #1 (io_0_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
`FR_OE_1 : io_1_oe
<= #1 (io_1_oe & ~serial_data[31:16]) | (serial_data[15:0] & serial_data[31:16] );
endcase // case(serial_addr)
endmodule // io_pins
|
//*****************************************************************************
// (c) Copyright 2009-10 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Application : MIG
// \ \ Filename : memc_wrapper.v
// / / Date Last Modified : $Date: 2010/08/
// /___/ /\ Date Created : Mon Mar 2 2009
// \ \ / \
// \___\/\___\
//
//Device : Spartan-6
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : This is a static top level module instantiating the mcb_ui_top,
// which provides interface to all the standard as well as AXI ports.
// This module memc_wrapper provides interface to only the standard ports.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ns/1ps
module memc_wrapper #
(
parameter C_MEMCLK_PERIOD = 2500,
parameter C_P0_MASK_SIZE = 4,
parameter C_P0_DATA_PORT_SIZE = 32,
parameter C_P1_MASK_SIZE = 4,
parameter C_P1_DATA_PORT_SIZE = 32,
parameter C_PORT_ENABLE = 6'b111111,
parameter C_PORT_CONFIG = "B128",
parameter C_MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// The following parameter reflects the GUI selection of the Arbitration algorithm.
// Zero value corresponds to round robin algorithm and one to custom selection.
// The parameter is used to calculate the arbitration time slot parameters.
parameter C_ARB_ALGORITHM = 0,
parameter C_ARB_NUM_TIME_SLOTS = 12,
parameter C_ARB_TIME_SLOT_0 = 18'o012345,
parameter C_ARB_TIME_SLOT_1 = 18'o123450,
parameter C_ARB_TIME_SLOT_2 = 18'o234501,
parameter C_ARB_TIME_SLOT_3 = 18'o345012,
parameter C_ARB_TIME_SLOT_4 = 18'o450123,
parameter C_ARB_TIME_SLOT_5 = 18'o501234,
parameter C_ARB_TIME_SLOT_6 = 18'o012345,
parameter C_ARB_TIME_SLOT_7 = 18'o123450,
parameter C_ARB_TIME_SLOT_8 = 18'o234501,
parameter C_ARB_TIME_SLOT_9 = 18'o345012,
parameter C_ARB_TIME_SLOT_10 = 18'o450123,
parameter C_ARB_TIME_SLOT_11 = 18'o501234,
parameter C_MEM_TRAS = 45000,
parameter C_MEM_TRCD = 12500,
parameter C_MEM_TREFI = 7800,
parameter C_MEM_TRFC = 127500,
parameter C_MEM_TRP = 12500,
parameter C_MEM_TWR = 15000,
parameter C_MEM_TRTP = 7500,
parameter C_MEM_TWTR = 7500,
parameter C_NUM_DQ_PINS = 8,
parameter C_MEM_TYPE = "DDR3",
parameter C_MEM_DENSITY = "512M",
parameter C_MEM_BURST_LEN = 8,
parameter C_MEM_CAS_LATENCY = 4,
parameter C_MEM_ADDR_WIDTH = 13,
parameter C_MEM_BANKADDR_WIDTH = 3,
parameter C_MEM_NUM_COL_BITS = 11,
parameter C_MEM_DDR3_CAS_LATENCY = 7,
parameter C_MEM_MOBILE_PA_SR = "FULL",
parameter C_MEM_DDR1_2_ODS = "FULL",
parameter C_MEM_DDR3_ODS = "DIV6",
parameter C_MEM_DDR2_RTT = "50OHMS",
parameter C_MEM_DDR3_RTT = "DIV2",
parameter C_MEM_MDDR_ODS = "FULL",
parameter C_MEM_DDR2_DIFF_DQS_EN = "YES",
parameter C_MEM_DDR2_3_PA_SR = "OFF",
parameter C_MEM_DDR3_CAS_WR_LATENCY = 5,
parameter C_MEM_DDR3_AUTO_SR = "ENABLED",
parameter C_MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL",
parameter C_MEM_DDR3_DYN_WRT_ODT = "OFF",
parameter C_MC_CALIB_BYPASS = "NO",
parameter LDQSP_TAP_DELAY_VAL = 0,
parameter UDQSP_TAP_DELAY_VAL = 0,
parameter LDQSN_TAP_DELAY_VAL = 0,
parameter UDQSN_TAP_DELAY_VAL = 0,
parameter DQ0_TAP_DELAY_VAL = 0,
parameter DQ1_TAP_DELAY_VAL = 0,
parameter DQ2_TAP_DELAY_VAL = 0,
parameter DQ3_TAP_DELAY_VAL = 0,
parameter DQ4_TAP_DELAY_VAL = 0,
parameter DQ5_TAP_DELAY_VAL = 0,
parameter DQ6_TAP_DELAY_VAL = 0,
parameter DQ7_TAP_DELAY_VAL = 0,
parameter DQ8_TAP_DELAY_VAL = 0,
parameter DQ9_TAP_DELAY_VAL = 0,
parameter DQ10_TAP_DELAY_VAL = 0,
parameter DQ11_TAP_DELAY_VAL = 0,
parameter DQ12_TAP_DELAY_VAL = 0,
parameter DQ13_TAP_DELAY_VAL = 0,
parameter DQ14_TAP_DELAY_VAL = 0,
parameter DQ15_TAP_DELAY_VAL = 0,
parameter C_CALIB_SOFT_IP = "TRUE",
parameter C_SIMULATION = "FALSE",
parameter C_SKIP_IN_TERM_CAL = 1'b0,
parameter C_SKIP_DYNAMIC_CAL = 1'b0,
parameter C_MC_CALIBRATION_MODE = "CALIBRATION",
parameter C_MC_CALIBRATION_DELAY = "HALF"
)
(
// Raw Wrapper Signals
input sysclk_2x,
input sysclk_2x_180,
input pll_ce_0,
input pll_ce_90,
input pll_lock,
input async_rst,
input mcb_drp_clk,
output [C_MEM_ADDR_WIDTH-1:0] mcbx_dram_addr,
output [C_MEM_BANKADDR_WIDTH-1:0] mcbx_dram_ba,
output mcbx_dram_ras_n,
output mcbx_dram_cas_n,
output mcbx_dram_we_n,
output mcbx_dram_cke,
output mcbx_dram_clk,
output mcbx_dram_clk_n,
inout [C_NUM_DQ_PINS-1:0] mcbx_dram_dq,
inout mcbx_dram_dqs,
inout mcbx_dram_dqs_n,
inout mcbx_dram_udqs,
inout mcbx_dram_udqs_n,
output mcbx_dram_udm,
output mcbx_dram_ldm,
output mcbx_dram_odt,
output mcbx_dram_ddr3_rst,
inout mcbx_rzq,
inout mcbx_zio,
output calib_done,
input selfrefresh_enter,
output selfrefresh_mode,
// This new memc_wrapper shows all the six logical static user ports. The port
// configuration parameter and the port enable parameter are the ones that
// determine the active and non-active ports. The following list shows the
// default active ports for each port configuration.
//
// Config 1: "B32_B32_X32_X32_X32_X32"
// User port 0 --> 32 bit, User port 1 --> 32 bit
// User port 2 --> 32 bit, User port 3 --> 32 bit
// User port 4 --> 32 bit, User port 5 --> 32 bit
// Config 2: "B32_B32_B32_B32"
// User port 0 --> 32 bit
// User port 1 --> 32 bit
// User port 2 --> 32 bit
// User port 3 --> 32 bit
// Config 3: "B64_B32_B3"
// User port 0 --> 64 bit
// User port 1 --> 32 bit
// User port 2 --> 32 bit
// Config 4: "B64_B64"
// User port 0 --> 64 bit
// User port 1 --> 64 bit
// Config 5 "B128"
// User port 0 --> 128 bit
// User Port-0 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
input p0_cmd_clk,
input p0_cmd_en,
input [2:0] p0_cmd_instr,
input [5:0] p0_cmd_bl,
input [29:0] p0_cmd_byte_addr,
output p0_cmd_full,
output p0_cmd_empty,
// User Port-0 data write interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
input p0_wr_clk,
input p0_wr_en,
input [C_P0_MASK_SIZE-1:0] p0_wr_mask,
input [C_P0_DATA_PORT_SIZE-1:0] p0_wr_data,
output p0_wr_full,
output [6:0] p0_wr_count,
output p0_wr_empty,
output p0_wr_underrun,
output p0_wr_error,
// User Port-0 data read interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3, Config-4 and Config-5
input p0_rd_clk,
input p0_rd_en,
output [C_P0_DATA_PORT_SIZE-1:0] p0_rd_data,
output p0_rd_empty,
output [6:0] p0_rd_count,
output p0_rd_full,
output p0_rd_overflow,
output p0_rd_error,
// User Port-1 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
input p1_cmd_clk,
input p1_cmd_en,
input [2:0] p1_cmd_instr,
input [5:0] p1_cmd_bl,
input [29:0] p1_cmd_byte_addr,
output p1_cmd_full,
output p1_cmd_empty,
// User Port-1 data write interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
input p1_wr_clk,
input p1_wr_en,
input [C_P1_MASK_SIZE-1:0] p1_wr_mask,
input [C_P1_DATA_PORT_SIZE-1:0] p1_wr_data,
output p1_wr_full,
output [6:0] p1_wr_count,
output p1_wr_empty,
output p1_wr_underrun,
output p1_wr_error,
// User Port-1 data read interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2, Config-3 and Config-4
input p1_rd_clk,
input p1_rd_en,
output [C_P1_DATA_PORT_SIZE-1:0] p1_rd_data,
output p1_rd_empty,
output [6:0] p1_rd_count,
output p1_rd_full,
output p1_rd_overflow,
output p1_rd_error,
// User Port-2 command interface will be active only when the port is enabled in
// the port configurations Config-1, Config-2 and Config-3
input p2_cmd_clk,
input p2_cmd_en,
input [2:0] p2_cmd_instr,
input [5:0] p2_cmd_bl,
input [29:0] p2_cmd_byte_addr,
output p2_cmd_full,
output p2_cmd_empty,
// User Port-2 data write interface will be active only when the port is enabled in
// the port configurations Config-1 write direction, Config-2 and Config-3
input p2_wr_clk,
input p2_wr_en,
input [3:0] p2_wr_mask,
input [31:0] p2_wr_data,
output p2_wr_full,
output [6:0] p2_wr_count,
output p2_wr_empty,
output p2_wr_underrun,
output p2_wr_error,
// User Port-2 data read interface will be active only when the port is enabled in
// the port configurations Config-1 read direction, Config-2 and Config-3
input p2_rd_clk,
input p2_rd_en,
output [31:0] p2_rd_data,
output p2_rd_empty,
output [6:0] p2_rd_count,
output p2_rd_full,
output p2_rd_overflow,
output p2_rd_error,
// User Port-3 command interface will be active only when the port is enabled in
// the port configurations Config-1 and Config-2
input p3_cmd_clk,
input p3_cmd_en,
input [2:0] p3_cmd_instr,
input [5:0] p3_cmd_bl,
input [29:0] p3_cmd_byte_addr,
output p3_cmd_full,
output p3_cmd_empty,
// User Port-3 data write interface will be active only when the port is enabled in
// the port configurations Config-1 write direction and Config-2
input p3_wr_clk,
input p3_wr_en,
input [3:0] p3_wr_mask,
input [31:0] p3_wr_data,
output p3_wr_full,
output [6:0] p3_wr_count,
output p3_wr_empty,
output p3_wr_underrun,
output p3_wr_error,
// User Port-3 data read interface will be active only when the port is enabled in
// the port configurations Config-1 read direction and Config-2
input p3_rd_clk,
input p3_rd_en,
output [31:0] p3_rd_data,
output p3_rd_empty,
output [6:0] p3_rd_count,
output p3_rd_full,
output p3_rd_overflow,
output p3_rd_error,
// User Port-4 command interface will be active only when the port is enabled in
// the port configuration Config-1
input p4_cmd_clk,
input p4_cmd_en,
input [2:0] p4_cmd_instr,
input [5:0] p4_cmd_bl,
input [29:0] p4_cmd_byte_addr,
output p4_cmd_full,
output p4_cmd_empty,
// User Port-4 data write interface will be active only when the port is enabled in
// the port configuration Config-1 write direction
input p4_wr_clk,
input p4_wr_en,
input [3:0] p4_wr_mask,
input [31:0] p4_wr_data,
output p4_wr_full,
output [6:0] p4_wr_count,
output p4_wr_empty,
output p4_wr_underrun,
output p4_wr_error,
// User Port-4 data read interface will be active only when the port is enabled in
// the port configuration Config-1 read direction
input p4_rd_clk,
input p4_rd_en,
output [31:0] p4_rd_data,
output p4_rd_empty,
output [6:0] p4_rd_count,
output p4_rd_full,
output p4_rd_overflow,
output p4_rd_error,
// User Port-5 command interface will be active only when the port is enabled in
// the port configuration Config-1
input p5_cmd_clk,
input p5_cmd_en,
input [2:0] p5_cmd_instr,
input [5:0] p5_cmd_bl,
input [29:0] p5_cmd_byte_addr,
output p5_cmd_full,
output p5_cmd_empty,
// User Port-5 data write interface will be active only when the port is enabled in
// the port configuration Config-1 write direction
input p5_wr_clk,
input p5_wr_en,
input [3:0] p5_wr_mask,
input [31:0] p5_wr_data,
output p5_wr_full,
output [6:0] p5_wr_count,
output p5_wr_empty,
output p5_wr_underrun,
output p5_wr_error,
// User Port-5 data read interface will be active only when the port is enabled in
// the port configuration Config-1 read direction
input p5_rd_clk,
input p5_rd_en,
output [31:0] p5_rd_data,
output p5_rd_empty,
output [6:0] p5_rd_count,
output p5_rd_full,
output p5_rd_overflow,
output p5_rd_error
);
localparam C_MC_CALIBRATION_CLK_DIV = 1;
localparam C_MEM_TZQINIT_MAXCNT = 10'd512 + 10'd16; // 16 clock cycles are added to avoid trfc violations
localparam C_SKIP_DYN_IN_TERM = 1'b1;
localparam C_MC_CALIBRATION_RA = 16'h0000;
localparam C_MC_CALIBRATION_BA = 3'h0;
localparam C_MC_CALIBRATION_CA = 12'h000;
// All the following new localparams and signals are added to support
// the AXI slave interface. They have no function to play in a standard
// interface design and can be ignored.
localparam C_S0_AXI_ID_WIDTH = 4;
localparam C_S0_AXI_ADDR_WIDTH = 64;
localparam C_S0_AXI_DATA_WIDTH = 32;
localparam C_S1_AXI_ID_WIDTH = 4;
localparam C_S1_AXI_ADDR_WIDTH = 64;
localparam C_S1_AXI_DATA_WIDTH = 32;
localparam C_S2_AXI_ID_WIDTH = 4;
localparam C_S2_AXI_ADDR_WIDTH = 64;
localparam C_S2_AXI_DATA_WIDTH = 32;
localparam C_S3_AXI_ID_WIDTH = 4;
localparam C_S3_AXI_ADDR_WIDTH = 64;
localparam C_S3_AXI_DATA_WIDTH = 32;
localparam C_S4_AXI_ID_WIDTH = 4;
localparam C_S4_AXI_ADDR_WIDTH = 64;
localparam C_S4_AXI_DATA_WIDTH = 32;
localparam C_S5_AXI_ID_WIDTH = 4;
localparam C_S5_AXI_ADDR_WIDTH = 64;
localparam C_S5_AXI_DATA_WIDTH = 32;
localparam C_MCB_USE_EXTERNAL_BUFPLL = 1;
// AXI wire declarations
// AXI interface of the mcb_ui_top module is connected to the following
// floating wires in all the standard interface designs.
wire s0_axi_aclk;
wire s0_axi_aresetn;
wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_awid;
wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_awaddr;
wire [7:0] s0_axi_awlen;
wire [2:0] s0_axi_awsize;
wire [1:0] s0_axi_awburst;
wire [0:0] s0_axi_awlock;
wire [3:0] s0_axi_awcache;
wire [2:0] s0_axi_awprot;
wire [3:0] s0_axi_awqos;
wire s0_axi_awvalid;
wire s0_axi_awready;
wire [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_wdata;
wire [C_S0_AXI_DATA_WIDTH/8-1:0] s0_axi_wstrb;
wire s0_axi_wlast;
wire s0_axi_wvalid;
wire s0_axi_wready;
wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_bid;
wire [1:0] s0_axi_bresp;
wire s0_axi_bvalid;
wire s0_axi_bready;
wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_arid;
wire [C_S0_AXI_ADDR_WIDTH-1:0] s0_axi_araddr;
wire [7:0] s0_axi_arlen;
wire [2:0] s0_axi_arsize;
wire [1:0] s0_axi_arburst;
wire [0:0] s0_axi_arlock;
wire [3:0] s0_axi_arcache;
wire [2:0] s0_axi_arprot;
wire [3:0] s0_axi_arqos;
wire s0_axi_arvalid;
wire s0_axi_arready;
wire [C_S0_AXI_ID_WIDTH-1:0] s0_axi_rid;
wire [C_S0_AXI_DATA_WIDTH-1:0] s0_axi_rdata;
wire [1:0] s0_axi_rresp;
wire s0_axi_rlast;
wire s0_axi_rvalid;
wire s0_axi_rready;
wire s1_axi_aclk;
wire s1_axi_aresetn;
wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_awid;
wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_awaddr;
wire [7:0] s1_axi_awlen;
wire [2:0] s1_axi_awsize;
wire [1:0] s1_axi_awburst;
wire [0:0] s1_axi_awlock;
wire [3:0] s1_axi_awcache;
wire [2:0] s1_axi_awprot;
wire [3:0] s1_axi_awqos;
wire s1_axi_awvalid;
wire s1_axi_awready;
wire [C_S1_AXI_DATA_WIDTH-1:0] s1_axi_wdata;
wire [C_S1_AXI_DATA_WIDTH/8-1:0] s1_axi_wstrb;
wire s1_axi_wlast;
wire s1_axi_wvalid;
wire s1_axi_wready;
wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_bid;
wire [1:0] s1_axi_bresp;
wire s1_axi_bvalid;
wire s1_axi_bready;
wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_arid;
wire [C_S1_AXI_ADDR_WIDTH-1:0] s1_axi_araddr;
wire [7:0] s1_axi_arlen;
wire [2:0] s1_axi_arsize;
wire [1:0] s1_axi_arburst;
wire [0:0] s1_axi_arlock;
wire [3:0] s1_axi_arcache;
wire [2:0] s1_axi_arprot;
wire [3:0] s1_axi_arqos;
wire s1_axi_arvalid;
wire s1_axi_arready;
wire [C_S1_AXI_ID_WIDTH-1:0] s1_axi_rid;
wire [C_S1_AXI_DATA_WIDTH-1:0] s1_axi_rdata;
wire [1:0] s1_axi_rresp;
wire s1_axi_rlast;
wire s1_axi_rvalid;
wire s1_axi_rready;
wire s2_axi_aclk;
wire s2_axi_aresetn;
wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_awid;
wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_awaddr;
wire [7:0] s2_axi_awlen;
wire [2:0] s2_axi_awsize;
wire [1:0] s2_axi_awburst;
wire [0:0] s2_axi_awlock;
wire [3:0] s2_axi_awcache;
wire [2:0] s2_axi_awprot;
wire [3:0] s2_axi_awqos;
wire s2_axi_awvalid;
wire s2_axi_awready;
wire [C_S2_AXI_DATA_WIDTH-1:0] s2_axi_wdata;
wire [C_S2_AXI_DATA_WIDTH/8-1:0] s2_axi_wstrb;
wire s2_axi_wlast;
wire s2_axi_wvalid;
wire s2_axi_wready;
wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_bid;
wire [1:0] s2_axi_bresp;
wire s2_axi_bvalid;
wire s2_axi_bready;
wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_arid;
wire [C_S2_AXI_ADDR_WIDTH-1:0] s2_axi_araddr;
wire [7:0] s2_axi_arlen;
wire [2:0] s2_axi_arsize;
wire [1:0] s2_axi_arburst;
wire [0:0] s2_axi_arlock;
wire [3:0] s2_axi_arcache;
wire [2:0] s2_axi_arprot;
wire [3:0] s2_axi_arqos;
wire s2_axi_arvalid;
wire s2_axi_arready;
wire [C_S2_AXI_ID_WIDTH-1:0] s2_axi_rid;
wire [C_S2_AXI_DATA_WIDTH-1:0] s2_axi_rdata;
wire [1:0] s2_axi_rresp;
wire s2_axi_rlast;
wire s2_axi_rvalid;
wire s2_axi_rready;
wire s3_axi_aclk;
wire s3_axi_aresetn;
wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_awid;
wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_awaddr;
wire [7:0] s3_axi_awlen;
wire [2:0] s3_axi_awsize;
wire [1:0] s3_axi_awburst;
wire [0:0] s3_axi_awlock;
wire [3:0] s3_axi_awcache;
wire [2:0] s3_axi_awprot;
wire [3:0] s3_axi_awqos;
wire s3_axi_awvalid;
wire s3_axi_awready;
wire [C_S3_AXI_DATA_WIDTH-1:0] s3_axi_wdata;
wire [C_S3_AXI_DATA_WIDTH/8-1:0] s3_axi_wstrb;
wire s3_axi_wlast;
wire s3_axi_wvalid;
wire s3_axi_wready;
wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_bid;
wire [1:0] s3_axi_bresp;
wire s3_axi_bvalid;
wire s3_axi_bready;
wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_arid;
wire [C_S3_AXI_ADDR_WIDTH-1:0] s3_axi_araddr;
wire [7:0] s3_axi_arlen;
wire [2:0] s3_axi_arsize;
wire [1:0] s3_axi_arburst;
wire [0:0] s3_axi_arlock;
wire [3:0] s3_axi_arcache;
wire [2:0] s3_axi_arprot;
wire [3:0] s3_axi_arqos;
wire s3_axi_arvalid;
wire s3_axi_arready;
wire [C_S3_AXI_ID_WIDTH-1:0] s3_axi_rid;
wire [C_S3_AXI_DATA_WIDTH-1:0] s3_axi_rdata;
wire [1:0] s3_axi_rresp;
wire s3_axi_rlast;
wire s3_axi_rvalid;
wire s3_axi_rready;
wire s4_axi_aclk;
wire s4_axi_aresetn;
wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_awid;
wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_awaddr;
wire [7:0] s4_axi_awlen;
wire [2:0] s4_axi_awsize;
wire [1:0] s4_axi_awburst;
wire [0:0] s4_axi_awlock;
wire [3:0] s4_axi_awcache;
wire [2:0] s4_axi_awprot;
wire [3:0] s4_axi_awqos;
wire s4_axi_awvalid;
wire s4_axi_awready;
wire [C_S4_AXI_DATA_WIDTH-1:0] s4_axi_wdata;
wire [C_S4_AXI_DATA_WIDTH/8-1:0] s4_axi_wstrb;
wire s4_axi_wlast;
wire s4_axi_wvalid;
wire s4_axi_wready;
wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_bid;
wire [1:0] s4_axi_bresp;
wire s4_axi_bvalid;
wire s4_axi_bready;
wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_arid;
wire [C_S4_AXI_ADDR_WIDTH-1:0] s4_axi_araddr;
wire [7:0] s4_axi_arlen;
wire [2:0] s4_axi_arsize;
wire [1:0] s4_axi_arburst;
wire [0:0] s4_axi_arlock;
wire [3:0] s4_axi_arcache;
wire [2:0] s4_axi_arprot;
wire [3:0] s4_axi_arqos;
wire s4_axi_arvalid;
wire s4_axi_arready;
wire [C_S4_AXI_ID_WIDTH-1:0] s4_axi_rid;
wire [C_S4_AXI_DATA_WIDTH-1:0] s4_axi_rdata;
wire [1:0] s4_axi_rresp;
wire s4_axi_rlast;
wire s4_axi_rvalid;
wire s4_axi_rready;
wire s5_axi_aclk;
wire s5_axi_aresetn;
wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_awid;
wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_awaddr;
wire [7:0] s5_axi_awlen;
wire [2:0] s5_axi_awsize;
wire [1:0] s5_axi_awburst;
wire [0:0] s5_axi_awlock;
wire [3:0] s5_axi_awcache;
wire [2:0] s5_axi_awprot;
wire [3:0] s5_axi_awqos;
wire s5_axi_awvalid;
wire s5_axi_awready;
wire [C_S5_AXI_DATA_WIDTH-1:0] s5_axi_wdata;
wire [C_S5_AXI_DATA_WIDTH/8-1:0] s5_axi_wstrb;
wire s5_axi_wlast;
wire s5_axi_wvalid;
wire s5_axi_wready;
wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_bid;
wire [1:0] s5_axi_bresp;
wire s5_axi_bvalid;
wire s5_axi_bready;
wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_arid;
wire [C_S5_AXI_ADDR_WIDTH-1:0] s5_axi_araddr;
wire [7:0] s5_axi_arlen;
wire [2:0] s5_axi_arsize;
wire [1:0] s5_axi_arburst;
wire [0:0] s5_axi_arlock;
wire [3:0] s5_axi_arcache;
wire [2:0] s5_axi_arprot;
wire [3:0] s5_axi_arqos;
wire s5_axi_arvalid;
wire s5_axi_arready;
wire [C_S5_AXI_ID_WIDTH-1:0] s5_axi_rid;
wire [C_S5_AXI_DATA_WIDTH-1:0] s5_axi_rdata;
wire [1:0] s5_axi_rresp;
wire s5_axi_rlast;
wire s5_axi_rvalid;
wire s5_axi_rready;
wire [7:0] uo_data;
wire uo_data_valid;
wire uo_cmd_ready_in;
wire uo_refrsh_flag;
wire uo_cal_start;
wire uo_sdo;
wire [31:0] status;
wire sysclk_2x_bufpll_o;
wire sysclk_2x_180_bufpll_o;
wire pll_ce_0_bufpll_o;
wire pll_ce_90_bufpll_o;
wire pll_lock_bufpll_o;
// mcb_ui_top instantiation
mcb_ui_top #
(
// Raw Wrapper Parameters
.C_MEMCLK_PERIOD (C_MEMCLK_PERIOD),
.C_PORT_ENABLE (C_PORT_ENABLE),
.C_MEM_ADDR_ORDER (C_MEM_ADDR_ORDER),
.C_ARB_ALGORITHM (C_ARB_ALGORITHM),
.C_ARB_NUM_TIME_SLOTS (C_ARB_NUM_TIME_SLOTS),
.C_ARB_TIME_SLOT_0 (C_ARB_TIME_SLOT_0),
.C_ARB_TIME_SLOT_1 (C_ARB_TIME_SLOT_1),
.C_ARB_TIME_SLOT_2 (C_ARB_TIME_SLOT_2),
.C_ARB_TIME_SLOT_3 (C_ARB_TIME_SLOT_3),
.C_ARB_TIME_SLOT_4 (C_ARB_TIME_SLOT_4),
.C_ARB_TIME_SLOT_5 (C_ARB_TIME_SLOT_5),
.C_ARB_TIME_SLOT_6 (C_ARB_TIME_SLOT_6),
.C_ARB_TIME_SLOT_7 (C_ARB_TIME_SLOT_7),
.C_ARB_TIME_SLOT_8 (C_ARB_TIME_SLOT_8),
.C_ARB_TIME_SLOT_9 (C_ARB_TIME_SLOT_9),
.C_ARB_TIME_SLOT_10 (C_ARB_TIME_SLOT_10),
.C_ARB_TIME_SLOT_11 (C_ARB_TIME_SLOT_11),
.C_PORT_CONFIG (C_PORT_CONFIG),
.C_MEM_TRAS (C_MEM_TRAS),
.C_MEM_TRCD (C_MEM_TRCD),
.C_MEM_TREFI (C_MEM_TREFI),
.C_MEM_TRFC (C_MEM_TRFC),
.C_MEM_TRP (C_MEM_TRP),
.C_MEM_TWR (C_MEM_TWR),
.C_MEM_TRTP (C_MEM_TRTP),
.C_MEM_TWTR (C_MEM_TWTR),
.C_NUM_DQ_PINS (C_NUM_DQ_PINS),
.C_MEM_TYPE (C_MEM_TYPE),
.C_MEM_DENSITY (C_MEM_DENSITY),
.C_MEM_BURST_LEN (C_MEM_BURST_LEN),
.C_MEM_CAS_LATENCY (C_MEM_CAS_LATENCY),
.C_MEM_ADDR_WIDTH (C_MEM_ADDR_WIDTH),
.C_MEM_BANKADDR_WIDTH (C_MEM_BANKADDR_WIDTH),
.C_MEM_NUM_COL_BITS (C_MEM_NUM_COL_BITS),
.C_MEM_DDR3_CAS_LATENCY (C_MEM_DDR3_CAS_LATENCY),
.C_MEM_MOBILE_PA_SR (C_MEM_MOBILE_PA_SR),
.C_MEM_DDR1_2_ODS (C_MEM_DDR1_2_ODS),
.C_MEM_DDR3_ODS (C_MEM_DDR3_ODS),
.C_MEM_DDR2_RTT (C_MEM_DDR2_RTT),
.C_MEM_DDR3_RTT (C_MEM_DDR3_RTT),
.C_MEM_MDDR_ODS (C_MEM_MDDR_ODS),
.C_MEM_DDR2_DIFF_DQS_EN (C_MEM_DDR2_DIFF_DQS_EN),
.C_MEM_DDR2_3_PA_SR (C_MEM_DDR2_3_PA_SR),
.C_MEM_DDR3_CAS_WR_LATENCY (C_MEM_DDR3_CAS_WR_LATENCY),
.C_MEM_DDR3_AUTO_SR (C_MEM_DDR3_AUTO_SR),
.C_MEM_DDR2_3_HIGH_TEMP_SR (C_MEM_DDR2_3_HIGH_TEMP_SR),
.C_MEM_DDR3_DYN_WRT_ODT (C_MEM_DDR3_DYN_WRT_ODT),
.C_MEM_TZQINIT_MAXCNT (C_MEM_TZQINIT_MAXCNT),
.C_MC_CALIB_BYPASS (C_MC_CALIB_BYPASS),
.C_MC_CALIBRATION_RA (C_MC_CALIBRATION_RA),
.C_MC_CALIBRATION_BA (C_MC_CALIBRATION_BA),
.C_MC_CALIBRATION_CA (C_MC_CALIBRATION_CA),
.C_CALIB_SOFT_IP (C_CALIB_SOFT_IP),
.C_SKIP_IN_TERM_CAL (C_SKIP_IN_TERM_CAL),
.C_SKIP_DYNAMIC_CAL (C_SKIP_DYNAMIC_CAL),
.C_SKIP_DYN_IN_TERM (C_SKIP_DYN_IN_TERM),
.LDQSP_TAP_DELAY_VAL (LDQSP_TAP_DELAY_VAL),
.UDQSP_TAP_DELAY_VAL (UDQSP_TAP_DELAY_VAL),
.LDQSN_TAP_DELAY_VAL (LDQSN_TAP_DELAY_VAL),
.UDQSN_TAP_DELAY_VAL (UDQSN_TAP_DELAY_VAL),
.DQ0_TAP_DELAY_VAL (DQ0_TAP_DELAY_VAL),
.DQ1_TAP_DELAY_VAL (DQ1_TAP_DELAY_VAL),
.DQ2_TAP_DELAY_VAL (DQ2_TAP_DELAY_VAL),
.DQ3_TAP_DELAY_VAL (DQ3_TAP_DELAY_VAL),
.DQ4_TAP_DELAY_VAL (DQ4_TAP_DELAY_VAL),
.DQ5_TAP_DELAY_VAL (DQ5_TAP_DELAY_VAL),
.DQ6_TAP_DELAY_VAL (DQ6_TAP_DELAY_VAL),
.DQ7_TAP_DELAY_VAL (DQ7_TAP_DELAY_VAL),
.DQ8_TAP_DELAY_VAL (DQ8_TAP_DELAY_VAL),
.DQ9_TAP_DELAY_VAL (DQ9_TAP_DELAY_VAL),
.DQ10_TAP_DELAY_VAL (DQ10_TAP_DELAY_VAL),
.DQ11_TAP_DELAY_VAL (DQ11_TAP_DELAY_VAL),
.DQ12_TAP_DELAY_VAL (DQ12_TAP_DELAY_VAL),
.DQ13_TAP_DELAY_VAL (DQ13_TAP_DELAY_VAL),
.DQ14_TAP_DELAY_VAL (DQ14_TAP_DELAY_VAL),
.DQ15_TAP_DELAY_VAL (DQ15_TAP_DELAY_VAL),
.C_MC_CALIBRATION_CLK_DIV (C_MC_CALIBRATION_CLK_DIV),
.C_MC_CALIBRATION_MODE (C_MC_CALIBRATION_MODE),
.C_MC_CALIBRATION_DELAY (C_MC_CALIBRATION_DELAY),
.C_SIMULATION (C_SIMULATION),
.C_P0_MASK_SIZE (C_P0_MASK_SIZE),
.C_P0_DATA_PORT_SIZE (C_P0_DATA_PORT_SIZE),
.C_P1_MASK_SIZE (C_P1_MASK_SIZE),
.C_P1_DATA_PORT_SIZE (C_P1_DATA_PORT_SIZE),
.C_MCB_USE_EXTERNAL_BUFPLL (C_MCB_USE_EXTERNAL_BUFPLL)
)
mcb_ui_top_inst
(
// Raw Wrapper Signals
.sysclk_2x (sysclk_2x),
.sysclk_2x_180 (sysclk_2x_180),
.pll_ce_0 (pll_ce_0),
.pll_ce_90 (pll_ce_90),
.pll_lock (pll_lock),
.sysclk_2x_bufpll_o (sysclk_2x_bufpll_o),
.sysclk_2x_180_bufpll_o (sysclk_2x_180_bufpll_o),
.pll_ce_0_bufpll_o (pll_ce_0_bufpll_o),
.pll_ce_90_bufpll_o (pll_ce_90_bufpll_o),
.pll_lock_bufpll_o (pll_lock_bufpll_o),
.sys_rst (async_rst),
.p0_arb_en (1'b1),
.p0_cmd_clk (p0_cmd_clk),
.p0_cmd_en (p0_cmd_en),
.p0_cmd_instr (p0_cmd_instr),
.p0_cmd_bl (p0_cmd_bl),
.p0_cmd_byte_addr (p0_cmd_byte_addr),
.p0_cmd_empty (p0_cmd_empty),
.p0_cmd_full (p0_cmd_full),
.p0_wr_clk (p0_wr_clk),
.p0_wr_en (p0_wr_en),
.p0_wr_mask (p0_wr_mask),
.p0_wr_data (p0_wr_data),
.p0_wr_full (p0_wr_full),
.p0_wr_empty (p0_wr_empty),
.p0_wr_count (p0_wr_count),
.p0_wr_underrun (p0_wr_underrun),
.p0_wr_error (p0_wr_error),
.p0_rd_clk (p0_rd_clk),
.p0_rd_en (p0_rd_en),
.p0_rd_data (p0_rd_data),
.p0_rd_full (p0_rd_full),
.p0_rd_empty (p0_rd_empty),
.p0_rd_count (p0_rd_count),
.p0_rd_overflow (p0_rd_overflow),
.p0_rd_error (p0_rd_error),
.p1_arb_en (1'b1),
.p1_cmd_clk (p1_cmd_clk),
.p1_cmd_en (p1_cmd_en),
.p1_cmd_instr (p1_cmd_instr),
.p1_cmd_bl (p1_cmd_bl),
.p1_cmd_byte_addr (p1_cmd_byte_addr),
.p1_cmd_empty (p1_cmd_empty),
.p1_cmd_full (p1_cmd_full),
.p1_wr_clk (p1_wr_clk),
.p1_wr_en (p1_wr_en),
.p1_wr_mask (p1_wr_mask),
.p1_wr_data (p1_wr_data),
.p1_wr_full (p1_wr_full),
.p1_wr_empty (p1_wr_empty),
.p1_wr_count (p1_wr_count),
.p1_wr_underrun (p1_wr_underrun),
.p1_wr_error (p1_wr_error),
.p1_rd_clk (p1_rd_clk),
.p1_rd_en (p1_rd_en),
.p1_rd_data (p1_rd_data),
.p1_rd_full (p1_rd_full),
.p1_rd_empty (p1_rd_empty),
.p1_rd_count (p1_rd_count),
.p1_rd_overflow (p1_rd_overflow),
.p1_rd_error (p1_rd_error),
.p2_arb_en (1'b1),
.p2_cmd_clk (p2_cmd_clk),
.p2_cmd_en (p2_cmd_en),
.p2_cmd_instr (p2_cmd_instr),
.p2_cmd_bl (p2_cmd_bl),
.p2_cmd_byte_addr (p2_cmd_byte_addr),
.p2_cmd_empty (p2_cmd_empty),
.p2_cmd_full (p2_cmd_full),
.p2_wr_clk (p2_wr_clk),
.p2_wr_en (p2_wr_en),
.p2_wr_mask (p2_wr_mask),
.p2_wr_data (p2_wr_data),
.p2_wr_full (p2_wr_full),
.p2_wr_empty (p2_wr_empty),
.p2_wr_count (p2_wr_count),
.p2_wr_underrun (p2_wr_underrun),
.p2_wr_error (p2_wr_error),
.p2_rd_clk (p2_rd_clk),
.p2_rd_en (p2_rd_en),
.p2_rd_data (p2_rd_data),
.p2_rd_full (p2_rd_full),
.p2_rd_empty (p2_rd_empty),
.p2_rd_count (p2_rd_count),
.p2_rd_overflow (p2_rd_overflow),
.p2_rd_error (p2_rd_error),
.p3_arb_en (1'b1),
.p3_cmd_clk (p3_cmd_clk),
.p3_cmd_en (p3_cmd_en),
.p3_cmd_instr (p3_cmd_instr),
.p3_cmd_bl (p3_cmd_bl),
.p3_cmd_byte_addr (p3_cmd_byte_addr),
.p3_cmd_empty (p3_cmd_empty),
.p3_cmd_full (p3_cmd_full),
.p3_wr_clk (p3_wr_clk),
.p3_wr_en (p3_wr_en),
.p3_wr_mask (p3_wr_mask),
.p3_wr_data (p3_wr_data),
.p3_wr_full (p3_wr_full),
.p3_wr_empty (p3_wr_empty),
.p3_wr_count (p3_wr_count),
.p3_wr_underrun (p3_wr_underrun),
.p3_wr_error (p3_wr_error),
.p3_rd_clk (p3_rd_clk),
.p3_rd_en (p3_rd_en),
.p3_rd_data (p3_rd_data),
.p3_rd_full (p3_rd_full),
.p3_rd_empty (p3_rd_empty),
.p3_rd_count (p3_rd_count),
.p3_rd_overflow (p3_rd_overflow),
.p3_rd_error (p3_rd_error),
.p4_arb_en (1'b1),
.p4_cmd_clk (p4_cmd_clk),
.p4_cmd_en (p4_cmd_en),
.p4_cmd_instr (p4_cmd_instr),
.p4_cmd_bl (p4_cmd_bl),
.p4_cmd_byte_addr (p4_cmd_byte_addr),
.p4_cmd_empty (p4_cmd_empty),
.p4_cmd_full (p4_cmd_full),
.p4_wr_clk (p4_wr_clk),
.p4_wr_en (p4_wr_en),
.p4_wr_mask (p4_wr_mask),
.p4_wr_data (p4_wr_data),
.p4_wr_full (p4_wr_full),
.p4_wr_empty (p4_wr_empty),
.p4_wr_count (p4_wr_count),
.p4_wr_underrun (p4_wr_underrun),
.p4_wr_error (p4_wr_error),
.p4_rd_clk (p4_rd_clk),
.p4_rd_en (p4_rd_en),
.p4_rd_data (p4_rd_data),
.p4_rd_full (p4_rd_full),
.p4_rd_empty (p4_rd_empty),
.p4_rd_count (p4_rd_count),
.p4_rd_overflow (p4_rd_overflow),
.p4_rd_error (p4_rd_error),
.p5_arb_en (1'b1),
.p5_cmd_clk (p5_cmd_clk),
.p5_cmd_en (p5_cmd_en),
.p5_cmd_instr (p5_cmd_instr),
.p5_cmd_bl (p5_cmd_bl),
.p5_cmd_byte_addr (p5_cmd_byte_addr),
.p5_cmd_empty (p5_cmd_empty),
.p5_cmd_full (p5_cmd_full),
.p5_wr_clk (p5_wr_clk),
.p5_wr_en (p5_wr_en),
.p5_wr_mask (p5_wr_mask),
.p5_wr_data (p5_wr_data),
.p5_wr_full (p5_wr_full),
.p5_wr_empty (p5_wr_empty),
.p5_wr_count (p5_wr_count),
.p5_wr_underrun (p5_wr_underrun),
.p5_wr_error (p5_wr_error),
.p5_rd_clk (p5_rd_clk),
.p5_rd_en (p5_rd_en),
.p5_rd_data (p5_rd_data),
.p5_rd_full (p5_rd_full),
.p5_rd_empty (p5_rd_empty),
.p5_rd_count (p5_rd_count),
.p5_rd_overflow (p5_rd_overflow),
.p5_rd_error (p5_rd_error),
.mcbx_dram_addr (mcbx_dram_addr),
.mcbx_dram_ba (mcbx_dram_ba),
.mcbx_dram_ras_n (mcbx_dram_ras_n),
.mcbx_dram_cas_n (mcbx_dram_cas_n),
.mcbx_dram_we_n (mcbx_dram_we_n),
.mcbx_dram_cke (mcbx_dram_cke),
.mcbx_dram_clk (mcbx_dram_clk),
.mcbx_dram_clk_n (mcbx_dram_clk_n),
.mcbx_dram_dq (mcbx_dram_dq),
.mcbx_dram_dqs (mcbx_dram_dqs),
.mcbx_dram_dqs_n (mcbx_dram_dqs_n),
.mcbx_dram_udqs (mcbx_dram_udqs),
.mcbx_dram_udqs_n (mcbx_dram_udqs_n),
.mcbx_dram_udm (mcbx_dram_udm),
.mcbx_dram_ldm (mcbx_dram_ldm),
.mcbx_dram_odt (mcbx_dram_odt),
.mcbx_dram_ddr3_rst (mcbx_dram_ddr3_rst),
.calib_recal (1'b0),
.rzq (mcbx_rzq),
.zio (mcbx_zio),
.ui_read (1'b0),
.ui_add (1'b0),
.ui_cs (1'b0),
.ui_clk (mcb_drp_clk),
.ui_sdi (1'b0),
.ui_addr (5'b0),
.ui_broadcast (1'b0),
.ui_drp_update (1'b0),
.ui_done_cal (1'b1),
.ui_cmd (1'b0),
.ui_cmd_in (1'b0),
.ui_cmd_en (1'b0),
.ui_dqcount (4'b0),
.ui_dq_lower_dec (1'b0),
.ui_dq_lower_inc (1'b0),
.ui_dq_upper_dec (1'b0),
.ui_dq_upper_inc (1'b0),
.ui_udqs_inc (1'b0),
.ui_udqs_dec (1'b0),
.ui_ldqs_inc (1'b0),
.ui_ldqs_dec (1'b0),
.uo_data (uo_data),
.uo_data_valid (uo_data_valid),
.uo_done_cal (calib_done),
.uo_cmd_ready_in (uo_cmd_ready_in),
.uo_refrsh_flag (uo_refrsh_flag),
.uo_cal_start (uo_cal_start),
.uo_sdo (uo_sdo),
.status (status),
.selfrefresh_enter (selfrefresh_enter),
.selfrefresh_mode (selfrefresh_mode),
// AXI Signals
.s0_axi_aclk (s0_axi_aclk),
.s0_axi_aresetn (s0_axi_aresetn),
.s0_axi_awid (s0_axi_awid),
.s0_axi_awaddr (s0_axi_awaddr),
.s0_axi_awlen (s0_axi_awlen),
.s0_axi_awsize (s0_axi_awsize),
.s0_axi_awburst (s0_axi_awburst),
.s0_axi_awlock (s0_axi_awlock),
.s0_axi_awcache (s0_axi_awcache),
.s0_axi_awprot (s0_axi_awprot),
.s0_axi_awqos (s0_axi_awqos),
.s0_axi_awvalid (s0_axi_awvalid),
.s0_axi_awready (s0_axi_awready),
.s0_axi_wdata (s0_axi_wdata),
.s0_axi_wstrb (s0_axi_wstrb),
.s0_axi_wlast (s0_axi_wlast),
.s0_axi_wvalid (s0_axi_wvalid),
.s0_axi_wready (s0_axi_wready),
.s0_axi_bid (s0_axi_bid),
.s0_axi_bresp (s0_axi_bresp),
.s0_axi_bvalid (s0_axi_bvalid),
.s0_axi_bready (s0_axi_bready),
.s0_axi_arid (s0_axi_arid),
.s0_axi_araddr (s0_axi_araddr),
.s0_axi_arlen (s0_axi_arlen),
.s0_axi_arsize (s0_axi_arsize),
.s0_axi_arburst (s0_axi_arburst),
.s0_axi_arlock (s0_axi_arlock),
.s0_axi_arcache (s0_axi_arcache),
.s0_axi_arprot (s0_axi_arprot),
.s0_axi_arqos (s0_axi_arqos),
.s0_axi_arvalid (s0_axi_arvalid),
.s0_axi_arready (s0_axi_arready),
.s0_axi_rid (s0_axi_rid),
.s0_axi_rdata (s0_axi_rdata),
.s0_axi_rresp (s0_axi_rresp),
.s0_axi_rlast (s0_axi_rlast),
.s0_axi_rvalid (s0_axi_rvalid),
.s0_axi_rready (s0_axi_rready),
.s1_axi_aclk (s1_axi_aclk),
.s1_axi_aresetn (s1_axi_aresetn),
.s1_axi_awid (s1_axi_awid),
.s1_axi_awaddr (s1_axi_awaddr),
.s1_axi_awlen (s1_axi_awlen),
.s1_axi_awsize (s1_axi_awsize),
.s1_axi_awburst (s1_axi_awburst),
.s1_axi_awlock (s1_axi_awlock),
.s1_axi_awcache (s1_axi_awcache),
.s1_axi_awprot (s1_axi_awprot),
.s1_axi_awqos (s1_axi_awqos),
.s1_axi_awvalid (s1_axi_awvalid),
.s1_axi_awready (s1_axi_awready),
.s1_axi_wdata (s1_axi_wdata),
.s1_axi_wstrb (s1_axi_wstrb),
.s1_axi_wlast (s1_axi_wlast),
.s1_axi_wvalid (s1_axi_wvalid),
.s1_axi_wready (s1_axi_wready),
.s1_axi_bid (s1_axi_bid),
.s1_axi_bresp (s1_axi_bresp),
.s1_axi_bvalid (s1_axi_bvalid),
.s1_axi_bready (s1_axi_bready),
.s1_axi_arid (s1_axi_arid),
.s1_axi_araddr (s1_axi_araddr),
.s1_axi_arlen (s1_axi_arlen),
.s1_axi_arsize (s1_axi_arsize),
.s1_axi_arburst (s1_axi_arburst),
.s1_axi_arlock (s1_axi_arlock),
.s1_axi_arcache (s1_axi_arcache),
.s1_axi_arprot (s1_axi_arprot),
.s1_axi_arqos (s1_axi_arqos),
.s1_axi_arvalid (s1_axi_arvalid),
.s1_axi_arready (s1_axi_arready),
.s1_axi_rid (s1_axi_rid),
.s1_axi_rdata (s1_axi_rdata),
.s1_axi_rresp (s1_axi_rresp),
.s1_axi_rlast (s1_axi_rlast),
.s1_axi_rvalid (s1_axi_rvalid),
.s1_axi_rready (s1_axi_rready),
.s2_axi_aclk (s2_axi_aclk),
.s2_axi_aresetn (s2_axi_aresetn),
.s2_axi_awid (s2_axi_awid),
.s2_axi_awaddr (s2_axi_awaddr),
.s2_axi_awlen (s2_axi_awlen),
.s2_axi_awsize (s2_axi_awsize),
.s2_axi_awburst (s2_axi_awburst),
.s2_axi_awlock (s2_axi_awlock),
.s2_axi_awcache (s2_axi_awcache),
.s2_axi_awprot (s2_axi_awprot),
.s2_axi_awqos (s2_axi_awqos),
.s2_axi_awvalid (s2_axi_awvalid),
.s2_axi_awready (s2_axi_awready),
.s2_axi_wdata (s2_axi_wdata),
.s2_axi_wstrb (s2_axi_wstrb),
.s2_axi_wlast (s2_axi_wlast),
.s2_axi_wvalid (s2_axi_wvalid),
.s2_axi_wready (s2_axi_wready),
.s2_axi_bid (s2_axi_bid),
.s2_axi_bresp (s2_axi_bresp),
.s2_axi_bvalid (s2_axi_bvalid),
.s2_axi_bready (s2_axi_bready),
.s2_axi_arid (s2_axi_arid),
.s2_axi_araddr (s2_axi_araddr),
.s2_axi_arlen (s2_axi_arlen),
.s2_axi_arsize (s2_axi_arsize),
.s2_axi_arburst (s2_axi_arburst),
.s2_axi_arlock (s2_axi_arlock),
.s2_axi_arcache (s2_axi_arcache),
.s2_axi_arprot (s2_axi_arprot),
.s2_axi_arqos (s2_axi_arqos),
.s2_axi_arvalid (s2_axi_arvalid),
.s2_axi_arready (s2_axi_arready),
.s2_axi_rid (s2_axi_rid),
.s2_axi_rdata (s2_axi_rdata),
.s2_axi_rresp (s2_axi_rresp),
.s2_axi_rlast (s2_axi_rlast),
.s2_axi_rvalid (s2_axi_rvalid),
.s2_axi_rready (s2_axi_rready),
.s3_axi_aclk (s3_axi_aclk),
.s3_axi_aresetn (s3_axi_aresetn),
.s3_axi_awid (s3_axi_awid),
.s3_axi_awaddr (s3_axi_awaddr),
.s3_axi_awlen (s3_axi_awlen),
.s3_axi_awsize (s3_axi_awsize),
.s3_axi_awburst (s3_axi_awburst),
.s3_axi_awlock (s3_axi_awlock),
.s3_axi_awcache (s3_axi_awcache),
.s3_axi_awprot (s3_axi_awprot),
.s3_axi_awqos (s3_axi_awqos),
.s3_axi_awvalid (s3_axi_awvalid),
.s3_axi_awready (s3_axi_awready),
.s3_axi_wdata (s3_axi_wdata),
.s3_axi_wstrb (s3_axi_wstrb),
.s3_axi_wlast (s3_axi_wlast),
.s3_axi_wvalid (s3_axi_wvalid),
.s3_axi_wready (s3_axi_wready),
.s3_axi_bid (s3_axi_bid),
.s3_axi_bresp (s3_axi_bresp),
.s3_axi_bvalid (s3_axi_bvalid),
.s3_axi_bready (s3_axi_bready),
.s3_axi_arid (s3_axi_arid),
.s3_axi_araddr (s3_axi_araddr),
.s3_axi_arlen (s3_axi_arlen),
.s3_axi_arsize (s3_axi_arsize),
.s3_axi_arburst (s3_axi_arburst),
.s3_axi_arlock (s3_axi_arlock),
.s3_axi_arcache (s3_axi_arcache),
.s3_axi_arprot (s3_axi_arprot),
.s3_axi_arqos (s3_axi_arqos),
.s3_axi_arvalid (s3_axi_arvalid),
.s3_axi_arready (s3_axi_arready),
.s3_axi_rid (s3_axi_rid),
.s3_axi_rdata (s3_axi_rdata),
.s3_axi_rresp (s3_axi_rresp),
.s3_axi_rlast (s3_axi_rlast),
.s3_axi_rvalid (s3_axi_rvalid),
.s3_axi_rready (s3_axi_rready),
.s4_axi_aclk (s4_axi_aclk),
.s4_axi_aresetn (s4_axi_aresetn),
.s4_axi_awid (s4_axi_awid),
.s4_axi_awaddr (s4_axi_awaddr),
.s4_axi_awlen (s4_axi_awlen),
.s4_axi_awsize (s4_axi_awsize),
.s4_axi_awburst (s4_axi_awburst),
.s4_axi_awlock (s4_axi_awlock),
.s4_axi_awcache (s4_axi_awcache),
.s4_axi_awprot (s4_axi_awprot),
.s4_axi_awqos (s4_axi_awqos),
.s4_axi_awvalid (s4_axi_awvalid),
.s4_axi_awready (s4_axi_awready),
.s4_axi_wdata (s4_axi_wdata),
.s4_axi_wstrb (s4_axi_wstrb),
.s4_axi_wlast (s4_axi_wlast),
.s4_axi_wvalid (s4_axi_wvalid),
.s4_axi_wready (s4_axi_wready),
.s4_axi_bid (s4_axi_bid),
.s4_axi_bresp (s4_axi_bresp),
.s4_axi_bvalid (s4_axi_bvalid),
.s4_axi_bready (s4_axi_bready),
.s4_axi_arid (s4_axi_arid),
.s4_axi_araddr (s4_axi_araddr),
.s4_axi_arlen (s4_axi_arlen),
.s4_axi_arsize (s4_axi_arsize),
.s4_axi_arburst (s4_axi_arburst),
.s4_axi_arlock (s4_axi_arlock),
.s4_axi_arcache (s4_axi_arcache),
.s4_axi_arprot (s4_axi_arprot),
.s4_axi_arqos (s4_axi_arqos),
.s4_axi_arvalid (s4_axi_arvalid),
.s4_axi_arready (s4_axi_arready),
.s4_axi_rid (s4_axi_rid),
.s4_axi_rdata (s4_axi_rdata),
.s4_axi_rresp (s4_axi_rresp),
.s4_axi_rlast (s4_axi_rlast),
.s4_axi_rvalid (s4_axi_rvalid),
.s4_axi_rready (s4_axi_rready),
.s5_axi_aclk (s5_axi_aclk),
.s5_axi_aresetn (s5_axi_aresetn),
.s5_axi_awid (s5_axi_awid),
.s5_axi_awaddr (s5_axi_awaddr),
.s5_axi_awlen (s5_axi_awlen),
.s5_axi_awsize (s5_axi_awsize),
.s5_axi_awburst (s5_axi_awburst),
.s5_axi_awlock (s5_axi_awlock),
.s5_axi_awcache (s5_axi_awcache),
.s5_axi_awprot (s5_axi_awprot),
.s5_axi_awqos (s5_axi_awqos),
.s5_axi_awvalid (s5_axi_awvalid),
.s5_axi_awready (s5_axi_awready),
.s5_axi_wdata (s5_axi_wdata),
.s5_axi_wstrb (s5_axi_wstrb),
.s5_axi_wlast (s5_axi_wlast),
.s5_axi_wvalid (s5_axi_wvalid),
.s5_axi_wready (s5_axi_wready),
.s5_axi_bid (s5_axi_bid),
.s5_axi_bresp (s5_axi_bresp),
.s5_axi_bvalid (s5_axi_bvalid),
.s5_axi_bready (s5_axi_bready),
.s5_axi_arid (s5_axi_arid),
.s5_axi_araddr (s5_axi_araddr),
.s5_axi_arlen (s5_axi_arlen),
.s5_axi_arsize (s5_axi_arsize),
.s5_axi_arburst (s5_axi_arburst),
.s5_axi_arlock (s5_axi_arlock),
.s5_axi_arcache (s5_axi_arcache),
.s5_axi_arprot (s5_axi_arprot),
.s5_axi_arqos (s5_axi_arqos),
.s5_axi_arvalid (s5_axi_arvalid),
.s5_axi_arready (s5_axi_arready),
.s5_axi_rid (s5_axi_rid),
.s5_axi_rdata (s5_axi_rdata),
.s5_axi_rresp (s5_axi_rresp),
.s5_axi_rlast (s5_axi_rlast),
.s5_axi_rvalid (s5_axi_rvalid),
.s5_axi_rready (s5_axi_rready)
);
endmodule
|
`timescale 1ns / 1ps
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:49:03 02/02/2015
// Design Name:
// Module Name: sha256
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module sha256_core (
input clk,
input load_i,
input [511:0] data_i,
input [255:0] state_i,
output [255:0] state_o,
output reg busy_o
);
localparam SHA256_MAX_STEP = 64;
`define STATE_LOAD(i) state_i[256 - (i * 32) - 1: 256 - (i * 32) - 32]
reg [31:0] A, B, C, D, E, F, G, H;
reg [31:0] A_new, B_new, C_new, D_new, E_new, F_new, G_new, H_new;
reg [31:0] HKW, HKW_new;
reg [6:0] step, step_new;
reg busy_new;
wire [31:0] W, K;
assign state_o = { A, B, C, D, E, F, G, H };
sha256_W W_inst(
.clk(clk),
.data_i(data_i),
.load_i(load_i),
.busy_i(busy_o),
.W_o(W)
);
sha256_K K_inst(
.step_i(step[5:0]),
.K_o(K)
);
always @(posedge clk)
begin
busy_o <= busy_new;
step <= step_new;
A <= A_new;
B <= B_new;
C <= C_new;
D <= D_new;
E <= E_new;
F <= F_new;
G <= G_new;
H <= H_new;
HKW <= HKW_new;
end
always @*
begin
step_new = 0;
if(~load_i & busy_o)
step_new = step + 1;
end
always @*
begin : HKW_update
reg [31:0] H_pre;
H_pre = G;
if(step == 0)
H_pre = `STATE_LOAD(7);
HKW_new = H_pre + K + W;
end
reg [31:0] T1, T2;
always @*
begin : T1_update
reg [31:0] Ch, S1;
Ch = (E & F) ^ (~E & G);
S1 = {E[5:0],E[31:6]} ^ {E[10:0],E[31:11]} ^ {E[24:0],E[31:25]};
T1 = S1 + Ch + HKW;
end
always @*
begin : T2_update
reg [31:0] Maj, S0;
Maj = (A & (B ^ C)) ^ (B & C);
S0 = {A[1:0],A[31:2]} ^ {A[12:0],A[31:13]} ^ {A[21:0],A[31:22]};
T2 = S0 + Maj;
end
always @*
begin
busy_new = 0;
A_new = A;
B_new = B;
C_new = C;
D_new = D;
E_new = E;
F_new = F;
G_new = G;
H_new = H;
if(load_i)
begin
busy_new = 1;
A_new = `STATE_LOAD(0);
B_new = `STATE_LOAD(1);
C_new = `STATE_LOAD(2);
D_new = `STATE_LOAD(3);
E_new = `STATE_LOAD(4);
F_new = `STATE_LOAD(5);
G_new = `STATE_LOAD(6);
H_new = `STATE_LOAD(7);
end
else if(busy_o)
begin
if(step == SHA256_MAX_STEP + 1)
begin
A_new = A + `STATE_LOAD(0);
B_new = B + `STATE_LOAD(1);
C_new = C + `STATE_LOAD(2);
D_new = D + `STATE_LOAD(3);
E_new = E + `STATE_LOAD(4);
F_new = F + `STATE_LOAD(5);
G_new = G + `STATE_LOAD(6);
H_new = H + `STATE_LOAD(7);
end
else if(step == 0)
begin
busy_new = 1;
A_new = A;
B_new = B;
C_new = C;
D_new = D;
E_new = E;
F_new = F;
G_new = G;
H_new = H;
end
else
begin
busy_new = 1;
A_new = T1 + T2;
B_new = A;
C_new = B;
D_new = C;
E_new = D + T1;
F_new = E;
G_new = F;
H_new = G;
end
end
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:27:32 06/14/2012
// Design Name:
// Module Name: reorder_queue
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// Reorders downstream TLPs to output in increasing tag sequence. Input packets
// are stored in RAM and then read out when all previous sequence numbers have
// arrived and been read out. This module also provides the next available tag
// for the TX engine to use when sending memory request TLPs.
//
// Dependencies:
// reorder_queue_input.v
// reorder_queue_output.v
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "trellis.vh"
`timescale 1ns / 1ps
module reorder_queue
#(
parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_NUM_CHNL = 4'd12,
parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
// Local parameters
parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
parameter C_PCI_DATA_COUNT_WIDTH = clog2(C_PCI_DATA_WORD+1),
parameter C_NUM_TAGS = 2**C_TAG_WIDTH,
parameter C_DW_PER_TAG = C_MAX_READ_REQ_BYTES/4,
parameter C_TAG_DW_COUNT_WIDTH = clog2s(C_DW_PER_TAG+1),
parameter C_DATA_ADDR_STRIDE_WIDTH = clog2s(C_DW_PER_TAG/C_PCI_DATA_WORD), // div by C_PCI_DATA_WORD b/c there are C_PCI_DATA_WORD RAMs
parameter C_DATA_ADDR_WIDTH = C_TAG_WIDTH + C_DATA_ADDR_STRIDE_WIDTH
)
(
input CLK, // Clock
input RST, // Synchronous reset
input VALID, // Valid input packet
input [C_PCI_DATA_WIDTH-1:0] DATA, // Input packet payload
input [(C_PCI_DATA_WIDTH/32)-1:0] DATA_EN, // Input packet payload data enable
input DATA_START_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_START_OFFSET, // Input packet payload data enable count
input DATA_END_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_END_OFFSET, // Input packet payload data enable count
input DONE, // Input packet done
input ERR, // Input packet has error
input [C_TAG_WIDTH-1:0] TAG, // Input packet tag (external tag)
input [5:0] INT_TAG, // Internal tag to exchange with external
input INT_TAG_VALID, // High to signal tag exchange
output [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
output EXT_TAG_VALID, // High to signal external tag is valid
output [C_PCI_DATA_WIDTH-1:0] ENG_DATA, // Engine data
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN, // Main data enable
output [C_NUM_CHNL-1:0] MAIN_DONE, // Main data complete
output [C_NUM_CHNL-1:0] MAIN_ERR, // Main data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN, // Scatter gather for RX data enable
output [C_NUM_CHNL-1:0] SG_RX_DONE, // Scatter gather for RX data complete
output [C_NUM_CHNL-1:0] SG_RX_ERR, // Scatter gather for RX data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN, // Scatter gather for TX data enable
output [C_NUM_CHNL-1:0] SG_TX_DONE, // Scatter gather for TX data complete
output [C_NUM_CHNL-1:0] SG_TX_ERR // Scatter gather for TX data completed with error
);
wire [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0] wWrDataAddr;
wire [C_PCI_DATA_WIDTH-1:0] wWrData;
wire [C_PCI_DATA_WORD-1:0] wWrDataEn;
wire [C_TAG_WIDTH-1:0] wWrPktTag;
wire [C_TAG_DW_COUNT_WIDTH-1:0] wWrPktWords;
wire wWrPktWordsLTE1;
wire wWrPktWordsLTE2;
wire wWrPktValid;
wire wWrPktDone;
wire wWrPktErr;
wire [C_DATA_ADDR_WIDTH-1:0] wRdDataAddr;
wire [C_PCI_DATA_WIDTH-1:0] wRdData;
wire [C_TAG_WIDTH-1:0] wRdPktTag;
wire [(1+1+1+1+C_TAG_DW_COUNT_WIDTH)-1:0] wRdPktInfo;
wire [5:0] wRdTagMap;
wire [C_NUM_TAGS-1:0] wFinish;
wire [C_NUM_TAGS-1:0] wClear;
reg [C_TAG_WIDTH-1:0] rPos=0;
reg rValid=0;
reg [C_NUM_TAGS-1:0] rFinished=0;
reg [C_NUM_TAGS-1:0] rUse=0;
reg [C_NUM_TAGS-1:0] rUsing=0;
assign EXT_TAG = rPos;
assign EXT_TAG_VALID = rValid;
// Move through tag/slot/bucket space.
always @ (posedge CLK) begin
if (RST) begin
rPos <= #1 0;
rUse <= #1 0;
rValid <= #1 0;
end
else begin
if (INT_TAG_VALID & EXT_TAG_VALID) begin
rPos <= #1 rPos + 1'd1;
rUse <= #1 1<<rPos;
rValid <= #1 !rUsing[rPos + 1'd1];
end
else begin
rUse <= #1 0;
rValid <= #1 !rUsing[rPos];
end
end
end
// Update tag/slot/bucket status.
always @ (posedge CLK) begin
if (RST) begin
rUsing <= #1 0;
rFinished <= #1 0;
end
else begin
rUsing <= #1 (rUsing | rUse) & ~wClear;
rFinished <= #1 (rFinished | wFinish) & ~wClear;
end
end
genvar r;
generate
for (r = 0; r < C_PCI_DATA_WORD; r = r + 1) begin : rams
// RAMs for packet reordering.
(* RAM_STYLE="BLOCK" *)
ram_1clk_1w_1r
#(.C_RAM_WIDTH(32),
.C_RAM_DEPTH(C_NUM_TAGS*C_DW_PER_TAG/C_PCI_DATA_WORD)
)
ram
(
.CLK(CLK),
.ADDRA(wWrDataAddr[C_DATA_ADDR_WIDTH*r +:C_DATA_ADDR_WIDTH]),
.WEA(wWrDataEn[r]),
.DINA(wWrData[32*r +:32]),
.ADDRB(wRdDataAddr),
.DOUTB(wRdData[32*r +:32])
);
end
endgenerate
// RAM for bucket done, err, final DW count
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(.C_RAM_WIDTH(1 + 1 + 1 + 1 + C_TAG_DW_COUNT_WIDTH),
.C_RAM_DEPTH(C_NUM_TAGS))
pktRam
(
.CLK(CLK),
.ADDRA(wWrPktTag),
.WEA((wWrPktDone | wWrPktErr) & wWrPktValid),
.DINA({wWrPktDone, wWrPktErr, wWrPktWordsLTE2, wWrPktWordsLTE1, wWrPktWords}),
.ADDRB(wRdPktTag),
.DOUTB(wRdPktInfo)
);
// RAM for tag map
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(.C_RAM_WIDTH(6),
.C_RAM_DEPTH(C_NUM_TAGS))
mapRam
(
.CLK(CLK),
.ADDRA(rPos),
.WEA(INT_TAG_VALID & EXT_TAG_VALID),
.DINA(INT_TAG),
.ADDRB(wRdPktTag),
.DOUTB(wRdTagMap)
);
// Demux input data into the correct slot/bucket.
reorder_queue_input
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_TAG_WIDTH(C_TAG_WIDTH),
.C_TAG_DW_COUNT_WIDTH(C_TAG_DW_COUNT_WIDTH),
.C_DATA_ADDR_STRIDE_WIDTH(C_DATA_ADDR_STRIDE_WIDTH),
.C_DATA_ADDR_WIDTH(C_DATA_ADDR_WIDTH)
)
data_input
(
.CLK(CLK),
.RST(RST),
.VALID(VALID),
.DATA_START_FLAG (DATA_START_FLAG),
.DATA_START_OFFSET (DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA_END_FLAG (DATA_END_FLAG),
.DATA_END_OFFSET (DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA (DATA),
.DATA_EN (DATA_EN),
.DONE(DONE),
.ERR(ERR),
.TAG(TAG),
.TAG_FINISH(wFinish),
.TAG_CLEAR(wClear),
.STORED_DATA_ADDR(wWrDataAddr),
.STORED_DATA(wWrData),
.STORED_DATA_EN(wWrDataEn),
.PKT_VALID(wWrPktValid),
.PKT_TAG(wWrPktTag),
.PKT_WORDS(wWrPktWords),
.PKT_WORDS_LTE1(wWrPktWordsLTE1),
.PKT_WORDS_LTE2(wWrPktWordsLTE2),
.PKT_DONE(wWrPktDone),
.PKT_ERR(wWrPktErr)
);
// Output packets in increasing tag order.
reorder_queue_output
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_TAG_WIDTH(C_TAG_WIDTH),
.C_TAG_DW_COUNT_WIDTH(C_TAG_DW_COUNT_WIDTH),
.C_DATA_ADDR_STRIDE_WIDTH(C_DATA_ADDR_STRIDE_WIDTH),
.C_DATA_ADDR_WIDTH(C_DATA_ADDR_WIDTH)
)
data_output
(
.CLK(CLK),
.RST(RST),
.DATA_ADDR(wRdDataAddr),
.DATA(wRdData),
.TAG_FINISHED(rFinished),
.TAG_CLEAR(wClear),
.TAG(wRdPktTag),
.TAG_MAPPED(wRdTagMap),
.PKT_WORDS(wRdPktInfo[0 +:C_TAG_DW_COUNT_WIDTH]),
.PKT_WORDS_LTE1(wRdPktInfo[C_TAG_DW_COUNT_WIDTH]),
.PKT_WORDS_LTE2(wRdPktInfo[C_TAG_DW_COUNT_WIDTH+1]),
.PKT_ERR(wRdPktInfo[C_TAG_DW_COUNT_WIDTH+2]),
.PKT_DONE(wRdPktInfo[C_TAG_DW_COUNT_WIDTH+3]),
.ENG_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : axi_basic_tx.v
//----------------------------------------------------------------------------//
// File: axi_basic_tx.v //
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TKEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [STRB_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
/**
* @module EX_MEM
* @author sabertazimi
* @email [email protected]
* @brief EX_MEM pipeline register
* @input clk clock signal
* @input rst reset signal
* @input en load enable signal
* @input EX_PC PC value in EX stage
* @input EX_IR instruction value in EX stage
* @input EX_writetolo writetolo signal in EX stage
* @input EX_regwe regwe signal in EX stage
* @input EX_ramtoreg ramtoreg signal in EX stage
* @input EX_lotoreg lotoreg signal in EX stage
* @input EX_syscall syscall signal in EX stage
* @input EX_ramwe ramwe signal in EX stage
* @input EX_rambyte rambyte signal in EX stage
* @input EX_rt rt value in EX stage
* @input EX_result result value in EX stage
* @input EX_RW RW value in EX stage
* @input EX_r2 r2 value in EX stage
* @output MEM_PC PC value in MEM stage
* @output MEM_IR instruction value in MEM stage
* @output MEM_writetolo writetolo signal in MEM stage
* @output MEM_regwe regwe signal in MEM stage
* @output MEM_ramtoreg ramtoreg signal in MEM stage
* @output MEM_lotoreg lotoreg signal in MEM stage
* @output MEM_syscall syscall signal in MEM stage
* @output MEM_ramwe ramwe signal in MEM stage
* @output MEM_rambyte rambyte signal in MEM stage
* @output MEM_rt rt value in MEM stage
* @output MEM_result result value in MEM stage
* @output MEM_RW RW value in MEM stage
* @output MEM_r2 r2 value in MEM stage
*/
module EX_MEM
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input en,
input [DATA_WIDTH-1:0] EX_PC,
input [DATA_WIDTH-1:0] EX_IR,
input EX_writetolo,
input EX_regwe,
input EX_ramtoreg,
input EX_lotoreg,
input EX_syscall,
input EX_ramwe,
input EX_rambyte,
input [4:0] EX_rt,
input [DATA_WIDTH-1:0] EX_result,
input [4:0] EX_RW,
input [DATA_WIDTH-1:0] EX_r2,
output [DATA_WIDTH-1:0] MEM_PC,
output [DATA_WIDTH-1:0] MEM_IR,
output MEM_writetolo,
output MEM_regwe,
output MEM_ramtoreg,
output MEM_lotoreg,
output MEM_syscall,
output MEM_ramwe,
output MEM_rambyte,
output [4:0] MEM_rt,
output [DATA_WIDTH-1:0] MEM_result,
output [4:0] MEM_RW,
output [DATA_WIDTH-1:0] MEM_r2
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) PC (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_PC),
.dout(MEM_PC)
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) IR (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_IR),
.dout(MEM_IR)
);
register #(
.DATA_WIDTH(1)
) writetolo (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_writetolo),
.dout(MEM_writetolo)
);
register #(
.DATA_WIDTH(1)
) regwe (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_regwe),
.dout(MEM_regwe)
);
register #(
.DATA_WIDTH(1)
) ramtoreg (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_ramtoreg),
.dout(MEM_ramtoreg)
);
register #(
.DATA_WIDTH(1)
) lotoreg (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_lotoreg),
.dout(MEM_lotoreg)
);
register #(
.DATA_WIDTH(1)
) syscall (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_syscall),
.dout(MEM_syscall)
);
register #(
.DATA_WIDTH(1)
) ramwe (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_ramwe),
.dout(MEM_ramwe)
);
register #(
.DATA_WIDTH(1)
) rambyte (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_rambyte),
.dout(MEM_rambyte)
);
register #(
.DATA_WIDTH(5)
) rt (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_rt),
.dout(MEM_rt)
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) result (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_result),
.dout(MEM_result)
);
register #(
.DATA_WIDTH(5)
) RW (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_RW),
.dout(MEM_RW)
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) r2 (
.clk(clk),
.rst(rst),
.en(en),
.din(EX_r2),
.dout(MEM_r2)
);
endmodule // EX_MEM
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V
/**
* mux4: 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_4to2/sky130_fd_sc_hd__udp_mux_4to2.v"
`celldefine
module sky130_fd_sc_hd__mux4 (
X ,
A0 ,
A1 ,
A2 ,
A3 ,
S0 ,
S1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A0 ;
input A1 ;
input A2 ;
input A3 ;
input S0 ;
input S1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_4to20_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_4to2 mux_4to20 (mux_4to20_out_X , A0, A1, A2, A3, S0, S1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, mux_4to20_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MUX4_FUNCTIONAL_PP_V |
module mojo_top(
// 50MHz clock input
input clk,
// Input from rst button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard leds
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
output [23:0] io_led, // LEDs on IO Shield
output [7:0] io_seg, // 7-segment LEDs on IO Shield
output [3:0] io_sel, // Digit select on IO Shield
input [3:0] F,
input en,
input [23:0] io_dip,
output [3:0] D,
output [3:0] Q,
output A,
output B,
output A_latch,
output B_latch
);
wire rst = ~rst_n; // make rst active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
reg [26:0] slow_clk_d, slow_clk_q;
always @(slow_clk_q) begin
if (~io_dip[23] & ~io_dip[22]) begin
slow_clk_d = slow_clk_q + 2'b1;
end else if (io_dip[23] & ~io_dip[22]) begin
slow_clk_d = slow_clk_q + 2'b10;
end else if (~io_dip[23] & io_dip[22]) begin
slow_clk_d = slow_clk_q + 3'b100;
end else begin
slow_clk_d = slow_clk_q + 4'b1000;
end
end
always @(posedge clk, posedge rst) begin
if (rst == 1) begin
slow_clk_q <= 27'b0;
end
else begin
slow_clk_q <= slow_clk_d;
end
end
assign led[7:4] = {4{slow_clk_q[26]}};
assign io_led[23:0] = {24{slow_clk_q[26]}};
assign io_sel[3:0] = 4'b0000;
elevator real_deal (
.clk(slow_clk_q[26]),
.reset(rst),
.en(~en),
.F(F),
.D(D),
.Q(Q),
.A(A),
.B(B),
.A_latch(A_latch),
.B_latch(B_latch),
.LED(led[3:0]),
.io_seg(io_seg)
);
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 20:36:12
// Design Name:
// Module Name: D_behavior_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module D_behavior_tb(
);
reg D, Clk;
wire Qa, Qb, Qc;
D_behavior DUT (.D(D), .Clk(Clk), .Qa(Qa), .Qb(Qb), .Qc(Qc));
initial begin
#180 $finish;
end
initial begin
Clk = 0; D = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 D = 1;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; D = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 D = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; D = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
#20;
end
endmodule
|
module fifo_full_block (/*AUTOARG*/
// Outputs
wr_fifo_full, wr_fifo_almost_full, wr_addr, wr_gray_pointer,
// Inputs
reset, wr_clk, wr_rd_gray_pointer, wr_write
);
parameter AW = 2; // Number of bits to access all the entries
//##########
//# INPUTS
//##########
input reset;
input wr_clk;
input [AW:0] wr_rd_gray_pointer;//synced from read domain
input wr_write;
//###########
//# OUTPUTS
//###########
output wr_fifo_full;
output wr_fifo_almost_full;
output [AW-1:0] wr_addr;
output [AW:0] wr_gray_pointer;//for read domain
//#########
//# REGS
//#########
reg [AW:0] wr_gray_pointer;
reg [AW:0] wr_binary_pointer;
reg wr_fifo_full;
//##########
//# WIRES
//##########
wire wr_fifo_full_next;
wire [AW:0] wr_gray_next;
wire [AW:0] wr_binary_next;
wire wr_fifo_almost_full_next;
reg wr_fifo_almost_full;
//Counter States
always @(posedge wr_clk or posedge reset)
if(reset)
begin
wr_binary_pointer[AW:0] <= {(AW+1){1'b0}};
wr_gray_pointer[AW:0] <= {(AW+1){1'b0}};
end
else if(wr_write)
begin
wr_binary_pointer[AW:0] <= wr_binary_next[AW:0];
wr_gray_pointer[AW:0] <= wr_gray_next[AW:0];
end
//Write Address
assign wr_addr[AW-1:0] = wr_binary_pointer[AW-1:0];
//Updating binary pointer
assign wr_binary_next[AW:0] = wr_binary_pointer[AW:0] +
{{(AW){1'b0}},wr_write};
//Gray Pointer Conversion (for more reliable synchronization)!
assign wr_gray_next[AW:0] = {1'b0,wr_binary_next[AW:1]} ^
wr_binary_next[AW:0];
//FIFO full indication
assign wr_fifo_full_next =
(wr_gray_next[AW-2:0] == wr_rd_gray_pointer[AW-2:0]) &
(wr_gray_next[AW] ^ wr_rd_gray_pointer[AW]) &
(wr_gray_next[AW-1] ^ wr_rd_gray_pointer[AW-1]);
always @ (posedge wr_clk or posedge reset)
if(reset)
wr_fifo_full <= 1'b0;
else
wr_fifo_full <=wr_fifo_full_next;
//FIFO almost full
assign wr_fifo_almost_full_next =
(wr_gray_next[AW-3:0] == wr_rd_gray_pointer[AW-3:0]) &
(wr_gray_next[AW] ^ wr_rd_gray_pointer[AW]) &
(wr_gray_next[AW-1] ^ wr_rd_gray_pointer[AW-1]) &
(wr_gray_next[AW-2] ^ wr_rd_gray_pointer[AW-2]);
always @ (posedge wr_clk or posedge reset)
if(reset)
wr_fifo_almost_full <= 1'b0;
else
wr_fifo_almost_full <=wr_fifo_almost_full_next;
endmodule // fifo_full_block
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: write_data_path.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This is top level of write path .
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_write_data_path #(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_TYPE = "DDR3",
parameter ADDR_WIDTH = 32,
parameter START_ADDR = 32'h00000000,
parameter BL_WIDTH = 6,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_BURST_LEN = 8,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10,
parameter EYE_TEST = "FALSE"
)
(
input clk_i,
input [9:0] rst_i,
output cmd_rdy_o,
input cmd_valid_i,
input cmd_validB_i,
input cmd_validC_i,
input [31:0] prbs_fseed_i,
input [3:0] data_mode_i,
input mem_init_done_i,
input wr_data_mask_gen_i,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input mode_load_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
// input [5:0] port_data_counts_i,// connect to data port fifo counts
input memc_cmd_full_i,
input data_rdy_i,
output data_valid_o,
output last_word_wr_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o,
output [(NUM_DQ_PINS*nCK_PER_CLK*2/8) - 1:0] data_mask_o,
output data_wr_end_o
);
wire data_valid;
reg cmd_rdy;
assign data_valid_o = data_valid;// & data_rdy_i;
mig_7series_v2_3_wr_data_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_BURST_LEN (MEM_BURST_LEN),
.BL_WIDTH (BL_WIDTH),
.START_ADDR (START_ADDR),
.nCK_PER_CLK (nCK_PER_CLK),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH (DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH),
.EYE_TEST (EYE_TEST)
)
wr_data_gen(
.clk_i (clk_i ),
.rst_i (rst_i[9:5]),
.prbs_fseed_i (prbs_fseed_i),
.wr_data_mask_gen_i (wr_data_mask_gen_i),
.mem_init_done_i (mem_init_done_i),
.data_mode_i (data_mode_i ),
.cmd_rdy_o (cmd_rdy_o ),
.cmd_valid_i (cmd_valid_i ),
.cmd_validB_i (cmd_validB_i ),
.cmd_validC_i (cmd_validC_i ),
.last_word_o (last_word_wr_o ),
// .port_data_counts_i (port_data_counts_i),
// .m_addr_i (m_addr_i ),
.fixed_data_i (fixed_data_i),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.mode_load_i (mode_load_i),
.addr_i (addr_i ),
.bl_i (bl_i ),
.memc_cmd_full_i (memc_cmd_full_i),
.data_rdy_i (data_rdy_i ),
.data_valid_o ( data_valid ),
.data_o (data_o ),
.data_wr_end_o (data_wr_end_o),
.data_mask_o (data_mask_o)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2010 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
module t ();
`ifndef VERILATOR
`error "Only Verilator supports PLI-ish DPI calls and sformat conversion."
`endif
import "DPI-C" context dpii_display_call
= function void \$dpii_display (input string formatted /*verilator sformat*/ );
integer a;
initial begin
// Check variable width constant string conversions
$dpii_display("");
$dpii_display("c");
$dpii_display("co");
$dpii_display("cons");
$dpii_display("constant");
$dpii_display("constant_value");
a = $c("10"); // Don't optimize away "a"
$display ("one10=%x ",a); // Check single arg
$dpii_display("one10=%x ",a);
$display ("Mod=%m 16=%d 10=%x ",a,a); // Check multiarg
$dpii_display("Mod=%m 16=%d 10=%x ",a,a);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
//
// Generated by Bluespec Compiler, version 2021.07 (build 4cac6eb)
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// RDY_set_verbosity O 1 const
// v_from_masters_0_awready O 1 reg
// v_from_masters_0_wready O 1 reg
// v_from_masters_0_bvalid O 1 reg
// v_from_masters_0_bid O 16 reg
// v_from_masters_0_bresp O 2 reg
// v_from_masters_0_arready O 1 reg
// v_from_masters_0_rvalid O 1 reg
// v_from_masters_0_rid O 16 reg
// v_from_masters_0_rdata O 64 reg
// v_from_masters_0_rresp O 2 reg
// v_from_masters_0_rlast O 1 reg
// v_to_slaves_0_awvalid O 1 reg
// v_to_slaves_0_awid O 16 reg
// v_to_slaves_0_awaddr O 64 reg
// v_to_slaves_0_awlen O 8 reg
// v_to_slaves_0_awsize O 3 reg
// v_to_slaves_0_awburst O 2 reg
// v_to_slaves_0_awlock O 1 reg
// v_to_slaves_0_awcache O 4 reg
// v_to_slaves_0_awprot O 3 reg
// v_to_slaves_0_awqos O 4 reg
// v_to_slaves_0_awregion O 4 reg
// v_to_slaves_0_wvalid O 1 reg
// v_to_slaves_0_wdata O 64 reg
// v_to_slaves_0_wstrb O 8 reg
// v_to_slaves_0_wlast O 1 reg
// v_to_slaves_0_bready O 1 reg
// v_to_slaves_0_arvalid O 1 reg
// v_to_slaves_0_arid O 16 reg
// v_to_slaves_0_araddr O 64 reg
// v_to_slaves_0_arlen O 8 reg
// v_to_slaves_0_arsize O 3 reg
// v_to_slaves_0_arburst O 2 reg
// v_to_slaves_0_arlock O 1 reg
// v_to_slaves_0_arcache O 4 reg
// v_to_slaves_0_arprot O 3 reg
// v_to_slaves_0_arqos O 4 reg
// v_to_slaves_0_arregion O 4 reg
// v_to_slaves_0_rready O 1 reg
// v_to_slaves_1_awvalid O 1 reg
// v_to_slaves_1_awid O 16 reg
// v_to_slaves_1_awaddr O 64 reg
// v_to_slaves_1_awlen O 8 reg
// v_to_slaves_1_awsize O 3 reg
// v_to_slaves_1_awburst O 2 reg
// v_to_slaves_1_awlock O 1 reg
// v_to_slaves_1_awcache O 4 reg
// v_to_slaves_1_awprot O 3 reg
// v_to_slaves_1_awqos O 4 reg
// v_to_slaves_1_awregion O 4 reg
// v_to_slaves_1_wvalid O 1 reg
// v_to_slaves_1_wdata O 64 reg
// v_to_slaves_1_wstrb O 8 reg
// v_to_slaves_1_wlast O 1 reg
// v_to_slaves_1_bready O 1 reg
// v_to_slaves_1_arvalid O 1 reg
// v_to_slaves_1_arid O 16 reg
// v_to_slaves_1_araddr O 64 reg
// v_to_slaves_1_arlen O 8 reg
// v_to_slaves_1_arsize O 3 reg
// v_to_slaves_1_arburst O 2 reg
// v_to_slaves_1_arlock O 1 reg
// v_to_slaves_1_arcache O 4 reg
// v_to_slaves_1_arprot O 3 reg
// v_to_slaves_1_arqos O 4 reg
// v_to_slaves_1_arregion O 4 reg
// v_to_slaves_1_rready O 1 reg
// v_to_slaves_2_awvalid O 1 reg
// v_to_slaves_2_awid O 16 reg
// v_to_slaves_2_awaddr O 64 reg
// v_to_slaves_2_awlen O 8 reg
// v_to_slaves_2_awsize O 3 reg
// v_to_slaves_2_awburst O 2 reg
// v_to_slaves_2_awlock O 1 reg
// v_to_slaves_2_awcache O 4 reg
// v_to_slaves_2_awprot O 3 reg
// v_to_slaves_2_awqos O 4 reg
// v_to_slaves_2_awregion O 4 reg
// v_to_slaves_2_wvalid O 1 reg
// v_to_slaves_2_wdata O 64 reg
// v_to_slaves_2_wstrb O 8 reg
// v_to_slaves_2_wlast O 1 reg
// v_to_slaves_2_bready O 1 reg
// v_to_slaves_2_arvalid O 1 reg
// v_to_slaves_2_arid O 16 reg
// v_to_slaves_2_araddr O 64 reg
// v_to_slaves_2_arlen O 8 reg
// v_to_slaves_2_arsize O 3 reg
// v_to_slaves_2_arburst O 2 reg
// v_to_slaves_2_arlock O 1 reg
// v_to_slaves_2_arcache O 4 reg
// v_to_slaves_2_arprot O 3 reg
// v_to_slaves_2_arqos O 4 reg
// v_to_slaves_2_arregion O 4 reg
// v_to_slaves_2_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// v_from_masters_0_awvalid I 1
// v_from_masters_0_awid I 16 reg
// v_from_masters_0_awaddr I 64 reg
// v_from_masters_0_awlen I 8 reg
// v_from_masters_0_awsize I 3 reg
// v_from_masters_0_awburst I 2 reg
// v_from_masters_0_awlock I 1 reg
// v_from_masters_0_awcache I 4 reg
// v_from_masters_0_awprot I 3 reg
// v_from_masters_0_awqos I 4 reg
// v_from_masters_0_awregion I 4 reg
// v_from_masters_0_wvalid I 1
// v_from_masters_0_wdata I 64 reg
// v_from_masters_0_wstrb I 8 reg
// v_from_masters_0_wlast I 1 reg
// v_from_masters_0_bready I 1
// v_from_masters_0_arvalid I 1
// v_from_masters_0_arid I 16 reg
// v_from_masters_0_araddr I 64 reg
// v_from_masters_0_arlen I 8 reg
// v_from_masters_0_arsize I 3 reg
// v_from_masters_0_arburst I 2 reg
// v_from_masters_0_arlock I 1 reg
// v_from_masters_0_arcache I 4 reg
// v_from_masters_0_arprot I 3 reg
// v_from_masters_0_arqos I 4 reg
// v_from_masters_0_arregion I 4 reg
// v_from_masters_0_rready I 1
// v_to_slaves_0_awready I 1
// v_to_slaves_0_wready I 1
// v_to_slaves_0_bvalid I 1
// v_to_slaves_0_bid I 16 reg
// v_to_slaves_0_bresp I 2 reg
// v_to_slaves_0_arready I 1
// v_to_slaves_0_rvalid I 1
// v_to_slaves_0_rid I 16 reg
// v_to_slaves_0_rdata I 64 reg
// v_to_slaves_0_rresp I 2 reg
// v_to_slaves_0_rlast I 1 reg
// v_to_slaves_1_awready I 1
// v_to_slaves_1_wready I 1
// v_to_slaves_1_bvalid I 1
// v_to_slaves_1_bid I 16 reg
// v_to_slaves_1_bresp I 2 reg
// v_to_slaves_1_arready I 1
// v_to_slaves_1_rvalid I 1
// v_to_slaves_1_rid I 16 reg
// v_to_slaves_1_rdata I 64 reg
// v_to_slaves_1_rresp I 2 reg
// v_to_slaves_1_rlast I 1 reg
// v_to_slaves_2_awready I 1
// v_to_slaves_2_wready I 1
// v_to_slaves_2_bvalid I 1
// v_to_slaves_2_bid I 16 reg
// v_to_slaves_2_bresp I 2 reg
// v_to_slaves_2_arready I 1
// v_to_slaves_2_rvalid I 1
// v_to_slaves_2_rid I 16 reg
// v_to_slaves_2_rdata I 64 reg
// v_to_slaves_2_rresp I 2 reg
// v_to_slaves_2_rlast I 1 reg
// EN_reset I 1
// EN_set_verbosity I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFabric_1x3(CLK,
RST_N,
EN_reset,
RDY_reset,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
v_from_masters_0_awvalid,
v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion,
v_from_masters_0_awready,
v_from_masters_0_wvalid,
v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast,
v_from_masters_0_wready,
v_from_masters_0_bvalid,
v_from_masters_0_bid,
v_from_masters_0_bresp,
v_from_masters_0_bready,
v_from_masters_0_arvalid,
v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion,
v_from_masters_0_arready,
v_from_masters_0_rvalid,
v_from_masters_0_rid,
v_from_masters_0_rdata,
v_from_masters_0_rresp,
v_from_masters_0_rlast,
v_from_masters_0_rready,
v_to_slaves_0_awvalid,
v_to_slaves_0_awid,
v_to_slaves_0_awaddr,
v_to_slaves_0_awlen,
v_to_slaves_0_awsize,
v_to_slaves_0_awburst,
v_to_slaves_0_awlock,
v_to_slaves_0_awcache,
v_to_slaves_0_awprot,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_0_awready,
v_to_slaves_0_wvalid,
v_to_slaves_0_wdata,
v_to_slaves_0_wstrb,
v_to_slaves_0_wlast,
v_to_slaves_0_wready,
v_to_slaves_0_bvalid,
v_to_slaves_0_bid,
v_to_slaves_0_bresp,
v_to_slaves_0_bready,
v_to_slaves_0_arvalid,
v_to_slaves_0_arid,
v_to_slaves_0_araddr,
v_to_slaves_0_arlen,
v_to_slaves_0_arsize,
v_to_slaves_0_arburst,
v_to_slaves_0_arlock,
v_to_slaves_0_arcache,
v_to_slaves_0_arprot,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_arready,
v_to_slaves_0_rvalid,
v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast,
v_to_slaves_0_rready,
v_to_slaves_1_awvalid,
v_to_slaves_1_awid,
v_to_slaves_1_awaddr,
v_to_slaves_1_awlen,
v_to_slaves_1_awsize,
v_to_slaves_1_awburst,
v_to_slaves_1_awlock,
v_to_slaves_1_awcache,
v_to_slaves_1_awprot,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_1_awready,
v_to_slaves_1_wvalid,
v_to_slaves_1_wdata,
v_to_slaves_1_wstrb,
v_to_slaves_1_wlast,
v_to_slaves_1_wready,
v_to_slaves_1_bvalid,
v_to_slaves_1_bid,
v_to_slaves_1_bresp,
v_to_slaves_1_bready,
v_to_slaves_1_arvalid,
v_to_slaves_1_arid,
v_to_slaves_1_araddr,
v_to_slaves_1_arlen,
v_to_slaves_1_arsize,
v_to_slaves_1_arburst,
v_to_slaves_1_arlock,
v_to_slaves_1_arcache,
v_to_slaves_1_arprot,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_arready,
v_to_slaves_1_rvalid,
v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast,
v_to_slaves_1_rready,
v_to_slaves_2_awvalid,
v_to_slaves_2_awid,
v_to_slaves_2_awaddr,
v_to_slaves_2_awlen,
v_to_slaves_2_awsize,
v_to_slaves_2_awburst,
v_to_slaves_2_awlock,
v_to_slaves_2_awcache,
v_to_slaves_2_awprot,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion,
v_to_slaves_2_awready,
v_to_slaves_2_wvalid,
v_to_slaves_2_wdata,
v_to_slaves_2_wstrb,
v_to_slaves_2_wlast,
v_to_slaves_2_wready,
v_to_slaves_2_bvalid,
v_to_slaves_2_bid,
v_to_slaves_2_bresp,
v_to_slaves_2_bready,
v_to_slaves_2_arvalid,
v_to_slaves_2_arid,
v_to_slaves_2_araddr,
v_to_slaves_2_arlen,
v_to_slaves_2_arsize,
v_to_slaves_2_arburst,
v_to_slaves_2_arlock,
v_to_slaves_2_arcache,
v_to_slaves_2_arprot,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_arready,
v_to_slaves_2_rvalid,
v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast,
v_to_slaves_2_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method v_from_masters_0_m_awvalid
input v_from_masters_0_awvalid;
input [15 : 0] v_from_masters_0_awid;
input [63 : 0] v_from_masters_0_awaddr;
input [7 : 0] v_from_masters_0_awlen;
input [2 : 0] v_from_masters_0_awsize;
input [1 : 0] v_from_masters_0_awburst;
input v_from_masters_0_awlock;
input [3 : 0] v_from_masters_0_awcache;
input [2 : 0] v_from_masters_0_awprot;
input [3 : 0] v_from_masters_0_awqos;
input [3 : 0] v_from_masters_0_awregion;
// value method v_from_masters_0_m_awready
output v_from_masters_0_awready;
// action method v_from_masters_0_m_wvalid
input v_from_masters_0_wvalid;
input [63 : 0] v_from_masters_0_wdata;
input [7 : 0] v_from_masters_0_wstrb;
input v_from_masters_0_wlast;
// value method v_from_masters_0_m_wready
output v_from_masters_0_wready;
// value method v_from_masters_0_m_bvalid
output v_from_masters_0_bvalid;
// value method v_from_masters_0_m_bid
output [15 : 0] v_from_masters_0_bid;
// value method v_from_masters_0_m_bresp
output [1 : 0] v_from_masters_0_bresp;
// value method v_from_masters_0_m_buser
// action method v_from_masters_0_m_bready
input v_from_masters_0_bready;
// action method v_from_masters_0_m_arvalid
input v_from_masters_0_arvalid;
input [15 : 0] v_from_masters_0_arid;
input [63 : 0] v_from_masters_0_araddr;
input [7 : 0] v_from_masters_0_arlen;
input [2 : 0] v_from_masters_0_arsize;
input [1 : 0] v_from_masters_0_arburst;
input v_from_masters_0_arlock;
input [3 : 0] v_from_masters_0_arcache;
input [2 : 0] v_from_masters_0_arprot;
input [3 : 0] v_from_masters_0_arqos;
input [3 : 0] v_from_masters_0_arregion;
// value method v_from_masters_0_m_arready
output v_from_masters_0_arready;
// value method v_from_masters_0_m_rvalid
output v_from_masters_0_rvalid;
// value method v_from_masters_0_m_rid
output [15 : 0] v_from_masters_0_rid;
// value method v_from_masters_0_m_rdata
output [63 : 0] v_from_masters_0_rdata;
// value method v_from_masters_0_m_rresp
output [1 : 0] v_from_masters_0_rresp;
// value method v_from_masters_0_m_rlast
output v_from_masters_0_rlast;
// value method v_from_masters_0_m_ruser
// action method v_from_masters_0_m_rready
input v_from_masters_0_rready;
// value method v_to_slaves_0_m_awvalid
output v_to_slaves_0_awvalid;
// value method v_to_slaves_0_m_awid
output [15 : 0] v_to_slaves_0_awid;
// value method v_to_slaves_0_m_awaddr
output [63 : 0] v_to_slaves_0_awaddr;
// value method v_to_slaves_0_m_awlen
output [7 : 0] v_to_slaves_0_awlen;
// value method v_to_slaves_0_m_awsize
output [2 : 0] v_to_slaves_0_awsize;
// value method v_to_slaves_0_m_awburst
output [1 : 0] v_to_slaves_0_awburst;
// value method v_to_slaves_0_m_awlock
output v_to_slaves_0_awlock;
// value method v_to_slaves_0_m_awcache
output [3 : 0] v_to_slaves_0_awcache;
// value method v_to_slaves_0_m_awprot
output [2 : 0] v_to_slaves_0_awprot;
// value method v_to_slaves_0_m_awqos
output [3 : 0] v_to_slaves_0_awqos;
// value method v_to_slaves_0_m_awregion
output [3 : 0] v_to_slaves_0_awregion;
// value method v_to_slaves_0_m_awuser
// action method v_to_slaves_0_m_awready
input v_to_slaves_0_awready;
// value method v_to_slaves_0_m_wvalid
output v_to_slaves_0_wvalid;
// value method v_to_slaves_0_m_wdata
output [63 : 0] v_to_slaves_0_wdata;
// value method v_to_slaves_0_m_wstrb
output [7 : 0] v_to_slaves_0_wstrb;
// value method v_to_slaves_0_m_wlast
output v_to_slaves_0_wlast;
// value method v_to_slaves_0_m_wuser
// action method v_to_slaves_0_m_wready
input v_to_slaves_0_wready;
// action method v_to_slaves_0_m_bvalid
input v_to_slaves_0_bvalid;
input [15 : 0] v_to_slaves_0_bid;
input [1 : 0] v_to_slaves_0_bresp;
// value method v_to_slaves_0_m_bready
output v_to_slaves_0_bready;
// value method v_to_slaves_0_m_arvalid
output v_to_slaves_0_arvalid;
// value method v_to_slaves_0_m_arid
output [15 : 0] v_to_slaves_0_arid;
// value method v_to_slaves_0_m_araddr
output [63 : 0] v_to_slaves_0_araddr;
// value method v_to_slaves_0_m_arlen
output [7 : 0] v_to_slaves_0_arlen;
// value method v_to_slaves_0_m_arsize
output [2 : 0] v_to_slaves_0_arsize;
// value method v_to_slaves_0_m_arburst
output [1 : 0] v_to_slaves_0_arburst;
// value method v_to_slaves_0_m_arlock
output v_to_slaves_0_arlock;
// value method v_to_slaves_0_m_arcache
output [3 : 0] v_to_slaves_0_arcache;
// value method v_to_slaves_0_m_arprot
output [2 : 0] v_to_slaves_0_arprot;
// value method v_to_slaves_0_m_arqos
output [3 : 0] v_to_slaves_0_arqos;
// value method v_to_slaves_0_m_arregion
output [3 : 0] v_to_slaves_0_arregion;
// value method v_to_slaves_0_m_aruser
// action method v_to_slaves_0_m_arready
input v_to_slaves_0_arready;
// action method v_to_slaves_0_m_rvalid
input v_to_slaves_0_rvalid;
input [15 : 0] v_to_slaves_0_rid;
input [63 : 0] v_to_slaves_0_rdata;
input [1 : 0] v_to_slaves_0_rresp;
input v_to_slaves_0_rlast;
// value method v_to_slaves_0_m_rready
output v_to_slaves_0_rready;
// value method v_to_slaves_1_m_awvalid
output v_to_slaves_1_awvalid;
// value method v_to_slaves_1_m_awid
output [15 : 0] v_to_slaves_1_awid;
// value method v_to_slaves_1_m_awaddr
output [63 : 0] v_to_slaves_1_awaddr;
// value method v_to_slaves_1_m_awlen
output [7 : 0] v_to_slaves_1_awlen;
// value method v_to_slaves_1_m_awsize
output [2 : 0] v_to_slaves_1_awsize;
// value method v_to_slaves_1_m_awburst
output [1 : 0] v_to_slaves_1_awburst;
// value method v_to_slaves_1_m_awlock
output v_to_slaves_1_awlock;
// value method v_to_slaves_1_m_awcache
output [3 : 0] v_to_slaves_1_awcache;
// value method v_to_slaves_1_m_awprot
output [2 : 0] v_to_slaves_1_awprot;
// value method v_to_slaves_1_m_awqos
output [3 : 0] v_to_slaves_1_awqos;
// value method v_to_slaves_1_m_awregion
output [3 : 0] v_to_slaves_1_awregion;
// value method v_to_slaves_1_m_awuser
// action method v_to_slaves_1_m_awready
input v_to_slaves_1_awready;
// value method v_to_slaves_1_m_wvalid
output v_to_slaves_1_wvalid;
// value method v_to_slaves_1_m_wdata
output [63 : 0] v_to_slaves_1_wdata;
// value method v_to_slaves_1_m_wstrb
output [7 : 0] v_to_slaves_1_wstrb;
// value method v_to_slaves_1_m_wlast
output v_to_slaves_1_wlast;
// value method v_to_slaves_1_m_wuser
// action method v_to_slaves_1_m_wready
input v_to_slaves_1_wready;
// action method v_to_slaves_1_m_bvalid
input v_to_slaves_1_bvalid;
input [15 : 0] v_to_slaves_1_bid;
input [1 : 0] v_to_slaves_1_bresp;
// value method v_to_slaves_1_m_bready
output v_to_slaves_1_bready;
// value method v_to_slaves_1_m_arvalid
output v_to_slaves_1_arvalid;
// value method v_to_slaves_1_m_arid
output [15 : 0] v_to_slaves_1_arid;
// value method v_to_slaves_1_m_araddr
output [63 : 0] v_to_slaves_1_araddr;
// value method v_to_slaves_1_m_arlen
output [7 : 0] v_to_slaves_1_arlen;
// value method v_to_slaves_1_m_arsize
output [2 : 0] v_to_slaves_1_arsize;
// value method v_to_slaves_1_m_arburst
output [1 : 0] v_to_slaves_1_arburst;
// value method v_to_slaves_1_m_arlock
output v_to_slaves_1_arlock;
// value method v_to_slaves_1_m_arcache
output [3 : 0] v_to_slaves_1_arcache;
// value method v_to_slaves_1_m_arprot
output [2 : 0] v_to_slaves_1_arprot;
// value method v_to_slaves_1_m_arqos
output [3 : 0] v_to_slaves_1_arqos;
// value method v_to_slaves_1_m_arregion
output [3 : 0] v_to_slaves_1_arregion;
// value method v_to_slaves_1_m_aruser
// action method v_to_slaves_1_m_arready
input v_to_slaves_1_arready;
// action method v_to_slaves_1_m_rvalid
input v_to_slaves_1_rvalid;
input [15 : 0] v_to_slaves_1_rid;
input [63 : 0] v_to_slaves_1_rdata;
input [1 : 0] v_to_slaves_1_rresp;
input v_to_slaves_1_rlast;
// value method v_to_slaves_1_m_rready
output v_to_slaves_1_rready;
// value method v_to_slaves_2_m_awvalid
output v_to_slaves_2_awvalid;
// value method v_to_slaves_2_m_awid
output [15 : 0] v_to_slaves_2_awid;
// value method v_to_slaves_2_m_awaddr
output [63 : 0] v_to_slaves_2_awaddr;
// value method v_to_slaves_2_m_awlen
output [7 : 0] v_to_slaves_2_awlen;
// value method v_to_slaves_2_m_awsize
output [2 : 0] v_to_slaves_2_awsize;
// value method v_to_slaves_2_m_awburst
output [1 : 0] v_to_slaves_2_awburst;
// value method v_to_slaves_2_m_awlock
output v_to_slaves_2_awlock;
// value method v_to_slaves_2_m_awcache
output [3 : 0] v_to_slaves_2_awcache;
// value method v_to_slaves_2_m_awprot
output [2 : 0] v_to_slaves_2_awprot;
// value method v_to_slaves_2_m_awqos
output [3 : 0] v_to_slaves_2_awqos;
// value method v_to_slaves_2_m_awregion
output [3 : 0] v_to_slaves_2_awregion;
// value method v_to_slaves_2_m_awuser
// action method v_to_slaves_2_m_awready
input v_to_slaves_2_awready;
// value method v_to_slaves_2_m_wvalid
output v_to_slaves_2_wvalid;
// value method v_to_slaves_2_m_wdata
output [63 : 0] v_to_slaves_2_wdata;
// value method v_to_slaves_2_m_wstrb
output [7 : 0] v_to_slaves_2_wstrb;
// value method v_to_slaves_2_m_wlast
output v_to_slaves_2_wlast;
// value method v_to_slaves_2_m_wuser
// action method v_to_slaves_2_m_wready
input v_to_slaves_2_wready;
// action method v_to_slaves_2_m_bvalid
input v_to_slaves_2_bvalid;
input [15 : 0] v_to_slaves_2_bid;
input [1 : 0] v_to_slaves_2_bresp;
// value method v_to_slaves_2_m_bready
output v_to_slaves_2_bready;
// value method v_to_slaves_2_m_arvalid
output v_to_slaves_2_arvalid;
// value method v_to_slaves_2_m_arid
output [15 : 0] v_to_slaves_2_arid;
// value method v_to_slaves_2_m_araddr
output [63 : 0] v_to_slaves_2_araddr;
// value method v_to_slaves_2_m_arlen
output [7 : 0] v_to_slaves_2_arlen;
// value method v_to_slaves_2_m_arsize
output [2 : 0] v_to_slaves_2_arsize;
// value method v_to_slaves_2_m_arburst
output [1 : 0] v_to_slaves_2_arburst;
// value method v_to_slaves_2_m_arlock
output v_to_slaves_2_arlock;
// value method v_to_slaves_2_m_arcache
output [3 : 0] v_to_slaves_2_arcache;
// value method v_to_slaves_2_m_arprot
output [2 : 0] v_to_slaves_2_arprot;
// value method v_to_slaves_2_m_arqos
output [3 : 0] v_to_slaves_2_arqos;
// value method v_to_slaves_2_m_arregion
output [3 : 0] v_to_slaves_2_arregion;
// value method v_to_slaves_2_m_aruser
// action method v_to_slaves_2_m_arready
input v_to_slaves_2_arready;
// action method v_to_slaves_2_m_rvalid
input v_to_slaves_2_rvalid;
input [15 : 0] v_to_slaves_2_rid;
input [63 : 0] v_to_slaves_2_rdata;
input [1 : 0] v_to_slaves_2_rresp;
input v_to_slaves_2_rlast;
// value method v_to_slaves_2_m_rready
output v_to_slaves_2_rready;
// signals for module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [15 : 0] v_from_masters_0_bid,
v_from_masters_0_rid,
v_to_slaves_0_arid,
v_to_slaves_0_awid,
v_to_slaves_1_arid,
v_to_slaves_1_awid,
v_to_slaves_2_arid,
v_to_slaves_2_awid;
wire [7 : 0] v_to_slaves_0_arlen,
v_to_slaves_0_awlen,
v_to_slaves_0_wstrb,
v_to_slaves_1_arlen,
v_to_slaves_1_awlen,
v_to_slaves_1_wstrb,
v_to_slaves_2_arlen,
v_to_slaves_2_awlen,
v_to_slaves_2_wstrb;
wire [3 : 0] v_to_slaves_0_arcache,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_awcache,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_1_arcache,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_awcache,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_2_arcache,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_awcache,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion;
wire [2 : 0] v_to_slaves_0_arprot,
v_to_slaves_0_arsize,
v_to_slaves_0_awprot,
v_to_slaves_0_awsize,
v_to_slaves_1_arprot,
v_to_slaves_1_arsize,
v_to_slaves_1_awprot,
v_to_slaves_1_awsize,
v_to_slaves_2_arprot,
v_to_slaves_2_arsize,
v_to_slaves_2_awprot,
v_to_slaves_2_awsize;
wire [1 : 0] v_from_masters_0_bresp,
v_from_masters_0_rresp,
v_to_slaves_0_arburst,
v_to_slaves_0_awburst,
v_to_slaves_1_arburst,
v_to_slaves_1_awburst,
v_to_slaves_2_arburst,
v_to_slaves_2_awburst;
wire RDY_reset,
RDY_set_verbosity,
v_from_masters_0_arready,
v_from_masters_0_awready,
v_from_masters_0_bvalid,
v_from_masters_0_rlast,
v_from_masters_0_rvalid,
v_from_masters_0_wready,
v_to_slaves_0_arlock,
v_to_slaves_0_arvalid,
v_to_slaves_0_awlock,
v_to_slaves_0_awvalid,
v_to_slaves_0_bready,
v_to_slaves_0_rready,
v_to_slaves_0_wlast,
v_to_slaves_0_wvalid,
v_to_slaves_1_arlock,
v_to_slaves_1_arvalid,
v_to_slaves_1_awlock,
v_to_slaves_1_awvalid,
v_to_slaves_1_bready,
v_to_slaves_1_rready,
v_to_slaves_1_wlast,
v_to_slaves_1_wvalid,
v_to_slaves_2_arlock,
v_to_slaves_2_arvalid,
v_to_slaves_2_awlock,
v_to_slaves_2_awvalid,
v_to_slaves_2_bready,
v_to_slaves_2_rready,
v_to_slaves_2_wlast,
v_to_slaves_2_wvalid;
// register fabric_cfg_verbosity
reg [3 : 0] fabric_cfg_verbosity;
wire [3 : 0] fabric_cfg_verbosity$D_IN;
wire fabric_cfg_verbosity$EN;
// register fabric_rg_reset
reg fabric_rg_reset;
wire fabric_rg_reset$D_IN, fabric_rg_reset$EN;
// register fabric_v_rg_r_beat_count_0
reg [7 : 0] fabric_v_rg_r_beat_count_0;
wire [7 : 0] fabric_v_rg_r_beat_count_0$D_IN;
wire fabric_v_rg_r_beat_count_0$EN;
// register fabric_v_rg_r_beat_count_1
reg [7 : 0] fabric_v_rg_r_beat_count_1;
wire [7 : 0] fabric_v_rg_r_beat_count_1$D_IN;
wire fabric_v_rg_r_beat_count_1$EN;
// register fabric_v_rg_r_beat_count_2
reg [7 : 0] fabric_v_rg_r_beat_count_2;
wire [7 : 0] fabric_v_rg_r_beat_count_2$D_IN;
wire fabric_v_rg_r_beat_count_2$EN;
// register fabric_v_rg_r_err_beat_count_0
reg [7 : 0] fabric_v_rg_r_err_beat_count_0;
wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN;
wire fabric_v_rg_r_err_beat_count_0$EN;
// register fabric_v_rg_wd_beat_count_0
reg [7 : 0] fabric_v_rg_wd_beat_count_0;
wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN;
wire fabric_v_rg_wd_beat_count_0$EN;
// ports of submodule fabric_v_f_rd_err_info_0
wire [23 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT;
wire fabric_v_f_rd_err_info_0$CLR,
fabric_v_f_rd_err_info_0$DEQ,
fabric_v_f_rd_err_info_0$EMPTY_N,
fabric_v_f_rd_err_info_0$ENQ;
// ports of submodule fabric_v_f_rd_mis_0
wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT;
wire fabric_v_f_rd_mis_0$CLR,
fabric_v_f_rd_mis_0$DEQ,
fabric_v_f_rd_mis_0$EMPTY_N,
fabric_v_f_rd_mis_0$ENQ,
fabric_v_f_rd_mis_0$FULL_N;
// ports of submodule fabric_v_f_rd_mis_1
wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT;
wire fabric_v_f_rd_mis_1$CLR,
fabric_v_f_rd_mis_1$DEQ,
fabric_v_f_rd_mis_1$EMPTY_N,
fabric_v_f_rd_mis_1$ENQ,
fabric_v_f_rd_mis_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_2
wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT;
wire fabric_v_f_rd_mis_2$CLR,
fabric_v_f_rd_mis_2$DEQ,
fabric_v_f_rd_mis_2$EMPTY_N,
fabric_v_f_rd_mis_2$ENQ,
fabric_v_f_rd_mis_2$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_0
reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT;
wire fabric_v_f_rd_sjs_0$CLR,
fabric_v_f_rd_sjs_0$DEQ,
fabric_v_f_rd_sjs_0$EMPTY_N,
fabric_v_f_rd_sjs_0$ENQ,
fabric_v_f_rd_sjs_0$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_0
reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT;
wire fabric_v_f_wd_tasks_0$CLR,
fabric_v_f_wd_tasks_0$DEQ,
fabric_v_f_wd_tasks_0$EMPTY_N,
fabric_v_f_wd_tasks_0$ENQ,
fabric_v_f_wd_tasks_0$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_0
wire [15 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT;
wire fabric_v_f_wr_err_info_0$CLR,
fabric_v_f_wr_err_info_0$DEQ,
fabric_v_f_wr_err_info_0$EMPTY_N,
fabric_v_f_wr_err_info_0$ENQ;
// ports of submodule fabric_v_f_wr_mis_0
wire fabric_v_f_wr_mis_0$CLR,
fabric_v_f_wr_mis_0$DEQ,
fabric_v_f_wr_mis_0$D_IN,
fabric_v_f_wr_mis_0$D_OUT,
fabric_v_f_wr_mis_0$EMPTY_N,
fabric_v_f_wr_mis_0$ENQ,
fabric_v_f_wr_mis_0$FULL_N;
// ports of submodule fabric_v_f_wr_mis_1
wire fabric_v_f_wr_mis_1$CLR,
fabric_v_f_wr_mis_1$DEQ,
fabric_v_f_wr_mis_1$D_IN,
fabric_v_f_wr_mis_1$D_OUT,
fabric_v_f_wr_mis_1$EMPTY_N,
fabric_v_f_wr_mis_1$ENQ,
fabric_v_f_wr_mis_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_2
wire fabric_v_f_wr_mis_2$CLR,
fabric_v_f_wr_mis_2$DEQ,
fabric_v_f_wr_mis_2$D_IN,
fabric_v_f_wr_mis_2$D_OUT,
fabric_v_f_wr_mis_2$EMPTY_N,
fabric_v_f_wr_mis_2$ENQ,
fabric_v_f_wr_mis_2$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_0
reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT;
wire fabric_v_f_wr_sjs_0$CLR,
fabric_v_f_wr_sjs_0$DEQ,
fabric_v_f_wr_sjs_0$EMPTY_N,
fabric_v_f_wr_sjs_0$ENQ,
fabric_v_f_wr_sjs_0$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_addr
wire [108 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN,
fabric_xactors_from_masters_0_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_addr$CLR,
fabric_xactors_from_masters_0_f_rd_addr$DEQ,
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_addr$ENQ,
fabric_xactors_from_masters_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_data
reg [82 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN;
wire [82 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_data$CLR,
fabric_xactors_from_masters_0_f_rd_data$DEQ,
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_data$ENQ,
fabric_xactors_from_masters_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_addr
wire [108 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN,
fabric_xactors_from_masters_0_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_addr$CLR,
fabric_xactors_from_masters_0_f_wr_addr$DEQ,
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_addr$ENQ,
fabric_xactors_from_masters_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN,
fabric_xactors_from_masters_0_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_data$CLR,
fabric_xactors_from_masters_0_f_wr_data$DEQ,
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_data$ENQ,
fabric_xactors_from_masters_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_resp
reg [17 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN;
wire [17 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_resp$CLR,
fabric_xactors_from_masters_0_f_wr_resp$DEQ,
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_resp$ENQ,
fabric_xactors_from_masters_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN,
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_addr$CLR,
fabric_xactors_to_slaves_0_f_rd_addr$DEQ,
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_addr$ENQ,
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_data$CLR,
fabric_xactors_to_slaves_0_f_rd_data$DEQ,
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_data$ENQ,
fabric_xactors_to_slaves_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN,
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_addr$CLR,
fabric_xactors_to_slaves_0_f_wr_addr$DEQ,
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_addr$ENQ,
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN,
fabric_xactors_to_slaves_0_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_data$CLR,
fabric_xactors_to_slaves_0_f_wr_data$DEQ,
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_data$ENQ,
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN,
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_resp$CLR,
fabric_xactors_to_slaves_0_f_wr_resp$DEQ,
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_resp$ENQ,
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN,
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_addr$CLR,
fabric_xactors_to_slaves_1_f_rd_addr$DEQ,
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_addr$ENQ,
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_data$CLR,
fabric_xactors_to_slaves_1_f_rd_data$DEQ,
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_data$ENQ,
fabric_xactors_to_slaves_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN,
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_addr$CLR,
fabric_xactors_to_slaves_1_f_wr_addr$DEQ,
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_addr$ENQ,
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN,
fabric_xactors_to_slaves_1_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_data$CLR,
fabric_xactors_to_slaves_1_f_wr_data$DEQ,
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_data$ENQ,
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN,
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_resp$CLR,
fabric_xactors_to_slaves_1_f_wr_resp$DEQ,
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_resp$ENQ,
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN,
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_addr$CLR,
fabric_xactors_to_slaves_2_f_rd_addr$DEQ,
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_addr$ENQ,
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_data$CLR,
fabric_xactors_to_slaves_2_f_rd_data$DEQ,
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_data$ENQ,
fabric_xactors_to_slaves_2_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN,
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_addr$CLR,
fabric_xactors_to_slaves_2_f_wr_addr$DEQ,
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_addr$ENQ,
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN,
fabric_xactors_to_slaves_2_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_data$CLR,
fabric_xactors_to_slaves_2_f_wr_data$DEQ,
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_data$ENQ,
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN,
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_resp$CLR,
fabric_xactors_to_slaves_2_f_wr_resp$DEQ,
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_resp$ENQ,
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_reset,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
CAN_FIRE_reset,
CAN_FIRE_set_verbosity,
CAN_FIRE_v_from_masters_0_m_arvalid,
CAN_FIRE_v_from_masters_0_m_awvalid,
CAN_FIRE_v_from_masters_0_m_bready,
CAN_FIRE_v_from_masters_0_m_rready,
CAN_FIRE_v_from_masters_0_m_wvalid,
CAN_FIRE_v_to_slaves_0_m_arready,
CAN_FIRE_v_to_slaves_0_m_awready,
CAN_FIRE_v_to_slaves_0_m_bvalid,
CAN_FIRE_v_to_slaves_0_m_rvalid,
CAN_FIRE_v_to_slaves_0_m_wready,
CAN_FIRE_v_to_slaves_1_m_arready,
CAN_FIRE_v_to_slaves_1_m_awready,
CAN_FIRE_v_to_slaves_1_m_bvalid,
CAN_FIRE_v_to_slaves_1_m_rvalid,
CAN_FIRE_v_to_slaves_1_m_wready,
CAN_FIRE_v_to_slaves_2_m_arready,
CAN_FIRE_v_to_slaves_2_m_awready,
CAN_FIRE_v_to_slaves_2_m_bvalid,
CAN_FIRE_v_to_slaves_2_m_rvalid,
CAN_FIRE_v_to_slaves_2_m_wready,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_reset,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
WILL_FIRE_reset,
WILL_FIRE_set_verbosity,
WILL_FIRE_v_from_masters_0_m_arvalid,
WILL_FIRE_v_from_masters_0_m_awvalid,
WILL_FIRE_v_from_masters_0_m_bready,
WILL_FIRE_v_from_masters_0_m_rready,
WILL_FIRE_v_from_masters_0_m_wvalid,
WILL_FIRE_v_to_slaves_0_m_arready,
WILL_FIRE_v_to_slaves_0_m_awready,
WILL_FIRE_v_to_slaves_0_m_bvalid,
WILL_FIRE_v_to_slaves_0_m_rvalid,
WILL_FIRE_v_to_slaves_0_m_wready,
WILL_FIRE_v_to_slaves_1_m_arready,
WILL_FIRE_v_to_slaves_1_m_awready,
WILL_FIRE_v_to_slaves_1_m_bvalid,
WILL_FIRE_v_to_slaves_1_m_rvalid,
WILL_FIRE_v_to_slaves_1_m_wready,
WILL_FIRE_v_to_slaves_2_m_arready,
WILL_FIRE_v_to_slaves_2_m_awready,
WILL_FIRE_v_to_slaves_2_m_bvalid,
WILL_FIRE_v_to_slaves_2_m_rvalid,
WILL_FIRE_v_to_slaves_2_m_wready;
// inputs to muxes for submodule ports
wire [82 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
wire [17 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h6565;
reg [31 : 0] v__h6916;
reg [31 : 0] v__h7267;
reg [31 : 0] v__h7953;
reg [31 : 0] v__h8200;
reg [31 : 0] v__h8557;
reg [31 : 0] v__h8827;
reg [31 : 0] v__h9097;
reg [31 : 0] v__h9331;
reg [31 : 0] v__h9735;
reg [31 : 0] v__h10073;
reg [31 : 0] v__h10411;
reg [31 : 0] v__h11108;
reg [31 : 0] v__h11389;
reg [31 : 0] v__h11757;
reg [31 : 0] v__h12028;
reg [31 : 0] v__h12396;
reg [31 : 0] v__h12667;
reg [31 : 0] v__h13120;
reg [31 : 0] v__h4397;
reg [31 : 0] v__h6910;
reg [31 : 0] v__h4391;
reg [31 : 0] v__h6559;
reg [31 : 0] v__h7261;
reg [31 : 0] v__h7947;
reg [31 : 0] v__h8194;
reg [31 : 0] v__h8551;
reg [31 : 0] v__h8821;
reg [31 : 0] v__h9091;
reg [31 : 0] v__h9325;
reg [31 : 0] v__h9729;
reg [31 : 0] v__h10067;
reg [31 : 0] v__h10405;
reg [31 : 0] v__h11102;
reg [31 : 0] v__h11383;
reg [31 : 0] v__h11751;
reg [31 : 0] v__h12022;
reg [31 : 0] v__h12390;
reg [31 : 0] v__h12661;
reg [31 : 0] v__h13114;
// synopsys translate_on
// remaining internal signals
reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1;
wire [7 : 0] x__h11272, x__h11921, x__h12560, x__h13057, x__h8102;
wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_ETC___d245,
IF_fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_ETC___d284,
IF_fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_ETC___d323,
x1_avValue_rresp__h11250,
x1_avValue_rresp__h11899,
x1_avValue_rresp__h12538;
wire fabric_v_f_wd_tasks_0_i_notEmpty__9_AND_fabric_ETC___d78,
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218,
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258,
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297,
fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338,
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d166,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d167,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d170,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d171,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23;
// action method reset
assign RDY_reset = !fabric_rg_reset ;
assign CAN_FIRE_reset = !fabric_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method v_from_masters_0_m_awvalid
assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
// value method v_from_masters_0_m_awready
assign v_from_masters_0_awready =
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
// action method v_from_masters_0_m_wvalid
assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
// value method v_from_masters_0_m_wready
assign v_from_masters_0_wready =
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
// value method v_from_masters_0_m_bvalid
assign v_from_masters_0_bvalid =
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
// value method v_from_masters_0_m_bid
assign v_from_masters_0_bid =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[17:2] ;
// value method v_from_masters_0_m_bresp
assign v_from_masters_0_bresp =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_0_m_bready
assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ;
// action method v_from_masters_0_m_arvalid
assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
// value method v_from_masters_0_m_arready
assign v_from_masters_0_arready =
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
// value method v_from_masters_0_m_rvalid
assign v_from_masters_0_rvalid =
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
// value method v_from_masters_0_m_rid
assign v_from_masters_0_rid =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[82:67] ;
// value method v_from_masters_0_m_rdata
assign v_from_masters_0_rdata =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_0_m_rresp
assign v_from_masters_0_rresp =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_0_m_rlast
assign v_from_masters_0_rlast =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ;
// action method v_from_masters_0_m_rready
assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ;
// value method v_to_slaves_0_m_awvalid
assign v_to_slaves_0_awvalid =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_0_m_awid
assign v_to_slaves_0_awid =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_0_m_awaddr
assign v_to_slaves_0_awaddr =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_awlen
assign v_to_slaves_0_awlen =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_awsize
assign v_to_slaves_0_awsize =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_awburst
assign v_to_slaves_0_awburst =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_awlock
assign v_to_slaves_0_awlock =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_awcache
assign v_to_slaves_0_awcache =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_awprot
assign v_to_slaves_0_awprot =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_awqos
assign v_to_slaves_0_awqos =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_awregion
assign v_to_slaves_0_awregion =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_awready
assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
// value method v_to_slaves_0_m_wvalid
assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ;
// value method v_to_slaves_0_m_wdata
assign v_to_slaves_0_wdata =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_0_m_wstrb
assign v_to_slaves_0_wstrb =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_0_m_wlast
assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_0_m_wready
assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
// action method v_to_slaves_0_m_bvalid
assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
// value method v_to_slaves_0_m_bready
assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
// value method v_to_slaves_0_m_arvalid
assign v_to_slaves_0_arvalid =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_0_m_arid
assign v_to_slaves_0_arid =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_0_m_araddr
assign v_to_slaves_0_araddr =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_arlen
assign v_to_slaves_0_arlen =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_arsize
assign v_to_slaves_0_arsize =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_arburst
assign v_to_slaves_0_arburst =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_arlock
assign v_to_slaves_0_arlock =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_arcache
assign v_to_slaves_0_arcache =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_arprot
assign v_to_slaves_0_arprot =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_arqos
assign v_to_slaves_0_arqos =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_arregion
assign v_to_slaves_0_arregion =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_arready
assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
// action method v_to_slaves_0_m_rvalid
assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
// value method v_to_slaves_0_m_rready
assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
// value method v_to_slaves_1_m_awvalid
assign v_to_slaves_1_awvalid =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_1_m_awid
assign v_to_slaves_1_awid =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_1_m_awaddr
assign v_to_slaves_1_awaddr =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_awlen
assign v_to_slaves_1_awlen =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_awsize
assign v_to_slaves_1_awsize =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_awburst
assign v_to_slaves_1_awburst =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_awlock
assign v_to_slaves_1_awlock =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_awcache
assign v_to_slaves_1_awcache =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_awprot
assign v_to_slaves_1_awprot =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_awqos
assign v_to_slaves_1_awqos =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_awregion
assign v_to_slaves_1_awregion =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_awready
assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
// value method v_to_slaves_1_m_wvalid
assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ;
// value method v_to_slaves_1_m_wdata
assign v_to_slaves_1_wdata =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_1_m_wstrb
assign v_to_slaves_1_wstrb =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_1_m_wlast
assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_1_m_wready
assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
// action method v_to_slaves_1_m_bvalid
assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
// value method v_to_slaves_1_m_bready
assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
// value method v_to_slaves_1_m_arvalid
assign v_to_slaves_1_arvalid =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_1_m_arid
assign v_to_slaves_1_arid =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_1_m_araddr
assign v_to_slaves_1_araddr =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_arlen
assign v_to_slaves_1_arlen =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_arsize
assign v_to_slaves_1_arsize =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_arburst
assign v_to_slaves_1_arburst =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_arlock
assign v_to_slaves_1_arlock =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_arcache
assign v_to_slaves_1_arcache =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_arprot
assign v_to_slaves_1_arprot =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_arqos
assign v_to_slaves_1_arqos =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_arregion
assign v_to_slaves_1_arregion =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_arready
assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
// action method v_to_slaves_1_m_rvalid
assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
// value method v_to_slaves_1_m_rready
assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
// value method v_to_slaves_2_m_awvalid
assign v_to_slaves_2_awvalid =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_2_m_awid
assign v_to_slaves_2_awid =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_2_m_awaddr
assign v_to_slaves_2_awaddr =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_awlen
assign v_to_slaves_2_awlen =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_awsize
assign v_to_slaves_2_awsize =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_awburst
assign v_to_slaves_2_awburst =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_awlock
assign v_to_slaves_2_awlock =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_awcache
assign v_to_slaves_2_awcache =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_awprot
assign v_to_slaves_2_awprot =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_awqos
assign v_to_slaves_2_awqos =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_awregion
assign v_to_slaves_2_awregion =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_awready
assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
// value method v_to_slaves_2_m_wvalid
assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ;
// value method v_to_slaves_2_m_wdata
assign v_to_slaves_2_wdata =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_2_m_wstrb
assign v_to_slaves_2_wstrb =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_2_m_wlast
assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_2_m_wready
assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
// action method v_to_slaves_2_m_bvalid
assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
// value method v_to_slaves_2_m_bready
assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
// value method v_to_slaves_2_m_arvalid
assign v_to_slaves_2_arvalid =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_2_m_arid
assign v_to_slaves_2_arid =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_2_m_araddr
assign v_to_slaves_2_araddr =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_arlen
assign v_to_slaves_2_arlen =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_arsize
assign v_to_slaves_2_arsize =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_arburst
assign v_to_slaves_2_arburst =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_arlock
assign v_to_slaves_2_arlock =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_arcache
assign v_to_slaves_2_arcache =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_arprot
assign v_to_slaves_2_arprot =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_arqos
assign v_to_slaves_2_arqos =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_arregion
assign v_to_slaves_2_arregion =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_arready
assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
// action method v_to_slaves_2_m_rvalid
assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
// value method v_to_slaves_2_m_rready
assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
// submodule fabric_v_f_rd_err_info_0
SizedFIFO #(.p1width(32'd24),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_0$D_IN),
.ENQ(fabric_v_f_rd_err_info_0$ENQ),
.DEQ(fabric_v_f_rd_err_info_0$DEQ),
.CLR(fabric_v_f_rd_err_info_0$CLR),
.D_OUT(fabric_v_f_rd_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_0
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_0$D_IN),
.ENQ(fabric_v_f_rd_mis_0$ENQ),
.DEQ(fabric_v_f_rd_mis_0$DEQ),
.CLR(fabric_v_f_rd_mis_0$CLR),
.D_OUT(fabric_v_f_rd_mis_0$D_OUT),
.FULL_N(fabric_v_f_rd_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_1
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_1$D_IN),
.ENQ(fabric_v_f_rd_mis_1$ENQ),
.DEQ(fabric_v_f_rd_mis_1$DEQ),
.CLR(fabric_v_f_rd_mis_1$CLR),
.D_OUT(fabric_v_f_rd_mis_1$D_OUT),
.FULL_N(fabric_v_f_rd_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_2
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_2$D_IN),
.ENQ(fabric_v_f_rd_mis_2$ENQ),
.DEQ(fabric_v_f_rd_mis_2$DEQ),
.CLR(fabric_v_f_rd_mis_2$CLR),
.D_OUT(fabric_v_f_rd_mis_2$D_OUT),
.FULL_N(fabric_v_f_rd_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N));
// submodule fabric_v_f_rd_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_0$D_IN),
.ENQ(fabric_v_f_rd_sjs_0$ENQ),
.DEQ(fabric_v_f_rd_sjs_0$DEQ),
.CLR(fabric_v_f_rd_sjs_0$CLR),
.D_OUT(fabric_v_f_rd_sjs_0$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N));
// submodule fabric_v_f_wd_tasks_0
FIFO2 #(.width(32'd10), .guarded(1'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_0$D_IN),
.ENQ(fabric_v_f_wd_tasks_0$ENQ),
.DEQ(fabric_v_f_wd_tasks_0$DEQ),
.CLR(fabric_v_f_wd_tasks_0$CLR),
.D_OUT(fabric_v_f_wd_tasks_0$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_0$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N));
// submodule fabric_v_f_wr_err_info_0
SizedFIFO #(.p1width(32'd16),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_0$D_IN),
.ENQ(fabric_v_f_wr_err_info_0$ENQ),
.DEQ(fabric_v_f_wr_err_info_0$DEQ),
.CLR(fabric_v_f_wr_err_info_0$CLR),
.D_OUT(fabric_v_f_wr_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_0
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_0$D_IN),
.ENQ(fabric_v_f_wr_mis_0$ENQ),
.DEQ(fabric_v_f_wr_mis_0$DEQ),
.CLR(fabric_v_f_wr_mis_0$CLR),
.D_OUT(fabric_v_f_wr_mis_0$D_OUT),
.FULL_N(fabric_v_f_wr_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_1
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_1$D_IN),
.ENQ(fabric_v_f_wr_mis_1$ENQ),
.DEQ(fabric_v_f_wr_mis_1$DEQ),
.CLR(fabric_v_f_wr_mis_1$CLR),
.D_OUT(fabric_v_f_wr_mis_1$D_OUT),
.FULL_N(fabric_v_f_wr_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_2
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_2$D_IN),
.ENQ(fabric_v_f_wr_mis_2$ENQ),
.DEQ(fabric_v_f_wr_mis_2$DEQ),
.CLR(fabric_v_f_wr_mis_2$CLR),
.D_OUT(fabric_v_f_wr_mis_2$D_OUT),
.FULL_N(fabric_v_f_wr_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N));
// submodule fabric_v_f_wr_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(1'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_0$D_IN),
.ENQ(fabric_v_f_wr_sjs_0$ENQ),
.DEQ(fabric_v_f_wr_sjs_0$DEQ),
.CLR(fabric_v_f_wr_sjs_0$CLR),
.D_OUT(fabric_v_f_wr_sjs_0$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(1'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N));
// rule RL_fabric_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
(fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) &&
(fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23) ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
(fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19) &&
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_0_i_notEmpty__9_AND_fabric_ETC___d78 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
!fabric_v_f_wr_mis_0$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
// rule RL_fabric_rl_wr_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
!fabric_v_f_wr_mis_1$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
!fabric_v_f_wr_mis_2$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
// rule RL_fabric_rl_wr_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_0$EMPTY_N &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
// rule RL_fabric_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
(fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d166 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d167) &&
(fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d170 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d171) ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d166 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d167 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
(fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d166 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d167) &&
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d170 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d171 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
(fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_0$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
// rule RL_fabric_rl_rd_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
(fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_1$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
(fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_2$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
// rule RL_fabric_rl_rd_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master =
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_0$EMPTY_N &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// rule RL_fabric_rl_reset
assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 =
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 ?
8'd0 :
x__h11272 ;
assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 =
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 ?
8'd0 :
x__h11921 ;
assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 =
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 ?
8'd0 :
x__h12560 ;
assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 ?
8'd0 :
x__h8102 ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 =
{ fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_ETC___d245,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 =
{ fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_ETC___d284,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 =
{ fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_ETC___d323,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_0$D_OUT[15:0],
66'd3,
fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338 } ;
assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ;
// register fabric_cfg_verbosity
assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign fabric_cfg_verbosity$EN = EN_set_verbosity ;
// register fabric_rg_reset
assign fabric_rg_reset$D_IN = !fabric_rg_reset ;
assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ;
// register fabric_v_rg_r_beat_count_0
assign fabric_v_rg_r_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_r_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_1
assign fabric_v_rg_r_beat_count_1$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 ;
assign fabric_v_rg_r_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_2
assign fabric_v_rg_r_beat_count_2$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 ;
assign fabric_v_rg_r_beat_count_2$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
fabric_rg_reset ;
// register fabric_v_rg_r_err_beat_count_0
assign fabric_v_rg_r_err_beat_count_0$D_IN =
fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338 ?
8'd0 :
x__h13057 ;
assign fabric_v_rg_r_err_beat_count_0$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// register fabric_v_rg_wd_beat_count_0
assign fabric_v_rg_wd_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ||
fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_0
assign fabric_v_f_rd_err_info_0$D_IN = 24'h0 ;
assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_rd_err_info_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338 ;
assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_0
assign fabric_v_f_rd_mis_0$D_IN =
{ 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ;
assign fabric_v_f_rd_mis_0$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_v_f_rd_mis_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 ;
assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_1
assign fabric_v_f_rd_mis_1$D_IN = fabric_v_f_rd_mis_0$D_IN ;
assign fabric_v_f_rd_mis_1$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
assign fabric_v_f_rd_mis_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 ;
assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_2
assign fabric_v_f_rd_mis_2$D_IN = fabric_v_f_rd_mis_0$D_IN ;
assign fabric_v_f_rd_mis_2$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_v_f_rd_mis_2$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 ;
assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_0
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1:
fabric_v_f_rd_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2:
fabric_v_f_rd_sjs_0$D_IN = 2'd2;
default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_v_f_rd_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338 ;
assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
default: fabric_v_f_wd_tasks_0$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wd_tasks_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 ;
assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_0
assign fabric_v_f_wr_err_info_0$D_IN = 16'h0 ;
assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_wr_err_info_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_0
assign fabric_v_f_wr_mis_0$D_IN = 1'd0 ;
assign fabric_v_f_wr_mis_0$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_v_f_wr_mis_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_1
assign fabric_v_f_wr_mis_1$D_IN = 1'd0 ;
assign fabric_v_f_wr_mis_1$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
assign fabric_v_f_wr_mis_1$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_2
assign fabric_v_f_wr_mis_2$D_IN = 1'd0 ;
assign fabric_v_f_wr_mis_2$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_mis_2$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wr_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wr_sjs_0$D_IN = 2'd2;
default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_addr
assign fabric_xactors_from_masters_0_f_rd_addr$D_IN =
{ v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion } ;
assign fabric_xactors_from_masters_0_f_rd_addr$ENQ =
v_from_masters_0_arvalid &&
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_rd_data$D_IN =
83'h2AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_rd_data$DEQ =
v_from_masters_0_rready &&
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_addr
assign fabric_xactors_from_masters_0_f_wr_addr$D_IN =
{ v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion } ;
assign fabric_xactors_from_masters_0_f_wr_addr$ENQ =
v_from_masters_0_awvalid &&
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_data
assign fabric_xactors_from_masters_0_f_wr_data$D_IN =
{ v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast } ;
assign fabric_xactors_from_masters_0_f_wr_data$ENQ =
v_from_masters_0_wvalid &&
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_data$DEQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_wr_resp$D_IN =
18'b101010101010101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_wr_resp$DEQ =
v_from_masters_0_bready &&
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_addr
assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N &&
v_to_slaves_0_arready ;
assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_data
assign fabric_xactors_to_slaves_0_f_rd_data$D_IN =
{ v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast } ;
assign fabric_xactors_to_slaves_0_f_rd_data$ENQ =
v_to_slaves_0_rvalid &&
fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_0_f_rd_data$DEQ =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_addr
assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N &&
v_to_slaves_0_awready ;
assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_data
assign fabric_xactors_to_slaves_0_f_wr_data$D_IN =
fabric_xactors_from_masters_0_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ;
assign fabric_xactors_to_slaves_0_f_wr_data$DEQ =
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N &&
v_to_slaves_0_wready ;
assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_resp
assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN =
{ v_to_slaves_0_bid, v_to_slaves_0_bresp } ;
assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ =
v_to_slaves_0_bvalid &&
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_addr
assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N &&
v_to_slaves_1_arready ;
assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_data
assign fabric_xactors_to_slaves_1_f_rd_data$D_IN =
{ v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast } ;
assign fabric_xactors_to_slaves_1_f_rd_data$ENQ =
v_to_slaves_1_rvalid &&
fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_1_f_rd_data$DEQ =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_addr
assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N &&
v_to_slaves_1_awready ;
assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_data
assign fabric_xactors_to_slaves_1_f_wr_data$D_IN =
fabric_xactors_from_masters_0_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ;
assign fabric_xactors_to_slaves_1_f_wr_data$DEQ =
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N &&
v_to_slaves_1_wready ;
assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_resp
assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN =
{ v_to_slaves_1_bid, v_to_slaves_1_bresp } ;
assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ =
v_to_slaves_1_bvalid &&
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_addr
assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N &&
v_to_slaves_2_arready ;
assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_data
assign fabric_xactors_to_slaves_2_f_rd_data$D_IN =
{ v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast } ;
assign fabric_xactors_to_slaves_2_f_rd_data$ENQ =
v_to_slaves_2_rvalid &&
fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_2_f_rd_data$DEQ =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_addr
assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N &&
v_to_slaves_2_awready ;
assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_data
assign fabric_xactors_to_slaves_2_f_wr_data$D_IN =
fabric_xactors_from_masters_0_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ;
assign fabric_xactors_to_slaves_2_f_wr_data$DEQ =
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N &&
v_to_slaves_2_wready ;
assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_resp
assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN =
{ v_to_slaves_2_bid, v_to_slaves_2_bresp } ;
assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ =
v_to_slaves_2_bvalid &&
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ;
// remaining internal signals
assign IF_fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_ETC___d245 =
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 ?
x1_avValue_rresp__h11250 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_ETC___d284 =
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 ?
x1_avValue_rresp__h11899 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_ETC___d323 =
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 ?
x1_avValue_rresp__h12538 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign fabric_v_f_wd_tasks_0_i_notEmpty__9_AND_fabric_ETC___d78 =
fabric_v_f_wd_tasks_0$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ;
assign fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 =
fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 =
fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 =
fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ;
assign fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338 =
fabric_v_rg_r_err_beat_count_0 ==
fabric_v_f_rd_err_info_0$D_OUT[23:16] ;
assign fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 =
fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d166 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'h0000000002000000 ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d167 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'd33603584 ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d170 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'h000000000C000000 ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d171 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
64'd205520896 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d18 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'h0000000002000000 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d19 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'd33603584 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'h000000000C000000 ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d23 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
64'd205520896 ;
assign x1_avValue_rresp__h11250 =
(fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h11899 =
(fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h12538 =
(fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign x__h11272 = fabric_v_rg_r_beat_count_0 + 8'd1 ;
assign x__h11921 = fabric_v_rg_r_beat_count_1 + 8'd1 ;
assign x__h12560 = fabric_v_rg_r_beat_count_2 + 8'd1 ;
assign x__h13057 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ;
assign x__h8102 = fabric_v_rg_wd_beat_count_0 + 8'd1 ;
always@(fabric_v_f_wd_tasks_0$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_0$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (fabric_cfg_verbosity$EN)
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
fabric_cfg_verbosity$D_IN;
if (fabric_rg_reset$EN)
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN;
if (fabric_v_rg_r_beat_count_0$EN)
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_0$D_IN;
if (fabric_v_rg_r_beat_count_1$EN)
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_1$D_IN;
if (fabric_v_rg_r_beat_count_2$EN)
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_2$D_IN;
if (fabric_v_rg_r_err_beat_count_0$EN)
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_0$D_IN;
if (fabric_v_rg_wd_beat_count_0$EN)
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_0$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fabric_cfg_verbosity = 4'hA;
fabric_rg_reset = 1'h0;
fabric_v_rg_r_beat_count_0 = 8'hAA;
fabric_v_rg_r_beat_count_1 = 8'hAA;
fabric_v_rg_r_beat_count_2 = 8'hAA;
fabric_v_rg_r_err_beat_count_0 = 8'hAA;
fabric_v_rg_wd_beat_count_0 = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h6565 = $stime;
#0;
end
v__h6559 = v__h6565 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h6559,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h6916 = $stime;
#0;
end
v__h6910 = v__h6916 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h6910,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h7267 = $stime;
#0;
end
v__h7261 = v__h7267 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h7261,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
begin
v__h7953 = $stime;
#0;
end
v__h7947 = v__h7953 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h7947,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8],
fabric_v_rg_wd_beat_count_0,
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
begin
v__h8200 = $stime;
#0;
end
v__h8194 = v__h8200 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h8194,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_6_EQ_fabric_v_f_wd_ETC___d94 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8557 = $stime;
#0;
end
v__h8551 = v__h8557 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h8551,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8827 = $stime;
#0;
end
v__h8821 = v__h8827 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h8821,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9097 = $stime;
#0;
end
v__h9091 = v__h9097 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h9091,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9331 = $stime;
#0;
end
v__h9325 = v__h9331 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h9325,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_0$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9735 = $stime;
#0;
end
v__h9729 = v__h9735 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h9729,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10073 = $stime;
#0;
end
v__h10067 = v__h10073 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h10067,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10411 = $stime;
#0;
end
v__h10405 = v__h10411 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h10405,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h11108 = $stime;
#0;
end
v__h11102 = v__h11108 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h11102,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_rd_ETC___d218 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11389 = $stime;
#0;
end
v__h11383 = v__h11389 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h11383,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_16_EQ_fabric_v_f_ETC___d245);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h11757 = $stime;
#0;
end
v__h11751 = v__h11757 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h11751,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_rd_ETC___d258 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12028 = $stime;
#0;
end
v__h12022 = v__h12028 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h12022,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_56_EQ_fabric_v_f_ETC___d284);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h12396 = $stime;
#0;
end
v__h12390 = v__h12396 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h12390,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_rd_ETC___d297 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12667 = $stime;
#0;
end
v__h12661 = v__h12667 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h12661,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_95_EQ_fabric_v_f_ETC___d323);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13120 = $stime;
#0;
end
v__h13114 = v__h13120 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h13114,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[15:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_0_36_EQ_fabric_v__ETC___d338)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
begin
v__h4397 = $stime;
#0;
end
v__h4391 = v__h4397 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_reset", v__h4391);
end
// synopsys translate_on
endmodule // mkFabric_1x3
|
///////////////////////////////////////////////////////////////////////////////
// (c) Copyright 2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
///////////////////////////////////////////////////////////////////////////////
//
// RX_STREAM
//
//
// Description: The RX_LL module receives data from the Aurora Channel,
// converts it to a simple streaming format. This module expects
// all data to be carried in a single, infinite frame, and it
// expects the data data in lanes to be all valid or all invalid
//
// This module supports 4 2-byte lane designs.
//
//
`timescale 1 ns / 1 ps
module aur1_RX_STREAM
(
// LocalLink PDU Interface
RX_D,
RX_SRC_RDY_N,
// Global Logic Interface
START_RX,
// Aurora Lane Interface
RX_PAD,
RX_PE_DATA,
RX_PE_DATA_V,
RX_SCP,
RX_ECP,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
output [0:63] RX_D;
output RX_SRC_RDY_N;
// Global Logic Interface
input START_RX;
// Aurora Lane Interface
input [0:3] RX_PAD;
input [0:63] RX_PE_DATA;
input [0:3] RX_PE_DATA_V;
input [0:3] RX_SCP;
input [0:3] RX_ECP;
// System Interface
input USER_CLK;
//************************Register Declarations********************
reg infinite_frame_started_r;
//***********************Main Body of Code*************************
//Don't start presenting data until the infinite frame starts
always @(posedge USER_CLK)
if(!START_RX)
infinite_frame_started_r <= `DLY 1'b0;
else if(RX_SCP > 4'd0)
infinite_frame_started_r <= `DLY 1'b1;
assign RX_D = RX_PE_DATA;
assign RX_SRC_RDY_N = !(RX_PE_DATA_V[0] && infinite_frame_started_r);
endmodule
|
// Note: The for is translated to a begin/while is it tests the while.
module main;
reg val = 1'b0;
reg cond = 1'b1;
reg [1:0] cval;
integer idx;
integer dly = 1;
// Simple assign (error).
always val = 1'b1;
// A zero delay assign (error).
always #0 val = 1'b1;
// A variable delay assign (warning).
always #dly val = 1'b1;
// Non-blocking assign (error).
always val <= #1 1'b1;
// No delay if (error).
always if (cond) val = 1'b1;
// No delay if/else (error).
always if (cond) val = 1'b1; else val = 1'b0;
// Delay if/no delay else (warning).
always if (cond) #1 val = 1'b1; else val = 1'b0;
// Delay if/no delay else (warning).
always #0 if (cond) #1 val = 1'b1; else val = 1'b0;
// No delay if/delay else (warning).
always if (cond) val = 1'b1; else #1 val = 1'b0;
// No delay forever (error).
always forever val = 1'b1;
// Zero delay forever (error).
always forever #0 val = 1'b1;
// Possible delay forever (warning).
always forever if (cond) #1 val = 1'b1; else val = 1'b0;
// No delay for (error).
always for(idx=0; idx<1; idx=idx+1) val = 1'b1;
// Zero delay for (error).
always for(idx=0; idx<1; idx=idx+1) #0 val = 1'b1;
// Possible delay for (warning).
always for(idx=0; idx<1; idx=idx+1) if (cond) #1 val = 1'b1; else val = 1'b0;
// Never run for (error).
always for(idx=0; 0; idx=idx+1) #1 val = 1'b1;
// Always run for (error).
always for(idx=0; 1; idx=idx+1) #0 val = 1'b1;
// An empty bock (error).
always begin end
// Block with no delay (error).
always begin val = 1'b1; end
// Block with zero delay (error).
always begin #0 val = 1'b1; end
// Block with zero delay (warning).
always begin #0; if (cond) #1 val = 1'b1; else val = 1'b0; end
// Never run repeat (error).
always repeat(0) #1 val = 1'b1;
// Always run repeat (error).
always repeat(1) #0 val = 1'b1;
// Possibly run repeat (warning).
always repeat(cond) #1 val = 1'b1;
// No wait (error).
always wait(1) val = 1'b1;
// May wait (warning).
always wait(cond) val = 1'b1;
// Not all paths covered (warning).
always case(cval)
2'b00: #1 val = 1'b1;
2'b10: #1 val = 1'b1;
endcase
// Not all paths have delay (warning).
always case(cval)
2'b00: #1 val = 1'b1;
2'b10: #1 val = 1'b1;
default: #0 val = 1'b1;
endcase
// Check task calls (error, error, warning).
always no_delay;
always zero_delay;
always possible_delay;
task no_delay;
val = 1'b1;
endtask
task zero_delay;
#0 val = 1'b1;
endtask
task possible_delay;
#dly val = 1'b1;
endtask
// Check a function call (error).
always val = func(1'b1);
function func;
input in;
func = in;
endfunction
endmodule
|
`include "./Definition.v"
// RGB2XYZ
`define RGB2XYZ1 106 // 0.412453 * `ScaleNumber = 105.587968
`define RGB2XYZ2 92 // 0.357580 * `ScaleNumber = 91.54048
`define RGB2XYZ3 46 // 0.180423 * `ScaleNumber = 46.188288
`define RGB2XYZ4 54 // 0.212671 * `ScaleNumber = 54.443776
`define RGB2XYZ5 183 // 0.715160 * `ScaleNumber = 183.08096
`define RGB2XYZ6 18 // 0.072169 * `ScaleNumber = 18.475264
`define RGB2XYZ7 5 // 0.019334 * `ScaleNumber = 4.949504
`define RGB2XYZ8 31 // 0.119193 * `ScaleNumber = 30.513408
`define RGB2XYZ9 243 // 0.950227 * `ScaleNumber = 243.258112
//16 * 6.3496042078727978990068225569719 * `ScaleNumber = 26007.978835446980194331945193353
`define pow_16_256_1_3 26008
`define RGB2LabLimit 2 // 0.008856 * ScaleNumber = 2.267136
module ForwardSpace
(
input[ `size_int - 1 : 0 ]R,
input[ `size_int - 1 : 0 ]G,
input[ `size_int - 1 : 0 ]B,
output wire[ `size_int - 1 : 0 ]CIEL,
output wire signed[ `size_int - 1 : 0 ]CIEa,
output wire signed[ `size_int - 1 : 0 ]CIEb
);
reg[ `size_int - 1 : 0 ]X;
reg[ `size_int - 1 : 0 ]Y;
reg[ `size_int - 1 : 0 ]Z;
reg[ `size_int - 1 : 0 ]fX;
reg[ `size_int - 1 : 0 ]fY;
reg[ `size_int - 1 : 0 ]fZ;
always@( R or G or B )
begin
// 256 * 0.950456 * 256
X = ( R * `RGB2XYZ1 + G * `RGB2XYZ2 + B * `RGB2XYZ3 ) >> ( `ScaleBit + `ScaleBit );
X = ( X * 269 ) >> `ScaleBit; // 256 / 0.950456 = 269
Y = ( R * `RGB2XYZ4 + G * `RGB2XYZ5 + B * `RGB2XYZ6 ) >> ( `ScaleBit + `ScaleBit );
// 256 * 1.088754 * 256
Z = ( R * `RGB2XYZ7 + G * `RGB2XYZ8 + B * `RGB2XYZ9 ) >> ( `ScaleBit + `ScaleBit );
Z = ( Z * 235 ) >> `ScaleBit; // 256 / 1.088754 = 235
// avoid extreme case of Y
if( Y < `RGB2LabLimit )
Y = `RGB2LabLimit;
// avoid extreme case of X
if( X < `RGB2LabLimit )
X = `RGB2LabLimit;
// avoid extreme case of Z
if( Z < `RGB2LabLimit )
Z = `RGB2LabLimit;
fX = LUTPow033( X );
fY = LUTPow033( Y );
fZ = LUTPow033( Z );
end
assign CIEL = 116 * fX - `pow_16_256_1_3;
assign CIEa = 500 * ( fX - fY );
assign CIEb = 200 * ( fY - fZ );
function[ `size_int - 1 : 0 ]LUTPow033;
input[ `size_int - 1 : 0 ]Index;
begin
case( Index )
0 : LUTPow033 = 0;
1 : LUTPow033 = 256;
2 : LUTPow033 = 322;
3 : LUTPow033 = 369;
4 : LUTPow033 = 406;
5 : LUTPow033 = 437;
6 : LUTPow033 = 465;
7 : LUTPow033 = 489;
8 : LUTPow033 = 511;
9 : LUTPow033 = 532;
10 : LUTPow033 = 551;
11 : LUTPow033 = 569;
12 : LUTPow033 = 586;
13 : LUTPow033 = 601;
14 : LUTPow033 = 616;
15 : LUTPow033 = 631;
16 : LUTPow033 = 645;
17 : LUTPow033 = 658;
18 : LUTPow033 = 670;
19 : LUTPow033 = 683;
20 : LUTPow033 = 694;
21 : LUTPow033 = 706;
22 : LUTPow033 = 717;
23 : LUTPow033 = 728;
24 : LUTPow033 = 738;
25 : LUTPow033 = 748;
26 : LUTPow033 = 758;
27 : LUTPow033 = 767;
28 : LUTPow033 = 777;
29 : LUTPow033 = 786;
30 : LUTPow033 = 795;
31 : LUTPow033 = 804;
32 : LUTPow033 = 812;
33 : LUTPow033 = 821;
34 : LUTPow033 = 829;
35 : LUTPow033 = 837;
36 : LUTPow033 = 845;
37 : LUTPow033 = 853;
38 : LUTPow033 = 860;
39 : LUTPow033 = 868;
40 : LUTPow033 = 875;
41 : LUTPow033 = 882;
42 : LUTPow033 = 889;
43 : LUTPow033 = 896;
44 : LUTPow033 = 903;
45 : LUTPow033 = 910;
46 : LUTPow033 = 917;
47 : LUTPow033 = 923;
48 : LUTPow033 = 930;
49 : LUTPow033 = 936;
50 : LUTPow033 = 943;
51 : LUTPow033 = 949;
52 : LUTPow033 = 955;
53 : LUTPow033 = 961;
54 : LUTPow033 = 967;
55 : LUTPow033 = 973;
56 : LUTPow033 = 979;
57 : LUTPow033 = 985;
58 : LUTPow033 = 990;
59 : LUTPow033 = 996;
60 : LUTPow033 = 1002;
61 : LUTPow033 = 1007;
62 : LUTPow033 = 1013;
63 : LUTPow033 = 1018;
64 : LUTPow033 = 1023;
65 : LUTPow033 = 1029;
66 : LUTPow033 = 1034;
67 : LUTPow033 = 1039;
68 : LUTPow033 = 1044;
69 : LUTPow033 = 1050;
70 : LUTPow033 = 1055;
71 : LUTPow033 = 1060;
72 : LUTPow033 = 1065;
73 : LUTPow033 = 1069;
74 : LUTPow033 = 1074;
75 : LUTPow033 = 1079;
76 : LUTPow033 = 1084;
77 : LUTPow033 = 1089;
78 : LUTPow033 = 1093;
79 : LUTPow033 = 1098;
80 : LUTPow033 = 1103;
81 : LUTPow033 = 1107;
82 : LUTPow033 = 1112;
83 : LUTPow033 = 1116;
84 : LUTPow033 = 1121;
85 : LUTPow033 = 1125;
86 : LUTPow033 = 1129;
87 : LUTPow033 = 1134;
88 : LUTPow033 = 1138;
89 : LUTPow033 = 1142;
90 : LUTPow033 = 1147;
91 : LUTPow033 = 1151;
92 : LUTPow033 = 1155;
93 : LUTPow033 = 1159;
94 : LUTPow033 = 1163;
95 : LUTPow033 = 1168;
96 : LUTPow033 = 1172;
97 : LUTPow033 = 1176;
98 : LUTPow033 = 1180;
99 : LUTPow033 = 1184;
100 : LUTPow033 = 1188;
101 : LUTPow033 = 1192;
102 : LUTPow033 = 1196;
103 : LUTPow033 = 1200;
104 : LUTPow033 = 1203;
105 : LUTPow033 = 1207;
106 : LUTPow033 = 1211;
107 : LUTPow033 = 1215;
108 : LUTPow033 = 1219;
109 : LUTPow033 = 1222;
110 : LUTPow033 = 1226;
111 : LUTPow033 = 1230;
112 : LUTPow033 = 1233;
113 : LUTPow033 = 1237;
114 : LUTPow033 = 1241;
115 : LUTPow033 = 1244;
116 : LUTPow033 = 1248;
117 : LUTPow033 = 1252;
118 : LUTPow033 = 1255;
119 : LUTPow033 = 1259;
120 : LUTPow033 = 1262;
121 : LUTPow033 = 1266;
122 : LUTPow033 = 1269;
123 : LUTPow033 = 1273;
124 : LUTPow033 = 1276;
125 : LUTPow033 = 1279;
126 : LUTPow033 = 1283;
127 : LUTPow033 = 1286;
128 : LUTPow033 = 1290;
129 : LUTPow033 = 1293;
130 : LUTPow033 = 1296;
131 : LUTPow033 = 1300;
132 : LUTPow033 = 1303;
133 : LUTPow033 = 1306;
134 : LUTPow033 = 1310;
135 : LUTPow033 = 1313;
136 : LUTPow033 = 1316;
137 : LUTPow033 = 1319;
138 : LUTPow033 = 1322;
139 : LUTPow033 = 1326;
140 : LUTPow033 = 1329;
141 : LUTPow033 = 1332;
142 : LUTPow033 = 1335;
143 : LUTPow033 = 1338;
144 : LUTPow033 = 1341;
145 : LUTPow033 = 1344;
146 : LUTPow033 = 1348;
147 : LUTPow033 = 1351;
148 : LUTPow033 = 1354;
149 : LUTPow033 = 1357;
150 : LUTPow033 = 1360;
151 : LUTPow033 = 1363;
152 : LUTPow033 = 1366;
153 : LUTPow033 = 1369;
154 : LUTPow033 = 1372;
155 : LUTPow033 = 1375;
156 : LUTPow033 = 1378;
157 : LUTPow033 = 1381;
158 : LUTPow033 = 1383;
159 : LUTPow033 = 1386;
160 : LUTPow033 = 1389;
161 : LUTPow033 = 1392;
162 : LUTPow033 = 1395;
163 : LUTPow033 = 1398;
164 : LUTPow033 = 1401;
165 : LUTPow033 = 1404;
166 : LUTPow033 = 1406;
167 : LUTPow033 = 1409;
168 : LUTPow033 = 1412;
169 : LUTPow033 = 1415;
170 : LUTPow033 = 1418;
171 : LUTPow033 = 1420;
172 : LUTPow033 = 1423;
173 : LUTPow033 = 1426;
174 : LUTPow033 = 1429;
175 : LUTPow033 = 1431;
176 : LUTPow033 = 1434;
177 : LUTPow033 = 1437;
178 : LUTPow033 = 1440;
179 : LUTPow033 = 1442;
180 : LUTPow033 = 1445;
181 : LUTPow033 = 1448;
182 : LUTPow033 = 1450;
183 : LUTPow033 = 1453;
184 : LUTPow033 = 1456;
185 : LUTPow033 = 1458;
186 : LUTPow033 = 1461;
187 : LUTPow033 = 1463;
188 : LUTPow033 = 1466;
189 : LUTPow033 = 1469;
190 : LUTPow033 = 1471;
191 : LUTPow033 = 1474;
192 : LUTPow033 = 1476;
193 : LUTPow033 = 1479;
194 : LUTPow033 = 1481;
195 : LUTPow033 = 1484;
196 : LUTPow033 = 1487;
197 : LUTPow033 = 1489;
198 : LUTPow033 = 1492;
199 : LUTPow033 = 1494;
200 : LUTPow033 = 1497;
201 : LUTPow033 = 1499;
202 : LUTPow033 = 1502;
203 : LUTPow033 = 1504;
204 : LUTPow033 = 1507;
205 : LUTPow033 = 1509;
206 : LUTPow033 = 1511;
207 : LUTPow033 = 1514;
208 : LUTPow033 = 1516;
209 : LUTPow033 = 1519;
210 : LUTPow033 = 1521;
211 : LUTPow033 = 1524;
212 : LUTPow033 = 1526;
213 : LUTPow033 = 1528;
214 : LUTPow033 = 1531;
215 : LUTPow033 = 1533;
216 : LUTPow033 = 1535;
217 : LUTPow033 = 1538;
218 : LUTPow033 = 1540;
219 : LUTPow033 = 1543;
220 : LUTPow033 = 1545;
221 : LUTPow033 = 1547;
222 : LUTPow033 = 1550;
223 : LUTPow033 = 1552;
224 : LUTPow033 = 1554;
225 : LUTPow033 = 1557;
226 : LUTPow033 = 1559;
227 : LUTPow033 = 1561;
228 : LUTPow033 = 1563;
229 : LUTPow033 = 1566;
230 : LUTPow033 = 1568;
231 : LUTPow033 = 1570;
232 : LUTPow033 = 1573;
233 : LUTPow033 = 1575;
234 : LUTPow033 = 1577;
235 : LUTPow033 = 1579;
236 : LUTPow033 = 1582;
237 : LUTPow033 = 1584;
238 : LUTPow033 = 1586;
239 : LUTPow033 = 1588;
240 : LUTPow033 = 1590;
241 : LUTPow033 = 1593;
242 : LUTPow033 = 1595;
243 : LUTPow033 = 1597;
244 : LUTPow033 = 1599;
245 : LUTPow033 = 1601;
246 : LUTPow033 = 1604;
247 : LUTPow033 = 1606;
248 : LUTPow033 = 1608;
249 : LUTPow033 = 1610;
250 : LUTPow033 = 1612;
251 : LUTPow033 = 1614;
252 : LUTPow033 = 1616;
253 : LUTPow033 = 1619;
254 : LUTPow033 = 1621;
255 : LUTPow033 = 1623;
256 : LUTPow033 = 1625;
endcase
end
endfunction
endmodule
module ForwardSpace_testbench;
reg[ `size_int - 1 : 0 ]R;
reg[ `size_int - 1 : 0 ]G;
reg[ `size_int - 1 : 0 ]B;
wire[ `size_int - 1 : 0 ]CIEL;
wire signed[ `size_int - 1 : 0 ]CIEa;
wire signed[ `size_int - 1 : 0 ]CIEb;
ForwardSpace ForwardSpace_test( R, G, B, CIEL, CIEa, CIEb );
initial
begin
$monitor( "R = %d, G = %d, B = %d, CIEL = %d, CIEa = %d, CIEb = %d",
R, G, B, CIEL, CIEa, CIEb );
#100
begin
R = 50 << `ScaleBit; // 12800
G = 70 << `ScaleBit; // 17920
B = 40 << `ScaleBit; // 10240
end
#100
begin
R = 29 << `ScaleBit; // 7424
G = 85 << `ScaleBit; // 21760
B = 89 << `ScaleBit; // 22784
end
#100 $stop;
#100 $finish;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: read_posted_fifo.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module instantiated by read_data_path module and sits between
// mcb_flow_control module and read_data_gen module to buffer up the
// commands that has sent to memory controller.
//Reference:
//Revision History: 3/14/2012 Adding support for "nCK_PER_CLK == 2" abd MEM_BURST_LEN == 2 "
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_read_posted_fifo #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter nCK_PER_CLK = 4,
parameter MEM_BURST_LEN = 4,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6
)
(
input clk_i,
input rst_i,
output reg cmd_rdy_o,
input memc_cmd_full_i,
input cmd_valid_i,
input data_valid_i,
input cmd_start_i,
input [ADDR_WIDTH-1:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
output gen_valid_o,
output [ADDR_WIDTH-1:0] gen_addr_o,
output [BL_WIDTH-1:0] gen_bl_o,
output rd_mdata_en
);
//reg empty_r;
reg rd_en_r;
wire full;
wire empty;
wire wr_en;
reg mcb_rd_fifo_port_almost_full;
reg [6:0] buf_avail_r;
reg [6:0] rd_data_received_counts;
reg [6:0] rd_data_counts_asked;
reg dfifo_has_enough_room;
reg [1:0] wait_cnt;
reg wait_done;
assign rd_mdata_en = rd_en_r;
generate
if (FAMILY == "SPARTAN6")
begin: gen_sp6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room ;//& wait_done;
end
// if ((FAMILY == "VIRTEX7") || (FAMILY == "7SERIES") || (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ||
// (FAMILY == "VIRTEX6") )
else
begin: gen_v6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & wait_done & dfifo_has_enough_room;
end
endgenerate
always @ (posedge clk_i)
begin
if (rst_i)
wait_cnt <= #TCQ 'b0;
else if (cmd_rdy_o && cmd_valid_i)
wait_cnt <= #TCQ 2'b10;
else if (wait_cnt > 0)
wait_cnt <= #TCQ wait_cnt - 1'b1;
end
always @(posedge clk_i)
begin
if (rst_i)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i)
wait_done <= #TCQ 1'b0;
else if (wait_cnt == 0)
wait_done <= #TCQ 1'b1;
else
wait_done <= #TCQ 1'b0;
end
reg dfifo_has_enough_room_d1;
always @ (posedge clk_i)
begin
dfifo_has_enough_room <= #TCQ (buf_avail_r >= 32 ) ? 1'b1: 1'b0;
dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ;
end
// remove the dfifo_has_enough_room term. Just need to push pressure to the front to stop
// sending more read commands but still accepting it if there is one coming.
assign wr_en = cmd_valid_i & !full & wait_done;
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_counts_asked <= #TCQ 'b0;
end
else if (cmd_en_i && cmd_sent[0] == 1 && ~memc_cmd_full_i) begin
if (FAMILY == "SPARTAN6")
rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ;
else
// if (nCK_PER_CLK == 2 )
// rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ;
// else
// rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ;
if (nCK_PER_CLK == 4 || (nCK_PER_CLK == 2 && (MEM_BURST_LEN == 4 || MEM_BURST_LEN == 2 ) ))
rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ;
else if (nCK_PER_CLK == 2 && MEM_BURST_LEN == 8)
rd_data_counts_asked <= #TCQ rd_data_counts_asked + 2'b10 ;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_received_counts <= #TCQ 'b0;
end
else if (data_valid_i) begin
rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1;
end
end
// calculate how many buf still available
always @ (posedge clk_i)
if (rd_data_received_counts[6] == rd_data_counts_asked[6])
buf_avail_r <= #TCQ (rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] + 7'd64 );
else
buf_avail_r <= #TCQ ( rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] );
always @ (posedge clk_i) begin
rd_en_r <= #TCQ cmd_start_i;
end
assign gen_valid_o = !empty;
mig_7series_v1_9_afifo #
(
.TCQ (TCQ),
.DSIZE (BL_WIDTH+ADDR_WIDTH),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_fifo
(
.wr_clk (clk_i),
.rst (rst_i),
.wr_en (wr_en),
.wr_data ({bl_i,addr_i}),
.rd_en (rd_en_r),
.rd_clk (clk_i),
.rd_data ({gen_bl_o,gen_addr_o}),
.full (full),
.empty (empty),
.almost_full ()
);
endmodule
|
// file: clk_wiz_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____33.333______0.000______50.0______165.726_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_4_1_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module clk_wiz_0
(
// Clock out ports
output clk_out1,
// Clock in ports
input clk_in1
);
clk_wiz_0_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
|
// Double pumped single precision floating point add
// Latency = 9 kernel clocks
//
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_custom_add_dbl_pumped
#( parameter WIDTH = 32 )
(
input clock,
input clock2x,
input enable,
input resetn,
input [WIDTH-1:0] a1,
input [WIDTH-1:0] b1,
input [WIDTH-1:0] a2,
input [WIDTH-1:0] b2,
output reg [WIDTH-1:0] y1,
output reg [WIDTH-1:0] y2
);
reg [WIDTH-1:0] a1_reg;
reg [WIDTH-1:0] b1_reg;
reg [WIDTH-1:0] a2_reg;
reg [WIDTH-1:0] b2_reg;
// Prevent sharing of these registers across different instances
// (and even kernels!). The sharing may cause very long paths
// across the chip, which limits fmax of clock2x.
reg sel2x /* synthesis preserve */;
wire [WIDTH-1:0] fp_add_sub_inp_a;
wire [WIDTH-1:0] fp_add_sub_inp_b;
wire [WIDTH-1:0] fp_add_sub_res;
initial
begin
sel2x = 1'b0;
end
always@(posedge clock2x)
if (enable)
sel2x<=~sel2x;
//Register before double pumping
reg selector, selector_2x;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
a1_reg <= {WIDTH{1'b0}};
a2_reg <= {WIDTH{1'b0}};
b1_reg <= {WIDTH{1'b0}};
b2_reg <= {WIDTH{1'b0}};
selector <= 1'b0;
end
else if (enable)
begin
a1_reg <= a1;
a2_reg <= a2;
b1_reg <= b1;
b2_reg <= b2;
selector <= sel2x;
end
end
reg [WIDTH-1:0] a1_reg_2x;
reg [WIDTH-1:0] a2_reg_2x;
reg [WIDTH-1:0] b1_reg_2x;
reg [WIDTH-1:0] b2_reg_2x;
// Clock domain transfer
always@(posedge clock2x)
if (enable)
begin
a1_reg_2x <= a1_reg;
a2_reg_2x <= a2_reg;
b1_reg_2x <= b1_reg;
b2_reg_2x <= b2_reg;
selector_2x <= selector;
end
assign fp_add_sub_inp_a = (sel2x) ? a2_reg_2x : a1_reg_2x;
assign fp_add_sub_inp_b = (sel2x) ? b2_reg_2x : b1_reg_2x;
acl_fp_custom_add the_add(
.resetn(resetn),
.enable(enable),
.clock(clock2x),
.dataa(fp_add_sub_inp_a),
.datab(fp_add_sub_inp_b),
.result(fp_add_sub_res));
//For testing purposes
//always@(posedge clk2x)
//begin
// fp_sub_res1 <= fp_sub_inp_a + fp_sub_inp_b;
// fp_sub_res <= fp_sub_res1;
//end
reg [WIDTH-1:0] res1;
reg [WIDTH-1:0] res2;
reg [WIDTH-1:0] temp;
always@(posedge clock2x)
begin
if (enable)
begin
if (~sel2x == selector_2x)
begin
res1 <= (~selector_2x) ? temp : fp_add_sub_res;
res2 <= (~selector_2x) ? fp_add_sub_res : temp;
end
temp <= fp_add_sub_res;
end
end
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
y1 <= {WIDTH{1'b0}};
y2 <= {WIDTH{1'b0}};
end
else if (enable)
begin
y1 <= res1;
y2 <= res2;
end
end
endmodule
|
/////////////////////////////////////////////////////
// DCM SPI Controller
/////////////////////////////////////////////////////
`timescale 1ns / 1ps
module dcmspi (
input RST, //Synchronous Reset
input PROGCLK, //SPI clock
input PROGDONE, //DCM is ready to take next command
input DFSLCKD,
input [7:0] M, //DCM M value
input [7:0] D, //DCM D value
input GO, //Go programme the M and D value into DCM(1 cycle pulse)
output reg BUSY,
output reg PROGEN, //SlaveSelect,
output reg PROGDATA //CommandData
);
parameter TCQ = 1;
wire [9:0] mval = {M, 1'b1, 1'b1}; //M command: 11,M0-M7
wire [9:0] dval = {D, 1'b0, 1'b1}; //D command: 10,D0-D7
reg dfslckd_q;
reg dfslckd_rising;
always @ (posedge PROGCLK)
begin
dfslckd_q <=#TCQ DFSLCKD;
dfslckd_rising <=#TCQ !dfslckd_q & DFSLCKD;
end
always @ (posedge PROGCLK)
begin
if(RST || (PROGDONE & dfslckd_rising))
BUSY <=#TCQ 1'b0;
else if (GO)
BUSY <=#TCQ 1'b1;
end
reg [9:0] sndval;
reg sndm = 1'b0;
reg sndd = 1'b0;
wire ddone;
SRL16E VCNT (
.Q(ddone), // SRL data output
.A0(1'b1), // Select[0] input
.A1(1'b0), // Select[1] input
.A2(1'b0), // Select[2] input
.A3(1'b1), // Select[3] input
.CE(1'b1), //clock enable
.CLK(PROGCLK), // Clock input
.D(GO) // SRL data input
);
// The following defparam declaration
defparam VCNT.INIT = 16'h0;
always @ (posedge PROGCLK)
begin
if(RST || ddone)
sndd <=#TCQ 1'b0;
else if(GO)
sndd <=#TCQ 1'b1;
end
//V has been sent now it is M's turn
wire ldm;
SRL16E DMGAP (
.Q(ldm), // SRL data output
.A0(1'b0), // Select[0] input
.A1(1'b0), // Select[1] input
.A2(1'b1), // Select[2] input
.A3(1'b0), // Select[3] input
.CE(1'b1), //clock enable
.CLK(PROGCLK), // Clock input
.D(ddone) // SRL data input
);
// The following defparam declaration
defparam DMGAP.INIT = 16'h0;
wire mdone;
SRL16E MCNT (
.Q(mdone), // SRL data output
.A0(1'b1), // Select[0] input
.A1(1'b0), // Select[1] input
.A2(1'b0), // Select[2] input
.A3(1'b1), // Select[3] input
.CE(1'b1), //clock enable
.CLK(PROGCLK), // Clock input
.D(ldm) // SRL data input
);
// The following defparam declaration
defparam MCNT.INIT = 16'h0;
always @ (posedge PROGCLK)
begin
if(RST || mdone)
sndm <=#TCQ 1'b0;
else if(ldm)
sndm <=#TCQ 1'b1;
end
wire gocmd;
SRL16E GOGAP (
.Q(gocmd), // SRL data output
.A0(1'b0), // Select[0] input
.A1(1'b0), // Select[1] input
.A2(1'b1), // Select[2] input
.A3(1'b0), // Select[3] input
.CE(1'b1), //clock enable
.CLK(PROGCLK), // Clock input
.D(mdone) // SRL data input
);
// The following defparam declaration
defparam GOGAP.INIT = 16'h0;
always @ (posedge PROGCLK)
begin
if(RST)
sndval <=#TCQ 10'h0;
else if(GO) //send D first
sndval <=#TCQ dval;
else if(ldm)
sndval <=#TCQ mval;
else if(sndm || sndd)
sndval <=#TCQ sndval >> 1;
end
always @ (posedge PROGCLK)
begin
PROGEN <=#TCQ sndd | sndm | gocmd;
end
always @ (posedge PROGCLK)
begin
if(sndm || sndd)
PROGDATA <=#TCQ sndval[0];
else
PROGDATA <=#TCQ 1'b0;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
// verilator lint_off MULTIDRIVEN
wire [31:0] outb0c0;
wire [31:0] outb0c1;
wire [31:0] outb1c0;
wire [31:0] outb1c1;
reg [7:0] lclmem [7:0];
ma ma0 (.outb0c0(outb0c0), .outb0c1(outb0c1),
.outb1c0(outb1c0), .outb1c1(outb1c1)
);
global_mod #(32'hf00d) global_cell ();
global_mod #(32'hf22d) global_cell2 ();
input clk;
integer cyc=1;
always @ (posedge clk) begin
cyc <= cyc + 1;
`ifdef TEST_VERBOSE
$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
`endif
if (cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf22d) $stop;
if (outb0c0 != 32'h00) $stop;
if (outb0c1 != 32'h01) $stop;
if (outb1c0 != 32'h10) $stop;
if (outb1c1 != 32'h11) $stop;
end
if (cyc==3) begin
// Can we scope down and read and write vars?
ma0.mb0.mc0.out <= ma0.mb0.mc0.out + 32'h100;
ma0.mb0.mc1.out <= ma0.mb0.mc1.out + 32'h100;
ma0.mb1.mc0.out <= ma0.mb1.mc0.out + 32'h100;
ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100;
end
if (cyc==4) begin
// Can we do dotted's inside array sels?
ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12;
lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24;
if (outb0c0 != 32'h100) $stop;
if (outb0c1 != 32'h101) $stop;
if (outb1c0 != 32'h110) $stop;
if (outb1c1 != 32'h111) $stop;
end
if (cyc==5) begin
if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop;
if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop;
if (outb0c0 != 32'h1100) $stop;
if (outb0c1 != 32'h2101) $stop;
if (outb1c0 != 32'h2110) $stop;
if (outb1c1 != 32'h3111) $stop;
end
if (cyc==6) begin
if (outb0c0 != 32'h31100) $stop;
if (outb0c1 != 32'h02101) $stop;
if (outb1c0 != 32'h42110) $stop;
if (outb1c1 != 32'h03111) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
`ifdef USE_INLINE_MID
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator no_inline_module*/
`else
`ifdef USE_INLINE
`define INLINE_MODULE /*verilator inline_module*/
`define INLINE_MID_MODULE /*verilator inline_module*/
`else
`define INLINE_MODULE /*verilator public_module*/
`define INLINE_MID_MODULE /*verilator public_module*/
`endif
`endif
module global_mod;
`INLINE_MODULE
parameter INITVAL = 0;
integer globali;
initial globali = INITVAL;
endmodule
module ma (
output wire [31:0] outb0c0,
output wire [31:0] outb0c1,
output wire [31:0] outb1c0,
output wire [31:0] outb1c1
);
`INLINE_MODULE
reg [7:0] rmtmem [7:0];
mb #(0) mb0 (.outc0(outb0c0), .outc1(outb0c1));
mb #(1) mb1 (.outc0(outb1c0), .outc1(outb1c1));
endmodule
module mb (
output wire [31:0] outc0,
output wire [31:0] outc1
);
`INLINE_MID_MODULE
parameter P2 = 0;
mc #(P2,0) mc0 (.out(outc0));
mc #(P2,1) mc1 (.out(outc1));
global_mod #(32'hf33d) global_cell2 ();
wire reach_up_clk = t.clk;
always @(reach_up_clk) begin
if (P2==0) begin // Only for mb0
if (outc0 !== t.ma0.mb0.mc0.out) $stop; // Top module name and lower instances
if (outc0 !== ma0.mb0.mc0.out) $stop; // Upper module name and lower instances
if (outc0 !== ma .mb0.mc0.out) $stop; // Upper module name and lower instances
if (outc0 !== mb.mc0.out) $stop; // This module name and lower instances
if (outc0 !== mb0.mc0.out) $stop; // Upper instance name and lower instances
if (outc0 !== mc0.out) $stop; // Lower instances
if (outc1 !== t.ma0.mb0.mc1.out) $stop; // Top module name and lower instances
if (outc1 !== ma0.mb0.mc1.out) $stop; // Upper module name and lower instances
if (outc1 !== ma .mb0.mc1.out) $stop; // Upper module name and lower instances
if (outc1 !== mb.mc1.out) $stop; // This module name and lower instances
if (outc1 !== mb0.mc1.out) $stop; // Upper instance name and lower instances
if (outc1 !== mc1.out) $stop; // Lower instances
end
end
endmodule
module mc (output reg [31:0] out);
`INLINE_MODULE
parameter P2 = 0;
parameter P3 = 0;
initial begin
out = {24'h0,P2[3:0],P3[3:0]};
//$write("%m P2=%0x p3=%0x out=%x\n",P2, P3, out);
end
// Can we look from the top module name down?
wire [31:0] reach_up_cyc = t.cyc;
always @ (posedge t.clk) begin
//$write("[%0t] %m: Got reachup, cyc=%0d\n", $time, reach_up_cyc);
if (reach_up_cyc==2) begin
if (global_cell.globali != 32'hf00d) $stop;
if (global_cell2.globali != 32'hf33d) $stop;
end
if (reach_up_cyc==4) begin
out[15:12] <= {P2[3:0]+P3[3:0]+4'd1};
end
if (reach_up_cyc==5) begin
// Can we set another instance?
if (P3==1) begin // Without this, there are two possible correct answers...
mc0.out[19:16] <= {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2};
$display("%m Set %x->%x %x %x %x %x",mc0.out, {mc0.out[19:16]+P2[3:0]+P3[3:0]+4'd2}, mc0.out[19:16],P2[3:0],P3[3:0],4'd2);
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2030 by Stephen Henry.
// SPDX-License-Identifier: CC0-1.0
module t;
int fdin_bin, fdout_txt, fdout_bin;
`define STRINGIFY(x) `"x`"
`define checkh(gotv,expv) \
do if ((gotv) !== (expv)) begin\
$write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv));\
end while(0)
//
//
task automatic test1; begin
for (int i = 0; i < 256; i++) begin
byte actual, expected;
expected = i[7:0];
$fscanf(fdin_bin, "%u", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%u", actual);
end
for (int i = 0; i < 256; i++) begin
shortint actual, expected;
for (int j = 0; j < 2; j++)
expected[(8 * j)+:8] = i[7:0] + j[7:0];
$fscanf(fdin_bin, "%u", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%u", actual);
end
for (int i = 0; i < 256; i++) begin
int actual, expected;
for (int j = 0; j < 4; j++)
expected[(8 * j)+:8] = i[7:0] + j[7:0];
$fscanf(fdin_bin, "%u", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%u", actual);
end
for (int i = 0; i < 256; i++) begin
longint actual, expected;
for (int j = 0; j < 8; j++)
expected[(8 * j)+:8] = i[7:0] + j[7:0];
$fscanf(fdin_bin, "%u", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%u", actual);
end
end endtask
//
//
task automatic test2; begin
for (int i = 0; i < 256; i++) begin
byte actual, expected;
expected = i[7:0];
$fscanf(fdin_bin, "%z", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%z", actual);
end
for (int i = 0; i < 256; i++) begin
shortint actual, expected;
for (int j = 0; j < 2; j++)
expected[(8 * j)+:8] = i[7:0] + j[7:0];
$fscanf(fdin_bin, "%z", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%z", actual);
end
for (int i = 0; i < 256; i++) begin
int actual, expected;
for (int j = 0; j < 4; j++)
expected[(8 * j)+:8] = i[7:0] + j[7:0];
$fscanf(fdin_bin, "%z", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%z", actual);
end
for (int i = 0; i < 256; i++) begin
longint actual, expected;
for (int j = 0; j < 8; j++)
expected[(8 * j)+:8] = i[7:0] + j[7:0];
$fscanf(fdin_bin, "%z", actual);
`checkh(actual, expected);
$fdisplay(fdout_txt, "%h", actual);
$fwrite(fdout_bin, "%z", actual);
end
end endtask
initial begin : main_PROC
string filename;
filename = "t/t_sys_file_basic_uz.dat";
fdin_bin = $fopen(filename, "rb");
`ifdef IVERILOG
filename = $sformatf("%s/t_sys_file_basic_uz_test.log","obj_iv/t_sys_file_basic_uz");
`else
filename = $sformatf("%s/t_sys_file_basic_uz_test.log",`STRINGIFY(`TEST_OBJ_DIR));
`endif
fdout_txt = $fopen(filename, "w");
`ifdef IVERILOG
filename = $sformatf("%s/t_sys_file_basic_uz_test.bin","obj_iv/t_sys_file_basic_uz");
`else
filename = $sformatf("%s/t_sys_file_basic_uz_test.bin",`STRINGIFY(`TEST_OBJ_DIR));
`endif
$display(filename);
fdout_bin = $fopen(filename, "wb");
test1;
test2;
$fclose(fdin_bin);
$fclose(fdout_txt);
$write("*-* All Finished *-*\n");
$finish(0); // Test arguments to finish
end // block: main_PROC
`undef STRINGIFY
endmodule // t
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_1_V
`define SKY130_FD_SC_HS__SDFRTP_1_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrtp_1 (
RESET_B,
CLK ,
D ,
Q ,
SCD ,
SCE ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfrtp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrtp_1 (
RESET_B,
CLK ,
D ,
Q ,
SCD ,
SCE
);
input RESET_B;
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfrtp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_1_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 11:10:13 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, Sgf_operation_RECURSIVE_EVEN1_left_N23,
Sgf_operation_RECURSIVE_EVEN1_left_N22,
Sgf_operation_RECURSIVE_EVEN1_left_N21,
Sgf_operation_RECURSIVE_EVEN1_left_N20,
Sgf_operation_RECURSIVE_EVEN1_left_N19,
Sgf_operation_RECURSIVE_EVEN1_left_N18,
Sgf_operation_RECURSIVE_EVEN1_left_N17,
Sgf_operation_RECURSIVE_EVEN1_left_N16,
Sgf_operation_RECURSIVE_EVEN1_left_N15,
Sgf_operation_RECURSIVE_EVEN1_left_N14,
Sgf_operation_RECURSIVE_EVEN1_left_N13,
Sgf_operation_RECURSIVE_EVEN1_left_N12,
Sgf_operation_RECURSIVE_EVEN1_left_N11,
Sgf_operation_RECURSIVE_EVEN1_left_N10,
Sgf_operation_RECURSIVE_EVEN1_left_N9,
Sgf_operation_RECURSIVE_EVEN1_left_N8,
Sgf_operation_RECURSIVE_EVEN1_left_N7,
Sgf_operation_RECURSIVE_EVEN1_left_N6,
Sgf_operation_RECURSIVE_EVEN1_left_N5,
Sgf_operation_RECURSIVE_EVEN1_left_N4,
Sgf_operation_RECURSIVE_EVEN1_left_N3,
Sgf_operation_RECURSIVE_EVEN1_left_N2,
Sgf_operation_RECURSIVE_EVEN1_left_N1,
Sgf_operation_RECURSIVE_EVEN1_left_N0,
Sgf_operation_RECURSIVE_EVEN1_middle_N25,
Sgf_operation_RECURSIVE_EVEN1_middle_N24,
Sgf_operation_RECURSIVE_EVEN1_middle_N23,
Sgf_operation_RECURSIVE_EVEN1_middle_N22,
Sgf_operation_RECURSIVE_EVEN1_middle_N21,
Sgf_operation_RECURSIVE_EVEN1_middle_N20,
Sgf_operation_RECURSIVE_EVEN1_middle_N19,
Sgf_operation_RECURSIVE_EVEN1_middle_N18,
Sgf_operation_RECURSIVE_EVEN1_middle_N17,
Sgf_operation_RECURSIVE_EVEN1_middle_N16,
Sgf_operation_RECURSIVE_EVEN1_middle_N15,
Sgf_operation_RECURSIVE_EVEN1_middle_N14,
Sgf_operation_RECURSIVE_EVEN1_middle_N13,
Sgf_operation_RECURSIVE_EVEN1_middle_N12,
Sgf_operation_RECURSIVE_EVEN1_middle_N11,
Sgf_operation_RECURSIVE_EVEN1_middle_N10,
Sgf_operation_RECURSIVE_EVEN1_middle_N9,
Sgf_operation_RECURSIVE_EVEN1_middle_N8,
Sgf_operation_RECURSIVE_EVEN1_middle_N7,
Sgf_operation_RECURSIVE_EVEN1_middle_N6,
Sgf_operation_RECURSIVE_EVEN1_middle_N5,
Sgf_operation_RECURSIVE_EVEN1_middle_N4,
Sgf_operation_RECURSIVE_EVEN1_middle_N3,
Sgf_operation_RECURSIVE_EVEN1_middle_N2,
Sgf_operation_RECURSIVE_EVEN1_middle_N1,
Sgf_operation_RECURSIVE_EVEN1_middle_N0,
Sgf_operation_RECURSIVE_EVEN1_right_N23,
Sgf_operation_RECURSIVE_EVEN1_right_N22,
Sgf_operation_RECURSIVE_EVEN1_right_N21,
Sgf_operation_RECURSIVE_EVEN1_right_N20,
Sgf_operation_RECURSIVE_EVEN1_right_N19,
Sgf_operation_RECURSIVE_EVEN1_right_N18,
Sgf_operation_RECURSIVE_EVEN1_right_N17,
Sgf_operation_RECURSIVE_EVEN1_right_N16,
Sgf_operation_RECURSIVE_EVEN1_right_N15,
Sgf_operation_RECURSIVE_EVEN1_right_N14,
Sgf_operation_RECURSIVE_EVEN1_right_N13,
Sgf_operation_RECURSIVE_EVEN1_right_N12,
Sgf_operation_RECURSIVE_EVEN1_right_N11,
Sgf_operation_RECURSIVE_EVEN1_right_N10,
Sgf_operation_RECURSIVE_EVEN1_right_N9,
Sgf_operation_RECURSIVE_EVEN1_right_N8,
Sgf_operation_RECURSIVE_EVEN1_right_N7,
Sgf_operation_RECURSIVE_EVEN1_right_N6,
Sgf_operation_RECURSIVE_EVEN1_right_N5,
Sgf_operation_RECURSIVE_EVEN1_right_N4,
Sgf_operation_RECURSIVE_EVEN1_right_N3,
Sgf_operation_RECURSIVE_EVEN1_right_N2,
Sgf_operation_RECURSIVE_EVEN1_right_N1, n167, n169, n170, n171, n172,
n173, n174, n175, n176, n177, n178, n179, n180, n181, n182, n183,
n184, n185, n186, n187, n188, n189, n190, n191, n192, n193, n194,
n195, n196, n197, n198, n199, n200, n201, n202, n203, n204, n205,
n206, n207, n208, n209, n210, n211, n212, n213, n214, n215, n216,
n217, n218, n219, n220, n221, n222, n223, n224, n225, n226, n227,
n228, n229, n230, n231, n232, n233, n234, n235, n236, n237, n238,
n239, n240, n241, n242, n243, n244, n245, n246, n247, n248, n249,
n250, n251, n252, n253, n254, n255, n256, n257, n258, n259, n260,
n261, n262, n263, n264, n265, n266, n267, n268, n269, n270, n271,
n272, n273, n274, n275, n276, n277, n278, n279, n280, n281, n282,
n283, n284, n285, n286, n287, n288, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n310, n311, n312, n313, n314, n315, n316,
n317, n318, n319, n320, n321, n322, n323, n324, n325, n326, n327,
n328, n329, n330, n331, n332, n333, n334, n335, n336, n337, n338,
n339, n340, n341, n342, n343, n344, n345, n346, n347, n348, n349,
n350, n351, n352, n353, n354, n355, n356, n357, n358, n359, n360,
n361, n362, n363, n364, n365, n366, n367, n368, n369, n370, n371,
n372, n373, n374, n375, n376, n377, n378, n379, n380,
DP_OP_36J22_124_9196_n22, DP_OP_36J22_124_9196_n21,
DP_OP_36J22_124_9196_n20, DP_OP_36J22_124_9196_n19,
DP_OP_36J22_124_9196_n18, DP_OP_36J22_124_9196_n17,
DP_OP_36J22_124_9196_n16, DP_OP_36J22_124_9196_n15,
DP_OP_36J22_124_9196_n9, DP_OP_36J22_124_9196_n8,
DP_OP_36J22_124_9196_n7, DP_OP_36J22_124_9196_n6,
DP_OP_36J22_124_9196_n5, DP_OP_36J22_124_9196_n4,
DP_OP_36J22_124_9196_n3, DP_OP_36J22_124_9196_n2,
DP_OP_36J22_124_9196_n1, DP_OP_111J22_123_4462_n727,
DP_OP_111J22_123_4462_n474, DP_OP_111J22_123_4462_n473,
DP_OP_111J22_123_4462_n472, DP_OP_111J22_123_4462_n471,
DP_OP_111J22_123_4462_n470, DP_OP_111J22_123_4462_n469,
DP_OP_111J22_123_4462_n468, DP_OP_111J22_123_4462_n467,
DP_OP_111J22_123_4462_n461, DP_OP_111J22_123_4462_n460,
DP_OP_111J22_123_4462_n459, DP_OP_111J22_123_4462_n458,
DP_OP_111J22_123_4462_n457, DP_OP_111J22_123_4462_n456,
DP_OP_111J22_123_4462_n455, DP_OP_111J22_123_4462_n454,
DP_OP_111J22_123_4462_n453, DP_OP_111J22_123_4462_n452,
DP_OP_111J22_123_4462_n448, DP_OP_111J22_123_4462_n447,
DP_OP_111J22_123_4462_n445, DP_OP_111J22_123_4462_n444,
DP_OP_111J22_123_4462_n443, DP_OP_111J22_123_4462_n442,
DP_OP_111J22_123_4462_n441, DP_OP_111J22_123_4462_n440,
DP_OP_111J22_123_4462_n439, DP_OP_111J22_123_4462_n438,
DP_OP_111J22_123_4462_n437, DP_OP_111J22_123_4462_n436,
DP_OP_111J22_123_4462_n435, DP_OP_111J22_123_4462_n431,
DP_OP_111J22_123_4462_n430, DP_OP_111J22_123_4462_n429,
DP_OP_111J22_123_4462_n428, DP_OP_111J22_123_4462_n427,
DP_OP_111J22_123_4462_n426, DP_OP_111J22_123_4462_n425,
DP_OP_111J22_123_4462_n424, DP_OP_111J22_123_4462_n423,
DP_OP_111J22_123_4462_n418, DP_OP_111J22_123_4462_n417,
DP_OP_111J22_123_4462_n415, DP_OP_111J22_123_4462_n414,
DP_OP_111J22_123_4462_n413, DP_OP_111J22_123_4462_n412,
DP_OP_111J22_123_4462_n411, DP_OP_111J22_123_4462_n410,
DP_OP_111J22_123_4462_n409, DP_OP_111J22_123_4462_n408,
DP_OP_111J22_123_4462_n407, DP_OP_111J22_123_4462_n406,
DP_OP_111J22_123_4462_n401, DP_OP_111J22_123_4462_n400,
DP_OP_111J22_123_4462_n399, DP_OP_111J22_123_4462_n398,
DP_OP_111J22_123_4462_n397, DP_OP_111J22_123_4462_n396,
DP_OP_111J22_123_4462_n395, DP_OP_111J22_123_4462_n394,
DP_OP_111J22_123_4462_n388, DP_OP_111J22_123_4462_n387,
DP_OP_111J22_123_4462_n385, DP_OP_111J22_123_4462_n384,
DP_OP_111J22_123_4462_n369, DP_OP_111J22_123_4462_n366,
DP_OP_111J22_123_4462_n365, DP_OP_111J22_123_4462_n364,
DP_OP_111J22_123_4462_n363, DP_OP_111J22_123_4462_n362,
DP_OP_111J22_123_4462_n361, DP_OP_111J22_123_4462_n360,
DP_OP_111J22_123_4462_n359, DP_OP_111J22_123_4462_n358,
DP_OP_111J22_123_4462_n356, DP_OP_111J22_123_4462_n355,
DP_OP_111J22_123_4462_n354, DP_OP_111J22_123_4462_n352,
DP_OP_111J22_123_4462_n351, DP_OP_111J22_123_4462_n350,
DP_OP_111J22_123_4462_n349, DP_OP_111J22_123_4462_n348,
DP_OP_111J22_123_4462_n347, DP_OP_111J22_123_4462_n346,
DP_OP_111J22_123_4462_n345, DP_OP_111J22_123_4462_n344,
DP_OP_111J22_123_4462_n343, DP_OP_111J22_123_4462_n342,
DP_OP_111J22_123_4462_n341, DP_OP_111J22_123_4462_n340,
DP_OP_111J22_123_4462_n339, DP_OP_111J22_123_4462_n338,
DP_OP_111J22_123_4462_n337, DP_OP_111J22_123_4462_n336,
DP_OP_111J22_123_4462_n335, DP_OP_111J22_123_4462_n334,
DP_OP_111J22_123_4462_n333, DP_OP_111J22_123_4462_n332,
DP_OP_111J22_123_4462_n330, DP_OP_111J22_123_4462_n329,
DP_OP_111J22_123_4462_n328, DP_OP_111J22_123_4462_n327,
DP_OP_111J22_123_4462_n326, DP_OP_111J22_123_4462_n325,
DP_OP_111J22_123_4462_n324, DP_OP_111J22_123_4462_n323,
DP_OP_111J22_123_4462_n322, DP_OP_111J22_123_4462_n321,
DP_OP_111J22_123_4462_n320, DP_OP_111J22_123_4462_n319,
DP_OP_111J22_123_4462_n318, DP_OP_111J22_123_4462_n317,
DP_OP_111J22_123_4462_n315, DP_OP_111J22_123_4462_n313,
DP_OP_111J22_123_4462_n312, DP_OP_111J22_123_4462_n311,
DP_OP_111J22_123_4462_n310, DP_OP_111J22_123_4462_n309,
DP_OP_111J22_123_4462_n308, DP_OP_111J22_123_4462_n305,
DP_OP_111J22_123_4462_n304, DP_OP_111J22_123_4462_n303,
DP_OP_111J22_123_4462_n302, DP_OP_111J22_123_4462_n301,
DP_OP_111J22_123_4462_n300, DP_OP_111J22_123_4462_n299,
DP_OP_111J22_123_4462_n298, DP_OP_111J22_123_4462_n297,
DP_OP_111J22_123_4462_n296, DP_OP_111J22_123_4462_n295,
DP_OP_111J22_123_4462_n294, DP_OP_111J22_123_4462_n293,
DP_OP_111J22_123_4462_n292, DP_OP_111J22_123_4462_n291,
DP_OP_111J22_123_4462_n290, DP_OP_111J22_123_4462_n289,
DP_OP_111J22_123_4462_n288, DP_OP_111J22_123_4462_n287,
DP_OP_111J22_123_4462_n286, DP_OP_111J22_123_4462_n285,
DP_OP_111J22_123_4462_n284, DP_OP_111J22_123_4462_n283,
DP_OP_111J22_123_4462_n282, DP_OP_111J22_123_4462_n281,
DP_OP_111J22_123_4462_n280, DP_OP_111J22_123_4462_n279,
DP_OP_111J22_123_4462_n278, DP_OP_111J22_123_4462_n277,
DP_OP_111J22_123_4462_n274, DP_OP_111J22_123_4462_n273,
DP_OP_111J22_123_4462_n272, DP_OP_111J22_123_4462_n271,
DP_OP_111J22_123_4462_n270, DP_OP_111J22_123_4462_n269,
DP_OP_111J22_123_4462_n268, DP_OP_111J22_123_4462_n267,
DP_OP_111J22_123_4462_n266, DP_OP_111J22_123_4462_n265,
DP_OP_111J22_123_4462_n264, DP_OP_111J22_123_4462_n263,
DP_OP_111J22_123_4462_n262, DP_OP_111J22_123_4462_n261,
DP_OP_111J22_123_4462_n260, DP_OP_111J22_123_4462_n259,
DP_OP_111J22_123_4462_n258, DP_OP_111J22_123_4462_n257,
mult_x_23_n355, mult_x_23_n351, mult_x_23_n350, mult_x_23_n343,
mult_x_23_n342, mult_x_23_n340, mult_x_23_n339, mult_x_23_n338,
mult_x_23_n337, mult_x_23_n336, mult_x_23_n335, mult_x_23_n334,
mult_x_23_n331, mult_x_23_n330, mult_x_23_n329, mult_x_23_n327,
mult_x_23_n326, mult_x_23_n325, mult_x_23_n323, mult_x_23_n322,
mult_x_23_n321, mult_x_23_n320, mult_x_23_n319, mult_x_23_n318,
mult_x_23_n317, mult_x_23_n315, mult_x_23_n314, mult_x_23_n313,
mult_x_23_n312, mult_x_23_n311, mult_x_23_n310, mult_x_23_n309,
mult_x_23_n308, mult_x_23_n306, mult_x_23_n303, mult_x_23_n302,
mult_x_23_n301, mult_x_23_n300, mult_x_23_n299, mult_x_23_n298,
mult_x_23_n297, mult_x_23_n296, mult_x_23_n295, mult_x_23_n294,
mult_x_23_n293, mult_x_23_n292, mult_x_23_n291, mult_x_23_n285,
mult_x_23_n284, mult_x_23_n281, mult_x_23_n280, mult_x_23_n265,
mult_x_23_n262, mult_x_23_n261, mult_x_23_n260, mult_x_23_n259,
mult_x_23_n258, mult_x_23_n257, mult_x_23_n256, mult_x_23_n255,
mult_x_23_n254, mult_x_23_n253, mult_x_23_n252, mult_x_23_n251,
mult_x_23_n250, mult_x_23_n249, mult_x_23_n248, mult_x_23_n247,
mult_x_23_n246, mult_x_23_n245, mult_x_23_n244, mult_x_23_n243,
mult_x_23_n242, mult_x_23_n241, mult_x_23_n240, mult_x_23_n239,
mult_x_23_n238, mult_x_23_n237, mult_x_23_n236, mult_x_23_n235,
mult_x_23_n234, mult_x_23_n233, mult_x_23_n232, mult_x_23_n231,
mult_x_23_n230, mult_x_23_n229, mult_x_23_n228, mult_x_23_n227,
mult_x_23_n226, mult_x_23_n225, mult_x_23_n224, mult_x_23_n223,
mult_x_23_n222, mult_x_23_n221, mult_x_23_n219, mult_x_23_n218,
mult_x_23_n217, mult_x_23_n216, mult_x_23_n215, mult_x_23_n214,
mult_x_23_n213, mult_x_23_n212, mult_x_23_n209, mult_x_23_n208,
mult_x_23_n207, mult_x_23_n206, mult_x_23_n205, mult_x_23_n204,
mult_x_23_n203, mult_x_23_n202, mult_x_23_n201, mult_x_23_n200,
mult_x_23_n199, mult_x_23_n198, mult_x_23_n197, mult_x_23_n196,
mult_x_23_n195, mult_x_23_n194, mult_x_23_n191, mult_x_23_n190,
mult_x_23_n189, mult_x_23_n188, mult_x_23_n187, mult_x_23_n186,
mult_x_23_n185, mult_x_23_n184, mult_x_23_n183, mult_x_23_n182,
mult_x_23_n181, mult_x_23_n180, mult_x_23_n177, mult_x_23_n176,
mult_x_23_n175, mult_x_23_n174, mult_x_23_n173, mult_x_23_n172,
mult_x_23_n171, mult_x_23_n170, mult_x_23_n169, mult_x_23_n168,
mult_x_23_n165, mult_x_23_n164, mult_x_23_n163, mult_x_23_n162,
mult_x_23_n161, mult_x_23_n160, mult_x_55_n363, mult_x_55_n361,
mult_x_55_n359, mult_x_55_n357, mult_x_55_n351, mult_x_55_n350,
mult_x_55_n348, mult_x_55_n347, mult_x_55_n346, mult_x_55_n345,
mult_x_55_n344, mult_x_55_n343, mult_x_55_n342, mult_x_55_n339,
mult_x_55_n338, mult_x_55_n337, mult_x_55_n335, mult_x_55_n334,
mult_x_55_n331, mult_x_55_n330, mult_x_55_n329, mult_x_55_n328,
mult_x_55_n327, mult_x_55_n326, mult_x_55_n323, mult_x_55_n322,
mult_x_55_n321, mult_x_55_n320, mult_x_55_n317, mult_x_55_n316,
mult_x_55_n314, mult_x_55_n311, mult_x_55_n307, mult_x_55_n306,
mult_x_55_n305, mult_x_55_n304, mult_x_55_n301, mult_x_55_n300,
mult_x_55_n299, mult_x_55_n298, mult_x_55_n297, mult_x_55_n296,
mult_x_55_n295, mult_x_55_n294, mult_x_55_n293, mult_x_55_n292,
mult_x_55_n291, mult_x_55_n290, mult_x_55_n289, mult_x_55_n288,
mult_x_55_n282, mult_x_55_n280, mult_x_55_n273, mult_x_55_n267,
mult_x_55_n264, mult_x_55_n263, mult_x_55_n262, mult_x_55_n261,
mult_x_55_n260, mult_x_55_n259, mult_x_55_n258, mult_x_55_n257,
mult_x_55_n256, mult_x_55_n255, mult_x_55_n254, mult_x_55_n253,
mult_x_55_n252, mult_x_55_n251, mult_x_55_n250, mult_x_55_n249,
mult_x_55_n248, mult_x_55_n247, mult_x_55_n246, mult_x_55_n245,
mult_x_55_n244, mult_x_55_n243, mult_x_55_n242, mult_x_55_n241,
mult_x_55_n240, mult_x_55_n239, mult_x_55_n238, mult_x_55_n237,
mult_x_55_n236, mult_x_55_n235, mult_x_55_n234, mult_x_55_n233,
mult_x_55_n232, mult_x_55_n231, mult_x_55_n230, mult_x_55_n229,
mult_x_55_n228, mult_x_55_n227, mult_x_55_n226, mult_x_55_n225,
mult_x_55_n224, mult_x_55_n223, mult_x_55_n221, mult_x_55_n220,
mult_x_55_n219, mult_x_55_n218, mult_x_55_n217, mult_x_55_n216,
mult_x_55_n215, mult_x_55_n214, mult_x_55_n211, mult_x_55_n210,
mult_x_55_n209, mult_x_55_n208, mult_x_55_n207, mult_x_55_n206,
mult_x_55_n205, mult_x_55_n204, mult_x_55_n203, mult_x_55_n202,
mult_x_55_n201, mult_x_55_n200, mult_x_55_n199, mult_x_55_n198,
mult_x_55_n197, mult_x_55_n196, mult_x_55_n195, mult_x_55_n194,
mult_x_55_n193, mult_x_55_n192, mult_x_55_n191, mult_x_55_n190,
mult_x_55_n189, mult_x_55_n188, mult_x_55_n187, mult_x_55_n186,
mult_x_55_n185, mult_x_55_n184, mult_x_55_n183, mult_x_55_n182,
mult_x_55_n179, mult_x_55_n178, mult_x_55_n177, mult_x_55_n176,
mult_x_55_n175, mult_x_55_n174, mult_x_55_n173, mult_x_55_n172,
mult_x_55_n171, mult_x_55_n170, mult_x_55_n169, mult_x_55_n168,
mult_x_55_n167, mult_x_55_n166, mult_x_55_n165, mult_x_55_n164,
mult_x_55_n163, mult_x_55_n162, n390, n391, n392, n393, n394, n395,
n396, n397, n398, n399, n400, n401, n402, n403, n404, n405, n406,
n407, n408, n409, n410, n411, n412, n413, n414, n415, n416, n417,
n418, n419, n420, n421, n422, n423, n424, n425, n426, n427, n428,
n429, n430, n431, n432, n433, n434, n435, n436, n437, n438, n439,
n440, n441, n442, n443, n444, n445, n446, n447, n448, n449, n450,
n451, n452, n453, n454, n455, n456, n457, n458, n459, n460, n461,
n462, n463, n464, n465, n466, n467, n468, n469, n470, n471, n472,
n473, n474, n475, n476, n477, n478, n479, n480, n481, n482, n483,
n484, n485, n486, n487, n488, n489, n490, n491, n492, n493, n494,
n495, n496, n498, n499, n500, n501, n502, n503, n504, n505, n506,
n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517,
n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528,
n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539,
n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550,
n551, n552, n553, n554, n555, n556, n557, n558, n559, n560, n561,
n562, n563, n564, n565, n566, n567, n568, n569, n570, n571, n572,
n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, n583,
n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, n594,
n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605,
n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616,
n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638,
n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649,
n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660,
n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671,
n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682,
n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693,
n694, n695, n696, n697, n698, n699, n700, n701, n702, n703, n704,
n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715,
n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726,
n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737,
n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748,
n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759,
n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770,
n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781,
n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792,
n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803,
n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814,
n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, n825,
n826, n827, n828, n829, n830, n831, n832, n833, n834, n835, n836,
n837, n838, n839, n840, n841, n842, n843, n844, n845, n846, n847,
n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, n858,
n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869,
n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880,
n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891,
n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902,
n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913,
n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924,
n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935,
n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946,
n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701,
n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711,
n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721,
n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761,
n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771,
n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781,
n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791,
n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801,
n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811,
n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821,
n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831,
n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841,
n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851,
n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861,
n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871,
n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881,
n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891,
n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901,
n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911,
n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921,
n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931,
n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941,
n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951,
n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961,
n1962, n1963, n1964, n1966, n1967, n1968, n1969, n1970, n1971, n1972,
n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982,
n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992,
n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002,
n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042,
n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052,
n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062,
n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072,
n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082,
n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092,
n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102,
n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112,
n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122,
n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132,
n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142,
n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152,
n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162,
n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172,
n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182,
n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192,
n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202,
n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212,
n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222,
n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232,
n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242,
n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2381, n2382, n2383,
n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393,
n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403,
n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413,
n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423,
n2424;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [11:1] Sgf_operation_Result;
wire [25:0] Sgf_operation_RECURSIVE_EVEN1_Q_middle;
wire [23:12] Sgf_operation_RECURSIVE_EVEN1_Q_right;
wire [23:0] Sgf_operation_RECURSIVE_EVEN1_Q_left;
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_19_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N19), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[19]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_20_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N20), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[20]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_21_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N21), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[21]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_22_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N22), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[22]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_23_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N23), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[23]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_24_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N24), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_25_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N25), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[25]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_19_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N19), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[19]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_21_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N21), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[21]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_22_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N22), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[22]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_23_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N23), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[23]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n310), .CK(clk), .RN(
n2406), .Q(Op_MY[31]) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n378), .CK(clk), .RN(n2403), .Q(
FS_Module_state_reg[0]), .QN(n2390) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(clk), .RN(
n2407), .Q(Op_MX[21]), .QN(n414) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(clk), .RN(
n2407), .Q(Op_MX[19]), .QN(n420) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n358), .CK(clk), .RN(
n2407), .Q(Op_MX[14]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n356), .CK(clk), .RN(
n2408), .Q(Op_MX[12]), .QN(n589) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(clk), .RN(
n2408), .Q(Op_MX[8]), .QN(n575) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n345), .CK(clk), .RN(
n2409), .Q(Op_MX[1]), .QN(n576) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(clk), .RN(
n2409), .Q(Op_MX[31]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n306), .CK(clk), .RN(n2411),
.Q(Add_result[0]) );
DFFRXLTS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n282), .CK(clk), .RN(
n2411), .Q(FSM_add_overflow_flag), .QN(n2395) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(clk), .RN(
n2413), .Q(Op_MY[14]), .QN(n528) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(clk), .RN(
n2413), .Q(Op_MY[13]), .QN(n588) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(clk), .RN(
n2413), .Q(Op_MY[12]), .QN(n551) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(clk), .RN(
n2414), .Q(Op_MY[7]), .QN(n413) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(clk), .RN(
n2414), .Q(Op_MY[6]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(clk), .RN(
n2414), .Q(Op_MY[2]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(clk), .RN(
n2414), .Q(Op_MY[1]), .QN(n403) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n312), .CK(clk), .RN(
n2415), .Q(Op_MY[0]), .QN(n566) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(clk),
.RN(n2415), .Q(zero_flag), .QN(n2398) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_23_ ( .D(n238), .CK(
clk), .RN(n2403), .Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_22_ ( .D(n237), .CK(
clk), .RN(n2402), .Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_14_ ( .D(n229), .CK(
clk), .RN(n2401), .Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_12_ ( .D(n227), .CK(
clk), .RN(n2401), .Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_10_ ( .D(n225), .CK(
clk), .RN(n2401), .Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_9_ ( .D(n224), .CK(clk), .RN(n2401), .Q(P_Sgf[9]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_2_ ( .D(n217), .CK(clk), .RN(n2401), .Q(P_Sgf[2]) );
DFFRXLTS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_0_ ( .D(n215), .CK(clk), .RN(n2401), .Q(P_Sgf[0]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n307), .CK(clk),
.RN(n1943), .Q(Sgf_normalized_result[23]) );
CMPR32X2TS DP_OP_36J22_124_9196_U9 ( .A(DP_OP_36J22_124_9196_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J22_124_9196_n9), .CO(
DP_OP_36J22_124_9196_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J22_124_9196_U8 ( .A(DP_OP_36J22_124_9196_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J22_124_9196_n8), .CO(
DP_OP_36J22_124_9196_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J22_124_9196_U7 ( .A(DP_OP_36J22_124_9196_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J22_124_9196_n7), .CO(
DP_OP_36J22_124_9196_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J22_124_9196_U6 ( .A(DP_OP_36J22_124_9196_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J22_124_9196_n6), .CO(
DP_OP_36J22_124_9196_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J22_124_9196_U5 ( .A(DP_OP_36J22_124_9196_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J22_124_9196_n5), .CO(
DP_OP_36J22_124_9196_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J22_124_9196_U4 ( .A(DP_OP_36J22_124_9196_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J22_124_9196_n4), .CO(
DP_OP_36J22_124_9196_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J22_124_9196_U3 ( .A(DP_OP_36J22_124_9196_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J22_124_9196_n3), .CO(
DP_OP_36J22_124_9196_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J22_124_9196_U2 ( .A(n527), .B(S_Oper_A_exp[8]), .C(
DP_OP_36J22_124_9196_n2), .CO(DP_OP_36J22_124_9196_n1), .S(
Exp_module_Data_S[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n262),
.CK(clk), .RN(n2419), .Q(final_result_ieee[31]), .QN(n2399) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n198), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[7]), .QN(n2397) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n201), .CK(clk),
.RN(n2417), .Q(Sgf_normalized_result[10]), .QN(n2396) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n197), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[6]), .QN(n2393) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n195), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[4]), .QN(n2392) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n196), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[5]), .QN(n2389) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n200), .CK(clk),
.RN(n1943), .Q(Sgf_normalized_result[9]), .QN(n2388) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n194), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[3]), .QN(n2387) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n375), .CK(clk), .RN(n2406), .Q(FSM_selector_A),
.QN(n2394) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n199), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[8]), .QN(n2384) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n308), .CK(clk), .RN(n2415), .Q(
FSM_selector_B[1]), .QN(n2382) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n190),
.CK(clk), .RN(n2419), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n189),
.CK(clk), .RN(n2420), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n188),
.CK(clk), .RN(n2420), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n187),
.CK(clk), .RN(n2420), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n186),
.CK(clk), .RN(n2420), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n185),
.CK(clk), .RN(n2420), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n184),
.CK(clk), .RN(n2420), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n183),
.CK(clk), .RN(n2420), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n182),
.CK(clk), .RN(n2420), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n181),
.CK(clk), .RN(n2420), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n180),
.CK(clk), .RN(n2420), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n179),
.CK(clk), .RN(n2421), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n178),
.CK(clk), .RN(n2421), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n177),
.CK(clk), .RN(n2421), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n176),
.CK(clk), .RN(n2421), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n175),
.CK(clk), .RN(n2421), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n174),
.CK(clk), .RN(n2421), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n173),
.CK(clk), .RN(n2421), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n172),
.CK(clk), .RN(n2421), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n171),
.CK(clk), .RN(n2421), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n170),
.CK(clk), .RN(n2421), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n169),
.CK(clk), .RN(n2422), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n167),
.CK(clk), .RN(n2422), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n270),
.CK(clk), .RN(n2419), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n269),
.CK(clk), .RN(n2419), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n268),
.CK(clk), .RN(n2419), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n267),
.CK(clk), .RN(n2419), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n266),
.CK(clk), .RN(n2419), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n265),
.CK(clk), .RN(n2419), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n264),
.CK(clk), .RN(n2419), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n263),
.CK(clk), .RN(n2419), .Q(final_result_ieee[30]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n271), .CK(clk), .RN(n2416), .Q(
Exp_module_Overflow_flag_A) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n272), .CK(clk), .RN(n2418),
.Q(underflow_flag), .QN(n2400) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_23_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N23), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[23]) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n376), .CK(clk), .RN(n2403), .Q(
FS_Module_state_reg[2]), .QN(n2383) );
CMPR42X1TS DP_OP_111J22_123_4462_U319 ( .A(DP_OP_111J22_123_4462_n447), .B(
DP_OP_111J22_123_4462_n363), .C(DP_OP_111J22_123_4462_n364), .D(
DP_OP_111J22_123_4462_n460), .ICI(DP_OP_111J22_123_4462_n473), .S(
DP_OP_111J22_123_4462_n361), .ICO(DP_OP_111J22_123_4462_n359), .CO(
DP_OP_111J22_123_4462_n360) );
CMPR42X1TS DP_OP_111J22_123_4462_U310 ( .A(DP_OP_111J22_123_4462_n417), .B(
DP_OP_111J22_123_4462_n340), .C(DP_OP_111J22_123_4462_n344), .D(
DP_OP_111J22_123_4462_n430), .ICI(DP_OP_111J22_123_4462_n443), .S(
DP_OP_111J22_123_4462_n338), .ICO(DP_OP_111J22_123_4462_n336), .CO(
DP_OP_111J22_123_4462_n337) );
CMPR42X2TS DP_OP_111J22_123_4462_U309 ( .A(DP_OP_111J22_123_4462_n456), .B(
DP_OP_111J22_123_4462_n469), .C(DP_OP_111J22_123_4462_n345), .D(
DP_OP_111J22_123_4462_n341), .ICI(DP_OP_111J22_123_4462_n338), .S(
DP_OP_111J22_123_4462_n335), .ICO(DP_OP_111J22_123_4462_n333), .CO(
DP_OP_111J22_123_4462_n334) );
CMPR42X1TS DP_OP_111J22_123_4462_U307 ( .A(DP_OP_111J22_123_4462_n339), .B(
DP_OP_111J22_123_4462_n332), .C(DP_OP_111J22_123_4462_n442), .D(
DP_OP_111J22_123_4462_n429), .ICI(DP_OP_111J22_123_4462_n455), .S(
DP_OP_111J22_123_4462_n330), .ICO(DP_OP_111J22_123_4462_n328), .CO(
DP_OP_111J22_123_4462_n329) );
CMPR42X2TS DP_OP_111J22_123_4462_U303 ( .A(DP_OP_111J22_123_4462_n441), .B(
DP_OP_111J22_123_4462_n454), .C(DP_OP_111J22_123_4462_n329), .D(
DP_OP_111J22_123_4462_n325), .ICI(DP_OP_111J22_123_4462_n322), .S(
DP_OP_111J22_123_4462_n319), .ICO(DP_OP_111J22_123_4462_n317), .CO(
DP_OP_111J22_123_4462_n318) );
CMPR42X2TS DP_OP_111J22_123_4462_U299 ( .A(DP_OP_111J22_123_4462_n453), .B(
DP_OP_111J22_123_4462_n440), .C(DP_OP_111J22_123_4462_n321), .D(
DP_OP_111J22_123_4462_n313), .ICI(DP_OP_111J22_123_4462_n317), .S(
DP_OP_111J22_123_4462_n310), .ICO(DP_OP_111J22_123_4462_n308), .CO(
DP_OP_111J22_123_4462_n309) );
CMPR42X2TS DP_OP_111J22_123_4462_U295 ( .A(DP_OP_111J22_123_4462_n426), .B(
DP_OP_111J22_123_4462_n439), .C(DP_OP_111J22_123_4462_n312), .D(
DP_OP_111J22_123_4462_n303), .ICI(DP_OP_111J22_123_4462_n308), .S(
DP_OP_111J22_123_4462_n300), .ICO(DP_OP_111J22_123_4462_n298), .CO(
DP_OP_111J22_123_4462_n299) );
CMPR42X1TS DP_OP_111J22_123_4462_U290 ( .A(DP_OP_111J22_123_4462_n388), .B(
DP_OP_111J22_123_4462_n290), .C(DP_OP_111J22_123_4462_n437), .D(
DP_OP_111J22_123_4462_n399), .ICI(DP_OP_111J22_123_4462_n294), .S(
DP_OP_111J22_123_4462_n288), .ICO(DP_OP_111J22_123_4462_n286), .CO(
DP_OP_111J22_123_4462_n287) );
CMPR42X2TS DP_OP_111J22_123_4462_U289 ( .A(DP_OP_111J22_123_4462_n411), .B(
DP_OP_111J22_123_4462_n424), .C(DP_OP_111J22_123_4462_n295), .D(
DP_OP_111J22_123_4462_n288), .ICI(DP_OP_111J22_123_4462_n291), .S(
DP_OP_111J22_123_4462_n285), .ICO(DP_OP_111J22_123_4462_n283), .CO(
DP_OP_111J22_123_4462_n284) );
CMPR42X1TS DP_OP_111J22_123_4462_U288 ( .A(DP_OP_111J22_123_4462_n436), .B(
DP_OP_111J22_123_4462_n289), .C(DP_OP_111J22_123_4462_n387), .D(
DP_OP_111J22_123_4462_n398), .ICI(DP_OP_111J22_123_4462_n423), .S(
DP_OP_111J22_123_4462_n282), .ICO(DP_OP_111J22_123_4462_n280), .CO(
DP_OP_111J22_123_4462_n281) );
CMPR42X2TS DP_OP_111J22_123_4462_U284 ( .A(DP_OP_111J22_123_4462_n397), .B(
DP_OP_111J22_123_4462_n409), .C(DP_OP_111J22_123_4462_n274), .D(
DP_OP_111J22_123_4462_n281), .ICI(DP_OP_111J22_123_4462_n277), .S(
DP_OP_111J22_123_4462_n272), .ICO(DP_OP_111J22_123_4462_n270), .CO(
DP_OP_111J22_123_4462_n271) );
CMPR42X2TS DP_OP_111J22_123_4462_U282 ( .A(DP_OP_111J22_123_4462_n408), .B(
DP_OP_111J22_123_4462_n269), .C(DP_OP_111J22_123_4462_n396), .D(
DP_OP_111J22_123_4462_n273), .ICI(DP_OP_111J22_123_4462_n270), .S(
DP_OP_111J22_123_4462_n267), .ICO(DP_OP_111J22_123_4462_n265), .CO(
DP_OP_111J22_123_4462_n266) );
CMPR42X1TS DP_OP_111J22_123_4462_U280 ( .A(DP_OP_111J22_123_4462_n264), .B(
DP_OP_111J22_123_4462_n385), .C(DP_OP_111J22_123_4462_n268), .D(
DP_OP_111J22_123_4462_n395), .ICI(DP_OP_111J22_123_4462_n265), .S(
DP_OP_111J22_123_4462_n262), .ICO(DP_OP_111J22_123_4462_n260), .CO(
DP_OP_111J22_123_4462_n261) );
CMPR42X2TS mult_x_23_U218 ( .A(mult_x_23_n342), .B(mult_x_23_n318), .C(
mult_x_23_n330), .D(mult_x_23_n259), .ICI(mult_x_23_n260), .S(
mult_x_23_n257), .ICO(mult_x_23_n255), .CO(mult_x_23_n256) );
CMPR42X2TS mult_x_23_U216 ( .A(mult_x_23_n329), .B(mult_x_23_n317), .C(
mult_x_23_n258), .D(mult_x_23_n255), .ICI(mult_x_23_n254), .S(
mult_x_23_n252), .ICO(mult_x_23_n250), .CO(mult_x_23_n251) );
CMPR42X2TS mult_x_23_U212 ( .A(mult_x_23_n291), .B(mult_x_23_n351), .C(
mult_x_23_n339), .D(mult_x_23_n327), .ICI(mult_x_23_n248), .S(
mult_x_23_n242), .ICO(mult_x_23_n240), .CO(mult_x_23_n241) );
CMPR42X2TS mult_x_23_U211 ( .A(mult_x_23_n315), .B(mult_x_23_n303), .C(
mult_x_23_n246), .D(mult_x_23_n243), .ICI(mult_x_23_n242), .S(
mult_x_23_n239), .ICO(mult_x_23_n237), .CO(mult_x_23_n238) );
CMPR42X2TS mult_x_23_U209 ( .A(mult_x_23_n350), .B(mult_x_23_n338), .C(
mult_x_23_n302), .D(mult_x_23_n236), .ICI(mult_x_23_n240), .S(
mult_x_23_n234), .ICO(mult_x_23_n232), .CO(mult_x_23_n233) );
CMPR42X1TS mult_x_23_U208 ( .A(mult_x_23_n326), .B(mult_x_23_n314), .C(
mult_x_23_n237), .D(mult_x_23_n241), .ICI(mult_x_23_n234), .S(
mult_x_23_n231), .ICO(mult_x_23_n229), .CO(mult_x_23_n230) );
CMPR42X2TS mult_x_23_U201 ( .A(mult_x_23_n227), .B(mult_x_23_n219), .C(
mult_x_23_n225), .D(mult_x_23_n217), .ICI(mult_x_23_n221), .S(
mult_x_23_n214), .ICO(mult_x_23_n212), .CO(mult_x_23_n213) );
CMPR42X1TS mult_x_23_U198 ( .A(mult_x_23_n311), .B(mult_x_23_n335), .C(
mult_x_23_n323), .D(mult_x_23_n209), .ICI(mult_x_23_n215), .S(
mult_x_23_n207), .ICO(mult_x_23_n205), .CO(mult_x_23_n206) );
CMPR42X1TS mult_x_23_U192 ( .A(n590), .B(mult_x_23_n285), .C(mult_x_23_n321),
.D(mult_x_23_n297), .ICI(mult_x_23_n309), .S(mult_x_23_n191), .ICO(
mult_x_23_n189), .CO(mult_x_23_n190) );
CMPR42X2TS mult_x_23_U191 ( .A(mult_x_23_n200), .B(mult_x_23_n197), .C(
mult_x_23_n191), .D(mult_x_23_n198), .ICI(mult_x_23_n194), .S(
mult_x_23_n188), .ICO(mult_x_23_n186), .CO(mult_x_23_n187) );
CMPR42X1TS mult_x_23_U190 ( .A(n398), .B(n442), .C(mult_x_23_n284), .D(
mult_x_23_n308), .ICI(mult_x_23_n296), .S(mult_x_23_n185), .ICO(
mult_x_23_n183), .CO(mult_x_23_n184) );
CMPR42X1TS mult_x_23_U189 ( .A(mult_x_23_n320), .B(mult_x_23_n189), .C(
mult_x_23_n190), .D(mult_x_23_n185), .ICI(mult_x_23_n186), .S(
mult_x_23_n182), .ICO(mult_x_23_n180), .CO(mult_x_23_n181) );
CMPR42X2TS mult_x_23_U186 ( .A(mult_x_23_n295), .B(mult_x_23_n183), .C(
mult_x_23_n177), .D(mult_x_23_n184), .ICI(mult_x_23_n180), .S(
mult_x_23_n175), .ICO(mult_x_23_n173), .CO(mult_x_23_n174) );
CMPR42X1TS mult_x_55_U222 ( .A(mult_x_55_n327), .B(mult_x_55_n339), .C(
mult_x_55_n351), .D(mult_x_55_n363), .ICI(mult_x_55_n267), .S(
mult_x_55_n264), .ICO(mult_x_55_n262), .CO(mult_x_55_n263) );
CMPR42X2TS mult_x_55_U220 ( .A(mult_x_55_n350), .B(mult_x_55_n326), .C(
mult_x_55_n338), .D(mult_x_55_n261), .ICI(mult_x_55_n262), .S(
mult_x_55_n259), .ICO(mult_x_55_n257), .CO(mult_x_55_n258) );
CMPR42X2TS mult_x_55_U215 ( .A(mult_x_55_n348), .B(mult_x_55_n251), .C(
mult_x_55_n255), .D(mult_x_55_n249), .ICI(mult_x_55_n252), .S(
mult_x_55_n247), .ICO(mult_x_55_n245), .CO(mult_x_55_n246) );
CMPR42X1TS mult_x_55_U214 ( .A(mult_x_55_n299), .B(mult_x_55_n323), .C(
mult_x_55_n347), .D(mult_x_55_n311), .ICI(mult_x_55_n248), .S(
mult_x_55_n244), .ICO(mult_x_55_n242), .CO(mult_x_55_n243) );
CMPR42X2TS mult_x_55_U211 ( .A(mult_x_55_n322), .B(mult_x_55_n334), .C(
mult_x_55_n273), .D(mult_x_55_n298), .ICI(mult_x_55_n239), .S(
mult_x_55_n236), .ICO(mult_x_55_n234), .CO(mult_x_55_n235) );
CMPR42X1TS mult_x_55_U210 ( .A(mult_x_55_n346), .B(mult_x_55_n238), .C(
mult_x_55_n242), .D(mult_x_55_n243), .ICI(mult_x_55_n236), .S(
mult_x_55_n233), .ICO(mult_x_55_n231), .CO(mult_x_55_n232) );
CMPR42X1TS mult_x_55_U208 ( .A(mult_x_55_n321), .B(mult_x_55_n345), .C(
mult_x_55_n297), .D(mult_x_55_n357), .ICI(mult_x_55_n230), .S(
mult_x_55_n228), .ICO(mult_x_55_n226), .CO(mult_x_55_n227) );
CMPR42X1TS mult_x_55_U204 ( .A(mult_x_55_n320), .B(mult_x_55_n344), .C(
mult_x_55_n296), .D(n403), .ICI(mult_x_55_n221), .S(mult_x_55_n219),
.ICO(mult_x_55_n217), .CO(mult_x_55_n218) );
CMPR42X2TS mult_x_55_U203 ( .A(mult_x_55_n226), .B(mult_x_55_n229), .C(
mult_x_55_n227), .D(mult_x_55_n223), .ICI(mult_x_55_n219), .S(
mult_x_55_n216), .ICO(mult_x_55_n214), .CO(mult_x_55_n215) );
CMPR42X1TS mult_x_55_U200 ( .A(mult_x_55_n307), .B(mult_x_55_n343), .C(
mult_x_55_n331), .D(mult_x_55_n295), .ICI(mult_x_55_n220), .S(
mult_x_55_n209), .ICO(mult_x_55_n207), .CO(mult_x_55_n208) );
CMPR42X2TS mult_x_55_U199 ( .A(mult_x_55_n211), .B(mult_x_55_n217), .C(
mult_x_55_n218), .D(mult_x_55_n209), .ICI(mult_x_55_n214), .S(
mult_x_55_n206), .ICO(mult_x_55_n204), .CO(mult_x_55_n205) );
CMPR42X2TS mult_x_55_U197 ( .A(mult_x_55_n306), .B(mult_x_55_n330), .C(
mult_x_55_n294), .D(mult_x_55_n342), .ICI(mult_x_55_n207), .S(
mult_x_55_n201), .ICO(mult_x_55_n199), .CO(mult_x_55_n200) );
CMPR42X2TS mult_x_55_U196 ( .A(mult_x_55_n210), .B(mult_x_55_n203), .C(
mult_x_55_n208), .D(mult_x_55_n201), .ICI(mult_x_55_n204), .S(
mult_x_55_n198), .ICO(mult_x_55_n196), .CO(mult_x_55_n197) );
CMPR42X1TS mult_x_55_U194 ( .A(mult_x_55_n195), .B(mult_x_55_n329), .C(
mult_x_55_n317), .D(mult_x_55_n305), .ICI(mult_x_55_n202), .S(
mult_x_55_n193), .ICO(mult_x_55_n191), .CO(mult_x_55_n192) );
CMPR42X1TS mult_x_55_U192 ( .A(mult_x_55_n194), .B(mult_x_55_n282), .C(
mult_x_55_n316), .D(mult_x_55_n304), .ICI(mult_x_55_n328), .S(
mult_x_55_n187), .ICO(mult_x_55_n185), .CO(mult_x_55_n186) );
CMPR42X1TS mult_x_55_U191 ( .A(mult_x_55_n292), .B(mult_x_55_n191), .C(
mult_x_55_n187), .D(mult_x_55_n192), .ICI(mult_x_55_n188), .S(
mult_x_55_n184), .ICO(mult_x_55_n182), .CO(mult_x_55_n183) );
CMPR42X2TS mult_x_23_U197 ( .A(mult_x_23_n299), .B(mult_x_23_n218), .C(
mult_x_23_n216), .D(mult_x_23_n207), .ICI(mult_x_23_n212), .S(
mult_x_23_n204), .ICO(mult_x_23_n202), .CO(mult_x_23_n203) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(clk), .RN(
n2414), .Q(Op_MY[10]) );
CMPR42X2TS DP_OP_111J22_123_4462_U317 ( .A(DP_OP_111J22_123_4462_n362), .B(
DP_OP_111J22_123_4462_n358), .C(DP_OP_111J22_123_4462_n472), .D(
DP_OP_111J22_123_4462_n459), .ICI(DP_OP_111J22_123_4462_n359), .S(
DP_OP_111J22_123_4462_n356), .ICO(DP_OP_111J22_123_4462_n354), .CO(
DP_OP_111J22_123_4462_n355) );
CMPR42X2TS DP_OP_111J22_123_4462_U296 ( .A(DP_OP_111J22_123_4462_n452), .B(
DP_OP_111J22_123_4462_n401), .C(DP_OP_111J22_123_4462_n413), .D(
DP_OP_111J22_123_4462_n305), .ICI(DP_OP_111J22_123_4462_n311), .S(
DP_OP_111J22_123_4462_n303), .ICO(DP_OP_111J22_123_4462_n301), .CO(
DP_OP_111J22_123_4462_n302) );
CMPR42X2TS DP_OP_111J22_123_4462_U287 ( .A(DP_OP_111J22_123_4462_n410), .B(
DP_OP_111J22_123_4462_n286), .C(DP_OP_111J22_123_4462_n282), .D(
DP_OP_111J22_123_4462_n287), .ICI(DP_OP_111J22_123_4462_n283), .S(
DP_OP_111J22_123_4462_n279), .ICO(DP_OP_111J22_123_4462_n277), .CO(
DP_OP_111J22_123_4462_n278) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(clk), .RN(
n2412), .Q(Op_MY[22]), .QN(n573) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n330), .CK(clk), .RN(
n2413), .Q(Op_MY[18]), .QN(n574) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(clk), .RN(
n2413), .Q(Op_MY[11]), .QN(DP_OP_111J22_123_4462_n727) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(clk), .RN(
n2414), .Q(Op_MY[9]), .QN(n584) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(clk), .RN(
n2414), .Q(Op_MY[8]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n344), .CK(clk), .RN(
n2409), .Q(Op_MX[0]), .QN(n585) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n281), .CK(clk), .RN(n2415),
.Q(exp_oper_result[8]) );
MDFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_0_ ( .D0(n585), .D1(
1'b1), .S0(n455), .CK(clk), .Q(n2381) );
DFFRX1TS FS_Module_state_reg_reg_3_ ( .D(n379), .CK(clk), .RN(n2424), .Q(
FS_Module_state_reg[3]), .QN(n562) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n191), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n193), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(clk), .RN(
n2413), .Q(Op_MY[20]), .QN(n592) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(clk), .RN(
n2408), .Q(Op_MX[11]), .QN(n561) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n202), .CK(clk),
.RN(n2416), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n204), .CK(clk),
.RN(n2417), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n206), .CK(clk),
.RN(n1943), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n208), .CK(clk),
.RN(n2416), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n210), .CK(clk),
.RN(n2417), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n212), .CK(clk),
.RN(n2416), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n203), .CK(clk),
.RN(n2417), .Q(Sgf_normalized_result[12]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n205), .CK(clk),
.RN(n2416), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n207), .CK(clk),
.RN(n2417), .Q(Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n209), .CK(clk),
.RN(n2416), .Q(Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n211), .CK(clk),
.RN(n2417), .Q(Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n213), .CK(clk),
.RN(n2416), .Q(Sgf_normalized_result[22]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(
n2406), .Q(Op_MX[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(
n2406), .Q(Op_MX[29]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_47_ ( .D(n380), .CK(
clk), .RN(n2403), .Q(P_Sgf[47]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(clk), .RN(
n2412), .Q(Op_MY[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(
n2406), .Q(Op_MX[24]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(clk), .RN(
n2412), .Q(Op_MY[27]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n273), .CK(clk), .RN(n1955),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n275), .CK(clk), .RN(n1955),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n277), .CK(clk), .RN(n2415),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n278), .CK(clk), .RN(n2415),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n280), .CK(clk), .RN(n2415),
.Q(exp_oper_result[0]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(clk), .RN(
n2412), .Q(Op_MY[23]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_21_ ( .D(n236), .CK(
clk), .RN(n2402), .Q(P_Sgf[21]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_1_ ( .D(n216), .CK(clk), .RN(n2402), .Q(P_Sgf[1]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_13_ ( .D(n228), .CK(
clk), .RN(n2403), .Q(P_Sgf[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n192), .CK(clk),
.RN(n2418), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(
n2406), .Q(Op_MX[25]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(
n2406), .Q(Op_MX[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(
n2406), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(
n2406), .Q(Op_MX[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(
n2407), .Q(Op_MX[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n284), .CK(clk), .RN(n2409),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n285), .CK(clk), .RN(n2409),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n286), .CK(clk), .RN(n2409),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n287), .CK(clk), .RN(n2409),
.Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n288), .CK(clk), .RN(n2409),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n289), .CK(clk), .RN(n2410),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n290), .CK(clk), .RN(n2410),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n291), .CK(clk), .RN(n2410),
.Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n292), .CK(clk), .RN(n2410),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n293), .CK(clk), .RN(n2410),
.Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n294), .CK(clk), .RN(n2410),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n295), .CK(clk), .RN(n2410),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n296), .CK(clk), .RN(n2410),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n297), .CK(clk), .RN(n2410),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n298), .CK(clk), .RN(n2410),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n299), .CK(clk), .RN(n2411),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n300), .CK(clk), .RN(n2411),
.Q(Add_result[6]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n301), .CK(clk), .RN(n2411),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n302), .CK(clk), .RN(n2411),
.Q(Add_result[4]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n303), .CK(clk), .RN(n2411),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n304), .CK(clk), .RN(n2411),
.Q(Add_result[2]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n305), .CK(clk), .RN(n2411),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n283), .CK(clk), .RN(n2411),
.Q(Add_result[23]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(clk), .RN(
n2412), .Q(Op_MY[29]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(clk), .RN(
n2412), .Q(Op_MY[25]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n279), .CK(clk), .RN(n2415),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n276), .CK(clk), .RN(n2415),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n274), .CK(clk), .RN(n1955),
.Q(exp_oper_result[6]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(clk), .RN(
n2412), .Q(Op_MY[26]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(clk), .RN(
n2412), .Q(Op_MY[28]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(clk), .RN(
n2412), .Q(Op_MY[24]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_46_ ( .D(n261), .CK(
clk), .RN(n2424), .Q(P_Sgf[46]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_45_ ( .D(n260), .CK(
clk), .RN(n2405), .Q(P_Sgf[45]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_44_ ( .D(n259), .CK(
clk), .RN(n2405), .Q(P_Sgf[44]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_43_ ( .D(n258), .CK(
clk), .RN(n2405), .Q(P_Sgf[43]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_42_ ( .D(n257), .CK(
clk), .RN(n2405), .Q(P_Sgf[42]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_41_ ( .D(n256), .CK(
clk), .RN(n2405), .Q(P_Sgf[41]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_40_ ( .D(n255), .CK(
clk), .RN(n2405), .Q(P_Sgf[40]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_39_ ( .D(n254), .CK(
clk), .RN(n2405), .Q(P_Sgf[39]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_38_ ( .D(n253), .CK(
clk), .RN(n2405), .Q(P_Sgf[38]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_37_ ( .D(n252), .CK(
clk), .RN(n2405), .Q(P_Sgf[37]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_36_ ( .D(n251), .CK(
clk), .RN(n2405), .Q(P_Sgf[36]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_35_ ( .D(n250), .CK(
clk), .RN(n2404), .Q(P_Sgf[35]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_34_ ( .D(n249), .CK(
clk), .RN(n2404), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_33_ ( .D(n248), .CK(
clk), .RN(n2404), .Q(P_Sgf[33]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_32_ ( .D(n247), .CK(
clk), .RN(n2404), .Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_31_ ( .D(n246), .CK(
clk), .RN(n2404), .Q(P_Sgf[31]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_30_ ( .D(n245), .CK(
clk), .RN(n2404), .Q(P_Sgf[30]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_29_ ( .D(n244), .CK(
clk), .RN(n2404), .Q(P_Sgf[29]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_28_ ( .D(n243), .CK(
clk), .RN(n2404), .Q(P_Sgf[28]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_27_ ( .D(n242), .CK(
clk), .RN(n2404), .Q(P_Sgf[27]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_26_ ( .D(n241), .CK(
clk), .RN(n2404), .Q(P_Sgf[26]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_25_ ( .D(n240), .CK(
clk), .RN(n2403), .Q(P_Sgf[25]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_24_ ( .D(n239), .CK(
clk), .RN(n2403), .Q(P_Sgf[24]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_20_ ( .D(n235), .CK(
clk), .RN(n2402), .Q(P_Sgf[20]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_19_ ( .D(n234), .CK(
clk), .RN(n2402), .Q(P_Sgf[19]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_15_ ( .D(n230), .CK(
clk), .RN(n2403), .Q(P_Sgf[15]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_3_ ( .D(n218), .CK(clk), .RN(n2402), .Q(P_Sgf[3]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_18_ ( .D(n233), .CK(
clk), .RN(n2402), .Q(P_Sgf[18]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_17_ ( .D(n232), .CK(
clk), .RN(n2403), .Q(P_Sgf[17]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_5_ ( .D(n220), .CK(clk), .RN(n2402), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_16_ ( .D(n231), .CK(
clk), .RN(n2402), .Q(P_Sgf[16]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_4_ ( .D(n219), .CK(clk), .RN(n2402), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_8_ ( .D(n223), .CK(clk), .RN(n2401), .Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_7_ ( .D(n222), .CK(clk), .RN(n2401), .Q(P_Sgf[7]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_6_ ( .D(n221), .CK(clk), .RN(n2401), .Q(P_Sgf[6]) );
DFFRX1TS Sgf_operation_RECURSIVE_EVEN1_finalreg_Q_reg_11_ ( .D(n226), .CK(
clk), .RN(n2401), .Q(P_Sgf[11]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(clk), .RN(
n2407), .Q(Op_MX[15]), .QN(n421) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n346), .CK(clk), .RN(
n2409), .Q(Op_MX[2]), .QN(n572) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(clk), .RN(
n2407), .Q(Op_MX[17]), .QN(n419) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n357), .CK(clk), .RN(
n2408), .Q(Op_MX[13]), .QN(n596) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(clk), .RN(
n2413), .Q(n398), .QN(n590) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(clk), .RN(
n2412), .Q(n399), .QN(n407) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(clk), .RN(
n2408), .Q(n397), .QN(n579) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_1_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N1), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[1]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_6_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N6), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[6]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_13_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N13), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[13]) );
DFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_14_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N14), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[14]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_18_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N18), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[18]) );
DFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_4_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N4), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[4]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_14_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N14), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[14]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_16_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N16), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[16]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_17_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N17), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[17]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_18_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N18), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[18]) );
DFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_3_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N3), .CK(clk), .Q(
Sgf_operation_Result[3]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_4_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N4), .CK(clk), .Q(
Sgf_operation_Result[4]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_8_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N8), .CK(clk), .Q(
Sgf_operation_Result[8]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_17_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N17), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[17]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_18_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N18), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[18]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_20_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N20), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[20]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(clk), .RN(
n2407), .Q(Op_MX[18]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(clk), .RN(
n2408), .Q(n400), .QN(n569) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(clk), .RN(
n2408), .Q(Op_MX[6]), .QN(n393) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(clk), .RN(
n2408), .Q(n401), .QN(n586) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(clk), .RN(
n2408), .Q(Op_MX[4]), .QN(n394) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_20_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N20), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[20]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_22_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N22), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[22]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_21_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N21), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[21]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_19_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N19), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[19]) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n214), .CK(clk), .RN(n1955), .Q(FSM_selector_C),
.QN(n2391) );
DFFSX1TS Sel_B_Q_reg_0_ ( .D(n2423), .CK(clk), .SN(n2415), .Q(n2386), .QN(
FSM_selector_B[0]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_16_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N16), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[16]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(clk), .RN(
n2414), .Q(Op_MY[4]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(clk), .RN(
n2409), .Q(Op_MX[3]), .QN(n577) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(clk), .RN(
n2407), .Q(Op_MX[22]), .QN(n568) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(clk), .RN(
n2407), .Q(Op_MX[16]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(clk), .RN(
n2414), .Q(Op_MY[5]), .QN(n418) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(clk), .RN(
n2407), .Q(Op_MX[20]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(clk), .RN(
n2413), .Q(Op_MY[17]), .QN(n396) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(clk), .RN(
n2413), .Q(Op_MY[15]), .QN(n392) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n331), .CK(clk), .RN(
n2413), .Q(Op_MY[19]), .QN(n391) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_7_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N7), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[7]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_6_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N6), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[6]) );
DFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_5_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N5), .CK(clk), .Q(
Sgf_operation_Result[5]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_10_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N10), .CK(clk), .Q(
Sgf_operation_Result[10]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_3_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N3), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[3]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_8_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N8), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[8]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_9_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N9), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_14_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N14), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[14]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_6_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N6), .CK(clk), .Q(
Sgf_operation_Result[6]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_7_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N7), .CK(clk), .Q(
Sgf_operation_Result[7]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_9_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N9), .CK(clk), .Q(
Sgf_operation_Result[9]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_11_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N11), .CK(clk), .Q(
Sgf_operation_Result[11]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_4_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N4), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[4]) );
DFFHQX2TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_15_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N15), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[15]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_11_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N11), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[11]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_5_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N5), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[5]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_0_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N0), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_12_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N12), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[12]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_10_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N10), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[10]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_13_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N13), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[13]) );
DFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_1_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N1), .CK(clk), .Q(
Sgf_operation_Result[1]) );
DFFHQX1TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_2_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N2), .CK(clk), .Q(
Sgf_operation_Result[2]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_15_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N15), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[15]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_2_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N2), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[2]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_right_DatO_reg_12_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_right_N12), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_right[12]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_2_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N2), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[2]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_7_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N7), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[7]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_9_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N9), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[9]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_11_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N11), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[11]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_13_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N13), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[13]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_15_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N15), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[15]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_10_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N10), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[10]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_12_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N12), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[12]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_0_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N0), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[0]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_1_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N1), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_3_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N3), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[3]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_5_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N5), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[5]) );
DFFQX4TS Sgf_operation_RECURSIVE_EVEN1_middle_DatO_reg_8_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_middle_N8), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_middle[8]) );
DFFQX1TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_17_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N17), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[17]) );
DFFQX2TS Sgf_operation_RECURSIVE_EVEN1_left_DatO_reg_16_ ( .D(
Sgf_operation_RECURSIVE_EVEN1_left_N16), .CK(clk), .Q(
Sgf_operation_RECURSIVE_EVEN1_Q_left[16]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(clk), .RN(
n2408), .Q(Op_MX[10]), .QN(n581) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(clk), .RN(
n2414), .Q(Op_MY[3]), .QN(n415) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n377), .CK(clk), .RN(n2403), .Q(
FS_Module_state_reg[1]), .QN(n2385) );
CMPR42X1TS mult_x_55_U213 ( .A(mult_x_55_n335), .B(mult_x_55_n359), .C(
mult_x_55_n250), .D(mult_x_55_n245), .ICI(mult_x_55_n244), .S(
mult_x_55_n241), .ICO(mult_x_55_n239), .CO(mult_x_55_n240) );
CMPR32X2TS DP_OP_36J22_124_9196_U10 ( .A(S_Oper_A_exp[0]), .B(n1954), .C(
DP_OP_36J22_124_9196_n22), .CO(DP_OP_36J22_124_9196_n9), .S(
Exp_module_Data_S[0]) );
CMPR42X1TS mult_x_55_U193 ( .A(mult_x_55_n293), .B(mult_x_55_n199), .C(
mult_x_55_n200), .D(mult_x_55_n193), .ICI(mult_x_55_n196), .S(
mult_x_55_n190), .ICO(mult_x_55_n188), .CO(mult_x_55_n189) );
CMPR42X1TS mult_x_23_U205 ( .A(mult_x_23_n325), .B(mult_x_23_n228), .C(
mult_x_23_n233), .D(mult_x_23_n226), .ICI(mult_x_23_n229), .S(
mult_x_23_n223), .ICO(mult_x_23_n221), .CO(mult_x_23_n222) );
XOR2X1TS U405 ( .A(n861), .B(n860), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N17) );
BUFX3TS U406 ( .A(n2305), .Y(n2088) );
BUFX3TS U407 ( .A(n2305), .Y(n2225) );
INVX2TS U408 ( .A(n2375), .Y(n2374) );
NAND2X1TS U409 ( .A(n933), .B(n937), .Y(n934) );
AOI21X2TS U410 ( .A0(n1377), .A1(n1371), .B0(n1370), .Y(n1376) );
BUFX3TS U411 ( .A(n2305), .Y(n2337) );
OAI21X1TS U412 ( .A0(n939), .A1(n938), .B0(n937), .Y(n940) );
INVX2TS U413 ( .A(n982), .Y(n1005) );
NOR2X6TS U414 ( .A(n1999), .B(n1998), .Y(n1935) );
OR3X1TS U415 ( .A(underflow_flag), .B(overflow_flag), .C(n2378), .Y(n2375)
);
NAND2X2TS U416 ( .A(n1933), .B(n1953), .Y(n2305) );
AOI21X1TS U417 ( .A0(n2150), .A1(n2107), .B0(n2106), .Y(n2126) );
NAND2XLTS U418 ( .A(n1946), .B(FS_Module_state_reg[1]), .Y(n1933) );
NOR2X2TS U419 ( .A(n2390), .B(FS_Module_state_reg[1]), .Y(n2265) );
INVX2TS U420 ( .A(n2372), .Y(n2378) );
NAND2X2TS U421 ( .A(n1371), .B(n789), .Y(n790) );
OAI21X1TS U422 ( .A0(n1182), .A1(n1184), .B0(n1185), .Y(n841) );
NAND2X1TS U423 ( .A(DP_OP_111J22_123_4462_n285), .B(
DP_OP_111J22_123_4462_n292), .Y(n858) );
NAND2X2TS U424 ( .A(DP_OP_111J22_123_4462_n279), .B(
DP_OP_111J22_123_4462_n284), .Y(n922) );
NAND2X2TS U425 ( .A(DP_OP_111J22_123_4462_n293), .B(
DP_OP_111J22_123_4462_n299), .Y(n1373) );
NOR2X2TS U426 ( .A(DP_OP_111J22_123_4462_n279), .B(
DP_OP_111J22_123_4462_n284), .Y(n883) );
NAND2X1TS U427 ( .A(n984), .B(n642), .Y(n644) );
INVX2TS U428 ( .A(n1949), .Y(n2128) );
NAND2X2TS U429 ( .A(n899), .B(n563), .Y(n1570) );
CLKBUFX2TS U430 ( .A(n2370), .Y(n2372) );
OR2X2TS U431 ( .A(DP_OP_111J22_123_4462_n271), .B(DP_OP_111J22_123_4462_n267), .Y(n563) );
NOR2X2TS U432 ( .A(DP_OP_111J22_123_4462_n327), .B(
DP_OP_111J22_123_4462_n334), .Y(n1536) );
NOR2X4TS U433 ( .A(DP_OP_111J22_123_4462_n319), .B(
DP_OP_111J22_123_4462_n326), .Y(n1382) );
NOR2X1TS U434 ( .A(n1007), .B(n1106), .Y(n640) );
OAI21X2TS U435 ( .A0(n1222), .A1(n1227), .B0(n1223), .Y(n1208) );
OAI21X1TS U436 ( .A0(n985), .A1(n991), .B0(n986), .Y(n641) );
NAND2X1TS U437 ( .A(mult_x_23_n204), .B(mult_x_23_n213), .Y(n1223) );
NAND2X1TS U438 ( .A(mult_x_55_n216), .B(mult_x_55_n224), .Y(n1002) );
NOR2X2TS U439 ( .A(mult_x_23_n204), .B(mult_x_23_n213), .Y(n1222) );
NOR2X2TS U440 ( .A(mult_x_55_n206), .B(mult_x_55_n215), .Y(n997) );
NOR2X1TS U441 ( .A(n2385), .B(n2390), .Y(n1957) );
NOR2X2TS U442 ( .A(mult_x_23_n188), .B(mult_x_23_n195), .Y(n1210) );
NOR2X1TS U443 ( .A(n1967), .B(n2395), .Y(n1946) );
OAI21X2TS U444 ( .A0(n1035), .A1(n1032), .B0(n1033), .Y(n1021) );
OR2X2TS U445 ( .A(DP_OP_111J22_123_4462_n365), .B(DP_OP_111J22_123_4462_n361), .Y(n406) );
CMPR32X2TS U446 ( .A(n1604), .B(n1603), .C(n1602), .CO(
DP_OP_111J22_123_4462_n304), .S(DP_OP_111J22_123_4462_n305) );
CMPR32X2TS U447 ( .A(n1568), .B(n1567), .C(n1566), .CO(
DP_OP_111J22_123_4462_n268), .S(DP_OP_111J22_123_4462_n269) );
CMPR32X2TS U448 ( .A(n552), .B(n1282), .C(n1281), .CO(mult_x_23_n227), .S(
mult_x_23_n228) );
NAND2X1TS U449 ( .A(n773), .B(n772), .Y(n1411) );
NAND2X2TS U450 ( .A(DP_OP_111J22_123_4462_n361), .B(
DP_OP_111J22_123_4462_n365), .Y(n1404) );
CMPR32X2TS U451 ( .A(n1561), .B(n1560), .C(n1559), .CO(
DP_OP_111J22_123_4462_n350), .S(DP_OP_111J22_123_4462_n351) );
CMPR32X2TS U452 ( .A(Op_MY[14]), .B(n588), .C(n1278), .CO(mult_x_23_n208),
.S(mult_x_23_n209) );
CMPR32X2TS U453 ( .A(n1621), .B(n1620), .C(n1619), .CO(n1622), .S(
DP_OP_111J22_123_4462_n332) );
INVX2TS U454 ( .A(n408), .Y(n457) );
NOR2X2TS U455 ( .A(n627), .B(n626), .Y(n1038) );
AOI21X1TS U456 ( .A0(n1270), .A1(n570), .B0(n805), .Y(n1267) );
ADDHXLTS U457 ( .A(n1355), .B(n1354), .CO(mult_x_23_n258), .S(mult_x_23_n259) );
INVX2TS U458 ( .A(n408), .Y(n456) );
ADDHX1TS U459 ( .A(n1626), .B(n1625), .CO(DP_OP_111J22_123_4462_n369), .S(
n775) );
NOR2X1TS U460 ( .A(n2134), .B(n2136), .Y(n2107) );
NOR2X1TS U461 ( .A(n2166), .B(n2168), .Y(n1859) );
XNOR2X1TS U462 ( .A(n1504), .B(n473), .Y(n1598) );
INVX4TS U463 ( .A(n417), .Y(n449) );
NAND2X1TS U464 ( .A(n1923), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[12]),
.Y(n2084) );
NOR2X1TS U465 ( .A(n2383), .B(FS_Module_state_reg[0]), .Y(n1932) );
NOR2X1TS U466 ( .A(n1856), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .Y(
n2166) );
INVX2TS U467 ( .A(n395), .Y(n512) );
INVX2TS U468 ( .A(n693), .Y(n502) );
AOI21X1TS U469 ( .A0(n895), .A1(n1449), .B0(n1448), .Y(n1454) );
INVX2TS U470 ( .A(n1534), .Y(n542) );
NAND2XLTS U471 ( .A(n1449), .B(n1447), .Y(n692) );
NAND2X4TS U472 ( .A(n1146), .B(n602), .Y(n1148) );
INVX4TS U473 ( .A(n482), .Y(n483) );
NAND2X4TS U474 ( .A(n1074), .B(n511), .Y(n1154) );
INVX4TS U475 ( .A(n1335), .Y(n532) );
AND2X2TS U476 ( .A(n882), .B(n881), .Y(n1611) );
AOI21X1TS U477 ( .A0(n1439), .A1(n765), .B0(n764), .Y(n770) );
NAND2X2TS U478 ( .A(n888), .B(n554), .Y(n897) );
XOR2X1TS U479 ( .A(Op_MY[4]), .B(n450), .Y(n602) );
INVX4TS U480 ( .A(n390), .Y(n485) );
INVX4TS U481 ( .A(n465), .Y(n466) );
INVX4TS U482 ( .A(n465), .Y(n467) );
CLKINVX6TS U483 ( .A(n390), .Y(n484) );
INVX2TS U484 ( .A(n395), .Y(n511) );
INVX4TS U485 ( .A(n477), .Y(n478) );
AOI21X1TS U486 ( .A0(n1725), .A1(n1731), .B0(n1734), .Y(n1730) );
AND2X2TS U487 ( .A(n754), .B(n741), .Y(n1556) );
INVX2TS U488 ( .A(n1614), .Y(n1608) );
CLKINVX6TS U489 ( .A(n410), .Y(n515) );
INVX2TS U490 ( .A(n757), .Y(n477) );
INVX4TS U491 ( .A(n584), .Y(n468) );
AND2X4TS U492 ( .A(n800), .B(n486), .Y(n1335) );
NAND2X1TS U493 ( .A(n1902), .B(n1901), .Y(n1905) );
BUFX3TS U494 ( .A(Op_MY[1]), .Y(n1093) );
INVX2TS U495 ( .A(n1759), .Y(n1755) );
NAND2XLTS U496 ( .A(n704), .B(n703), .Y(n705) );
NAND2X1TS U497 ( .A(n1433), .B(n1432), .Y(n1434) );
INVX2TS U498 ( .A(n421), .Y(n505) );
NAND2X1TS U499 ( .A(Op_MY[15]), .B(Op_MY[3]), .Y(n729) );
NOR2X1TS U500 ( .A(Op_MX[1]), .B(Op_MX[13]), .Y(n707) );
INVX2TS U501 ( .A(n586), .Y(n435) );
NOR2X1TS U502 ( .A(n1801), .B(n1803), .Y(n1646) );
NOR2X2TS U503 ( .A(n1717), .B(n1719), .Y(n1701) );
NOR2X1TS U504 ( .A(n1656), .B(n1655), .Y(n1774) );
NOR2X2TS U505 ( .A(n1699), .B(n1698), .Y(n1719) );
NOR2X2TS U506 ( .A(n1697), .B(n1696), .Y(n1717) );
ADDFX2TS U507 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[10]), .B(n1681),
.CI(n1680), .CO(n1688), .S(n1687) );
NOR2X2TS U508 ( .A(Op_MY[15]), .B(Op_MY[3]), .Y(n728) );
INVX4TS U509 ( .A(n412), .Y(n473) );
NAND2X1TS U510 ( .A(n1909), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]),
.Y(n1911) );
CLKINVX3TS U511 ( .A(n477), .Y(n479) );
AO21X2TS U512 ( .A0(n542), .A1(n432), .B0(n465), .Y(n1595) );
NOR2XLTS U513 ( .A(n471), .B(n577), .Y(n1120) );
INVX2TS U514 ( .A(n1556), .Y(n544) );
OAI22X1TS U515 ( .A0(n544), .A1(n1485), .B0(n741), .B1(n758), .Y(n1626) );
ADDHXLTS U516 ( .A(n1358), .B(n1357), .CO(mult_x_23_n235), .S(mult_x_23_n236) );
CLKINVX3TS U517 ( .A(n1427), .Y(n491) );
INVX2TS U518 ( .A(n416), .Y(n481) );
NOR2XLTS U519 ( .A(DP_OP_111J22_123_4462_n727), .B(n569), .Y(n1170) );
INVX2TS U520 ( .A(n502), .Y(n504) );
INVX4TS U521 ( .A(n462), .Y(n463) );
NOR2XLTS U522 ( .A(n1988), .B(n2389), .Y(n1990) );
OAI21X1TS U523 ( .A0(n1246), .A1(n1252), .B0(n1247), .Y(n829) );
NOR2X4TS U524 ( .A(DP_OP_111J22_123_4462_n300), .B(
DP_OP_111J22_123_4462_n309), .Y(n864) );
NOR2X6TS U525 ( .A(n2057), .B(n1928), .Y(n2048) );
CMPR42X1TS U526 ( .A(mult_x_23_n298), .B(mult_x_23_n334), .C(mult_x_23_n206),
.D(mult_x_23_n199), .ICI(mult_x_23_n202), .S(mult_x_23_n196), .ICO(
mult_x_23_n194), .CO(mult_x_23_n195) );
NAND2X1TS U527 ( .A(n1949), .B(n1994), .Y(n1947) );
OR2X1TS U528 ( .A(DP_OP_111J22_123_4462_n366), .B(n777), .Y(n597) );
OR2X1TS U529 ( .A(n823), .B(n822), .Y(n582) );
OAI21XLTS U530 ( .A0(n2258), .A1(n2254), .B0(n2255), .Y(n2246) );
OAI21XLTS U531 ( .A0(n2082), .A1(n2095), .B0(n2096), .Y(n2087) );
OR2X2TS U532 ( .A(DP_OP_111J22_123_4462_n343), .B(DP_OP_111J22_123_4462_n348), .Y(n405) );
BUFX3TS U533 ( .A(n1954), .Y(n527) );
OR2X1TS U534 ( .A(mult_x_55_n176), .B(mult_x_55_n172), .Y(n969) );
OR2X1TS U535 ( .A(mult_x_55_n247), .B(mult_x_55_n253), .Y(n580) );
OR2X1TS U536 ( .A(n909), .B(n908), .Y(n1575) );
CLKINVX3TS U537 ( .A(n392), .Y(n440) );
OAI21XLTS U538 ( .A0(n1255), .A1(n1251), .B0(n1252), .Y(n1250) );
INVX4TS U539 ( .A(n1181), .Y(n1206) );
CLKINVX3TS U540 ( .A(n561), .Y(n554) );
OAI21XLTS U541 ( .A0(n2383), .A1(n2266), .B0(FS_Module_state_reg[3]), .Y(
n1966) );
INVX2TS U542 ( .A(n2375), .Y(n2377) );
AND2X2TS U543 ( .A(n1956), .B(n1957), .Y(n2370) );
NAND2X1TS U544 ( .A(n1981), .B(n1957), .Y(n2368) );
OAI211XLTS U545 ( .A0(n2398), .A1(n2339), .B0(n2128), .C0(n1966), .Y(n379)
);
CLKXOR2X2TS U546 ( .A(n1428), .B(n1426), .Y(n390) );
CLKBUFX2TS U547 ( .A(Op_MX[19]), .Y(n1351) );
INVX2TS U548 ( .A(n419), .Y(n507) );
CLKXOR2X2TS U549 ( .A(Op_MX[21]), .B(Op_MX[22]), .Y(n416) );
INVX2TS U550 ( .A(Op_MY[11]), .Y(n471) );
CLKXOR2X2TS U551 ( .A(Op_MY[6]), .B(Op_MY[5]), .Y(n395) );
CLKMX2X2TS U552 ( .A(P_Sgf[44]), .B(n1941), .S0(n2088), .Y(n259) );
XOR2X1TS U553 ( .A(n1376), .B(n1375), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N16) );
INVX2TS U554 ( .A(n1570), .Y(n901) );
XOR2X1TS U555 ( .A(n994), .B(n993), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N15) );
CLKMX2X2TS U556 ( .A(n1992), .B(Add_result[23]), .S0(n2240), .Y(n283) );
NAND2X1TS U557 ( .A(n563), .B(n919), .Y(n920) );
CLKMX2X2TS U558 ( .A(P_Sgf[19]), .B(n2310), .S0(n2326), .Y(n234) );
CLKMX2X2TS U559 ( .A(P_Sgf[17]), .B(n2277), .S0(n2340), .Y(n232) );
INVX2TS U560 ( .A(n2220), .Y(n2222) );
CLKMX2X2TS U561 ( .A(P_Sgf[16]), .B(n2287), .S0(n2340), .Y(n231) );
OAI21X1TS U562 ( .A0(n1210), .A1(n1216), .B0(n1211), .Y(n836) );
OR2X2TS U563 ( .A(n1589), .B(n1588), .Y(n1591) );
CLKMX2X2TS U564 ( .A(n2045), .B(Add_result[16]), .S0(n2261), .Y(n290) );
AO21X1TS U565 ( .A0(n544), .A1(n519), .B0(n1485), .Y(
DP_OP_111J22_123_4462_n436) );
CLKMX2X2TS U566 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(
n2338), .Y(n276) );
CLKMX2X2TS U567 ( .A(n2056), .B(Add_result[15]), .S0(n2035), .Y(n291) );
CLKMX2X2TS U568 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(
n2338), .Y(n277) );
CLKMX2X2TS U569 ( .A(n2070), .B(Add_result[14]), .S0(n2261), .Y(n292) );
OR2X2TS U570 ( .A(n658), .B(n657), .Y(n660) );
AO21X1TS U571 ( .A0(n464), .A1(n504), .B0(n1542), .Y(n1586) );
NAND2BX1TS U572 ( .AN(n1608), .B(n483), .Y(n1549) );
MX2X1TS U573 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n2338),
.Y(n279) );
CLKMX2X2TS U574 ( .A(n2081), .B(Add_result[13]), .S0(n2261), .Y(n293) );
MX2X1TS U575 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n2338),
.Y(n280) );
AO21X1TS U576 ( .A0(Sgf_normalized_result[23]), .A1(n2128), .B0(n1995), .Y(
n307) );
OAI31XLTS U577 ( .A0(FS_Module_state_reg[0]), .A1(FS_Module_state_reg[2]),
.A2(n2385), .B0(n1971), .Y(n377) );
OR2X2TS U578 ( .A(n715), .B(n714), .Y(n571) );
OR2X2TS U579 ( .A(n804), .B(n803), .Y(n570) );
AO21X1TS U580 ( .A0(n541), .A1(n493), .B0(n584), .Y(mult_x_55_n300) );
INVX4TS U581 ( .A(n1983), .Y(n1982) );
INVX2TS U582 ( .A(n1760), .Y(n1762) );
INVX4TS U583 ( .A(n2044), .Y(n2261) );
AOI211X1TS U584 ( .A0(FSM_selector_B[0]), .A1(n1960), .B0(n2044), .C0(n2344),
.Y(n2423) );
INVX4TS U585 ( .A(n690), .Y(n1439) );
AND2X4TS U586 ( .A(n480), .B(n568), .Y(n417) );
INVX2TS U587 ( .A(n1803), .Y(n1805) );
BUFX3TS U588 ( .A(n1146), .Y(n470) );
INVX1TS U589 ( .A(n1953), .Y(n1945) );
INVX4TS U590 ( .A(n416), .Y(n480) );
OR2X2TS U591 ( .A(n1638), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n1641) );
INVX2TS U592 ( .A(n1440), .Y(n1442) );
OAI21X1TS U593 ( .A0(FSM_selector_B[0]), .A1(n1979), .B0(n567), .Y(n1980) );
NAND2BX1TS U594 ( .AN(n1152), .B(n450), .Y(n604) );
NAND2BX1TS U595 ( .AN(n1362), .B(n521), .Y(n1363) );
INVX4TS U596 ( .A(n471), .Y(n472) );
NAND2BX1TS U597 ( .AN(n1152), .B(Op_MY[7]), .Y(n1153) );
CLKMX2X2TS U598 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
CLKMX2X2TS U599 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
CLKMX2X2TS U600 ( .A(Op_MX[29]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
INVX4TS U601 ( .A(n419), .Y(n508) );
CLKMX2X2TS U602 ( .A(Op_MX[30]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
MX2X2TS U603 ( .A(P_Sgf[47]), .B(n1938), .S0(n2340), .Y(n380) );
NAND2X4TS U604 ( .A(n1935), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[22]),
.Y(n1937) );
CLKMX2X2TS U605 ( .A(P_Sgf[43]), .B(n2014), .S0(n2088), .Y(n258) );
CLKMX2X2TS U606 ( .A(P_Sgf[42]), .B(n2022), .S0(n2088), .Y(n257) );
CLKMX2X2TS U607 ( .A(P_Sgf[41]), .B(n2030), .S0(n2088), .Y(n256) );
CLKMX2X2TS U608 ( .A(P_Sgf[40]), .B(n2039), .S0(n2088), .Y(n255) );
CLKMX2X2TS U609 ( .A(P_Sgf[39]), .B(n2051), .S0(n2088), .Y(n254) );
CLKMX2X2TS U610 ( .A(P_Sgf[37]), .B(n2076), .S0(n2088), .Y(n252) );
CLKMX2X2TS U611 ( .A(P_Sgf[35]), .B(n2100), .S0(n2225), .Y(n250) );
XOR2X1TS U612 ( .A(n1392), .B(n1391), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N11) );
XOR2X1TS U613 ( .A(n1540), .B(n1539), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N12) );
CLKMX2X2TS U614 ( .A(P_Sgf[33]), .B(n2127), .S0(n2225), .Y(n248) );
CLKMX2X2TS U615 ( .A(P_Sgf[32]), .B(n2141), .S0(n2225), .Y(n247) );
CLKMX2X2TS U616 ( .A(P_Sgf[31]), .B(n2151), .S0(n2225), .Y(n246) );
INVX3TS U617 ( .A(n2082), .Y(n2099) );
XOR2X2TS U618 ( .A(n662), .B(n661), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N23) );
XOR2X2TS U619 ( .A(n851), .B(n850), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N23) );
CLKMX2X2TS U620 ( .A(P_Sgf[29]), .B(n2183), .S0(n2225), .Y(n244) );
INVX6TS U621 ( .A(n2046), .Y(n2150) );
CLKMX2X2TS U622 ( .A(n2262), .B(FSM_add_overflow_flag), .S0(n2261), .Y(n282)
);
XOR2X1TS U623 ( .A(n955), .B(n954), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N21) );
CLKMX2X2TS U624 ( .A(P_Sgf[28]), .B(n2197), .S0(n2225), .Y(n243) );
XOR2X1TS U625 ( .A(n1219), .B(n1218), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N15) );
CLKMX2X2TS U626 ( .A(P_Sgf[27]), .B(n2207), .S0(n2225), .Y(n242) );
XOR2X1TS U627 ( .A(n1226), .B(n1225), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N14) );
OAI21X1TS U628 ( .A0(n994), .A1(n990), .B0(n991), .Y(n989) );
CLKMX2X2TS U629 ( .A(P_Sgf[26]), .B(n2226), .S0(n2225), .Y(n241) );
XOR2X1TS U630 ( .A(n1403), .B(n1402), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N8) );
XOR2X1TS U631 ( .A(n1001), .B(n1000), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N14) );
XOR2X1TS U632 ( .A(n1180), .B(n1179), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N21) );
CLKMX2X2TS U633 ( .A(P_Sgf[22]), .B(n2325), .S0(n2326), .Y(n237) );
CLKMX2X2TS U634 ( .A(P_Sgf[24]), .B(n2247), .S0(n2340), .Y(n239) );
CLKMX2X2TS U635 ( .A(n1997), .B(Add_result[22]), .S0(n2035), .Y(n284) );
CLKMX2X2TS U636 ( .A(P_Sgf[25]), .B(n2236), .S0(n2340), .Y(n240) );
INVX6TS U637 ( .A(n956), .Y(n981) );
NOR2X2TS U638 ( .A(n1382), .B(n1536), .Y(n788) );
CLKMX2X2TS U639 ( .A(P_Sgf[20]), .B(n2296), .S0(n2340), .Y(n235) );
OAI21X2TS U640 ( .A0(n1382), .A1(n1537), .B0(n1383), .Y(n787) );
NOR2X4TS U641 ( .A(n883), .B(n925), .Y(n1571) );
XOR2X1TS U642 ( .A(n1110), .B(n1109), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N11) );
CLKMX2X2TS U643 ( .A(n2005), .B(Add_result[21]), .S0(n2261), .Y(n285) );
CLKMX2X2TS U644 ( .A(P_Sgf[23]), .B(n2259), .S0(n2340), .Y(n238) );
XOR2X1TS U645 ( .A(n1241), .B(n1240), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N10) );
OAI21X1TS U646 ( .A0(n1110), .A1(n1106), .B0(n1107), .Y(n1011) );
CLKMX2X2TS U647 ( .A(P_Sgf[21]), .B(n2316), .S0(n2326), .Y(n236) );
OAI21X2TS U648 ( .A0(n857), .A1(n1373), .B0(n858), .Y(n694) );
NAND2X1TS U649 ( .A(n944), .B(n943), .Y(n945) );
XOR2X1TS U650 ( .A(n1329), .B(n1328), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N11) );
CLKMX2X2TS U651 ( .A(P_Sgf[18]), .B(n2306), .S0(n2326), .Y(n233) );
XOR2X1TS U652 ( .A(n1017), .B(n1016), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N10) );
OAI21X1TS U653 ( .A0(n2319), .A1(n2318), .B0(n2317), .Y(n2324) );
NOR2X4TS U654 ( .A(DP_OP_111J22_123_4462_n285), .B(
DP_OP_111J22_123_4462_n292), .Y(n857) );
CLKMX2X2TS U655 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(
n2338), .Y(n281) );
CLKMX2X2TS U656 ( .A(n2011), .B(Add_result[20]), .S0(n2035), .Y(n286) );
NOR2X4TS U657 ( .A(DP_OP_111J22_123_4462_n278), .B(
DP_OP_111J22_123_4462_n272), .Y(n925) );
CLKMX2X2TS U658 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(
n2338), .Y(n273) );
CLKMX2X2TS U659 ( .A(n2019), .B(Add_result[19]), .S0(n2261), .Y(n287) );
XOR2X1TS U660 ( .A(n1255), .B(n1254), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N7) );
NAND3BX1TS U661 ( .AN(Exp_module_Data_S[7]), .B(n2344), .C(n2343), .Y(n2345)
);
OR2X2TS U662 ( .A(DP_OP_111J22_123_4462_n349), .B(DP_OP_111J22_123_4462_n355), .Y(n782) );
INVX2TS U663 ( .A(n1190), .Y(n1191) );
CLKMX2X2TS U664 ( .A(n2027), .B(Add_result[18]), .S0(n2035), .Y(n288) );
OAI21X1TS U665 ( .A0(n2299), .A1(n2298), .B0(n2297), .Y(n2304) );
XOR2X1TS U666 ( .A(n1031), .B(n1030), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N7) );
NAND4BX1TS U667 ( .AN(n2342), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n2343) );
CLKMX2X2TS U668 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(
n2338), .Y(n274) );
CLKMX2X2TS U669 ( .A(n2036), .B(Add_result[17]), .S0(n2261), .Y(n289) );
XOR2X1TS U670 ( .A(n1260), .B(n1259), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N6) );
CLKMX2X2TS U671 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(
n2338), .Y(n275) );
NAND2X2TS U672 ( .A(mult_x_23_n196), .B(mult_x_23_n203), .Y(n1216) );
OR2X2TS U673 ( .A(n749), .B(n748), .Y(n598) );
OAI21X1TS U674 ( .A0(n1047), .A1(n1043), .B0(n1044), .Y(n1042) );
XOR2X1TS U675 ( .A(n1047), .B(n1046), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N4) );
XOR2X2TS U676 ( .A(n1730), .B(n1729), .Y(n1856) );
OR2X2TS U677 ( .A(mult_x_23_n174), .B(mult_x_23_n170), .Y(n1194) );
XOR2X1TS U678 ( .A(n1052), .B(n1051), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N3) );
OR2X2TS U679 ( .A(mult_x_23_n245), .B(mult_x_23_n251), .Y(n594) );
OR2X2TS U680 ( .A(mult_x_23_n161), .B(n843), .Y(n1173) );
OR2X1TS U681 ( .A(n847), .B(n846), .Y(n849) );
OR2X2TS U682 ( .A(mult_x_23_n239), .B(mult_x_23_n244), .Y(n595) );
OR2X2TS U683 ( .A(mult_x_55_n163), .B(n650), .Y(n948) );
NAND2BX1TS U684 ( .AN(n1608), .B(n479), .Y(n758) );
AO21X1TS U685 ( .A0(n549), .A1(n425), .B0(n1550), .Y(
DP_OP_111J22_123_4462_n407) );
OAI21X1TS U686 ( .A0(FS_Module_state_reg[1]), .A1(n2263), .B0(n1964), .Y(
n376) );
NAND2BX1TS U687 ( .AN(n1608), .B(n467), .Y(n723) );
OR2X2TS U688 ( .A(n1809), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .Y(
n1808) );
XOR2X1TS U689 ( .A(n1275), .B(n1323), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N2) );
NAND2BX1TS U690 ( .AN(n1608), .B(n485), .Y(n1530) );
AO22X1TS U691 ( .A0(Sgf_normalized_result[8]), .A1(n2374), .B0(
final_result_ieee[8]), .B1(n2373), .Y(n182) );
NOR2X4TS U692 ( .A(n2337), .B(n2344), .Y(n2338) );
AO21X1TS U693 ( .A0(n539), .A1(n512), .B0(n413), .Y(mult_x_55_n314) );
AO22X1TS U694 ( .A0(Sgf_normalized_result[4]), .A1(n2374), .B0(
final_result_ieee[4]), .B1(n2373), .Y(n186) );
AO22X1TS U695 ( .A0(Sgf_normalized_result[5]), .A1(n2374), .B0(
final_result_ieee[5]), .B1(n2373), .Y(n185) );
AO22X1TS U696 ( .A0(Sgf_normalized_result[6]), .A1(n2374), .B0(
final_result_ieee[6]), .B1(n2373), .Y(n184) );
AO22X1TS U697 ( .A0(Sgf_normalized_result[7]), .A1(n2374), .B0(
final_result_ieee[7]), .B1(n2373), .Y(n183) );
OAI22X2TS U698 ( .A0(n449), .A1(n440), .B0(n481), .B1(n398), .Y(n1278) );
AO22X1TS U699 ( .A0(n1983), .A1(Data_MX[31]), .B0(n2369), .B1(Op_MX[31]),
.Y(n343) );
OAI21X1TS U700 ( .A0(Sgf_normalized_result[0]), .A1(n2240), .B0(n1959), .Y(
n306) );
OAI21X2TS U701 ( .A0(n1711), .A1(n1703), .B0(n1702), .Y(n1704) );
AO22X1TS U702 ( .A0(n1983), .A1(Data_MY[31]), .B0(n2369), .B1(Op_MY[31]),
.Y(n310) );
OR2X2TS U703 ( .A(FSM_selector_C), .B(n1947), .Y(n422) );
AO21X1TS U704 ( .A0(n534), .A1(n492), .B0(n420), .Y(mult_x_23_n306) );
AO21X1TS U705 ( .A0(n532), .A1(n487), .B0(n421), .Y(mult_x_23_n334) );
NOR2X4TS U706 ( .A(n1994), .B(n2391), .Y(n2006) );
INVX2TS U707 ( .A(n1983), .Y(n2369) );
OR2X2TS U708 ( .A(n1994), .B(FSM_selector_C), .Y(n2250) );
NAND2X2TS U709 ( .A(n1713), .B(n1701), .Y(n1703) );
AO21X1TS U710 ( .A0(n536), .A1(n496), .B0(n1364), .Y(mult_x_23_n292) );
AO21X1TS U711 ( .A0(n1345), .A1(n489), .B0(n419), .Y(mult_x_23_n320) );
INVX2TS U712 ( .A(n1776), .Y(n1778) );
OAI21X2TS U713 ( .A0(n1760), .A1(n1756), .B0(n1761), .Y(n1714) );
INVX2TS U714 ( .A(n1823), .Y(n1825) );
INVX2TS U715 ( .A(n1821), .Y(n1772) );
INVX2TS U716 ( .A(n1748), .Y(n1750) );
INVX2TS U717 ( .A(n1831), .Y(n1833) );
NAND2BX1TS U718 ( .AN(n1362), .B(n514), .Y(n1352) );
NAND3X1TS U719 ( .A(n1632), .B(n1631), .C(n1630), .Y(n1634) );
AND2X2TS U720 ( .A(n1944), .B(FS_Module_state_reg[1]), .Y(n1949) );
OR2X2TS U721 ( .A(n1878), .B(n1877), .Y(n1882) );
INVX1TS U722 ( .A(n1967), .Y(n1970) );
NAND2BX1TS U723 ( .AN(n1152), .B(n472), .Y(n1057) );
NOR2X1TS U724 ( .A(n2211), .B(Sgf_normalized_result[2]), .Y(n2212) );
OR2X2TS U725 ( .A(n1894), .B(n1893), .Y(n1898) );
NOR2X2TS U726 ( .A(n1687), .B(n1686), .Y(n1746) );
OR2X2TS U727 ( .A(n1909), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[24]),
.Y(n1913) );
AND2X4TS U728 ( .A(n2265), .B(n1981), .Y(n1983) );
AND2X4TS U729 ( .A(n1284), .B(n495), .Y(n1365) );
OR2X2TS U730 ( .A(n1728), .B(n1727), .Y(n583) );
NAND2X2TS U731 ( .A(n1981), .B(n1942), .Y(n1955) );
NAND3X1TS U732 ( .A(n2265), .B(P_Sgf[47]), .C(n1958), .Y(n1960) );
OR2X2TS U733 ( .A(n1740), .B(n1739), .Y(n1866) );
AND2X2TS U734 ( .A(n2265), .B(n1956), .Y(n2044) );
INVX4TS U735 ( .A(n411), .Y(n493) );
NAND2BX1TS U736 ( .AN(n1152), .B(n469), .Y(n614) );
NAND2X2TS U737 ( .A(n681), .B(n680), .Y(n871) );
OR2X2TS U738 ( .A(n1708), .B(n1707), .Y(n1731) );
NOR2X4TS U739 ( .A(n1953), .B(FS_Module_state_reg[1]), .Y(n1954) );
NAND2BX1TS U740 ( .AN(n1362), .B(n452), .Y(n796) );
NOR2X1TS U741 ( .A(n1988), .B(n2156), .Y(n1989) );
OAI21X2TS U742 ( .A0(n702), .A1(n706), .B0(n703), .Y(n695) );
INVX1TS U743 ( .A(n2263), .Y(n1958) );
NAND2BX1TS U744 ( .AN(n552), .B(n506), .Y(n802) );
NAND2BX1TS U745 ( .AN(n1362), .B(n508), .Y(n818) );
XOR2X2TS U746 ( .A(Op_MY[8]), .B(n509), .Y(n411) );
OR2X2TS U747 ( .A(Op_MY[12]), .B(Op_MY[0]), .Y(n587) );
AND2X2TS U748 ( .A(Op_MX[0]), .B(Op_MX[12]), .Y(n698) );
OR2X2TS U749 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
XOR2X1TS U750 ( .A(n929), .B(n928), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N19) );
AOI21X4TS U751 ( .A0(n1583), .A1(n924), .B0(n923), .Y(n929) );
XNOR2X2TS U752 ( .A(n1883), .B(n1879), .Y(n1917) );
XOR2X4TS U753 ( .A(n911), .B(n910), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N24) );
CMPR42X2TS U754 ( .A(DP_OP_111J22_123_4462_n297), .B(
DP_OP_111J22_123_4462_n412), .C(DP_OP_111J22_123_4462_n400), .D(
DP_OP_111J22_123_4462_n304), .ICI(DP_OP_111J22_123_4462_n301), .S(
DP_OP_111J22_123_4462_n296), .ICO(DP_OP_111J22_123_4462_n294), .CO(
DP_OP_111J22_123_4462_n295) );
NOR2X4TS U755 ( .A(DP_OP_111J22_123_4462_n293), .B(
DP_OP_111J22_123_4462_n299), .Y(n1372) );
AOI21X2TS U756 ( .A0(n635), .A1(n1021), .B0(n634), .Y(n1012) );
XOR2X4TS U757 ( .A(n918), .B(n917), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N23) );
AOI21X4TS U758 ( .A0(n1390), .A1(n1388), .B0(n784), .Y(n785) );
CMPR42X2TS U759 ( .A(DP_OP_111J22_123_4462_n336), .B(
DP_OP_111J22_123_4462_n468), .C(DP_OP_111J22_123_4462_n337), .D(
DP_OP_111J22_123_4462_n333), .ICI(DP_OP_111J22_123_4462_n330), .S(
DP_OP_111J22_123_4462_n327), .ICO(DP_OP_111J22_123_4462_n325), .CO(
DP_OP_111J22_123_4462_n326) );
NAND2X6TS U760 ( .A(n1294), .B(n491), .Y(n1353) );
OAI21X1TS U761 ( .A0(n1219), .A1(n1215), .B0(n1216), .Y(n1214) );
NAND2X6TS U762 ( .A(n2062), .B(n1926), .Y(n1928) );
NOR2X6TS U763 ( .A(n2071), .B(n2063), .Y(n1926) );
ADDFX2TS U764 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[8]), .B(n1675),
.CI(n1674), .CO(n1684), .S(n1683) );
OR2X2TS U765 ( .A(n1810), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .Y(
n560) );
CMPR42X2TS U766 ( .A(DP_OP_111J22_123_4462_n315), .B(
DP_OP_111J22_123_4462_n427), .C(DP_OP_111J22_123_4462_n414), .D(
DP_OP_111J22_123_4462_n323), .ICI(DP_OP_111J22_123_4462_n320), .S(
DP_OP_111J22_123_4462_n313), .ICO(DP_OP_111J22_123_4462_n311), .CO(
DP_OP_111J22_123_4462_n312) );
NAND2X2TS U767 ( .A(n1916), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(
n2147) );
OAI21X2TS U768 ( .A0(n2291), .A1(n2307), .B0(n2292), .Y(n2311) );
NOR2X2TS U769 ( .A(n977), .B(n972), .Y(n964) );
AOI21X2TS U770 ( .A0(n1377), .A1(n856), .B0(n855), .Y(n861) );
CMPR42X2TS U771 ( .A(DP_OP_111J22_123_4462_n445), .B(
DP_OP_111J22_123_4462_n458), .C(DP_OP_111J22_123_4462_n351), .D(
DP_OP_111J22_123_4462_n471), .ICI(DP_OP_111J22_123_4462_n354), .S(
DP_OP_111J22_123_4462_n349), .ICO(DP_OP_111J22_123_4462_n347), .CO(
DP_OP_111J22_123_4462_n348) );
OAI21X4TS U772 ( .A0(n922), .A1(n925), .B0(n926), .Y(n1582) );
OAI21X2TS U773 ( .A0(n1579), .A1(n1578), .B0(n1577), .Y(n1580) );
NOR2X4TS U774 ( .A(n938), .B(n942), .Y(n899) );
AOI21X2TS U775 ( .A0(n983), .A1(n642), .B0(n641), .Y(n643) );
OAI21X2TS U776 ( .A0(n997), .A1(n1002), .B0(n998), .Y(n983) );
XNOR2X4TS U777 ( .A(n1914), .B(n1910), .Y(n1923) );
CMPR42X2TS U778 ( .A(mult_x_55_n337), .B(mult_x_55_n361), .C(mult_x_55_n260),
.D(mult_x_55_n257), .ICI(mult_x_55_n256), .S(mult_x_55_n254), .ICO(
mult_x_55_n252), .CO(mult_x_55_n253) );
OAI21X2TS U779 ( .A0(n2075), .A1(n2071), .B0(n2072), .Y(n2064) );
OAI21X2TS U780 ( .A0(n1022), .A1(n1028), .B0(n1023), .Y(n634) );
OAI21X4TS U781 ( .A0(n1207), .A1(n839), .B0(n838), .Y(n1181) );
OAI21X2TS U782 ( .A0(n1272), .A1(n1323), .B0(n1273), .Y(n1270) );
AND2X4TS U783 ( .A(n1070), .B(n493), .Y(n1168) );
XOR2X2TS U784 ( .A(n868), .B(n867), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N15) );
NAND2X2TS U785 ( .A(DP_OP_111J22_123_4462_n349), .B(
DP_OP_111J22_123_4462_n355), .Y(n1396) );
XNOR2X2TS U786 ( .A(n752), .B(n736), .Y(n740) );
NOR2X8TS U787 ( .A(n2029), .B(n2028), .Y(n2021) );
NAND2X6TS U788 ( .A(n2038), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[16]),
.Y(n2029) );
NAND2X4TS U789 ( .A(n2048), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[15]),
.Y(n1930) );
NAND2X4TS U790 ( .A(n2047), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[15]),
.Y(n1929) );
XNOR2X2TS U791 ( .A(n1899), .B(n1895), .Y(n1919) );
NAND2X2TS U792 ( .A(n873), .B(n871), .Y(n682) );
XNOR2X4TS U793 ( .A(n873), .B(n871), .Y(n872) );
NOR2X2TS U794 ( .A(n936), .B(n938), .Y(n941) );
OAI21X1TS U795 ( .A0(n1540), .A1(n1536), .B0(n1537), .Y(n1386) );
AOI21X2TS U796 ( .A0(n1582), .A1(n563), .B0(n930), .Y(n939) );
OAI21X4TS U797 ( .A0(n781), .A1(n1399), .B0(n780), .Y(n1398) );
MX2X1TS U798 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U799 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
XOR2X1TS U800 ( .A(Op_MY[8]), .B(n468), .Y(n1070) );
NOR2X1TS U801 ( .A(n471), .B(n394), .Y(mult_x_55_n194) );
NOR2X1TS U802 ( .A(n1840), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[19]),
.Y(n2289) );
OAI21X1TS U803 ( .A0(n2230), .A1(n2387), .B0(n1987), .Y(n2155) );
BUFX3TS U804 ( .A(n1095), .Y(n1163) );
AOI21X2TS U805 ( .A0(n830), .A1(n1245), .B0(n829), .Y(n1237) );
MX2X1TS U806 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
NOR2X1TS U807 ( .A(DP_OP_111J22_123_4462_n727), .B(n393), .Y(n1171) );
OAI22X1TS U808 ( .A0(n1464), .A1(n463), .B0(n1462), .B1(n503), .Y(
DP_OP_111J22_123_4462_n398) );
AND2X2TS U809 ( .A(n719), .B(n402), .Y(n1534) );
AO21XLTS U810 ( .A0(n1140), .A1(n429), .B0(n415), .Y(mult_x_55_n342) );
NOR2X2TS U811 ( .A(n1440), .B(n686), .Y(n688) );
AO21X1TS U812 ( .A0(n546), .A1(n516), .B0(n1562), .Y(n1568) );
NOR2X1TS U813 ( .A(n1850), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .Y(
n2218) );
NOR2X1TS U814 ( .A(n1916), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(
n2134) );
AOI21X1TS U815 ( .A0(n1990), .A1(n2155), .B0(n1989), .Y(n2118) );
INVX2TS U816 ( .A(n1781), .Y(n1783) );
NAND2X1TS U817 ( .A(n2312), .B(n1845), .Y(n1847) );
NOR2X1TS U818 ( .A(n2318), .B(n2320), .Y(n1845) );
CMPR42X1TS U819 ( .A(mult_x_55_n291), .B(mult_x_55_n185), .C(mult_x_55_n179),
.D(mult_x_55_n186), .ICI(mult_x_55_n182), .S(mult_x_55_n177), .ICO(
mult_x_55_n175), .CO(mult_x_55_n176) );
NOR2X1TS U820 ( .A(mult_x_55_n216), .B(mult_x_55_n224), .Y(n995) );
CMPR42X1TS U821 ( .A(mult_x_23_n319), .B(mult_x_23_n355), .C(mult_x_23_n343),
.D(mult_x_23_n331), .ICI(mult_x_23_n265), .S(mult_x_23_n262), .ICO(
mult_x_23_n260), .CO(mult_x_23_n261) );
INVX2TS U822 ( .A(n2155), .Y(n2201) );
INVX2TS U823 ( .A(n2118), .Y(n2145) );
INVX2TS U824 ( .A(n2320), .Y(n2322) );
NAND4XLTS U825 ( .A(n2349), .B(n2348), .C(n2347), .D(n2346), .Y(n2366) );
NAND4XLTS U826 ( .A(n2362), .B(n2361), .C(n2360), .D(n2359), .Y(n2363) );
NOR2X1TS U827 ( .A(n958), .B(n959), .Y(n647) );
NAND2X1TS U828 ( .A(n964), .B(n969), .Y(n958) );
OAI21X2TS U829 ( .A0(n978), .A1(n972), .B0(n973), .Y(n965) );
OR2X1TS U830 ( .A(n616), .B(n615), .Y(n1054) );
NOR2X2TS U831 ( .A(DP_OP_111J22_123_4462_n258), .B(n902), .Y(n916) );
NAND2X1TS U832 ( .A(DP_OP_111J22_123_4462_n258), .B(n902), .Y(n1572) );
AOI21X2TS U833 ( .A0(n1416), .A1(n598), .B0(n750), .Y(n1413) );
NAND4XLTS U834 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n2342) );
INVX2TS U835 ( .A(n413), .Y(n509) );
XOR2X1TS U836 ( .A(Op_MX[10]), .B(Op_MX[22]), .Y(n679) );
INVX2TS U837 ( .A(n569), .Y(n436) );
XOR2X1TS U838 ( .A(n525), .B(Op_MX[20]), .Y(n876) );
INVX2TS U839 ( .A(n575), .Y(n525) );
INVX2TS U840 ( .A(n897), .Y(n453) );
XOR2X1TS U841 ( .A(Op_MX[6]), .B(Op_MX[18]), .Y(n1431) );
NOR2X2TS U842 ( .A(Op_MY[17]), .B(Op_MY[5]), .Y(n766) );
XOR2X1TS U843 ( .A(Op_MX[4]), .B(Op_MX[16]), .Y(n752) );
XOR2X1TS U844 ( .A(Op_MX[2]), .B(Op_MX[14]), .Y(n717) );
AOI21X2TS U845 ( .A0(n1770), .A1(n1664), .B0(n1663), .Y(n1665) );
NOR2X1TS U846 ( .A(n1829), .B(n1831), .Y(n1742) );
NOR2X1TS U847 ( .A(n471), .B(n576), .Y(n1121) );
NAND2BXLTS U848 ( .AN(n1152), .B(Op_MY[9]), .Y(n1112) );
NOR2X1TS U849 ( .A(n869), .B(n1450), .Y(n884) );
NOR2X2TS U850 ( .A(n439), .B(Op_MY[7]), .Y(n686) );
NOR2X2TS U851 ( .A(Op_MY[18]), .B(Op_MY[6]), .Y(n1440) );
OAI21X1TS U852 ( .A0(n686), .A1(n1441), .B0(n685), .Y(n687) );
NAND2X1TS U853 ( .A(n730), .B(n729), .Y(n731) );
NAND2X1TS U854 ( .A(n721), .B(n720), .Y(n737) );
INVX2TS U855 ( .A(n1283), .Y(n495) );
NAND2X1TS U856 ( .A(n1656), .B(n1655), .Y(n1796) );
INVX2TS U857 ( .A(n1769), .Y(n1799) );
NAND2X1TS U858 ( .A(n1660), .B(n1659), .Y(n1820) );
INVX2TS U859 ( .A(n1717), .Y(n1766) );
INVX2TS U860 ( .A(n1714), .Y(n1715) );
AOI21X1TS U861 ( .A0(n2163), .A1(n1859), .B0(n1858), .Y(n1860) );
NAND2X1TS U862 ( .A(n1642), .B(n1641), .Y(n1800) );
NAND2X1TS U863 ( .A(n1683), .B(n1682), .Y(n1828) );
AO21XLTS U864 ( .A0(n1148), .A1(n470), .B0(n418), .Y(mult_x_55_n328) );
INVX2TS U865 ( .A(n395), .Y(n513) );
BUFX3TS U866 ( .A(n601), .Y(n1146) );
NAND2BXLTS U867 ( .AN(n550), .B(Op_MY[3]), .Y(n610) );
NAND2X4TS U868 ( .A(n600), .B(n599), .Y(n1140) );
NAND2X1TS U869 ( .A(Op_MY[22]), .B(Op_MY[10]), .Y(n890) );
INVX2TS U870 ( .A(n919), .Y(n930) );
CMPR42X1TS U871 ( .A(DP_OP_111J22_123_4462_n467), .B(
DP_OP_111J22_123_4462_n415), .C(DP_OP_111J22_123_4462_n428), .D(
DP_OP_111J22_123_4462_n324), .ICI(DP_OP_111J22_123_4462_n328), .S(
DP_OP_111J22_123_4462_n322), .ICO(DP_OP_111J22_123_4462_n320), .CO(
DP_OP_111J22_123_4462_n321) );
CMPR42X1TS U872 ( .A(DP_OP_111J22_123_4462_n406), .B(
DP_OP_111J22_123_4462_n418), .C(DP_OP_111J22_123_4462_n431), .D(
DP_OP_111J22_123_4462_n352), .ICI(DP_OP_111J22_123_4462_n457), .S(
DP_OP_111J22_123_4462_n346), .ICO(DP_OP_111J22_123_4462_n344), .CO(
DP_OP_111J22_123_4462_n345) );
XNOR2X1TS U873 ( .A(n1502), .B(n467), .Y(n1505) );
OAI22X1TS U874 ( .A0(n546), .A1(n1562), .B0(n515), .B1(n1530), .Y(n1533) );
CMPR42X1TS U875 ( .A(mult_x_23_n310), .B(mult_x_23_n322), .C(mult_x_23_n208),
.D(mult_x_23_n201), .ICI(mult_x_23_n205), .S(mult_x_23_n199), .ICO(
mult_x_23_n197), .CO(mult_x_23_n198) );
CMPR42X1TS U876 ( .A(mult_x_23_n313), .B(mult_x_23_n337), .C(mult_x_23_n301),
.D(mult_x_23_n235), .ICI(mult_x_23_n232), .S(mult_x_23_n226), .ICO(
mult_x_23_n224), .CO(mult_x_23_n225) );
INVX2TS U877 ( .A(n1335), .Y(n531) );
NAND2X1TS U878 ( .A(n451), .B(n589), .Y(n1320) );
NOR2X1TS U879 ( .A(n2254), .B(n2242), .Y(n2214) );
NOR2X1TS U880 ( .A(n2192), .B(n2189), .Y(n2162) );
NAND2X1TS U881 ( .A(n1569), .B(n1575), .Y(n1578) );
NAND2X1TS U882 ( .A(n1571), .B(n563), .Y(n936) );
NOR2X2TS U883 ( .A(n1372), .B(n857), .Y(n789) );
CMPR42X1TS U884 ( .A(DP_OP_111J22_123_4462_n435), .B(
DP_OP_111J22_123_4462_n448), .C(DP_OP_111J22_123_4462_n461), .D(
DP_OP_111J22_123_4462_n369), .ICI(DP_OP_111J22_123_4462_n474), .S(
DP_OP_111J22_123_4462_n366), .ICO(DP_OP_111J22_123_4462_n364), .CO(
DP_OP_111J22_123_4462_n365) );
BUFX3TS U885 ( .A(n1320), .Y(n1361) );
INVX2TS U886 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[14]), .Y(n2063) );
NOR2X1TS U887 ( .A(n2118), .B(n1991), .Y(n2104) );
CLKAND2X2TS U888 ( .A(n449), .B(n481), .Y(n845) );
MX2X1TS U889 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
INVX2TS U890 ( .A(n1983), .Y(n2336) );
XOR3X1TS U891 ( .A(n656), .B(n655), .C(n654), .Y(n657) );
AO21XLTS U892 ( .A0(n457), .A1(n500), .B0(DP_OP_111J22_123_4462_n727), .Y(
n654) );
OAI21X2TS U893 ( .A0(n955), .A1(n951), .B0(n952), .Y(n950) );
CLKAND2X2TS U894 ( .A(n1571), .B(n1581), .Y(n565) );
NOR2X2TS U895 ( .A(DP_OP_111J22_123_4462_n259), .B(
DP_OP_111J22_123_4462_n261), .Y(n942) );
NAND2BXLTS U896 ( .AN(n1608), .B(n460), .Y(n713) );
OAI22X1TS U897 ( .A0(n1523), .A1(n553), .B0(n712), .B1(n476), .Y(n1527) );
MX2X1TS U898 ( .A(Data_MY[17]), .B(n442), .S0(n2369), .Y(n329) );
MX2X1TS U899 ( .A(Data_MX[9]), .B(n397), .S0(n1982), .Y(n353) );
MX2X1TS U900 ( .A(Data_MY[21]), .B(n438), .S0(n459), .Y(n333) );
MX2X1TS U901 ( .A(Data_MY[16]), .B(n441), .S0(n2336), .Y(n328) );
MX2X1TS U902 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n1985), .Y(n357) );
MX2X1TS U903 ( .A(Data_MY[15]), .B(n440), .S0(n2336), .Y(n327) );
MX2X1TS U904 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n1984), .Y(n361) );
MX2X1TS U905 ( .A(Data_MX[3]), .B(n434), .S0(n1982), .Y(n347) );
MX2X1TS U906 ( .A(Data_MX[10]), .B(n444), .S0(n1982), .Y(n354) );
MX2X1TS U907 ( .A(Data_MX[2]), .B(n433), .S0(n1982), .Y(n346) );
MX2X1TS U908 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(n1984), .Y(n359) );
MX2X1TS U909 ( .A(P_Sgf[11]), .B(Sgf_operation_Result[11]), .S0(n2337), .Y(
n226) );
MX2X1TS U910 ( .A(P_Sgf[6]), .B(Sgf_operation_Result[6]), .S0(n2337), .Y(
n221) );
MX2X1TS U911 ( .A(P_Sgf[7]), .B(Sgf_operation_Result[7]), .S0(n2337), .Y(
n222) );
MX2X1TS U912 ( .A(P_Sgf[8]), .B(Sgf_operation_Result[8]), .S0(n2337), .Y(
n223) );
MX2X1TS U913 ( .A(P_Sgf[4]), .B(Sgf_operation_Result[4]), .S0(n2326), .Y(
n219) );
MX2X1TS U914 ( .A(P_Sgf[5]), .B(Sgf_operation_Result[5]), .S0(n2326), .Y(
n220) );
MX2X1TS U915 ( .A(P_Sgf[3]), .B(Sgf_operation_Result[3]), .S0(n2326), .Y(
n218) );
MX2X1TS U916 ( .A(P_Sgf[15]), .B(n2281), .S0(n2340), .Y(n230) );
MX2X1TS U917 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n459), .Y(n316) );
MX2X1TS U918 ( .A(P_Sgf[30]), .B(n2173), .S0(n2225), .Y(n245) );
MX2X1TS U919 ( .A(P_Sgf[45]), .B(n2000), .S0(n2088), .Y(n260) );
MX2X1TS U920 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n2336), .Y(n336) );
MX2X1TS U921 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n2336), .Y(n340) );
MX2X1TS U922 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n1985), .Y(n338) );
MX2X1TS U923 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n2369), .Y(n337) );
MX2X1TS U924 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n2369), .Y(n341) );
MX2X1TS U925 ( .A(n2241), .B(Add_result[1]), .S0(n2035), .Y(n305) );
MX2X1TS U926 ( .A(n2231), .B(Add_result[2]), .S0(n2035), .Y(n304) );
MX2X1TS U927 ( .A(n2213), .B(Add_result[3]), .S0(n2240), .Y(n303) );
INVX2TS U928 ( .A(n2230), .Y(n2211) );
MX2X1TS U929 ( .A(n2202), .B(Add_result[4]), .S0(n2240), .Y(n302) );
MX2X1TS U930 ( .A(n2188), .B(Add_result[5]), .S0(n2240), .Y(n301) );
MX2X1TS U931 ( .A(n2178), .B(Add_result[6]), .S0(n2240), .Y(n300) );
MX2X1TS U932 ( .A(n2158), .B(Add_result[7]), .S0(n2240), .Y(n299) );
MX2X1TS U933 ( .A(n2146), .B(Add_result[8]), .S0(n2261), .Y(n298) );
MX2X1TS U934 ( .A(n2133), .B(Add_result[9]), .S0(n2035), .Y(n297) );
MX2X1TS U935 ( .A(n2121), .B(Add_result[10]), .S0(n2261), .Y(n296) );
MX2X1TS U936 ( .A(n2105), .B(Add_result[11]), .S0(n2261), .Y(n295) );
MX2X1TS U937 ( .A(n2094), .B(Add_result[12]), .S0(n2035), .Y(n294) );
MX2X1TS U938 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n458), .Y(n367) );
MX2X1TS U939 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n2369), .Y(n372) );
MX2X1TS U940 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n2336), .Y(n370) );
MX2X1TS U941 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n459), .Y(n374) );
MX2X1TS U942 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n1985), .Y(n369) );
MX2X1TS U943 ( .A(P_Sgf[13]), .B(n2273), .S0(n2340), .Y(n228) );
MX2X1TS U944 ( .A(P_Sgf[1]), .B(Sgf_operation_Result[1]), .S0(n2326), .Y(
n216) );
MX2X1TS U945 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n2369), .Y(n335) );
MX2X1TS U946 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n2338),
.Y(n278) );
MX2X1TS U947 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n458), .Y(n339) );
MX2X1TS U948 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n2336), .Y(n368) );
MX2X1TS U949 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n2336), .Y(n342) );
MX2X1TS U950 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n2336), .Y(n373) );
MX2X1TS U951 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n459), .Y(n371) );
MX2X1TS U952 ( .A(Data_MX[11]), .B(n554), .S0(n2369), .Y(n355) );
MX2X1TS U953 ( .A(Data_MY[20]), .B(n555), .S0(n1985), .Y(n332) );
MX2X1TS U954 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n1985), .Y(n366) );
MX2X1TS U955 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n1982), .Y(n344) );
CLKAND2X2TS U956 ( .A(n1099), .B(n1098), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N1) );
MX2X1TS U957 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n458), .Y(n320) );
MX2X1TS U958 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n458), .Y(n321) );
MX2X1TS U959 ( .A(Data_MY[11]), .B(Op_MY[11]), .S0(n458), .Y(n323) );
MX2X1TS U960 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n458), .Y(n330) );
MX2X1TS U961 ( .A(Data_MY[22]), .B(n1986), .S0(n458), .Y(n334) );
MX2X1TS U962 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n459), .Y(n331) );
MX2X1TS U963 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n1985), .Y(n322) );
OAI21XLTS U964 ( .A0(n1206), .A1(n1192), .B0(n1191), .Y(n1196) );
NOR2XLTS U965 ( .A(n1961), .B(underflow_flag), .Y(n1962) );
OAI21XLTS U966 ( .A0(n1206), .A1(n1183), .B0(n1182), .Y(n1188) );
MX2X1TS U967 ( .A(P_Sgf[0]), .B(n2327), .S0(n2326), .Y(n215) );
MX2X1TS U968 ( .A(P_Sgf[2]), .B(Sgf_operation_Result[2]), .S0(n2326), .Y(
n217) );
MX2X1TS U969 ( .A(P_Sgf[9]), .B(Sgf_operation_Result[9]), .S0(n2337), .Y(
n224) );
MX2X1TS U970 ( .A(P_Sgf[10]), .B(Sgf_operation_Result[10]), .S0(n2337), .Y(
n225) );
MX2X1TS U971 ( .A(P_Sgf[12]), .B(n2335), .S0(n2337), .Y(n227) );
CLKAND2X2TS U972 ( .A(n2334), .B(n2333), .Y(n2335) );
OR2X1TS U973 ( .A(n2332), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[12]), .Y(
n2334) );
MX2X1TS U974 ( .A(P_Sgf[14]), .B(n2331), .S0(n2337), .Y(n229) );
NAND4XLTS U975 ( .A(n2357), .B(n2356), .C(n2355), .D(n2354), .Y(n2364) );
NAND4XLTS U976 ( .A(n2353), .B(n2352), .C(n2351), .D(n2350), .Y(n2365) );
MX2X1TS U977 ( .A(Data_MY[0]), .B(Op_MY[0]), .S0(n459), .Y(n312) );
MX2X1TS U978 ( .A(Data_MY[1]), .B(Op_MY[1]), .S0(n459), .Y(n313) );
MX2X1TS U979 ( .A(Data_MY[2]), .B(Op_MY[2]), .S0(n1984), .Y(n314) );
MX2X1TS U980 ( .A(Data_MY[3]), .B(Op_MY[3]), .S0(n1985), .Y(n315) );
MX2X1TS U981 ( .A(Data_MY[5]), .B(Op_MY[5]), .S0(n458), .Y(n317) );
MX2X1TS U982 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n458), .Y(n318) );
MX2X1TS U983 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n1985), .Y(n319) );
MX2X1TS U984 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n1984), .Y(n324) );
MX2X1TS U985 ( .A(Data_MY[13]), .B(Op_MY[13]), .S0(n2336), .Y(n325) );
MX2X1TS U986 ( .A(Data_MY[14]), .B(n529), .S0(n2369), .Y(n326) );
MX2X1TS U987 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n1984), .Y(n345) );
MX2X1TS U988 ( .A(Data_MX[4]), .B(n443), .S0(n1982), .Y(n348) );
MX2X1TS U989 ( .A(Data_MX[5]), .B(n401), .S0(n1982), .Y(n349) );
MX2X1TS U990 ( .A(Data_MX[6]), .B(n2358), .S0(n1982), .Y(n350) );
MX2X1TS U991 ( .A(Data_MX[7]), .B(n400), .S0(n1982), .Y(n351) );
MX2X1TS U992 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n1982), .Y(n352) );
MX2X1TS U993 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n459), .Y(n356) );
MX2X1TS U994 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(n459), .Y(n358) );
MX2X1TS U995 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n1984), .Y(n360) );
MX2X1TS U996 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(n1984), .Y(n362) );
MX2X1TS U997 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n1984), .Y(n363) );
MX2X1TS U998 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n1984), .Y(n364) );
MX2X1TS U999 ( .A(Data_MX[21]), .B(n520), .S0(n1985), .Y(n365) );
NAND2BXLTS U1000 ( .AN(zero_flag), .B(n527), .Y(n2267) );
OAI21XLTS U1001 ( .A0(n981), .A1(n958), .B0(n957), .Y(n963) );
OAI21XLTS U1002 ( .A0(n981), .A1(n977), .B0(n978), .Y(n976) );
XOR2XLTS U1003 ( .A(n981), .B(n980), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N17) );
NOR2X1TS U1004 ( .A(n912), .B(n916), .Y(n904) );
XNOR2X1TS U1005 ( .A(n1583), .B(n793), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N18) );
AOI21X1TS U1006 ( .A0(n1377), .A1(n1379), .B0(n863), .Y(n868) );
INVX2TS U1007 ( .A(n1382), .Y(n1384) );
XOR2XLTS U1008 ( .A(n1414), .B(n1413), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N5) );
XOR2XLTS U1009 ( .A(n1422), .B(n1421), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N3) );
CLKAND2X2TS U1010 ( .A(n1529), .B(n1528), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N1) );
OR2X1TS U1011 ( .A(n1527), .B(n1526), .Y(n1529) );
OAI21XLTS U1012 ( .A0(n1206), .A1(n1202), .B0(n1203), .Y(n1201) );
XOR2XLTS U1013 ( .A(n1206), .B(n1205), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N17) );
OAI21XLTS U1014 ( .A0(n1329), .A1(n1325), .B0(n1326), .Y(n1236) );
CLKAND2X2TS U1015 ( .A(n1324), .B(n1323), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N1) );
OR2X1TS U1016 ( .A(n1322), .B(n1321), .Y(n1324) );
NAND2X2TS U1017 ( .A(n591), .B(n406), .Y(n781) );
CMPR42X2TS U1018 ( .A(DP_OP_111J22_123_4462_n438), .B(
DP_OP_111J22_123_4462_n425), .C(DP_OP_111J22_123_4462_n302), .D(
DP_OP_111J22_123_4462_n296), .ICI(DP_OP_111J22_123_4462_n298), .S(
DP_OP_111J22_123_4462_n293), .ICO(DP_OP_111J22_123_4462_n291), .CO(
DP_OP_111J22_123_4462_n292) );
AOI21X4TS U1019 ( .A0(n1181), .A1(n842), .B0(n841), .Y(n1180) );
XNOR2X4TS U1020 ( .A(n1435), .B(n1434), .Y(n410) );
XNOR2X2TS U1021 ( .A(n1431), .B(n1430), .Y(n1435) );
AND2X4TS U1022 ( .A(n1436), .B(n515), .Y(n1563) );
AOI21X2TS U1023 ( .A0(n1230), .A1(n1209), .B0(n1208), .Y(n1219) );
INVX4TS U1024 ( .A(n722), .Y(n465) );
INVX2TS U1025 ( .A(n409), .Y(n461) );
INVX2TS U1026 ( .A(n807), .Y(n488) );
INVX2TS U1027 ( .A(n794), .Y(n486) );
INVX2TS U1028 ( .A(n741), .Y(n517) );
INVX2TS U1029 ( .A(n699), .Y(n1525) );
CLKXOR2X2TS U1030 ( .A(n710), .B(n709), .Y(n402) );
CLKBUFX2TS U1031 ( .A(n1093), .Y(n469) );
OR2X1TS U1032 ( .A(P_Sgf[9]), .B(P_Sgf[10]), .Y(n404) );
INVX4TS U1033 ( .A(n1168), .Y(n541) );
INVX2TS U1034 ( .A(n1168), .Y(n540) );
AND2X2TS U1035 ( .A(n649), .B(n648), .Y(n408) );
CLKXOR2X2TS U1036 ( .A(n683), .B(n682), .Y(n693) );
CLKXOR2X2TS U1037 ( .A(Op_MX[13]), .B(Op_MX[14]), .Y(n794) );
CLKXOR2X2TS U1038 ( .A(Op_MX[19]), .B(Op_MX[20]), .Y(n1283) );
CLKXOR2X2TS U1039 ( .A(n708), .B(n698), .Y(n409) );
INVX2TS U1040 ( .A(n872), .Y(n482) );
CLKXOR2X2TS U1041 ( .A(Op_MX[17]), .B(Op_MX[18]), .Y(n1427) );
CLKXOR2X4TS U1042 ( .A(n888), .B(Op_MX[11]), .Y(n412) );
CLKXOR2X2TS U1043 ( .A(n740), .B(n739), .Y(n741) );
INVX2TS U1044 ( .A(n402), .Y(n430) );
INVX2TS U1045 ( .A(n1616), .Y(n462) );
NAND2X2TS U1046 ( .A(n684), .B(n693), .Y(n1616) );
INVX2TS U1047 ( .A(n599), .Y(n427) );
INVX2TS U1048 ( .A(n421), .Y(n506) );
OR2X1TS U1049 ( .A(P_Sgf[14]), .B(P_Sgf[12]), .Y(n423) );
NOR4X1TS U1050 ( .A(P_Sgf[8]), .B(P_Sgf[6]), .C(P_Sgf[7]), .D(P_Sgf[11]),
.Y(n424) );
INVX2TS U1051 ( .A(n1983), .Y(n1985) );
BUFX3TS U1052 ( .A(n881), .Y(n425) );
BUFX3TS U1053 ( .A(n881), .Y(n426) );
CLKXOR2X2TS U1054 ( .A(n880), .B(n879), .Y(n881) );
CLKXOR2X4TS U1055 ( .A(n1444), .B(n1443), .Y(n1519) );
AOI21X2TS U1056 ( .A0(n899), .A1(n930), .B0(n898), .Y(n1579) );
OAI21X2TS U1057 ( .A0(n937), .A1(n942), .B0(n943), .Y(n898) );
ADDFHX2TS U1058 ( .A(n1596), .B(n1595), .CI(n1594), .CO(
DP_OP_111J22_123_4462_n289), .S(DP_OP_111J22_123_4462_n297) );
CMPR42X2TS U1059 ( .A(DP_OP_111J22_123_4462_n444), .B(
DP_OP_111J22_123_4462_n350), .C(DP_OP_111J22_123_4462_n470), .D(
DP_OP_111J22_123_4462_n346), .ICI(DP_OP_111J22_123_4462_n347), .S(
DP_OP_111J22_123_4462_n343), .ICO(DP_OP_111J22_123_4462_n341), .CO(
DP_OP_111J22_123_4462_n342) );
AOI21X4TS U1060 ( .A0(n950), .A1(n948), .B0(n651), .Y(n662) );
BUFX3TS U1061 ( .A(n1148), .Y(n538) );
AOI21X2TS U1062 ( .A0(n629), .A1(n1037), .B0(n628), .Y(n1035) );
INVX2TS U1063 ( .A(n427), .Y(n428) );
INVX2TS U1064 ( .A(n427), .Y(n429) );
INVX2TS U1065 ( .A(n430), .Y(n431) );
INVX2TS U1066 ( .A(n430), .Y(n432) );
INVX2TS U1067 ( .A(n572), .Y(n433) );
INVX2TS U1068 ( .A(n577), .Y(n434) );
INVX2TS U1069 ( .A(n579), .Y(n437) );
INVX2TS U1070 ( .A(n407), .Y(n438) );
INVX2TS U1071 ( .A(n391), .Y(n439) );
INVX2TS U1072 ( .A(n590), .Y(n441) );
INVX2TS U1073 ( .A(n396), .Y(n442) );
INVX2TS U1074 ( .A(n394), .Y(n443) );
INVX2TS U1075 ( .A(n581), .Y(n444) );
INVX2TS U1076 ( .A(n2006), .Y(n445) );
INVX2TS U1077 ( .A(n445), .Y(n446) );
INVX2TS U1078 ( .A(n445), .Y(n447) );
INVX4TS U1079 ( .A(n417), .Y(n448) );
INVX2TS U1080 ( .A(n418), .Y(n450) );
INVX2TS U1081 ( .A(n596), .Y(n451) );
INVX2TS U1082 ( .A(n596), .Y(n452) );
INVX2TS U1083 ( .A(n897), .Y(n454) );
INVX2TS U1084 ( .A(Op_MY[0]), .Y(n455) );
INVX2TS U1085 ( .A(n1983), .Y(n458) );
INVX2TS U1086 ( .A(n1983), .Y(n459) );
INVX4TS U1087 ( .A(n409), .Y(n460) );
INVX2TS U1088 ( .A(n462), .Y(n464) );
XNOR2X2TS U1089 ( .A(n1093), .B(Op_MY[2]), .Y(n599) );
INVX2TS U1090 ( .A(n412), .Y(n474) );
INVX2TS U1091 ( .A(n412), .Y(n475) );
INVX2TS U1092 ( .A(n699), .Y(n476) );
INVX2TS U1093 ( .A(n794), .Y(n487) );
INVX2TS U1094 ( .A(n488), .Y(n489) );
INVX2TS U1095 ( .A(n488), .Y(n490) );
INVX2TS U1096 ( .A(n1427), .Y(n492) );
INVX2TS U1097 ( .A(n411), .Y(n494) );
INVX2TS U1098 ( .A(n1283), .Y(n496) );
INVX2TS U1099 ( .A(n415), .Y(n498) );
INVX2TS U1100 ( .A(n648), .Y(n499) );
INVX2TS U1101 ( .A(n499), .Y(n500) );
INVX2TS U1102 ( .A(n499), .Y(n501) );
INVX4TS U1103 ( .A(n502), .Y(n503) );
INVX2TS U1104 ( .A(n413), .Y(n510) );
INVX2TS U1105 ( .A(n420), .Y(n514) );
INVX2TS U1106 ( .A(n410), .Y(n516) );
INVX2TS U1107 ( .A(n517), .Y(n518) );
INVX2TS U1108 ( .A(n517), .Y(n519) );
INVX2TS U1109 ( .A(n414), .Y(n520) );
INVX2TS U1110 ( .A(n414), .Y(n521) );
NOR2XLTS U1111 ( .A(P_Sgf[47]), .B(n2263), .Y(n2264) );
CMPR42X1TS U1112 ( .A(mult_x_23_n340), .B(mult_x_23_n249), .C(mult_x_23_n253), .D(mult_x_23_n247), .ICI(mult_x_23_n250), .S(mult_x_23_n245), .ICO(
mult_x_23_n243), .CO(mult_x_23_n244) );
ADDHX1TS U1113 ( .A(n1367), .B(n1366), .CO(mult_x_23_n248), .S(
mult_x_23_n249) );
NOR2X2TS U1114 ( .A(FS_Module_state_reg[3]), .B(FS_Module_state_reg[2]), .Y(
n1981) );
NOR4X1TS U1115 ( .A(n554), .B(n444), .C(n400), .D(Op_MX[0]), .Y(n2360) );
NOR4X1TS U1116 ( .A(Op_MY[11]), .B(Op_MY[0]), .C(Op_MY[13]), .D(Op_MY[9]),
.Y(n2351) );
NOR4X1TS U1117 ( .A(Op_MY[8]), .B(Op_MY[6]), .C(Op_MY[4]), .D(Op_MY[2]), .Y(
n2352) );
NAND2X1TS U1118 ( .A(n804), .B(n803), .Y(n1269) );
ADDHX1TS U1119 ( .A(n811), .B(n810), .CO(n812), .S(n804) );
INVX2TS U1120 ( .A(n422), .Y(n522) );
INVX2TS U1121 ( .A(n422), .Y(n523) );
INVX2TS U1122 ( .A(n422), .Y(n524) );
NOR2X2TS U1123 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n2230) );
INVX2TS U1124 ( .A(n576), .Y(n526) );
XNOR2X2TS U1125 ( .A(Op_MX[1]), .B(Op_MX[13]), .Y(n708) );
INVX2TS U1126 ( .A(n528), .Y(n529) );
NOR2X2TS U1127 ( .A(Op_MY[14]), .B(Op_MY[2]), .Y(n726) );
BUFX3TS U1128 ( .A(n897), .Y(n530) );
OR2X1TS U1129 ( .A(n1587), .B(n530), .Y(n1588) );
CLKBUFX2TS U1130 ( .A(n1345), .Y(n533) );
CLKBUFX2TS U1131 ( .A(n1353), .Y(n534) );
INVX2TS U1132 ( .A(n1365), .Y(n535) );
INVX2TS U1133 ( .A(n1365), .Y(n536) );
CLKBUFX2TS U1134 ( .A(n1140), .Y(n537) );
BUFX3TS U1135 ( .A(n1154), .Y(n539) );
INVX2TS U1136 ( .A(n1534), .Y(n543) );
INVX2TS U1137 ( .A(n1556), .Y(n545) );
INVX4TS U1138 ( .A(n1563), .Y(n546) );
INVX2TS U1139 ( .A(n1563), .Y(n547) );
INVX4TS U1140 ( .A(n1611), .Y(n548) );
INVX2TS U1141 ( .A(n1611), .Y(n549) );
INVX2TS U1142 ( .A(n585), .Y(n550) );
BUFX3TS U1143 ( .A(Op_MX[0]), .Y(n1152) );
INVX2TS U1144 ( .A(n551), .Y(n552) );
BUFX3TS U1145 ( .A(Op_MY[12]), .Y(n1362) );
AOI21X1TS U1146 ( .A0(n1208), .A1(n837), .B0(n836), .Y(n838) );
NOR2XLTS U1147 ( .A(n404), .B(n423), .Y(n1627) );
OAI22X1TS U1148 ( .A0(n456), .A1(n1065), .B0(n501), .B1(n1064), .Y(
mult_x_55_n294) );
NOR4X1TS U1149 ( .A(P_Sgf[20]), .B(P_Sgf[18]), .C(P_Sgf[19]), .D(P_Sgf[21]),
.Y(n1631) );
NOR4X1TS U1150 ( .A(Op_MX[22]), .B(Op_MX[19]), .C(Op_MX[17]), .D(Op_MX[15]),
.Y(n2355) );
NOR4X1TS U1151 ( .A(Op_MY[7]), .B(Op_MY[5]), .C(Op_MY[3]), .D(Op_MY[1]), .Y(
n2353) );
OAI22X2TS U1152 ( .A0(ack_FSM), .A1(n1963), .B0(beg_FSM), .B1(n2406), .Y(
n2266) );
INVX2TS U1153 ( .A(n1614), .Y(n553) );
NAND2X1TS U1154 ( .A(n587), .B(n706), .Y(n1614) );
NOR3XLTS U1155 ( .A(Op_MY[10]), .B(Op_MY[12]), .C(Op_MY[23]), .Y(n2350) );
NOR3XLTS U1156 ( .A(Op_MX[12]), .B(Op_MX[13]), .C(Op_MX[24]), .Y(n2359) );
INVX2TS U1157 ( .A(n592), .Y(n555) );
NAND2X1TS U1158 ( .A(Op_MY[20]), .B(Op_MY[8]), .Y(n1447) );
NOR2X1TS U1159 ( .A(Op_MY[20]), .B(Op_MY[8]), .Y(n869) );
BUFX3TS U1160 ( .A(n1948), .Y(n556) );
BUFX3TS U1161 ( .A(n1948), .Y(n2252) );
NOR2X2TS U1162 ( .A(n2391), .B(n1947), .Y(n1948) );
INVX2TS U1163 ( .A(n2250), .Y(n557) );
INVX2TS U1164 ( .A(n2250), .Y(n558) );
INVX2TS U1165 ( .A(n2250), .Y(n559) );
NAND2X1TS U1166 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n1987) );
AO21X1TS U1167 ( .A0(n1582), .A1(n1581), .B0(n1580), .Y(n564) );
OR2X2TS U1168 ( .A(FSM_selector_B[1]), .B(n2386), .Y(n567) );
BUFX3TS U1169 ( .A(Op_MY[22]), .Y(n1986) );
INVX2TS U1170 ( .A(n2381), .Y(n2327) );
BUFX3TS U1171 ( .A(Op_MY[18]), .Y(n1330) );
OR2X1TS U1172 ( .A(n1794), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[14]),
.Y(n578) );
INVX2TS U1173 ( .A(Op_MX[12]), .Y(n700) );
OR2X2TS U1174 ( .A(DP_OP_111J22_123_4462_n356), .B(
DP_OP_111J22_123_4462_n360), .Y(n591) );
AO21X1TS U1175 ( .A0(n889), .A1(n885), .B0(n870), .Y(n593) );
NAND2X1TS U1176 ( .A(Op_MY[18]), .B(Op_MY[6]), .Y(n1441) );
NAND2X1TS U1177 ( .A(n1771), .B(n1664), .Y(n1666) );
NOR2XLTS U1178 ( .A(n596), .B(n589), .Y(n1281) );
NAND2X4TS U1179 ( .A(n815), .B(n807), .Y(n1345) );
NOR2XLTS U1180 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n1979) );
CMPR42X1TS U1181 ( .A(mult_x_23_n312), .B(mult_x_23_n336), .C(mult_x_23_n300), .D(n596), .ICI(mult_x_23_n224), .S(mult_x_23_n217), .ICO(mult_x_23_n215),
.CO(mult_x_23_n216) );
INVX2TS U1182 ( .A(n2136), .Y(n2138) );
INVX2TS U1183 ( .A(n2108), .Y(n2110) );
CMPR42X1TS U1184 ( .A(mult_x_55_n237), .B(mult_x_55_n234), .C(mult_x_55_n231), .D(mult_x_55_n235), .ICI(mult_x_55_n228), .S(mult_x_55_n225), .ICO(
mult_x_55_n223), .CO(mult_x_55_n224) );
INVX2TS U1185 ( .A(n2159), .Y(n2258) );
AOI21X1TS U1186 ( .A0(n965), .A1(n969), .B0(n645), .Y(n957) );
OAI21X2TS U1187 ( .A0(n638), .A1(n1012), .B0(n637), .Y(n1006) );
INVX2TS U1188 ( .A(n1418), .Y(n1420) );
OAI21XLTS U1189 ( .A0(n1031), .A1(n1027), .B0(n1028), .Y(n1026) );
OR2X1TS U1190 ( .A(n1097), .B(n1096), .Y(n1099) );
NAND2X1TS U1191 ( .A(n927), .B(n926), .Y(n928) );
OAI21X1TS U1192 ( .A0(n1421), .A1(n1418), .B0(n1419), .Y(n1416) );
AOI21X2TS U1193 ( .A0(n1263), .A1(n582), .B0(n824), .Y(n1259) );
NOR2X2TS U1195 ( .A(mult_x_55_n225), .B(mult_x_55_n232), .Y(n1007) );
NOR2X2TS U1196 ( .A(mult_x_55_n233), .B(mult_x_55_n240), .Y(n1106) );
OR2X2TS U1197 ( .A(mult_x_55_n241), .B(mult_x_55_n246), .Y(n1015) );
NAND2X1TS U1198 ( .A(n1015), .B(n580), .Y(n638) );
NOR2X2TS U1199 ( .A(mult_x_55_n254), .B(mult_x_55_n258), .Y(n1022) );
NOR2X2TS U1200 ( .A(mult_x_55_n259), .B(mult_x_55_n263), .Y(n1027) );
NOR2X1TS U1201 ( .A(n1022), .B(n1027), .Y(n635) );
XOR2X1TS U1202 ( .A(Op_MY[2]), .B(Op_MY[3]), .Y(n600) );
XNOR2X1TS U1203 ( .A(Op_MY[3]), .B(n433), .Y(n605) );
XNOR2X1TS U1204 ( .A(n498), .B(n434), .Y(n1092) );
OAI22X1TS U1205 ( .A0(n537), .A1(n605), .B0(n428), .B1(n1092), .Y(n632) );
XNOR2X1TS U1206 ( .A(Op_MY[4]), .B(Op_MY[3]), .Y(n601) );
XNOR2X1TS U1207 ( .A(n450), .B(n550), .Y(n603) );
XNOR2X1TS U1208 ( .A(Op_MY[5]), .B(Op_MX[1]), .Y(n1085) );
OAI22X1TS U1209 ( .A0(n538), .A1(n603), .B0(n1146), .B1(n1085), .Y(n631) );
OAI22X1TS U1210 ( .A0(n1148), .A1(n418), .B0(n1146), .B1(n604), .Y(n664) );
NAND2X2TS U1211 ( .A(n1093), .B(n455), .Y(n1095) );
XNOR2X1TS U1212 ( .A(n1093), .B(n443), .Y(n606) );
XNOR2X1TS U1213 ( .A(n1093), .B(n401), .Y(n1094) );
OAI22X1TS U1214 ( .A0(n1163), .A1(n606), .B0(n1094), .B1(n566), .Y(n663) );
NOR2BX1TS U1215 ( .AN(n550), .B(n1146), .Y(n609) );
XNOR2X1TS U1216 ( .A(Op_MY[3]), .B(Op_MX[1]), .Y(n611) );
OAI22X1TS U1217 ( .A0(n1140), .A1(n611), .B0(n599), .B1(n605), .Y(n608) );
XNOR2X1TS U1218 ( .A(n469), .B(n434), .Y(n620) );
OAI22X1TS U1219 ( .A0(n1163), .A1(n620), .B0(n606), .B1(n566), .Y(n607) );
CMPR32X2TS U1220 ( .A(n609), .B(n608), .C(n607), .CO(n626), .S(n625) );
OAI22X1TS U1221 ( .A0(n1140), .A1(n415), .B0(n428), .B1(n610), .Y(n619) );
XNOR2X1TS U1222 ( .A(Op_MY[3]), .B(n1152), .Y(n612) );
OAI22X1TS U1223 ( .A0(n1140), .A1(n612), .B0(n429), .B1(n611), .Y(n618) );
NOR2X2TS U1224 ( .A(n625), .B(n624), .Y(n1043) );
NOR2X1TS U1225 ( .A(n1038), .B(n1043), .Y(n629) );
XNOR2X1TS U1226 ( .A(n1093), .B(Op_MX[1]), .Y(n613) );
XNOR2X1TS U1227 ( .A(n1093), .B(n433), .Y(n621) );
OAI22X1TS U1228 ( .A0(n1095), .A1(n613), .B0(n621), .B1(n455), .Y(n616) );
NOR2BX1TS U1229 ( .AN(n1152), .B(n429), .Y(n615) );
OAI22X1TS U1230 ( .A0(n1163), .A1(n1152), .B0(n613), .B1(n455), .Y(n1097) );
NAND2X1TS U1231 ( .A(n614), .B(n1163), .Y(n1096) );
NAND2X1TS U1232 ( .A(n1097), .B(n1096), .Y(n1098) );
INVX2TS U1233 ( .A(n1098), .Y(n1055) );
NAND2X1TS U1234 ( .A(n616), .B(n615), .Y(n1053) );
INVX2TS U1235 ( .A(n1053), .Y(n617) );
AOI21X1TS U1236 ( .A0(n1054), .A1(n1055), .B0(n617), .Y(n1051) );
ADDHX1TS U1237 ( .A(n619), .B(n618), .CO(n624), .S(n623) );
OAI22X1TS U1238 ( .A0(n1163), .A1(n621), .B0(n620), .B1(n566), .Y(n622) );
NOR2X1TS U1239 ( .A(n623), .B(n622), .Y(n1048) );
NAND2X1TS U1240 ( .A(n623), .B(n622), .Y(n1049) );
OAI21X1TS U1241 ( .A0(n1051), .A1(n1048), .B0(n1049), .Y(n1037) );
NAND2X1TS U1242 ( .A(n625), .B(n624), .Y(n1044) );
NAND2X1TS U1243 ( .A(n627), .B(n626), .Y(n1039) );
OAI21X1TS U1244 ( .A0(n1038), .A1(n1044), .B0(n1039), .Y(n628) );
CMPR32X2TS U1245 ( .A(n632), .B(n631), .C(n630), .CO(n633), .S(n627) );
NOR2X1TS U1246 ( .A(mult_x_55_n264), .B(n633), .Y(n1032) );
NAND2X1TS U1247 ( .A(mult_x_55_n264), .B(n633), .Y(n1033) );
NAND2X1TS U1248 ( .A(mult_x_55_n259), .B(mult_x_55_n263), .Y(n1028) );
NAND2X1TS U1249 ( .A(mult_x_55_n254), .B(mult_x_55_n258), .Y(n1023) );
NAND2X1TS U1250 ( .A(mult_x_55_n247), .B(mult_x_55_n253), .Y(n1018) );
INVX2TS U1251 ( .A(n1018), .Y(n1013) );
NAND2X1TS U1252 ( .A(mult_x_55_n241), .B(mult_x_55_n246), .Y(n1014) );
INVX2TS U1253 ( .A(n1014), .Y(n636) );
AOI21X1TS U1254 ( .A0(n1015), .A1(n1013), .B0(n636), .Y(n637) );
NAND2X2TS U1255 ( .A(mult_x_55_n233), .B(mult_x_55_n240), .Y(n1107) );
NAND2X1TS U1256 ( .A(mult_x_55_n225), .B(mult_x_55_n232), .Y(n1008) );
OAI21X1TS U1257 ( .A0(n1007), .A1(n1107), .B0(n1008), .Y(n639) );
AOI21X4TS U1258 ( .A0(n640), .A1(n1006), .B0(n639), .Y(n982) );
NOR2X2TS U1259 ( .A(n997), .B(n995), .Y(n984) );
NOR2X2TS U1260 ( .A(mult_x_55_n198), .B(mult_x_55_n205), .Y(n990) );
NOR2X2TS U1261 ( .A(mult_x_55_n190), .B(mult_x_55_n197), .Y(n985) );
NOR2X2TS U1262 ( .A(n990), .B(n985), .Y(n642) );
NAND2X1TS U1263 ( .A(mult_x_55_n206), .B(mult_x_55_n215), .Y(n998) );
NAND2X1TS U1264 ( .A(mult_x_55_n198), .B(mult_x_55_n205), .Y(n991) );
NAND2X1TS U1265 ( .A(mult_x_55_n190), .B(mult_x_55_n197), .Y(n986) );
OAI21X4TS U1266 ( .A0(n982), .A1(n644), .B0(n643), .Y(n956) );
NOR2X2TS U1267 ( .A(mult_x_55_n184), .B(mult_x_55_n189), .Y(n977) );
NOR2X2TS U1268 ( .A(mult_x_55_n183), .B(mult_x_55_n177), .Y(n972) );
NOR2X2TS U1269 ( .A(mult_x_55_n171), .B(mult_x_55_n167), .Y(n959) );
NAND2X2TS U1270 ( .A(mult_x_55_n184), .B(mult_x_55_n189), .Y(n978) );
NAND2X1TS U1271 ( .A(mult_x_55_n183), .B(mult_x_55_n177), .Y(n973) );
NAND2X1TS U1272 ( .A(mult_x_55_n176), .B(mult_x_55_n172), .Y(n968) );
INVX2TS U1273 ( .A(n968), .Y(n645) );
NAND2X1TS U1274 ( .A(mult_x_55_n171), .B(mult_x_55_n167), .Y(n960) );
OAI21X1TS U1275 ( .A0(n957), .A1(n959), .B0(n960), .Y(n646) );
AOI21X4TS U1276 ( .A0(n956), .A1(n647), .B0(n646), .Y(n955) );
NOR2X1TS U1277 ( .A(mult_x_55_n166), .B(mult_x_55_n164), .Y(n951) );
NAND2X1TS U1278 ( .A(mult_x_55_n166), .B(mult_x_55_n164), .Y(n952) );
NOR2X1TS U1279 ( .A(n471), .B(n581), .Y(n656) );
INVX2TS U1280 ( .A(n656), .Y(n653) );
XOR2X1TS U1281 ( .A(Op_MY[10]), .B(Op_MY[11]), .Y(n649) );
XNOR2X1TS U1282 ( .A(Op_MY[10]), .B(Op_MY[9]), .Y(n648) );
XNOR2X1TS U1283 ( .A(n472), .B(n554), .Y(n1058) );
OAI22X1TS U1284 ( .A0(n457), .A1(n1058), .B0(n501), .B1(
DP_OP_111J22_123_4462_n727), .Y(n652) );
NAND2X1TS U1285 ( .A(mult_x_55_n163), .B(n650), .Y(n947) );
INVX2TS U1286 ( .A(n947), .Y(n651) );
CMPR32X2TS U1287 ( .A(n653), .B(n652), .C(mult_x_55_n162), .CO(n658), .S(
n650) );
NOR2X1TS U1288 ( .A(n471), .B(n561), .Y(n655) );
NAND2X1TS U1289 ( .A(n658), .B(n657), .Y(n659) );
NAND2X1TS U1290 ( .A(n660), .B(n659), .Y(n661) );
ADDHX1TS U1291 ( .A(n664), .B(n663), .CO(mult_x_55_n267), .S(n630) );
NOR2X2TS U1292 ( .A(Op_MY[13]), .B(Op_MY[1]), .Y(n702) );
NAND2X2TS U1293 ( .A(Op_MY[12]), .B(Op_MY[0]), .Y(n706) );
NAND2X1TS U1294 ( .A(Op_MY[13]), .B(Op_MY[1]), .Y(n703) );
NOR2X2TS U1295 ( .A(n726), .B(n728), .Y(n666) );
NAND2X2TS U1296 ( .A(Op_MY[14]), .B(Op_MY[2]), .Y(n725) );
OAI21X2TS U1297 ( .A0(n728), .A1(n725), .B0(n729), .Y(n665) );
AOI21X4TS U1298 ( .A0(n695), .A1(n666), .B0(n665), .Y(n690) );
NOR2X2TS U1299 ( .A(n441), .B(Op_MY[4]), .Y(n743) );
NOR2X2TS U1300 ( .A(n743), .B(n766), .Y(n1438) );
INVX2TS U1301 ( .A(n1438), .Y(n667) );
NOR2X1TS U1302 ( .A(n667), .B(n1440), .Y(n670) );
NAND2X2TS U1303 ( .A(n441), .B(Op_MY[4]), .Y(n763) );
NAND2X1TS U1304 ( .A(Op_MY[17]), .B(Op_MY[5]), .Y(n767) );
OAI21X4TS U1305 ( .A0(n766), .A1(n763), .B0(n767), .Y(n1437) );
INVX2TS U1306 ( .A(n1437), .Y(n668) );
OAI21X1TS U1307 ( .A0(n668), .A1(n1440), .B0(n1441), .Y(n669) );
AOI21X2TS U1308 ( .A0(n1439), .A1(n670), .B0(n669), .Y(n673) );
INVX2TS U1309 ( .A(n686), .Y(n671) );
NAND2X1TS U1310 ( .A(n439), .B(Op_MY[7]), .Y(n685) );
NAND2X1TS U1311 ( .A(n671), .B(n685), .Y(n672) );
CLKXOR2X4TS U1312 ( .A(n673), .B(n672), .Y(n1517) );
OAI21X1TS U1313 ( .A0(Op_MX[10]), .A1(Op_MX[22]), .B0(n437), .Y(n675) );
NAND2X1TS U1314 ( .A(Op_MX[10]), .B(Op_MX[22]), .Y(n674) );
NAND2X2TS U1315 ( .A(n675), .B(n674), .Y(n888) );
XNOR2X1TS U1316 ( .A(n1517), .B(n474), .Y(n1464) );
XOR2X1TS U1317 ( .A(Op_MX[21]), .B(Op_MX[10]), .Y(n676) );
NOR2X1TS U1318 ( .A(n676), .B(n679), .Y(n677) );
XOR2X1TS U1319 ( .A(n677), .B(n554), .Y(n684) );
NOR2X1TS U1320 ( .A(n437), .B(Op_MX[21]), .Y(n678) );
XNOR2X1TS U1321 ( .A(n679), .B(n678), .Y(n683) );
XNOR2X2TS U1322 ( .A(n437), .B(Op_MX[21]), .Y(n873) );
OAI21X1TS U1323 ( .A0(Op_MX[8]), .A1(Op_MX[20]), .B0(n436), .Y(n681) );
NAND2X1TS U1324 ( .A(Op_MX[8]), .B(Op_MX[20]), .Y(n680) );
NAND2X2TS U1325 ( .A(n1438), .B(n688), .Y(n691) );
AOI21X2TS U1326 ( .A0(n1437), .A1(n688), .B0(n687), .Y(n689) );
OAI21X4TS U1327 ( .A0(n691), .A1(n690), .B0(n689), .Y(n895) );
INVX2TS U1328 ( .A(n869), .Y(n1449) );
XNOR2X4TS U1329 ( .A(n895), .B(n692), .Y(n1515) );
XNOR2X1TS U1330 ( .A(n1515), .B(n475), .Y(n1462) );
NAND2X4TS U1331 ( .A(DP_OP_111J22_123_4462_n310), .B(
DP_OP_111J22_123_4462_n318), .Y(n1378) );
NAND2X2TS U1332 ( .A(DP_OP_111J22_123_4462_n300), .B(
DP_OP_111J22_123_4462_n309), .Y(n865) );
OAI21X4TS U1333 ( .A0(n864), .A1(n1378), .B0(n865), .Y(n1370) );
AOI21X4TS U1334 ( .A0(n1370), .A1(n789), .B0(n694), .Y(n792) );
INVX2TS U1335 ( .A(n695), .Y(n727) );
INVX2TS U1336 ( .A(n726), .Y(n696) );
NAND2X1TS U1337 ( .A(n696), .B(n725), .Y(n697) );
CLKXOR2X4TS U1338 ( .A(n727), .B(n697), .Y(n1609) );
XNOR2X1TS U1339 ( .A(n1609), .B(n460), .Y(n733) );
XOR2X1TS U1340 ( .A(Op_MX[0]), .B(Op_MX[12]), .Y(n699) );
XOR2X1TS U1341 ( .A(n700), .B(n708), .Y(n701) );
AND2X2TS U1342 ( .A(n701), .B(n476), .Y(n711) );
INVX2TS U1343 ( .A(n711), .Y(n1521) );
INVX2TS U1344 ( .A(n702), .Y(n704) );
CLKXOR2X4TS U1345 ( .A(n705), .B(n706), .Y(n1543) );
XNOR2X1TS U1346 ( .A(n1543), .B(n460), .Y(n712) );
OAI22X1TS U1347 ( .A0(n733), .A1(n476), .B0(n1521), .B1(n712), .Y(n715) );
XNOR2X1TS U1348 ( .A(n717), .B(n707), .Y(n710) );
NAND2X1TS U1349 ( .A(n708), .B(n698), .Y(n709) );
NOR2BX1TS U1350 ( .AN(n553), .B(n432), .Y(n714) );
INVX2TS U1351 ( .A(n711), .Y(n1523) );
NAND2X1TS U1352 ( .A(n713), .B(n1523), .Y(n1526) );
NAND2X1TS U1353 ( .A(n1527), .B(n1526), .Y(n1528) );
INVX2TS U1354 ( .A(n1528), .Y(n1424) );
NAND2X1TS U1355 ( .A(n715), .B(n714), .Y(n1423) );
INVX2TS U1356 ( .A(n1423), .Y(n716) );
AOI21X2TS U1357 ( .A0(n571), .A1(n1424), .B0(n716), .Y(n1421) );
NOR2X1TS U1358 ( .A(n794), .B(n717), .Y(n718) );
XNOR2X2TS U1359 ( .A(Op_MX[15]), .B(Op_MX[3]), .Y(n738) );
XOR2X1TS U1360 ( .A(n718), .B(n738), .Y(n719) );
OAI21X1TS U1361 ( .A0(Op_MX[2]), .A1(Op_MX[14]), .B0(n526), .Y(n721) );
NAND2X1TS U1362 ( .A(Op_MX[2]), .B(Op_MX[14]), .Y(n720) );
XNOR2X1TS U1363 ( .A(n738), .B(n737), .Y(n722) );
OAI22X1TS U1364 ( .A0(n542), .A1(n465), .B0(n432), .B1(n723), .Y(n747) );
XNOR2X1TS U1365 ( .A(n466), .B(n553), .Y(n724) );
XNOR2X1TS U1366 ( .A(n1543), .B(n466), .Y(n742) );
OAI22X1TS U1367 ( .A0(n542), .A1(n724), .B0(n742), .B1(n432), .Y(n746) );
OAI21X1TS U1368 ( .A0(n727), .A1(n726), .B0(n725), .Y(n732) );
INVX2TS U1369 ( .A(n728), .Y(n730) );
XNOR2X4TS U1370 ( .A(n732), .B(n731), .Y(n1597) );
XNOR2X1TS U1371 ( .A(n1597), .B(n460), .Y(n745) );
OAI22X1TS U1372 ( .A0(n745), .A1(n476), .B0(n733), .B1(n1523), .Y(n734) );
NOR2X1TS U1373 ( .A(n735), .B(n734), .Y(n1418) );
NAND2X1TS U1374 ( .A(n735), .B(n734), .Y(n1419) );
NOR2X1TS U1375 ( .A(Op_MX[15]), .B(Op_MX[3]), .Y(n736) );
NAND2X1TS U1376 ( .A(n738), .B(n737), .Y(n739) );
NOR2BX1TS U1377 ( .AN(n553), .B(n518), .Y(n762) );
XNOR2X1TS U1378 ( .A(n1609), .B(n466), .Y(n751) );
OAI22X1TS U1379 ( .A0(n751), .A1(n431), .B0(n542), .B1(n742), .Y(n761) );
INVX2TS U1380 ( .A(n743), .Y(n765) );
NAND2X2TS U1381 ( .A(n765), .B(n763), .Y(n744) );
XNOR2X4TS U1382 ( .A(n1439), .B(n744), .Y(n1504) );
XNOR2X1TS U1383 ( .A(n1504), .B(n460), .Y(n771) );
OAI22X1TS U1384 ( .A0(n771), .A1(n1525), .B0(n745), .B1(n1523), .Y(n760) );
ADDHX1TS U1385 ( .A(n747), .B(n746), .CO(n748), .S(n735) );
NAND2X1TS U1386 ( .A(n749), .B(n748), .Y(n1415) );
INVX2TS U1387 ( .A(n1415), .Y(n750) );
XNOR2X1TS U1388 ( .A(n1597), .B(n466), .Y(n1506) );
OAI22X1TS U1389 ( .A0(n1506), .A1(n432), .B0(n751), .B1(n543), .Y(n776) );
XOR2X1TS U1390 ( .A(Op_MX[15]), .B(Op_MX[16]), .Y(n806) );
NOR2X1TS U1391 ( .A(n806), .B(n752), .Y(n753) );
XNOR2X2TS U1392 ( .A(Op_MX[17]), .B(n435), .Y(n1433) );
XOR2X1TS U1393 ( .A(n753), .B(n1433), .Y(n754) );
OAI21X1TS U1394 ( .A0(Op_MX[4]), .A1(Op_MX[16]), .B0(Op_MX[3]), .Y(n756) );
NAND2X1TS U1395 ( .A(Op_MX[4]), .B(Op_MX[16]), .Y(n755) );
NAND2X2TS U1396 ( .A(n756), .B(n755), .Y(n1432) );
XNOR2X1TS U1397 ( .A(n1433), .B(n1432), .Y(n757) );
INVX2TS U1398 ( .A(n478), .Y(n1485) );
XNOR2X1TS U1399 ( .A(n478), .B(n1608), .Y(n759) );
XNOR2X1TS U1400 ( .A(n1543), .B(n478), .Y(n1494) );
OAI22X1TS U1401 ( .A0(n544), .A1(n759), .B0(n1494), .B1(n518), .Y(n1625) );
CMPR32X2TS U1402 ( .A(n762), .B(n761), .C(n760), .CO(n774), .S(n749) );
INVX2TS U1403 ( .A(n763), .Y(n764) );
INVX2TS U1404 ( .A(n766), .Y(n768) );
NAND2X1TS U1405 ( .A(n768), .B(n767), .Y(n769) );
CLKXOR2X4TS U1406 ( .A(n770), .B(n769), .Y(n1502) );
XNOR2X1TS U1407 ( .A(n1502), .B(n461), .Y(n1524) );
OAI22X1TS U1408 ( .A0(n1524), .A1(n476), .B0(n771), .B1(n1521), .Y(n772) );
NOR2X2TS U1409 ( .A(n773), .B(n772), .Y(n1410) );
OAI21X4TS U1410 ( .A0(n1413), .A1(n1410), .B0(n1411), .Y(n1408) );
CMPR32X2TS U1411 ( .A(n776), .B(n775), .C(n774), .CO(n777), .S(n773) );
NAND2X1TS U1412 ( .A(DP_OP_111J22_123_4462_n366), .B(n777), .Y(n1407) );
INVX2TS U1413 ( .A(n1407), .Y(n778) );
AOI21X4TS U1414 ( .A0(n1408), .A1(n597), .B0(n778), .Y(n1399) );
INVX2TS U1415 ( .A(n1404), .Y(n1400) );
NAND2X2TS U1416 ( .A(DP_OP_111J22_123_4462_n356), .B(
DP_OP_111J22_123_4462_n360), .Y(n1401) );
INVX2TS U1417 ( .A(n1401), .Y(n779) );
AOI21X4TS U1418 ( .A0(n1400), .A1(n591), .B0(n779), .Y(n780) );
INVX2TS U1419 ( .A(n1396), .Y(n783) );
AOI21X4TS U1420 ( .A0(n1398), .A1(n782), .B0(n783), .Y(n1387) );
OR2X4TS U1421 ( .A(DP_OP_111J22_123_4462_n335), .B(
DP_OP_111J22_123_4462_n342), .Y(n1390) );
NAND2X2TS U1422 ( .A(n1390), .B(n405), .Y(n786) );
NAND2X2TS U1423 ( .A(DP_OP_111J22_123_4462_n343), .B(
DP_OP_111J22_123_4462_n348), .Y(n1393) );
INVX2TS U1424 ( .A(n1393), .Y(n1388) );
NAND2X2TS U1425 ( .A(DP_OP_111J22_123_4462_n335), .B(
DP_OP_111J22_123_4462_n342), .Y(n1389) );
INVX2TS U1426 ( .A(n1389), .Y(n784) );
OAI21X4TS U1427 ( .A0(n1387), .A1(n786), .B0(n785), .Y(n1381) );
NAND2X2TS U1428 ( .A(DP_OP_111J22_123_4462_n327), .B(
DP_OP_111J22_123_4462_n334), .Y(n1537) );
NAND2X2TS U1429 ( .A(DP_OP_111J22_123_4462_n319), .B(
DP_OP_111J22_123_4462_n326), .Y(n1383) );
AOI21X4TS U1430 ( .A0(n1381), .A1(n788), .B0(n787), .Y(n852) );
NOR2X4TS U1431 ( .A(DP_OP_111J22_123_4462_n310), .B(
DP_OP_111J22_123_4462_n318), .Y(n862) );
NOR2X4TS U1432 ( .A(n864), .B(n862), .Y(n1371) );
OR2X8TS U1433 ( .A(n852), .B(n790), .Y(n791) );
NAND2X8TS U1434 ( .A(n792), .B(n791), .Y(n1583) );
INVX2TS U1435 ( .A(n883), .Y(n924) );
NAND2X1TS U1436 ( .A(n924), .B(n922), .Y(n793) );
NOR2X2TS U1437 ( .A(mult_x_23_n223), .B(mult_x_23_n230), .Y(n1232) );
NOR2X2TS U1438 ( .A(mult_x_23_n231), .B(mult_x_23_n238), .Y(n1325) );
NOR2X2TS U1439 ( .A(n1232), .B(n1325), .Y(n835) );
NOR2X2TS U1440 ( .A(mult_x_23_n252), .B(mult_x_23_n256), .Y(n1246) );
NOR2X2TS U1441 ( .A(mult_x_23_n257), .B(mult_x_23_n261), .Y(n1251) );
NOR2X1TS U1442 ( .A(n1246), .B(n1251), .Y(n830) );
BUFX3TS U1443 ( .A(Op_MY[13]), .Y(n1356) );
XNOR2X1TS U1444 ( .A(n451), .B(n1356), .Y(n795) );
XNOR2X1TS U1445 ( .A(n451), .B(Op_MY[14]), .Y(n799) );
OAI22X1TS U1446 ( .A0(n1361), .A1(n795), .B0(n799), .B1(n589), .Y(n798) );
NOR2BX1TS U1447 ( .AN(n1362), .B(n486), .Y(n797) );
NOR2X1TS U1448 ( .A(n798), .B(n797), .Y(n1272) );
OAI22X1TS U1449 ( .A0(n1361), .A1(n1362), .B0(n795), .B1(n589), .Y(n1322) );
NAND2X1TS U1450 ( .A(n796), .B(n1361), .Y(n1321) );
NAND2X1TS U1451 ( .A(n1322), .B(n1321), .Y(n1323) );
NAND2X1TS U1452 ( .A(n798), .B(n797), .Y(n1273) );
XNOR2X1TS U1453 ( .A(n452), .B(n440), .Y(n808) );
OAI22X1TS U1454 ( .A0(n1361), .A1(n799), .B0(n808), .B1(n700), .Y(n811) );
XOR2X1TS U1455 ( .A(n505), .B(Op_MX[14]), .Y(n800) );
XNOR2X1TS U1456 ( .A(n506), .B(n1362), .Y(n801) );
XNOR2X1TS U1457 ( .A(n506), .B(n1356), .Y(n809) );
OAI22X1TS U1458 ( .A0(n531), .A1(n801), .B0(n809), .B1(n487), .Y(n810) );
OAI22X1TS U1459 ( .A0(n532), .A1(n421), .B0(n487), .B1(n802), .Y(n803) );
INVX2TS U1460 ( .A(n1269), .Y(n805) );
INVX2TS U1461 ( .A(n806), .Y(n807) );
NOR2BX1TS U1462 ( .AN(n552), .B(n489), .Y(n821) );
XNOR2X1TS U1463 ( .A(n452), .B(n441), .Y(n817) );
OAI22X1TS U1464 ( .A0(n1320), .A1(n808), .B0(n817), .B1(n589), .Y(n820) );
XNOR2X1TS U1465 ( .A(n506), .B(Op_MY[14]), .Y(n814) );
OAI22X1TS U1466 ( .A0(n532), .A1(n809), .B0(n814), .B1(n486), .Y(n819) );
NOR2X1TS U1467 ( .A(n813), .B(n812), .Y(n1264) );
NAND2X1TS U1468 ( .A(n813), .B(n812), .Y(n1265) );
OAI21X2TS U1469 ( .A0(n1267), .A1(n1264), .B0(n1265), .Y(n1263) );
XNOR2X1TS U1470 ( .A(n506), .B(n440), .Y(n1317) );
OAI22X1TS U1471 ( .A0(n532), .A1(n814), .B0(n1317), .B1(n486), .Y(n827) );
XOR2X1TS U1472 ( .A(n507), .B(Op_MX[16]), .Y(n815) );
XNOR2X1TS U1473 ( .A(n508), .B(n552), .Y(n816) );
XNOR2X1TS U1474 ( .A(n508), .B(n1356), .Y(n1311) );
OAI22X1TS U1475 ( .A0(n1345), .A1(n816), .B0(n1311), .B1(n490), .Y(n826) );
XNOR2X1TS U1476 ( .A(n452), .B(n442), .Y(n1319) );
OAI22X1TS U1477 ( .A0(n1361), .A1(n817), .B0(n1319), .B1(n589), .Y(n1369) );
OAI22X1TS U1478 ( .A0(n1345), .A1(n419), .B0(n489), .B1(n818), .Y(n1368) );
CMPR32X2TS U1479 ( .A(n821), .B(n820), .C(n819), .CO(n822), .S(n813) );
NAND2X1TS U1480 ( .A(n823), .B(n822), .Y(n1261) );
INVX2TS U1481 ( .A(n1261), .Y(n824) );
CMPR32X2TS U1482 ( .A(n827), .B(n826), .C(n825), .CO(n828), .S(n823) );
NOR2X1TS U1483 ( .A(mult_x_23_n262), .B(n828), .Y(n1256) );
NAND2X1TS U1484 ( .A(mult_x_23_n262), .B(n828), .Y(n1257) );
OAI21X4TS U1485 ( .A0(n1259), .A1(n1256), .B0(n1257), .Y(n1245) );
NAND2X1TS U1486 ( .A(mult_x_23_n257), .B(mult_x_23_n261), .Y(n1252) );
NAND2X1TS U1487 ( .A(mult_x_23_n252), .B(mult_x_23_n256), .Y(n1247) );
NAND2X1TS U1488 ( .A(n595), .B(n594), .Y(n833) );
NAND2X1TS U1489 ( .A(mult_x_23_n245), .B(mult_x_23_n251), .Y(n1242) );
INVX2TS U1490 ( .A(n1242), .Y(n1238) );
NAND2X1TS U1491 ( .A(mult_x_23_n239), .B(mult_x_23_n244), .Y(n1239) );
INVX2TS U1492 ( .A(n1239), .Y(n831) );
AOI21X1TS U1493 ( .A0(n595), .A1(n1238), .B0(n831), .Y(n832) );
OAI21X4TS U1494 ( .A0(n1237), .A1(n833), .B0(n832), .Y(n1231) );
NAND2X1TS U1495 ( .A(mult_x_23_n231), .B(mult_x_23_n238), .Y(n1326) );
NAND2X1TS U1496 ( .A(mult_x_23_n223), .B(mult_x_23_n230), .Y(n1233) );
OAI21X1TS U1497 ( .A0(n1232), .A1(n1326), .B0(n1233), .Y(n834) );
AOI21X4TS U1498 ( .A0(n835), .A1(n1231), .B0(n834), .Y(n1207) );
NOR2X1TS U1499 ( .A(mult_x_23_n214), .B(mult_x_23_n222), .Y(n1220) );
NOR2X2TS U1500 ( .A(n1220), .B(n1222), .Y(n1209) );
NOR2X2TS U1501 ( .A(mult_x_23_n196), .B(mult_x_23_n203), .Y(n1215) );
NOR2X2TS U1502 ( .A(n1215), .B(n1210), .Y(n837) );
NAND2X1TS U1503 ( .A(n1209), .B(n837), .Y(n839) );
NAND2X2TS U1504 ( .A(mult_x_23_n214), .B(mult_x_23_n222), .Y(n1227) );
NAND2X1TS U1505 ( .A(mult_x_23_n188), .B(mult_x_23_n195), .Y(n1211) );
NOR2X2TS U1506 ( .A(mult_x_23_n182), .B(mult_x_23_n187), .Y(n1202) );
NOR2X2TS U1507 ( .A(mult_x_23_n181), .B(mult_x_23_n175), .Y(n1197) );
NOR2X1TS U1508 ( .A(n1202), .B(n1197), .Y(n1189) );
NAND2X1TS U1509 ( .A(n1189), .B(n1194), .Y(n1183) );
NOR2X2TS U1510 ( .A(mult_x_23_n169), .B(mult_x_23_n165), .Y(n1184) );
NOR2X1TS U1511 ( .A(n1183), .B(n1184), .Y(n842) );
NAND2X1TS U1512 ( .A(mult_x_23_n182), .B(mult_x_23_n187), .Y(n1203) );
NAND2X1TS U1513 ( .A(mult_x_23_n181), .B(mult_x_23_n175), .Y(n1198) );
OAI21X2TS U1514 ( .A0(n1203), .A1(n1197), .B0(n1198), .Y(n1190) );
NAND2X1TS U1515 ( .A(mult_x_23_n174), .B(mult_x_23_n170), .Y(n1193) );
INVX2TS U1516 ( .A(n1193), .Y(n840) );
AOI21X1TS U1517 ( .A0(n1190), .A1(n1194), .B0(n840), .Y(n1182) );
NAND2X1TS U1518 ( .A(mult_x_23_n169), .B(mult_x_23_n165), .Y(n1185) );
NOR2X1TS U1519 ( .A(mult_x_23_n162), .B(mult_x_23_n164), .Y(n1176) );
NAND2X1TS U1520 ( .A(mult_x_23_n162), .B(mult_x_23_n164), .Y(n1177) );
OAI21X2TS U1521 ( .A0(n1180), .A1(n1176), .B0(n1177), .Y(n1175) );
NAND2X1TS U1522 ( .A(mult_x_23_n161), .B(n843), .Y(n1172) );
INVX2TS U1523 ( .A(n1172), .Y(n844) );
AOI21X4TS U1524 ( .A0(n1175), .A1(n1173), .B0(n844), .Y(n851) );
CMPR32X2TS U1525 ( .A(n573), .B(n416), .C(mult_x_23_n160), .CO(n847), .S(
n843) );
XNOR2X1TS U1526 ( .A(n845), .B(n1986), .Y(n846) );
NAND2X1TS U1527 ( .A(n847), .B(n846), .Y(n848) );
NAND2X1TS U1528 ( .A(n849), .B(n848), .Y(n850) );
INVX4TS U1529 ( .A(n852), .Y(n1377) );
INVX2TS U1530 ( .A(n1371), .Y(n853) );
NOR2X1TS U1531 ( .A(n853), .B(n1372), .Y(n856) );
INVX2TS U1532 ( .A(n1370), .Y(n854) );
OAI21X1TS U1533 ( .A0(n854), .A1(n1372), .B0(n1373), .Y(n855) );
INVX2TS U1534 ( .A(n857), .Y(n859) );
NAND2X1TS U1535 ( .A(n859), .B(n858), .Y(n860) );
INVX2TS U1536 ( .A(n862), .Y(n1379) );
INVX2TS U1537 ( .A(n1378), .Y(n863) );
INVX2TS U1538 ( .A(n864), .Y(n866) );
NAND2X1TS U1539 ( .A(n866), .B(n865), .Y(n867) );
NOR2X2TS U1540 ( .A(n438), .B(Op_MY[9]), .Y(n1450) );
NOR2X1TS U1541 ( .A(Op_MY[22]), .B(Op_MY[10]), .Y(n891) );
INVX2TS U1542 ( .A(n891), .Y(n885) );
AND2X4TS U1543 ( .A(n884), .B(n885), .Y(n894) );
NAND2X1TS U1544 ( .A(n438), .B(Op_MY[9]), .Y(n1451) );
OAI21X4TS U1545 ( .A0(n1450), .A1(n1447), .B0(n1451), .Y(n889) );
NAND2X1TS U1546 ( .A(n890), .B(DP_OP_111J22_123_4462_n727), .Y(n870) );
AOI21X4TS U1547 ( .A0(n895), .A1(n894), .B0(n593), .Y(n1587) );
INVX6TS U1548 ( .A(n1587), .Y(n1508) );
XNOR2X1TS U1549 ( .A(n1508), .B(n483), .Y(n1467) );
NOR2X1TS U1550 ( .A(n1283), .B(n876), .Y(n874) );
XOR2X1TS U1551 ( .A(n874), .B(n873), .Y(n882) );
NOR2X1TS U1552 ( .A(Op_MX[19]), .B(n436), .Y(n875) );
XNOR2X1TS U1553 ( .A(n876), .B(n875), .Y(n880) );
XNOR2X2TS U1554 ( .A(Op_MX[19]), .B(n436), .Y(n1428) );
OAI21X1TS U1555 ( .A0(Op_MX[6]), .A1(Op_MX[18]), .B0(n435), .Y(n878) );
NAND2X1TS U1556 ( .A(Op_MX[6]), .B(Op_MX[18]), .Y(n877) );
NAND2X2TS U1557 ( .A(n878), .B(n877), .Y(n1426) );
NAND2X1TS U1558 ( .A(n1428), .B(n1426), .Y(n879) );
INVX2TS U1559 ( .A(n483), .Y(n1550) );
OAI22X2TS U1560 ( .A0(n1467), .A1(n549), .B0(n426), .B1(n1550), .Y(
DP_OP_111J22_123_4462_n263) );
XNOR2X1TS U1561 ( .A(Op_MY[11]), .B(n443), .Y(n1065) );
XNOR2X1TS U1562 ( .A(n472), .B(n401), .Y(n1064) );
NOR2X4TS U1563 ( .A(DP_OP_111J22_123_4462_n266), .B(
DP_OP_111J22_123_4462_n262), .Y(n938) );
NAND2X2TS U1564 ( .A(n1571), .B(n901), .Y(n912) );
XNOR2X1TS U1565 ( .A(n1508), .B(n475), .Y(n1459) );
INVX2TS U1566 ( .A(n475), .Y(n1542) );
OAI22X1TS U1567 ( .A0(n1459), .A1(n464), .B0(n504), .B1(n1542), .Y(n1585) );
INVX2TS U1568 ( .A(n1585), .Y(n906) );
AOI21X1TS U1569 ( .A0(n895), .A1(n884), .B0(n889), .Y(n887) );
NAND2X1TS U1570 ( .A(n885), .B(n890), .Y(n886) );
CLKXOR2X4TS U1571 ( .A(n887), .B(n886), .Y(n1511) );
INVX2TS U1572 ( .A(n1511), .Y(n1455) );
INVX2TS U1573 ( .A(n889), .Y(n892) );
OAI21X1TS U1574 ( .A0(n892), .A1(n891), .B0(n890), .Y(n893) );
AOI21X2TS U1575 ( .A0(n895), .A1(n894), .B0(n893), .Y(n896) );
CLKXOR2X4TS U1576 ( .A(n896), .B(Op_MY[11]), .Y(n1509) );
INVX2TS U1577 ( .A(n1509), .Y(n907) );
OAI22X1TS U1578 ( .A0(n1455), .A1(n530), .B0(n907), .B1(n454), .Y(n905) );
NAND2X2TS U1579 ( .A(DP_OP_111J22_123_4462_n278), .B(
DP_OP_111J22_123_4462_n272), .Y(n926) );
NAND2X2TS U1580 ( .A(DP_OP_111J22_123_4462_n271), .B(
DP_OP_111J22_123_4462_n267), .Y(n919) );
NAND2X2TS U1581 ( .A(DP_OP_111J22_123_4462_n266), .B(
DP_OP_111J22_123_4462_n262), .Y(n937) );
NAND2X1TS U1582 ( .A(DP_OP_111J22_123_4462_n261), .B(
DP_OP_111J22_123_4462_n259), .Y(n943) );
INVX2TS U1583 ( .A(n1579), .Y(n900) );
AOI21X4TS U1584 ( .A0(n1582), .A1(n901), .B0(n900), .Y(n913) );
OAI21X2TS U1585 ( .A0(n913), .A1(n916), .B0(n1572), .Y(n903) );
AOI21X2TS U1586 ( .A0(n1583), .A1(n904), .B0(n903), .Y(n911) );
CMPR32X2TS U1587 ( .A(n906), .B(n905), .C(DP_OP_111J22_123_4462_n257), .CO(
n909), .S(n902) );
OAI22X1TS U1588 ( .A0(n907), .A1(n530), .B0(n454), .B1(n1587), .Y(n1584) );
NAND2X1TS U1589 ( .A(n909), .B(n908), .Y(n1573) );
NAND2X1TS U1590 ( .A(n1575), .B(n1573), .Y(n910) );
INVX2TS U1591 ( .A(n912), .Y(n915) );
INVX2TS U1592 ( .A(n913), .Y(n914) );
AOI21X2TS U1593 ( .A0(n1583), .A1(n915), .B0(n914), .Y(n918) );
INVX2TS U1594 ( .A(n916), .Y(n1569) );
NAND2X1TS U1595 ( .A(n1569), .B(n1572), .Y(n917) );
AOI21X2TS U1596 ( .A0(n1583), .A1(n1571), .B0(n1582), .Y(n921) );
XOR2X4TS U1597 ( .A(n921), .B(n920), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N20) );
INVX2TS U1598 ( .A(n922), .Y(n923) );
INVX2TS U1599 ( .A(n925), .Y(n927) );
INVX2TS U1600 ( .A(n936), .Y(n932) );
INVX2TS U1601 ( .A(n939), .Y(n931) );
AOI21X2TS U1602 ( .A0(n1583), .A1(n932), .B0(n931), .Y(n935) );
INVX2TS U1603 ( .A(n938), .Y(n933) );
XOR2X4TS U1604 ( .A(n935), .B(n934), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N21) );
AOI21X2TS U1605 ( .A0(n1583), .A1(n941), .B0(n940), .Y(n946) );
INVX2TS U1606 ( .A(n942), .Y(n944) );
XOR2X4TS U1607 ( .A(n946), .B(n945), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N22) );
NAND2X1TS U1608 ( .A(n948), .B(n947), .Y(n949) );
XNOR2X1TS U1609 ( .A(n950), .B(n949), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N22) );
INVX2TS U1610 ( .A(n951), .Y(n953) );
NAND2X1TS U1611 ( .A(n953), .B(n952), .Y(n954) );
INVX2TS U1612 ( .A(n959), .Y(n961) );
NAND2X1TS U1613 ( .A(n961), .B(n960), .Y(n962) );
XNOR2X1TS U1614 ( .A(n963), .B(n962), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N20) );
INVX2TS U1615 ( .A(n964), .Y(n967) );
INVX2TS U1616 ( .A(n965), .Y(n966) );
OAI21X1TS U1617 ( .A0(n981), .A1(n967), .B0(n966), .Y(n971) );
NAND2X1TS U1618 ( .A(n969), .B(n968), .Y(n970) );
XNOR2X1TS U1619 ( .A(n971), .B(n970), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N19) );
INVX2TS U1620 ( .A(n972), .Y(n974) );
NAND2X1TS U1621 ( .A(n974), .B(n973), .Y(n975) );
XNOR2X1TS U1622 ( .A(n976), .B(n975), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N18) );
INVX2TS U1623 ( .A(n977), .Y(n979) );
NAND2X1TS U1624 ( .A(n979), .B(n978), .Y(n980) );
AOI21X2TS U1625 ( .A0(n1005), .A1(n984), .B0(n983), .Y(n994) );
INVX2TS U1626 ( .A(n985), .Y(n987) );
NAND2X1TS U1627 ( .A(n987), .B(n986), .Y(n988) );
XNOR2X1TS U1628 ( .A(n989), .B(n988), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N16) );
INVX2TS U1629 ( .A(n990), .Y(n992) );
NAND2X1TS U1630 ( .A(n992), .B(n991), .Y(n993) );
INVX2TS U1631 ( .A(n995), .Y(n1003) );
INVX2TS U1632 ( .A(n1002), .Y(n996) );
AOI21X1TS U1633 ( .A0(n1005), .A1(n1003), .B0(n996), .Y(n1001) );
INVX2TS U1634 ( .A(n997), .Y(n999) );
NAND2X1TS U1635 ( .A(n999), .B(n998), .Y(n1000) );
NAND2X1TS U1636 ( .A(n1003), .B(n1002), .Y(n1004) );
XNOR2X1TS U1637 ( .A(n1005), .B(n1004), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N13) );
INVX2TS U1638 ( .A(n1006), .Y(n1110) );
INVX2TS U1639 ( .A(n1007), .Y(n1009) );
NAND2X1TS U1640 ( .A(n1009), .B(n1008), .Y(n1010) );
XNOR2X1TS U1641 ( .A(n1011), .B(n1010), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N12) );
INVX2TS U1642 ( .A(n1012), .Y(n1020) );
AOI21X1TS U1643 ( .A0(n1020), .A1(n580), .B0(n1013), .Y(n1017) );
NAND2X1TS U1644 ( .A(n1015), .B(n1014), .Y(n1016) );
NAND2X1TS U1645 ( .A(n580), .B(n1018), .Y(n1019) );
XNOR2X1TS U1646 ( .A(n1020), .B(n1019), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N9) );
INVX2TS U1647 ( .A(n1021), .Y(n1031) );
INVX2TS U1648 ( .A(n1022), .Y(n1024) );
NAND2X1TS U1649 ( .A(n1024), .B(n1023), .Y(n1025) );
XNOR2X1TS U1650 ( .A(n1026), .B(n1025), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N8) );
INVX2TS U1651 ( .A(n1027), .Y(n1029) );
NAND2X1TS U1652 ( .A(n1029), .B(n1028), .Y(n1030) );
INVX2TS U1653 ( .A(n1032), .Y(n1034) );
NAND2X1TS U1654 ( .A(n1034), .B(n1033), .Y(n1036) );
XOR2X1TS U1655 ( .A(n1036), .B(n1035), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N6) );
INVX2TS U1656 ( .A(n1037), .Y(n1047) );
INVX2TS U1657 ( .A(n1038), .Y(n1040) );
NAND2X1TS U1658 ( .A(n1040), .B(n1039), .Y(n1041) );
XNOR2X1TS U1659 ( .A(n1042), .B(n1041), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N5) );
INVX2TS U1660 ( .A(n1043), .Y(n1045) );
NAND2X1TS U1661 ( .A(n1045), .B(n1044), .Y(n1046) );
INVX2TS U1662 ( .A(n1048), .Y(n1050) );
NAND2X1TS U1663 ( .A(n1050), .B(n1049), .Y(n1052) );
NAND2X1TS U1664 ( .A(n1054), .B(n1053), .Y(n1056) );
XNOR2X1TS U1665 ( .A(n1056), .B(n1055), .Y(
Sgf_operation_RECURSIVE_EVEN1_right_N2) );
OAI22X1TS U1666 ( .A0(n456), .A1(DP_OP_111J22_123_4462_n727), .B0(n501),
.B1(n1057), .Y(mult_x_55_n273) );
XNOR2X1TS U1667 ( .A(n472), .B(n444), .Y(n1059) );
OAI22X1TS U1668 ( .A0(n457), .A1(n1059), .B0(n500), .B1(n1058), .Y(
mult_x_55_n288) );
XNOR2X1TS U1669 ( .A(n472), .B(n397), .Y(n1060) );
OAI22X1TS U1670 ( .A0(n457), .A1(n1060), .B0(n501), .B1(n1059), .Y(
mult_x_55_n289) );
XNOR2X1TS U1671 ( .A(n472), .B(Op_MX[8]), .Y(n1061) );
OAI22X1TS U1672 ( .A0(n457), .A1(n1061), .B0(n501), .B1(n1060), .Y(
mult_x_55_n290) );
XNOR2X1TS U1673 ( .A(n472), .B(n400), .Y(n1062) );
OAI22X1TS U1674 ( .A0(n457), .A1(n1062), .B0(n500), .B1(n1061), .Y(
mult_x_55_n291) );
BUFX3TS U1675 ( .A(Op_MX[6]), .Y(n2358) );
XNOR2X1TS U1676 ( .A(n472), .B(n2358), .Y(n1063) );
OAI22X1TS U1677 ( .A0(n457), .A1(n1063), .B0(n501), .B1(n1062), .Y(
mult_x_55_n292) );
OAI22X1TS U1678 ( .A0(n457), .A1(n1064), .B0(n500), .B1(n1063), .Y(
mult_x_55_n293) );
XNOR2X1TS U1679 ( .A(Op_MY[11]), .B(n434), .Y(n1066) );
OAI22X1TS U1680 ( .A0(n456), .A1(n1066), .B0(n501), .B1(n1065), .Y(
mult_x_55_n295) );
XNOR2X1TS U1681 ( .A(Op_MY[11]), .B(n433), .Y(n1067) );
OAI22X1TS U1682 ( .A0(n456), .A1(n1067), .B0(n501), .B1(n1066), .Y(
mult_x_55_n296) );
XNOR2X1TS U1683 ( .A(n472), .B(Op_MX[1]), .Y(n1068) );
OAI22X1TS U1684 ( .A0(n456), .A1(n1068), .B0(n500), .B1(n1067), .Y(
mult_x_55_n297) );
XNOR2X1TS U1685 ( .A(n472), .B(n550), .Y(n1069) );
OAI22X1TS U1686 ( .A0(n457), .A1(n1069), .B0(n500), .B1(n1068), .Y(
mult_x_55_n298) );
NOR2BX1TS U1687 ( .AN(n550), .B(n500), .Y(mult_x_55_n299) );
XNOR2X1TS U1688 ( .A(n468), .B(n554), .Y(n1166) );
OAI22X1TS U1689 ( .A0(n540), .A1(n1166), .B0(n494), .B1(n584), .Y(
mult_x_55_n301) );
XNOR2X1TS U1690 ( .A(n468), .B(Op_MX[8]), .Y(n1071) );
XNOR2X1TS U1691 ( .A(n468), .B(n397), .Y(n1131) );
OAI22X1TS U1692 ( .A0(n540), .A1(n1071), .B0(n493), .B1(n1131), .Y(
mult_x_55_n304) );
XNOR2X1TS U1693 ( .A(Op_MY[9]), .B(n400), .Y(n1072) );
OAI22X1TS U1694 ( .A0(n541), .A1(n1072), .B0(n494), .B1(n1071), .Y(
mult_x_55_n305) );
XNOR2X1TS U1695 ( .A(n468), .B(n2358), .Y(n1073) );
OAI22X1TS U1696 ( .A0(n541), .A1(n1073), .B0(n494), .B1(n1072), .Y(
mult_x_55_n306) );
XNOR2X1TS U1697 ( .A(n468), .B(n401), .Y(n1126) );
OAI22X1TS U1698 ( .A0(n540), .A1(n1126), .B0(n493), .B1(n1073), .Y(
mult_x_55_n307) );
XNOR2X1TS U1699 ( .A(Op_MY[9]), .B(Op_MX[1]), .Y(n1100) );
XNOR2X1TS U1700 ( .A(Op_MY[9]), .B(n433), .Y(n1160) );
OAI22X1TS U1701 ( .A0(n541), .A1(n1100), .B0(n493), .B1(n1160), .Y(
mult_x_55_n311) );
XOR2X1TS U1702 ( .A(Op_MY[6]), .B(n509), .Y(n1074) );
XNOR2X1TS U1703 ( .A(n510), .B(n444), .Y(n1075) );
XNOR2X1TS U1704 ( .A(n509), .B(n554), .Y(n1132) );
OAI22X1TS U1705 ( .A0(n1154), .A1(n1075), .B0(n511), .B1(n1132), .Y(
mult_x_55_n316) );
XNOR2X1TS U1706 ( .A(Op_MY[7]), .B(n397), .Y(n1118) );
OAI22X1TS U1707 ( .A0(n1154), .A1(n1118), .B0(n512), .B1(n1075), .Y(
mult_x_55_n317) );
XNOR2X1TS U1708 ( .A(n510), .B(n2358), .Y(n1076) );
XNOR2X1TS U1709 ( .A(n510), .B(n400), .Y(n1123) );
OAI22X1TS U1710 ( .A0(n1154), .A1(n1076), .B0(n513), .B1(n1123), .Y(
mult_x_55_n320) );
XNOR2X1TS U1711 ( .A(n510), .B(n401), .Y(n1077) );
OAI22X1TS U1712 ( .A0(n1154), .A1(n1077), .B0(n512), .B1(n1076), .Y(
mult_x_55_n321) );
XNOR2X1TS U1713 ( .A(n510), .B(n443), .Y(n1078) );
OAI22X1TS U1714 ( .A0(n1154), .A1(n1078), .B0(n513), .B1(n1077), .Y(
mult_x_55_n322) );
XNOR2X1TS U1715 ( .A(Op_MY[7]), .B(n434), .Y(n1111) );
OAI22X1TS U1716 ( .A0(n1154), .A1(n1111), .B0(n513), .B1(n1078), .Y(
mult_x_55_n323) );
XNOR2X1TS U1717 ( .A(n510), .B(n550), .Y(n1079) );
XNOR2X1TS U1718 ( .A(n510), .B(Op_MX[1]), .Y(n1137) );
OAI22X1TS U1719 ( .A0(n539), .A1(n1079), .B0(n513), .B1(n1137), .Y(
mult_x_55_n326) );
NOR2BX1TS U1720 ( .AN(n550), .B(n512), .Y(mult_x_55_n327) );
XNOR2X1TS U1721 ( .A(n450), .B(n554), .Y(n1080) );
OAI22X1TS U1722 ( .A0(n1148), .A1(n1080), .B0(n1146), .B1(n418), .Y(
mult_x_55_n329) );
XNOR2X1TS U1723 ( .A(Op_MY[5]), .B(n444), .Y(n1081) );
OAI22X1TS U1724 ( .A0(n1148), .A1(n1081), .B0(n1146), .B1(n1080), .Y(
mult_x_55_n330) );
XNOR2X1TS U1725 ( .A(Op_MY[5]), .B(n397), .Y(n1127) );
OAI22X1TS U1726 ( .A0(n1148), .A1(n1127), .B0(n1146), .B1(n1081), .Y(
mult_x_55_n331) );
XNOR2X1TS U1727 ( .A(n450), .B(n2358), .Y(n1082) );
XNOR2X1TS U1728 ( .A(Op_MY[5]), .B(n400), .Y(n1147) );
OAI22X1TS U1729 ( .A0(n1148), .A1(n1082), .B0(n470), .B1(n1147), .Y(
mult_x_55_n334) );
XNOR2X1TS U1730 ( .A(n450), .B(n401), .Y(n1113) );
OAI22X1TS U1731 ( .A0(n538), .A1(n1113), .B0(n470), .B1(n1082), .Y(
mult_x_55_n335) );
XNOR2X1TS U1732 ( .A(n450), .B(n434), .Y(n1083) );
XNOR2X1TS U1733 ( .A(n450), .B(n443), .Y(n1114) );
OAI22X1TS U1734 ( .A0(n538), .A1(n1083), .B0(n470), .B1(n1114), .Y(
mult_x_55_n337) );
XNOR2X1TS U1735 ( .A(n450), .B(n433), .Y(n1084) );
OAI22X1TS U1736 ( .A0(n538), .A1(n1084), .B0(n470), .B1(n1083), .Y(
mult_x_55_n338) );
OAI22X1TS U1737 ( .A0(n1148), .A1(n1085), .B0(n470), .B1(n1084), .Y(
mult_x_55_n339) );
XNOR2X1TS U1738 ( .A(n498), .B(n554), .Y(n1086) );
OAI22X1TS U1739 ( .A0(n1140), .A1(n1086), .B0(n428), .B1(n415), .Y(
mult_x_55_n343) );
XNOR2X1TS U1740 ( .A(n498), .B(n444), .Y(n1087) );
OAI22X1TS U1741 ( .A0(n1140), .A1(n1087), .B0(n429), .B1(n1086), .Y(
mult_x_55_n344) );
XNOR2X1TS U1742 ( .A(n498), .B(n397), .Y(n1088) );
OAI22X1TS U1743 ( .A0(n1140), .A1(n1088), .B0(n428), .B1(n1087), .Y(
mult_x_55_n345) );
XNOR2X1TS U1744 ( .A(n498), .B(Op_MX[8]), .Y(n1089) );
OAI22X1TS U1745 ( .A0(n537), .A1(n1089), .B0(n428), .B1(n1088), .Y(
mult_x_55_n346) );
XNOR2X1TS U1746 ( .A(n498), .B(n400), .Y(n1090) );
OAI22X1TS U1747 ( .A0(n1140), .A1(n1090), .B0(n429), .B1(n1089), .Y(
mult_x_55_n347) );
XNOR2X1TS U1748 ( .A(n498), .B(n2358), .Y(n1138) );
OAI22X1TS U1749 ( .A0(n537), .A1(n1138), .B0(n428), .B1(n1090), .Y(
mult_x_55_n348) );
XNOR2X1TS U1750 ( .A(n498), .B(n443), .Y(n1091) );
XNOR2X1TS U1751 ( .A(n498), .B(n401), .Y(n1139) );
OAI22X1TS U1752 ( .A0(n537), .A1(n1091), .B0(n429), .B1(n1139), .Y(
mult_x_55_n350) );
OAI22X1TS U1753 ( .A0(n537), .A1(n1092), .B0(n429), .B1(n1091), .Y(
mult_x_55_n351) );
XNOR2X1TS U1754 ( .A(n469), .B(n554), .Y(n1161) );
OAI22X1TS U1755 ( .A0(n1095), .A1(n1161), .B0(n566), .B1(n403), .Y(
mult_x_55_n357) );
XNOR2X1TS U1756 ( .A(n469), .B(n397), .Y(n1102) );
XNOR2X1TS U1757 ( .A(n469), .B(n444), .Y(n1162) );
OAI22X1TS U1758 ( .A0(n1163), .A1(n1102), .B0(n1162), .B1(n566), .Y(
mult_x_55_n359) );
XNOR2X1TS U1759 ( .A(n1093), .B(n400), .Y(n1155) );
XNOR2X1TS U1760 ( .A(n469), .B(Op_MX[8]), .Y(n1103) );
OAI22X1TS U1761 ( .A0(n1163), .A1(n1155), .B0(n1103), .B1(n566), .Y(
mult_x_55_n361) );
XNOR2X1TS U1762 ( .A(n1093), .B(n2358), .Y(n1156) );
OAI22X1TS U1763 ( .A0(n1095), .A1(n1094), .B0(n1156), .B1(n455), .Y(
mult_x_55_n363) );
XNOR2X1TS U1764 ( .A(n468), .B(n1152), .Y(n1101) );
OAI22X1TS U1765 ( .A0(n541), .A1(n1101), .B0(n494), .B1(n1100), .Y(n1105) );
OAI22X1TS U1766 ( .A0(n1163), .A1(n1103), .B0(n1102), .B1(n566), .Y(n1104)
);
ADDHX1TS U1767 ( .A(n1105), .B(n1104), .CO(mult_x_55_n250), .S(
mult_x_55_n251) );
NOR2X1TS U1768 ( .A(n471), .B(n586), .Y(mult_x_55_n282) );
INVX2TS U1769 ( .A(n1106), .Y(n1108) );
NAND2X1TS U1770 ( .A(n1108), .B(n1107), .Y(n1109) );
NOR2X1TS U1771 ( .A(DP_OP_111J22_123_4462_n727), .B(n579), .Y(mult_x_55_n280) );
INVX2TS U1772 ( .A(mult_x_55_n194), .Y(mult_x_55_n195) );
NOR2X1TS U1773 ( .A(DP_OP_111J22_123_4462_n727), .B(n575), .Y(mult_x_55_n168) );
INVX2TS U1774 ( .A(mult_x_55_n168), .Y(mult_x_55_n169) );
XNOR2X1TS U1775 ( .A(n510), .B(n433), .Y(n1136) );
OAI22X1TS U1776 ( .A0(n539), .A1(n1136), .B0(n513), .B1(n1111), .Y(n1117) );
OAI22X1TS U1777 ( .A0(n541), .A1(n584), .B0(n494), .B1(n1112), .Y(n1116) );
OAI22X1TS U1778 ( .A0(n538), .A1(n1114), .B0(n470), .B1(n1113), .Y(n1115) );
CMPR32X2TS U1779 ( .A(n1117), .B(n1116), .C(n1115), .CO(mult_x_55_n248), .S(
mult_x_55_n249) );
XNOR2X1TS U1780 ( .A(n510), .B(Op_MX[8]), .Y(n1122) );
OAI22X1TS U1781 ( .A0(n1154), .A1(n1122), .B0(n512), .B1(n1118), .Y(n1119)
);
CMPR32X2TS U1782 ( .A(n1121), .B(n1120), .C(n1119), .CO(mult_x_55_n202), .S(
mult_x_55_n203) );
NOR2X1TS U1783 ( .A(DP_OP_111J22_123_4462_n727), .B(n572), .Y(n1125) );
INVX2TS U1784 ( .A(n1121), .Y(n1130) );
OAI22X1TS U1785 ( .A0(n539), .A1(n1123), .B0(n512), .B1(n1122), .Y(n1124) );
CMPR32X2TS U1786 ( .A(n1125), .B(n1130), .C(n1124), .CO(mult_x_55_n210), .S(
mult_x_55_n211) );
XNOR2X1TS U1787 ( .A(n468), .B(n443), .Y(n1144) );
OAI22X1TS U1788 ( .A0(n540), .A1(n1144), .B0(n493), .B1(n1126), .Y(n1129) );
XNOR2X1TS U1789 ( .A(Op_MY[5]), .B(Op_MX[8]), .Y(n1145) );
OAI22X1TS U1790 ( .A0(n1148), .A1(n1145), .B0(n1146), .B1(n1127), .Y(n1128)
);
CMPR32X2TS U1791 ( .A(n1130), .B(n1129), .C(n1128), .CO(mult_x_55_n220), .S(
mult_x_55_n221) );
INVX2TS U1792 ( .A(n1171), .Y(n1135) );
XNOR2X1TS U1793 ( .A(n468), .B(n444), .Y(n1167) );
OAI22X1TS U1794 ( .A0(n541), .A1(n1131), .B0(n494), .B1(n1167), .Y(n1134) );
OAI22X1TS U1795 ( .A0(n539), .A1(n1132), .B0(n513), .B1(n413), .Y(n1133) );
CMPR32X2TS U1796 ( .A(n1135), .B(n1134), .C(n1133), .CO(mult_x_55_n178), .S(
mult_x_55_n179) );
NOR2BX1TS U1797 ( .AN(n550), .B(n494), .Y(n1143) );
OAI22X1TS U1798 ( .A0(n1154), .A1(n1137), .B0(n512), .B1(n1136), .Y(n1142)
);
OAI22X1TS U1799 ( .A0(n1140), .A1(n1139), .B0(n428), .B1(n1138), .Y(n1141)
);
CMPR32X2TS U1800 ( .A(n1143), .B(n1142), .C(n1141), .CO(mult_x_55_n255), .S(
mult_x_55_n256) );
NOR2BX1TS U1801 ( .AN(n1152), .B(n471), .Y(n1151) );
XNOR2X1TS U1802 ( .A(n468), .B(n434), .Y(n1159) );
OAI22X1TS U1803 ( .A0(n541), .A1(n1159), .B0(n494), .B1(n1144), .Y(n1150) );
OAI22X1TS U1804 ( .A0(n1148), .A1(n1147), .B0(n1146), .B1(n1145), .Y(n1149)
);
CMPR32X2TS U1805 ( .A(n1151), .B(n1150), .C(n1149), .CO(mult_x_55_n229), .S(
mult_x_55_n230) );
OAI22X1TS U1806 ( .A0(n1154), .A1(n413), .B0(n513), .B1(n1153), .Y(n1158) );
OAI22X1TS U1807 ( .A0(n1163), .A1(n1156), .B0(n1155), .B1(n566), .Y(n1157)
);
ADDHXLTS U1808 ( .A(n1158), .B(n1157), .CO(mult_x_55_n260), .S(
mult_x_55_n261) );
OAI22X1TS U1809 ( .A0(n541), .A1(n1160), .B0(n494), .B1(n1159), .Y(n1165) );
OAI22X1TS U1810 ( .A0(n1163), .A1(n1162), .B0(n1161), .B1(n566), .Y(n1164)
);
ADDHX1TS U1811 ( .A(n1165), .B(n1164), .CO(mult_x_55_n237), .S(
mult_x_55_n238) );
OAI22X1TS U1812 ( .A0(n541), .A1(n1167), .B0(n493), .B1(n1166), .Y(n1169) );
CMPR32X2TS U1813 ( .A(n1171), .B(n1170), .C(n1169), .CO(mult_x_55_n173), .S(
mult_x_55_n174) );
NAND2X1TS U1814 ( .A(n1173), .B(n1172), .Y(n1174) );
XNOR2X1TS U1815 ( .A(n1175), .B(n1174), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N22) );
INVX2TS U1816 ( .A(n1176), .Y(n1178) );
NAND2X1TS U1817 ( .A(n1178), .B(n1177), .Y(n1179) );
INVX2TS U1818 ( .A(n1184), .Y(n1186) );
NAND2X1TS U1819 ( .A(n1186), .B(n1185), .Y(n1187) );
XNOR2X1TS U1820 ( .A(n1188), .B(n1187), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N20) );
INVX2TS U1821 ( .A(n1189), .Y(n1192) );
NAND2X1TS U1822 ( .A(n1194), .B(n1193), .Y(n1195) );
XNOR2X1TS U1823 ( .A(n1196), .B(n1195), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N19) );
INVX2TS U1824 ( .A(n1197), .Y(n1199) );
NAND2X1TS U1825 ( .A(n1199), .B(n1198), .Y(n1200) );
XNOR2X1TS U1826 ( .A(n1201), .B(n1200), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N18) );
INVX2TS U1827 ( .A(n1202), .Y(n1204) );
NAND2X1TS U1828 ( .A(n1204), .B(n1203), .Y(n1205) );
INVX4TS U1829 ( .A(n1207), .Y(n1230) );
INVX2TS U1830 ( .A(n1210), .Y(n1212) );
NAND2X1TS U1831 ( .A(n1212), .B(n1211), .Y(n1213) );
XNOR2X1TS U1832 ( .A(n1214), .B(n1213), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N16) );
INVX2TS U1833 ( .A(n1215), .Y(n1217) );
NAND2X1TS U1834 ( .A(n1217), .B(n1216), .Y(n1218) );
INVX2TS U1835 ( .A(n1220), .Y(n1228) );
INVX2TS U1836 ( .A(n1227), .Y(n1221) );
AOI21X1TS U1837 ( .A0(n1230), .A1(n1228), .B0(n1221), .Y(n1226) );
INVX2TS U1838 ( .A(n1222), .Y(n1224) );
NAND2X1TS U1839 ( .A(n1224), .B(n1223), .Y(n1225) );
NAND2X1TS U1840 ( .A(n1228), .B(n1227), .Y(n1229) );
XNOR2X1TS U1841 ( .A(n1230), .B(n1229), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N13) );
INVX2TS U1842 ( .A(n1231), .Y(n1329) );
INVX2TS U1843 ( .A(n1232), .Y(n1234) );
NAND2X1TS U1844 ( .A(n1234), .B(n1233), .Y(n1235) );
XNOR2X1TS U1845 ( .A(n1236), .B(n1235), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N12) );
INVX2TS U1846 ( .A(n1237), .Y(n1244) );
AOI21X1TS U1847 ( .A0(n1244), .A1(n594), .B0(n1238), .Y(n1241) );
NAND2X1TS U1848 ( .A(n595), .B(n1239), .Y(n1240) );
NAND2X1TS U1849 ( .A(n594), .B(n1242), .Y(n1243) );
XNOR2X1TS U1850 ( .A(n1244), .B(n1243), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N9) );
INVX2TS U1851 ( .A(n1245), .Y(n1255) );
INVX2TS U1852 ( .A(n1246), .Y(n1248) );
NAND2X1TS U1853 ( .A(n1248), .B(n1247), .Y(n1249) );
XNOR2X1TS U1854 ( .A(n1250), .B(n1249), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N8) );
INVX2TS U1855 ( .A(n1251), .Y(n1253) );
NAND2X1TS U1856 ( .A(n1253), .B(n1252), .Y(n1254) );
INVX2TS U1857 ( .A(n1256), .Y(n1258) );
NAND2X1TS U1858 ( .A(n1258), .B(n1257), .Y(n1260) );
NAND2X1TS U1859 ( .A(n582), .B(n1261), .Y(n1262) );
XNOR2X1TS U1860 ( .A(n1263), .B(n1262), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N5) );
INVX2TS U1861 ( .A(n1264), .Y(n1266) );
NAND2X1TS U1862 ( .A(n1266), .B(n1265), .Y(n1268) );
XOR2X1TS U1863 ( .A(n1268), .B(n1267), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N4) );
NAND2X1TS U1864 ( .A(n570), .B(n1269), .Y(n1271) );
XNOR2X1TS U1865 ( .A(n1271), .B(n1270), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N3) );
INVX2TS U1866 ( .A(n1272), .Y(n1274) );
NAND2X1TS U1867 ( .A(n1274), .B(n1273), .Y(n1275) );
OAI22X1TS U1868 ( .A0(n449), .A1(n555), .B0(n481), .B1(n399), .Y(n1276) );
CMPR32X2TS U1869 ( .A(n1330), .B(Op_MY[19]), .C(n1276), .CO(mult_x_23_n171),
.S(mult_x_23_n172) );
OAI22X1TS U1870 ( .A0(n448), .A1(n398), .B0(n480), .B1(n442), .Y(n1277) );
CMPR32X2TS U1871 ( .A(n1356), .B(n440), .C(n1277), .CO(mult_x_23_n200), .S(
mult_x_23_n201) );
OAI22X1TS U1872 ( .A0(n449), .A1(Op_MY[14]), .B0(n481), .B1(n440), .Y(n1280)
);
XNOR2X1TS U1873 ( .A(n508), .B(n555), .Y(n1306) );
XNOR2X1TS U1874 ( .A(n507), .B(n399), .Y(n1305) );
OAI22X1TS U1875 ( .A0(n1345), .A1(n1306), .B0(n1305), .B1(n490), .Y(n1279)
);
CMPR32X2TS U1876 ( .A(n588), .B(n1280), .C(n1279), .CO(mult_x_23_n218), .S(
mult_x_23_n219) );
OAI22X1TS U1877 ( .A0(n449), .A1(n1356), .B0(n481), .B1(n529), .Y(n1282) );
OAI22X1TS U1878 ( .A0(n449), .A1(n438), .B0(n481), .B1(n1986), .Y(
mult_x_23_n281) );
OAI22X1TS U1879 ( .A0(n448), .A1(n1330), .B0(n480), .B1(Op_MY[19]), .Y(
mult_x_23_n284) );
OAI22X1TS U1880 ( .A0(n448), .A1(n442), .B0(n480), .B1(n1330), .Y(
mult_x_23_n285) );
NOR2BX1TS U1881 ( .AN(n1362), .B(n480), .Y(mult_x_23_n291) );
XOR2X1TS U1882 ( .A(n521), .B(Op_MX[20]), .Y(n1284) );
INVX2TS U1883 ( .A(n521), .Y(n1364) );
OAI22X1TS U1884 ( .A0(n536), .A1(n521), .B0(n495), .B1(n1364), .Y(
mult_x_23_n293) );
XNOR2X1TS U1885 ( .A(n520), .B(n1986), .Y(n1285) );
OAI22X1TS U1886 ( .A0(n536), .A1(n1285), .B0(n495), .B1(n520), .Y(
mult_x_23_n294) );
XNOR2X1TS U1887 ( .A(n520), .B(n399), .Y(n1286) );
OAI22X1TS U1888 ( .A0(n536), .A1(n1286), .B0(n1285), .B1(n495), .Y(
mult_x_23_n295) );
XNOR2X1TS U1889 ( .A(n520), .B(n555), .Y(n1287) );
OAI22X1TS U1890 ( .A0(n535), .A1(n1287), .B0(n1286), .B1(n495), .Y(
mult_x_23_n296) );
XNOR2X1TS U1891 ( .A(n521), .B(Op_MY[19]), .Y(n1288) );
OAI22X1TS U1892 ( .A0(n535), .A1(n1288), .B0(n1287), .B1(n496), .Y(
mult_x_23_n297) );
XNOR2X1TS U1893 ( .A(n521), .B(n1330), .Y(n1289) );
OAI22X1TS U1894 ( .A0(n536), .A1(n1289), .B0(n1288), .B1(n496), .Y(
mult_x_23_n298) );
XNOR2X1TS U1895 ( .A(n521), .B(n442), .Y(n1290) );
OAI22X1TS U1896 ( .A0(n536), .A1(n1290), .B0(n1289), .B1(n496), .Y(
mult_x_23_n299) );
XNOR2X1TS U1897 ( .A(n520), .B(n398), .Y(n1291) );
OAI22X1TS U1898 ( .A0(n535), .A1(n1291), .B0(n1290), .B1(n496), .Y(
mult_x_23_n300) );
XNOR2X1TS U1899 ( .A(n521), .B(n440), .Y(n1292) );
OAI22X1TS U1900 ( .A0(n536), .A1(n1292), .B0(n1291), .B1(n496), .Y(
mult_x_23_n301) );
XNOR2X1TS U1901 ( .A(n520), .B(Op_MY[14]), .Y(n1293) );
OAI22X1TS U1902 ( .A0(n536), .A1(n1293), .B0(n1292), .B1(n496), .Y(
mult_x_23_n302) );
XNOR2X1TS U1903 ( .A(n520), .B(n1356), .Y(n1341) );
OAI22X1TS U1904 ( .A0(n536), .A1(n1341), .B0(n1293), .B1(n496), .Y(
mult_x_23_n303) );
XOR2X1TS U1905 ( .A(Op_MX[19]), .B(Op_MX[18]), .Y(n1294) );
XNOR2X1TS U1906 ( .A(Op_MX[19]), .B(Op_MY[22]), .Y(n1295) );
OAI22X1TS U1907 ( .A0(n1353), .A1(n1295), .B0(n491), .B1(n514), .Y(
mult_x_23_n308) );
XNOR2X1TS U1908 ( .A(n514), .B(n438), .Y(n1296) );
OAI22X1TS U1909 ( .A0(n1353), .A1(n1296), .B0(n1295), .B1(n491), .Y(
mult_x_23_n309) );
XNOR2X1TS U1910 ( .A(Op_MX[19]), .B(Op_MY[20]), .Y(n1297) );
OAI22X1TS U1911 ( .A0(n1353), .A1(n1297), .B0(n1296), .B1(n492), .Y(
mult_x_23_n310) );
XNOR2X1TS U1912 ( .A(n514), .B(Op_MY[19]), .Y(n1298) );
OAI22X1TS U1913 ( .A0(n1353), .A1(n1298), .B0(n1297), .B1(n491), .Y(
mult_x_23_n311) );
XNOR2X1TS U1914 ( .A(n514), .B(n1330), .Y(n1299) );
OAI22X1TS U1915 ( .A0(n1353), .A1(n1299), .B0(n1298), .B1(n492), .Y(
mult_x_23_n312) );
XNOR2X1TS U1916 ( .A(n1351), .B(n442), .Y(n1300) );
OAI22X1TS U1917 ( .A0(n1353), .A1(n1300), .B0(n1299), .B1(n492), .Y(
mult_x_23_n313) );
XNOR2X1TS U1918 ( .A(n514), .B(n398), .Y(n1301) );
OAI22X1TS U1919 ( .A0(n534), .A1(n1301), .B0(n1300), .B1(n491), .Y(
mult_x_23_n314) );
XNOR2X1TS U1920 ( .A(n514), .B(n440), .Y(n1339) );
OAI22X1TS U1921 ( .A0(n1353), .A1(n1339), .B0(n1301), .B1(n492), .Y(
mult_x_23_n315) );
XNOR2X1TS U1922 ( .A(n1351), .B(n1356), .Y(n1302) );
XNOR2X1TS U1923 ( .A(n514), .B(Op_MY[14]), .Y(n1340) );
OAI22X1TS U1924 ( .A0(n534), .A1(n1302), .B0(n1340), .B1(n492), .Y(
mult_x_23_n317) );
XNOR2X1TS U1925 ( .A(n1351), .B(n552), .Y(n1303) );
OAI22X1TS U1926 ( .A0(n534), .A1(n1303), .B0(n1302), .B1(n491), .Y(
mult_x_23_n318) );
NOR2BX1TS U1927 ( .AN(n552), .B(n492), .Y(mult_x_23_n319) );
OAI22X1TS U1928 ( .A0(n1345), .A1(n508), .B0(n807), .B1(n419), .Y(
mult_x_23_n321) );
XNOR2X1TS U1929 ( .A(n507), .B(n1986), .Y(n1304) );
OAI22X1TS U1930 ( .A0(n1345), .A1(n1304), .B0(n490), .B1(n508), .Y(
mult_x_23_n322) );
OAI22X1TS U1931 ( .A0(n1345), .A1(n1305), .B0(n1304), .B1(n489), .Y(
mult_x_23_n323) );
XNOR2X1TS U1932 ( .A(n508), .B(Op_MY[19]), .Y(n1307) );
OAI22X1TS U1933 ( .A0(n533), .A1(n1307), .B0(n1306), .B1(n489), .Y(
mult_x_23_n325) );
XNOR2X1TS U1934 ( .A(n508), .B(n1330), .Y(n1308) );
OAI22X1TS U1935 ( .A0(n533), .A1(n1308), .B0(n1307), .B1(n489), .Y(
mult_x_23_n326) );
XNOR2X1TS U1936 ( .A(n507), .B(n442), .Y(n1343) );
OAI22X1TS U1937 ( .A0(n1345), .A1(n1343), .B0(n1308), .B1(n490), .Y(
mult_x_23_n327) );
XNOR2X1TS U1938 ( .A(n508), .B(n440), .Y(n1309) );
XNOR2X1TS U1939 ( .A(n507), .B(n398), .Y(n1344) );
OAI22X1TS U1940 ( .A0(n533), .A1(n1309), .B0(n1344), .B1(n489), .Y(
mult_x_23_n329) );
XNOR2X1TS U1941 ( .A(n508), .B(Op_MY[14]), .Y(n1310) );
OAI22X1TS U1942 ( .A0(n533), .A1(n1310), .B0(n1309), .B1(n490), .Y(
mult_x_23_n330) );
OAI22X1TS U1943 ( .A0(n533), .A1(n1311), .B0(n1310), .B1(n490), .Y(
mult_x_23_n331) );
OAI22X1TS U1944 ( .A0(n531), .A1(n506), .B0(n486), .B1(n421), .Y(
mult_x_23_n335) );
XNOR2X1TS U1945 ( .A(n505), .B(n1986), .Y(n1312) );
OAI22X1TS U1946 ( .A0(n531), .A1(n1312), .B0(n487), .B1(n506), .Y(
mult_x_23_n336) );
XNOR2X1TS U1947 ( .A(n506), .B(n399), .Y(n1313) );
OAI22X1TS U1948 ( .A0(n532), .A1(n1313), .B0(n1312), .B1(n486), .Y(
mult_x_23_n337) );
XNOR2X1TS U1949 ( .A(n505), .B(n555), .Y(n1314) );
OAI22X1TS U1950 ( .A0(n532), .A1(n1314), .B0(n1313), .B1(n487), .Y(
mult_x_23_n338) );
XNOR2X1TS U1951 ( .A(n505), .B(Op_MY[19]), .Y(n1315) );
OAI22X1TS U1952 ( .A0(n531), .A1(n1315), .B0(n1314), .B1(n487), .Y(
mult_x_23_n339) );
XNOR2X1TS U1953 ( .A(n505), .B(n1330), .Y(n1333) );
OAI22X1TS U1954 ( .A0(n532), .A1(n1333), .B0(n1315), .B1(n487), .Y(
mult_x_23_n340) );
XNOR2X1TS U1955 ( .A(n506), .B(n398), .Y(n1316) );
XNOR2X1TS U1956 ( .A(n505), .B(Op_MY[17]), .Y(n1334) );
OAI22X1TS U1957 ( .A0(n532), .A1(n1316), .B0(n1334), .B1(n486), .Y(
mult_x_23_n342) );
OAI22X1TS U1958 ( .A0(n532), .A1(n1317), .B0(n1316), .B1(n487), .Y(
mult_x_23_n343) );
XNOR2X1TS U1959 ( .A(n452), .B(n1986), .Y(n1318) );
OAI22X1TS U1960 ( .A0(n1361), .A1(n1318), .B0(n589), .B1(n452), .Y(
mult_x_23_n350) );
XNOR2X1TS U1961 ( .A(n452), .B(n438), .Y(n1359) );
OAI22X1TS U1962 ( .A0(n1361), .A1(n1359), .B0(n1318), .B1(n589), .Y(
mult_x_23_n351) );
XNOR2X1TS U1963 ( .A(n452), .B(n1330), .Y(n1350) );
OAI22X1TS U1964 ( .A0(n1320), .A1(n1319), .B0(n1350), .B1(n700), .Y(
mult_x_23_n355) );
NOR2BX1TS U1965 ( .AN(n552), .B(n700), .Y(
Sgf_operation_RECURSIVE_EVEN1_left_N0) );
INVX2TS U1966 ( .A(n1325), .Y(n1327) );
NAND2X1TS U1967 ( .A(n1327), .B(n1326), .Y(n1328) );
NOR2X1TS U1968 ( .A(n449), .B(n1986), .Y(mult_x_23_n280) );
OAI22X1TS U1969 ( .A0(n449), .A1(Op_MY[19]), .B0(n481), .B1(n555), .Y(n1332)
);
OAI22X1TS U1970 ( .A0(n534), .A1(n514), .B0(n491), .B1(n420), .Y(n1331) );
CMPR32X2TS U1971 ( .A(n574), .B(n1332), .C(n1331), .CO(mult_x_23_n176), .S(
mult_x_23_n177) );
NOR2BX1TS U1972 ( .AN(n1362), .B(n495), .Y(n1338) );
XNOR2X1TS U1973 ( .A(n451), .B(n439), .Y(n1349) );
XNOR2X1TS U1974 ( .A(n451), .B(Op_MY[20]), .Y(n1360) );
OAI22X1TS U1975 ( .A0(n1361), .A1(n1349), .B0(n1360), .B1(n589), .Y(n1337)
);
OAI22X1TS U1976 ( .A0(n531), .A1(n1334), .B0(n1333), .B1(n487), .Y(n1336) );
CMPR32X2TS U1977 ( .A(n1338), .B(n1337), .C(n1336), .CO(mult_x_23_n253), .S(
mult_x_23_n254) );
OAI22X1TS U1978 ( .A0(n1353), .A1(n1340), .B0(n1339), .B1(n492), .Y(n1348)
);
XNOR2X1TS U1979 ( .A(n520), .B(n1362), .Y(n1342) );
OAI22X1TS U1980 ( .A0(n535), .A1(n1342), .B0(n1341), .B1(n495), .Y(n1347) );
OAI22X1TS U1981 ( .A0(n1345), .A1(n1344), .B0(n1343), .B1(n490), .Y(n1346)
);
CMPR32X2TS U1982 ( .A(n1348), .B(n1347), .C(n1346), .CO(mult_x_23_n246), .S(
mult_x_23_n247) );
OAI22X1TS U1983 ( .A0(n1361), .A1(n1350), .B0(n1349), .B1(n589), .Y(n1355)
);
OAI22X1TS U1984 ( .A0(n1353), .A1(n420), .B0(n492), .B1(n1352), .Y(n1354) );
OAI21X1TS U1985 ( .A0(n481), .A1(n552), .B0(n448), .Y(n1358) );
OAI22X1TS U1986 ( .A0(n448), .A1(n552), .B0(n481), .B1(n1356), .Y(n1357) );
OAI22X1TS U1987 ( .A0(n1361), .A1(n1360), .B0(n1359), .B1(n700), .Y(n1367)
);
OAI22X1TS U1988 ( .A0(n535), .A1(n1364), .B0(n496), .B1(n1363), .Y(n1366) );
ADDHXLTS U1989 ( .A(n1369), .B(n1368), .CO(mult_x_23_n265), .S(n825) );
INVX2TS U1990 ( .A(n1372), .Y(n1374) );
NAND2X1TS U1991 ( .A(n1374), .B(n1373), .Y(n1375) );
NAND2X1TS U1992 ( .A(n1379), .B(n1378), .Y(n1380) );
XNOR2X1TS U1993 ( .A(n1377), .B(n1380), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N14) );
INVX2TS U1994 ( .A(n1381), .Y(n1540) );
NAND2X1TS U1995 ( .A(n1384), .B(n1383), .Y(n1385) );
XNOR2X1TS U1996 ( .A(n1386), .B(n1385), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N13) );
INVX2TS U1997 ( .A(n1387), .Y(n1395) );
AOI21X1TS U1998 ( .A0(n1395), .A1(n405), .B0(n1388), .Y(n1392) );
NAND2X1TS U1999 ( .A(n1390), .B(n1389), .Y(n1391) );
NAND2X1TS U2000 ( .A(n405), .B(n1393), .Y(n1394) );
XNOR2X1TS U2001 ( .A(n1395), .B(n1394), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N10) );
NAND2X1TS U2002 ( .A(n782), .B(n1396), .Y(n1397) );
XNOR2X1TS U2003 ( .A(n1398), .B(n1397), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N9) );
INVX2TS U2004 ( .A(n1399), .Y(n1405) );
AOI21X1TS U2005 ( .A0(n406), .A1(n1405), .B0(n1400), .Y(n1403) );
NAND2X1TS U2006 ( .A(n591), .B(n1401), .Y(n1402) );
NAND2X1TS U2007 ( .A(n1404), .B(n406), .Y(n1406) );
XNOR2X1TS U2008 ( .A(n1406), .B(n1405), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N7) );
NAND2X1TS U2009 ( .A(n597), .B(n1407), .Y(n1409) );
XNOR2X1TS U2010 ( .A(n1409), .B(n1408), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N6) );
INVX2TS U2011 ( .A(n1410), .Y(n1412) );
NAND2X1TS U2012 ( .A(n1412), .B(n1411), .Y(n1414) );
NAND2X1TS U2013 ( .A(n598), .B(n1415), .Y(n1417) );
XNOR2X1TS U2014 ( .A(n1417), .B(n1416), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N4) );
NAND2X1TS U2015 ( .A(n1420), .B(n1419), .Y(n1422) );
NAND2X1TS U2016 ( .A(n571), .B(n1423), .Y(n1425) );
XNOR2X1TS U2017 ( .A(n1425), .B(n1424), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N2) );
XNOR2X1TS U2018 ( .A(n1508), .B(n485), .Y(n1476) );
NOR2X1TS U2019 ( .A(n1427), .B(n1431), .Y(n1429) );
XOR2X1TS U2020 ( .A(n1429), .B(n1428), .Y(n1436) );
NOR2X1TS U2021 ( .A(Op_MX[17]), .B(n435), .Y(n1430) );
INVX2TS U2022 ( .A(n484), .Y(n1562) );
OAI22X1TS U2023 ( .A0(n1476), .A1(n547), .B0(n515), .B1(n1562), .Y(n1446) );
AOI21X1TS U2024 ( .A0(n1439), .A1(n1438), .B0(n1437), .Y(n1444) );
NAND2X1TS U2025 ( .A(n1442), .B(n1441), .Y(n1443) );
INVX2TS U2026 ( .A(n1519), .Y(n1457) );
INVX2TS U2027 ( .A(n1517), .Y(n1565) );
OAI22X1TS U2028 ( .A0(n1457), .A1(n530), .B0(n1565), .B1(n453), .Y(n1566) );
INVX2TS U2029 ( .A(n1566), .Y(n1445) );
CMPR32X2TS U2030 ( .A(n1446), .B(n1445), .C(DP_OP_111J22_123_4462_n280),
.CO(DP_OP_111J22_123_4462_n273), .S(DP_OP_111J22_123_4462_n274) );
INVX2TS U2031 ( .A(n1447), .Y(n1448) );
CLKINVX1TS U2032 ( .A(n1450), .Y(n1452) );
NAND2X1TS U2033 ( .A(n1452), .B(n1451), .Y(n1453) );
CLKXOR2X4TS U2034 ( .A(n1454), .B(n1453), .Y(n1513) );
INVX2TS U2035 ( .A(n1513), .Y(n1456) );
OAI22X1TS U2036 ( .A0(n1456), .A1(n530), .B0(n1455), .B1(n454), .Y(
DP_OP_111J22_123_4462_n384) );
INVX2TS U2037 ( .A(n1515), .Y(n1564) );
OAI22X1TS U2038 ( .A0(n1456), .A1(n454), .B0(n1564), .B1(n530), .Y(
DP_OP_111J22_123_4462_n385) );
INVX2TS U2039 ( .A(n1502), .Y(n1458) );
OAI22X1TS U2040 ( .A0(n1458), .A1(n530), .B0(n1457), .B1(n454), .Y(
DP_OP_111J22_123_4462_n387) );
INVX2TS U2041 ( .A(n1504), .Y(n1535) );
OAI22X1TS U2042 ( .A0(n1458), .A1(n454), .B0(n1535), .B1(n530), .Y(
DP_OP_111J22_123_4462_n388) );
XNOR2X1TS U2043 ( .A(n1509), .B(n474), .Y(n1460) );
OAI22X1TS U2044 ( .A0(n1460), .A1(n463), .B0(n1459), .B1(n504), .Y(
DP_OP_111J22_123_4462_n394) );
XNOR2X1TS U2045 ( .A(n1511), .B(n475), .Y(n1461) );
OAI22X1TS U2046 ( .A0(n1461), .A1(n463), .B0(n1460), .B1(n503), .Y(
DP_OP_111J22_123_4462_n395) );
XNOR2X1TS U2047 ( .A(n1513), .B(n474), .Y(n1463) );
OAI22X1TS U2048 ( .A0(n1463), .A1(n464), .B0(n1461), .B1(n504), .Y(
DP_OP_111J22_123_4462_n396) );
OAI22X1TS U2049 ( .A0(n1463), .A1(n503), .B0(n1462), .B1(n463), .Y(
DP_OP_111J22_123_4462_n397) );
XNOR2X1TS U2050 ( .A(n1519), .B(n474), .Y(n1465) );
OAI22X1TS U2051 ( .A0(n1465), .A1(n464), .B0(n1464), .B1(n504), .Y(
DP_OP_111J22_123_4462_n399) );
XNOR2X1TS U2052 ( .A(n1502), .B(n475), .Y(n1466) );
OAI22X1TS U2053 ( .A0(n1466), .A1(n464), .B0(n1465), .B1(n504), .Y(
DP_OP_111J22_123_4462_n400) );
OAI22X1TS U2054 ( .A0(n1466), .A1(n504), .B0(n1598), .B1(n463), .Y(
DP_OP_111J22_123_4462_n401) );
NOR2BX1TS U2055 ( .AN(n553), .B(n503), .Y(DP_OP_111J22_123_4462_n406) );
XNOR2X1TS U2056 ( .A(n1509), .B(n483), .Y(n1468) );
OAI22X1TS U2057 ( .A0(n1468), .A1(n549), .B0(n1467), .B1(n425), .Y(
DP_OP_111J22_123_4462_n408) );
XNOR2X1TS U2058 ( .A(n1511), .B(n483), .Y(n1469) );
OAI22X1TS U2059 ( .A0(n1469), .A1(n549), .B0(n1468), .B1(n426), .Y(
DP_OP_111J22_123_4462_n409) );
XNOR2X1TS U2060 ( .A(n1513), .B(n483), .Y(n1470) );
OAI22X1TS U2061 ( .A0(n1470), .A1(n549), .B0(n1469), .B1(n426), .Y(
DP_OP_111J22_123_4462_n410) );
XNOR2X1TS U2062 ( .A(n1515), .B(n483), .Y(n1471) );
OAI22X1TS U2063 ( .A0(n1470), .A1(n425), .B0(n1471), .B1(n549), .Y(
DP_OP_111J22_123_4462_n411) );
XNOR2X1TS U2064 ( .A(n1517), .B(n483), .Y(n1472) );
OAI22X1TS U2065 ( .A0(n1472), .A1(n548), .B0(n1471), .B1(n426), .Y(
DP_OP_111J22_123_4462_n412) );
XNOR2X1TS U2066 ( .A(n1519), .B(n483), .Y(n1473) );
OAI22X1TS U2067 ( .A0(n1473), .A1(n549), .B0(n1472), .B1(n425), .Y(
DP_OP_111J22_123_4462_n413) );
XNOR2X1TS U2068 ( .A(n1502), .B(n483), .Y(n1474) );
OAI22X1TS U2069 ( .A0(n1474), .A1(n549), .B0(n1473), .B1(n425), .Y(
DP_OP_111J22_123_4462_n414) );
XNOR2X1TS U2070 ( .A(n1504), .B(n872), .Y(n1613) );
OAI22X1TS U2071 ( .A0(n1474), .A1(n426), .B0(n1613), .B1(n549), .Y(
DP_OP_111J22_123_4462_n415) );
XNOR2X1TS U2072 ( .A(n1597), .B(n872), .Y(n1612) );
XNOR2X1TS U2073 ( .A(n1609), .B(n872), .Y(n1475) );
OAI22X1TS U2074 ( .A0(n1612), .A1(n425), .B0(n1475), .B1(n548), .Y(
DP_OP_111J22_123_4462_n417) );
XNOR2X1TS U2075 ( .A(n1543), .B(n872), .Y(n1547) );
OAI22X1TS U2076 ( .A0(n1475), .A1(n425), .B0(n548), .B1(n1547), .Y(
DP_OP_111J22_123_4462_n418) );
XNOR2X1TS U2077 ( .A(n1509), .B(n485), .Y(n1477) );
OAI22X1TS U2078 ( .A0(n1477), .A1(n547), .B0(n1476), .B1(n515), .Y(
DP_OP_111J22_123_4462_n423) );
XNOR2X1TS U2079 ( .A(n1511), .B(n485), .Y(n1478) );
OAI22X1TS U2080 ( .A0(n1478), .A1(n547), .B0(n1477), .B1(n516), .Y(
DP_OP_111J22_123_4462_n424) );
XNOR2X1TS U2081 ( .A(n1513), .B(n485), .Y(n1479) );
OAI22X1TS U2082 ( .A0(n1479), .A1(n547), .B0(n1478), .B1(n516), .Y(
DP_OP_111J22_123_4462_n425) );
XNOR2X1TS U2083 ( .A(n1515), .B(n485), .Y(n1480) );
OAI22X1TS U2084 ( .A0(n1479), .A1(n515), .B0(n1480), .B1(n547), .Y(
DP_OP_111J22_123_4462_n426) );
XNOR2X1TS U2085 ( .A(n1517), .B(n485), .Y(n1481) );
OAI22X1TS U2086 ( .A0(n1481), .A1(n547), .B0(n1480), .B1(n515), .Y(
DP_OP_111J22_123_4462_n427) );
XNOR2X1TS U2087 ( .A(n1519), .B(n485), .Y(n1482) );
OAI22X1TS U2088 ( .A0(n1482), .A1(n547), .B0(n1481), .B1(n516), .Y(
DP_OP_111J22_123_4462_n428) );
XNOR2X1TS U2089 ( .A(n1502), .B(n485), .Y(n1483) );
OAI22X1TS U2090 ( .A0(n1483), .A1(n547), .B0(n1482), .B1(n515), .Y(
DP_OP_111J22_123_4462_n429) );
XNOR2X1TS U2091 ( .A(n1504), .B(n484), .Y(n1484) );
OAI22X1TS U2092 ( .A0(n1483), .A1(n516), .B0(n1484), .B1(n547), .Y(
DP_OP_111J22_123_4462_n430) );
XNOR2X1TS U2093 ( .A(n1597), .B(n484), .Y(n1551) );
OAI22X1TS U2094 ( .A0(n1484), .A1(n516), .B0(n1551), .B1(n546), .Y(
DP_OP_111J22_123_4462_n431) );
NOR2BX1TS U2095 ( .AN(n553), .B(n516), .Y(DP_OP_111J22_123_4462_n435) );
XNOR2X1TS U2096 ( .A(n1508), .B(n479), .Y(n1486) );
OAI22X1TS U2097 ( .A0(n1486), .A1(n545), .B0(n519), .B1(n1485), .Y(
DP_OP_111J22_123_4462_n437) );
XNOR2X1TS U2098 ( .A(n1509), .B(n479), .Y(n1487) );
OAI22X1TS U2099 ( .A0(n1487), .A1(n545), .B0(n1486), .B1(n518), .Y(
DP_OP_111J22_123_4462_n438) );
XNOR2X1TS U2100 ( .A(n1511), .B(n479), .Y(n1488) );
OAI22X1TS U2101 ( .A0(n1488), .A1(n545), .B0(n1487), .B1(n519), .Y(
DP_OP_111J22_123_4462_n439) );
XNOR2X1TS U2102 ( .A(n1513), .B(n479), .Y(n1489) );
OAI22X1TS U2103 ( .A0(n1489), .A1(n545), .B0(n1488), .B1(n518), .Y(
DP_OP_111J22_123_4462_n440) );
XNOR2X1TS U2104 ( .A(n1515), .B(n479), .Y(n1490) );
OAI22X1TS U2105 ( .A0(n1489), .A1(n518), .B0(n1490), .B1(n545), .Y(
DP_OP_111J22_123_4462_n441) );
XNOR2X1TS U2106 ( .A(n1517), .B(n479), .Y(n1491) );
OAI22X1TS U2107 ( .A0(n1491), .A1(n545), .B0(n1490), .B1(n519), .Y(
DP_OP_111J22_123_4462_n442) );
XNOR2X1TS U2108 ( .A(n1519), .B(n479), .Y(n1492) );
OAI22X1TS U2109 ( .A0(n1492), .A1(n545), .B0(n1491), .B1(n519), .Y(
DP_OP_111J22_123_4462_n443) );
XNOR2X1TS U2110 ( .A(n1502), .B(n479), .Y(n1493) );
OAI22X1TS U2111 ( .A0(n1493), .A1(n545), .B0(n1492), .B1(n518), .Y(
DP_OP_111J22_123_4462_n444) );
XNOR2X1TS U2112 ( .A(n1504), .B(n478), .Y(n1558) );
OAI22X1TS U2113 ( .A0(n1493), .A1(n519), .B0(n1558), .B1(n545), .Y(
DP_OP_111J22_123_4462_n445) );
XNOR2X1TS U2114 ( .A(n1597), .B(n478), .Y(n1557) );
XNOR2X1TS U2115 ( .A(n1609), .B(n478), .Y(n1495) );
OAI22X1TS U2116 ( .A0(n1557), .A1(n519), .B0(n1495), .B1(n544), .Y(
DP_OP_111J22_123_4462_n447) );
OAI22X1TS U2117 ( .A0(n1495), .A1(n518), .B0(n544), .B1(n1494), .Y(
DP_OP_111J22_123_4462_n448) );
XNOR2X1TS U2118 ( .A(n1508), .B(n467), .Y(n1496) );
OAI22X1TS U2119 ( .A0(n1496), .A1(n543), .B0(n432), .B1(n465), .Y(
DP_OP_111J22_123_4462_n452) );
XNOR2X1TS U2120 ( .A(n1509), .B(n467), .Y(n1497) );
OAI22X1TS U2121 ( .A0(n1497), .A1(n543), .B0(n1496), .B1(n431), .Y(
DP_OP_111J22_123_4462_n453) );
XNOR2X1TS U2122 ( .A(n1511), .B(n467), .Y(n1498) );
OAI22X1TS U2123 ( .A0(n1498), .A1(n543), .B0(n1497), .B1(n432), .Y(
DP_OP_111J22_123_4462_n454) );
XNOR2X1TS U2124 ( .A(n1513), .B(n467), .Y(n1499) );
OAI22X1TS U2125 ( .A0(n1499), .A1(n543), .B0(n1498), .B1(n431), .Y(
DP_OP_111J22_123_4462_n455) );
XNOR2X1TS U2126 ( .A(n1515), .B(n467), .Y(n1500) );
OAI22X1TS U2127 ( .A0(n1499), .A1(n432), .B0(n1500), .B1(n543), .Y(
DP_OP_111J22_123_4462_n456) );
XNOR2X1TS U2128 ( .A(n1517), .B(n467), .Y(n1501) );
OAI22X1TS U2129 ( .A0(n1501), .A1(n543), .B0(n1500), .B1(n432), .Y(
DP_OP_111J22_123_4462_n457) );
XNOR2X1TS U2130 ( .A(n1519), .B(n467), .Y(n1503) );
OAI22X1TS U2131 ( .A0(n1503), .A1(n543), .B0(n1501), .B1(n431), .Y(
DP_OP_111J22_123_4462_n458) );
OAI22X1TS U2132 ( .A0(n1505), .A1(n543), .B0(n1503), .B1(n431), .Y(
DP_OP_111J22_123_4462_n459) );
XNOR2X1TS U2133 ( .A(n1504), .B(n466), .Y(n1507) );
OAI22X1TS U2134 ( .A0(n1505), .A1(n431), .B0(n1507), .B1(n542), .Y(
DP_OP_111J22_123_4462_n460) );
OAI22X1TS U2135 ( .A0(n1507), .A1(n431), .B0(n1506), .B1(n542), .Y(
DP_OP_111J22_123_4462_n461) );
XNOR2X1TS U2136 ( .A(n1508), .B(n461), .Y(n1510) );
OAI22X1TS U2137 ( .A0(n1510), .A1(n1523), .B0(n409), .B1(n1525), .Y(
DP_OP_111J22_123_4462_n467) );
XNOR2X1TS U2138 ( .A(n1509), .B(n461), .Y(n1512) );
OAI22X1TS U2139 ( .A0(n1512), .A1(n1521), .B0(n1510), .B1(n1525), .Y(
DP_OP_111J22_123_4462_n468) );
XNOR2X1TS U2140 ( .A(n1511), .B(n461), .Y(n1514) );
OAI22X1TS U2141 ( .A0(n1514), .A1(n1521), .B0(n1512), .B1(n1525), .Y(
DP_OP_111J22_123_4462_n469) );
XNOR2X1TS U2142 ( .A(n1513), .B(n461), .Y(n1516) );
OAI22X1TS U2143 ( .A0(n1516), .A1(n1523), .B0(n1514), .B1(n476), .Y(
DP_OP_111J22_123_4462_n470) );
XNOR2X1TS U2144 ( .A(n1515), .B(n461), .Y(n1518) );
OAI22X1TS U2145 ( .A0(n1516), .A1(n1525), .B0(n1518), .B1(n1521), .Y(
DP_OP_111J22_123_4462_n471) );
XNOR2X1TS U2146 ( .A(n1517), .B(n461), .Y(n1520) );
OAI22X1TS U2147 ( .A0(n1520), .A1(n1523), .B0(n1518), .B1(n1525), .Y(
DP_OP_111J22_123_4462_n472) );
XNOR2X1TS U2148 ( .A(n1519), .B(n461), .Y(n1522) );
OAI22X1TS U2149 ( .A0(n1522), .A1(n1521), .B0(n1520), .B1(n1525), .Y(
DP_OP_111J22_123_4462_n473) );
OAI22X1TS U2150 ( .A0(n1524), .A1(n1523), .B0(n1522), .B1(n476), .Y(
DP_OP_111J22_123_4462_n474) );
NOR2BX1TS U2151 ( .AN(n553), .B(n1525), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N0) );
XNOR2X1TS U2152 ( .A(n484), .B(n1608), .Y(n1531) );
XNOR2X1TS U2153 ( .A(n1543), .B(n484), .Y(n1554) );
OAI22X1TS U2154 ( .A0(n546), .A1(n1531), .B0(n1554), .B1(n516), .Y(n1532) );
ADDHX1TS U2155 ( .A(n1533), .B(n1532), .CO(DP_OP_111J22_123_4462_n362), .S(
DP_OP_111J22_123_4462_n363) );
INVX2TS U2156 ( .A(DP_OP_111J22_123_4462_n263), .Y(
DP_OP_111J22_123_4462_n264) );
INVX2TS U2157 ( .A(n1609), .Y(n1599) );
INVX2TS U2158 ( .A(n1543), .Y(n1615) );
OAI22X2TS U2159 ( .A0(n1599), .A1(n453), .B0(n1615), .B1(n897), .Y(n1596) );
INVX2TS U2160 ( .A(n1597), .Y(n1600) );
OAI22X1TS U2161 ( .A0(n1535), .A1(n453), .B0(n1600), .B1(n897), .Y(n1594) );
INVX2TS U2162 ( .A(DP_OP_111J22_123_4462_n289), .Y(
DP_OP_111J22_123_4462_n290) );
INVX2TS U2163 ( .A(n1536), .Y(n1538) );
NAND2X1TS U2164 ( .A(n1538), .B(n1537), .Y(n1539) );
NAND2BX1TS U2165 ( .AN(n1608), .B(n474), .Y(n1541) );
OAI22X1TS U2166 ( .A0(n1616), .A1(n1542), .B0(n503), .B1(n1541), .Y(n1546)
);
XNOR2X1TS U2167 ( .A(n474), .B(n1608), .Y(n1544) );
XNOR2X1TS U2168 ( .A(n1543), .B(n473), .Y(n1610) );
OAI22X1TS U2169 ( .A0(n463), .A1(n1544), .B0(n1610), .B1(n503), .Y(n1545) );
ADDHX1TS U2170 ( .A(n1546), .B(n1545), .CO(DP_OP_111J22_123_4462_n339), .S(
DP_OP_111J22_123_4462_n340) );
XNOR2X1TS U2171 ( .A(n872), .B(n1608), .Y(n1548) );
OAI22X1TS U2172 ( .A0(n548), .A1(n1548), .B0(n1547), .B1(n426), .Y(n1553) );
OAI22X1TS U2173 ( .A0(n548), .A1(n1550), .B0(n425), .B1(n1549), .Y(n1552) );
XNOR2X1TS U2174 ( .A(n1609), .B(n484), .Y(n1555) );
OAI22X1TS U2175 ( .A0(n1551), .A1(n516), .B0(n1555), .B1(n546), .Y(n1561) );
ADDHX1TS U2176 ( .A(n1553), .B(n1552), .CO(DP_OP_111J22_123_4462_n352), .S(
n1560) );
NOR2BX1TS U2177 ( .AN(n553), .B(n425), .Y(n1607) );
OAI22X1TS U2178 ( .A0(n1555), .A1(n515), .B0(n546), .B1(n1554), .Y(n1606) );
OAI22X1TS U2179 ( .A0(n1558), .A1(n519), .B0(n1557), .B1(n544), .Y(n1605) );
OAI22X1TS U2180 ( .A0(n1565), .A1(n530), .B0(n1564), .B1(n454), .Y(n1567) );
NOR2X2TS U2181 ( .A(n1570), .B(n1578), .Y(n1581) );
INVX2TS U2182 ( .A(n1572), .Y(n1576) );
INVX2TS U2183 ( .A(n1573), .Y(n1574) );
AOI21X1TS U2184 ( .A0(n1576), .A1(n1575), .B0(n1574), .Y(n1577) );
AOI21X4TS U2185 ( .A0(n565), .A1(n1583), .B0(n564), .Y(n1593) );
CMPR32X2TS U2186 ( .A(n1586), .B(n1585), .C(n1584), .CO(n1589), .S(n908) );
NAND2X1TS U2187 ( .A(n1589), .B(n1588), .Y(n1590) );
NAND2X1TS U2188 ( .A(n1591), .B(n1590), .Y(n1592) );
XOR2X2TS U2189 ( .A(n1593), .B(n1592), .Y(
Sgf_operation_RECURSIVE_EVEN1_middle_N25) );
INVX2TS U2190 ( .A(n1596), .Y(n1604) );
XNOR2X1TS U2191 ( .A(n1597), .B(n473), .Y(n1618) );
OAI22X2TS U2192 ( .A0(n1598), .A1(n504), .B0(n1618), .B1(n463), .Y(n1601) );
OAI22X1TS U2193 ( .A0(n1600), .A1(n454), .B0(n1599), .B1(n897), .Y(n1603) );
CMPR32X2TS U2194 ( .A(n1604), .B(n409), .C(n1601), .CO(n1602), .S(
DP_OP_111J22_123_4462_n315) );
CMPR32X2TS U2195 ( .A(n1607), .B(n1606), .C(n1605), .CO(n1559), .S(
DP_OP_111J22_123_4462_n358) );
NOR2BX1TS U2196 ( .AN(n553), .B(n453), .Y(n1621) );
XNOR2X1TS U2197 ( .A(n1609), .B(n473), .Y(n1617) );
OAI22X1TS U2198 ( .A0(n1617), .A1(n503), .B0(n1616), .B1(n1610), .Y(n1620)
);
OAI22X1TS U2199 ( .A0(n1613), .A1(n426), .B0(n1612), .B1(n548), .Y(n1619) );
OAI22X1TS U2200 ( .A0(n1615), .A1(n454), .B0(n530), .B1(n1614), .Y(n1624) );
OAI22X1TS U2201 ( .A0(n1618), .A1(n504), .B0(n1617), .B1(n464), .Y(n1623) );
CMPR32X2TS U2202 ( .A(n1624), .B(n1623), .C(n1622), .CO(
DP_OP_111J22_123_4462_n323), .S(DP_OP_111J22_123_4462_n324) );
NOR2X2TS U2203 ( .A(n562), .B(FS_Module_state_reg[2]), .Y(n1956) );
NAND2X2TS U2204 ( .A(n1956), .B(n2390), .Y(n1967) );
NOR4X1TS U2205 ( .A(P_Sgf[13]), .B(P_Sgf[17]), .C(P_Sgf[15]), .D(P_Sgf[16]),
.Y(n1632) );
NOR4X1TS U2206 ( .A(P_Sgf[1]), .B(P_Sgf[5]), .C(P_Sgf[3]), .D(P_Sgf[4]), .Y(
n1629) );
NOR3XLTS U2207 ( .A(P_Sgf[22]), .B(P_Sgf[2]), .C(P_Sgf[0]), .Y(n1628) );
AND4X1TS U2208 ( .A(n1629), .B(n1628), .C(n1627), .D(n424), .Y(n1630) );
XOR2X1TS U2209 ( .A(Op_MY[31]), .B(Op_MX[31]), .Y(n1961) );
MXI2X1TS U2210 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n1961), .Y(n1633)
);
OAI211X1TS U2211 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n1634), .C0(
n1633), .Y(n1969) );
OAI31X1TS U2212 ( .A0(FS_Module_state_reg[1]), .A1(n1967), .A2(n1969), .B0(
n2391), .Y(n214) );
INVX2TS U2213 ( .A(Sgf_operation_Result[1]), .Y(n1638) );
XNOR2X1TS U2214 ( .A(n1638), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[1]),
.Y(n1637) );
INVX2TS U2215 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[1]), .Y(n1636) );
NOR2X2TS U2216 ( .A(n1637), .B(n1636), .Y(n1781) );
OR2X2TS U2217 ( .A(n2381), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]),
.Y(n1787) );
INVX2TS U2218 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .Y(n1788) );
NAND2X2TS U2219 ( .A(n2381), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[0]),
.Y(n1786) );
INVX2TS U2220 ( .A(n1786), .Y(n1635) );
AOI21X1TS U2221 ( .A0(n1787), .A1(n1788), .B0(n1635), .Y(n1784) );
NAND2X1TS U2222 ( .A(n1637), .B(n1636), .Y(n1782) );
OAI21X2TS U2223 ( .A0(n1781), .A1(n1784), .B0(n1782), .Y(n1791) );
INVX2TS U2224 ( .A(Sgf_operation_Result[2]), .Y(n1640) );
INVX2TS U2225 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .Y(n1639) );
NOR2X2TS U2226 ( .A(n1642), .B(n1641), .Y(n1801) );
INVX2TS U2227 ( .A(Sgf_operation_Result[3]), .Y(n1648) );
INVX2TS U2228 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .Y(n1647) );
CMPR32X2TS U2229 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[2]), .B(n1640),
.C(n1639), .CO(n1643), .S(n1642) );
NOR2X2TS U2230 ( .A(n1644), .B(n1643), .Y(n1803) );
NAND2X1TS U2231 ( .A(n1644), .B(n1643), .Y(n1804) );
OAI21X2TS U2232 ( .A0(n1803), .A1(n1800), .B0(n1804), .Y(n1645) );
AOI21X4TS U2233 ( .A0(n1791), .A1(n1646), .B0(n1645), .Y(n1769) );
INVX2TS U2234 ( .A(Sgf_operation_Result[4]), .Y(n1650) );
INVX2TS U2235 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .Y(n1649) );
CMPR32X2TS U2236 ( .A(n1648), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[3]),
.C(n1647), .CO(n1655), .S(n1644) );
INVX2TS U2237 ( .A(Sgf_operation_Result[5]), .Y(n1652) );
INVX2TS U2238 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[5]), .Y(n1651) );
CMPR32X2TS U2239 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[4]), .B(n1650),
.C(n1649), .CO(n1657), .S(n1656) );
NOR2X2TS U2240 ( .A(n1658), .B(n1657), .Y(n1776) );
NOR2X2TS U2241 ( .A(n1774), .B(n1776), .Y(n1771) );
INVX2TS U2242 ( .A(Sgf_operation_Result[6]), .Y(n1654) );
INVX2TS U2243 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .Y(n1653) );
CMPR32X2TS U2244 ( .A(n1652), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[5]),
.C(n1651), .CO(n1659), .S(n1658) );
NOR2X2TS U2245 ( .A(n1660), .B(n1659), .Y(n1821) );
INVX2TS U2246 ( .A(Sgf_operation_Result[7]), .Y(n1673) );
INVX2TS U2247 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[7]), .Y(n1672) );
CMPR32X2TS U2248 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[6]), .B(n1654),
.C(n1653), .CO(n1661), .S(n1660) );
NOR2X2TS U2249 ( .A(n1662), .B(n1661), .Y(n1823) );
NOR2X2TS U2250 ( .A(n1821), .B(n1823), .Y(n1664) );
NAND2X1TS U2251 ( .A(n1658), .B(n1657), .Y(n1777) );
OAI21X2TS U2252 ( .A0(n1776), .A1(n1796), .B0(n1777), .Y(n1770) );
NAND2X1TS U2253 ( .A(n1662), .B(n1661), .Y(n1824) );
OAI21X1TS U2254 ( .A0(n1823), .A1(n1820), .B0(n1824), .Y(n1663) );
OAI21X4TS U2255 ( .A0(n1769), .A1(n1666), .B0(n1665), .Y(n1710) );
INVX2TS U2256 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .Y(n1668) );
INVX2TS U2257 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[12]), .Y(n1667) );
INVX2TS U2258 ( .A(Sgf_operation_Result[11]), .Y(n1679) );
INVX2TS U2259 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[11]), .Y(n1678) );
NOR2X2TS U2260 ( .A(n1693), .B(n1692), .Y(n1753) );
INVX2TS U2261 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[13]), .Y(n1670) );
INVX2TS U2262 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[13]), .Y(n1669) );
CMPR32X2TS U2263 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[12]), .B(n1668),
.C(n1667), .CO(n1694), .S(n1693) );
NOR2X2TS U2264 ( .A(n1695), .B(n1694), .Y(n1760) );
NOR2X2TS U2265 ( .A(n1753), .B(n1760), .Y(n1713) );
INVX2TS U2266 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[14]), .Y(n1671) );
CMPR32X2TS U2267 ( .A(n1670), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[13]),
.C(n1669), .CO(n1696), .S(n1695) );
INVX2TS U2268 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[15]), .Y(n2049) );
INVX2TS U2269 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[15]), .Y(n1706) );
CMPR32X2TS U2270 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[14]), .B(n2063),
.C(n1671), .CO(n1698), .S(n1697) );
INVX2TS U2271 ( .A(Sgf_operation_Result[8]), .Y(n1675) );
INVX2TS U2272 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .Y(n1674) );
CMPR32X2TS U2273 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[7]), .B(n1673),
.C(n1672), .CO(n1682), .S(n1662) );
NOR2X2TS U2274 ( .A(n1683), .B(n1682), .Y(n1829) );
INVX2TS U2275 ( .A(Sgf_operation_Result[9]), .Y(n1677) );
INVX2TS U2276 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .Y(n1676) );
NOR2X2TS U2277 ( .A(n1685), .B(n1684), .Y(n1831) );
INVX2TS U2278 ( .A(Sgf_operation_Result[10]), .Y(n1681) );
INVX2TS U2279 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[10]), .Y(n1680) );
CMPR32X2TS U2280 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[9]), .B(n1677),
.C(n1676), .CO(n1686), .S(n1685) );
CMPR32X2TS U2281 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[11]), .B(n1679),
.C(n1678), .CO(n1692), .S(n1689) );
NOR2X2TS U2282 ( .A(n1689), .B(n1688), .Y(n1748) );
NOR2X2TS U2283 ( .A(n1746), .B(n1748), .Y(n1691) );
NAND2X2TS U2284 ( .A(n1742), .B(n1691), .Y(n1712) );
NOR2X2TS U2285 ( .A(n1703), .B(n1712), .Y(n1705) );
NAND2X1TS U2286 ( .A(n1685), .B(n1684), .Y(n1832) );
OAI21X2TS U2287 ( .A0(n1831), .A1(n1828), .B0(n1832), .Y(n1743) );
NAND2X2TS U2288 ( .A(n1687), .B(n1686), .Y(n1836) );
NAND2X1TS U2289 ( .A(n1689), .B(n1688), .Y(n1749) );
OAI21X1TS U2290 ( .A0(n1748), .A1(n1836), .B0(n1749), .Y(n1690) );
AOI21X4TS U2291 ( .A0(n1743), .A1(n1691), .B0(n1690), .Y(n1711) );
NAND2X2TS U2292 ( .A(n1693), .B(n1692), .Y(n1756) );
NAND2X1TS U2293 ( .A(n1695), .B(n1694), .Y(n1761) );
NAND2X2TS U2294 ( .A(n1697), .B(n1696), .Y(n1765) );
NAND2X1TS U2295 ( .A(n1699), .B(n1698), .Y(n1720) );
OAI21X1TS U2296 ( .A0(n1719), .A1(n1765), .B0(n1720), .Y(n1700) );
AOI21X2TS U2297 ( .A0(n1714), .A1(n1701), .B0(n1700), .Y(n1702) );
AOI21X4TS U2298 ( .A0(n1710), .A1(n1705), .B0(n1704), .Y(n1737) );
INVX2TS U2299 ( .A(n1737), .Y(n1725) );
INVX2TS U2300 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[16]), .Y(n2037) );
INVX2TS U2301 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[16]), .Y(n1726) );
CMPR32X2TS U2302 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[15]), .B(n2049),
.C(n1706), .CO(n1707), .S(n1699) );
NAND2X1TS U2303 ( .A(n1708), .B(n1707), .Y(n1724) );
NAND2X1TS U2304 ( .A(n1731), .B(n1724), .Y(n1709) );
XNOR2X1TS U2305 ( .A(n1725), .B(n1709), .Y(n1855) );
NOR2X2TS U2306 ( .A(n1855), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[4]), .Y(
n2192) );
INVX6TS U2307 ( .A(n1710), .Y(n1830) );
OAI21X4TS U2308 ( .A0(n1830), .A1(n1712), .B0(n1711), .Y(n1759) );
INVX2TS U2309 ( .A(n1713), .Y(n1716) );
OAI21X2TS U2310 ( .A0(n1755), .A1(n1716), .B0(n1715), .Y(n1768) );
INVX2TS U2311 ( .A(n1765), .Y(n1718) );
AOI21X2TS U2312 ( .A0(n1768), .A1(n1766), .B0(n1718), .Y(n1723) );
INVX2TS U2313 ( .A(n1719), .Y(n1721) );
NAND2X1TS U2314 ( .A(n1721), .B(n1720), .Y(n1722) );
CLKXOR2X2TS U2315 ( .A(n1723), .B(n1722), .Y(n1854) );
NOR2X2TS U2316 ( .A(n1854), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[3]), .Y(
n2189) );
INVX2TS U2317 ( .A(n1724), .Y(n1734) );
INVX2TS U2318 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[17]), .Y(n2028) );
INVX2TS U2319 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[17]), .Y(n1738) );
CMPR32X2TS U2320 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[16]), .B(n2037),
.C(n1726), .CO(n1727), .S(n1708) );
NAND2X1TS U2321 ( .A(n1728), .B(n1727), .Y(n1732) );
NAND2X1TS U2322 ( .A(n583), .B(n1732), .Y(n1729) );
NAND2X1TS U2323 ( .A(n1731), .B(n583), .Y(n1736) );
INVX2TS U2324 ( .A(n1732), .Y(n1733) );
AOI21X1TS U2325 ( .A0(n583), .A1(n1734), .B0(n1733), .Y(n1735) );
OAI21X4TS U2326 ( .A0(n1737), .A1(n1736), .B0(n1735), .Y(n1867) );
INVX2TS U2327 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[18]), .Y(n2020) );
INVX2TS U2328 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[18]), .Y(n1868) );
CMPR32X2TS U2329 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[17]), .B(n2028),
.C(n1738), .CO(n1739), .S(n1728) );
NAND2X1TS U2330 ( .A(n1740), .B(n1739), .Y(n1864) );
NAND2X1TS U2331 ( .A(n1866), .B(n1864), .Y(n1741) );
XNOR2X1TS U2332 ( .A(n1867), .B(n1741), .Y(n1857) );
NOR2X2TS U2333 ( .A(n1857), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[6]), .Y(
n2168) );
NAND2X2TS U2334 ( .A(n2162), .B(n1859), .Y(n1861) );
INVX2TS U2335 ( .A(n1742), .Y(n1745) );
INVX2TS U2336 ( .A(n1743), .Y(n1744) );
OAI21X2TS U2337 ( .A0(n1830), .A1(n1745), .B0(n1744), .Y(n1839) );
INVX2TS U2338 ( .A(n1746), .Y(n1837) );
INVX2TS U2339 ( .A(n1836), .Y(n1747) );
AOI21X1TS U2340 ( .A0(n1839), .A1(n1837), .B0(n1747), .Y(n1752) );
NAND2X1TS U2341 ( .A(n1750), .B(n1749), .Y(n1751) );
CLKXOR2X2TS U2342 ( .A(n1752), .B(n1751), .Y(n1848) );
NOR2X2TS U2343 ( .A(n1848), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[23]),
.Y(n2254) );
INVX2TS U2344 ( .A(n1753), .Y(n1758) );
NAND2X1TS U2345 ( .A(n1758), .B(n1756), .Y(n1754) );
XOR2X1TS U2346 ( .A(n1755), .B(n1754), .Y(n1849) );
NOR2X2TS U2347 ( .A(n1849), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[0]), .Y(
n2242) );
INVX2TS U2348 ( .A(n1756), .Y(n1757) );
AOI21X1TS U2349 ( .A0(n1759), .A1(n1758), .B0(n1757), .Y(n1764) );
NAND2X1TS U2350 ( .A(n1762), .B(n1761), .Y(n1763) );
XOR2X1TS U2351 ( .A(n1764), .B(n1763), .Y(n1850) );
NAND2X1TS U2352 ( .A(n1766), .B(n1765), .Y(n1767) );
XNOR2X1TS U2353 ( .A(n1768), .B(n1767), .Y(n1851) );
NOR2X2TS U2354 ( .A(n1851), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[2]), .Y(
n2220) );
NOR2X2TS U2355 ( .A(n2218), .B(n2220), .Y(n1853) );
NAND2X2TS U2356 ( .A(n2214), .B(n1853), .Y(n2161) );
NOR2X2TS U2357 ( .A(n1861), .B(n2161), .Y(n1863) );
AOI21X2TS U2358 ( .A0(n1799), .A1(n1771), .B0(n1770), .Y(n1822) );
NAND2X1TS U2359 ( .A(n1772), .B(n1820), .Y(n1773) );
XOR2X1TS U2360 ( .A(n1822), .B(n1773), .Y(n1815) );
NOR2X2TS U2361 ( .A(n1815), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[18]),
.Y(n2300) );
INVX2TS U2362 ( .A(n1774), .Y(n1797) );
INVX2TS U2363 ( .A(n1796), .Y(n1775) );
AOI21X1TS U2364 ( .A0(n1799), .A1(n1797), .B0(n1775), .Y(n1780) );
NAND2X1TS U2365 ( .A(n1778), .B(n1777), .Y(n1779) );
XOR2X1TS U2366 ( .A(n1780), .B(n1779), .Y(n1814) );
NOR2X2TS U2367 ( .A(n1814), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[17]),
.Y(n2298) );
NOR2X1TS U2368 ( .A(n2300), .B(n2298), .Y(n1817) );
NAND2X1TS U2369 ( .A(n1783), .B(n1782), .Y(n1785) );
XOR2X1TS U2370 ( .A(n1785), .B(n1784), .Y(n1790) );
NOR2X1TS U2371 ( .A(n1790), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[13]),
.Y(n2269) );
NAND2X1TS U2372 ( .A(n1787), .B(n1786), .Y(n1789) );
XNOR2X1TS U2373 ( .A(n1789), .B(n1788), .Y(n2332) );
NAND2X1TS U2374 ( .A(n2332), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[12]),
.Y(n2333) );
NAND2X1TS U2375 ( .A(n1790), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[13]),
.Y(n2270) );
OAI21X1TS U2376 ( .A0(n2269), .A1(n2333), .B0(n2270), .Y(n2329) );
INVX2TS U2377 ( .A(n1791), .Y(n1802) );
INVX2TS U2378 ( .A(n1801), .Y(n1792) );
NAND2X1TS U2379 ( .A(n1792), .B(n1800), .Y(n1793) );
XOR2X1TS U2380 ( .A(n1802), .B(n1793), .Y(n1794) );
NAND2X1TS U2381 ( .A(n1794), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[14]),
.Y(n2328) );
INVX2TS U2382 ( .A(n2328), .Y(n1795) );
AOI21X1TS U2383 ( .A0(n2329), .A1(n578), .B0(n1795), .Y(n2278) );
NAND2X1TS U2384 ( .A(n1797), .B(n1796), .Y(n1798) );
XNOR2X1TS U2385 ( .A(n1799), .B(n1798), .Y(n1810) );
OAI21X1TS U2386 ( .A0(n1802), .A1(n1801), .B0(n1800), .Y(n1807) );
NAND2X1TS U2387 ( .A(n1805), .B(n1804), .Y(n1806) );
XNOR2X1TS U2388 ( .A(n1807), .B(n1806), .Y(n1809) );
NAND2X1TS U2389 ( .A(n560), .B(n1808), .Y(n1813) );
NAND2X1TS U2390 ( .A(n1809), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[15]),
.Y(n2279) );
INVX2TS U2391 ( .A(n2279), .Y(n2282) );
NAND2X1TS U2392 ( .A(n1810), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[16]),
.Y(n2284) );
INVX2TS U2393 ( .A(n2284), .Y(n1811) );
AOI21X1TS U2394 ( .A0(n560), .A1(n2282), .B0(n1811), .Y(n1812) );
OAI21X1TS U2395 ( .A0(n2278), .A1(n1813), .B0(n1812), .Y(n2274) );
NAND2X1TS U2396 ( .A(n1814), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[17]),
.Y(n2297) );
NAND2X1TS U2397 ( .A(n1815), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[18]),
.Y(n2301) );
OAI21X1TS U2398 ( .A0(n2300), .A1(n2297), .B0(n2301), .Y(n1816) );
AOI21X2TS U2399 ( .A0(n1817), .A1(n2274), .B0(n1816), .Y(n2288) );
INVX2TS U2400 ( .A(n1829), .Y(n1818) );
NAND2X1TS U2401 ( .A(n1818), .B(n1828), .Y(n1819) );
XOR2X1TS U2402 ( .A(n1830), .B(n1819), .Y(n1841) );
NOR2X2TS U2403 ( .A(n1841), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[20]),
.Y(n2291) );
OAI21X1TS U2404 ( .A0(n1822), .A1(n1821), .B0(n1820), .Y(n1827) );
NAND2X1TS U2405 ( .A(n1825), .B(n1824), .Y(n1826) );
XNOR2X1TS U2406 ( .A(n1827), .B(n1826), .Y(n1840) );
NOR2X2TS U2407 ( .A(n2291), .B(n2289), .Y(n2312) );
OAI21X1TS U2408 ( .A0(n1830), .A1(n1829), .B0(n1828), .Y(n1835) );
NAND2X1TS U2409 ( .A(n1833), .B(n1832), .Y(n1834) );
XNOR2X1TS U2410 ( .A(n1835), .B(n1834), .Y(n1842) );
NOR2X2TS U2411 ( .A(n1842), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[21]),
.Y(n2318) );
NAND2X1TS U2412 ( .A(n1837), .B(n1836), .Y(n1838) );
XNOR2X1TS U2413 ( .A(n1839), .B(n1838), .Y(n1843) );
NOR2X2TS U2414 ( .A(n1843), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[22]),
.Y(n2320) );
NAND2X2TS U2415 ( .A(n1840), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[19]),
.Y(n2307) );
NAND2X1TS U2416 ( .A(n1841), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[20]),
.Y(n2292) );
NAND2X1TS U2417 ( .A(n1842), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[21]),
.Y(n2317) );
NAND2X1TS U2418 ( .A(n1843), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[22]),
.Y(n2321) );
OAI21X1TS U2419 ( .A0(n2320), .A1(n2317), .B0(n2321), .Y(n1844) );
AOI21X1TS U2420 ( .A0(n2311), .A1(n1845), .B0(n1844), .Y(n1846) );
OAI21X4TS U2421 ( .A0(n2288), .A1(n1847), .B0(n1846), .Y(n2159) );
NAND2X2TS U2422 ( .A(n1848), .B(Sgf_operation_RECURSIVE_EVEN1_Q_right[23]),
.Y(n2255) );
NAND2X1TS U2423 ( .A(n1849), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[0]),
.Y(n2243) );
OAI21X1TS U2424 ( .A0(n2242), .A1(n2255), .B0(n2243), .Y(n2215) );
NAND2X1TS U2425 ( .A(n1850), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[1]),
.Y(n2232) );
NAND2X1TS U2426 ( .A(n1851), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[2]),
.Y(n2221) );
OAI21X1TS U2427 ( .A0(n2220), .A1(n2232), .B0(n2221), .Y(n1852) );
AOI21X2TS U2428 ( .A0(n2215), .A1(n1853), .B0(n1852), .Y(n2160) );
NAND2X4TS U2429 ( .A(n1854), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[3]),
.Y(n2203) );
NAND2X1TS U2430 ( .A(n1855), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[4]),
.Y(n2193) );
OAI21X1TS U2431 ( .A0(n2192), .A1(n2203), .B0(n2193), .Y(n2163) );
NAND2X1TS U2432 ( .A(n1856), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[5]),
.Y(n2179) );
NAND2X1TS U2433 ( .A(n1857), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[6]),
.Y(n2169) );
OAI21X1TS U2434 ( .A0(n2168), .A1(n2179), .B0(n2169), .Y(n1858) );
OAI21X2TS U2435 ( .A0(n1861), .A1(n2160), .B0(n1860), .Y(n1862) );
AOI21X4TS U2436 ( .A0(n1863), .A1(n2159), .B0(n1862), .Y(n2046) );
INVX2TS U2437 ( .A(n1864), .Y(n1865) );
AOI21X4TS U2438 ( .A0(n1867), .A1(n1866), .B0(n1865), .Y(n1875) );
INVX2TS U2439 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[19]), .Y(n2012) );
INVX2TS U2440 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[19]), .Y(n1876) );
CMPR32X2TS U2441 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[18]), .B(n2020),
.C(n1868), .CO(n1869), .S(n1740) );
NOR2X1TS U2442 ( .A(n1870), .B(n1869), .Y(n1874) );
INVX2TS U2443 ( .A(n1874), .Y(n1871) );
NAND2X1TS U2444 ( .A(n1870), .B(n1869), .Y(n1873) );
NAND2X1TS U2445 ( .A(n1871), .B(n1873), .Y(n1872) );
XOR2X1TS U2446 ( .A(n1875), .B(n1872), .Y(n1916) );
OAI21X4TS U2447 ( .A0(n1875), .A1(n1874), .B0(n1873), .Y(n1883) );
INVX2TS U2448 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[20]), .Y(n1939) );
INVX2TS U2449 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[20]), .Y(n1884) );
CMPR32X2TS U2450 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[19]), .B(n2012),
.C(n1876), .CO(n1877), .S(n1870) );
NAND2X1TS U2451 ( .A(n1878), .B(n1877), .Y(n1880) );
NAND2X1TS U2452 ( .A(n1882), .B(n1880), .Y(n1879) );
NOR2X2TS U2453 ( .A(n1917), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[8]), .Y(
n2136) );
INVX2TS U2454 ( .A(n1880), .Y(n1881) );
AOI21X4TS U2455 ( .A0(n1883), .A1(n1882), .B0(n1881), .Y(n1891) );
INVX2TS U2456 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[21]), .Y(n1998) );
INVX2TS U2457 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[21]), .Y(n1892) );
CMPR32X2TS U2458 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[20]), .B(n1939),
.C(n1884), .CO(n1885), .S(n1878) );
NOR2X1TS U2459 ( .A(n1886), .B(n1885), .Y(n1890) );
INVX2TS U2460 ( .A(n1890), .Y(n1887) );
NAND2X1TS U2461 ( .A(n1886), .B(n1885), .Y(n1889) );
NAND2X1TS U2462 ( .A(n1887), .B(n1889), .Y(n1888) );
CLKXOR2X2TS U2463 ( .A(n1891), .B(n1888), .Y(n1918) );
NOR2X2TS U2464 ( .A(n1918), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[9]), .Y(
n2122) );
OAI21X4TS U2465 ( .A0(n1891), .A1(n1890), .B0(n1889), .Y(n1899) );
INVX2TS U2466 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[22]), .Y(n1931) );
INVX2TS U2467 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[22]), .Y(n1900) );
CMPR32X2TS U2468 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[21]), .B(n1998),
.C(n1892), .CO(n1893), .S(n1886) );
NAND2X1TS U2469 ( .A(n1894), .B(n1893), .Y(n1896) );
NAND2X1TS U2470 ( .A(n1898), .B(n1896), .Y(n1895) );
NOR2X2TS U2471 ( .A(n1919), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[10]),
.Y(n2108) );
NOR2X2TS U2472 ( .A(n2122), .B(n2108), .Y(n1921) );
NAND2X2TS U2473 ( .A(n2107), .B(n1921), .Y(n2057) );
INVX2TS U2474 ( .A(n1896), .Y(n1897) );
AOI21X4TS U2475 ( .A0(n1899), .A1(n1898), .B0(n1897), .Y(n1907) );
INVX2TS U2476 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[23]), .Y(n1936) );
INVX2TS U2477 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_right[23]), .Y(n1908) );
CMPR32X2TS U2478 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[22]), .B(n1931),
.C(n1900), .CO(n1901), .S(n1894) );
NOR2X1TS U2479 ( .A(n1902), .B(n1901), .Y(n1906) );
INVX2TS U2480 ( .A(n1906), .Y(n1903) );
NAND2X1TS U2481 ( .A(n1903), .B(n1905), .Y(n1904) );
CLKXOR2X2TS U2482 ( .A(n1907), .B(n1904), .Y(n1922) );
NOR2X2TS U2483 ( .A(n1922), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[11]),
.Y(n2095) );
OAI21X4TS U2484 ( .A0(n1907), .A1(n1906), .B0(n1905), .Y(n1914) );
CMPR32X2TS U2485 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_middle[23]), .B(n1936),
.C(n1908), .CO(n1909), .S(n1902) );
NAND2X1TS U2486 ( .A(n1913), .B(n1911), .Y(n1910) );
NOR2X4TS U2487 ( .A(Sgf_operation_RECURSIVE_EVEN1_Q_left[12]), .B(n1923),
.Y(n2083) );
NOR2X2TS U2488 ( .A(n2095), .B(n2083), .Y(n2062) );
INVX2TS U2489 ( .A(n1911), .Y(n1912) );
AOI21X2TS U2490 ( .A0(n1914), .A1(n1913), .B0(n1912), .Y(n1915) );
XOR2X4TS U2491 ( .A(n1915), .B(Sgf_operation_RECURSIVE_EVEN1_Q_middle[25]),
.Y(n1924) );
NOR2X4TS U2492 ( .A(n1924), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[13]),
.Y(n2071) );
NAND2X1TS U2493 ( .A(n1917), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[8]),
.Y(n2137) );
OAI21X1TS U2494 ( .A0(n2136), .A1(n2147), .B0(n2137), .Y(n2106) );
NAND2X1TS U2495 ( .A(n1918), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[9]),
.Y(n2123) );
NAND2X1TS U2496 ( .A(n1919), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[10]),
.Y(n2109) );
OAI21X1TS U2497 ( .A0(n2108), .A1(n2123), .B0(n2109), .Y(n1920) );
AOI21X2TS U2498 ( .A0(n2106), .A1(n1921), .B0(n1920), .Y(n2058) );
NAND2X2TS U2499 ( .A(n1922), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[11]),
.Y(n2096) );
OAI21X2TS U2500 ( .A0(n2083), .A1(n2096), .B0(n2084), .Y(n2061) );
NAND2X2TS U2501 ( .A(n1924), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[13]),
.Y(n2072) );
NOR2X4TS U2502 ( .A(n2072), .B(n2063), .Y(n1925) );
AOI21X4TS U2503 ( .A0(n2061), .A1(n1926), .B0(n1925), .Y(n1927) );
OAI21X4TS U2504 ( .A0(n2058), .A1(n1928), .B0(n1927), .Y(n2047) );
OAI21X4TS U2505 ( .A0(n2046), .A1(n1930), .B0(n1929), .Y(n2038) );
NAND2X4TS U2506 ( .A(n2021), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[18]),
.Y(n2013) );
NOR2X8TS U2507 ( .A(n2013), .B(n2012), .Y(n1940) );
NAND2X8TS U2508 ( .A(n1940), .B(Sgf_operation_RECURSIVE_EVEN1_Q_left[20]),
.Y(n1999) );
XNOR2X4TS U2509 ( .A(n1935), .B(n1931), .Y(n1934) );
NAND2X2TS U2510 ( .A(n562), .B(n1932), .Y(n1953) );
CLKMX2X2TS U2511 ( .A(P_Sgf[46]), .B(n1934), .S0(n2337), .Y(n261) );
XOR2X4TS U2512 ( .A(n1937), .B(n1936), .Y(n1938) );
BUFX3TS U2513 ( .A(n2305), .Y(n2340) );
XNOR2X1TS U2514 ( .A(n1940), .B(n1939), .Y(n1941) );
INVX2TS U2515 ( .A(rst), .Y(n2424) );
BUFX3TS U2516 ( .A(n2424), .Y(n2404) );
BUFX3TS U2517 ( .A(n2424), .Y(n2402) );
BUFX3TS U2518 ( .A(n2424), .Y(n2401) );
NOR2XLTS U2519 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[1]), .Y(
n1942) );
BUFX3TS U2520 ( .A(n2416), .Y(n2420) );
CLKBUFX2TS U2521 ( .A(n1955), .Y(n1943) );
BUFX3TS U2522 ( .A(n2417), .Y(n2421) );
BUFX3TS U2523 ( .A(n2424), .Y(n2403) );
BUFX3TS U2524 ( .A(n2416), .Y(n2407) );
BUFX3TS U2525 ( .A(n1943), .Y(n2409) );
BUFX3TS U2526 ( .A(n1943), .Y(n2410) );
BUFX3TS U2527 ( .A(n2417), .Y(n2408) );
BUFX3TS U2528 ( .A(n2416), .Y(n2412) );
CLKBUFX2TS U2529 ( .A(n2417), .Y(n2422) );
BUFX3TS U2530 ( .A(n1943), .Y(n2414) );
BUFX3TS U2531 ( .A(n2417), .Y(n2415) );
BUFX3TS U2532 ( .A(n2424), .Y(n2405) );
BUFX3TS U2533 ( .A(n1955), .Y(n2406) );
NAND2X1TS U2534 ( .A(FS_Module_state_reg[2]), .B(n562), .Y(n2263) );
NAND2X1TS U2535 ( .A(n1967), .B(n2263), .Y(n1944) );
OAI21X2TS U2536 ( .A0(n1946), .A1(n1945), .B0(FS_Module_state_reg[1]), .Y(
n1994) );
BUFX3TS U2537 ( .A(n2128), .Y(n2114) );
AOI22X1TS U2538 ( .A0(n446), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n2114), .Y(n1950) );
OAI2BB1X1TS U2539 ( .A0N(n559), .A1N(P_Sgf[24]), .B0(n1950), .Y(n1951) );
AOI21X1TS U2540 ( .A0(n556), .A1(Add_result[0]), .B0(n1951), .Y(n1952) );
OAI2BB1X1TS U2541 ( .A0N(P_Sgf[23]), .A1N(n524), .B0(n1952), .Y(n191) );
BUFX3TS U2542 ( .A(n2375), .Y(n2371) );
INVX2TS U2543 ( .A(n2371), .Y(n2379) );
INVX2TS U2544 ( .A(n2372), .Y(n2376) );
AO22X1TS U2545 ( .A0(Sgf_normalized_result[22]), .A1(n2379), .B0(
final_result_ieee[22]), .B1(n2376), .Y(n167) );
AO22X1TS U2546 ( .A0(Sgf_normalized_result[20]), .A1(n2379), .B0(
final_result_ieee[20]), .B1(n2378), .Y(n170) );
BUFX3TS U2547 ( .A(n1955), .Y(n2417) );
BUFX3TS U2548 ( .A(n2422), .Y(n2419) );
BUFX3TS U2549 ( .A(n2422), .Y(n2418) );
BUFX3TS U2550 ( .A(n2422), .Y(n2411) );
BUFX3TS U2551 ( .A(n2422), .Y(n2413) );
BUFX3TS U2552 ( .A(n1955), .Y(n2416) );
INVX2TS U2553 ( .A(n2368), .Y(n2344) );
OAI31X1TS U2554 ( .A0(n2044), .A1(n2344), .A2(n2382), .B0(n1960), .Y(n308)
);
INVX2TS U2555 ( .A(n2044), .Y(n2240) );
NAND2X1TS U2556 ( .A(Add_result[0]), .B(n2240), .Y(n1959) );
OAI32X1TS U2557 ( .A0(n2378), .A1(n1962), .A2(overflow_flag), .B0(n2370),
.B1(n2399), .Y(n262) );
NAND2X1TS U2558 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n1968) );
NOR3X1TS U2559 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n1968), .Y(ready) );
INVX2TS U2560 ( .A(ready), .Y(n1963) );
AOI32X1TS U2561 ( .A0(FS_Module_state_reg[1]), .A1(n2383), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n2266), .Y(
n1964) );
INVX2TS U2562 ( .A(n527), .Y(n2339) );
AOI22X1TS U2563 ( .A0(n1970), .A1(n1969), .B0(n2265), .B1(n1968), .Y(n1971)
);
NOR3BX1TS U2564 ( .AN(Op_MY[30]), .B(FSM_selector_B[1]), .C(
FSM_selector_B[0]), .Y(n1972) );
XOR2X1TS U2565 ( .A(n527), .B(n1972), .Y(DP_OP_36J22_124_9196_n15) );
OAI2BB1X1TS U2566 ( .A0N(Op_MY[29]), .A1N(n2382), .B0(n567), .Y(n1973) );
XOR2X1TS U2567 ( .A(n527), .B(n1973), .Y(DP_OP_36J22_124_9196_n16) );
OAI2BB1X1TS U2568 ( .A0N(Op_MY[28]), .A1N(n2382), .B0(n567), .Y(n1974) );
XOR2X1TS U2569 ( .A(n527), .B(n1974), .Y(DP_OP_36J22_124_9196_n17) );
OAI2BB1X1TS U2570 ( .A0N(Op_MY[27]), .A1N(n2382), .B0(n567), .Y(n1975) );
XOR2X1TS U2571 ( .A(n527), .B(n1975), .Y(DP_OP_36J22_124_9196_n18) );
OAI2BB1X1TS U2572 ( .A0N(Op_MY[26]), .A1N(n2382), .B0(n567), .Y(n1976) );
XOR2X1TS U2573 ( .A(n527), .B(n1976), .Y(DP_OP_36J22_124_9196_n19) );
OAI2BB1X1TS U2574 ( .A0N(Op_MY[25]), .A1N(n2382), .B0(n567), .Y(n1977) );
XOR2X1TS U2575 ( .A(n527), .B(n1977), .Y(DP_OP_36J22_124_9196_n20) );
OAI2BB1X1TS U2576 ( .A0N(Op_MY[24]), .A1N(n2382), .B0(n567), .Y(n1978) );
XOR2X1TS U2577 ( .A(n527), .B(n1978), .Y(DP_OP_36J22_124_9196_n21) );
XOR2X1TS U2578 ( .A(n1954), .B(n1980), .Y(DP_OP_36J22_124_9196_n22) );
INVX2TS U2579 ( .A(n1983), .Y(n1984) );
NAND2X1TS U2580 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n1988) );
NAND2X1TS U2581 ( .A(Sgf_normalized_result[5]), .B(Sgf_normalized_result[4]),
.Y(n2156) );
NOR2X1TS U2582 ( .A(n2384), .B(n2388), .Y(n2119) );
NAND2X1TS U2583 ( .A(n2119), .B(Sgf_normalized_result[10]), .Y(n1991) );
MXI2X1TS U2584 ( .A(P_Sgf[46]), .B(Add_result[23]), .S0(FSM_selector_C), .Y(
n1993) );
AOI21X1TS U2585 ( .A0(n1994), .A1(n1993), .B0(n2128), .Y(n1995) );
AHHCINX2TS U2586 ( .A(Sgf_normalized_result[22]), .CIN(n1996), .S(n1997),
.CO(n2260) );
INVX2TS U2587 ( .A(n2044), .Y(n2035) );
XOR2X1TS U2588 ( .A(n1999), .B(n1998), .Y(n2000) );
AOI22X1TS U2589 ( .A0(n447), .A1(Add_result[23]), .B0(
Sgf_normalized_result[22]), .B1(n2128), .Y(n2001) );
OAI2BB1X1TS U2590 ( .A0N(P_Sgf[46]), .A1N(n558), .B0(n2001), .Y(n2002) );
AOI21X1TS U2591 ( .A0(n2252), .A1(Add_result[22]), .B0(n2002), .Y(n2003) );
OAI2BB1X1TS U2592 ( .A0N(n522), .A1N(P_Sgf[45]), .B0(n2003), .Y(n213) );
AHHCONX2TS U2593 ( .A(Sgf_normalized_result[21]), .CI(n2004), .CON(n1996),
.S(n2005) );
AOI22X1TS U2594 ( .A0(n2006), .A1(Add_result[22]), .B0(
Sgf_normalized_result[21]), .B1(n2128), .Y(n2007) );
OAI2BB1X1TS U2595 ( .A0N(P_Sgf[45]), .A1N(n557), .B0(n2007), .Y(n2008) );
AOI21X1TS U2596 ( .A0(n556), .A1(Add_result[21]), .B0(n2008), .Y(n2009) );
OAI2BB1X1TS U2597 ( .A0N(n522), .A1N(P_Sgf[44]), .B0(n2009), .Y(n212) );
AHHCINX2TS U2598 ( .A(Sgf_normalized_result[20]), .CIN(n2010), .S(n2011),
.CO(n2004) );
XOR2X1TS U2599 ( .A(n2013), .B(n2012), .Y(n2014) );
AOI22X1TS U2600 ( .A0(n447), .A1(Add_result[21]), .B0(
Sgf_normalized_result[20]), .B1(n2128), .Y(n2015) );
OAI2BB1X1TS U2601 ( .A0N(n558), .A1N(P_Sgf[44]), .B0(n2015), .Y(n2016) );
AOI21X1TS U2602 ( .A0(n1948), .A1(Add_result[20]), .B0(n2016), .Y(n2017) );
OAI2BB1X1TS U2603 ( .A0N(n522), .A1N(P_Sgf[43]), .B0(n2017), .Y(n211) );
AHHCONX2TS U2604 ( .A(Sgf_normalized_result[19]), .CI(n2018), .CON(n2010),
.S(n2019) );
XNOR2X1TS U2605 ( .A(n2021), .B(n2020), .Y(n2022) );
AOI22X1TS U2606 ( .A0(n446), .A1(Add_result[20]), .B0(
Sgf_normalized_result[19]), .B1(n2114), .Y(n2023) );
OAI2BB1X1TS U2607 ( .A0N(n559), .A1N(P_Sgf[43]), .B0(n2023), .Y(n2024) );
AOI21X1TS U2608 ( .A0(n556), .A1(Add_result[19]), .B0(n2024), .Y(n2025) );
OAI2BB1X1TS U2609 ( .A0N(n522), .A1N(P_Sgf[42]), .B0(n2025), .Y(n210) );
AHHCINX2TS U2610 ( .A(Sgf_normalized_result[18]), .CIN(n2026), .S(n2027),
.CO(n2018) );
XOR2X1TS U2611 ( .A(n2029), .B(n2028), .Y(n2030) );
AOI22X1TS U2612 ( .A0(n447), .A1(Add_result[19]), .B0(
Sgf_normalized_result[18]), .B1(n2114), .Y(n2031) );
OAI2BB1X1TS U2613 ( .A0N(n559), .A1N(P_Sgf[42]), .B0(n2031), .Y(n2032) );
AOI21X1TS U2614 ( .A0(n1948), .A1(Add_result[18]), .B0(n2032), .Y(n2033) );
OAI2BB1X1TS U2615 ( .A0N(n522), .A1N(P_Sgf[41]), .B0(n2033), .Y(n209) );
AHHCONX2TS U2616 ( .A(Sgf_normalized_result[17]), .CI(n2034), .CON(n2026),
.S(n2036) );
XNOR2X1TS U2617 ( .A(n2038), .B(n2037), .Y(n2039) );
AOI22X1TS U2618 ( .A0(n2006), .A1(Add_result[18]), .B0(
Sgf_normalized_result[17]), .B1(n2114), .Y(n2040) );
OAI2BB1X1TS U2619 ( .A0N(n557), .A1N(P_Sgf[41]), .B0(n2040), .Y(n2041) );
AOI21X1TS U2620 ( .A0(n556), .A1(Add_result[17]), .B0(n2041), .Y(n2042) );
OAI2BB1X1TS U2621 ( .A0N(n522), .A1N(P_Sgf[40]), .B0(n2042), .Y(n208) );
AHHCINX2TS U2622 ( .A(Sgf_normalized_result[16]), .CIN(n2043), .S(n2045),
.CO(n2034) );
AOI21X1TS U2623 ( .A0(n2150), .A1(n2048), .B0(n2047), .Y(n2050) );
XOR2X1TS U2624 ( .A(n2050), .B(n2049), .Y(n2051) );
AOI22X1TS U2625 ( .A0(n446), .A1(Add_result[17]), .B0(
Sgf_normalized_result[16]), .B1(n2114), .Y(n2052) );
OAI2BB1X1TS U2626 ( .A0N(n557), .A1N(P_Sgf[40]), .B0(n2052), .Y(n2053) );
AOI21X1TS U2627 ( .A0(n556), .A1(Add_result[16]), .B0(n2053), .Y(n2054) );
OAI2BB1X1TS U2628 ( .A0N(n523), .A1N(P_Sgf[39]), .B0(n2054), .Y(n207) );
AHHCONX2TS U2629 ( .A(Sgf_normalized_result[15]), .CI(n2055), .CON(n2043),
.S(n2056) );
INVX2TS U2630 ( .A(n2057), .Y(n2060) );
INVX2TS U2631 ( .A(n2058), .Y(n2059) );
AOI21X4TS U2632 ( .A0(n2150), .A1(n2060), .B0(n2059), .Y(n2082) );
AOI21X2TS U2633 ( .A0(n2099), .A1(n2062), .B0(n2061), .Y(n2075) );
XNOR2X1TS U2634 ( .A(n2064), .B(n2063), .Y(n2065) );
CLKMX2X2TS U2635 ( .A(P_Sgf[38]), .B(n2065), .S0(n2088), .Y(n253) );
AOI22X1TS U2636 ( .A0(n2006), .A1(Add_result[16]), .B0(
Sgf_normalized_result[15]), .B1(n2114), .Y(n2066) );
OAI2BB1X1TS U2637 ( .A0N(n558), .A1N(P_Sgf[39]), .B0(n2066), .Y(n2067) );
AOI21X1TS U2638 ( .A0(n556), .A1(Add_result[15]), .B0(n2067), .Y(n2068) );
OAI2BB1X1TS U2639 ( .A0N(n524), .A1N(P_Sgf[38]), .B0(n2068), .Y(n206) );
AHHCINX2TS U2640 ( .A(Sgf_normalized_result[14]), .CIN(n2069), .S(n2070),
.CO(n2055) );
INVX2TS U2641 ( .A(n2071), .Y(n2073) );
NAND2X1TS U2642 ( .A(n2073), .B(n2072), .Y(n2074) );
XOR2X1TS U2643 ( .A(n2075), .B(n2074), .Y(n2076) );
AOI22X1TS U2644 ( .A0(n446), .A1(Add_result[15]), .B0(
Sgf_normalized_result[14]), .B1(n2114), .Y(n2077) );
OAI2BB1X1TS U2645 ( .A0N(n558), .A1N(P_Sgf[38]), .B0(n2077), .Y(n2078) );
AOI21X1TS U2646 ( .A0(n1948), .A1(Add_result[14]), .B0(n2078), .Y(n2079) );
OAI2BB1X1TS U2647 ( .A0N(n523), .A1N(P_Sgf[37]), .B0(n2079), .Y(n205) );
AHHCONX2TS U2648 ( .A(Sgf_normalized_result[13]), .CI(n2080), .CON(n2069),
.S(n2081) );
INVX2TS U2649 ( .A(n2083), .Y(n2085) );
NAND2X1TS U2650 ( .A(n2085), .B(n2084), .Y(n2086) );
XNOR2X1TS U2651 ( .A(n2087), .B(n2086), .Y(n2089) );
CLKMX2X2TS U2652 ( .A(P_Sgf[36]), .B(n2089), .S0(n2088), .Y(n251) );
AOI22X1TS U2653 ( .A0(n447), .A1(Add_result[14]), .B0(
Sgf_normalized_result[13]), .B1(n2114), .Y(n2090) );
OAI2BB1X1TS U2654 ( .A0N(n559), .A1N(P_Sgf[37]), .B0(n2090), .Y(n2091) );
AOI21X1TS U2655 ( .A0(n556), .A1(Add_result[13]), .B0(n2091), .Y(n2092) );
OAI2BB1X1TS U2656 ( .A0N(n524), .A1N(P_Sgf[36]), .B0(n2092), .Y(n204) );
AHHCINX2TS U2657 ( .A(Sgf_normalized_result[12]), .CIN(n2093), .S(n2094),
.CO(n2080) );
INVX2TS U2658 ( .A(n2095), .Y(n2097) );
NAND2X1TS U2659 ( .A(n2097), .B(n2096), .Y(n2098) );
XNOR2X1TS U2660 ( .A(n2099), .B(n2098), .Y(n2100) );
AOI22X1TS U2661 ( .A0(n447), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n2114), .Y(n2101) );
OAI2BB1X1TS U2662 ( .A0N(n559), .A1N(P_Sgf[36]), .B0(n2101), .Y(n2102) );
AOI21X1TS U2663 ( .A0(n556), .A1(Add_result[12]), .B0(n2102), .Y(n2103) );
OAI2BB1X1TS U2664 ( .A0N(n523), .A1N(P_Sgf[35]), .B0(n2103), .Y(n203) );
AHHCONX2TS U2665 ( .A(Sgf_normalized_result[11]), .CI(n2104), .CON(n2093),
.S(n2105) );
OAI21X1TS U2666 ( .A0(n2126), .A1(n2122), .B0(n2123), .Y(n2112) );
NAND2X1TS U2667 ( .A(n2110), .B(n2109), .Y(n2111) );
XNOR2X1TS U2668 ( .A(n2112), .B(n2111), .Y(n2113) );
CLKMX2X2TS U2669 ( .A(P_Sgf[34]), .B(n2113), .S0(n2225), .Y(n249) );
AOI22X1TS U2670 ( .A0(n2006), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n2114), .Y(n2115) );
OAI2BB1X1TS U2671 ( .A0N(n557), .A1N(P_Sgf[35]), .B0(n2115), .Y(n2116) );
AOI21X1TS U2672 ( .A0(n556), .A1(Add_result[11]), .B0(n2116), .Y(n2117) );
OAI2BB1X1TS U2673 ( .A0N(n524), .A1N(P_Sgf[34]), .B0(n2117), .Y(n202) );
NAND2X1TS U2674 ( .A(n2145), .B(n2119), .Y(n2120) );
XOR2X1TS U2675 ( .A(n2120), .B(n2396), .Y(n2121) );
INVX2TS U2676 ( .A(n2122), .Y(n2124) );
NAND2X1TS U2677 ( .A(n2124), .B(n2123), .Y(n2125) );
XOR2X1TS U2678 ( .A(n2126), .B(n2125), .Y(n2127) );
BUFX3TS U2679 ( .A(n2128), .Y(n2248) );
AOI22X1TS U2680 ( .A0(n446), .A1(Add_result[11]), .B0(
Sgf_normalized_result[10]), .B1(n2248), .Y(n2129) );
OAI2BB1X1TS U2681 ( .A0N(n557), .A1N(P_Sgf[34]), .B0(n2129), .Y(n2130) );
AOI21X1TS U2682 ( .A0(n2252), .A1(Add_result[10]), .B0(n2130), .Y(n2131) );
OAI2BB1X1TS U2683 ( .A0N(n523), .A1N(P_Sgf[33]), .B0(n2131), .Y(n201) );
NAND2X1TS U2684 ( .A(n2145), .B(Sgf_normalized_result[8]), .Y(n2132) );
XOR2X1TS U2685 ( .A(n2132), .B(n2388), .Y(n2133) );
INVX2TS U2686 ( .A(n2134), .Y(n2148) );
INVX2TS U2687 ( .A(n2147), .Y(n2135) );
AOI21X1TS U2688 ( .A0(n2150), .A1(n2148), .B0(n2135), .Y(n2140) );
NAND2X1TS U2689 ( .A(n2138), .B(n2137), .Y(n2139) );
XOR2X1TS U2690 ( .A(n2140), .B(n2139), .Y(n2141) );
AOI22X1TS U2691 ( .A0(n447), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n2248), .Y(n2142) );
OAI2BB1X1TS U2692 ( .A0N(n558), .A1N(P_Sgf[33]), .B0(n2142), .Y(n2143) );
AOI21X1TS U2693 ( .A0(n2252), .A1(Add_result[9]), .B0(n2143), .Y(n2144) );
OAI2BB1X1TS U2694 ( .A0N(n524), .A1N(P_Sgf[32]), .B0(n2144), .Y(n200) );
XNOR2X1TS U2695 ( .A(n2145), .B(n2384), .Y(n2146) );
NAND2X1TS U2696 ( .A(n2148), .B(n2147), .Y(n2149) );
XNOR2X1TS U2697 ( .A(n2150), .B(n2149), .Y(n2151) );
AOI22X1TS U2698 ( .A0(n447), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n2248), .Y(n2152) );
OAI2BB1X1TS U2699 ( .A0N(n559), .A1N(P_Sgf[32]), .B0(n2152), .Y(n2153) );
AOI21X1TS U2700 ( .A0(n2252), .A1(Add_result[8]), .B0(n2153), .Y(n2154) );
OAI2BB1X1TS U2701 ( .A0N(n523), .A1N(P_Sgf[31]), .B0(n2154), .Y(n199) );
OAI21X1TS U2702 ( .A0(n2201), .A1(n2389), .B0(n2156), .Y(n2177) );
NAND2X1TS U2703 ( .A(n2177), .B(Sgf_normalized_result[6]), .Y(n2157) );
XOR2X1TS U2704 ( .A(n2157), .B(n2397), .Y(n2158) );
OAI21X2TS U2705 ( .A0(n2258), .A1(n2161), .B0(n2160), .Y(n2191) );
INVX2TS U2706 ( .A(n2191), .Y(n2206) );
INVX2TS U2707 ( .A(n2162), .Y(n2165) );
INVX2TS U2708 ( .A(n2163), .Y(n2164) );
OAI21X2TS U2709 ( .A0(n2206), .A1(n2165), .B0(n2164), .Y(n2182) );
INVX2TS U2710 ( .A(n2166), .Y(n2180) );
INVX2TS U2711 ( .A(n2179), .Y(n2167) );
AOI21X1TS U2712 ( .A0(n2182), .A1(n2180), .B0(n2167), .Y(n2172) );
INVX2TS U2713 ( .A(n2168), .Y(n2170) );
NAND2X1TS U2714 ( .A(n2170), .B(n2169), .Y(n2171) );
XOR2X1TS U2715 ( .A(n2172), .B(n2171), .Y(n2173) );
AOI22X1TS U2716 ( .A0(n2006), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n2248), .Y(n2174) );
OAI2BB1X1TS U2717 ( .A0N(n557), .A1N(P_Sgf[31]), .B0(n2174), .Y(n2175) );
AOI21X1TS U2718 ( .A0(n2252), .A1(Add_result[7]), .B0(n2175), .Y(n2176) );
OAI2BB1X1TS U2719 ( .A0N(n524), .A1N(P_Sgf[30]), .B0(n2176), .Y(n198) );
XNOR2X1TS U2720 ( .A(n2177), .B(n2393), .Y(n2178) );
NAND2X1TS U2721 ( .A(n2180), .B(n2179), .Y(n2181) );
XNOR2X1TS U2722 ( .A(n2182), .B(n2181), .Y(n2183) );
AOI22X1TS U2723 ( .A0(n446), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n2248), .Y(n2184) );
OAI2BB1X1TS U2724 ( .A0N(n558), .A1N(P_Sgf[30]), .B0(n2184), .Y(n2185) );
AOI21X1TS U2725 ( .A0(n2252), .A1(Add_result[6]), .B0(n2185), .Y(n2186) );
OAI2BB1X1TS U2726 ( .A0N(n523), .A1N(P_Sgf[29]), .B0(n2186), .Y(n197) );
NAND2X1TS U2727 ( .A(n2201), .B(n2392), .Y(n2187) );
XNOR2X1TS U2728 ( .A(n2187), .B(n2389), .Y(n2188) );
INVX2TS U2729 ( .A(n2189), .Y(n2204) );
INVX2TS U2730 ( .A(n2203), .Y(n2190) );
AOI21X1TS U2731 ( .A0(n2191), .A1(n2204), .B0(n2190), .Y(n2196) );
INVX2TS U2732 ( .A(n2192), .Y(n2194) );
NAND2X1TS U2733 ( .A(n2194), .B(n2193), .Y(n2195) );
XOR2X1TS U2734 ( .A(n2196), .B(n2195), .Y(n2197) );
AOI22X1TS U2735 ( .A0(n446), .A1(Add_result[6]), .B0(
Sgf_normalized_result[5]), .B1(n2248), .Y(n2198) );
OAI2BB1X1TS U2736 ( .A0N(n559), .A1N(P_Sgf[29]), .B0(n2198), .Y(n2199) );
AOI21X1TS U2737 ( .A0(n2252), .A1(Add_result[5]), .B0(n2199), .Y(n2200) );
OAI2BB1X1TS U2738 ( .A0N(n524), .A1N(P_Sgf[28]), .B0(n2200), .Y(n196) );
XOR2X1TS U2739 ( .A(n2201), .B(Sgf_normalized_result[4]), .Y(n2202) );
NAND2X1TS U2740 ( .A(n2204), .B(n2203), .Y(n2205) );
XOR2X1TS U2741 ( .A(n2206), .B(n2205), .Y(n2207) );
AOI22X1TS U2742 ( .A0(n447), .A1(Add_result[5]), .B0(
Sgf_normalized_result[4]), .B1(n2248), .Y(n2208) );
OAI2BB1X1TS U2743 ( .A0N(n557), .A1N(P_Sgf[28]), .B0(n2208), .Y(n2209) );
AOI21X1TS U2744 ( .A0(n2252), .A1(Add_result[4]), .B0(n2209), .Y(n2210) );
OAI2BB1X1TS U2745 ( .A0N(n523), .A1N(P_Sgf[27]), .B0(n2210), .Y(n195) );
XOR2X1TS U2746 ( .A(n2212), .B(n2387), .Y(n2213) );
INVX2TS U2747 ( .A(n2214), .Y(n2217) );
INVX2TS U2748 ( .A(n2215), .Y(n2216) );
OAI21X1TS U2749 ( .A0(n2258), .A1(n2217), .B0(n2216), .Y(n2235) );
INVX2TS U2750 ( .A(n2218), .Y(n2233) );
INVX2TS U2751 ( .A(n2232), .Y(n2219) );
AOI21X1TS U2752 ( .A0(n2235), .A1(n2233), .B0(n2219), .Y(n2224) );
NAND2X1TS U2753 ( .A(n2222), .B(n2221), .Y(n2223) );
XOR2X1TS U2754 ( .A(n2224), .B(n2223), .Y(n2226) );
AOI22X1TS U2755 ( .A0(n446), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n2248), .Y(n2227) );
OAI2BB1X1TS U2756 ( .A0N(n558), .A1N(P_Sgf[27]), .B0(n2227), .Y(n2228) );
AOI21X1TS U2757 ( .A0(n2252), .A1(Add_result[3]), .B0(n2228), .Y(n2229) );
OAI2BB1X1TS U2758 ( .A0N(n524), .A1N(P_Sgf[26]), .B0(n2229), .Y(n194) );
XOR2X1TS U2759 ( .A(n2230), .B(Sgf_normalized_result[2]), .Y(n2231) );
NAND2X1TS U2760 ( .A(n2233), .B(n2232), .Y(n2234) );
XNOR2X1TS U2761 ( .A(n2235), .B(n2234), .Y(n2236) );
AOI22X1TS U2762 ( .A0(n446), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n2248), .Y(n2237) );
OAI2BB1X1TS U2763 ( .A0N(n557), .A1N(P_Sgf[26]), .B0(n2237), .Y(n2238) );
AOI21X1TS U2764 ( .A0(n2252), .A1(Add_result[2]), .B0(n2238), .Y(n2239) );
OAI2BB1X1TS U2765 ( .A0N(n522), .A1N(P_Sgf[25]), .B0(n2239), .Y(n193) );
XNOR2X1TS U2766 ( .A(Sgf_normalized_result[0]), .B(Sgf_normalized_result[1]),
.Y(n2241) );
INVX2TS U2767 ( .A(n2242), .Y(n2244) );
NAND2X1TS U2768 ( .A(n2244), .B(n2243), .Y(n2245) );
XNOR2X1TS U2769 ( .A(n2246), .B(n2245), .Y(n2247) );
AOI22X1TS U2770 ( .A0(n2006), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n2248), .Y(n2249) );
OAI2BB1X1TS U2771 ( .A0N(n558), .A1N(P_Sgf[25]), .B0(n2249), .Y(n2251) );
AOI21X1TS U2772 ( .A0(n556), .A1(Add_result[1]), .B0(n2251), .Y(n2253) );
OAI2BB1X1TS U2773 ( .A0N(n523), .A1N(P_Sgf[24]), .B0(n2253), .Y(n192) );
INVX2TS U2774 ( .A(n2254), .Y(n2256) );
NAND2X1TS U2775 ( .A(n2256), .B(n2255), .Y(n2257) );
XOR2X1TS U2776 ( .A(n2258), .B(n2257), .Y(n2259) );
ADDHXLTS U2777 ( .A(Sgf_normalized_result[23]), .B(n2260), .CO(n2262), .S(
n1992) );
AOI22X1TS U2778 ( .A0(n2265), .A1(n2264), .B0(n2390), .B1(n2383), .Y(n2268)
);
AOI21X1TS U2779 ( .A0(n2268), .A1(n2267), .B0(n2266), .Y(n378) );
INVX2TS U2780 ( .A(n2269), .Y(n2271) );
NAND2X1TS U2781 ( .A(n2271), .B(n2270), .Y(n2272) );
XOR2X1TS U2782 ( .A(n2272), .B(n2333), .Y(n2273) );
INVX2TS U2783 ( .A(n2274), .Y(n2299) );
INVX2TS U2784 ( .A(n2298), .Y(n2275) );
NAND2X1TS U2785 ( .A(n2275), .B(n2297), .Y(n2276) );
XOR2X1TS U2786 ( .A(n2299), .B(n2276), .Y(n2277) );
INVX2TS U2787 ( .A(n2278), .Y(n2283) );
NAND2X1TS U2788 ( .A(n1808), .B(n2279), .Y(n2280) );
XNOR2X1TS U2789 ( .A(n2283), .B(n2280), .Y(n2281) );
AOI21X1TS U2790 ( .A0(n2283), .A1(n1808), .B0(n2282), .Y(n2286) );
NAND2X1TS U2791 ( .A(n560), .B(n2284), .Y(n2285) );
XOR2X1TS U2792 ( .A(n2286), .B(n2285), .Y(n2287) );
INVX2TS U2793 ( .A(n2288), .Y(n2313) );
INVX2TS U2794 ( .A(n2289), .Y(n2308) );
INVX2TS U2795 ( .A(n2307), .Y(n2290) );
AOI21X1TS U2796 ( .A0(n2313), .A1(n2308), .B0(n2290), .Y(n2295) );
INVX2TS U2797 ( .A(n2291), .Y(n2293) );
NAND2X1TS U2798 ( .A(n2293), .B(n2292), .Y(n2294) );
XOR2X1TS U2799 ( .A(n2295), .B(n2294), .Y(n2296) );
INVX2TS U2800 ( .A(n2300), .Y(n2302) );
NAND2X1TS U2801 ( .A(n2302), .B(n2301), .Y(n2303) );
XNOR2X1TS U2802 ( .A(n2304), .B(n2303), .Y(n2306) );
BUFX3TS U2803 ( .A(n2305), .Y(n2326) );
NAND2X1TS U2804 ( .A(n2308), .B(n2307), .Y(n2309) );
XNOR2X1TS U2805 ( .A(n2313), .B(n2309), .Y(n2310) );
AOI21X1TS U2806 ( .A0(n2313), .A1(n2312), .B0(n2311), .Y(n2319) );
INVX2TS U2807 ( .A(n2318), .Y(n2314) );
NAND2X1TS U2808 ( .A(n2314), .B(n2317), .Y(n2315) );
XOR2X1TS U2809 ( .A(n2319), .B(n2315), .Y(n2316) );
NAND2X1TS U2810 ( .A(n2322), .B(n2321), .Y(n2323) );
XNOR2X1TS U2811 ( .A(n2324), .B(n2323), .Y(n2325) );
NAND2X1TS U2812 ( .A(n578), .B(n2328), .Y(n2330) );
XNOR2X1TS U2813 ( .A(n2330), .B(n2329), .Y(n2331) );
NAND2X1TS U2814 ( .A(n2368), .B(n2394), .Y(n375) );
NOR2BX1TS U2815 ( .AN(exp_oper_result[8]), .B(n2394), .Y(S_Oper_A_exp[8]) );
XNOR2X1TS U2816 ( .A(DP_OP_36J22_124_9196_n1), .B(n2339), .Y(n2341) );
CLKMX2X2TS U2817 ( .A(Exp_module_Overflow_flag_A), .B(n2341), .S0(n2340),
.Y(n271) );
OAI22X1TS U2818 ( .A0(Exp_module_Data_S[8]), .A1(n2345), .B0(n2344), .B1(
n2400), .Y(n272) );
AO22X1TS U2819 ( .A0(n2374), .A1(Sgf_normalized_result[0]), .B0(
final_result_ieee[0]), .B1(n2378), .Y(n190) );
AO22X1TS U2820 ( .A0(n2374), .A1(Sgf_normalized_result[1]), .B0(
final_result_ieee[1]), .B1(n2378), .Y(n189) );
AO22X1TS U2821 ( .A0(n2374), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n2378), .Y(n188) );
NOR4X1TS U2822 ( .A(Op_MY[27]), .B(Op_MY[26]), .C(Op_MY[25]), .D(Op_MY[24]),
.Y(n2349) );
NOR4X1TS U2823 ( .A(n555), .B(Op_MY[18]), .C(n440), .D(n398), .Y(n2348) );
NOR4X1TS U2824 ( .A(n438), .B(n442), .C(Op_MY[14]), .D(Op_MY[19]), .Y(n2347)
);
NOR4X1TS U2825 ( .A(Op_MY[22]), .B(Op_MY[30]), .C(Op_MY[29]), .D(Op_MY[28]),
.Y(n2346) );
NOR4X1TS U2826 ( .A(Op_MX[27]), .B(Op_MX[26]), .C(Op_MX[25]), .D(Op_MX[23]),
.Y(n2357) );
NOR4X1TS U2827 ( .A(Op_MX[20]), .B(Op_MX[18]), .C(Op_MX[16]), .D(Op_MX[14]),
.Y(n2356) );
NOR4X1TS U2828 ( .A(Op_MX[21]), .B(Op_MX[30]), .C(Op_MX[29]), .D(Op_MX[28]),
.Y(n2354) );
NOR4X1TS U2829 ( .A(n397), .B(n401), .C(n434), .D(Op_MX[1]), .Y(n2362) );
NOR4X1TS U2830 ( .A(Op_MX[8]), .B(n2358), .C(n443), .D(n433), .Y(n2361) );
OA22X1TS U2831 ( .A0(n2366), .A1(n2365), .B0(n2364), .B1(n2363), .Y(n2367)
);
OAI2BB2XLTS U2832 ( .B0(n2368), .B1(n2367), .A0N(n2368), .A1N(zero_flag),
.Y(n311) );
OA22X1TS U2833 ( .A0(n2372), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n2371), .Y(n270) );
OA22X1TS U2834 ( .A0(n2372), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n2371), .Y(n269) );
OA22X1TS U2835 ( .A0(n2370), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n2371), .Y(n268) );
OA22X1TS U2836 ( .A0(n2370), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n2371), .Y(n267) );
OA22X1TS U2837 ( .A0(n2370), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n2371), .Y(n266) );
OA22X1TS U2838 ( .A0(n2370), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n2371), .Y(n265) );
OA22X1TS U2839 ( .A0(n2370), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n2371), .Y(n264) );
OA22X1TS U2840 ( .A0(n2372), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n2371), .Y(n263) );
AO22X1TS U2841 ( .A0(Sgf_normalized_result[3]), .A1(n2374), .B0(
final_result_ieee[3]), .B1(n2378), .Y(n187) );
INVX2TS U2842 ( .A(n2372), .Y(n2373) );
AO22X1TS U2843 ( .A0(Sgf_normalized_result[9]), .A1(n2374), .B0(
final_result_ieee[9]), .B1(n2376), .Y(n181) );
AO22X1TS U2844 ( .A0(Sgf_normalized_result[10]), .A1(n2377), .B0(
final_result_ieee[10]), .B1(n2376), .Y(n180) );
AO22X1TS U2845 ( .A0(Sgf_normalized_result[11]), .A1(n2377), .B0(
final_result_ieee[11]), .B1(n2376), .Y(n179) );
AO22X1TS U2846 ( .A0(Sgf_normalized_result[12]), .A1(n2377), .B0(
final_result_ieee[12]), .B1(n2376), .Y(n178) );
AO22X1TS U2847 ( .A0(Sgf_normalized_result[13]), .A1(n2377), .B0(
final_result_ieee[13]), .B1(n2376), .Y(n177) );
AO22X1TS U2848 ( .A0(Sgf_normalized_result[14]), .A1(n2377), .B0(
final_result_ieee[14]), .B1(n2376), .Y(n176) );
AO22X1TS U2849 ( .A0(Sgf_normalized_result[15]), .A1(n2377), .B0(
final_result_ieee[15]), .B1(n2376), .Y(n175) );
AO22X1TS U2850 ( .A0(Sgf_normalized_result[16]), .A1(n2377), .B0(
final_result_ieee[16]), .B1(n2376), .Y(n174) );
AO22X1TS U2851 ( .A0(Sgf_normalized_result[17]), .A1(n2377), .B0(
final_result_ieee[17]), .B1(n2376), .Y(n173) );
AO22X1TS U2852 ( .A0(Sgf_normalized_result[18]), .A1(n2377), .B0(
final_result_ieee[18]), .B1(n2378), .Y(n172) );
AO22X1TS U2853 ( .A0(Sgf_normalized_result[19]), .A1(n2377), .B0(
final_result_ieee[19]), .B1(n2378), .Y(n171) );
AO22X1TS U2854 ( .A0(Sgf_normalized_result[21]), .A1(n2379), .B0(
final_result_ieee[21]), .B1(n2378), .Y(n169) );
CMPR42X1TS U2855 ( .A(mult_x_55_n168), .B(mult_x_55_n280), .C(mult_x_55_n288), .D(mult_x_55_n300), .ICI(mult_x_55_n165), .S(mult_x_55_n164), .ICO(
mult_x_55_n162), .CO(mult_x_55_n163) );
CMPR42X1TS U2856 ( .A(mult_x_55_n169), .B(mult_x_55_n301), .C(mult_x_55_n289), .D(mult_x_55_n173), .ICI(mult_x_55_n170), .S(mult_x_55_n167), .ICO(
mult_x_55_n165), .CO(mult_x_55_n166) );
CMPR42X1TS U2857 ( .A(mult_x_55_n290), .B(mult_x_55_n314), .C(mult_x_55_n174), .D(mult_x_55_n178), .ICI(mult_x_55_n175), .S(mult_x_55_n172), .ICO(
mult_x_55_n170), .CO(mult_x_55_n171) );
CMPR42X1TS U2858 ( .A(n555), .B(n438), .C(mult_x_23_n280), .D(mult_x_23_n292), .ICI(mult_x_23_n163), .S(mult_x_23_n162), .ICO(mult_x_23_n160), .CO(
mult_x_23_n161) );
CMPR42X1TS U2859 ( .A(n592), .B(mult_x_23_n281), .C(mult_x_23_n293), .D(
mult_x_23_n171), .ICI(mult_x_23_n168), .S(mult_x_23_n165), .ICO(
mult_x_23_n163), .CO(mult_x_23_n164) );
CMPR42X1TS U2860 ( .A(mult_x_23_n294), .B(mult_x_23_n306), .C(mult_x_23_n172), .D(mult_x_23_n176), .ICI(mult_x_23_n173), .S(mult_x_23_n170), .ICO(
mult_x_23_n168), .CO(mult_x_23_n169) );
CMPR42X1TS U2861 ( .A(DP_OP_111J22_123_4462_n407), .B(
DP_OP_111J22_123_4462_n263), .C(DP_OP_111J22_123_4462_n384), .D(
DP_OP_111J22_123_4462_n394), .ICI(DP_OP_111J22_123_4462_n260), .S(
DP_OP_111J22_123_4462_n259), .ICO(DP_OP_111J22_123_4462_n257), .CO(
DP_OP_111J22_123_4462_n258) );
initial $sdf_annotate("FPU_Multiplication_Function_KOA_2STAGE_syn.sdf");
endmodule
|
/*
7-segment driver
.--0--.
5 1
|--6--|
4 2
`--3--' 7
*/
`define SSEG_0 7'b0111111
`define SSEG_1 7'b0000110
`define SSEG_2 7'b1011011
`define SSEG_3 7'b1001111
`define SSEG_4 7'b1100110
`define SSEG_5 7'b1101101
`define SSEG_6 7'b1111101
`define SSEG_7 7'b0000111
`define SSEG_8 7'b1111111
`define SSEG_9 7'b1101111
`define SSEG_A 7'b1110111
`define SSEG_B 7'b1111100
`define SSEG_C 7'b0111001
`define SSEG_D 7'b1011110
`define SSEG_E 7'b1111001
`define SSEG_F 7'b1110001
`define SSEG_NONE 7'b0000000
`define SSEG_MINUS 7'b1000000
`define SSEG_R 7'b1010000
`define SSEG_K 7'b1110100
`define SSEG_N 7'b1010100
`define SSEG_II 7'b0010100
`define SSEG_1_ 7'b0110000
`define SSEG_I `SSEG_1
`define SSEG_S `SSEG_5
`define SSEG_Z `SSEG_2
// -----------------------------------------------------------------------
module sevenseg_drv(
input clk,
input [6:0] digs [7:0],
input [7:0] dots,
output reg [7:0] dig,
output reg [7:0] seg
);
reg [0:18] counter;
always @ (posedge clk) begin
counter <= counter + 1'b1;
end
wire [2:0] addr = counter[0:2]; // 3 most significant bits as the digit address
always @ (addr, dots, digs) begin
dig <= ~(1'b1 << addr);
seg <= ~{dots[addr], digs[addr]};
end
endmodule
// -----------------------------------------------------------------------
module none2seg(
output reg [6:0] seg
);
assign seg = `SSEG_NONE;
endmodule
// -----------------------------------------------------------------------
module ra2seg(
input [10:0] r,
output reg [6:0] seg
);
always @ (r) begin
if (r[10]) seg <= `SSEG_R;
else if (r[6]) seg <= `SSEG_I;
else if (r[5]) seg <= `SSEG_A;
else if (r[4]) seg <= `SSEG_A;
else if (r[3]) seg <= `SSEG_I;
else if (r[2]) seg <= `SSEG_S;
else if (r[1]) seg <= `SSEG_I;
else if (r[0]) seg <= `SSEG_II;
else seg <= `SSEG_NONE;
end
endmodule
// -----------------------------------------------------------------------
module rb2seg(
input [10:0] r,
output reg [6:0] seg
);
always @ (r) begin
if (r[10]) begin
case (r[9:7])
3'd0 : seg <= `SSEG_0;
3'd1 : seg <= `SSEG_1_;
3'd2 : seg <= `SSEG_2;
3'd3 : seg <= `SSEG_3;
3'd4 : seg <= `SSEG_4;
3'd5 : seg <= `SSEG_5;
3'd6 : seg <= `SSEG_6;
3'd7 : seg <= `SSEG_7;
default : seg <= `SSEG_NONE;
endcase
end else begin
if (r[6]) seg <= `SSEG_C;
else if (r[5]) seg <= `SSEG_C;
else if (r[4]) seg <= `SSEG_R;
else if (r[3]) seg <= `SSEG_R;
else if (r[2]) seg <= `SSEG_R;
else if (r[1]) seg <= `SSEG_N;
else if (r[0]) seg <= `SSEG_II;
else seg <= `SSEG_NONE;
end
end
endmodule
// -----------------------------------------------------------------------
module hex2seg(
input [3:0] hex,
output reg [6:0] seg
);
always @ (hex) begin
case (hex)
4'h0 : seg <= `SSEG_0;
4'h1 : seg <= `SSEG_1;
4'h2 : seg <= `SSEG_2;
4'h3 : seg <= `SSEG_3;
4'h4 : seg <= `SSEG_4;
4'h5 : seg <= `SSEG_5;
4'h6 : seg <= `SSEG_6;
4'h7 : seg <= `SSEG_7;
4'h8 : seg <= `SSEG_8;
4'h9 : seg <= `SSEG_9;
4'ha : seg <= `SSEG_A;
4'hb : seg <= `SSEG_B;
4'hc : seg <= `SSEG_C;
4'hd : seg <= `SSEG_D;
4'he : seg <= `SSEG_E;
4'hf : seg <= `SSEG_F;
endcase
end
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
(** * Gen: Generalizing Induction Hypotheses *)
(* $Date: 2011-06-07 16:49:17 -0400 (Tue, 07 Jun 2011) $ *)
Require Export Poly.
(** In the previous chapter, we saw a proof that the [double] function
is injective. The way we _start_ this proof is a little bit
delicate: if we begin it with
[[
intros n. induction n.
]]
all is well. But if we begin it with
[[
intros n m. induction n.
]]
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'".
assert (n' = m') as H.
SSCase "Proof of assertion".
(* Here we are stuck. We need the assertion in order to
rewrite the final goal (subgoal 2 at this point) to an
identity. But the induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the assertion is not provable. *)
Admitted.
(** What went wrong here?
The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context
-- intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we can prove
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.)
To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective' : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for *every* [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O". inversion eq. (* The 0 case is trivial *)
SCase "m = S m'".
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
assert (n' = m') as H.
SSCase "Proof of assertion". apply IHn'.
inversion eq. reflexivity.
rewrite -> H. reflexivity. Qed.
(** So what we've learned is that we need to be careful about
using induction to try to prove something too specific: If
we're proving a property of [n] and [m] by induction on [n],
we may need to leave [m] generic.
However, this strategy doesn't always apply directly;
sometimes a little rearrangement is needed. Suppose, for
example, that we had decided we wanted to prove
[double_injective] by induction on [m] instead of [n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'".
assert (n' = m') as H.
SSCase "Proof of assertion".
(* Here we are stuck again, just like before. *)
Admitted.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) What can we do about this?
One possibility is to rewrite the statement of the lemma so
that [m] is quantified before [n]. This will work, but it's
not nice: We don't want to have to mangle the statements of
lemmas to fit the needs of a particular strategy for proving
them -- we want to state them in the most clear and natural
way.
What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'".
assert (n' = m') as H.
SSCase "Proof of assertion".
apply IHm'. inversion eq. reflexivity.
rewrite -> H. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that the
proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Carry out this proof by induction on [m]. *)
Theorem plus_n_n_injective_take2 : forall n m,
n + n = m + m ->
n = m.
Proof.
(* FILL IN HERE *) Admitted.
(** Now prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index (S n) l = None.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_opt) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/23/2016 11:26:28 AM
// Design Name:
// Module Name: Sgf_Multiplication
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Sgf_Multiplication
//#(parameter SW = 24)
#(parameter SW = 54)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
//wire [SW-1:0] Data_A_i;
//wire [SW-1:0] Data_B_i;
//wire [2*(SW/2)-1:0] result_left_mult;
//wire [2*(SW/2+1)-1:0] result_right_mult;
wire [SW/2+1:0] result_A_adder;
//wire [SW/2+1:0] Q_result_A_adder;
wire [SW/2+1:0] result_B_adder;
//wire [SW/2+1:0] Q_result_B_adder;
//wire [2*(SW/2+2)-1:0] result_middle_mult;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level1)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(SW)) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
multiplier #(.W(SW/2)/*,.level(level1)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
/*RegisterAdd #(.W(SW)) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult[2*(SW/2)-1:0]),
.Q(Q_right[2*(SW/2)-1:0])
);//*/
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+1)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder[SW/2:0]),
.Q(Q_result_A_adder[SW/2:0])
);//
RegisterAdd #(.W(SW/2+1)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder[SW/2:0]),
.Q(Q_result_B_adder[SW/2:0])
);//*/
//multiplication for middle
multiplier #(.W(SW/2+1)/*,.level(level1)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.Data_S_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
//segmentation registers array
/*RegisterAdd #(.W(SW+2)) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult[2*(SW/2)+1:0]),
.Q(Q_middle[2*(SW/2)+1:0])
);//*/
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level2)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(2*(SW/2))) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
multiplier #(.W((SW/2)+1)/*,.level(level2)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(/*result_right_mult*/Q_right)
);
/*RegisterAdd #(.W(2*((SW/2)+1))) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult),
.Q(Q_right)
);//*/
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+2)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder),
.Q(Q_result_A_adder)
);//
RegisterAdd #(.W(SW/2+2)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder),
.Q(Q_result_B_adder)
);//*/
//multiplication for middle
multiplier #(.W(SW/2+2)/*,.level(level2)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.Data_S_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
/*RegisterAdd #(.W(2*((SW/2)+2))) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult),
.Q(Q_middle)
);//*/
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_12_V
`define SKY130_FD_SC_HD__BUF_12_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 12 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__buf_12 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__buf_12 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_12_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__HA_PP_SYMBOL_V
`define SKY130_FD_SC_MS__HA_PP_SYMBOL_V
/**
* ha: Half adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__ha (
//# {{data|Data Signals}}
input A ,
input B ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__HA_PP_SYMBOL_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module routing_buffer(clock, resetn,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATA_WIDTH = 32;
parameter INSERT_REGISTER = 0;
input clock, resetn;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output reg o_datain_stall;
output reg [DATA_WIDTH-1:0] o_dataout;
input i_dataout_stall;
output reg o_dataout_valid;
generate
if (INSERT_REGISTER)
begin
always @ (negedge resetn or posedge clock)
begin
if (~resetn)
begin
o_datain_stall <= 1'b0;
o_dataout_valid <= 1'b0;
o_dataout <= 'x;
end
else
begin
o_datain_stall <= i_dataout_stall;
o_dataout_valid <= i_datain_valid;
o_dataout <= i_datain;
end
end
end
else
begin //non-registered version
always @ (*)
begin
o_datain_stall <= i_dataout_stall;
o_dataout_valid <= i_datain_valid;
o_dataout <= i_datain;
end
end
endgenerate
endmodule
|
// test_parse2synthtrans_behavopt_1_test.v
module f1_test(in, out, clk, reset);
input in, reset;
output reg out;
input clk;
reg signed [3:0] a;
reg signed [3:0] b;
reg signed [3:0] c;
reg [5:0] d;
reg [5:0] e;
always @(clk or reset) begin
a = -4;
b = 2;
c = a + b;
d = a + b + c;
d = d*d;
if(b)
e = d*d;
else
e = d + d;
end
endmodule
// test_parse2synthtrans_case_1_test.v
module f2_demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);
output out0, out1, out2, out3;
reg out0, out1, out2, out3;
input in;
input s1, s0;
reg [3:0] encoding;
reg [1:0] state;
always @(encoding) begin
case (encoding)
4'bxx11: state = 1;
4'bx0xx: state = 3;
4'b11xx: state = 4;
4'bx1xx: state = 2;
4'bxx1x: state = 1;
4'bxxx1: state = 0;
default: state = 0;
endcase
end
always @(encoding) begin
case (encoding)
4'b0000: state = 1;
default: state = 0;
endcase
end
endmodule
// test_parse2synthtrans_contassign_1_test.v
module f3_test(in, out);
input wire in;
output out;
assign out = (in+in);
assign out = 74;
endmodule
// test_parse2synthtrans_module_basic0_test.v
module f4_test;
endmodule
// test_parse2synthtrans_operators_1_test.v
module f5_test(in, out);
input in;
output out;
parameter p1 = 10;
parameter p2 = 5;
assign out = +p1;
assign out = -p2;
assign out = p1 + p2;
assign out = p1 - p2;
endmodule
// test_parse2synthtrans_param_1_test.v
module f6_test(in, out);
input in;
output out;
parameter p = 10;
assign out = p;
endmodule
// test_parse2synthtrans_port_scalar_1_test.v
module f7_test(in, out, io);
inout io;
output out;
input in;
endmodule
// test_parse2synthtrans_port_vector_1_test.v
module f8_test(in1, in2, out1, out2, io1, io2);
inout [1:0] io1;
inout [0:1] io2;
output [1:0] out1;
output [0:1] out2;
input [1:0] in1;
input [0:1] in2;
endmodule
// test_parse2synthtrans_v2k_comb_logic_sens_list_test.v
module f9_test(q, d, clk, reset);
output reg q;
input d, clk, reset;
always @ (posedge clk, negedge reset)
if(!reset) q <= 0;
else q <= d;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
reg _ranit;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [4:0] par1; // From a1 of t_param_first_a.v
wire [4:0] par2; // From a2 of t_param_first_a.v
wire [4:0] par3; // From a3 of t_param_first_a.v
wire [4:0] par4; // From a4 of t_param_first_a.v
wire [1:0] varwidth1; // From a1 of t_param_first_a.v
wire [2:0] varwidth2; // From a2 of t_param_first_a.v
wire [3:0] varwidth3; // From a3 of t_param_first_a.v
wire [3:0] varwidth4; // From a4 of t_param_first_a.v
// End of automatics
/*t_param_first_a AUTO_TEMPLATE (
.par (par@[]));
.varwidth (varwidth@[]));
*/
parameter XX = 2'bXX;
parameter THREE = 3;
t_param_first_a #(1,5) a1
(
// Outputs
.varwidth (varwidth1[1:0]),
/*AUTOINST*/
// Outputs
.par (par1[4:0])); // Templated
t_param_first_a #(2,5) a2
(
// Outputs
.varwidth (varwidth2[2:0]),
/*AUTOINST*/
// Outputs
.par (par2[4:0])); // Templated
t_param_first_a #(THREE,5) a3
(
// Outputs
.varwidth (varwidth3[3:0]),
/*AUTOINST*/
// Outputs
.par (par3[4:0])); // Templated
t_param_first_a #(THREE,5) a4
(
// Outputs
.varwidth (varwidth4[3:0]),
/*AUTOINST*/
// Outputs
.par (par4[4:0])); // Templated
parameter THREE_BITS_WIDE = 3'b011;
parameter THREE_2WIDE = 2'b11;
parameter ALSO_THREE_WIDE = THREE_BITS_WIDE;
parameter THREEPP_32_WIDE = 2*8*2+3;
parameter THREEPP_3_WIDE = 3'd4*3'd4*3'd2+3'd3; // Yes folks VCS says 3 bits wide
// Width propagation doesn't care about LHS vs RHS
// But the width of a RHS/LHS on a upper node does affect lower nodes;
// Thus must double-descend in width analysis.
// VCS 7.0.1 is broken on this test!
parameter T10 = (3'h7+3'h7)+4'h0; //initial if (T10!==4'd14) $stop;
parameter T11 = 4'h0+(3'h7+3'h7); //initial if (T11!==4'd14) $stop;
// Parameters assign LHS is affectively width zero.
parameter T12 = THREE_2WIDE + THREE_2WIDE; initial if (T12!==2'd2) $stop;
parameter T13 = THREE_2WIDE + 3; initial if (T13!==32'd6) $stop;
// Must be careful about LSB's with extracts
parameter [39:8] T14 = 32'h00_1234_56; initial if (T14[24:16]!==9'h34) $stop;
//
parameter THREEPP_32P_WIDE = 3'd4*3'd4*2+3'd3;
parameter THREE_32_WIDE = 3%32;
parameter THIRTYTWO = 2; // Param is 32 bits
parameter [40:0] WIDEPARAM = 41'h12_3456789a;
parameter [40:0] WIDEPARAM2 = WIDEPARAM;
reg [7:0] eightb;
reg [3:0] fourb;
wire [7:0] eight = 8'b00010000;
wire [1:0] eight2two = eight[THREE_32_WIDE+1:THREE_32_WIDE];
wire [2:0] threebits = ALSO_THREE_WIDE;
// surefire lint_off CWCCXX
initial _ranit = 0;
always @ (posedge clk) begin
if (!_ranit) begin
_ranit <= 1;
$write("[%0t] t_param: Running\n", $time);
//
$write(" %d %d %d\n", par1,par2,par3);
if (par1!==5'd1) $stop;
if (par2!==5'd2) $stop;
if (par3!==5'd3) $stop;
if (par4!==5'd3) $stop;
if (varwidth1!==2'd2) $stop;
if (varwidth2!==3'd2) $stop;
if (varwidth3!==4'd2) $stop;
if (varwidth4!==4'd2) $stop;
if (threebits !== 3'b011) $stop;
if (eight !== 8'b00010000) $stop;
if (eight2two !== 2'b10) $stop;
$write(" Params = %b %b\n %b %b\n",
THREEPP_32_WIDE,THREEPP_3_WIDE,
THIRTYTWO, THREEPP_32P_WIDE);
if (THREEPP_32_WIDE !== 32'h23) $stop;
if (THREEPP_3_WIDE !== 3'h3) $stop;
if (THREEPP_32P_WIDE !== 32'h23) $stop;
if (THIRTYTWO[1:0] !== 2'h2) $stop;
if (THIRTYTWO !== 32'h2) $stop;
if (THIRTYTWO !== 2) $stop;
if ((THIRTYTWO[1:0]+2'b00) !== 2'b10) $stop;
if ({1'b1,{THIRTYTWO[1:0]+2'b00}} !== 3'b110) $stop;
if (XX===0 || XX===1 || XX===2 || XX===3) $stop; // Paradoxical but right, since 1'bx!=0 && !=1
//
// Example of assignment LHS affecting expression widths.
// verilator lint_off WIDTH
// surefire lint_off ASWCMB
// surefire lint_off ASWCBB
eightb = (4'd8+4'd8)/4'd4; if (eightb!==8'd4) $stop;
fourb = (4'd8+4'd8)/4'd4; if (fourb!==4'd0) $stop;
fourb = (4'd8+8)/4'd4; if (fourb!==4'd4) $stop;
// verilator lint_on WIDTH
// surefire lint_on ASWCMB
// surefire lint_on ASWCBB
//
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
module top;
reg pass;
reg [7:0] a, b;
wire [15:0] ruu, rsu, rus, rss;
reg signed [15:0] res;
integer i;
assign ruu = a % b;
assign rsu = $signed(a) % b;
assign rus = a % $signed(b);
assign rss = $signed(a) % $signed(b);
initial begin
pass = 1'b1;
// Run 1000 random vectors
for (i = 0; i < 1000; i = i + 1) begin
// Random vectors
a = $random;
b = $random;
#1;
// Check unsigned % unsigned.
if (ruu !== a%b) begin
$display("FAILED: u%%u (%b%%%b) gave %b, expected %b", a, b, ruu, a%b);
pass = 1'b0;
end
// Check signed % unsigned division.
if (rsu !== a%b) begin
$display("FAILED: s%%u (%b%%%b) gave %b, expected %b", a, b, rsu, a%b);
pass = 1'b0;
end
// Check unsigned % signed division.
if (rus !== a%b) begin
$display("FAILED: u%%s (%b%%%b) gave %b, expected %b", a, b, rus, a%b);
pass = 1'b0;
end
// Check signed % signed division.
res = $signed(a)%$signed(b);
if (rss !== res) begin
$display("FAILED: s%%s (%b%%%b) gave %b, expected %b", a, b, rss, res);
pass = 1'b0;
end
end
if (pass) $display("PASSED");
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_rx_recv # (
parameter C_PCIE_DATA_WIDTH = 128
)
(
input pcie_user_clk,
input pcie_user_rst_n,
//pcie rx signal
input [C_PCIE_DATA_WIDTH-1:0] s_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_rx_tkeep,
input s_axis_rx_tlast,
input s_axis_rx_tvalid,
output s_axis_rx_tready,
input [21:0] s_axis_rx_tuser,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
output mreq_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output [7:0] cpld_fifo_tag,
output [C_PCIE_DATA_WIDTH-1:0] cpld_fifo_wr_data,
output cpld_fifo_wr_en,
output cpld_fifo_tag_last
);
localparam S_RX_IDLE_SOF = 4'b0001;
localparam S_RX_DATA = 4'b0010;
localparam S_RX_STRADDLED = 4'b0100;
localparam S_RX_STRADDLED_HOLD = 4'b1000;
reg [3:0] cur_state;
reg [3:0] next_state;
wire [4:0] w_rx_is_sof;
wire [4:0] w_rx_is_eof;
reg [31:0] r_pcie_head0;
reg [31:0] r_pcie_head1;
reg [31:0] r_pcie_head2;
wire [2:0] w_mreq_head_fmt;
wire [4:0] w_mreq_head_type;
//wire [2:0] w_mreq_head_tc;
//wire w_mreq_head_attr1;
//wire w_mreq_head_th;
//wire w_mreq_head_td;
wire w_mreq_head_ep;
//wire [1:0] w_mreq_head_atqtr0;
//wire [1:0] w_mreq_head_at;
//wire [9:0] w_mreq_head_len;
//wire [7:0] w_mreq_head_re_bus_num;
//wire [4:0] w_mreq_head_req_dev_num;
//wire [2:0] w_mreq_head_req_func_num;
//wire [15:0] w_mreq_head_req_id;
//wire [7:0] w_mreq_head_tag;
wire [2:0] w_cpld_head_fmt;
wire [4:0] w_cpld_head_type;
//wire [2:0] w_cpld_head_tc;
//wire w_cpld_head_attr1;
//wire w_cpld_head_th;
//wire w_cpld_head_td;
wire w_cpld_head_ep;
//wire [1:0] w_cpld_head_attr0;
//wire [1:0] w_cpld_head_at;
wire [9:0] w_cpld_head_len;
//wire [7:0] w_cpld_head_cpl_bus_num;
//wire [4:0] w_cpld_head_cpl_dev_num;
//wire [2:0] w_cpld_head_cpl_func_num;
//wire [15:0] w_cpld_head_cpl_id;
wire [2:0] w_cpld_head_cs;
//wire w_cpld_head_bcm;
wire [11:0] w_cpld_head_bc;
//wire [7:0] w_cpld_head_req_bus_num;
//wire [4:0] w_cpld_head_req_dev_num;
//wire [2:0] w_cpld_head_req_func_num;
//wire [15:0] w_cpld_head_req_id;
wire [7:0] w_cpld_head_tag;
//wire [6:0] w_cpld_head_la;
wire w_pcie_mreq_type;
wire w_pcie_cpld_type;
reg r_pcie_mreq_type;
reg r_pcie_cpld_type;
reg r_pcie_mreq_err;
reg r_pcie_cpld_err;
reg r_pcie_cpld_len_err;
reg [7:0] r_cpld_tag;
reg [11:2] r_cpld_len;
reg [11:2] r_cpld_bc;
reg r_cpld_lhead;
reg r_mem_req_en;
reg r_cpld_data_en;
reg r_cpld_tag_last;
reg r_rx_straddled;
reg r_rx_straddled_hold;
reg r_rx_data_straddled;
reg [127:0] r_s_axis_rx_tdata;
reg [127:0] r_s_axis_rx_tdata_d1;
reg r_mreq_fifo_wr_en;
reg [127:0] r_mreq_fifo_wr_data;
reg r_cpld_fifo_tag_en;
reg r_cpld_fifo_wr_en;
reg [127:0] r_cpld_fifo_wr_data;
reg r_cpld_fifo_tag_last;
assign s_axis_rx_tready = ~r_rx_straddled_hold;
assign pcie_mreq_err = r_pcie_mreq_err;
assign pcie_cpld_err = r_pcie_cpld_err;
assign pcie_cpld_len_err = r_pcie_cpld_len_err;
assign mreq_fifo_wr_en = r_mreq_fifo_wr_en;
assign mreq_fifo_wr_data = r_mreq_fifo_wr_data;
assign cpld_fifo_tag = r_cpld_tag;
assign cpld_fifo_wr_en = r_cpld_fifo_wr_en;
assign cpld_fifo_wr_data[31:0] = {r_cpld_fifo_wr_data[7:0], r_cpld_fifo_wr_data[15:8], r_cpld_fifo_wr_data[23:16], r_cpld_fifo_wr_data[31:24]};
assign cpld_fifo_wr_data[63:32] = {r_cpld_fifo_wr_data[39:32], r_cpld_fifo_wr_data[47:40], r_cpld_fifo_wr_data[55:48], r_cpld_fifo_wr_data[63:56]};
assign cpld_fifo_wr_data[95:64] = {r_cpld_fifo_wr_data[71:64], r_cpld_fifo_wr_data[79:72], r_cpld_fifo_wr_data[87:80], r_cpld_fifo_wr_data[95:88]};
assign cpld_fifo_wr_data[127:96] = {r_cpld_fifo_wr_data[103:96], r_cpld_fifo_wr_data[111:104], r_cpld_fifo_wr_data[119:112], r_cpld_fifo_wr_data[127:120]};
assign cpld_fifo_tag_last = r_cpld_fifo_tag_last;
assign w_rx_is_sof = s_axis_rx_tuser[14:10];
assign w_rx_is_eof = s_axis_rx_tuser[21:17];
always @ (*)
begin
if(w_rx_is_sof[3] == 1) begin
r_pcie_head0 <= s_axis_rx_tdata[95:64];
r_pcie_head1 <= s_axis_rx_tdata[127:96];
end
else begin
r_pcie_head0 <= s_axis_rx_tdata[31:0];
r_pcie_head1 <= s_axis_rx_tdata[63:32];
end
if(r_rx_straddled == 1)
r_pcie_head2 <= s_axis_rx_tdata[31:0];
else
r_pcie_head2 <= s_axis_rx_tdata[95:64];
end
//pcie mrd or mwr, memory rd/wr request
assign w_mreq_head_fmt = r_pcie_head0[31:29];
assign w_mreq_head_type = r_pcie_head0[28:24];
//assign w_mreq_head_tc = r_pcie_head0[22:20];
//assign w_mreq_head_attr1 = r_pcie_head0[18];
//assign w_mreq_head_th = r_pcie_head0[16];
//assign w_mreq_head_td = r_pcie_head0[15];
assign w_mreq_head_ep = r_pcie_head0[14];
//assign w_mreq_head_attr0 = r_pcie_head0[13:12];
//assign w_mreq_head_at = r_pcie_head0[11:10];
//assign w_mreq_head_len = r_pcie_head0[9:0];
//assign w_mreq_head_req_bus_num = r_pcie_head1[31:24];
//assign w_mreq_head_req_dev_num = r_pcie_head1[23:19];
//assign w_mreq_head_req_func_num = r_pcie_head1[18:16];
//assign w_mreq_head_req_id = {w_mreq_head_req_bus_num, w_mreq_head_req_dev_num, w_mreq_head_req_func_num};
//assign w_mreq_head_tag = r_pcie_head1[15:8];
//pcie cpl or cpld
assign w_cpld_head_fmt = r_pcie_head0[31:29];
assign w_cpld_head_type = r_pcie_head0[28:24];
//assign w_cpld_head_tc = r_pcie_head0[22:20];
//assign w_cpld_head_attr1 = r_pcie_head0[18];
//assign w_cpld_head_th = r_pcie_head0[16];
//assign w_cpld_head_td = r_pcie_head0[15];
assign w_cpld_head_ep = r_pcie_head0[14];
//assign w_cpld_head_attr0 = r_pcie_head0[13:12];
//assign w_cpld_head_at = r_pcie_head0[11:10];
assign w_cpld_head_len = r_pcie_head0[9:0];
//assign w_cpld_head_cpl_bus_num = r_pcie_head1[31:24];
//assign w_cpld_head_cpl_dev_num = r_pcie_head1[23:19];
//assign w_cpld_head_cpl_func_num = r_pcie_head1[18:16];
//assign w_cpld_head_cpl_id = {w_cpld_head_cpl_bus_num, w_cpld_head_cpl_dev_num, w_cpld_head_cpl_func_num};
assign w_cpld_head_cs = r_pcie_head1[15:13];
//assign w_cpld_head_bcm = r_pcie_head1[12];
assign w_cpld_head_bc = r_pcie_head1[11:0];
//assign w_cpld_head_req_bus_num = r_pcie_head2[31:24];
//assign w_cpld_head_req_dev_num = r_pcie_head2[23:19];
//assign w_cpld_head_req_func_num = r_pcie_head2[18:16];
//assign w_cpld_head_req_id = {w_cpld_head_req_bus_num, w_cpld_head_req_dev_num, w_cpld_head_req_func_num};
assign w_cpld_head_tag = r_pcie_head2[15:8];
//assign w_cpld_head_la = r_pcie_head2[6:0];
assign w_pcie_mreq_type = ({w_mreq_head_fmt[2], w_mreq_head_type} == {1'b0, 5'b00000});
assign w_pcie_cpld_type = ({w_cpld_head_fmt, w_cpld_head_type} == {3'b010, 5'b01010});
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_RX_IDLE_SOF;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_RX_IDLE_SOF: begin
if(s_axis_rx_tvalid == 1 && w_rx_is_sof[4] == 1 && w_rx_is_eof[4] == 0 ) begin
if(w_rx_is_sof[3] == 1)
next_state <= S_RX_STRADDLED;
else
next_state <= S_RX_DATA;
end
else
next_state <= S_RX_IDLE_SOF;
end
S_RX_DATA: begin
if(s_axis_rx_tvalid == 1 && w_rx_is_eof[4] == 1) begin
if(w_rx_is_sof[4] == 1)
next_state <= S_RX_STRADDLED;
else
next_state <= S_RX_IDLE_SOF;
end
else
next_state <= S_RX_DATA;
end
S_RX_STRADDLED: begin
if(s_axis_rx_tvalid == 1 && w_rx_is_eof[4] == 1) begin
if(w_rx_is_sof[4] == 1)
next_state <= S_RX_STRADDLED;
else if(w_rx_is_eof[3] == 1)
next_state <= S_RX_STRADDLED_HOLD;
else
next_state <= S_RX_IDLE_SOF;
end
else
next_state <= S_RX_STRADDLED;
end
S_RX_STRADDLED_HOLD: begin
next_state <= S_RX_IDLE_SOF;
end
default: begin
next_state <= S_RX_IDLE_SOF;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
if(s_axis_rx_tvalid == 1 && w_rx_is_sof[4] == 1) begin
r_pcie_mreq_type <= w_pcie_mreq_type & ~w_mreq_head_ep;
r_pcie_cpld_type <= w_pcie_cpld_type & ~w_cpld_head_ep & (w_cpld_head_cs == 0);
r_cpld_len <= w_cpld_head_len;
r_cpld_bc[11:2] <= w_cpld_head_bc[11:2];
end
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_pcie_mreq_err <= 0;
r_pcie_cpld_err <= 0;
r_pcie_cpld_len_err <= 0;
end
else begin
if(r_pcie_cpld_type == 1 && r_cpld_len < 2) begin
r_pcie_cpld_len_err <= 1;
end
if(s_axis_rx_tvalid == 1 && w_rx_is_sof[4] == 1) begin
r_pcie_mreq_err <= w_pcie_mreq_type & w_mreq_head_ep;
r_pcie_cpld_err <= w_pcie_cpld_type & (w_cpld_head_ep | (w_cpld_head_cs != 0));
end
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_RX_IDLE_SOF: begin
r_cpld_tag <= w_cpld_head_tag;
r_cpld_lhead <= 0;
end
S_RX_DATA: begin
end
S_RX_STRADDLED: begin
if(s_axis_rx_tvalid == 1)
r_cpld_lhead <= ~w_rx_is_sof[4];
if(r_cpld_lhead == 0)
r_cpld_tag <= w_cpld_head_tag;
end
S_RX_STRADDLED_HOLD: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_RX_IDLE_SOF: begin
r_mem_req_en <= (s_axis_rx_tvalid & w_rx_is_sof[4] & ~w_rx_is_sof[3]) & w_pcie_mreq_type;
r_cpld_data_en <= 0;
r_cpld_tag_last <= 0;
r_rx_straddled <= 0;
r_rx_straddled_hold <= 0;
end
S_RX_DATA: begin
r_mem_req_en <= s_axis_rx_tvalid & r_pcie_mreq_type;
r_cpld_data_en <= s_axis_rx_tvalid & r_pcie_cpld_type;
r_cpld_tag_last <= (r_cpld_len == r_cpld_bc[11:2]) & (s_axis_rx_tvalid & r_pcie_cpld_type & w_rx_is_eof[4]);
r_rx_straddled <= 0;
r_rx_straddled_hold <= 0;
end
S_RX_STRADDLED: begin
r_mem_req_en <= s_axis_rx_tvalid & r_pcie_mreq_type;
r_cpld_data_en <= s_axis_rx_tvalid & r_pcie_cpld_type & r_cpld_lhead;
r_cpld_tag_last <= (r_cpld_len == r_cpld_bc[11:2]) & (s_axis_rx_tvalid & r_pcie_cpld_type & w_rx_is_eof[4] & ~w_rx_is_eof[3]);
r_rx_straddled <= 1;
r_rx_straddled_hold <= 0;
end
S_RX_STRADDLED_HOLD: begin
r_mem_req_en <= r_pcie_mreq_type;
r_cpld_data_en <= r_pcie_cpld_type;
r_cpld_tag_last <= (r_cpld_len == r_cpld_bc[11:2]) & r_pcie_cpld_type;
r_rx_straddled <= 1;
r_rx_straddled_hold <= 1;
end
default: begin
r_mem_req_en <= 0;
r_cpld_data_en <= 0;
r_cpld_tag_last <= 0;
r_rx_straddled <= 0;
r_rx_straddled_hold <= 0;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
r_mreq_fifo_wr_en <= r_mem_req_en;
r_cpld_fifo_wr_en <= r_cpld_data_en;
r_cpld_fifo_tag_last <= r_cpld_tag_last;
r_rx_data_straddled <= r_rx_straddled;
if(s_axis_rx_tvalid == 1 || r_rx_straddled_hold == 1) begin
r_s_axis_rx_tdata <= s_axis_rx_tdata;
r_s_axis_rx_tdata_d1 <= r_s_axis_rx_tdata;
end
end
always @ (*)
begin
if(r_rx_data_straddled == 1)
r_mreq_fifo_wr_data <= {r_s_axis_rx_tdata[63:0], r_s_axis_rx_tdata_d1[127:64]};
else
r_mreq_fifo_wr_data <= r_s_axis_rx_tdata;
if(r_rx_data_straddled == 1)
r_cpld_fifo_wr_data <= {r_s_axis_rx_tdata[31:0], r_s_axis_rx_tdata_d1[127:32]};
else
r_cpld_fifo_wr_data <= {r_s_axis_rx_tdata[95:0], r_s_axis_rx_tdata_d1[127:96]};
end
endmodule |
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 9
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_auto_pc_4 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [11 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [11 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [11 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [11 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_9_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(0),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 15:03:00 10/24/2016
// Module Name: ADDER_tb
// Project Name: MIPS
// Description: Testing the ADDER module in the MIPS EXECUTE stage.
//
// Dependencies: ADDER.v
//
////////////////////////////////////////////////////////////////////////////////
module ADDER_tb;
// Inputs.
reg [31:0] add_in1;
reg [31:0] add_in2;
// Outputs.
wire [31:0] add_out;
// Instantiate the module.
ADDER adder(.add_in1(add_in1), .add_in2(add_in2), .add_out(add_out));
initial begin
// Initialize inputs.
add_in1 = 0;
add_in2 = 0;
// Wait 100 ns for global reset to finish.
#100;
$monitor("add_in1 = %h add_in2 = %h add_out = %h", add_in1, add_in2, add_out);
add_in1 = 32'h00110000;
add_in2 = 32'h001100BB;
#10;
add_in1 = 32'h0011FF00;
add_in2 = 32'h001100C0;
#10;
add_in1 = 32'h00110010;
add_in2 = 32'h00110CCC;
end
endmodule
|
module snake (input [0:0] CLOCK_27, input [1:0] KEY, input [0:0] SW,
output reg [3:0] VGA_R, VGA_G, VGA_B, output reg VGA_HS, VGA_VS, output [6:0] HEX0, HEX1, HEX2, HEX3
/*, output [9:0] LEDR, output [7:0] LEDG*/);
parameter FRONT_PORCH_A = 16;
parameter SYNC_PULSE_B = 96;
parameter BACK_PORCH_C = 48;
parameter ACTIVE_VIDEO_D= 640;
parameter CYCLES_LINE = FRONT_PORCH_A + SYNC_PULSE_B + BACK_PORCH_C + ACTIVE_VIDEO_D;
parameter V_FRONT_PORCH_A = 10;
parameter V_SYNC_PULSE_B = 2;
parameter V_BACK_PORCH_C = 33;
parameter V_ACTIVE_VIDEO_D = 480;
parameter CYCLES_ROW = V_FRONT_PORCH_A + V_SYNC_PULSE_B + V_BACK_PORCH_C + V_ACTIVE_VIDEO_D;
parameter COLS = 8'd80;
parameter ROWS = 8'd60;
parameter BODYMAX = 50;
integer i;
wire VGA_CLK;
clock_25_2 u0( .clk_out_clk(VGA_CLK), .clk_res_reset(0), .clk_in_clk(CLOCK_27[0]) );
reg [31:0] tickCounter;
reg [31:0] ticks;
reg clkFrame;
reg [15:0] HS_count;
reg [15:0] VS_count;
wire [15:0] rndBig;
LFSR16 lfsr1(VGA_CLK, rndBig);
wire [7:0] rndHi;
wire [7:0] rndLo;
assign {rndHi, rndLo} = rndBig[15:0];
reg [7:0] xFood;
reg [7:0] yFood;
reg isFoodPlaced;
reg isDead;
reg [7:0] score;
led7 h3((score / 1000) % 10, HEX3); led7 h2((score / 100) % 10, HEX2); led7 h1((score / 10) % 10, HEX1); led7 h0(score % 10, HEX0);
//led7 h3(xFood/10, HEX3); led7 h2(xFood%10, HEX2); led7 h1(yFood/10, HEX1); led7 h0(yFood%10, HEX0);
reg [7:0] bodyX [BODYMAX-1:0];
reg [7:0] bodyY [BODYMAX-1:0];
reg [6:0] bodyLength;
reg [7:0] x;
reg [7:0] y;
reg [1:0] direction;
//assign LEDG[1:0]=direction;
//led7 h3(x/10, HEX3); led7 h2(x%10, HEX2); led7 h1(y/10, HEX1); led7 h0(y%10, HEX0);
//*Timer*************************************************************************
always @(posedge VGA_CLK) begin
tickCounter <= tickCounter + 1;
if( tickCounter==(32'd25_200_000 / (60+bodyLength)) )
begin
tickCounter <=0;
clkFrame <= ~clkFrame;
if(ticks==29)
ticks<=0;
else
ticks <= ticks + 1;
end
end
//*Logika************************************************************************
always @(posedge clkFrame) begin
if(SW[0]==0) begin
x <= (COLS/2'd2);
y <= (ROWS/2'd2);
isFoodPlaced = 0;
score = 0;
bodyLength = 1'b1;
isDead <= 0;
end
if(SW[0] && !isDead) begin
if(!isFoodPlaced) begin
xFood <= rndHi;
yFood <= rndLo;
isFoodPlaced = 1;
end
if(xFood>79) xFood <= rndHi;
if(yFood>59) yFood <= rndLo;
// eat food
if(x==xFood && y==yFood) begin
score = score + 1'b1;
if(bodyLength<BODYMAX-1)
bodyLength = bodyLength + 1'b1;
isFoodPlaced = 0;
bodyX[bodyLength-1] = x;
bodyY[bodyLength-1] = y;
end
// is food inside body?
i=0;
while(i<bodyLength-2 && i<BODYMAX-1)
begin
if( bodyX[i] == xFood && bodyY[i] == yFood) begin
xFood <= rndHi;
yFood <= rndLo;
end
i = i + 1;
end
// head move
case(direction)
0 : if(x==COLS-1) x <= 0;
else x <= x + 1'b1;
1 : if(y==ROWS-1) y <= 0;
else y <= y + 1'b1;
2 : if(x==0) x <= COLS - 1'b1;
else x <= x - 1'b1;
3 : if(y==0) y <= ROWS - 1'b1;
else y <= y - 1'b1;
default : ;
endcase
// crash test
i=0;
while(i<bodyLength-1 && i<BODYMAX-1)
begin
if( bodyX[i] == x && bodyY[i] == y)
isDead <= 1;
i = i + 1;
end
// body move
i=0;
while(i<bodyLength-1 && i<BODYMAX-1)
begin
bodyX[i] = bodyX[i+1];
bodyY[i] = bodyY[i+1];
i = i + 1;
end
bodyX[bodyLength-1] = x;
bodyY[bodyLength-1] = y;
end //if(SW[0] && !isDead)
end
//*Przyciski*********************************************************************
reg [1:0] det_edge;
wire sig_edge;
assign sig_edge = (det_edge == 2'b10);
reg [1:0] det_edge1;
wire sig_edge1;
assign sig_edge1 = (det_edge1 == 2'b10);
always @(posedge VGA_CLK) begin
det_edge <= {det_edge[0], KEY[0]};
det_edge1 <= {det_edge1[0], KEY[1]};
if(sig_edge) begin
if(direction==3) direction<=0;
else direction<= direction + 1'b1;
end
else if(sig_edge1) begin
if(direction>3) direction<=3;
else direction<= direction - 1'b1;
end
else if(!SW[0])
direction <= 0;
end
//*Wyświetlanie*****************************************************************
always @(posedge VGA_CLK)
if(HS_count<640 && VS_count<480) begin
if(SW[0]) begin
VGA_R <= 4'b1000;
VGA_G <= 4'b1010;
VGA_B <= 4'b0110;
/*
if(HS_count==x && VS_count==y) begin
VGA_R <= 4'b0000;
VGA_G <= 4'b0000;
VGA_B <= 4'b1111;
end
*/
i=0;
while(i<BODYMAX && i<bodyLength) begin
if(bodyX[i]==HS_count/8 && bodyY[i]==VS_count/8) begin
VGA_R <= 4'b0000;
VGA_G <= 4'b0000;
VGA_B <= 4'b0000;
end
i=i+1;
end
if(xFood==HS_count/8 && yFood==VS_count/8) begin
if(ticks<22) begin
VGA_R <= 4'b0000;
VGA_G <= 4'b0000;
VGA_B <= 4'b0000;
end
end
end else begin
VGA_R <= (VS_count-ticks+5);
VGA_G <= (VS_count-ticks+10);
VGA_B <= (VS_count-ticks);
end
end else begin
VGA_R <= 4'b0000;
VGA_G <= 4'b0000;
VGA_B <= 4'b0000;
end
//*Sync************************************************************************************
always @(posedge VGA_CLK) // HSYNC
begin
if(HS_count < CYCLES_LINE)
HS_count <= HS_count + 1'b1;
else
HS_count <= 0;
if(HS_count > ACTIVE_VIDEO_D + FRONT_PORCH_A && HS_count < CYCLES_LINE - BACK_PORCH_C)
VGA_HS <= 0;
else
VGA_HS <= 1;
end
always @(posedge VGA_CLK) // VSYNC
if(HS_count==CYCLES_LINE-1)
begin
if(VS_count < CYCLES_ROW)
VS_count <= VS_count + 1'b1;
else
VS_count <= 0;
if(VS_count > V_ACTIVE_VIDEO_D+V_FRONT_PORCH_A && VS_count < CYCLES_ROW - V_BACK_PORCH_C)
VGA_VS <= 0;
else
VGA_VS <= 1;
end
endmodule
//*Random***********************************************************************
module LFSR16(
input clk,
output reg [15:0] LFSR
);
always @(posedge clk)
begin
LFSR[0] <= ~(LFSR[1] ^ LFSR[2] ^ LFSR[4] ^ LFSR[15]);
LFSR[15:1] <= LFSR[14:0];
end
endmodule
//*LCD**************************************************************************
module led7(input [3:0] mod0, output reg [6:0] led);
always begin
case(mod0) //654_3210
0 : led = 7'b100_0000;
1 : led = 7'b111_1001;
2 : led = 7'b010_0100;
3 : led = 7'b011_0000;
4 : led = 7'b001_1001;
5 : led = 7'b001_0010;
6 : led = 7'b000_0010;
7 : led = 7'b111_1000;
8 : led = 7'b000_0000;
9 : led = 7'b001_0000;
default : led = 7'b111_1111;
endcase
end
endmodule
|
`define ADDER_WIDTH 022
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
module memory(
gm_or_lds,
rd_en,
wr_en,
addresses,
wr_data,
input_tag,
// wr_mask,
rd_data,
output_tag,
ack,
clk,
rst
);
input clk;
input rst;
input gm_or_lds;
input rd_en, wr_en;
input [31:0] addresses;
input [31:0] wr_data;
input [6:0] input_tag;
output [6:0] output_tag;
output ack;
output [31:0] rd_data;
reg[7:0] data_memory[50000:0];
reg[7:0] lds_memory[65535:0];
reg ack_reg;
reg [6:0] tag_reg;
//integer locrd = 4; // num of loc to read
assign ack = ack_reg;
assign output_tag = tag_reg;
integer i;
always@(posedge clk, posedge rst) begin
// if(rst) begin
// for(i = 0; i < 50001; i = i+1) begin
// data_memory[i] <= 0;
// end
// for(i = 0; i < 65536; i = i+1) begin
// lds_memory[i] <= 0;
// end
// end
// else
if(wr_en) begin
if(gm_or_lds) begin
lds_memory [addresses] <= wr_data[7:0];
lds_memory [addresses+1] <= wr_data[15:7];
lds_memory [addresses+2] <= wr_data[23:16];
lds_memory [addresses+3] <= wr_data[31:24];
end
else begin
data_memory [addresses] <= wr_data[7:0];
data_memory [addresses+1] <= wr_data[15:7];
data_memory [addresses+2] <= wr_data[23:16];
data_memory [addresses+3] <= wr_data[31:24];
end
end
end
always@(posedge clk) begin
if(rst) begin
ack_reg <= 1'b0;
tag_reg <= 7'd0;
end
else begin
ack_reg <= 1'b0;
tag_reg <= 7'd0;
if(rd_en | wr_en) begin
ack_reg <= 1'b1;
tag_reg <= input_tag;
end
end
end
wire [31:0] rd_lds;
wire [31:0] rd_dm;
assign rd_lds = {lds_memory[addresses+3],lds_memory[addresses+2],lds_memory[addresses+1],lds_memory[addresses]};
assign rd_dm = {data_memory[addresses+3],data_memory[addresses+2],data_memory[addresses+1],data_memory[addresses]};
assign rd_data = (gm_or_lds) ? rd_lds:rd_dm;
endmodule
|
/*
*******************************************************************************
*
* FIFO Generator - Verilog Behavioral Model
*
*******************************************************************************
*
* (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
*
* This file contains confidential and proprietary information
* of Xilinx, Inc. and is protected under U.S. and
* international copyright and other intellectual property
* laws.
*
* DISCLAIMER
* This disclaimer is not a license and does not grant any
* rights to the materials distributed herewith. Except as
* otherwise provided in a valid license issued to you by
* Xilinx, and to the maximum extent permitted by applicable
* law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
* WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
* AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
* BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
* INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
* (2) Xilinx shall not be liable (whether in contract or tort,
* including negligence, or under any other theory of
* liability) for any loss or damage of any kind or nature
* related to, arising under or in connection with these
* materials, including for any direct, or any indirect,
* special, incidental, or consequential loss or damage
* (including loss of data, profits, goodwill, or any type of
* loss or damage suffered as a result of any action brought
* by a third party) even if such damage or loss was
* reasonably foreseeable or Xilinx had been advised of the
* possibility of the same.
*
* CRITICAL APPLICATIONS
* Xilinx products are not designed or intended to be fail-
* safe, or for use in any application requiring fail-safe
* performance, such as life-support or safety devices or
* systems, Class III medical devices, nuclear facilities,
* applications related to the deployment of airbags, or any
* other applications that could lead to death, personal
* injury, or severe property or environmental damage
* (individually and collectively, "Critical
* Applications"). Customer assumes the sole risk and
* liability of any use of Xilinx products in Critical
* Applications, subject only to applicable laws and
* regulations governing limitations on product liability.
*
* THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
* PART OF THIS FILE AT ALL TIMES.
*
*******************************************************************************
*******************************************************************************
*
* Filename: fifo_generator_vlog_beh.v
*
* Author : Xilinx
*
*******************************************************************************
* Structure:
*
* fifo_generator_vlog_beh.v
* |
* +-fifo_generator_v13_1_0_bhv_ver_as
* |
* +-fifo_generator_v13_1_0_bhv_ver_ss
* |
* +-fifo_generator_v13_1_0_bhv_ver_preload0
*
*******************************************************************************
* Description:
*
* The Verilog behavioral model for the FIFO Generator.
*
* The behavioral model has three parts:
* - The behavioral model for independent clocks FIFOs (_as)
* - The behavioral model for common clock FIFOs (_ss)
* - The "preload logic" block which implements First-word Fall-through
*
*******************************************************************************
* Description:
* The verilog behavioral model for the FIFO generator core.
*
*******************************************************************************
*/
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_vlog_beh
#(
//-----------------------------------------------------------------------
// Generic Declarations
//-----------------------------------------------------------------------
parameter C_COMMON_CLOCK = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "",
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 1,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "4kx4",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_PIPELINE_REG = 0,
parameter C_POWER_SAVING_MODE = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface, 1: AXI4 Stream, 2: AXI4/AXI3
parameter C_AXI_TYPE = 0, // 1: AXI4, 2: AXI4 Lite, 3: AXI3
parameter C_HAS_AXI_WR_CHANNEL = 0,
parameter C_HAS_AXI_RD_CHANNEL = 0,
parameter C_HAS_SLAVE_CE = 0,
parameter C_HAS_MASTER_CE = 0,
parameter C_ADD_NGC_CONSTRAINT = 0,
parameter C_USE_COMMON_UNDERFLOW = 0,
parameter C_USE_COMMON_OVERFLOW = 0,
parameter C_USE_DEFAULT_SETTINGS = 0,
// AXI Full/Lite
parameter C_AXI_ID_WIDTH = 0,
parameter C_AXI_ADDR_WIDTH = 0,
parameter C_AXI_DATA_WIDTH = 0,
parameter C_AXI_LEN_WIDTH = 8,
parameter C_AXI_LOCK_WIDTH = 2,
parameter C_HAS_AXI_ID = 0,
parameter C_HAS_AXI_AWUSER = 0,
parameter C_HAS_AXI_WUSER = 0,
parameter C_HAS_AXI_BUSER = 0,
parameter C_HAS_AXI_ARUSER = 0,
parameter C_HAS_AXI_RUSER = 0,
parameter C_AXI_ARUSER_WIDTH = 0,
parameter C_AXI_AWUSER_WIDTH = 0,
parameter C_AXI_WUSER_WIDTH = 0,
parameter C_AXI_BUSER_WIDTH = 0,
parameter C_AXI_RUSER_WIDTH = 0,
// AXI Streaming
parameter C_HAS_AXIS_TDATA = 0,
parameter C_HAS_AXIS_TID = 0,
parameter C_HAS_AXIS_TDEST = 0,
parameter C_HAS_AXIS_TUSER = 0,
parameter C_HAS_AXIS_TREADY = 0,
parameter C_HAS_AXIS_TLAST = 0,
parameter C_HAS_AXIS_TSTRB = 0,
parameter C_HAS_AXIS_TKEEP = 0,
parameter C_AXIS_TDATA_WIDTH = 1,
parameter C_AXIS_TID_WIDTH = 1,
parameter C_AXIS_TDEST_WIDTH = 1,
parameter C_AXIS_TUSER_WIDTH = 1,
parameter C_AXIS_TSTRB_WIDTH = 1,
parameter C_AXIS_TKEEP_WIDTH = 1,
// AXI Channel Type
// WACH --> Write Address Channel
// WDCH --> Write Data Channel
// WRCH --> Write Response Channel
// RACH --> Read Address Channel
// RDCH --> Read Data Channel
// AXIS --> AXI Streaming
parameter C_WACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logic
parameter C_WDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_WRCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RACH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_RDCH_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
parameter C_AXIS_TYPE = 0, // 0 = FIFO, 1 = Register Slice, 2 = Pass Through Logie
// AXI Implementation Type
// 1 = Common Clock Block RAM FIFO
// 2 = Common Clock Distributed RAM FIFO
// 11 = Independent Clock Block RAM FIFO
// 12 = Independent Clock Distributed RAM FIFO
parameter C_IMPLEMENTATION_TYPE_WACH = 0,
parameter C_IMPLEMENTATION_TYPE_WDCH = 0,
parameter C_IMPLEMENTATION_TYPE_WRCH = 0,
parameter C_IMPLEMENTATION_TYPE_RACH = 0,
parameter C_IMPLEMENTATION_TYPE_RDCH = 0,
parameter C_IMPLEMENTATION_TYPE_AXIS = 0,
// AXI FIFO Type
// 0 = Data FIFO
// 1 = Packet FIFO
// 2 = Low Latency Sync FIFO
// 3 = Low Latency Async FIFO
parameter C_APPLICATION_TYPE_WACH = 0,
parameter C_APPLICATION_TYPE_WDCH = 0,
parameter C_APPLICATION_TYPE_WRCH = 0,
parameter C_APPLICATION_TYPE_RACH = 0,
parameter C_APPLICATION_TYPE_RDCH = 0,
parameter C_APPLICATION_TYPE_AXIS = 0,
// AXI Built-in FIFO Primitive Type
// 512x36, 1kx18, 2kx9, 4kx4, etc
parameter C_PRIM_FIFO_TYPE_WACH = "512x36",
parameter C_PRIM_FIFO_TYPE_WDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_WRCH = "512x36",
parameter C_PRIM_FIFO_TYPE_RACH = "512x36",
parameter C_PRIM_FIFO_TYPE_RDCH = "512x36",
parameter C_PRIM_FIFO_TYPE_AXIS = "512x36",
// Enable ECC
// 0 = ECC disabled
// 1 = ECC enabled
parameter C_USE_ECC_WACH = 0,
parameter C_USE_ECC_WDCH = 0,
parameter C_USE_ECC_WRCH = 0,
parameter C_USE_ECC_RACH = 0,
parameter C_USE_ECC_RDCH = 0,
parameter C_USE_ECC_AXIS = 0,
// ECC Error Injection Type
// 0 = No Error Injection
// 1 = Single Bit Error Injection
// 2 = Double Bit Error Injection
// 3 = Single Bit and Double Bit Error Injection
parameter C_ERROR_INJECTION_TYPE_WACH = 0,
parameter C_ERROR_INJECTION_TYPE_WDCH = 0,
parameter C_ERROR_INJECTION_TYPE_WRCH = 0,
parameter C_ERROR_INJECTION_TYPE_RACH = 0,
parameter C_ERROR_INJECTION_TYPE_RDCH = 0,
parameter C_ERROR_INJECTION_TYPE_AXIS = 0,
// Input Data Width
// Accumulation of all AXI input signal's width
parameter C_DIN_WIDTH_WACH = 1,
parameter C_DIN_WIDTH_WDCH = 1,
parameter C_DIN_WIDTH_WRCH = 1,
parameter C_DIN_WIDTH_RACH = 1,
parameter C_DIN_WIDTH_RDCH = 1,
parameter C_DIN_WIDTH_AXIS = 1,
parameter C_WR_DEPTH_WACH = 16,
parameter C_WR_DEPTH_WDCH = 16,
parameter C_WR_DEPTH_WRCH = 16,
parameter C_WR_DEPTH_RACH = 16,
parameter C_WR_DEPTH_RDCH = 16,
parameter C_WR_DEPTH_AXIS = 16,
parameter C_WR_PNTR_WIDTH_WACH = 4,
parameter C_WR_PNTR_WIDTH_WDCH = 4,
parameter C_WR_PNTR_WIDTH_WRCH = 4,
parameter C_WR_PNTR_WIDTH_RACH = 4,
parameter C_WR_PNTR_WIDTH_RDCH = 4,
parameter C_WR_PNTR_WIDTH_AXIS = 4,
parameter C_HAS_DATA_COUNTS_WACH = 0,
parameter C_HAS_DATA_COUNTS_WDCH = 0,
parameter C_HAS_DATA_COUNTS_WRCH = 0,
parameter C_HAS_DATA_COUNTS_RACH = 0,
parameter C_HAS_DATA_COUNTS_RDCH = 0,
parameter C_HAS_DATA_COUNTS_AXIS = 0,
parameter C_HAS_PROG_FLAGS_WACH = 0,
parameter C_HAS_PROG_FLAGS_WDCH = 0,
parameter C_HAS_PROG_FLAGS_WRCH = 0,
parameter C_HAS_PROG_FLAGS_RACH = 0,
parameter C_HAS_PROG_FLAGS_RDCH = 0,
parameter C_HAS_PROG_FLAGS_AXIS = 0,
parameter C_PROG_FULL_TYPE_WACH = 0,
parameter C_PROG_FULL_TYPE_WDCH = 0,
parameter C_PROG_FULL_TYPE_WRCH = 0,
parameter C_PROG_FULL_TYPE_RACH = 0,
parameter C_PROG_FULL_TYPE_RDCH = 0,
parameter C_PROG_FULL_TYPE_AXIS = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_PROG_EMPTY_TYPE_WACH = 0,
parameter C_PROG_EMPTY_TYPE_WDCH = 0,
parameter C_PROG_EMPTY_TYPE_WRCH = 0,
parameter C_PROG_EMPTY_TYPE_RACH = 0,
parameter C_PROG_EMPTY_TYPE_RDCH = 0,
parameter C_PROG_EMPTY_TYPE_AXIS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = 0,
parameter C_REG_SLICE_MODE_WACH = 0,
parameter C_REG_SLICE_MODE_WDCH = 0,
parameter C_REG_SLICE_MODE_WRCH = 0,
parameter C_REG_SLICE_MODE_RACH = 0,
parameter C_REG_SLICE_MODE_RDCH = 0,
parameter C_REG_SLICE_MODE_AXIS = 0
)
(
//------------------------------------------------------------------------------
// Input and Output Declarations
//------------------------------------------------------------------------------
// Conventional FIFO Interface Signals
input backup,
input backup_marker,
input clk,
input rst,
input srst,
input wr_clk,
input wr_rst,
input rd_clk,
input rd_rst,
input [C_DIN_WIDTH-1:0] din,
input wr_en,
input rd_en,
// Optional inputs
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert,
input [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert,
input [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate,
input int_clk,
input injectdbiterr,
input injectsbiterr,
input sleep,
output [C_DOUT_WIDTH-1:0] dout,
output full,
output almost_full,
output wr_ack,
output overflow,
output empty,
output almost_empty,
output valid,
output underflow,
output [C_DATA_COUNT_WIDTH-1:0] data_count,
output [C_RD_DATA_COUNT_WIDTH-1:0] rd_data_count,
output [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count,
output prog_full,
output prog_empty,
output sbiterr,
output dbiterr,
output wr_rst_busy,
output rd_rst_busy,
// AXI Global Signal
input m_aclk,
input s_aclk,
input s_aresetn,
input s_aclk_en,
input m_aclk_en,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_awlen,
input [3-1:0] s_axi_awsize,
input [2-1:0] s_axi_awburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_awlock,
input [4-1:0] s_axi_awcache,
input [3-1:0] s_axi_awprot,
input [4-1:0] s_axi_awqos,
input [4-1:0] s_axi_awregion,
input [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input s_axi_awvalid,
output s_axi_awready,
input [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [2-1:0] s_axi_bresp,
output [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output s_axi_bvalid,
input s_axi_bready,
// AXI Full/Lite Master Write Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_awlen,
output [3-1:0] m_axi_awsize,
output [2-1:0] m_axi_awburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_awlock,
output [4-1:0] m_axi_awcache,
output [3-1:0] m_axi_awprot,
output [4-1:0] m_axi_awqos,
output [4-1:0] m_axi_awregion,
output [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output m_axi_awvalid,
input m_axi_awready,
output [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output m_axi_wlast,
output [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output m_axi_wvalid,
input m_axi_wready,
input [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input [2-1:0] m_axi_bresp,
input [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input m_axi_bvalid,
output m_axi_bready,
// AXI Full/Lite Slave Read Channel (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [C_AXI_LEN_WIDTH-1:0] s_axi_arlen,
input [3-1:0] s_axi_arsize,
input [2-1:0] s_axi_arburst,
input [C_AXI_LOCK_WIDTH-1:0] s_axi_arlock,
input [4-1:0] s_axi_arcache,
input [3-1:0] s_axi_arprot,
input [4-1:0] s_axi_arqos,
input [4-1:0] s_axi_arregion,
input [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [2-1:0] s_axi_rresp,
output s_axi_rlast,
output [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output s_axi_rvalid,
input s_axi_rready,
// AXI Full/Lite Master Read Channel (read side)
output [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output [C_AXI_LEN_WIDTH-1:0] m_axi_arlen,
output [3-1:0] m_axi_arsize,
output [2-1:0] m_axi_arburst,
output [C_AXI_LOCK_WIDTH-1:0] m_axi_arlock,
output [4-1:0] m_axi_arcache,
output [3-1:0] m_axi_arprot,
output [4-1:0] m_axi_arqos,
output [4-1:0] m_axi_arregion,
output [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output m_axi_arvalid,
input m_axi_arready,
input [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input [2-1:0] m_axi_rresp,
input m_axi_rlast,
input [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input m_axi_rvalid,
output m_axi_rready,
// AXI Streaming Slave Signals (Write side)
input s_axis_tvalid,
output s_axis_tready,
input [C_AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input [C_AXIS_TSTRB_WIDTH-1:0] s_axis_tstrb,
input [C_AXIS_TKEEP_WIDTH-1:0] s_axis_tkeep,
input s_axis_tlast,
input [C_AXIS_TID_WIDTH-1:0] s_axis_tid,
input [C_AXIS_TDEST_WIDTH-1:0] s_axis_tdest,
input [C_AXIS_TUSER_WIDTH-1:0] s_axis_tuser,
// AXI Streaming Master Signals (Read side)
output m_axis_tvalid,
input m_axis_tready,
output [C_AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output [C_AXIS_TSTRB_WIDTH-1:0] m_axis_tstrb,
output [C_AXIS_TKEEP_WIDTH-1:0] m_axis_tkeep,
output m_axis_tlast,
output [C_AXIS_TID_WIDTH-1:0] m_axis_tid,
output [C_AXIS_TDEST_WIDTH-1:0] m_axis_tdest,
output [C_AXIS_TUSER_WIDTH-1:0] m_axis_tuser,
// AXI Full/Lite Write Address Channel signals
input axi_aw_injectsbiterr,
input axi_aw_injectdbiterr,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WACH-1:0] axi_aw_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_wr_data_count,
output [C_WR_PNTR_WIDTH_WACH:0] axi_aw_rd_data_count,
output axi_aw_sbiterr,
output axi_aw_dbiterr,
output axi_aw_overflow,
output axi_aw_underflow,
output axi_aw_prog_full,
output axi_aw_prog_empty,
// AXI Full/Lite Write Data Channel signals
input axi_w_injectsbiterr,
input axi_w_injectdbiterr,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WDCH-1:0] axi_w_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_wr_data_count,
output [C_WR_PNTR_WIDTH_WDCH:0] axi_w_rd_data_count,
output axi_w_sbiterr,
output axi_w_dbiterr,
output axi_w_overflow,
output axi_w_underflow,
output axi_w_prog_full,
output axi_w_prog_empty,
// AXI Full/Lite Write Response Channel signals
input axi_b_injectsbiterr,
input axi_b_injectdbiterr,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_full_thresh,
input [C_WR_PNTR_WIDTH_WRCH-1:0] axi_b_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_wr_data_count,
output [C_WR_PNTR_WIDTH_WRCH:0] axi_b_rd_data_count,
output axi_b_sbiterr,
output axi_b_dbiterr,
output axi_b_overflow,
output axi_b_underflow,
output axi_b_prog_full,
output axi_b_prog_empty,
// AXI Full/Lite Read Address Channel signals
input axi_ar_injectsbiterr,
input axi_ar_injectdbiterr,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RACH-1:0] axi_ar_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_wr_data_count,
output [C_WR_PNTR_WIDTH_RACH:0] axi_ar_rd_data_count,
output axi_ar_sbiterr,
output axi_ar_dbiterr,
output axi_ar_overflow,
output axi_ar_underflow,
output axi_ar_prog_full,
output axi_ar_prog_empty,
// AXI Full/Lite Read Data Channel Signals
input axi_r_injectsbiterr,
input axi_r_injectdbiterr,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_full_thresh,
input [C_WR_PNTR_WIDTH_RDCH-1:0] axi_r_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_wr_data_count,
output [C_WR_PNTR_WIDTH_RDCH:0] axi_r_rd_data_count,
output axi_r_sbiterr,
output axi_r_dbiterr,
output axi_r_overflow,
output axi_r_underflow,
output axi_r_prog_full,
output axi_r_prog_empty,
// AXI Streaming FIFO Related Signals
input axis_injectsbiterr,
input axis_injectdbiterr,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_full_thresh,
input [C_WR_PNTR_WIDTH_AXIS-1:0] axis_prog_empty_thresh,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_wr_data_count,
output [C_WR_PNTR_WIDTH_AXIS:0] axis_rd_data_count,
output axis_sbiterr,
output axis_dbiterr,
output axis_overflow,
output axis_underflow,
output axis_prog_full,
output axis_prog_empty
);
wire BACKUP;
wire BACKUP_MARKER;
wire CLK;
wire RST;
wire SRST;
wire WR_CLK;
wire WR_RST;
wire RD_CLK;
wire RD_RST;
wire [C_DIN_WIDTH-1:0] DIN;
wire WR_EN;
wire RD_EN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire INT_CLK;
wire INJECTDBITERR;
wire INJECTSBITERR;
wire SLEEP;
wire [C_DOUT_WIDTH-1:0] DOUT;
wire FULL;
wire ALMOST_FULL;
wire WR_ACK;
wire OVERFLOW;
wire EMPTY;
wire ALMOST_EMPTY;
wire VALID;
wire UNDERFLOW;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT;
wire PROG_FULL;
wire PROG_EMPTY;
wire SBITERR;
wire DBITERR;
wire WR_RST_BUSY;
wire RD_RST_BUSY;
wire M_ACLK;
wire S_ACLK;
wire S_ARESETN;
wire S_ACLK_EN;
wire M_ACLK_EN;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_AWLEN;
wire [3-1:0] S_AXI_AWSIZE;
wire [2-1:0] S_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_AWLOCK;
wire [4-1:0] S_AXI_AWCACHE;
wire [3-1:0] S_AXI_AWPROT;
wire [4-1:0] S_AXI_AWQOS;
wire [4-1:0] S_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER;
wire S_AXI_AWVALID;
wire S_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB;
wire S_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER;
wire S_AXI_WVALID;
wire S_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [2-1:0] S_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER;
wire S_AXI_BVALID;
wire S_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_AWLEN;
wire [3-1:0] M_AXI_AWSIZE;
wire [2-1:0] M_AXI_AWBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_AWLOCK;
wire [4-1:0] M_AXI_AWCACHE;
wire [3-1:0] M_AXI_AWPROT;
wire [4-1:0] M_AXI_AWQOS;
wire [4-1:0] M_AXI_AWREGION;
wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER;
wire M_AXI_AWVALID;
wire M_AXI_AWREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB;
wire M_AXI_WLAST;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER;
wire M_AXI_WVALID;
wire M_AXI_WREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID;
wire [2-1:0] M_AXI_BRESP;
wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER;
wire M_AXI_BVALID;
wire M_AXI_BREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] S_AXI_ARLEN;
wire [3-1:0] S_AXI_ARSIZE;
wire [2-1:0] S_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] S_AXI_ARLOCK;
wire [4-1:0] S_AXI_ARCACHE;
wire [3-1:0] S_AXI_ARPROT;
wire [4-1:0] S_AXI_ARQOS;
wire [4-1:0] S_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER;
wire S_AXI_ARVALID;
wire S_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA;
wire [2-1:0] S_AXI_RRESP;
wire S_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER;
wire S_AXI_RVALID;
wire S_AXI_RREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR;
wire [C_AXI_LEN_WIDTH-1:0] M_AXI_ARLEN;
wire [3-1:0] M_AXI_ARSIZE;
wire [2-1:0] M_AXI_ARBURST;
wire [C_AXI_LOCK_WIDTH-1:0] M_AXI_ARLOCK;
wire [4-1:0] M_AXI_ARCACHE;
wire [3-1:0] M_AXI_ARPROT;
wire [4-1:0] M_AXI_ARQOS;
wire [4-1:0] M_AXI_ARREGION;
wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER;
wire M_AXI_ARVALID;
wire M_AXI_ARREADY;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA;
wire [2-1:0] M_AXI_RRESP;
wire M_AXI_RLAST;
wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER;
wire M_AXI_RVALID;
wire M_AXI_RREADY;
wire S_AXIS_TVALID;
wire S_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] S_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] S_AXIS_TKEEP;
wire S_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER;
wire M_AXIS_TVALID;
wire M_AXIS_TREADY;
wire [C_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA;
wire [C_AXIS_TSTRB_WIDTH-1:0] M_AXIS_TSTRB;
wire [C_AXIS_TKEEP_WIDTH-1:0] M_AXIS_TKEEP;
wire M_AXIS_TLAST;
wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID;
wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST;
wire [C_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER;
wire AXI_AW_INJECTSBITERR;
wire AXI_AW_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WACH-1:0] AXI_AW_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WACH:0] AXI_AW_RD_DATA_COUNT;
wire AXI_AW_SBITERR;
wire AXI_AW_DBITERR;
wire AXI_AW_OVERFLOW;
wire AXI_AW_UNDERFLOW;
wire AXI_AW_PROG_FULL;
wire AXI_AW_PROG_EMPTY;
wire AXI_W_INJECTSBITERR;
wire AXI_W_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH-1:0] AXI_W_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WDCH:0] AXI_W_RD_DATA_COUNT;
wire AXI_W_SBITERR;
wire AXI_W_DBITERR;
wire AXI_W_OVERFLOW;
wire AXI_W_UNDERFLOW;
wire AXI_W_PROG_FULL;
wire AXI_W_PROG_EMPTY;
wire AXI_B_INJECTSBITERR;
wire AXI_B_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH-1:0] AXI_B_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_WRCH:0] AXI_B_RD_DATA_COUNT;
wire AXI_B_SBITERR;
wire AXI_B_DBITERR;
wire AXI_B_OVERFLOW;
wire AXI_B_UNDERFLOW;
wire AXI_B_PROG_FULL;
wire AXI_B_PROG_EMPTY;
wire AXI_AR_INJECTSBITERR;
wire AXI_AR_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RACH-1:0] AXI_AR_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RACH:0] AXI_AR_RD_DATA_COUNT;
wire AXI_AR_SBITERR;
wire AXI_AR_DBITERR;
wire AXI_AR_OVERFLOW;
wire AXI_AR_UNDERFLOW;
wire AXI_AR_PROG_FULL;
wire AXI_AR_PROG_EMPTY;
wire AXI_R_INJECTSBITERR;
wire AXI_R_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH-1:0] AXI_R_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_RDCH:0] AXI_R_RD_DATA_COUNT;
wire AXI_R_SBITERR;
wire AXI_R_DBITERR;
wire AXI_R_OVERFLOW;
wire AXI_R_UNDERFLOW;
wire AXI_R_PROG_FULL;
wire AXI_R_PROG_EMPTY;
wire AXIS_INJECTSBITERR;
wire AXIS_INJECTDBITERR;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS-1:0] AXIS_PROG_EMPTY_THRESH;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_WR_DATA_COUNT;
wire [C_WR_PNTR_WIDTH_AXIS:0] AXIS_RD_DATA_COUNT;
wire AXIS_SBITERR;
wire AXIS_DBITERR;
wire AXIS_OVERFLOW;
wire AXIS_UNDERFLOW;
wire AXIS_PROG_FULL;
wire AXIS_PROG_EMPTY;
wire [C_WR_DATA_COUNT_WIDTH-1:0] wr_data_count_in;
wire wr_rst_int;
wire rd_rst_int;
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// Conventional FIFO Interface Signals
assign BACKUP = backup;
assign BACKUP_MARKER = backup_marker;
assign CLK = clk;
assign RST = rst;
assign SRST = srst;
assign WR_CLK = wr_clk;
assign WR_RST = wr_rst;
assign RD_CLK = rd_clk;
assign RD_RST = rd_rst;
assign WR_EN = wr_en;
assign RD_EN = rd_en;
assign INT_CLK = int_clk;
assign INJECTDBITERR = injectdbiterr;
assign INJECTSBITERR = injectsbiterr;
assign SLEEP = sleep;
assign full = FULL;
assign almost_full = ALMOST_FULL;
assign wr_ack = WR_ACK;
assign overflow = OVERFLOW;
assign empty = EMPTY;
assign almost_empty = ALMOST_EMPTY;
assign valid = VALID;
assign underflow = UNDERFLOW;
assign prog_full = PROG_FULL;
assign prog_empty = PROG_EMPTY;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign wr_rst_busy = WR_RST_BUSY;
assign rd_rst_busy = RD_RST_BUSY;
assign M_ACLK = m_aclk;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_ACLK_EN = s_aclk_en;
assign M_ACLK_EN = m_aclk_en;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign m_axi_awvalid = M_AXI_AWVALID;
assign M_AXI_AWREADY = m_axi_awready;
assign m_axi_wlast = M_AXI_WLAST;
assign m_axi_wvalid = M_AXI_WVALID;
assign M_AXI_WREADY = m_axi_wready;
assign M_AXI_BVALID = m_axi_bvalid;
assign m_axi_bready = M_AXI_BREADY;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign m_axi_arvalid = M_AXI_ARVALID;
assign M_AXI_ARREADY = m_axi_arready;
assign M_AXI_RLAST = m_axi_rlast;
assign M_AXI_RVALID = m_axi_rvalid;
assign m_axi_rready = M_AXI_RREADY;
assign S_AXIS_TVALID = s_axis_tvalid;
assign s_axis_tready = S_AXIS_TREADY;
assign S_AXIS_TLAST = s_axis_tlast;
assign m_axis_tvalid = M_AXIS_TVALID;
assign M_AXIS_TREADY = m_axis_tready;
assign m_axis_tlast = M_AXIS_TLAST;
assign AXI_AW_INJECTSBITERR = axi_aw_injectsbiterr;
assign AXI_AW_INJECTDBITERR = axi_aw_injectdbiterr;
assign axi_aw_sbiterr = AXI_AW_SBITERR;
assign axi_aw_dbiterr = AXI_AW_DBITERR;
assign axi_aw_overflow = AXI_AW_OVERFLOW;
assign axi_aw_underflow = AXI_AW_UNDERFLOW;
assign axi_aw_prog_full = AXI_AW_PROG_FULL;
assign axi_aw_prog_empty = AXI_AW_PROG_EMPTY;
assign AXI_W_INJECTSBITERR = axi_w_injectsbiterr;
assign AXI_W_INJECTDBITERR = axi_w_injectdbiterr;
assign axi_w_sbiterr = AXI_W_SBITERR;
assign axi_w_dbiterr = AXI_W_DBITERR;
assign axi_w_overflow = AXI_W_OVERFLOW;
assign axi_w_underflow = AXI_W_UNDERFLOW;
assign axi_w_prog_full = AXI_W_PROG_FULL;
assign axi_w_prog_empty = AXI_W_PROG_EMPTY;
assign AXI_B_INJECTSBITERR = axi_b_injectsbiterr;
assign AXI_B_INJECTDBITERR = axi_b_injectdbiterr;
assign axi_b_sbiterr = AXI_B_SBITERR;
assign axi_b_dbiterr = AXI_B_DBITERR;
assign axi_b_overflow = AXI_B_OVERFLOW;
assign axi_b_underflow = AXI_B_UNDERFLOW;
assign axi_b_prog_full = AXI_B_PROG_FULL;
assign axi_b_prog_empty = AXI_B_PROG_EMPTY;
assign AXI_AR_INJECTSBITERR = axi_ar_injectsbiterr;
assign AXI_AR_INJECTDBITERR = axi_ar_injectdbiterr;
assign axi_ar_sbiterr = AXI_AR_SBITERR;
assign axi_ar_dbiterr = AXI_AR_DBITERR;
assign axi_ar_overflow = AXI_AR_OVERFLOW;
assign axi_ar_underflow = AXI_AR_UNDERFLOW;
assign axi_ar_prog_full = AXI_AR_PROG_FULL;
assign axi_ar_prog_empty = AXI_AR_PROG_EMPTY;
assign AXI_R_INJECTSBITERR = axi_r_injectsbiterr;
assign AXI_R_INJECTDBITERR = axi_r_injectdbiterr;
assign axi_r_sbiterr = AXI_R_SBITERR;
assign axi_r_dbiterr = AXI_R_DBITERR;
assign axi_r_overflow = AXI_R_OVERFLOW;
assign axi_r_underflow = AXI_R_UNDERFLOW;
assign axi_r_prog_full = AXI_R_PROG_FULL;
assign axi_r_prog_empty = AXI_R_PROG_EMPTY;
assign AXIS_INJECTSBITERR = axis_injectsbiterr;
assign AXIS_INJECTDBITERR = axis_injectdbiterr;
assign axis_sbiterr = AXIS_SBITERR;
assign axis_dbiterr = AXIS_DBITERR;
assign axis_overflow = AXIS_OVERFLOW;
assign axis_underflow = AXIS_UNDERFLOW;
assign axis_prog_full = AXIS_PROG_FULL;
assign axis_prog_empty = AXIS_PROG_EMPTY;
assign DIN = din;
assign PROG_EMPTY_THRESH = prog_empty_thresh;
assign PROG_EMPTY_THRESH_ASSERT = prog_empty_thresh_assert;
assign PROG_EMPTY_THRESH_NEGATE = prog_empty_thresh_negate;
assign PROG_FULL_THRESH = prog_full_thresh;
assign PROG_FULL_THRESH_ASSERT = prog_full_thresh_assert;
assign PROG_FULL_THRESH_NEGATE = prog_full_thresh_negate;
assign dout = DOUT;
assign data_count = DATA_COUNT;
assign rd_data_count = RD_DATA_COUNT;
assign wr_data_count = WR_DATA_COUNT;
assign S_AXI_AWID = s_axi_awid;
assign S_AXI_AWADDR = s_axi_awaddr;
assign S_AXI_AWLEN = s_axi_awlen;
assign S_AXI_AWSIZE = s_axi_awsize;
assign S_AXI_AWBURST = s_axi_awburst;
assign S_AXI_AWLOCK = s_axi_awlock;
assign S_AXI_AWCACHE = s_axi_awcache;
assign S_AXI_AWPROT = s_axi_awprot;
assign S_AXI_AWQOS = s_axi_awqos;
assign S_AXI_AWREGION = s_axi_awregion;
assign S_AXI_AWUSER = s_axi_awuser;
assign S_AXI_WID = s_axi_wid;
assign S_AXI_WDATA = s_axi_wdata;
assign S_AXI_WSTRB = s_axi_wstrb;
assign S_AXI_WUSER = s_axi_wuser;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_buser = S_AXI_BUSER;
assign m_axi_awid = M_AXI_AWID;
assign m_axi_awaddr = M_AXI_AWADDR;
assign m_axi_awlen = M_AXI_AWLEN;
assign m_axi_awsize = M_AXI_AWSIZE;
assign m_axi_awburst = M_AXI_AWBURST;
assign m_axi_awlock = M_AXI_AWLOCK;
assign m_axi_awcache = M_AXI_AWCACHE;
assign m_axi_awprot = M_AXI_AWPROT;
assign m_axi_awqos = M_AXI_AWQOS;
assign m_axi_awregion = M_AXI_AWREGION;
assign m_axi_awuser = M_AXI_AWUSER;
assign m_axi_wid = M_AXI_WID;
assign m_axi_wdata = M_AXI_WDATA;
assign m_axi_wstrb = M_AXI_WSTRB;
assign m_axi_wuser = M_AXI_WUSER;
assign M_AXI_BID = m_axi_bid;
assign M_AXI_BRESP = m_axi_bresp;
assign M_AXI_BUSER = m_axi_buser;
assign S_AXI_ARID = s_axi_arid;
assign S_AXI_ARADDR = s_axi_araddr;
assign S_AXI_ARLEN = s_axi_arlen;
assign S_AXI_ARSIZE = s_axi_arsize;
assign S_AXI_ARBURST = s_axi_arburst;
assign S_AXI_ARLOCK = s_axi_arlock;
assign S_AXI_ARCACHE = s_axi_arcache;
assign S_AXI_ARPROT = s_axi_arprot;
assign S_AXI_ARQOS = s_axi_arqos;
assign S_AXI_ARREGION = s_axi_arregion;
assign S_AXI_ARUSER = s_axi_aruser;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_ruser = S_AXI_RUSER;
assign m_axi_arid = M_AXI_ARID;
assign m_axi_araddr = M_AXI_ARADDR;
assign m_axi_arlen = M_AXI_ARLEN;
assign m_axi_arsize = M_AXI_ARSIZE;
assign m_axi_arburst = M_AXI_ARBURST;
assign m_axi_arlock = M_AXI_ARLOCK;
assign m_axi_arcache = M_AXI_ARCACHE;
assign m_axi_arprot = M_AXI_ARPROT;
assign m_axi_arqos = M_AXI_ARQOS;
assign m_axi_arregion = M_AXI_ARREGION;
assign m_axi_aruser = M_AXI_ARUSER;
assign M_AXI_RID = m_axi_rid;
assign M_AXI_RDATA = m_axi_rdata;
assign M_AXI_RRESP = m_axi_rresp;
assign M_AXI_RUSER = m_axi_ruser;
assign S_AXIS_TDATA = s_axis_tdata;
assign S_AXIS_TSTRB = s_axis_tstrb;
assign S_AXIS_TKEEP = s_axis_tkeep;
assign S_AXIS_TID = s_axis_tid;
assign S_AXIS_TDEST = s_axis_tdest;
assign S_AXIS_TUSER = s_axis_tuser;
assign m_axis_tdata = M_AXIS_TDATA;
assign m_axis_tstrb = M_AXIS_TSTRB;
assign m_axis_tkeep = M_AXIS_TKEEP;
assign m_axis_tid = M_AXIS_TID;
assign m_axis_tdest = M_AXIS_TDEST;
assign m_axis_tuser = M_AXIS_TUSER;
assign AXI_AW_PROG_FULL_THRESH = axi_aw_prog_full_thresh;
assign AXI_AW_PROG_EMPTY_THRESH = axi_aw_prog_empty_thresh;
assign axi_aw_data_count = AXI_AW_DATA_COUNT;
assign axi_aw_wr_data_count = AXI_AW_WR_DATA_COUNT;
assign axi_aw_rd_data_count = AXI_AW_RD_DATA_COUNT;
assign AXI_W_PROG_FULL_THRESH = axi_w_prog_full_thresh;
assign AXI_W_PROG_EMPTY_THRESH = axi_w_prog_empty_thresh;
assign axi_w_data_count = AXI_W_DATA_COUNT;
assign axi_w_wr_data_count = AXI_W_WR_DATA_COUNT;
assign axi_w_rd_data_count = AXI_W_RD_DATA_COUNT;
assign AXI_B_PROG_FULL_THRESH = axi_b_prog_full_thresh;
assign AXI_B_PROG_EMPTY_THRESH = axi_b_prog_empty_thresh;
assign axi_b_data_count = AXI_B_DATA_COUNT;
assign axi_b_wr_data_count = AXI_B_WR_DATA_COUNT;
assign axi_b_rd_data_count = AXI_B_RD_DATA_COUNT;
assign AXI_AR_PROG_FULL_THRESH = axi_ar_prog_full_thresh;
assign AXI_AR_PROG_EMPTY_THRESH = axi_ar_prog_empty_thresh;
assign axi_ar_data_count = AXI_AR_DATA_COUNT;
assign axi_ar_wr_data_count = AXI_AR_WR_DATA_COUNT;
assign axi_ar_rd_data_count = AXI_AR_RD_DATA_COUNT;
assign AXI_R_PROG_FULL_THRESH = axi_r_prog_full_thresh;
assign AXI_R_PROG_EMPTY_THRESH = axi_r_prog_empty_thresh;
assign axi_r_data_count = AXI_R_DATA_COUNT;
assign axi_r_wr_data_count = AXI_R_WR_DATA_COUNT;
assign axi_r_rd_data_count = AXI_R_RD_DATA_COUNT;
assign AXIS_PROG_FULL_THRESH = axis_prog_full_thresh;
assign AXIS_PROG_EMPTY_THRESH = axis_prog_empty_thresh;
assign axis_data_count = AXIS_DATA_COUNT;
assign axis_wr_data_count = AXIS_WR_DATA_COUNT;
assign axis_rd_data_count = AXIS_RD_DATA_COUNT;
generate if (C_INTERFACE_TYPE == 0) begin : conv_fifo
fifo_generator_v13_1_0_CONV_VER
#(
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_USE_DOUT_RST == 1 ? C_DOUT_RST_VAL : 0),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_FAMILY (C_FAMILY),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RD_RST (C_HAS_RD_RST),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_HAS_WR_RST (C_HAS_WR_RST),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_FREQ (C_RD_FREQ),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
)
fifo_generator_v13_1_0_conv_dut
(
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.CLK (CLK),
.RST (RST),
.SRST (SRST),
.WR_CLK (WR_CLK),
.WR_RST (WR_RST),
.RD_CLK (RD_CLK),
.RD_RST (RD_RST),
.DIN (DIN),
.WR_EN (WR_EN),
.RD_EN (RD_EN),
.PROG_EMPTY_THRESH (PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT (PROG_EMPTY_THRESH_ASSERT),
.PROG_EMPTY_THRESH_NEGATE (PROG_EMPTY_THRESH_NEGATE),
.PROG_FULL_THRESH (PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT (PROG_FULL_THRESH_ASSERT),
.PROG_FULL_THRESH_NEGATE (PROG_FULL_THRESH_NEGATE),
.INT_CLK (INT_CLK),
.INJECTDBITERR (INJECTDBITERR),
.INJECTSBITERR (INJECTSBITERR),
.DOUT (DOUT),
.FULL (FULL),
.ALMOST_FULL (ALMOST_FULL),
.WR_ACK (WR_ACK),
.OVERFLOW (OVERFLOW),
.EMPTY (EMPTY),
.ALMOST_EMPTY (ALMOST_EMPTY),
.VALID (VALID),
.UNDERFLOW (UNDERFLOW),
.DATA_COUNT (DATA_COUNT),
.RD_DATA_COUNT (RD_DATA_COUNT),
.WR_DATA_COUNT (wr_data_count_in),
.PROG_FULL (PROG_FULL),
.PROG_EMPTY (PROG_EMPTY),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.wr_rst_busy (wr_rst_busy),
.rd_rst_busy (rd_rst_busy),
.wr_rst_i_out (wr_rst_int),
.rd_rst_i_out (rd_rst_int)
);
end endgenerate
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_AXI_SIZE_WIDTH = 3;
localparam C_AXI_BURST_WIDTH = 2;
localparam C_AXI_CACHE_WIDTH = 4;
localparam C_AXI_PROT_WIDTH = 3;
localparam C_AXI_QOS_WIDTH = 4;
localparam C_AXI_REGION_WIDTH = 4;
localparam C_AXI_BRESP_WIDTH = 2;
localparam C_AXI_RRESP_WIDTH = 2;
localparam IS_AXI_STREAMING = C_INTERFACE_TYPE == 1 ? 1 : 0;
localparam TDATA_OFFSET = C_HAS_AXIS_TDATA == 1 ? C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH : C_DIN_WIDTH_AXIS;
localparam TSTRB_OFFSET = C_HAS_AXIS_TSTRB == 1 ? TDATA_OFFSET-C_AXIS_TSTRB_WIDTH : TDATA_OFFSET;
localparam TKEEP_OFFSET = C_HAS_AXIS_TKEEP == 1 ? TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH : TSTRB_OFFSET;
localparam TID_OFFSET = C_HAS_AXIS_TID == 1 ? TKEEP_OFFSET-C_AXIS_TID_WIDTH : TKEEP_OFFSET;
localparam TDEST_OFFSET = C_HAS_AXIS_TDEST == 1 ? TID_OFFSET-C_AXIS_TDEST_WIDTH : TID_OFFSET;
localparam TUSER_OFFSET = C_HAS_AXIS_TUSER == 1 ? TDEST_OFFSET-C_AXIS_TUSER_WIDTH : TDEST_OFFSET;
localparam LOG_DEPTH_AXIS = find_log2(C_WR_DEPTH_AXIS);
localparam LOG_WR_DEPTH = find_log2(C_WR_DEPTH);
function [LOG_DEPTH_AXIS-1:0] bin2gray;
input [LOG_DEPTH_AXIS-1:0] x;
begin
bin2gray = x ^ (x>>1);
end
endfunction
function [LOG_DEPTH_AXIS-1:0] gray2bin;
input [LOG_DEPTH_AXIS-1:0] x;
integer i;
begin
gray2bin[LOG_DEPTH_AXIS-1] = x[LOG_DEPTH_AXIS-1];
for(i=LOG_DEPTH_AXIS-2; i>=0; i=i-1) begin
gray2bin[i] = gray2bin[i+1] ^ x[i];
end
end
endfunction
wire [(LOG_WR_DEPTH)-1 : 0] w_cnt_gc_asreg_last;
wire [LOG_WR_DEPTH-1 : 0] w_q [0:C_SYNCHRONIZER_STAGE] ;
wire [LOG_WR_DEPTH-1 : 0] w_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_rd = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt = 0;
reg [LOG_WR_DEPTH-1 : 0] w_cnt_gc = 0;
reg [LOG_WR_DEPTH-1 : 0] r_cnt = 0;
wire [LOG_WR_DEPTH : 0] adj_w_cnt_rd_pad;
wire [LOG_WR_DEPTH : 0] r_inv_pad;
wire [LOG_WR_DEPTH-1 : 0] d_cnt;
reg [LOG_WR_DEPTH : 0] d_cnt_pad = 0;
reg adj_w_cnt_rd_pad_0 = 0;
reg r_inv_pad_0 = 0;
genvar l;
generate for (l = 1; ((l <= C_SYNCHRONIZER_STAGE) && (C_HAS_DATA_COUNTS_AXIS == 3 && C_INTERFACE_TYPE == 0) ); l = l + 1) begin : g_cnt_sync_stage
fifo_generator_v13_1_0_sync_stage
#(
.C_WIDTH (LOG_WR_DEPTH)
)
rd_stg_inst
(
.RST (rd_rst_int),
.CLK (RD_CLK),
.DIN (w_q[l-1]),
.DOUT (w_q[l])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS == 3) begin : fifo_ic_adapter
assign wr_eop_ad = WR_EN & !(FULL);
assign rd_eop_ad = RD_EN & !(EMPTY);
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt <= 1'b0;
else if (wr_eop_ad)
w_cnt <= w_cnt + 1;
end
always @ (posedge wr_rst_int or posedge WR_CLK)
begin
if (wr_rst_int)
w_cnt_gc <= 1'b0;
else
w_cnt_gc <= bin2gray(w_cnt);
end
assign w_q[0] = w_cnt_gc;
assign w_cnt_gc_asreg_last = w_q[C_SYNCHRONIZER_STAGE];
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
w_cnt_rd <= 1'b0;
else
w_cnt_rd <= gray2bin(w_cnt_gc_asreg_last);
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
r_cnt <= 1'b0;
else if (rd_eop_ad)
r_cnt <= r_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_w_cnt_rd_pad[LOG_WR_DEPTH : 1] = w_cnt_rd;
assign r_inv_pad[LOG_WR_DEPTH : 1] = ~r_cnt;
assign adj_w_cnt_rd_pad[0] = adj_w_cnt_rd_pad_0;
assign r_inv_pad[0] = r_inv_pad_0;
always @ ( rd_eop_ad )
begin
if (!rd_eop_ad) begin
adj_w_cnt_rd_pad_0 <= 1'b1;
r_inv_pad_0 <= 1'b1;
end else begin
adj_w_cnt_rd_pad_0 <= 1'b0;
r_inv_pad_0 <= 1'b0;
end
end
always @ (posedge rd_rst_int or posedge RD_CLK)
begin
if (rd_rst_int)
d_cnt_pad <= 1'b0;
else
d_cnt_pad <= adj_w_cnt_rd_pad + r_inv_pad ;
end
assign d_cnt = d_cnt_pad [LOG_WR_DEPTH : 1] ;
assign WR_DATA_COUNT = d_cnt;
end endgenerate // fifo_ic_adapter
generate if (C_INTERFACE_TYPE == 0 && C_HAS_DATA_COUNTS_AXIS != 3) begin : fifo_icn_adapter
assign WR_DATA_COUNT = wr_data_count_in;
end endgenerate // fifo_icn_adapter
wire inverted_reset = ~S_ARESETN;
wire axi_rs_rst;
reg rst_d1 = 0 ;
reg rst_d2 = 0 ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_din ;
wire [C_DIN_WIDTH_AXIS-1:0] axis_dout ;
wire axis_full ;
wire axis_almost_full ;
wire axis_empty ;
wire axis_s_axis_tready;
wire axis_m_axis_tvalid;
wire axis_wr_en ;
wire axis_rd_en ;
wire axis_we ;
wire axis_re ;
wire [C_WR_PNTR_WIDTH_AXIS:0] axis_dc;
reg axis_pkt_read = 1'b0;
wire axis_rd_rst;
wire axis_wr_rst;
generate if (C_INTERFACE_TYPE > 0 && (C_AXIS_TYPE == 1 || C_WACH_TYPE == 1 ||
C_WDCH_TYPE == 1 || C_WRCH_TYPE == 1 || C_RACH_TYPE == 1 || C_RDCH_TYPE == 1)) begin : gaxi_rs_rst
always @ (posedge inverted_reset or posedge S_ACLK) begin
if (inverted_reset) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
end
end
assign axi_rs_rst = rst_d2;
end endgenerate // gaxi_rs_rst
generate if (IS_AXI_STREAMING == 1 && C_AXIS_TYPE == 0) begin : axi_streaming
// Write protection when almost full or prog_full is high
assign axis_we = (C_PROG_FULL_TYPE_AXIS != 0) ? axis_s_axis_tready & S_AXIS_TVALID :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_s_axis_tready & S_AXIS_TVALID : S_AXIS_TVALID;
// Read protection when almost empty or prog_empty is high
assign axis_re = (C_PROG_EMPTY_TYPE_AXIS != 0) ? axis_m_axis_tvalid & M_AXIS_TREADY :
(C_APPLICATION_TYPE_AXIS == 1) ? axis_m_axis_tvalid & M_AXIS_TREADY : M_AXIS_TREADY;
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? axis_we & S_ACLK_EN : axis_we;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? axis_re & M_ACLK_EN : axis_re;
fifo_generator_v13_1_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_AXIS == 2 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_AXIS == 1 || C_IMPLEMENTATION_TYPE_AXIS == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_AXIS == 11 || C_IMPLEMENTATION_TYPE_AXIS == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_AXIS),
.C_WR_DEPTH (C_WR_DEPTH_AXIS),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_DOUT_WIDTH (C_DIN_WIDTH_AXIS),
.C_RD_DEPTH (C_WR_DEPTH_AXIS),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_AXIS),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_AXIS),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_AXIS),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_AXIS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS),
.C_USE_ECC (C_USE_ECC_AXIS),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_AXIS),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (C_APPLICATION_TYPE_AXIS == 1 ? 1: 0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
//.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_FIFO_TYPE (C_APPLICATION_TYPE_AXIS == 1 ? 0: C_APPLICATION_TYPE_AXIS),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_AXIS == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_AXIS + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_0_axis_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (axis_wr_en),
.RD_EN (axis_rd_en),
.PROG_FULL_THRESH (AXIS_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH (AXIS_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_AXIS{1'b0}}),
.INJECTDBITERR (AXIS_INJECTDBITERR),
.INJECTSBITERR (AXIS_INJECTSBITERR),
.DIN (axis_din),
.DOUT (axis_dout),
.FULL (axis_full),
.EMPTY (axis_empty),
.ALMOST_FULL (axis_almost_full),
.PROG_FULL (AXIS_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXIS_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (AXIS_OVERFLOW),
.VALID (),
.UNDERFLOW (AXIS_UNDERFLOW),
.DATA_COUNT (axis_dc),
.RD_DATA_COUNT (AXIS_RD_DATA_COUNT),
.WR_DATA_COUNT (AXIS_WR_DATA_COUNT),
.SBITERR (AXIS_SBITERR),
.DBITERR (AXIS_DBITERR),
.wr_rst_busy (wr_rst_busy_axis),
.rd_rst_busy (rd_rst_busy_axis),
.wr_rst_i_out (axis_wr_rst),
.rd_rst_i_out (axis_rd_rst),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign axis_s_axis_tready = (IS_8SERIES == 0) ? ~axis_full : (C_IMPLEMENTATION_TYPE_AXIS == 5 || C_IMPLEMENTATION_TYPE_AXIS == 13) ? ~(axis_full | wr_rst_busy_axis) : ~axis_full;
assign axis_m_axis_tvalid = (C_APPLICATION_TYPE_AXIS != 1) ? ~axis_empty : ~axis_empty & axis_pkt_read;
assign S_AXIS_TREADY = axis_s_axis_tready;
assign M_AXIS_TVALID = axis_m_axis_tvalid;
end endgenerate // axi_streaming
wire axis_wr_eop;
reg axis_wr_eop_d1 = 1'b0;
wire axis_rd_eop;
integer axis_pkt_cnt;
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 1) begin : gaxis_pkt_fifo_cc
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (axis_pkt_cnt == 1) && ~axis_wr_eop_d1)
axis_pkt_read <= 1'b0;
else if ((axis_pkt_cnt > 0) || (axis_almost_full && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_wr_eop_d1 <= 1'b0;
else
axis_wr_eop_d1 <= axis_wr_eop;
end
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_pkt_cnt <= 0;
else if (axis_wr_eop_d1 && ~axis_rd_eop)
axis_pkt_cnt <= axis_pkt_cnt + 1;
else if (axis_rd_eop && ~axis_wr_eop_d1)
axis_pkt_cnt <= axis_pkt_cnt - 1;
end
end endgenerate // gaxis_pkt_fifo_cc
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_gc = 0;
wire [(LOG_DEPTH_AXIS)-1 : 0] axis_wpkt_cnt_gc_asreg_last;
wire axis_rd_has_rst;
wire [0:C_SYNCHRONIZER_STAGE] axis_af_q ;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q [0:C_SYNCHRONIZER_STAGE] ;
wire [1:C_SYNCHRONIZER_STAGE] axis_af_q_temp = 0;
wire [LOG_DEPTH_AXIS-1 : 0] wpkt_q_temp [1:C_SYNCHRONIZER_STAGE] ;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt_rd = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_wpkt_cnt = 0;
reg [LOG_DEPTH_AXIS-1 : 0] axis_rpkt_cnt = 0;
wire [LOG_DEPTH_AXIS : 0] adj_axis_wpkt_cnt_rd_pad;
wire [LOG_DEPTH_AXIS : 0] rpkt_inv_pad;
wire [LOG_DEPTH_AXIS-1 : 0] diff_pkt_cnt;
reg [LOG_DEPTH_AXIS : 0] diff_pkt_cnt_pad = 0;
reg adj_axis_wpkt_cnt_rd_pad_0 = 0;
reg rpkt_inv_pad_0 = 0;
wire axis_af_rd ;
generate if (C_HAS_RST == 1) begin : rst_blk_has
assign axis_rd_has_rst = axis_rd_rst;
end endgenerate //rst_blk_has
generate if (C_HAS_RST == 0) begin :rst_blk_no
assign axis_rd_has_rst = 1'b0;
end endgenerate //rst_blk_no
genvar i;
generate for (i = 1; ((i <= C_SYNCHRONIZER_STAGE) && (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) ); i = i + 1) begin : gpkt_cnt_sync_stage
fifo_generator_v13_1_0_sync_stage
#(
.C_WIDTH (LOG_DEPTH_AXIS)
)
rd_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (wpkt_q[i-1]),
.DOUT (wpkt_q[i])
);
fifo_generator_v13_1_0_sync_stage
#(
.C_WIDTH (1)
)
wr_stg_inst
(
.RST (axis_rd_has_rst),
.CLK (M_ACLK),
.DIN (axis_af_q[i-1]),
.DOUT (axis_af_q[i])
);
end endgenerate // gpkt_cnt_sync_stage
generate if (C_APPLICATION_TYPE_AXIS == 1 && C_COMMON_CLOCK == 0) begin : gaxis_pkt_fifo_ic
assign axis_wr_eop = axis_wr_en & S_AXIS_TLAST;
assign axis_rd_eop = axis_rd_en & axis_dout[0];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_pkt_read <= 1'b0;
else if (axis_rd_eop && (diff_pkt_cnt == 1))
axis_pkt_read <= 1'b0;
else if ((diff_pkt_cnt > 0) || (axis_af_rd && ~axis_empty))
axis_pkt_read <= 1'b1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt <= 1'b0;
else if (axis_wr_eop)
axis_wpkt_cnt <= axis_wpkt_cnt + 1;
end
always @ (posedge axis_wr_rst or posedge S_ACLK)
begin
if (axis_wr_rst)
axis_wpkt_cnt_gc <= 1'b0;
else
axis_wpkt_cnt_gc <= bin2gray(axis_wpkt_cnt);
end
assign wpkt_q[0] = axis_wpkt_cnt_gc;
assign axis_wpkt_cnt_gc_asreg_last = wpkt_q[C_SYNCHRONIZER_STAGE];
assign axis_af_q[0] = axis_almost_full;
//assign axis_af_q[1:C_SYNCHRONIZER_STAGE] = axis_af_q_temp[1:C_SYNCHRONIZER_STAGE];
assign axis_af_rd = axis_af_q[C_SYNCHRONIZER_STAGE];
always @ (posedge axis_rd_has_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_wpkt_cnt_rd <= 1'b0;
else
axis_wpkt_cnt_rd <= gray2bin(axis_wpkt_cnt_gc_asreg_last);
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
axis_rpkt_cnt <= 1'b0;
else if (axis_rd_eop)
axis_rpkt_cnt <= axis_rpkt_cnt + 1;
end
// Take the difference of write and read packet count
// Logic is similar to rd_pe_as
assign adj_axis_wpkt_cnt_rd_pad[LOG_DEPTH_AXIS : 1] = axis_wpkt_cnt_rd;
assign rpkt_inv_pad[LOG_DEPTH_AXIS : 1] = ~axis_rpkt_cnt;
assign adj_axis_wpkt_cnt_rd_pad[0] = adj_axis_wpkt_cnt_rd_pad_0;
assign rpkt_inv_pad[0] = rpkt_inv_pad_0;
always @ ( axis_rd_eop )
begin
if (!axis_rd_eop) begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b1;
rpkt_inv_pad_0 <= 1'b1;
end else begin
adj_axis_wpkt_cnt_rd_pad_0 <= 1'b0;
rpkt_inv_pad_0 <= 1'b0;
end
end
always @ (posedge axis_rd_rst or posedge M_ACLK)
begin
if (axis_rd_has_rst)
diff_pkt_cnt_pad <= 1'b0;
else
diff_pkt_cnt_pad <= adj_axis_wpkt_cnt_rd_pad + rpkt_inv_pad ;
end
assign diff_pkt_cnt = diff_pkt_cnt_pad [LOG_DEPTH_AXIS : 1] ;
end endgenerate // gaxis_pkt_fifo_ic
// Generate the accurate data count for axi stream packet fifo configuration
reg [C_WR_PNTR_WIDTH_AXIS:0] axis_dc_pkt_fifo = 0;
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 1 && C_APPLICATION_TYPE_AXIS == 1) begin : gdc_pkt
always @ (posedge inverted_reset or posedge S_ACLK)
begin
if (inverted_reset)
axis_dc_pkt_fifo <= 0;
else if (axis_wr_en && (~axis_rd_en))
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo + 1;
else if (~axis_wr_en && axis_rd_en)
axis_dc_pkt_fifo <= #`TCQ axis_dc_pkt_fifo - 1;
end
assign AXIS_DATA_COUNT = axis_dc_pkt_fifo;
end endgenerate // gdc_pkt
generate if (IS_AXI_STREAMING == 1 && C_HAS_DATA_COUNTS_AXIS == 0 && C_APPLICATION_TYPE_AXIS == 1) begin : gndc_pkt
assign AXIS_DATA_COUNT = 0;
end endgenerate // gndc_pkt
generate if (IS_AXI_STREAMING == 1 && C_APPLICATION_TYPE_AXIS != 1) begin : gdc
assign AXIS_DATA_COUNT = axis_dc;
end endgenerate // gdc
// Register Slice for Write Address Channel
generate if (C_AXIS_TYPE == 1) begin : gaxis_reg_slice
assign axis_wr_en = (C_HAS_SLAVE_CE == 1) ? S_AXIS_TVALID & S_ACLK_EN : S_AXIS_TVALID;
assign axis_rd_en = (C_HAS_MASTER_CE == 1) ? M_AXIS_TREADY & M_ACLK_EN : M_AXIS_TREADY;
fifo_generator_v13_1_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_AXIS),
.C_REG_CONFIG (C_REG_SLICE_MODE_AXIS)
)
axis_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (axis_din),
.S_VALID (axis_wr_en),
.S_READY (S_AXIS_TREADY),
// Master side
.M_PAYLOAD_DATA (axis_dout),
.M_VALID (M_AXIS_TVALID),
.M_READY (axis_rd_en)
);
end endgenerate // gaxis_reg_slice
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDATA == 1) begin : tdata
assign axis_din[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET] = S_AXIS_TDATA;
assign M_AXIS_TDATA = axis_dout[C_DIN_WIDTH_AXIS-1:TDATA_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TSTRB == 1) begin : tstrb
assign axis_din[TDATA_OFFSET-1:TSTRB_OFFSET] = S_AXIS_TSTRB;
assign M_AXIS_TSTRB = axis_dout[TDATA_OFFSET-1:TSTRB_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TKEEP == 1) begin : tkeep
assign axis_din[TSTRB_OFFSET-1:TKEEP_OFFSET] = S_AXIS_TKEEP;
assign M_AXIS_TKEEP = axis_dout[TSTRB_OFFSET-1:TKEEP_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TID == 1) begin : tid
assign axis_din[TKEEP_OFFSET-1:TID_OFFSET] = S_AXIS_TID;
assign M_AXIS_TID = axis_dout[TKEEP_OFFSET-1:TID_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TDEST == 1) begin : tdest
assign axis_din[TID_OFFSET-1:TDEST_OFFSET] = S_AXIS_TDEST;
assign M_AXIS_TDEST = axis_dout[TID_OFFSET-1:TDEST_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TUSER == 1) begin : tuser
assign axis_din[TDEST_OFFSET-1:TUSER_OFFSET] = S_AXIS_TUSER;
assign M_AXIS_TUSER = axis_dout[TDEST_OFFSET-1:TUSER_OFFSET];
end endgenerate
generate if ((IS_AXI_STREAMING == 1 || C_AXIS_TYPE == 1) && C_HAS_AXIS_TLAST == 1) begin : tlast
assign axis_din[0] = S_AXIS_TLAST;
assign M_AXIS_TLAST = axis_dout[0];
end endgenerate
//###########################################################################
// AXI FULL Write Channel (axi_write_channel)
//###########################################################################
localparam IS_AXI_FULL = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE != 2)) ? 1 : 0;
localparam IS_AXI_LITE = ((C_INTERFACE_TYPE == 2) && (C_AXI_TYPE == 2)) ? 1 : 0;
localparam IS_AXI_FULL_WACH = ((IS_AXI_FULL == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WDCH = ((IS_AXI_FULL == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_WRCH = ((IS_AXI_FULL == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RACH = ((IS_AXI_FULL == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_FULL_RDCH = ((IS_AXI_FULL == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WACH = ((IS_AXI_LITE == 1) && (C_WACH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WDCH = ((IS_AXI_LITE == 1) && (C_WDCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_WRCH = ((IS_AXI_LITE == 1) && (C_WRCH_TYPE == 0) && C_HAS_AXI_WR_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RACH = ((IS_AXI_LITE == 1) && (C_RACH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_AXI_LITE_RDCH = ((IS_AXI_LITE == 1) && (C_RDCH_TYPE == 0) && C_HAS_AXI_RD_CHANNEL == 1) ? 1 : 0;
localparam IS_WR_ADDR_CH = ((IS_AXI_FULL_WACH == 1) || (IS_AXI_LITE_WACH == 1)) ? 1 : 0;
localparam IS_WR_DATA_CH = ((IS_AXI_FULL_WDCH == 1) || (IS_AXI_LITE_WDCH == 1)) ? 1 : 0;
localparam IS_WR_RESP_CH = ((IS_AXI_FULL_WRCH == 1) || (IS_AXI_LITE_WRCH == 1)) ? 1 : 0;
localparam IS_RD_ADDR_CH = ((IS_AXI_FULL_RACH == 1) || (IS_AXI_LITE_RACH == 1)) ? 1 : 0;
localparam IS_RD_DATA_CH = ((IS_AXI_FULL_RDCH == 1) || (IS_AXI_LITE_RDCH == 1)) ? 1 : 0;
localparam AWID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WACH;
localparam AWADDR_OFFSET = AWID_OFFSET - C_AXI_ADDR_WIDTH;
localparam AWLEN_OFFSET = C_AXI_TYPE != 2 ? AWADDR_OFFSET - C_AXI_LEN_WIDTH : AWADDR_OFFSET;
localparam AWSIZE_OFFSET = C_AXI_TYPE != 2 ? AWLEN_OFFSET - C_AXI_SIZE_WIDTH : AWLEN_OFFSET;
localparam AWBURST_OFFSET = C_AXI_TYPE != 2 ? AWSIZE_OFFSET - C_AXI_BURST_WIDTH : AWSIZE_OFFSET;
localparam AWLOCK_OFFSET = C_AXI_TYPE != 2 ? AWBURST_OFFSET - C_AXI_LOCK_WIDTH : AWBURST_OFFSET;
localparam AWCACHE_OFFSET = C_AXI_TYPE != 2 ? AWLOCK_OFFSET - C_AXI_CACHE_WIDTH : AWLOCK_OFFSET;
localparam AWPROT_OFFSET = AWCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam AWQOS_OFFSET = AWPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam AWREGION_OFFSET = C_AXI_TYPE == 1 ? AWQOS_OFFSET - C_AXI_REGION_WIDTH : AWQOS_OFFSET;
localparam AWUSER_OFFSET = C_HAS_AXI_AWUSER == 1 ? AWREGION_OFFSET-C_AXI_AWUSER_WIDTH : AWREGION_OFFSET;
localparam WID_OFFSET = (C_AXI_TYPE == 3 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WDCH;
localparam WDATA_OFFSET = WID_OFFSET - C_AXI_DATA_WIDTH;
localparam WSTRB_OFFSET = WDATA_OFFSET - C_AXI_DATA_WIDTH/8;
localparam WUSER_OFFSET = C_HAS_AXI_WUSER == 1 ? WSTRB_OFFSET-C_AXI_WUSER_WIDTH : WSTRB_OFFSET;
localparam BID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_WRCH;
localparam BRESP_OFFSET = BID_OFFSET - C_AXI_BRESP_WIDTH;
localparam BUSER_OFFSET = C_HAS_AXI_BUSER == 1 ? BRESP_OFFSET-C_AXI_BUSER_WIDTH : BRESP_OFFSET;
wire [C_DIN_WIDTH_WACH-1:0] wach_din ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout ;
wire [C_DIN_WIDTH_WACH-1:0] wach_dout_pkt ;
wire wach_full ;
wire wach_almost_full ;
wire wach_prog_full ;
wire wach_empty ;
wire wach_almost_empty ;
wire wach_prog_empty ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_din ;
wire [C_DIN_WIDTH_WDCH-1:0] wdch_dout ;
wire wdch_full ;
wire wdch_almost_full ;
wire wdch_prog_full ;
wire wdch_empty ;
wire wdch_almost_empty ;
wire wdch_prog_empty ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_din ;
wire [C_DIN_WIDTH_WRCH-1:0] wrch_dout ;
wire wrch_full ;
wire wrch_almost_full ;
wire wrch_prog_full ;
wire wrch_empty ;
wire wrch_almost_empty ;
wire wrch_prog_empty ;
wire axi_aw_underflow_i;
wire axi_w_underflow_i ;
wire axi_b_underflow_i ;
wire axi_aw_overflow_i ;
wire axi_w_overflow_i ;
wire axi_b_overflow_i ;
wire axi_wr_underflow_i;
wire axi_wr_overflow_i ;
wire wach_s_axi_awready;
wire wach_m_axi_awvalid;
wire wach_wr_en ;
wire wach_rd_en ;
wire wdch_s_axi_wready ;
wire wdch_m_axi_wvalid ;
wire wdch_wr_en ;
wire wdch_rd_en ;
wire wrch_s_axi_bvalid ;
wire wrch_m_axi_bready ;
wire wrch_wr_en ;
wire wrch_rd_en ;
wire txn_count_up ;
wire txn_count_down ;
wire awvalid_en ;
wire awvalid_pkt ;
wire awready_pkt ;
integer wr_pkt_count ;
wire wach_we ;
wire wach_re ;
wire wdch_we ;
wire wdch_re ;
wire wrch_we ;
wire wrch_re ;
generate if (IS_WR_ADDR_CH == 1) begin : axi_write_address_channel
// Write protection when almost full or prog_full is high
assign wach_we = (C_PROG_FULL_TYPE_WACH != 0) ? wach_s_axi_awready & S_AXI_AWVALID : S_AXI_AWVALID;
// Read protection when almost empty or prog_empty is high
assign wach_re = (C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH == 1) ?
wach_m_axi_awvalid & awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH != 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY && wach_m_axi_awvalid :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH == 1) ?
awready_pkt & awvalid_en :
(C_PROG_EMPTY_TYPE_WACH == 0 && C_APPLICATION_TYPE_WACH != 1) ?
M_AXI_AWREADY : 1'b0;
assign wach_wr_en = (C_HAS_SLAVE_CE == 1) ? wach_we & S_ACLK_EN : wach_we;
assign wach_rd_en = (C_HAS_MASTER_CE == 1) ? wach_re & M_ACLK_EN : wach_re;
fifo_generator_v13_1_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WACH == 2 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WACH == 1 || C_IMPLEMENTATION_TYPE_WACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WACH == 11 || C_IMPLEMENTATION_TYPE_WACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_DEPTH (C_WR_DEPTH_WACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WACH),
.C_RD_DEPTH (C_WR_DEPTH_WACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH),
.C_USE_ECC (C_USE_ECC_WACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_WACH == 1)?0:C_APPLICATION_TYPE_WACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_EN_SAFETY_CKT (1),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
//.C_EN_SAFETY_CKT (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_0_wach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wach_wr_en),
.RD_EN (wach_rd_en),
.PROG_FULL_THRESH (AXI_AW_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AW_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WACH{1'b0}}),
.INJECTDBITERR (AXI_AW_INJECTDBITERR),
.INJECTSBITERR (AXI_AW_INJECTSBITERR),
.DIN (wach_din),
.DOUT (wach_dout_pkt),
.FULL (wach_full),
.EMPTY (wach_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_AW_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_AW_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_aw_overflow_i),
.VALID (),
.UNDERFLOW (axi_aw_underflow_i),
.DATA_COUNT (AXI_AW_DATA_COUNT),
.RD_DATA_COUNT (AXI_AW_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AW_WR_DATA_COUNT),
.SBITERR (AXI_AW_SBITERR),
.DBITERR (AXI_AW_DBITERR),
.wr_rst_busy (wr_rst_busy_wach),
.rd_rst_busy (rd_rst_busy_wach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wach_s_axi_awready = (IS_8SERIES == 0) ? ~wach_full : (C_IMPLEMENTATION_TYPE_WACH == 5 || C_IMPLEMENTATION_TYPE_WACH == 13) ? ~(wach_full | wr_rst_busy_wach) : ~wach_full;
assign wach_m_axi_awvalid = ~wach_empty;
assign S_AXI_AWREADY = wach_s_axi_awready;
assign AXI_AW_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_aw_underflow_i : 0;
assign AXI_AW_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_aw_overflow_i : 0;
end endgenerate // axi_write_address_channel
// Register Slice for Write Address Channel
generate if (C_WACH_TYPE == 1) begin : gwach_reg_slice
fifo_generator_v13_1_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WACH)
)
wach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wach_din),
.S_VALID (S_AXI_AWVALID),
.S_READY (S_AXI_AWREADY),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
end endgenerate // gwach_reg_slice
generate if (C_APPLICATION_TYPE_WACH == 1 && C_HAS_AXI_WR_CHANNEL == 1) begin : axi_mm_pkt_fifo_wr
fifo_generator_v13_1_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WACH),
.C_REG_CONFIG (1)
)
wach_pkt_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (wach_dout_pkt),
.S_VALID (awvalid_pkt),
.S_READY (awready_pkt),
// Master side
.M_PAYLOAD_DATA (wach_dout),
.M_VALID (M_AXI_AWVALID),
.M_READY (M_AXI_AWREADY)
);
assign awvalid_pkt = wach_m_axi_awvalid && awvalid_en;
assign txn_count_up = wdch_s_axi_wready && wdch_wr_en && wdch_din[0];
assign txn_count_down = wach_m_axi_awvalid && awready_pkt && awvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset == 1) begin
wr_pkt_count <= 0;
end else begin
if(txn_count_up == 1 && txn_count_down == 0) begin
wr_pkt_count <= wr_pkt_count + 1;
end else if(txn_count_up == 0 && txn_count_down == 1) begin
wr_pkt_count <= wr_pkt_count - 1;
end
end
end //Always end
assign awvalid_en = (wr_pkt_count > 0)?1:0;
end endgenerate
generate if (C_APPLICATION_TYPE_WACH != 1) begin : axi_mm_fifo_wr
assign awvalid_en = 1;
assign wach_dout = wach_dout_pkt;
assign M_AXI_AWVALID = wach_m_axi_awvalid;
end
endgenerate
generate if (IS_WR_DATA_CH == 1) begin : axi_write_data_channel
// Write protection when almost full or prog_full is high
assign wdch_we = (C_PROG_FULL_TYPE_WDCH != 0) ? wdch_s_axi_wready & S_AXI_WVALID : S_AXI_WVALID;
// Read protection when almost empty or prog_empty is high
assign wdch_re = (C_PROG_EMPTY_TYPE_WDCH != 0) ? wdch_m_axi_wvalid & M_AXI_WREADY : M_AXI_WREADY;
assign wdch_wr_en = (C_HAS_SLAVE_CE == 1) ? wdch_we & S_ACLK_EN : wdch_we;
assign wdch_rd_en = (C_HAS_MASTER_CE == 1) ? wdch_re & M_ACLK_EN : wdch_re;
fifo_generator_v13_1_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WDCH == 2 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WDCH == 1 || C_IMPLEMENTATION_TYPE_WDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WDCH == 11 || C_IMPLEMENTATION_TYPE_WDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WDCH),
.C_WR_DEPTH (C_WR_DEPTH_WDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WDCH),
.C_RD_DEPTH (C_WR_DEPTH_WDCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH),
.C_USE_ECC (C_USE_ECC_WDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_0_wdch_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wdch_wr_en),
.RD_EN (wdch_rd_en),
.PROG_FULL_THRESH (AXI_W_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_W_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WDCH{1'b0}}),
.INJECTDBITERR (AXI_W_INJECTDBITERR),
.INJECTSBITERR (AXI_W_INJECTSBITERR),
.DIN (wdch_din),
.DOUT (wdch_dout),
.FULL (wdch_full),
.EMPTY (wdch_empty),
.ALMOST_FULL (),
.PROG_FULL (AXI_W_PROG_FULL),
.ALMOST_EMPTY (),
.PROG_EMPTY (AXI_W_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_w_overflow_i),
.VALID (),
.UNDERFLOW (axi_w_underflow_i),
.DATA_COUNT (AXI_W_DATA_COUNT),
.RD_DATA_COUNT (AXI_W_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_W_WR_DATA_COUNT),
.SBITERR (AXI_W_SBITERR),
.DBITERR (AXI_W_DBITERR),
.wr_rst_busy (wr_rst_busy_wdch),
.rd_rst_busy (rd_rst_busy_wdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wdch_s_axi_wready = (IS_8SERIES == 0) ? ~wdch_full : (C_IMPLEMENTATION_TYPE_WDCH == 5 || C_IMPLEMENTATION_TYPE_WDCH == 13) ? ~(wdch_full | wr_rst_busy_wdch) : ~wdch_full;
assign wdch_m_axi_wvalid = ~wdch_empty;
assign S_AXI_WREADY = wdch_s_axi_wready;
assign M_AXI_WVALID = wdch_m_axi_wvalid;
assign AXI_W_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_w_underflow_i : 0;
assign AXI_W_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_w_overflow_i : 0;
end endgenerate // axi_write_data_channel
// Register Slice for Write Data Channel
generate if (C_WDCH_TYPE == 1) begin : gwdch_reg_slice
fifo_generator_v13_1_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WDCH)
)
wdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wdch_din),
.S_VALID (S_AXI_WVALID),
.S_READY (S_AXI_WREADY),
// Master side
.M_PAYLOAD_DATA (wdch_dout),
.M_VALID (M_AXI_WVALID),
.M_READY (M_AXI_WREADY)
);
end endgenerate // gwdch_reg_slice
generate if (IS_WR_RESP_CH == 1) begin : axi_write_resp_channel
// Write protection when almost full or prog_full is high
assign wrch_we = (C_PROG_FULL_TYPE_WRCH != 0) ? wrch_m_axi_bready & M_AXI_BVALID : M_AXI_BVALID;
// Read protection when almost empty or prog_empty is high
assign wrch_re = (C_PROG_EMPTY_TYPE_WRCH != 0) ? wrch_s_axi_bvalid & S_AXI_BREADY : S_AXI_BREADY;
assign wrch_wr_en = (C_HAS_MASTER_CE == 1) ? wrch_we & M_ACLK_EN : wrch_we;
assign wrch_rd_en = (C_HAS_SLAVE_CE == 1) ? wrch_re & S_ACLK_EN : wrch_re;
fifo_generator_v13_1_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_WRCH == 2 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_WRCH == 1 || C_IMPLEMENTATION_TYPE_WRCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_WRCH == 11 || C_IMPLEMENTATION_TYPE_WRCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_WRCH),
.C_WR_DEPTH (C_WR_DEPTH_WRCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_WRCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_DEPTH (C_WR_DEPTH_WRCH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_WRCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_WRCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_WRCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_WRCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH),
.C_USE_ECC (C_USE_ECC_WRCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_WRCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_WRCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_WRCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_WRCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_0_wrch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (wrch_wr_en),
.RD_EN (wrch_rd_en),
.PROG_FULL_THRESH (AXI_B_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_B_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_WRCH{1'b0}}),
.INJECTDBITERR (AXI_B_INJECTDBITERR),
.INJECTSBITERR (AXI_B_INJECTSBITERR),
.DIN (wrch_din),
.DOUT (wrch_dout),
.FULL (wrch_full),
.EMPTY (wrch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_B_PROG_FULL),
.PROG_EMPTY (AXI_B_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_b_overflow_i),
.VALID (),
.UNDERFLOW (axi_b_underflow_i),
.DATA_COUNT (AXI_B_DATA_COUNT),
.RD_DATA_COUNT (AXI_B_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_B_WR_DATA_COUNT),
.SBITERR (AXI_B_SBITERR),
.DBITERR (AXI_B_DBITERR),
.wr_rst_busy (wr_rst_busy_wrch),
.rd_rst_busy (rd_rst_busy_wrch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign wrch_s_axi_bvalid = ~wrch_empty;
assign wrch_m_axi_bready = (IS_8SERIES == 0) ? ~wrch_full : (C_IMPLEMENTATION_TYPE_WRCH == 5 || C_IMPLEMENTATION_TYPE_WRCH == 13) ? ~(wrch_full | wr_rst_busy_wrch) : ~wrch_full;
assign S_AXI_BVALID = wrch_s_axi_bvalid;
assign M_AXI_BREADY = wrch_m_axi_bready;
assign AXI_B_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_b_underflow_i : 0;
assign AXI_B_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_b_overflow_i : 0;
end endgenerate // axi_write_resp_channel
// Register Slice for Write Response Channel
generate if (C_WRCH_TYPE == 1) begin : gwrch_reg_slice
fifo_generator_v13_1_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_WRCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_WRCH)
)
wrch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (wrch_din),
.S_VALID (M_AXI_BVALID),
.S_READY (M_AXI_BREADY),
// Master side
.M_PAYLOAD_DATA (wrch_dout),
.M_VALID (S_AXI_BVALID),
.M_READY (S_AXI_BREADY)
);
end endgenerate // gwrch_reg_slice
assign axi_wr_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_aw_underflow_i || axi_w_underflow_i || axi_b_underflow_i) : 0;
assign axi_wr_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_aw_overflow_i || axi_w_overflow_i || axi_b_overflow_i) : 0;
generate if (IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output
assign M_AXI_AWADDR = wach_dout[AWID_OFFSET-1:AWADDR_OFFSET];
assign M_AXI_AWLEN = wach_dout[AWADDR_OFFSET-1:AWLEN_OFFSET];
assign M_AXI_AWSIZE = wach_dout[AWLEN_OFFSET-1:AWSIZE_OFFSET];
assign M_AXI_AWBURST = wach_dout[AWSIZE_OFFSET-1:AWBURST_OFFSET];
assign M_AXI_AWLOCK = wach_dout[AWBURST_OFFSET-1:AWLOCK_OFFSET];
assign M_AXI_AWCACHE = wach_dout[AWLOCK_OFFSET-1:AWCACHE_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWCACHE_OFFSET-1:AWPROT_OFFSET];
assign M_AXI_AWQOS = wach_dout[AWPROT_OFFSET-1:AWQOS_OFFSET];
assign wach_din[AWID_OFFSET-1:AWADDR_OFFSET] = S_AXI_AWADDR;
assign wach_din[AWADDR_OFFSET-1:AWLEN_OFFSET] = S_AXI_AWLEN;
assign wach_din[AWLEN_OFFSET-1:AWSIZE_OFFSET] = S_AXI_AWSIZE;
assign wach_din[AWSIZE_OFFSET-1:AWBURST_OFFSET] = S_AXI_AWBURST;
assign wach_din[AWBURST_OFFSET-1:AWLOCK_OFFSET] = S_AXI_AWLOCK;
assign wach_din[AWLOCK_OFFSET-1:AWCACHE_OFFSET] = S_AXI_AWCACHE;
assign wach_din[AWCACHE_OFFSET-1:AWPROT_OFFSET] = S_AXI_AWPROT;
assign wach_din[AWPROT_OFFSET-1:AWQOS_OFFSET] = S_AXI_AWQOS;
end endgenerate // axi_wach_output
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_awregion
assign M_AXI_AWREGION = wach_dout[AWQOS_OFFSET-1:AWREGION_OFFSET];
end endgenerate // axi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_awregion
assign M_AXI_AWREGION = 0;
end endgenerate // naxi_awregion
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : axi_awuser
assign M_AXI_AWUSER = wach_dout[AWREGION_OFFSET-1:AWUSER_OFFSET];
end endgenerate // axi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 0) begin : naxi_awuser
assign M_AXI_AWUSER = 0;
end endgenerate // naxi_awuser
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_awid
assign M_AXI_AWID = wach_dout[C_DIN_WIDTH_WACH-1:AWID_OFFSET];
end endgenerate //axi_awid
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_awid
assign M_AXI_AWID = 0;
end endgenerate //naxi_awid
generate if (IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output
assign M_AXI_WDATA = wdch_dout[WID_OFFSET-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
assign M_AXI_WLAST = wdch_dout[0];
assign wdch_din[WID_OFFSET-1:WDATA_OFFSET] = S_AXI_WDATA;
assign wdch_din[WDATA_OFFSET-1:WSTRB_OFFSET] = S_AXI_WSTRB;
assign wdch_din[0] = S_AXI_WLAST;
end endgenerate // axi_wdch_output
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin
assign M_AXI_WID = wdch_dout[C_DIN_WIDTH_WDCH-1:WID_OFFSET];
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && (C_HAS_AXI_ID == 0 || C_AXI_TYPE != 3)) begin
assign M_AXI_WID = 0;
end endgenerate
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1 ) begin
assign M_AXI_WUSER = wdch_dout[WSTRB_OFFSET-1:WUSER_OFFSET];
end endgenerate
generate if (C_HAS_AXI_WUSER == 0) begin
assign M_AXI_WUSER = 0;
end endgenerate
generate if (IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output
assign S_AXI_BRESP = wrch_dout[BID_OFFSET-1:BRESP_OFFSET];
assign wrch_din[BID_OFFSET-1:BRESP_OFFSET] = M_AXI_BRESP;
end endgenerate // axi_wrch_output
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : axi_buser
assign S_AXI_BUSER = wrch_dout[BRESP_OFFSET-1:BUSER_OFFSET];
end endgenerate // axi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 0) begin : naxi_buser
assign S_AXI_BUSER = 0;
end endgenerate // naxi_buser
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_bid
assign S_AXI_BID = wrch_dout[C_DIN_WIDTH_WRCH-1:BID_OFFSET];
end endgenerate // axi_bid
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_bid
assign S_AXI_BID = 0 ;
end endgenerate // naxi_bid
generate if (IS_AXI_LITE_WACH == 1 || (IS_AXI_LITE == 1 && C_WACH_TYPE == 1)) begin : axi_wach_output1
assign wach_din = {S_AXI_AWADDR, S_AXI_AWPROT};
assign M_AXI_AWADDR = wach_dout[C_DIN_WIDTH_WACH-1:AWADDR_OFFSET];
assign M_AXI_AWPROT = wach_dout[AWADDR_OFFSET-1:AWPROT_OFFSET];
end endgenerate // axi_wach_output1
generate if (IS_AXI_LITE_WDCH == 1 || (IS_AXI_LITE == 1 && C_WDCH_TYPE == 1)) begin : axi_wdch_output1
assign wdch_din = {S_AXI_WDATA, S_AXI_WSTRB};
assign M_AXI_WDATA = wdch_dout[C_DIN_WIDTH_WDCH-1:WDATA_OFFSET];
assign M_AXI_WSTRB = wdch_dout[WDATA_OFFSET-1:WSTRB_OFFSET];
end endgenerate // axi_wdch_output1
generate if (IS_AXI_LITE_WRCH == 1 || (IS_AXI_LITE == 1 && C_WRCH_TYPE == 1)) begin : axi_wrch_output1
assign wrch_din = M_AXI_BRESP;
assign S_AXI_BRESP = wrch_dout[C_DIN_WIDTH_WRCH-1:BRESP_OFFSET];
end endgenerate // axi_wrch_output1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_AWUSER == 1) begin : gwach_din1
assign wach_din[AWREGION_OFFSET-1:AWUSER_OFFSET] = S_AXI_AWUSER;
end endgenerate // gwach_din1
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwach_din2
assign wach_din[C_DIN_WIDTH_WACH-1:AWID_OFFSET] = S_AXI_AWID;
end endgenerate // gwach_din2
generate if ((IS_AXI_FULL_WACH == 1 || (IS_AXI_FULL == 1 && C_WACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : gwach_din3
assign wach_din[AWQOS_OFFSET-1:AWREGION_OFFSET] = S_AXI_AWREGION;
end endgenerate // gwach_din3
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_WUSER == 1) begin : gwdch_din1
assign wdch_din[WSTRB_OFFSET-1:WUSER_OFFSET] = S_AXI_WUSER;
end endgenerate // gwdch_din1
generate if ((IS_AXI_FULL_WDCH == 1 || (IS_AXI_FULL == 1 && C_WDCH_TYPE == 1)) && C_HAS_AXI_ID == 1 && C_AXI_TYPE == 3) begin : gwdch_din2
assign wdch_din[C_DIN_WIDTH_WDCH-1:WID_OFFSET] = S_AXI_WID;
end endgenerate // gwdch_din2
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_BUSER == 1) begin : gwrch_din1
assign wrch_din[BRESP_OFFSET-1:BUSER_OFFSET] = M_AXI_BUSER;
end endgenerate // gwrch_din1
generate if ((IS_AXI_FULL_WRCH == 1 || (IS_AXI_FULL == 1 && C_WRCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : gwrch_din2
assign wrch_din[C_DIN_WIDTH_WRCH-1:BID_OFFSET] = M_AXI_BID;
end endgenerate // gwrch_din2
//end of axi_write_channel
//###########################################################################
// AXI FULL Read Channel (axi_read_channel)
//###########################################################################
wire [C_DIN_WIDTH_RACH-1:0] rach_din ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout ;
wire [C_DIN_WIDTH_RACH-1:0] rach_dout_pkt ;
wire rach_full ;
wire rach_almost_full ;
wire rach_prog_full ;
wire rach_empty ;
wire rach_almost_empty ;
wire rach_prog_empty ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_din ;
wire [C_DIN_WIDTH_RDCH-1:0] rdch_dout ;
wire rdch_full ;
wire rdch_almost_full ;
wire rdch_prog_full ;
wire rdch_empty ;
wire rdch_almost_empty ;
wire rdch_prog_empty ;
wire axi_ar_underflow_i ;
wire axi_r_underflow_i ;
wire axi_ar_overflow_i ;
wire axi_r_overflow_i ;
wire axi_rd_underflow_i ;
wire axi_rd_overflow_i ;
wire rach_s_axi_arready ;
wire rach_m_axi_arvalid ;
wire rach_wr_en ;
wire rach_rd_en ;
wire rdch_m_axi_rready ;
wire rdch_s_axi_rvalid ;
wire rdch_wr_en ;
wire rdch_rd_en ;
wire arvalid_pkt ;
wire arready_pkt ;
wire arvalid_en ;
wire rdch_rd_ok ;
wire accept_next_pkt ;
integer rdch_free_space ;
integer rdch_commited_space ;
wire rach_we ;
wire rach_re ;
wire rdch_we ;
wire rdch_re ;
localparam ARID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RACH;
localparam ARADDR_OFFSET = ARID_OFFSET - C_AXI_ADDR_WIDTH;
localparam ARLEN_OFFSET = C_AXI_TYPE != 2 ? ARADDR_OFFSET - C_AXI_LEN_WIDTH : ARADDR_OFFSET;
localparam ARSIZE_OFFSET = C_AXI_TYPE != 2 ? ARLEN_OFFSET - C_AXI_SIZE_WIDTH : ARLEN_OFFSET;
localparam ARBURST_OFFSET = C_AXI_TYPE != 2 ? ARSIZE_OFFSET - C_AXI_BURST_WIDTH : ARSIZE_OFFSET;
localparam ARLOCK_OFFSET = C_AXI_TYPE != 2 ? ARBURST_OFFSET - C_AXI_LOCK_WIDTH : ARBURST_OFFSET;
localparam ARCACHE_OFFSET = C_AXI_TYPE != 2 ? ARLOCK_OFFSET - C_AXI_CACHE_WIDTH : ARLOCK_OFFSET;
localparam ARPROT_OFFSET = ARCACHE_OFFSET - C_AXI_PROT_WIDTH;
localparam ARQOS_OFFSET = ARPROT_OFFSET - C_AXI_QOS_WIDTH;
localparam ARREGION_OFFSET = C_AXI_TYPE == 1 ? ARQOS_OFFSET - C_AXI_REGION_WIDTH : ARQOS_OFFSET;
localparam ARUSER_OFFSET = C_HAS_AXI_ARUSER == 1 ? ARREGION_OFFSET-C_AXI_ARUSER_WIDTH : ARREGION_OFFSET;
localparam RID_OFFSET = (C_AXI_TYPE != 2 && C_HAS_AXI_ID == 1) ? C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH : C_DIN_WIDTH_RDCH;
localparam RDATA_OFFSET = RID_OFFSET - C_AXI_DATA_WIDTH;
localparam RRESP_OFFSET = RDATA_OFFSET - C_AXI_RRESP_WIDTH;
localparam RUSER_OFFSET = C_HAS_AXI_RUSER == 1 ? RRESP_OFFSET-C_AXI_RUSER_WIDTH : RRESP_OFFSET;
generate if (IS_RD_ADDR_CH == 1) begin : axi_read_addr_channel
// Write protection when almost full or prog_full is high
assign rach_we = (C_PROG_FULL_TYPE_RACH != 0) ? rach_s_axi_arready & S_AXI_ARVALID : S_AXI_ARVALID;
// Read protection when almost empty or prog_empty is high
// assign rach_rd_en = (C_PROG_EMPTY_TYPE_RACH != 5) ? rach_m_axi_arvalid & M_AXI_ARREADY : M_AXI_ARREADY && arvalid_en;
assign rach_re = (C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH == 1) ?
rach_m_axi_arvalid & arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH != 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY && rach_m_axi_arvalid :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH == 1) ?
arready_pkt & arvalid_en :
(C_PROG_EMPTY_TYPE_RACH == 0 && C_APPLICATION_TYPE_RACH != 1) ?
M_AXI_ARREADY : 1'b0;
assign rach_wr_en = (C_HAS_SLAVE_CE == 1) ? rach_we & S_ACLK_EN : rach_we;
assign rach_rd_en = (C_HAS_MASTER_CE == 1) ? rach_re & M_ACLK_EN : rach_re;
fifo_generator_v13_1_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RACH == 2 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RACH == 1 || C_IMPLEMENTATION_TYPE_RACH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RACH == 11 || C_IMPLEMENTATION_TYPE_RACH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RACH),
.C_WR_DEPTH (C_WR_DEPTH_RACH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_DOUT_WIDTH (C_DIN_WIDTH_RACH),
.C_RD_DEPTH (C_WR_DEPTH_RACH),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RACH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RACH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RACH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RACH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH),
.C_USE_ECC (C_USE_ECC_RACH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RACH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE ((C_APPLICATION_TYPE_RACH == 1)?0:C_APPLICATION_TYPE_RACH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RACH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RACH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_0_rach_dut
(
.CLK (S_ACLK),
.WR_CLK (S_ACLK),
.RD_CLK (M_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rach_wr_en),
.RD_EN (rach_rd_en),
.PROG_FULL_THRESH (AXI_AR_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_AR_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RACH{1'b0}}),
.INJECTDBITERR (AXI_AR_INJECTDBITERR),
.INJECTSBITERR (AXI_AR_INJECTSBITERR),
.DIN (rach_din),
.DOUT (rach_dout_pkt),
.FULL (rach_full),
.EMPTY (rach_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_AR_PROG_FULL),
.PROG_EMPTY (AXI_AR_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_ar_overflow_i),
.VALID (),
.UNDERFLOW (axi_ar_underflow_i),
.DATA_COUNT (AXI_AR_DATA_COUNT),
.RD_DATA_COUNT (AXI_AR_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_AR_WR_DATA_COUNT),
.SBITERR (AXI_AR_SBITERR),
.DBITERR (AXI_AR_DBITERR),
.wr_rst_busy (wr_rst_busy_rach),
.rd_rst_busy (rd_rst_busy_rach),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rach_s_axi_arready = (IS_8SERIES == 0) ? ~rach_full : (C_IMPLEMENTATION_TYPE_RACH == 5 || C_IMPLEMENTATION_TYPE_RACH == 13) ? ~(rach_full | wr_rst_busy_rach) : ~rach_full;
assign rach_m_axi_arvalid = ~rach_empty;
assign S_AXI_ARREADY = rach_s_axi_arready;
assign AXI_AR_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_ar_underflow_i : 0;
assign AXI_AR_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_ar_overflow_i : 0;
end endgenerate // axi_read_addr_channel
// Register Slice for Read Address Channel
generate if (C_RACH_TYPE == 1) begin : grach_reg_slice
fifo_generator_v13_1_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RACH)
)
rach_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rach_din),
.S_VALID (S_AXI_ARVALID),
.S_READY (S_AXI_ARREADY),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice
// Register Slice for Read Address Channel for MM Packet FIFO
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH == 1) begin : grach_reg_slice_mm_pkt_fifo
fifo_generator_v13_1_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RACH),
.C_REG_CONFIG (1)
)
reg_slice_mm_pkt_fifo_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (inverted_reset),
// Slave side
.S_PAYLOAD_DATA (rach_dout_pkt),
.S_VALID (arvalid_pkt),
.S_READY (arready_pkt),
// Master side
.M_PAYLOAD_DATA (rach_dout),
.M_VALID (M_AXI_ARVALID),
.M_READY (M_AXI_ARREADY)
);
end endgenerate // grach_reg_slice_mm_pkt_fifo
generate if (C_RACH_TYPE == 0 && C_APPLICATION_TYPE_RACH != 1) begin : grach_m_axi_arvalid
assign M_AXI_ARVALID = rach_m_axi_arvalid;
assign rach_dout = rach_dout_pkt;
end endgenerate // grach_m_axi_arvalid
generate if (C_APPLICATION_TYPE_RACH == 1 && C_HAS_AXI_RD_CHANNEL == 1) begin : axi_mm_pkt_fifo_rd
assign rdch_rd_ok = rdch_s_axi_rvalid && rdch_rd_en;
assign arvalid_pkt = rach_m_axi_arvalid && arvalid_en;
assign accept_next_pkt = rach_m_axi_arvalid && arready_pkt && arvalid_en;
always@(posedge S_ACLK or posedge inverted_reset) begin
if(inverted_reset) begin
rdch_commited_space <= 0;
end else begin
if(rdch_rd_ok && !accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space-1;
end else if(!rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1);
end else if(rdch_rd_ok && accept_next_pkt) begin
rdch_commited_space <= rdch_commited_space+(rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]);
end
end
end //Always end
always@(*) begin
rdch_free_space <= (C_WR_DEPTH_RDCH-(rdch_commited_space+rach_dout_pkt[ARADDR_OFFSET-1:ARLEN_OFFSET]+1));
end
assign arvalid_en = (rdch_free_space >= 0)?1:0;
end
endgenerate
generate if (C_APPLICATION_TYPE_RACH != 1) begin : axi_mm_fifo_rd
assign arvalid_en = 1;
end
endgenerate
generate if (IS_RD_DATA_CH == 1) begin : axi_read_data_channel
// Write protection when almost full or prog_full is high
assign rdch_we = (C_PROG_FULL_TYPE_RDCH != 0) ? rdch_m_axi_rready & M_AXI_RVALID : M_AXI_RVALID;
// Read protection when almost empty or prog_empty is high
assign rdch_re = (C_PROG_EMPTY_TYPE_RDCH != 0) ? rdch_s_axi_rvalid & S_AXI_RREADY : S_AXI_RREADY;
assign rdch_wr_en = (C_HAS_MASTER_CE == 1) ? rdch_we & M_ACLK_EN : rdch_we;
assign rdch_rd_en = (C_HAS_SLAVE_CE == 1) ? rdch_re & S_ACLK_EN : rdch_re;
fifo_generator_v13_1_0_CONV_VER
#(
.C_FAMILY (C_FAMILY),
.C_COMMON_CLOCK (C_COMMON_CLOCK),
.C_MEMORY_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 11) ? 1 :
(C_IMPLEMENTATION_TYPE_RDCH == 2 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 4),
.C_IMPLEMENTATION_TYPE ((C_IMPLEMENTATION_TYPE_RDCH == 1 || C_IMPLEMENTATION_TYPE_RDCH == 2) ? 0 :
(C_IMPLEMENTATION_TYPE_RDCH == 11 || C_IMPLEMENTATION_TYPE_RDCH == 12) ? 2 : 6),
.C_PRELOAD_REGS (1), // always FWFT for AXI
.C_PRELOAD_LATENCY (0), // always FWFT for AXI
.C_DIN_WIDTH (C_DIN_WIDTH_RDCH),
.C_WR_DEPTH (C_WR_DEPTH_RDCH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_DOUT_WIDTH (C_DIN_WIDTH_RDCH),
.C_RD_DEPTH (C_WR_DEPTH_RDCH),
.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_RD_PNTR_WIDTH (C_WR_PNTR_WIDTH_RDCH),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE_RDCH),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL_RDCH),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE_RDCH),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH),
.C_USE_ECC (C_USE_ECC_RDCH),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE_RDCH),
.C_HAS_ALMOST_EMPTY (0),
.C_HAS_ALMOST_FULL (0),
.C_AXI_TYPE (C_INTERFACE_TYPE == 1 ? 0 : C_AXI_TYPE),
.C_FIFO_TYPE (C_APPLICATION_TYPE_RDCH),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_HAS_WR_RST (0),
.C_HAS_RD_RST (0),
.C_HAS_RST (1),
.C_HAS_SRST (0),
.C_DOUT_RST_VAL (0),
.C_HAS_VALID (0),
.C_VALID_LOW (C_VALID_LOW),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_HAS_WR_ACK (0),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_HAS_DATA_COUNT ((C_COMMON_CLOCK == 1 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_HAS_RD_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_RD_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_USE_FWFT_DATA_COUNT (1), // use extra logic is always true
.C_HAS_WR_DATA_COUNT ((C_COMMON_CLOCK == 0 && C_HAS_DATA_COUNTS_RDCH == 1) ? 1 : 0),
.C_WR_DATA_COUNT_WIDTH (C_WR_PNTR_WIDTH_RDCH + 1),
.C_FULL_FLAGS_RST_VAL (1),
.C_USE_EMBEDDED_REG (0),
.C_USE_DOUT_RST (0),
.C_MSGON_VAL (C_MSGON_VAL),
.C_ENABLE_RST_SYNC (1),
.C_EN_SAFETY_CKT (1),
.C_COUNT_TYPE (C_COUNT_TYPE),
.C_DEFAULT_VALUE (C_DEFAULT_VALUE),
.C_ENABLE_RLOCS (C_ENABLE_RLOCS),
.C_HAS_BACKUP (C_HAS_BACKUP),
.C_HAS_INT_CLK (C_HAS_INT_CLK),
.C_MIF_FILE_NAME (C_MIF_FILE_NAME),
.C_HAS_MEMINIT_FILE (C_HAS_MEMINIT_FILE),
.C_INIT_WR_PNTR_VAL (C_INIT_WR_PNTR_VAL),
.C_OPTIMIZATION_MODE (C_OPTIMIZATION_MODE),
.C_PRIM_FIFO_TYPE (C_PRIM_FIFO_TYPE),
.C_RD_FREQ (C_RD_FREQ),
.C_USE_FIFO16_FLAGS (C_USE_FIFO16_FLAGS),
.C_WR_FREQ (C_WR_FREQ),
.C_WR_RESPONSE_LATENCY (C_WR_RESPONSE_LATENCY)
)
fifo_generator_v13_1_0_rdch_dut
(
.CLK (S_ACLK),
.WR_CLK (M_ACLK),
.RD_CLK (S_ACLK),
.RST (inverted_reset),
.SRST (1'b0),
.WR_RST (inverted_reset),
.RD_RST (inverted_reset),
.WR_EN (rdch_wr_en),
.RD_EN (rdch_rd_en),
.PROG_FULL_THRESH (AXI_R_PROG_FULL_THRESH),
.PROG_FULL_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_FULL_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH (AXI_R_PROG_EMPTY_THRESH),
.PROG_EMPTY_THRESH_ASSERT ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.PROG_EMPTY_THRESH_NEGATE ({C_WR_PNTR_WIDTH_RDCH{1'b0}}),
.INJECTDBITERR (AXI_R_INJECTDBITERR),
.INJECTSBITERR (AXI_R_INJECTSBITERR),
.DIN (rdch_din),
.DOUT (rdch_dout),
.FULL (rdch_full),
.EMPTY (rdch_empty),
.ALMOST_FULL (),
.ALMOST_EMPTY (),
.PROG_FULL (AXI_R_PROG_FULL),
.PROG_EMPTY (AXI_R_PROG_EMPTY),
.WR_ACK (),
.OVERFLOW (axi_r_overflow_i),
.VALID (),
.UNDERFLOW (axi_r_underflow_i),
.DATA_COUNT (AXI_R_DATA_COUNT),
.RD_DATA_COUNT (AXI_R_RD_DATA_COUNT),
.WR_DATA_COUNT (AXI_R_WR_DATA_COUNT),
.SBITERR (AXI_R_SBITERR),
.DBITERR (AXI_R_DBITERR),
.wr_rst_busy (wr_rst_busy_rdch),
.rd_rst_busy (rd_rst_busy_rdch),
.wr_rst_i_out (),
.rd_rst_i_out (),
.BACKUP (BACKUP),
.BACKUP_MARKER (BACKUP_MARKER),
.INT_CLK (INT_CLK)
);
assign rdch_s_axi_rvalid = ~rdch_empty;
assign rdch_m_axi_rready = (IS_8SERIES == 0) ? ~rdch_full : (C_IMPLEMENTATION_TYPE_RDCH == 5 || C_IMPLEMENTATION_TYPE_RDCH == 13) ? ~(rdch_full | wr_rst_busy_rdch) : ~rdch_full;
assign S_AXI_RVALID = rdch_s_axi_rvalid;
assign M_AXI_RREADY = rdch_m_axi_rready;
assign AXI_R_UNDERFLOW = C_USE_COMMON_UNDERFLOW == 0 ? axi_r_underflow_i : 0;
assign AXI_R_OVERFLOW = C_USE_COMMON_OVERFLOW == 0 ? axi_r_overflow_i : 0;
end endgenerate //axi_read_data_channel
// Register Slice for read Data Channel
generate if (C_RDCH_TYPE == 1) begin : grdch_reg_slice
fifo_generator_v13_1_0_axic_reg_slice
#(
.C_FAMILY (C_FAMILY),
.C_DATA_WIDTH (C_DIN_WIDTH_RDCH),
.C_REG_CONFIG (C_REG_SLICE_MODE_RDCH)
)
rdch_reg_slice_inst
(
// System Signals
.ACLK (S_ACLK),
.ARESET (axi_rs_rst),
// Slave side
.S_PAYLOAD_DATA (rdch_din),
.S_VALID (M_AXI_RVALID),
.S_READY (M_AXI_RREADY),
// Master side
.M_PAYLOAD_DATA (rdch_dout),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY)
);
end endgenerate // grdch_reg_slice
assign axi_rd_underflow_i = C_USE_COMMON_UNDERFLOW == 1 ? (axi_ar_underflow_i || axi_r_underflow_i) : 0;
assign axi_rd_overflow_i = C_USE_COMMON_OVERFLOW == 1 ? (axi_ar_overflow_i || axi_r_overflow_i) : 0;
generate if (IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) begin : axi_full_rach_output
assign M_AXI_ARADDR = rach_dout[ARID_OFFSET-1:ARADDR_OFFSET];
assign M_AXI_ARLEN = rach_dout[ARADDR_OFFSET-1:ARLEN_OFFSET];
assign M_AXI_ARSIZE = rach_dout[ARLEN_OFFSET-1:ARSIZE_OFFSET];
assign M_AXI_ARBURST = rach_dout[ARSIZE_OFFSET-1:ARBURST_OFFSET];
assign M_AXI_ARLOCK = rach_dout[ARBURST_OFFSET-1:ARLOCK_OFFSET];
assign M_AXI_ARCACHE = rach_dout[ARLOCK_OFFSET-1:ARCACHE_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARCACHE_OFFSET-1:ARPROT_OFFSET];
assign M_AXI_ARQOS = rach_dout[ARPROT_OFFSET-1:ARQOS_OFFSET];
assign rach_din[ARID_OFFSET-1:ARADDR_OFFSET] = S_AXI_ARADDR;
assign rach_din[ARADDR_OFFSET-1:ARLEN_OFFSET] = S_AXI_ARLEN;
assign rach_din[ARLEN_OFFSET-1:ARSIZE_OFFSET] = S_AXI_ARSIZE;
assign rach_din[ARSIZE_OFFSET-1:ARBURST_OFFSET] = S_AXI_ARBURST;
assign rach_din[ARBURST_OFFSET-1:ARLOCK_OFFSET] = S_AXI_ARLOCK;
assign rach_din[ARLOCK_OFFSET-1:ARCACHE_OFFSET] = S_AXI_ARCACHE;
assign rach_din[ARCACHE_OFFSET-1:ARPROT_OFFSET] = S_AXI_ARPROT;
assign rach_din[ARPROT_OFFSET-1:ARQOS_OFFSET] = S_AXI_ARQOS;
end endgenerate // axi_full_rach_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin : axi_arregion
assign M_AXI_ARREGION = rach_dout[ARQOS_OFFSET-1:ARREGION_OFFSET];
end endgenerate // axi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE != 1) begin : naxi_arregion
assign M_AXI_ARREGION = 0;
end endgenerate // naxi_arregion
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : axi_aruser
assign M_AXI_ARUSER = rach_dout[ARREGION_OFFSET-1:ARUSER_OFFSET];
end endgenerate // axi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 0) begin : naxi_aruser
assign M_AXI_ARUSER = 0;
end endgenerate // naxi_aruser
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_arid
assign M_AXI_ARID = rach_dout[C_DIN_WIDTH_RACH-1:ARID_OFFSET];
end endgenerate // axi_arid
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_arid
assign M_AXI_ARID = 0;
end endgenerate // naxi_arid
generate if (IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) begin : axi_full_rdch_output
assign S_AXI_RDATA = rdch_dout[RID_OFFSET-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
assign S_AXI_RLAST = rdch_dout[0];
assign rdch_din[RID_OFFSET-1:RDATA_OFFSET] = M_AXI_RDATA;
assign rdch_din[RDATA_OFFSET-1:RRESP_OFFSET] = M_AXI_RRESP;
assign rdch_din[0] = M_AXI_RLAST;
end endgenerate // axi_full_rdch_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : axi_full_ruser_output
assign S_AXI_RUSER = rdch_dout[RRESP_OFFSET-1:RUSER_OFFSET];
end endgenerate // axi_full_ruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 0) begin : axi_full_nruser_output
assign S_AXI_RUSER = 0;
end endgenerate // axi_full_nruser_output
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : axi_rid
assign S_AXI_RID = rdch_dout[C_DIN_WIDTH_RDCH-1:RID_OFFSET];
end endgenerate // axi_rid
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 0) begin : naxi_rid
assign S_AXI_RID = 0;
end endgenerate // naxi_rid
generate if (IS_AXI_LITE_RACH == 1 || (IS_AXI_LITE == 1 && C_RACH_TYPE == 1)) begin : axi_lite_rach_output1
assign rach_din = {S_AXI_ARADDR, S_AXI_ARPROT};
assign M_AXI_ARADDR = rach_dout[C_DIN_WIDTH_RACH-1:ARADDR_OFFSET];
assign M_AXI_ARPROT = rach_dout[ARADDR_OFFSET-1:ARPROT_OFFSET];
end endgenerate // axi_lite_rach_output
generate if (IS_AXI_LITE_RDCH == 1 || (IS_AXI_LITE == 1 && C_RDCH_TYPE == 1)) begin : axi_lite_rdch_output1
assign rdch_din = {M_AXI_RDATA, M_AXI_RRESP};
assign S_AXI_RDATA = rdch_dout[C_DIN_WIDTH_RDCH-1:RDATA_OFFSET];
assign S_AXI_RRESP = rdch_dout[RDATA_OFFSET-1:RRESP_OFFSET];
end endgenerate // axi_lite_rdch_output
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ARUSER == 1) begin : grach_din1
assign rach_din[ARREGION_OFFSET-1:ARUSER_OFFSET] = S_AXI_ARUSER;
end endgenerate // grach_din1
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grach_din2
assign rach_din[C_DIN_WIDTH_RACH-1:ARID_OFFSET] = S_AXI_ARID;
end endgenerate // grach_din2
generate if ((IS_AXI_FULL_RACH == 1 || (IS_AXI_FULL == 1 && C_RACH_TYPE == 1)) && C_AXI_TYPE == 1) begin
assign rach_din[ARQOS_OFFSET-1:ARREGION_OFFSET] = S_AXI_ARREGION;
end endgenerate
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_RUSER == 1) begin : grdch_din1
assign rdch_din[RRESP_OFFSET-1:RUSER_OFFSET] = M_AXI_RUSER;
end endgenerate // grdch_din1
generate if ((IS_AXI_FULL_RDCH == 1 || (IS_AXI_FULL == 1 && C_RDCH_TYPE == 1)) && C_HAS_AXI_ID == 1) begin : grdch_din2
assign rdch_din[C_DIN_WIDTH_RDCH-1:RID_OFFSET] = M_AXI_RID;
end endgenerate // grdch_din2
//end of axi_read_channel
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_UNDERFLOW == 1) begin : gaxi_comm_uf
assign UNDERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_underflow_i || axi_rd_underflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_underflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_underflow_i : 0;
end endgenerate // gaxi_comm_uf
generate if (C_INTERFACE_TYPE == 1 && C_USE_COMMON_OVERFLOW == 1) begin : gaxi_comm_of
assign OVERFLOW = (C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 1) ? (axi_wr_overflow_i || axi_rd_overflow_i) :
(C_HAS_AXI_WR_CHANNEL == 1 && C_HAS_AXI_RD_CHANNEL == 0) ? axi_wr_overflow_i :
(C_HAS_AXI_WR_CHANNEL == 0 && C_HAS_AXI_RD_CHANNEL == 1) ? axi_rd_overflow_i : 0;
end endgenerate // gaxi_comm_of
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic or Wiring Logic
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Write Address Channel
generate if (C_WACH_TYPE == 2) begin : gwach_pass_through
assign M_AXI_AWID = S_AXI_AWID;
assign M_AXI_AWADDR = S_AXI_AWADDR;
assign M_AXI_AWLEN = S_AXI_AWLEN;
assign M_AXI_AWSIZE = S_AXI_AWSIZE;
assign M_AXI_AWBURST = S_AXI_AWBURST;
assign M_AXI_AWLOCK = S_AXI_AWLOCK;
assign M_AXI_AWCACHE = S_AXI_AWCACHE;
assign M_AXI_AWPROT = S_AXI_AWPROT;
assign M_AXI_AWQOS = S_AXI_AWQOS;
assign M_AXI_AWREGION = S_AXI_AWREGION;
assign M_AXI_AWUSER = S_AXI_AWUSER;
assign S_AXI_AWREADY = M_AXI_AWREADY;
assign M_AXI_AWVALID = S_AXI_AWVALID;
end endgenerate // gwach_pass_through;
// Wiring logic for Write Data Channel
generate if (C_WDCH_TYPE == 2) begin : gwdch_pass_through
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
assign S_AXI_WREADY = M_AXI_WREADY;
assign M_AXI_WVALID = S_AXI_WVALID;
end endgenerate // gwdch_pass_through;
// Wiring logic for Write Response Channel
generate if (C_WRCH_TYPE == 2) begin : gwrch_pass_through
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign M_AXI_BREADY = S_AXI_BREADY;
assign S_AXI_BVALID = M_AXI_BVALID;
end endgenerate // gwrch_pass_through;
//-------------------------------------------------------------------------
// Pass Through Logic for Read Channel
//-------------------------------------------------------------------------
// Wiring logic for Read Address Channel
generate if (C_RACH_TYPE == 2) begin : grach_pass_through
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARREGION = S_AXI_ARREGION;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign S_AXI_ARREADY = M_AXI_ARREADY;
assign M_AXI_ARVALID = S_AXI_ARVALID;
end endgenerate // grach_pass_through;
// Wiring logic for Read Data Channel
generate if (C_RDCH_TYPE == 2) begin : grdch_pass_through
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end endgenerate // grdch_pass_through;
// Wiring logic for AXI Streaming
generate if (C_AXIS_TYPE == 2) begin : gaxis_pass_through
assign M_AXIS_TDATA = S_AXIS_TDATA;
assign M_AXIS_TSTRB = S_AXIS_TSTRB;
assign M_AXIS_TKEEP = S_AXIS_TKEEP;
assign M_AXIS_TID = S_AXIS_TID;
assign M_AXIS_TDEST = S_AXIS_TDEST;
assign M_AXIS_TUSER = S_AXIS_TUSER;
assign M_AXIS_TLAST = S_AXIS_TLAST;
assign S_AXIS_TREADY = M_AXIS_TREADY;
assign M_AXIS_TVALID = S_AXIS_TVALID;
end endgenerate // gaxis_pass_through;
endmodule //fifo_generator_v13_1_0
/*******************************************************************************
* Declaration of top-level module for Conventional FIFO
******************************************************************************/
module fifo_generator_v13_1_0_CONV_VER
#(
parameter C_COMMON_CLOCK = 0,
parameter C_INTERFACE_TYPE = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_TYPE = 0,
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DEFAULT_VALUE = "",
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_ENABLE_RLOCS = 0,
parameter C_FAMILY = "virtex7", //Not allowed in Verilog model
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_BACKUP = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_INT_CLK = 0,
parameter C_HAS_MEMINIT_FILE = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RD_RST = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_HAS_WR_RST = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_INIT_WR_PNTR_VAL = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_MIF_FILE_NAME = "",
parameter C_OPTIMIZATION_MODE = 0,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PRIM_FIFO_TYPE = "",
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_FREQ = 1,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_USE_FIFO16_FLAGS = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_FREQ = 1,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_WR_RESPONSE_LATENCY = 1,
parameter C_MSGON_VAL = 1,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2,
parameter C_AXI_TYPE = 0
)
(
input BACKUP,
input BACKUP_MARKER,
input CLK,
input RST,
input SRST,
input WR_CLK,
input WR_RST,
input RD_CLK,
input RD_RST,
input [C_DIN_WIDTH-1:0] DIN,
input WR_EN,
input RD_EN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input INT_CLK,
input INJECTDBITERR,
input INJECTSBITERR,
output [C_DOUT_WIDTH-1:0] DOUT,
output FULL,
output ALMOST_FULL,
output WR_ACK,
output OVERFLOW,
output EMPTY,
output ALMOST_EMPTY,
output VALID,
output UNDERFLOW,
output [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_FULL,
output PROG_EMPTY,
output SBITERR,
output DBITERR,
output wr_rst_busy,
output rd_rst_busy,
output wr_rst_i_out,
output rd_rst_i_out
);
/*
******************************************************************************
* Definition of Parameters
******************************************************************************
* C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0)
* C_COUNT_TYPE : *not used
* C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus
* C_DEFAULT_VALUE : *not used
* C_DIN_WIDTH : Width of DIN bus
* C_DOUT_RST_VAL : Reset value of DOUT
* C_DOUT_WIDTH : Width of DOUT bus
* C_ENABLE_RLOCS : *not used
* C_FAMILY : not used in bhv model
* C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1)
* C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag
* C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag
* C_HAS_BACKUP : *not used
* C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus
* C_HAS_INT_CLK : not used in bhv model
* C_HAS_MEMINIT_FILE : *not used
* C_HAS_OVERFLOW : 1=Core has OVERFLOW flag
* C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus
* C_HAS_RD_RST : *not used
* C_HAS_RST : 1=Core has Async Rst
* C_HAS_SRST : 1=Core has Sync Rst
* C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag
* C_HAS_VALID : 1=Core has VALID flag
* C_HAS_WR_ACK : 1=Core has WR_ACK flag
* C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus
* C_HAS_WR_RST : *not used
* C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram
* 1=Common-Clock ShiftRam
* 2=Indep. Clocks Bram/Dram
* 3=Virtex-4 Built-in
* 4=Virtex-5 Built-in
* C_INIT_WR_PNTR_VAL : *not used
* C_MEMORY_TYPE : 1=Block RAM
* 2=Distributed RAM
* 3=Shift RAM
* 4=Built-in FIFO
* C_MIF_FILE_NAME : *not used
* C_OPTIMIZATION_MODE : *not used
* C_OVERFLOW_LOW : 1=OVERFLOW active low
* C_PRELOAD_LATENCY : Latency of read: 0, 1, 2
* C_PRELOAD_REGS : 1=Use output registers
* C_PRIM_FIFO_TYPE : not used in bhv model
* C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold
* C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold
* C_PROG_EMPTY_TYPE : 0=No programmable empty
* 1=Single prog empty thresh constant
* 2=Multiple prog empty thresh constants
* 3=Single prog empty thresh input
* 4=Multiple prog empty thresh inputs
* C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold
* C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold
* C_PROG_FULL_TYPE : 0=No prog full
* 1=Single prog full thresh constant
* 2=Multiple prog full thresh constants
* 3=Single prog full thresh input
* 4=Multiple prog full thresh inputs
* C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus
* C_RD_DEPTH : Depth of read interface (2^N)
* C_RD_FREQ : not used in bhv model
* C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH)
* C_UNDERFLOW_LOW : 1=UNDERFLOW active low
* C_USE_DOUT_RST : 1=Resets DOUT on RST
* C_USE_ECC : Used for error injection purpose
* C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register
* C_USE_FIFO16_FLAGS : not used in bhv model
* C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count
* C_VALID_LOW : 1=VALID active low
* C_WR_ACK_LOW : 1=WR_ACK active low
* C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus
* C_WR_DEPTH : Depth of write interface (2^N)
* C_WR_FREQ : not used in bhv model
* C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH)
* C_WR_RESPONSE_LATENCY : *not used
* C_MSGON_VAL : *not used by bhv model
* C_ENABLE_RST_SYNC : 0 = Use WR_RST & RD_RST
* 1 = Use RST
* C_ERROR_INJECTION_TYPE : 0 = No error injection
* 1 = Single bit error injection only
* 2 = Double bit error injection only
* 3 = Single and double bit error injection
******************************************************************************
* Definition of Ports
******************************************************************************
* BACKUP : Not used
* BACKUP_MARKER: Not used
* CLK : Clock
* DIN : Input data bus
* PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag
* PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag
* PROG_FULL_THRESH : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag
* PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag
* RD_CLK : Read Domain Clock
* RD_EN : Read enable
* RD_RST : Read Reset
* RST : Asynchronous Reset
* SRST : Synchronous Reset
* WR_CLK : Write Domain Clock
* WR_EN : Write enable
* WR_RST : Write Reset
* INT_CLK : Internal Clock
* INJECTSBITERR: Inject Signle bit error
* INJECTDBITERR: Inject Double bit error
* ALMOST_EMPTY : One word remaining in FIFO
* ALMOST_FULL : One empty space remaining in FIFO
* DATA_COUNT : Number of data words in fifo( synchronous to CLK)
* DOUT : Output data bus
* EMPTY : Empty flag
* FULL : Full flag
* OVERFLOW : Last write rejected
* PROG_EMPTY : Programmable Empty Flag
* PROG_FULL : Programmable Full Flag
* RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK)
* UNDERFLOW : Last read rejected
* VALID : Last read acknowledged, DOUT bus VALID
* WR_ACK : Last write acknowledged
* WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK)
* SBITERR : Single Bit ECC Error Detected
* DBITERR : Double Bit ECC Error Detected
******************************************************************************
*/
//----------------------------------------------------------------------------
//- Internal Signals for delayed input signals
//- All the input signals except Clock are delayed by 100 ps and then given to
//- the models.
//----------------------------------------------------------------------------
reg rst_delayed ;
reg empty_fb ;
reg srst_delayed ;
reg wr_rst_delayed ;
reg rd_rst_delayed ;
reg wr_en_delayed ;
reg rd_en_delayed ;
reg [C_DIN_WIDTH-1:0] din_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_assert_delayed ;
reg [C_RD_PNTR_WIDTH-1:0] prog_empty_thresh_negate_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_assert_delayed ;
reg [C_WR_PNTR_WIDTH-1:0] prog_full_thresh_negate_delayed ;
reg injectdbiterr_delayed ;
reg injectsbiterr_delayed ;
wire empty_p0_out;
always @* rst_delayed <= #`TCQ RST ;
always @* empty_fb <= #`TCQ empty_p0_out ;
always @* srst_delayed <= #`TCQ SRST ;
always @* wr_rst_delayed <= #`TCQ WR_RST ;
always @* rd_rst_delayed <= #`TCQ RD_RST ;
always @* din_delayed <= #`TCQ DIN ;
always @* wr_en_delayed <= #`TCQ WR_EN ;
always @* rd_en_delayed <= #`TCQ RD_EN ;
always @* prog_empty_thresh_delayed <= #`TCQ PROG_EMPTY_THRESH ;
always @* prog_empty_thresh_assert_delayed <= #`TCQ PROG_EMPTY_THRESH_ASSERT ;
always @* prog_empty_thresh_negate_delayed <= #`TCQ PROG_EMPTY_THRESH_NEGATE ;
always @* prog_full_thresh_delayed <= #`TCQ PROG_FULL_THRESH ;
always @* prog_full_thresh_assert_delayed <= #`TCQ PROG_FULL_THRESH_ASSERT ;
always @* prog_full_thresh_negate_delayed <= #`TCQ PROG_FULL_THRESH_NEGATE ;
always @* injectdbiterr_delayed <= #`TCQ INJECTDBITERR ;
always @* injectsbiterr_delayed <= #`TCQ INJECTSBITERR ;
/*****************************************************************************
* Derived parameters
****************************************************************************/
//There are 2 Verilog behavioral models
// 0 = Common-Clock FIFO/ShiftRam FIFO
// 1 = Independent Clocks FIFO
// 2 = Low Latency Synchronous FIFO
// 3 = Low Latency Asynchronous FIFO
localparam C_VERILOG_IMPL = (C_FIFO_TYPE == 3) ? 2 :
(C_IMPLEMENTATION_TYPE == 2) ? 1 : 0;
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//Internal reset signals
reg rd_rst_asreg = 0;
reg rd_rst_asreg_d1 = 0;
reg rd_rst_asreg_d2 = 0;
reg rd_rst_asreg_d3 = 0;
reg rd_rst_reg = 0;
wire rd_rst_comb;
reg wr_rst_d0 = 0;
reg wr_rst_d1 = 0;
reg wr_rst_d2 = 0;
reg rd_rst_d0 = 0;
reg rd_rst_d1 = 0;
reg rd_rst_d2 = 0;
reg rd_rst_d3 = 0;
reg wrrst_done = 0;
reg rdrst_done = 0;
reg wr_rst_asreg = 0;
reg wr_rst_asreg_d1 = 0;
reg wr_rst_asreg_d2 = 0;
reg wr_rst_asreg_d3 = 0;
reg rd_rst_wr_d0 = 0;
reg rd_rst_wr_d1 = 0;
reg rd_rst_wr_d2 = 0;
reg wr_rst_reg = 0;
reg rst_active_i = 1'b1;
reg rst_delayed_d1 = 1'b1;
reg rst_delayed_d2 = 1'b1;
wire wr_rst_comb;
wire wr_rst_i;
wire rd_rst_i;
wire rst_i;
//Internal reset signals
reg rst_asreg = 0;
reg srst_asreg = 0;
reg rst_asreg_d1 = 0;
reg rst_asreg_d2 = 0;
reg srst_asreg_d1 = 0;
reg srst_asreg_d2 = 0;
reg rst_reg = 0;
reg srst_reg = 0;
wire rst_comb;
wire srst_comb;
reg rst_full_gen_i = 0;
reg rst_full_ff_i = 0;
wire RD_CLK_P0_IN;
wire RST_P0_IN;
wire RD_EN_FIFO_IN;
wire RD_EN_P0_IN;
wire ALMOST_EMPTY_FIFO_OUT;
wire ALMOST_FULL_FIFO_OUT;
wire [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT_FIFO_OUT;
wire [C_DOUT_WIDTH-1:0] DOUT_FIFO_OUT;
wire EMPTY_FIFO_OUT;
wire FULL_FIFO_OUT;
wire OVERFLOW_FIFO_OUT;
wire PROG_EMPTY_FIFO_OUT;
wire PROG_FULL_FIFO_OUT;
wire VALID_FIFO_OUT;
wire [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT_FIFO_OUT;
wire UNDERFLOW_FIFO_OUT;
wire WR_ACK_FIFO_OUT;
wire [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT_FIFO_OUT;
//***************************************************************************
// Internal Signals
// The core uses either the internal_ wires or the preload0_ wires depending
// on whether the core uses Preload0 or not.
// When using preload0, the internal signals connect the internal core to
// the preload logic, and the external core's interfaces are tied to the
// preload0 signals from the preload logic.
//***************************************************************************
wire [C_DOUT_WIDTH-1:0] DATA_P0_OUT;
wire VALID_P0_OUT;
wire EMPTY_P0_OUT;
wire ALMOSTEMPTY_P0_OUT;
reg EMPTY_P0_OUT_Q;
reg ALMOSTEMPTY_P0_OUT_Q;
wire UNDERFLOW_P0_OUT;
wire RDEN_P0_OUT;
wire [C_DOUT_WIDTH-1:0] DATA_P0_IN;
wire EMPTY_P0_IN;
reg [31:0] DATA_COUNT_FWFT;
reg SS_FWFT_WR ;
reg SS_FWFT_RD ;
wire sbiterr_fifo_out;
wire dbiterr_fifo_out;
wire inject_sbit_err;
wire inject_dbit_err;
wire w_fab_read_data_valid_i;
wire w_read_data_valid_i;
wire w_ram_valid_i;
// Assign 0 if not selected to avoid 'X' propogation to S/DBITERR.
assign inject_sbit_err = ((C_ERROR_INJECTION_TYPE == 1) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectsbiterr_delayed : 0;
assign inject_dbit_err = ((C_ERROR_INJECTION_TYPE == 2) || (C_ERROR_INJECTION_TYPE == 3)) ?
injectdbiterr_delayed : 0;
assign wr_rst_i_out = wr_rst_i;
assign rd_rst_i_out = rd_rst_i;
// Choose the behavioral model to instantiate based on the C_VERILOG_IMPL
// parameter (1=Independent Clocks, 0=Common Clock)
localparam FULL_FLAGS_RST_VAL = (C_HAS_SRST == 1) ? 0 : C_FULL_FLAGS_RST_VAL;
generate
case (C_VERILOG_IMPL)
0 : begin : block1
//Common Clock Behavioral Model
fifo_generator_v13_1_0_bhv_ver_ss
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL ((C_AXI_TYPE == 0 && C_FIFO_TYPE == 1) ? 1 : C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ss
(
.CLK (CLK),
.RST (rst_i),
.SRST (srst_delayed),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.USER_EMPTY_FB (empty_fb),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.DATA_COUNT (DATA_COUNT_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
1 : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_0_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.fab_read_data_valid_i (w_fab_read_data_valid_i),
.read_data_valid_i (w_read_data_valid_i),
.ram_valid_i (w_ram_valid_i),
.DBITERR (dbiterr_fifo_out)
);
end
2 : begin : ll_afifo_inst
fifo_generator_v13_1_0_beh_ver_ll_afifo
#(
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
gen_ll_afifo
(
.DIN (din_delayed),
.RD_CLK (RD_CLK),
.RD_EN (rd_en_delayed),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.WR_CLK (WR_CLK),
.WR_EN (wr_en_delayed),
.DOUT (DOUT),
.EMPTY (EMPTY),
.FULL (FULL)
);
end
default : begin : block1
//Independent Clocks Behavioral Model
fifo_generator_v13_1_0_bhv_ver_as
#(
.C_FAMILY (C_FAMILY),
.C_DATA_COUNT_WIDTH (C_DATA_COUNT_WIDTH),
.C_DIN_WIDTH (C_DIN_WIDTH),
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_FULL_FLAGS_RST_VAL (C_FULL_FLAGS_RST_VAL),
.C_HAS_ALMOST_EMPTY (C_HAS_ALMOST_EMPTY),
.C_HAS_ALMOST_FULL (C_HAS_ALMOST_FULL),
.C_HAS_DATA_COUNT (C_HAS_DATA_COUNT),
.C_HAS_OVERFLOW (C_HAS_OVERFLOW),
.C_HAS_RD_DATA_COUNT (C_HAS_RD_DATA_COUNT),
.C_HAS_RST (C_HAS_RST),
.C_HAS_UNDERFLOW (C_HAS_UNDERFLOW),
.C_HAS_VALID (C_HAS_VALID),
.C_HAS_WR_ACK (C_HAS_WR_ACK),
.C_HAS_WR_DATA_COUNT (C_HAS_WR_DATA_COUNT),
.C_IMPLEMENTATION_TYPE (C_IMPLEMENTATION_TYPE),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_OVERFLOW_LOW (C_OVERFLOW_LOW),
.C_PRELOAD_LATENCY (C_PRELOAD_LATENCY),
.C_PRELOAD_REGS (C_PRELOAD_REGS),
.C_PROG_EMPTY_THRESH_ASSERT_VAL (C_PROG_EMPTY_THRESH_ASSERT_VAL),
.C_PROG_EMPTY_THRESH_NEGATE_VAL (C_PROG_EMPTY_THRESH_NEGATE_VAL),
.C_PROG_EMPTY_TYPE (C_PROG_EMPTY_TYPE),
.C_PROG_FULL_THRESH_ASSERT_VAL (C_PROG_FULL_THRESH_ASSERT_VAL),
.C_PROG_FULL_THRESH_NEGATE_VAL (C_PROG_FULL_THRESH_NEGATE_VAL),
.C_PROG_FULL_TYPE (C_PROG_FULL_TYPE),
.C_RD_DATA_COUNT_WIDTH (C_RD_DATA_COUNT_WIDTH),
.C_RD_DEPTH (C_RD_DEPTH),
.C_RD_PNTR_WIDTH (C_RD_PNTR_WIDTH),
.C_UNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USE_FWFT_DATA_COUNT (C_USE_FWFT_DATA_COUNT),
.C_VALID_LOW (C_VALID_LOW),
.C_WR_ACK_LOW (C_WR_ACK_LOW),
.C_WR_DATA_COUNT_WIDTH (C_WR_DATA_COUNT_WIDTH),
.C_WR_DEPTH (C_WR_DEPTH),
.C_WR_PNTR_WIDTH (C_WR_PNTR_WIDTH),
.C_USE_ECC (C_USE_ECC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_ERROR_INJECTION_TYPE (C_ERROR_INJECTION_TYPE)
)
gen_as
(
.WR_CLK (WR_CLK),
.RD_CLK (RD_CLK),
.RST (rst_i),
.RST_FULL_GEN (rst_full_gen_i),
.RST_FULL_FF (rst_full_ff_i),
.WR_RST (wr_rst_i),
.RD_RST (rd_rst_i),
.DIN (din_delayed),
.WR_EN (wr_en_delayed),
.RD_EN (RD_EN_FIFO_IN),
.RD_EN_USER (rd_en_delayed),
.PROG_EMPTY_THRESH (prog_empty_thresh_delayed),
.PROG_EMPTY_THRESH_ASSERT (prog_empty_thresh_assert_delayed),
.PROG_EMPTY_THRESH_NEGATE (prog_empty_thresh_negate_delayed),
.PROG_FULL_THRESH (prog_full_thresh_delayed),
.PROG_FULL_THRESH_ASSERT (prog_full_thresh_assert_delayed),
.PROG_FULL_THRESH_NEGATE (prog_full_thresh_negate_delayed),
.INJECTSBITERR (inject_sbit_err),
.INJECTDBITERR (inject_dbit_err),
.USER_EMPTY_FB (EMPTY_P0_OUT),
.DOUT (DOUT_FIFO_OUT),
.FULL (FULL_FIFO_OUT),
.ALMOST_FULL (ALMOST_FULL_FIFO_OUT),
.WR_ACK (WR_ACK_FIFO_OUT),
.OVERFLOW (OVERFLOW_FIFO_OUT),
.EMPTY (EMPTY_FIFO_OUT),
.ALMOST_EMPTY (ALMOST_EMPTY_FIFO_OUT),
.VALID (VALID_FIFO_OUT),
.UNDERFLOW (UNDERFLOW_FIFO_OUT),
.RD_DATA_COUNT (RD_DATA_COUNT_FIFO_OUT),
.WR_DATA_COUNT (WR_DATA_COUNT_FIFO_OUT),
.PROG_FULL (PROG_FULL_FIFO_OUT),
.PROG_EMPTY (PROG_EMPTY_FIFO_OUT),
.SBITERR (sbiterr_fifo_out),
.DBITERR (dbiterr_fifo_out)
);
end
endcase
endgenerate
//**************************************************************************
// Connect Internal Signals
// (Signals labeled internal_*)
// In the normal case, these signals tie directly to the FIFO's inputs and
// outputs.
// In the case of Preload Latency 0 or 1, there are intermediate
// signals between the internal FIFO and the preload logic.
//**************************************************************************
//***********************************************
// If First-Word Fall-Through, instantiate
// the preload0 (FWFT) module
//***********************************************
wire rd_en_to_fwft_fifo;
wire sbiterr_fwft;
wire dbiterr_fwft;
wire [C_DOUT_WIDTH-1:0] dout_fwft;
wire empty_fwft;
wire rd_en_fifo_in;
wire stage2_reg_en_i;
wire [1:0] valid_stages_i;
wire rst_fwft;
//wire empty_p0_out;
reg [C_SYNCHRONIZER_STAGE-1:0] pkt_empty_sync = 'b1;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
localparam IS_PKT_FIFO = (C_FIFO_TYPE == 1) ? 1 : 0;
localparam IS_AXIS_PKT_FIFO = (C_FIFO_TYPE == 1 && C_AXI_TYPE == 0) ? 1 : 0;
assign rst_fwft = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 1'b0;
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 3) begin : block2
fifo_generator_v13_1_0_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_EMBEDDED_REG (C_USE_EMBEDDED_REG),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (C_FIFO_TYPE)
)
fgpl0
(
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (RST_P0_IN),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (RD_EN_P0_IN),
.FIFOEMPTY (EMPTY_P0_IN),
.FIFODATA (DATA_P0_IN),
.FIFOSBITERR (sbiterr_fifo_out),
.FIFODBITERR (dbiterr_fifo_out),
// Output
.USERDATA (dout_fwft),
.USERVALID (VALID_P0_OUT),
.USEREMPTY (empty_fwft),
.USERALMOSTEMPTY (ALMOSTEMPTY_P0_OUT),
.USERUNDERFLOW (UNDERFLOW_P0_OUT),
.RAMVALID (),
.FIFORDEN (rd_en_fifo_in),
.USERSBITERR (sbiterr_fwft),
.USERDBITERR (dbiterr_fwft),
.STAGE2_REG_EN (stage2_reg_en_i),
.fab_read_data_valid_i_o (w_fab_read_data_valid_i),
.read_data_valid_i_o (w_read_data_valid_i),
.ram_valid_i_o (w_ram_valid_i),
.VALID_STAGES (valid_stages_i)
);
//***********************************************
// Connect inputs to preload (FWFT) module
//***********************************************
//Connect the RD_CLK of the Preload (FWFT) module to CLK if we
// have a common-clock FIFO, or RD_CLK if we have an
// independent clock FIFO
assign RD_CLK_P0_IN = ((C_VERILOG_IMPL == 0) ? CLK : RD_CLK);
assign RST_P0_IN = (C_COMMON_CLOCK == 0) ? rd_rst_i : (C_HAS_RST == 1) ? rst_i : 0;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
assign EMPTY_P0_IN = EMPTY_FIFO_OUT;
assign DATA_P0_IN = DOUT_FIFO_OUT;
//***********************************************
// Connect outputs from preload (FWFT) module
//***********************************************
assign VALID = VALID_P0_OUT ;
assign ALMOST_EMPTY = ALMOSTEMPTY_P0_OUT;
assign UNDERFLOW = UNDERFLOW_P0_OUT ;
assign RD_EN_FIFO_IN = rd_en_fifo_in;
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
assign DATA_COUNT = (C_USE_FWFT_DATA_COUNT == 0)? DATA_COUNT_FIFO_OUT:
(C_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) ? DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:0] :
DATA_COUNT_FWFT[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1];
//***********************************************
// Create DATA_COUNT from First-Word Fall-Through
// data count
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
EMPTY_P0_OUT_Q <= #`TCQ 1;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ 1;
end else begin
EMPTY_P0_OUT_Q <= #`TCQ empty_p0_out;
// EMPTY_P0_OUT_Q <= #`TCQ EMPTY_FIFO_OUT;
ALMOSTEMPTY_P0_OUT_Q <= #`TCQ ALMOSTEMPTY_P0_OUT;
end
end //always
//***********************************************
// logic for common-clock data count when FWFT is selected
//***********************************************
initial begin
SS_FWFT_RD = 1'b0;
DATA_COUNT_FWFT = 0 ;
SS_FWFT_WR = 1'b0 ;
end //initial
//***********************************************
// common-clock data count is implemented as an
// up-down counter. SS_FWFT_WR and SS_FWFT_RD
// are the up/down enables for the counter.
//***********************************************
always @ (RD_EN or VALID_P0_OUT or WR_EN or FULL_FIFO_OUT or empty_p0_out) begin
if (C_VALID_LOW == 1) begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && ~VALID_P0_OUT) : (~empty_p0_out && RD_EN && ~VALID_P0_OUT) ;
end else begin
SS_FWFT_RD = (C_FIFO_TYPE != 1) ? (RD_EN && VALID_P0_OUT) : (~empty_p0_out && RD_EN && VALID_P0_OUT) ;
end
SS_FWFT_WR = (WR_EN && (~FULL_FIFO_OUT)) ;
end
//***********************************************
// common-clock data count is implemented as an
// up-down counter for FWFT. This always block
// calculates the counter.
//***********************************************
always @ (posedge RD_CLK_P0_IN or posedge RST_P0_IN) begin
if (RST_P0_IN) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
//if (srst_delayed && (C_HAS_SRST == 1) ) begin
if ((srst_delayed | wr_rst_busy | rd_rst_busy) && (C_HAS_SRST == 1) ) begin
DATA_COUNT_FWFT <= #`TCQ 0;
end else begin
case ( {SS_FWFT_WR, SS_FWFT_RD})
2'b00: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
2'b01: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT - 1 ;
2'b10: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT + 1 ;
2'b11: DATA_COUNT_FWFT <= #`TCQ DATA_COUNT_FWFT ;
endcase
end //if SRST
end //IF RST
end //always
end endgenerate // : block2
// AXI Streaming Packet FIFO
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_plus1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pkt_count_reg = 0;
reg partial_packet = 0;
reg stage1_eop_d1 = 0;
reg rd_en_fifo_in_d1 = 0;
reg eop_at_stage2 = 0;
reg ram_pkt_empty = 0;
reg ram_pkt_empty_d1 = 0;
wire [C_DOUT_WIDTH-1:0] dout_p0_out;
wire packet_empty_wr;
wire wr_rst_fwft_pkt_fifo;
wire dummy_wr_eop;
wire ram_wr_en_pkt_fifo;
wire wr_eop;
wire ram_rd_en_compare;
wire stage1_eop;
wire pkt_ready_to_read;
wire rd_en_2_stage2;
// Generate Dummy WR_EOP for partial packet (Only for AXI Streaming)
// When Packet EMPTY is high, and FIFO is full, then generate the dummy WR_EOP
// When dummy WR_EOP is high, mask the actual EOP to avoid double increment of
// write packet count
generate if (IS_FWFT == 1 && IS_AXIS_PKT_FIFO == 1) begin // gdummy_wr_eop
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
partial_packet <= 1'b0;
else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy)
partial_packet <= #`TCQ 1'b0;
else if (ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]))
partial_packet <= #`TCQ 1'b1;
else if (partial_packet && din_delayed[0] && ram_wr_en_pkt_fifo)
partial_packet <= #`TCQ 1'b0;
end
end
end endgenerate // gdummy_wr_eop
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1) begin // gpkt_fifo_fwft
assign wr_rst_fwft_pkt_fifo = (C_COMMON_CLOCK == 0) ? wr_rst_i : (C_HAS_RST == 1) ? rst_i:1'b0;
assign dummy_wr_eop = ALMOST_FULL_FIFO_OUT && ram_wr_en_pkt_fifo && packet_empty_wr && (~din_delayed[0]) && (~partial_packet);
assign packet_empty_wr = (C_COMMON_CLOCK == 1) ? empty_p0_out : pkt_empty_sync[C_SYNCHRONIZER_STAGE-1];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
stage1_eop_d1 <= 1'b0;
rd_en_fifo_in_d1 <= 1'b0;
end else begin
if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
stage1_eop_d1 <= #`TCQ 1'b0;
rd_en_fifo_in_d1 <= #`TCQ 1'b0;
end else begin
stage1_eop_d1 <= #`TCQ stage1_eop;
rd_en_fifo_in_d1 <= #`TCQ rd_en_fifo_in;
end
end
end
assign stage1_eop = (rd_en_fifo_in_d1) ? DOUT_FIFO_OUT[0] : stage1_eop_d1;
assign ram_wr_en_pkt_fifo = wr_en_delayed && (~FULL_FIFO_OUT);
assign wr_eop = ram_wr_en_pkt_fifo && ((din_delayed[0] && (~partial_packet)) || dummy_wr_eop);
assign ram_rd_en_compare = stage2_reg_en_i && stage1_eop;
fifo_generator_v13_1_0_bhv_ver_preload0
#(
.C_DOUT_RST_VAL (C_DOUT_RST_VAL),
.C_DOUT_WIDTH (C_DOUT_WIDTH),
.C_HAS_RST (C_HAS_RST),
.C_HAS_SRST (C_HAS_SRST),
.C_USE_DOUT_RST (C_USE_DOUT_RST),
.C_USE_ECC (C_USE_ECC),
.C_USERVALID_LOW (C_VALID_LOW),
.C_EN_SAFETY_CKT (C_EN_SAFETY_CKT),
.C_USERUNDERFLOW_LOW (C_UNDERFLOW_LOW),
.C_ENABLE_RST_SYNC (C_ENABLE_RST_SYNC),
.C_MEMORY_TYPE (C_MEMORY_TYPE),
.C_FIFO_TYPE (2) // Enable low latency fwft logic
)
pkt_fifo_fwft
(
.RD_CLK (RD_CLK_P0_IN),
.RD_RST (rst_fwft),
.SRST (srst_delayed),
.WR_RST_BUSY (wr_rst_busy),
.RD_RST_BUSY (rd_rst_busy),
.RD_EN (rd_en_delayed),
.FIFOEMPTY (pkt_ready_to_read),
.FIFODATA (dout_fwft),
.FIFOSBITERR (sbiterr_fwft),
.FIFODBITERR (dbiterr_fwft),
// Output
.USERDATA (dout_p0_out),
.USERVALID (),
.USEREMPTY (empty_p0_out),
.USERALMOSTEMPTY (),
.USERUNDERFLOW (),
.RAMVALID (),
.FIFORDEN (rd_en_2_stage2),
.USERSBITERR (SBITERR),
.USERDBITERR (DBITERR),
.STAGE2_REG_EN (),
.VALID_STAGES ()
);
assign pkt_ready_to_read = ~(!(ram_pkt_empty || empty_fwft) && ((valid_stages_i[0] && valid_stages_i[1]) || eop_at_stage2));
assign rd_en_to_fwft_fifo = ~empty_fwft && rd_en_2_stage2;
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
eop_at_stage2 <= 1'b0;
else if (stage2_reg_en_i)
eop_at_stage2 <= #`TCQ stage1_eop;
end
//---------------------------------------------------------------------------
// Write and Read Packet Count
//---------------------------------------------------------------------------
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count <= 0;
else if (srst_delayed | wr_rst_busy | rd_rst_busy)
wr_pkt_count <= #`TCQ 0;
else if (wr_eop)
wr_pkt_count <= #`TCQ wr_pkt_count + 1;
end
end endgenerate // gpkt_fifo_fwft
assign DOUT = (C_FIFO_TYPE != 1) ? dout_fwft : dout_p0_out;
assign EMPTY = (C_FIFO_TYPE != 1) ? empty_fwft : empty_p0_out;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 1) begin // grss_pkt_cnt
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
rd_pkt_count <= 0;
rd_pkt_count_plus1 <= 1;
end else if (srst_delayed | wr_rst_busy | rd_rst_busy) begin
rd_pkt_count <= #`TCQ 0;
rd_pkt_count_plus1 <= #`TCQ 1;
end else if (stage2_reg_en_i && stage1_eop) begin
rd_pkt_count <= #`TCQ rd_pkt_count + 1;
rd_pkt_count_plus1 <= #`TCQ rd_pkt_count_plus1 + 1;
end
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (SRST | wr_rst_busy | rd_rst_busy) begin
ram_pkt_empty <= #`TCQ 1'b1;
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count) && wr_eop) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count_plus1 == wr_pkt_count) && ~wr_eop && ~ALMOST_FULL_FIFO_OUT && ram_rd_en_compare) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
end endgenerate //grss_pkt_cnt
localparam SYNC_STAGE_WIDTH = (C_SYNCHRONIZER_STAGE+1)*C_WR_PNTR_WIDTH;
reg [SYNC_STAGE_WIDTH-1:0] wr_pkt_count_q = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_b2g = 0;
wire [C_WR_PNTR_WIDTH-1:0] wr_pkt_count_rd;
generate if (IS_FWFT == 1 && IS_PKT_FIFO == 1 && C_COMMON_CLOCK == 0) begin // gras_pkt_cnt
// Delay the write packet count in write clock domain to accomodate the binary to gray conversion delay
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
wr_pkt_count_b2g <= 0;
else
wr_pkt_count_b2g <= #`TCQ wr_pkt_count;
end
// Synchronize the delayed write packet count in read domain, and also compensate the gray to binay conversion delay
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
wr_pkt_count_q <= 0;
else
wr_pkt_count_q <= #`TCQ {wr_pkt_count_q[SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH-1:0],wr_pkt_count_b2g};
end
always @* begin
if (stage1_eop)
rd_pkt_count <= rd_pkt_count_reg + 1;
else
rd_pkt_count <= rd_pkt_count_reg;
end
assign wr_pkt_count_rd = wr_pkt_count_q[SYNC_STAGE_WIDTH-1:SYNC_STAGE_WIDTH-C_WR_PNTR_WIDTH];
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft)
rd_pkt_count_reg <= 0;
else if (rd_en_fifo_in)
rd_pkt_count_reg <= #`TCQ rd_pkt_count;
end
always @ (posedge rst_fwft or posedge RD_CLK_P0_IN) begin
if (rst_fwft) begin
ram_pkt_empty <= 1'b1;
ram_pkt_empty_d1 <= 1'b1;
end else if (rd_pkt_count != wr_pkt_count_rd) begin
ram_pkt_empty <= #`TCQ 1'b0;
ram_pkt_empty_d1 <= #`TCQ 1'b0;
end else if (ram_pkt_empty_d1 && rd_en_to_fwft_fifo) begin
ram_pkt_empty <= #`TCQ 1'b1;
end else if ((rd_pkt_count == wr_pkt_count_rd) && stage2_reg_en_i) begin
ram_pkt_empty_d1 <= #`TCQ 1'b1;
end
end
// Synchronize the empty in write domain
always @ (posedge wr_rst_fwft_pkt_fifo or posedge WR_CLK) begin
if (wr_rst_fwft_pkt_fifo)
pkt_empty_sync <= 'b1;
else
pkt_empty_sync <= #`TCQ {pkt_empty_sync[C_SYNCHRONIZER_STAGE-2:0], empty_p0_out};
end
end endgenerate //gras_pkt_cnt
generate if (IS_FWFT == 0 || C_FIFO_TYPE == 3) begin : STD_FIFO
//***********************************************
// If NOT First-Word Fall-Through, wire the outputs
// of the internal _ss or _as FIFO directly to the
// output, and do not instantiate the preload0
// module.
//***********************************************
assign RD_CLK_P0_IN = 0;
assign RST_P0_IN = 0;
assign RD_EN_P0_IN = 0;
assign RD_EN_FIFO_IN = rd_en_delayed;
assign DOUT = DOUT_FIFO_OUT;
assign DATA_P0_IN = 0;
assign VALID = VALID_FIFO_OUT;
assign EMPTY = EMPTY_FIFO_OUT;
assign ALMOST_EMPTY = ALMOST_EMPTY_FIFO_OUT;
assign EMPTY_P0_IN = 0;
assign UNDERFLOW = UNDERFLOW_FIFO_OUT;
assign DATA_COUNT = DATA_COUNT_FIFO_OUT;
assign SBITERR = sbiterr_fifo_out;
assign DBITERR = dbiterr_fifo_out;
end endgenerate // STD_FIFO
generate if (IS_FWFT == 1 && C_FIFO_TYPE != 1) begin : NO_PKT_FIFO
assign empty_p0_out = empty_fwft;
assign SBITERR = sbiterr_fwft;
assign DBITERR = dbiterr_fwft;
assign DOUT = dout_fwft;
assign RD_EN_P0_IN = (C_FIFO_TYPE != 1) ? rd_en_delayed : rd_en_to_fwft_fifo;
end endgenerate // NO_PKT_FIFO
//***********************************************
// Connect user flags to internal signals
//***********************************************
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//RD_DATA_COUNT is 0 when EMPTY and 1 when ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block3
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : RD_DATA_COUNT_FIFO_OUT);
end //block_ic
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG < 3) ) begin : block30
if (C_COMMON_CLOCK == 0) begin : block_ic
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : RD_DATA_COUNT_FIFO_OUT);
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30
endgenerate
//If we are using extra logic for the FWFT data count, then override the
//RD_DATA_COUNT output when we are EMPTY or ALMOST_EMPTY.
//Due to asymmetric ports, RD_DATA_COUNT is 0 when EMPTY or ALMOST_EMPTY.
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH <=C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block30_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 0 : (RD_DATA_COUNT_FIFO_OUT));
end
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block30_both
endgenerate
generate
if (C_USE_FWFT_DATA_COUNT==1 && (C_RD_DATA_COUNT_WIDTH>C_RD_PNTR_WIDTH) && (C_USE_EMBEDDED_REG == 3) ) begin : block3_both
if (C_COMMON_CLOCK == 0) begin : block_ic_both
assign RD_DATA_COUNT = (EMPTY_P0_OUT_Q | RST_P0_IN) ? 0 : (ALMOSTEMPTY_P0_OUT_Q ? 1 : (RD_DATA_COUNT_FIFO_OUT));
end //block_ic_both
else begin
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
end //block3_both
endgenerate
//If we are not using extra logic for the FWFT data count,
//then connect RD_DATA_COUNT to the RD_DATA_COUNT from the
//internal FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==0 ) begin : block31
assign RD_DATA_COUNT = RD_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Always connect WR_DATA_COUNT to the WR_DATA_COUNT from the internal
//FIFO instance
generate
if (C_USE_FWFT_DATA_COUNT==1) begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
else begin : block4
assign WR_DATA_COUNT = WR_DATA_COUNT_FIFO_OUT;
end
endgenerate
//Connect other flags to the internal FIFO instance
assign FULL = FULL_FIFO_OUT;
assign ALMOST_FULL = ALMOST_FULL_FIFO_OUT;
assign WR_ACK = WR_ACK_FIFO_OUT;
assign OVERFLOW = OVERFLOW_FIFO_OUT;
assign PROG_FULL = PROG_FULL_FIFO_OUT;
assign PROG_EMPTY = PROG_EMPTY_FIFO_OUT;
/**************************************************************************
* find_log2
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function integer find_log2;
input integer int_val;
integer i,j;
begin
i = 1;
j = 0;
for (i = 1; i < int_val; i = i*2) begin
j = j + 1;
end
find_log2 = j;
end
endfunction
// if an asynchronous FIFO has been selected, display a message that the FIFO
// will not be cycle-accurate in simulation
initial begin
if (C_IMPLEMENTATION_TYPE == 2) begin
$display("WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information.");
end else if (C_MEMORY_TYPE == 4) begin
$display("FAILURE : Behavioral models do not support built-in FIFO configurations. Please use post-synthesis or post-implement simulation in Vivado.");
$finish;
end
if (C_WR_PNTR_WIDTH != find_log2(C_WR_DEPTH)) begin
$display("FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH.");
$finish;
end
if (C_RD_PNTR_WIDTH != find_log2(C_RD_DEPTH)) begin
$display("FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH.");
$finish;
end
if (C_USE_ECC == 1) begin
if (C_DIN_WIDTH != C_DOUT_WIDTH) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be equal for ECC configuration.");
$finish;
end
if (C_DIN_WIDTH == 1 && C_ERROR_INJECTION_TYPE > 1) begin
$display("FAILURE : C_DIN_WIDTH and C_DOUT_WIDTH must be > 1 for double bit error injection.");
$finish;
end
end
end //initial
/**************************************************************************
* Internal reset logic
**************************************************************************/
assign wr_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? wr_rst_reg : 0;
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? rd_rst_reg : 0;
assign rst_i = C_HAS_RST ? rst_reg : 0;
wire rst_2_sync;
wire rst_2_sync_safety = (C_ENABLE_RST_SYNC == 1) ? RST : RD_RST;
wire clk_2_sync = (C_COMMON_CLOCK == 1) ? CLK : WR_CLK;
wire clk_2_sync_safety = (C_COMMON_CLOCK == 1) ? CLK : RD_CLK;
generate
if (C_EN_SAFETY_CKT == 1 && C_INTERFACE_TYPE == 0) begin : grst_safety_ckt
reg[1:0] rst_d1_safety =1;
reg[1:0] rst_d2_safety =1;
reg[1:0] rst_d3_safety =1;
reg[1:0] rst_d4_safety =1;
reg[1:0] rst_d5_safety =1;
reg[1:0] rst_d6_safety =1;
reg[1:0] rst_d7_safety =1;
always@(posedge rst_2_sync_safety or posedge clk_2_sync_safety) begin : prst
if (rst_2_sync_safety == 1'b1) begin
rst_d1_safety <= 1'b1;
rst_d2_safety <= 1'b1;
rst_d3_safety <= 1'b1;
rst_d4_safety <= 1'b1;
rst_d5_safety <= 1'b1;
rst_d6_safety <= 1'b1;
rst_d7_safety <= 1'b1;
end
else begin
rst_d1_safety <= #`TCQ 1'b0;
rst_d2_safety <= #`TCQ rst_d1_safety;
rst_d3_safety <= #`TCQ rst_d2_safety;
rst_d4_safety <= #`TCQ rst_d3_safety;
rst_d5_safety <= #`TCQ rst_d4_safety;
rst_d6_safety <= #`TCQ rst_d5_safety;
rst_d7_safety <= #`TCQ rst_d6_safety;
end //if
end //prst
always@(posedge rst_d7_safety or posedge WR_EN) begin : assert_safety
if(rst_d7_safety == 1 && WR_EN == 1) begin
$display("WARNING:A write attempt has been made within the 7 clock cycles of reset de-assertion. This can lead to data discrepancy when safety circuit is enabled.");
end //if
end //always
end // grst_safety_ckt
endgenerate
// if (C_EN_SAFET_CKT == 1)
// assertion:the reset shud be atleast 3 cycles wide.
generate
if (C_ENABLE_RST_SYNC == 0) begin : gnrst_sync
always @* begin
wr_rst_reg <= wr_rst_delayed;
rd_rst_reg <= rd_rst_delayed;
rst_reg <= 1'b0;
srst_reg <= 1'b0;
end
assign rst_2_sync = wr_rst_delayed;
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 0) begin : g7s_ic_rst
assign wr_rst_comb = !wr_rst_asreg_d2 && wr_rst_asreg;
assign rd_rst_comb = !rd_rst_asreg_d2 && rd_rst_asreg;
assign rst_2_sync = rst_delayed;
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
always @(posedge WR_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b1;
end else begin
if (wr_rst_asreg_d1 == 1'b1) begin
wr_rst_asreg <= #`TCQ 1'b0;
end else begin
wr_rst_asreg <= #`TCQ wr_rst_asreg;
end
end
end
always @(posedge WR_CLK) begin
wr_rst_asreg_d1 <= #`TCQ wr_rst_asreg;
wr_rst_asreg_d2 <= #`TCQ wr_rst_asreg_d1;
end
always @(posedge WR_CLK or posedge wr_rst_comb) begin
if (wr_rst_comb == 1'b1) begin
wr_rst_reg <= #`TCQ 1'b1;
end else begin
wr_rst_reg <= #`TCQ 1'b0;
end
end
always @(posedge RD_CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b1;
end else begin
if (rd_rst_asreg_d1 == 1'b1) begin
rd_rst_asreg <= #`TCQ 1'b0;
end else begin
rd_rst_asreg <= #`TCQ rd_rst_asreg;
end
end
end
always @(posedge RD_CLK) begin
rd_rst_asreg_d1 <= #`TCQ rd_rst_asreg;
rd_rst_asreg_d2 <= #`TCQ rd_rst_asreg_d1;
end
always @(posedge RD_CLK or posedge rd_rst_comb) begin
if (rd_rst_comb == 1'b1) begin
rd_rst_reg <= #`TCQ 1'b1;
end else begin
rd_rst_reg <= #`TCQ 1'b0;
end
end
end else if (C_HAS_RST == 1 && C_COMMON_CLOCK == 1) begin : g7s_cc_rst
assign rst_comb = !rst_asreg_d2 && rst_asreg;
assign rst_2_sync = rst_delayed;
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
always @(posedge CLK or posedge rst_delayed) begin
if (rst_delayed == 1'b1) begin
rst_asreg <= #`TCQ 1'b1;
end else begin
if (rst_asreg_d1 == 1'b1) begin
rst_asreg <= #`TCQ 1'b0;
end else begin
rst_asreg <= #`TCQ rst_asreg;
end
end
end
always @(posedge CLK) begin
rst_asreg_d1 <= #`TCQ rst_asreg;
rst_asreg_d2 <= #`TCQ rst_asreg_d1;
end
always @(posedge CLK or posedge rst_comb) begin
if (rst_comb == 1'b1) begin
rst_reg <= #`TCQ 1'b1;
end else begin
rst_reg <= #`TCQ 1'b0;
end
end
end else if (IS_8SERIES == 1 && C_HAS_SRST == 1 && C_COMMON_CLOCK == 1) begin : g8s_cc_rst
assign wr_rst_busy = (C_MEMORY_TYPE != 4) ? rst_reg : rst_active_i;
assign rd_rst_busy = rst_reg;
assign rst_2_sync = srst_delayed;
always @* rst_full_ff_i <= rst_reg;
always @* rst_full_gen_i <= C_FULL_FLAGS_RST_VAL == 1 ? rst_active_i : 0;
always @(posedge CLK) begin
rst_delayed_d1 <= #`TCQ srst_delayed;
rst_delayed_d2 <= #`TCQ rst_delayed_d1;
if (rst_reg || rst_delayed_d2) begin
rst_active_i <= #`TCQ 1'b1;
end else begin
rst_active_i <= #`TCQ rst_reg;
end
end
always @(posedge CLK) begin
if (~rst_reg && srst_delayed) begin
rst_reg <= #`TCQ 1'b1;
end else if (rst_reg) begin
rst_reg <= #`TCQ 1'b0;
end else begin
rst_reg <= #`TCQ rst_reg;
end
end
end else begin
assign wr_rst_busy = 1'b0;
assign rd_rst_busy = 1'b0;
end
// end g8s_cc_rst
endgenerate
reg rst_d1 = 1'b0;
reg rst_d2 = 1'b0;
reg rst_d3 = 1'b0;
reg rst_d4 = 1'b0;
reg rst_d5 = 1'b0;
reg rst_d6 = 1'b0;
reg rst_d7 = 1'b0;
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1 && C_INTERFACE_TYPE == 0) begin : grstd1
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
rst_d5 <= 1'b1;
rst_d6 <= 1'b1;
rst_d7 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
rst_d5 <= #`TCQ 1'b1;
rst_d6 <= #`TCQ 1'b1;
rst_d7 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2;
rst_d4 <= #`TCQ rst_d3;
rst_d5 <= #`TCQ rst_d4;
rst_d6 <= #`TCQ rst_d5;
rst_d7 <= #`TCQ rst_d6;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0 && C_EN_SAFETY_CKT == 0) ? rst_d2 : (C_HAS_SRST == 0 && C_EN_SAFETY_CKT == 1) ? rst_d6 : 1'b0 ;
//always @* rst_full_gen_i <= rst_d4;
always @* rst_full_gen_i <= (C_HAS_SRST == 1) ? rst_d4 : (C_EN_SAFETY_CKT == 0) ? rst_d3 : rst_d7;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0 && C_INTERFACE_TYPE == 0) begin : gnrst_full
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1
generate
if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 1 && C_INTERFACE_TYPE > 0) begin : grstd1_axis
// RST_FULL_GEN replaces the reset falling edge detection used to de-assert
// FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1.
// RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL &
// PROG_FULL
always @ (posedge rst_2_sync or posedge clk_2_sync) begin
if (rst_2_sync) begin
rst_d1 <= 1'b1;
rst_d2 <= 1'b1;
rst_d3 <= 1'b1;
rst_d4 <= 1'b1;
rst_d5 <= 1'b1;
rst_d6 <= 1'b1;
rst_d7 <= 1'b1;
end else begin
if (srst_delayed) begin
rst_d1 <= #`TCQ 1'b1;
rst_d2 <= #`TCQ 1'b1;
rst_d3 <= #`TCQ 1'b1;
rst_d4 <= #`TCQ 1'b1;
rst_d5 <= #`TCQ 1'b1;
rst_d6 <= #`TCQ 1'b1;
rst_d7 <= #`TCQ 1'b1;
end else begin
rst_d1 <= #`TCQ 1'b0;
rst_d2 <= #`TCQ rst_d1;
rst_d3 <= #`TCQ rst_d2;
rst_d4 <= #`TCQ rst_d3;
rst_d5 <= #`TCQ rst_d4;
rst_d6 <= #`TCQ rst_d5;
rst_d7 <= #`TCQ rst_d6;
end
end
end
always @* rst_full_ff_i <= (C_HAS_SRST == 0) ? rst_d2 : 1'b0 ;
//always @* rst_full_gen_i <= rst_d4;
always @* rst_full_gen_i <= (C_HAS_SRST == 1) ? rst_d4 : (C_EN_SAFETY_CKT == 0) ? rst_d3 : rst_d5;
end else if ((C_HAS_RST == 1 || C_HAS_SRST == 1 || C_ENABLE_RST_SYNC == 0) && C_FULL_FLAGS_RST_VAL == 0 && C_INTERFACE_TYPE > 0) begin : gnrst_full_axis
always @* rst_full_ff_i <= (C_COMMON_CLOCK == 0) ? wr_rst_i : rst_i;
end
endgenerate // grstd1_axis
endmodule //fifo_generator_v13_1_0_CONV_VER
module fifo_generator_v13_1_0_sync_stage
#(
parameter C_WIDTH = 10
)
(
input RST,
input CLK,
input [C_WIDTH-1:0] DIN,
output reg [C_WIDTH-1:0] DOUT = 0
);
always @ (posedge RST or posedge CLK) begin
if (RST)
DOUT <= 0;
else
DOUT <= #`TCQ DIN;
end
endmodule // fifo_generator_v13_1_0_sync_stage
/*******************************************************************************
* Declaration of Independent-Clocks FIFO Module
******************************************************************************/
module fifo_generator_v13_1_0_bhv_ver_as
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_SYNCHRONIZER_STAGE = 2
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_CLK,
input RD_EN,
input RD_EN_USER,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input USER_EMPTY_FB,
input fab_read_data_valid_i,
input read_data_valid_i,
input ram_valid_i,
output reg ALMOST_EMPTY = 1'b1,
output reg ALMOST_FULL = C_FULL_FLAGS_RST_VAL,
output [C_DOUT_WIDTH-1:0] DOUT,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL,
output OVERFLOW,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output UNDERFLOW,
output WR_ACK,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC_1 && SYMMETRIC_PORT && ERR_INJECTION;
// Array that holds the error injection type (single/double bit error) on
// a specific write operation, which is returned on read to corrupt the
// output data.
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
//The amount of data stored in the FIFO at any time is given
// by num_wr_bits (in the WR_CLK domain) and num_rd_bits (in the RD_CLK
// domain.
//num_wr_bits is calculated by considering the total words in the FIFO,
// and the state of the read pointer (which may not have yet crossed clock
// domains.)
//num_rd_bits is calculated by considering the total words in the FIFO,
// and the state of the write pointer (which may not have yet crossed clock
// domains.)
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
wire wr_rst_i = WR_RST;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0; // UP counter: Rolls back to 0 when reaches to max value.
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire rd_rst_i = RD_RST;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
// Delayed ram_rd_en is needed only for STD Embedded register option
generate
if (C_PRELOAD_LATENCY == 2) begin : grd_d
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
end
endgenerate
generate
if (C_PRELOAD_LATENCY == 2 && C_USE_EMBEDDED_REG == 3) begin : grd_d1
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
end
endgenerate
// Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : rdg // Read depth greater than write depth
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1:0] = 0;
end else begin : rdl // Read depth lesser than or equal to write depth
assign adj_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
endgenerate
// Generate Empty and Almost Empty
// ram_rd_en used to determine EMPTY should depend on the EMPTY.
assign ram_rd_en = RD_EN & !EMPTY;
assign empty_int = ((adj_wr_pntr_rd == rd_pntr) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+1'h1))));
assign almost_empty_int = ((adj_wr_pntr_rd == (rd_pntr+1'h1)) || (ram_rd_en && (adj_wr_pntr_rd == (rd_pntr+2'h2))));
// Register Empty and Almost Empty
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin
EMPTY <= #`TCQ 1'b1;
ALMOST_EMPTY <= #`TCQ 1'b1;
rd_data_count_int <= #`TCQ {C_RD_PNTR_WIDTH{1'b0}};
end else begin
rd_data_count_int <= #`TCQ {(adj_wr_pntr_rd[C_RD_PNTR_WIDTH-1:0] - rd_pntr[C_RD_PNTR_WIDTH-1:0]), 1'b0};
if (empty_int)
EMPTY <= #`TCQ 1'b1;
else
EMPTY <= #`TCQ 1'b0;
if (!EMPTY) begin
if (almost_empty_int)
ALMOST_EMPTY <= #`TCQ 1'b1;
else
ALMOST_EMPTY <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
// Read pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation
generate
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wdg // Write depth greater than read depth
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1:0] = 0;
end else begin : wdl // Write depth lesser than or equal to read depth
assign adj_rd_pntr_wr = rd_pntr_wr[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end
endgenerate
// Generate FULL and ALMOST_FULL
// ram_wr_en used to determine FULL should depend on the FULL.
assign ram_wr_en = WR_EN & !FULL;
assign full_int = ((adj_rd_pntr_wr == (wr_pntr+1'h1)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+2'h2))));
assign almost_full_int = ((adj_rd_pntr_wr == (wr_pntr+2'h2)) || (ram_wr_en && (adj_rd_pntr_wr == (wr_pntr+3'h3))));
// Register FULL and ALMOST_FULL Empty
always @ (posedge WR_CLK or posedge RST_FULL_FF)
begin
if (RST_FULL_FF) begin
FULL <= #`TCQ C_FULL_FLAGS_RST_VAL;
ALMOST_FULL <= #`TCQ C_FULL_FLAGS_RST_VAL;
end else begin
if (full_int) begin
FULL <= #`TCQ 1'b1;
end else begin
FULL <= #`TCQ 1'b0;
end
if (RST_FULL_GEN) begin
ALMOST_FULL <= #`TCQ 1'b0;
end else if (!FULL) begin
if (almost_full_int)
ALMOST_FULL <= #`TCQ 1'b1;
else
ALMOST_FULL <= #`TCQ 1'b0;
end
end // wr_rst_i
end // always
always @ (posedge WR_CLK or posedge wr_rst_i)
begin
if (wr_rst_i) begin
wr_data_count_int <= #`TCQ {C_WR_DATA_COUNT_WIDTH{1'b0}};
end else begin
wr_data_count_int <= #`TCQ {(wr_pntr[C_WR_PNTR_WIDTH-1:0] - adj_rd_pntr_wr[C_WR_PNTR_WIDTH-1:0]), 1'b0};
end // wr_rst_i
end // always
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN_USER) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//Pointers passed into opposite clock domain
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_EMPTY.
wire [31:0] num_read_words_pe =
num_rd_bits/(C_DOUT_WIDTH/C_DEPTH_RATIO_WR);
//Amount of data stored in the FIFO scaled to the narrowest (deepest) port
// (Do not include data in FWFT stages)
//Used to calculate PROG_FULL.
wire [31:0] num_write_words_pf =
num_wr_bits/(C_DIN_WIDTH/C_DEPTH_RATIO_RD);
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/***************************************************************************
* Internal registers and wires
**************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire valid_i;
wire valid_out1;
wire valid_out2;
wire valid_out;
wire underflow_i;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
reg valid_d1 = 0;
reg valid_d2 = 0;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/****************************************************************************
* Function Declarations
***************************************************************************/
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
/***********************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
ideal_dout_d1 = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_d2 = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_CLK;
wire RD_EN;
wire RST;
wire WR_CLK;
wire WR_EN;
*/
//***************************************************************************
// Dout may change behavior based on latency
//***************************************************************************
assign ideal_dout_out[C_DOUT_WIDTH-1:0] = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) )?
ideal_dout_d1: ideal_dout;
assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_out;
//***************************************************************************
// Assign SBITERR and DBITERR based on latency
//***************************************************************************
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY == 2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) ) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
(C_PRELOAD_LATENCY==2 && (C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
//***************************************************************************
// Safety-ckt logic with embedded reg/fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d1;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end
end
endgenerate
//***************************************************************************
// Safety-ckt logic with embedded reg + fabric reg
//***************************************************************************
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
// if (C_HAS_VALID == 1) begin
// assign valid_out = valid_d2;
// end
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft4 or posedge rd_rst_i or posedge RD_CLK)
begin
if( rst_delayed_sft4 == 1'b1 || rd_rst_i == 1'b1)
ram_rd_en_d1 <= #`TCQ 1'b0;
else
ram_rd_en_d1 <= #`TCQ ram_rd_en;
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
end
always@(posedge rst_delayed_sft2 or posedge RD_CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
else begin
if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
end
end
endgenerate
//***************************************************************************
// Overflow may be active-low
//***************************************************************************
generate
if (C_HAS_OVERFLOW==1) begin : blockOF1
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end
endgenerate
assign PROG_EMPTY = ideal_prog_empty;
assign PROG_FULL = ideal_prog_full;
//***************************************************************************
// Valid may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_VALID==1) begin : blockVL1
assign valid_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out1 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG < 3)?
valid_d1: valid_i;
assign valid_out2 = (C_PRELOAD_LATENCY==2 &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_USE_EMBEDDED_REG == 3)?
valid_d2: valid_i;
assign valid_out = (C_USE_EMBEDDED_REG == 3) ? valid_out2 : valid_out1;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end
endgenerate
//***************************************************************************
// Underflow may change behavior based on latency or active-low
//***************************************************************************
generate
if (C_HAS_UNDERFLOW==1) begin : blockUF1
assign underflow_i = (C_PRELOAD_LATENCY==0) ? (RD_EN & EMPTY) : ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end
endgenerate
//***************************************************************************
// Write acknowledge may be active low
//***************************************************************************
generate
if (C_HAS_WR_ACK==1) begin : blockWK1
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : wdc_fwft_ext
reg [C_PNTR_WIDTH-1:0] adjusted_wr_pntr = 0;
reg [C_PNTR_WIDTH-1:0] adjusted_rd_pntr = 0;
wire [C_PNTR_WIDTH-1:0] diff_wr_rd_tmp;
wire [C_PNTR_WIDTH:0] diff_wr_rd;
reg [C_PNTR_WIDTH:0] wr_data_count_i = 0;
always @* begin
if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = 0;
adjusted_rd_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr_wr;
end else if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin
adjusted_rd_pntr = rd_pntr_wr;
adjusted_wr_pntr = 0;
adjusted_wr_pntr[C_PNTR_WIDTH-1:C_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
end else begin
adjusted_wr_pntr = wr_pntr;
adjusted_rd_pntr = rd_pntr_wr;
end
end // always @*
assign diff_wr_rd_tmp = adjusted_wr_pntr - adjusted_rd_pntr;
assign diff_wr_rd = {1'b0,diff_wr_rd_tmp};
always @ (posedge wr_rst_i or posedge WR_CLK)
begin
if (wr_rst_i)
wr_data_count_i <= #`TCQ 0;
else
wr_data_count_i <= #`TCQ diff_wr_rd + EXTRA_WORDS_DC;
end // always @ (posedge WR_CLK or posedge WR_CLK)
always @* begin
if (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH)
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:0];
else
wdc_fwft_ext_as = wr_data_count_i[C_PNTR_WIDTH:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end // always @*
end // wdc_fwft_ext
endgenerate
//***************************************************************************
// Generate RD_DATA_COUNT if Use Extra Logic option is selected
//***************************************************************************
reg [C_RD_PNTR_WIDTH:0] rdc_fwft_ext_as = 0;
generate if (C_USE_EMBEDDED_REG < 3) begin: rdc_fwft_ext_both
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
if (!stage2_valid)
rdc_fwft_ext_as <= #`TCQ 0;
else if (!stage1_valid && stage2_valid)
rdc_fwft_ext_as <= #`TCQ 1;
else
rdc_fwft_ext_as <= #`TCQ diff_rd_wr + 2'h2;
end
end // always @ (posedge WR_CLK or posedge WR_CLK)
end // rdc_fwft_ext
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3) begin
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : rdc_fwft_ext
reg [C_RD_PNTR_WIDTH-1:0] adjusted_wr_pntr_rd = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_rd_wr_tmp;
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr;
always @* begin
if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin
adjusted_wr_pntr_rd = 0;
adjusted_wr_pntr_rd[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr_rd;
end else begin
adjusted_wr_pntr_rd = wr_pntr_rd[C_WR_PNTR_WIDTH-1:C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end
end // always @*
assign diff_rd_wr_tmp = adjusted_wr_pntr_rd - rd_pntr;
assign diff_rd_wr = {1'b0,diff_rd_wr_tmp};
wire [C_RD_PNTR_WIDTH:0] diff_rd_wr_1;
// assign diff_rd_wr_1 = diff_rd_wr +2'h2;
always @ (posedge rd_rst_i or posedge RD_CLK)
begin
if (rd_rst_i) begin
rdc_fwft_ext_as <= #`TCQ 0;
end else begin
//if (fab_read_data_valid_i == 1'b0 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b1 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b0;
//else if (fab_read_data_valid_i == 1'b1 && ((ram_valid_i == 1'b0 && read_data_valid_i ==1'b0) || (ram_valid_i == 1'b0 && read_data_valid_i ==1'b1)))
// rdc_fwft_ext_as <= 1'b1;
//else
rdc_fwft_ext_as <= diff_rd_wr + 2'h2 ;
end
end
end
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = C_USE_FWFT_DATA_COUNT ?
rdc_fwft_ext_as[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH] :
rd_data_count_int[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = (C_USE_FWFT_DATA_COUNT == 1) ?
wdc_fwft_ext_as[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] :
wr_data_count_int[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate
if (C_HAS_VALID==1) begin : blockVL2
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
valid_d1 <= #`TCQ 1'b0;
valid_d2 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
valid_d2 <= #`TCQ valid_d1;
end
// if (C_USE_EMBEDDED_REG == 3 && (C_EN_SAFETY_CKT == 0 || C_EN_SAFETY_CKT == 1 ) begin
// valid_d2 <= #`TCQ valid_d1;
// end
end
end
endgenerate
//Capture delayed version of dout
/**************************************************************************
*embedded/fabric reg with no safety ckt
**************************************************************************/
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
endgenerate
/**************************************************************************
*embedded + fabric reg with no safety ckt
**************************************************************************/
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3) begin
always @(posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge RD_CLK)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
end else if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate
if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge WR_CLK) begin
ideal_overflow <= #`TCQ WR_EN & FULL;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge WR_CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (FULL | wr_rst_i);
ideal_overflow <= #`TCQ WR_EN & (FULL );
end
end
endgenerate
generate
if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ EMPTY & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge RD_CLK) begin
ideal_underflow <= #`TCQ (EMPTY) & RD_EN;
//ideal_underflow <= #`TCQ (rd_rst_i | EMPTY) & RD_EN;
end
end
endgenerate
/**************************************************************************
* Write/Read Pointer Synchronization
**************************************************************************/
localparam NO_OF_SYNC_STAGE_INC_G2B = C_SYNCHRONIZER_STAGE + 1;
wire [C_WR_PNTR_WIDTH-1:0] wr_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_sync_stgs [0:NO_OF_SYNC_STAGE_INC_G2B];
genvar gss;
generate for (gss = 1; gss <= NO_OF_SYNC_STAGE_INC_G2B; gss = gss + 1) begin : Sync_stage_inst
fifo_generator_v13_1_0_sync_stage
#(
.C_WIDTH (C_WR_PNTR_WIDTH)
)
rd_stg_inst
(
.RST (rd_rst_i),
.CLK (RD_CLK),
.DIN (wr_pntr_sync_stgs[gss-1]),
.DOUT (wr_pntr_sync_stgs[gss])
);
fifo_generator_v13_1_0_sync_stage
#(
.C_WIDTH (C_RD_PNTR_WIDTH)
)
wr_stg_inst
(
.RST (wr_rst_i),
.CLK (WR_CLK),
.DIN (rd_pntr_sync_stgs[gss-1]),
.DOUT (rd_pntr_sync_stgs[gss])
);
end endgenerate // Sync_stage_inst
assign wr_pntr_sync_stgs[0] = wr_pntr_rd1;
assign rd_pntr_sync_stgs[0] = rd_pntr_wr1;
always@* begin
wr_pntr_rd <= wr_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
rd_pntr_wr <= rd_pntr_sync_stgs[NO_OF_SYNC_STAGE_INC_G2B];
end
/**************************************************************************
* Write Domain Logic
**************************************************************************/
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
always @(posedge WR_CLK or posedge wr_rst_i ) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (wr_rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //wr_rst_i==0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
//If this is a write, handle the write by adding the value
// to the linked list, and updating all outputs appropriately
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD
>= C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full, but reporting full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//With DEPTH-1 words in the FIFO, it is almost_full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is completely empty, but it is
// reporting FULL for some reason (like reset)
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <=
C_FIFO_WR_DEPTH-2) begin
//No change to FIFO
//Write not successful
ideal_wr_ack <= #`TCQ 0;
//FIFO is really not close to full, so change flag status.
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end //(tmp_wr_listsize == 0)
end else begin
//If the FIFO is full, do NOT perform the write,
// update flags accordingly
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD >=
C_FIFO_WR_DEPTH) begin
//write unsuccessful - do not change contents
//Do not acknowledge the write
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is one from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-1) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//This write is CAUSING the FIFO to go full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is 2 from full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD ==
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Still 2 from full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
//If the FIFO is not close to being full
end else
if ((tmp_wr_listsize + C_DEPTH_RATIO_RD - 1)/C_DEPTH_RATIO_RD <
C_FIFO_WR_DEPTH-2) begin
//Add value on DIN port to FIFO
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //wr_rst_i==0
end // gen_fifo_w
/***************************************************************************
* Programmable FULL flags
***************************************************************************/
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_assert_val;
wire [C_WR_PNTR_WIDTH-1:0] pf_thr_negate_val;
generate if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin : FWFT
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC;
end else begin // STD
assign pf_thr_assert_val = C_PROG_FULL_THRESH_ASSERT_VAL;
assign pf_thr_negate_val = C_PROG_FULL_THRESH_NEGATE_VAL;
end endgenerate
always @(posedge WR_CLK or posedge wr_rst_i) begin
if (wr_rst_i == 1'b1) begin
diff_pntr <= 0;
end else begin
if (ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr + 2'h1);
else if (!ram_wr_en)
diff_pntr <= #`TCQ (wr_pntr - adj_rd_pntr_wr);
end
end
always @(posedge WR_CLK or posedge RST_FULL_FF) begin : gen_pf
if (RST_FULL_FF == 1'b1) begin
ideal_prog_full <= #`TCQ C_FULL_FLAGS_RST_VAL;
end else begin
if (RST_FULL_GEN)
ideal_prog_full <= #`TCQ 0;
//Single Programmable Full Constant Threshold
else if (C_PROG_FULL_TYPE == 1) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Constant Thresholds
end else if (C_PROG_FULL_TYPE == 2) begin
if (FULL == 0) begin
if (diff_pntr >= pf_thr_assert_val)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < pf_thr_negate_val)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Single Programmable Full Threshold Input
end else if (C_PROG_FULL_TYPE == 3) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH)
ideal_prog_full <= #`TCQ 1;
else
ideal_prog_full <= #`TCQ 0;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
//Two Programmable Full Threshold Inputs
end else if (C_PROG_FULL_TYPE == 4) begin
if (FULL == 0) begin
if (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) begin // FWFT
if (diff_pntr >= (PROG_FULL_THRESH_ASSERT - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < (PROG_FULL_THRESH_NEGATE - EXTRA_WORDS_DC))
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end else begin // STD
if (diff_pntr >= PROG_FULL_THRESH_ASSERT)
ideal_prog_full <= #`TCQ 1;
else if (diff_pntr < PROG_FULL_THRESH_NEGATE)
ideal_prog_full <= #`TCQ 0;
else
ideal_prog_full <= #`TCQ ideal_prog_full;
end
end else
ideal_prog_full <= #`TCQ ideal_prog_full;
end // C_PROG_FULL_TYPE
end //wr_rst_i==0
end //
/**************************************************************************
* Read Domain Logic
**************************************************************************/
/*********************************************************
* Programmable EMPTY flags
*********************************************************/
//Determine the Assert and Negate thresholds for Programmable Empty
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_assert_val;
wire [C_RD_PNTR_WIDTH-1:0] pe_thr_negate_val;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_rd = 0;
always @(posedge RD_CLK or posedge rd_rst_i) begin : gen_pe
if (rd_rst_i) begin
diff_pntr_rd <= #`TCQ 0;
ideal_prog_empty <= #`TCQ 1'b1;
end else begin
if (ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr) - 1'h1;
else if (!ram_rd_en)
diff_pntr_rd <= #`TCQ (adj_wr_pntr_rd - rd_pntr);
else
diff_pntr_rd <= #`TCQ diff_pntr_rd;
if (C_PROG_EMPTY_TYPE == 1) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 2) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 3) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else
ideal_prog_empty <= #`TCQ 0;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else if (C_PROG_EMPTY_TYPE == 4) begin
if (EMPTY == 0) begin
if (diff_pntr_rd <= pe_thr_assert_val)
ideal_prog_empty <= #`TCQ 1;
else if (diff_pntr_rd > pe_thr_negate_val)
ideal_prog_empty <= #`TCQ 0;
else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end else
ideal_prog_empty <= #`TCQ ideal_prog_empty;
end //C_PROG_EMPTY_TYPE
end
end // gen_pe
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH - 2'h2 : PROG_EMPTY_THRESH;
end endgenerate // single_pe_thr_input
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_thr_input
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_ASSERT - 2'h2 : PROG_EMPTY_THRESH_ASSERT;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
PROG_EMPTY_THRESH_NEGATE - 2'h2 : PROG_EMPTY_THRESH_NEGATE;
end endgenerate // multiple_pe_thr_input
generate if (C_PROG_EMPTY_TYPE < 3) begin : single_multiple_pe_thr_const
assign pe_thr_assert_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2'h2 : C_PROG_EMPTY_THRESH_ASSERT_VAL;
assign pe_thr_negate_val = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2'h2 : C_PROG_EMPTY_THRESH_NEGATE_VAL;
end endgenerate // single_multiple_pe_thr_const
// // block memory has a synchronous reset
// always @(posedge RD_CLK) begin : gen_fifo_blkmemdout
// // make it consistent with the core.
// if (rd_rst_i) begin
// // Reset err_type only if ECC is not selected
// if (C_USE_ECC == 0 && C_MEMORY_TYPE < 2)
// err_type <= #`TCQ 0;
//
// // BRAM resets synchronously
// if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2) begin
// //ideal_dout <= #`TCQ dout_reset_val;
// //ideal_dout_d1 <= #`TCQ dout_reset_val;
// end
// end
// end //always
always @(posedge RD_CLK or posedge rd_rst_i ) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rd_rst_i == 1'b1 ) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_MEMORY_TYPE == 2 && C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type <= #`TCQ 0;
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
/*****************************************************************/
// Read Operation - Read Latency 1
/*****************************************************************/
if (C_PRELOAD_LATENCY==1 || C_PRELOAD_LATENCY==2) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
//If the FIFO is one from empty, but it is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is two from empty, and is reporting empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH))
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end // else: if(ideal_empty == 1'b1)
else //if (ideal_empty == 1'b0)
begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == C_FIFO_RD_DEPTH)
//If the FIFO is not close to being empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) && (tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
//If the FIFO is two from empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2)
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
//If the FIFO is one from empty
else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR == 1))
begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 1)
//If the FIFO is completely empty
else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0)
begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end //(RD_EN == 1'b1)
else //if (RD_EN == 1'b0)
begin
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
/*****************************************************************/
// Read Operation - Read Latency 0
/*****************************************************************/
end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
ideal_valid <= #`TCQ 1'b0;
if (ram_rd_en == 1'b1) begin
if (EMPTY == 1'b1) begin
//If the FIFO is completely empty, and is reporting empty
if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty, but it is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that FIFO is no longer empty, but is almost empty (has one word left)
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty, and is reporting empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Fifo has two words, so is neither empty or almost empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to empty, but is reporting that it is
// Treat the FIFO as empty this time, but unset EMPTY flags.
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<C_FIFO_RD_DEPTH)) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Note that the FIFO is No Longer Empty or Almost Empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))
end else begin
//If the FIFO is completely full, and we are successfully reading from it
if (tmp_rd_listsize/C_DEPTH_RATIO_WR >= C_FIFO_RD_DEPTH) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is not close to being empty
end else if ((tmp_rd_listsize/C_DEPTH_RATIO_WR > 2) &&
(tmp_rd_listsize/C_DEPTH_RATIO_WR<=C_FIFO_RD_DEPTH)) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Not close to empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is two from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 2) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Fifo is not yet empty. It is going almost_empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is one from empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR == 1) begin
//Read the value from the FIFO
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
//Note that FIFO is GOING empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
//If the FIFO is completely empty
end else if (tmp_rd_listsize/C_DEPTH_RATIO_WR <= 0) begin
//Do not change the contents of the FIFO
//Do not acknowledge the read from empty FIFO
ideal_valid <= #`TCQ 1'b0;
//Reminder that FIFO is still empty
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize <= 0)
end // if (ideal_empty == 1'b0)
end else begin//(RD_EN == 1'b0)
//If user did not attempt a read, do not give an ack or err
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // else: !if(RD_EN == 1'b1)
end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //rd_rst_i==0
end //always
endmodule // fifo_generator_v13_1_0_bhv_ver_as
/*******************************************************************************
* Declaration of Low Latency Asynchronous FIFO
******************************************************************************/
module fifo_generator_v13_1_0_beh_ver_ll_afifo
/***************************************************************************
* Declare user parameters and their defaults
***************************************************************************/
#(
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_USE_DOUT_RST = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_FIFO_TYPE = 0
)
/***************************************************************************
* Declare Input and Output Ports
***************************************************************************/
(
input [C_DIN_WIDTH-1:0] DIN,
input RD_CLK,
input RD_EN,
input WR_RST,
input RD_RST,
input WR_CLK,
input WR_EN,
output reg [C_DOUT_WIDTH-1:0] DOUT = 0,
output reg EMPTY = 1'b1,
output reg FULL = C_FULL_FLAGS_RST_VAL
);
//-----------------------------------------------------------------------------
// Low Latency Asynchronous FIFO
//-----------------------------------------------------------------------------
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
integer i;
initial begin
for (i = 0; i < C_WR_DEPTH; i = i + 1)
memory[i] = 0;
end
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_ll_afifo = 0;
wire [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_ll_afifo_q = 0;
reg ll_afifo_full = 1'b0;
reg ll_afifo_empty = 1'b1;
wire write_allow;
wire read_allow;
assign write_allow = WR_EN & ~ll_afifo_full;
assign read_allow = RD_EN & ~ll_afifo_empty;
//-----------------------------------------------------------------------------
// Write Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
wr_pntr_ll_afifo <= 0;
else if (write_allow)
wr_pntr_ll_afifo <= #`TCQ wr_pntr_ll_afifo + 1;
end
//-----------------------------------------------------------------------------
// Read Pointer Generation
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
rd_pntr_ll_afifo_q <= 0;
else
rd_pntr_ll_afifo_q <= #`TCQ rd_pntr_ll_afifo;
end
assign rd_pntr_ll_afifo = read_allow ? rd_pntr_ll_afifo_q + 1 : rd_pntr_ll_afifo_q;
//-----------------------------------------------------------------------------
// Fill the Memory
//-----------------------------------------------------------------------------
always @(posedge WR_CLK) begin
if (write_allow)
memory[wr_pntr_ll_afifo] <= #`TCQ DIN;
end
//-----------------------------------------------------------------------------
// Generate DOUT
//-----------------------------------------------------------------------------
always @(posedge RD_CLK) begin
DOUT <= #`TCQ memory[rd_pntr_ll_afifo];
end
//-----------------------------------------------------------------------------
// Generate EMPTY
//-----------------------------------------------------------------------------
always @(posedge RD_CLK or posedge RD_RST) begin
if (RD_RST)
ll_afifo_empty <= 1'b1;
else
ll_afifo_empty <= ((wr_pntr_ll_afifo == rd_pntr_ll_afifo_q) |
(read_allow & (wr_pntr_ll_afifo == (rd_pntr_ll_afifo_q + 2'h1))));
end
//-----------------------------------------------------------------------------
// Generate FULL
//-----------------------------------------------------------------------------
always @(posedge WR_CLK or posedge WR_RST) begin
if (WR_RST)
ll_afifo_full <= 1'b1;
else
ll_afifo_full <= ((rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h1)) |
(write_allow & (rd_pntr_ll_afifo_q == (wr_pntr_ll_afifo + 2'h2))));
end
always @* begin
FULL <= ll_afifo_full;
EMPTY <= ll_afifo_empty;
end
endmodule // fifo_generator_v13_1_0_beh_ver_ll_afifo
/*******************************************************************************
* Declaration of top-level module
******************************************************************************/
module fifo_generator_v13_1_0_bhv_ver_ss
/**************************************************************************
* Declare user parameters and their defaults
*************************************************************************/
#(
parameter C_FAMILY = "virtex7",
parameter C_DATA_COUNT_WIDTH = 2,
parameter C_DIN_WIDTH = 8,
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_FULL_FLAGS_RST_VAL = 1,
parameter C_HAS_ALMOST_EMPTY = 0,
parameter C_HAS_ALMOST_FULL = 0,
parameter C_HAS_DATA_COUNT = 0,
parameter C_HAS_OVERFLOW = 0,
parameter C_HAS_RD_DATA_COUNT = 0,
parameter C_HAS_RST = 0,
parameter C_HAS_SRST = 0,
parameter C_HAS_UNDERFLOW = 0,
parameter C_HAS_VALID = 0,
parameter C_HAS_WR_ACK = 0,
parameter C_HAS_WR_DATA_COUNT = 0,
parameter C_IMPLEMENTATION_TYPE = 0,
parameter C_MEMORY_TYPE = 1,
parameter C_OVERFLOW_LOW = 0,
parameter C_PRELOAD_LATENCY = 1,
parameter C_PRELOAD_REGS = 0,
parameter C_PROG_EMPTY_THRESH_ASSERT_VAL = 0,
parameter C_PROG_EMPTY_THRESH_NEGATE_VAL = 0,
parameter C_PROG_EMPTY_TYPE = 0,
parameter C_PROG_FULL_THRESH_ASSERT_VAL = 0,
parameter C_PROG_FULL_THRESH_NEGATE_VAL = 0,
parameter C_PROG_FULL_TYPE = 0,
parameter C_RD_DATA_COUNT_WIDTH = 2,
parameter C_RD_DEPTH = 256,
parameter C_RD_PNTR_WIDTH = 8,
parameter C_UNDERFLOW_LOW = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_FWFT_DATA_COUNT = 0,
parameter C_VALID_LOW = 0,
parameter C_WR_ACK_LOW = 0,
parameter C_WR_DATA_COUNT_WIDTH = 2,
parameter C_WR_DEPTH = 256,
parameter C_WR_PNTR_WIDTH = 8,
parameter C_USE_ECC = 0,
parameter C_ENABLE_RST_SYNC = 1,
parameter C_ERROR_INJECTION_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
/**************************************************************************
* Declare Input and Output Ports
*************************************************************************/
(
//Inputs
input CLK,
input [C_DIN_WIDTH-1:0] DIN,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT,
input [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT,
input [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE,
input RD_EN,
input RD_EN_USER,
input USER_EMPTY_FB,
input RST,
input RST_FULL_GEN,
input RST_FULL_FF,
input SRST,
input WR_EN,
input INJECTDBITERR,
input INJECTSBITERR,
input WR_RST_BUSY,
input RD_RST_BUSY,
//Outputs
output ALMOST_EMPTY,
output ALMOST_FULL,
output reg [C_DATA_COUNT_WIDTH-1:0] DATA_COUNT = 0,
output [C_DOUT_WIDTH-1:0] DOUT,
output EMPTY,
output FULL,
output OVERFLOW,
output [C_RD_DATA_COUNT_WIDTH-1:0] RD_DATA_COUNT,
output [C_WR_DATA_COUNT_WIDTH-1:0] WR_DATA_COUNT,
output PROG_EMPTY,
output PROG_FULL,
output VALID,
output UNDERFLOW,
output WR_ACK,
output SBITERR,
output DBITERR
);
reg [C_RD_PNTR_WIDTH:0] rd_data_count_int = 0;
reg [C_WR_PNTR_WIDTH:0] wr_data_count_int = 0;
wire [C_RD_PNTR_WIDTH:0] rd_data_count_i_ss;
wire [C_WR_PNTR_WIDTH:0] wr_data_count_i_ss;
reg [C_WR_PNTR_WIDTH:0] wdc_fwft_ext_as = 0;
/***************************************************************************
* Parameters used as constants
**************************************************************************/
localparam IS_8SERIES = (C_FAMILY == "virtexu" || C_FAMILY == "kintexu" || C_FAMILY == "artixu" || C_FAMILY == "virtexuplus" || C_FAMILY == "zynquplus" || C_FAMILY == "kintexuplus") ? 1 : 0;
localparam C_DEPTH_RATIO_WR =
(C_WR_DEPTH>C_RD_DEPTH) ? (C_WR_DEPTH/C_RD_DEPTH) : 1;
localparam C_DEPTH_RATIO_RD =
(C_RD_DEPTH>C_WR_DEPTH) ? (C_RD_DEPTH/C_WR_DEPTH) : 1;
//localparam C_FIFO_WR_DEPTH = C_WR_DEPTH - 1;
//localparam C_FIFO_RD_DEPTH = C_RD_DEPTH - 1;
localparam C_GRTR_PNTR_WIDTH = (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH ;
// C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC
// -----------------|------------------|-----------------|---------------
// 1 | 8 | C_RD_PNTR_WIDTH | 2
// 1 | 4 | C_RD_PNTR_WIDTH | 2
// 1 | 2 | C_RD_PNTR_WIDTH | 2
// 1 | 1 | C_WR_PNTR_WIDTH | 2
// 2 | 1 | C_WR_PNTR_WIDTH | 4
// 4 | 1 | C_WR_PNTR_WIDTH | 8
// 8 | 1 | C_WR_PNTR_WIDTH | 16
localparam C_PNTR_WIDTH = (C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
wire [C_PNTR_WIDTH:0] EXTRA_WORDS_DC = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
wire [C_WR_PNTR_WIDTH:0] EXTRA_WORDS_PF = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//wire [C_RD_PNTR_WIDTH:0] EXTRA_WORDS_PE = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam EXTRA_WORDS_PF_PARAM = (C_DEPTH_RATIO_WR == 1) ? 2 : (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD);
//localparam EXTRA_WORDS_PE_PARAM = (C_DEPTH_RATIO_RD == 1) ? 2 : (2 * C_DEPTH_RATIO_RD/C_DEPTH_RATIO_WR);
localparam [31:0] reads_per_write = C_DIN_WIDTH/C_DOUT_WIDTH;
localparam [31:0] log2_reads_per_write = log2_val(reads_per_write);
localparam [31:0] writes_per_read = C_DOUT_WIDTH/C_DIN_WIDTH;
localparam [31:0] log2_writes_per_read = log2_val(writes_per_read);
//When RST is present, set FULL reset value to '1'.
//If core has no RST, make sure FULL powers-on as '0'.
//The reset value assignments for FULL, ALMOST_FULL, and PROG_FULL are not
//changed for v3.2(IP2_Im). When the core has Sync Reset, C_HAS_SRST=1 and C_HAS_RST=0.
// Therefore, during SRST, all the FULL flags reset to 0.
localparam C_HAS_FAST_FIFO = 0;
localparam C_FIFO_WR_DEPTH = C_WR_DEPTH;
localparam C_FIFO_RD_DEPTH = C_RD_DEPTH;
// Local parameters used to determine whether to inject ECC error or not
localparam SYMMETRIC_PORT = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 1 : 0;
localparam ERR_INJECTION = (C_ERROR_INJECTION_TYPE != 0) ? 1 : 0;
localparam C_USE_ECC_1 = (C_USE_ECC == 1 || C_USE_ECC ==2) ? 1:0;
localparam ENABLE_ERR_INJECTION = C_USE_ECC && SYMMETRIC_PORT && ERR_INJECTION;
localparam C_DATA_WIDTH = (ENABLE_ERR_INJECTION == 1) ? (C_DIN_WIDTH+2) : C_DIN_WIDTH;
localparam IS_ASYMMETRY = (C_DIN_WIDTH == C_DOUT_WIDTH) ? 0 : 1;
localparam LESSER_WIDTH = (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) ? C_WR_PNTR_WIDTH : C_RD_PNTR_WIDTH;
localparam [C_RD_PNTR_WIDTH-1 : 0] DIFF_MAX_RD = {C_RD_PNTR_WIDTH{1'b1}};
localparam [C_WR_PNTR_WIDTH-1 : 0] DIFF_MAX_WR = {C_WR_PNTR_WIDTH{1'b1}};
/**************************************************************************
* FIFO Contents Tracking and Data Count Calculations
*************************************************************************/
// Memory which will be used to simulate a FIFO
reg [C_DIN_WIDTH-1:0] memory[C_WR_DEPTH-1:0];
reg [1:0] ecc_err[C_WR_DEPTH-1:0];
/**************************************************************************
* Internal Registers and wires
*************************************************************************/
//Temporary signals used for calculating the model's outputs. These
//are only used in the assign statements immediately following wire,
//parameter, and function declarations.
wire underflow_i;
wire valid_i;
wire valid_out;
reg [31:0] num_wr_bits;
reg [31:0] num_rd_bits;
reg [31:0] next_num_wr_bits;
reg [31:0] next_num_rd_bits;
//The write pointer - tracks write operations
// (Works opposite to core: wr_ptr is a DOWN counter)
reg [31:0] wr_ptr;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd1 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd3 = 0;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr_rd = 0;
reg wr_rst_d1 =0;
//The read pointer - tracks read operations
// (rd_ptr Works opposite to core: rd_ptr is a DOWN counter)
reg [31:0] rd_ptr;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr2 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr3 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr4 = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr_wr = 0;
wire ram_rd_en;
wire empty_int;
wire almost_empty_int;
wire ram_wr_en;
wire full_int;
wire almost_full_int;
reg ram_rd_en_reg = 1'b0;
reg ram_rd_en_d1 = 1'b0;
reg fab_rd_en_d1 = 1'b0;
wire srst_rrst_busy;
//Ideal FIFO signals. These are the raw output of the behavioral model,
//which behaves like an ideal FIFO.
reg [1:0] err_type = 0;
reg [1:0] err_type_d1 = 0;
reg [1:0] err_type_both = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_d1 = 0;
reg [C_DOUT_WIDTH-1:0] ideal_dout_both = 0;
wire [C_DOUT_WIDTH-1:0] ideal_dout_out;
wire fwft_enabled;
reg ideal_wr_ack = 0;
reg ideal_valid = 0;
reg ideal_overflow = C_OVERFLOW_LOW;
reg ideal_underflow = C_UNDERFLOW_LOW;
reg full_i = C_FULL_FLAGS_RST_VAL;
reg full_i_temp = 0;
reg empty_i = 1;
reg almost_full_i = 0;
reg almost_empty_i = 1;
reg prog_full_i = 0;
reg prog_empty_i = 1;
reg [C_WR_PNTR_WIDTH-1:0] wr_pntr = 0;
reg [C_RD_PNTR_WIDTH-1:0] rd_pntr = 0;
wire [C_RD_PNTR_WIDTH-1:0] adj_wr_pntr_rd;
wire [C_WR_PNTR_WIDTH-1:0] adj_rd_pntr_wr;
reg [C_RD_PNTR_WIDTH-1:0] diff_count = 0;
reg write_allow_q = 0;
reg read_allow_q = 0;
reg valid_d1 = 0;
reg valid_both = 0;
reg valid_d2 = 0;
wire rst_i;
wire srst_i;
//user specified value for reseting the size of the fifo
reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
reg [31:0] wr_ptr_rdclk;
reg [31:0] wr_ptr_rdclk_next;
reg [31:0] rd_ptr_wrclk;
reg [31:0] rd_ptr_wrclk_next;
/****************************************************************************
* Function Declarations
***************************************************************************/
/****************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***************************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 ) begin
case (def_data[7:0])
8'b00000000 : begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default : begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1) begin
if ((index*4)+j < C_DOUT_WIDTH) begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
/**************************************************************************
* log2_val
* Returns the 'log2' value for the input value for the supported ratios
***************************************************************************/
function [31:0] log2_val;
input [31:0] binary_val;
begin
if (binary_val == 8) begin
log2_val = 3;
end else if (binary_val == 4) begin
log2_val = 2;
end else begin
log2_val = 1;
end
end
endfunction
reg ideal_prog_full = 0;
reg ideal_prog_empty = 1;
reg [C_WR_DATA_COUNT_WIDTH-1 : 0] ideal_wr_count = 0;
reg [C_RD_DATA_COUNT_WIDTH-1 : 0] ideal_rd_count = 0;
//Assorted reg values for delayed versions of signals
//reg valid_d1 = 0;
//user specified value for reseting the size of the fifo
//reg [C_DOUT_WIDTH-1:0] dout_reset_val = 0;
//temporary registers for WR_RESPONSE_LATENCY feature
integer tmp_wr_listsize;
integer tmp_rd_listsize;
//Signal for registered version of prog full and empty
//Threshold values for Programmable Flags
integer prog_empty_actual_thresh_assert;
integer prog_empty_actual_thresh_negate;
integer prog_full_actual_thresh_assert;
integer prog_full_actual_thresh_negate;
/**************************************************************************
* write_fifo
* This task writes a word to the FIFO memory and updates the
* write pointer.
* FIFO size is relative to write domain.
***************************************************************************/
task write_fifo;
begin
memory[wr_ptr] <= DIN;
wr_pntr <= #`TCQ wr_pntr + 1;
// Store the type of error injection (double/single) on write
case (C_ERROR_INJECTION_TYPE)
3: ecc_err[wr_ptr] <= {INJECTDBITERR,INJECTSBITERR};
2: ecc_err[wr_ptr] <= {INJECTDBITERR,1'b0};
1: ecc_err[wr_ptr] <= {1'b0,INJECTSBITERR};
default: ecc_err[wr_ptr] <= 0;
endcase
// (Works opposite to core: wr_ptr is a DOWN counter)
if (wr_ptr == 0) begin
wr_ptr <= C_WR_DEPTH - 1;
end else begin
wr_ptr <= wr_ptr - 1;
end
end
endtask // write_fifo
/**************************************************************************
* read_fifo
* This task reads a word from the FIFO memory and updates the read
* pointer. It's output is the ideal_dout bus.
* FIFO size is relative to write domain.
***************************************************************************/
task read_fifo;
integer i;
reg [C_DOUT_WIDTH-1:0] tmp_dout;
reg [C_DIN_WIDTH-1:0] memory_read;
reg [31:0] tmp_rd_ptr;
reg [31:0] rd_ptr_high;
reg [31:0] rd_ptr_low;
reg [1:0] tmp_ecc_err;
begin
rd_pntr <= #`TCQ rd_pntr + 1;
// output is wider than input
if (reads_per_write == 0) begin
tmp_dout = 0;
tmp_rd_ptr = (rd_ptr << log2_writes_per_read)+(writes_per_read-1);
for (i = writes_per_read - 1; i >= 0; i = i - 1) begin
tmp_dout = tmp_dout << C_DIN_WIDTH;
tmp_dout = tmp_dout | memory[tmp_rd_ptr];
// (Works opposite to core: rd_ptr is a DOWN counter)
if (tmp_rd_ptr == 0) begin
tmp_rd_ptr = C_WR_DEPTH - 1;
end else begin
tmp_rd_ptr = tmp_rd_ptr - 1;
end
end
// output is symmetric
end else if (reads_per_write == 1) begin
tmp_dout = memory[rd_ptr][C_DIN_WIDTH-1:0];
// Retreive the error injection type. Based on the error injection type
// corrupt the output data.
tmp_ecc_err = ecc_err[rd_ptr];
if (ENABLE_ERR_INJECTION && C_DIN_WIDTH == C_DOUT_WIDTH) begin
if (tmp_ecc_err[1]) begin // Corrupt the output data only for double bit error
if (C_DOUT_WIDTH == 1) begin
$display("FAILURE : Data width must be >= 2 for double bit error injection.");
$finish;
end else if (C_DOUT_WIDTH == 2)
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2]};
else
tmp_dout = {~tmp_dout[C_DOUT_WIDTH-1],~tmp_dout[C_DOUT_WIDTH-2],(tmp_dout << 2)};
end else begin
tmp_dout = tmp_dout[C_DOUT_WIDTH-1:0];
end
err_type <= {tmp_ecc_err[1], tmp_ecc_err[0] & !tmp_ecc_err[1]};
end else begin
err_type <= 0;
end
// input is wider than output
end else begin
rd_ptr_high = rd_ptr >> log2_reads_per_write;
rd_ptr_low = rd_ptr & (reads_per_write - 1);
memory_read = memory[rd_ptr_high];
tmp_dout = memory_read >> (rd_ptr_low*C_DOUT_WIDTH);
end
ideal_dout <= tmp_dout;
// (Works opposite to core: rd_ptr is a DOWN counter)
if (rd_ptr == 0) begin
rd_ptr <= C_RD_DEPTH - 1;
end else begin
rd_ptr <= rd_ptr - 1;
end
end
endtask
/*************************************************************************
* Initialize Signals for clean power-on simulation
*************************************************************************/
initial begin
num_wr_bits = 0;
num_rd_bits = 0;
next_num_wr_bits = 0;
next_num_rd_bits = 0;
rd_ptr = C_RD_DEPTH - 1;
wr_ptr = C_WR_DEPTH - 1;
wr_pntr = 0;
rd_pntr = 0;
rd_ptr_wrclk = rd_ptr;
wr_ptr_rdclk = wr_ptr;
dout_reset_val = hexstr_conv(C_DOUT_RST_VAL);
ideal_dout = dout_reset_val;
err_type = 0;
ideal_dout_d1 = dout_reset_val;
ideal_dout_both = dout_reset_val;
ideal_wr_ack = 1'b0;
ideal_valid = 1'b0;
valid_d1 = 1'b0;
valid_both = 1'b0;
ideal_overflow = C_OVERFLOW_LOW;
ideal_underflow = C_UNDERFLOW_LOW;
ideal_wr_count = 0;
ideal_rd_count = 0;
ideal_prog_full = 1'b0;
ideal_prog_empty = 1'b1;
end
/*************************************************************************
* Connect the module inputs and outputs to the internal signals of the
* behavioral model.
*************************************************************************/
//Inputs
/*
wire CLK;
wire [C_DIN_WIDTH-1:0] DIN;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_ASSERT;
wire [C_RD_PNTR_WIDTH-1:0] PROG_EMPTY_THRESH_NEGATE;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_ASSERT;
wire [C_WR_PNTR_WIDTH-1:0] PROG_FULL_THRESH_NEGATE;
wire RD_EN;
wire RST;
wire WR_EN;
*/
// Assign ALMOST_EPMTY
generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae
assign ALMOST_EMPTY = almost_empty_i;
end else begin : gnae
assign ALMOST_EMPTY = 0;
end endgenerate // gae
// Assign ALMOST_FULL
generate if (C_HAS_ALMOST_FULL==1) begin : gaf
assign ALMOST_FULL = almost_full_i;
end else begin : gnaf
assign ALMOST_FULL = 0;
end endgenerate // gaf
// Dout may change behavior based on latency
localparam C_FWFT_ENABLED = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign fwft_enabled = (C_PRELOAD_LATENCY == 0 && C_PRELOAD_REGS == 1)?
1: 0;
assign ideal_dout_out= ((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1))?
ideal_dout_d1: ideal_dout;
assign DOUT = ideal_dout_out;
// Assign SBITERR and DBITERR based on latency
assign SBITERR = (C_ERROR_INJECTION_TYPE == 1 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[0]: err_type[0];
assign DBITERR = (C_ERROR_INJECTION_TYPE == 2 || C_ERROR_INJECTION_TYPE == 3) &&
((C_USE_EMBEDDED_REG>0 && (fwft_enabled == 0)) &&
(C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1)) ?
err_type_d1[1]: err_type[1];
assign EMPTY = empty_i;
assign FULL = full_i;
//saftey_ckt with one register
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && (C_USE_EMBEDDED_REG == 1 || C_USE_EMBEDDED_REG == 2 )) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
valid_d1 <= #`TCQ valid_i;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1[0] <= #`TCQ err_type[0];
err_type_d1[1] <= #`TCQ err_type[1];
end
end
end //if
endgenerate
//safety ckt with both registers
generate
if ((C_MEMORY_TYPE==0 || C_MEMORY_TYPE==1) && C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge CLK)
begin
rst_delayed_sft1 <= #`TCQ rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always@(posedge rst_delayed_sft2 or posedge rst_i or posedge CLK)
begin
if( rst_delayed_sft2 == 1'b1 || rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
valid_d1 <= #`TCQ 1'b0;
end
else begin
ram_rd_en_d1 <= #`TCQ (RD_EN && ~(empty_i));
fab_rd_en_d1 <= #`TCQ ram_rd_en_d1;
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
always@(posedge rst_delayed_sft2 or posedge CLK)
begin
if (rst_delayed_sft2 == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end
else if (srst_rrst_busy == 1'b1) begin
if (C_USE_DOUT_RST == 1'b1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else if (ram_rd_en_d1) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both[0] <= #`TCQ err_type[0];
err_type_both[1] <= #`TCQ err_type[1];
end
if (fab_rd_en_d1) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1[0] <= #`TCQ err_type_both[0];
err_type_d1[1] <= #`TCQ err_type_both[1];
end
end
//assign SBITERR = (C_USE_ECC == 0) ? err_type[0]:err_type_d1[0];
//assign DBITERR = (C_USE_ECC == 0) ? err_type[1]:err_type_d1[1];
//assign DOUT[C_DOUT_WIDTH-1:0] = ideal_dout_d1;
end //if
endgenerate
//Overflow may be active-low
generate if (C_HAS_OVERFLOW==1) begin : gof
assign OVERFLOW = ideal_overflow ? !C_OVERFLOW_LOW : C_OVERFLOW_LOW;
end else begin : gnof
assign OVERFLOW = 0;
end endgenerate // gof
assign PROG_EMPTY = prog_empty_i;
assign PROG_FULL = prog_full_i;
//Valid may change behavior based on latency or active-low
generate if (C_HAS_VALID==1) begin : gvalid
assign valid_i = (C_PRELOAD_LATENCY == 0) ? (RD_EN & ~EMPTY) : ideal_valid;
assign valid_out = (C_PRELOAD_LATENCY == 2 && C_MEMORY_TYPE < 2) ?
valid_d1 : valid_i;
assign VALID = valid_out ? !C_VALID_LOW : C_VALID_LOW;
end else begin : gnvalid
assign VALID = 0;
end endgenerate // gvalid
//Trim data count differently depending on set widths
generate if (C_HAS_DATA_COUNT == 1) begin : gdc
always @* begin
diff_count <= wr_pntr - rd_pntr;
if (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) begin
DATA_COUNT[C_RD_PNTR_WIDTH-1:0] <= diff_count;
DATA_COUNT[C_DATA_COUNT_WIDTH-1] <= 1'b0 ;
end else begin
DATA_COUNT <= diff_count[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH];
end
end
// end else begin : gndc
// always @* DATA_COUNT <= 0;
end endgenerate // gdc
//Underflow may change behavior based on latency or active-low
generate if (C_HAS_UNDERFLOW==1) begin : guf
assign underflow_i = ideal_underflow;
assign UNDERFLOW = underflow_i ? !C_UNDERFLOW_LOW : C_UNDERFLOW_LOW;
end else begin : gnuf
assign UNDERFLOW = 0;
end endgenerate // guf
//Write acknowledge may be active low
generate if (C_HAS_WR_ACK==1) begin : gwr_ack
assign WR_ACK = ideal_wr_ack ? !C_WR_ACK_LOW : C_WR_ACK_LOW;
end else begin : gnwr_ack
assign WR_ACK = 0;
end endgenerate // gwr_ack
/*****************************************************************************
* Internal reset logic
****************************************************************************/
assign srst_i = C_HAS_SRST ? SRST : 0;
assign srst_wrst_busy = C_HAS_SRST ? (SRST || WR_RST_BUSY) : 0;
assign srst_rrst_busy = C_HAS_SRST ? (SRST || RD_RST_BUSY) : 0;
assign rst_i = C_HAS_RST ? RST : 0;
/**************************************************************************
* Assorted registers for delayed versions of signals
**************************************************************************/
//Capture delayed version of valid
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG <3)) begin : blockVL20
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
end else begin
valid_d1 <= #`TCQ valid_i;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
generate if (C_HAS_VALID == 1 && (C_USE_EMBEDDED_REG == 3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
if (srst_rrst_busy) begin
valid_d1 <= #`TCQ 1'b0;
valid_both <= #`TCQ 1'b0;
end else begin
valid_both <= #`TCQ valid_i;
valid_d1 <= #`TCQ valid_both;
end
end
end // always @ (posedge CLK or posedge rst_i)
end
endgenerate // blockVL20
// Determine which stage in FWFT registers are valid
reg stage1_valid = 0;
reg stage2_valid = 0;
generate
if (C_PRELOAD_LATENCY == 0) begin : grd_fwft_proc
always @ (posedge CLK or posedge rst_i) begin
if (rst_i) begin
stage1_valid <= #`TCQ 0;
stage2_valid <= #`TCQ 0;
end else begin
if (!stage1_valid && !stage2_valid) begin
if (!EMPTY)
stage1_valid <= #`TCQ 1'b1;
else
stage1_valid <= #`TCQ 1'b0;
end else if (stage1_valid && !stage2_valid) begin
if (EMPTY) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else if (!stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b0;
end else if (!EMPTY && !RD_EN) begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end
end else if (stage1_valid && stage2_valid) begin
if (EMPTY && RD_EN) begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b1;
end else begin
stage1_valid <= #`TCQ 1'b1;
stage2_valid <= #`TCQ 1'b1;
end
end else begin
stage1_valid <= #`TCQ 1'b0;
stage2_valid <= #`TCQ 1'b0;
end
end // rd_rst_i
end // always
end
endgenerate
//***************************************************************************
// Assign the read data count value only if it is selected,
// otherwise output zeros.
//***************************************************************************
generate
if (C_HAS_RD_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT ==1) begin : grdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = rd_data_count_i_ss[C_RD_PNTR_WIDTH:C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH];
end
endgenerate
generate
if (C_HAS_RD_DATA_COUNT == 0) begin : gnrdc
assign RD_DATA_COUNT[C_RD_DATA_COUNT_WIDTH-1:0] = {C_RD_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
//***************************************************************************
// Assign the write data count value only if it is selected,
// otherwise output zeros
//***************************************************************************
generate
if (C_HAS_WR_DATA_COUNT == 1 && C_USE_FWFT_DATA_COUNT == 1) begin : gwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = wr_data_count_i_ss[C_WR_PNTR_WIDTH:C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH] ;
end
endgenerate
generate
if (C_HAS_WR_DATA_COUNT == 0) begin : gnwdc
assign WR_DATA_COUNT[C_WR_DATA_COUNT_WIDTH-1:0] = {C_WR_DATA_COUNT_WIDTH{1'b0}};
end
endgenerate
// block memory has a synchronous reset
// no safety ckt with emb/fabric reg
//generate if (C_MEMORY_TYPE < 2 && C_EN_SAFETY_CKT == 0) begin : gen_fifo_blkmemdout_emb
// always @(posedge CLK) begin
// // BRAM resets synchronously
// // make it consistent with the core.
// if ((rst_i || srst_rrst_busy) && (C_USE_DOUT_RST == 1))
// ideal_dout_d1 <= #`TCQ dout_reset_val;
// ideal_dout_both <= #`TCQ dout_reset_val;
// end //always
//end endgenerate // gen_fifo_blkmemdout_emb
//reg ram_rd_en_d1 = 1'b0;
//Capture delayed version of dout
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG<3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
ram_rd_en_d1 <= #`TCQ 1'b0;
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout;
err_type_d1 <= #`TCQ err_type;
end
end
end
end // always
end
endgenerate
//no safety ckt with both registers
generate if (C_EN_SAFETY_CKT == 0 && (C_USE_EMBEDDED_REG==3)) begin
always @(posedge CLK or posedge rst_i) begin
if (rst_i == 1'b1) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
fab_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type_d1 <= #`TCQ 0;
// DRAM and SRAM reset asynchronously
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
@(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
ram_rd_en_d1 <= #`TCQ RD_EN & ~EMPTY;
fab_rd_en_d1 <= #`TCQ (ram_rd_en_d1);
if (srst_rrst_busy) begin
ram_rd_en_d1 <= #`TCQ 1'b0;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0) begin
err_type_d1 <= #`TCQ 0;
end
// Reset DRAM and SRAM based FIFO, BRAM based FIFO is reset above
if ((C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3) && C_USE_DOUT_RST == 1) begin
ideal_dout_d1 <= #`TCQ dout_reset_val;
// ideal_dout_both <= #`TCQ dout_reset_val;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge CLK)
ideal_dout_d1 <= #`TCQ dout_reset_val;
// ideal_dout_both <= #`TCQ dout_reset_val;
end
end else begin
if (ram_rd_en_d1 ) begin
ideal_dout_both <= #`TCQ ideal_dout;
err_type_both <= #`TCQ err_type;
end
if (fab_rd_en_d1 ) begin
ideal_dout_d1 <= #`TCQ ideal_dout_both;
err_type_d1 <= #`TCQ err_type_both;
end
end
end
end // always
end
endgenerate
/**************************************************************************
* Overflow and Underflow Flag calculation
* (handled separately because they don't support rst)
**************************************************************************/
generate if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 0) begin : g7s_ovflw
always @(posedge CLK) begin
ideal_overflow <= #`TCQ WR_EN & full_i;
end
end else if (C_HAS_OVERFLOW == 1 && IS_8SERIES == 1) begin : g8s_ovflw
always @(posedge CLK) begin
//ideal_overflow <= #`TCQ WR_EN & (rst_i | full_i);
ideal_overflow <= #`TCQ WR_EN & (WR_RST_BUSY | full_i);
end
end endgenerate // blockOF20
generate if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 0) begin : g7s_unflw
always @(posedge CLK) begin
ideal_underflow <= #`TCQ empty_i & RD_EN;
end
end else if (C_HAS_UNDERFLOW == 1 && IS_8SERIES == 1) begin : g8s_unflw
always @(posedge CLK) begin
//ideal_underflow <= #`TCQ (rst_i | empty_i) & RD_EN;
ideal_underflow <= #`TCQ (RD_RST_BUSY | empty_i) & RD_EN;
end
end endgenerate // blockUF20
/**************************
* Read Data Count
*************************/
reg [31:0] num_read_words_dc;
reg [C_RD_DATA_COUNT_WIDTH-1:0] num_read_words_sized_i;
always @(num_rd_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//If using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain,
// and add two read words for FWFT stages
//This value is only a temporary value and not used in the code.
num_read_words_dc = (num_rd_bits/C_DOUT_WIDTH+2);
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH+1];
end else begin
//If not using extra logic for FWFT Data Counts,
// then scale FIFO contents to read domain.
//This value is only a temporary value and not used in the code.
num_read_words_dc = num_rd_bits/C_DOUT_WIDTH;
//Trim the read words for use with RD_DATA_COUNT
num_read_words_sized_i =
num_read_words_dc[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/**************************
* Write Data Count
*************************/
reg [31:0] num_write_words_dc;
reg [C_WR_DATA_COUNT_WIDTH-1:0] num_write_words_sized_i;
always @(num_wr_bits) begin
if (C_USE_FWFT_DATA_COUNT) begin
//Calculate the Data Count value for the number of write words,
// when using First-Word Fall-Through with extra logic for Data
// Counts. This takes into consideration the number of words that
// are expected to be stored in the FWFT register stages (it always
// assumes they are filled).
//This value is scaled to the Write Domain.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//EXTRA_WORDS_DC is the number of words added to write_words
// due to FWFT.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? EXTRA_WORDS_DC : (((num_wr_bits-1)/C_DIN_WIDTH)+1) + EXTRA_WORDS_DC ;
//Trim the write words for use with WR_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH+1];
end else begin
//Calculate the Data Count value for the number of write words, when NOT
// using First-Word Fall-Through with extra logic for Data Counts. This
// calculates only the number of words in the internal FIFO.
//The expression (((A-1)/B))+1 divides A/B, but takes the
// ceiling of the result.
//This value is scaled to the Write Domain.
//When num_wr_bits==0, set the result manually to prevent
// division errors.
//This value is only a temporary value and not used in the code.
num_write_words_dc = (num_wr_bits==0) ? 0 : ((num_wr_bits-1)/C_DIN_WIDTH)+1;
//Trim the read words for use with RD_DATA_COUNT
num_write_words_sized_i =
num_write_words_dc[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_WR_DATA_COUNT_WIDTH];
end //if (C_USE_FWFT_DATA_COUNT)
end //always
/*************************************************************************
* Write and Read Logic
************************************************************************/
wire write_allow;
wire read_allow;
wire read_allow_dc;
wire write_only;
wire read_only;
//wire write_only_q;
reg write_only_q;
//wire read_only_q;
reg read_only_q;
reg full_reg;
reg rst_full_ff_reg1;
reg rst_full_ff_reg2;
wire ram_full_comb;
wire carry;
assign write_allow = WR_EN & ~full_i;
assign read_allow = RD_EN & ~empty_i;
assign read_allow_dc = RD_EN_USER & ~USER_EMPTY_FB;
//assign write_only = write_allow & ~read_allow;
//assign write_only_q = write_allow_q;
//assign read_only = read_allow & ~write_allow;
//assign read_only_q = read_allow_q ;
wire [C_WR_PNTR_WIDTH-1:0] diff_pntr;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg1 = 0;
reg [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_reg1 = 0;
reg [C_RD_PNTR_WIDTH:0] diff_pntr_pe_asym = 0;
wire [C_RD_PNTR_WIDTH:0] adj_wr_pntr_rd_asym ;
wire [C_RD_PNTR_WIDTH:0] rd_pntr_asym;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_reg2 = 0;
reg [C_WR_PNTR_WIDTH-1:0] diff_pntr_pe_reg2 = 0;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_pe_max;
wire [C_RD_PNTR_WIDTH-1:0] diff_pntr_max;
assign diff_pntr_pe_max = DIFF_MAX_RD;
assign diff_pntr_max = DIFF_MAX_WR;
generate if (IS_ASYMMETRY == 0) begin : diff_pntr_sym
assign write_only = write_allow & ~read_allow;
assign read_only = read_allow & ~write_allow;
end endgenerate
generate if ( IS_ASYMMETRY == 1 && C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : wr_grt_rd
assign read_only = read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]) & ~write_allow;
assign write_only = write_allow & ~(read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (IS_ASYMMETRY ==1 && C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : rd_grt_wr
assign read_only = read_allow & ~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
assign write_only = write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]) & ~read_allow;
end endgenerate
//-----------------------------------------------------------------------------
// Write and Read pointer generation
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i) begin
wr_pntr <= 0;
rd_pntr <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy ) begin
if (srst_wrst_busy)
wr_pntr <= #`TCQ 0;
if (srst_rrst_busy)
rd_pntr <= #`TCQ 0;
end else begin
if (write_allow) wr_pntr <= #`TCQ wr_pntr + 1;
if (read_allow) rd_pntr <= #`TCQ rd_pntr + 1;
end
end
end
generate if (C_FIFO_TYPE == 2) begin : gll_dm_dout
always @(posedge CLK) begin
if (write_allow) begin
if (ENABLE_ERR_INJECTION == 1)
memory[wr_pntr] <= #`TCQ {INJECTDBITERR,INJECTSBITERR,DIN};
else
memory[wr_pntr] <= #`TCQ DIN;
end
end
reg [C_DATA_WIDTH-1:0] dout_tmp_q;
reg [C_DATA_WIDTH-1:0] dout_tmp = 0;
reg [C_DATA_WIDTH-1:0] dout_tmp1 = 0;
always @(posedge CLK) begin
dout_tmp_q <= #`TCQ ideal_dout;
end
always @* begin
if (read_allow)
ideal_dout <= memory[rd_pntr];
else
ideal_dout <= dout_tmp_q;
end
end endgenerate // gll_dm_dout
/**************************************************************************
* Write Domain Logic
**************************************************************************/
assign ram_rd_en = RD_EN & !EMPTY;
//reg [C_WR_PNTR_WIDTH-1:0] diff_pntr = 0;
generate if (C_FIFO_TYPE != 2) begin : gnll_din
always @(posedge CLK or posedge rst_i) begin : gen_fifo_w
/****** Reset fifo (case 1)***************************************/
if (rst_i == 1'b1) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin //rst_i==0
if (srst_wrst_busy) begin
num_wr_bits <= #`TCQ 0;
next_num_wr_bits = #`TCQ 0;
wr_ptr <= #`TCQ C_WR_DEPTH - 1;
rd_ptr_wrclk <= #`TCQ C_RD_DEPTH - 1;
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ 0;
tmp_wr_listsize = #`TCQ 0;
rd_ptr_wrclk_next <= #`TCQ 0;
wr_pntr <= #`TCQ 0;
wr_pntr_rd1 <= #`TCQ 0;
end else begin//srst_i=0
wr_pntr_rd1 <= #`TCQ wr_pntr;
//Determine the current number of words in the FIFO
tmp_wr_listsize = (C_DEPTH_RATIO_RD > 1) ? num_wr_bits/C_DOUT_WIDTH :
num_wr_bits/C_DIN_WIDTH;
rd_ptr_wrclk_next = rd_ptr;
if (rd_ptr_wrclk < rd_ptr_wrclk_next) begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk + C_RD_DEPTH
- rd_ptr_wrclk_next);
end else begin
next_num_wr_bits = num_wr_bits -
C_DOUT_WIDTH*(rd_ptr_wrclk - rd_ptr_wrclk_next);
end
if (WR_EN == 1'b1) begin
if (FULL == 1'b1) begin
ideal_wr_ack <= #`TCQ 0;
//Reminder that FIFO is still full
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end else begin
write_fifo;
next_num_wr_bits = next_num_wr_bits + C_DIN_WIDTH;
//Write successful, so issue acknowledge
// and no error
ideal_wr_ack <= #`TCQ 1;
//Not even close to full.
ideal_wr_count <= num_write_words_sized_i;
//end
end
end else begin //(WR_EN == 1'b1)
//If user did not attempt a write, then do not
// give ack or err
ideal_wr_ack <= #`TCQ 0;
ideal_wr_count <= #`TCQ num_write_words_sized_i;
end
num_wr_bits <= #`TCQ next_num_wr_bits;
rd_ptr_wrclk <= #`TCQ rd_ptr;
end //srst_i==0
end //wr_rst_i==0
end // gen_fifo_w
end endgenerate
generate if (C_FIFO_TYPE < 2 && C_MEMORY_TYPE < 2 && C_EN_SAFETY_CKT == 0) begin : gnll_dm_dout
always @(posedge CLK) begin
if (rst_i || srst_rrst_busy) begin
if (C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
ideal_dout_both <= #`TCQ dout_reset_val;
end
end
end endgenerate
generate if (C_FIFO_TYPE != 2) begin : gnll_dout
always @(posedge CLK or posedge rst_i) begin : gen_fifo_r
/****** Reset fifo (case 1)***************************************/
if (rst_i) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets asynchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type <= #`TCQ 0;
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end else begin //rd_rst_i==0
if (srst_rrst_busy) begin
num_rd_bits <= #`TCQ 0;
next_num_rd_bits = #`TCQ 0;
rd_ptr <= #`TCQ C_RD_DEPTH -1;
rd_pntr <= #`TCQ 0;
//rd_pntr_wr1 <= #`TCQ 0;
wr_ptr_rdclk <= #`TCQ C_WR_DEPTH -1;
// DRAM resets synchronously
if (C_FIFO_TYPE < 2 && (C_MEMORY_TYPE == 2 || C_MEMORY_TYPE == 3 )&& C_USE_DOUT_RST == 1)
ideal_dout <= #`TCQ dout_reset_val;
// Reset err_type only if ECC is not selected
if (C_USE_ECC == 0)
err_type <= #`TCQ 0;
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ 0;
end //srst_i
else begin
//rd_pntr_wr1 <= #`TCQ rd_pntr;
//Determine the current number of words in the FIFO
tmp_rd_listsize = (C_DEPTH_RATIO_WR > 1) ? num_rd_bits/C_DIN_WIDTH :
num_rd_bits/C_DOUT_WIDTH;
wr_ptr_rdclk_next = wr_ptr;
if (wr_ptr_rdclk < wr_ptr_rdclk_next) begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk +C_WR_DEPTH
- wr_ptr_rdclk_next);
end else begin
next_num_rd_bits = num_rd_bits +
C_DIN_WIDTH*(wr_ptr_rdclk - wr_ptr_rdclk_next);
end
if (RD_EN == 1'b1) begin
if (EMPTY == 1'b1) begin
ideal_valid <= #`TCQ 1'b0;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end
else
begin
read_fifo;
next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
//Acknowledge the read from the FIFO, no error
ideal_valid <= #`TCQ 1'b1;
ideal_rd_count <= #`TCQ num_read_words_sized_i;
end // if (tmp_rd_listsize == 2)
end
num_rd_bits <= #`TCQ next_num_rd_bits;
wr_ptr_rdclk <= #`TCQ wr_ptr;
end //s_rst_i==0
end //rd_rst_i==0
end //always
end endgenerate
//-----------------------------------------------------------------------------
// Generate diff_pntr for PROG_FULL generation
// Generate diff_pntr_pe for PROG_EMPTY generation
//-----------------------------------------------------------------------------
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 0) begin : reg_write_allow
always @(posedge CLK ) begin
if (rst_i) begin
write_only_q <= 1'b0;
read_only_q <= 1'b0;
diff_pntr_reg1 <= 0;
diff_pntr_pe_reg1 <= 0;
diff_pntr_reg2 <= 0;
diff_pntr_pe_reg2 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_rrst_busy) begin
read_only_q <= #`TCQ 1'b0;
diff_pntr_pe_reg1 <= #`TCQ 0;
diff_pntr_pe_reg2 <= #`TCQ 0;
end
if (srst_wrst_busy) begin
write_only_q <= #`TCQ 1'b0;
diff_pntr_reg1 <= #`TCQ 0;
diff_pntr_reg2 <= #`TCQ 0;
end
end else begin
write_only_q <= #`TCQ write_only;
read_only_q <= #`TCQ read_only;
diff_pntr_reg2 <= #`TCQ diff_pntr_reg1;
diff_pntr_pe_reg2 <= #`TCQ diff_pntr_pe_reg1;
// Add 1 to the difference pointer value when only write happens.
if (write_only)
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr + 1;
else
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
// Add 1 to the difference pointer value when write or both write & read or no write & read happen.
if (read_only)
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr - 1;
else
diff_pntr_pe_reg1 <= #`TCQ adj_wr_pntr_rd - rd_pntr;
end
end
end
assign diff_pntr_pe = diff_pntr_pe_reg1;
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow
generate if ((C_PROG_FULL_TYPE != 0 || C_PROG_EMPTY_TYPE != 0) && IS_ASYMMETRY == 1) begin : reg_write_allow_asym
assign adj_wr_pntr_rd_asym[C_RD_PNTR_WIDTH:0] = {adj_wr_pntr_rd,1'b1};
assign rd_pntr_asym[C_RD_PNTR_WIDTH:0] = {~rd_pntr,1'b1};
always @(posedge CLK ) begin
if (rst_i) begin
diff_pntr_pe_asym <= 0;
diff_pntr_reg1 <= 0;
full_reg <= 0;
rst_full_ff_reg1 <= 1;
rst_full_ff_reg2 <= 1;
diff_pntr_pe_reg1 <= 0;
end else begin
if (srst_i || srst_wrst_busy || srst_rrst_busy) begin
if (srst_wrst_busy)
diff_pntr_reg1 <= #`TCQ 0;
if (srst_rrst_busy)
full_reg <= #`TCQ 0;
rst_full_ff_reg1 <= #`TCQ 1;
rst_full_ff_reg2 <= #`TCQ 1;
diff_pntr_pe_asym <= #`TCQ 0;
diff_pntr_pe_reg1 <= #`TCQ 0;
end else begin
diff_pntr_pe_asym <= #`TCQ adj_wr_pntr_rd_asym + rd_pntr_asym;
full_reg <= #`TCQ full_i;
rst_full_ff_reg1 <= #`TCQ RST_FULL_FF;
rst_full_ff_reg2 <= #`TCQ rst_full_ff_reg1;
if (~full_i) begin
diff_pntr_reg1 <= #`TCQ wr_pntr - adj_rd_pntr_wr;
end
end
end
end
assign carry = (~(|(diff_pntr_pe_asym [C_RD_PNTR_WIDTH : 1])));
assign diff_pntr_pe = (full_reg && ~rst_full_ff_reg2 && carry ) ? diff_pntr_pe_max : diff_pntr_pe_asym[C_RD_PNTR_WIDTH:1];
assign diff_pntr = diff_pntr_reg1;
end endgenerate // reg_write_allow_asym
//-----------------------------------------------------------------------------
// Generate FULL flag
//-----------------------------------------------------------------------------
wire comp0;
wire comp1;
wire going_full;
wire leaving_full;
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gpad
assign adj_rd_pntr_wr [C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH] = rd_pntr;
assign adj_rd_pntr_wr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) begin : gtrim
assign adj_rd_pntr_wr = rd_pntr[C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
assign comp1 = (adj_rd_pntr_wr == (wr_pntr + 1'b1));
assign comp0 = (adj_rd_pntr_wr == wr_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gf_wp_eq_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full = (comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gf_asym
assign going_full = (comp1 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_full = (comp0 & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gf_wp_gt_rp
assign going_full = (comp1 & write_allow & ~read_allow);
assign leaving_full =(comp0 & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_full_comb = going_full | (~leaving_full & full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
full_i <= #`TCQ ram_full_comb;
end
//-----------------------------------------------------------------------------
// Generate EMPTY flag
//-----------------------------------------------------------------------------
wire ecomp0;
wire ecomp1;
wire going_empty;
wire leaving_empty;
wire ram_empty_comb;
generate if (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) begin : pad
assign adj_wr_pntr_rd [C_RD_PNTR_WIDTH-1 : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH] = wr_pntr;
assign adj_wr_pntr_rd[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0] = 0;
end endgenerate
generate if (C_RD_PNTR_WIDTH <= C_WR_PNTR_WIDTH) begin : trim
assign adj_wr_pntr_rd = wr_pntr[C_WR_PNTR_WIDTH-1 : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
assign ecomp1 = (adj_wr_pntr_rd == (rd_pntr + 1'b1));
assign ecomp0 = (adj_wr_pntr_rd == rd_pntr);
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : ge_wp_eq_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty = (ecomp0 & write_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : ge_wp_gt_rp
assign going_empty = (ecomp1 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_empty = (ecomp0 & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : ge_wp_lt_rp
assign going_empty = (ecomp1 & ~write_allow & read_allow);
assign leaving_empty =(ecomp0 & write_allow);
end endgenerate
assign ram_empty_comb = going_empty | (~leaving_empty & empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
empty_i <= 1'b1;
else if (srst_rrst_busy)
empty_i <= #`TCQ 1'b1;
else
empty_i <= #`TCQ ram_empty_comb;
end
//-----------------------------------------------------------------------------
// Generate Read and write data counts for asymmetic common clock
//-----------------------------------------------------------------------------
reg [C_GRTR_PNTR_WIDTH :0] count_dc = 0;
wire [C_GRTR_PNTR_WIDTH :0] ratio;
wire decr_by_one;
wire incr_by_ratio;
wire incr_by_one;
wire decr_by_ratio;
localparam IS_FWFT = (C_PRELOAD_REGS == 1 && C_PRELOAD_LATENCY == 0) ? 1 : 0;
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : rd_depth_gt_wr
assign ratio = C_DEPTH_RATIO_RD;
assign decr_by_one = (IS_FWFT == 1)? read_allow_dc : read_allow;
assign incr_by_ratio = write_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (decr_by_one) begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc - 1;
else
count_dc <= #`TCQ count_dc - 1 + ratio ;
end
else begin
if (!incr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc + ratio ;
end
end
end
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc;
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc[C_RD_PNTR_WIDTH : C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH];
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : wr_depth_gt_rd
assign ratio = C_DEPTH_RATIO_WR;
assign incr_by_one = write_allow;
assign decr_by_ratio = (IS_FWFT == 1)? read_allow_dc : read_allow;
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
count_dc <= #`TCQ 0;
else if (srst_wrst_busy)
count_dc <= #`TCQ 0;
else begin
if (incr_by_one) begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc + 1;
else
count_dc <= #`TCQ count_dc + 1 - ratio ;
end
else begin
if (!decr_by_ratio)
count_dc <= #`TCQ count_dc ;
else
count_dc <= #`TCQ count_dc - ratio ;
end
end
end
assign wr_data_count_i_ss[C_WR_PNTR_WIDTH : 0] = count_dc;
assign rd_data_count_i_ss[C_RD_PNTR_WIDTH : 0] = count_dc[C_WR_PNTR_WIDTH : C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH];
end endgenerate
//-----------------------------------------------------------------------------
// Generate WR_ACK flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_wr_ack <= 1'b0;
else if (srst_wrst_busy)
ideal_wr_ack <= #`TCQ 1'b0;
else if (WR_EN & ~full_i)
ideal_wr_ack <= #`TCQ 1'b1;
else
ideal_wr_ack <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate VALID flag
//-----------------------------------------------------------------------------
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
ideal_valid <= 1'b0;
else if (srst_rrst_busy)
ideal_valid <= #`TCQ 1'b0;
else if (RD_EN & ~empty_i)
ideal_valid <= #`TCQ 1'b1;
else
ideal_valid <= #`TCQ 1'b0;
end
//-----------------------------------------------------------------------------
// Generate ALMOST_FULL flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_FULL == 1 || C_PROG_FULL_TYPE > 2 || C_PROG_EMPTY_TYPE > 2) begin : gaf_ss
wire fcomp2;
wire going_afull;
wire leaving_afull;
wire ram_afull_comb;
assign fcomp2 = (adj_rd_pntr_wr == (wr_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gaf_wp_eq_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull = (comp1 & read_allow & ~write_allow) | RST_FULL_GEN;
end endgenerate
// Write data width is bigger than read data width
// Write depth is smaller than read depth
// One write could be equal to 2 or 4 or 8 reads
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gaf_asym
assign going_afull = (fcomp2 & write_allow & (~ (read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0]))));
assign leaving_afull = (comp1 & (~write_allow) & read_allow & &(rd_pntr[C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 : 0])) | RST_FULL_GEN;
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gaf_wp_gt_rp
assign going_afull = (fcomp2 & write_allow & ~read_allow);
assign leaving_afull =((comp0 | comp1 | fcomp2) & read_allow) | RST_FULL_GEN;
end endgenerate
assign ram_afull_comb = going_afull | (~leaving_afull & almost_full_i);
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF)
almost_full_i <= C_FULL_FLAGS_RST_VAL;
else if (srst_wrst_busy)
almost_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else
almost_full_i <= #`TCQ ram_afull_comb;
end
// end endgenerate // gaf_ss
//-----------------------------------------------------------------------------
// Generate ALMOST_EMPTY flag
//-----------------------------------------------------------------------------
//generate if (C_HAS_ALMOST_EMPTY == 1) begin : gae_ss
wire ecomp2;
wire going_aempty;
wire leaving_aempty;
wire ram_aempty_comb;
assign ecomp2 = (adj_wr_pntr_rd == (rd_pntr + 2'h2));
generate if (C_WR_PNTR_WIDTH == C_RD_PNTR_WIDTH) begin : gae_wp_eq_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty = (ecomp1 & write_allow & ~read_allow);
end endgenerate
generate if (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) begin : gae_wp_gt_rp
assign going_aempty = (ecomp2 & read_allow & (~(write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]))));
assign leaving_aempty = (ecomp1 & ~read_allow & write_allow & &(wr_pntr[C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 : 0]));
end endgenerate
generate if (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) begin : gae_wp_lt_rp
assign going_aempty = (ecomp2 & ~write_allow & read_allow);
assign leaving_aempty =((ecomp2 | ecomp1 |ecomp0) & write_allow);
end endgenerate
assign ram_aempty_comb = going_aempty | (~leaving_aempty & almost_empty_i);
always @(posedge CLK or posedge rst_i) begin
if (rst_i)
almost_empty_i <= 1'b1;
else if (srst_rrst_busy)
almost_empty_i <= #`TCQ 1'b1;
else
almost_empty_i <= #`TCQ ram_aempty_comb;
end
// end endgenerate // gae_ss
//-----------------------------------------------------------------------------
// Generate PROG_FULL
//-----------------------------------------------------------------------------
localparam C_PF_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_PF_PARAM : // FWFT
C_PROG_FULL_THRESH_ASSERT_VAL; // STD
localparam C_PF_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_PF_PARAM: // FWFT
C_PROG_FULL_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold constant
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] temp = C_PF_ASSERT_VAL;
generate if (C_PROG_FULL_TYPE == 1) begin : single_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_ASSERT_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr>= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr) < C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b0;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate // single_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_FULL_TYPE == 2) begin : multiple_pf_const
always @(posedge CLK or posedge RST_FULL_FF) begin
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (diff_pntr == C_PF_ASSERT_VAL && write_only_q)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == C_PF_NEGATE_VAL && read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~RST_FULL_GEN ) begin
if (diff_pntr >= C_PF_ASSERT_VAL )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < C_PF_NEGATE_VAL)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_const
//-----------------------------------------------------------------------------
// Generate PROG_FULL for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf3_assert_val = (C_PRELOAD_LATENCY == 0) ?
PROG_FULL_THRESH - EXTRA_WORDS_PF: // FWFT
PROG_FULL_THRESH; // STD
generate if (C_PROG_FULL_TYPE == 3) begin : single_pf_input
always @(posedge CLK or posedge RST_FULL_FF) begin//0
//if (RST_FULL_FF)
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin //1
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin//2
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin//3
if (diff_pntr > pf3_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr == pf3_assert_val) begin//4
if (read_only_q)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ 1'b1;
end else//4
prog_full_i <= #`TCQ 1'b0;
end else//3
prog_full_i <= #`TCQ prog_full_i;
end //2
else begin//5
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin//6
if (diff_pntr >= pf3_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf3_assert_val) begin//7
prog_full_i <= #`TCQ 1'b0;
end//7
end//6
else
prog_full_i <= #`TCQ prog_full_i;
end//5
end//1
end//0
end endgenerate //single_pf_input
//-----------------------------------------------------------------------------
// Generate PROG_FULL for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_WR_PNTR_WIDTH-1:0] pf_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_ASSERT -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_ASSERT; // STD
wire [C_WR_PNTR_WIDTH-1:0] pf_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_FULL_THRESH_NEGATE -EXTRA_WORDS_PF) : // FWFT
PROG_FULL_THRESH_NEGATE; // STD
generate if (C_PROG_FULL_TYPE == 4) begin : multiple_pf_inputs
always @(posedge CLK or posedge RST_FULL_FF) begin
if (RST_FULL_FF && C_HAS_RST)
prog_full_i <= C_FULL_FLAGS_RST_VAL;
else begin
if (srst_wrst_busy)
prog_full_i <= #`TCQ C_FULL_FLAGS_RST_VAL;
else if (IS_ASYMMETRY == 0) begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~almost_full_i) begin
if (diff_pntr >= pf_assert_val)
prog_full_i <= #`TCQ 1'b1;
else if ((diff_pntr == pf_negate_val && read_only_q) ||
diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end else
prog_full_i <= #`TCQ prog_full_i;
end
else begin
if (RST_FULL_GEN)
prog_full_i <= #`TCQ 1'b0;
else if (~full_i ) begin
if (diff_pntr >= pf_assert_val )
prog_full_i <= #`TCQ 1'b1;
else if (diff_pntr < pf_negate_val)
prog_full_i <= #`TCQ 1'b0;
else
prog_full_i <= #`TCQ prog_full_i;
end
else
prog_full_i <= #`TCQ prog_full_i;
end
end
end
end endgenerate //multiple_pf_inputs
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY
//-----------------------------------------------------------------------------
localparam C_PE_ASSERT_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_ASSERT_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_ASSERT_VAL; // STD
localparam C_PE_NEGATE_VAL = (C_PRELOAD_LATENCY == 0) ?
C_PROG_EMPTY_THRESH_NEGATE_VAL - 2: // FWFT
C_PROG_EMPTY_THRESH_NEGATE_VAL; // STD
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold constant
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 1) begin : single_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_ASSERT_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_ASSERT_VAL)
prog_empty_i <= #`TCQ 1'b0;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold constants
//-----------------------------------------------------------------------------
generate if (C_PROG_EMPTY_TYPE == 2) begin : multiple_pe_const
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (diff_pntr_pe == C_PE_ASSERT_VAL && read_only_q)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == C_PE_NEGATE_VAL && write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (~rst_i ) begin
if (diff_pntr_pe <= C_PE_ASSERT_VAL )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > C_PE_NEGATE_VAL)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate //multiple_pe_const
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for single programmable threshold input port
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe3_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH -2) : // FWFT
PROG_EMPTY_THRESH; // STD
generate if (C_PROG_EMPTY_TYPE == 3) begin : single_pe_input
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe < pe3_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe == pe3_assert_val) begin
if (write_only_q)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ 1'b1;
end else
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe3_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe3_assert_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // single_pe_input
//-----------------------------------------------------------------------------
// Generate PROG_EMPTY for multiple programmable threshold input ports
//-----------------------------------------------------------------------------
wire [C_RD_PNTR_WIDTH-1:0] pe4_assert_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_ASSERT - 2) : // FWFT
PROG_EMPTY_THRESH_ASSERT; // STD
wire [C_RD_PNTR_WIDTH-1:0] pe4_negate_val = (C_PRELOAD_LATENCY == 0) ?
(PROG_EMPTY_THRESH_NEGATE - 2) : // FWFT
PROG_EMPTY_THRESH_NEGATE; // STD
generate if (C_PROG_EMPTY_TYPE == 4) begin : multiple_pe_inputs
always @(posedge CLK or posedge rst_i) begin
//if (rst_i)
if (rst_i && C_HAS_RST)
prog_empty_i <= 1'b1;
else begin
if (srst_rrst_busy)
prog_empty_i <= #`TCQ 1'b1;
else if (IS_ASYMMETRY == 0) begin
if (~almost_full_i) begin
if (diff_pntr_pe <= pe4_assert_val)
prog_empty_i <= #`TCQ 1'b1;
else if (((diff_pntr_pe == pe4_negate_val) && write_only_q) ||
(diff_pntr_pe > pe4_negate_val)) begin
prog_empty_i <= #`TCQ 1'b0;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end else
prog_empty_i <= #`TCQ prog_empty_i;
end
else begin
if (diff_pntr_pe <= pe4_assert_val )
prog_empty_i <= #`TCQ 1'b1;
else if (diff_pntr_pe > pe4_negate_val)
prog_empty_i <= #`TCQ 1'b0;
else
prog_empty_i <= #`TCQ prog_empty_i;
end
end
end
end endgenerate // multiple_pe_inputs
endmodule // fifo_generator_v13_1_0_bhv_ver_ss
/**************************************************************************
* First-Word Fall-Through module (preload 0)
**************************************************************************/
module fifo_generator_v13_1_0_bhv_ver_preload0
#(
parameter C_DOUT_RST_VAL = "",
parameter C_DOUT_WIDTH = 8,
parameter C_HAS_RST = 0,
parameter C_ENABLE_RST_SYNC = 0,
parameter C_HAS_SRST = 0,
parameter C_USE_EMBEDDED_REG = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_USE_DOUT_RST = 0,
parameter C_USE_ECC = 0,
parameter C_USERVALID_LOW = 0,
parameter C_USERUNDERFLOW_LOW = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_FIFO_TYPE = 0
)
(
//Inputs
input RD_CLK,
input RD_RST,
input SRST,
input WR_RST_BUSY,
input RD_RST_BUSY,
input RD_EN,
input FIFOEMPTY,
input [C_DOUT_WIDTH-1:0] FIFODATA,
input FIFOSBITERR,
input FIFODBITERR,
//Outputs
output reg [C_DOUT_WIDTH-1:0] USERDATA,
output reg [C_DOUT_WIDTH-1:0] USERDATA_BOTH,
output USERVALID,
output USERVALID_BOTH,
output USERVALID_ONE,
output USERUNDERFLOW,
output USEREMPTY,
output USERALMOSTEMPTY,
output RAMVALID,
output FIFORDEN,
output reg USERSBITERR,
output reg USERDBITERR,
output reg USERSBITERR_BOTH,
output reg USERDBITERR_BOTH,
output reg STAGE2_REG_EN,
output fab_read_data_valid_i_o,
output read_data_valid_i_o,
output ram_valid_i_o,
output [1:0] VALID_STAGES
);
//Internal signals
wire preloadstage1;
wire preloadstage2;
reg ram_valid_i;
reg fab_valid;
reg read_data_valid_i;
reg fab_read_data_valid_i;
reg fab_read_data_valid_i_1;
reg ram_valid_i_d;
reg read_data_valid_i_d;
reg fab_read_data_valid_i_d;
wire ram_regout_en;
reg ram_regout_en_d1;
reg ram_regout_en_d2;
wire fab_regout_en;
wire ram_rd_en;
reg empty_i = 1'b1;
reg empty_q = 1'b1;
reg rd_en_q = 1'b0;
reg almost_empty_i = 1'b1;
reg almost_empty_q = 1'b1;
wire rd_rst_i;
wire srst_i;
assign ram_valid_i_o = ram_valid_i;
assign read_data_valid_i_o = read_data_valid_i;
assign fab_read_data_valid_i_o = fab_read_data_valid_i;
/*************************************************************************
* FUNCTIONS
*************************************************************************/
/*************************************************************************
* hexstr_conv
* Converts a string of type hex to a binary value (for C_DOUT_RST_VAL)
***********************************************************************/
function [C_DOUT_WIDTH-1:0] hexstr_conv;
input [(C_DOUT_WIDTH*8)-1:0] def_data;
integer index,i,j;
reg [3:0] bin;
begin
index = 0;
hexstr_conv = 'b0;
for( i=C_DOUT_WIDTH-1; i>=0; i=i-1 )
begin
case (def_data[7:0])
8'b00000000 :
begin
bin = 4'b0000;
i = -1;
end
8'b00110000 : bin = 4'b0000;
8'b00110001 : bin = 4'b0001;
8'b00110010 : bin = 4'b0010;
8'b00110011 : bin = 4'b0011;
8'b00110100 : bin = 4'b0100;
8'b00110101 : bin = 4'b0101;
8'b00110110 : bin = 4'b0110;
8'b00110111 : bin = 4'b0111;
8'b00111000 : bin = 4'b1000;
8'b00111001 : bin = 4'b1001;
8'b01000001 : bin = 4'b1010;
8'b01000010 : bin = 4'b1011;
8'b01000011 : bin = 4'b1100;
8'b01000100 : bin = 4'b1101;
8'b01000101 : bin = 4'b1110;
8'b01000110 : bin = 4'b1111;
8'b01100001 : bin = 4'b1010;
8'b01100010 : bin = 4'b1011;
8'b01100011 : bin = 4'b1100;
8'b01100100 : bin = 4'b1101;
8'b01100101 : bin = 4'b1110;
8'b01100110 : bin = 4'b1111;
default :
begin
bin = 4'bx;
end
endcase
for( j=0; j<4; j=j+1)
begin
if ((index*4)+j < C_DOUT_WIDTH)
begin
hexstr_conv[(index*4)+j] = bin[j];
end
end
index = index + 1;
def_data = def_data >> 8;
end
end
endfunction
//*************************************************************************
// Set power-on states for regs
//*************************************************************************
initial begin
ram_valid_i = 1'b0;
fab_valid = 1'b0;
read_data_valid_i = 1'b0;
fab_read_data_valid_i = 1'b0;
fab_read_data_valid_i_1 = 1'b0;
USERDATA = hexstr_conv(C_DOUT_RST_VAL);
USERDATA_BOTH = hexstr_conv(C_DOUT_RST_VAL);
USERSBITERR = 1'b0;
USERDBITERR = 1'b0;
end //initial
//***************************************************************************
// connect up optional reset
//***************************************************************************
assign rd_rst_i = (C_HAS_RST == 1 || C_ENABLE_RST_SYNC == 0) ? RD_RST : 0;
assign srst_i = C_HAS_SRST ? SRST || WR_RST_BUSY || RD_RST_BUSY : 0;
localparam INVALID = 0;
localparam STAGE1_VALID = 2;
localparam STAGE2_VALID = 1;
localparam BOTH_STAGES_VALID = 3;
reg [1:0] curr_fwft_state = INVALID;
reg [1:0] next_fwft_state = INVALID;
generate if (C_USE_EMBEDDED_REG < 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = preloadstage2;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = (RD_EN & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
reg curr_state = 0;
reg next_state = 0;
reg leaving_empty_fwft = 0;
reg going_empty_fwft = 0;
reg empty_i_q = 0;
reg ram_rd_en_fwft = 0;
generate if (C_FIFO_TYPE == 2) begin : gll_fifo
always @* begin // FSM fo FWFT
case (curr_state)
1'b0: begin
if (~FIFOEMPTY)
next_state <= 1'b1;
else
next_state <= 1'b0;
end
1'b1: begin
if (FIFOEMPTY && RD_EN)
next_state <= 1'b0;
else
next_state <= 1'b1;
end
default: next_state <= 1'b0;
endcase
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
empty_i <= 1'b1;
empty_i_q <= 1'b1;
curr_state <= 1'b0;
ram_valid_i <= 1'b0;
end else if (srst_i) begin
empty_i <= #`TCQ 1'b1;
empty_i_q <= #`TCQ 1'b1;
curr_state <= #`TCQ 1'b0;
ram_valid_i <= #`TCQ 1'b0;
end else begin
empty_i <= #`TCQ going_empty_fwft | (~leaving_empty_fwft & empty_i);
empty_i_q <= #`TCQ FIFOEMPTY;
curr_state <= #`TCQ next_state;
ram_valid_i <= #`TCQ next_state;
end
end //always
wire fe_of_empty;
assign fe_of_empty = empty_i_q & ~FIFOEMPTY;
always @* begin // Finding leaving empty
case (curr_state)
1'b0: leaving_empty_fwft <= fe_of_empty;
1'b1: leaving_empty_fwft <= 1'b1;
default: leaving_empty_fwft <= 1'b0;
endcase
end
always @* begin // Finding going empty
case (curr_state)
1'b1: going_empty_fwft <= FIFOEMPTY & RD_EN;
default: going_empty_fwft <= 1'b0;
endcase
end
always @* begin // Generating FWFT rd_en
case (curr_state)
1'b0: ram_rd_en_fwft <= ~FIFOEMPTY;
1'b1: ram_rd_en_fwft <= ~FIFOEMPTY & RD_EN;
default: ram_rd_en_fwft <= 1'b0;
endcase
end
assign ram_regout_en = ram_rd_en_fwft;
//assign ram_regout_en_d1 = ram_rd_en_fwft;
//assign ram_regout_en_d2 = ram_rd_en_fwft;
assign ram_rd_en = ram_rd_en_fwft;
end endgenerate // gll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false.
// Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2) begin : gnll_fifo_ram_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
ram_valid_i <= #`TCQ 1'b0;
end else begin
if (ram_rd_en == 1'b1) begin
ram_valid_i <= #`TCQ 1'b1;
end else begin
if (ram_regout_en == 1'b1)
ram_valid_i <= #`TCQ 1'b0;
else
ram_valid_i <= #`TCQ ram_valid_i;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_ram_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ ram_valid_i | (read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG < 3) begin : gnll_fifo_empty
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~ram_valid_i & ~read_data_valid_i) | (~ram_valid_i & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
generate if ( C_USE_EMBEDDED_REG < 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((ram_regout_en) | (~FIFOEMPTY & read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ FIFOEMPTY;
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
// BRAM resets synchronously
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG < 3) begin
always @ ( posedge rd_rst_i)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin
if (ram_regout_en) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
//safety ckt with one register
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG < 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
//@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1) begin
// @(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ FIFODATA;
USERSBITERR <= #`TCQ FIFOSBITERR;
USERDBITERR <= #`TCQ FIFODBITERR;
end
end
end
end //always
end //if
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 && C_FIFO_TYPE != 2) begin
always @* begin
case (curr_fwft_state)
INVALID: begin
if (~FIFOEMPTY)
next_fwft_state <= STAGE1_VALID;
else
next_fwft_state <= INVALID;
end
STAGE1_VALID: begin
if (FIFOEMPTY)
next_fwft_state <= STAGE2_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
STAGE2_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= INVALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE1_VALID;
else if (~FIFOEMPTY && ~RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= STAGE2_VALID;
end
BOTH_STAGES_VALID: begin
if (FIFOEMPTY && RD_EN)
next_fwft_state <= STAGE2_VALID;
else if (~FIFOEMPTY && RD_EN)
next_fwft_state <= BOTH_STAGES_VALID;
else
next_fwft_state <= BOTH_STAGES_VALID;
end
default: next_fwft_state <= INVALID;
endcase
end
always @ (posedge rd_rst_i or posedge RD_CLK) begin
if (rd_rst_i)
curr_fwft_state <= INVALID;
else if (srst_i)
curr_fwft_state <= #`TCQ INVALID;
else
curr_fwft_state <= #`TCQ next_fwft_state;
end
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay
if (rd_rst_i == 1) begin
ram_regout_en_d1 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d1 <= #`TCQ 1'b0;
else
ram_regout_en_d1 <= #`TCQ ram_regout_en;
end
end //always
// assign fab_regout_en = ((ram_regout_en_d1 & ~(ram_regout_en_d2) & empty_i) | (RD_EN & !empty_i));
assign fab_regout_en = ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b0 )? 1'b1: ((ram_valid_i == 1'b0 || ram_valid_i == 1'b1) && read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1) ? RD_EN : 1'b0;
always @ (posedge RD_CLK or posedge rd_rst_i) begin : proc_delay1
if (rd_rst_i == 1) begin
ram_regout_en_d2 <= #`TCQ 1'b0;
end
else begin
if (srst_i == 1'b1)
ram_regout_en_d2 <= #`TCQ 1'b0;
else
ram_regout_en_d2 <= #`TCQ ram_regout_en_d1;
end
end //always
always @* begin
case (curr_fwft_state)
INVALID: STAGE2_REG_EN <= 1'b0;
STAGE1_VALID: STAGE2_REG_EN <= 1'b1;
STAGE2_VALID: STAGE2_REG_EN <= 1'b0;
BOTH_STAGES_VALID: STAGE2_REG_EN <= RD_EN;
default: STAGE2_REG_EN <= 1'b0;
endcase
end
always @ (posedge RD_CLK) begin
ram_valid_i_d <= #`TCQ ram_valid_i;
read_data_valid_i_d <= #`TCQ read_data_valid_i;
fab_read_data_valid_i_d <= #`TCQ fab_read_data_valid_i;
end
assign VALID_STAGES = curr_fwft_state;
//***************************************************************************
// preloadstage2 indicates that stage2 needs to be updated. This is true
// whenever read_data_valid is false, and RAM_valid is true.
//***************************************************************************
assign preloadstage2 = ram_valid_i & (~read_data_valid_i | RD_EN );
//***************************************************************************
// preloadstage1 indicates that stage1 needs to be updated. This is true
// whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is
// false (indicating that Stage1 needs updating), or preloadstage2 is active
// (indicating that Stage2 is going to update, so Stage1, therefore, must
// also be updated to keep it valid.
//***************************************************************************
assign preloadstage1 = ((~ram_valid_i | preloadstage2) & ~FIFOEMPTY);
//***************************************************************************
// Calculate RAM_REGOUT_EN
// The output registers are controlled by the ram_regout_en signal.
// These registers should be updated either when the output in Stage2 is
// invalid (preloadstage2), OR when the user is reading, in which case the
// Stage2 value will go invalid unless it is replenished.
//***************************************************************************
assign ram_regout_en = (ram_valid_i == 1'b1 && (read_data_valid_i == 1'b0 || fab_read_data_valid_i == 1'b0)) ? 1'b1 : (read_data_valid_i == 1'b1 && fab_read_data_valid_i == 1'b1 && ram_valid_i == 1'b1) ? RD_EN : 1'b0;
//***************************************************************************
// Calculate RAM_RD_EN
// RAM_RD_EN will be asserted whenever the RAM needs to be read in order to
// update the value in Stage1.
// One case when this happens is when preloadstage1=true, which indicates
// that the data in Stage1 or Stage2 is invalid, and needs to automatically
// be updated.
// The other case is when the user is reading from the FIFO, which
// guarantees that Stage1 or Stage2 will be invalid on the next clock
// cycle, unless it is replinished by data from the memory. So, as long
// as the RAM has data in it, a read of the RAM should occur.
//***************************************************************************
assign ram_rd_en = ((RD_EN | ~ fab_read_data_valid_i) & ~FIFOEMPTY) | preloadstage1;
end
endgenerate // gnll_fifo
//***************************************************************************
// Calculate RAMVALID_P0_OUT
// RAMVALID_P0_OUT indicates that the data in Stage1 is valid.
//
// If the RAM is being read from on this clock cycle (ram_rd_en=1), then
// RAMVALID_P0_OUT is certainly going to be true.
// If the RAM is not being read from, but the output registers are being
// updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying,
// therefore causing RAMVALID_P0_OUT to be false // Otherwise, RAMVALID_P0_OUT will remain unchanged.
//***************************************************************************
// PROCESS regout_valid
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3) begin : gnll_fifo_fab_valid
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (srst_i) begin
// synchronous reset (active high)
fab_valid <= #`TCQ 1'b0;
end else begin
if (ram_regout_en == 1'b1) begin
fab_valid <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
fab_valid <= #`TCQ 1'b0;
else
fab_valid <= #`TCQ fab_valid;
end
end //srst_i
end //rd_rst_i
end //always
end endgenerate // gnll_fifo_fab_valid
//***************************************************************************
// Calculate READ_DATA_VALID
// READ_DATA_VALID indicates whether the value in Stage2 is valid or not.
// Stage2 has valid data whenever Stage1 had valid data and
// ram_regout_en_i=1, such that the data in Stage1 is propogated
// into Stage2.
//***************************************************************************
generate if(C_USE_EMBEDDED_REG == 3) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i)
read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
read_data_valid_i <= #`TCQ 1'b0;
else begin
if (ram_regout_en == 1'b1) begin
read_data_valid_i <= #`TCQ 1'b1;
end else begin
if (fab_regout_en == 1'b1)
read_data_valid_i <= #`TCQ 1'b0;
else
read_data_valid_i <= #`TCQ read_data_valid_i;
end
end
end //always
end
endgenerate
//generate if(C_USE_EMBEDDED_REG == 3) begin
// always @ (posedge RD_CLK or posedge rd_rst_i) begin
// if (rd_rst_i)
// read_data_valid_i <= #`TCQ 1'b0;
// else if (srst_i)
// read_data_valid_i <= #`TCQ 1'b0;
//
// if (ram_regout_en == 1'b1) begin
// fab_read_data_valid_i <= #`TCQ 1'b0;
// end else begin
// if (fab_regout_en == 1'b1)
// fab_read_data_valid_i <= #`TCQ 1'b1;
// else
// fab_read_data_valid_i <= #`TCQ fab_read_data_valid_i;
// end
// end //always
//end
//endgenerate
generate if(C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i) begin :fabout_dvalid
if (rd_rst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else if (srst_i)
fab_read_data_valid_i <= #`TCQ 1'b0;
else
fab_read_data_valid_i <= #`TCQ fab_valid | (fab_read_data_valid_i & ~RD_EN);
end //always
end
endgenerate
always @ (posedge RD_CLK ) begin : proc_del1
begin
fab_read_data_valid_i_1 <= #`TCQ fab_read_data_valid_i;
end
end //always
//**************************************************************************
// Calculate EMPTY
// Defined as the inverse of READ_DATA_VALID
//
// Description:
//
// If read_data_valid_i indicates that the output is not valid,
// and there is no valid data on the output of the ram to preload it
// with, then we will report empty.
//
// If there is no valid data on the output of the ram and we are
// reading, then the FIFO will go empty.
//
//**************************************************************************
generate if (C_FIFO_TYPE < 2 && C_USE_EMBEDDED_REG == 3 ) begin : gnll_fifo_empty_both
always @ (posedge RD_CLK or posedge rd_rst_i) begin
if (rd_rst_i) begin
// asynchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
if (srst_i) begin
// synchronous reset (active high)
empty_i <= #`TCQ 1'b1;
end else begin
// rising clock edge
empty_i <= #`TCQ (~fab_valid & ~fab_read_data_valid_i) | (~fab_valid & RD_EN);
end
end
end //always
end endgenerate // gnll_fifo_empty_both
// Register RD_EN from user to calculate USERUNDERFLOW.
// Register empty_i to calculate USERUNDERFLOW.
always @ (posedge RD_CLK) begin
rd_en_q <= #`TCQ RD_EN;
empty_q <= #`TCQ empty_i;
end //always
//***************************************************************************
// Calculate user_almost_empty
// user_almost_empty is defined such that, unless more words are written
// to the FIFO, the next read will cause the FIFO to go EMPTY.
//
// In most cases, whenever the output registers are updated (due to a user
// read or a preload condition), then user_almost_empty will update to
// whatever RAM_EMPTY is.
//
// The exception is when the output is valid, the user is not reading, and
// Stage1 is not empty. In this condition, Stage1 will be preloaded from the
// memory, so we need to make sure user_almost_empty deasserts properly under
// this condition.
//***************************************************************************
reg FIFOEMPTY_1;
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @(posedge RD_CLK) begin
FIFOEMPTY_1 <= #`TCQ FIFOEMPTY;
end
end
endgenerate
generate if (C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK or posedge rd_rst_i)
// begin
// if (((ram_valid_i == 1'b1) && (read_data_valid_i == 1'b1) && (fab_read_data_valid_i == 1'b1)) || ((ram_valid_i == 1'b0) && (read_data_valid_i == 1'b1) && (fab_read_data_valid_i == 1'b1)))
// almost_empty_i <= #`TCQ 1'b0;
// else
// almost_empty_i <= #`TCQ 1'b1;
begin
if (rd_rst_i) begin // asynchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin // rising clock edge
if (srst_i) begin // synchronous reset (active high)
almost_empty_i <= #`TCQ 1'b1;
almost_empty_q <= #`TCQ 1'b1;
end else begin
if ((fab_regout_en) | (ram_valid_i & fab_read_data_valid_i & ~RD_EN)) begin
almost_empty_i <= #`TCQ (~ram_valid_i);
end
almost_empty_q <= #`TCQ empty_i;
end
end
end //always
end
endgenerate
assign USEREMPTY = empty_i;
assign USERALMOSTEMPTY = almost_empty_i;
assign FIFORDEN = ram_rd_en;
assign RAMVALID = (C_USE_EMBEDDED_REG == 3)? fab_valid : ram_valid_i;
assign USERVALID_BOTH = (C_USERVALID_LOW && C_USE_EMBEDDED_REG == 3) ? ~fab_read_data_valid_i : ((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG == 3) ? fab_read_data_valid_i : 1'b0);
assign USERVALID_ONE = (C_USERVALID_LOW && C_USE_EMBEDDED_REG < 3) ? ~read_data_valid_i :((C_USERVALID_LOW == 0 && C_USE_EMBEDDED_REG < 3) ? read_data_valid_i : 1'b0);
assign USERVALID = (C_USE_EMBEDDED_REG == 3) ? USERVALID_BOTH : USERVALID_ONE;
assign USERUNDERFLOW = C_USERUNDERFLOW_LOW ? ~(empty_q & rd_en_q) : empty_q & rd_en_q;
//no safety ckt with both reg
generate
if (C_EN_SAFETY_CKT==0 && C_USE_EMBEDDED_REG == 3 ) begin
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
USERDATA_BOTH <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
USERDATA_BOTH <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
USERDATA_BOTH <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin
if (ram_regout_en) begin
USERDATA_BOTH <= #`TCQ FIFODATA;
USERDBITERR <= #`TCQ FIFODBITERR;
USERSBITERR <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en) begin
USERDATA <= #`TCQ USERDATA_BOTH;
end
end
end
end //always
end //if
endgenerate
//safety_ckt with both registers
generate
if (C_EN_SAFETY_CKT==1 && C_USE_EMBEDDED_REG == 3) begin
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d1;
reg [C_DOUT_WIDTH-1:0] dout_rst_val_d2;
reg [1:0] rst_delayed_sft1 =1;
reg [1:0] rst_delayed_sft2 =1;
reg [1:0] rst_delayed_sft3 =1;
reg [1:0] rst_delayed_sft4 =1;
always@(posedge RD_CLK)
begin
rst_delayed_sft1 <= #`TCQ rd_rst_i;
rst_delayed_sft2 <= #`TCQ rst_delayed_sft1;
rst_delayed_sft3 <= #`TCQ rst_delayed_sft2;
rst_delayed_sft4 <= #`TCQ rst_delayed_sft3;
end
always @ (posedge RD_CLK)
begin
if (rd_rst_i || srst_i) begin
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE < 2 && rst_delayed_sft1 == 1'b1) begin
@(posedge RD_CLK)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
USERDATA_BOTH <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
end //always
always @ (posedge RD_CLK or posedge rd_rst_i)
begin
if (rd_rst_i) begin //asynchronous reset (active high)
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
// DRAM resets asynchronously
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2)begin //asynchronous reset (active high)
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
USERDATA_BOTH <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end
else begin // rising clock edge
if (srst_i) begin
if (C_USE_ECC == 0) begin // Reset S/DBITERR only if ECC is OFF
USERSBITERR <= #`TCQ 0;
USERDBITERR <= #`TCQ 0;
end
if (C_USE_DOUT_RST == 1 && C_MEMORY_TYPE == 2) begin
USERDATA <= #`TCQ hexstr_conv(C_DOUT_RST_VAL);
end
end else begin
if (ram_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA_BOTH <= #`TCQ FIFODATA;
USERDBITERR <= #`TCQ FIFODBITERR;
USERSBITERR <= #`TCQ FIFOSBITERR;
end
if (fab_regout_en == 1'b1 && rd_rst_i == 1'b0) begin
USERDATA <= #`TCQ USERDATA_BOTH;
end
end
end
end //always
end //if
endgenerate
endmodule //fifo_generator_v13_1_0_bhv_ver_preload0
//-----------------------------------------------------------------------------
//
// Register Slice
// Register one AXI channel on forward and/or reverse signal path
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// reg_slice
//
//--------------------------------------------------------------------------
module fifo_generator_v13_1_0_axic_reg_slice #
(
parameter C_FAMILY = "virtex7",
parameter C_DATA_WIDTH = 32,
parameter C_REG_CONFIG = 32'h00000000
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Slave side
input wire [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
input wire S_VALID,
output wire S_READY,
// Master side
output wire [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA,
output wire M_VALID,
input wire M_READY
);
generate
////////////////////////////////////////////////////////////////////
//
// Both FWD and REV mode
//
////////////////////////////////////////////////////////////////////
if (C_REG_CONFIG == 32'h00000000)
begin
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg [C_DATA_WIDTH-1:0] storage_data2 = 0;
reg load_s1;
wire load_s2;
wire load_s1_from_s2;
reg s_ready_i; //local signal of output
wire m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_PAYLOAD_DATA;
end
// Load storage2 with slave side data
always @(posedge ACLK)
begin
if (load_s2)
storage_data2 <= S_PAYLOAD_DATA;
end
assign M_PAYLOAD_DATA = storage_data1;
// Always load s2 on a valid transaction even if it's unnecessary
assign load_s2 = S_VALID & s_ready_i;
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
state <= ZERO;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else begin
case (state)
// No transaction stored locally
ZERO: if (S_VALID) state <= ONE; // Got one so move to ONE
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) state <= ZERO; // Read out one so move to ZERO
if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
s_ready_i <= 1'b0;
end
end
// TWO transaction stored locally
TWO: if (M_READY) begin
state <= ONE; // Read out one so move to ONE
s_ready_i <= 1'b1;
end
endcase // case (state)
end
end // always @ (posedge ACLK)
assign m_valid_i = state[0];
end // if (C_REG_CONFIG == 1)
////////////////////////////////////////////////////////////////////
//
// 1-stage pipeline register with bubble cycle, both FWD and REV pipelining
// Operates same as 1-deep FIFO
//
////////////////////////////////////////////////////////////////////
else if (C_REG_CONFIG == 32'h00000001)
begin
reg [C_DATA_WIDTH-1:0] storage_data1 = 0;
reg s_ready_i; //local signal of output
reg m_valid_i; //local signal of output
// assign local signal to its output signal
assign S_READY = s_ready_i;
assign M_VALID = m_valid_i;
reg areset_d1; // Reset delay register
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with slave side data
always @(posedge ACLK)
begin
if (ARESET) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (m_valid_i & M_READY) begin
s_ready_i <= 1'b1;
m_valid_i <= 1'b0;
end else if (S_VALID & s_ready_i) begin
s_ready_i <= 1'b0;
m_valid_i <= 1'b1;
end
if (~m_valid_i) begin
storage_data1 <= S_PAYLOAD_DATA;
end
end
assign M_PAYLOAD_DATA = storage_data1;
end // if (C_REG_CONFIG == 7)
else begin : default_case
// Passthrough
assign M_PAYLOAD_DATA = S_PAYLOAD_DATA;
assign M_VALID = S_VALID;
assign S_READY = M_READY;
end
endgenerate
endmodule // reg_slice
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: This module is the logic that interfaces with the Xilinx MIG DDR2
// controller for the SODIMM on the ML555 and the PCIe DMA block.
// This module is responsible for crossing clock domains between the
// two blocks. There are three fifos in this module. One for egress
// data, one for ingress data, and one for passing address and
// command to the MIG controller.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Jiansong:
// TX flow control:
// (1) control signal: TX_fetch_next_4k, one cycle
// it's the falling edge of egress_data_fifo almost full
// egress_data_fifo almostfull is slightly less than half of the FIFO size
// (2) TX has higher priority than transfer, or mrd > mwr
//
// modified by Jiansong Zhang:
// (1) ddr2 read/write scheduling, pending
// divide address fifo into two fifos: rd and wr ctrl fifo
// rd/wr ctrl fifo wren control
// rd/wr scheduling in 200MHz domain
// (2) modify egress data fifo, use bram IP core instead -------------- done
//
// modification on 2009-8-18, to slove the low throughput problem
// (1) condense ddr_sm, in previous version, overhead could be 100% if data is 64 bytes
// (2) modify pause_read_requests logic: if ingress_data_fifo is more than half full,
// delay next dma read request
//
// Revision 1.00 - add scheduling for four egress fifos and one ingress fifo
// notes: (1) addr_fifo for each egress stream and the ingress stream
// (2) scheduling between all the addr_fifos and the ToDDR_addr_fifo
// (3) egress_addr data is passed from ToDDR_addr_fifo to FromDDR_addr_fifo
// (4) one egress_data_fifo is dispatched to four ToFRL_data_fifos, according to FromDDR_addr_fifo
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "Sora_config.v"
module dma_ddr2_if(
input dma_clk,
input ddr_clk,
input reset,
`ifdef sora_chipscope
// chipscope
inout [35:0] CONTROL0,
input TX_Start_one,
`endif
input radio_clk,
output [31:0] ToFRL_data_fifo_rddata,
output ToFRL_data_fifo_pempty,
input ToFRL_data_fifo_rden,
input radio_2nd_clk,
output [31:0] ToFRL_2nd_data_fifo_rddata,
output ToFRL_2nd_data_fifo_pempty,
input ToFRL_2nd_data_fifo_rden,
`ifdef MIMO_4X4
input radio_3rd_clk,
output [31:0] ToFRL_3rd_data_fifo_rddata,
output ToFRL_3rd_data_fifo_pempty,
input ToFRL_3rd_data_fifo_rden,
input radio_4th_clk,
output [31:0] ToFRL_4th_data_fifo_rddata,
output ToFRL_4th_data_fifo_pempty,
input ToFRL_4th_data_fifo_rden,
`endif //MIMO_4X4
//input wire full_rst,
//input wire soft_rst,
//DMA SIGNALS
//`ifdef Sora_16B_TX
// output wire [31:0] egress_data,
//`else
// output wire [15:0] egress_data,
//`endif
//input wire [1:0] egress_fifo_ctrl, //bit 1 = reserved bit 0 = read_en
// input wire egress_fifo_rden,
//output wire [2:0] egress_fifo_status, //bit 2 = almost full
// //(needs to be empty before more
// //egress requests complete)
// //bit 1 = empty bit 0 = almostempty
// output wire egress_fifo_pempty,
input [2:0] egress_xfer_size,
input [27:6] egress_start_addr,
input egress_data_req,
output reg egress_data_ack,
input [2:0] egress_2nd_xfer_size,
input [27:6] egress_2nd_start_addr,
input egress_2nd_data_req,
output reg egress_2nd_data_ack,
`ifdef MIMO_4X4
input [2:0] egress_3rd_xfer_size,
input [27:6] egress_3rd_start_addr,
input egress_3rd_data_req,
output reg egress_3rd_data_ack,
input [2:0] egress_4th_xfer_size,
input [27:6] egress_4th_start_addr,
input egress_4th_data_req,
output reg egress_4th_data_ack,
`endif //MIMO_4X4
//ingress
input wire [127:0] ingress_data,
// input wire [1:0] ingress_fifo_ctrl, //bit 1 = reserved bit 0 = write_en
input ingress_fifo_wren,
// output wire [1:0] ingress_fifo_status, //bit 1 = full bit 0 = almostfull
input wire [2:0] ingress_xfer_size,
input wire [27:6] ingress_start_addr,
input wire ingress_data_req,
output reg ingress_data_ack,
//END OF DMA SIGNALS
/// Jiansong: error signals
output wire egress_overflow_one,
output reg [31:0] egress_wr_data_count,
//MEMORY CNTRLR SIGNALS
output wire [127:0] m_wrdata,
input wire [127:0] m_rddata,
output reg [30:0] m_addr,
output reg [2:0] m_cmd, //3'b000 == write command
//3'b001 == read command
//all others invalid - see MIG 1.72 documentaion for
//more information
output reg m_data_wen,
output reg m_addr_wen,
input wire m_data_valid,
input wire m_af_afull,
input wire m_wdf_afull,
//END OF MEMORY CNTRLR SIGNALS
output reg pause_read_requests,
output reg [31:0] DebugDDREgressFIFOCnt, // [31:16] write cnt; [15:0] read cnt
output reg [31:0] DebugDDRFIFOFullCnt,
output reg [31:0] DebugDDRSignals,
output reg [8:0] DebugDDRSMs
// output reg [31:0] Debug18DDR1,
// output reg [31:0] Debug19DDR2
);
reg ddr_reset, ddr_reset1;
/// Jiansong: debug signals
//`ifdef Sora_16B_TX
//wire [10:0] egress_read_data_count;
//`else
//wire [11:0] egress_read_data_count;
//`endif
//wire [8:0] egress_write_data_count;
///Jiansong: signal for egress/TX flow control
//reg egress_fifo_ready;
//wire egress_pfull_falling; // one cycle to detect falling edge of egress_pfull
//reg less_4k_pass;
////reg addr_fifo_wren;
////reg [31:0] addr_fifo_wrdata;
////wire addr_fifo_almost_full;
reg ingress_addr_fifo_wren;
reg [31:0] ingress_addr_fifo_wrdata;
wire ingress_addr_fifo_pfull;
reg ingress_addr_fifo_rden;
wire [31:0] ingress_addr_fifo_rddata;
wire ingress_addr_fifo_empty;
wire ingress_addr_fifo_full;
//wire ingress_addr_fifo_almost_full;
//wire ingress_addr_fifo_almost_empty;
reg [9:0] xfer_cnt;
reg ingress_fifo_rden;
wire ingress_fifo_pempty;
wire ingress_fifo_empty;
wire ingress_fifo_almostempty;
wire ingress_fifo_full;
wire ingress_fifo_pfull;
//reg ToDDR_addr_fifo_wren;
//reg [31:0] ToDDR_addr_fifo_wrdata;
//wire ToDDR_addr_fifo_empty;
//wire ToDDR_addr_fifo_full;
//reg ToDDR_addr_fifo_ren;
//wire [31:0] ToDDR_addr_fifo_rddata;
reg FromDDR_addr_fifo_wren;
reg [31:0] FromDDR_addr_fifo_wrdata;
wire FromDDR_addr_fifo_empty;
wire FromDDR_addr_fifo_full;
reg FromDDR_addr_fifo_rden;
wire [31:0] FromDDR_addr_fifo_rddata;
reg egress_addr_fifo_wren;
reg [31:0] egress_addr_fifo_wrdata;
wire egress_addr_fifo_empty;
wire egress_addr_fifo_full;
reg egress_addr_fifo_rden;
wire [31:0] egress_addr_fifo_rddata;
//wire egress_addr_fifo_almost_full;
//wire egress_addr_fifo_almost_empty;
reg egress_2nd_addr_fifo_wren;
reg [31:0] egress_2nd_addr_fifo_wrdata;
wire egress_2nd_addr_fifo_empty;
wire egress_2nd_addr_fifo_full;
reg egress_2nd_addr_fifo_rden;
wire [31:0] egress_2nd_addr_fifo_rddata;
`ifdef MIMO_4X4
reg egress_3rd_addr_fifo_wren;
reg [31:0] egress_3rd_addr_fifo_wrdata;
wire egress_3rd_addr_fifo_empty;
wire egress_3rd_addr_fifo_full;
reg egress_3rd_addr_fifo_rden;
wire [31:0] egress_3rd_addr_fifo_rddata;
reg egress_4th_addr_fifo_wren;
reg [31:0] egress_4th_addr_fifo_wrdata;
wire egress_4th_addr_fifo_empty;
wire egress_4th_addr_fifo_full;
reg egress_4th_addr_fifo_rden;
wire [31:0] egress_4th_addr_fifo_rddata;
`endif //MIMO_4X4
////reg addr_fifo_ren;
////wire [31:0] addr_fifo_rddata;
wire ToFRL_data_fifo_almost_full_this;
wire ToFRL_data_fifo_pfull_this;
reg ToFRL_data_fifo_wren;
wire [127:0] ToFRL_data_fifo_wrdata;
wire ToFRL_data_fifo_pfull;
wire ToFRL_data_fifo_full;
wire ToFRL_data_fifo_almost_full;
wire ToFRL_data_fifo_empty;
reg ToFRL_2nd_data_fifo_wren;
wire [127:0] ToFRL_2nd_data_fifo_wrdata;
wire ToFRL_2nd_data_fifo_pfull;
wire ToFRL_2nd_data_fifo_full;
wire ToFRL_2nd_data_fifo_almost_full;
wire ToFRL_2nd_data_fifo_empty;
`ifdef MIMO_4X4
reg ToFRL_3rd_data_fifo_wren;
wire [127:0] ToFRL_3rd_data_fifo_wrdata;
wire ToFRL_3rd_data_fifo_pfull;
wire ToFRL_3rd_data_fifo_full;
wire ToFRL_3rd_data_fifo_almost_full;
wire ToFRL_3rd_data_fifo_empty;
reg ToFRL_4th_data_fifo_wren;
wire [127:0] ToFRL_4th_data_fifo_wrdata;
wire ToFRL_4th_data_fifo_pfull;
wire ToFRL_4th_data_fifo_full;
wire ToFRL_4th_data_fifo_almost_full;
wire ToFRL_4th_data_fifo_empty;
`endif //MIMO_4X4
//for the fifo status logic
reg egress_fifo_rden;
reg egress_fifo_wren;
wire [127:0] egress_fifo_rddata;
reg [127:0] m_rddata_reg; // wrdata
wire egress_fifo_full;
wire egress_fifo_empty;
wire egress_fifo_pfull;
wire egress_fifo_pempty;
////wire egress_full_a;
////wire egress_pfull_a;
////wire egress_full_b;
////wire egress_pfull_b;
////wire egress_pempty_a;
////wire egress_pempty_b;
//wire ingress_fifo_pempty_a;
//wire ingress_fifo_empty_a;
//wire ingress_fifo_pempty_b;
//wire ingress_fifo_empty_b;
////wire addr_fifo_empty;
////wire addr_fifo_full;
//wire [1:0] ingress_fifo_status_a;
//wire [1:0] ingress_fifo_status_b;
//ML505 specific wires/regs
//wire [8:0] wrcount, rdcount;
//reg [8:0] wrcount_gray_dma;
//reg [8:0] wrcount_gray_ddr, wrcount_gray_ddr1;
//wire [8:0] wrcount_ddr;
//reg [8:0] wrcount_ddr_reg;
//reg [8:0] rdcount_reg = 0;
////reg at_least_64B;
//reg [1:0] dma_state;
////States for DMA state machine
//localparam IDLE = 2'b00;
//localparam LOADI = 2'b01;
//localparam DONE = 2'b10;
////localparam LOADE = 3'b001;
////localparam WAITE = 3'b100; /// Jiansong: add one cycle to wait for the deassertion of egress request
reg [2:0] token; // 000: egress; 001: egress2; 010: egress3; 011: egress4; 100: ingress
////States for rr scheduler
reg [3:0] sche_state;
localparam IDLE = 4'b0000;
localparam LOADE = 4'b0001;
localparam SETE = 4'b0010;
localparam LOADE2 = 4'b0011;
localparam SETE2 = 4'b0100;
localparam LOADE3 = 4'b0101;
localparam SETE3 = 4'b0110;
localparam LOADE4 = 4'b0111;
localparam SETE4 = 4'b1000;
localparam LOADI = 4'b1001;
localparam SETI = 4'b1010;
reg [4:0] ddr_state;
//States for the DDR state machine
localparam NOOP = 5'b00000;
////localparam LOAD0 = 5'b00001;
////localparam LOAD1 = 5'b00010;
//localparam E_LOAD0 = 5'b00001;
//localparam E_LOAD1 = 5'b00010;
//localparam IN_LOAD0 = 5'b01101;
//localparam IN_LOAD1 = 5'b01110;
localparam R1 = 5'b00011;
localparam R2 = 5'b00100;
//localparam W0 = 5'b00101;
localparam W1 = 5'b00110;
localparam W2 = 5'b00111;
localparam W3 = 5'b01000;
localparam W4 = 5'b01001;
localparam W5 = 5'b01010;
//localparam W6 = 5'b01011;
//localparam WAIT_FOR_ROOM = 5'b01100;
reg [1:0] egress_state;
localparam E_IDLE = 2'b00;
localparam E_WAIT_ADDR = 2'b01;
localparam E_PASS_START = 2'b10;
localparam E_PASS = 2'b11;
///// Jiansong: debug register
//always@(posedge ddr_clk)begin
// Debug18DDR1[7:0] <= {3'b000,ddr_state[4:0]};
//// Debug18DDR1[11:8] <= {3'b000,less_4k_pass};
//// Debug18DDR1[15:12] <= {3'b000,egress_fifo_ready};
// Debug18DDR1[19:16] <= {3'b000,egress_fifo_empty};
// Debug18DDR1[23:20] <= {3'b000,egress_addr_fifo_empty};
// Debug18DDR1[27:24] <= {3'b000,ingress_addr_fifo_empty};
// Debug18DDR1[31:28] <= {3'b000,ingress_data_req};
//end
//
//always@(posedge ddr_clk)begin
// Debug19DDR2[3:0] <= {3'b000,egress_addr_fifo_full};
//// Debug19DDR2[7:4] <= {1'b0,egress_fifo_status[2:0]};
//// Debug19DDR2[7:4] <= {3'b000,egress_fifo_pempty};
////`ifdef Sora_16B_TX
//// Debug19DDR2[18:8] <= egress_read_data_count[10:0];
////`else
//// Debug19DDR2[19:8] <= egress_read_data_count[11:0];
////`endif
//// Debug19DDR2[31:20] <= {3'b000,egress_write_data_count[8:0]};
//end
//synchronize the DMA reset signal to the DDR2 clock
always@(posedge ddr_clk)begin
ddr_reset1 <= reset;
ddr_reset <= ddr_reset1;
end
//create a single gating signal for the ingress path so that the transmit
//engine will stop executing read requests if the fifos are nearing full
//condition; this signal is fedback to the DMA CNTRL block
always@(posedge dma_clk)begin
//// pause_read_requests <= ingress_fifo_pfull | addr_fifo_almost_full;
// pause_read_requests <= ingress_fifo_pfull | ingress_addr_fifo_almost_full;
pause_read_requests <= (~ingress_fifo_pempty) | ingress_addr_fifo_pfull; // either fifo more than half full
end
/// Jiansong: modifications
/// (1) separate addr_cntrl_fifo to ingress addr fifo and egress addr fifo
/// (2) scheduling at addr fifo rd side, or 200MHz clock domain
/// (3) egress always has higher priority
///////////////////////////////////////////////////////////////////////////////
// DMA state machine
//
// Takes request from the dma and loads into the ADDRESS/CNTRL FIFO(64 deep)
// for the ddr state machine
//
// The TX and RX engines provide a request signal (*_data_req), and encoded
// transfer size (*_xfer_size) and a starting address (*_start_addr).
// The bottom 6 bits of the start address are not needed since the
// address should always be aligned on a 64B boundary (which is the smallest
// incremental address that a completion packet may be returned on)
///////////////////////////////////////////////////////////////////////////////
always@(posedge dma_clk) begin
if (reset) begin
egress_data_ack <= 1'b0;
egress_addr_fifo_wren <= 1'b0;
egress_addr_fifo_wrdata <= 32'h00000000;
end else if (egress_data_ack) begin
egress_data_ack <= 1'b0;
egress_addr_fifo_wren <= 1'b0;
egress_addr_fifo_wrdata <= 32'h00000000;
end else if (egress_data_req & ~egress_addr_fifo_full) begin
egress_data_ack <= 1'b1;
egress_addr_fifo_wren <= 1'b1;
egress_addr_fifo_wrdata <= ({4'b0000,2'b00,egress_xfer_size[2:0],egress_start_addr[27:6],1'b1});//bit 0 == 1'b1 denotes read from ddr2
end else begin
egress_data_ack <= 1'b0;
egress_addr_fifo_wren <= 1'b0;
egress_addr_fifo_wrdata <= 32'h00000000;
end
end
always@(posedge dma_clk) begin
if (reset) begin
egress_2nd_data_ack <= 1'b0;
egress_2nd_addr_fifo_wren <= 1'b0;
egress_2nd_addr_fifo_wrdata <= 32'h00000000;
end else if (egress_2nd_data_ack) begin
egress_2nd_data_ack <= 1'b0;
egress_2nd_addr_fifo_wren <= 1'b0;
egress_2nd_addr_fifo_wrdata <= 32'h00000000;
end else if (egress_2nd_data_req & ~egress_2nd_addr_fifo_full) begin
egress_2nd_data_ack <= 1'b1;
egress_2nd_addr_fifo_wren <= 1'b1;
egress_2nd_addr_fifo_wrdata <= ({4'b0000,2'b01,egress_2nd_xfer_size[2:0],egress_2nd_start_addr[27:6],1'b1});//bit 0 == 1'b1 denotes read from ddr2
end else begin
egress_2nd_data_ack <= 1'b0;
egress_2nd_addr_fifo_wren <= 1'b0;
egress_2nd_addr_fifo_wrdata <= 32'h00000000;
end
end
`ifdef MIMO_4X4
always@(posedge dma_clk) begin
if (reset) begin
egress_3rd_data_ack <= 1'b0;
egress_3rd_addr_fifo_wren <= 1'b0;
egress_3rd_addr_fifo_wrdata <= 32'h00000000;
end else if (egress_3rd_data_ack) begin
egress_3rd_data_ack <= 1'b0;
egress_3rd_addr_fifo_wren <= 1'b0;
egress_3rd_addr_fifo_wrdata <= 32'h00000000;
end else if (egress_3rd_data_req & ~egress_3rd_addr_fifo_full) begin
egress_3rd_data_ack <= 1'b1;
egress_3rd_addr_fifo_wren <= 1'b1;
egress_3rd_addr_fifo_wrdata <= ({4'b0000,2'b10,egress_3rd_xfer_size[2:0],egress_3rd_start_addr[27:6],1'b1});//bit 0 == 1'b1 denotes read from ddr2
end else begin
egress_3rd_data_ack <= 1'b0;
egress_3rd_addr_fifo_wren <= 1'b0;
egress_3rd_addr_fifo_wrdata <= 32'h00000000;
end
end
always@(posedge dma_clk) begin
if (reset) begin
egress_4th_data_ack <= 1'b0;
egress_4th_addr_fifo_wren <= 1'b0;
egress_4th_addr_fifo_wrdata <= 32'h00000000;
end else if (egress_4th_data_ack) begin
egress_4th_data_ack <= 1'b0;
egress_4th_addr_fifo_wren <= 1'b0;
egress_4th_addr_fifo_wrdata <= 32'h00000000;
end else if (egress_4th_data_req & ~egress_4th_addr_fifo_full) begin
egress_4th_data_ack <= 1'b1;
egress_4th_addr_fifo_wren <= 1'b1;
egress_4th_addr_fifo_wrdata <= ({4'b0000,2'b11,egress_4th_xfer_size[2:0],egress_4th_start_addr[27:6],1'b1});//bit 0 == 1'b1 denotes read from ddr2
end else begin
egress_4th_data_ack <= 1'b0;
egress_4th_addr_fifo_wren <= 1'b0;
egress_4th_addr_fifo_wrdata <= 32'h00000000;
end
end
`endif //MIMO_4X4
always@(posedge dma_clk) begin
if (reset) begin
ingress_data_ack <= 1'b0;
ingress_addr_fifo_wren <= 1'b0;
ingress_addr_fifo_wrdata <= 32'h00000000;
end else if (ingress_data_ack) begin
ingress_data_ack <= 1'b0;
ingress_addr_fifo_wren <= 1'b0;
ingress_addr_fifo_wrdata <= 32'h00000000;
end else if (ingress_data_req & ~ingress_addr_fifo_full & ~ingress_fifo_pfull) begin
ingress_data_ack <= 1'b1;
ingress_addr_fifo_wren <= 1'b1;
ingress_addr_fifo_wrdata <= ({6'b000000,ingress_xfer_size[2:0],ingress_start_addr[27:6],1'b0});//bit 0 == 1'b0 denotes write to ddr2
end else begin
ingress_data_ack <= 1'b0;
ingress_addr_fifo_wren <= 1'b0;
ingress_addr_fifo_wrdata <= 32'h00000000;
end
end
////ingress_addr_fifo
//always @ (posedge dma_clk) begin
// if(reset)begin
// ingress_addr_fifo_wren <= 1'b0;
// ingress_addr_fifo_wrdata[31:0] <= 32'h00000000;
// ingress_data_ack <= 1'b0;
// dma_state <= IDLE;
// end else begin
// case(dma_state)
// IDLE: begin
// ingress_data_ack <= 1'b0;
// ingress_addr_fifo_wren <= 1'b0;
// if(ingress_data_req &
// ~ingress_addr_fifo_full &
// ~ingress_fifo_pfull) begin /// Jiansong: if ingress_fifo_status is almostfull, block ingress data request
// //assert the ingress ack and load the ADDR/CNTRL fifo with the correct ddr2 write parameters
// ingress_data_ack <= 1'b1;
// ingress_addr_fifo_wrdata[31:0]<= ({6'b000000,ingress_xfer_size[2:0],ingress_start_addr[27:6],1'b0});//bit 0 == 1'b0 denotes write to ddr2
// ingress_addr_fifo_wren <= 1'b1;
// dma_state <= LOADI;
// end else begin
// dma_state <= IDLE;
// end
// end
// LOADI: begin
// ingress_addr_fifo_wren <= 1'b0;
// ingress_data_ack <= 1'b0;
// dma_state <= DONE;
// end
// DONE: begin
// ingress_data_ack <= 1'b0;
// ingress_addr_fifo_wren <= 1'b0;
// dma_state <= IDLE;
// end
// default: begin
// ingress_data_ack <= 1'b0;
// ingress_addr_fifo_wren <= 1'b0;
// dma_state <= IDLE;
// end
// endcase
// end
//end
//always @ (posedge dma_clk) begin
// if(reset)begin
// dma_state <= IDLE;
// ingress_addr_fifo_wren <= 1'b0;
// ingress_addr_fifo_wrdata[31:0] <= 32'h00000000;
// egress_addr_fifo_wren <= 1'b0;
// egress_addr_fifo_wrdata[31:0] <= 32'h00000000;
// egress_data_ack <= 1'b0;
// ingress_data_ack <= 1'b0;
// end else begin
// case(dma_state)
// IDLE: begin
// egress_data_ack <= 1'b0;
// ingress_data_ack <= 1'b0;
// egress_addr_fifo_wren <= 1'b0;
// ingress_addr_fifo_wren <= 1'b0;
////// if(~addr_fifo_full)begin //don't do anything if addr_fifo is full
///// Jiansong: ddr read/write scheduling here
////// if(ingress_data_req) begin
// if(ingress_data_req &
// ~ingress_addr_fifo_full &
// ~ingress_fifo_pfull) begin /// Jiansong: if ingress_fifo_status
// /// is almostfull, block
// /// ingress data request
// dma_state <= LOADI;
// //assert the ingress ack and load the ADDR/CNTRL fifo with
// //the correct ddr2 write parameters
// ingress_data_ack <= 1'b1;
// ingress_addr_fifo_wrdata[31:0] <= ({6'b000000,
// ingress_xfer_size[2:0],
// ingress_start_addr[27:6],
// 1'b0});//bit 0 == 1'b0 denotes
// //write to ddr2
// ingress_addr_fifo_wren <= 1'b1;
////// end else if(egress_data_req)begin
// end else if(egress_data_req & ~egress_addr_fifo_full)begin
// //Don't grant ack for egress if the egress fifo is almost
// //full, otherwise the MIG controller might overfill the
// //egress fifo.
////// if(egress_pfull) begin /// Jiansong: how much is almost?
////// dma_state <= IDLE;
////// end else begin
// //Otherwise, assert the egress ack and load the
// //ADDR/CNTRL fifo with the correct ddr2 read parameters
// dma_state <= LOADE;
// egress_data_ack <= 1'b1;
// egress_addr_fifo_wrdata[31:0] <= ({6'b000000,
// egress_xfer_size[2:0],
// egress_start_addr[27:6],
// 1'b1});//bit 0 == 1'b1 denotes
// //read from ddr2
// egress_addr_fifo_wren <= 1'b1;
////// end
////// end
// end else begin
// dma_state <= IDLE;
// end
// end
// //LOADE and LOADI are for deasserting the ack and wren signals
// //before returning to IDLE
// LOADE: begin
// egress_addr_fifo_wren <= 1'b0;
// egress_data_ack <= 1'b0;
// dma_state <= WAITE;
// end
// /// Jiansong: add one cycle to wait for the deassertion of egress request
// WAITE: begin
// egress_addr_fifo_wren <= 1'b0;
// egress_data_ack <= 1'b0;
// dma_state <= DONE;
// end
// LOADI: begin
// ingress_addr_fifo_wren <= 1'b0;
// ingress_data_ack <= 1'b0;
// dma_state <= DONE;
// end
// DONE: begin
// dma_state <= IDLE;
// egress_data_ack <= 1'b0;
// ingress_data_ack <= 1'b0;
// ingress_addr_fifo_wren <= 1'b0;
// egress_addr_fifo_wren <= 1'b0;
// end
// default: begin
// dma_state <= IDLE;
// egress_data_ack <= 1'b0;
// ingress_data_ack <= 1'b0;
// ingress_addr_fifo_wren <= 1'b0;
// egress_addr_fifo_wren <= 1'b0;
// end
// endcase
// end
//end
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
//// Jiansong, 2012-12-15, add pipeline to save overhead
////ToDDR_addr_valid
wire R1_one;
wire W1_one;
rising_edge_detect R1_one_inst(.clk(ddr_clk),.rst(ddr_reset),.in(ddr_state==R1),.one_shot_out(R1_one));
rising_edge_detect W1_one_inst(.clk(ddr_clk),.rst(ddr_reset),.in(ddr_state==W1),.one_shot_out(W1_one));
reg ToDDR_addr_valid;
reg [25:0] ToDDR_addr_data;
always@(posedge ddr_clk) begin
if (ddr_reset)
ToDDR_addr_valid <= 1'b0;
else if (sche_state==SETE | sche_state==SETE2 | sche_state==SETE3 | sche_state==SETE4 | sche_state==SETI)
ToDDR_addr_valid <= 1'b1;
else if (R1_one | W1_one)
ToDDR_addr_valid <= 1'b0;
else
ToDDR_addr_valid <= ToDDR_addr_valid;
end
//////////////////////////////////////////////////////
////////////////// Scheduler ///////////////////////
// input: four egress_addr_fifos and one ingress_addr_fifo
// output: ToDDR_addr_fifo
// round-robin scheduling
always@(posedge ddr_clk) begin
if (ddr_reset) begin
sche_state <= IDLE;
token <= 3'b000;
ingress_addr_fifo_rden <= 1'b0;
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ToDDR_addr_data <= 26'h000_0000;
FromDDR_addr_fifo_wren <= 1'b0;
FromDDR_addr_fifo_wrdata <= 32'h0000_0000;
// ToDDR_addr_fifo_wren <= 1'b0;
// ToDDR_addr_fifo_wrdata[31:0] <= 32'h0000_0000;
end else begin
case (sche_state)
IDLE: begin
token <= token[2:0];
ToDDR_addr_data <= ToDDR_addr_data[25:0];
FromDDR_addr_fifo_wren <= 1'b0;
FromDDR_addr_fifo_wrdata <= 32'h0000_0000;
// ToDDR_addr_fifo_wren <= 1'b0;
// ToDDR_addr_fifo_wrdata[31:0] <= 32'h0000_0000;
// if (~ToDDR_addr_fifo_full) begin
if (~ToDDR_addr_valid) begin
casex({token[2:0],egress_addr_fifo_empty | ToFRL_data_fifo_pfull, /// liuchang: add ToFRL_data_fifo_pfull
egress_2nd_addr_fifo_empty | ToFRL_2nd_data_fifo_pfull,
egress_3rd_addr_fifo_empty | ToFRL_3rd_data_fifo_pfull,
egress_4th_addr_fifo_empty | ToFRL_4th_data_fifo_pfull,
ingress_addr_fifo_empty,
egress_fifo_pfull|FromDDR_addr_fifo_full})
// 9'b000_0xxxx_0, 9'b001_01111_0, 9'b010_0x111_0, 9'b011_0xx11_0, 9'b1xx_0xxx1_0: begin
9'b000_0xxxx_0, 9'b001_0111x_0, 9'b010_0x11x_0, 9'b011_0xx1x_0, 9'b1xx_0xxxx_0: begin
sche_state <= LOADE;
egress_addr_fifo_rden <= 1'b1;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
end
// 9'b000_10xxx_0, 9'b001_x0xxx_0, 9'b010_10111_0, 9'b011_10x11_0, 9'b1xx_10xx1_0: begin
9'b000_10xxx_0, 9'b001_x0xxx_0, 9'b010_1011x_0, 9'b011_10x1x_0, 9'b1xx_10xxx_0: begin
sche_state <= LOADE2;
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b1;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
end
// 9'b000_110xx_0, 9'b001_x10xx_0, 9'b010_xx0xx_0, 9'b011_11011_0, 9'b1xx_110x1_0: begin
9'b000_110xx_0, 9'b001_x10xx_0, 9'b010_xx0xx_0, 9'b011_1101x_0, 9'b1xx_110xx_0: begin
sche_state <= LOADE3;
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b1;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
end
// 9'b000_1110x_0, 9'b001_x110x_0, 9'b010_xx10x_0, 9'b011_xxx0x_0, 9'b1xx_11101_0: begin
9'b000_1110x_0, 9'b001_x110x_0, 9'b010_xx10x_0, 9'b011_xxx0x_0, 9'b1xx_1110x_0: begin
sche_state <= LOADE4;
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b1;
ingress_addr_fifo_rden <= 1'b0;
end
// 9'b000_11110_x, 9'b001_x1110_x, 9'b010_xx110_x, 9'b011_xxx10_x, 9'b1xx_xxxx0_x, 9'bxxx_xxxx0_1: begin
9'b000_11110_x, 9'b001_11110_x, 9'b010_11110_x, 9'b011_11110_x, 9'b1xx_11110_x, 9'bxxx_xxxx0_1: begin
sche_state <= LOADI;
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b1;
end
default: begin
sche_state <= IDLE;
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
end
endcase
end else begin
sche_state <= IDLE;
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
end
end
LOADE: begin
sche_state <= SETE;
token <= 3'b001;
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
ToDDR_addr_data <= ToDDR_addr_data[25:0];
FromDDR_addr_fifo_wren <= 1'b0;
FromDDR_addr_fifo_wrdata <= 32'h0000_0000;
// ToDDR_addr_fifo_wren <= 1'b0;
// ToDDR_addr_fifo_wrdata[31:0] <= 32'h0000_0000;
end
SETE: begin
sche_state <= IDLE;
token <= token[2:0];
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
ToDDR_addr_data <= egress_addr_fifo_rddata[25:0];
FromDDR_addr_fifo_wren <= 1'b1;
FromDDR_addr_fifo_wrdata <= egress_addr_fifo_rddata[31:0];
// ToDDR_addr_fifo_wren <= 1'b1;
// ToDDR_addr_fifo_wrdata[31:0] <= egress_addr_fifo_rddata[31:0];
end
LOADE2: begin
sche_state <= SETE2;
token <= 3'b010;
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
ToDDR_addr_data <= ToDDR_addr_data[25:0];
FromDDR_addr_fifo_wren <= 1'b0;
FromDDR_addr_fifo_wrdata <= 32'h0000_0000;
// ToDDR_addr_fifo_wren <= 1'b0;
// ToDDR_addr_fifo_wrdata[31:0] <= 32'h0000_0000;
end
SETE2: begin
sche_state <= IDLE;
token <= token[2:0];
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
ToDDR_addr_data <= egress_2nd_addr_fifo_rddata[25:0];
FromDDR_addr_fifo_wren <= 1'b1;
FromDDR_addr_fifo_wrdata <= egress_2nd_addr_fifo_rddata[31:0];
// ToDDR_addr_fifo_wren <= 1'b1;
// ToDDR_addr_fifo_wrdata[31:0] <= egress_2nd_addr_fifo_rddata[31:0];
end
LOADE3: begin
sche_state <= SETE3;
token <= 3'b011;
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
ToDDR_addr_data <= ToDDR_addr_data[25:0];
FromDDR_addr_fifo_wren <= 1'b0;
FromDDR_addr_fifo_wrdata <= 32'h0000_0000;
// ToDDR_addr_fifo_wren <= 1'b0;
// ToDDR_addr_fifo_wrdata[31:0] <= 32'h0000_0000;
end
SETE3: begin
sche_state <= IDLE;
token <= token[2:0];
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
ToDDR_addr_data <= egress_3rd_addr_fifo_rddata[25:0];
FromDDR_addr_fifo_wren <= 1'b1;
FromDDR_addr_fifo_wrdata <= egress_3rd_addr_fifo_rddata[31:0];
// ToDDR_addr_fifo_wren <= 1'b1;
// ToDDR_addr_fifo_wrdata[31:0] <= egress_3rd_addr_fifo_rddata[31:0];
end
LOADE4: begin
sche_state <= SETE4;
// token <= 3'b100;
token <= 3'b000;
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
ToDDR_addr_data <= ToDDR_addr_data[25:0];
FromDDR_addr_fifo_wren <= 1'b0;
FromDDR_addr_fifo_wrdata <= 32'h0000_0000;
// ToDDR_addr_fifo_wren <= 1'b0;
// ToDDR_addr_fifo_wrdata[31:0] <= 32'h0000_0000;
end
SETE4: begin
sche_state <= IDLE;
token <= token[2:0];
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
ToDDR_addr_data <= egress_4th_addr_fifo_rddata[25:0];
FromDDR_addr_fifo_wren <= 1'b1;
FromDDR_addr_fifo_wrdata <= egress_4th_addr_fifo_rddata[31:0];
// ToDDR_addr_fifo_wren <= 1'b1;
// ToDDR_addr_fifo_wrdata[31:0] <= egress_4th_addr_fifo_rddata[31:0];
end
LOADI: begin
sche_state <= SETI;
// token <= 3'b000;
token <= token[2:0];
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
ToDDR_addr_data <= ToDDR_addr_data[25:0];
FromDDR_addr_fifo_wren <= 1'b0;
FromDDR_addr_fifo_wrdata <= 32'h0000_0000;
// ToDDR_addr_fifo_wren <= 1'b0;
// ToDDR_addr_fifo_wrdata[31:0] <= 32'h0000_0000;
end
SETI: begin
sche_state <= IDLE;
token <= token[2:0];
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ingress_addr_fifo_rden <= 1'b0;
ToDDR_addr_data <= ingress_addr_fifo_rddata[25:0];
FromDDR_addr_fifo_wren <= 1'b0; // ingress_addr should not be passed to FromDDR_addr_fifo
FromDDR_addr_fifo_wrdata <= 32'h0000_0000;
// ToDDR_addr_fifo_wren <= 1'b1;
// ToDDR_addr_fifo_wrdata[31:0] <= ingress_addr_fifo_rddata[31:0];
end
default: begin
sche_state <= IDLE;
token <= token[2:0];
ingress_addr_fifo_rden <= 1'b0;
egress_addr_fifo_rden <= 1'b0;
egress_2nd_addr_fifo_rden <= 1'b0;
egress_3rd_addr_fifo_rden <= 1'b0;
egress_4th_addr_fifo_rden <= 1'b0;
ToDDR_addr_data <= ToDDR_addr_data[25:0];
FromDDR_addr_fifo_wren <= 1'b0;
FromDDR_addr_fifo_wrdata <= 32'h0000_0000;
// ToDDR_addr_fifo_wren <= 1'b0;
// ToDDR_addr_fifo_wrdata[31:0] <= 32'h0000_0000;
end
endcase
end
end
///// Jiansong: generate egress_fifo_ready signal
//rising_edge_detect egress_fifo_almostfull_falling_inst(
// .clk(ddr_clk),
// .rst(reset),
// .in(~egress_pfull),
// .one_shot_out(egress_pfull_falling)
// );
//always@(posedge ddr_clk)begin
// if(reset)
// egress_fifo_ready <= 1'b0;
// // During a 4k-read-requests writing into ddr module, if a DRAM refresh cycle occurs that read
// // requests write in is interrupted, the egress_pfull signal may be deasserted and asserted
// // one more time unexpectedly. (ddr_stat != R1) means to bypass the deassert event if current 4k
// // reading is still ongoing, which will prevent asserting egress_fifo_ready by mistake.
// else if(egress_pfull_falling && (ddr_state != R1))
// egress_fifo_ready <= 1'b1;
// else if(egress_addr_fifo_rden)
// egress_fifo_ready <= 1'b0;
//end
//always@(posedge ddr_clk)begin
// if(reset)
// less_4k_pass <= 1'b0;
// else if(egress_addr_fifo_rddata[25:23] < 3'b110)
// less_4k_pass <= 1'b1;
// else
// less_4k_pass <= 1'b0;
//end
/// Jiansong: modifications
/// (1) ingress/egress scheduling
/// (2) egress always has higher priority
/// (3) egress flow control to prevent egress_data_fifo overflow
///////////////////////////////////////////////////////////////////////
// DDR state machine
//
// Monitors the ADDR/CNTRL FIFO and and translates incoming requests for
// MIG DDR2 controller
//
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
//// Jiansong, 2012-12-15, add pipeline to save overhead
////ToDDR_addr_valid
//reg ToDDR_addr_valid;
//always@(posedge ddr_clk) begin
// if (rst)
// ToDDR_addr_valid <= 1'b0;
// else if (ToDDR_addr_valid) begin
// if (ddr_state == R1 | ddr_state == W1)
// ToDDR_addr_valid <= 1'b0;
// else
// ToDDR_addr_valid <= ToDDR_addr_valid;
// end else begin
// if (ToDDR_addr_fifo_ren)
// ToDDR_addr_valid <= 1'b1;
// else
// ToDDR_addr_valid <= ToDDR_addr_valid;
// end
//end
//// ToDDR_addr_fifo_ren
//always@(posedge ddr_clk) begin
// if (rst)
// ToDDR_addr_fifo_ren <= 1'b0;
// else if (~ToDDR_addr_valid & ~ToDDR_addr_fifo_ren & ~ToDDR_addr_fifo_empty) // ren should be one cycle each time
// ToDDR_addr_fifo_ren <= 1'b1;
// else
// ToDDR_addr_fifo_ren <= 1'b0;
//end
always@(posedge ddr_clk) begin
if(ddr_reset)begin
ddr_state <= NOOP;
//// addr_fifo_ren <= 1'b0;
// egress_addr_fifo_rden <= 1'b0;
// ingress_addr_fifo_rden <= 1'b0;
xfer_cnt <= 10'b0000000000;
m_addr <= 31'h00000000;
m_cmd <= 3'b000;
m_addr_wen <= 1'b0;
m_data_wen <= 1'b0;
ingress_fifo_rden <= 1'b0;
end else begin
case(ddr_state)
// NOOP: begin
// m_data_wen <= 1'b0;
// m_addr_wen <= 1'b0;
////// //if the ADDR/CTRL fifo is not empty then read one entry
////// //from the fifo, otherwise stay in this state and do nothing
////// if(addr_fifo_empty) begin
////// ddr_state <= NOOP;
////// end else begin
////// ddr_state <= LOAD0;
////// addr_fifo_ren <= 1'b1;
////// end
//
// // egress flow control: egress_fifo_ready signal and less_4k_pass signal
// // read out data only in 3 situation:
// // (1) first request (egress_empty)
// // (2) data in fifo becomes less than half full(egress_fifo_ready)
// // (3) small/the_last requests will not make egress_data_fifo overflow
// // (less_4k_pass)
// // egress always has higher priority
// if(~egress_addr_fifo_empty &
// (egress_empty | egress_fifo_ready | less_4k_pass)) begin
// ddr_state <= E_LOAD0;
// egress_addr_fifo_rden <= 1'b1;
// end else if(~ingress_addr_fifo_empty & ~ingress_fifo_almostempty) begin
// ddr_state <= IN_LOAD0;
// ingress_addr_fifo_rden <= 1'b1;
// end else begin
// ddr_state <= NOOP;
// end
// end
// E_LOAD0: begin //state for deasserting the addr_fifo_ren signal
// ddr_state <= E_LOAD1;
// egress_addr_fifo_rden <= 1'b0;
// end
// E_LOAD1: begin /// Jiansong: m_addr distance 1 means 8bytes(64bits)
// //map a byte address into ddr2 column address:
// //since the ddr2 memory in this ref. design is
// //64 bits (i.e. 8 bytes) wide, each column address
// //addresses 8 bytes - therefore the byte address
// //needs to be divided-by-8 for the ddr2 memory cntrl
// //NOTE: addr_fifo_rddata[0] denotes read vs. write
// //and is not part of the address
// m_addr[30:25] <= 6'b000000; //upper bits not used
// m_addr[24:3] <= egress_addr_fifo_rddata[22:1];//byte-to-column mapping
// m_addr[2:0] <= 3'b000; //always 0 for 64B boundary
// egress_addr_fifo_rden <= 1'b0;
// //decode the transfer size information into bytes
// //and setup a counter (xfer_cnt) to keep track
// //of how much data is transferred (ingress or egress)
// case(egress_addr_fifo_rddata[25:23])
// 3'b000: xfer_cnt <= 10'b0000000100; //64B
// 3'b001: xfer_cnt <= 10'b0000001000; //128B
// 3'b010: xfer_cnt <= 10'b0000010000; //256B
// 3'b011: xfer_cnt <= 10'b0000100000; //512B
// 3'b100: xfer_cnt <= 10'b0001000000; //1KB
// 3'b101: xfer_cnt <= 10'b0010000000; //2KB
// 3'b110: xfer_cnt <= 10'b0100000000; //4KB
// default: xfer_cnt <= 10'b0000001000; //default to 128B
// endcase
// if(~m_af_afull)begin
// ddr_state <= R1;
// m_addr_wen <= 1'b1;//assert the write enable first
// m_cmd[2:0] <= 3'b001;
// end else begin
// ddr_state <= E_LOAD1;
// end
// end
// IN_LOAD0: begin //state for deasserting the addr_fifo_ren signal
// ddr_state <= IN_LOAD1;
// ingress_addr_fifo_rden <= 1'b0;
// end
// IN_LOAD1: begin /// Jiansong: m_addr distance 1 means 8bytes(64bits)
// //map a byte address into ddr2 column address:
// //since the ddr2 memory in this ref. design is
// //64 bits (i.e. 8 bytes) wide, each column address
// //addresses 8 bytes - therefore the byte address
// //needs to be divided-by-8 for the ddr2 memory cntrl
// //NOTE: addr_fifo_rddata[0] denotes read vs. write
// //and is not part of the address
// m_addr[30:25] <= 6'b000000; //upper bits not used
// m_addr[24:3] <= ingress_addr_fifo_rddata[22:1];//byte-to-column mapping
// m_addr[2:0] <= 3'b000; //always 0 for 64B boundary
// ingress_addr_fifo_rden <= 1'b0;
// //decode the transfer size information into bytes
// //and setup a counter (xfer_cnt) to keep track
// //of how much data is transferred (ingress or egress)
// case(ingress_addr_fifo_rddata[25:23])
// 3'b000: xfer_cnt <= 10'b0000000100; //64B
// 3'b001: xfer_cnt <= 10'b0000001000; //128B
// 3'b010: xfer_cnt <= 10'b0000010000; //256B
// 3'b011: xfer_cnt <= 10'b0000100000; //512B
// 3'b100: xfer_cnt <= 10'b0001000000; //1KB
// 3'b101: xfer_cnt <= 10'b0010000000; //2KB
// 3'b110: xfer_cnt <= 10'b0100000000; //4KB
// default: xfer_cnt <= 10'b0000001000; //default to 128B
// endcase
// if(~m_af_afull && ~m_wdf_afull)begin
// ddr_state <= W1;
// m_cmd[2:0] <= 3'b000;
// end else begin
// ddr_state <= IN_LOAD1;
// end
// end
////// LOAD0: begin //state for deasserting the addr_fifo_ren signal
////// ddr_state <= LOAD1;
////// addr_fifo_ren <= 1'b0;
////// end
////// //LOAD1 state for latching the read data from the ADDR/CTRL fifo
////// //and decoding the information
////// LOAD1: begin /// Jiansong: m_addr distance 1 means 8bytes(64bits)
////// //map a byte address into ddr2 column address:
////// //since the ddr2 memory in this ref. design is
////// //64 bits (i.e. 8 bytes) wide, each column address
////// //addresses 8 bytes - therefore the byte address
////// //needs to be divided-by-8 for the ddr2 memory cntrl
////// //NOTE: addr_fifo_rddata[0] denotes read vs. write
////// //and is not part of the address
////// m_addr[30:25] <= 6'b000000; //upper bits not used
////// m_addr[24:3] <= addr_fifo_rddata[22:1];//byte-to-column mapping
////// m_addr[2:0] <= 3'b000; //always 0 for 128B boundary
////// addr_fifo_ren <= 1'b0;
////// //decode the transfer size information into bytes
////// //and setup a counter (xfer_cnt) to keep track
////// //of how much data is transferred (ingress or egress)
////// case(addr_fifo_rddata[25:23])
////// 3'b000: xfer_cnt <= 10'b0000000100; //64B
////// 3'b001: xfer_cnt <= 10'b0000001000; //128B
////// 3'b010: xfer_cnt <= 10'b0000010000; //256B
////// 3'b011: xfer_cnt <= 10'b0000100000; //512B
////// 3'b100: xfer_cnt <= 10'b0001000000; //1KB
////// 3'b101: xfer_cnt <= 10'b0010000000; //2KB
////// 3'b110: xfer_cnt <= 10'b0100000000; //4KB
////// default: xfer_cnt <= 10'b0000001000; //default to 128B
////// endcase
////// //if bit 0 is a 1 then egress or read from ddr
////// //and jump to egress flow (state R)
////// /// Jiansong: if egress fifo is full, block the process
////// /// it's temporary solution to prevent egress fifo overflow
////////// if(addr_fifo_rddata[0] && ~m_af_afull)begin
////// if(addr_fifo_rddata[0] && ~m_af_afull && ~egress_pfull)begin
////// ddr_state <= R1;
////// m_addr_wen <= 1'b1;//assert the write enable first
////// m_cmd[2:0] <= 3'b001;
////// //otherwise it is ingress or write to ddr
////// //and jump to ingress flow (state W1)
////////// end else if(~m_af_afull && ~m_wdf_afull)begin
////// end else if(~addr_fifo_rddata[0] && ~m_af_afull && ~m_wdf_afull)begin
////// ddr_state <= W1;
////// m_cmd[2:0] <= 3'b000;
////// end else begin
////// ddr_state <= LOAD1;
////// end
////// end
NOOP: begin
m_data_wen <= 1'b0; //NOOP
m_addr_wen <= 1'b0; //NOOP
if (ToDDR_addr_valid) begin
//map a byte address into ddr2 column address:
//since the ddr2 memory in this ref. design is
//64 bits (i.e. 8 bytes) wide, each column address
//addresses 8 bytes - therefore the byte address
//needs to be divided-by-8 for the ddr2 memory cntrl
//NOTE: addr_fifo_rddata[0] denotes read vs. write
//and is not part of the address
m_addr[30:25] <= 6'b000000; //upper bits not used
m_addr[24:3] <= ToDDR_addr_data[22:1];//byte-to-column mapping
m_addr[2:0] <= 3'b000; //always 0 for 128B(64B?) boundary
// addr_fifo_ren <= 1'b0;
//decode the transfer size information into bytes
//and setup a counter (xfer_cnt) to keep track
//of how much data is transferred (ingress or egress)
case(ToDDR_addr_data[25:23])
3'b000: xfer_cnt <= 10'b00_0000_0100; //64B
3'b001: xfer_cnt <= 10'b00_0000_1000; //128B
3'b010: xfer_cnt <= 10'b00_0001_0000; //256B
3'b011: xfer_cnt <= 10'b00_0010_0000; //512B
3'b100: xfer_cnt <= 10'b00_0100_0000; //1KB
3'b101: xfer_cnt <= 10'b00_1000_0000; //2KB
3'b110: xfer_cnt <= 10'b01_0000_0000; //4KB
default: xfer_cnt <= 10'b00_0000_1000; //default to 128B
endcase
//if bit 0 is a 1 then egress or read from ddr
//and jump to egress flow (state R)
if((ToDDR_addr_data[0]) && (~m_af_afull))begin
ddr_state <= R1;
m_addr_wen <= 1'b1;//assert the write enable first
m_cmd[2:0] <= 3'b001;
//otherwise it is ingress or write to ddr
//and jump to ingress flow (state W1)
end else if((~ToDDR_addr_data[0]) && (~m_af_afull) && (~m_wdf_afull))begin
ddr_state <= W1;
m_cmd[2:0] <= 3'b000;
end else begin
// ddr_state <= LOAD1;
ddr_state <= NOOP;
end
end else begin
// ddr_state <= LOAD1;
ddr_state <= NOOP;
end
end
//Start of read from ddr2 (egress) flow
R1: begin
if(xfer_cnt == 10'h002)begin
ddr_state <= NOOP;
m_addr_wen <= 1'b0;
m_addr <= 31'h0000_0000;
xfer_cnt <= 10'h000;
end else if (~m_af_afull) begin
ddr_state <= R1;
m_addr_wen <= 1'b1;
m_addr <= m_addr[30:0] + 31'h0000_0004;
xfer_cnt <= xfer_cnt[9:0] - 10'h002;
end else begin
ddr_state <= R1;
m_addr_wen <= 1'b0;
m_addr <= m_addr[30:0];
xfer_cnt <= xfer_cnt[9:0];
end
// //assert the write enable and increment the address
// //to the memory cntrl;
// //the ddr2 memory in this reference design is configured as
// //burst-of-4 the address needs to be incremented by four
// //for each read request
// m_addr[30:0] <= m_addr[30:0] + 3'b100;
// xfer_cnt <= xfer_cnt - 3'b10;
// //when it gets to the penultimate transfer, go to R2
// //to deassert the write enable
// if(xfer_cnt == 10'h002)begin
// ddr_state <= NOOP;
// m_addr_wen <= 1'b0;
// end else begin
// ddr_state <= R1;
// m_addr_wen <= 1'b1;
// end
end
// R2: begin
// ddr_state <= NOOP;
// m_addr_wen <= 1'b0;
// end
//Start of write to ddr2 (ingress) flow
W1: begin //assert the read enable from the ingress fifo
//to get the ingress data ready for writing
//into the memory cntrl
m_addr_wen <= 1'b0;
m_data_wen <= 1'b0;
// if(at_least_64B && ~m_wdf_afull)begin
if((~ingress_fifo_almostempty) && (~m_wdf_afull))begin
ddr_state <= W2;
ingress_fifo_rden <= 1'b1;
end else begin
ddr_state <= W1;
ingress_fifo_rden <= 1'b0;
end
end
W2: begin //now assert the address and data write enables
//to the memory cntrl
ddr_state <= W3;
m_addr_wen <= 1'b1;
m_data_wen <= 1'b1;
ingress_fifo_rden <= 1'b1;
end
W3: begin //deassert the address write enable but keep the
//data write enable asserted - this is because
//the data is written in 16 bytes (128 bit) at a time
//and each address is for 32 bytes, so we need two
//data cycles for each address cycles;
//also increment the address to the memory controller
//to the next column
if((~ingress_fifo_almostempty) && (~m_wdf_afull))begin
ddr_state <= W4;
m_addr_wen <= 1'b0;
m_data_wen <= 1'b1;
ingress_fifo_rden <= 1'b1;
m_addr[30:0] <= m_addr[30:0] + 3'b100;
end else begin
ddr_state <= W3;
m_addr_wen <= 1'b0;
m_data_wen <= 1'b0;
ingress_fifo_rden <= 1'b0;
m_addr[30:0] <= m_addr[30:0];
end
end
W4: begin //write the second column address to the memory cntrl
ddr_state <= W5;
m_addr_wen <= 1'b1;
m_data_wen <= 1'b1;
ingress_fifo_rden <= 1'b1;
end
W5: begin //decide whether to repeat the cycle or not
m_addr_wen <= 1'b0;
//when it gets to the penultimate transfer, deassert the
//read enable to the ingress fifo read enable and then
//jump to W6 so that the data and address write enables
//to the memory cntrl are deasserted one clock later
if(xfer_cnt == 10'h004) begin
ddr_state <= NOOP; /// bug? no. state W6 is not used
m_data_wen <= 1'b1;
ingress_fifo_rden <= 1'b0;
end else if((~ingress_fifo_almostempty) && (~m_af_afull) && (~m_wdf_afull))begin
//otherwise decrement the transfer count, increase the
//address and repeat the cycle
ddr_state <= W2;
m_data_wen <= 1'b1;
ingress_fifo_rden <= 1'b1;
xfer_cnt <= xfer_cnt - 3'b100;
m_addr[30:0] <= m_addr[30:0] + 3'b100;
end else begin
ddr_state <= W5;
m_data_wen <= 1'b0;
ingress_fifo_rden <= 1'b0;
// ddr_state <= WAIT_FOR_ROOM;
// ingress_fifo_rden <= 1'b0;
end
end
// W6: begin /// this state is not used
// ddr_state <= NOOP;
// m_data_wen <= 1'b0;
// m_addr_wen <= 1'b0;
// end
// WAIT_FOR_ROOM: begin
// m_addr_wen <= 1'b0;
// if(~m_af_afull && ~m_wdf_afull)begin
// m_data_wen <= 1'b1;
// ddr_state <= W5;
// end else begin
// m_data_wen <= 1'b0;
// ddr_state <= WAIT_FOR_ROOM;
// end
// end
default: begin
ddr_state <= NOOP;
//// addr_fifo_ren <= 1'b0;
// egress_addr_fifo_rden <= 1'b0;
// ingress_addr_fifo_rden <= 1'b0;
xfer_cnt <= 10'b00_0000_0000;
m_addr[30:0] <= 31'h0000_0000;
m_cmd[2:0] <= 3'b000;
m_addr_wen <= 1'b0;
m_data_wen <= 1'b0;
ingress_fifo_rden <= 1'b0;
end
endcase
end
end
///////////////////////////////////////////////////////////
/////// egress_data_fifo to ToFRL_data_fifos ////////////
///////////////////////////////////////////////////////////
wire E_PASS_one;
rising_edge_detect E_PASS_one_inst(.clk(ddr_clk),.rst(ddr_reset),.in(egress_state==E_PASS),.one_shot_out(E_PASS_one));
//reg FromDDR_addr_valid;
reg [8:0] egress_cnt;
always@(posedge ddr_clk) begin
if (ddr_reset) begin
egress_fifo_rden <= 1'b0;
egress_cnt <= 9'b000000_000;
egress_state <= E_IDLE;
end else begin
case(egress_state)
E_IDLE: begin
if (~FromDDR_addr_fifo_empty) begin
FromDDR_addr_fifo_rden <= 1'b1;
egress_fifo_rden <= 1'b0;
egress_cnt <= 9'b000000_000;
egress_state <= E_WAIT_ADDR;
end else begin
FromDDR_addr_fifo_rden <= 1'b0;
egress_fifo_rden <= 1'b0;
egress_cnt <= 9'b000000_000;
egress_state <= E_IDLE;
end
end
E_WAIT_ADDR: begin
FromDDR_addr_fifo_rden <= 1'b0;
egress_fifo_rden <= 1'b0;
egress_cnt <= 9'b000000_000;
egress_state <= E_PASS_START;
end
E_PASS_START: begin
// if ( ~ToFRL_data_fifo_pfull_this & ~egress_fifo_pempty ) begin
if ( ~ToFRL_data_fifo_almost_full_this & ~egress_fifo_pempty ) begin /// liuchang
egress_fifo_rden <= 1'b1;
case(FromDDR_addr_fifo_rddata[25:23])
3'b001: egress_cnt <= 9'b000001_000 - 9'b000000_001; //128B
3'b010: egress_cnt <= 9'b000010_000 - 9'b000000_001; //256B
3'b011: egress_cnt <= 9'b000100_000 - 9'b000000_001; //512B
3'b100: egress_cnt <= 9'b001000_000 - 9'b000000_001; //1KB
3'b101: egress_cnt <= 9'b010000_000 - 9'b000000_001; //2KB
3'b110: egress_cnt <= 9'b100000_000 - 9'b000000_001; //4KB
default: egress_cnt <= 9'b000001_000 - 9'b000000_001; //default to 128B
endcase
egress_state <= E_PASS;
end else begin
egress_fifo_rden <= 1'b0;
egress_cnt <= 9'b000000_000;
egress_state <= E_PASS_START;
end
end
E_PASS: begin
if (egress_cnt == 9'b000000_000) begin
egress_fifo_rden <= 1'b0;
egress_cnt <= egress_cnt;
egress_state <= E_IDLE;
end else begin
// if ( ~ToFRL_data_fifo_pfull_this & ~egress_fifo_pempty ) begin // flow control, while the block size increases to 1kB, flow control becomes necessary
if ( ~ToFRL_data_fifo_almost_full_this & ~egress_fifo_pempty ) begin /// liuchang
egress_fifo_rden <= 1'b1;
egress_cnt <= egress_cnt - 9'b000000_001;
end else begin
egress_fifo_rden <= 1'b0;
egress_cnt <= egress_cnt;
end
egress_state <= E_PASS;
end
end
default: begin
egress_fifo_rden <= 1'b0;
egress_cnt <= 9'b000000_000;
egress_state <= E_IDLE;
end
endcase
end
end
//always@(posedge ddr_clk) begin
// if (ddr_reset)
// FromDDR_addr_valid <= 1'b0;
// else if (~FromDDR_addr_valid) begin
// if (FromDDR_addr_fifo_rden)
// FromDDR_addr_valid <= 1'b1;
// else
// FromDDR_addr_valid <= FromDDR_addr_valid;
// end else begin
// if (E_PASS_one)
// FromDDR_addr_valid <= 1'b0;
// else
// FromDDR_addr_valid <= FromDDR_addr_valid;
// end
//end
//always@(posedge ddr_clk) begin
// if (ddr_reset)
// FromDDR_addr_fifo_rden <= 1'b0;
// else if (~FromDDR_addr_valid & ~FromDDR_addr_fifo_rden & ~FromDDR_addr_fifo_empty)
// FromDDR_addr_fifo_rden <= 1'b1;
// else
// FromDDR_addr_fifo_rden <= 1'b0;
//end
//
//always@(posedge ddr_clk) begin
// if (ddr_reset) begin
// egress_fifo_rden <= 1'b0;
// egress_cnt <= 9'b000000_000;
// egress_pathindex <= 2'b00;
// egress_state <= E_IDLE;
// end else begin
// case(egress_state)
// E_IDLE: begin
// if (FromDDR_addr_valid &
// ( (FromDDR_addr_fifo_rddata[27:26]==2'b00 & ~ToFRL_data_fifo_pfull) |
// (FromDDR_addr_fifo_rddata[27:26]==2'b01 & ~ToFRL_2nd_data_fifo_pfull) |
// (FromDDR_addr_fifo_rddata[27:26]==2'b10 & ~ToFRL_3rd_data_fifo_pfull) |
// (FromDDR_addr_fifo_rddata[27:26]==2'b11 & ~ToFRL_4th_data_fifo_pfull) ) &
// ~egress_fifo_pempty
// ) begin
// egress_fifo_rden <= 1'b1;
// egress_pathindex <= FromDDR_addr_fifo_rddata[27:26];
// case(FromDDR_addr_fifo_rddata[25:23])
// 3'b001: egress_cnt <= 9'b000001_000 - 9'b000000_001; //128B
// 3'b010: egress_cnt <= 9'b000010_000 - 9'b000000_001; //256B
// 3'b011: egress_cnt <= 9'b000100_000 - 9'b000000_001; //512B
// 3'b100: egress_cnt <= 9'b001000_000 - 9'b000000_001; //1KB
// 3'b101: egress_cnt <= 9'b010000_000 - 9'b000000_001; //2KB
// 3'b110: egress_cnt <= 9'b100000_000 - 9'b000000_001; //4KB
// default: egress_cnt <= 9'b000001_000 - 9'b000000_001; //default to 128B
// endcase
// egress_state <= E_PASS;
// end else begin
// egress_fifo_rden <= 1'b0;
// egress_pathindex <= egress_pathindex;
// egress_cnt <= 9'b000000_000;
// egress_state <= E_IDLE;
// end
// end
// E_PASS: begin
// if (egress_cnt == 9'b000000_000) begin
// egress_fifo_rden <= 1'b0;
// egress_cnt <= egress_cnt;
// egress_state <= E_IDLE;
// end else begin
// if (egress_fifo_pempty | ToFRL_data_fifo_almost_full_this) begin // flow control, while the block size increases to 1kB, flow control becomes necessary
// egress_fifo_rden <= 1'b0;
// egress_cnt <= egress_cnt;
// end else begin
// egress_fifo_rden <= 1'b1;
// egress_cnt <= egress_cnt - 9'b000000_001;
// end
// egress_state <= E_PASS;
// end
// egress_pathindex <= egress_pathindex;
// end
// default: begin
// egress_fifo_rden <= 1'b0;
// egress_pathindex <= egress_pathindex;
// egress_cnt <= 9'b000000_000;
// egress_state <= E_IDLE;
// end
// endcase
// end
//end
assign ToFRL_data_fifo_pfull_this = FromDDR_addr_fifo_rddata[27] ?
(FromDDR_addr_fifo_rddata[26] ?
ToFRL_4th_data_fifo_pfull : ToFRL_3rd_data_fifo_pfull) :
(FromDDR_addr_fifo_rddata[26] ?
ToFRL_2nd_data_fifo_pfull : ToFRL_data_fifo_pfull);
assign ToFRL_data_fifo_almost_full_this = FromDDR_addr_fifo_rddata[27] ?
(FromDDR_addr_fifo_rddata[26] ?
ToFRL_4th_data_fifo_almost_full : ToFRL_3rd_data_fifo_almost_full) :
(FromDDR_addr_fifo_rddata[26] ?
ToFRL_2nd_data_fifo_almost_full : ToFRL_data_fifo_almost_full);
always@(posedge ddr_clk) ToFRL_data_fifo_wren <= egress_fifo_rden & (FromDDR_addr_fifo_rddata[27:26]==2'b00);
assign ToFRL_data_fifo_wrdata = egress_fifo_rddata[127:0];
always@(posedge ddr_clk) ToFRL_2nd_data_fifo_wren <= egress_fifo_rden & (FromDDR_addr_fifo_rddata[27:26]==2'b01);
assign ToFRL_2nd_data_fifo_wrdata = egress_fifo_rddata[127:0];
`ifdef MIMO_4X4
always@(posedge ddr_clk) ToFRL_3rd_data_fifo_wren <= egress_fifo_rden & (FromDDR_addr_fifo_rddata[27:26]==2'b10);
assign ToFRL_3rd_data_fifo_wrdata = egress_fifo_rddata[127:0];
always@(posedge ddr_clk) ToFRL_4th_data_fifo_wren <= egress_fifo_rden & (FromDDR_addr_fifo_rddata[27:26]==2'b11);
assign ToFRL_4th_data_fifo_wrdata = egress_fifo_rddata[127:0];
`endif //MIMO_4X4
FromDDR_addr_cntrl_fifo FromDDR_addr_cntrl_fifo_inst(
.clk (ddr_clk),
.rst (ddr_reset),
.din (FromDDR_addr_fifo_wrdata[31:0]), //32
.wr_en (FromDDR_addr_fifo_wren),
.rd_en (FromDDR_addr_fifo_rden),
.dout (FromDDR_addr_fifo_rddata[31:0]), //32
.empty (FromDDR_addr_fifo_empty),
.full (FromDDR_addr_fifo_full)
);
//egress_addr_cntrl_fifo ToDDR_addr_cntrl_fifo(
// .din (ToDDR_addr_fifo_wrdata[31:0]), //32
// .rd_clk (ddr_clk),
// .rd_en (ToDDR_addr_fifo_ren),
// .rst (reset),
// .wr_clk (dma_clk),
// .wr_en (ToDDR_addr_fifo_wren),
// .dout (ToDDR_addr_fifo_rddata[31:0]), //32
// .empty (ToDDR_addr_fifo_empty),
// .full (ToDDR_addr_fifo_full)
//);
/// FIFOs for TX requests
egress_addr_cntrl_fifo egress_addr_cntrl_fifo(
.din (egress_addr_fifo_wrdata[31:0]), //16
.rd_clk (ddr_clk),
.rd_en (egress_addr_fifo_rden),
.rst (reset),
.wr_clk (dma_clk),
.wr_en (egress_addr_fifo_wren),
// .almost_empty (egress_addr_fifo_almost_empty),
// .almost_full (egress_addr_fifo_almost_full),
.dout (egress_addr_fifo_rddata[31:0]), //16
.empty (egress_addr_fifo_empty),
.full (egress_addr_fifo_full)
);
egress_addr_cntrl_fifo egress_2nd_addr_cntrl_fifo(
.din (egress_2nd_addr_fifo_wrdata[31:0]), //16
.rd_clk (ddr_clk),
.rd_en (egress_2nd_addr_fifo_rden),
.rst (reset),
.wr_clk (dma_clk),
.wr_en (egress_2nd_addr_fifo_wren),
.dout (egress_2nd_addr_fifo_rddata[31:0]), //16
.empty (egress_2nd_addr_fifo_empty),
.full (egress_2nd_addr_fifo_full)
);
`ifdef MIMO_4X4
egress_addr_cntrl_fifo egress_3rd_addr_cntrl_fifo(
.din (egress_3rd_addr_fifo_wrdata[31:0]), //16
.rd_clk (ddr_clk),
.rd_en (egress_3rd_addr_fifo_rden),
.rst (reset),
.wr_clk (dma_clk),
.wr_en (egress_3rd_addr_fifo_wren),
.dout (egress_3rd_addr_fifo_rddata[31:0]), //16
.empty (egress_3rd_addr_fifo_empty),
.full (egress_3rd_addr_fifo_full)
);
egress_addr_cntrl_fifo egress_4th_addr_cntrl_fifo(
.din (egress_4th_addr_fifo_wrdata[31:0]), //16
.rd_clk (ddr_clk),
.rd_en (egress_4th_addr_fifo_rden),
.rst (reset),
.wr_clk (dma_clk),
.wr_en (egress_4th_addr_fifo_wren),
.dout (egress_4th_addr_fifo_rddata[31:0]), //16
.empty (egress_4th_addr_fifo_empty),
.full (egress_4th_addr_fifo_full)
);
`endif //MIMO_4X4
/// Jiansong: added for ingress/transfer requests
ingress_addr_cntrl_fifo ingress_addr_cntrl_fifo(
.din (ingress_addr_fifo_wrdata[31:0]), //128
.rd_clk (ddr_clk),
.rd_en (ingress_addr_fifo_rden),
.rst (reset),
.wr_clk (dma_clk),
.wr_en (ingress_addr_fifo_wren),
.dout (ingress_addr_fifo_rddata[31:0]), //128
.prog_full (ingress_addr_fifo_pfull),
.empty (ingress_addr_fifo_empty),
.full (ingress_addr_fifo_full)
// .almost_empty (ingress_addr_fifo_almost_empty),
// .almost_full (ingress_addr_fifo_almost_full),
);
//////ADDRESS/CNTRL FIFO to cross clock domains 32X64
////addr_cntrl_fifo addr_cntrl_fifo_inst(
////.din (addr_fifo_wrdata[31:0]), //32
////.rd_clk (ddr_clk),
////.rd_en (addr_fifo_ren),
////.rst (reset),
////.wr_clk (dma_clk),
////.wr_en (addr_fifo_wren),
////.almost_empty (addr_fifo_almost_empty),
////.almost_full (addr_fifo_almost_full),
////.dout (addr_fifo_rddata[31:0]), //32
////.empty (addr_fifo_empty),
////.full (addr_fifo_full)
////);
////// END ADDRESS/CNTRL FIFO
/// Jiansong: generate egress_overflow_one signal
rising_edge_detect egress_overflow_one_inst(
.clk(ddr_clk),
.rst(reset),
.in(egress_fifo_full),
.one_shot_out(egress_overflow_one)
);
ToFRL_data_fifo ToFRL_data_fifo_inst(
.rst (ddr_reset),
.wr_clk (ddr_clk),
.rd_clk (radio_clk),
.din (ToFRL_data_fifo_wrdata[127:0]), // Bus [127 : 0]
.wr_en (ToFRL_data_fifo_wren),
.rd_en (ToFRL_data_fifo_rden),
.dout (ToFRL_data_fifo_rddata[31:0]), // Bus [31 : 0]
.full (ToFRL_data_fifo_full),
.almost_full(ToFRL_data_fifo_almost_full),
.empty (ToFRL_data_fifo_empty),
.prog_full (ToFRL_data_fifo_pfull), // 768 of 128 /// liuchang: 2047 of 128
.prog_empty (ToFRL_data_fifo_pempty) // 7 of 32
);
ToFRL_data_fifo ToFRL_2nd_data_fifo_inst(
.rst (ddr_reset),
.wr_clk (ddr_clk),
.rd_clk (radio_2nd_clk),
.din (ToFRL_2nd_data_fifo_wrdata[127:0]), // Bus [127 : 0]
.wr_en (ToFRL_2nd_data_fifo_wren),
.rd_en (ToFRL_2nd_data_fifo_rden),
.dout (ToFRL_2nd_data_fifo_rddata[31:0]), // Bus [31 : 0]
.full (ToFRL_2nd_data_fifo_full),
.almost_full(ToFRL_2nd_data_fifo_almost_full),
.empty (ToFRL_2nd_data_fifo_empty),
.prog_full (ToFRL_2nd_data_fifo_pfull), // 768 of 128
.prog_empty (ToFRL_2nd_data_fifo_pempty) // 7 of 32
);
`ifdef MIMO_4X4
ToFRL_data_fifo ToFRL_3rd_data_fifo_inst(
.rst (ddr_reset),
.wr_clk (ddr_clk),
.rd_clk (radio_3rd_clk),
.din (ToFRL_3rd_data_fifo_wrdata[127:0]), // Bus [127 : 0]
.wr_en (ToFRL_3rd_data_fifo_wren),
.rd_en (ToFRL_3rd_data_fifo_rden),
.dout (ToFRL_3rd_data_fifo_rddata[31:0]), // Bus [31 : 0]
.full (ToFRL_3rd_data_fifo_full),
.almost_full(ToFRL_3rd_data_fifo_almost_full),
.empty (ToFRL_3rd_data_fifo_empty),
.prog_full (ToFRL_3rd_data_fifo_pfull), // 768 of 128
.prog_empty (ToFRL_3rd_data_fifo_pempty) // 7 of 32
);
ToFRL_data_fifo ToFRL_4th_data_fifo_inst(
.rst (ddr_reset),
.wr_clk (ddr_clk),
.rd_clk (radio_4th_clk),
.din (ToFRL_4th_data_fifo_wrdata[127:0]), // Bus [127 : 0]
.wr_en (ToFRL_4th_data_fifo_wren),
.rd_en (ToFRL_4th_data_fifo_rden),
.dout (ToFRL_4th_data_fifo_rddata[31:0]), // Bus [31 : 0]
.full (ToFRL_4th_data_fifo_full),
.almost_full(ToFRL_4th_data_fifo_almost_full),
.empty (ToFRL_4th_data_fifo_empty),
.prog_full (ToFRL_4th_data_fifo_pfull), // 768 of 128
.prog_empty (ToFRL_4th_data_fifo_pempty) // 7 of 32
);
`endif //MIMO_4X4
//pipeline the egress write enable and data from the memory cntrl
//and write into the egress fifos
always@(posedge ddr_clk)begin
if(ddr_reset)begin
egress_fifo_wren <= 1'b0;
end else begin
egress_fifo_wren <= m_data_valid;
end
end
always@(posedge ddr_clk) m_rddata_reg[127:0] <= m_rddata[127:0];
// size = 8KB
Egress_data_FIFO Egress_data_FIFO_inst (
.rst (ddr_reset),
.clk (ddr_clk),
//// .din (m_rddata_reg[127:0]),
// .din ({m_rddata_reg[15:0],m_rddata_reg[31:16],m_rddata_reg[47:32],
// m_rddata_reg[63:48],m_rddata_reg[79:64],m_rddata_reg[95:80],
// m_rddata_reg[111:96],m_rddata_reg[127:112]}),
// 32b data width or 16-bit IQ
.din ({m_rddata_reg[31:0],m_rddata_reg[63:32],
m_rddata_reg[95:64],m_rddata_reg[127:96]}),
// .wr_clk (ddr_clk),
// .rd_en (egress_fifo_ctrl[0]),
.rd_en (egress_fifo_rden),
.wr_en (egress_fifo_wren),
.dout (egress_fifo_rddata[127:0]),
// .rd_clk (radio_clk),
.empty (egress_fifo_empty),
// .empty (),
.full (egress_fifo_full),
.prog_empty (egress_fifo_pempty), // 7 of 128 /// liuchang: 2 of 128
.prog_full (egress_fifo_pfull) //240/512 of 128 /// liuchang: 1919 of 128
);
/// Jiansong: data count
always@(posedge ddr_clk)begin
if(reset)
egress_wr_data_count <= 32'h0000_0000;
else if (egress_fifo_wren)
egress_wr_data_count <= egress_wr_data_count + 32'h0000_0001;
else
egress_wr_data_count <= egress_wr_data_count;
end
// Jiansong: it is replaced by an IP core fifo. The new fifo is from 200MHz to
// 44MHz (or 40MHz). The old one is from 200MHz to 250MHz. So the timing
// requirement is relaxed.
/////// Jiansong: why not use IP core?
//////the egress fifos are built using two fifo36 primitives in
//////parallel - they have been placed in a wrapper because the
//////read data path and empty signal has been pipelined for timing purposes
//////(mainly because of tight timing on the empty signal) and
//////require some complex logic to support - the signals
//////at this wrapper interface appear to the user exactly like
//////a regular fifo i.e. there is no extra clock of latency on the
//////read datapath due to the pipeline.
////egress_fifo_wrapper egress_fifo_wrapper_inst(
//// .RST(reset),
//// .WRCLK(ddr_clk),
//// .WREN(egress_fifo_wren),
//// .DI(m_rddata_reg[127:0]),
//// .FULL(egress_full),
//// .ALMOSTFULL(egress_pfull),
//// .RDCLK(dma_clk),
//// .RDEN(egress_fifo_ctrl[0]),
//// .DO(egress_data[127:0]),
//// .EMPTY(empty),
//// .ALMOSTEMPTY(egress_pempty)
////);
//assign egress_fifo_status[2] = egress_pfull;
//assign egress_fifo_status[1] = egress_empty;
//assign egress_fifo_status[0] = egress_pempty;
//assign egress_fifo_pempty = egress_pempty;
ingress_data_fifo ingress_data_fifo_inst(
.din (ingress_data[127:0]),
.rd_clk (ddr_clk),
.rd_en (ingress_fifo_rden),
.rst (reset),
.wr_clk (dma_clk),
// .wr_en (ingress_fifo_ctrl[0]),
.wr_en (ingress_fifo_wren),
.dout (m_wrdata[127:0]),
.empty (ingress_fifo_empty),
// .empty (),
.almost_empty (ingress_fifo_almostempty),
.full (ingress_fifo_full),
// .full (),
.prog_empty (ingress_fifo_pempty), // set to half of the fifo, used for transfer flow control
.prog_full (ingress_fifo_pfull) // flow control from rx engine
// .rd_data_count (rdcount[8:0]),
// .wr_data_count (wrcount[8:0])
);
/// Jiansong: the parameter ALMOST_EMPTY_OFFSET not realy works, don't know why
////
//////INGRESS or WRITE to DDR2 MEMORY FIFO
////FIFO36_72 #(
//////.ALMOST_EMPTY_OFFSET (9'h005),
////.ALMOST_EMPTY_OFFSET (9'h100), // Jiansong: if (~almost empty), assert pause_read_requests
////.ALMOST_FULL_OFFSET (9'h1C4),
////.DO_REG (1),
////.EN_ECC_WRITE ("FALSE"),
////.EN_ECC_READ ("FALSE"),
////.EN_SYN ("FALSE"),
////.FIRST_WORD_FALL_THROUGH ("FALSE"))
////ingress_fifo_a(
////.ALMOSTEMPTY (ingress_fifo_pempty_a),
////.ALMOSTFULL (ingress_fifo_status_a[0]),
////.DBITERR (),
////.DO (m_wrdata[63:0]),
////.DOP (),
////.ECCPARITY (),
////.EMPTY (ingress_fifo_empty_a),
////.FULL (ingress_fifo_status_a[1]),
////.RDCOUNT (),
////.RDERR (),
////.SBITERR (),
////.WRCOUNT (),
////.WRERR (),
////.DI (ingress_data[63:0]),
////.DIP (),
////.RDCLK (ddr_clk),
////.RDEN (ingress_fifo_rden),
////.RST (reset),
////.WRCLK (dma_clk),
////.WREN (ingress_fifo_ctrl[0])
////);
////
////FIFO36_72 #(
//////.ALMOST_EMPTY_OFFSET (9'h005),
////.ALMOST_EMPTY_OFFSET (9'h100), // Jiansong: if (~almost empty), assert pause_read_requests
////.ALMOST_FULL_OFFSET (9'h1C4),
////.DO_REG (1),
////.EN_ECC_WRITE ("FALSE"),
////.EN_ECC_READ ("FALSE"),
////.EN_SYN ("FALSE"),
////.FIRST_WORD_FALL_THROUGH ("FALSE"))
////ingress_fifo_b(
////.ALMOSTEMPTY (ingress_fifo_pempty_b),
////.ALMOSTFULL (ingress_fifo_status_b[0]),
////.DBITERR (),
////.DO (m_wrdata[127:64]),
////.DOP (),
////.ECCPARITY (),
////.EMPTY (ingress_fifo_empty_b),
////.FULL (ingress_fifo_status_b[1]),
////.RDCOUNT (rdcount[8:0]),
////.RDERR (),
////.SBITERR (),
////.WRCOUNT (wrcount[8:0]),
////.WRERR (),
////.DI (ingress_data[127:64]),
////.DIP (),
////.RDCLK (ddr_clk),
////.RDEN (ingress_fifo_rden),
////.RST (reset),
////.WRCLK (dma_clk),
////.WREN (ingress_fifo_ctrl[0])
////);
///////////////////////////////////////////////////////////////////////////
//////
////// Block-based transfer detector needed when DDR2 clock is faster
////// than PCIe clock i.e. ML505. Otherwise could use empty flag.
//////
////// Monitors the rdcount and wrcount of the ingress_fifo to determine
////// when there is at least 64B block of data in the fifo
//////
////// signal at_least_64B is fed to the ddr state machine
//////
///////////////////////////////////////////////////////////////////////////
//////Binary to Gray encode wrcount /// interesting
////always@(posedge dma_clk)begin
//// wrcount_gray_dma[8:0] = {wrcount[8], wrcount[8:1] ^ wrcount[7:0]};
////end
////
//////transfer to ddr_clock domain
////always@(posedge ddr_clk)begin
//// wrcount_gray_ddr <= wrcount_gray_ddr1;
//// wrcount_gray_ddr1 <= wrcount_gray_dma;
////end
////
//////Gray to Binary decode wrcount_gray_ddr and register the output
////assign wrcount_ddr[8:0] = {wrcount_gray_ddr[8],
//// wrcount_ddr[8:1] ^ wrcount_gray_ddr[7:0]};
////always@(posedge ddr_clk)
//// wrcount_ddr_reg[8:0] <= wrcount_ddr[8:0];
////
//////need to pipeline rdcount since DO_REG is set to 1
////always@(posedge ddr_clk)begin
//// if(ingress_fifo_rden) rdcount_reg <= rdcount;
////end
////
//////do a compare - if read count is 4 (or more) less than write count than that
//////means there is at least 64B of data in the ingress fifo and I can
//////safely do a 64B block read of the fifo
////always@(posedge ddr_clk)begin
//// if(ddr_reset)begin
//// at_least_64B <= 1'b0;
//// end else begin
//// at_least_64B <= ((wrcount_ddr_reg[8:0] - rdcount_reg[8:0]) >= 9'h004)
//// ? 1'b1 : 1'b0;
//// end
////end
//Careful with the fifo status signals when using two fifos in parallel
//Empty flags (and Almost Empty flags) which are synchronous to rdclk
//could deassert on different rdclk cycles due to minute differences in the
//wrclk arrival time (wrclk clock skew). This is because deassertion
//is caused by writing data into an empty fifo i.e. a wrclk domain event
//and this event must cross clock domains.
//Assertion is caused by reading the last piece of data out of the fifo.
//Since rden is a rdclk domain signal/event it is guaranteed that both fifos
//will assert empty on the same rdclk cycle (as long as rden and rdclk are
//are the same signals for both fifos)
//Similarily the Full flags (and almost full flags) which are synchronous to
//wrclk could deassert on different wrclk cycles due to minute differences
//in the rdclk arrival time (rdclk clock skew).
//In both cases the flags should be wire or'ed (since they are positive logic)
//so that the flag doesn't deassert unless both flags are deasserted
//assign ingress_fifo_pempty = ingress_fifo_pempty_a | ingress_fifo_pempty_b;
//assign ingress_fifo_pempty = ingress_fifo_pempty_a & ingress_fifo_pempty_b;
//assign ingress_fifo_empty = ingress_fifo_empty_a | ingress_fifo_empty_b;
//assign ingress_fifo_status[1:0] = ingress_fifo_status_a[1:0]
// | ingress_fifo_status_b[1:0];
always@(posedge ddr_clk) begin
DebugDDRSignals[0] <= ~egress_addr_fifo_full;
DebugDDRSignals[1] <= ~egress_2nd_addr_fifo_full;
DebugDDRSignals[2] <= ~egress_3rd_addr_fifo_full;
DebugDDRSignals[3] <= ~egress_4th_addr_fifo_full;
DebugDDRSignals[4] <= egress_addr_fifo_empty;
DebugDDRSignals[5] <= egress_2nd_addr_fifo_empty;
DebugDDRSignals[6] <= egress_3rd_addr_fifo_empty;
DebugDDRSignals[7] <= egress_4th_addr_fifo_empty;
DebugDDRSignals[8] <= ~ingress_fifo_pfull;
DebugDDRSignals[9] <= ~ingress_addr_fifo_full;
DebugDDRSignals[10] <= ~ingress_addr_fifo_pfull;
DebugDDRSignals[11] <= ToDDR_addr_valid;
DebugDDRSignals[12] <= ~FromDDR_addr_fifo_full;
DebugDDRSignals[13] <= FromDDR_addr_fifo_empty;
// DebugDDRSignals[14] <= ~FromDDR_addr_valid;
// DebugDDRSignals[15]
DebugDDRSignals[16] <= ~m_af_afull;
DebugDDRSignals[17] <= ~m_wdf_afull;
// DebugDDRSignals[19:18]
DebugDDRSignals[20] <= egress_fifo_pempty;
DebugDDRSignals[21] <= ~egress_fifo_pfull;
DebugDDRSignals[22] <= egress_fifo_empty;
DebugDDRSignals[23] <= ~egress_fifo_full;
DebugDDRSignals[24] <= ~ToFRL_data_fifo_pfull;
DebugDDRSignals[25] <= ~ToFRL_2nd_data_fifo_pfull;
DebugDDRSignals[26] <= ~ToFRL_3rd_data_fifo_pfull;
DebugDDRSignals[27] <= ~ToFRL_4th_data_fifo_pfull;
DebugDDRSignals[28] <= ToFRL_data_fifo_pempty;
DebugDDRSignals[29] <= ToFRL_2nd_data_fifo_pempty;
DebugDDRSignals[30] <= ToFRL_3rd_data_fifo_pempty;
DebugDDRSignals[31] <= ToFRL_4th_data_fifo_pempty;
end
always@(posedge ddr_clk) begin
DebugDDRSMs[2:0] <= token[2:0];
DebugDDRSMs[8:4] <= ddr_state[4:0];
end
always@(posedge ddr_clk) begin
if (ddr_reset)
DebugDDRFIFOFullCnt[31:16] <= 16'h0000;
else if (ingress_fifo_full)
DebugDDRFIFOFullCnt[31:16] <= DebugDDRFIFOFullCnt[31:16] + 16'h0001;
else
DebugDDRFIFOFullCnt[31:16] <= DebugDDRFIFOFullCnt[31:16];
end
always@(posedge ddr_clk) begin
if (ddr_reset)
DebugDDRFIFOFullCnt[15:0] <= 16'h0000;
else if (egress_fifo_full)
DebugDDRFIFOFullCnt[15:0] <= DebugDDRFIFOFullCnt[15:0] + 16'h0001;
else
DebugDDRFIFOFullCnt[15:0] <= DebugDDRFIFOFullCnt[15:0];
end
always@(posedge ddr_clk) begin
if (ddr_reset)
DebugDDREgressFIFOCnt[31:16] <= 16'h0000;
else if (egress_fifo_wren)
DebugDDREgressFIFOCnt[31:16] <= DebugDDREgressFIFOCnt[31:16] + 16'h0001;
else
DebugDDREgressFIFOCnt[31:16] <= DebugDDREgressFIFOCnt[31:16];
end
always@(posedge ddr_clk) begin
if (ddr_reset)
DebugDDREgressFIFOCnt[15:0] <= 16'h0000;
else if (egress_fifo_rden)
DebugDDREgressFIFOCnt[15:0] <= DebugDDREgressFIFOCnt[15:0] + 16'h0001;
else
DebugDDREgressFIFOCnt[15:0] <= DebugDDREgressFIFOCnt[15:0];
end
`ifdef sora_chipscope
reg TX_Start_one_ddr;
always@(posedge ddr_clk) TX_Start_one_ddr <= TX_Start_one;
ila ila_inst (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(ddr_clk), // IN
.DATA({ egress_fifo_empty,
egress_fifo_rden,
egress_fifo_full,
egress_fifo_wren,
egress_fifo_pempty,
ToFRL_data_fifo_pfull_this,
ToFRL_data_fifo_pfull,
ToFRL_2nd_data_fifo_pfull,
ToFRL_3rd_data_fifo_pfull,
ToFRL_4th_data_fifo_pfull,
FromDDR_addr_fifo_empty,
FromDDR_addr_fifo_rden,
FromDDR_addr_fifo_full,
FromDDR_addr_fifo_wren,
FromDDR_addr_fifo_rddata[27:26],
FromDDR_addr_fifo_rddata[25:23],
egress_cnt[8:0],
ToFRL_data_fifo_wren,
ToFRL_2nd_data_fifo_wren
}), // IN BUS [17:0]
.TRIG0(TX_Start_one_ddr) // IN BUS [0:0]
);
`endif
endmodule
|
/*
* fifo module implements simple fifo which could read
* and write entry in same cycle.
* NOTE: when issued rd command fifo shouldn't be empty,
* when issued wr command fifo shouldn't be full,
* when issued rd and wr commands fifo shouldn't be empty or full
* only when fifo is empty data_out isn't valid
* Author: Kimi - Aug 2010
*/
`ifndef _my_fifo
`define _my_fifo
`timescale 1ns / 1ns
module my_fifo #(parameter max_len = 16, len_wd = 4, entry_wd = 32)
(
input wire clk, rst, // standard input signals
input wire rd, wr, // raed and write signals
input wire [entry_wd-1:0] data_in, // input entry
output wire full, empty,// fifo status indicators
output wire [entry_wd-1:0] data_out, // output entry
output reg [len_wd-1:0] len // indicated current fifo length
);
reg [entry_wd-1:0] reg_ram [max_len-1:0]; // registers array that implements ram.
reg [len_wd:0] rd_ptr, // point to ram address of entry that will be retrieved in next read command
wr_ptr; // point to next free ram address that will be occupied during next write cmd.
assign full = (len == max_len);
assign empty = (len == 0);
assign data_out = reg_ram[rd_ptr];
// pointers and length managements FSM
always @ (posedge clk) begin
if(rst) begin
len <= #5 0;
rd_ptr <= #5 0;
wr_ptr <= #5 0;
end
else begin
if(rd && wr && rd_ptr != wr_ptr) begin // to prevent read and write to same address (read and write)
if(rd_ptr == max_len-1) begin
rd_ptr <= #5 {len_wd{1'b0}}; // 0
end
else begin
rd_ptr <= #5 rd_ptr + {{(len_wd-1){1'b0}},1'b1}; // 1
end
if(wr_ptr == max_len-1) begin
wr_ptr <= #5 {len_wd{1'b0}}; // 0
end
else begin
wr_ptr <= #5 wr_ptr + {{(len_wd-1){1'b0}},1'b1}; // 1
end
end
else if (rd && !empty) begin // read only
len <= #5 len - {{(len_wd-1){1'b0}},1'b1}; // len--
if(rd_ptr == max_len-1) begin
rd_ptr <= #5 {len_wd{1'b0}}; // 0
end
else begin
rd_ptr <= #5 rd_ptr + {{(len_wd-1){1'b0}},1'b1}; // rd_ptr++
end
end
else if (wr && !full) begin // write only
len <= #5 len + {{(len_wd-1){1'b0}},1'b1}; // len++
if(wr_ptr == max_len-1) begin
wr_ptr <= #5 {len_wd{1'b0}}; // 0
end
else begin
wr_ptr <= #5 wr_ptr + {{(len_wd-1){1'b0}},1'b1}; // wr_ptr++
end
end
end
end
// write data into fifo
always @ (posedge clk) begin
if(!rst && ((wr && !full) || (rd && wr && rd_ptr != wr_ptr))) begin
reg_ram[wr_ptr] <= #5 data_in;
end
end
endmodule
`endif |