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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__AND2_FUNCTIONAL_PP_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and2 (
VPWR,
VGND,
X ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
// Local signals
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND2_FUNCTIONAL_PP_V |
/***************************************************************************************************
** fpga_nes/hw/src/cmn/vga_sync/vga_sync.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Outputs HSYNC and VSYNC signals to control 640x480@60Hz VGA output. x/y outputs indicates the
* current {x, y} pixel position being displayed.
*
* Note: VSYNC/HSYNC signals are latched for stability, introducing a 1 CLK delay. The RGB
* generation circuit must be aware of this, and should latch its output as well.
***************************************************************************************************/
`timescale 1ps / 1ps
module vga_sync
(
input wire clk, // 100Mhz clock signal
input wire rst,
output wire hsync, // HSYNC VGA control output
output wire vsync, // VSYNC VGA control output
output wire en, // Indicates when RGB generation circuit should enable (x,y valid)
output wire [9:0] x, // Current X position being displayed
output wire [9:0] y, // Current Y position being displayed (top = 0)
output wire [9:0] x_next, // Next X position to be displayed next clock
output wire [9:0] y_next // Next Y position to be displayed
);
//
// VGA signal timing parameters. Taken from http://tinyvga.com/vga-timing/640x480@60Hz. Note
// that this circuit uses a 25MHz clock instead of specified 25.175MHz clock. Most displays can
// cope with this out of spec behavior.
//
localparam H_DISP = 640; // Number of displayable columns
localparam H_FP = 16; // Horizontal front porch in pixel clocks
localparam H_RT = 96; // Horizontal retrace (hsync pulse) in pixel clocks
localparam H_BP = 48; // Horizontal back porch in pixel clocks
localparam V_DISP = 480; // Number of displayable rows
localparam V_FP = 10; // Vertical front porch in lines
localparam V_RT = 2; // Vertical retrace (vsync pulse) in lines
localparam V_BP = 29; // Vertical back porch in lines
//localparam H_DISP = 4; // Number of displayable columns
//localparam H_FP = 10; // Horizontal front porch in pixel clocks
//localparam H_RT = 2; // Horizontal retrace (hsync pulse) in pixel clocks
//localparam H_BP = 20; // Horizontal back porch in pixel clocks
//localparam V_DISP = 2; // Number of displayable rows
//localparam V_FP = 1; // Vertical front porch in lines
/*
localparam V_RT = 3; // Vertical retrace (vsync pulse) in lines
localparam V_BP = 2; // Vertical back porch in lines
*/
// FF for mod-4 counter. Used to generate a 25MHz pixel enable signal.
reg [1:0] q_mod4_cnt;
reg [1:0] d_mod4_cnt;
// Horizontal and vertical counters. Used relative to timings specified in pixels or lines, above.
// Equivalent to x,y position when in the displayable region.
reg [9:0] q_hcnt, q_vcnt;
reg [9:0] d_hcnt, d_vcnt;
// Output signal FFs.
reg q_hsync, q_vsync, q_en;
reg d_hsync, d_vsync, d_en;
// FF update logic.
always @(posedge clk) begin
q_mod4_cnt <= d_mod4_cnt;
q_hcnt <= d_hcnt;
q_vcnt <= d_vcnt;
q_hsync <= d_hsync;
q_vsync <= d_vsync;
q_en <= d_en;
end
wire pix_pulse; // 1 clk tick per-pixel
wire line_pulse; // 1 clk tick per-line (reset to h-pos 0)
wire screen_pulse; // 1 clk tick per-screen (reset to v-pos 0)
assign pix_pulse = (q_mod4_cnt == 0);
assign line_pulse = pix_pulse && (q_hcnt == (H_DISP + H_FP + H_RT + H_BP - 1));
assign screen_pulse = line_pulse && (q_vcnt == (V_DISP + V_FP + V_RT + V_BP - 1));
// Assign output wires to appropriate FFs.
assign hsync = q_hsync;
assign vsync = q_vsync;
assign x = q_hcnt;
assign y = q_vcnt;
assign x_next = d_hcnt;
assign y_next = (y == (V_DISP + V_FP + V_RT + V_BP - 10'h001)) ? 10'h000 : (q_vcnt + 10'h001);
assign en = q_en;
always @ (*) begin
if (rst) begin
d_mod4_cnt = 2'b00;
d_hcnt = 9'h000;
d_vcnt = 9'h000;
d_hsync = 1'b0;
d_en = 1'b0;
end
else begin
d_mod4_cnt = q_mod4_cnt + 2'h1;
d_hcnt = (line_pulse) ? 10'h000 : ((pix_pulse) ? q_hcnt + 10'h001 : q_hcnt);
d_vcnt = (screen_pulse) ? 10'h000 : ((line_pulse) ? q_vcnt + 10'h001 : q_vcnt);
d_hsync = (q_hcnt >= (H_DISP + H_FP)) && (q_hcnt < (H_DISP + H_FP + H_RT));
d_vsync = (q_vcnt >= (V_DISP + V_FP)) && (q_vcnt < (V_DISP + V_FP + V_RT));
d_en = (q_hcnt < H_DISP) && (q_vcnt < V_DISP);
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O31A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__O31A_BEHAVIORAL_PP_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__o31a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O31A_BEHAVIORAL_PP_V |
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Thu Jul 18 09:15:11 2019
//Host : graviton running 64-bit Devuan GNU/Linux ascii
//Command : generate_target cpu.bd
//Design : cpu
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module cpu
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
EPC_INTF_addr,
EPC_INTF_ads,
EPC_INTF_be,
EPC_INTF_burst,
EPC_INTF_clk,
EPC_INTF_cs_n,
EPC_INTF_data_i,
EPC_INTF_data_o,
EPC_INTF_data_t,
EPC_INTF_rd_n,
EPC_INTF_rdy,
EPC_INTF_rnw,
EPC_INTF_rst,
EPC_INTF_wr_n,
FCLK_CLK0,
FCLK_RESET0_N,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
GPIO_tri_i,
GPIO_tri_o,
GPIO_tri_t,
IIC_0_scl_i,
IIC_0_scl_o,
IIC_0_scl_t,
IIC_0_sda_i,
IIC_0_sda_o,
IIC_0_sda_t,
IIC_1_scl_i,
IIC_1_scl_o,
IIC_1_scl_t,
IIC_1_sda_i,
IIC_1_sda_o,
IIC_1_sda_t,
IIC_scl_i,
IIC_scl_o,
IIC_scl_t,
IIC_sda_i,
IIC_sda_o,
IIC_sda_t,
Int0,
Int1,
Int2,
Int3,
OCXO_CLK100,
OCXO_RESETN,
UART_0_rxd,
UART_0_txd,
Vp_Vn_v_n,
Vp_Vn_v_p);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
output [0:31]EPC_INTF_addr;
output EPC_INTF_ads;
output [0:3]EPC_INTF_be;
output EPC_INTF_burst;
input EPC_INTF_clk;
output [0:0]EPC_INTF_cs_n;
input [0:31]EPC_INTF_data_i;
output [0:31]EPC_INTF_data_o;
output [0:31]EPC_INTF_data_t;
output EPC_INTF_rd_n;
input [0:0]EPC_INTF_rdy;
output EPC_INTF_rnw;
input EPC_INTF_rst;
output EPC_INTF_wr_n;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [15:0]GPIO_tri_i;
output [15:0]GPIO_tri_o;
output [15:0]GPIO_tri_t;
input IIC_0_scl_i;
output IIC_0_scl_o;
output IIC_0_scl_t;
input IIC_0_sda_i;
output IIC_0_sda_o;
output IIC_0_sda_t;
input IIC_1_scl_i;
output IIC_1_scl_o;
output IIC_1_scl_t;
input IIC_1_sda_i;
output IIC_1_sda_o;
output IIC_1_sda_t;
input IIC_scl_i;
output IIC_scl_o;
output IIC_scl_t;
input IIC_sda_i;
output IIC_sda_o;
output IIC_sda_t;
input [0:0]Int0;
input [0:0]Int1;
input [0:0]Int2;
input [0:0]Int3;
input OCXO_CLK100;
output [0:0]OCXO_RESETN;
input UART_0_rxd;
output UART_0_txd;
input Vp_Vn_v_n;
input Vp_Vn_v_p;
wire GND_1;
wire [0:0]In4_1;
wire [0:0]In5_1;
wire [0:0]Int0_1;
wire [0:0]Int1_1;
wire M_AXI_GP0_ACLK_1;
wire M_AXI_GP1_ACLK_1;
wire VCC_1;
wire Vp_Vn_1_V_N;
wire Vp_Vn_1_V_P;
wire [0:31]axi_epc_0_EPC_INTF_ADDR;
wire axi_epc_0_EPC_INTF_ADS;
wire [0:3]axi_epc_0_EPC_INTF_BE;
wire axi_epc_0_EPC_INTF_BURST;
wire axi_epc_0_EPC_INTF_CLK;
wire [0:0]axi_epc_0_EPC_INTF_CS_N;
wire [0:31]axi_epc_0_EPC_INTF_DATA_I;
wire [0:31]axi_epc_0_EPC_INTF_DATA_O;
wire [0:31]axi_epc_0_EPC_INTF_DATA_T;
wire [0:0]axi_epc_0_EPC_INTF_RDY;
wire axi_epc_0_EPC_INTF_RD_N;
wire axi_epc_0_EPC_INTF_RNW;
wire axi_epc_0_EPC_INTF_RST;
wire axi_epc_0_EPC_INTF_WR_N;
wire [15:0]axi_gpio_0_GPIO_TRI_I;
wire [15:0]axi_gpio_0_GPIO_TRI_O;
wire [15:0]axi_gpio_0_GPIO_TRI_T;
wire axi_iic_0_IIC_SCL_I;
wire axi_iic_0_IIC_SCL_O;
wire axi_iic_0_IIC_SCL_T;
wire axi_iic_0_IIC_SDA_I;
wire axi_iic_0_IIC_SDA_O;
wire axi_iic_0_IIC_SDA_T;
wire axi_iic_0_iic2intc_irpt;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FCLK_RESET0_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
wire processing_system7_0_IIC_0_SCL_I;
wire processing_system7_0_IIC_0_SCL_O;
wire processing_system7_0_IIC_0_SCL_T;
wire processing_system7_0_IIC_0_SDA_I;
wire processing_system7_0_IIC_0_SDA_O;
wire processing_system7_0_IIC_0_SDA_T;
wire processing_system7_0_IIC_1_SCL_I;
wire processing_system7_0_IIC_1_SCL_O;
wire processing_system7_0_IIC_1_SCL_T;
wire processing_system7_0_IIC_1_SDA_I;
wire processing_system7_0_IIC_1_SDA_O;
wire processing_system7_0_IIC_1_SDA_T;
wire [31:0]processing_system7_0_M_AXI_GP0_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_ARID;
wire [3:0]processing_system7_0_M_AXI_GP0_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_ARQOS;
wire processing_system7_0_M_AXI_GP0_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_ARSIZE;
wire processing_system7_0_M_AXI_GP0_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP0_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP0_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP0_AWID;
wire [3:0]processing_system7_0_M_AXI_GP0_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP0_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP0_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP0_AWQOS;
wire processing_system7_0_M_AXI_GP0_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP0_AWSIZE;
wire processing_system7_0_M_AXI_GP0_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP0_BID;
wire processing_system7_0_M_AXI_GP0_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_BRESP;
wire processing_system7_0_M_AXI_GP0_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_RID;
wire processing_system7_0_M_AXI_GP0_RLAST;
wire processing_system7_0_M_AXI_GP0_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP0_RRESP;
wire processing_system7_0_M_AXI_GP0_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP0_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP0_WID;
wire processing_system7_0_M_AXI_GP0_WLAST;
wire processing_system7_0_M_AXI_GP0_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB;
wire processing_system7_0_M_AXI_GP0_WVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_ARADDR;
wire [1:0]processing_system7_0_M_AXI_GP1_ARBURST;
wire [3:0]processing_system7_0_M_AXI_GP1_ARCACHE;
wire [11:0]processing_system7_0_M_AXI_GP1_ARID;
wire [3:0]processing_system7_0_M_AXI_GP1_ARLEN;
wire [1:0]processing_system7_0_M_AXI_GP1_ARLOCK;
wire [2:0]processing_system7_0_M_AXI_GP1_ARPROT;
wire [3:0]processing_system7_0_M_AXI_GP1_ARQOS;
wire processing_system7_0_M_AXI_GP1_ARREADY;
wire [2:0]processing_system7_0_M_AXI_GP1_ARSIZE;
wire processing_system7_0_M_AXI_GP1_ARVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_AWADDR;
wire [1:0]processing_system7_0_M_AXI_GP1_AWBURST;
wire [3:0]processing_system7_0_M_AXI_GP1_AWCACHE;
wire [11:0]processing_system7_0_M_AXI_GP1_AWID;
wire [3:0]processing_system7_0_M_AXI_GP1_AWLEN;
wire [1:0]processing_system7_0_M_AXI_GP1_AWLOCK;
wire [2:0]processing_system7_0_M_AXI_GP1_AWPROT;
wire [3:0]processing_system7_0_M_AXI_GP1_AWQOS;
wire processing_system7_0_M_AXI_GP1_AWREADY;
wire [2:0]processing_system7_0_M_AXI_GP1_AWSIZE;
wire processing_system7_0_M_AXI_GP1_AWVALID;
wire [11:0]processing_system7_0_M_AXI_GP1_BID;
wire processing_system7_0_M_AXI_GP1_BREADY;
wire [1:0]processing_system7_0_M_AXI_GP1_BRESP;
wire processing_system7_0_M_AXI_GP1_BVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_RDATA;
wire [11:0]processing_system7_0_M_AXI_GP1_RID;
wire processing_system7_0_M_AXI_GP1_RLAST;
wire processing_system7_0_M_AXI_GP1_RREADY;
wire [1:0]processing_system7_0_M_AXI_GP1_RRESP;
wire processing_system7_0_M_AXI_GP1_RVALID;
wire [31:0]processing_system7_0_M_AXI_GP1_WDATA;
wire [11:0]processing_system7_0_M_AXI_GP1_WID;
wire processing_system7_0_M_AXI_GP1_WLAST;
wire processing_system7_0_M_AXI_GP1_WREADY;
wire [3:0]processing_system7_0_M_AXI_GP1_WSTRB;
wire processing_system7_0_M_AXI_GP1_WVALID;
wire processing_system7_0_UART_0_RxD;
wire processing_system7_0_UART_0_TxD;
wire [31:0]processing_system7_0_axi_periph_1_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_1_M00_AXI_ARREADY;
wire processing_system7_0_axi_periph_1_M00_AXI_ARVALID;
wire [31:0]processing_system7_0_axi_periph_1_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_1_M00_AXI_AWREADY;
wire processing_system7_0_axi_periph_1_M00_AXI_AWVALID;
wire processing_system7_0_axi_periph_1_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_1_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_1_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_1_M00_AXI_RDATA;
wire processing_system7_0_axi_periph_1_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_1_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_1_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_1_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_1_M00_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_1_M00_AXI_WSTRB;
wire processing_system7_0_axi_periph_1_M00_AXI_WVALID;
wire [8:0]processing_system7_0_axi_periph_M00_AXI_ARADDR;
wire processing_system7_0_axi_periph_M00_AXI_ARREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_ARVALID;
wire [8:0]processing_system7_0_axi_periph_M00_AXI_AWADDR;
wire processing_system7_0_axi_periph_M00_AXI_AWREADY;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_AWVALID;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_BRESP;
wire processing_system7_0_axi_periph_M00_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_RDATA;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M00_AXI_RRESP;
wire processing_system7_0_axi_periph_M00_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M00_AXI_WDATA;
wire processing_system7_0_axi_periph_M00_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M00_AXI_WSTRB;
wire [0:0]processing_system7_0_axi_periph_M00_AXI_WVALID;
wire [8:0]processing_system7_0_axi_periph_M01_AXI_ARADDR;
wire processing_system7_0_axi_periph_M01_AXI_ARREADY;
wire processing_system7_0_axi_periph_M01_AXI_ARVALID;
wire [8:0]processing_system7_0_axi_periph_M01_AXI_AWADDR;
wire processing_system7_0_axi_periph_M01_AXI_AWREADY;
wire processing_system7_0_axi_periph_M01_AXI_AWVALID;
wire processing_system7_0_axi_periph_M01_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_BRESP;
wire processing_system7_0_axi_periph_M01_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_RDATA;
wire processing_system7_0_axi_periph_M01_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M01_AXI_RRESP;
wire processing_system7_0_axi_periph_M01_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M01_AXI_WDATA;
wire processing_system7_0_axi_periph_M01_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M01_AXI_WSTRB;
wire processing_system7_0_axi_periph_M01_AXI_WVALID;
wire [10:0]processing_system7_0_axi_periph_M02_AXI_ARADDR;
wire processing_system7_0_axi_periph_M02_AXI_ARREADY;
wire processing_system7_0_axi_periph_M02_AXI_ARVALID;
wire [10:0]processing_system7_0_axi_periph_M02_AXI_AWADDR;
wire processing_system7_0_axi_periph_M02_AXI_AWREADY;
wire processing_system7_0_axi_periph_M02_AXI_AWVALID;
wire processing_system7_0_axi_periph_M02_AXI_BREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_BRESP;
wire processing_system7_0_axi_periph_M02_AXI_BVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_RDATA;
wire processing_system7_0_axi_periph_M02_AXI_RREADY;
wire [1:0]processing_system7_0_axi_periph_M02_AXI_RRESP;
wire processing_system7_0_axi_periph_M02_AXI_RVALID;
wire [31:0]processing_system7_0_axi_periph_M02_AXI_WDATA;
wire processing_system7_0_axi_periph_M02_AXI_WREADY;
wire [3:0]processing_system7_0_axi_periph_M02_AXI_WSTRB;
wire processing_system7_0_axi_periph_M02_AXI_WVALID;
wire [0:0]rst_M_AXI_GP1_ACLK_100M_interconnect_aresetn;
wire [0:0]rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn;
wire [0:0]rst_processing_system7_0_100M_interconnect_aresetn;
wire [0:0]rst_processing_system7_0_100M_peripheral_aresetn;
wire xadc_wiz_0_ip2intc_irpt;
wire [5:0]xlconcat_0_dout;
assign EPC_INTF_addr[0:31] = axi_epc_0_EPC_INTF_ADDR;
assign EPC_INTF_ads = axi_epc_0_EPC_INTF_ADS;
assign EPC_INTF_be[0:3] = axi_epc_0_EPC_INTF_BE;
assign EPC_INTF_burst = axi_epc_0_EPC_INTF_BURST;
assign EPC_INTF_cs_n[0] = axi_epc_0_EPC_INTF_CS_N;
assign EPC_INTF_data_o[0:31] = axi_epc_0_EPC_INTF_DATA_O;
assign EPC_INTF_data_t[0:31] = axi_epc_0_EPC_INTF_DATA_T;
assign EPC_INTF_rd_n = axi_epc_0_EPC_INTF_RD_N;
assign EPC_INTF_rnw = axi_epc_0_EPC_INTF_RNW;
assign EPC_INTF_wr_n = axi_epc_0_EPC_INTF_WR_N;
assign FCLK_CLK0 = M_AXI_GP0_ACLK_1;
assign FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N;
assign GPIO_tri_o[15:0] = axi_gpio_0_GPIO_TRI_O;
assign GPIO_tri_t[15:0] = axi_gpio_0_GPIO_TRI_T;
assign IIC_0_scl_o = processing_system7_0_IIC_0_SCL_O;
assign IIC_0_scl_t = processing_system7_0_IIC_0_SCL_T;
assign IIC_0_sda_o = processing_system7_0_IIC_0_SDA_O;
assign IIC_0_sda_t = processing_system7_0_IIC_0_SDA_T;
assign IIC_1_scl_o = processing_system7_0_IIC_1_SCL_O;
assign IIC_1_scl_t = processing_system7_0_IIC_1_SCL_T;
assign IIC_1_sda_o = processing_system7_0_IIC_1_SDA_O;
assign IIC_1_sda_t = processing_system7_0_IIC_1_SDA_T;
assign IIC_scl_o = axi_iic_0_IIC_SCL_O;
assign IIC_scl_t = axi_iic_0_IIC_SCL_T;
assign IIC_sda_o = axi_iic_0_IIC_SDA_O;
assign IIC_sda_t = axi_iic_0_IIC_SDA_T;
assign In4_1 = Int2[0];
assign In5_1 = Int3[0];
assign Int0_1 = Int0[0];
assign Int1_1 = Int1[0];
assign M_AXI_GP1_ACLK_1 = OCXO_CLK100;
assign OCXO_RESETN[0] = rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn;
assign UART_0_txd = processing_system7_0_UART_0_TxD;
assign Vp_Vn_1_V_N = Vp_Vn_v_n;
assign Vp_Vn_1_V_P = Vp_Vn_v_p;
assign axi_epc_0_EPC_INTF_CLK = EPC_INTF_clk;
assign axi_epc_0_EPC_INTF_DATA_I = EPC_INTF_data_i[0:31];
assign axi_epc_0_EPC_INTF_RDY = EPC_INTF_rdy[0];
assign axi_epc_0_EPC_INTF_RST = EPC_INTF_rst;
assign axi_gpio_0_GPIO_TRI_I = GPIO_tri_i[15:0];
assign axi_iic_0_IIC_SCL_I = IIC_scl_i;
assign axi_iic_0_IIC_SDA_I = IIC_sda_i;
assign processing_system7_0_IIC_0_SCL_I = IIC_0_scl_i;
assign processing_system7_0_IIC_0_SDA_I = IIC_0_sda_i;
assign processing_system7_0_IIC_1_SCL_I = IIC_1_scl_i;
assign processing_system7_0_IIC_1_SDA_I = IIC_1_sda_i;
assign processing_system7_0_UART_0_RxD = UART_0_rxd;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
cpu_axi_epc_0_0 axi_epc_0
(.prh_addr(axi_epc_0_EPC_INTF_ADDR),
.prh_ads(axi_epc_0_EPC_INTF_ADS),
.prh_be(axi_epc_0_EPC_INTF_BE),
.prh_burst(axi_epc_0_EPC_INTF_BURST),
.prh_clk(axi_epc_0_EPC_INTF_CLK),
.prh_cs_n(axi_epc_0_EPC_INTF_CS_N),
.prh_data_i(axi_epc_0_EPC_INTF_DATA_I),
.prh_data_o(axi_epc_0_EPC_INTF_DATA_O),
.prh_data_t(axi_epc_0_EPC_INTF_DATA_T),
.prh_rd_n(axi_epc_0_EPC_INTF_RD_N),
.prh_rdy(axi_epc_0_EPC_INTF_RDY),
.prh_rnw(axi_epc_0_EPC_INTF_RNW),
.prh_rst(axi_epc_0_EPC_INTF_RST),
.prh_wr_n(axi_epc_0_EPC_INTF_WR_N),
.s_axi_aclk(M_AXI_GP1_ACLK_1),
.s_axi_araddr(processing_system7_0_axi_periph_1_M00_AXI_ARADDR),
.s_axi_aresetn(rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_1_M00_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_1_M00_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_1_M00_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_1_M00_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_1_M00_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_1_M00_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_1_M00_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_1_M00_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_1_M00_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_1_M00_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_1_M00_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_1_M00_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_1_M00_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_1_M00_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_1_M00_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_1_M00_AXI_WVALID));
cpu_axi_gpio_0_0 axi_gpio_0
(.gpio_io_i(axi_gpio_0_GPIO_TRI_I),
.gpio_io_o(axi_gpio_0_GPIO_TRI_O),
.gpio_io_t(axi_gpio_0_GPIO_TRI_T),
.s_axi_aclk(M_AXI_GP0_ACLK_1),
.s_axi_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M00_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID));
cpu_axi_iic_0_0 axi_iic_0
(.iic2intc_irpt(axi_iic_0_iic2intc_irpt),
.s_axi_aclk(M_AXI_GP0_ACLK_1),
.s_axi_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M01_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.scl_i(axi_iic_0_IIC_SCL_I),
.scl_o(axi_iic_0_IIC_SCL_O),
.scl_t(axi_iic_0_IIC_SCL_T),
.sda_i(axi_iic_0_IIC_SDA_I),
.sda_o(axi_iic_0_IIC_SDA_O),
.sda_t(axi_iic_0_IIC_SDA_T));
cpu_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(M_AXI_GP0_ACLK_1),
.FCLK_RESET0_N(processing_system7_0_FCLK_RESET0_N),
.I2C0_SCL_I(processing_system7_0_IIC_0_SCL_I),
.I2C0_SCL_O(processing_system7_0_IIC_0_SCL_O),
.I2C0_SCL_T(processing_system7_0_IIC_0_SCL_T),
.I2C0_SDA_I(processing_system7_0_IIC_0_SDA_I),
.I2C0_SDA_O(processing_system7_0_IIC_0_SDA_O),
.I2C0_SDA_T(processing_system7_0_IIC_0_SDA_T),
.I2C1_SCL_I(processing_system7_0_IIC_1_SCL_I),
.I2C1_SCL_O(processing_system7_0_IIC_1_SCL_O),
.I2C1_SCL_T(processing_system7_0_IIC_1_SCL_T),
.I2C1_SDA_I(processing_system7_0_IIC_1_SDA_I),
.I2C1_SDA_O(processing_system7_0_IIC_1_SDA_O),
.I2C1_SDA_T(processing_system7_0_IIC_1_SDA_T),
.IRQ_F2P(xlconcat_0_dout),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK_1),
.M_AXI_GP0_ARADDR(processing_system7_0_M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(processing_system7_0_M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(processing_system7_0_M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARID(processing_system7_0_M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(processing_system7_0_M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(processing_system7_0_M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(processing_system7_0_M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(processing_system7_0_M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(processing_system7_0_M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(processing_system7_0_M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(processing_system7_0_M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(processing_system7_0_M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(processing_system7_0_M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(processing_system7_0_M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(processing_system7_0_M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(processing_system7_0_M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(processing_system7_0_M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(processing_system7_0_M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(processing_system7_0_M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(processing_system7_0_M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(processing_system7_0_M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(processing_system7_0_M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(processing_system7_0_M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(processing_system7_0_M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(processing_system7_0_M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(processing_system7_0_M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(processing_system7_0_M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(processing_system7_0_M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(processing_system7_0_M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(processing_system7_0_M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(processing_system7_0_M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(processing_system7_0_M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(processing_system7_0_M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(processing_system7_0_M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(processing_system7_0_M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(processing_system7_0_M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(processing_system7_0_M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(processing_system7_0_M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(M_AXI_GP1_ACLK_1),
.M_AXI_GP1_ARADDR(processing_system7_0_M_AXI_GP1_ARADDR),
.M_AXI_GP1_ARBURST(processing_system7_0_M_AXI_GP1_ARBURST),
.M_AXI_GP1_ARCACHE(processing_system7_0_M_AXI_GP1_ARCACHE),
.M_AXI_GP1_ARID(processing_system7_0_M_AXI_GP1_ARID),
.M_AXI_GP1_ARLEN(processing_system7_0_M_AXI_GP1_ARLEN),
.M_AXI_GP1_ARLOCK(processing_system7_0_M_AXI_GP1_ARLOCK),
.M_AXI_GP1_ARPROT(processing_system7_0_M_AXI_GP1_ARPROT),
.M_AXI_GP1_ARQOS(processing_system7_0_M_AXI_GP1_ARQOS),
.M_AXI_GP1_ARREADY(processing_system7_0_M_AXI_GP1_ARREADY),
.M_AXI_GP1_ARSIZE(processing_system7_0_M_AXI_GP1_ARSIZE),
.M_AXI_GP1_ARVALID(processing_system7_0_M_AXI_GP1_ARVALID),
.M_AXI_GP1_AWADDR(processing_system7_0_M_AXI_GP1_AWADDR),
.M_AXI_GP1_AWBURST(processing_system7_0_M_AXI_GP1_AWBURST),
.M_AXI_GP1_AWCACHE(processing_system7_0_M_AXI_GP1_AWCACHE),
.M_AXI_GP1_AWID(processing_system7_0_M_AXI_GP1_AWID),
.M_AXI_GP1_AWLEN(processing_system7_0_M_AXI_GP1_AWLEN),
.M_AXI_GP1_AWLOCK(processing_system7_0_M_AXI_GP1_AWLOCK),
.M_AXI_GP1_AWPROT(processing_system7_0_M_AXI_GP1_AWPROT),
.M_AXI_GP1_AWQOS(processing_system7_0_M_AXI_GP1_AWQOS),
.M_AXI_GP1_AWREADY(processing_system7_0_M_AXI_GP1_AWREADY),
.M_AXI_GP1_AWSIZE(processing_system7_0_M_AXI_GP1_AWSIZE),
.M_AXI_GP1_AWVALID(processing_system7_0_M_AXI_GP1_AWVALID),
.M_AXI_GP1_BID(processing_system7_0_M_AXI_GP1_BID),
.M_AXI_GP1_BREADY(processing_system7_0_M_AXI_GP1_BREADY),
.M_AXI_GP1_BRESP(processing_system7_0_M_AXI_GP1_BRESP),
.M_AXI_GP1_BVALID(processing_system7_0_M_AXI_GP1_BVALID),
.M_AXI_GP1_RDATA(processing_system7_0_M_AXI_GP1_RDATA),
.M_AXI_GP1_RID(processing_system7_0_M_AXI_GP1_RID),
.M_AXI_GP1_RLAST(processing_system7_0_M_AXI_GP1_RLAST),
.M_AXI_GP1_RREADY(processing_system7_0_M_AXI_GP1_RREADY),
.M_AXI_GP1_RRESP(processing_system7_0_M_AXI_GP1_RRESP),
.M_AXI_GP1_RVALID(processing_system7_0_M_AXI_GP1_RVALID),
.M_AXI_GP1_WDATA(processing_system7_0_M_AXI_GP1_WDATA),
.M_AXI_GP1_WID(processing_system7_0_M_AXI_GP1_WID),
.M_AXI_GP1_WLAST(processing_system7_0_M_AXI_GP1_WLAST),
.M_AXI_GP1_WREADY(processing_system7_0_M_AXI_GP1_WREADY),
.M_AXI_GP1_WSTRB(processing_system7_0_M_AXI_GP1_WSTRB),
.M_AXI_GP1_WVALID(processing_system7_0_M_AXI_GP1_WVALID),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.UART0_RX(processing_system7_0_UART_0_RxD),
.UART0_TX(processing_system7_0_UART_0_TxD),
.USB0_VBUS_PWRFAULT(GND_1));
cpu_processing_system7_0_axi_periph_0 processing_system7_0_axi_periph
(.ACLK(M_AXI_GP0_ACLK_1),
.ARESETN(rst_processing_system7_0_100M_interconnect_aresetn),
.M00_ACLK(M_AXI_GP0_ACLK_1),
.M00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M00_AXI_araddr(processing_system7_0_axi_periph_M00_AXI_ARADDR),
.M00_AXI_arready(processing_system7_0_axi_periph_M00_AXI_ARREADY),
.M00_AXI_arvalid(processing_system7_0_axi_periph_M00_AXI_ARVALID),
.M00_AXI_awaddr(processing_system7_0_axi_periph_M00_AXI_AWADDR),
.M00_AXI_awready(processing_system7_0_axi_periph_M00_AXI_AWREADY),
.M00_AXI_awvalid(processing_system7_0_axi_periph_M00_AXI_AWVALID),
.M00_AXI_bready(processing_system7_0_axi_periph_M00_AXI_BREADY),
.M00_AXI_bresp(processing_system7_0_axi_periph_M00_AXI_BRESP),
.M00_AXI_bvalid(processing_system7_0_axi_periph_M00_AXI_BVALID),
.M00_AXI_rdata(processing_system7_0_axi_periph_M00_AXI_RDATA),
.M00_AXI_rready(processing_system7_0_axi_periph_M00_AXI_RREADY),
.M00_AXI_rresp(processing_system7_0_axi_periph_M00_AXI_RRESP),
.M00_AXI_rvalid(processing_system7_0_axi_periph_M00_AXI_RVALID),
.M00_AXI_wdata(processing_system7_0_axi_periph_M00_AXI_WDATA),
.M00_AXI_wready(processing_system7_0_axi_periph_M00_AXI_WREADY),
.M00_AXI_wstrb(processing_system7_0_axi_periph_M00_AXI_WSTRB),
.M00_AXI_wvalid(processing_system7_0_axi_periph_M00_AXI_WVALID),
.M01_ACLK(M_AXI_GP0_ACLK_1),
.M01_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M01_AXI_araddr(processing_system7_0_axi_periph_M01_AXI_ARADDR),
.M01_AXI_arready(processing_system7_0_axi_periph_M01_AXI_ARREADY),
.M01_AXI_arvalid(processing_system7_0_axi_periph_M01_AXI_ARVALID),
.M01_AXI_awaddr(processing_system7_0_axi_periph_M01_AXI_AWADDR),
.M01_AXI_awready(processing_system7_0_axi_periph_M01_AXI_AWREADY),
.M01_AXI_awvalid(processing_system7_0_axi_periph_M01_AXI_AWVALID),
.M01_AXI_bready(processing_system7_0_axi_periph_M01_AXI_BREADY),
.M01_AXI_bresp(processing_system7_0_axi_periph_M01_AXI_BRESP),
.M01_AXI_bvalid(processing_system7_0_axi_periph_M01_AXI_BVALID),
.M01_AXI_rdata(processing_system7_0_axi_periph_M01_AXI_RDATA),
.M01_AXI_rready(processing_system7_0_axi_periph_M01_AXI_RREADY),
.M01_AXI_rresp(processing_system7_0_axi_periph_M01_AXI_RRESP),
.M01_AXI_rvalid(processing_system7_0_axi_periph_M01_AXI_RVALID),
.M01_AXI_wdata(processing_system7_0_axi_periph_M01_AXI_WDATA),
.M01_AXI_wready(processing_system7_0_axi_periph_M01_AXI_WREADY),
.M01_AXI_wstrb(processing_system7_0_axi_periph_M01_AXI_WSTRB),
.M01_AXI_wvalid(processing_system7_0_axi_periph_M01_AXI_WVALID),
.M02_ACLK(M_AXI_GP0_ACLK_1),
.M02_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.M02_AXI_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.M02_AXI_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.M02_AXI_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.M02_AXI_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.M02_AXI_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.M02_AXI_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.M02_AXI_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.M02_AXI_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.M02_AXI_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.M02_AXI_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.M02_AXI_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.M02_AXI_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.M02_AXI_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.M02_AXI_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.M02_AXI_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.M02_AXI_wstrb(processing_system7_0_axi_periph_M02_AXI_WSTRB),
.M02_AXI_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.S00_ACLK(M_AXI_GP0_ACLK_1),
.S00_ARESETN(rst_processing_system7_0_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP0_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP0_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP0_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP0_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP0_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP0_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP0_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP0_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP0_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP0_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP0_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP0_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP0_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP0_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP0_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP0_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP0_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP0_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP0_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP0_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP0_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP0_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP0_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP0_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP0_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP0_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP0_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP0_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP0_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP0_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP0_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP0_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP0_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP0_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP0_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP0_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP0_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP0_WVALID));
cpu_processing_system7_0_axi_periph_1_0 processing_system7_0_axi_periph_1
(.ACLK(M_AXI_GP1_ACLK_1),
.ARESETN(rst_M_AXI_GP1_ACLK_100M_interconnect_aresetn),
.M00_ACLK(M_AXI_GP1_ACLK_1),
.M00_ARESETN(rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn),
.M00_AXI_araddr(processing_system7_0_axi_periph_1_M00_AXI_ARADDR),
.M00_AXI_arready(processing_system7_0_axi_periph_1_M00_AXI_ARREADY),
.M00_AXI_arvalid(processing_system7_0_axi_periph_1_M00_AXI_ARVALID),
.M00_AXI_awaddr(processing_system7_0_axi_periph_1_M00_AXI_AWADDR),
.M00_AXI_awready(processing_system7_0_axi_periph_1_M00_AXI_AWREADY),
.M00_AXI_awvalid(processing_system7_0_axi_periph_1_M00_AXI_AWVALID),
.M00_AXI_bready(processing_system7_0_axi_periph_1_M00_AXI_BREADY),
.M00_AXI_bresp(processing_system7_0_axi_periph_1_M00_AXI_BRESP),
.M00_AXI_bvalid(processing_system7_0_axi_periph_1_M00_AXI_BVALID),
.M00_AXI_rdata(processing_system7_0_axi_periph_1_M00_AXI_RDATA),
.M00_AXI_rready(processing_system7_0_axi_periph_1_M00_AXI_RREADY),
.M00_AXI_rresp(processing_system7_0_axi_periph_1_M00_AXI_RRESP),
.M00_AXI_rvalid(processing_system7_0_axi_periph_1_M00_AXI_RVALID),
.M00_AXI_wdata(processing_system7_0_axi_periph_1_M00_AXI_WDATA),
.M00_AXI_wready(processing_system7_0_axi_periph_1_M00_AXI_WREADY),
.M00_AXI_wstrb(processing_system7_0_axi_periph_1_M00_AXI_WSTRB),
.M00_AXI_wvalid(processing_system7_0_axi_periph_1_M00_AXI_WVALID),
.S00_ACLK(M_AXI_GP1_ACLK_1),
.S00_ARESETN(rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn),
.S00_AXI_araddr(processing_system7_0_M_AXI_GP1_ARADDR),
.S00_AXI_arburst(processing_system7_0_M_AXI_GP1_ARBURST),
.S00_AXI_arcache(processing_system7_0_M_AXI_GP1_ARCACHE),
.S00_AXI_arid(processing_system7_0_M_AXI_GP1_ARID),
.S00_AXI_arlen(processing_system7_0_M_AXI_GP1_ARLEN),
.S00_AXI_arlock(processing_system7_0_M_AXI_GP1_ARLOCK),
.S00_AXI_arprot(processing_system7_0_M_AXI_GP1_ARPROT),
.S00_AXI_arqos(processing_system7_0_M_AXI_GP1_ARQOS),
.S00_AXI_arready(processing_system7_0_M_AXI_GP1_ARREADY),
.S00_AXI_arsize(processing_system7_0_M_AXI_GP1_ARSIZE),
.S00_AXI_arvalid(processing_system7_0_M_AXI_GP1_ARVALID),
.S00_AXI_awaddr(processing_system7_0_M_AXI_GP1_AWADDR),
.S00_AXI_awburst(processing_system7_0_M_AXI_GP1_AWBURST),
.S00_AXI_awcache(processing_system7_0_M_AXI_GP1_AWCACHE),
.S00_AXI_awid(processing_system7_0_M_AXI_GP1_AWID),
.S00_AXI_awlen(processing_system7_0_M_AXI_GP1_AWLEN),
.S00_AXI_awlock(processing_system7_0_M_AXI_GP1_AWLOCK),
.S00_AXI_awprot(processing_system7_0_M_AXI_GP1_AWPROT),
.S00_AXI_awqos(processing_system7_0_M_AXI_GP1_AWQOS),
.S00_AXI_awready(processing_system7_0_M_AXI_GP1_AWREADY),
.S00_AXI_awsize(processing_system7_0_M_AXI_GP1_AWSIZE),
.S00_AXI_awvalid(processing_system7_0_M_AXI_GP1_AWVALID),
.S00_AXI_bid(processing_system7_0_M_AXI_GP1_BID),
.S00_AXI_bready(processing_system7_0_M_AXI_GP1_BREADY),
.S00_AXI_bresp(processing_system7_0_M_AXI_GP1_BRESP),
.S00_AXI_bvalid(processing_system7_0_M_AXI_GP1_BVALID),
.S00_AXI_rdata(processing_system7_0_M_AXI_GP1_RDATA),
.S00_AXI_rid(processing_system7_0_M_AXI_GP1_RID),
.S00_AXI_rlast(processing_system7_0_M_AXI_GP1_RLAST),
.S00_AXI_rready(processing_system7_0_M_AXI_GP1_RREADY),
.S00_AXI_rresp(processing_system7_0_M_AXI_GP1_RRESP),
.S00_AXI_rvalid(processing_system7_0_M_AXI_GP1_RVALID),
.S00_AXI_wdata(processing_system7_0_M_AXI_GP1_WDATA),
.S00_AXI_wid(processing_system7_0_M_AXI_GP1_WID),
.S00_AXI_wlast(processing_system7_0_M_AXI_GP1_WLAST),
.S00_AXI_wready(processing_system7_0_M_AXI_GP1_WREADY),
.S00_AXI_wstrb(processing_system7_0_M_AXI_GP1_WSTRB),
.S00_AXI_wvalid(processing_system7_0_M_AXI_GP1_WVALID));
cpu_rst_M_AXI_GP1_ACLK_100M_0 rst_M_AXI_GP1_ACLK_100M
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_M_AXI_GP1_ACLK_100M_interconnect_aresetn),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn),
.slowest_sync_clk(M_AXI_GP1_ACLK_1));
cpu_rst_processing_system7_0_100M_0 rst_processing_system7_0_100M
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_0_FCLK_RESET0_N),
.interconnect_aresetn(rst_processing_system7_0_100M_interconnect_aresetn),
.mb_debug_sys_rst(GND_1),
.peripheral_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.slowest_sync_clk(M_AXI_GP0_ACLK_1));
cpu_xadc_wiz_0_0 xadc_wiz_0
(.ip2intc_irpt(xadc_wiz_0_ip2intc_irpt),
.s_axi_aclk(M_AXI_GP0_ACLK_1),
.s_axi_araddr(processing_system7_0_axi_periph_M02_AXI_ARADDR),
.s_axi_aresetn(rst_processing_system7_0_100M_peripheral_aresetn),
.s_axi_arready(processing_system7_0_axi_periph_M02_AXI_ARREADY),
.s_axi_arvalid(processing_system7_0_axi_periph_M02_AXI_ARVALID),
.s_axi_awaddr(processing_system7_0_axi_periph_M02_AXI_AWADDR),
.s_axi_awready(processing_system7_0_axi_periph_M02_AXI_AWREADY),
.s_axi_awvalid(processing_system7_0_axi_periph_M02_AXI_AWVALID),
.s_axi_bready(processing_system7_0_axi_periph_M02_AXI_BREADY),
.s_axi_bresp(processing_system7_0_axi_periph_M02_AXI_BRESP),
.s_axi_bvalid(processing_system7_0_axi_periph_M02_AXI_BVALID),
.s_axi_rdata(processing_system7_0_axi_periph_M02_AXI_RDATA),
.s_axi_rready(processing_system7_0_axi_periph_M02_AXI_RREADY),
.s_axi_rresp(processing_system7_0_axi_periph_M02_AXI_RRESP),
.s_axi_rvalid(processing_system7_0_axi_periph_M02_AXI_RVALID),
.s_axi_wdata(processing_system7_0_axi_periph_M02_AXI_WDATA),
.s_axi_wready(processing_system7_0_axi_periph_M02_AXI_WREADY),
.s_axi_wstrb(processing_system7_0_axi_periph_M02_AXI_WSTRB),
.s_axi_wvalid(processing_system7_0_axi_periph_M02_AXI_WVALID),
.vn_in(Vp_Vn_1_V_N),
.vp_in(Vp_Vn_1_V_P));
cpu_xlconcat_0_0 xlconcat_0
(.In0(axi_iic_0_iic2intc_irpt),
.In1(xadc_wiz_0_ip2intc_irpt),
.In2(Int0_1),
.In3(Int1_1),
.In4(In4_1),
.In5(In5_1),
.dout(xlconcat_0_dout));
endmodule
module cpu_processing_system7_0_axi_periph_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
M01_ACLK,
M01_ARESETN,
M01_AXI_araddr,
M01_AXI_arready,
M01_AXI_arvalid,
M01_AXI_awaddr,
M01_AXI_awready,
M01_AXI_awvalid,
M01_AXI_bready,
M01_AXI_bresp,
M01_AXI_bvalid,
M01_AXI_rdata,
M01_AXI_rready,
M01_AXI_rresp,
M01_AXI_rvalid,
M01_AXI_wdata,
M01_AXI_wready,
M01_AXI_wstrb,
M01_AXI_wvalid,
M02_ACLK,
M02_ARESETN,
M02_AXI_araddr,
M02_AXI_arready,
M02_AXI_arvalid,
M02_AXI_awaddr,
M02_AXI_awready,
M02_AXI_awvalid,
M02_AXI_bready,
M02_AXI_bresp,
M02_AXI_bvalid,
M02_AXI_rdata,
M02_AXI_rready,
M02_AXI_rresp,
M02_AXI_rvalid,
M02_AXI_wdata,
M02_AXI_wready,
M02_AXI_wstrb,
M02_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [8:0]M00_AXI_araddr;
input [0:0]M00_AXI_arready;
output [0:0]M00_AXI_arvalid;
output [8:0]M00_AXI_awaddr;
input [0:0]M00_AXI_awready;
output [0:0]M00_AXI_awvalid;
output [0:0]M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input [0:0]M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output [0:0]M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input [0:0]M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input [0:0]M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output [0:0]M00_AXI_wvalid;
input M01_ACLK;
input [0:0]M01_ARESETN;
output [8:0]M01_AXI_araddr;
input M01_AXI_arready;
output M01_AXI_arvalid;
output [8:0]M01_AXI_awaddr;
input M01_AXI_awready;
output M01_AXI_awvalid;
output M01_AXI_bready;
input [1:0]M01_AXI_bresp;
input M01_AXI_bvalid;
input [31:0]M01_AXI_rdata;
output M01_AXI_rready;
input [1:0]M01_AXI_rresp;
input M01_AXI_rvalid;
output [31:0]M01_AXI_wdata;
input M01_AXI_wready;
output [3:0]M01_AXI_wstrb;
output M01_AXI_wvalid;
input M02_ACLK;
input [0:0]M02_ARESETN;
output [10:0]M02_AXI_araddr;
input M02_AXI_arready;
output M02_AXI_arvalid;
output [10:0]M02_AXI_awaddr;
input M02_AXI_awready;
output M02_AXI_awvalid;
output M02_AXI_bready;
input [1:0]M02_AXI_bresp;
input M02_AXI_bvalid;
input [31:0]M02_AXI_rdata;
output M02_AXI_rready;
input [1:0]M02_AXI_rresp;
input M02_AXI_rvalid;
output [31:0]M02_AXI_wdata;
input M02_AXI_wready;
output [3:0]M02_AXI_wstrb;
output M02_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire M00_ACLK_1;
wire [0:0]M00_ARESETN_1;
wire M01_ACLK_1;
wire [0:0]M01_ARESETN_1;
wire M02_ACLK_1;
wire [0:0]M02_ARESETN_1;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire [8:0]m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [8:0]m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_BRESP;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_RDATA;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m00_couplers_to_processing_system7_0_axi_periph_RRESP;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m00_couplers_to_processing_system7_0_axi_periph_WDATA;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m00_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire [0:0]m00_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [8:0]m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m01_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [8:0]m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m01_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m01_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m01_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m01_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m01_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m01_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m01_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m01_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m01_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire m01_couplers_to_processing_system7_0_axi_periph_WVALID;
wire [10:0]m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
wire m02_couplers_to_processing_system7_0_axi_periph_ARREADY;
wire m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
wire [10:0]m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
wire m02_couplers_to_processing_system7_0_axi_periph_AWREADY;
wire m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
wire m02_couplers_to_processing_system7_0_axi_periph_BREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_BRESP;
wire m02_couplers_to_processing_system7_0_axi_periph_BVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_RDATA;
wire m02_couplers_to_processing_system7_0_axi_periph_RREADY;
wire [1:0]m02_couplers_to_processing_system7_0_axi_periph_RRESP;
wire m02_couplers_to_processing_system7_0_axi_periph_RVALID;
wire [31:0]m02_couplers_to_processing_system7_0_axi_periph_WDATA;
wire m02_couplers_to_processing_system7_0_axi_periph_WREADY;
wire [3:0]m02_couplers_to_processing_system7_0_axi_periph_WSTRB;
wire m02_couplers_to_processing_system7_0_axi_periph_WVALID;
wire processing_system7_0_axi_periph_ACLK_net;
wire [0:0]processing_system7_0_axi_periph_ARESETN_net;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_ARADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_ARID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_ARLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_ARQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_ARSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_ARVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_AWADDR;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWBURST;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWCACHE;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_AWID;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWLEN;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_AWLOCK;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWPROT;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_AWQOS;
wire processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
wire [2:0]processing_system7_0_axi_periph_to_s00_couplers_AWSIZE;
wire processing_system7_0_axi_periph_to_s00_couplers_AWVALID;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_BID;
wire processing_system7_0_axi_periph_to_s00_couplers_BREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_BRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_BVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_RDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_RID;
wire processing_system7_0_axi_periph_to_s00_couplers_RLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_RREADY;
wire [1:0]processing_system7_0_axi_periph_to_s00_couplers_RRESP;
wire processing_system7_0_axi_periph_to_s00_couplers_RVALID;
wire [31:0]processing_system7_0_axi_periph_to_s00_couplers_WDATA;
wire [11:0]processing_system7_0_axi_periph_to_s00_couplers_WID;
wire processing_system7_0_axi_periph_to_s00_couplers_WLAST;
wire processing_system7_0_axi_periph_to_s00_couplers_WREADY;
wire [3:0]processing_system7_0_axi_periph_to_s00_couplers_WSTRB;
wire processing_system7_0_axi_periph_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_xbar_ARADDR;
wire [2:0]s00_couplers_to_xbar_ARPROT;
wire [0:0]s00_couplers_to_xbar_ARREADY;
wire s00_couplers_to_xbar_ARVALID;
wire [31:0]s00_couplers_to_xbar_AWADDR;
wire [2:0]s00_couplers_to_xbar_AWPROT;
wire [0:0]s00_couplers_to_xbar_AWREADY;
wire s00_couplers_to_xbar_AWVALID;
wire s00_couplers_to_xbar_BREADY;
wire [1:0]s00_couplers_to_xbar_BRESP;
wire [0:0]s00_couplers_to_xbar_BVALID;
wire [31:0]s00_couplers_to_xbar_RDATA;
wire s00_couplers_to_xbar_RREADY;
wire [1:0]s00_couplers_to_xbar_RRESP;
wire [0:0]s00_couplers_to_xbar_RVALID;
wire [31:0]s00_couplers_to_xbar_WDATA;
wire [0:0]s00_couplers_to_xbar_WREADY;
wire [3:0]s00_couplers_to_xbar_WSTRB;
wire s00_couplers_to_xbar_WVALID;
wire [31:0]xbar_to_m00_couplers_ARADDR;
wire [0:0]xbar_to_m00_couplers_ARREADY;
wire [0:0]xbar_to_m00_couplers_ARVALID;
wire [31:0]xbar_to_m00_couplers_AWADDR;
wire [0:0]xbar_to_m00_couplers_AWREADY;
wire [0:0]xbar_to_m00_couplers_AWVALID;
wire [0:0]xbar_to_m00_couplers_BREADY;
wire [1:0]xbar_to_m00_couplers_BRESP;
wire [0:0]xbar_to_m00_couplers_BVALID;
wire [31:0]xbar_to_m00_couplers_RDATA;
wire [0:0]xbar_to_m00_couplers_RREADY;
wire [1:0]xbar_to_m00_couplers_RRESP;
wire [0:0]xbar_to_m00_couplers_RVALID;
wire [31:0]xbar_to_m00_couplers_WDATA;
wire [0:0]xbar_to_m00_couplers_WREADY;
wire [3:0]xbar_to_m00_couplers_WSTRB;
wire [0:0]xbar_to_m00_couplers_WVALID;
wire [63:32]xbar_to_m01_couplers_ARADDR;
wire xbar_to_m01_couplers_ARREADY;
wire [1:1]xbar_to_m01_couplers_ARVALID;
wire [63:32]xbar_to_m01_couplers_AWADDR;
wire xbar_to_m01_couplers_AWREADY;
wire [1:1]xbar_to_m01_couplers_AWVALID;
wire [1:1]xbar_to_m01_couplers_BREADY;
wire [1:0]xbar_to_m01_couplers_BRESP;
wire xbar_to_m01_couplers_BVALID;
wire [31:0]xbar_to_m01_couplers_RDATA;
wire [1:1]xbar_to_m01_couplers_RREADY;
wire [1:0]xbar_to_m01_couplers_RRESP;
wire xbar_to_m01_couplers_RVALID;
wire [63:32]xbar_to_m01_couplers_WDATA;
wire xbar_to_m01_couplers_WREADY;
wire [7:4]xbar_to_m01_couplers_WSTRB;
wire [1:1]xbar_to_m01_couplers_WVALID;
wire [95:64]xbar_to_m02_couplers_ARADDR;
wire xbar_to_m02_couplers_ARREADY;
wire [2:2]xbar_to_m02_couplers_ARVALID;
wire [95:64]xbar_to_m02_couplers_AWADDR;
wire xbar_to_m02_couplers_AWREADY;
wire [2:2]xbar_to_m02_couplers_AWVALID;
wire [2:2]xbar_to_m02_couplers_BREADY;
wire [1:0]xbar_to_m02_couplers_BRESP;
wire xbar_to_m02_couplers_BVALID;
wire [31:0]xbar_to_m02_couplers_RDATA;
wire [2:2]xbar_to_m02_couplers_RREADY;
wire [1:0]xbar_to_m02_couplers_RRESP;
wire xbar_to_m02_couplers_RVALID;
wire [95:64]xbar_to_m02_couplers_WDATA;
wire xbar_to_m02_couplers_WREADY;
wire [11:8]xbar_to_m02_couplers_WSTRB;
wire [2:2]xbar_to_m02_couplers_WVALID;
assign M00_ACLK_1 = M00_ACLK;
assign M00_ARESETN_1 = M00_ARESETN[0];
assign M00_AXI_araddr[8:0] = m00_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M00_AXI_arvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M00_AXI_awaddr[8:0] = m00_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M00_AXI_awvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M00_AXI_bready[0] = m00_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M00_AXI_rready[0] = m00_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M00_AXI_wdata[31:0] = m00_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M00_AXI_wstrb[3:0] = m00_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M00_AXI_wvalid[0] = m00_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M01_ACLK_1 = M01_ACLK;
assign M01_ARESETN_1 = M01_ARESETN[0];
assign M01_AXI_araddr[8:0] = m01_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M01_AXI_arvalid = m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M01_AXI_awaddr[8:0] = m01_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M01_AXI_awvalid = m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M01_AXI_bready = m01_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M01_AXI_rready = m01_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M01_AXI_wdata[31:0] = m01_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M01_AXI_wstrb[3:0] = m01_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M01_AXI_wvalid = m01_couplers_to_processing_system7_0_axi_periph_WVALID;
assign M02_ACLK_1 = M02_ACLK;
assign M02_ARESETN_1 = M02_ARESETN[0];
assign M02_AXI_araddr[10:0] = m02_couplers_to_processing_system7_0_axi_periph_ARADDR;
assign M02_AXI_arvalid = m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
assign M02_AXI_awaddr[10:0] = m02_couplers_to_processing_system7_0_axi_periph_AWADDR;
assign M02_AXI_awvalid = m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
assign M02_AXI_bready = m02_couplers_to_processing_system7_0_axi_periph_BREADY;
assign M02_AXI_rready = m02_couplers_to_processing_system7_0_axi_periph_RREADY;
assign M02_AXI_wdata[31:0] = m02_couplers_to_processing_system7_0_axi_periph_WDATA;
assign M02_AXI_wstrb[3:0] = m02_couplers_to_processing_system7_0_axi_periph_WSTRB;
assign M02_AXI_wvalid = m02_couplers_to_processing_system7_0_axi_periph_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
assign S00_AXI_awready = processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = processing_system7_0_axi_periph_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = processing_system7_0_axi_periph_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = processing_system7_0_axi_periph_to_s00_couplers_RID;
assign S00_AXI_rlast = processing_system7_0_axi_periph_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = processing_system7_0_axi_periph_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = processing_system7_0_axi_periph_to_s00_couplers_RVALID;
assign S00_AXI_wready = processing_system7_0_axi_periph_to_s00_couplers_WREADY;
assign m00_couplers_to_processing_system7_0_axi_periph_ARREADY = M00_AXI_arready[0];
assign m00_couplers_to_processing_system7_0_axi_periph_AWREADY = M00_AXI_awready[0];
assign m00_couplers_to_processing_system7_0_axi_periph_BRESP = M00_AXI_bresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_BVALID = M00_AXI_bvalid[0];
assign m00_couplers_to_processing_system7_0_axi_periph_RDATA = M00_AXI_rdata[31:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RRESP = M00_AXI_rresp[1:0];
assign m00_couplers_to_processing_system7_0_axi_periph_RVALID = M00_AXI_rvalid[0];
assign m00_couplers_to_processing_system7_0_axi_periph_WREADY = M00_AXI_wready[0];
assign m01_couplers_to_processing_system7_0_axi_periph_ARREADY = M01_AXI_arready;
assign m01_couplers_to_processing_system7_0_axi_periph_AWREADY = M01_AXI_awready;
assign m01_couplers_to_processing_system7_0_axi_periph_BRESP = M01_AXI_bresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_BVALID = M01_AXI_bvalid;
assign m01_couplers_to_processing_system7_0_axi_periph_RDATA = M01_AXI_rdata[31:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RRESP = M01_AXI_rresp[1:0];
assign m01_couplers_to_processing_system7_0_axi_periph_RVALID = M01_AXI_rvalid;
assign m01_couplers_to_processing_system7_0_axi_periph_WREADY = M01_AXI_wready;
assign m02_couplers_to_processing_system7_0_axi_periph_ARREADY = M02_AXI_arready;
assign m02_couplers_to_processing_system7_0_axi_periph_AWREADY = M02_AXI_awready;
assign m02_couplers_to_processing_system7_0_axi_periph_BRESP = M02_AXI_bresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_BVALID = M02_AXI_bvalid;
assign m02_couplers_to_processing_system7_0_axi_periph_RDATA = M02_AXI_rdata[31:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RRESP = M02_AXI_rresp[1:0];
assign m02_couplers_to_processing_system7_0_axi_periph_RVALID = M02_AXI_rvalid;
assign m02_couplers_to_processing_system7_0_axi_periph_WREADY = M02_AXI_wready;
assign processing_system7_0_axi_periph_ACLK_net = ACLK;
assign processing_system7_0_axi_periph_ARESETN_net = ARESETN[0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign processing_system7_0_axi_periph_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign processing_system7_0_axi_periph_to_s00_couplers_BREADY = S00_AXI_bready;
assign processing_system7_0_axi_periph_to_s00_couplers_RREADY = S00_AXI_rready;
assign processing_system7_0_axi_periph_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WLAST = S00_AXI_wlast;
assign processing_system7_0_axi_periph_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign processing_system7_0_axi_periph_to_s00_couplers_WVALID = S00_AXI_wvalid;
m00_couplers_imp_ZVW4AE m00_couplers
(.M_ACLK(M00_ACLK_1),
.M_ARESETN(M00_ARESETN_1),
.M_AXI_araddr(m00_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m00_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m00_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m00_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m00_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m00_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m00_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m00_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m00_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m00_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m00_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m00_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m00_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m00_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m00_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m00_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m00_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m00_couplers_ARADDR[8:0]),
.S_AXI_arready(xbar_to_m00_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m00_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m00_couplers_AWADDR[8:0]),
.S_AXI_awready(xbar_to_m00_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m00_couplers_AWVALID),
.S_AXI_bready(xbar_to_m00_couplers_BREADY),
.S_AXI_bresp(xbar_to_m00_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m00_couplers_BVALID),
.S_AXI_rdata(xbar_to_m00_couplers_RDATA),
.S_AXI_rready(xbar_to_m00_couplers_RREADY),
.S_AXI_rresp(xbar_to_m00_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m00_couplers_RVALID),
.S_AXI_wdata(xbar_to_m00_couplers_WDATA),
.S_AXI_wready(xbar_to_m00_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m00_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m00_couplers_WVALID));
m01_couplers_imp_PQKNCJ m01_couplers
(.M_ACLK(M01_ACLK_1),
.M_ARESETN(M01_ARESETN_1),
.M_AXI_araddr(m01_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m01_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m01_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m01_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m01_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m01_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m01_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m01_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m01_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m01_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m01_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m01_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m01_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m01_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m01_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m01_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m01_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m01_couplers_ARADDR[40:32]),
.S_AXI_arready(xbar_to_m01_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m01_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m01_couplers_AWADDR[40:32]),
.S_AXI_awready(xbar_to_m01_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m01_couplers_AWVALID),
.S_AXI_bready(xbar_to_m01_couplers_BREADY),
.S_AXI_bresp(xbar_to_m01_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m01_couplers_BVALID),
.S_AXI_rdata(xbar_to_m01_couplers_RDATA),
.S_AXI_rready(xbar_to_m01_couplers_RREADY),
.S_AXI_rresp(xbar_to_m01_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m01_couplers_RVALID),
.S_AXI_wdata(xbar_to_m01_couplers_WDATA),
.S_AXI_wready(xbar_to_m01_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m01_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m01_couplers_WVALID));
m02_couplers_imp_1QFTZ3X m02_couplers
(.M_ACLK(M02_ACLK_1),
.M_ARESETN(M02_ARESETN_1),
.M_AXI_araddr(m02_couplers_to_processing_system7_0_axi_periph_ARADDR),
.M_AXI_arready(m02_couplers_to_processing_system7_0_axi_periph_ARREADY),
.M_AXI_arvalid(m02_couplers_to_processing_system7_0_axi_periph_ARVALID),
.M_AXI_awaddr(m02_couplers_to_processing_system7_0_axi_periph_AWADDR),
.M_AXI_awready(m02_couplers_to_processing_system7_0_axi_periph_AWREADY),
.M_AXI_awvalid(m02_couplers_to_processing_system7_0_axi_periph_AWVALID),
.M_AXI_bready(m02_couplers_to_processing_system7_0_axi_periph_BREADY),
.M_AXI_bresp(m02_couplers_to_processing_system7_0_axi_periph_BRESP),
.M_AXI_bvalid(m02_couplers_to_processing_system7_0_axi_periph_BVALID),
.M_AXI_rdata(m02_couplers_to_processing_system7_0_axi_periph_RDATA),
.M_AXI_rready(m02_couplers_to_processing_system7_0_axi_periph_RREADY),
.M_AXI_rresp(m02_couplers_to_processing_system7_0_axi_periph_RRESP),
.M_AXI_rvalid(m02_couplers_to_processing_system7_0_axi_periph_RVALID),
.M_AXI_wdata(m02_couplers_to_processing_system7_0_axi_periph_WDATA),
.M_AXI_wready(m02_couplers_to_processing_system7_0_axi_periph_WREADY),
.M_AXI_wstrb(m02_couplers_to_processing_system7_0_axi_periph_WSTRB),
.M_AXI_wvalid(m02_couplers_to_processing_system7_0_axi_periph_WVALID),
.S_ACLK(processing_system7_0_axi_periph_ACLK_net),
.S_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.S_AXI_araddr(xbar_to_m02_couplers_ARADDR[74:64]),
.S_AXI_arready(xbar_to_m02_couplers_ARREADY),
.S_AXI_arvalid(xbar_to_m02_couplers_ARVALID),
.S_AXI_awaddr(xbar_to_m02_couplers_AWADDR[74:64]),
.S_AXI_awready(xbar_to_m02_couplers_AWREADY),
.S_AXI_awvalid(xbar_to_m02_couplers_AWVALID),
.S_AXI_bready(xbar_to_m02_couplers_BREADY),
.S_AXI_bresp(xbar_to_m02_couplers_BRESP),
.S_AXI_bvalid(xbar_to_m02_couplers_BVALID),
.S_AXI_rdata(xbar_to_m02_couplers_RDATA),
.S_AXI_rready(xbar_to_m02_couplers_RREADY),
.S_AXI_rresp(xbar_to_m02_couplers_RRESP),
.S_AXI_rvalid(xbar_to_m02_couplers_RVALID),
.S_AXI_wdata(xbar_to_m02_couplers_WDATA),
.S_AXI_wready(xbar_to_m02_couplers_WREADY),
.S_AXI_wstrb(xbar_to_m02_couplers_WSTRB),
.S_AXI_wvalid(xbar_to_m02_couplers_WVALID));
s00_couplers_imp_B67PN0 s00_couplers
(.M_ACLK(processing_system7_0_axi_periph_ACLK_net),
.M_ARESETN(processing_system7_0_axi_periph_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_xbar_ARADDR),
.M_AXI_arprot(s00_couplers_to_xbar_ARPROT),
.M_AXI_arready(s00_couplers_to_xbar_ARREADY),
.M_AXI_arvalid(s00_couplers_to_xbar_ARVALID),
.M_AXI_awaddr(s00_couplers_to_xbar_AWADDR),
.M_AXI_awprot(s00_couplers_to_xbar_AWPROT),
.M_AXI_awready(s00_couplers_to_xbar_AWREADY),
.M_AXI_awvalid(s00_couplers_to_xbar_AWVALID),
.M_AXI_bready(s00_couplers_to_xbar_BREADY),
.M_AXI_bresp(s00_couplers_to_xbar_BRESP),
.M_AXI_bvalid(s00_couplers_to_xbar_BVALID),
.M_AXI_rdata(s00_couplers_to_xbar_RDATA),
.M_AXI_rready(s00_couplers_to_xbar_RREADY),
.M_AXI_rresp(s00_couplers_to_xbar_RRESP),
.M_AXI_rvalid(s00_couplers_to_xbar_RVALID),
.M_AXI_wdata(s00_couplers_to_xbar_WDATA),
.M_AXI_wready(s00_couplers_to_xbar_WREADY),
.M_AXI_wstrb(s00_couplers_to_xbar_WSTRB),
.M_AXI_wvalid(s00_couplers_to_xbar_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(processing_system7_0_axi_periph_to_s00_couplers_ARADDR),
.S_AXI_arburst(processing_system7_0_axi_periph_to_s00_couplers_ARBURST),
.S_AXI_arcache(processing_system7_0_axi_periph_to_s00_couplers_ARCACHE),
.S_AXI_arid(processing_system7_0_axi_periph_to_s00_couplers_ARID),
.S_AXI_arlen(processing_system7_0_axi_periph_to_s00_couplers_ARLEN),
.S_AXI_arlock(processing_system7_0_axi_periph_to_s00_couplers_ARLOCK),
.S_AXI_arprot(processing_system7_0_axi_periph_to_s00_couplers_ARPROT),
.S_AXI_arqos(processing_system7_0_axi_periph_to_s00_couplers_ARQOS),
.S_AXI_arready(processing_system7_0_axi_periph_to_s00_couplers_ARREADY),
.S_AXI_arsize(processing_system7_0_axi_periph_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(processing_system7_0_axi_periph_to_s00_couplers_ARVALID),
.S_AXI_awaddr(processing_system7_0_axi_periph_to_s00_couplers_AWADDR),
.S_AXI_awburst(processing_system7_0_axi_periph_to_s00_couplers_AWBURST),
.S_AXI_awcache(processing_system7_0_axi_periph_to_s00_couplers_AWCACHE),
.S_AXI_awid(processing_system7_0_axi_periph_to_s00_couplers_AWID),
.S_AXI_awlen(processing_system7_0_axi_periph_to_s00_couplers_AWLEN),
.S_AXI_awlock(processing_system7_0_axi_periph_to_s00_couplers_AWLOCK),
.S_AXI_awprot(processing_system7_0_axi_periph_to_s00_couplers_AWPROT),
.S_AXI_awqos(processing_system7_0_axi_periph_to_s00_couplers_AWQOS),
.S_AXI_awready(processing_system7_0_axi_periph_to_s00_couplers_AWREADY),
.S_AXI_awsize(processing_system7_0_axi_periph_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(processing_system7_0_axi_periph_to_s00_couplers_AWVALID),
.S_AXI_bid(processing_system7_0_axi_periph_to_s00_couplers_BID),
.S_AXI_bready(processing_system7_0_axi_periph_to_s00_couplers_BREADY),
.S_AXI_bresp(processing_system7_0_axi_periph_to_s00_couplers_BRESP),
.S_AXI_bvalid(processing_system7_0_axi_periph_to_s00_couplers_BVALID),
.S_AXI_rdata(processing_system7_0_axi_periph_to_s00_couplers_RDATA),
.S_AXI_rid(processing_system7_0_axi_periph_to_s00_couplers_RID),
.S_AXI_rlast(processing_system7_0_axi_periph_to_s00_couplers_RLAST),
.S_AXI_rready(processing_system7_0_axi_periph_to_s00_couplers_RREADY),
.S_AXI_rresp(processing_system7_0_axi_periph_to_s00_couplers_RRESP),
.S_AXI_rvalid(processing_system7_0_axi_periph_to_s00_couplers_RVALID),
.S_AXI_wdata(processing_system7_0_axi_periph_to_s00_couplers_WDATA),
.S_AXI_wid(processing_system7_0_axi_periph_to_s00_couplers_WID),
.S_AXI_wlast(processing_system7_0_axi_periph_to_s00_couplers_WLAST),
.S_AXI_wready(processing_system7_0_axi_periph_to_s00_couplers_WREADY),
.S_AXI_wstrb(processing_system7_0_axi_periph_to_s00_couplers_WSTRB),
.S_AXI_wvalid(processing_system7_0_axi_periph_to_s00_couplers_WVALID));
cpu_xbar_0 xbar
(.aclk(processing_system7_0_axi_periph_ACLK_net),
.aresetn(processing_system7_0_axi_periph_ARESETN_net),
.m_axi_araddr({xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}),
.m_axi_arready({xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}),
.m_axi_arvalid({xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}),
.m_axi_awaddr({xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}),
.m_axi_awready({xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}),
.m_axi_awvalid({xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}),
.m_axi_bready({xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}),
.m_axi_bresp({xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}),
.m_axi_bvalid({xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}),
.m_axi_rdata({xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}),
.m_axi_rready({xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}),
.m_axi_rresp({xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}),
.m_axi_rvalid({xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}),
.m_axi_wdata({xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}),
.m_axi_wready({xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}),
.m_axi_wstrb({xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}),
.m_axi_wvalid({xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}),
.s_axi_araddr(s00_couplers_to_xbar_ARADDR),
.s_axi_arprot(s00_couplers_to_xbar_ARPROT),
.s_axi_arready(s00_couplers_to_xbar_ARREADY),
.s_axi_arvalid(s00_couplers_to_xbar_ARVALID),
.s_axi_awaddr(s00_couplers_to_xbar_AWADDR),
.s_axi_awprot(s00_couplers_to_xbar_AWPROT),
.s_axi_awready(s00_couplers_to_xbar_AWREADY),
.s_axi_awvalid(s00_couplers_to_xbar_AWVALID),
.s_axi_bready(s00_couplers_to_xbar_BREADY),
.s_axi_bresp(s00_couplers_to_xbar_BRESP),
.s_axi_bvalid(s00_couplers_to_xbar_BVALID),
.s_axi_rdata(s00_couplers_to_xbar_RDATA),
.s_axi_rready(s00_couplers_to_xbar_RREADY),
.s_axi_rresp(s00_couplers_to_xbar_RRESP),
.s_axi_rvalid(s00_couplers_to_xbar_RVALID),
.s_axi_wdata(s00_couplers_to_xbar_WDATA),
.s_axi_wready(s00_couplers_to_xbar_WREADY),
.s_axi_wstrb(s00_couplers_to_xbar_WSTRB),
.s_axi_wvalid(s00_couplers_to_xbar_WVALID));
endmodule
module cpu_processing_system7_0_axi_periph_1_0
(ACLK,
ARESETN,
M00_ACLK,
M00_ARESETN,
M00_AXI_araddr,
M00_AXI_arready,
M00_AXI_arvalid,
M00_AXI_awaddr,
M00_AXI_awready,
M00_AXI_awvalid,
M00_AXI_bready,
M00_AXI_bresp,
M00_AXI_bvalid,
M00_AXI_rdata,
M00_AXI_rready,
M00_AXI_rresp,
M00_AXI_rvalid,
M00_AXI_wdata,
M00_AXI_wready,
M00_AXI_wstrb,
M00_AXI_wvalid,
S00_ACLK,
S00_ARESETN,
S00_AXI_araddr,
S00_AXI_arburst,
S00_AXI_arcache,
S00_AXI_arid,
S00_AXI_arlen,
S00_AXI_arlock,
S00_AXI_arprot,
S00_AXI_arqos,
S00_AXI_arready,
S00_AXI_arsize,
S00_AXI_arvalid,
S00_AXI_awaddr,
S00_AXI_awburst,
S00_AXI_awcache,
S00_AXI_awid,
S00_AXI_awlen,
S00_AXI_awlock,
S00_AXI_awprot,
S00_AXI_awqos,
S00_AXI_awready,
S00_AXI_awsize,
S00_AXI_awvalid,
S00_AXI_bid,
S00_AXI_bready,
S00_AXI_bresp,
S00_AXI_bvalid,
S00_AXI_rdata,
S00_AXI_rid,
S00_AXI_rlast,
S00_AXI_rready,
S00_AXI_rresp,
S00_AXI_rvalid,
S00_AXI_wdata,
S00_AXI_wid,
S00_AXI_wlast,
S00_AXI_wready,
S00_AXI_wstrb,
S00_AXI_wvalid);
input ACLK;
input [0:0]ARESETN;
input M00_ACLK;
input [0:0]M00_ARESETN;
output [31:0]M00_AXI_araddr;
input M00_AXI_arready;
output M00_AXI_arvalid;
output [31:0]M00_AXI_awaddr;
input M00_AXI_awready;
output M00_AXI_awvalid;
output M00_AXI_bready;
input [1:0]M00_AXI_bresp;
input M00_AXI_bvalid;
input [31:0]M00_AXI_rdata;
output M00_AXI_rready;
input [1:0]M00_AXI_rresp;
input M00_AXI_rvalid;
output [31:0]M00_AXI_wdata;
input M00_AXI_wready;
output [3:0]M00_AXI_wstrb;
output M00_AXI_wvalid;
input S00_ACLK;
input [0:0]S00_ARESETN;
input [31:0]S00_AXI_araddr;
input [1:0]S00_AXI_arburst;
input [3:0]S00_AXI_arcache;
input [11:0]S00_AXI_arid;
input [3:0]S00_AXI_arlen;
input [1:0]S00_AXI_arlock;
input [2:0]S00_AXI_arprot;
input [3:0]S00_AXI_arqos;
output S00_AXI_arready;
input [2:0]S00_AXI_arsize;
input S00_AXI_arvalid;
input [31:0]S00_AXI_awaddr;
input [1:0]S00_AXI_awburst;
input [3:0]S00_AXI_awcache;
input [11:0]S00_AXI_awid;
input [3:0]S00_AXI_awlen;
input [1:0]S00_AXI_awlock;
input [2:0]S00_AXI_awprot;
input [3:0]S00_AXI_awqos;
output S00_AXI_awready;
input [2:0]S00_AXI_awsize;
input S00_AXI_awvalid;
output [11:0]S00_AXI_bid;
input S00_AXI_bready;
output [1:0]S00_AXI_bresp;
output S00_AXI_bvalid;
output [31:0]S00_AXI_rdata;
output [11:0]S00_AXI_rid;
output S00_AXI_rlast;
input S00_AXI_rready;
output [1:0]S00_AXI_rresp;
output S00_AXI_rvalid;
input [31:0]S00_AXI_wdata;
input [11:0]S00_AXI_wid;
input S00_AXI_wlast;
output S00_AXI_wready;
input [3:0]S00_AXI_wstrb;
input S00_AXI_wvalid;
wire S00_ACLK_1;
wire [0:0]S00_ARESETN_1;
wire processing_system7_0_axi_periph_1_ACLK_net;
wire [0:0]processing_system7_0_axi_periph_1_ARESETN_net;
wire [31:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARID;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK;
wire [2:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS;
wire processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY;
wire [2:0]processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE;
wire processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID;
wire [31:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWID;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK;
wire [2:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS;
wire processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY;
wire [2:0]processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE;
wire processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_BID;
wire processing_system7_0_axi_periph_1_to_s00_couplers_BREADY;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_BRESP;
wire processing_system7_0_axi_periph_1_to_s00_couplers_BVALID;
wire [31:0]processing_system7_0_axi_periph_1_to_s00_couplers_RDATA;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_RID;
wire processing_system7_0_axi_periph_1_to_s00_couplers_RLAST;
wire processing_system7_0_axi_periph_1_to_s00_couplers_RREADY;
wire [1:0]processing_system7_0_axi_periph_1_to_s00_couplers_RRESP;
wire processing_system7_0_axi_periph_1_to_s00_couplers_RVALID;
wire [31:0]processing_system7_0_axi_periph_1_to_s00_couplers_WDATA;
wire [11:0]processing_system7_0_axi_periph_1_to_s00_couplers_WID;
wire processing_system7_0_axi_periph_1_to_s00_couplers_WLAST;
wire processing_system7_0_axi_periph_1_to_s00_couplers_WREADY;
wire [3:0]processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB;
wire processing_system7_0_axi_periph_1_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR;
wire s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY;
wire s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID;
wire [31:0]s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR;
wire s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY;
wire s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID;
wire s00_couplers_to_processing_system7_0_axi_periph_1_BREADY;
wire [1:0]s00_couplers_to_processing_system7_0_axi_periph_1_BRESP;
wire s00_couplers_to_processing_system7_0_axi_periph_1_BVALID;
wire [31:0]s00_couplers_to_processing_system7_0_axi_periph_1_RDATA;
wire s00_couplers_to_processing_system7_0_axi_periph_1_RREADY;
wire [1:0]s00_couplers_to_processing_system7_0_axi_periph_1_RRESP;
wire s00_couplers_to_processing_system7_0_axi_periph_1_RVALID;
wire [31:0]s00_couplers_to_processing_system7_0_axi_periph_1_WDATA;
wire s00_couplers_to_processing_system7_0_axi_periph_1_WREADY;
wire [3:0]s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB;
wire s00_couplers_to_processing_system7_0_axi_periph_1_WVALID;
assign M00_AXI_araddr[31:0] = s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR;
assign M00_AXI_arvalid = s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID;
assign M00_AXI_awaddr[31:0] = s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR;
assign M00_AXI_awvalid = s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID;
assign M00_AXI_bready = s00_couplers_to_processing_system7_0_axi_periph_1_BREADY;
assign M00_AXI_rready = s00_couplers_to_processing_system7_0_axi_periph_1_RREADY;
assign M00_AXI_wdata[31:0] = s00_couplers_to_processing_system7_0_axi_periph_1_WDATA;
assign M00_AXI_wstrb[3:0] = s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB;
assign M00_AXI_wvalid = s00_couplers_to_processing_system7_0_axi_periph_1_WVALID;
assign S00_ACLK_1 = S00_ACLK;
assign S00_ARESETN_1 = S00_ARESETN[0];
assign S00_AXI_arready = processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY;
assign S00_AXI_awready = processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY;
assign S00_AXI_bid[11:0] = processing_system7_0_axi_periph_1_to_s00_couplers_BID;
assign S00_AXI_bresp[1:0] = processing_system7_0_axi_periph_1_to_s00_couplers_BRESP;
assign S00_AXI_bvalid = processing_system7_0_axi_periph_1_to_s00_couplers_BVALID;
assign S00_AXI_rdata[31:0] = processing_system7_0_axi_periph_1_to_s00_couplers_RDATA;
assign S00_AXI_rid[11:0] = processing_system7_0_axi_periph_1_to_s00_couplers_RID;
assign S00_AXI_rlast = processing_system7_0_axi_periph_1_to_s00_couplers_RLAST;
assign S00_AXI_rresp[1:0] = processing_system7_0_axi_periph_1_to_s00_couplers_RRESP;
assign S00_AXI_rvalid = processing_system7_0_axi_periph_1_to_s00_couplers_RVALID;
assign S00_AXI_wready = processing_system7_0_axi_periph_1_to_s00_couplers_WREADY;
assign processing_system7_0_axi_periph_1_ACLK_net = M00_ACLK;
assign processing_system7_0_axi_periph_1_ARESETN_net = M00_ARESETN[0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR = S00_AXI_araddr[31:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARID = S00_AXI_arid[11:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN = S00_AXI_arlen[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK = S00_AXI_arlock[1:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS = S00_AXI_arqos[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID = S00_AXI_arvalid;
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR = S00_AXI_awaddr[31:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWID = S00_AXI_awid[11:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN = S00_AXI_awlen[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK = S00_AXI_awlock[1:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS = S00_AXI_awqos[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID = S00_AXI_awvalid;
assign processing_system7_0_axi_periph_1_to_s00_couplers_BREADY = S00_AXI_bready;
assign processing_system7_0_axi_periph_1_to_s00_couplers_RREADY = S00_AXI_rready;
assign processing_system7_0_axi_periph_1_to_s00_couplers_WDATA = S00_AXI_wdata[31:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_WID = S00_AXI_wid[11:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_WLAST = S00_AXI_wlast;
assign processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB = S00_AXI_wstrb[3:0];
assign processing_system7_0_axi_periph_1_to_s00_couplers_WVALID = S00_AXI_wvalid;
assign s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY = M00_AXI_arready;
assign s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY = M00_AXI_awready;
assign s00_couplers_to_processing_system7_0_axi_periph_1_BRESP = M00_AXI_bresp[1:0];
assign s00_couplers_to_processing_system7_0_axi_periph_1_BVALID = M00_AXI_bvalid;
assign s00_couplers_to_processing_system7_0_axi_periph_1_RDATA = M00_AXI_rdata[31:0];
assign s00_couplers_to_processing_system7_0_axi_periph_1_RRESP = M00_AXI_rresp[1:0];
assign s00_couplers_to_processing_system7_0_axi_periph_1_RVALID = M00_AXI_rvalid;
assign s00_couplers_to_processing_system7_0_axi_periph_1_WREADY = M00_AXI_wready;
s00_couplers_imp_1AHKP6S s00_couplers
(.M_ACLK(processing_system7_0_axi_periph_1_ACLK_net),
.M_ARESETN(processing_system7_0_axi_periph_1_ARESETN_net),
.M_AXI_araddr(s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR),
.M_AXI_arready(s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY),
.M_AXI_arvalid(s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID),
.M_AXI_awaddr(s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR),
.M_AXI_awready(s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY),
.M_AXI_awvalid(s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID),
.M_AXI_bready(s00_couplers_to_processing_system7_0_axi_periph_1_BREADY),
.M_AXI_bresp(s00_couplers_to_processing_system7_0_axi_periph_1_BRESP),
.M_AXI_bvalid(s00_couplers_to_processing_system7_0_axi_periph_1_BVALID),
.M_AXI_rdata(s00_couplers_to_processing_system7_0_axi_periph_1_RDATA),
.M_AXI_rready(s00_couplers_to_processing_system7_0_axi_periph_1_RREADY),
.M_AXI_rresp(s00_couplers_to_processing_system7_0_axi_periph_1_RRESP),
.M_AXI_rvalid(s00_couplers_to_processing_system7_0_axi_periph_1_RVALID),
.M_AXI_wdata(s00_couplers_to_processing_system7_0_axi_periph_1_WDATA),
.M_AXI_wready(s00_couplers_to_processing_system7_0_axi_periph_1_WREADY),
.M_AXI_wstrb(s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB),
.M_AXI_wvalid(s00_couplers_to_processing_system7_0_axi_periph_1_WVALID),
.S_ACLK(S00_ACLK_1),
.S_ARESETN(S00_ARESETN_1),
.S_AXI_araddr(processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR),
.S_AXI_arburst(processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST),
.S_AXI_arcache(processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE),
.S_AXI_arid(processing_system7_0_axi_periph_1_to_s00_couplers_ARID),
.S_AXI_arlen(processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN),
.S_AXI_arlock(processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK),
.S_AXI_arprot(processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT),
.S_AXI_arqos(processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS),
.S_AXI_arready(processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY),
.S_AXI_arsize(processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE),
.S_AXI_arvalid(processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID),
.S_AXI_awaddr(processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR),
.S_AXI_awburst(processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST),
.S_AXI_awcache(processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE),
.S_AXI_awid(processing_system7_0_axi_periph_1_to_s00_couplers_AWID),
.S_AXI_awlen(processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN),
.S_AXI_awlock(processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK),
.S_AXI_awprot(processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT),
.S_AXI_awqos(processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS),
.S_AXI_awready(processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY),
.S_AXI_awsize(processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE),
.S_AXI_awvalid(processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID),
.S_AXI_bid(processing_system7_0_axi_periph_1_to_s00_couplers_BID),
.S_AXI_bready(processing_system7_0_axi_periph_1_to_s00_couplers_BREADY),
.S_AXI_bresp(processing_system7_0_axi_periph_1_to_s00_couplers_BRESP),
.S_AXI_bvalid(processing_system7_0_axi_periph_1_to_s00_couplers_BVALID),
.S_AXI_rdata(processing_system7_0_axi_periph_1_to_s00_couplers_RDATA),
.S_AXI_rid(processing_system7_0_axi_periph_1_to_s00_couplers_RID),
.S_AXI_rlast(processing_system7_0_axi_periph_1_to_s00_couplers_RLAST),
.S_AXI_rready(processing_system7_0_axi_periph_1_to_s00_couplers_RREADY),
.S_AXI_rresp(processing_system7_0_axi_periph_1_to_s00_couplers_RRESP),
.S_AXI_rvalid(processing_system7_0_axi_periph_1_to_s00_couplers_RVALID),
.S_AXI_wdata(processing_system7_0_axi_periph_1_to_s00_couplers_WDATA),
.S_AXI_wid(processing_system7_0_axi_periph_1_to_s00_couplers_WID),
.S_AXI_wlast(processing_system7_0_axi_periph_1_to_s00_couplers_WLAST),
.S_AXI_wready(processing_system7_0_axi_periph_1_to_s00_couplers_WREADY),
.S_AXI_wstrb(processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB),
.S_AXI_wvalid(processing_system7_0_axi_periph_1_to_s00_couplers_WVALID));
endmodule
module m00_couplers_imp_ZVW4AE
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [8:0]M_AXI_araddr;
input [0:0]M_AXI_arready;
output [0:0]M_AXI_arvalid;
output [8:0]M_AXI_awaddr;
input [0:0]M_AXI_awready;
output [0:0]M_AXI_awvalid;
output [0:0]M_AXI_bready;
input [1:0]M_AXI_bresp;
input [0:0]M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output [0:0]M_AXI_rready;
input [1:0]M_AXI_rresp;
input [0:0]M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input [0:0]M_AXI_wready;
output [3:0]M_AXI_wstrb;
output [0:0]M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [8:0]S_AXI_araddr;
output [0:0]S_AXI_arready;
input [0:0]S_AXI_arvalid;
input [8:0]S_AXI_awaddr;
output [0:0]S_AXI_awready;
input [0:0]S_AXI_awvalid;
input [0:0]S_AXI_bready;
output [1:0]S_AXI_bresp;
output [0:0]S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input [0:0]S_AXI_rready;
output [1:0]S_AXI_rresp;
output [0:0]S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output [0:0]S_AXI_wready;
input [3:0]S_AXI_wstrb;
input [0:0]S_AXI_wvalid;
wire [8:0]m00_couplers_to_m00_couplers_ARADDR;
wire [0:0]m00_couplers_to_m00_couplers_ARREADY;
wire [0:0]m00_couplers_to_m00_couplers_ARVALID;
wire [8:0]m00_couplers_to_m00_couplers_AWADDR;
wire [0:0]m00_couplers_to_m00_couplers_AWREADY;
wire [0:0]m00_couplers_to_m00_couplers_AWVALID;
wire [0:0]m00_couplers_to_m00_couplers_BREADY;
wire [1:0]m00_couplers_to_m00_couplers_BRESP;
wire [0:0]m00_couplers_to_m00_couplers_BVALID;
wire [31:0]m00_couplers_to_m00_couplers_RDATA;
wire [0:0]m00_couplers_to_m00_couplers_RREADY;
wire [1:0]m00_couplers_to_m00_couplers_RRESP;
wire [0:0]m00_couplers_to_m00_couplers_RVALID;
wire [31:0]m00_couplers_to_m00_couplers_WDATA;
wire [0:0]m00_couplers_to_m00_couplers_WREADY;
wire [3:0]m00_couplers_to_m00_couplers_WSTRB;
wire [0:0]m00_couplers_to_m00_couplers_WVALID;
assign M_AXI_araddr[8:0] = m00_couplers_to_m00_couplers_ARADDR;
assign M_AXI_arvalid[0] = m00_couplers_to_m00_couplers_ARVALID;
assign M_AXI_awaddr[8:0] = m00_couplers_to_m00_couplers_AWADDR;
assign M_AXI_awvalid[0] = m00_couplers_to_m00_couplers_AWVALID;
assign M_AXI_bready[0] = m00_couplers_to_m00_couplers_BREADY;
assign M_AXI_rready[0] = m00_couplers_to_m00_couplers_RREADY;
assign M_AXI_wdata[31:0] = m00_couplers_to_m00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m00_couplers_to_m00_couplers_WSTRB;
assign M_AXI_wvalid[0] = m00_couplers_to_m00_couplers_WVALID;
assign S_AXI_arready[0] = m00_couplers_to_m00_couplers_ARREADY;
assign S_AXI_awready[0] = m00_couplers_to_m00_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m00_couplers_to_m00_couplers_BRESP;
assign S_AXI_bvalid[0] = m00_couplers_to_m00_couplers_BVALID;
assign S_AXI_rdata[31:0] = m00_couplers_to_m00_couplers_RDATA;
assign S_AXI_rresp[1:0] = m00_couplers_to_m00_couplers_RRESP;
assign S_AXI_rvalid[0] = m00_couplers_to_m00_couplers_RVALID;
assign S_AXI_wready[0] = m00_couplers_to_m00_couplers_WREADY;
assign m00_couplers_to_m00_couplers_ARADDR = S_AXI_araddr[8:0];
assign m00_couplers_to_m00_couplers_ARREADY = M_AXI_arready[0];
assign m00_couplers_to_m00_couplers_ARVALID = S_AXI_arvalid[0];
assign m00_couplers_to_m00_couplers_AWADDR = S_AXI_awaddr[8:0];
assign m00_couplers_to_m00_couplers_AWREADY = M_AXI_awready[0];
assign m00_couplers_to_m00_couplers_AWVALID = S_AXI_awvalid[0];
assign m00_couplers_to_m00_couplers_BREADY = S_AXI_bready[0];
assign m00_couplers_to_m00_couplers_BRESP = M_AXI_bresp[1:0];
assign m00_couplers_to_m00_couplers_BVALID = M_AXI_bvalid[0];
assign m00_couplers_to_m00_couplers_RDATA = M_AXI_rdata[31:0];
assign m00_couplers_to_m00_couplers_RREADY = S_AXI_rready[0];
assign m00_couplers_to_m00_couplers_RRESP = M_AXI_rresp[1:0];
assign m00_couplers_to_m00_couplers_RVALID = M_AXI_rvalid[0];
assign m00_couplers_to_m00_couplers_WDATA = S_AXI_wdata[31:0];
assign m00_couplers_to_m00_couplers_WREADY = M_AXI_wready[0];
assign m00_couplers_to_m00_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m00_couplers_to_m00_couplers_WVALID = S_AXI_wvalid[0];
endmodule
module m01_couplers_imp_PQKNCJ
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [8:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [8:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [8:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [8:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire [8:0]m01_couplers_to_m01_couplers_ARADDR;
wire m01_couplers_to_m01_couplers_ARREADY;
wire m01_couplers_to_m01_couplers_ARVALID;
wire [8:0]m01_couplers_to_m01_couplers_AWADDR;
wire m01_couplers_to_m01_couplers_AWREADY;
wire m01_couplers_to_m01_couplers_AWVALID;
wire m01_couplers_to_m01_couplers_BREADY;
wire [1:0]m01_couplers_to_m01_couplers_BRESP;
wire m01_couplers_to_m01_couplers_BVALID;
wire [31:0]m01_couplers_to_m01_couplers_RDATA;
wire m01_couplers_to_m01_couplers_RREADY;
wire [1:0]m01_couplers_to_m01_couplers_RRESP;
wire m01_couplers_to_m01_couplers_RVALID;
wire [31:0]m01_couplers_to_m01_couplers_WDATA;
wire m01_couplers_to_m01_couplers_WREADY;
wire [3:0]m01_couplers_to_m01_couplers_WSTRB;
wire m01_couplers_to_m01_couplers_WVALID;
assign M_AXI_araddr[8:0] = m01_couplers_to_m01_couplers_ARADDR;
assign M_AXI_arvalid = m01_couplers_to_m01_couplers_ARVALID;
assign M_AXI_awaddr[8:0] = m01_couplers_to_m01_couplers_AWADDR;
assign M_AXI_awvalid = m01_couplers_to_m01_couplers_AWVALID;
assign M_AXI_bready = m01_couplers_to_m01_couplers_BREADY;
assign M_AXI_rready = m01_couplers_to_m01_couplers_RREADY;
assign M_AXI_wdata[31:0] = m01_couplers_to_m01_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m01_couplers_to_m01_couplers_WSTRB;
assign M_AXI_wvalid = m01_couplers_to_m01_couplers_WVALID;
assign S_AXI_arready = m01_couplers_to_m01_couplers_ARREADY;
assign S_AXI_awready = m01_couplers_to_m01_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m01_couplers_to_m01_couplers_BRESP;
assign S_AXI_bvalid = m01_couplers_to_m01_couplers_BVALID;
assign S_AXI_rdata[31:0] = m01_couplers_to_m01_couplers_RDATA;
assign S_AXI_rresp[1:0] = m01_couplers_to_m01_couplers_RRESP;
assign S_AXI_rvalid = m01_couplers_to_m01_couplers_RVALID;
assign S_AXI_wready = m01_couplers_to_m01_couplers_WREADY;
assign m01_couplers_to_m01_couplers_ARADDR = S_AXI_araddr[8:0];
assign m01_couplers_to_m01_couplers_ARREADY = M_AXI_arready;
assign m01_couplers_to_m01_couplers_ARVALID = S_AXI_arvalid;
assign m01_couplers_to_m01_couplers_AWADDR = S_AXI_awaddr[8:0];
assign m01_couplers_to_m01_couplers_AWREADY = M_AXI_awready;
assign m01_couplers_to_m01_couplers_AWVALID = S_AXI_awvalid;
assign m01_couplers_to_m01_couplers_BREADY = S_AXI_bready;
assign m01_couplers_to_m01_couplers_BRESP = M_AXI_bresp[1:0];
assign m01_couplers_to_m01_couplers_BVALID = M_AXI_bvalid;
assign m01_couplers_to_m01_couplers_RDATA = M_AXI_rdata[31:0];
assign m01_couplers_to_m01_couplers_RREADY = S_AXI_rready;
assign m01_couplers_to_m01_couplers_RRESP = M_AXI_rresp[1:0];
assign m01_couplers_to_m01_couplers_RVALID = M_AXI_rvalid;
assign m01_couplers_to_m01_couplers_WDATA = S_AXI_wdata[31:0];
assign m01_couplers_to_m01_couplers_WREADY = M_AXI_wready;
assign m01_couplers_to_m01_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m01_couplers_to_m01_couplers_WVALID = S_AXI_wvalid;
endmodule
module m02_couplers_imp_1QFTZ3X
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arready,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awready,
S_AXI_awvalid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [10:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [10:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [10:0]S_AXI_araddr;
output S_AXI_arready;
input S_AXI_arvalid;
input [10:0]S_AXI_awaddr;
output S_AXI_awready;
input S_AXI_awvalid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire [10:0]m02_couplers_to_m02_couplers_ARADDR;
wire m02_couplers_to_m02_couplers_ARREADY;
wire m02_couplers_to_m02_couplers_ARVALID;
wire [10:0]m02_couplers_to_m02_couplers_AWADDR;
wire m02_couplers_to_m02_couplers_AWREADY;
wire m02_couplers_to_m02_couplers_AWVALID;
wire m02_couplers_to_m02_couplers_BREADY;
wire [1:0]m02_couplers_to_m02_couplers_BRESP;
wire m02_couplers_to_m02_couplers_BVALID;
wire [31:0]m02_couplers_to_m02_couplers_RDATA;
wire m02_couplers_to_m02_couplers_RREADY;
wire [1:0]m02_couplers_to_m02_couplers_RRESP;
wire m02_couplers_to_m02_couplers_RVALID;
wire [31:0]m02_couplers_to_m02_couplers_WDATA;
wire m02_couplers_to_m02_couplers_WREADY;
wire [3:0]m02_couplers_to_m02_couplers_WSTRB;
wire m02_couplers_to_m02_couplers_WVALID;
assign M_AXI_araddr[10:0] = m02_couplers_to_m02_couplers_ARADDR;
assign M_AXI_arvalid = m02_couplers_to_m02_couplers_ARVALID;
assign M_AXI_awaddr[10:0] = m02_couplers_to_m02_couplers_AWADDR;
assign M_AXI_awvalid = m02_couplers_to_m02_couplers_AWVALID;
assign M_AXI_bready = m02_couplers_to_m02_couplers_BREADY;
assign M_AXI_rready = m02_couplers_to_m02_couplers_RREADY;
assign M_AXI_wdata[31:0] = m02_couplers_to_m02_couplers_WDATA;
assign M_AXI_wstrb[3:0] = m02_couplers_to_m02_couplers_WSTRB;
assign M_AXI_wvalid = m02_couplers_to_m02_couplers_WVALID;
assign S_AXI_arready = m02_couplers_to_m02_couplers_ARREADY;
assign S_AXI_awready = m02_couplers_to_m02_couplers_AWREADY;
assign S_AXI_bresp[1:0] = m02_couplers_to_m02_couplers_BRESP;
assign S_AXI_bvalid = m02_couplers_to_m02_couplers_BVALID;
assign S_AXI_rdata[31:0] = m02_couplers_to_m02_couplers_RDATA;
assign S_AXI_rresp[1:0] = m02_couplers_to_m02_couplers_RRESP;
assign S_AXI_rvalid = m02_couplers_to_m02_couplers_RVALID;
assign S_AXI_wready = m02_couplers_to_m02_couplers_WREADY;
assign m02_couplers_to_m02_couplers_ARADDR = S_AXI_araddr[10:0];
assign m02_couplers_to_m02_couplers_ARREADY = M_AXI_arready;
assign m02_couplers_to_m02_couplers_ARVALID = S_AXI_arvalid;
assign m02_couplers_to_m02_couplers_AWADDR = S_AXI_awaddr[10:0];
assign m02_couplers_to_m02_couplers_AWREADY = M_AXI_awready;
assign m02_couplers_to_m02_couplers_AWVALID = S_AXI_awvalid;
assign m02_couplers_to_m02_couplers_BREADY = S_AXI_bready;
assign m02_couplers_to_m02_couplers_BRESP = M_AXI_bresp[1:0];
assign m02_couplers_to_m02_couplers_BVALID = M_AXI_bvalid;
assign m02_couplers_to_m02_couplers_RDATA = M_AXI_rdata[31:0];
assign m02_couplers_to_m02_couplers_RREADY = S_AXI_rready;
assign m02_couplers_to_m02_couplers_RRESP = M_AXI_rresp[1:0];
assign m02_couplers_to_m02_couplers_RVALID = M_AXI_rvalid;
assign m02_couplers_to_m02_couplers_WDATA = S_AXI_wdata[31:0];
assign m02_couplers_to_m02_couplers_WREADY = M_AXI_wready;
assign m02_couplers_to_m02_couplers_WSTRB = S_AXI_wstrb[3:0];
assign m02_couplers_to_m02_couplers_WVALID = S_AXI_wvalid;
endmodule
module s00_couplers_imp_1AHKP6S
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
cpu_auto_pc_1 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
module s00_couplers_imp_B67PN0
(M_ACLK,
M_ARESETN,
M_AXI_araddr,
M_AXI_arprot,
M_AXI_arready,
M_AXI_arvalid,
M_AXI_awaddr,
M_AXI_awprot,
M_AXI_awready,
M_AXI_awvalid,
M_AXI_bready,
M_AXI_bresp,
M_AXI_bvalid,
M_AXI_rdata,
M_AXI_rready,
M_AXI_rresp,
M_AXI_rvalid,
M_AXI_wdata,
M_AXI_wready,
M_AXI_wstrb,
M_AXI_wvalid,
S_ACLK,
S_ARESETN,
S_AXI_araddr,
S_AXI_arburst,
S_AXI_arcache,
S_AXI_arid,
S_AXI_arlen,
S_AXI_arlock,
S_AXI_arprot,
S_AXI_arqos,
S_AXI_arready,
S_AXI_arsize,
S_AXI_arvalid,
S_AXI_awaddr,
S_AXI_awburst,
S_AXI_awcache,
S_AXI_awid,
S_AXI_awlen,
S_AXI_awlock,
S_AXI_awprot,
S_AXI_awqos,
S_AXI_awready,
S_AXI_awsize,
S_AXI_awvalid,
S_AXI_bid,
S_AXI_bready,
S_AXI_bresp,
S_AXI_bvalid,
S_AXI_rdata,
S_AXI_rid,
S_AXI_rlast,
S_AXI_rready,
S_AXI_rresp,
S_AXI_rvalid,
S_AXI_wdata,
S_AXI_wid,
S_AXI_wlast,
S_AXI_wready,
S_AXI_wstrb,
S_AXI_wvalid);
input M_ACLK;
input [0:0]M_ARESETN;
output [31:0]M_AXI_araddr;
output [2:0]M_AXI_arprot;
input M_AXI_arready;
output M_AXI_arvalid;
output [31:0]M_AXI_awaddr;
output [2:0]M_AXI_awprot;
input M_AXI_awready;
output M_AXI_awvalid;
output M_AXI_bready;
input [1:0]M_AXI_bresp;
input M_AXI_bvalid;
input [31:0]M_AXI_rdata;
output M_AXI_rready;
input [1:0]M_AXI_rresp;
input M_AXI_rvalid;
output [31:0]M_AXI_wdata;
input M_AXI_wready;
output [3:0]M_AXI_wstrb;
output M_AXI_wvalid;
input S_ACLK;
input [0:0]S_ARESETN;
input [31:0]S_AXI_araddr;
input [1:0]S_AXI_arburst;
input [3:0]S_AXI_arcache;
input [11:0]S_AXI_arid;
input [3:0]S_AXI_arlen;
input [1:0]S_AXI_arlock;
input [2:0]S_AXI_arprot;
input [3:0]S_AXI_arqos;
output S_AXI_arready;
input [2:0]S_AXI_arsize;
input S_AXI_arvalid;
input [31:0]S_AXI_awaddr;
input [1:0]S_AXI_awburst;
input [3:0]S_AXI_awcache;
input [11:0]S_AXI_awid;
input [3:0]S_AXI_awlen;
input [1:0]S_AXI_awlock;
input [2:0]S_AXI_awprot;
input [3:0]S_AXI_awqos;
output S_AXI_awready;
input [2:0]S_AXI_awsize;
input S_AXI_awvalid;
output [11:0]S_AXI_bid;
input S_AXI_bready;
output [1:0]S_AXI_bresp;
output S_AXI_bvalid;
output [31:0]S_AXI_rdata;
output [11:0]S_AXI_rid;
output S_AXI_rlast;
input S_AXI_rready;
output [1:0]S_AXI_rresp;
output S_AXI_rvalid;
input [31:0]S_AXI_wdata;
input [11:0]S_AXI_wid;
input S_AXI_wlast;
output S_AXI_wready;
input [3:0]S_AXI_wstrb;
input S_AXI_wvalid;
wire S_ACLK_1;
wire [0:0]S_ARESETN_1;
wire [31:0]auto_pc_to_s00_couplers_ARADDR;
wire [2:0]auto_pc_to_s00_couplers_ARPROT;
wire auto_pc_to_s00_couplers_ARREADY;
wire auto_pc_to_s00_couplers_ARVALID;
wire [31:0]auto_pc_to_s00_couplers_AWADDR;
wire [2:0]auto_pc_to_s00_couplers_AWPROT;
wire auto_pc_to_s00_couplers_AWREADY;
wire auto_pc_to_s00_couplers_AWVALID;
wire auto_pc_to_s00_couplers_BREADY;
wire [1:0]auto_pc_to_s00_couplers_BRESP;
wire auto_pc_to_s00_couplers_BVALID;
wire [31:0]auto_pc_to_s00_couplers_RDATA;
wire auto_pc_to_s00_couplers_RREADY;
wire [1:0]auto_pc_to_s00_couplers_RRESP;
wire auto_pc_to_s00_couplers_RVALID;
wire [31:0]auto_pc_to_s00_couplers_WDATA;
wire auto_pc_to_s00_couplers_WREADY;
wire [3:0]auto_pc_to_s00_couplers_WSTRB;
wire auto_pc_to_s00_couplers_WVALID;
wire [31:0]s00_couplers_to_auto_pc_ARADDR;
wire [1:0]s00_couplers_to_auto_pc_ARBURST;
wire [3:0]s00_couplers_to_auto_pc_ARCACHE;
wire [11:0]s00_couplers_to_auto_pc_ARID;
wire [3:0]s00_couplers_to_auto_pc_ARLEN;
wire [1:0]s00_couplers_to_auto_pc_ARLOCK;
wire [2:0]s00_couplers_to_auto_pc_ARPROT;
wire [3:0]s00_couplers_to_auto_pc_ARQOS;
wire s00_couplers_to_auto_pc_ARREADY;
wire [2:0]s00_couplers_to_auto_pc_ARSIZE;
wire s00_couplers_to_auto_pc_ARVALID;
wire [31:0]s00_couplers_to_auto_pc_AWADDR;
wire [1:0]s00_couplers_to_auto_pc_AWBURST;
wire [3:0]s00_couplers_to_auto_pc_AWCACHE;
wire [11:0]s00_couplers_to_auto_pc_AWID;
wire [3:0]s00_couplers_to_auto_pc_AWLEN;
wire [1:0]s00_couplers_to_auto_pc_AWLOCK;
wire [2:0]s00_couplers_to_auto_pc_AWPROT;
wire [3:0]s00_couplers_to_auto_pc_AWQOS;
wire s00_couplers_to_auto_pc_AWREADY;
wire [2:0]s00_couplers_to_auto_pc_AWSIZE;
wire s00_couplers_to_auto_pc_AWVALID;
wire [11:0]s00_couplers_to_auto_pc_BID;
wire s00_couplers_to_auto_pc_BREADY;
wire [1:0]s00_couplers_to_auto_pc_BRESP;
wire s00_couplers_to_auto_pc_BVALID;
wire [31:0]s00_couplers_to_auto_pc_RDATA;
wire [11:0]s00_couplers_to_auto_pc_RID;
wire s00_couplers_to_auto_pc_RLAST;
wire s00_couplers_to_auto_pc_RREADY;
wire [1:0]s00_couplers_to_auto_pc_RRESP;
wire s00_couplers_to_auto_pc_RVALID;
wire [31:0]s00_couplers_to_auto_pc_WDATA;
wire [11:0]s00_couplers_to_auto_pc_WID;
wire s00_couplers_to_auto_pc_WLAST;
wire s00_couplers_to_auto_pc_WREADY;
wire [3:0]s00_couplers_to_auto_pc_WSTRB;
wire s00_couplers_to_auto_pc_WVALID;
assign M_AXI_araddr[31:0] = auto_pc_to_s00_couplers_ARADDR;
assign M_AXI_arprot[2:0] = auto_pc_to_s00_couplers_ARPROT;
assign M_AXI_arvalid = auto_pc_to_s00_couplers_ARVALID;
assign M_AXI_awaddr[31:0] = auto_pc_to_s00_couplers_AWADDR;
assign M_AXI_awprot[2:0] = auto_pc_to_s00_couplers_AWPROT;
assign M_AXI_awvalid = auto_pc_to_s00_couplers_AWVALID;
assign M_AXI_bready = auto_pc_to_s00_couplers_BREADY;
assign M_AXI_rready = auto_pc_to_s00_couplers_RREADY;
assign M_AXI_wdata[31:0] = auto_pc_to_s00_couplers_WDATA;
assign M_AXI_wstrb[3:0] = auto_pc_to_s00_couplers_WSTRB;
assign M_AXI_wvalid = auto_pc_to_s00_couplers_WVALID;
assign S_ACLK_1 = S_ACLK;
assign S_ARESETN_1 = S_ARESETN[0];
assign S_AXI_arready = s00_couplers_to_auto_pc_ARREADY;
assign S_AXI_awready = s00_couplers_to_auto_pc_AWREADY;
assign S_AXI_bid[11:0] = s00_couplers_to_auto_pc_BID;
assign S_AXI_bresp[1:0] = s00_couplers_to_auto_pc_BRESP;
assign S_AXI_bvalid = s00_couplers_to_auto_pc_BVALID;
assign S_AXI_rdata[31:0] = s00_couplers_to_auto_pc_RDATA;
assign S_AXI_rid[11:0] = s00_couplers_to_auto_pc_RID;
assign S_AXI_rlast = s00_couplers_to_auto_pc_RLAST;
assign S_AXI_rresp[1:0] = s00_couplers_to_auto_pc_RRESP;
assign S_AXI_rvalid = s00_couplers_to_auto_pc_RVALID;
assign S_AXI_wready = s00_couplers_to_auto_pc_WREADY;
assign auto_pc_to_s00_couplers_ARREADY = M_AXI_arready;
assign auto_pc_to_s00_couplers_AWREADY = M_AXI_awready;
assign auto_pc_to_s00_couplers_BRESP = M_AXI_bresp[1:0];
assign auto_pc_to_s00_couplers_BVALID = M_AXI_bvalid;
assign auto_pc_to_s00_couplers_RDATA = M_AXI_rdata[31:0];
assign auto_pc_to_s00_couplers_RRESP = M_AXI_rresp[1:0];
assign auto_pc_to_s00_couplers_RVALID = M_AXI_rvalid;
assign auto_pc_to_s00_couplers_WREADY = M_AXI_wready;
assign s00_couplers_to_auto_pc_ARADDR = S_AXI_araddr[31:0];
assign s00_couplers_to_auto_pc_ARBURST = S_AXI_arburst[1:0];
assign s00_couplers_to_auto_pc_ARCACHE = S_AXI_arcache[3:0];
assign s00_couplers_to_auto_pc_ARID = S_AXI_arid[11:0];
assign s00_couplers_to_auto_pc_ARLEN = S_AXI_arlen[3:0];
assign s00_couplers_to_auto_pc_ARLOCK = S_AXI_arlock[1:0];
assign s00_couplers_to_auto_pc_ARPROT = S_AXI_arprot[2:0];
assign s00_couplers_to_auto_pc_ARQOS = S_AXI_arqos[3:0];
assign s00_couplers_to_auto_pc_ARSIZE = S_AXI_arsize[2:0];
assign s00_couplers_to_auto_pc_ARVALID = S_AXI_arvalid;
assign s00_couplers_to_auto_pc_AWADDR = S_AXI_awaddr[31:0];
assign s00_couplers_to_auto_pc_AWBURST = S_AXI_awburst[1:0];
assign s00_couplers_to_auto_pc_AWCACHE = S_AXI_awcache[3:0];
assign s00_couplers_to_auto_pc_AWID = S_AXI_awid[11:0];
assign s00_couplers_to_auto_pc_AWLEN = S_AXI_awlen[3:0];
assign s00_couplers_to_auto_pc_AWLOCK = S_AXI_awlock[1:0];
assign s00_couplers_to_auto_pc_AWPROT = S_AXI_awprot[2:0];
assign s00_couplers_to_auto_pc_AWQOS = S_AXI_awqos[3:0];
assign s00_couplers_to_auto_pc_AWSIZE = S_AXI_awsize[2:0];
assign s00_couplers_to_auto_pc_AWVALID = S_AXI_awvalid;
assign s00_couplers_to_auto_pc_BREADY = S_AXI_bready;
assign s00_couplers_to_auto_pc_RREADY = S_AXI_rready;
assign s00_couplers_to_auto_pc_WDATA = S_AXI_wdata[31:0];
assign s00_couplers_to_auto_pc_WID = S_AXI_wid[11:0];
assign s00_couplers_to_auto_pc_WLAST = S_AXI_wlast;
assign s00_couplers_to_auto_pc_WSTRB = S_AXI_wstrb[3:0];
assign s00_couplers_to_auto_pc_WVALID = S_AXI_wvalid;
cpu_auto_pc_0 auto_pc
(.aclk(S_ACLK_1),
.aresetn(S_ARESETN_1),
.m_axi_araddr(auto_pc_to_s00_couplers_ARADDR),
.m_axi_arprot(auto_pc_to_s00_couplers_ARPROT),
.m_axi_arready(auto_pc_to_s00_couplers_ARREADY),
.m_axi_arvalid(auto_pc_to_s00_couplers_ARVALID),
.m_axi_awaddr(auto_pc_to_s00_couplers_AWADDR),
.m_axi_awprot(auto_pc_to_s00_couplers_AWPROT),
.m_axi_awready(auto_pc_to_s00_couplers_AWREADY),
.m_axi_awvalid(auto_pc_to_s00_couplers_AWVALID),
.m_axi_bready(auto_pc_to_s00_couplers_BREADY),
.m_axi_bresp(auto_pc_to_s00_couplers_BRESP),
.m_axi_bvalid(auto_pc_to_s00_couplers_BVALID),
.m_axi_rdata(auto_pc_to_s00_couplers_RDATA),
.m_axi_rready(auto_pc_to_s00_couplers_RREADY),
.m_axi_rresp(auto_pc_to_s00_couplers_RRESP),
.m_axi_rvalid(auto_pc_to_s00_couplers_RVALID),
.m_axi_wdata(auto_pc_to_s00_couplers_WDATA),
.m_axi_wready(auto_pc_to_s00_couplers_WREADY),
.m_axi_wstrb(auto_pc_to_s00_couplers_WSTRB),
.m_axi_wvalid(auto_pc_to_s00_couplers_WVALID),
.s_axi_araddr(s00_couplers_to_auto_pc_ARADDR),
.s_axi_arburst(s00_couplers_to_auto_pc_ARBURST),
.s_axi_arcache(s00_couplers_to_auto_pc_ARCACHE),
.s_axi_arid(s00_couplers_to_auto_pc_ARID),
.s_axi_arlen(s00_couplers_to_auto_pc_ARLEN),
.s_axi_arlock(s00_couplers_to_auto_pc_ARLOCK),
.s_axi_arprot(s00_couplers_to_auto_pc_ARPROT),
.s_axi_arqos(s00_couplers_to_auto_pc_ARQOS),
.s_axi_arready(s00_couplers_to_auto_pc_ARREADY),
.s_axi_arsize(s00_couplers_to_auto_pc_ARSIZE),
.s_axi_arvalid(s00_couplers_to_auto_pc_ARVALID),
.s_axi_awaddr(s00_couplers_to_auto_pc_AWADDR),
.s_axi_awburst(s00_couplers_to_auto_pc_AWBURST),
.s_axi_awcache(s00_couplers_to_auto_pc_AWCACHE),
.s_axi_awid(s00_couplers_to_auto_pc_AWID),
.s_axi_awlen(s00_couplers_to_auto_pc_AWLEN),
.s_axi_awlock(s00_couplers_to_auto_pc_AWLOCK),
.s_axi_awprot(s00_couplers_to_auto_pc_AWPROT),
.s_axi_awqos(s00_couplers_to_auto_pc_AWQOS),
.s_axi_awready(s00_couplers_to_auto_pc_AWREADY),
.s_axi_awsize(s00_couplers_to_auto_pc_AWSIZE),
.s_axi_awvalid(s00_couplers_to_auto_pc_AWVALID),
.s_axi_bid(s00_couplers_to_auto_pc_BID),
.s_axi_bready(s00_couplers_to_auto_pc_BREADY),
.s_axi_bresp(s00_couplers_to_auto_pc_BRESP),
.s_axi_bvalid(s00_couplers_to_auto_pc_BVALID),
.s_axi_rdata(s00_couplers_to_auto_pc_RDATA),
.s_axi_rid(s00_couplers_to_auto_pc_RID),
.s_axi_rlast(s00_couplers_to_auto_pc_RLAST),
.s_axi_rready(s00_couplers_to_auto_pc_RREADY),
.s_axi_rresp(s00_couplers_to_auto_pc_RRESP),
.s_axi_rvalid(s00_couplers_to_auto_pc_RVALID),
.s_axi_wdata(s00_couplers_to_auto_pc_WDATA),
.s_axi_wid(s00_couplers_to_auto_pc_WID),
.s_axi_wlast(s00_couplers_to_auto_pc_WLAST),
.s_axi_wready(s00_couplers_to_auto_pc_WREADY),
.s_axi_wstrb(s00_couplers_to_auto_pc_WSTRB),
.s_axi_wvalid(s00_couplers_to_auto_pc_WVALID));
endmodule
|
/*
Copyright (c) 2014-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100MHz
* Reset: Push button, active low
*/
input wire clk,
input wire reset_n,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 9600 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// Clock and reset
wire clk_ibufg;
wire clk_bufg;
wire clk_mmcm_out;
// Internal 125 MHz clock
wire clk_int;
wire rst_int;
wire mmcm_rst = ~reset_n;
wire mmcm_locked;
wire mmcm_clkfb;
IBUFG
clk_ibufg_inst(
.I(clk),
.O(clk_ibufg)
);
// MMCM instance
// 100 MHz in, 125 MHz out
// PFD range: 10 MHz to 550 MHz
// VCO range: 600 MHz to 1200 MHz
// M = 10, D = 1 sets Fvco = 1000 MHz (in range)
// Divide by 8 to get output frequency of 125 MHz
MMCME2_BASE #(
.BANDWIDTH("OPTIMIZED"),
.CLKOUT0_DIVIDE_F(8),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0),
.CLKOUT2_DIVIDE(5),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.5),
.CLKOUT6_PHASE(0),
.CLKFBOUT_MULT_F(10),
.CLKFBOUT_PHASE(0),
.DIVCLK_DIVIDE(1),
.REF_JITTER1(0.010),
.CLKIN1_PERIOD(10.0),
.STARTUP_WAIT("FALSE"),
.CLKOUT4_CASCADE("FALSE")
)
clk_mmcm_inst (
.CLKIN1(clk_ibufg),
.CLKFBIN(mmcm_clkfb),
.RST(mmcm_rst),
.PWRDWN(1'b0),
.CLKOUT0(clk_mmcm_out),
.CLKOUT0B(),
.CLKOUT1(),
.CLKOUT1B(),
.CLKOUT2(),
.CLKOUT2B(),
.CLKOUT3(),
.CLKOUT3B(),
.CLKOUT4(),
.CLKOUT5(),
.CLKOUT6(),
.CLKFBOUT(mmcm_clkfb),
.CLKFBOUTB(),
.LOCKED(mmcm_locked)
);
BUFG
clk_bufg_inst (
.I(clk_mmcm_out),
.O(clk_int)
);
sync_reset #(
.N(4)
)
sync_reset_inst (
.clk(clk_int),
.rst(~mmcm_locked),
.sync_reset_out(rst_int)
);
// GPIO
wire btnu_int;
wire btnl_int;
wire btnd_int;
wire btnr_int;
wire btnc_int;
wire [7:0] sw_int;
debounce_switch #(
.WIDTH(13),
.N(4),
.RATE(125000)
)
debounce_switch_inst (
.clk(clk_int),
.rst(rst_int),
.in({btnu,
btnl,
btnd,
btnr,
btnc,
sw}),
.out({btnu_int,
btnl_int,
btnd_int,
btnr_int,
btnc_int,
sw_int})
);
sync_signal #(
.WIDTH(1),
.N(2)
)
sync_signal_inst (
.clk(clk_int),
.in({uart_rxd}),
.out({uart_rxd_int})
);
fpga_core
core_inst (
/*
* Clock: 125MHz
* Synchronous reset
*/
.clk(clk_int),
.rst(rst_int),
/*
* GPIO
*/
.btnu(btnu_int),
.btnl(btnl_int),
.btnd(btnd_int),
.btnr(btnr_int),
.btnc(btnc_int),
.sw(sw_int),
.led(led),
/*
* UART: 9600 bps, 8N1
*/
.uart_rxd(uart_rxd_int),
.uart_txd(uart_txd)
);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="hls_contrast_stretch,hls_ip_2017_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg400-1,HLS_INPUT_CLOCK=6.670000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=6.380000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=9,HLS_SYN_FF=3094,HLS_SYN_LUT=4583}" *)
module hls_contrast_stretch (
s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP,
ap_clk,
ap_rst_n,
stream_in_TDATA,
stream_in_TKEEP,
stream_in_TSTRB,
stream_in_TUSER,
stream_in_TLAST,
stream_in_TID,
stream_in_TDEST,
stream_out_TDATA,
stream_out_TKEEP,
stream_out_TSTRB,
stream_out_TUSER,
stream_out_TLAST,
stream_out_TID,
stream_out_TDEST,
stream_in_TVALID,
stream_in_TREADY,
stream_out_TVALID,
stream_out_TREADY
);
parameter C_S_AXI_AXILITES_DATA_WIDTH = 32;
parameter C_S_AXI_AXILITES_ADDR_WIDTH = 6;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter C_S_AXI_ADDR_WIDTH = 32;
parameter C_S_AXI_AXILITES_WSTRB_WIDTH = (32 / 8);
parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1:0] s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
input [C_S_AXI_AXILITES_DATA_WIDTH - 1:0] s_axi_AXILiteS_WDATA;
input [C_S_AXI_AXILITES_WSTRB_WIDTH - 1:0] s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1:0] s_axi_AXILiteS_ARADDR;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
output [C_S_AXI_AXILITES_DATA_WIDTH - 1:0] s_axi_AXILiteS_RDATA;
output [1:0] s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
output [1:0] s_axi_AXILiteS_BRESP;
input ap_clk;
input ap_rst_n;
input [23:0] stream_in_TDATA;
input [2:0] stream_in_TKEEP;
input [2:0] stream_in_TSTRB;
input [0:0] stream_in_TUSER;
input [0:0] stream_in_TLAST;
input [0:0] stream_in_TID;
input [0:0] stream_in_TDEST;
output [23:0] stream_out_TDATA;
output [2:0] stream_out_TKEEP;
output [2:0] stream_out_TSTRB;
output [0:0] stream_out_TUSER;
output [0:0] stream_out_TLAST;
output [0:0] stream_out_TID;
output [0:0] stream_out_TDEST;
input stream_in_TVALID;
output stream_in_TREADY;
output stream_out_TVALID;
input stream_out_TREADY;
reg ap_rst_n_inv;
wire [15:0] height;
wire [15:0] width;
wire [7:0] min;
wire [7:0] max;
wire Block_Mat_exit1573_p_U0_ap_start;
wire Block_Mat_exit1573_p_U0_start_full_n;
wire Block_Mat_exit1573_p_U0_ap_done;
wire Block_Mat_exit1573_p_U0_ap_continue;
wire Block_Mat_exit1573_p_U0_ap_idle;
wire Block_Mat_exit1573_p_U0_ap_ready;
wire Block_Mat_exit1573_p_U0_start_out;
wire Block_Mat_exit1573_p_U0_start_write;
wire [7:0] Block_Mat_exit1573_p_U0_min_out_din;
wire Block_Mat_exit1573_p_U0_min_out_write;
wire [15:0] Block_Mat_exit1573_p_U0_img0_rows_V_out_din;
wire Block_Mat_exit1573_p_U0_img0_rows_V_out_write;
wire [15:0] Block_Mat_exit1573_p_U0_img0_cols_V_out_din;
wire Block_Mat_exit1573_p_U0_img0_cols_V_out_write;
wire [15:0] Block_Mat_exit1573_p_U0_img2_rows_V_out_din;
wire Block_Mat_exit1573_p_U0_img2_rows_V_out_write;
wire [15:0] Block_Mat_exit1573_p_U0_img2_cols_V_out_din;
wire Block_Mat_exit1573_p_U0_img2_cols_V_out_write;
wire [15:0] Block_Mat_exit1573_p_U0_img3_rows_V_out_din;
wire Block_Mat_exit1573_p_U0_img3_rows_V_out_write;
wire [15:0] Block_Mat_exit1573_p_U0_img3_cols_V_out_din;
wire Block_Mat_exit1573_p_U0_img3_cols_V_out_write;
wire [11:0] Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_din;
wire Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_write;
wire [11:0] Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_din;
wire Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_write;
wire [7:0] Block_Mat_exit1573_p_U0_tmp_3_cast_out_out_din;
wire Block_Mat_exit1573_p_U0_tmp_3_cast_out_out_write;
wire [7:0] Block_Mat_exit1573_p_U0_max_out_din;
wire Block_Mat_exit1573_p_U0_max_out_write;
wire AXIvideo2Mat_U0_ap_start;
wire AXIvideo2Mat_U0_ap_done;
wire AXIvideo2Mat_U0_ap_continue;
wire AXIvideo2Mat_U0_ap_idle;
wire AXIvideo2Mat_U0_ap_ready;
wire AXIvideo2Mat_U0_start_out;
wire AXIvideo2Mat_U0_start_write;
wire AXIvideo2Mat_U0_stream_in_TREADY;
wire AXIvideo2Mat_U0_img_rows_V_read;
wire AXIvideo2Mat_U0_img_cols_V_read;
wire [7:0] AXIvideo2Mat_U0_img_data_stream_0_V_din;
wire AXIvideo2Mat_U0_img_data_stream_0_V_write;
wire [7:0] AXIvideo2Mat_U0_img_data_stream_1_V_din;
wire AXIvideo2Mat_U0_img_data_stream_1_V_write;
wire [7:0] AXIvideo2Mat_U0_img_data_stream_2_V_din;
wire AXIvideo2Mat_U0_img_data_stream_2_V_write;
wire [15:0] AXIvideo2Mat_U0_img_rows_V_out_din;
wire AXIvideo2Mat_U0_img_rows_V_out_write;
wire [15:0] AXIvideo2Mat_U0_img_cols_V_out_din;
wire AXIvideo2Mat_U0_img_cols_V_out_write;
wire CvtColor_1_U0_ap_start;
wire CvtColor_1_U0_ap_done;
wire CvtColor_1_U0_ap_continue;
wire CvtColor_1_U0_ap_idle;
wire CvtColor_1_U0_ap_ready;
wire CvtColor_1_U0_p_src_rows_V_read;
wire CvtColor_1_U0_p_src_cols_V_read;
wire CvtColor_1_U0_p_src_data_stream_0_V_read;
wire CvtColor_1_U0_p_src_data_stream_1_V_read;
wire CvtColor_1_U0_p_src_data_stream_2_V_read;
wire [7:0] CvtColor_1_U0_p_dst_data_stream_0_V_din;
wire CvtColor_1_U0_p_dst_data_stream_0_V_write;
wire [7:0] CvtColor_1_U0_p_dst_data_stream_1_V_din;
wire CvtColor_1_U0_p_dst_data_stream_1_V_write;
wire [7:0] CvtColor_1_U0_p_dst_data_stream_2_V_din;
wire CvtColor_1_U0_p_dst_data_stream_2_V_write;
wire Loop_loop_height_pro_U0_ap_start;
wire Loop_loop_height_pro_U0_ap_done;
wire Loop_loop_height_pro_U0_ap_continue;
wire Loop_loop_height_pro_U0_ap_idle;
wire Loop_loop_height_pro_U0_ap_ready;
wire Loop_loop_height_pro_U0_max_read;
wire Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read;
wire Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read;
wire [7:0] Loop_loop_height_pro_U0_img2_data_stream_0_V_din;
wire Loop_loop_height_pro_U0_img2_data_stream_0_V_write;
wire [7:0] Loop_loop_height_pro_U0_img2_data_stream_1_V_din;
wire Loop_loop_height_pro_U0_img2_data_stream_1_V_write;
wire [7:0] Loop_loop_height_pro_U0_img2_data_stream_2_V_din;
wire Loop_loop_height_pro_U0_img2_data_stream_2_V_write;
wire Loop_loop_height_pro_U0_img1_data_stream_0_V_read;
wire Loop_loop_height_pro_U0_img1_data_stream_1_V_read;
wire Loop_loop_height_pro_U0_img1_data_stream_2_V_read;
wire Loop_loop_height_pro_U0_min_read;
wire Loop_loop_height_pro_U0_tmp_3_cast_loc_read;
wire CvtColor_U0_ap_start;
wire CvtColor_U0_ap_done;
wire CvtColor_U0_ap_continue;
wire CvtColor_U0_ap_idle;
wire CvtColor_U0_ap_ready;
wire CvtColor_U0_p_src_rows_V_read;
wire CvtColor_U0_p_src_cols_V_read;
wire CvtColor_U0_p_src_data_stream_0_V_read;
wire CvtColor_U0_p_src_data_stream_1_V_read;
wire CvtColor_U0_p_src_data_stream_2_V_read;
wire [7:0] CvtColor_U0_p_dst_data_stream_0_V_din;
wire CvtColor_U0_p_dst_data_stream_0_V_write;
wire [7:0] CvtColor_U0_p_dst_data_stream_1_V_din;
wire CvtColor_U0_p_dst_data_stream_1_V_write;
wire [7:0] CvtColor_U0_p_dst_data_stream_2_V_din;
wire CvtColor_U0_p_dst_data_stream_2_V_write;
wire Mat2AXIvideo_U0_ap_start;
wire Mat2AXIvideo_U0_ap_done;
wire Mat2AXIvideo_U0_ap_continue;
wire Mat2AXIvideo_U0_ap_idle;
wire Mat2AXIvideo_U0_ap_ready;
wire Mat2AXIvideo_U0_img_rows_V_read;
wire Mat2AXIvideo_U0_img_cols_V_read;
wire Mat2AXIvideo_U0_img_data_stream_0_V_read;
wire Mat2AXIvideo_U0_img_data_stream_1_V_read;
wire Mat2AXIvideo_U0_img_data_stream_2_V_read;
wire [23:0] Mat2AXIvideo_U0_stream_out_TDATA;
wire Mat2AXIvideo_U0_stream_out_TVALID;
wire [2:0] Mat2AXIvideo_U0_stream_out_TKEEP;
wire [2:0] Mat2AXIvideo_U0_stream_out_TSTRB;
wire [0:0] Mat2AXIvideo_U0_stream_out_TUSER;
wire [0:0] Mat2AXIvideo_U0_stream_out_TLAST;
wire [0:0] Mat2AXIvideo_U0_stream_out_TID;
wire [0:0] Mat2AXIvideo_U0_stream_out_TDEST;
wire ap_sync_continue;
wire min_c_full_n;
wire [7:0] min_c_dout;
wire min_c_empty_n;
wire img0_rows_V_c_full_n;
wire [15:0] img0_rows_V_c_dout;
wire img0_rows_V_c_empty_n;
wire img0_cols_V_c_full_n;
wire [15:0] img0_cols_V_c_dout;
wire img0_cols_V_c_empty_n;
wire img2_rows_V_c_full_n;
wire [15:0] img2_rows_V_c_dout;
wire img2_rows_V_c_empty_n;
wire img2_cols_V_c_full_n;
wire [15:0] img2_cols_V_c_dout;
wire img2_cols_V_c_empty_n;
wire img3_rows_V_c_full_n;
wire [15:0] img3_rows_V_c_dout;
wire img3_rows_V_c_empty_n;
wire img3_cols_V_c_full_n;
wire [15:0] img3_cols_V_c_dout;
wire img3_cols_V_c_empty_n;
wire p_cols_assign_cast_lo_full_n;
wire [11:0] p_cols_assign_cast_lo_dout;
wire p_cols_assign_cast_lo_empty_n;
wire p_rows_assign_cast_lo_full_n;
wire [11:0] p_rows_assign_cast_lo_dout;
wire p_rows_assign_cast_lo_empty_n;
wire tmp_3_cast_loc_c_full_n;
wire [7:0] tmp_3_cast_loc_c_dout;
wire tmp_3_cast_loc_c_empty_n;
wire max_c_full_n;
wire [7:0] max_c_dout;
wire max_c_empty_n;
wire img0_data_stream_0_s_full_n;
wire [7:0] img0_data_stream_0_s_dout;
wire img0_data_stream_0_s_empty_n;
wire img0_data_stream_1_s_full_n;
wire [7:0] img0_data_stream_1_s_dout;
wire img0_data_stream_1_s_empty_n;
wire img0_data_stream_2_s_full_n;
wire [7:0] img0_data_stream_2_s_dout;
wire img0_data_stream_2_s_empty_n;
wire img0_rows_V_c83_full_n;
wire [15:0] img0_rows_V_c83_dout;
wire img0_rows_V_c83_empty_n;
wire img0_cols_V_c84_full_n;
wire [15:0] img0_cols_V_c84_dout;
wire img0_cols_V_c84_empty_n;
wire img1_data_stream_0_s_full_n;
wire [7:0] img1_data_stream_0_s_dout;
wire img1_data_stream_0_s_empty_n;
wire img1_data_stream_1_s_full_n;
wire [7:0] img1_data_stream_1_s_dout;
wire img1_data_stream_1_s_empty_n;
wire img1_data_stream_2_s_full_n;
wire [7:0] img1_data_stream_2_s_dout;
wire img1_data_stream_2_s_empty_n;
wire img2_data_stream_0_s_full_n;
wire [7:0] img2_data_stream_0_s_dout;
wire img2_data_stream_0_s_empty_n;
wire img2_data_stream_1_s_full_n;
wire [7:0] img2_data_stream_1_s_dout;
wire img2_data_stream_1_s_empty_n;
wire img2_data_stream_2_s_full_n;
wire [7:0] img2_data_stream_2_s_dout;
wire img2_data_stream_2_s_empty_n;
wire img3_data_stream_0_s_full_n;
wire [7:0] img3_data_stream_0_s_dout;
wire img3_data_stream_0_s_empty_n;
wire img3_data_stream_1_s_full_n;
wire [7:0] img3_data_stream_1_s_dout;
wire img3_data_stream_1_s_empty_n;
wire img3_data_stream_2_s_full_n;
wire [7:0] img3_data_stream_2_s_dout;
wire img3_data_stream_2_s_empty_n;
wire [0:0] start_for_Loop_loop_height_pro_U0_din;
wire start_for_Loop_loop_height_pro_U0_full_n;
wire [0:0] start_for_Loop_loop_height_pro_U0_dout;
wire start_for_Loop_loop_height_pro_U0_empty_n;
wire [0:0] start_for_CvtColor_U0_din;
wire start_for_CvtColor_U0_full_n;
wire [0:0] start_for_CvtColor_U0_dout;
wire start_for_CvtColor_U0_empty_n;
wire [0:0] start_for_Mat2AXIvideo_U0_din;
wire start_for_Mat2AXIvideo_U0_full_n;
wire [0:0] start_for_Mat2AXIvideo_U0_dout;
wire start_for_Mat2AXIvideo_U0_empty_n;
wire [0:0] start_for_CvtColor_1_U0_din;
wire start_for_CvtColor_1_U0_full_n;
wire [0:0] start_for_CvtColor_1_U0_dout;
wire start_for_CvtColor_1_U0_empty_n;
wire CvtColor_1_U0_start_full_n;
wire CvtColor_1_U0_start_write;
wire Loop_loop_height_pro_U0_start_full_n;
wire Loop_loop_height_pro_U0_start_write;
wire CvtColor_U0_start_full_n;
wire CvtColor_U0_start_write;
wire Mat2AXIvideo_U0_start_full_n;
wire Mat2AXIvideo_U0_start_write;
hls_contrast_stretch_AXILiteS_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_AXILITES_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_AXILITES_DATA_WIDTH ))
hls_contrast_stretch_AXILiteS_s_axi_U(
.AWVALID(s_axi_AXILiteS_AWVALID),
.AWREADY(s_axi_AXILiteS_AWREADY),
.AWADDR(s_axi_AXILiteS_AWADDR),
.WVALID(s_axi_AXILiteS_WVALID),
.WREADY(s_axi_AXILiteS_WREADY),
.WDATA(s_axi_AXILiteS_WDATA),
.WSTRB(s_axi_AXILiteS_WSTRB),
.ARVALID(s_axi_AXILiteS_ARVALID),
.ARREADY(s_axi_AXILiteS_ARREADY),
.ARADDR(s_axi_AXILiteS_ARADDR),
.RVALID(s_axi_AXILiteS_RVALID),
.RREADY(s_axi_AXILiteS_RREADY),
.RDATA(s_axi_AXILiteS_RDATA),
.RRESP(s_axi_AXILiteS_RRESP),
.BVALID(s_axi_AXILiteS_BVALID),
.BREADY(s_axi_AXILiteS_BREADY),
.BRESP(s_axi_AXILiteS_BRESP),
.ACLK(ap_clk),
.ARESET(ap_rst_n_inv),
.ACLK_EN(1'b1),
.height(height),
.width(width),
.min(min),
.max(max)
);
Block_Mat_exit1573_p Block_Mat_exit1573_p_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(Block_Mat_exit1573_p_U0_ap_start),
.start_full_n(Block_Mat_exit1573_p_U0_start_full_n),
.ap_done(Block_Mat_exit1573_p_U0_ap_done),
.ap_continue(Block_Mat_exit1573_p_U0_ap_continue),
.ap_idle(Block_Mat_exit1573_p_U0_ap_idle),
.ap_ready(Block_Mat_exit1573_p_U0_ap_ready),
.start_out(Block_Mat_exit1573_p_U0_start_out),
.start_write(Block_Mat_exit1573_p_U0_start_write),
.height(height),
.width(width),
.min(min),
.max(max),
.min_out_din(Block_Mat_exit1573_p_U0_min_out_din),
.min_out_full_n(min_c_full_n),
.min_out_write(Block_Mat_exit1573_p_U0_min_out_write),
.img0_rows_V_out_din(Block_Mat_exit1573_p_U0_img0_rows_V_out_din),
.img0_rows_V_out_full_n(img0_rows_V_c_full_n),
.img0_rows_V_out_write(Block_Mat_exit1573_p_U0_img0_rows_V_out_write),
.img0_cols_V_out_din(Block_Mat_exit1573_p_U0_img0_cols_V_out_din),
.img0_cols_V_out_full_n(img0_cols_V_c_full_n),
.img0_cols_V_out_write(Block_Mat_exit1573_p_U0_img0_cols_V_out_write),
.img2_rows_V_out_din(Block_Mat_exit1573_p_U0_img2_rows_V_out_din),
.img2_rows_V_out_full_n(img2_rows_V_c_full_n),
.img2_rows_V_out_write(Block_Mat_exit1573_p_U0_img2_rows_V_out_write),
.img2_cols_V_out_din(Block_Mat_exit1573_p_U0_img2_cols_V_out_din),
.img2_cols_V_out_full_n(img2_cols_V_c_full_n),
.img2_cols_V_out_write(Block_Mat_exit1573_p_U0_img2_cols_V_out_write),
.img3_rows_V_out_din(Block_Mat_exit1573_p_U0_img3_rows_V_out_din),
.img3_rows_V_out_full_n(img3_rows_V_c_full_n),
.img3_rows_V_out_write(Block_Mat_exit1573_p_U0_img3_rows_V_out_write),
.img3_cols_V_out_din(Block_Mat_exit1573_p_U0_img3_cols_V_out_din),
.img3_cols_V_out_full_n(img3_cols_V_c_full_n),
.img3_cols_V_out_write(Block_Mat_exit1573_p_U0_img3_cols_V_out_write),
.p_cols_assign_cast_out_out_din(Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_din),
.p_cols_assign_cast_out_out_full_n(p_cols_assign_cast_lo_full_n),
.p_cols_assign_cast_out_out_write(Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_write),
.p_rows_assign_cast_out_out_din(Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_din),
.p_rows_assign_cast_out_out_full_n(p_rows_assign_cast_lo_full_n),
.p_rows_assign_cast_out_out_write(Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_write),
.tmp_3_cast_out_out_din(Block_Mat_exit1573_p_U0_tmp_3_cast_out_out_din),
.tmp_3_cast_out_out_full_n(tmp_3_cast_loc_c_full_n),
.tmp_3_cast_out_out_write(Block_Mat_exit1573_p_U0_tmp_3_cast_out_out_write),
.max_out_din(Block_Mat_exit1573_p_U0_max_out_din),
.max_out_full_n(max_c_full_n),
.max_out_write(Block_Mat_exit1573_p_U0_max_out_write)
);
AXIvideo2Mat AXIvideo2Mat_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(AXIvideo2Mat_U0_ap_start),
.start_full_n(start_for_CvtColor_1_U0_full_n),
.ap_done(AXIvideo2Mat_U0_ap_done),
.ap_continue(AXIvideo2Mat_U0_ap_continue),
.ap_idle(AXIvideo2Mat_U0_ap_idle),
.ap_ready(AXIvideo2Mat_U0_ap_ready),
.start_out(AXIvideo2Mat_U0_start_out),
.start_write(AXIvideo2Mat_U0_start_write),
.stream_in_TDATA(stream_in_TDATA),
.stream_in_TVALID(stream_in_TVALID),
.stream_in_TREADY(AXIvideo2Mat_U0_stream_in_TREADY),
.stream_in_TKEEP(stream_in_TKEEP),
.stream_in_TSTRB(stream_in_TSTRB),
.stream_in_TUSER(stream_in_TUSER),
.stream_in_TLAST(stream_in_TLAST),
.stream_in_TID(stream_in_TID),
.stream_in_TDEST(stream_in_TDEST),
.img_rows_V_dout(img0_rows_V_c_dout),
.img_rows_V_empty_n(img0_rows_V_c_empty_n),
.img_rows_V_read(AXIvideo2Mat_U0_img_rows_V_read),
.img_cols_V_dout(img0_cols_V_c_dout),
.img_cols_V_empty_n(img0_cols_V_c_empty_n),
.img_cols_V_read(AXIvideo2Mat_U0_img_cols_V_read),
.img_data_stream_0_V_din(AXIvideo2Mat_U0_img_data_stream_0_V_din),
.img_data_stream_0_V_full_n(img0_data_stream_0_s_full_n),
.img_data_stream_0_V_write(AXIvideo2Mat_U0_img_data_stream_0_V_write),
.img_data_stream_1_V_din(AXIvideo2Mat_U0_img_data_stream_1_V_din),
.img_data_stream_1_V_full_n(img0_data_stream_1_s_full_n),
.img_data_stream_1_V_write(AXIvideo2Mat_U0_img_data_stream_1_V_write),
.img_data_stream_2_V_din(AXIvideo2Mat_U0_img_data_stream_2_V_din),
.img_data_stream_2_V_full_n(img0_data_stream_2_s_full_n),
.img_data_stream_2_V_write(AXIvideo2Mat_U0_img_data_stream_2_V_write),
.img_rows_V_out_din(AXIvideo2Mat_U0_img_rows_V_out_din),
.img_rows_V_out_full_n(img0_rows_V_c83_full_n),
.img_rows_V_out_write(AXIvideo2Mat_U0_img_rows_V_out_write),
.img_cols_V_out_din(AXIvideo2Mat_U0_img_cols_V_out_din),
.img_cols_V_out_full_n(img0_cols_V_c84_full_n),
.img_cols_V_out_write(AXIvideo2Mat_U0_img_cols_V_out_write)
);
CvtColor_1 CvtColor_1_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(CvtColor_1_U0_ap_start),
.ap_done(CvtColor_1_U0_ap_done),
.ap_continue(CvtColor_1_U0_ap_continue),
.ap_idle(CvtColor_1_U0_ap_idle),
.ap_ready(CvtColor_1_U0_ap_ready),
.p_src_rows_V_dout(img0_rows_V_c83_dout),
.p_src_rows_V_empty_n(img0_rows_V_c83_empty_n),
.p_src_rows_V_read(CvtColor_1_U0_p_src_rows_V_read),
.p_src_cols_V_dout(img0_cols_V_c84_dout),
.p_src_cols_V_empty_n(img0_cols_V_c84_empty_n),
.p_src_cols_V_read(CvtColor_1_U0_p_src_cols_V_read),
.p_src_data_stream_0_V_dout(img0_data_stream_0_s_dout),
.p_src_data_stream_0_V_empty_n(img0_data_stream_0_s_empty_n),
.p_src_data_stream_0_V_read(CvtColor_1_U0_p_src_data_stream_0_V_read),
.p_src_data_stream_1_V_dout(img0_data_stream_1_s_dout),
.p_src_data_stream_1_V_empty_n(img0_data_stream_1_s_empty_n),
.p_src_data_stream_1_V_read(CvtColor_1_U0_p_src_data_stream_1_V_read),
.p_src_data_stream_2_V_dout(img0_data_stream_2_s_dout),
.p_src_data_stream_2_V_empty_n(img0_data_stream_2_s_empty_n),
.p_src_data_stream_2_V_read(CvtColor_1_U0_p_src_data_stream_2_V_read),
.p_dst_data_stream_0_V_din(CvtColor_1_U0_p_dst_data_stream_0_V_din),
.p_dst_data_stream_0_V_full_n(img1_data_stream_0_s_full_n),
.p_dst_data_stream_0_V_write(CvtColor_1_U0_p_dst_data_stream_0_V_write),
.p_dst_data_stream_1_V_din(CvtColor_1_U0_p_dst_data_stream_1_V_din),
.p_dst_data_stream_1_V_full_n(img1_data_stream_1_s_full_n),
.p_dst_data_stream_1_V_write(CvtColor_1_U0_p_dst_data_stream_1_V_write),
.p_dst_data_stream_2_V_din(CvtColor_1_U0_p_dst_data_stream_2_V_din),
.p_dst_data_stream_2_V_full_n(img1_data_stream_2_s_full_n),
.p_dst_data_stream_2_V_write(CvtColor_1_U0_p_dst_data_stream_2_V_write)
);
Loop_loop_height_pro Loop_loop_height_pro_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(Loop_loop_height_pro_U0_ap_start),
.ap_done(Loop_loop_height_pro_U0_ap_done),
.ap_continue(Loop_loop_height_pro_U0_ap_continue),
.ap_idle(Loop_loop_height_pro_U0_ap_idle),
.ap_ready(Loop_loop_height_pro_U0_ap_ready),
.max_dout(max_c_dout),
.max_empty_n(max_c_empty_n),
.max_read(Loop_loop_height_pro_U0_max_read),
.p_rows_assign_cast_loc_dout(p_rows_assign_cast_lo_dout),
.p_rows_assign_cast_loc_empty_n(p_rows_assign_cast_lo_empty_n),
.p_rows_assign_cast_loc_read(Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read),
.p_cols_assign_cast_loc_dout(p_cols_assign_cast_lo_dout),
.p_cols_assign_cast_loc_empty_n(p_cols_assign_cast_lo_empty_n),
.p_cols_assign_cast_loc_read(Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read),
.img2_data_stream_0_V_din(Loop_loop_height_pro_U0_img2_data_stream_0_V_din),
.img2_data_stream_0_V_full_n(img2_data_stream_0_s_full_n),
.img2_data_stream_0_V_write(Loop_loop_height_pro_U0_img2_data_stream_0_V_write),
.img2_data_stream_1_V_din(Loop_loop_height_pro_U0_img2_data_stream_1_V_din),
.img2_data_stream_1_V_full_n(img2_data_stream_1_s_full_n),
.img2_data_stream_1_V_write(Loop_loop_height_pro_U0_img2_data_stream_1_V_write),
.img2_data_stream_2_V_din(Loop_loop_height_pro_U0_img2_data_stream_2_V_din),
.img2_data_stream_2_V_full_n(img2_data_stream_2_s_full_n),
.img2_data_stream_2_V_write(Loop_loop_height_pro_U0_img2_data_stream_2_V_write),
.img1_data_stream_0_V_dout(img1_data_stream_0_s_dout),
.img1_data_stream_0_V_empty_n(img1_data_stream_0_s_empty_n),
.img1_data_stream_0_V_read(Loop_loop_height_pro_U0_img1_data_stream_0_V_read),
.img1_data_stream_1_V_dout(img1_data_stream_1_s_dout),
.img1_data_stream_1_V_empty_n(img1_data_stream_1_s_empty_n),
.img1_data_stream_1_V_read(Loop_loop_height_pro_U0_img1_data_stream_1_V_read),
.img1_data_stream_2_V_dout(img1_data_stream_2_s_dout),
.img1_data_stream_2_V_empty_n(img1_data_stream_2_s_empty_n),
.img1_data_stream_2_V_read(Loop_loop_height_pro_U0_img1_data_stream_2_V_read),
.min_dout(min_c_dout),
.min_empty_n(min_c_empty_n),
.min_read(Loop_loop_height_pro_U0_min_read),
.tmp_3_cast_loc_dout(tmp_3_cast_loc_c_dout),
.tmp_3_cast_loc_empty_n(tmp_3_cast_loc_c_empty_n),
.tmp_3_cast_loc_read(Loop_loop_height_pro_U0_tmp_3_cast_loc_read)
);
CvtColor CvtColor_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(CvtColor_U0_ap_start),
.ap_done(CvtColor_U0_ap_done),
.ap_continue(CvtColor_U0_ap_continue),
.ap_idle(CvtColor_U0_ap_idle),
.ap_ready(CvtColor_U0_ap_ready),
.p_src_rows_V_dout(img2_rows_V_c_dout),
.p_src_rows_V_empty_n(img2_rows_V_c_empty_n),
.p_src_rows_V_read(CvtColor_U0_p_src_rows_V_read),
.p_src_cols_V_dout(img2_cols_V_c_dout),
.p_src_cols_V_empty_n(img2_cols_V_c_empty_n),
.p_src_cols_V_read(CvtColor_U0_p_src_cols_V_read),
.p_src_data_stream_0_V_dout(img2_data_stream_0_s_dout),
.p_src_data_stream_0_V_empty_n(img2_data_stream_0_s_empty_n),
.p_src_data_stream_0_V_read(CvtColor_U0_p_src_data_stream_0_V_read),
.p_src_data_stream_1_V_dout(img2_data_stream_1_s_dout),
.p_src_data_stream_1_V_empty_n(img2_data_stream_1_s_empty_n),
.p_src_data_stream_1_V_read(CvtColor_U0_p_src_data_stream_1_V_read),
.p_src_data_stream_2_V_dout(img2_data_stream_2_s_dout),
.p_src_data_stream_2_V_empty_n(img2_data_stream_2_s_empty_n),
.p_src_data_stream_2_V_read(CvtColor_U0_p_src_data_stream_2_V_read),
.p_dst_data_stream_0_V_din(CvtColor_U0_p_dst_data_stream_0_V_din),
.p_dst_data_stream_0_V_full_n(img3_data_stream_0_s_full_n),
.p_dst_data_stream_0_V_write(CvtColor_U0_p_dst_data_stream_0_V_write),
.p_dst_data_stream_1_V_din(CvtColor_U0_p_dst_data_stream_1_V_din),
.p_dst_data_stream_1_V_full_n(img3_data_stream_1_s_full_n),
.p_dst_data_stream_1_V_write(CvtColor_U0_p_dst_data_stream_1_V_write),
.p_dst_data_stream_2_V_din(CvtColor_U0_p_dst_data_stream_2_V_din),
.p_dst_data_stream_2_V_full_n(img3_data_stream_2_s_full_n),
.p_dst_data_stream_2_V_write(CvtColor_U0_p_dst_data_stream_2_V_write)
);
Mat2AXIvideo Mat2AXIvideo_U0(
.ap_clk(ap_clk),
.ap_rst(ap_rst_n_inv),
.ap_start(Mat2AXIvideo_U0_ap_start),
.ap_done(Mat2AXIvideo_U0_ap_done),
.ap_continue(Mat2AXIvideo_U0_ap_continue),
.ap_idle(Mat2AXIvideo_U0_ap_idle),
.ap_ready(Mat2AXIvideo_U0_ap_ready),
.img_rows_V_dout(img3_rows_V_c_dout),
.img_rows_V_empty_n(img3_rows_V_c_empty_n),
.img_rows_V_read(Mat2AXIvideo_U0_img_rows_V_read),
.img_cols_V_dout(img3_cols_V_c_dout),
.img_cols_V_empty_n(img3_cols_V_c_empty_n),
.img_cols_V_read(Mat2AXIvideo_U0_img_cols_V_read),
.img_data_stream_0_V_dout(img3_data_stream_0_s_dout),
.img_data_stream_0_V_empty_n(img3_data_stream_0_s_empty_n),
.img_data_stream_0_V_read(Mat2AXIvideo_U0_img_data_stream_0_V_read),
.img_data_stream_1_V_dout(img3_data_stream_1_s_dout),
.img_data_stream_1_V_empty_n(img3_data_stream_1_s_empty_n),
.img_data_stream_1_V_read(Mat2AXIvideo_U0_img_data_stream_1_V_read),
.img_data_stream_2_V_dout(img3_data_stream_2_s_dout),
.img_data_stream_2_V_empty_n(img3_data_stream_2_s_empty_n),
.img_data_stream_2_V_read(Mat2AXIvideo_U0_img_data_stream_2_V_read),
.stream_out_TDATA(Mat2AXIvideo_U0_stream_out_TDATA),
.stream_out_TVALID(Mat2AXIvideo_U0_stream_out_TVALID),
.stream_out_TREADY(stream_out_TREADY),
.stream_out_TKEEP(Mat2AXIvideo_U0_stream_out_TKEEP),
.stream_out_TSTRB(Mat2AXIvideo_U0_stream_out_TSTRB),
.stream_out_TUSER(Mat2AXIvideo_U0_stream_out_TUSER),
.stream_out_TLAST(Mat2AXIvideo_U0_stream_out_TLAST),
.stream_out_TID(Mat2AXIvideo_U0_stream_out_TID),
.stream_out_TDEST(Mat2AXIvideo_U0_stream_out_TDEST)
);
fifo_w8_d3_A min_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_min_out_din),
.if_full_n(min_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_min_out_write),
.if_dout(min_c_dout),
.if_empty_n(min_c_empty_n),
.if_read(Loop_loop_height_pro_U0_min_read)
);
fifo_w16_d1_A img0_rows_V_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_img0_rows_V_out_din),
.if_full_n(img0_rows_V_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_img0_rows_V_out_write),
.if_dout(img0_rows_V_c_dout),
.if_empty_n(img0_rows_V_c_empty_n),
.if_read(AXIvideo2Mat_U0_img_rows_V_read)
);
fifo_w16_d1_A img0_cols_V_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_img0_cols_V_out_din),
.if_full_n(img0_cols_V_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_img0_cols_V_out_write),
.if_dout(img0_cols_V_c_dout),
.if_empty_n(img0_cols_V_c_empty_n),
.if_read(AXIvideo2Mat_U0_img_cols_V_read)
);
fifo_w16_d4_A img2_rows_V_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_img2_rows_V_out_din),
.if_full_n(img2_rows_V_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_img2_rows_V_out_write),
.if_dout(img2_rows_V_c_dout),
.if_empty_n(img2_rows_V_c_empty_n),
.if_read(CvtColor_U0_p_src_rows_V_read)
);
fifo_w16_d4_A img2_cols_V_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_img2_cols_V_out_din),
.if_full_n(img2_cols_V_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_img2_cols_V_out_write),
.if_dout(img2_cols_V_c_dout),
.if_empty_n(img2_cols_V_c_empty_n),
.if_read(CvtColor_U0_p_src_cols_V_read)
);
fifo_w16_d5_A img3_rows_V_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_img3_rows_V_out_din),
.if_full_n(img3_rows_V_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_img3_rows_V_out_write),
.if_dout(img3_rows_V_c_dout),
.if_empty_n(img3_rows_V_c_empty_n),
.if_read(Mat2AXIvideo_U0_img_rows_V_read)
);
fifo_w16_d5_A img3_cols_V_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_img3_cols_V_out_din),
.if_full_n(img3_cols_V_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_img3_cols_V_out_write),
.if_dout(img3_cols_V_c_dout),
.if_empty_n(img3_cols_V_c_empty_n),
.if_read(Mat2AXIvideo_U0_img_cols_V_read)
);
fifo_w12_d3_A p_cols_assign_cast_lo_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_din),
.if_full_n(p_cols_assign_cast_lo_full_n),
.if_write(Block_Mat_exit1573_p_U0_p_cols_assign_cast_out_out_write),
.if_dout(p_cols_assign_cast_lo_dout),
.if_empty_n(p_cols_assign_cast_lo_empty_n),
.if_read(Loop_loop_height_pro_U0_p_cols_assign_cast_loc_read)
);
fifo_w12_d3_A p_rows_assign_cast_lo_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_din),
.if_full_n(p_rows_assign_cast_lo_full_n),
.if_write(Block_Mat_exit1573_p_U0_p_rows_assign_cast_out_out_write),
.if_dout(p_rows_assign_cast_lo_dout),
.if_empty_n(p_rows_assign_cast_lo_empty_n),
.if_read(Loop_loop_height_pro_U0_p_rows_assign_cast_loc_read)
);
fifo_w8_d3_A tmp_3_cast_loc_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_tmp_3_cast_out_out_din),
.if_full_n(tmp_3_cast_loc_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_tmp_3_cast_out_out_write),
.if_dout(tmp_3_cast_loc_c_dout),
.if_empty_n(tmp_3_cast_loc_c_empty_n),
.if_read(Loop_loop_height_pro_U0_tmp_3_cast_loc_read)
);
fifo_w8_d3_A max_c_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Block_Mat_exit1573_p_U0_max_out_din),
.if_full_n(max_c_full_n),
.if_write(Block_Mat_exit1573_p_U0_max_out_write),
.if_dout(max_c_dout),
.if_empty_n(max_c_empty_n),
.if_read(Loop_loop_height_pro_U0_max_read)
);
fifo_w8_d1_A img0_data_stream_0_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(AXIvideo2Mat_U0_img_data_stream_0_V_din),
.if_full_n(img0_data_stream_0_s_full_n),
.if_write(AXIvideo2Mat_U0_img_data_stream_0_V_write),
.if_dout(img0_data_stream_0_s_dout),
.if_empty_n(img0_data_stream_0_s_empty_n),
.if_read(CvtColor_1_U0_p_src_data_stream_0_V_read)
);
fifo_w8_d1_A img0_data_stream_1_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(AXIvideo2Mat_U0_img_data_stream_1_V_din),
.if_full_n(img0_data_stream_1_s_full_n),
.if_write(AXIvideo2Mat_U0_img_data_stream_1_V_write),
.if_dout(img0_data_stream_1_s_dout),
.if_empty_n(img0_data_stream_1_s_empty_n),
.if_read(CvtColor_1_U0_p_src_data_stream_1_V_read)
);
fifo_w8_d1_A img0_data_stream_2_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(AXIvideo2Mat_U0_img_data_stream_2_V_din),
.if_full_n(img0_data_stream_2_s_full_n),
.if_write(AXIvideo2Mat_U0_img_data_stream_2_V_write),
.if_dout(img0_data_stream_2_s_dout),
.if_empty_n(img0_data_stream_2_s_empty_n),
.if_read(CvtColor_1_U0_p_src_data_stream_2_V_read)
);
fifo_w16_d1_A img0_rows_V_c83_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(AXIvideo2Mat_U0_img_rows_V_out_din),
.if_full_n(img0_rows_V_c83_full_n),
.if_write(AXIvideo2Mat_U0_img_rows_V_out_write),
.if_dout(img0_rows_V_c83_dout),
.if_empty_n(img0_rows_V_c83_empty_n),
.if_read(CvtColor_1_U0_p_src_rows_V_read)
);
fifo_w16_d1_A img0_cols_V_c84_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(AXIvideo2Mat_U0_img_cols_V_out_din),
.if_full_n(img0_cols_V_c84_full_n),
.if_write(AXIvideo2Mat_U0_img_cols_V_out_write),
.if_dout(img0_cols_V_c84_dout),
.if_empty_n(img0_cols_V_c84_empty_n),
.if_read(CvtColor_1_U0_p_src_cols_V_read)
);
fifo_w8_d1_A img1_data_stream_0_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(CvtColor_1_U0_p_dst_data_stream_0_V_din),
.if_full_n(img1_data_stream_0_s_full_n),
.if_write(CvtColor_1_U0_p_dst_data_stream_0_V_write),
.if_dout(img1_data_stream_0_s_dout),
.if_empty_n(img1_data_stream_0_s_empty_n),
.if_read(Loop_loop_height_pro_U0_img1_data_stream_0_V_read)
);
fifo_w8_d1_A img1_data_stream_1_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(CvtColor_1_U0_p_dst_data_stream_1_V_din),
.if_full_n(img1_data_stream_1_s_full_n),
.if_write(CvtColor_1_U0_p_dst_data_stream_1_V_write),
.if_dout(img1_data_stream_1_s_dout),
.if_empty_n(img1_data_stream_1_s_empty_n),
.if_read(Loop_loop_height_pro_U0_img1_data_stream_1_V_read)
);
fifo_w8_d1_A img1_data_stream_2_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(CvtColor_1_U0_p_dst_data_stream_2_V_din),
.if_full_n(img1_data_stream_2_s_full_n),
.if_write(CvtColor_1_U0_p_dst_data_stream_2_V_write),
.if_dout(img1_data_stream_2_s_dout),
.if_empty_n(img1_data_stream_2_s_empty_n),
.if_read(Loop_loop_height_pro_U0_img1_data_stream_2_V_read)
);
fifo_w8_d1_A img2_data_stream_0_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Loop_loop_height_pro_U0_img2_data_stream_0_V_din),
.if_full_n(img2_data_stream_0_s_full_n),
.if_write(Loop_loop_height_pro_U0_img2_data_stream_0_V_write),
.if_dout(img2_data_stream_0_s_dout),
.if_empty_n(img2_data_stream_0_s_empty_n),
.if_read(CvtColor_U0_p_src_data_stream_0_V_read)
);
fifo_w8_d1_A img2_data_stream_1_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Loop_loop_height_pro_U0_img2_data_stream_1_V_din),
.if_full_n(img2_data_stream_1_s_full_n),
.if_write(Loop_loop_height_pro_U0_img2_data_stream_1_V_write),
.if_dout(img2_data_stream_1_s_dout),
.if_empty_n(img2_data_stream_1_s_empty_n),
.if_read(CvtColor_U0_p_src_data_stream_1_V_read)
);
fifo_w8_d1_A img2_data_stream_2_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(Loop_loop_height_pro_U0_img2_data_stream_2_V_din),
.if_full_n(img2_data_stream_2_s_full_n),
.if_write(Loop_loop_height_pro_U0_img2_data_stream_2_V_write),
.if_dout(img2_data_stream_2_s_dout),
.if_empty_n(img2_data_stream_2_s_empty_n),
.if_read(CvtColor_U0_p_src_data_stream_2_V_read)
);
fifo_w8_d1_A img3_data_stream_0_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(CvtColor_U0_p_dst_data_stream_0_V_din),
.if_full_n(img3_data_stream_0_s_full_n),
.if_write(CvtColor_U0_p_dst_data_stream_0_V_write),
.if_dout(img3_data_stream_0_s_dout),
.if_empty_n(img3_data_stream_0_s_empty_n),
.if_read(Mat2AXIvideo_U0_img_data_stream_0_V_read)
);
fifo_w8_d1_A img3_data_stream_1_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(CvtColor_U0_p_dst_data_stream_1_V_din),
.if_full_n(img3_data_stream_1_s_full_n),
.if_write(CvtColor_U0_p_dst_data_stream_1_V_write),
.if_dout(img3_data_stream_1_s_dout),
.if_empty_n(img3_data_stream_1_s_empty_n),
.if_read(Mat2AXIvideo_U0_img_data_stream_1_V_read)
);
fifo_w8_d1_A img3_data_stream_2_s_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(CvtColor_U0_p_dst_data_stream_2_V_din),
.if_full_n(img3_data_stream_2_s_full_n),
.if_write(CvtColor_U0_p_dst_data_stream_2_V_write),
.if_dout(img3_data_stream_2_s_dout),
.if_empty_n(img3_data_stream_2_s_empty_n),
.if_read(Mat2AXIvideo_U0_img_data_stream_2_V_read)
);
start_for_Loop_lojbC start_for_Loop_lojbC_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(start_for_Loop_loop_height_pro_U0_din),
.if_full_n(start_for_Loop_loop_height_pro_U0_full_n),
.if_write(Block_Mat_exit1573_p_U0_start_write),
.if_dout(start_for_Loop_loop_height_pro_U0_dout),
.if_empty_n(start_for_Loop_loop_height_pro_U0_empty_n),
.if_read(Loop_loop_height_pro_U0_ap_ready)
);
start_for_CvtColokbM start_for_CvtColokbM_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(start_for_CvtColor_U0_din),
.if_full_n(start_for_CvtColor_U0_full_n),
.if_write(Block_Mat_exit1573_p_U0_start_write),
.if_dout(start_for_CvtColor_U0_dout),
.if_empty_n(start_for_CvtColor_U0_empty_n),
.if_read(CvtColor_U0_ap_ready)
);
start_for_Mat2AXIlbW start_for_Mat2AXIlbW_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(start_for_Mat2AXIvideo_U0_din),
.if_full_n(start_for_Mat2AXIvideo_U0_full_n),
.if_write(Block_Mat_exit1573_p_U0_start_write),
.if_dout(start_for_Mat2AXIvideo_U0_dout),
.if_empty_n(start_for_Mat2AXIvideo_U0_empty_n),
.if_read(Mat2AXIvideo_U0_ap_ready)
);
start_for_CvtColomb6 start_for_CvtColomb6_U(
.clk(ap_clk),
.reset(ap_rst_n_inv),
.if_read_ce(1'b1),
.if_write_ce(1'b1),
.if_din(start_for_CvtColor_1_U0_din),
.if_full_n(start_for_CvtColor_1_U0_full_n),
.if_write(AXIvideo2Mat_U0_start_write),
.if_dout(start_for_CvtColor_1_U0_dout),
.if_empty_n(start_for_CvtColor_1_U0_empty_n),
.if_read(CvtColor_1_U0_ap_ready)
);
assign AXIvideo2Mat_U0_ap_continue = 1'b1;
assign AXIvideo2Mat_U0_ap_start = 1'b1;
assign Block_Mat_exit1573_p_U0_ap_continue = 1'b1;
assign Block_Mat_exit1573_p_U0_ap_start = 1'b1;
assign Block_Mat_exit1573_p_U0_start_full_n = (start_for_Mat2AXIvideo_U0_full_n & start_for_Loop_loop_height_pro_U0_full_n & start_for_CvtColor_U0_full_n);
assign CvtColor_1_U0_ap_continue = 1'b1;
assign CvtColor_1_U0_ap_start = start_for_CvtColor_1_U0_empty_n;
assign CvtColor_1_U0_start_full_n = 1'b1;
assign CvtColor_1_U0_start_write = 1'b0;
assign CvtColor_U0_ap_continue = 1'b1;
assign CvtColor_U0_ap_start = start_for_CvtColor_U0_empty_n;
assign CvtColor_U0_start_full_n = 1'b1;
assign CvtColor_U0_start_write = 1'b0;
assign Loop_loop_height_pro_U0_ap_continue = 1'b1;
assign Loop_loop_height_pro_U0_ap_start = start_for_Loop_loop_height_pro_U0_empty_n;
assign Loop_loop_height_pro_U0_start_full_n = 1'b1;
assign Loop_loop_height_pro_U0_start_write = 1'b0;
assign Mat2AXIvideo_U0_ap_continue = 1'b1;
assign Mat2AXIvideo_U0_ap_start = start_for_Mat2AXIvideo_U0_empty_n;
assign Mat2AXIvideo_U0_start_full_n = 1'b1;
assign Mat2AXIvideo_U0_start_write = 1'b0;
always @ (*) begin
ap_rst_n_inv = ~ap_rst_n;
end
assign ap_sync_continue = 1'b0;
assign start_for_CvtColor_1_U0_din = 1'b1;
assign start_for_CvtColor_U0_din = 1'b1;
assign start_for_Loop_loop_height_pro_U0_din = 1'b1;
assign start_for_Mat2AXIvideo_U0_din = 1'b1;
assign stream_in_TREADY = AXIvideo2Mat_U0_stream_in_TREADY;
assign stream_out_TDATA = Mat2AXIvideo_U0_stream_out_TDATA;
assign stream_out_TDEST = Mat2AXIvideo_U0_stream_out_TDEST;
assign stream_out_TID = Mat2AXIvideo_U0_stream_out_TID;
assign stream_out_TKEEP = Mat2AXIvideo_U0_stream_out_TKEEP;
assign stream_out_TLAST = Mat2AXIvideo_U0_stream_out_TLAST;
assign stream_out_TSTRB = Mat2AXIvideo_U0_stream_out_TSTRB;
assign stream_out_TUSER = Mat2AXIvideo_U0_stream_out_TUSER;
assign stream_out_TVALID = Mat2AXIvideo_U0_stream_out_TVALID;
endmodule //hls_contrast_stretch
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: memport_bs.v,v 1.1 2001/10/13 03:35:01 sib4 Exp $
// $Log: memport_bs.v,v $
// Revision 1.1 2001/10/13 03:35:01 sib4
// PR#303 memport_bs.v
//
module pr303;
reg [3:0] mem [2:5];
wire [3:0] m1 = mem[1];
wire [3:0] m2 = mem[2];
wire [3:0] m3 = mem[3];
wire [3:0] m4 = mem[4];
wire [3:0] m5 = mem[5];
wire [3:0] m6 = mem[6];
reg [2:0] a;
reg [3:0] e;
initial
begin
e = 0;
for (a=0; a<7; a=a+1) mem[a] <= a;
#1;
if ( m1 !== 4'hx) begin e=e+1; $display("FAILED m1=%b", m1 ); end
if (mem[1] !== 4'hx) begin e=e+1; $display("FAILED mem[1]=%b", mem[1]); end
if ( m2 !== 4'h2) begin e=e+1; $display("FAILED m2=%b", m2 ); end
if (mem[2] !== 4'h2) begin e=e+1; $display("FAILED mem[2]=%b", mem[2]); end
if ( m3 !== 4'h3) begin e=e+1; $display("FAILED m3=%b", m3 ); end
if (mem[3] !== 4'h3) begin e=e+1; $display("FAILED mem[3]=%b", mem[3]); end
if ( m4 !== 4'h4) begin e=e+1; $display("FAILED m4=%b", m4 ); end
if (mem[4] !== 4'h4) begin e=e+1; $display("FAILED mem[4]=%b", mem[4]); end
if ( m5 !== 4'h5) begin e=e+1; $display("FAILED m5=%b", m5 ); end
if (mem[5] !== 4'h5) begin e=e+1; $display("FAILED mem[5]=%b", mem[5]); end
if ( m6 !== 4'hx) begin e=e+1; $display("FAILED m6=%b", m6 ); end
if (mem[6] !== 4'hx) begin e=e+1; $display("FAILED mem[6]=%b", mem[6]); end
if (e===0) $display("PASSED");
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_irq_gen # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input pcie_legacy_irq_set,
input pcie_msi_irq_set,
input [2:0] pcie_irq_vector,
input pcie_legacy_irq_clear,
output pcie_irq_done
);
localparam S_IDLE = 7'b0000001;
localparam S_SEND_MSI = 7'b0000010;
localparam S_LEGACY_ASSERT = 7'b0000100;
localparam S_LEGACY_ASSERT_HOLD = 7'b0001000;
localparam S_LEGACY_DEASSERT = 7'b0010000;
localparam S_WAIT_RDY_N = 7'b0100000;
localparam S_IRQ_DONE = 7'b1000000;
reg [6:0] cur_state;
reg [6:0] next_state;
reg r_cfg_interrupt;
reg r_cfg_interrupt_assert;
reg [7:0] r_cfg_interrupt_di;
reg [2:0] r_pcie_irq_vector;
reg r_pcie_irq_done;
assign cfg_interrupt = r_cfg_interrupt;
assign cfg_interrupt_assert = r_cfg_interrupt_assert;
assign cfg_interrupt_di = r_cfg_interrupt_di;
assign cfg_interrupt_stat = 1'b0;
assign cfg_pciecap_interrupt_msgnum = 5'b0;
assign pcie_irq_done = r_pcie_irq_done;
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(pcie_msi_irq_set == 1)
next_state <= S_SEND_MSI;
else if(pcie_legacy_irq_set == 1)
next_state <= S_LEGACY_ASSERT;
else
next_state <= S_IDLE;
end
S_SEND_MSI: begin
if(cfg_interrupt_rdy == 1)
next_state <= S_WAIT_RDY_N;
else
next_state <= S_SEND_MSI;
end
S_LEGACY_ASSERT: begin
if(cfg_interrupt_rdy == 1)
next_state <= S_LEGACY_ASSERT_HOLD;
else
next_state <= S_LEGACY_ASSERT;
end
S_LEGACY_ASSERT_HOLD: begin
if(pcie_legacy_irq_clear == 1)
next_state <= S_LEGACY_DEASSERT;
else
next_state <= S_LEGACY_ASSERT_HOLD;
end
S_LEGACY_DEASSERT: begin
if(cfg_interrupt_rdy == 1)
next_state <= S_WAIT_RDY_N;
else
next_state <= S_LEGACY_DEASSERT;
end
S_WAIT_RDY_N: begin
if(cfg_interrupt_rdy == 0)
next_state <= S_IRQ_DONE;
else
next_state <= S_WAIT_RDY_N;
end
S_IRQ_DONE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
r_pcie_irq_vector <= pcie_irq_vector;
end
S_SEND_MSI: begin
end
S_LEGACY_ASSERT: begin
end
S_LEGACY_ASSERT_HOLD: begin
end
S_LEGACY_DEASSERT: begin
end
S_WAIT_RDY_N: begin
end
S_IRQ_DONE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_cfg_interrupt <= 0;
r_cfg_interrupt_assert <= 0;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 0;
end
S_SEND_MSI: begin
r_cfg_interrupt <= 1;
r_cfg_interrupt_assert <= 0;
r_cfg_interrupt_di <= {5'b0, r_pcie_irq_vector};
r_pcie_irq_done <= 0;
end
S_LEGACY_ASSERT: begin
r_cfg_interrupt <= 1;
r_cfg_interrupt_assert <= 1;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 0;
end
S_LEGACY_ASSERT_HOLD: begin
r_cfg_interrupt <= 0;
r_cfg_interrupt_assert <= 1;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 0;
end
S_LEGACY_DEASSERT: begin
r_cfg_interrupt <= 1;
r_cfg_interrupt_assert <= 0;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 0;
end
S_WAIT_RDY_N: begin
r_cfg_interrupt <= 1;
r_cfg_interrupt_assert <= 0;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 0;
end
S_IRQ_DONE: begin
r_cfg_interrupt <= 0;
r_cfg_interrupt_assert <= 0;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 1;
end
default: begin
r_cfg_interrupt <= 0;
r_cfg_interrupt_assert <= 0;
r_cfg_interrupt_di <= 0;
r_pcie_irq_done <= 0;
end
endcase
end
endmodule |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module des_crypt_salt_test;
// Inputs
reg [63:0] Din;
reg [63:0] K;
reg [11:0] salt;
reg CLK;
// Outputs
wire [67:0] Kout;
wire [31:0] L_out;
wire [31:0] R_out;
// Instantiate the Unit Under Test (UUT)
descrypt_salt uut (
.Din(Din),
.K(K),
.salt(salt),
.Kout(Kout),
.CLK(CLK),
.L_out(L_out),
.R_out(R_out)
);
initial begin
// Initialize Inputs
Din = 0;
K = 0;
salt = 0;
CLK = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
// Hash: abcdefgh Salt: AA
Din = 64'h00;
K = 64'b1100001011000100110001101100100011001010110011001100111011010000;
salt = 12'b001100001100;
#19000;
if(!(L_out === 32'h18df29dc)) $finish;
if(!(R_out === 32'hdbab5b10)) $finish;
end
initial
begin
#100;
while (1)
begin
CLK = ~CLK;
#10;
end;
end
endmodule
|
//-----------------------------------------------------------------------------
// ISO14443-A support for the Proxmark III
// Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
// constants for the different modes:
`define SNIFFER 3'b000
`define TAGSIM_LISTEN 3'b001
`define TAGSIM_MOD 3'b010
`define READER_LISTEN 3'b011
`define READER_MOD 3'b100
module hi_iso14443a(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
mod_type
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [2:0] mod_type;
wire adc_clk = ck_1356meg;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Reader -> PM3:
// detecting and shaping the reader's signal. Reader will modulate the carrier by 100% (signal is either on or off). Use a
// hysteresis (Schmitt Trigger) to avoid false triggers during slowly increasing or decreasing carrier amplitudes
reg after_hysteresis;
reg [11:0] has_been_low_for;
always @(negedge adc_clk)
begin
if(adc_d >= 16) after_hysteresis <= 1'b1; // U >= 1,14V -> after_hysteresis = 1
else if(adc_d < 8) after_hysteresis <= 1'b0; // U < 1,04V -> after_hysteresis = 0
// Note: was >= 3,53V and <= 1,19V. The new trigger values allow more reliable detection of the first bit
// (it might not reach 3,53V due to the high time constant of the high pass filter in the analogue RF part).
// In addition, the new values are more in line with ISO14443-2: "The PICC shall detect the ”End of Pause” after the field exceeds
// 5% of H_INITIAL and before it exceeds 60% of H_INITIAL." Depending on the signal strength, 60% might well be less than 3,53V.
// detecting a loss of reader's field (adc_d < 192 for 4096 clock cycles). If this is the case,
// set the detected reader signal (after_hysteresis) to '1' (unmodulated)
if(adc_d >= 192)
begin
has_been_low_for <= 12'd0;
end
else
begin
if(has_been_low_for == 12'd4095)
begin
has_been_low_for <= 12'd0;
after_hysteresis <= 1'b1;
end
else
begin
has_been_low_for <= has_been_low_for + 1;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Reader -> PM3
// detect when a reader is active (modulating). We assume that the reader is active, if we see the carrier off for at least 8
// carrier cycles. We assume that the reader is inactive, if the carrier stayed high for at least 256 carrier cycles.
reg deep_modulation;
reg [2:0] deep_counter;
reg [8:0] saw_deep_modulation;
always @(negedge adc_clk)
begin
if(~(| adc_d[7:0])) // if adc_d == 0 (U <= 0,94V)
begin
if(deep_counter == 3'd7) // adc_d == 0 for 8 adc_clk ticks -> deep_modulation (by reader)
begin
deep_modulation <= 1'b1;
saw_deep_modulation <= 8'd0;
end
else
deep_counter <= deep_counter + 1;
end
else
begin
deep_counter <= 3'd0;
if(saw_deep_modulation == 8'd255) // adc_d != 0 for 256 adc_clk ticks -> deep_modulation is over, probably waiting for tag's response
deep_modulation <= 1'b0;
else
saw_deep_modulation <= saw_deep_modulation + 1;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3
// filter the input for a tag's signal. The filter box needs the 4 previous input values and is a gaussian derivative filter
// for noise reduction and edge detection.
// store 4 previous samples:
reg [7:0] input_prev_4, input_prev_3, input_prev_2, input_prev_1;
// convert to signed signals (and multiply by two for samples at t-4 and t)
wire signed [10:0] input_prev_4_times_2 = {0, 0, input_prev_4, 0};
wire signed [10:0] input_prev_3_times_1 = {0, 0, 0, input_prev_3};
wire signed [10:0] input_prev_1_times_1 = {0, 0, 0, input_prev_1};
wire signed [10:0] adc_d_times_2 = {0, 0, adc_d, 0};
wire signed [10:0] tmp_1, tmp_2;
wire signed [10:0] adc_d_filtered;
integer i;
assign tmp_1 = input_prev_4_times_2 + input_prev_3_times_1;
assign tmp_2 = input_prev_1_times_1 + adc_d_times_2;
always @(negedge adc_clk)
begin
// for (i = 3; i > 0; i = i - 1)
// begin
// input_shift[i] <= input_shift[i-1];
// end
// input_shift[0] <= adc_d;
input_prev_4 <= input_prev_3;
input_prev_3 <= input_prev_2;
input_prev_2 <= input_prev_1;
input_prev_1 <= adc_d;
end
// assign adc_d_filtered = (input_shift[3] << 1) + input_shift[2] - input_shift[0] - (adc_d << 1);
assign adc_d_filtered = tmp_1 - tmp_2;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// internal FPGA timing. Maximum required period is 128 carrier clock cycles for a full 8 Bit transfer to ARM. (i.e. we need a
// 7 bit counter). Adjust its frequency to external reader's clock when simulating a tag or sniffing.
reg pre_after_hysteresis;
reg [3:0] reader_falling_edge_time;
reg [6:0] negedge_cnt;
always @(negedge adc_clk)
begin
// detect a reader signal's falling edge and remember its timing:
pre_after_hysteresis <= after_hysteresis;
if (pre_after_hysteresis && ~after_hysteresis)
begin
reader_falling_edge_time[3:0] <= negedge_cnt[3:0];
end
// adjust internal timer counter if necessary:
if (negedge_cnt[3:0] == 4'd13 && (mod_type == `SNIFFER || mod_type == `TAGSIM_LISTEN) && deep_modulation)
begin
if (reader_falling_edge_time == 4'd1) // reader signal changes right after sampling. Better sample earlier next time.
begin
negedge_cnt <= negedge_cnt + 2; // time warp
end
else if (reader_falling_edge_time == 4'd0) // reader signal changes right before sampling. Better sample later next time.
begin
negedge_cnt <= negedge_cnt; // freeze time
end
else
begin
negedge_cnt <= negedge_cnt + 1; // Continue as usual
end
reader_falling_edge_time[3:0] <= 4'd8; // adjust only once per detected edge
end
else if (negedge_cnt == 7'd127) // normal operation: count from 0 to 127
begin
negedge_cnt <= 0;
end
else
begin
negedge_cnt <= negedge_cnt + 1;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3:
// determine best possible time for starting/resetting the modulation detector.
reg [3:0] mod_detect_reset_time;
always @(negedge adc_clk)
begin
if (mod_type == `READER_LISTEN)
// (our) reader signal changes at t=1, tag response expected n*16+4 ticks later, further delayed by
// 3 ticks ADC conversion.
// 1 + 4 + 3 = 8
begin
mod_detect_reset_time <= 4'd8;
end
else
if (mod_type == `SNIFFER)
begin
// detect a rising edge of reader's signal and sync modulation detector to the tag's answer:
if (~pre_after_hysteresis && after_hysteresis && deep_modulation)
// reader signal rising edge detected at negedge_cnt[3:0]. This signal had been delayed
// 9 ticks by the RF part + 3 ticks by the A/D converter + 1 tick to assign to after_hysteresis.
// The tag will respond n*16 + 4 ticks later + 3 ticks A/D converter delay.
// - 9 - 3 - 1 + 4 + 3 = -6
begin
mod_detect_reset_time <= negedge_cnt[3:0] - 4'd4;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3:
// modulation detector. Looks for the steepest falling and rising edges within a 16 clock period. If there is both a significant
// falling and rising edge (in any order), a modulation is detected.
reg signed [10:0] rx_mod_falling_edge_max;
reg signed [10:0] rx_mod_rising_edge_max;
reg curbit;
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == mod_detect_reset_time)
begin
// detect modulation signal: if modulating, there must have been a falling AND a rising edge
if (rx_mod_falling_edge_max > 5 && rx_mod_rising_edge_max > 5)
curbit <= 1'b1; // modulation
else
curbit <= 1'b0; // no modulation
// reset modulation detector
rx_mod_rising_edge_max <= 0;
rx_mod_falling_edge_max <= 0;
end
else // look for steepest edges (slopes)
begin
if (adc_d_filtered > 0)
begin
if (adc_d_filtered > rx_mod_falling_edge_max)
rx_mod_falling_edge_max <= adc_d_filtered;
end
else
begin
if (-adc_d_filtered > rx_mod_rising_edge_max)
rx_mod_rising_edge_max <= -adc_d_filtered;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag+Reader -> PM3
// sample 4 bits reader data and 4 bits tag data for sniffing
reg [3:0] reader_data;
reg [3:0] tag_data;
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == 4'd0)
begin
reader_data[3:0] <= {reader_data[2:0], after_hysteresis};
tag_data[3:0] <= {tag_data[2:0], curbit};
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Tag:
// a delay line to ensure that we send the (emulated) tag's answer at the correct time according to ISO14443-3
reg [31:0] mod_sig_buf;
reg [4:0] mod_sig_ptr;
reg mod_sig;
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == 4'd0) // sample data at rising edge of ssp_clk - ssp_dout changes at the falling edge.
begin
mod_sig_buf[31:2] <= mod_sig_buf[30:1]; // shift
if (~ssp_dout && ~mod_sig_buf[1])
mod_sig_buf[1] <= 1'b0; // delete the correction bit (a single 1 preceded and succeeded by 0)
else
mod_sig_buf[1] <= mod_sig_buf[0];
mod_sig_buf[0] <= ssp_dout; // add new data to the delay line
mod_sig = mod_sig_buf[mod_sig_ptr]; // the delayed signal.
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Tag, internal timing:
// a timer for the 1172 cycles fdt (Frame Delay Time). Start the timer with a rising edge of the reader's signal.
// set fdt_elapsed when we no longer need to delay data. Set fdt_indicator when we can start sending data.
// Note: the FPGA only takes care for the 1172 delay. To achieve an additional 1236-1172=64 ticks delay, the ARM must send
// a correction bit (before the start bit). The correction bit will be coded as 00010000, i.e. it adds 4 bits to the
// transmission stream, causing the required additional delay.
reg [10:0] fdt_counter;
reg fdt_indicator, fdt_elapsed;
reg [3:0] mod_sig_flip;
reg [3:0] sub_carrier_cnt;
// we want to achieve a delay of 1172. The RF part already has delayed the reader signals's rising edge
// by 9 ticks, the ADC took 3 ticks and there is always a delay of 32 ticks by the mod_sig_buf. Therefore need to
// count to 1172 - 9 - 3 - 32 = 1128
`define FDT_COUNT 11'd1128
// The ARM must not send too early, otherwise the mod_sig_buf will overflow, therefore signal that we are ready
// with fdt_indicator. The mod_sig_buf can buffer 29 excess data bits, i.e. a maximum delay of 29 * 16 = 464 adc_clk ticks.
// fdt_indicator could appear at ssp_din after 1 tick, the transfer needs 16 ticks, the ARM can send 128 ticks later.
// 1128 - 464 - 1 - 128 - 8 = 535
`define FDT_INDICATOR_COUNT 11'd535
// reset on a pause in listen mode. I.e. the counter starts when the pause is over:
assign fdt_reset = ~after_hysteresis && mod_type == `TAGSIM_LISTEN;
always @(negedge adc_clk)
begin
if (fdt_reset)
begin
fdt_counter <= 11'd0;
fdt_elapsed <= 1'b0;
fdt_indicator <= 1'b0;
end
else
begin
if(fdt_counter == `FDT_COUNT)
begin
if(~fdt_elapsed) // just reached fdt.
begin
mod_sig_flip <= negedge_cnt[3:0]; // start modulation at this time
sub_carrier_cnt <= 4'd0; // subcarrier phase in sync with start of modulation
fdt_elapsed <= 1'b1;
end
else
begin
sub_carrier_cnt <= sub_carrier_cnt + 1;
end
end
else
begin
fdt_counter <= fdt_counter + 1;
end
end
if(fdt_counter == `FDT_INDICATOR_COUNT) fdt_indicator <= 1'b1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader or Tag
// assign a modulation signal to the antenna. This signal is either a delayed signal (to achieve fdt when sending to a reader)
// or undelayed when sending to a tag
reg mod_sig_coil;
always @(negedge adc_clk)
begin
if (mod_type == `TAGSIM_MOD) // need to take care of proper fdt timing
begin
if(fdt_counter == `FDT_COUNT)
begin
if(fdt_elapsed)
begin
if(negedge_cnt[3:0] == mod_sig_flip) mod_sig_coil <= mod_sig;
end
else
begin
mod_sig_coil <= mod_sig; // just reached fdt. Immediately assign signal to coil
end
end
end
else // other modes: don't delay
begin
mod_sig_coil <= ssp_dout;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader
// determine the required delay in the mod_sig_buf (set mod_sig_ptr).
reg temp_buffer_reset;
always @(negedge adc_clk)
begin
if(fdt_reset)
begin
mod_sig_ptr <= 5'd0;
temp_buffer_reset = 1'b0;
end
else
begin
if(fdt_counter == `FDT_COUNT && ~fdt_elapsed) // if we just reached fdt
if(~(| mod_sig_ptr[4:0]))
mod_sig_ptr <= 5'd8; // ... but didn't buffer a 1 yet, delay next 1 by n*128 ticks.
else
temp_buffer_reset = 1'b1; // else no need for further delays.
if(negedge_cnt[3:0] == 4'd0) // at rising edge of ssp_clk - ssp_dout changes at the falling edge.
begin
if((ssp_dout || (| mod_sig_ptr[4:0])) && ~fdt_elapsed) // buffer a 1 (and all subsequent data) until fdt is reached.
if (mod_sig_ptr == 5'd31)
mod_sig_ptr <= 5'd0; // buffer overflow - data loss.
else
mod_sig_ptr <= mod_sig_ptr + 1; // increase buffer (= increase delay by 16 adc_clk ticks). mod_sig_ptr always points ahead of first 1.
else if(fdt_elapsed && ~temp_buffer_reset)
begin
// wait for the next 1 after fdt_elapsed before fixing the delay and starting modulation. This ensures that the response can only happen
// at intervals of 8 * 16 = 128 adc_clk ticks (as defined in ISO14443-3)
if(ssp_dout)
temp_buffer_reset = 1'b1;
if(mod_sig_ptr == 5'd1)
mod_sig_ptr <= 5'd8; // still nothing received, need to go for the next interval
else
mod_sig_ptr <= mod_sig_ptr - 1; // decrease buffer.
end
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA -> ARM communication:
// buffer 8 bits data to be sent to ARM. Shift them out bit by bit.
reg [7:0] to_arm;
always @(negedge adc_clk)
begin
if (negedge_cnt[5:0] == 6'd63) // fill the buffer
begin
if (mod_type == `SNIFFER)
begin
if(deep_modulation) // a reader is sending (or there's no field at all)
begin
to_arm <= {reader_data[3:0], 4'b0000}; // don't send tag data
end
else
begin
to_arm <= {reader_data[3:0], tag_data[3:0]};
end
end
else
begin
to_arm[7:0] <= {mod_sig_ptr[4:0], mod_sig_flip[3:1]}; // feedback timing information
end
end
if(negedge_cnt[2:0] == 3'b000 && mod_type == `SNIFFER) // shift at double speed
begin
// Don't shift if we just loaded new data, obviously.
if(negedge_cnt[5:0] != 6'd0)
begin
to_arm[7:1] <= to_arm[6:0];
end
end
if(negedge_cnt[3:0] == 4'b0000 && mod_type != `SNIFFER)
begin
// Don't shift if we just loaded new data, obviously.
if(negedge_cnt[6:0] != 7'd0)
begin
to_arm[7:1] <= to_arm[6:0];
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA -> ARM communication:
// generate a ssp clock and ssp frame signal for the synchronous transfer from/to the ARM
reg ssp_clk;
reg ssp_frame;
reg [2:0] ssp_frame_counter;
always @(negedge adc_clk)
begin
if(mod_type == `SNIFFER)
// SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
begin
if(negedge_cnt[2:0] == 3'd0)
ssp_clk <= 1'b1;
if(negedge_cnt[2:0] == 3'd4)
ssp_clk <= 1'b0;
if(negedge_cnt[5:0] == 6'd0) // ssp_frame rising edge indicates start of frame
ssp_frame <= 1'b1;
if(negedge_cnt[5:0] == 6'd8)
ssp_frame <= 1'b0;
end
else
// all other modes (ssp_clk = adc_clk / 16, ssp_frame clock = adc_clk / 128):
begin
if(negedge_cnt[3:0] == 4'd0)
ssp_clk <= 1'b1;
if(negedge_cnt[3:0] == 4'd8)
ssp_clk <= 1'b0;
if(negedge_cnt[6:0] == 7'd7) // ssp_frame rising edge indicates start of frame
ssp_frame <= 1'b1;
if(negedge_cnt[6:0] == 7'd23)
ssp_frame <= 1'b0;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA -> ARM communication:
// select the data to be sent to ARM
reg bit_to_arm;
reg sendbit;
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == 4'd0)
begin
// What do we communicate to the ARM
if(mod_type == `TAGSIM_LISTEN)
sendbit = after_hysteresis;
else if(mod_type == `TAGSIM_MOD)
/* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh?
else */
sendbit = fdt_indicator;
else if (mod_type == `READER_LISTEN)
sendbit = curbit;
else
sendbit = 1'b0;
end
if(mod_type == `SNIFFER)
// send sampled reader and tag data:
bit_to_arm = to_arm[7];
else if (mod_type == `TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
// send timing information:
bit_to_arm = to_arm[7];
else
// send data or fdt_indicator
bit_to_arm = sendbit;
end
assign ssp_din = bit_to_arm;
// Subcarrier (adc_clk/16, for TAGSIM_MOD only).
wire sub_carrier;
assign sub_carrier = ~sub_carrier_cnt[3];
// in READER_MOD: drop carrier for mod_sig_coil==1 (pause); in READER_LISTEN: carrier always on; in other modes: carrier always off
assign pwr_hi = (ck_1356megb & (((mod_type == `READER_MOD) & ~mod_sig_coil) || (mod_type == `READER_LISTEN)));
// Enable HF antenna drivers:
assign pwr_oe1 = 1'b0;
assign pwr_oe3 = 1'b0;
// TAGSIM_MOD: short circuit antenna with different resistances (modulated by sub_carrier modulated by mod_sig_coil)
// for pwr_oe4 = 1 (tristate): antenna load = 10k || 33 = 32,9 Ohms
// for pwr_oe4 = 0 (active): antenna load = 10k || 33 || 33 = 16,5 Ohms
assign pwr_oe4 = ~(mod_sig_coil & sub_carrier & (mod_type == `TAGSIM_MOD));
// This is all LF, so doesn't matter.
assign pwr_oe2 = 1'b0;
assign pwr_lo = 1'b0;
assign dbg = negedge_cnt[3];
endmodule
|
`include "hi_simulate.v"
/*
pck0 - input main 24Mhz clock (PLL / 4)
[7:0] adc_d - input data from A/D converter
mod_type - modulation type
pwr_lo - output to coil drivers (ssp_clk / 8)
adc_clk - output A/D clock signal
ssp_frame - output SSS frame indicator (goes high while the 8 bits are shifted)
ssp_din - output SSP data to ARM (shifts 8 bit A/D value serially to ARM MSB first)
ssp_clk - output SSP clock signal
ck_1356meg - input unused
ck_1356megb - input unused
ssp_dout - input unused
cross_hi - input unused
cross_lo - input unused
pwr_hi - output unused, tied low
pwr_oe1 - output unused, undefined
pwr_oe2 - output unused, undefined
pwr_oe3 - output unused, undefined
pwr_oe4 - output unused, undefined
dbg - output alias for adc_clk
*/
module testbed_hi_simulate;
reg pck0;
reg [7:0] adc_d;
reg mod_type;
wire pwr_lo;
wire adc_clk;
reg ck_1356meg;
reg ck_1356megb;
wire ssp_frame;
wire ssp_din;
wire ssp_clk;
reg ssp_dout;
wire pwr_hi;
wire pwr_oe1;
wire pwr_oe2;
wire pwr_oe3;
wire pwr_oe4;
wire cross_lo;
wire cross_hi;
wire dbg;
hi_simulate #(5,200) dut(
.pck0(pck0),
.ck_1356meg(ck_1356meg),
.ck_1356megb(ck_1356megb),
.pwr_lo(pwr_lo),
.pwr_hi(pwr_hi),
.pwr_oe1(pwr_oe1),
.pwr_oe2(pwr_oe2),
.pwr_oe3(pwr_oe3),
.pwr_oe4(pwr_oe4),
.adc_d(adc_d),
.adc_clk(adc_clk),
.ssp_frame(ssp_frame),
.ssp_din(ssp_din),
.ssp_dout(ssp_dout),
.ssp_clk(ssp_clk),
.cross_hi(cross_hi),
.cross_lo(cross_lo),
.dbg(dbg),
.mod_type(mod_type)
);
integer idx, i;
// main clock
always #5 begin
ck_1356megb = !ck_1356megb;
ck_1356meg = ck_1356megb;
end
always begin
@(negedge adc_clk) ;
adc_d = $random;
end
//crank DUT
task crank_dut;
begin
@(negedge ssp_clk) ;
ssp_dout = $random;
end
endtask
initial begin
// init inputs
ck_1356megb = 0;
// random values
adc_d = 0;
ssp_dout=1;
// shallow modulation off
mod_type=0;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
// shallow modulation on
mod_type=1;
for (i = 0 ; i < 16 ; i = i + 1) begin
crank_dut;
end
$finish;
end
endmodule // main
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: div8.v
// /___/ /\ Timestamp: Fri Apr 24 18:09:52 2015
// \ \ / \
// \___\/\___\
//
// Command : -intstyle ise -w -sim -ofmt verilog ./tmp/_cg/div8.ngc ./tmp/_cg/div8.v
// Device : 6slx45csg324-2
// Input file : ./tmp/_cg/div8.ngc
// Output file : ./tmp/_cg/div8.v
// # of Modules : 1
// Design Name : div8
// Xilinx : /mnt/data/Xilinx/14.7/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module div8 (
rfd, clk, dividend, quotient, divisor, fractional
)/* synthesis syn_black_box syn_noprune=1 */;
output rfd;
input clk;
input [7 : 0] dividend;
output [7 : 0] quotient;
input [7 : 0] divisor;
output [7 : 0] fractional;
// synthesis translate_off
wire NlwRenamedSig_OI_rfd;
wire \blk00000003/sig000003ad ;
wire \blk00000003/sig000003ac ;
wire \blk00000003/sig000003ab ;
wire \blk00000003/sig000003aa ;
wire \blk00000003/sig000003a9 ;
wire \blk00000003/sig000003a8 ;
wire \blk00000003/sig000003a7 ;
wire \blk00000003/sig000003a6 ;
wire \blk00000003/sig000003a5 ;
wire \blk00000003/sig000003a4 ;
wire \blk00000003/sig000003a3 ;
wire \blk00000003/sig000003a2 ;
wire \blk00000003/sig000003a1 ;
wire \blk00000003/sig000003a0 ;
wire \blk00000003/sig0000039f ;
wire \blk00000003/sig0000039e ;
wire \blk00000003/sig0000039d ;
wire \blk00000003/sig0000039c ;
wire \blk00000003/sig0000039b ;
wire \blk00000003/sig0000039a ;
wire \blk00000003/sig00000399 ;
wire \blk00000003/sig00000398 ;
wire \blk00000003/sig00000397 ;
wire \blk00000003/sig00000396 ;
wire \blk00000003/sig00000395 ;
wire \blk00000003/sig00000394 ;
wire \blk00000003/sig00000393 ;
wire \blk00000003/sig00000392 ;
wire \blk00000003/sig00000391 ;
wire \blk00000003/sig00000390 ;
wire \blk00000003/sig0000038f ;
wire \blk00000003/sig0000038e ;
wire \blk00000003/sig0000038d ;
wire \blk00000003/sig0000038c ;
wire \blk00000003/sig0000038b ;
wire \blk00000003/sig0000038a ;
wire \blk00000003/sig00000389 ;
wire \blk00000003/sig00000388 ;
wire \blk00000003/sig00000387 ;
wire \blk00000003/sig00000386 ;
wire \blk00000003/sig00000385 ;
wire \blk00000003/sig00000384 ;
wire \blk00000003/sig00000383 ;
wire \blk00000003/sig00000382 ;
wire \blk00000003/sig00000381 ;
wire \blk00000003/sig00000380 ;
wire \blk00000003/sig0000037f ;
wire \blk00000003/sig0000037e ;
wire \blk00000003/sig0000037d ;
wire \blk00000003/sig0000037c ;
wire \blk00000003/sig0000037b ;
wire \blk00000003/sig0000037a ;
wire \blk00000003/sig00000379 ;
wire \blk00000003/sig00000378 ;
wire \blk00000003/sig00000377 ;
wire \blk00000003/sig00000376 ;
wire \blk00000003/sig00000375 ;
wire \blk00000003/sig00000374 ;
wire \blk00000003/sig00000373 ;
wire \blk00000003/sig00000372 ;
wire \blk00000003/sig00000371 ;
wire \blk00000003/sig00000370 ;
wire \blk00000003/sig0000036f ;
wire \blk00000003/sig0000036e ;
wire \blk00000003/sig0000036d ;
wire \blk00000003/sig0000036c ;
wire \blk00000003/sig0000036b ;
wire \blk00000003/sig0000036a ;
wire \blk00000003/sig00000369 ;
wire \blk00000003/sig00000368 ;
wire \blk00000003/sig00000367 ;
wire \blk00000003/sig00000366 ;
wire \blk00000003/sig00000365 ;
wire \blk00000003/sig00000364 ;
wire \blk00000003/sig00000363 ;
wire \blk00000003/sig00000362 ;
wire \blk00000003/sig00000361 ;
wire \blk00000003/sig00000360 ;
wire \blk00000003/sig0000035f ;
wire \blk00000003/sig0000035e ;
wire \blk00000003/sig0000035d ;
wire \blk00000003/sig0000035c ;
wire \blk00000003/sig0000035b ;
wire \blk00000003/sig0000035a ;
wire \blk00000003/sig00000359 ;
wire \blk00000003/sig00000358 ;
wire \blk00000003/sig00000357 ;
wire \blk00000003/sig00000356 ;
wire \blk00000003/sig00000355 ;
wire \blk00000003/sig00000354 ;
wire \blk00000003/sig00000353 ;
wire \blk00000003/sig00000352 ;
wire \blk00000003/sig00000351 ;
wire \blk00000003/sig00000350 ;
wire \blk00000003/sig0000034f ;
wire \blk00000003/sig0000034e ;
wire \blk00000003/sig0000034d ;
wire \blk00000003/sig0000034c ;
wire \blk00000003/sig0000034b ;
wire \blk00000003/sig0000034a ;
wire \blk00000003/sig00000349 ;
wire \blk00000003/sig00000348 ;
wire \blk00000003/sig00000347 ;
wire \blk00000003/sig00000346 ;
wire \blk00000003/sig00000345 ;
wire \blk00000003/sig00000344 ;
wire \blk00000003/sig00000343 ;
wire \blk00000003/sig00000342 ;
wire \blk00000003/sig00000341 ;
wire \blk00000003/sig00000340 ;
wire \blk00000003/sig0000033f ;
wire \blk00000003/sig0000033e ;
wire \blk00000003/sig0000033d ;
wire \blk00000003/sig0000033c ;
wire \blk00000003/sig0000033b ;
wire \blk00000003/sig0000033a ;
wire \blk00000003/sig00000339 ;
wire \blk00000003/sig00000338 ;
wire \blk00000003/sig00000337 ;
wire \blk00000003/sig00000336 ;
wire \blk00000003/sig00000335 ;
wire \blk00000003/sig00000334 ;
wire \blk00000003/sig00000333 ;
wire \blk00000003/sig00000332 ;
wire \blk00000003/sig00000331 ;
wire \blk00000003/sig00000330 ;
wire \blk00000003/sig0000032f ;
wire \blk00000003/sig0000032e ;
wire \blk00000003/sig0000032d ;
wire \blk00000003/sig0000032c ;
wire \blk00000003/sig0000032b ;
wire \blk00000003/sig0000032a ;
wire \blk00000003/sig00000329 ;
wire \blk00000003/sig00000328 ;
wire \blk00000003/sig00000327 ;
wire \blk00000003/sig00000326 ;
wire \blk00000003/sig00000325 ;
wire \blk00000003/sig00000324 ;
wire \blk00000003/sig00000323 ;
wire \blk00000003/sig00000322 ;
wire \blk00000003/sig00000321 ;
wire \blk00000003/sig00000320 ;
wire \blk00000003/sig0000031f ;
wire \blk00000003/sig0000031e ;
wire \blk00000003/sig0000031d ;
wire \blk00000003/sig0000031c ;
wire \blk00000003/sig0000031b ;
wire \blk00000003/sig0000031a ;
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wire \blk00000003/sig00000095 ;
wire \blk00000003/sig00000094 ;
wire \blk00000003/sig00000093 ;
wire \blk00000003/sig00000092 ;
wire \blk00000003/sig00000091 ;
wire \blk00000003/sig00000090 ;
wire \blk00000003/sig0000008f ;
wire \blk00000003/sig0000008e ;
wire \blk00000003/sig0000008d ;
wire \blk00000003/sig0000008c ;
wire \blk00000003/sig0000008b ;
wire \blk00000003/sig0000008a ;
wire \blk00000003/sig00000089 ;
wire \blk00000003/sig00000088 ;
wire \blk00000003/sig00000087 ;
wire \blk00000003/sig00000086 ;
wire \blk00000003/sig00000085 ;
wire \blk00000003/sig00000084 ;
wire \blk00000003/sig00000083 ;
wire \blk00000003/sig00000082 ;
wire \blk00000003/sig00000081 ;
wire \blk00000003/sig00000080 ;
wire \blk00000003/sig0000007f ;
wire \blk00000003/sig0000007e ;
wire \blk00000003/sig0000007d ;
wire \blk00000003/sig0000007c ;
wire \blk00000003/sig0000007b ;
wire \blk00000003/sig0000007a ;
wire \blk00000003/sig00000079 ;
wire \blk00000003/sig00000078 ;
wire \blk00000003/sig00000077 ;
wire \blk00000003/sig00000076 ;
wire \blk00000003/sig00000075 ;
wire \blk00000003/sig00000074 ;
wire \blk00000003/sig00000073 ;
wire \blk00000003/sig00000072 ;
wire \blk00000003/sig00000071 ;
wire \blk00000003/sig00000070 ;
wire \blk00000003/sig0000006f ;
wire \blk00000003/sig0000006e ;
wire \blk00000003/sig0000006d ;
wire \blk00000003/sig0000006c ;
wire \blk00000003/sig0000006b ;
wire \blk00000003/sig0000006a ;
wire \blk00000003/sig00000069 ;
wire \blk00000003/sig00000068 ;
wire \blk00000003/sig00000067 ;
wire \blk00000003/sig00000066 ;
wire \blk00000003/sig00000065 ;
wire \blk00000003/sig00000064 ;
wire \blk00000003/sig00000063 ;
wire \blk00000003/sig00000062 ;
wire \blk00000003/sig00000061 ;
wire \blk00000003/sig00000060 ;
wire \blk00000003/sig0000005f ;
wire \blk00000003/sig0000005e ;
wire \blk00000003/sig0000005d ;
wire \blk00000003/sig0000005c ;
wire \blk00000003/sig0000005b ;
wire \blk00000003/sig0000005a ;
wire \blk00000003/sig00000059 ;
wire \blk00000003/sig00000058 ;
wire \blk00000003/sig00000057 ;
wire \blk00000003/sig00000056 ;
wire \blk00000003/sig00000055 ;
wire \blk00000003/sig00000054 ;
wire \blk00000003/sig00000053 ;
wire \blk00000003/sig00000052 ;
wire \blk00000003/sig00000051 ;
wire \blk00000003/sig00000050 ;
wire \blk00000003/sig0000004f ;
wire \blk00000003/sig0000004e ;
wire \blk00000003/sig0000004d ;
wire \blk00000003/sig0000004c ;
wire \blk00000003/sig0000004b ;
wire \blk00000003/sig0000004a ;
wire \blk00000003/sig00000049 ;
wire \blk00000003/sig00000048 ;
wire \blk00000003/sig00000047 ;
wire \blk00000003/sig00000046 ;
wire \blk00000003/sig00000045 ;
wire \blk00000003/sig00000044 ;
wire \blk00000003/sig00000043 ;
wire \blk00000003/sig00000042 ;
wire \blk00000003/sig00000041 ;
wire \blk00000003/sig00000040 ;
wire \blk00000003/sig0000003f ;
wire \blk00000003/sig0000003e ;
wire \blk00000003/sig0000003d ;
wire \blk00000003/sig0000003c ;
wire \blk00000003/sig0000003b ;
wire \blk00000003/sig0000003a ;
wire \blk00000003/sig00000039 ;
wire \blk00000003/sig00000038 ;
wire \blk00000003/sig00000037 ;
wire \blk00000003/sig00000036 ;
wire \blk00000003/sig00000035 ;
wire \blk00000003/sig00000034 ;
wire \blk00000003/sig00000033 ;
wire \blk00000003/sig00000032 ;
wire \blk00000003/sig00000031 ;
wire \blk00000003/sig00000030 ;
wire \blk00000003/sig0000002f ;
wire \blk00000003/sig0000002e ;
wire \blk00000003/sig0000002d ;
wire \blk00000003/sig0000002c ;
wire \blk00000003/sig0000002b ;
wire \blk00000003/sig0000002a ;
wire \blk00000003/sig00000029 ;
wire \blk00000003/sig00000028 ;
wire \blk00000003/sig00000027 ;
wire \blk00000003/sig00000026 ;
wire \blk00000003/sig00000025 ;
wire \blk00000003/sig00000024 ;
wire \blk00000003/sig00000022 ;
wire NLW_blk00000001_P_UNCONNECTED;
wire NLW_blk00000002_G_UNCONNECTED;
wire [7 : 0] dividend_0;
wire [7 : 0] divisor_1;
wire [7 : 0] quotient_2;
wire [7 : 0] fractional_3;
assign
dividend_0[7] = dividend[7],
dividend_0[6] = dividend[6],
dividend_0[5] = dividend[5],
dividend_0[4] = dividend[4],
dividend_0[3] = dividend[3],
dividend_0[2] = dividend[2],
dividend_0[1] = dividend[1],
dividend_0[0] = dividend[0],
quotient[7] = quotient_2[7],
quotient[6] = quotient_2[6],
quotient[5] = quotient_2[5],
quotient[4] = quotient_2[4],
quotient[3] = quotient_2[3],
quotient[2] = quotient_2[2],
quotient[1] = quotient_2[1],
quotient[0] = quotient_2[0],
divisor_1[7] = divisor[7],
divisor_1[6] = divisor[6],
divisor_1[5] = divisor[5],
divisor_1[4] = divisor[4],
divisor_1[3] = divisor[3],
divisor_1[2] = divisor[2],
divisor_1[1] = divisor[1],
divisor_1[0] = divisor[0],
rfd = NlwRenamedSig_OI_rfd,
fractional[7] = fractional_3[7],
fractional[6] = fractional_3[6],
fractional[5] = fractional_3[5],
fractional[4] = fractional_3[4],
fractional[3] = fractional_3[3],
fractional[2] = fractional_3[2],
fractional[1] = fractional_3[1],
fractional[0] = fractional_3[0];
VCC blk00000001 (
.P(NLW_blk00000001_P_UNCONNECTED)
);
GND blk00000002 (
.G(NLW_blk00000002_G_UNCONNECTED)
);
INV \blk00000003/blk0000039f (
.I(\blk00000003/sig000000e3 ),
.O(\blk00000003/sig000000ee )
);
INV \blk00000003/blk0000039e (
.I(\blk00000003/sig000000e4 ),
.O(\blk00000003/sig000000f1 )
);
INV \blk00000003/blk0000039d (
.I(\blk00000003/sig000000e5 ),
.O(\blk00000003/sig000000f4 )
);
INV \blk00000003/blk0000039c (
.I(\blk00000003/sig000000e6 ),
.O(\blk00000003/sig000000f7 )
);
INV \blk00000003/blk0000039b (
.I(\blk00000003/sig000000e7 ),
.O(\blk00000003/sig000000fa )
);
INV \blk00000003/blk0000039a (
.I(\blk00000003/sig000000e8 ),
.O(\blk00000003/sig000000fd )
);
INV \blk00000003/blk00000399 (
.I(\blk00000003/sig000000e9 ),
.O(\blk00000003/sig00000100 )
);
INV \blk00000003/blk00000398 (
.I(\blk00000003/sig0000038f ),
.O(\blk00000003/sig0000039e )
);
INV \blk00000003/blk00000397 (
.I(\blk00000003/sig00000390 ),
.O(\blk00000003/sig0000039f )
);
INV \blk00000003/blk00000396 (
.I(\blk00000003/sig00000391 ),
.O(\blk00000003/sig000003a0 )
);
INV \blk00000003/blk00000395 (
.I(\blk00000003/sig00000392 ),
.O(\blk00000003/sig000003a1 )
);
INV \blk00000003/blk00000394 (
.I(\blk00000003/sig00000393 ),
.O(\blk00000003/sig000003a2 )
);
INV \blk00000003/blk00000393 (
.I(\blk00000003/sig00000394 ),
.O(\blk00000003/sig000003a3 )
);
INV \blk00000003/blk00000392 (
.I(\blk00000003/sig00000395 ),
.O(\blk00000003/sig000003a4 )
);
INV \blk00000003/blk00000391 (
.I(\blk00000003/sig00000396 ),
.O(\blk00000003/sig000003a5 )
);
INV \blk00000003/blk00000390 (
.I(\blk00000003/sig00000397 ),
.O(\blk00000003/sig000003a6 )
);
INV \blk00000003/blk0000038f (
.I(\blk00000003/sig00000398 ),
.O(\blk00000003/sig000003a7 )
);
INV \blk00000003/blk0000038e (
.I(\blk00000003/sig00000399 ),
.O(\blk00000003/sig000003a8 )
);
INV \blk00000003/blk0000038d (
.I(\blk00000003/sig0000039a ),
.O(\blk00000003/sig000003a9 )
);
INV \blk00000003/blk0000038c (
.I(\blk00000003/sig0000039b ),
.O(\blk00000003/sig000003aa )
);
INV \blk00000003/blk0000038b (
.I(\blk00000003/sig0000039c ),
.O(\blk00000003/sig000003ab )
);
INV \blk00000003/blk0000038a (
.I(\blk00000003/sig0000039d ),
.O(\blk00000003/sig000003ac )
);
INV \blk00000003/blk00000389 (
.I(\blk00000003/sig0000033a ),
.O(\blk00000003/sig0000032d )
);
INV \blk00000003/blk00000388 (
.I(\blk00000003/sig0000033b ),
.O(\blk00000003/sig00000308 )
);
INV \blk00000003/blk00000387 (
.I(\blk00000003/sig0000033c ),
.O(\blk00000003/sig000002e3 )
);
INV \blk00000003/blk00000386 (
.I(\blk00000003/sig0000033d ),
.O(\blk00000003/sig000002be )
);
INV \blk00000003/blk00000385 (
.I(\blk00000003/sig0000033e ),
.O(\blk00000003/sig00000299 )
);
INV \blk00000003/blk00000384 (
.I(\blk00000003/sig0000033f ),
.O(\blk00000003/sig00000274 )
);
INV \blk00000003/blk00000383 (
.I(\blk00000003/sig00000340 ),
.O(\blk00000003/sig0000024f )
);
INV \blk00000003/blk00000382 (
.I(\blk00000003/sig00000341 ),
.O(\blk00000003/sig0000022a )
);
INV \blk00000003/blk00000381 (
.I(\blk00000003/sig00000024 ),
.O(\blk00000003/sig00000205 )
);
INV \blk00000003/blk00000380 (
.I(\blk00000003/sig00000032 ),
.O(\blk00000003/sig000001e0 )
);
INV \blk00000003/blk0000037f (
.I(\blk00000003/sig0000003c ),
.O(\blk00000003/sig000001bb )
);
INV \blk00000003/blk0000037e (
.I(\blk00000003/sig00000045 ),
.O(\blk00000003/sig00000196 )
);
INV \blk00000003/blk0000037d (
.I(\blk00000003/sig0000004e ),
.O(\blk00000003/sig00000171 )
);
INV \blk00000003/blk0000037c (
.I(\blk00000003/sig00000057 ),
.O(\blk00000003/sig0000014c )
);
INV \blk00000003/blk0000037b (
.I(\blk00000003/sig00000060 ),
.O(\blk00000003/sig00000127 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk0000037a (
.I0(\blk00000003/sig0000032b ),
.I1(\blk00000003/sig0000033a ),
.O(\blk00000003/sig0000030d )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000379 (
.I0(\blk00000003/sig00000324 ),
.I1(\blk00000003/sig0000006c ),
.I2(\blk00000003/sig0000033a ),
.O(\blk00000003/sig00000310 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000378 (
.I0(\blk00000003/sig00000325 ),
.I1(\blk00000003/sig0000006e ),
.I2(\blk00000003/sig0000033a ),
.O(\blk00000003/sig00000313 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000377 (
.I0(\blk00000003/sig00000326 ),
.I1(\blk00000003/sig00000070 ),
.I2(\blk00000003/sig0000033a ),
.O(\blk00000003/sig00000316 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000376 (
.I0(\blk00000003/sig00000327 ),
.I1(\blk00000003/sig00000072 ),
.I2(\blk00000003/sig0000033a ),
.O(\blk00000003/sig00000319 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000375 (
.I0(\blk00000003/sig00000328 ),
.I1(\blk00000003/sig00000074 ),
.I2(\blk00000003/sig0000033a ),
.O(\blk00000003/sig0000031c )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000374 (
.I0(\blk00000003/sig00000329 ),
.I1(\blk00000003/sig00000076 ),
.I2(\blk00000003/sig0000033a ),
.O(\blk00000003/sig0000031f )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000373 (
.I0(\blk00000003/sig0000032a ),
.I1(\blk00000003/sig00000078 ),
.I2(\blk00000003/sig0000033a ),
.O(\blk00000003/sig00000322 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000372 (
.I0(\blk00000003/sig0000007a ),
.I1(\blk00000003/sig0000033a ),
.O(\blk00000003/sig0000032e )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000371 (
.I0(\blk00000003/sig00000306 ),
.I1(\blk00000003/sig0000033b ),
.O(\blk00000003/sig000002e8 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000370 (
.I0(\blk00000003/sig000002ff ),
.I1(\blk00000003/sig0000006b ),
.I2(\blk00000003/sig0000033b ),
.O(\blk00000003/sig000002eb )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000036f (
.I0(\blk00000003/sig00000300 ),
.I1(\blk00000003/sig0000006d ),
.I2(\blk00000003/sig0000033b ),
.O(\blk00000003/sig000002ee )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000036e (
.I0(\blk00000003/sig00000301 ),
.I1(\blk00000003/sig0000006f ),
.I2(\blk00000003/sig0000033b ),
.O(\blk00000003/sig000002f1 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000036d (
.I0(\blk00000003/sig00000302 ),
.I1(\blk00000003/sig00000071 ),
.I2(\blk00000003/sig0000033b ),
.O(\blk00000003/sig000002f4 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000036c (
.I0(\blk00000003/sig00000303 ),
.I1(\blk00000003/sig00000073 ),
.I2(\blk00000003/sig0000033b ),
.O(\blk00000003/sig000002f7 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000036b (
.I0(\blk00000003/sig00000304 ),
.I1(\blk00000003/sig00000075 ),
.I2(\blk00000003/sig0000033b ),
.O(\blk00000003/sig000002fa )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000036a (
.I0(\blk00000003/sig00000305 ),
.I1(\blk00000003/sig00000077 ),
.I2(\blk00000003/sig0000033b ),
.O(\blk00000003/sig000002fd )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000369 (
.I0(\blk00000003/sig00000079 ),
.I1(\blk00000003/sig0000033b ),
.O(\blk00000003/sig00000309 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000368 (
.I0(\blk00000003/sig000002e1 ),
.I1(\blk00000003/sig0000033c ),
.O(\blk00000003/sig000002c3 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000367 (
.I0(\blk00000003/sig000002da ),
.I1(\blk00000003/sig0000007b ),
.I2(\blk00000003/sig0000033c ),
.O(\blk00000003/sig000002c6 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000366 (
.I0(\blk00000003/sig000002db ),
.I1(\blk00000003/sig0000007c ),
.I2(\blk00000003/sig0000033c ),
.O(\blk00000003/sig000002c9 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000365 (
.I0(\blk00000003/sig000002dc ),
.I1(\blk00000003/sig0000007d ),
.I2(\blk00000003/sig0000033c ),
.O(\blk00000003/sig000002cc )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000364 (
.I0(\blk00000003/sig000002dd ),
.I1(\blk00000003/sig0000007e ),
.I2(\blk00000003/sig0000033c ),
.O(\blk00000003/sig000002cf )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000363 (
.I0(\blk00000003/sig000002de ),
.I1(\blk00000003/sig0000007f ),
.I2(\blk00000003/sig0000033c ),
.O(\blk00000003/sig000002d2 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000362 (
.I0(\blk00000003/sig000002df ),
.I1(\blk00000003/sig00000080 ),
.I2(\blk00000003/sig0000033c ),
.O(\blk00000003/sig000002d5 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000361 (
.I0(\blk00000003/sig000002e0 ),
.I1(\blk00000003/sig00000081 ),
.I2(\blk00000003/sig0000033c ),
.O(\blk00000003/sig000002d8 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000360 (
.I0(\blk00000003/sig00000082 ),
.I1(\blk00000003/sig0000033c ),
.O(\blk00000003/sig000002e4 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk0000035f (
.I0(\blk00000003/sig000002bc ),
.I1(\blk00000003/sig0000033d ),
.O(\blk00000003/sig0000029e )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000035e (
.I0(\blk00000003/sig000002b5 ),
.I1(\blk00000003/sig00000083 ),
.I2(\blk00000003/sig0000033d ),
.O(\blk00000003/sig000002a1 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000035d (
.I0(\blk00000003/sig000002b6 ),
.I1(\blk00000003/sig00000084 ),
.I2(\blk00000003/sig0000033d ),
.O(\blk00000003/sig000002a4 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000035c (
.I0(\blk00000003/sig000002b7 ),
.I1(\blk00000003/sig00000085 ),
.I2(\blk00000003/sig0000033d ),
.O(\blk00000003/sig000002a7 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000035b (
.I0(\blk00000003/sig000002b8 ),
.I1(\blk00000003/sig00000086 ),
.I2(\blk00000003/sig0000033d ),
.O(\blk00000003/sig000002aa )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000035a (
.I0(\blk00000003/sig000002b9 ),
.I1(\blk00000003/sig00000087 ),
.I2(\blk00000003/sig0000033d ),
.O(\blk00000003/sig000002ad )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000359 (
.I0(\blk00000003/sig000002ba ),
.I1(\blk00000003/sig00000088 ),
.I2(\blk00000003/sig0000033d ),
.O(\blk00000003/sig000002b0 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000358 (
.I0(\blk00000003/sig000002bb ),
.I1(\blk00000003/sig00000089 ),
.I2(\blk00000003/sig0000033d ),
.O(\blk00000003/sig000002b3 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000357 (
.I0(\blk00000003/sig0000008a ),
.I1(\blk00000003/sig0000033d ),
.O(\blk00000003/sig000002bf )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000356 (
.I0(\blk00000003/sig00000297 ),
.I1(\blk00000003/sig0000033e ),
.O(\blk00000003/sig00000279 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000355 (
.I0(\blk00000003/sig00000290 ),
.I1(\blk00000003/sig0000008b ),
.I2(\blk00000003/sig0000033e ),
.O(\blk00000003/sig0000027c )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000354 (
.I0(\blk00000003/sig00000291 ),
.I1(\blk00000003/sig0000008c ),
.I2(\blk00000003/sig0000033e ),
.O(\blk00000003/sig0000027f )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000353 (
.I0(\blk00000003/sig00000292 ),
.I1(\blk00000003/sig0000008d ),
.I2(\blk00000003/sig0000033e ),
.O(\blk00000003/sig00000282 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000352 (
.I0(\blk00000003/sig00000293 ),
.I1(\blk00000003/sig0000008e ),
.I2(\blk00000003/sig0000033e ),
.O(\blk00000003/sig00000285 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000351 (
.I0(\blk00000003/sig00000294 ),
.I1(\blk00000003/sig0000008f ),
.I2(\blk00000003/sig0000033e ),
.O(\blk00000003/sig00000288 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000350 (
.I0(\blk00000003/sig00000295 ),
.I1(\blk00000003/sig00000090 ),
.I2(\blk00000003/sig0000033e ),
.O(\blk00000003/sig0000028b )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000034f (
.I0(\blk00000003/sig00000296 ),
.I1(\blk00000003/sig00000091 ),
.I2(\blk00000003/sig0000033e ),
.O(\blk00000003/sig0000028e )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk0000034e (
.I0(\blk00000003/sig00000092 ),
.I1(\blk00000003/sig0000033e ),
.O(\blk00000003/sig0000029a )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk0000034d (
.I0(\blk00000003/sig00000272 ),
.I1(\blk00000003/sig0000033f ),
.O(\blk00000003/sig00000254 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000034c (
.I0(\blk00000003/sig0000026b ),
.I1(\blk00000003/sig00000093 ),
.I2(\blk00000003/sig0000033f ),
.O(\blk00000003/sig00000257 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000034b (
.I0(\blk00000003/sig0000026c ),
.I1(\blk00000003/sig00000094 ),
.I2(\blk00000003/sig0000033f ),
.O(\blk00000003/sig0000025a )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000034a (
.I0(\blk00000003/sig0000026d ),
.I1(\blk00000003/sig00000095 ),
.I2(\blk00000003/sig0000033f ),
.O(\blk00000003/sig0000025d )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000349 (
.I0(\blk00000003/sig0000026e ),
.I1(\blk00000003/sig00000096 ),
.I2(\blk00000003/sig0000033f ),
.O(\blk00000003/sig00000260 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000348 (
.I0(\blk00000003/sig0000026f ),
.I1(\blk00000003/sig00000097 ),
.I2(\blk00000003/sig0000033f ),
.O(\blk00000003/sig00000263 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000347 (
.I0(\blk00000003/sig00000270 ),
.I1(\blk00000003/sig00000098 ),
.I2(\blk00000003/sig0000033f ),
.O(\blk00000003/sig00000266 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000346 (
.I0(\blk00000003/sig00000271 ),
.I1(\blk00000003/sig00000099 ),
.I2(\blk00000003/sig0000033f ),
.O(\blk00000003/sig00000269 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000345 (
.I0(\blk00000003/sig0000009a ),
.I1(\blk00000003/sig0000033f ),
.O(\blk00000003/sig00000275 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000344 (
.I0(\blk00000003/sig0000024d ),
.I1(\blk00000003/sig00000340 ),
.O(\blk00000003/sig0000022f )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000343 (
.I0(\blk00000003/sig00000246 ),
.I1(\blk00000003/sig0000009b ),
.I2(\blk00000003/sig00000340 ),
.O(\blk00000003/sig00000232 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000342 (
.I0(\blk00000003/sig00000247 ),
.I1(\blk00000003/sig0000009c ),
.I2(\blk00000003/sig00000340 ),
.O(\blk00000003/sig00000235 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000341 (
.I0(\blk00000003/sig00000248 ),
.I1(\blk00000003/sig0000009d ),
.I2(\blk00000003/sig00000340 ),
.O(\blk00000003/sig00000238 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000340 (
.I0(\blk00000003/sig00000249 ),
.I1(\blk00000003/sig0000009e ),
.I2(\blk00000003/sig00000340 ),
.O(\blk00000003/sig0000023b )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000033f (
.I0(\blk00000003/sig0000024a ),
.I1(\blk00000003/sig0000009f ),
.I2(\blk00000003/sig00000340 ),
.O(\blk00000003/sig0000023e )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000033e (
.I0(\blk00000003/sig0000024b ),
.I1(\blk00000003/sig000000a0 ),
.I2(\blk00000003/sig00000340 ),
.O(\blk00000003/sig00000241 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000033d (
.I0(\blk00000003/sig0000024c ),
.I1(\blk00000003/sig000000a1 ),
.I2(\blk00000003/sig00000340 ),
.O(\blk00000003/sig00000244 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk0000033c (
.I0(\blk00000003/sig000000a2 ),
.I1(\blk00000003/sig00000340 ),
.O(\blk00000003/sig00000250 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk0000033b (
.I0(\blk00000003/sig00000228 ),
.I1(\blk00000003/sig00000341 ),
.O(\blk00000003/sig0000020a )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000033a (
.I0(\blk00000003/sig00000221 ),
.I1(\blk00000003/sig000000a3 ),
.I2(\blk00000003/sig00000341 ),
.O(\blk00000003/sig0000020d )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000339 (
.I0(\blk00000003/sig00000222 ),
.I1(\blk00000003/sig000000a4 ),
.I2(\blk00000003/sig00000341 ),
.O(\blk00000003/sig00000210 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000338 (
.I0(\blk00000003/sig00000223 ),
.I1(\blk00000003/sig000000a5 ),
.I2(\blk00000003/sig00000341 ),
.O(\blk00000003/sig00000213 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000337 (
.I0(\blk00000003/sig00000224 ),
.I1(\blk00000003/sig000000a6 ),
.I2(\blk00000003/sig00000341 ),
.O(\blk00000003/sig00000216 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000336 (
.I0(\blk00000003/sig00000225 ),
.I1(\blk00000003/sig000000a7 ),
.I2(\blk00000003/sig00000341 ),
.O(\blk00000003/sig00000219 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000335 (
.I0(\blk00000003/sig00000226 ),
.I1(\blk00000003/sig000000a8 ),
.I2(\blk00000003/sig00000341 ),
.O(\blk00000003/sig0000021c )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000334 (
.I0(\blk00000003/sig00000227 ),
.I1(\blk00000003/sig000000a9 ),
.I2(\blk00000003/sig00000341 ),
.O(\blk00000003/sig0000021f )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000333 (
.I0(\blk00000003/sig000000aa ),
.I1(\blk00000003/sig00000341 ),
.O(\blk00000003/sig0000022b )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000332 (
.I0(\blk00000003/sig00000203 ),
.I1(\blk00000003/sig00000024 ),
.O(\blk00000003/sig000001e5 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000331 (
.I0(\blk00000003/sig000001fc ),
.I1(\blk00000003/sig000000ab ),
.I2(\blk00000003/sig00000024 ),
.O(\blk00000003/sig000001e8 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000330 (
.I0(\blk00000003/sig000001fd ),
.I1(\blk00000003/sig000000ac ),
.I2(\blk00000003/sig00000024 ),
.O(\blk00000003/sig000001eb )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000032f (
.I0(\blk00000003/sig000001fe ),
.I1(\blk00000003/sig000000ad ),
.I2(\blk00000003/sig00000024 ),
.O(\blk00000003/sig000001ee )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000032e (
.I0(\blk00000003/sig000001ff ),
.I1(\blk00000003/sig000000ae ),
.I2(\blk00000003/sig00000024 ),
.O(\blk00000003/sig000001f1 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000032d (
.I0(\blk00000003/sig00000200 ),
.I1(\blk00000003/sig000000af ),
.I2(\blk00000003/sig00000024 ),
.O(\blk00000003/sig000001f4 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000032c (
.I0(\blk00000003/sig00000201 ),
.I1(\blk00000003/sig000000b0 ),
.I2(\blk00000003/sig00000024 ),
.O(\blk00000003/sig000001f7 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000032b (
.I0(\blk00000003/sig00000202 ),
.I1(\blk00000003/sig000000b1 ),
.I2(\blk00000003/sig00000024 ),
.O(\blk00000003/sig000001fa )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000032a (
.I0(\blk00000003/sig00000069 ),
.I1(\blk00000003/sig000000b2 ),
.I2(\blk00000003/sig00000024 ),
.O(\blk00000003/sig00000206 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000329 (
.I0(\blk00000003/sig000001de ),
.I1(\blk00000003/sig00000032 ),
.O(\blk00000003/sig000001c0 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000328 (
.I0(\blk00000003/sig000001d7 ),
.I1(\blk00000003/sig000000b3 ),
.I2(\blk00000003/sig00000032 ),
.O(\blk00000003/sig000001c3 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000327 (
.I0(\blk00000003/sig000001d8 ),
.I1(\blk00000003/sig000000b4 ),
.I2(\blk00000003/sig00000032 ),
.O(\blk00000003/sig000001c6 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000326 (
.I0(\blk00000003/sig000001d9 ),
.I1(\blk00000003/sig000000b5 ),
.I2(\blk00000003/sig00000032 ),
.O(\blk00000003/sig000001c9 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000325 (
.I0(\blk00000003/sig000001da ),
.I1(\blk00000003/sig000000b6 ),
.I2(\blk00000003/sig00000032 ),
.O(\blk00000003/sig000001cc )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000324 (
.I0(\blk00000003/sig000001db ),
.I1(\blk00000003/sig000000b7 ),
.I2(\blk00000003/sig00000032 ),
.O(\blk00000003/sig000001cf )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000323 (
.I0(\blk00000003/sig000001dc ),
.I1(\blk00000003/sig000000b8 ),
.I2(\blk00000003/sig00000032 ),
.O(\blk00000003/sig000001d2 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000322 (
.I0(\blk00000003/sig000001dd ),
.I1(\blk00000003/sig000000b9 ),
.I2(\blk00000003/sig00000032 ),
.O(\blk00000003/sig000001d5 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000321 (
.I0(\blk00000003/sig0000003b ),
.I1(\blk00000003/sig000000ba ),
.I2(\blk00000003/sig00000032 ),
.O(\blk00000003/sig000001e1 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000320 (
.I0(\blk00000003/sig000001b9 ),
.I1(\blk00000003/sig0000003c ),
.O(\blk00000003/sig0000019b )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000031f (
.I0(\blk00000003/sig000001b2 ),
.I1(\blk00000003/sig000000bb ),
.I2(\blk00000003/sig0000003c ),
.O(\blk00000003/sig0000019e )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000031e (
.I0(\blk00000003/sig000001b3 ),
.I1(\blk00000003/sig000000bc ),
.I2(\blk00000003/sig0000003c ),
.O(\blk00000003/sig000001a1 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000031d (
.I0(\blk00000003/sig000001b4 ),
.I1(\blk00000003/sig000000bd ),
.I2(\blk00000003/sig0000003c ),
.O(\blk00000003/sig000001a4 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000031c (
.I0(\blk00000003/sig000001b5 ),
.I1(\blk00000003/sig000000be ),
.I2(\blk00000003/sig0000003c ),
.O(\blk00000003/sig000001a7 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000031b (
.I0(\blk00000003/sig000001b6 ),
.I1(\blk00000003/sig000000bf ),
.I2(\blk00000003/sig0000003c ),
.O(\blk00000003/sig000001aa )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000031a (
.I0(\blk00000003/sig000001b7 ),
.I1(\blk00000003/sig000000c0 ),
.I2(\blk00000003/sig0000003c ),
.O(\blk00000003/sig000001ad )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000319 (
.I0(\blk00000003/sig000001b8 ),
.I1(\blk00000003/sig000000c1 ),
.I2(\blk00000003/sig0000003c ),
.O(\blk00000003/sig000001b0 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000318 (
.I0(\blk00000003/sig00000044 ),
.I1(\blk00000003/sig000000c2 ),
.I2(\blk00000003/sig0000003c ),
.O(\blk00000003/sig000001bc )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000317 (
.I0(\blk00000003/sig00000194 ),
.I1(\blk00000003/sig00000045 ),
.O(\blk00000003/sig00000176 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000316 (
.I0(\blk00000003/sig0000018d ),
.I1(\blk00000003/sig000000c3 ),
.I2(\blk00000003/sig00000045 ),
.O(\blk00000003/sig00000179 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000315 (
.I0(\blk00000003/sig0000018e ),
.I1(\blk00000003/sig000000c4 ),
.I2(\blk00000003/sig00000045 ),
.O(\blk00000003/sig0000017c )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000314 (
.I0(\blk00000003/sig0000018f ),
.I1(\blk00000003/sig000000c5 ),
.I2(\blk00000003/sig00000045 ),
.O(\blk00000003/sig0000017f )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000313 (
.I0(\blk00000003/sig00000190 ),
.I1(\blk00000003/sig000000c6 ),
.I2(\blk00000003/sig00000045 ),
.O(\blk00000003/sig00000182 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000312 (
.I0(\blk00000003/sig00000191 ),
.I1(\blk00000003/sig000000c7 ),
.I2(\blk00000003/sig00000045 ),
.O(\blk00000003/sig00000185 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000311 (
.I0(\blk00000003/sig00000192 ),
.I1(\blk00000003/sig000000c8 ),
.I2(\blk00000003/sig00000045 ),
.O(\blk00000003/sig00000188 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000310 (
.I0(\blk00000003/sig00000193 ),
.I1(\blk00000003/sig000000c9 ),
.I2(\blk00000003/sig00000045 ),
.O(\blk00000003/sig0000018b )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000030f (
.I0(\blk00000003/sig0000004d ),
.I1(\blk00000003/sig000000ca ),
.I2(\blk00000003/sig00000045 ),
.O(\blk00000003/sig00000197 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk0000030e (
.I0(\blk00000003/sig0000016f ),
.I1(\blk00000003/sig0000004e ),
.O(\blk00000003/sig00000151 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000030d (
.I0(\blk00000003/sig00000168 ),
.I1(\blk00000003/sig000000cb ),
.I2(\blk00000003/sig0000004e ),
.O(\blk00000003/sig00000154 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000030c (
.I0(\blk00000003/sig00000169 ),
.I1(\blk00000003/sig000000cc ),
.I2(\blk00000003/sig0000004e ),
.O(\blk00000003/sig00000157 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000030b (
.I0(\blk00000003/sig0000016a ),
.I1(\blk00000003/sig000000cd ),
.I2(\blk00000003/sig0000004e ),
.O(\blk00000003/sig0000015a )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk0000030a (
.I0(\blk00000003/sig0000016b ),
.I1(\blk00000003/sig000000ce ),
.I2(\blk00000003/sig0000004e ),
.O(\blk00000003/sig0000015d )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000309 (
.I0(\blk00000003/sig0000016c ),
.I1(\blk00000003/sig000000cf ),
.I2(\blk00000003/sig0000004e ),
.O(\blk00000003/sig00000160 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000308 (
.I0(\blk00000003/sig0000016d ),
.I1(\blk00000003/sig000000d0 ),
.I2(\blk00000003/sig0000004e ),
.O(\blk00000003/sig00000163 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000307 (
.I0(\blk00000003/sig0000016e ),
.I1(\blk00000003/sig000000d1 ),
.I2(\blk00000003/sig0000004e ),
.O(\blk00000003/sig00000166 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000306 (
.I0(\blk00000003/sig00000056 ),
.I1(\blk00000003/sig000000d2 ),
.I2(\blk00000003/sig0000004e ),
.O(\blk00000003/sig00000172 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk00000305 (
.I0(\blk00000003/sig0000014a ),
.I1(\blk00000003/sig00000057 ),
.O(\blk00000003/sig0000012c )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000304 (
.I0(\blk00000003/sig00000143 ),
.I1(\blk00000003/sig000000d3 ),
.I2(\blk00000003/sig00000057 ),
.O(\blk00000003/sig0000012f )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000303 (
.I0(\blk00000003/sig00000144 ),
.I1(\blk00000003/sig000000d4 ),
.I2(\blk00000003/sig00000057 ),
.O(\blk00000003/sig00000132 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000302 (
.I0(\blk00000003/sig00000145 ),
.I1(\blk00000003/sig000000d5 ),
.I2(\blk00000003/sig00000057 ),
.O(\blk00000003/sig00000135 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000301 (
.I0(\blk00000003/sig00000146 ),
.I1(\blk00000003/sig000000d6 ),
.I2(\blk00000003/sig00000057 ),
.O(\blk00000003/sig00000138 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk00000300 (
.I0(\blk00000003/sig00000147 ),
.I1(\blk00000003/sig000000d7 ),
.I2(\blk00000003/sig00000057 ),
.O(\blk00000003/sig0000013b )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk000002ff (
.I0(\blk00000003/sig00000148 ),
.I1(\blk00000003/sig000000d8 ),
.I2(\blk00000003/sig00000057 ),
.O(\blk00000003/sig0000013e )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk000002fe (
.I0(\blk00000003/sig00000149 ),
.I1(\blk00000003/sig000000d9 ),
.I2(\blk00000003/sig00000057 ),
.O(\blk00000003/sig00000141 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk000002fd (
.I0(\blk00000003/sig0000005f ),
.I1(\blk00000003/sig000000da ),
.I2(\blk00000003/sig00000057 ),
.O(\blk00000003/sig0000014d )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk000002fc (
.I0(\blk00000003/sig00000125 ),
.I1(\blk00000003/sig00000060 ),
.O(\blk00000003/sig00000107 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk000002fb (
.I0(\blk00000003/sig0000011e ),
.I1(\blk00000003/sig000000db ),
.I2(\blk00000003/sig00000060 ),
.O(\blk00000003/sig0000010a )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk000002fa (
.I0(\blk00000003/sig0000011f ),
.I1(\blk00000003/sig000000dc ),
.I2(\blk00000003/sig00000060 ),
.O(\blk00000003/sig0000010d )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk000002f9 (
.I0(\blk00000003/sig00000120 ),
.I1(\blk00000003/sig000000dd ),
.I2(\blk00000003/sig00000060 ),
.O(\blk00000003/sig00000110 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk000002f8 (
.I0(\blk00000003/sig00000121 ),
.I1(\blk00000003/sig000000de ),
.I2(\blk00000003/sig00000060 ),
.O(\blk00000003/sig00000113 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk000002f7 (
.I0(\blk00000003/sig00000122 ),
.I1(\blk00000003/sig000000df ),
.I2(\blk00000003/sig00000060 ),
.O(\blk00000003/sig00000116 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk000002f6 (
.I0(\blk00000003/sig00000123 ),
.I1(\blk00000003/sig000000e0 ),
.I2(\blk00000003/sig00000060 ),
.O(\blk00000003/sig00000119 )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk000002f5 (
.I0(\blk00000003/sig00000124 ),
.I1(\blk00000003/sig000000e1 ),
.I2(\blk00000003/sig00000060 ),
.O(\blk00000003/sig0000011c )
);
LUT3 #(
.INIT ( 8'h69 ))
\blk00000003/blk000002f4 (
.I0(\blk00000003/sig00000068 ),
.I1(\blk00000003/sig000000e2 ),
.I2(\blk00000003/sig00000060 ),
.O(\blk00000003/sig00000128 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000003/blk000002f3 (
.I0(\blk00000003/sig0000006a ),
.I1(\blk00000003/sig000000ea ),
.O(\blk00000003/sig00000103 )
);
LUT1 #(
.INIT ( 2'h1 ))
\blk00000003/blk000002f2 (
.I0(\blk00000003/sig00000331 ),
.O(\blk00000003/sig000003ad )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002f1 (
.C(clk),
.D(\blk00000003/sig000003ad ),
.Q(fractional_3[0])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002f0 (
.C(clk),
.D(\blk00000003/sig000003ac ),
.Q(fractional_3[1])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002ef (
.C(clk),
.D(\blk00000003/sig000003ab ),
.Q(fractional_3[2])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002ee (
.C(clk),
.D(\blk00000003/sig000003aa ),
.Q(fractional_3[3])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002ed (
.C(clk),
.D(\blk00000003/sig000003a9 ),
.Q(fractional_3[4])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002ec (
.C(clk),
.D(\blk00000003/sig000003a8 ),
.Q(fractional_3[5])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002eb (
.C(clk),
.D(\blk00000003/sig000003a7 ),
.Q(fractional_3[6])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002ea (
.C(clk),
.D(\blk00000003/sig000003a6 ),
.Q(fractional_3[7])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002e9 (
.C(clk),
.D(\blk00000003/sig000003a5 ),
.Q(quotient_2[0])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002e8 (
.C(clk),
.D(\blk00000003/sig000003a4 ),
.Q(quotient_2[1])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002e7 (
.C(clk),
.D(\blk00000003/sig000003a3 ),
.Q(quotient_2[2])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002e6 (
.C(clk),
.D(\blk00000003/sig000003a2 ),
.Q(quotient_2[3])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002e5 (
.C(clk),
.D(\blk00000003/sig000003a1 ),
.Q(quotient_2[4])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002e4 (
.C(clk),
.D(\blk00000003/sig000003a0 ),
.Q(quotient_2[5])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002e3 (
.C(clk),
.D(\blk00000003/sig0000039f ),
.Q(quotient_2[6])
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000002e2 (
.C(clk),
.D(\blk00000003/sig0000039e ),
.Q(quotient_2[7])
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002e1 (
.C(clk),
.D(\blk00000003/sig0000033a ),
.Q(\blk00000003/sig0000039d )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002e0 (
.C(clk),
.D(\blk00000003/sig0000038e ),
.Q(\blk00000003/sig0000039c )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002df (
.C(clk),
.D(\blk00000003/sig0000038d ),
.Q(\blk00000003/sig0000039b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002de (
.C(clk),
.D(\blk00000003/sig0000038c ),
.Q(\blk00000003/sig0000039a )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002dd (
.C(clk),
.D(\blk00000003/sig0000038b ),
.Q(\blk00000003/sig00000399 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002dc (
.C(clk),
.D(\blk00000003/sig0000038a ),
.Q(\blk00000003/sig00000398 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002db (
.C(clk),
.D(\blk00000003/sig00000389 ),
.Q(\blk00000003/sig00000397 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002da (
.C(clk),
.D(\blk00000003/sig00000388 ),
.Q(\blk00000003/sig00000396 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002d9 (
.C(clk),
.D(\blk00000003/sig00000387 ),
.Q(\blk00000003/sig00000395 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002d8 (
.C(clk),
.D(\blk00000003/sig00000386 ),
.Q(\blk00000003/sig00000394 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002d7 (
.C(clk),
.D(\blk00000003/sig00000385 ),
.Q(\blk00000003/sig00000393 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002d6 (
.C(clk),
.D(\blk00000003/sig00000384 ),
.Q(\blk00000003/sig00000392 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002d5 (
.C(clk),
.D(\blk00000003/sig00000383 ),
.Q(\blk00000003/sig00000391 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002d4 (
.C(clk),
.D(\blk00000003/sig00000382 ),
.Q(\blk00000003/sig00000390 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002d3 (
.C(clk),
.D(\blk00000003/sig00000381 ),
.Q(\blk00000003/sig0000038f )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002d2 (
.C(clk),
.D(\blk00000003/sig0000033b ),
.Q(\blk00000003/sig0000038e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002d1 (
.C(clk),
.D(\blk00000003/sig00000380 ),
.Q(\blk00000003/sig0000038d )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002d0 (
.C(clk),
.D(\blk00000003/sig0000037f ),
.Q(\blk00000003/sig0000038c )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002cf (
.C(clk),
.D(\blk00000003/sig0000037e ),
.Q(\blk00000003/sig0000038b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002ce (
.C(clk),
.D(\blk00000003/sig0000037d ),
.Q(\blk00000003/sig0000038a )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002cd (
.C(clk),
.D(\blk00000003/sig0000037c ),
.Q(\blk00000003/sig00000389 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002cc (
.C(clk),
.D(\blk00000003/sig0000037b ),
.Q(\blk00000003/sig00000388 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002cb (
.C(clk),
.D(\blk00000003/sig0000037a ),
.Q(\blk00000003/sig00000387 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002ca (
.C(clk),
.D(\blk00000003/sig00000379 ),
.Q(\blk00000003/sig00000386 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002c9 (
.C(clk),
.D(\blk00000003/sig00000378 ),
.Q(\blk00000003/sig00000385 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002c8 (
.C(clk),
.D(\blk00000003/sig00000377 ),
.Q(\blk00000003/sig00000384 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002c7 (
.C(clk),
.D(\blk00000003/sig00000376 ),
.Q(\blk00000003/sig00000383 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002c6 (
.C(clk),
.D(\blk00000003/sig00000375 ),
.Q(\blk00000003/sig00000382 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002c5 (
.C(clk),
.D(\blk00000003/sig00000374 ),
.Q(\blk00000003/sig00000381 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002c4 (
.C(clk),
.D(\blk00000003/sig0000033c ),
.Q(\blk00000003/sig00000380 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002c3 (
.C(clk),
.D(\blk00000003/sig00000373 ),
.Q(\blk00000003/sig0000037f )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002c2 (
.C(clk),
.D(\blk00000003/sig00000372 ),
.Q(\blk00000003/sig0000037e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002c1 (
.C(clk),
.D(\blk00000003/sig00000371 ),
.Q(\blk00000003/sig0000037d )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002c0 (
.C(clk),
.D(\blk00000003/sig00000370 ),
.Q(\blk00000003/sig0000037c )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002bf (
.C(clk),
.D(\blk00000003/sig0000036f ),
.Q(\blk00000003/sig0000037b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002be (
.C(clk),
.D(\blk00000003/sig0000036e ),
.Q(\blk00000003/sig0000037a )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002bd (
.C(clk),
.D(\blk00000003/sig0000036d ),
.Q(\blk00000003/sig00000379 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002bc (
.C(clk),
.D(\blk00000003/sig0000036c ),
.Q(\blk00000003/sig00000378 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002bb (
.C(clk),
.D(\blk00000003/sig0000036b ),
.Q(\blk00000003/sig00000377 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002ba (
.C(clk),
.D(\blk00000003/sig0000036a ),
.Q(\blk00000003/sig00000376 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002b9 (
.C(clk),
.D(\blk00000003/sig00000369 ),
.Q(\blk00000003/sig00000375 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002b8 (
.C(clk),
.D(\blk00000003/sig00000368 ),
.Q(\blk00000003/sig00000374 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002b7 (
.C(clk),
.D(\blk00000003/sig0000033d ),
.Q(\blk00000003/sig00000373 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002b6 (
.C(clk),
.D(\blk00000003/sig00000367 ),
.Q(\blk00000003/sig00000372 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002b5 (
.C(clk),
.D(\blk00000003/sig00000366 ),
.Q(\blk00000003/sig00000371 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002b4 (
.C(clk),
.D(\blk00000003/sig00000365 ),
.Q(\blk00000003/sig00000370 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002b3 (
.C(clk),
.D(\blk00000003/sig00000364 ),
.Q(\blk00000003/sig0000036f )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002b2 (
.C(clk),
.D(\blk00000003/sig00000363 ),
.Q(\blk00000003/sig0000036e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002b1 (
.C(clk),
.D(\blk00000003/sig00000362 ),
.Q(\blk00000003/sig0000036d )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002b0 (
.C(clk),
.D(\blk00000003/sig00000361 ),
.Q(\blk00000003/sig0000036c )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002af (
.C(clk),
.D(\blk00000003/sig00000360 ),
.Q(\blk00000003/sig0000036b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002ae (
.C(clk),
.D(\blk00000003/sig0000035f ),
.Q(\blk00000003/sig0000036a )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002ad (
.C(clk),
.D(\blk00000003/sig0000035e ),
.Q(\blk00000003/sig00000369 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002ac (
.C(clk),
.D(\blk00000003/sig0000035d ),
.Q(\blk00000003/sig00000368 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002ab (
.C(clk),
.D(\blk00000003/sig0000033e ),
.Q(\blk00000003/sig00000367 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002aa (
.C(clk),
.D(\blk00000003/sig0000035c ),
.Q(\blk00000003/sig00000366 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002a9 (
.C(clk),
.D(\blk00000003/sig0000035b ),
.Q(\blk00000003/sig00000365 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002a8 (
.C(clk),
.D(\blk00000003/sig0000035a ),
.Q(\blk00000003/sig00000364 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002a7 (
.C(clk),
.D(\blk00000003/sig00000359 ),
.Q(\blk00000003/sig00000363 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002a6 (
.C(clk),
.D(\blk00000003/sig00000358 ),
.Q(\blk00000003/sig00000362 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002a5 (
.C(clk),
.D(\blk00000003/sig00000357 ),
.Q(\blk00000003/sig00000361 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002a4 (
.C(clk),
.D(\blk00000003/sig00000356 ),
.Q(\blk00000003/sig00000360 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002a3 (
.C(clk),
.D(\blk00000003/sig00000355 ),
.Q(\blk00000003/sig0000035f )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002a2 (
.C(clk),
.D(\blk00000003/sig00000354 ),
.Q(\blk00000003/sig0000035e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002a1 (
.C(clk),
.D(\blk00000003/sig00000353 ),
.Q(\blk00000003/sig0000035d )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000002a0 (
.C(clk),
.D(\blk00000003/sig0000033f ),
.Q(\blk00000003/sig0000035c )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000029f (
.C(clk),
.D(\blk00000003/sig00000352 ),
.Q(\blk00000003/sig0000035b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000029e (
.C(clk),
.D(\blk00000003/sig00000351 ),
.Q(\blk00000003/sig0000035a )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000029d (
.C(clk),
.D(\blk00000003/sig0000034f ),
.Q(\blk00000003/sig00000359 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000029c (
.C(clk),
.D(\blk00000003/sig0000034d ),
.Q(\blk00000003/sig00000358 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000029b (
.C(clk),
.D(\blk00000003/sig0000034b ),
.Q(\blk00000003/sig00000357 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000029a (
.C(clk),
.D(\blk00000003/sig00000349 ),
.Q(\blk00000003/sig00000356 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000299 (
.C(clk),
.D(\blk00000003/sig00000347 ),
.Q(\blk00000003/sig00000355 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000298 (
.C(clk),
.D(\blk00000003/sig00000345 ),
.Q(\blk00000003/sig00000354 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000297 (
.C(clk),
.D(\blk00000003/sig00000343 ),
.Q(\blk00000003/sig00000353 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000296 (
.C(clk),
.D(\blk00000003/sig00000341 ),
.Q(\blk00000003/sig00000350 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000295 (
.C(clk),
.D(\blk00000003/sig00000025 ),
.Q(\blk00000003/sig0000034e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000294 (
.C(clk),
.D(\blk00000003/sig00000027 ),
.Q(\blk00000003/sig0000034c )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000293 (
.C(clk),
.D(\blk00000003/sig00000029 ),
.Q(\blk00000003/sig0000034a )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000292 (
.C(clk),
.D(\blk00000003/sig0000002b ),
.Q(\blk00000003/sig00000348 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000291 (
.C(clk),
.D(\blk00000003/sig0000002d ),
.Q(\blk00000003/sig00000346 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000290 (
.C(clk),
.D(\blk00000003/sig0000002f ),
.Q(\blk00000003/sig00000344 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000028f (
.C(clk),
.D(\blk00000003/sig00000031 ),
.Q(\blk00000003/sig00000342 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000028e (
.C(clk),
.D(\blk00000003/sig00000340 ),
.Q(\blk00000003/sig00000352 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000028d (
.C(clk),
.D(\blk00000003/sig00000350 ),
.Q(\blk00000003/sig00000351 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000028c (
.C(clk),
.D(\blk00000003/sig0000034e ),
.Q(\blk00000003/sig0000034f )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000028b (
.C(clk),
.D(\blk00000003/sig0000034c ),
.Q(\blk00000003/sig0000034d )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000028a (
.C(clk),
.D(\blk00000003/sig0000034a ),
.Q(\blk00000003/sig0000034b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000289 (
.C(clk),
.D(\blk00000003/sig00000348 ),
.Q(\blk00000003/sig00000349 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000288 (
.C(clk),
.D(\blk00000003/sig00000346 ),
.Q(\blk00000003/sig00000347 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000287 (
.C(clk),
.D(\blk00000003/sig00000344 ),
.Q(\blk00000003/sig00000345 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000286 (
.C(clk),
.D(\blk00000003/sig00000342 ),
.Q(\blk00000003/sig00000343 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000285 (
.C(clk),
.D(\blk00000003/sig00000104 ),
.Q(\blk00000003/sig00000124 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000284 (
.C(clk),
.D(\blk00000003/sig00000101 ),
.Q(\blk00000003/sig00000123 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000283 (
.C(clk),
.D(\blk00000003/sig000000fe ),
.Q(\blk00000003/sig00000122 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000282 (
.C(clk),
.D(\blk00000003/sig000000fb ),
.Q(\blk00000003/sig00000121 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000281 (
.C(clk),
.D(\blk00000003/sig000000f8 ),
.Q(\blk00000003/sig00000120 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000280 (
.C(clk),
.D(\blk00000003/sig000000f5 ),
.Q(\blk00000003/sig0000011f )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000027f (
.C(clk),
.D(\blk00000003/sig000000f2 ),
.Q(\blk00000003/sig0000011e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000027e (
.C(clk),
.D(\blk00000003/sig000000ef ),
.Q(\blk00000003/sig00000125 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000027d (
.C(clk),
.D(\blk00000003/sig000000ec ),
.Q(\blk00000003/sig00000060 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000027c (
.C(clk),
.D(\blk00000003/sig00000129 ),
.Q(\blk00000003/sig00000149 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000027b (
.C(clk),
.D(\blk00000003/sig0000011d ),
.Q(\blk00000003/sig00000148 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000027a (
.C(clk),
.D(\blk00000003/sig0000011a ),
.Q(\blk00000003/sig00000147 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000279 (
.C(clk),
.D(\blk00000003/sig00000117 ),
.Q(\blk00000003/sig00000146 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000278 (
.C(clk),
.D(\blk00000003/sig00000114 ),
.Q(\blk00000003/sig00000145 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000277 (
.C(clk),
.D(\blk00000003/sig00000111 ),
.Q(\blk00000003/sig00000144 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000276 (
.C(clk),
.D(\blk00000003/sig0000010e ),
.Q(\blk00000003/sig00000143 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000275 (
.C(clk),
.D(\blk00000003/sig0000010b ),
.Q(\blk00000003/sig0000014a )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000274 (
.C(clk),
.D(\blk00000003/sig00000108 ),
.Q(\blk00000003/sig00000057 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000273 (
.C(clk),
.D(\blk00000003/sig0000014e ),
.Q(\blk00000003/sig0000016e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000272 (
.C(clk),
.D(\blk00000003/sig00000142 ),
.Q(\blk00000003/sig0000016d )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000271 (
.C(clk),
.D(\blk00000003/sig0000013f ),
.Q(\blk00000003/sig0000016c )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000270 (
.C(clk),
.D(\blk00000003/sig0000013c ),
.Q(\blk00000003/sig0000016b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000026f (
.C(clk),
.D(\blk00000003/sig00000139 ),
.Q(\blk00000003/sig0000016a )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000026e (
.C(clk),
.D(\blk00000003/sig00000136 ),
.Q(\blk00000003/sig00000169 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000026d (
.C(clk),
.D(\blk00000003/sig00000133 ),
.Q(\blk00000003/sig00000168 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000026c (
.C(clk),
.D(\blk00000003/sig00000130 ),
.Q(\blk00000003/sig0000016f )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000026b (
.C(clk),
.D(\blk00000003/sig0000012d ),
.Q(\blk00000003/sig0000004e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000026a (
.C(clk),
.D(\blk00000003/sig00000173 ),
.Q(\blk00000003/sig00000193 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000269 (
.C(clk),
.D(\blk00000003/sig00000167 ),
.Q(\blk00000003/sig00000192 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000268 (
.C(clk),
.D(\blk00000003/sig00000164 ),
.Q(\blk00000003/sig00000191 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000267 (
.C(clk),
.D(\blk00000003/sig00000161 ),
.Q(\blk00000003/sig00000190 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000266 (
.C(clk),
.D(\blk00000003/sig0000015e ),
.Q(\blk00000003/sig0000018f )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000265 (
.C(clk),
.D(\blk00000003/sig0000015b ),
.Q(\blk00000003/sig0000018e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000264 (
.C(clk),
.D(\blk00000003/sig00000158 ),
.Q(\blk00000003/sig0000018d )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000263 (
.C(clk),
.D(\blk00000003/sig00000155 ),
.Q(\blk00000003/sig00000194 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000262 (
.C(clk),
.D(\blk00000003/sig00000152 ),
.Q(\blk00000003/sig00000045 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000261 (
.C(clk),
.D(\blk00000003/sig00000198 ),
.Q(\blk00000003/sig000001b8 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000260 (
.C(clk),
.D(\blk00000003/sig0000018c ),
.Q(\blk00000003/sig000001b7 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000025f (
.C(clk),
.D(\blk00000003/sig00000189 ),
.Q(\blk00000003/sig000001b6 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000025e (
.C(clk),
.D(\blk00000003/sig00000186 ),
.Q(\blk00000003/sig000001b5 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000025d (
.C(clk),
.D(\blk00000003/sig00000183 ),
.Q(\blk00000003/sig000001b4 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000025c (
.C(clk),
.D(\blk00000003/sig00000180 ),
.Q(\blk00000003/sig000001b3 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000025b (
.C(clk),
.D(\blk00000003/sig0000017d ),
.Q(\blk00000003/sig000001b2 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000025a (
.C(clk),
.D(\blk00000003/sig0000017a ),
.Q(\blk00000003/sig000001b9 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000259 (
.C(clk),
.D(\blk00000003/sig00000177 ),
.Q(\blk00000003/sig0000003c )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000258 (
.C(clk),
.D(\blk00000003/sig000001bd ),
.Q(\blk00000003/sig000001dd )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000257 (
.C(clk),
.D(\blk00000003/sig000001b1 ),
.Q(\blk00000003/sig000001dc )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000256 (
.C(clk),
.D(\blk00000003/sig000001ae ),
.Q(\blk00000003/sig000001db )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000255 (
.C(clk),
.D(\blk00000003/sig000001ab ),
.Q(\blk00000003/sig000001da )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000254 (
.C(clk),
.D(\blk00000003/sig000001a8 ),
.Q(\blk00000003/sig000001d9 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000253 (
.C(clk),
.D(\blk00000003/sig000001a5 ),
.Q(\blk00000003/sig000001d8 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000252 (
.C(clk),
.D(\blk00000003/sig000001a2 ),
.Q(\blk00000003/sig000001d7 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000251 (
.C(clk),
.D(\blk00000003/sig0000019f ),
.Q(\blk00000003/sig000001de )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000250 (
.C(clk),
.D(\blk00000003/sig0000019c ),
.Q(\blk00000003/sig00000032 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000024f (
.C(clk),
.D(\blk00000003/sig000001e2 ),
.Q(\blk00000003/sig00000202 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000024e (
.C(clk),
.D(\blk00000003/sig000001d6 ),
.Q(\blk00000003/sig00000201 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000024d (
.C(clk),
.D(\blk00000003/sig000001d3 ),
.Q(\blk00000003/sig00000200 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000024c (
.C(clk),
.D(\blk00000003/sig000001d0 ),
.Q(\blk00000003/sig000001ff )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000024b (
.C(clk),
.D(\blk00000003/sig000001cd ),
.Q(\blk00000003/sig000001fe )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000024a (
.C(clk),
.D(\blk00000003/sig000001ca ),
.Q(\blk00000003/sig000001fd )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000249 (
.C(clk),
.D(\blk00000003/sig000001c7 ),
.Q(\blk00000003/sig000001fc )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000248 (
.C(clk),
.D(\blk00000003/sig000001c4 ),
.Q(\blk00000003/sig00000203 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000247 (
.C(clk),
.D(\blk00000003/sig000001c1 ),
.Q(\blk00000003/sig00000024 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000246 (
.C(clk),
.D(\blk00000003/sig00000207 ),
.Q(\blk00000003/sig00000227 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000245 (
.C(clk),
.D(\blk00000003/sig000001fb ),
.Q(\blk00000003/sig00000226 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000244 (
.C(clk),
.D(\blk00000003/sig000001f8 ),
.Q(\blk00000003/sig00000225 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000243 (
.C(clk),
.D(\blk00000003/sig000001f5 ),
.Q(\blk00000003/sig00000224 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000242 (
.C(clk),
.D(\blk00000003/sig000001f2 ),
.Q(\blk00000003/sig00000223 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000241 (
.C(clk),
.D(\blk00000003/sig000001ef ),
.Q(\blk00000003/sig00000222 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000240 (
.C(clk),
.D(\blk00000003/sig000001ec ),
.Q(\blk00000003/sig00000221 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000023f (
.C(clk),
.D(\blk00000003/sig000001e9 ),
.Q(\blk00000003/sig00000228 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000023e (
.C(clk),
.D(\blk00000003/sig000001e6 ),
.Q(\blk00000003/sig00000341 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000023d (
.C(clk),
.D(\blk00000003/sig0000022c ),
.Q(\blk00000003/sig0000024c )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000023c (
.C(clk),
.D(\blk00000003/sig00000220 ),
.Q(\blk00000003/sig0000024b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000023b (
.C(clk),
.D(\blk00000003/sig0000021d ),
.Q(\blk00000003/sig0000024a )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000023a (
.C(clk),
.D(\blk00000003/sig0000021a ),
.Q(\blk00000003/sig00000249 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000239 (
.C(clk),
.D(\blk00000003/sig00000217 ),
.Q(\blk00000003/sig00000248 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000238 (
.C(clk),
.D(\blk00000003/sig00000214 ),
.Q(\blk00000003/sig00000247 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000237 (
.C(clk),
.D(\blk00000003/sig00000211 ),
.Q(\blk00000003/sig00000246 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000236 (
.C(clk),
.D(\blk00000003/sig0000020e ),
.Q(\blk00000003/sig0000024d )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000235 (
.C(clk),
.D(\blk00000003/sig0000020b ),
.Q(\blk00000003/sig00000340 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000234 (
.C(clk),
.D(\blk00000003/sig00000251 ),
.Q(\blk00000003/sig00000271 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000233 (
.C(clk),
.D(\blk00000003/sig00000245 ),
.Q(\blk00000003/sig00000270 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000232 (
.C(clk),
.D(\blk00000003/sig00000242 ),
.Q(\blk00000003/sig0000026f )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000231 (
.C(clk),
.D(\blk00000003/sig0000023f ),
.Q(\blk00000003/sig0000026e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000230 (
.C(clk),
.D(\blk00000003/sig0000023c ),
.Q(\blk00000003/sig0000026d )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000022f (
.C(clk),
.D(\blk00000003/sig00000239 ),
.Q(\blk00000003/sig0000026c )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000022e (
.C(clk),
.D(\blk00000003/sig00000236 ),
.Q(\blk00000003/sig0000026b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000022d (
.C(clk),
.D(\blk00000003/sig00000233 ),
.Q(\blk00000003/sig00000272 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000022c (
.C(clk),
.D(\blk00000003/sig00000230 ),
.Q(\blk00000003/sig0000033f )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000022b (
.C(clk),
.D(\blk00000003/sig00000276 ),
.Q(\blk00000003/sig00000296 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000022a (
.C(clk),
.D(\blk00000003/sig0000026a ),
.Q(\blk00000003/sig00000295 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000229 (
.C(clk),
.D(\blk00000003/sig00000267 ),
.Q(\blk00000003/sig00000294 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000228 (
.C(clk),
.D(\blk00000003/sig00000264 ),
.Q(\blk00000003/sig00000293 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000227 (
.C(clk),
.D(\blk00000003/sig00000261 ),
.Q(\blk00000003/sig00000292 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000226 (
.C(clk),
.D(\blk00000003/sig0000025e ),
.Q(\blk00000003/sig00000291 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000225 (
.C(clk),
.D(\blk00000003/sig0000025b ),
.Q(\blk00000003/sig00000290 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000224 (
.C(clk),
.D(\blk00000003/sig00000258 ),
.Q(\blk00000003/sig00000297 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000223 (
.C(clk),
.D(\blk00000003/sig00000255 ),
.Q(\blk00000003/sig0000033e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000222 (
.C(clk),
.D(\blk00000003/sig0000029b ),
.Q(\blk00000003/sig000002bb )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000221 (
.C(clk),
.D(\blk00000003/sig0000028f ),
.Q(\blk00000003/sig000002ba )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000220 (
.C(clk),
.D(\blk00000003/sig0000028c ),
.Q(\blk00000003/sig000002b9 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000021f (
.C(clk),
.D(\blk00000003/sig00000289 ),
.Q(\blk00000003/sig000002b8 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000021e (
.C(clk),
.D(\blk00000003/sig00000286 ),
.Q(\blk00000003/sig000002b7 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000021d (
.C(clk),
.D(\blk00000003/sig00000283 ),
.Q(\blk00000003/sig000002b6 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000021c (
.C(clk),
.D(\blk00000003/sig00000280 ),
.Q(\blk00000003/sig000002b5 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000021b (
.C(clk),
.D(\blk00000003/sig0000027d ),
.Q(\blk00000003/sig000002bc )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000021a (
.C(clk),
.D(\blk00000003/sig0000027a ),
.Q(\blk00000003/sig0000033d )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000219 (
.C(clk),
.D(\blk00000003/sig000002c0 ),
.Q(\blk00000003/sig000002e0 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000218 (
.C(clk),
.D(\blk00000003/sig000002b4 ),
.Q(\blk00000003/sig000002df )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000217 (
.C(clk),
.D(\blk00000003/sig000002b1 ),
.Q(\blk00000003/sig000002de )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000216 (
.C(clk),
.D(\blk00000003/sig000002ae ),
.Q(\blk00000003/sig000002dd )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000215 (
.C(clk),
.D(\blk00000003/sig000002ab ),
.Q(\blk00000003/sig000002dc )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000214 (
.C(clk),
.D(\blk00000003/sig000002a8 ),
.Q(\blk00000003/sig000002db )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000213 (
.C(clk),
.D(\blk00000003/sig000002a5 ),
.Q(\blk00000003/sig000002da )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000212 (
.C(clk),
.D(\blk00000003/sig000002a2 ),
.Q(\blk00000003/sig000002e1 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000211 (
.C(clk),
.D(\blk00000003/sig0000029f ),
.Q(\blk00000003/sig0000033c )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000210 (
.C(clk),
.D(\blk00000003/sig000002e5 ),
.Q(\blk00000003/sig00000305 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000020f (
.C(clk),
.D(\blk00000003/sig000002d9 ),
.Q(\blk00000003/sig00000304 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000020e (
.C(clk),
.D(\blk00000003/sig000002d6 ),
.Q(\blk00000003/sig00000303 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000020d (
.C(clk),
.D(\blk00000003/sig000002d3 ),
.Q(\blk00000003/sig00000302 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000020c (
.C(clk),
.D(\blk00000003/sig000002d0 ),
.Q(\blk00000003/sig00000301 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000020b (
.C(clk),
.D(\blk00000003/sig000002cd ),
.Q(\blk00000003/sig00000300 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000020a (
.C(clk),
.D(\blk00000003/sig000002ca ),
.Q(\blk00000003/sig000002ff )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000209 (
.C(clk),
.D(\blk00000003/sig000002c7 ),
.Q(\blk00000003/sig00000306 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000208 (
.C(clk),
.D(\blk00000003/sig000002c4 ),
.Q(\blk00000003/sig0000033b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000207 (
.C(clk),
.D(\blk00000003/sig0000030a ),
.Q(\blk00000003/sig0000032a )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000206 (
.C(clk),
.D(\blk00000003/sig000002fe ),
.Q(\blk00000003/sig00000329 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000205 (
.C(clk),
.D(\blk00000003/sig000002fb ),
.Q(\blk00000003/sig00000328 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000204 (
.C(clk),
.D(\blk00000003/sig000002f8 ),
.Q(\blk00000003/sig00000327 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000203 (
.C(clk),
.D(\blk00000003/sig000002f5 ),
.Q(\blk00000003/sig00000326 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000202 (
.C(clk),
.D(\blk00000003/sig000002f2 ),
.Q(\blk00000003/sig00000325 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000201 (
.C(clk),
.D(\blk00000003/sig000002ef ),
.Q(\blk00000003/sig00000324 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000200 (
.C(clk),
.D(\blk00000003/sig000002ec ),
.Q(\blk00000003/sig0000032b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000001ff (
.C(clk),
.D(\blk00000003/sig000002e9 ),
.Q(\blk00000003/sig0000033a )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000001fe (
.C(clk),
.D(\blk00000003/sig0000032f ),
.Q(\blk00000003/sig00000339 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000001fd (
.C(clk),
.D(\blk00000003/sig00000323 ),
.Q(\blk00000003/sig00000338 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000001fc (
.C(clk),
.D(\blk00000003/sig00000320 ),
.Q(\blk00000003/sig00000337 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000001fb (
.C(clk),
.D(\blk00000003/sig0000031d ),
.Q(\blk00000003/sig00000336 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000001fa (
.C(clk),
.D(\blk00000003/sig0000031a ),
.Q(\blk00000003/sig00000335 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000001f9 (
.C(clk),
.D(\blk00000003/sig00000317 ),
.Q(\blk00000003/sig00000334 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000001f8 (
.C(clk),
.D(\blk00000003/sig00000314 ),
.Q(\blk00000003/sig00000333 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000001f7 (
.C(clk),
.D(\blk00000003/sig00000311 ),
.Q(\blk00000003/sig00000332 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000001f6 (
.C(clk),
.D(\blk00000003/sig0000030e ),
.Q(\blk00000003/sig00000331 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000001f5 (
.C(clk),
.D(\blk00000003/sig0000032c ),
.Q(\blk00000003/sig00000330 )
);
MUXCY \blk00000003/blk000001f4 (
.CI(\blk00000003/sig0000032d ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig0000032e ),
.O(\blk00000003/sig00000321 )
);
XORCY \blk00000003/blk000001f3 (
.CI(\blk00000003/sig0000032d ),
.LI(\blk00000003/sig0000032e ),
.O(\blk00000003/sig0000032f )
);
MUXCY \blk00000003/blk000001f2 (
.CI(\blk00000003/sig0000030c ),
.DI(\blk00000003/sig0000032b ),
.S(\blk00000003/sig0000030d ),
.O(\blk00000003/sig0000032c )
);
MUXCY \blk00000003/blk000001f1 (
.CI(\blk00000003/sig00000321 ),
.DI(\blk00000003/sig0000032a ),
.S(\blk00000003/sig00000322 ),
.O(\blk00000003/sig0000031e )
);
MUXCY \blk00000003/blk000001f0 (
.CI(\blk00000003/sig0000031e ),
.DI(\blk00000003/sig00000329 ),
.S(\blk00000003/sig0000031f ),
.O(\blk00000003/sig0000031b )
);
MUXCY \blk00000003/blk000001ef (
.CI(\blk00000003/sig0000031b ),
.DI(\blk00000003/sig00000328 ),
.S(\blk00000003/sig0000031c ),
.O(\blk00000003/sig00000318 )
);
MUXCY \blk00000003/blk000001ee (
.CI(\blk00000003/sig00000318 ),
.DI(\blk00000003/sig00000327 ),
.S(\blk00000003/sig00000319 ),
.O(\blk00000003/sig00000315 )
);
MUXCY \blk00000003/blk000001ed (
.CI(\blk00000003/sig00000315 ),
.DI(\blk00000003/sig00000326 ),
.S(\blk00000003/sig00000316 ),
.O(\blk00000003/sig00000312 )
);
MUXCY \blk00000003/blk000001ec (
.CI(\blk00000003/sig00000312 ),
.DI(\blk00000003/sig00000325 ),
.S(\blk00000003/sig00000313 ),
.O(\blk00000003/sig0000030f )
);
MUXCY \blk00000003/blk000001eb (
.CI(\blk00000003/sig0000030f ),
.DI(\blk00000003/sig00000324 ),
.S(\blk00000003/sig00000310 ),
.O(\blk00000003/sig0000030c )
);
XORCY \blk00000003/blk000001ea (
.CI(\blk00000003/sig00000321 ),
.LI(\blk00000003/sig00000322 ),
.O(\blk00000003/sig00000323 )
);
XORCY \blk00000003/blk000001e9 (
.CI(\blk00000003/sig0000031e ),
.LI(\blk00000003/sig0000031f ),
.O(\blk00000003/sig00000320 )
);
XORCY \blk00000003/blk000001e8 (
.CI(\blk00000003/sig0000031b ),
.LI(\blk00000003/sig0000031c ),
.O(\blk00000003/sig0000031d )
);
XORCY \blk00000003/blk000001e7 (
.CI(\blk00000003/sig00000318 ),
.LI(\blk00000003/sig00000319 ),
.O(\blk00000003/sig0000031a )
);
XORCY \blk00000003/blk000001e6 (
.CI(\blk00000003/sig00000315 ),
.LI(\blk00000003/sig00000316 ),
.O(\blk00000003/sig00000317 )
);
XORCY \blk00000003/blk000001e5 (
.CI(\blk00000003/sig00000312 ),
.LI(\blk00000003/sig00000313 ),
.O(\blk00000003/sig00000314 )
);
XORCY \blk00000003/blk000001e4 (
.CI(\blk00000003/sig0000030f ),
.LI(\blk00000003/sig00000310 ),
.O(\blk00000003/sig00000311 )
);
XORCY \blk00000003/blk000001e3 (
.CI(\blk00000003/sig0000030c ),
.LI(\blk00000003/sig0000030d ),
.O(\blk00000003/sig0000030e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000001e2 (
.C(clk),
.D(\blk00000003/sig00000307 ),
.Q(\blk00000003/sig0000030b )
);
MUXCY \blk00000003/blk000001e1 (
.CI(\blk00000003/sig00000308 ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig00000309 ),
.O(\blk00000003/sig000002fc )
);
XORCY \blk00000003/blk000001e0 (
.CI(\blk00000003/sig00000308 ),
.LI(\blk00000003/sig00000309 ),
.O(\blk00000003/sig0000030a )
);
MUXCY \blk00000003/blk000001df (
.CI(\blk00000003/sig000002e7 ),
.DI(\blk00000003/sig00000306 ),
.S(\blk00000003/sig000002e8 ),
.O(\blk00000003/sig00000307 )
);
MUXCY \blk00000003/blk000001de (
.CI(\blk00000003/sig000002fc ),
.DI(\blk00000003/sig00000305 ),
.S(\blk00000003/sig000002fd ),
.O(\blk00000003/sig000002f9 )
);
MUXCY \blk00000003/blk000001dd (
.CI(\blk00000003/sig000002f9 ),
.DI(\blk00000003/sig00000304 ),
.S(\blk00000003/sig000002fa ),
.O(\blk00000003/sig000002f6 )
);
MUXCY \blk00000003/blk000001dc (
.CI(\blk00000003/sig000002f6 ),
.DI(\blk00000003/sig00000303 ),
.S(\blk00000003/sig000002f7 ),
.O(\blk00000003/sig000002f3 )
);
MUXCY \blk00000003/blk000001db (
.CI(\blk00000003/sig000002f3 ),
.DI(\blk00000003/sig00000302 ),
.S(\blk00000003/sig000002f4 ),
.O(\blk00000003/sig000002f0 )
);
MUXCY \blk00000003/blk000001da (
.CI(\blk00000003/sig000002f0 ),
.DI(\blk00000003/sig00000301 ),
.S(\blk00000003/sig000002f1 ),
.O(\blk00000003/sig000002ed )
);
MUXCY \blk00000003/blk000001d9 (
.CI(\blk00000003/sig000002ed ),
.DI(\blk00000003/sig00000300 ),
.S(\blk00000003/sig000002ee ),
.O(\blk00000003/sig000002ea )
);
MUXCY \blk00000003/blk000001d8 (
.CI(\blk00000003/sig000002ea ),
.DI(\blk00000003/sig000002ff ),
.S(\blk00000003/sig000002eb ),
.O(\blk00000003/sig000002e7 )
);
XORCY \blk00000003/blk000001d7 (
.CI(\blk00000003/sig000002fc ),
.LI(\blk00000003/sig000002fd ),
.O(\blk00000003/sig000002fe )
);
XORCY \blk00000003/blk000001d6 (
.CI(\blk00000003/sig000002f9 ),
.LI(\blk00000003/sig000002fa ),
.O(\blk00000003/sig000002fb )
);
XORCY \blk00000003/blk000001d5 (
.CI(\blk00000003/sig000002f6 ),
.LI(\blk00000003/sig000002f7 ),
.O(\blk00000003/sig000002f8 )
);
XORCY \blk00000003/blk000001d4 (
.CI(\blk00000003/sig000002f3 ),
.LI(\blk00000003/sig000002f4 ),
.O(\blk00000003/sig000002f5 )
);
XORCY \blk00000003/blk000001d3 (
.CI(\blk00000003/sig000002f0 ),
.LI(\blk00000003/sig000002f1 ),
.O(\blk00000003/sig000002f2 )
);
XORCY \blk00000003/blk000001d2 (
.CI(\blk00000003/sig000002ed ),
.LI(\blk00000003/sig000002ee ),
.O(\blk00000003/sig000002ef )
);
XORCY \blk00000003/blk000001d1 (
.CI(\blk00000003/sig000002ea ),
.LI(\blk00000003/sig000002eb ),
.O(\blk00000003/sig000002ec )
);
XORCY \blk00000003/blk000001d0 (
.CI(\blk00000003/sig000002e7 ),
.LI(\blk00000003/sig000002e8 ),
.O(\blk00000003/sig000002e9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000001cf (
.C(clk),
.D(\blk00000003/sig000002e2 ),
.Q(\blk00000003/sig000002e6 )
);
MUXCY \blk00000003/blk000001ce (
.CI(\blk00000003/sig000002e3 ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig000002e4 ),
.O(\blk00000003/sig000002d7 )
);
XORCY \blk00000003/blk000001cd (
.CI(\blk00000003/sig000002e3 ),
.LI(\blk00000003/sig000002e4 ),
.O(\blk00000003/sig000002e5 )
);
MUXCY \blk00000003/blk000001cc (
.CI(\blk00000003/sig000002c2 ),
.DI(\blk00000003/sig000002e1 ),
.S(\blk00000003/sig000002c3 ),
.O(\blk00000003/sig000002e2 )
);
MUXCY \blk00000003/blk000001cb (
.CI(\blk00000003/sig000002d7 ),
.DI(\blk00000003/sig000002e0 ),
.S(\blk00000003/sig000002d8 ),
.O(\blk00000003/sig000002d4 )
);
MUXCY \blk00000003/blk000001ca (
.CI(\blk00000003/sig000002d4 ),
.DI(\blk00000003/sig000002df ),
.S(\blk00000003/sig000002d5 ),
.O(\blk00000003/sig000002d1 )
);
MUXCY \blk00000003/blk000001c9 (
.CI(\blk00000003/sig000002d1 ),
.DI(\blk00000003/sig000002de ),
.S(\blk00000003/sig000002d2 ),
.O(\blk00000003/sig000002ce )
);
MUXCY \blk00000003/blk000001c8 (
.CI(\blk00000003/sig000002ce ),
.DI(\blk00000003/sig000002dd ),
.S(\blk00000003/sig000002cf ),
.O(\blk00000003/sig000002cb )
);
MUXCY \blk00000003/blk000001c7 (
.CI(\blk00000003/sig000002cb ),
.DI(\blk00000003/sig000002dc ),
.S(\blk00000003/sig000002cc ),
.O(\blk00000003/sig000002c8 )
);
MUXCY \blk00000003/blk000001c6 (
.CI(\blk00000003/sig000002c8 ),
.DI(\blk00000003/sig000002db ),
.S(\blk00000003/sig000002c9 ),
.O(\blk00000003/sig000002c5 )
);
MUXCY \blk00000003/blk000001c5 (
.CI(\blk00000003/sig000002c5 ),
.DI(\blk00000003/sig000002da ),
.S(\blk00000003/sig000002c6 ),
.O(\blk00000003/sig000002c2 )
);
XORCY \blk00000003/blk000001c4 (
.CI(\blk00000003/sig000002d7 ),
.LI(\blk00000003/sig000002d8 ),
.O(\blk00000003/sig000002d9 )
);
XORCY \blk00000003/blk000001c3 (
.CI(\blk00000003/sig000002d4 ),
.LI(\blk00000003/sig000002d5 ),
.O(\blk00000003/sig000002d6 )
);
XORCY \blk00000003/blk000001c2 (
.CI(\blk00000003/sig000002d1 ),
.LI(\blk00000003/sig000002d2 ),
.O(\blk00000003/sig000002d3 )
);
XORCY \blk00000003/blk000001c1 (
.CI(\blk00000003/sig000002ce ),
.LI(\blk00000003/sig000002cf ),
.O(\blk00000003/sig000002d0 )
);
XORCY \blk00000003/blk000001c0 (
.CI(\blk00000003/sig000002cb ),
.LI(\blk00000003/sig000002cc ),
.O(\blk00000003/sig000002cd )
);
XORCY \blk00000003/blk000001bf (
.CI(\blk00000003/sig000002c8 ),
.LI(\blk00000003/sig000002c9 ),
.O(\blk00000003/sig000002ca )
);
XORCY \blk00000003/blk000001be (
.CI(\blk00000003/sig000002c5 ),
.LI(\blk00000003/sig000002c6 ),
.O(\blk00000003/sig000002c7 )
);
XORCY \blk00000003/blk000001bd (
.CI(\blk00000003/sig000002c2 ),
.LI(\blk00000003/sig000002c3 ),
.O(\blk00000003/sig000002c4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000001bc (
.C(clk),
.D(\blk00000003/sig000002bd ),
.Q(\blk00000003/sig000002c1 )
);
MUXCY \blk00000003/blk000001bb (
.CI(\blk00000003/sig000002be ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig000002bf ),
.O(\blk00000003/sig000002b2 )
);
XORCY \blk00000003/blk000001ba (
.CI(\blk00000003/sig000002be ),
.LI(\blk00000003/sig000002bf ),
.O(\blk00000003/sig000002c0 )
);
MUXCY \blk00000003/blk000001b9 (
.CI(\blk00000003/sig0000029d ),
.DI(\blk00000003/sig000002bc ),
.S(\blk00000003/sig0000029e ),
.O(\blk00000003/sig000002bd )
);
MUXCY \blk00000003/blk000001b8 (
.CI(\blk00000003/sig000002b2 ),
.DI(\blk00000003/sig000002bb ),
.S(\blk00000003/sig000002b3 ),
.O(\blk00000003/sig000002af )
);
MUXCY \blk00000003/blk000001b7 (
.CI(\blk00000003/sig000002af ),
.DI(\blk00000003/sig000002ba ),
.S(\blk00000003/sig000002b0 ),
.O(\blk00000003/sig000002ac )
);
MUXCY \blk00000003/blk000001b6 (
.CI(\blk00000003/sig000002ac ),
.DI(\blk00000003/sig000002b9 ),
.S(\blk00000003/sig000002ad ),
.O(\blk00000003/sig000002a9 )
);
MUXCY \blk00000003/blk000001b5 (
.CI(\blk00000003/sig000002a9 ),
.DI(\blk00000003/sig000002b8 ),
.S(\blk00000003/sig000002aa ),
.O(\blk00000003/sig000002a6 )
);
MUXCY \blk00000003/blk000001b4 (
.CI(\blk00000003/sig000002a6 ),
.DI(\blk00000003/sig000002b7 ),
.S(\blk00000003/sig000002a7 ),
.O(\blk00000003/sig000002a3 )
);
MUXCY \blk00000003/blk000001b3 (
.CI(\blk00000003/sig000002a3 ),
.DI(\blk00000003/sig000002b6 ),
.S(\blk00000003/sig000002a4 ),
.O(\blk00000003/sig000002a0 )
);
MUXCY \blk00000003/blk000001b2 (
.CI(\blk00000003/sig000002a0 ),
.DI(\blk00000003/sig000002b5 ),
.S(\blk00000003/sig000002a1 ),
.O(\blk00000003/sig0000029d )
);
XORCY \blk00000003/blk000001b1 (
.CI(\blk00000003/sig000002b2 ),
.LI(\blk00000003/sig000002b3 ),
.O(\blk00000003/sig000002b4 )
);
XORCY \blk00000003/blk000001b0 (
.CI(\blk00000003/sig000002af ),
.LI(\blk00000003/sig000002b0 ),
.O(\blk00000003/sig000002b1 )
);
XORCY \blk00000003/blk000001af (
.CI(\blk00000003/sig000002ac ),
.LI(\blk00000003/sig000002ad ),
.O(\blk00000003/sig000002ae )
);
XORCY \blk00000003/blk000001ae (
.CI(\blk00000003/sig000002a9 ),
.LI(\blk00000003/sig000002aa ),
.O(\blk00000003/sig000002ab )
);
XORCY \blk00000003/blk000001ad (
.CI(\blk00000003/sig000002a6 ),
.LI(\blk00000003/sig000002a7 ),
.O(\blk00000003/sig000002a8 )
);
XORCY \blk00000003/blk000001ac (
.CI(\blk00000003/sig000002a3 ),
.LI(\blk00000003/sig000002a4 ),
.O(\blk00000003/sig000002a5 )
);
XORCY \blk00000003/blk000001ab (
.CI(\blk00000003/sig000002a0 ),
.LI(\blk00000003/sig000002a1 ),
.O(\blk00000003/sig000002a2 )
);
XORCY \blk00000003/blk000001aa (
.CI(\blk00000003/sig0000029d ),
.LI(\blk00000003/sig0000029e ),
.O(\blk00000003/sig0000029f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000001a9 (
.C(clk),
.D(\blk00000003/sig00000298 ),
.Q(\blk00000003/sig0000029c )
);
MUXCY \blk00000003/blk000001a8 (
.CI(\blk00000003/sig00000299 ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig0000029a ),
.O(\blk00000003/sig0000028d )
);
XORCY \blk00000003/blk000001a7 (
.CI(\blk00000003/sig00000299 ),
.LI(\blk00000003/sig0000029a ),
.O(\blk00000003/sig0000029b )
);
MUXCY \blk00000003/blk000001a6 (
.CI(\blk00000003/sig00000278 ),
.DI(\blk00000003/sig00000297 ),
.S(\blk00000003/sig00000279 ),
.O(\blk00000003/sig00000298 )
);
MUXCY \blk00000003/blk000001a5 (
.CI(\blk00000003/sig0000028d ),
.DI(\blk00000003/sig00000296 ),
.S(\blk00000003/sig0000028e ),
.O(\blk00000003/sig0000028a )
);
MUXCY \blk00000003/blk000001a4 (
.CI(\blk00000003/sig0000028a ),
.DI(\blk00000003/sig00000295 ),
.S(\blk00000003/sig0000028b ),
.O(\blk00000003/sig00000287 )
);
MUXCY \blk00000003/blk000001a3 (
.CI(\blk00000003/sig00000287 ),
.DI(\blk00000003/sig00000294 ),
.S(\blk00000003/sig00000288 ),
.O(\blk00000003/sig00000284 )
);
MUXCY \blk00000003/blk000001a2 (
.CI(\blk00000003/sig00000284 ),
.DI(\blk00000003/sig00000293 ),
.S(\blk00000003/sig00000285 ),
.O(\blk00000003/sig00000281 )
);
MUXCY \blk00000003/blk000001a1 (
.CI(\blk00000003/sig00000281 ),
.DI(\blk00000003/sig00000292 ),
.S(\blk00000003/sig00000282 ),
.O(\blk00000003/sig0000027e )
);
MUXCY \blk00000003/blk000001a0 (
.CI(\blk00000003/sig0000027e ),
.DI(\blk00000003/sig00000291 ),
.S(\blk00000003/sig0000027f ),
.O(\blk00000003/sig0000027b )
);
MUXCY \blk00000003/blk0000019f (
.CI(\blk00000003/sig0000027b ),
.DI(\blk00000003/sig00000290 ),
.S(\blk00000003/sig0000027c ),
.O(\blk00000003/sig00000278 )
);
XORCY \blk00000003/blk0000019e (
.CI(\blk00000003/sig0000028d ),
.LI(\blk00000003/sig0000028e ),
.O(\blk00000003/sig0000028f )
);
XORCY \blk00000003/blk0000019d (
.CI(\blk00000003/sig0000028a ),
.LI(\blk00000003/sig0000028b ),
.O(\blk00000003/sig0000028c )
);
XORCY \blk00000003/blk0000019c (
.CI(\blk00000003/sig00000287 ),
.LI(\blk00000003/sig00000288 ),
.O(\blk00000003/sig00000289 )
);
XORCY \blk00000003/blk0000019b (
.CI(\blk00000003/sig00000284 ),
.LI(\blk00000003/sig00000285 ),
.O(\blk00000003/sig00000286 )
);
XORCY \blk00000003/blk0000019a (
.CI(\blk00000003/sig00000281 ),
.LI(\blk00000003/sig00000282 ),
.O(\blk00000003/sig00000283 )
);
XORCY \blk00000003/blk00000199 (
.CI(\blk00000003/sig0000027e ),
.LI(\blk00000003/sig0000027f ),
.O(\blk00000003/sig00000280 )
);
XORCY \blk00000003/blk00000198 (
.CI(\blk00000003/sig0000027b ),
.LI(\blk00000003/sig0000027c ),
.O(\blk00000003/sig0000027d )
);
XORCY \blk00000003/blk00000197 (
.CI(\blk00000003/sig00000278 ),
.LI(\blk00000003/sig00000279 ),
.O(\blk00000003/sig0000027a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000196 (
.C(clk),
.D(\blk00000003/sig00000273 ),
.Q(\blk00000003/sig00000277 )
);
MUXCY \blk00000003/blk00000195 (
.CI(\blk00000003/sig00000274 ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig00000275 ),
.O(\blk00000003/sig00000268 )
);
XORCY \blk00000003/blk00000194 (
.CI(\blk00000003/sig00000274 ),
.LI(\blk00000003/sig00000275 ),
.O(\blk00000003/sig00000276 )
);
MUXCY \blk00000003/blk00000193 (
.CI(\blk00000003/sig00000253 ),
.DI(\blk00000003/sig00000272 ),
.S(\blk00000003/sig00000254 ),
.O(\blk00000003/sig00000273 )
);
MUXCY \blk00000003/blk00000192 (
.CI(\blk00000003/sig00000268 ),
.DI(\blk00000003/sig00000271 ),
.S(\blk00000003/sig00000269 ),
.O(\blk00000003/sig00000265 )
);
MUXCY \blk00000003/blk00000191 (
.CI(\blk00000003/sig00000265 ),
.DI(\blk00000003/sig00000270 ),
.S(\blk00000003/sig00000266 ),
.O(\blk00000003/sig00000262 )
);
MUXCY \blk00000003/blk00000190 (
.CI(\blk00000003/sig00000262 ),
.DI(\blk00000003/sig0000026f ),
.S(\blk00000003/sig00000263 ),
.O(\blk00000003/sig0000025f )
);
MUXCY \blk00000003/blk0000018f (
.CI(\blk00000003/sig0000025f ),
.DI(\blk00000003/sig0000026e ),
.S(\blk00000003/sig00000260 ),
.O(\blk00000003/sig0000025c )
);
MUXCY \blk00000003/blk0000018e (
.CI(\blk00000003/sig0000025c ),
.DI(\blk00000003/sig0000026d ),
.S(\blk00000003/sig0000025d ),
.O(\blk00000003/sig00000259 )
);
MUXCY \blk00000003/blk0000018d (
.CI(\blk00000003/sig00000259 ),
.DI(\blk00000003/sig0000026c ),
.S(\blk00000003/sig0000025a ),
.O(\blk00000003/sig00000256 )
);
MUXCY \blk00000003/blk0000018c (
.CI(\blk00000003/sig00000256 ),
.DI(\blk00000003/sig0000026b ),
.S(\blk00000003/sig00000257 ),
.O(\blk00000003/sig00000253 )
);
XORCY \blk00000003/blk0000018b (
.CI(\blk00000003/sig00000268 ),
.LI(\blk00000003/sig00000269 ),
.O(\blk00000003/sig0000026a )
);
XORCY \blk00000003/blk0000018a (
.CI(\blk00000003/sig00000265 ),
.LI(\blk00000003/sig00000266 ),
.O(\blk00000003/sig00000267 )
);
XORCY \blk00000003/blk00000189 (
.CI(\blk00000003/sig00000262 ),
.LI(\blk00000003/sig00000263 ),
.O(\blk00000003/sig00000264 )
);
XORCY \blk00000003/blk00000188 (
.CI(\blk00000003/sig0000025f ),
.LI(\blk00000003/sig00000260 ),
.O(\blk00000003/sig00000261 )
);
XORCY \blk00000003/blk00000187 (
.CI(\blk00000003/sig0000025c ),
.LI(\blk00000003/sig0000025d ),
.O(\blk00000003/sig0000025e )
);
XORCY \blk00000003/blk00000186 (
.CI(\blk00000003/sig00000259 ),
.LI(\blk00000003/sig0000025a ),
.O(\blk00000003/sig0000025b )
);
XORCY \blk00000003/blk00000185 (
.CI(\blk00000003/sig00000256 ),
.LI(\blk00000003/sig00000257 ),
.O(\blk00000003/sig00000258 )
);
XORCY \blk00000003/blk00000184 (
.CI(\blk00000003/sig00000253 ),
.LI(\blk00000003/sig00000254 ),
.O(\blk00000003/sig00000255 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000183 (
.C(clk),
.D(\blk00000003/sig0000024e ),
.Q(\blk00000003/sig00000252 )
);
MUXCY \blk00000003/blk00000182 (
.CI(\blk00000003/sig0000024f ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig00000250 ),
.O(\blk00000003/sig00000243 )
);
XORCY \blk00000003/blk00000181 (
.CI(\blk00000003/sig0000024f ),
.LI(\blk00000003/sig00000250 ),
.O(\blk00000003/sig00000251 )
);
MUXCY \blk00000003/blk00000180 (
.CI(\blk00000003/sig0000022e ),
.DI(\blk00000003/sig0000024d ),
.S(\blk00000003/sig0000022f ),
.O(\blk00000003/sig0000024e )
);
MUXCY \blk00000003/blk0000017f (
.CI(\blk00000003/sig00000243 ),
.DI(\blk00000003/sig0000024c ),
.S(\blk00000003/sig00000244 ),
.O(\blk00000003/sig00000240 )
);
MUXCY \blk00000003/blk0000017e (
.CI(\blk00000003/sig00000240 ),
.DI(\blk00000003/sig0000024b ),
.S(\blk00000003/sig00000241 ),
.O(\blk00000003/sig0000023d )
);
MUXCY \blk00000003/blk0000017d (
.CI(\blk00000003/sig0000023d ),
.DI(\blk00000003/sig0000024a ),
.S(\blk00000003/sig0000023e ),
.O(\blk00000003/sig0000023a )
);
MUXCY \blk00000003/blk0000017c (
.CI(\blk00000003/sig0000023a ),
.DI(\blk00000003/sig00000249 ),
.S(\blk00000003/sig0000023b ),
.O(\blk00000003/sig00000237 )
);
MUXCY \blk00000003/blk0000017b (
.CI(\blk00000003/sig00000237 ),
.DI(\blk00000003/sig00000248 ),
.S(\blk00000003/sig00000238 ),
.O(\blk00000003/sig00000234 )
);
MUXCY \blk00000003/blk0000017a (
.CI(\blk00000003/sig00000234 ),
.DI(\blk00000003/sig00000247 ),
.S(\blk00000003/sig00000235 ),
.O(\blk00000003/sig00000231 )
);
MUXCY \blk00000003/blk00000179 (
.CI(\blk00000003/sig00000231 ),
.DI(\blk00000003/sig00000246 ),
.S(\blk00000003/sig00000232 ),
.O(\blk00000003/sig0000022e )
);
XORCY \blk00000003/blk00000178 (
.CI(\blk00000003/sig00000243 ),
.LI(\blk00000003/sig00000244 ),
.O(\blk00000003/sig00000245 )
);
XORCY \blk00000003/blk00000177 (
.CI(\blk00000003/sig00000240 ),
.LI(\blk00000003/sig00000241 ),
.O(\blk00000003/sig00000242 )
);
XORCY \blk00000003/blk00000176 (
.CI(\blk00000003/sig0000023d ),
.LI(\blk00000003/sig0000023e ),
.O(\blk00000003/sig0000023f )
);
XORCY \blk00000003/blk00000175 (
.CI(\blk00000003/sig0000023a ),
.LI(\blk00000003/sig0000023b ),
.O(\blk00000003/sig0000023c )
);
XORCY \blk00000003/blk00000174 (
.CI(\blk00000003/sig00000237 ),
.LI(\blk00000003/sig00000238 ),
.O(\blk00000003/sig00000239 )
);
XORCY \blk00000003/blk00000173 (
.CI(\blk00000003/sig00000234 ),
.LI(\blk00000003/sig00000235 ),
.O(\blk00000003/sig00000236 )
);
XORCY \blk00000003/blk00000172 (
.CI(\blk00000003/sig00000231 ),
.LI(\blk00000003/sig00000232 ),
.O(\blk00000003/sig00000233 )
);
XORCY \blk00000003/blk00000171 (
.CI(\blk00000003/sig0000022e ),
.LI(\blk00000003/sig0000022f ),
.O(\blk00000003/sig00000230 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000170 (
.C(clk),
.D(\blk00000003/sig00000229 ),
.Q(\blk00000003/sig0000022d )
);
MUXCY \blk00000003/blk0000016f (
.CI(\blk00000003/sig0000022a ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig0000022b ),
.O(\blk00000003/sig0000021e )
);
XORCY \blk00000003/blk0000016e (
.CI(\blk00000003/sig0000022a ),
.LI(\blk00000003/sig0000022b ),
.O(\blk00000003/sig0000022c )
);
MUXCY \blk00000003/blk0000016d (
.CI(\blk00000003/sig00000209 ),
.DI(\blk00000003/sig00000228 ),
.S(\blk00000003/sig0000020a ),
.O(\blk00000003/sig00000229 )
);
MUXCY \blk00000003/blk0000016c (
.CI(\blk00000003/sig0000021e ),
.DI(\blk00000003/sig00000227 ),
.S(\blk00000003/sig0000021f ),
.O(\blk00000003/sig0000021b )
);
MUXCY \blk00000003/blk0000016b (
.CI(\blk00000003/sig0000021b ),
.DI(\blk00000003/sig00000226 ),
.S(\blk00000003/sig0000021c ),
.O(\blk00000003/sig00000218 )
);
MUXCY \blk00000003/blk0000016a (
.CI(\blk00000003/sig00000218 ),
.DI(\blk00000003/sig00000225 ),
.S(\blk00000003/sig00000219 ),
.O(\blk00000003/sig00000215 )
);
MUXCY \blk00000003/blk00000169 (
.CI(\blk00000003/sig00000215 ),
.DI(\blk00000003/sig00000224 ),
.S(\blk00000003/sig00000216 ),
.O(\blk00000003/sig00000212 )
);
MUXCY \blk00000003/blk00000168 (
.CI(\blk00000003/sig00000212 ),
.DI(\blk00000003/sig00000223 ),
.S(\blk00000003/sig00000213 ),
.O(\blk00000003/sig0000020f )
);
MUXCY \blk00000003/blk00000167 (
.CI(\blk00000003/sig0000020f ),
.DI(\blk00000003/sig00000222 ),
.S(\blk00000003/sig00000210 ),
.O(\blk00000003/sig0000020c )
);
MUXCY \blk00000003/blk00000166 (
.CI(\blk00000003/sig0000020c ),
.DI(\blk00000003/sig00000221 ),
.S(\blk00000003/sig0000020d ),
.O(\blk00000003/sig00000209 )
);
XORCY \blk00000003/blk00000165 (
.CI(\blk00000003/sig0000021e ),
.LI(\blk00000003/sig0000021f ),
.O(\blk00000003/sig00000220 )
);
XORCY \blk00000003/blk00000164 (
.CI(\blk00000003/sig0000021b ),
.LI(\blk00000003/sig0000021c ),
.O(\blk00000003/sig0000021d )
);
XORCY \blk00000003/blk00000163 (
.CI(\blk00000003/sig00000218 ),
.LI(\blk00000003/sig00000219 ),
.O(\blk00000003/sig0000021a )
);
XORCY \blk00000003/blk00000162 (
.CI(\blk00000003/sig00000215 ),
.LI(\blk00000003/sig00000216 ),
.O(\blk00000003/sig00000217 )
);
XORCY \blk00000003/blk00000161 (
.CI(\blk00000003/sig00000212 ),
.LI(\blk00000003/sig00000213 ),
.O(\blk00000003/sig00000214 )
);
XORCY \blk00000003/blk00000160 (
.CI(\blk00000003/sig0000020f ),
.LI(\blk00000003/sig00000210 ),
.O(\blk00000003/sig00000211 )
);
XORCY \blk00000003/blk0000015f (
.CI(\blk00000003/sig0000020c ),
.LI(\blk00000003/sig0000020d ),
.O(\blk00000003/sig0000020e )
);
XORCY \blk00000003/blk0000015e (
.CI(\blk00000003/sig00000209 ),
.LI(\blk00000003/sig0000020a ),
.O(\blk00000003/sig0000020b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000015d (
.C(clk),
.D(\blk00000003/sig00000204 ),
.Q(\blk00000003/sig00000208 )
);
MUXCY \blk00000003/blk0000015c (
.CI(\blk00000003/sig00000205 ),
.DI(\blk00000003/sig00000069 ),
.S(\blk00000003/sig00000206 ),
.O(\blk00000003/sig000001f9 )
);
XORCY \blk00000003/blk0000015b (
.CI(\blk00000003/sig00000205 ),
.LI(\blk00000003/sig00000206 ),
.O(\blk00000003/sig00000207 )
);
MUXCY \blk00000003/blk0000015a (
.CI(\blk00000003/sig000001e4 ),
.DI(\blk00000003/sig00000203 ),
.S(\blk00000003/sig000001e5 ),
.O(\blk00000003/sig00000204 )
);
MUXCY \blk00000003/blk00000159 (
.CI(\blk00000003/sig000001f9 ),
.DI(\blk00000003/sig00000202 ),
.S(\blk00000003/sig000001fa ),
.O(\blk00000003/sig000001f6 )
);
MUXCY \blk00000003/blk00000158 (
.CI(\blk00000003/sig000001f6 ),
.DI(\blk00000003/sig00000201 ),
.S(\blk00000003/sig000001f7 ),
.O(\blk00000003/sig000001f3 )
);
MUXCY \blk00000003/blk00000157 (
.CI(\blk00000003/sig000001f3 ),
.DI(\blk00000003/sig00000200 ),
.S(\blk00000003/sig000001f4 ),
.O(\blk00000003/sig000001f0 )
);
MUXCY \blk00000003/blk00000156 (
.CI(\blk00000003/sig000001f0 ),
.DI(\blk00000003/sig000001ff ),
.S(\blk00000003/sig000001f1 ),
.O(\blk00000003/sig000001ed )
);
MUXCY \blk00000003/blk00000155 (
.CI(\blk00000003/sig000001ed ),
.DI(\blk00000003/sig000001fe ),
.S(\blk00000003/sig000001ee ),
.O(\blk00000003/sig000001ea )
);
MUXCY \blk00000003/blk00000154 (
.CI(\blk00000003/sig000001ea ),
.DI(\blk00000003/sig000001fd ),
.S(\blk00000003/sig000001eb ),
.O(\blk00000003/sig000001e7 )
);
MUXCY \blk00000003/blk00000153 (
.CI(\blk00000003/sig000001e7 ),
.DI(\blk00000003/sig000001fc ),
.S(\blk00000003/sig000001e8 ),
.O(\blk00000003/sig000001e4 )
);
XORCY \blk00000003/blk00000152 (
.CI(\blk00000003/sig000001f9 ),
.LI(\blk00000003/sig000001fa ),
.O(\blk00000003/sig000001fb )
);
XORCY \blk00000003/blk00000151 (
.CI(\blk00000003/sig000001f6 ),
.LI(\blk00000003/sig000001f7 ),
.O(\blk00000003/sig000001f8 )
);
XORCY \blk00000003/blk00000150 (
.CI(\blk00000003/sig000001f3 ),
.LI(\blk00000003/sig000001f4 ),
.O(\blk00000003/sig000001f5 )
);
XORCY \blk00000003/blk0000014f (
.CI(\blk00000003/sig000001f0 ),
.LI(\blk00000003/sig000001f1 ),
.O(\blk00000003/sig000001f2 )
);
XORCY \blk00000003/blk0000014e (
.CI(\blk00000003/sig000001ed ),
.LI(\blk00000003/sig000001ee ),
.O(\blk00000003/sig000001ef )
);
XORCY \blk00000003/blk0000014d (
.CI(\blk00000003/sig000001ea ),
.LI(\blk00000003/sig000001eb ),
.O(\blk00000003/sig000001ec )
);
XORCY \blk00000003/blk0000014c (
.CI(\blk00000003/sig000001e7 ),
.LI(\blk00000003/sig000001e8 ),
.O(\blk00000003/sig000001e9 )
);
XORCY \blk00000003/blk0000014b (
.CI(\blk00000003/sig000001e4 ),
.LI(\blk00000003/sig000001e5 ),
.O(\blk00000003/sig000001e6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000014a (
.C(clk),
.D(\blk00000003/sig000001df ),
.Q(\blk00000003/sig000001e3 )
);
MUXCY \blk00000003/blk00000149 (
.CI(\blk00000003/sig000001e0 ),
.DI(\blk00000003/sig0000003b ),
.S(\blk00000003/sig000001e1 ),
.O(\blk00000003/sig000001d4 )
);
XORCY \blk00000003/blk00000148 (
.CI(\blk00000003/sig000001e0 ),
.LI(\blk00000003/sig000001e1 ),
.O(\blk00000003/sig000001e2 )
);
MUXCY \blk00000003/blk00000147 (
.CI(\blk00000003/sig000001bf ),
.DI(\blk00000003/sig000001de ),
.S(\blk00000003/sig000001c0 ),
.O(\blk00000003/sig000001df )
);
MUXCY \blk00000003/blk00000146 (
.CI(\blk00000003/sig000001d4 ),
.DI(\blk00000003/sig000001dd ),
.S(\blk00000003/sig000001d5 ),
.O(\blk00000003/sig000001d1 )
);
MUXCY \blk00000003/blk00000145 (
.CI(\blk00000003/sig000001d1 ),
.DI(\blk00000003/sig000001dc ),
.S(\blk00000003/sig000001d2 ),
.O(\blk00000003/sig000001ce )
);
MUXCY \blk00000003/blk00000144 (
.CI(\blk00000003/sig000001ce ),
.DI(\blk00000003/sig000001db ),
.S(\blk00000003/sig000001cf ),
.O(\blk00000003/sig000001cb )
);
MUXCY \blk00000003/blk00000143 (
.CI(\blk00000003/sig000001cb ),
.DI(\blk00000003/sig000001da ),
.S(\blk00000003/sig000001cc ),
.O(\blk00000003/sig000001c8 )
);
MUXCY \blk00000003/blk00000142 (
.CI(\blk00000003/sig000001c8 ),
.DI(\blk00000003/sig000001d9 ),
.S(\blk00000003/sig000001c9 ),
.O(\blk00000003/sig000001c5 )
);
MUXCY \blk00000003/blk00000141 (
.CI(\blk00000003/sig000001c5 ),
.DI(\blk00000003/sig000001d8 ),
.S(\blk00000003/sig000001c6 ),
.O(\blk00000003/sig000001c2 )
);
MUXCY \blk00000003/blk00000140 (
.CI(\blk00000003/sig000001c2 ),
.DI(\blk00000003/sig000001d7 ),
.S(\blk00000003/sig000001c3 ),
.O(\blk00000003/sig000001bf )
);
XORCY \blk00000003/blk0000013f (
.CI(\blk00000003/sig000001d4 ),
.LI(\blk00000003/sig000001d5 ),
.O(\blk00000003/sig000001d6 )
);
XORCY \blk00000003/blk0000013e (
.CI(\blk00000003/sig000001d1 ),
.LI(\blk00000003/sig000001d2 ),
.O(\blk00000003/sig000001d3 )
);
XORCY \blk00000003/blk0000013d (
.CI(\blk00000003/sig000001ce ),
.LI(\blk00000003/sig000001cf ),
.O(\blk00000003/sig000001d0 )
);
XORCY \blk00000003/blk0000013c (
.CI(\blk00000003/sig000001cb ),
.LI(\blk00000003/sig000001cc ),
.O(\blk00000003/sig000001cd )
);
XORCY \blk00000003/blk0000013b (
.CI(\blk00000003/sig000001c8 ),
.LI(\blk00000003/sig000001c9 ),
.O(\blk00000003/sig000001ca )
);
XORCY \blk00000003/blk0000013a (
.CI(\blk00000003/sig000001c5 ),
.LI(\blk00000003/sig000001c6 ),
.O(\blk00000003/sig000001c7 )
);
XORCY \blk00000003/blk00000139 (
.CI(\blk00000003/sig000001c2 ),
.LI(\blk00000003/sig000001c3 ),
.O(\blk00000003/sig000001c4 )
);
XORCY \blk00000003/blk00000138 (
.CI(\blk00000003/sig000001bf ),
.LI(\blk00000003/sig000001c0 ),
.O(\blk00000003/sig000001c1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000137 (
.C(clk),
.D(\blk00000003/sig000001ba ),
.Q(\blk00000003/sig000001be )
);
MUXCY \blk00000003/blk00000136 (
.CI(\blk00000003/sig000001bb ),
.DI(\blk00000003/sig00000044 ),
.S(\blk00000003/sig000001bc ),
.O(\blk00000003/sig000001af )
);
XORCY \blk00000003/blk00000135 (
.CI(\blk00000003/sig000001bb ),
.LI(\blk00000003/sig000001bc ),
.O(\blk00000003/sig000001bd )
);
MUXCY \blk00000003/blk00000134 (
.CI(\blk00000003/sig0000019a ),
.DI(\blk00000003/sig000001b9 ),
.S(\blk00000003/sig0000019b ),
.O(\blk00000003/sig000001ba )
);
MUXCY \blk00000003/blk00000133 (
.CI(\blk00000003/sig000001af ),
.DI(\blk00000003/sig000001b8 ),
.S(\blk00000003/sig000001b0 ),
.O(\blk00000003/sig000001ac )
);
MUXCY \blk00000003/blk00000132 (
.CI(\blk00000003/sig000001ac ),
.DI(\blk00000003/sig000001b7 ),
.S(\blk00000003/sig000001ad ),
.O(\blk00000003/sig000001a9 )
);
MUXCY \blk00000003/blk00000131 (
.CI(\blk00000003/sig000001a9 ),
.DI(\blk00000003/sig000001b6 ),
.S(\blk00000003/sig000001aa ),
.O(\blk00000003/sig000001a6 )
);
MUXCY \blk00000003/blk00000130 (
.CI(\blk00000003/sig000001a6 ),
.DI(\blk00000003/sig000001b5 ),
.S(\blk00000003/sig000001a7 ),
.O(\blk00000003/sig000001a3 )
);
MUXCY \blk00000003/blk0000012f (
.CI(\blk00000003/sig000001a3 ),
.DI(\blk00000003/sig000001b4 ),
.S(\blk00000003/sig000001a4 ),
.O(\blk00000003/sig000001a0 )
);
MUXCY \blk00000003/blk0000012e (
.CI(\blk00000003/sig000001a0 ),
.DI(\blk00000003/sig000001b3 ),
.S(\blk00000003/sig000001a1 ),
.O(\blk00000003/sig0000019d )
);
MUXCY \blk00000003/blk0000012d (
.CI(\blk00000003/sig0000019d ),
.DI(\blk00000003/sig000001b2 ),
.S(\blk00000003/sig0000019e ),
.O(\blk00000003/sig0000019a )
);
XORCY \blk00000003/blk0000012c (
.CI(\blk00000003/sig000001af ),
.LI(\blk00000003/sig000001b0 ),
.O(\blk00000003/sig000001b1 )
);
XORCY \blk00000003/blk0000012b (
.CI(\blk00000003/sig000001ac ),
.LI(\blk00000003/sig000001ad ),
.O(\blk00000003/sig000001ae )
);
XORCY \blk00000003/blk0000012a (
.CI(\blk00000003/sig000001a9 ),
.LI(\blk00000003/sig000001aa ),
.O(\blk00000003/sig000001ab )
);
XORCY \blk00000003/blk00000129 (
.CI(\blk00000003/sig000001a6 ),
.LI(\blk00000003/sig000001a7 ),
.O(\blk00000003/sig000001a8 )
);
XORCY \blk00000003/blk00000128 (
.CI(\blk00000003/sig000001a3 ),
.LI(\blk00000003/sig000001a4 ),
.O(\blk00000003/sig000001a5 )
);
XORCY \blk00000003/blk00000127 (
.CI(\blk00000003/sig000001a0 ),
.LI(\blk00000003/sig000001a1 ),
.O(\blk00000003/sig000001a2 )
);
XORCY \blk00000003/blk00000126 (
.CI(\blk00000003/sig0000019d ),
.LI(\blk00000003/sig0000019e ),
.O(\blk00000003/sig0000019f )
);
XORCY \blk00000003/blk00000125 (
.CI(\blk00000003/sig0000019a ),
.LI(\blk00000003/sig0000019b ),
.O(\blk00000003/sig0000019c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000124 (
.C(clk),
.D(\blk00000003/sig00000195 ),
.Q(\blk00000003/sig00000199 )
);
MUXCY \blk00000003/blk00000123 (
.CI(\blk00000003/sig00000196 ),
.DI(\blk00000003/sig0000004d ),
.S(\blk00000003/sig00000197 ),
.O(\blk00000003/sig0000018a )
);
XORCY \blk00000003/blk00000122 (
.CI(\blk00000003/sig00000196 ),
.LI(\blk00000003/sig00000197 ),
.O(\blk00000003/sig00000198 )
);
MUXCY \blk00000003/blk00000121 (
.CI(\blk00000003/sig00000175 ),
.DI(\blk00000003/sig00000194 ),
.S(\blk00000003/sig00000176 ),
.O(\blk00000003/sig00000195 )
);
MUXCY \blk00000003/blk00000120 (
.CI(\blk00000003/sig0000018a ),
.DI(\blk00000003/sig00000193 ),
.S(\blk00000003/sig0000018b ),
.O(\blk00000003/sig00000187 )
);
MUXCY \blk00000003/blk0000011f (
.CI(\blk00000003/sig00000187 ),
.DI(\blk00000003/sig00000192 ),
.S(\blk00000003/sig00000188 ),
.O(\blk00000003/sig00000184 )
);
MUXCY \blk00000003/blk0000011e (
.CI(\blk00000003/sig00000184 ),
.DI(\blk00000003/sig00000191 ),
.S(\blk00000003/sig00000185 ),
.O(\blk00000003/sig00000181 )
);
MUXCY \blk00000003/blk0000011d (
.CI(\blk00000003/sig00000181 ),
.DI(\blk00000003/sig00000190 ),
.S(\blk00000003/sig00000182 ),
.O(\blk00000003/sig0000017e )
);
MUXCY \blk00000003/blk0000011c (
.CI(\blk00000003/sig0000017e ),
.DI(\blk00000003/sig0000018f ),
.S(\blk00000003/sig0000017f ),
.O(\blk00000003/sig0000017b )
);
MUXCY \blk00000003/blk0000011b (
.CI(\blk00000003/sig0000017b ),
.DI(\blk00000003/sig0000018e ),
.S(\blk00000003/sig0000017c ),
.O(\blk00000003/sig00000178 )
);
MUXCY \blk00000003/blk0000011a (
.CI(\blk00000003/sig00000178 ),
.DI(\blk00000003/sig0000018d ),
.S(\blk00000003/sig00000179 ),
.O(\blk00000003/sig00000175 )
);
XORCY \blk00000003/blk00000119 (
.CI(\blk00000003/sig0000018a ),
.LI(\blk00000003/sig0000018b ),
.O(\blk00000003/sig0000018c )
);
XORCY \blk00000003/blk00000118 (
.CI(\blk00000003/sig00000187 ),
.LI(\blk00000003/sig00000188 ),
.O(\blk00000003/sig00000189 )
);
XORCY \blk00000003/blk00000117 (
.CI(\blk00000003/sig00000184 ),
.LI(\blk00000003/sig00000185 ),
.O(\blk00000003/sig00000186 )
);
XORCY \blk00000003/blk00000116 (
.CI(\blk00000003/sig00000181 ),
.LI(\blk00000003/sig00000182 ),
.O(\blk00000003/sig00000183 )
);
XORCY \blk00000003/blk00000115 (
.CI(\blk00000003/sig0000017e ),
.LI(\blk00000003/sig0000017f ),
.O(\blk00000003/sig00000180 )
);
XORCY \blk00000003/blk00000114 (
.CI(\blk00000003/sig0000017b ),
.LI(\blk00000003/sig0000017c ),
.O(\blk00000003/sig0000017d )
);
XORCY \blk00000003/blk00000113 (
.CI(\blk00000003/sig00000178 ),
.LI(\blk00000003/sig00000179 ),
.O(\blk00000003/sig0000017a )
);
XORCY \blk00000003/blk00000112 (
.CI(\blk00000003/sig00000175 ),
.LI(\blk00000003/sig00000176 ),
.O(\blk00000003/sig00000177 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000111 (
.C(clk),
.D(\blk00000003/sig00000170 ),
.Q(\blk00000003/sig00000174 )
);
MUXCY \blk00000003/blk00000110 (
.CI(\blk00000003/sig00000171 ),
.DI(\blk00000003/sig00000056 ),
.S(\blk00000003/sig00000172 ),
.O(\blk00000003/sig00000165 )
);
XORCY \blk00000003/blk0000010f (
.CI(\blk00000003/sig00000171 ),
.LI(\blk00000003/sig00000172 ),
.O(\blk00000003/sig00000173 )
);
MUXCY \blk00000003/blk0000010e (
.CI(\blk00000003/sig00000150 ),
.DI(\blk00000003/sig0000016f ),
.S(\blk00000003/sig00000151 ),
.O(\blk00000003/sig00000170 )
);
MUXCY \blk00000003/blk0000010d (
.CI(\blk00000003/sig00000165 ),
.DI(\blk00000003/sig0000016e ),
.S(\blk00000003/sig00000166 ),
.O(\blk00000003/sig00000162 )
);
MUXCY \blk00000003/blk0000010c (
.CI(\blk00000003/sig00000162 ),
.DI(\blk00000003/sig0000016d ),
.S(\blk00000003/sig00000163 ),
.O(\blk00000003/sig0000015f )
);
MUXCY \blk00000003/blk0000010b (
.CI(\blk00000003/sig0000015f ),
.DI(\blk00000003/sig0000016c ),
.S(\blk00000003/sig00000160 ),
.O(\blk00000003/sig0000015c )
);
MUXCY \blk00000003/blk0000010a (
.CI(\blk00000003/sig0000015c ),
.DI(\blk00000003/sig0000016b ),
.S(\blk00000003/sig0000015d ),
.O(\blk00000003/sig00000159 )
);
MUXCY \blk00000003/blk00000109 (
.CI(\blk00000003/sig00000159 ),
.DI(\blk00000003/sig0000016a ),
.S(\blk00000003/sig0000015a ),
.O(\blk00000003/sig00000156 )
);
MUXCY \blk00000003/blk00000108 (
.CI(\blk00000003/sig00000156 ),
.DI(\blk00000003/sig00000169 ),
.S(\blk00000003/sig00000157 ),
.O(\blk00000003/sig00000153 )
);
MUXCY \blk00000003/blk00000107 (
.CI(\blk00000003/sig00000153 ),
.DI(\blk00000003/sig00000168 ),
.S(\blk00000003/sig00000154 ),
.O(\blk00000003/sig00000150 )
);
XORCY \blk00000003/blk00000106 (
.CI(\blk00000003/sig00000165 ),
.LI(\blk00000003/sig00000166 ),
.O(\blk00000003/sig00000167 )
);
XORCY \blk00000003/blk00000105 (
.CI(\blk00000003/sig00000162 ),
.LI(\blk00000003/sig00000163 ),
.O(\blk00000003/sig00000164 )
);
XORCY \blk00000003/blk00000104 (
.CI(\blk00000003/sig0000015f ),
.LI(\blk00000003/sig00000160 ),
.O(\blk00000003/sig00000161 )
);
XORCY \blk00000003/blk00000103 (
.CI(\blk00000003/sig0000015c ),
.LI(\blk00000003/sig0000015d ),
.O(\blk00000003/sig0000015e )
);
XORCY \blk00000003/blk00000102 (
.CI(\blk00000003/sig00000159 ),
.LI(\blk00000003/sig0000015a ),
.O(\blk00000003/sig0000015b )
);
XORCY \blk00000003/blk00000101 (
.CI(\blk00000003/sig00000156 ),
.LI(\blk00000003/sig00000157 ),
.O(\blk00000003/sig00000158 )
);
XORCY \blk00000003/blk00000100 (
.CI(\blk00000003/sig00000153 ),
.LI(\blk00000003/sig00000154 ),
.O(\blk00000003/sig00000155 )
);
XORCY \blk00000003/blk000000ff (
.CI(\blk00000003/sig00000150 ),
.LI(\blk00000003/sig00000151 ),
.O(\blk00000003/sig00000152 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000fe (
.C(clk),
.D(\blk00000003/sig0000014b ),
.Q(\blk00000003/sig0000014f )
);
MUXCY \blk00000003/blk000000fd (
.CI(\blk00000003/sig0000014c ),
.DI(\blk00000003/sig0000005f ),
.S(\blk00000003/sig0000014d ),
.O(\blk00000003/sig00000140 )
);
XORCY \blk00000003/blk000000fc (
.CI(\blk00000003/sig0000014c ),
.LI(\blk00000003/sig0000014d ),
.O(\blk00000003/sig0000014e )
);
MUXCY \blk00000003/blk000000fb (
.CI(\blk00000003/sig0000012b ),
.DI(\blk00000003/sig0000014a ),
.S(\blk00000003/sig0000012c ),
.O(\blk00000003/sig0000014b )
);
MUXCY \blk00000003/blk000000fa (
.CI(\blk00000003/sig00000140 ),
.DI(\blk00000003/sig00000149 ),
.S(\blk00000003/sig00000141 ),
.O(\blk00000003/sig0000013d )
);
MUXCY \blk00000003/blk000000f9 (
.CI(\blk00000003/sig0000013d ),
.DI(\blk00000003/sig00000148 ),
.S(\blk00000003/sig0000013e ),
.O(\blk00000003/sig0000013a )
);
MUXCY \blk00000003/blk000000f8 (
.CI(\blk00000003/sig0000013a ),
.DI(\blk00000003/sig00000147 ),
.S(\blk00000003/sig0000013b ),
.O(\blk00000003/sig00000137 )
);
MUXCY \blk00000003/blk000000f7 (
.CI(\blk00000003/sig00000137 ),
.DI(\blk00000003/sig00000146 ),
.S(\blk00000003/sig00000138 ),
.O(\blk00000003/sig00000134 )
);
MUXCY \blk00000003/blk000000f6 (
.CI(\blk00000003/sig00000134 ),
.DI(\blk00000003/sig00000145 ),
.S(\blk00000003/sig00000135 ),
.O(\blk00000003/sig00000131 )
);
MUXCY \blk00000003/blk000000f5 (
.CI(\blk00000003/sig00000131 ),
.DI(\blk00000003/sig00000144 ),
.S(\blk00000003/sig00000132 ),
.O(\blk00000003/sig0000012e )
);
MUXCY \blk00000003/blk000000f4 (
.CI(\blk00000003/sig0000012e ),
.DI(\blk00000003/sig00000143 ),
.S(\blk00000003/sig0000012f ),
.O(\blk00000003/sig0000012b )
);
XORCY \blk00000003/blk000000f3 (
.CI(\blk00000003/sig00000140 ),
.LI(\blk00000003/sig00000141 ),
.O(\blk00000003/sig00000142 )
);
XORCY \blk00000003/blk000000f2 (
.CI(\blk00000003/sig0000013d ),
.LI(\blk00000003/sig0000013e ),
.O(\blk00000003/sig0000013f )
);
XORCY \blk00000003/blk000000f1 (
.CI(\blk00000003/sig0000013a ),
.LI(\blk00000003/sig0000013b ),
.O(\blk00000003/sig0000013c )
);
XORCY \blk00000003/blk000000f0 (
.CI(\blk00000003/sig00000137 ),
.LI(\blk00000003/sig00000138 ),
.O(\blk00000003/sig00000139 )
);
XORCY \blk00000003/blk000000ef (
.CI(\blk00000003/sig00000134 ),
.LI(\blk00000003/sig00000135 ),
.O(\blk00000003/sig00000136 )
);
XORCY \blk00000003/blk000000ee (
.CI(\blk00000003/sig00000131 ),
.LI(\blk00000003/sig00000132 ),
.O(\blk00000003/sig00000133 )
);
XORCY \blk00000003/blk000000ed (
.CI(\blk00000003/sig0000012e ),
.LI(\blk00000003/sig0000012f ),
.O(\blk00000003/sig00000130 )
);
XORCY \blk00000003/blk000000ec (
.CI(\blk00000003/sig0000012b ),
.LI(\blk00000003/sig0000012c ),
.O(\blk00000003/sig0000012d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000eb (
.C(clk),
.D(\blk00000003/sig00000126 ),
.Q(\blk00000003/sig0000012a )
);
MUXCY \blk00000003/blk000000ea (
.CI(\blk00000003/sig00000127 ),
.DI(\blk00000003/sig00000068 ),
.S(\blk00000003/sig00000128 ),
.O(\blk00000003/sig0000011b )
);
XORCY \blk00000003/blk000000e9 (
.CI(\blk00000003/sig00000127 ),
.LI(\blk00000003/sig00000128 ),
.O(\blk00000003/sig00000129 )
);
MUXCY \blk00000003/blk000000e8 (
.CI(\blk00000003/sig00000106 ),
.DI(\blk00000003/sig00000125 ),
.S(\blk00000003/sig00000107 ),
.O(\blk00000003/sig00000126 )
);
MUXCY \blk00000003/blk000000e7 (
.CI(\blk00000003/sig0000011b ),
.DI(\blk00000003/sig00000124 ),
.S(\blk00000003/sig0000011c ),
.O(\blk00000003/sig00000118 )
);
MUXCY \blk00000003/blk000000e6 (
.CI(\blk00000003/sig00000118 ),
.DI(\blk00000003/sig00000123 ),
.S(\blk00000003/sig00000119 ),
.O(\blk00000003/sig00000115 )
);
MUXCY \blk00000003/blk000000e5 (
.CI(\blk00000003/sig00000115 ),
.DI(\blk00000003/sig00000122 ),
.S(\blk00000003/sig00000116 ),
.O(\blk00000003/sig00000112 )
);
MUXCY \blk00000003/blk000000e4 (
.CI(\blk00000003/sig00000112 ),
.DI(\blk00000003/sig00000121 ),
.S(\blk00000003/sig00000113 ),
.O(\blk00000003/sig0000010f )
);
MUXCY \blk00000003/blk000000e3 (
.CI(\blk00000003/sig0000010f ),
.DI(\blk00000003/sig00000120 ),
.S(\blk00000003/sig00000110 ),
.O(\blk00000003/sig0000010c )
);
MUXCY \blk00000003/blk000000e2 (
.CI(\blk00000003/sig0000010c ),
.DI(\blk00000003/sig0000011f ),
.S(\blk00000003/sig0000010d ),
.O(\blk00000003/sig00000109 )
);
MUXCY \blk00000003/blk000000e1 (
.CI(\blk00000003/sig00000109 ),
.DI(\blk00000003/sig0000011e ),
.S(\blk00000003/sig0000010a ),
.O(\blk00000003/sig00000106 )
);
XORCY \blk00000003/blk000000e0 (
.CI(\blk00000003/sig0000011b ),
.LI(\blk00000003/sig0000011c ),
.O(\blk00000003/sig0000011d )
);
XORCY \blk00000003/blk000000df (
.CI(\blk00000003/sig00000118 ),
.LI(\blk00000003/sig00000119 ),
.O(\blk00000003/sig0000011a )
);
XORCY \blk00000003/blk000000de (
.CI(\blk00000003/sig00000115 ),
.LI(\blk00000003/sig00000116 ),
.O(\blk00000003/sig00000117 )
);
XORCY \blk00000003/blk000000dd (
.CI(\blk00000003/sig00000112 ),
.LI(\blk00000003/sig00000113 ),
.O(\blk00000003/sig00000114 )
);
XORCY \blk00000003/blk000000dc (
.CI(\blk00000003/sig0000010f ),
.LI(\blk00000003/sig00000110 ),
.O(\blk00000003/sig00000111 )
);
XORCY \blk00000003/blk000000db (
.CI(\blk00000003/sig0000010c ),
.LI(\blk00000003/sig0000010d ),
.O(\blk00000003/sig0000010e )
);
XORCY \blk00000003/blk000000da (
.CI(\blk00000003/sig00000109 ),
.LI(\blk00000003/sig0000010a ),
.O(\blk00000003/sig0000010b )
);
XORCY \blk00000003/blk000000d9 (
.CI(\blk00000003/sig00000106 ),
.LI(\blk00000003/sig00000107 ),
.O(\blk00000003/sig00000108 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000d8 (
.C(clk),
.D(\blk00000003/sig00000102 ),
.Q(\blk00000003/sig00000105 )
);
MUXCY \blk00000003/blk000000d7 (
.CI(NlwRenamedSig_OI_rfd),
.DI(\blk00000003/sig0000006a ),
.S(\blk00000003/sig00000103 ),
.O(\blk00000003/sig000000ff )
);
XORCY \blk00000003/blk000000d6 (
.CI(NlwRenamedSig_OI_rfd),
.LI(\blk00000003/sig00000103 ),
.O(\blk00000003/sig00000104 )
);
MUXCY \blk00000003/blk000000d5 (
.CI(\blk00000003/sig000000eb ),
.DI(\blk00000003/sig00000022 ),
.S(NlwRenamedSig_OI_rfd),
.O(\blk00000003/sig00000102 )
);
MUXCY \blk00000003/blk000000d4 (
.CI(\blk00000003/sig000000ff ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig00000100 ),
.O(\blk00000003/sig000000fc )
);
MUXCY \blk00000003/blk000000d3 (
.CI(\blk00000003/sig000000fc ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig000000fd ),
.O(\blk00000003/sig000000f9 )
);
MUXCY \blk00000003/blk000000d2 (
.CI(\blk00000003/sig000000f9 ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig000000fa ),
.O(\blk00000003/sig000000f6 )
);
MUXCY \blk00000003/blk000000d1 (
.CI(\blk00000003/sig000000f6 ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig000000f7 ),
.O(\blk00000003/sig000000f3 )
);
MUXCY \blk00000003/blk000000d0 (
.CI(\blk00000003/sig000000f3 ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig000000f4 ),
.O(\blk00000003/sig000000f0 )
);
MUXCY \blk00000003/blk000000cf (
.CI(\blk00000003/sig000000f0 ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig000000f1 ),
.O(\blk00000003/sig000000ed )
);
MUXCY \blk00000003/blk000000ce (
.CI(\blk00000003/sig000000ed ),
.DI(\blk00000003/sig00000022 ),
.S(\blk00000003/sig000000ee ),
.O(\blk00000003/sig000000eb )
);
XORCY \blk00000003/blk000000cd (
.CI(\blk00000003/sig000000ff ),
.LI(\blk00000003/sig00000100 ),
.O(\blk00000003/sig00000101 )
);
XORCY \blk00000003/blk000000cc (
.CI(\blk00000003/sig000000fc ),
.LI(\blk00000003/sig000000fd ),
.O(\blk00000003/sig000000fe )
);
XORCY \blk00000003/blk000000cb (
.CI(\blk00000003/sig000000f9 ),
.LI(\blk00000003/sig000000fa ),
.O(\blk00000003/sig000000fb )
);
XORCY \blk00000003/blk000000ca (
.CI(\blk00000003/sig000000f6 ),
.LI(\blk00000003/sig000000f7 ),
.O(\blk00000003/sig000000f8 )
);
XORCY \blk00000003/blk000000c9 (
.CI(\blk00000003/sig000000f3 ),
.LI(\blk00000003/sig000000f4 ),
.O(\blk00000003/sig000000f5 )
);
XORCY \blk00000003/blk000000c8 (
.CI(\blk00000003/sig000000f0 ),
.LI(\blk00000003/sig000000f1 ),
.O(\blk00000003/sig000000f2 )
);
XORCY \blk00000003/blk000000c7 (
.CI(\blk00000003/sig000000ed ),
.LI(\blk00000003/sig000000ee ),
.O(\blk00000003/sig000000ef )
);
XORCY \blk00000003/blk000000c6 (
.CI(\blk00000003/sig000000eb ),
.LI(NlwRenamedSig_OI_rfd),
.O(\blk00000003/sig000000ec )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000000c5 (
.C(clk),
.D(divisor_1[0]),
.Q(\blk00000003/sig000000ea )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000c4 (
.C(clk),
.D(divisor_1[1]),
.Q(\blk00000003/sig000000e9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000c3 (
.C(clk),
.D(divisor_1[2]),
.Q(\blk00000003/sig000000e8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000c2 (
.C(clk),
.D(divisor_1[3]),
.Q(\blk00000003/sig000000e7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000c1 (
.C(clk),
.D(divisor_1[4]),
.Q(\blk00000003/sig000000e6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000c0 (
.C(clk),
.D(divisor_1[5]),
.Q(\blk00000003/sig000000e5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000bf (
.C(clk),
.D(divisor_1[6]),
.Q(\blk00000003/sig000000e4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000be (
.C(clk),
.D(divisor_1[7]),
.Q(\blk00000003/sig000000e3 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000000bd (
.C(clk),
.D(\blk00000003/sig000000ea ),
.Q(\blk00000003/sig000000e2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000bc (
.C(clk),
.D(\blk00000003/sig000000e9 ),
.Q(\blk00000003/sig000000e1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000bb (
.C(clk),
.D(\blk00000003/sig000000e8 ),
.Q(\blk00000003/sig000000e0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000ba (
.C(clk),
.D(\blk00000003/sig000000e7 ),
.Q(\blk00000003/sig000000df )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000b9 (
.C(clk),
.D(\blk00000003/sig000000e6 ),
.Q(\blk00000003/sig000000de )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000b8 (
.C(clk),
.D(\blk00000003/sig000000e5 ),
.Q(\blk00000003/sig000000dd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000b7 (
.C(clk),
.D(\blk00000003/sig000000e4 ),
.Q(\blk00000003/sig000000dc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000b6 (
.C(clk),
.D(\blk00000003/sig000000e3 ),
.Q(\blk00000003/sig000000db )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000000b5 (
.C(clk),
.D(\blk00000003/sig000000e2 ),
.Q(\blk00000003/sig000000da )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000b4 (
.C(clk),
.D(\blk00000003/sig000000e1 ),
.Q(\blk00000003/sig000000d9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000b3 (
.C(clk),
.D(\blk00000003/sig000000e0 ),
.Q(\blk00000003/sig000000d8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000b2 (
.C(clk),
.D(\blk00000003/sig000000df ),
.Q(\blk00000003/sig000000d7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000b1 (
.C(clk),
.D(\blk00000003/sig000000de ),
.Q(\blk00000003/sig000000d6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000b0 (
.C(clk),
.D(\blk00000003/sig000000dd ),
.Q(\blk00000003/sig000000d5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000af (
.C(clk),
.D(\blk00000003/sig000000dc ),
.Q(\blk00000003/sig000000d4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000ae (
.C(clk),
.D(\blk00000003/sig000000db ),
.Q(\blk00000003/sig000000d3 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000000ad (
.C(clk),
.D(\blk00000003/sig000000da ),
.Q(\blk00000003/sig000000d2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000ac (
.C(clk),
.D(\blk00000003/sig000000d9 ),
.Q(\blk00000003/sig000000d1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000ab (
.C(clk),
.D(\blk00000003/sig000000d8 ),
.Q(\blk00000003/sig000000d0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000aa (
.C(clk),
.D(\blk00000003/sig000000d7 ),
.Q(\blk00000003/sig000000cf )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000a9 (
.C(clk),
.D(\blk00000003/sig000000d6 ),
.Q(\blk00000003/sig000000ce )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000a8 (
.C(clk),
.D(\blk00000003/sig000000d5 ),
.Q(\blk00000003/sig000000cd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000a7 (
.C(clk),
.D(\blk00000003/sig000000d4 ),
.Q(\blk00000003/sig000000cc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000a6 (
.C(clk),
.D(\blk00000003/sig000000d3 ),
.Q(\blk00000003/sig000000cb )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk000000a5 (
.C(clk),
.D(\blk00000003/sig000000d2 ),
.Q(\blk00000003/sig000000ca )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000a4 (
.C(clk),
.D(\blk00000003/sig000000d1 ),
.Q(\blk00000003/sig000000c9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000a3 (
.C(clk),
.D(\blk00000003/sig000000d0 ),
.Q(\blk00000003/sig000000c8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000a2 (
.C(clk),
.D(\blk00000003/sig000000cf ),
.Q(\blk00000003/sig000000c7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000a1 (
.C(clk),
.D(\blk00000003/sig000000ce ),
.Q(\blk00000003/sig000000c6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk000000a0 (
.C(clk),
.D(\blk00000003/sig000000cd ),
.Q(\blk00000003/sig000000c5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000009f (
.C(clk),
.D(\blk00000003/sig000000cc ),
.Q(\blk00000003/sig000000c4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000009e (
.C(clk),
.D(\blk00000003/sig000000cb ),
.Q(\blk00000003/sig000000c3 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000009d (
.C(clk),
.D(\blk00000003/sig000000ca ),
.Q(\blk00000003/sig000000c2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000009c (
.C(clk),
.D(\blk00000003/sig000000c9 ),
.Q(\blk00000003/sig000000c1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000009b (
.C(clk),
.D(\blk00000003/sig000000c8 ),
.Q(\blk00000003/sig000000c0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000009a (
.C(clk),
.D(\blk00000003/sig000000c7 ),
.Q(\blk00000003/sig000000bf )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000099 (
.C(clk),
.D(\blk00000003/sig000000c6 ),
.Q(\blk00000003/sig000000be )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000098 (
.C(clk),
.D(\blk00000003/sig000000c5 ),
.Q(\blk00000003/sig000000bd )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000097 (
.C(clk),
.D(\blk00000003/sig000000c4 ),
.Q(\blk00000003/sig000000bc )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000096 (
.C(clk),
.D(\blk00000003/sig000000c3 ),
.Q(\blk00000003/sig000000bb )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000095 (
.C(clk),
.D(\blk00000003/sig000000c2 ),
.Q(\blk00000003/sig000000ba )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000094 (
.C(clk),
.D(\blk00000003/sig000000c1 ),
.Q(\blk00000003/sig000000b9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000093 (
.C(clk),
.D(\blk00000003/sig000000c0 ),
.Q(\blk00000003/sig000000b8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000092 (
.C(clk),
.D(\blk00000003/sig000000bf ),
.Q(\blk00000003/sig000000b7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000091 (
.C(clk),
.D(\blk00000003/sig000000be ),
.Q(\blk00000003/sig000000b6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000090 (
.C(clk),
.D(\blk00000003/sig000000bd ),
.Q(\blk00000003/sig000000b5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000008f (
.C(clk),
.D(\blk00000003/sig000000bc ),
.Q(\blk00000003/sig000000b4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000008e (
.C(clk),
.D(\blk00000003/sig000000bb ),
.Q(\blk00000003/sig000000b3 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000008d (
.C(clk),
.D(\blk00000003/sig000000ba ),
.Q(\blk00000003/sig000000b2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000008c (
.C(clk),
.D(\blk00000003/sig000000b9 ),
.Q(\blk00000003/sig000000b1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000008b (
.C(clk),
.D(\blk00000003/sig000000b8 ),
.Q(\blk00000003/sig000000b0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000008a (
.C(clk),
.D(\blk00000003/sig000000b7 ),
.Q(\blk00000003/sig000000af )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000089 (
.C(clk),
.D(\blk00000003/sig000000b6 ),
.Q(\blk00000003/sig000000ae )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000088 (
.C(clk),
.D(\blk00000003/sig000000b5 ),
.Q(\blk00000003/sig000000ad )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000087 (
.C(clk),
.D(\blk00000003/sig000000b4 ),
.Q(\blk00000003/sig000000ac )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000086 (
.C(clk),
.D(\blk00000003/sig000000b3 ),
.Q(\blk00000003/sig000000ab )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000085 (
.C(clk),
.D(\blk00000003/sig000000b2 ),
.Q(\blk00000003/sig000000aa )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000084 (
.C(clk),
.D(\blk00000003/sig000000b1 ),
.Q(\blk00000003/sig000000a9 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000083 (
.C(clk),
.D(\blk00000003/sig000000b0 ),
.Q(\blk00000003/sig000000a8 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000082 (
.C(clk),
.D(\blk00000003/sig000000af ),
.Q(\blk00000003/sig000000a7 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000081 (
.C(clk),
.D(\blk00000003/sig000000ae ),
.Q(\blk00000003/sig000000a6 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000080 (
.C(clk),
.D(\blk00000003/sig000000ad ),
.Q(\blk00000003/sig000000a5 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000007f (
.C(clk),
.D(\blk00000003/sig000000ac ),
.Q(\blk00000003/sig000000a4 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000007e (
.C(clk),
.D(\blk00000003/sig000000ab ),
.Q(\blk00000003/sig000000a3 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000007d (
.C(clk),
.D(\blk00000003/sig000000aa ),
.Q(\blk00000003/sig000000a2 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000007c (
.C(clk),
.D(\blk00000003/sig000000a9 ),
.Q(\blk00000003/sig000000a1 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000007b (
.C(clk),
.D(\blk00000003/sig000000a8 ),
.Q(\blk00000003/sig000000a0 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000007a (
.C(clk),
.D(\blk00000003/sig000000a7 ),
.Q(\blk00000003/sig0000009f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000079 (
.C(clk),
.D(\blk00000003/sig000000a6 ),
.Q(\blk00000003/sig0000009e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000078 (
.C(clk),
.D(\blk00000003/sig000000a5 ),
.Q(\blk00000003/sig0000009d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000077 (
.C(clk),
.D(\blk00000003/sig000000a4 ),
.Q(\blk00000003/sig0000009c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000076 (
.C(clk),
.D(\blk00000003/sig000000a3 ),
.Q(\blk00000003/sig0000009b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000075 (
.C(clk),
.D(\blk00000003/sig000000a2 ),
.Q(\blk00000003/sig0000009a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000074 (
.C(clk),
.D(\blk00000003/sig000000a1 ),
.Q(\blk00000003/sig00000099 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000073 (
.C(clk),
.D(\blk00000003/sig000000a0 ),
.Q(\blk00000003/sig00000098 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000072 (
.C(clk),
.D(\blk00000003/sig0000009f ),
.Q(\blk00000003/sig00000097 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000071 (
.C(clk),
.D(\blk00000003/sig0000009e ),
.Q(\blk00000003/sig00000096 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000070 (
.C(clk),
.D(\blk00000003/sig0000009d ),
.Q(\blk00000003/sig00000095 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000006f (
.C(clk),
.D(\blk00000003/sig0000009c ),
.Q(\blk00000003/sig00000094 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000006e (
.C(clk),
.D(\blk00000003/sig0000009b ),
.Q(\blk00000003/sig00000093 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000006d (
.C(clk),
.D(\blk00000003/sig0000009a ),
.Q(\blk00000003/sig00000092 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000006c (
.C(clk),
.D(\blk00000003/sig00000099 ),
.Q(\blk00000003/sig00000091 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000006b (
.C(clk),
.D(\blk00000003/sig00000098 ),
.Q(\blk00000003/sig00000090 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000006a (
.C(clk),
.D(\blk00000003/sig00000097 ),
.Q(\blk00000003/sig0000008f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000069 (
.C(clk),
.D(\blk00000003/sig00000096 ),
.Q(\blk00000003/sig0000008e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000068 (
.C(clk),
.D(\blk00000003/sig00000095 ),
.Q(\blk00000003/sig0000008d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000067 (
.C(clk),
.D(\blk00000003/sig00000094 ),
.Q(\blk00000003/sig0000008c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000066 (
.C(clk),
.D(\blk00000003/sig00000093 ),
.Q(\blk00000003/sig0000008b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000065 (
.C(clk),
.D(\blk00000003/sig00000092 ),
.Q(\blk00000003/sig0000008a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000064 (
.C(clk),
.D(\blk00000003/sig00000091 ),
.Q(\blk00000003/sig00000089 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000063 (
.C(clk),
.D(\blk00000003/sig00000090 ),
.Q(\blk00000003/sig00000088 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000062 (
.C(clk),
.D(\blk00000003/sig0000008f ),
.Q(\blk00000003/sig00000087 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000061 (
.C(clk),
.D(\blk00000003/sig0000008e ),
.Q(\blk00000003/sig00000086 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000060 (
.C(clk),
.D(\blk00000003/sig0000008d ),
.Q(\blk00000003/sig00000085 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000005f (
.C(clk),
.D(\blk00000003/sig0000008c ),
.Q(\blk00000003/sig00000084 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000005e (
.C(clk),
.D(\blk00000003/sig0000008b ),
.Q(\blk00000003/sig00000083 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000005d (
.C(clk),
.D(\blk00000003/sig0000008a ),
.Q(\blk00000003/sig00000082 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000005c (
.C(clk),
.D(\blk00000003/sig00000089 ),
.Q(\blk00000003/sig00000081 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000005b (
.C(clk),
.D(\blk00000003/sig00000088 ),
.Q(\blk00000003/sig00000080 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000005a (
.C(clk),
.D(\blk00000003/sig00000087 ),
.Q(\blk00000003/sig0000007f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000059 (
.C(clk),
.D(\blk00000003/sig00000086 ),
.Q(\blk00000003/sig0000007e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000058 (
.C(clk),
.D(\blk00000003/sig00000085 ),
.Q(\blk00000003/sig0000007d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000057 (
.C(clk),
.D(\blk00000003/sig00000084 ),
.Q(\blk00000003/sig0000007c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000056 (
.C(clk),
.D(\blk00000003/sig00000083 ),
.Q(\blk00000003/sig0000007b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000055 (
.C(clk),
.D(\blk00000003/sig00000082 ),
.Q(\blk00000003/sig00000079 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000054 (
.C(clk),
.D(\blk00000003/sig00000081 ),
.Q(\blk00000003/sig00000077 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000053 (
.C(clk),
.D(\blk00000003/sig00000080 ),
.Q(\blk00000003/sig00000075 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000052 (
.C(clk),
.D(\blk00000003/sig0000007f ),
.Q(\blk00000003/sig00000073 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000051 (
.C(clk),
.D(\blk00000003/sig0000007e ),
.Q(\blk00000003/sig00000071 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000050 (
.C(clk),
.D(\blk00000003/sig0000007d ),
.Q(\blk00000003/sig0000006f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000004f (
.C(clk),
.D(\blk00000003/sig0000007c ),
.Q(\blk00000003/sig0000006d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000004e (
.C(clk),
.D(\blk00000003/sig0000007b ),
.Q(\blk00000003/sig0000006b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000004d (
.C(clk),
.D(\blk00000003/sig00000079 ),
.Q(\blk00000003/sig0000007a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000004c (
.C(clk),
.D(\blk00000003/sig00000077 ),
.Q(\blk00000003/sig00000078 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000004b (
.C(clk),
.D(\blk00000003/sig00000075 ),
.Q(\blk00000003/sig00000076 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000004a (
.C(clk),
.D(\blk00000003/sig00000073 ),
.Q(\blk00000003/sig00000074 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000049 (
.C(clk),
.D(\blk00000003/sig00000071 ),
.Q(\blk00000003/sig00000072 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000048 (
.C(clk),
.D(\blk00000003/sig0000006f ),
.Q(\blk00000003/sig00000070 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000047 (
.C(clk),
.D(\blk00000003/sig0000006d ),
.Q(\blk00000003/sig0000006e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000046 (
.C(clk),
.D(\blk00000003/sig0000006b ),
.Q(\blk00000003/sig0000006c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000045 (
.C(clk),
.D(dividend_0[0]),
.Q(\blk00000003/sig00000061 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000044 (
.C(clk),
.D(dividend_0[1]),
.Q(\blk00000003/sig00000062 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000043 (
.C(clk),
.D(dividend_0[2]),
.Q(\blk00000003/sig00000063 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000042 (
.C(clk),
.D(dividend_0[3]),
.Q(\blk00000003/sig00000064 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000041 (
.C(clk),
.D(dividend_0[4]),
.Q(\blk00000003/sig00000065 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000040 (
.C(clk),
.D(dividend_0[5]),
.Q(\blk00000003/sig00000066 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000003f (
.C(clk),
.D(dividend_0[6]),
.Q(\blk00000003/sig00000067 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000003e (
.C(clk),
.D(dividend_0[7]),
.Q(\blk00000003/sig0000006a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000003d (
.C(clk),
.D(\blk00000003/sig00000039 ),
.Q(\blk00000003/sig00000069 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000003c (
.C(clk),
.D(\blk00000003/sig00000067 ),
.Q(\blk00000003/sig00000068 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000003b (
.C(clk),
.D(\blk00000003/sig00000066 ),
.Q(\blk00000003/sig0000005e )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000003a (
.C(clk),
.D(\blk00000003/sig00000065 ),
.Q(\blk00000003/sig0000005d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000039 (
.C(clk),
.D(\blk00000003/sig00000064 ),
.Q(\blk00000003/sig0000005c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000038 (
.C(clk),
.D(\blk00000003/sig00000063 ),
.Q(\blk00000003/sig0000005b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000037 (
.C(clk),
.D(\blk00000003/sig00000062 ),
.Q(\blk00000003/sig0000005a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000036 (
.C(clk),
.D(\blk00000003/sig00000061 ),
.Q(\blk00000003/sig00000059 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000035 (
.C(clk),
.D(\blk00000003/sig00000060 ),
.Q(\blk00000003/sig00000058 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000034 (
.C(clk),
.D(\blk00000003/sig0000005e ),
.Q(\blk00000003/sig0000005f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000033 (
.C(clk),
.D(\blk00000003/sig0000005d ),
.Q(\blk00000003/sig00000055 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000032 (
.C(clk),
.D(\blk00000003/sig0000005c ),
.Q(\blk00000003/sig00000054 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000031 (
.C(clk),
.D(\blk00000003/sig0000005b ),
.Q(\blk00000003/sig00000053 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000030 (
.C(clk),
.D(\blk00000003/sig0000005a ),
.Q(\blk00000003/sig00000052 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000002f (
.C(clk),
.D(\blk00000003/sig00000059 ),
.Q(\blk00000003/sig00000051 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000002e (
.C(clk),
.D(\blk00000003/sig00000058 ),
.Q(\blk00000003/sig00000050 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000002d (
.C(clk),
.D(\blk00000003/sig00000057 ),
.Q(\blk00000003/sig0000004f )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000002c (
.C(clk),
.D(\blk00000003/sig00000055 ),
.Q(\blk00000003/sig00000056 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000002b (
.C(clk),
.D(\blk00000003/sig00000054 ),
.Q(\blk00000003/sig0000004c )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000002a (
.C(clk),
.D(\blk00000003/sig00000053 ),
.Q(\blk00000003/sig0000004b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000029 (
.C(clk),
.D(\blk00000003/sig00000052 ),
.Q(\blk00000003/sig0000004a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000028 (
.C(clk),
.D(\blk00000003/sig00000051 ),
.Q(\blk00000003/sig00000049 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000027 (
.C(clk),
.D(\blk00000003/sig00000050 ),
.Q(\blk00000003/sig00000048 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000026 (
.C(clk),
.D(\blk00000003/sig0000004f ),
.Q(\blk00000003/sig00000047 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000025 (
.C(clk),
.D(\blk00000003/sig0000004e ),
.Q(\blk00000003/sig00000046 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000024 (
.C(clk),
.D(\blk00000003/sig0000004c ),
.Q(\blk00000003/sig0000004d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000023 (
.C(clk),
.D(\blk00000003/sig0000004b ),
.Q(\blk00000003/sig00000043 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000022 (
.C(clk),
.D(\blk00000003/sig0000004a ),
.Q(\blk00000003/sig00000042 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000021 (
.C(clk),
.D(\blk00000003/sig00000049 ),
.Q(\blk00000003/sig00000041 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000020 (
.C(clk),
.D(\blk00000003/sig00000048 ),
.Q(\blk00000003/sig00000040 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000001f (
.C(clk),
.D(\blk00000003/sig00000047 ),
.Q(\blk00000003/sig0000003f )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000001e (
.C(clk),
.D(\blk00000003/sig00000046 ),
.Q(\blk00000003/sig0000003e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000001d (
.C(clk),
.D(\blk00000003/sig00000045 ),
.Q(\blk00000003/sig0000003d )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000001c (
.C(clk),
.D(\blk00000003/sig00000043 ),
.Q(\blk00000003/sig00000044 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000001b (
.C(clk),
.D(\blk00000003/sig00000042 ),
.Q(\blk00000003/sig0000003a )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk0000001a (
.C(clk),
.D(\blk00000003/sig00000041 ),
.Q(\blk00000003/sig00000038 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000019 (
.C(clk),
.D(\blk00000003/sig00000040 ),
.Q(\blk00000003/sig00000037 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000018 (
.C(clk),
.D(\blk00000003/sig0000003f ),
.Q(\blk00000003/sig00000036 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000017 (
.C(clk),
.D(\blk00000003/sig0000003e ),
.Q(\blk00000003/sig00000035 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000016 (
.C(clk),
.D(\blk00000003/sig0000003d ),
.Q(\blk00000003/sig00000034 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000015 (
.C(clk),
.D(\blk00000003/sig0000003c ),
.Q(\blk00000003/sig00000033 )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000014 (
.C(clk),
.D(\blk00000003/sig0000003a ),
.Q(\blk00000003/sig0000003b )
);
FD #(
.INIT ( 1'b0 ))
\blk00000003/blk00000013 (
.C(clk),
.D(\blk00000003/sig00000038 ),
.Q(\blk00000003/sig00000039 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000012 (
.C(clk),
.D(\blk00000003/sig00000037 ),
.Q(\blk00000003/sig00000030 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000011 (
.C(clk),
.D(\blk00000003/sig00000036 ),
.Q(\blk00000003/sig0000002e )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000010 (
.C(clk),
.D(\blk00000003/sig00000035 ),
.Q(\blk00000003/sig0000002c )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000000f (
.C(clk),
.D(\blk00000003/sig00000034 ),
.Q(\blk00000003/sig0000002a )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000000e (
.C(clk),
.D(\blk00000003/sig00000033 ),
.Q(\blk00000003/sig00000028 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000000d (
.C(clk),
.D(\blk00000003/sig00000032 ),
.Q(\blk00000003/sig00000026 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000000c (
.C(clk),
.D(\blk00000003/sig00000030 ),
.Q(\blk00000003/sig00000031 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000000b (
.C(clk),
.D(\blk00000003/sig0000002e ),
.Q(\blk00000003/sig0000002f )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk0000000a (
.C(clk),
.D(\blk00000003/sig0000002c ),
.Q(\blk00000003/sig0000002d )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000009 (
.C(clk),
.D(\blk00000003/sig0000002a ),
.Q(\blk00000003/sig0000002b )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000008 (
.C(clk),
.D(\blk00000003/sig00000028 ),
.Q(\blk00000003/sig00000029 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000007 (
.C(clk),
.D(\blk00000003/sig00000026 ),
.Q(\blk00000003/sig00000027 )
);
FD #(
.INIT ( 1'b1 ))
\blk00000003/blk00000006 (
.C(clk),
.D(\blk00000003/sig00000024 ),
.Q(\blk00000003/sig00000025 )
);
VCC \blk00000003/blk00000005 (
.P(NlwRenamedSig_OI_rfd)
);
GND \blk00000003/blk00000004 (
.G(\blk00000003/sig00000022 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
`timescale 1ns/10ps
`verilog
`suppress_faults
`nosuppress_faults
`enable_portfaults
`disable_portfaults
`delay_mode_distributed
`delay_mode_path
`delay_mode_unit
`delay_mode_zero
`default_decay_time 1
`default_decay_time 1.0
`default_decay_time infinite
// unsupported (recommended not to): `default_trireg_strength 10
`default_nettype wire
// unsupported: `default_nettype tri
// unsupported: `default_nettype tri0
// unsupported: `default_nettype wand
// unsupported: `default_nettype triand
// unsupported: `default_nettype wor
// unsupported: `default_nettype trior
// unsupported: `default_nettype trireg
`default_nettype none
`autoexpand_vectornets
`accelerate
`noaccelerate
`expand_vectornets
`noexpand_vectornets
`remove_gatenames
`noremove_gatenames
`remove_netnames
`noremove_netnames
`resetall
// unsupported: `unconnected_drive pull1
// unsupported: `unconnected_drive pull0
`nounconnected_drive
`line 100 "hallo.v" 0
// unsupported: `uselib file=../moto_lib.v
// unsupported: `uselib dir=../lib.dir libext=.v
module t;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module CSRs(
input [11:0] cadr_i,
output cvalid_o,
output [63:0] cdat_o,
input [63:0] cdat_i,
input coe_i,
input cwe_i,
input mie_0,
input mie_mpie,
input mpie_mie,
input mpie_1,
output [63:0] mtvec_o,
output [63:0] mepc_o,
output [3:0] cause_o,
input [63:0] ia_i,
input [63:0] pc_i,
output mie_o,
output mpie_o,
input ft0_i,
input tick_i,
input mcause_2,
input mcause_3,
input mcause_11,
input mcause_irq_i,
input mepc_ia,
input mepc_pc,
input irq_i,
output take_irq_o,
input reset_i,
input clk_i
);
reg mpie, mie;
reg [63:0] mtvec;
reg [63:0] mscratch;
reg [63:0] mepc;
reg [4:0] mcause; // Compacted; bit 4 here maps to bit 63 in software
reg [63:0] mbadaddr;
reg [63:0] mcycle;
reg [63:0] mtime;
reg [63:0] minstret;
reg irqEn;
wire mpie_mux, mie_mux;
wire [63:0] mtvec_mux;
wire [63:0] mscratch_mux;
wire [63:0] mepc_mux;
wire [4:0] mcause_mux;
wire [63:0] mbadaddr_mux;
wire [63:0] mcycle_mux;
wire [63:0] mtime_mux;
// wire [63:0] minstret_mux;
assign mtvec_o = mtvec;
assign mepc_o = mepc;
wire csrv_misa = (cadr_i == 12'hF10);
wire csrv_mvendorid = (cadr_i == 12'hF11);
wire csrv_marchid = (cadr_i == 12'hF12);
wire csrv_mimpid = (cadr_i == 12'hF13);
wire csrv_mhartid = (cadr_i == 12'hF14);
wire csrv_mstatus = (cadr_i == 12'h300);
wire csrv_medeleg = (cadr_i == 12'h302);
wire csrv_mideleg = (cadr_i == 12'h303);
wire csrv_mie = (cadr_i == 12'h304);
wire csrv_mtvec = (cadr_i == 12'h305);
wire csrv_mscratch = (cadr_i == 12'h340);
wire csrv_mepc = (cadr_i == 12'h341);
wire csrv_mcause = (cadr_i == 12'h342);
wire csrv_mbadaddr = (cadr_i == 12'h343);
wire csrv_mip = (cadr_i == 12'h344);
wire csrv_mcycle = (cadr_i == 12'hF00);
wire csrv_mtime = (cadr_i == 12'hF01);
wire csrv_minstret = (cadr_i == 12'hF02);
assign cvalid_o = |{
csrv_misa, csrv_mvendorid, csrv_marchid,
csrv_mimpid, csrv_mhartid, csrv_mstatus,
csrv_medeleg, csrv_mideleg, csrv_mie,
csrv_mtvec, csrv_mscratch, csrv_mepc,
csrv_mcause, csrv_mbadaddr, csrv_mip,
csrv_mcycle, csrv_mtime, csrv_minstret
};
wire [63:0] csrd_misa = {2'b10, 36'd0, 26'b00000001000000000100000000};
wire [63:0] csrd_mvendorid = 64'd0;
wire [63:0] csrd_marchid = 64'd0;
wire [63:0] csrd_mimpid = 64'h1161008010000000;
wire [63:0] csrd_mhartid = 64'd0;
wire [63:0] csrd_mstatus = {
1'b0, // SD
34'd0, // reserved
5'b00000, // VM
4'b0000, // reserved
3'b000, // MXR, PUM, MPRV
2'b00, // XS
2'b00, // FS
2'b11, // MPP
2'b10, // HPP
1'b1, // SPP
mpie, 3'b000,
mie, 3'b000
};
wire [63:0] csrd_medeleg = 64'd0;
wire [63:0] csrd_mideleg = 64'd0;
wire [63:0] csrd_mie = {
52'd0,
irqEn,
11'd0
};
wire [63:0] csrd_mtvec = mtvec;
wire [63:0] csrd_mscratch = mscratch;
wire [63:0] csrd_mepc = mepc;
wire [63:0] csrd_mcause = {
mcause[4],
59'd0, // reserved
mcause[3:0]
};
wire [63:0] csrd_mbadaddr = mbadaddr;
wire [63:0] csrd_mip = {
52'd0,
irq_i,
11'd0
};
wire [63:0] csrd_mcycle = mcycle;
wire [63:0] csrd_mtime = mtime;
wire [63:0] csrd_minstret = minstret;
assign take_irq_o = mie & irqEn & irq_i;
assign cdat_o =
(csrv_misa ? csrd_misa : 0) |
(csrv_mvendorid ? csrd_mvendorid : 0) |
(csrv_marchid ? csrd_marchid : 0) |
(csrv_mimpid ? csrd_mimpid : 0) |
(csrv_mhartid ? csrd_mhartid : 0) |
(csrv_mstatus ? csrd_mstatus : 0) |
(csrv_medeleg ? csrd_medeleg : 0) |
(csrv_mideleg ? csrd_mideleg : 0) |
(csrv_mie ? csrd_mie : 0) |
(csrv_mtvec ? csrd_mtvec : 0) |
(csrv_mscratch ? csrd_mscratch : 0) |
(csrv_mepc ? csrd_mepc : 0) |
(csrv_mcause ? csrd_mcause : 0) |
(csrv_mbadaddr ? csrd_mbadaddr : 0) |
(csrv_mip ? csrd_mip : 0) |
(csrv_mcycle ? csrd_mcycle : 0) |
(csrv_mtime ? csrd_mtime : 0) |
(csrv_minstret ? csrd_minstret : 0);
wire irqEn_cdat = csrv_mie & cwe_i;
wire irqEn_irqEn = ~|{irqEn_cdat, reset_i};
wire irqEn_mux =
(irqEn_cdat ? cdat_i[11] : 0) |
(irqEn_irqEn ? irqEn : 0);
wire mstatus_we = csrv_mstatus & cwe_i;
wire mie_mie = ~|{mie_0, mie_mpie, mstatus_we};
assign mie_mux =
(mie_0 ? 0 : 0) |
(mie_mpie ? mpie : 0) |
(mstatus_we ? cdat_i[3] : 0) |
(mie_mie ? mie : 0);
wire mpie_mpie = ~|{mpie_mie, mpie_1, mstatus_we};
assign mpie_mux =
(mpie_mie ? mie : 0) |
(mpie_1 ? 1 : 0) |
(mstatus_we ? cdat_i[7] : 0) |
(mpie_mpie ? mpie : 0);
assign mie_o = mie;
assign mpie_o = mpie;
wire mtvec_we = csrv_mtvec & cwe_i;
wire mtvec_mtvec = ~|{mtvec_we, reset_i};
assign mtvec_mux =
(mtvec_we ? cdat_i : 0) |
(reset_i ? 64'hFFFF_FFFF_FFFF_FE00 : 0) |
(mtvec_mtvec ? mtvec : 0);
wire mscratch_we = csrv_mscratch & cwe_i;
assign mscratch_mux = (mscratch_we ? cdat_i : mscratch);
wire mepc_we = csrv_mepc & cwe_i;
wire mepc_mepc = ~|{mepc_we, mepc_ia, mepc_pc};
assign mepc_mux =
(mepc_we ? cdat_i : 0) |
(mepc_ia ? ia_i : 0) |
(mepc_pc ? pc_i : 0) |
(mepc_mepc ? mepc : 0);
wire mcause_we = csrv_mcause & cwe_i;
wire mcause_mcause = ~|{mcause_2, mcause_3, mcause_11, mcause_we};
assign cause_o = mcause_mux[3:0];
assign mcause_mux =
(mcause_we ? {cdat_i[63], cdat_i[3:0]} : 0) |
(mcause_2 ? {mcause_irq_i, 4'd2} : 0) |
(mcause_3 ? {mcause_irq_i, 4'd3} : 0) |
(mcause_11 ? {mcause_irq_i, 4'd11} : 0) |
(mcause_mcause ? mcause : 0);
wire mbadaddr_we = csrv_mbadaddr & cwe_i;
assign mbadaddr_mux = (mbadaddr_we ? cdat_i : mbadaddr);
assign mcycle_mux = (~reset_i ? mcycle + 1 : 0);
// assign minstret_mux =
// (~reset_i & ft0_i ? minstret + 64'd1 : 0) |
// (~reset_i & ~ft0_i ? minstret : 0);
assign mtime_mux =
(~reset_i & tick_i ? mtime + 64'd1 : 0) |
(~reset_i & ~tick_i ? mtime : 0);
always @(posedge clk_i) begin
minstret <= minstret;
if (reset_i) begin
minstret <= 64'd0;
end
else begin
if (ft0_i) begin
minstret <= minstret + 1;
end
end
end
always @(posedge clk_i) begin
mie <= mie_mux;
mpie <= mpie_mux;
mtvec <= mtvec_mux;
mscratch <= mscratch_mux;
mepc <= mepc_mux;
mcause <= mcause_mux;
mbadaddr <= mbadaddr_mux;
mcycle <= mcycle_mux;
// minstret <= minstret_mux;
mtime <= mtime_mux;
irqEn <= irqEn_mux;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: mig_7series_v2_3_poc_cc.v
// /___/ /\ Date Last Modified: $$
// \ \ / \ Date Created:Tue 20 Jan 2014
// \___\/\___\
//
//Device: Virtex-7
//Design Name: DDR3 SDRAM
//Purpose: Phaser out characterization and control. Logic to interface with
//Chipscope and control. Intended to support real time observation. Largely
//not generated for production implementations.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_poc_cc #
(parameter TCQ = 100,
parameter CCENABLE = 0,
parameter PCT_SAMPS_SOLID = 95,
parameter SAMPCNTRWIDTH = 8,
parameter SAMPLES = 128,
parameter TAPCNTRWIDTH = 7)
(/*AUTOARG*/
// Outputs
samples, samps_solid_thresh, poc_error,
// Inputs
tap, samps_hi_held, psen, clk, rst, ktap_at_right_edge,
ktap_at_left_edge, mmcm_lbclk_edge_aligned, mmcm_edge_detect_done,
fall_lead_right, fall_trail_right, rise_lead_right,
rise_trail_right, fall_lead_left, fall_trail_left, rise_lead_left,
rise_trail_left, fall_lead_center, fall_trail_center,
rise_lead_center, rise_trail_center
);
// Remember SAMPLES is whole number counting. Zero corresponds to one sample.
localparam integer SAMPS_SOLID_THRESH = (SAMPLES+1) * PCT_SAMPS_SOLID * 0.01;
output [SAMPCNTRWIDTH:0] samples, samps_solid_thresh;
input [TAPCNTRWIDTH-1:0] tap;
input [SAMPCNTRWIDTH:0] samps_hi_held;
input psen;
input clk, rst;
input ktap_at_right_edge, ktap_at_left_edge;
input mmcm_lbclk_edge_aligned;
wire reset_aligned_cnt = rst || ktap_at_right_edge || ktap_at_left_edge || mmcm_lbclk_edge_aligned;
input mmcm_edge_detect_done;
reg mmcm_edge_detect_done_r;
always @(posedge clk) mmcm_edge_detect_done_r <= #TCQ mmcm_edge_detect_done;
wire done = mmcm_edge_detect_done && ~mmcm_edge_detect_done_r;
reg [6:0] aligned_cnt_r;
wire [6:0] aligned_cnt_ns = reset_aligned_cnt ? 7'b0 : aligned_cnt_r + {6'b0, done};
always @(posedge clk) aligned_cnt_r <= #TCQ aligned_cnt_ns;
reg poc_error_r;
wire poc_error_ns = ~rst && (aligned_cnt_r[6] || poc_error_r);
always @(posedge clk) poc_error_r <= #TCQ poc_error_ns;
output poc_error;
assign poc_error = poc_error_r;
input [TAPCNTRWIDTH-1:0] fall_lead_right, fall_trail_right, rise_lead_right, rise_trail_right;
input [TAPCNTRWIDTH-1:0] fall_lead_left, fall_trail_left, rise_lead_left, rise_trail_left;
input [TAPCNTRWIDTH-1:0] fall_lead_center, fall_trail_center, rise_lead_center, rise_trail_center;
generate if (CCENABLE == 0) begin : no_characterization
assign samples = SAMPLES[SAMPCNTRWIDTH:0];
assign samps_solid_thresh = SAMPS_SOLID_THRESH[SAMPCNTRWIDTH:0];
end else begin : characterization
end endgenerate
endmodule // mig_7series_v2_3_poc_cc
|
/*
* % 3
*/
module modulus3
(
input [8:0] y,
output [1:0] m
);
// lookup function
function [1:0] MOD3;
input [8:0] y;
begin
case ( y )
0: MOD3 = 2'd0;
1: MOD3 = 2'd1;
2: MOD3 = 2'd2;
3: MOD3 = 2'd0;
4: MOD3 = 2'd1;
5: MOD3 = 2'd2;
6: MOD3 = 2'd0;
7: MOD3 = 2'd1;
8: MOD3 = 2'd2;
9: MOD3 = 2'd0;
10: MOD3 = 2'd1;
11: MOD3 = 2'd2;
12: MOD3 = 2'd0;
13: MOD3 = 2'd1;
14: MOD3 = 2'd2;
15: MOD3 = 2'd0;
16: MOD3 = 2'd1;
17: MOD3 = 2'd2;
18: MOD3 = 2'd0;
19: MOD3 = 2'd1;
20: MOD3 = 2'd2;
21: MOD3 = 2'd0;
22: MOD3 = 2'd1;
23: MOD3 = 2'd2;
24: MOD3 = 2'd0;
25: MOD3 = 2'd1;
26: MOD3 = 2'd2;
27: MOD3 = 2'd0;
28: MOD3 = 2'd1;
29: MOD3 = 2'd2;
30: MOD3 = 2'd0;
31: MOD3 = 2'd1;
32: MOD3 = 2'd2;
33: MOD3 = 2'd0;
34: MOD3 = 2'd1;
35: MOD3 = 2'd2;
36: MOD3 = 2'd0;
37: MOD3 = 2'd1;
38: MOD3 = 2'd2;
39: MOD3 = 2'd0;
40: MOD3 = 2'd1;
41: MOD3 = 2'd2;
42: MOD3 = 2'd0;
43: MOD3 = 2'd1;
44: MOD3 = 2'd2;
45: MOD3 = 2'd0;
46: MOD3 = 2'd1;
47: MOD3 = 2'd2;
48: MOD3 = 2'd0;
49: MOD3 = 2'd1;
50: MOD3 = 2'd2;
51: MOD3 = 2'd0;
52: MOD3 = 2'd1;
53: MOD3 = 2'd2;
54: MOD3 = 2'd0;
55: MOD3 = 2'd1;
56: MOD3 = 2'd2;
57: MOD3 = 2'd0;
58: MOD3 = 2'd1;
59: MOD3 = 2'd2;
60: MOD3 = 2'd0;
61: MOD3 = 2'd1;
62: MOD3 = 2'd2;
63: MOD3 = 2'd0;
64: MOD3 = 2'd1;
65: MOD3 = 2'd2;
66: MOD3 = 2'd0;
67: MOD3 = 2'd1;
68: MOD3 = 2'd2;
69: MOD3 = 2'd0;
70: MOD3 = 2'd1;
71: MOD3 = 2'd2;
72: MOD3 = 2'd0;
73: MOD3 = 2'd1;
74: MOD3 = 2'd2;
75: MOD3 = 2'd0;
76: MOD3 = 2'd1;
77: MOD3 = 2'd2;
78: MOD3 = 2'd0;
79: MOD3 = 2'd1;
80: MOD3 = 2'd2;
81: MOD3 = 2'd0;
82: MOD3 = 2'd1;
83: MOD3 = 2'd2;
84: MOD3 = 2'd0;
85: MOD3 = 2'd1;
86: MOD3 = 2'd2;
87: MOD3 = 2'd0;
88: MOD3 = 2'd1;
89: MOD3 = 2'd2;
90: MOD3 = 2'd0;
91: MOD3 = 2'd1;
92: MOD3 = 2'd2;
93: MOD3 = 2'd0;
94: MOD3 = 2'd1;
95: MOD3 = 2'd2;
96: MOD3 = 2'd0;
97: MOD3 = 2'd1;
98: MOD3 = 2'd2;
99: MOD3 = 2'd0;
100: MOD3 = 2'd1;
101: MOD3 = 2'd2;
102: MOD3 = 2'd0;
103: MOD3 = 2'd1;
104: MOD3 = 2'd2;
105: MOD3 = 2'd0;
106: MOD3 = 2'd1;
107: MOD3 = 2'd2;
108: MOD3 = 2'd0;
109: MOD3 = 2'd1;
110: MOD3 = 2'd2;
111: MOD3 = 2'd0;
112: MOD3 = 2'd1;
113: MOD3 = 2'd2;
114: MOD3 = 2'd0;
115: MOD3 = 2'd1;
116: MOD3 = 2'd2;
117: MOD3 = 2'd0;
118: MOD3 = 2'd1;
119: MOD3 = 2'd2;
120: MOD3 = 2'd0;
121: MOD3 = 2'd1;
122: MOD3 = 2'd2;
123: MOD3 = 2'd0;
124: MOD3 = 2'd1;
125: MOD3 = 2'd2;
126: MOD3 = 2'd0;
127: MOD3 = 2'd1;
128: MOD3 = 2'd2;
129: MOD3 = 2'd0;
130: MOD3 = 2'd1;
131: MOD3 = 2'd2;
132: MOD3 = 2'd0;
133: MOD3 = 2'd1;
134: MOD3 = 2'd2;
135: MOD3 = 2'd0;
136: MOD3 = 2'd1;
137: MOD3 = 2'd2;
138: MOD3 = 2'd0;
139: MOD3 = 2'd1;
140: MOD3 = 2'd2;
141: MOD3 = 2'd0;
142: MOD3 = 2'd1;
143: MOD3 = 2'd2;
144: MOD3 = 2'd0;
145: MOD3 = 2'd1;
146: MOD3 = 2'd2;
147: MOD3 = 2'd0;
148: MOD3 = 2'd1;
149: MOD3 = 2'd2;
150: MOD3 = 2'd0;
151: MOD3 = 2'd1;
152: MOD3 = 2'd2;
153: MOD3 = 2'd0;
154: MOD3 = 2'd1;
155: MOD3 = 2'd2;
156: MOD3 = 2'd0;
157: MOD3 = 2'd1;
158: MOD3 = 2'd2;
159: MOD3 = 2'd0;
160: MOD3 = 2'd1;
161: MOD3 = 2'd2;
162: MOD3 = 2'd0;
163: MOD3 = 2'd1;
164: MOD3 = 2'd2;
165: MOD3 = 2'd0;
166: MOD3 = 2'd1;
167: MOD3 = 2'd2;
168: MOD3 = 2'd0;
169: MOD3 = 2'd1;
170: MOD3 = 2'd2;
171: MOD3 = 2'd0;
172: MOD3 = 2'd1;
173: MOD3 = 2'd2;
174: MOD3 = 2'd0;
175: MOD3 = 2'd1;
176: MOD3 = 2'd2;
177: MOD3 = 2'd0;
178: MOD3 = 2'd1;
179: MOD3 = 2'd2;
180: MOD3 = 2'd0;
181: MOD3 = 2'd1;
182: MOD3 = 2'd2;
183: MOD3 = 2'd0;
184: MOD3 = 2'd1;
185: MOD3 = 2'd2;
186: MOD3 = 2'd0;
187: MOD3 = 2'd1;
188: MOD3 = 2'd2;
189: MOD3 = 2'd0;
190: MOD3 = 2'd1;
191: MOD3 = 2'd2;
192: MOD3 = 2'd0;
193: MOD3 = 2'd1;
194: MOD3 = 2'd2;
195: MOD3 = 2'd0;
196: MOD3 = 2'd1;
197: MOD3 = 2'd2;
198: MOD3 = 2'd0;
199: MOD3 = 2'd1;
200: MOD3 = 2'd2;
201: MOD3 = 2'd0;
202: MOD3 = 2'd1;
203: MOD3 = 2'd2;
204: MOD3 = 2'd0;
205: MOD3 = 2'd1;
206: MOD3 = 2'd2;
207: MOD3 = 2'd0;
208: MOD3 = 2'd1;
209: MOD3 = 2'd2;
210: MOD3 = 2'd0;
211: MOD3 = 2'd1;
212: MOD3 = 2'd2;
213: MOD3 = 2'd0;
214: MOD3 = 2'd1;
215: MOD3 = 2'd2;
216: MOD3 = 2'd0;
217: MOD3 = 2'd1;
218: MOD3 = 2'd2;
219: MOD3 = 2'd0;
220: MOD3 = 2'd1;
221: MOD3 = 2'd2;
222: MOD3 = 2'd0;
223: MOD3 = 2'd1;
224: MOD3 = 2'd2;
225: MOD3 = 2'd0;
226: MOD3 = 2'd1;
227: MOD3 = 2'd2;
228: MOD3 = 2'd0;
229: MOD3 = 2'd1;
230: MOD3 = 2'd2;
231: MOD3 = 2'd0;
232: MOD3 = 2'd1;
233: MOD3 = 2'd2;
234: MOD3 = 2'd0;
235: MOD3 = 2'd1;
236: MOD3 = 2'd2;
237: MOD3 = 2'd0;
238: MOD3 = 2'd1;
239: MOD3 = 2'd2;
240: MOD3 = 2'd0;
241: MOD3 = 2'd1;
242: MOD3 = 2'd2;
243: MOD3 = 2'd0;
244: MOD3 = 2'd1;
245: MOD3 = 2'd2;
246: MOD3 = 2'd0;
247: MOD3 = 2'd1;
248: MOD3 = 2'd2;
249: MOD3 = 2'd0;
250: MOD3 = 2'd1;
251: MOD3 = 2'd2;
252: MOD3 = 2'd0;
253: MOD3 = 2'd1;
254: MOD3 = 2'd2;
255: MOD3 = 2'd0;
256: MOD3 = 2'd1;
257: MOD3 = 2'd2;
258: MOD3 = 2'd0;
259: MOD3 = 2'd1;
260: MOD3 = 2'd2;
261: MOD3 = 2'd0;
262: MOD3 = 2'd1;
263: MOD3 = 2'd2;
264: MOD3 = 2'd0;
265: MOD3 = 2'd1;
266: MOD3 = 2'd2;
267: MOD3 = 2'd0;
268: MOD3 = 2'd1;
269: MOD3 = 2'd2;
270: MOD3 = 2'd0;
271: MOD3 = 2'd1;
272: MOD3 = 2'd2;
273: MOD3 = 2'd0;
274: MOD3 = 2'd1;
275: MOD3 = 2'd2;
276: MOD3 = 2'd0;
277: MOD3 = 2'd1;
278: MOD3 = 2'd2;
279: MOD3 = 2'd0;
280: MOD3 = 2'd1;
281: MOD3 = 2'd2;
282: MOD3 = 2'd0;
283: MOD3 = 2'd1;
284: MOD3 = 2'd2;
285: MOD3 = 2'd0;
286: MOD3 = 2'd1;
287: MOD3 = 2'd2;
288: MOD3 = 2'd0;
289: MOD3 = 2'd1;
290: MOD3 = 2'd2;
291: MOD3 = 2'd0;
292: MOD3 = 2'd1;
293: MOD3 = 2'd2;
294: MOD3 = 2'd0;
295: MOD3 = 2'd1;
296: MOD3 = 2'd2;
297: MOD3 = 2'd0;
298: MOD3 = 2'd1;
299: MOD3 = 2'd2;
300: MOD3 = 2'd0;
301: MOD3 = 2'd1;
302: MOD3 = 2'd2;
303: MOD3 = 2'd0;
304: MOD3 = 2'd1;
305: MOD3 = 2'd2;
306: MOD3 = 2'd0;
307: MOD3 = 2'd1;
308: MOD3 = 2'd2;
309: MOD3 = 2'd0;
310: MOD3 = 2'd1;
311: MOD3 = 2'd2;
312: MOD3 = 2'd0;
313: MOD3 = 2'd1;
314: MOD3 = 2'd2;
315: MOD3 = 2'd0;
316: MOD3 = 2'd1;
317: MOD3 = 2'd2;
318: MOD3 = 2'd0;
319: MOD3 = 2'd1;
320: MOD3 = 2'd2;
321: MOD3 = 2'd0;
322: MOD3 = 2'd1;
323: MOD3 = 2'd2;
324: MOD3 = 2'd0;
325: MOD3 = 2'd1;
326: MOD3 = 2'd2;
327: MOD3 = 2'd0;
328: MOD3 = 2'd1;
329: MOD3 = 2'd2;
330: MOD3 = 2'd0;
331: MOD3 = 2'd1;
332: MOD3 = 2'd2;
333: MOD3 = 2'd0;
334: MOD3 = 2'd1;
335: MOD3 = 2'd2;
336: MOD3 = 2'd0;
337: MOD3 = 2'd1;
338: MOD3 = 2'd2;
339: MOD3 = 2'd0;
340: MOD3 = 2'd1;
341: MOD3 = 2'd2;
342: MOD3 = 2'd0;
343: MOD3 = 2'd1;
344: MOD3 = 2'd2;
345: MOD3 = 2'd0;
346: MOD3 = 2'd1;
347: MOD3 = 2'd2;
348: MOD3 = 2'd0;
349: MOD3 = 2'd1;
350: MOD3 = 2'd2;
351: MOD3 = 2'd0;
352: MOD3 = 2'd1;
353: MOD3 = 2'd2;
354: MOD3 = 2'd0;
355: MOD3 = 2'd1;
356: MOD3 = 2'd2;
357: MOD3 = 2'd0;
358: MOD3 = 2'd1;
359: MOD3 = 2'd2;
360: MOD3 = 2'd0;
361: MOD3 = 2'd1;
362: MOD3 = 2'd2;
363: MOD3 = 2'd0;
364: MOD3 = 2'd1;
365: MOD3 = 2'd2;
366: MOD3 = 2'd0;
367: MOD3 = 2'd1;
368: MOD3 = 2'd2;
369: MOD3 = 2'd0;
370: MOD3 = 2'd1;
371: MOD3 = 2'd2;
372: MOD3 = 2'd0;
373: MOD3 = 2'd1;
374: MOD3 = 2'd2;
375: MOD3 = 2'd0;
376: MOD3 = 2'd1;
377: MOD3 = 2'd2;
378: MOD3 = 2'd0;
379: MOD3 = 2'd1;
380: MOD3 = 2'd2;
381: MOD3 = 2'd0;
382: MOD3 = 2'd1;
383: MOD3 = 2'd2;
384: MOD3 = 2'd0;
385: MOD3 = 2'd1;
386: MOD3 = 2'd2;
387: MOD3 = 2'd0;
388: MOD3 = 2'd1;
389: MOD3 = 2'd2;
390: MOD3 = 2'd0;
391: MOD3 = 2'd1;
392: MOD3 = 2'd2;
393: MOD3 = 2'd0;
394: MOD3 = 2'd1;
395: MOD3 = 2'd2;
396: MOD3 = 2'd0;
397: MOD3 = 2'd1;
398: MOD3 = 2'd2;
399: MOD3 = 2'd0;
400: MOD3 = 2'd1;
401: MOD3 = 2'd2;
402: MOD3 = 2'd0;
403: MOD3 = 2'd1;
404: MOD3 = 2'd2;
405: MOD3 = 2'd0;
406: MOD3 = 2'd1;
407: MOD3 = 2'd2;
408: MOD3 = 2'd0;
409: MOD3 = 2'd1;
410: MOD3 = 2'd2;
411: MOD3 = 2'd0;
412: MOD3 = 2'd1;
413: MOD3 = 2'd2;
414: MOD3 = 2'd0;
415: MOD3 = 2'd1;
416: MOD3 = 2'd2;
417: MOD3 = 2'd0;
418: MOD3 = 2'd1;
419: MOD3 = 2'd2;
420: MOD3 = 2'd0;
421: MOD3 = 2'd1;
422: MOD3 = 2'd2;
423: MOD3 = 2'd0;
424: MOD3 = 2'd1;
425: MOD3 = 2'd2;
426: MOD3 = 2'd0;
427: MOD3 = 2'd1;
428: MOD3 = 2'd2;
429: MOD3 = 2'd0;
430: MOD3 = 2'd1;
431: MOD3 = 2'd2;
432: MOD3 = 2'd0;
433: MOD3 = 2'd1;
434: MOD3 = 2'd2;
435: MOD3 = 2'd0;
436: MOD3 = 2'd1;
437: MOD3 = 2'd2;
438: MOD3 = 2'd0;
439: MOD3 = 2'd1;
440: MOD3 = 2'd2;
441: MOD3 = 2'd0;
442: MOD3 = 2'd1;
443: MOD3 = 2'd2;
444: MOD3 = 2'd0;
445: MOD3 = 2'd1;
446: MOD3 = 2'd2;
447: MOD3 = 2'd0;
448: MOD3 = 2'd1;
449: MOD3 = 2'd2;
450: MOD3 = 2'd0;
451: MOD3 = 2'd1;
452: MOD3 = 2'd2;
453: MOD3 = 2'd0;
454: MOD3 = 2'd1;
455: MOD3 = 2'd2;
456: MOD3 = 2'd0;
457: MOD3 = 2'd1;
458: MOD3 = 2'd2;
459: MOD3 = 2'd0;
460: MOD3 = 2'd1;
461: MOD3 = 2'd2;
462: MOD3 = 2'd0;
463: MOD3 = 2'd1;
464: MOD3 = 2'd2;
465: MOD3 = 2'd0;
466: MOD3 = 2'd1;
467: MOD3 = 2'd2;
468: MOD3 = 2'd0;
469: MOD3 = 2'd1;
470: MOD3 = 2'd2;
471: MOD3 = 2'd0;
472: MOD3 = 2'd1;
473: MOD3 = 2'd2;
474: MOD3 = 2'd0;
475: MOD3 = 2'd1;
476: MOD3 = 2'd2;
477: MOD3 = 2'd0;
478: MOD3 = 2'd1;
479: MOD3 = 2'd2;
480: MOD3 = 2'd0;
481: MOD3 = 2'd1;
482: MOD3 = 2'd2;
483: MOD3 = 2'd0;
484: MOD3 = 2'd1;
485: MOD3 = 2'd2;
486: MOD3 = 2'd0;
487: MOD3 = 2'd1;
488: MOD3 = 2'd2;
489: MOD3 = 2'd0;
490: MOD3 = 2'd1;
491: MOD3 = 2'd2;
492: MOD3 = 2'd0;
493: MOD3 = 2'd1;
494: MOD3 = 2'd2;
495: MOD3 = 2'd0;
496: MOD3 = 2'd1;
497: MOD3 = 2'd2;
498: MOD3 = 2'd0;
499: MOD3 = 2'd1;
500: MOD3 = 2'd2;
501: MOD3 = 2'd0;
502: MOD3 = 2'd1;
503: MOD3 = 2'd2;
504: MOD3 = 2'd0;
505: MOD3 = 2'd1;
506: MOD3 = 2'd2;
507: MOD3 = 2'd0;
508: MOD3 = 2'd1;
509: MOD3 = 2'd2;
510: MOD3 = 2'd0;
511: MOD3 = 2'd1;
default: MOD3 = 2'd0;
endcase
end
endfunction
assign m = MOD3( y );
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_arb_rd.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between 2 read requests from 2 ports.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_arb_rd(
rstn,
sw_clk,
qos1,
qos2,
prt_req1,
prt_req2,
prt_bytes1,
prt_bytes2,
prt_addr1,
prt_addr2,
prt_data1,
prt_data2,
prt_dv1,
prt_dv2,
prt_req,
prt_qos,
prt_addr,
prt_bytes,
prt_data,
prt_dv
);
`include "processing_system7_bfm_v2_0_5_local_params.v"
input rstn, sw_clk;
input [axi_qos_width-1:0] qos1,qos2;
input prt_req1, prt_req2;
input [addr_width-1:0] prt_addr1, prt_addr2;
input [max_burst_bytes_width:0] prt_bytes1, prt_bytes2;
output reg prt_dv1, prt_dv2;
output reg [max_burst_bits-1:0] prt_data1,prt_data2;
output reg prt_req;
output reg [axi_qos_width-1:0] prt_qos;
output reg [addr_width-1:0] prt_addr;
output reg [max_burst_bytes_width:0] prt_bytes;
input [max_burst_bits-1:0] prt_data;
input prt_dv;
parameter wait_req = 2'b00, serv_req1 = 2'b01, serv_req2 = 2'b10,wait_dv_low = 2'b11;
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
state = wait_req;
prt_req = 1'b0;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_qos = 0;
end else begin
case(state)
wait_req:begin
state = wait_req;
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
prt_req = 0;
if(prt_req1 && !prt_req2) begin
state = serv_req1;
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
end else if(!prt_req1 && prt_req2) begin
state = serv_req2;
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
end else if(prt_req1 && prt_req2) begin
if(qos1 > qos2) begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else if(qos1 < qos2) begin
prt_req = 1;
prt_addr = prt_addr2;
prt_qos = qos2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end
end
end
serv_req1:begin
state = serv_req1;
prt_dv2 = 1'b0;
if(prt_dv) begin
prt_dv1 = 1'b1;
prt_data1 = prt_data;
prt_req = 0;
if(prt_req2) begin
prt_req = 1;
prt_qos = qos2;
prt_addr = prt_addr2;
prt_bytes = prt_bytes2;
state = serv_req2;
end else begin
state = wait_dv_low;
//state = wait_req;
end
end
end
serv_req2:begin
state = serv_req2;
prt_dv1 = 1'b0;
if(prt_dv) begin
prt_dv2 = 1'b1;
prt_data2 = prt_data;
prt_req = 0;
if(prt_req1) begin
prt_req = 1;
prt_qos = qos1;
prt_addr = prt_addr1;
prt_bytes = prt_bytes1;
state = serv_req1;
end else begin
state = wait_dv_low;
//state = wait_req;
end
end
end
wait_dv_low:begin
prt_dv1 = 1'b0;
prt_dv2 = 1'b0;
state = wait_dv_low;
if(!prt_dv)
state = wait_req;
end
endcase
end /// if else
end /// always
endmodule
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module RegTwoN(CLK, RST, Q_OUT, D_INA, ENA, D_INB, ENB);
parameter width = 1;
parameter init = {width {1'b0}} ;
input CLK;
input RST;
input ENA, ENB;
input [width - 1 : 0] D_INA;
input [width - 1 : 0] D_INB;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] Q_OUT;
always@(posedge CLK)
begin
if (RST == `BSV_RESET_VALUE)
Q_OUT <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if (ENA)
Q_OUT <= `BSV_ASSIGNMENT_DELAY D_INA;
else if (ENB)
Q_OUT <= `BSV_ASSIGNMENT_DELAY D_INB;
end // else: !if(RST == `BSV_RESET_VALUE)
end // always@ (posedge CLK)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
Q_OUT = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_wrlvl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/24 14:49:00 $
// \ \ / \ Date Created: Mon Jun 23 2008
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// Memory initialization and overall master state control during
// initialization and calibration. Specifically, the following functions
// are performed:
// 1. Memory initialization (initial AR, mode register programming, etc.)
// 2. Initiating write leveling
// 3. Generate training pattern writes for read leveling. Generate
// memory readback for read leveling.
// This module has a DFI interface for providing control/address and write
// data to the rest of the PHY datapath during initialization/calibration.
// Once initialization is complete, control is passed to the MC.
// NOTES:
// 1. Multiple CS (multi-rank) not supported
// 2. DDR2 not supported
// 3. ODT not supported
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: ddr_phy_wrlvl.v,v 1.3 2011/06/24 14:49:00 mgeorge Exp $
**$Date: 2011/06/24 14:49:00 $
**$Author: mgeorge $
**$Revision: 1.3 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_phy_wrlvl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_wrlvl #
(
parameter TCQ = 100,
parameter DQS_CNT_WIDTH = 3,
parameter DQ_WIDTH = 64,
parameter DQS_WIDTH = 2,
parameter DRAM_WIDTH = 8,
parameter RANKS = 1,
parameter nCK_PER_CLK = 4,
parameter CLK_PERIOD = 4,
parameter SIM_CAL_OPTION = "NONE"
)
(
input clk,
input rst,
input phy_ctl_ready,
input wr_level_start,
input wl_sm_start,
input wrlvl_final,
input wrlvl_byte_redo,
input [DQS_CNT_WIDTH:0] wrcal_cnt,
input early1_data,
input early2_data,
input [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt,
input oclkdelay_calib_done,
input [(DQ_WIDTH)-1:0] rd_data_rise0,
output reg wrlvl_byte_done,
output reg dqs_po_dec_done /* synthesis syn_maxfan = 2 */,
output phy_ctl_rdy_dly,
output reg wr_level_done /* synthesis syn_maxfan = 2 */,
// to phy_init for cs logic
output wrlvl_rank_done,
output done_dqs_tap_inc,
output [DQS_CNT_WIDTH:0] po_stg2_wl_cnt,
// Fine delay line used only during write leveling
// Inc/dec Phaser_Out fine delay line
output reg dqs_po_stg2_f_incdec,
// Enable Phaser_Out fine delay inc/dec
output reg dqs_po_en_stg2_f,
// Coarse delay line used during write leveling
// only if 64 taps of fine delay line were not
// sufficient to detect a 0->1 transition
// Inc Phaser_Out coarse delay line
output reg dqs_wl_po_stg2_c_incdec,
// Enable Phaser_Out coarse delay inc/dec
output reg dqs_wl_po_en_stg2_c,
// Read Phaser_Out delay value
input [8:0] po_counter_read_val,
// output reg dqs_wl_po_stg2_load,
// output reg [8:0] dqs_wl_po_stg2_reg_l,
// CK edge undetected
output reg wrlvl_err,
output reg [3*DQS_WIDTH-1:0] wl_po_coarse_cnt,
output reg [6*DQS_WIDTH-1:0] wl_po_fine_cnt,
// Debug ports
output [5:0] dbg_wl_tap_cnt,
output dbg_wl_edge_detect_valid,
output [(DQS_WIDTH)-1:0] dbg_rd_data_edge_detect,
output [DQS_CNT_WIDTH:0] dbg_dqs_count,
output [4:0] dbg_wl_state,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output [255:0] dbg_phy_wrlvl
);
localparam WL_IDLE = 5'h0;
localparam WL_INIT = 5'h1;
localparam WL_INIT_FINE_INC = 5'h2;
localparam WL_INIT_FINE_INC_WAIT1= 5'h3;
localparam WL_INIT_FINE_INC_WAIT = 5'h4;
localparam WL_INIT_FINE_DEC = 5'h5;
localparam WL_INIT_FINE_DEC_WAIT = 5'h6;
localparam WL_FINE_INC = 5'h7;
localparam WL_WAIT = 5'h8;
localparam WL_EDGE_CHECK = 5'h9;
localparam WL_DQS_CHECK = 5'hA;
localparam WL_DQS_CNT = 5'hB;
localparam WL_2RANK_TAP_DEC = 5'hC;
localparam WL_2RANK_DQS_CNT = 5'hD;
localparam WL_FINE_DEC = 5'hE;
localparam WL_FINE_DEC_WAIT = 5'hF;
localparam WL_CORSE_INC = 5'h10;
localparam WL_CORSE_INC_WAIT = 5'h11;
localparam WL_CORSE_INC_WAIT1 = 5'h12;
localparam WL_CORSE_INC_WAIT2 = 5'h13;
localparam WL_CORSE_DEC = 5'h14;
localparam WL_CORSE_DEC_WAIT = 5'h15;
localparam WL_CORSE_DEC_WAIT1 = 5'h16;
localparam WL_FINE_INC_WAIT = 5'h17;
localparam WL_2RANK_FINAL_TAP = 5'h18;
localparam WL_INIT_FINE_DEC_WAIT1= 5'h19;
localparam WL_FINE_DEC_WAIT1 = 5'h1A;
localparam WL_CORSE_INC_WAIT_TMP = 5'h1B;
localparam COARSE_TAPS = 7;
localparam FAST_CAL_FINE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 45 : 48;
localparam FAST_CAL_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 1 : 2;
localparam REDO_COARSE = (CLK_PERIOD/nCK_PER_CLK <= 2500) ? 2 : 5;
integer i, j, k, l, p, q, r, s, t, m, n, u, v, w, x,y;
reg phy_ctl_ready_r1;
reg phy_ctl_ready_r2;
reg phy_ctl_ready_r3;
reg phy_ctl_ready_r4;
reg phy_ctl_ready_r5;
reg phy_ctl_ready_r6;
(* max_fanout = 50 *) reg [DQS_CNT_WIDTH:0] dqs_count_r;
reg [1:0] rank_cnt_r;
reg [DQS_WIDTH-1:0] rd_data_rise_wl_r;
reg [DQS_WIDTH-1:0] rd_data_previous_r;
reg [DQS_WIDTH-1:0] rd_data_edge_detect_r;
reg wr_level_done_r;
reg wrlvl_rank_done_r;
reg wr_level_start_r;
reg [4:0] wl_state_r, wl_state_r1;
reg inhibit_edge_detect_r;
reg wl_edge_detect_valid_r;
reg [5:0] wl_tap_count_r;
reg [5:0] fine_dec_cnt;
reg [5:0] fine_inc[0:DQS_WIDTH-1]; // DQS_WIDTH number of counters 6-bit each
reg [2:0] corse_dec[0:DQS_WIDTH-1];
reg [2:0] corse_inc[0:DQS_WIDTH-1];
reg dq_cnt_inc;
reg [3:0] stable_cnt;
reg flag_ck_negedge;
//reg past_negedge;
reg flag_init;
reg [2:0] corse_cnt[0:DQS_WIDTH-1];
reg [3*DQS_WIDTH-1:0] corse_cnt_dbg;
reg [2:0] wl_corse_cnt[0:RANKS-1][0:DQS_WIDTH-1];
//reg [3*DQS_WIDTH-1:0] coarse_tap_inc;
reg [2:0] final_coarse_tap[0:DQS_WIDTH-1];
reg [5:0] add_smallest[0:DQS_WIDTH-1];
reg [5:0] add_largest[0:DQS_WIDTH-1];
//reg [6*DQS_WIDTH-1:0] fine_tap_inc;
//reg [6*DQS_WIDTH-1:0] fine_tap_dec;
reg wr_level_done_r1;
reg wr_level_done_r2;
reg wr_level_done_r3;
reg wr_level_done_r4;
reg wr_level_done_r5;
reg [5:0] wl_dqs_tap_count_r[0:RANKS-1][0:DQS_WIDTH-1];
reg [5:0] smallest[0:DQS_WIDTH-1];
reg [5:0] largest[0:DQS_WIDTH-1];
reg [5:0] final_val[0:DQS_WIDTH-1];
reg [5:0] po_dec_cnt[0:DQS_WIDTH-1];
reg done_dqs_dec;
reg [8:0] po_rdval_cnt;
reg po_cnt_dec;
reg po_dec_done;
reg dual_rnk_dec;
wire [DQS_CNT_WIDTH+2:0] dqs_count_w;
reg [5:0] fast_cal_fine_cnt;
reg [2:0] fast_cal_coarse_cnt;
reg wrlvl_byte_redo_r;
reg [2:0] wrlvl_redo_corse_inc;
reg wrlvl_final_r;
reg final_corse_dec;
wire [DQS_CNT_WIDTH+2:0] oclk_count_w;
reg wrlvl_tap_done_r ;
reg [3:0] wait_cnt;
reg [3:0] incdec_wait_cnt;
// Debug ports
assign dbg_wl_edge_detect_valid = wl_edge_detect_valid_r;
assign dbg_rd_data_edge_detect = rd_data_edge_detect_r;
assign dbg_wl_tap_cnt = wl_tap_count_r;
assign dbg_dqs_count = dqs_count_r;
assign dbg_wl_state = wl_state_r;
assign dbg_wrlvl_fine_tap_cnt = wl_po_fine_cnt;
assign dbg_wrlvl_coarse_tap_cnt = wl_po_coarse_cnt;
always @(*) begin
for (v = 0; v < DQS_WIDTH; v = v + 1)
corse_cnt_dbg[3*v+:3] = corse_cnt[v];
end
assign dbg_phy_wrlvl[0+:27] = corse_cnt_dbg;
assign dbg_phy_wrlvl[27+:5] = wl_state_r;
assign dbg_phy_wrlvl[32+:4] = dqs_count_r;
assign dbg_phy_wrlvl[36+:9] = rd_data_rise_wl_r;
assign dbg_phy_wrlvl[45+:9] = rd_data_previous_r;
assign dbg_phy_wrlvl[54+:4] = stable_cnt;
assign dbg_phy_wrlvl[58] = 'd0;
assign dbg_phy_wrlvl[59] = flag_ck_negedge;
assign dbg_phy_wrlvl [60] = wl_edge_detect_valid_r;
assign dbg_phy_wrlvl [61+:6] = wl_tap_count_r;
assign dbg_phy_wrlvl [67+:9] = rd_data_edge_detect_r;
assign dbg_phy_wrlvl [76+:54] = wl_po_fine_cnt;
assign dbg_phy_wrlvl [130+:27] = wl_po_coarse_cnt;
//**************************************************************************
// DQS count to hard PHY during write leveling using Phaser_OUT Stage2 delay
//**************************************************************************
assign po_stg2_wl_cnt = dqs_count_r;
assign wrlvl_rank_done = wrlvl_rank_done_r;
assign done_dqs_tap_inc = done_dqs_dec;
assign phy_ctl_rdy_dly = phy_ctl_ready_r6;
always @(posedge clk) begin
phy_ctl_ready_r1 <= #TCQ phy_ctl_ready;
phy_ctl_ready_r2 <= #TCQ phy_ctl_ready_r1;
phy_ctl_ready_r3 <= #TCQ phy_ctl_ready_r2;
phy_ctl_ready_r4 <= #TCQ phy_ctl_ready_r3;
phy_ctl_ready_r5 <= #TCQ phy_ctl_ready_r4;
phy_ctl_ready_r6 <= #TCQ phy_ctl_ready_r5;
wrlvl_byte_redo_r <= #TCQ wrlvl_byte_redo;
wrlvl_final_r <= #TCQ wrlvl_final;
if ((wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||
(wrlvl_final && ~wrlvl_final_r))
wr_level_done <= #TCQ 1'b0;
else
wr_level_done <= #TCQ done_dqs_dec;
end
// Status signal that will be asserted once the first
// pass of write leveling is done.
always @(posedge clk) begin
if(rst) begin
wrlvl_tap_done_r <= #TCQ 1'b0 ;
end else begin
if(wrlvl_tap_done_r == 1'b0) begin
if(oclkdelay_calib_done) begin
wrlvl_tap_done_r <= #TCQ 1'b1 ;
end
end
end
end
always @(posedge clk) begin
if (rst || po_cnt_dec)
wait_cnt <= #TCQ 'd8;
else if (phy_ctl_ready_r6 && (wait_cnt > 'd0))
wait_cnt <= #TCQ wait_cnt - 1;
end
always @(posedge clk) begin
if (rst) begin
po_rdval_cnt <= #TCQ 'd0;
end else if (phy_ctl_ready_r5 && ~phy_ctl_ready_r6) begin
po_rdval_cnt <= #TCQ po_counter_read_val;
end else if (po_rdval_cnt > 'd0) begin
if (po_cnt_dec)
po_rdval_cnt <= #TCQ po_rdval_cnt - 1;
else
po_rdval_cnt <= #TCQ po_rdval_cnt;
end else if (po_rdval_cnt == 'd0) begin
po_rdval_cnt <= #TCQ po_rdval_cnt;
end
end
always @(posedge clk) begin
if (rst || (po_rdval_cnt == 'd0))
po_cnt_dec <= #TCQ 1'b0;
else if (phy_ctl_ready_r6 && (po_rdval_cnt > 'd0) && (wait_cnt == 'd1))
po_cnt_dec <= #TCQ 1'b1;
else
po_cnt_dec <= #TCQ 1'b0;
end
always @(posedge clk) begin
if (rst)
po_dec_done <= #TCQ 1'b0;
else if (((po_cnt_dec == 'd1) && (po_rdval_cnt == 'd1)) ||
(phy_ctl_ready_r6 && (po_rdval_cnt == 'd0))) begin
po_dec_done <= #TCQ 1'b1;
end
end
always @(posedge clk) begin
dqs_po_dec_done <= #TCQ po_dec_done;
wr_level_done_r1 <= #TCQ wr_level_done_r;
wr_level_done_r2 <= #TCQ wr_level_done_r1;
wr_level_done_r3 <= #TCQ wr_level_done_r2;
wr_level_done_r4 <= #TCQ wr_level_done_r3;
wr_level_done_r5 <= #TCQ wr_level_done_r4;
for (l = 0; l < DQS_WIDTH; l = l + 1) begin
wl_po_coarse_cnt[3*l+:3] <= #TCQ final_coarse_tap[l];
if ((RANKS == 1) || ~oclkdelay_calib_done)
wl_po_fine_cnt[6*l+:6] <= #TCQ smallest[l];
else
wl_po_fine_cnt[6*l+:6] <= #TCQ final_val[l];
end
end
generate
if (RANKS == 2) begin: dual_rank
always @(posedge clk) begin
if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||
(wrlvl_final && ~wrlvl_final_r))
done_dqs_dec <= #TCQ 1'b0;
else if ((SIM_CAL_OPTION == "FAST_CAL") || ~oclkdelay_calib_done)
done_dqs_dec <= #TCQ wr_level_done_r;
else if (wr_level_done_r5 && (wl_state_r == WL_IDLE))
done_dqs_dec <= #TCQ 1'b1;
end
end else begin: single_rank
always @(posedge clk) begin
if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r) ||
(wrlvl_final && ~wrlvl_final_r))
done_dqs_dec <= #TCQ 1'b0;
else if (~oclkdelay_calib_done)
done_dqs_dec <= #TCQ wr_level_done_r;
else if (wr_level_done_r3 && ~wr_level_done_r4)
done_dqs_dec <= #TCQ 1'b1;
end
end
endgenerate
always @(posedge clk)
if (rst || (wrlvl_byte_redo && ~wrlvl_byte_redo_r))
wrlvl_byte_done <= #TCQ 1'b0;
else if (wrlvl_byte_redo && wr_level_done_r3 && ~wr_level_done_r4)
wrlvl_byte_done <= #TCQ 1'b1;
// Storing DQS tap values at the end of each DQS write leveling
always @(posedge clk) begin
if (rst) begin
for (k = 0; k < RANKS; k = k + 1) begin: rst_wl_dqs_tap_count_loop
for (n = 0; n < DQS_WIDTH; n = n + 1) begin
wl_corse_cnt[k][n] <= #TCQ 'b0;
wl_dqs_tap_count_r[k][n] <= #TCQ 'b0;
end
end
end else if ((wl_state_r == WL_DQS_CNT) | (wl_state_r == WL_WAIT) |
(wl_state_r == WL_FINE_DEC_WAIT1) |
(wl_state_r == WL_2RANK_TAP_DEC)) begin
wl_dqs_tap_count_r[rank_cnt_r][dqs_count_r] <= #TCQ wl_tap_count_r;
wl_corse_cnt[rank_cnt_r][dqs_count_r] <= #TCQ corse_cnt[dqs_count_r];
end else if ((SIM_CAL_OPTION == "FAST_CAL") & (wl_state_r == WL_DQS_CHECK)) begin
for (p = 0; p < RANKS; p = p +1) begin: dqs_tap_rank_cnt
for(q = 0; q < DQS_WIDTH; q = q +1) begin: dqs_tap_dqs_cnt
wl_dqs_tap_count_r[p][q] <= #TCQ wl_tap_count_r;
wl_corse_cnt[p][q] <= #TCQ corse_cnt[0];
end
end
end
end
// Convert coarse delay to fine taps in case of unequal number of coarse
// taps between ranks. Assuming a difference of 1 coarse tap counts
// between ranks. A common fine and coarse tap value must be used for both ranks
// because Phaser_Out has only one rank register.
// Coarse tap1 = period(ps)*93/360 = 34 fine taps
// Other coarse taps = period(ps)*103/360 = 38 fine taps
generate
genvar cnt;
if (RANKS == 2) begin // Dual rank
for(cnt = 0; cnt < DQS_WIDTH; cnt = cnt +1) begin: coarse_dqs_cnt
always @(posedge clk) begin
if (rst) begin
//coarse_tap_inc[3*cnt+:3] <= #TCQ 'b0;
add_smallest[cnt] <= #TCQ 'd0;
add_largest[cnt] <= #TCQ 'd0;
final_coarse_tap[cnt] <= #TCQ 'd0;
end else if (wr_level_done_r1 & ~wr_level_done_r2) begin
if (~oclkdelay_calib_done) begin
for(y = 0 ; y < DQS_WIDTH; y = y+1) begin
final_coarse_tap[y] <= #TCQ wl_corse_cnt[0][y];
add_smallest[y] <= #TCQ 'd0;
add_largest[y] <= #TCQ 'd0;
end
end else
if (wl_corse_cnt[0][cnt] == wl_corse_cnt[1][cnt]) begin
// Both ranks have use the same number of coarse delay taps.
// No conversion of coarse tap to fine taps required.
//coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3];
final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt];
add_smallest[cnt] <= #TCQ 'd0;
add_largest[cnt] <= #TCQ 'd0;
end else if (wl_corse_cnt[0][cnt] < wl_corse_cnt[1][cnt]) begin
// Rank 0 uses fewer coarse delay taps than rank1.
// conversion of coarse tap to fine taps required for rank1.
// The final coarse count will the smaller value.
//coarse_tap_inc[3*cnt+:3] <= #TCQ wl_corse_cnt[1][3*cnt+:3] - 1;
final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt] - 1;
if (|wl_corse_cnt[0][cnt])
// Coarse tap 2 or higher being converted to fine taps
// This will be added to 'largest' value in final_val
// computation
add_largest[cnt] <= #TCQ 'd38;
else
// Coarse tap 1 being converted to fine taps
// This will be added to 'largest' value in final_val
// computation
add_largest[cnt] <= #TCQ 'd34;
end else if (wl_corse_cnt[0][cnt] > wl_corse_cnt[1][cnt]) begin
// This may be an unlikely scenario in a real system.
// Rank 0 uses more coarse delay taps than rank1.
// conversion of coarse tap to fine taps required.
//coarse_tap_inc[3*cnt+:3] <= #TCQ 'd0;
final_coarse_tap[cnt] <= #TCQ wl_corse_cnt[1][cnt];
if (|wl_corse_cnt[1][cnt])
// Coarse tap 2 or higher being converted to fine taps
// This will be added to 'smallest' value in final_val
// computation
add_smallest[cnt] <= #TCQ 'd38;
else
// Coarse tap 1 being converted to fine taps
// This will be added to 'smallest' value in
// final_val computation
add_smallest[cnt] <= #TCQ 'd34;
end
end
end
end
end else begin
// Single rank
always @(posedge clk) begin
//coarse_tap_inc <= #TCQ 'd0;
for(w = 0; w < DQS_WIDTH; w = w + 1) begin
final_coarse_tap[w] <= #TCQ wl_corse_cnt[0][w];
add_smallest[w] <= #TCQ 'd0;
add_largest[w] <= #TCQ 'd0;
end
end
end
endgenerate
// Determine delay value for DQS in multirank system
// Assuming delay value is the smallest for rank 0 DQS
// and largest delay value for rank 4 DQS
// Set to smallest + ((largest-smallest)/2)
always @(posedge clk) begin
if (rst) begin
for(x = 0; x < DQS_WIDTH; x = x +1) begin
smallest[x] <= #TCQ 'b0;
largest[x] <= #TCQ 'b0;
end
end else if ((wl_state_r == WL_DQS_CNT) & wrlvl_byte_redo) begin
smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];
largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];
end else if ((wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_2RANK_TAP_DEC)) begin
smallest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[0][dqs_count_r];
largest[dqs_count_r] <= #TCQ wl_dqs_tap_count_r[RANKS-1][dqs_count_r];
end else if (((SIM_CAL_OPTION == "FAST_CAL") |
(~oclkdelay_calib_done & ~wrlvl_byte_redo)) &
wr_level_done_r1 & ~wr_level_done_r2) begin
for(i = 0; i < DQS_WIDTH; i = i +1) begin: smallest_dqs
smallest[i] <= #TCQ wl_dqs_tap_count_r[0][i];
largest[i] <= #TCQ wl_dqs_tap_count_r[0][i];
end
end
end
// final_val to be used for all DQSs in all ranks
genvar wr_i;
generate
for (wr_i = 0; wr_i < DQS_WIDTH; wr_i = wr_i +1) begin: gen_final_tap
always @(posedge clk) begin
if (rst)
final_val[wr_i] <= #TCQ 'b0;
else if (wr_level_done_r2 && ~wr_level_done_r3) begin
if (~oclkdelay_calib_done)
final_val[wr_i] <= #TCQ (smallest[wr_i] + add_smallest[wr_i]);
else if ((smallest[wr_i] + add_smallest[wr_i]) <
(largest[wr_i] + add_largest[wr_i]))
final_val[wr_i] <= #TCQ ((smallest[wr_i] + add_smallest[wr_i]) +
(((largest[wr_i] + add_largest[wr_i]) -
(smallest[wr_i] + add_smallest[wr_i]))/2));
else if ((smallest[wr_i] + add_smallest[wr_i]) >
(largest[wr_i] + add_largest[wr_i]))
final_val[wr_i] <= #TCQ ((largest[wr_i] + add_largest[wr_i]) +
(((smallest[wr_i] + add_smallest[wr_i]) -
(largest[wr_i] + add_largest[wr_i]))/2));
else if ((smallest[wr_i] + add_smallest[wr_i]) ==
(largest[wr_i] + add_largest[wr_i]))
final_val[wr_i] <= #TCQ (largest[wr_i] + add_largest[wr_i]);
end
end
end
endgenerate
// // fine tap inc/dec value for all DQSs in all ranks
// genvar dqs_i;
// generate
// for (dqs_i = 0; dqs_i < DQS_WIDTH; dqs_i = dqs_i +1) begin: gen_fine_tap
// always @(posedge clk) begin
// if (rst)
// fine_tap_inc[6*dqs_i+:6] <= #TCQ 'd0;
// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;
// else if (wr_level_done_r3 && ~wr_level_done_r4) begin
// fine_tap_inc[6*dqs_i+:6] <= #TCQ final_val[6*dqs_i+:6];
// //fine_tap_dec[6*dqs_i+:6] <= #TCQ 'd0;
// end
// end
// endgenerate
// Inc/Dec Phaser_Out stage 2 fine delay line
always @(posedge clk) begin
if (rst) begin
// Fine delay line used only during write leveling
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b0;
// Dec Phaser_Out fine delay (1)before write leveling,
// (2)if no 0 to 1 transition detected with 63 fine delay taps, or
// (3)dual rank case where fine taps for the first rank need to be 0
end else if (po_cnt_dec || (wl_state_r == WL_INIT_FINE_DEC) ||
(wl_state_r == WL_FINE_DEC)) begin
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b1;
// Inc Phaser_Out fine delay during write leveling
end else if ((wl_state_r == WL_INIT_FINE_INC) ||
(wl_state_r == WL_FINE_INC)) begin
dqs_po_stg2_f_incdec <= #TCQ 1'b1;
dqs_po_en_stg2_f <= #TCQ 1'b1;
end else begin
dqs_po_stg2_f_incdec <= #TCQ 1'b0;
dqs_po_en_stg2_f <= #TCQ 1'b0;
end
end
// Inc Phaser_Out stage 2 Coarse delay line
always @(posedge clk) begin
if (rst) begin
// Coarse delay line used during write leveling
// only if no 0->1 transition undetected with 64
// fine delay line taps
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;
dqs_wl_po_en_stg2_c <= #TCQ 1'b0;
end else if (wl_state_r == WL_CORSE_INC) begin
// Inc Phaser_Out coarse delay during write leveling
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b1;
dqs_wl_po_en_stg2_c <= #TCQ 1'b1;
end else begin
dqs_wl_po_stg2_c_incdec <= #TCQ 1'b0;
dqs_wl_po_en_stg2_c <= #TCQ 1'b0;
end
end
// only storing the rise data for checking. The data comming back during
// write leveling will be a static value. Just checking for rise data is
// enough.
genvar rd_i;
generate
for(rd_i = 0; rd_i < DQS_WIDTH; rd_i = rd_i +1)begin: gen_rd
always @(posedge clk)
rd_data_rise_wl_r[rd_i] <=
#TCQ |rd_data_rise0[(rd_i*DRAM_WIDTH)+DRAM_WIDTH-1:rd_i*DRAM_WIDTH];
end
endgenerate
// storing the previous data for checking later.
always @(posedge clk)begin
if ((wl_state_r == WL_INIT) || //(wl_state_r == WL_INIT_FINE_INC_WAIT) ||
//(wl_state_r == WL_INIT_FINE_INC_WAIT1) ||
((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)) ||
(wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT1) || (wl_state_r == WL_FINE_DEC_WAIT) ||
(wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) ||
(wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2) ||
((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)))
rd_data_previous_r <= #TCQ rd_data_rise_wl_r;
end
// changed stable count from 3 to 7 because of fine tap resolution
always @(posedge clk)begin
if (rst | (wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_2RANK_TAP_DEC) |
(wl_state_r == WL_FINE_DEC) |
(rd_data_previous_r[dqs_count_r] != rd_data_rise_wl_r[dqs_count_r]) |
(wl_state_r1 == WL_INIT_FINE_DEC))
stable_cnt <= #TCQ 'd0;
else if ((wl_tap_count_r > 6'd0) &
(((wl_state_r == WL_EDGE_CHECK) & (wl_edge_detect_valid_r)) |
((wl_state_r1 == WL_INIT_FINE_INC_WAIT) & (wl_state_r == WL_INIT_FINE_INC)))) begin
if ((rd_data_previous_r[dqs_count_r] == rd_data_rise_wl_r[dqs_count_r])
& (stable_cnt < 'd14))
stable_cnt <= #TCQ stable_cnt + 1;
end
end
// Signal to ensure that flag_ck_negedge does not incorrectly assert
// when DQS is very close to CK rising edge
//always @(posedge clk) begin
// if (rst | (wl_state_r == WL_DQS_CNT) |
// (wl_state_r == WL_DQS_CHECK) | wr_level_done_r)
// past_negedge <= #TCQ 1'b0;
// else if (~flag_ck_negedge && ~rd_data_previous_r[dqs_count_r] &&
// (stable_cnt == 'd0) && ((wl_state_r == WL_CORSE_INC_WAIT1) |
// (wl_state_r == WL_CORSE_INC_WAIT2)))
// past_negedge <= #TCQ 1'b1;
//end
// Flag to indicate negedge of CK detected and ignore 0->1 transitions
// in this region
always @(posedge clk)begin
if (rst | (wl_state_r == WL_DQS_CNT) |
(wl_state_r == WL_DQS_CHECK) | wr_level_done_r |
(wl_state_r1 == WL_INIT_FINE_DEC))
flag_ck_negedge <= #TCQ 1'd0;
else if ((rd_data_previous_r[dqs_count_r] && ((stable_cnt > 'd0) |
(wl_state_r == WL_FINE_DEC) | (wl_state_r == WL_FINE_DEC_WAIT) | (wl_state_r == WL_FINE_DEC_WAIT1))) |
(wl_state_r == WL_CORSE_INC))
flag_ck_negedge <= #TCQ 1'd1;
else if (~rd_data_previous_r[dqs_count_r] && (stable_cnt == 'd14))
//&& flag_ck_negedge)
flag_ck_negedge <= #TCQ 1'd0;
end
// Flag to inhibit rd_data_edge_detect_r before stable DQ
always @(posedge clk) begin
if (rst)
flag_init <= #TCQ 1'b1;
else if ((wl_state_r == WL_WAIT) && ((wl_state_r1 == WL_INIT_FINE_INC_WAIT) ||
(wl_state_r1 == WL_INIT_FINE_DEC_WAIT)))
flag_init <= #TCQ 1'b0;
end
//checking for transition from 0 to 1
always @(posedge clk)begin
if (rst | flag_ck_negedge | flag_init | (wl_tap_count_r < 'd1) |
inhibit_edge_detect_r)
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else if (rd_data_edge_detect_r[dqs_count_r] == 1'b1) begin
if ((wl_state_r == WL_FINE_DEC) || (wl_state_r == WL_FINE_DEC_WAIT) || (wl_state_r == WL_FINE_DEC_WAIT1) ||
(wl_state_r == WL_CORSE_INC) || (wl_state_r == WL_CORSE_INC_WAIT) || (wl_state_r == WL_CORSE_INC_WAIT_TMP) ||
(wl_state_r == WL_CORSE_INC_WAIT1) || (wl_state_r == WL_CORSE_INC_WAIT2))
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else
rd_data_edge_detect_r <= #TCQ rd_data_edge_detect_r;
end else if (rd_data_previous_r[dqs_count_r] && (stable_cnt < 'd14))
rd_data_edge_detect_r <= #TCQ {DQS_WIDTH{1'b0}};
else
rd_data_edge_detect_r <= #TCQ (~rd_data_previous_r & rd_data_rise_wl_r);
end
// registring the write level start signal
always@(posedge clk) begin
wr_level_start_r <= #TCQ wr_level_start;
end
// Assign dqs_count_r to dqs_count_w to perform the shift operation
// instead of multiply operation
assign dqs_count_w = {2'b00, dqs_count_r};
assign oclk_count_w = {2'b00, oclkdelay_calib_cnt};
always @(posedge clk) begin
if (rst)
incdec_wait_cnt <= #TCQ 'd0;
else if ((wl_state_r == WL_FINE_DEC_WAIT1) ||
(wl_state_r == WL_INIT_FINE_DEC_WAIT1) ||
(wl_state_r == WL_CORSE_INC_WAIT_TMP))
incdec_wait_cnt <= #TCQ incdec_wait_cnt + 1;
else
incdec_wait_cnt <= #TCQ 'd0;
end
// state machine to initiate the write leveling sequence
// The state machine operates on one byte at a time.
// It will increment the delays to the DQS OSERDES
// and sample the DQ from the memory. When it detects
// a transition from 1 to 0 then the write leveling is considered
// done.
always @(posedge clk) begin
if(rst)begin
wrlvl_err <= #TCQ 1'b0;
wr_level_done_r <= #TCQ 1'b0;
wrlvl_rank_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ {DQS_CNT_WIDTH+1{1'b0}};
dq_cnt_inc <= #TCQ 1'b1;
rank_cnt_r <= #TCQ 2'b00;
wl_state_r <= #TCQ WL_IDLE;
wl_state_r1 <= #TCQ WL_IDLE;
inhibit_edge_detect_r <= #TCQ 1'b1;
wl_edge_detect_valid_r <= #TCQ 1'b0;
wl_tap_count_r <= #TCQ 6'd0;
fine_dec_cnt <= #TCQ 6'd0;
for (r = 0; r < DQS_WIDTH; r = r + 1) begin
fine_inc[r] <= #TCQ 6'b0;
corse_dec[r] <= #TCQ 3'b0;
corse_inc[r] <= #TCQ 3'b0;
corse_cnt[r] <= #TCQ 3'b0;
end
dual_rnk_dec <= #TCQ 1'b0;
fast_cal_fine_cnt <= #TCQ FAST_CAL_FINE;
fast_cal_coarse_cnt <= #TCQ FAST_CAL_COARSE;
final_corse_dec <= #TCQ 1'b0;
//zero_tran_r <= #TCQ 1'b0;
wrlvl_redo_corse_inc <= #TCQ 'd0;
end else begin
wl_state_r1 <= #TCQ wl_state_r;
case (wl_state_r)
WL_IDLE: begin
wrlvl_rank_done_r <= #TCQ 1'd0;
inhibit_edge_detect_r <= #TCQ 1'b1;
if (wrlvl_byte_redo && ~wrlvl_byte_redo_r) begin
wr_level_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ wrcal_cnt;
corse_cnt[wrcal_cnt] <= #TCQ final_coarse_tap[wrcal_cnt];
wl_tap_count_r <= #TCQ smallest[wrcal_cnt];
if (early1_data &&
(((final_coarse_tap[wrcal_cnt] < 'd6) && (CLK_PERIOD/nCK_PER_CLK <= 2500)) ||
((final_coarse_tap[wrcal_cnt] < 'd3) && (CLK_PERIOD/nCK_PER_CLK > 2500))))
wrlvl_redo_corse_inc <= #TCQ REDO_COARSE;
else if (early2_data && (final_coarse_tap[wrcal_cnt] < 'd2))
wrlvl_redo_corse_inc <= #TCQ 3'd6;
else begin
wl_state_r <= #TCQ WL_IDLE;
wrlvl_err <= #TCQ 1'b1;
end
end else if (wrlvl_final && ~wrlvl_final_r) begin
wr_level_done_r <= #TCQ 1'b0;
dqs_count_r <= #TCQ 'd0;
end
// verilint STARC-2.2.3.3 off
if(!wr_level_done_r & wr_level_start_r & wl_sm_start) begin
if (SIM_CAL_OPTION == "FAST_CAL")
wl_state_r <= #TCQ WL_FINE_INC;
else
wl_state_r <= #TCQ WL_INIT;
end
end
// verilint STARC-2.2.3.3 on
WL_INIT: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
inhibit_edge_detect_r <= #TCQ 1'b1;
wrlvl_rank_done_r <= #TCQ 1'd0;
//zero_tran_r <= #TCQ 1'b0;
if (wrlvl_final)
corse_cnt[dqs_count_w ] <= #TCQ final_coarse_tap[dqs_count_w ];
if (wrlvl_byte_redo) begin
if (|wl_tap_count_r) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7)
wl_state_r <= #TCQ WL_CORSE_INC;
else begin
wl_state_r <= #TCQ WL_IDLE;
wrlvl_err <= #TCQ 1'b1;
end
end else if(wl_sm_start)
wl_state_r <= #TCQ WL_INIT_FINE_INC;
end
// Initially Phaser_Out fine delay taps incremented
// until stable_cnt=14. A stable_cnt of 14 indicates
// that rd_data_rise_wl_r=rd_data_previous_r for 14 fine
// tap increments. This is done to inhibit false 0->1
// edge detection when DQS is initially aligned to the
// negedge of CK
WL_INIT_FINE_INC: begin
wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT1;
wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1;
final_corse_dec <= #TCQ 1'b0;
end
WL_INIT_FINE_INC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_INIT_FINE_INC_WAIT;
end
// Case1: stable value of rd_data_previous_r=0 then
// proceed to 0->1 edge detection.
// Case2: stable value of rd_data_previous_r=1 then
// decrement fine taps to '0' and proceed to 0->1
// edge detection. Need to decrement in this case to
// make sure a valid 0->1 transition was not left
// undetected.
WL_INIT_FINE_INC_WAIT: begin
if (wl_sm_start) begin
if (stable_cnt < 'd14)
wl_state_r <= #TCQ WL_INIT_FINE_INC;
else if (~rd_data_previous_r[dqs_count_r]) begin
wl_state_r <= #TCQ WL_WAIT;
inhibit_edge_detect_r <= #TCQ 1'b0;
end else begin
wl_state_r <= #TCQ WL_INIT_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end
end
end
// Case2: stable value of rd_data_previous_r=1 then
// decrement fine taps to '0' and proceed to 0->1
// edge detection. Need to decrement in this case to
// make sure a valid 0->1 transition was not left
// undetected.
WL_INIT_FINE_DEC: begin
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT1;
if (fine_dec_cnt > 6'd0)
fine_dec_cnt <= #TCQ fine_dec_cnt - 1;
else
fine_dec_cnt <= #TCQ fine_dec_cnt;
end
WL_INIT_FINE_DEC_WAIT1: begin
if (incdec_wait_cnt == 'd8)
wl_state_r <= #TCQ WL_INIT_FINE_DEC_WAIT;
end
WL_INIT_FINE_DEC_WAIT: begin
if (fine_dec_cnt > 6'd0) begin
wl_state_r <= #TCQ WL_INIT_FINE_DEC;
inhibit_edge_detect_r <= #TCQ 1'b1;
end else begin
wl_state_r <= #TCQ WL_WAIT;
inhibit_edge_detect_r <= #TCQ 1'b0;
end
end
// Inc DQS Phaser_Out Stage2 Fine Delay line
WL_FINE_INC: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
if (SIM_CAL_OPTION == "FAST_CAL") begin
wl_state_r <= #TCQ WL_FINE_INC_WAIT;
if (fast_cal_fine_cnt > 'd0)
fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt - 1;
else
fast_cal_fine_cnt <= #TCQ fast_cal_fine_cnt;
end else if (wr_level_done_r5) begin
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_FINE_INC_WAIT;
if (|fine_inc[dqs_count_w])
fine_inc[dqs_count_w] <= #TCQ fine_inc[dqs_count_w] - 1;
end else begin
wl_state_r <= #TCQ WL_WAIT;
wl_tap_count_r <= #TCQ wl_tap_count_r + 1'b1;
end
end
WL_FINE_INC_WAIT: begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
if (fast_cal_fine_cnt > 'd0)
wl_state_r <= #TCQ WL_FINE_INC;
else if (fast_cal_coarse_cnt > 'd0)
wl_state_r <= #TCQ WL_CORSE_INC;
else
wl_state_r <= #TCQ WL_DQS_CNT;
end else if (|fine_inc[dqs_count_w])
wl_state_r <= #TCQ WL_FINE_INC;
else if (dqs_count_r == (DQS_WIDTH-1))
wl_state_r <= #TCQ WL_IDLE;
else begin
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
dqs_count_r <= #TCQ dqs_count_r + 1;
end
end
WL_FINE_DEC: begin
wl_edge_detect_valid_r <= #TCQ 1'b0;
wl_tap_count_r <= #TCQ 'd0;
wl_state_r <= #TCQ WL_FINE_DEC_WAIT1;
if (fine_dec_cnt > 6'd0)
fine_dec_cnt <= #TCQ fine_dec_cnt - 1;
else
fine_dec_cnt <= #TCQ fine_dec_cnt;
end
WL_FINE_DEC_WAIT1: begin
if (incdec_wait_cnt == 'd8)
wl_state_r <= #TCQ WL_FINE_DEC_WAIT;
end
WL_FINE_DEC_WAIT: begin
if (fine_dec_cnt > 6'd0)
wl_state_r <= #TCQ WL_FINE_DEC;
//else if (zero_tran_r)
// wl_state_r <= #TCQ WL_DQS_CNT;
else if (dual_rnk_dec) begin
if (|corse_dec[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_DEC;
else
wl_state_r <= #TCQ WL_2RANK_DQS_CNT;
end else if (wrlvl_byte_redo) begin
if ((corse_cnt[dqs_count_w] + wrlvl_redo_corse_inc) <= 'd7)
wl_state_r <= #TCQ WL_CORSE_INC;
else begin
wl_state_r <= #TCQ WL_IDLE;
wrlvl_err <= #TCQ 1'b1;
end
end else
wl_state_r <= #TCQ WL_CORSE_INC;
end
WL_CORSE_DEC: begin
wl_state_r <= #TCQ WL_CORSE_DEC_WAIT;
dual_rnk_dec <= #TCQ 1'b0;
if (|corse_dec[dqs_count_r])
corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r] - 1;
else
corse_dec[dqs_count_r] <= #TCQ corse_dec[dqs_count_r];
end
WL_CORSE_DEC_WAIT: begin
if (wl_sm_start) begin
//if (|corse_dec[dqs_count_r])
// wl_state_r <= #TCQ WL_CORSE_DEC;
if (|corse_dec[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_DEC_WAIT1;
else
wl_state_r <= #TCQ WL_2RANK_DQS_CNT;
end
end
WL_CORSE_DEC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_DEC;
end
WL_CORSE_INC: begin
wl_state_r <= #TCQ WL_CORSE_INC_WAIT_TMP;
if (SIM_CAL_OPTION == "FAST_CAL") begin
if (fast_cal_coarse_cnt > 'd0)
fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt - 1;
else
fast_cal_coarse_cnt <= #TCQ fast_cal_coarse_cnt;
end else if (wrlvl_byte_redo) begin
corse_cnt[dqs_count_w] <= #TCQ corse_cnt[dqs_count_w] + 1;
if (|wrlvl_redo_corse_inc)
wrlvl_redo_corse_inc <= #TCQ wrlvl_redo_corse_inc - 1;
end else if (~wr_level_done_r5)
corse_cnt[dqs_count_r] <= #TCQ corse_cnt[dqs_count_r] + 1;
else if (|corse_inc[dqs_count_w])
corse_inc[dqs_count_w] <= #TCQ corse_inc[dqs_count_w] - 1;
end
WL_CORSE_INC_WAIT_TMP: begin
if (incdec_wait_cnt == 'd8)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT;
end
WL_CORSE_INC_WAIT: begin
if (SIM_CAL_OPTION == "FAST_CAL") begin
if (fast_cal_coarse_cnt > 'd0)
wl_state_r <= #TCQ WL_CORSE_INC;
else
wl_state_r <= #TCQ WL_DQS_CNT;
end else if (wrlvl_byte_redo) begin
if (|wrlvl_redo_corse_inc)
wl_state_r <= #TCQ WL_CORSE_INC;
else begin
wl_state_r <= #TCQ WL_INIT_FINE_INC;
inhibit_edge_detect_r <= #TCQ 1'b1;
end
end else if (~wr_level_done_r5 && wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT1;
else if (wr_level_done_r5) begin
if (|corse_inc[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_INC;
else if (|fine_inc[dqs_count_w])
wl_state_r <= #TCQ WL_FINE_INC;
else if (dqs_count_r == (DQS_WIDTH-1))
wl_state_r <= #TCQ WL_IDLE;
else begin
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
dqs_count_r <= #TCQ dqs_count_r + 1;
end
end
end
WL_CORSE_INC_WAIT1: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_CORSE_INC_WAIT2;
end
WL_CORSE_INC_WAIT2: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_WAIT;
end
WL_WAIT: begin
if (wl_sm_start)
wl_state_r <= #TCQ WL_EDGE_CHECK;
end
WL_EDGE_CHECK: begin // Look for the edge
if (wl_edge_detect_valid_r == 1'b0) begin
wl_state_r <= #TCQ WL_WAIT;
wl_edge_detect_valid_r <= #TCQ 1'b1;
end
// 0->1 transition detected with DQS
else if(rd_data_edge_detect_r[dqs_count_r] &&
wl_edge_detect_valid_r)
begin
wl_tap_count_r <= #TCQ wl_tap_count_r;
if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) ||
~oclkdelay_calib_done)
wl_state_r <= #TCQ WL_DQS_CNT;
else
wl_state_r <= #TCQ WL_2RANK_TAP_DEC;
end
// For initial writes check only upto 56 taps. Reserving the
// remaining taps for OCLK calibration.
else if((~wrlvl_tap_done_r) && (wl_tap_count_r > 6'd55)) begin
if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else begin
wrlvl_err <= #TCQ 1'b1;
wl_state_r <= #TCQ WL_IDLE;
end
end else begin
if (wl_tap_count_r < 6'd56) //for reuse wrlvl for complex ocal
wl_state_r <= #TCQ WL_FINE_INC;
else if (corse_cnt[dqs_count_r] < COARSE_TAPS) begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
end else begin
wrlvl_err <= #TCQ 1'b1;
wl_state_r <= #TCQ WL_IDLE;
end
end
end
WL_2RANK_TAP_DEC: begin
wl_state_r <= #TCQ WL_FINE_DEC;
fine_dec_cnt <= #TCQ wl_tap_count_r;
for (m = 0; m < DQS_WIDTH; m = m + 1)
corse_dec[m] <= #TCQ corse_cnt[m];
wl_edge_detect_valid_r <= #TCQ 1'b0;
dual_rnk_dec <= #TCQ 1'b1;
end
WL_DQS_CNT: begin
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(dqs_count_r == (DQS_WIDTH-1)) ||
wrlvl_byte_redo) begin
dqs_count_r <= #TCQ dqs_count_r;
dq_cnt_inc <= #TCQ 1'b0;
end else begin
dqs_count_r <= #TCQ dqs_count_r + 1'b1;
dq_cnt_inc <= #TCQ 1'b1;
end
wl_state_r <= #TCQ WL_DQS_CHECK;
wl_edge_detect_valid_r <= #TCQ 1'b0;
end
WL_2RANK_DQS_CNT: begin
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(dqs_count_r == (DQS_WIDTH-1))) begin
dqs_count_r <= #TCQ dqs_count_r;
dq_cnt_inc <= #TCQ 1'b0;
end else begin
dqs_count_r <= #TCQ dqs_count_r + 1'b1;
dq_cnt_inc <= #TCQ 1'b1;
end
wl_state_r <= #TCQ WL_DQS_CHECK;
wl_edge_detect_valid_r <= #TCQ 1'b0;
dual_rnk_dec <= #TCQ 1'b0;
end
WL_DQS_CHECK: begin // check if all DQS have been calibrated
wl_tap_count_r <= #TCQ 'd0;
if (dq_cnt_inc == 1'b0)begin
wrlvl_rank_done_r <= #TCQ 1'd1;
for (t = 0; t < DQS_WIDTH; t = t + 1)
corse_cnt[t] <= #TCQ 3'b0;
if ((SIM_CAL_OPTION == "FAST_CAL") || (RANKS < 2) || ~oclkdelay_calib_done) begin
wl_state_r <= #TCQ WL_IDLE;
if (wrlvl_byte_redo)
dqs_count_r <= #TCQ dqs_count_r;
else
dqs_count_r <= #TCQ 'd0;
end else if (rank_cnt_r == RANKS-1) begin
dqs_count_r <= #TCQ dqs_count_r;
if (RANKS > 1)
wl_state_r <= #TCQ WL_2RANK_FINAL_TAP;
else
wl_state_r <= #TCQ WL_IDLE;
end else begin
wl_state_r <= #TCQ WL_INIT;
dqs_count_r <= #TCQ 'd0;
end
if ((SIM_CAL_OPTION == "FAST_CAL") ||
(rank_cnt_r == RANKS-1)) begin
wr_level_done_r <= #TCQ 1'd1;
rank_cnt_r <= #TCQ 2'b00;
end else begin
wr_level_done_r <= #TCQ 1'd0;
rank_cnt_r <= #TCQ rank_cnt_r + 1'b1;
end
end else
wl_state_r <= #TCQ WL_INIT;
end
WL_2RANK_FINAL_TAP: begin
if (wr_level_done_r4 && ~wr_level_done_r5) begin
for(u = 0; u < DQS_WIDTH; u = u + 1) begin
corse_inc[u] <= #TCQ final_coarse_tap[u];
fine_inc[u] <= #TCQ final_val[u];
end
dqs_count_r <= #TCQ 'd0;
end else if (wr_level_done_r5) begin
if (|corse_inc[dqs_count_r])
wl_state_r <= #TCQ WL_CORSE_INC;
else if (|fine_inc[dqs_count_w])
wl_state_r <= #TCQ WL_FINE_INC;
end
end
endcase
end
end // always @ (posedge clk)
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/14.0/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2014/02/16 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200 Top Level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// OR1200 Top Level ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_top.v,v $
// Revision 1.13 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.12 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.10.4.9 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
// Revision 1.10.4.8 2004/01/17 21:14:14 simons
// Errors fixed.
//
// Revision 1.10.4.7 2004/01/17 19:06:38 simons
// Error fixed.
//
// Revision 1.10.4.6 2004/01/17 18:39:48 simons
// Error fixed.
//
// Revision 1.10.4.5 2004/01/15 06:46:38 markom
// interface to debug changed; no more opselect; stb-ack protocol
//
// Revision 1.10.4.4 2003/12/09 11:46:49 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.10.4.3 2003/12/05 00:08:44 lampret
// Fixed instantiation name.
//
// Revision 1.10.4.2 2003/07/11 01:10:35 lampret
// Added three missing wire declarations. No functional changes.
//
// Revision 1.10.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.10 2002/12/08 08:57:56 lampret
// Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.
//
// Revision 1.9 2002/10/17 20:04:41 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.8 2002/08/18 19:54:22 lampret
// Added store buffer.
//
// Revision 1.7 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.6 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/02/01 19:56:55 lampret
// Fixed combinational loops.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.13 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.12 2001/11/20 00:57:22 lampret
// Fixed width of du_except.
//
// Revision 1.11 2001/11/18 08:36:28 lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.4 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.3 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:54 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_top(
// System
clk_i, rst_i, pic_ints_i, clmode_i,
//SPOOFER
`ifdef SPOOFER
clk_count,
spoof_out,
trigger,
`endif
// Instruction WISHBONE INTERFACE
iwb_clk_i, iwb_rst_i, iwb_ack_i, iwb_err_i, iwb_rty_i, iwb_dat_i,
iwb_cyc_o, iwb_adr_o, iwb_stb_o, iwb_we_o, iwb_sel_o, iwb_dat_o,
`ifdef OR1200_WB_CAB
iwb_cab_o,
`endif
`ifdef OR1200_WB_B3
iwb_cti_o, iwb_bte_o,
`endif
// Data WISHBONE INTERFACE
dwb_clk_i, dwb_rst_i, dwb_ack_i, dwb_err_i, dwb_rty_i, dwb_dat_i,
dwb_cyc_o, dwb_adr_o, dwb_stb_o, dwb_we_o, dwb_sel_o, dwb_dat_o,
`ifdef OR1200_WB_CAB
dwb_cab_o,
`endif
`ifdef OR1200_WB_B3
dwb_cti_o, dwb_bte_o,
`endif
// External Debug Interface
dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Power Management
pm_cpustall_i,
pm_clksd_o, pm_dc_gate_o, pm_ic_gate_o, pm_dmmu_gate_o,
pm_immu_gate_o, pm_tt_gate_o, pm_cpu_gate_o, pm_wakeup_o, pm_lvolt_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
parameter ppic_ints = `OR1200_PIC_INTS;
//
// I/O
//
//
// System
//
input clk_i;
input rst_i;
input [1:0] clmode_i; // 00 WB=RISC, 01 WB=RISC/2, 10 N/A, 11 WB=RISC/4
input [ppic_ints-1:0] pic_ints_i;
//
//SPOOFER INTERFACE
`ifdef SPOOFER
input [31:0] clk_count;
output [31:0] spoof_out;
output trigger;
`endif
// Instruction WISHBONE interface
//
input iwb_clk_i; // clock input
input iwb_rst_i; // reset input
input iwb_ack_i; // normal termination
input iwb_err_i; // termination w/ error
input iwb_rty_i; // termination w/ retry
input [dw-1:0] iwb_dat_i; // input data bus
output iwb_cyc_o; // cycle valid output
output [aw-1:0] iwb_adr_o; // address bus outputs
output iwb_stb_o; // strobe output
output iwb_we_o; // indicates write transfer
output [3:0] iwb_sel_o; // byte select outputs
output [dw-1:0] iwb_dat_o; // output data bus
`ifdef OR1200_WB_CAB
output iwb_cab_o; // indicates consecutive address burst
`endif
`ifdef OR1200_WB_B3
output [2:0] iwb_cti_o; // cycle type identifier
output [1:0] iwb_bte_o; // burst type extension
`endif
//
// Data WISHBONE interface
//
input dwb_clk_i; // clock input
input dwb_rst_i; // reset input
input dwb_ack_i; // normal termination
input dwb_err_i; // termination w/ error
input dwb_rty_i; // termination w/ retry
input [dw-1:0] dwb_dat_i; // input data bus
output dwb_cyc_o; // cycle valid output
output [aw-1:0] dwb_adr_o; // address bus outputs
output dwb_stb_o; // strobe output
output dwb_we_o; // indicates write transfer
output [3:0] dwb_sel_o; // byte select outputs
output [dw-1:0] dwb_dat_o; // output data bus
`ifdef OR1200_WB_CAB
output dwb_cab_o; // indicates consecutive address burst
`endif
`ifdef OR1200_WB_B3
output [2:0] dwb_cti_o; // cycle type identifier
output [1:0] dwb_bte_o; // burst type extension
`endif
//
// External Debug Interface
//
input dbg_stall_i; // External Stall Input
input dbg_ewt_i; // External Watchpoint Trigger Input
output [3:0] dbg_lss_o; // External Load/Store Unit Status
output [1:0] dbg_is_o; // External Insn Fetch Status
output [10:0] dbg_wp_o; // Watchpoints Outputs
output dbg_bp_o; // Breakpoint Output
input dbg_stb_i; // External Address/Data Strobe
input dbg_we_i; // External Write Enable
input [aw-1:0] dbg_adr_i; // External Address Input
input [dw-1:0] dbg_dat_i; // External Data Input
output [dw-1:0] dbg_dat_o; // External Data Output
output dbg_ack_o; // External Data Acknowledge (not WB compatible)
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Power Management
//
input pm_cpustall_i;
output [3:0] pm_clksd_o;
output pm_dc_gate_o;
output pm_ic_gate_o;
output pm_dmmu_gate_o;
output pm_immu_gate_o;
output pm_tt_gate_o;
output pm_cpu_gate_o;
output pm_wakeup_o;
output pm_lvolt_o;
//
// Internal wires and regs
//
//
// DC to SB
//
wire [dw-1:0] dcsb_dat_dc;
wire [aw-1:0] dcsb_adr_dc;
wire dcsb_cyc_dc;
wire dcsb_stb_dc;
wire dcsb_we_dc;
wire [3:0] dcsb_sel_dc;
wire dcsb_cab_dc;
wire [dw-1:0] dcsb_dat_sb;
wire dcsb_ack_sb;
wire dcsb_err_sb;
//
// SB to BIU
//
wire [dw-1:0] sbbiu_dat_sb;
wire [aw-1:0] sbbiu_adr_sb;
wire sbbiu_cyc_sb;
wire sbbiu_stb_sb;
wire sbbiu_we_sb;
wire [3:0] sbbiu_sel_sb;
wire sbbiu_cab_sb;
wire [dw-1:0] sbbiu_dat_biu;
wire sbbiu_ack_biu;
wire sbbiu_err_biu;
//
// IC to BIU
//
wire [dw-1:0] icbiu_dat_ic;
wire [aw-1:0] icbiu_adr_ic;
wire icbiu_cyc_ic;
wire icbiu_stb_ic;
wire icbiu_we_ic;
wire [3:0] icbiu_sel_ic;
wire [3:0] icbiu_tag_ic;
wire icbiu_cab_ic;
wire [dw-1:0] icbiu_dat_biu;
wire icbiu_ack_biu;
wire icbiu_err_biu;
wire [3:0] icbiu_tag_biu;
//
// CPU's SPR access to various RISC units (shared wires)
//
wire supv;
wire [aw-1:0] spr_addr;
wire [dw-1:0] spr_dat_cpu;
wire [31:0] spr_cs;
wire spr_we;
//
// DMMU and CPU
//
wire dmmu_en;
wire [31:0] spr_dat_dmmu;
//
// DMMU and QMEM
//
wire qmemdmmu_err_qmem;
wire [3:0] qmemdmmu_tag_qmem;
wire [aw-1:0] qmemdmmu_adr_dmmu;
wire qmemdmmu_cycstb_dmmu;
wire qmemdmmu_ci_dmmu;
//
// CPU and data memory subsystem
//
wire dc_en;
wire [31:0] dcpu_adr_cpu;
wire dcpu_cycstb_cpu;
wire dcpu_we_cpu;
wire [3:0] dcpu_sel_cpu;
wire [3:0] dcpu_tag_cpu;
wire [31:0] dcpu_dat_cpu;
wire [31:0] dcpu_dat_qmem;
wire dcpu_ack_qmem;
wire dcpu_rty_qmem;
wire dcpu_err_dmmu;
wire [3:0] dcpu_tag_dmmu;
//
// IMMU and CPU
//
wire immu_en;
wire [31:0] spr_dat_immu;
//
// CPU and insn memory subsystem
//
wire ic_en;
wire [31:0] icpu_adr_cpu;
wire icpu_cycstb_cpu;
wire [3:0] icpu_sel_cpu;
wire [3:0] icpu_tag_cpu;
wire [31:0] icpu_dat_qmem;
wire icpu_ack_qmem;
wire [31:0] icpu_adr_immu;
wire icpu_err_immu;
wire [3:0] icpu_tag_immu;
wire icpu_rty_immu;
//
// IMMU and QMEM
//
wire [aw-1:0] qmemimmu_adr_immu;
wire qmemimmu_rty_qmem;
wire qmemimmu_err_qmem;
wire [3:0] qmemimmu_tag_qmem;
wire qmemimmu_cycstb_immu;
wire qmemimmu_ci_immu;
//
// QMEM and IC
//
wire [aw-1:0] icqmem_adr_qmem;
wire icqmem_rty_ic;
wire icqmem_err_ic;
wire [3:0] icqmem_tag_ic;
wire icqmem_cycstb_qmem;
wire icqmem_ci_qmem;
wire [31:0] icqmem_dat_ic;
wire icqmem_ack_ic;
//
// QMEM and DC
//
wire [aw-1:0] dcqmem_adr_qmem;
wire dcqmem_rty_dc;
wire dcqmem_err_dc;
wire [3:0] dcqmem_tag_dc;
wire dcqmem_cycstb_qmem;
wire dcqmem_ci_qmem;
wire [31:0] dcqmem_dat_dc;
wire [31:0] dcqmem_dat_qmem;
wire dcqmem_we_qmem;
wire [3:0] dcqmem_sel_qmem;
wire dcqmem_ack_dc;
//
// Connection between CPU and PIC
//
wire [dw-1:0] spr_dat_pic;
wire pic_wakeup;
wire sig_int;
//
// Connection between CPU and PM
//
wire [dw-1:0] spr_dat_pm;
//
// CPU and TT
//
wire [dw-1:0] spr_dat_tt;
wire sig_tick;
//
// Debug port and caches/MMUs
//
wire [dw-1:0] spr_dat_du;
wire du_stall;
wire [dw-1:0] du_addr;
wire [dw-1:0] du_dat_du;
wire du_read;
wire du_write;
wire [12:0] du_except;
wire [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
wire [dw-1:0] du_dat_cpu;
wire du_hwbkpt;
wire ex_freeze;
wire [31:0] ex_insn;
wire [31:0] id_pc;
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
wire [31:0] spr_dat_npc;
wire [31:0] rf_dataw;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire mbist_immu_so;
wire mbist_ic_so;
wire mbist_dmmu_so;
wire mbist_dc_so;
wire mbist_qmem_so;
wire mbist_immu_si = mbist_si_i;
wire mbist_ic_si = mbist_immu_so;
wire mbist_qmem_si = mbist_ic_so;
wire mbist_dmmu_si = mbist_qmem_so;
wire mbist_dc_si = mbist_dmmu_so;
assign mbist_so_o = mbist_dc_so;
`endif
wire [3:0] icqmem_sel_qmem;
wire [3:0] icqmem_tag_qmem;
wire [3:0] dcqmem_tag_qmem;
`ifdef SPOOFER
//spoofer declare
wire [31:0] clk_count;
wire [31:0] spoof_out;
wire trigger;
SSDS_profiler profiler(
.clk(clk_i),
.iwb_clk(iwb_clk_i),
.dwb_clk(dwb_clk_i),
.iwb_cyc(iwb_cyc_o),
.dwb_cyc(dwb_cyc_o),
.iwb_we(iwb_we_o),
.dwb_we(dwb_we_o),
.iwb_err(iwb_err_i),
.dwb_err(dwb_err_i),
.iwb_rst(iwb_rst_i),
.dwb_rst(dwb_rst_i),
.clk_count(clk_count),
.data_out(spoof_out),
.dwb_dat_i(dwb_dat_i),
.iwb_dat_i(iwb_dat_i),
.reset(rst_i)
);
`endif
//
// Instantiation of Instruction WISHBONE BIU
//
or1200_iwb_biu iwb_biu(
// RISC clk, rst and clock control
.clk(clk_i),
.rst(rst_i),
.clmode(clmode_i),
// WISHBONE interface
.wb_clk_i(iwb_clk_i),
.wb_rst_i(iwb_rst_i),
.wb_ack_i(iwb_ack_i),
.wb_err_i(iwb_err_i),
.wb_rty_i(iwb_rty_i),
.wb_dat_i(iwb_dat_i),
.wb_cyc_o(iwb_cyc_o),
.wb_adr_o(iwb_adr_o),
.wb_stb_o(iwb_stb_o),
.wb_we_o(iwb_we_o),
.wb_sel_o(iwb_sel_o),
.wb_dat_o(iwb_dat_o),
`ifdef OR1200_WB_CAB
.wb_cab_o(iwb_cab_o),
`endif
`ifdef OR1200_WB_B3
.wb_cti_o(iwb_cti_o),
.wb_bte_o(iwb_bte_o),
`endif
// Internal RISC bus
.biu_dat_i(icbiu_dat_ic),
.biu_adr_i(icbiu_adr_ic),
.biu_cyc_i(icbiu_cyc_ic),
.biu_stb_i(icbiu_stb_ic),
.biu_we_i(icbiu_we_ic),
.biu_sel_i(icbiu_sel_ic),
.biu_cab_i(icbiu_cab_ic),
.biu_dat_o(icbiu_dat_biu),
.biu_ack_o(icbiu_ack_biu),
.biu_err_o(icbiu_err_biu)
);
//
// Instantiation of Data WISHBONE BIU
//
or1200_wb_biu dwb_biu(
// RISC clk, rst and clock control
.clk(clk_i),
.rst(rst_i),
.clmode(clmode_i),
// WISHBONE interface
.wb_clk_i(dwb_clk_i),
.wb_rst_i(dwb_rst_i),
.wb_ack_i(dwb_ack_i),
.wb_err_i(dwb_err_i),
.wb_rty_i(dwb_rty_i),
.wb_dat_i(dwb_dat_i),
.wb_cyc_o(dwb_cyc_o),
.wb_adr_o(dwb_adr_o),
.wb_stb_o(dwb_stb_o),
.wb_we_o(dwb_we_o),
.wb_sel_o(dwb_sel_o),
.wb_dat_o(dwb_dat_o),
`ifdef OR1200_WB_CAB
.wb_cab_o(dwb_cab_o),
`endif
`ifdef OR1200_WB_B3
.wb_cti_o(dwb_cti_o),
.wb_bte_o(dwb_bte_o),
`endif
// Internal RISC bus
.biu_dat_i(sbbiu_dat_sb),
.biu_adr_i(sbbiu_adr_sb),
.biu_cyc_i(sbbiu_cyc_sb),
.biu_stb_i(sbbiu_stb_sb),
.biu_we_i(sbbiu_we_sb),
.biu_sel_i(sbbiu_sel_sb),
.biu_cab_i(sbbiu_cab_sb),
.biu_dat_o(sbbiu_dat_biu),
.biu_ack_o(sbbiu_ack_biu),
.biu_err_o(sbbiu_err_biu)
);
//
// Instantiation of IMMU
//
or1200_immu_top or1200_immu_top(
// Rst and clk
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_immu_si),
.mbist_so_o(mbist_immu_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// CPU and IMMU
.ic_en(ic_en),
.immu_en(immu_en),
.supv(supv),
.icpu_adr_i(icpu_adr_cpu),
.icpu_cycstb_i(icpu_cycstb_cpu),
.icpu_adr_o(icpu_adr_immu),
.icpu_tag_o(icpu_tag_immu),
.icpu_rty_o(icpu_rty_immu),
.icpu_err_o(icpu_err_immu),
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IMMU]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_immu),
// QMEM and IMMU
.qmemimmu_rty_i(qmemimmu_rty_qmem),
.qmemimmu_err_i(qmemimmu_err_qmem),
.qmemimmu_tag_i(qmemimmu_tag_qmem),
.qmemimmu_adr_o(qmemimmu_adr_immu),
.qmemimmu_cycstb_o(qmemimmu_cycstb_immu),
.qmemimmu_ci_o(qmemimmu_ci_immu)
);
//
// Instantiation of Instruction Cache
//
or1200_ic_top or1200_ic_top(
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_ic_si),
.mbist_so_o(mbist_ic_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// IC and QMEM
.ic_en(ic_en),
.icqmem_adr_i(icqmem_adr_qmem),
.icqmem_cycstb_i(icqmem_cycstb_qmem),
.icqmem_ci_i(icqmem_ci_qmem),
.icqmem_sel_i(icqmem_sel_qmem),
.icqmem_tag_i(icqmem_tag_qmem),
.icqmem_dat_o(icqmem_dat_ic),
.icqmem_ack_o(icqmem_ack_ic),
.icqmem_rty_o(icqmem_rty_ic),
.icqmem_err_o(icqmem_err_ic),
.icqmem_tag_o(icqmem_tag_ic),
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_IC]),
.spr_write(spr_we),
.spr_dat_i(spr_dat_cpu),
// IC and BIU
.icbiu_dat_o(icbiu_dat_ic),
.icbiu_adr_o(icbiu_adr_ic),
.icbiu_cyc_o(icbiu_cyc_ic),
.icbiu_stb_o(icbiu_stb_ic),
.icbiu_we_o(icbiu_we_ic),
.icbiu_sel_o(icbiu_sel_ic),
.icbiu_cab_o(icbiu_cab_ic),
.icbiu_dat_i(icbiu_dat_biu),
.icbiu_ack_i(icbiu_ack_biu),
.icbiu_err_i(icbiu_err_biu)
);
//
// Instantiation of Instruction Cache
//
or1200_cpu or1200_cpu(
.clk(clk_i),
.rst(rst_i),
`ifdef SPOOFER
.trigger(trigger),
`endif
// Connection QMEM and IFETCHER inside CPU
.ic_en(ic_en),
.icpu_adr_o(icpu_adr_cpu),
.icpu_cycstb_o(icpu_cycstb_cpu),
.icpu_sel_o(icpu_sel_cpu),
.icpu_tag_o(icpu_tag_cpu),
.icpu_dat_i(icpu_dat_qmem),
.icpu_ack_i(icpu_ack_qmem),
.icpu_rty_i(icpu_rty_immu),
.icpu_adr_i(icpu_adr_immu),
.icpu_err_i(icpu_err_immu),
.icpu_tag_i(icpu_tag_immu),
// Connection CPU to external Debug port
.ex_freeze(ex_freeze),
.ex_insn(ex_insn),
.id_pc(id_pc),
.branch_op(branch_op),
.du_stall(du_stall),
.du_addr(du_addr),
.du_dat_du(du_dat_du),
.du_read(du_read),
.du_write(du_write),
.du_dsr(du_dsr),
.du_except(du_except),
.du_dat_cpu(du_dat_cpu),
.du_hwbkpt(du_hwbkpt),
.rf_dataw(rf_dataw),
// Connection IMMU and CPU internally
.immu_en(immu_en),
// Connection QMEM and CPU
.dc_en(dc_en),
.dcpu_adr_o(dcpu_adr_cpu),
.dcpu_cycstb_o(dcpu_cycstb_cpu),
.dcpu_we_o(dcpu_we_cpu),
.dcpu_sel_o(dcpu_sel_cpu),
.dcpu_tag_o(dcpu_tag_cpu),
.dcpu_dat_o(dcpu_dat_cpu),
.dcpu_dat_i(dcpu_dat_qmem),
.dcpu_ack_i(dcpu_ack_qmem),
.dcpu_rty_i(dcpu_rty_qmem),
.dcpu_err_i(dcpu_err_dmmu),
.dcpu_tag_i(dcpu_tag_dmmu),
// Connection DMMU and CPU internally
.dmmu_en(dmmu_en),
// Connection PIC and CPU's EXCEPT
.sig_int(sig_int),
.sig_tick(sig_tick),
// SPRs
.supv(supv),
.spr_addr(spr_addr),
.spr_dat_cpu(spr_dat_cpu),
.spr_dat_pic(spr_dat_pic),
.spr_dat_tt(spr_dat_tt),
.spr_dat_pm(spr_dat_pm),
.spr_dat_dmmu(spr_dat_dmmu),
.spr_dat_immu(spr_dat_immu),
.spr_dat_du(spr_dat_du),
.spr_dat_npc(spr_dat_npc),
.spr_cs(spr_cs),
.spr_we(spr_we)
);
//
// Instantiation of DMMU
//
or1200_dmmu_top or1200_dmmu_top(
// Rst and clk
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_dmmu_si),
.mbist_so_o(mbist_dmmu_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// CPU i/f
.dc_en(dc_en),
.dmmu_en(dmmu_en),
.supv(supv),
.dcpu_adr_i(dcpu_adr_cpu),
.dcpu_cycstb_i(dcpu_cycstb_cpu),
.dcpu_we_i(dcpu_we_cpu),
.dcpu_tag_o(dcpu_tag_dmmu),
.dcpu_err_o(dcpu_err_dmmu),
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DMMU]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_dmmu),
// QMEM and DMMU
.qmemdmmu_err_i(qmemdmmu_err_qmem),
.qmemdmmu_tag_i(qmemdmmu_tag_qmem),
.qmemdmmu_adr_o(qmemdmmu_adr_dmmu),
.qmemdmmu_cycstb_o(qmemdmmu_cycstb_dmmu),
.qmemdmmu_ci_o(qmemdmmu_ci_dmmu)
);
//
// Instantiation of Data Cache
//
or1200_dc_top or1200_dc_top(
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_dc_si),
.mbist_so_o(mbist_dc_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// DC and QMEM
.dc_en(dc_en),
.dcqmem_adr_i(dcqmem_adr_qmem),
.dcqmem_cycstb_i(dcqmem_cycstb_qmem),
.dcqmem_ci_i(dcqmem_ci_qmem),
.dcqmem_we_i(dcqmem_we_qmem),
.dcqmem_sel_i(dcqmem_sel_qmem),
.dcqmem_tag_i(dcqmem_tag_qmem),
.dcqmem_dat_i(dcqmem_dat_qmem),
.dcqmem_dat_o(dcqmem_dat_dc),
.dcqmem_ack_o(dcqmem_ack_dc),
.dcqmem_rty_o(dcqmem_rty_dc),
.dcqmem_err_o(dcqmem_err_dc),
.dcqmem_tag_o(dcqmem_tag_dc),
// SPR access
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DC]),
.spr_write(spr_we),
.spr_dat_i(spr_dat_cpu),
// DC and BIU
.dcsb_dat_o(dcsb_dat_dc),
.dcsb_adr_o(dcsb_adr_dc),
.dcsb_cyc_o(dcsb_cyc_dc),
.dcsb_stb_o(dcsb_stb_dc),
.dcsb_we_o(dcsb_we_dc),
.dcsb_sel_o(dcsb_sel_dc),
.dcsb_cab_o(dcsb_cab_dc),
.dcsb_dat_i(dcsb_dat_sb),
.dcsb_ack_i(dcsb_ack_sb),
.dcsb_err_i(dcsb_err_sb)
);
//
// Instantiation of embedded memory - qmem
//
or1200_qmem_top or1200_qmem_top(
.clk(clk_i),
.rst(rst_i),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_qmem_si),
.mbist_so_o(mbist_qmem_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
// QMEM and CPU/IMMU
.qmemimmu_adr_i(qmemimmu_adr_immu),
.qmemimmu_cycstb_i(qmemimmu_cycstb_immu),
.qmemimmu_ci_i(qmemimmu_ci_immu),
.qmemicpu_sel_i(icpu_sel_cpu),
.qmemicpu_tag_i(icpu_tag_cpu),
.qmemicpu_dat_o(icpu_dat_qmem),
.qmemicpu_ack_o(icpu_ack_qmem),
.qmemimmu_rty_o(qmemimmu_rty_qmem),
.qmemimmu_err_o(qmemimmu_err_qmem),
.qmemimmu_tag_o(qmemimmu_tag_qmem),
// QMEM and IC
.icqmem_adr_o(icqmem_adr_qmem),
.icqmem_cycstb_o(icqmem_cycstb_qmem),
.icqmem_ci_o(icqmem_ci_qmem),
.icqmem_sel_o(icqmem_sel_qmem),
.icqmem_tag_o(icqmem_tag_qmem),
.icqmem_dat_i(icqmem_dat_ic),
.icqmem_ack_i(icqmem_ack_ic),
.icqmem_rty_i(icqmem_rty_ic),
.icqmem_err_i(icqmem_err_ic),
.icqmem_tag_i(icqmem_tag_ic),
// QMEM and CPU/DMMU
.qmemdmmu_adr_i(qmemdmmu_adr_dmmu),
.qmemdmmu_cycstb_i(qmemdmmu_cycstb_dmmu),
.qmemdmmu_ci_i(qmemdmmu_ci_dmmu),
.qmemdcpu_we_i(dcpu_we_cpu),
.qmemdcpu_sel_i(dcpu_sel_cpu),
.qmemdcpu_tag_i(dcpu_tag_cpu),
.qmemdcpu_dat_i(dcpu_dat_cpu),
.qmemdcpu_dat_o(dcpu_dat_qmem),
.qmemdcpu_ack_o(dcpu_ack_qmem),
.qmemdcpu_rty_o(dcpu_rty_qmem),
.qmemdmmu_err_o(qmemdmmu_err_qmem),
.qmemdmmu_tag_o(qmemdmmu_tag_qmem),
// QMEM and DC
.dcqmem_adr_o(dcqmem_adr_qmem),
.dcqmem_cycstb_o(dcqmem_cycstb_qmem),
.dcqmem_ci_o(dcqmem_ci_qmem),
.dcqmem_we_o(dcqmem_we_qmem),
.dcqmem_sel_o(dcqmem_sel_qmem),
.dcqmem_tag_o(dcqmem_tag_qmem),
.dcqmem_dat_o(dcqmem_dat_qmem),
.dcqmem_dat_i(dcqmem_dat_dc),
.dcqmem_ack_i(dcqmem_ack_dc),
.dcqmem_rty_i(dcqmem_rty_dc),
.dcqmem_err_i(dcqmem_err_dc),
.dcqmem_tag_i(dcqmem_tag_dc)
);
//
// Instantiation of Store Buffer
//
or1200_sb or1200_sb(
// RISC clock, reset
.clk(clk_i),
.rst(rst_i),
// Internal RISC bus (DC<->SB)
.dcsb_dat_i(dcsb_dat_dc),
.dcsb_adr_i(dcsb_adr_dc),
.dcsb_cyc_i(dcsb_cyc_dc),
.dcsb_stb_i(dcsb_stb_dc),
.dcsb_we_i(dcsb_we_dc),
.dcsb_sel_i(dcsb_sel_dc),
.dcsb_cab_i(dcsb_cab_dc),
.dcsb_dat_o(dcsb_dat_sb),
.dcsb_ack_o(dcsb_ack_sb),
.dcsb_err_o(dcsb_err_sb),
// SB and BIU
.sbbiu_dat_o(sbbiu_dat_sb),
.sbbiu_adr_o(sbbiu_adr_sb),
.sbbiu_cyc_o(sbbiu_cyc_sb),
.sbbiu_stb_o(sbbiu_stb_sb),
.sbbiu_we_o(sbbiu_we_sb),
.sbbiu_sel_o(sbbiu_sel_sb),
.sbbiu_cab_o(sbbiu_cab_sb),
.sbbiu_dat_i(sbbiu_dat_biu),
.sbbiu_ack_i(sbbiu_ack_biu),
.sbbiu_err_i(sbbiu_err_biu)
);
//
// Instantiation of Debug Unit
//
or1200_du or1200_du(
// RISC Internal Interface
.clk(clk_i),
.rst(rst_i),
.dcpu_cycstb_i(dcpu_cycstb_cpu),
.dcpu_we_i(dcpu_we_cpu),
.dcpu_adr_i(dcpu_adr_cpu),
.dcpu_dat_lsu(dcpu_dat_cpu),
.dcpu_dat_dc(dcpu_dat_qmem),
.icpu_cycstb_i(icpu_cycstb_cpu),
.ex_freeze(ex_freeze),
.branch_op(branch_op),
.ex_insn(ex_insn),
.id_pc(id_pc),
.du_dsr(du_dsr),
// For Trace buffer
.spr_dat_npc(spr_dat_npc),
.rf_dataw(rf_dataw),
// DU's access to SPR unit
.du_stall(du_stall),
.du_addr(du_addr),
.du_dat_i(du_dat_cpu),
.du_dat_o(du_dat_du),
.du_read(du_read),
.du_write(du_write),
.du_except(du_except),
.du_hwbkpt(du_hwbkpt),
// Access to DU's SPRs
.spr_cs(spr_cs[`OR1200_SPR_GROUP_DU]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_du),
// External Debug Interface
.dbg_stall_i(dbg_stall_i),
.dbg_ewt_i(dbg_ewt_i),
.dbg_lss_o(dbg_lss_o),
.dbg_is_o(dbg_is_o),
.dbg_wp_o(dbg_wp_o),
.dbg_bp_o(dbg_bp_o),
.dbg_stb_i(dbg_stb_i),
.dbg_we_i(dbg_we_i),
.dbg_adr_i(dbg_adr_i),
.dbg_dat_i(dbg_dat_i),
.dbg_dat_o(dbg_dat_o),
.dbg_ack_o(dbg_ack_o)
);
//
// Programmable interrupt controller
//
or1200_pic or1200_pic(
// RISC Internal Interface
.clk(clk_i),
.rst(rst_i),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_PIC]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_pic),
.pic_wakeup(pic_wakeup),
.intr(sig_int),
// PIC Interface
.pic_int(pic_ints_i)
);
//
// Instantiation of Tick timer
//
/*
or1200_tt or1200_tt(
// RISC Internal Interface
.clk(clk_i),
.rst(rst_i),
.du_stall(du_stall),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_TT]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_tt),
.intr(sig_tick)
);
*/
//
// Instantiation of Power Management
//
/*
or1200_pm or1200_pm(
// RISC Internal Interface
.clk(clk_i),
.rst(rst_i),
.pic_wakeup(pic_wakeup),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_pm),
// Power Management Interface
.pm_cpustall(pm_cpustall_i),
.pm_clksd(pm_clksd_o),
.pm_dc_gate(pm_dc_gate_o),
.pm_ic_gate(pm_ic_gate_o),
.pm_dmmu_gate(pm_dmmu_gate_o),
.pm_immu_gate(pm_immu_gate_o),
.pm_tt_gate(pm_tt_gate_o),
.pm_cpu_gate(pm_cpu_gate_o),
.pm_wakeup(pm_wakeup_o),
.pm_lvolt(pm_lvolt_o)
);
*/
`ifdef SPOOFER
always@(posedge trigger) $display("TRIGGERED");
`endif
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Computer_System_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module Computer_System_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
Computer_System_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
module tester(
clk,
rst
);
parameter end_simulation = 32'hffff;
output clk,rst;
reg clk, rst;
integer clk_count;
integer tests_done;
integer tests_failed;
initial begin
forever begin
#10 clk <= ~clk;
if(clk) clk_count = clk_count + 1;
if(clk_count == end_simulation) begin
$display("not ok - Simulation took too long");
tests_failed = tests_failed+1;
print_report();
$finish;
end
end
end
initial begin
clk = 0;
rst = 0;
clk_count = 0;
tests_done = 0;
tests_failed = 0;
end
task reset_module;
begin
wait_clock();
rst = 1;
wait_clock();
wait_clock();
rst = 0;
end
endtask
task wait_clock;
begin
@( negedge clk );
end
endtask
task check_boolean;
input test_result;
input[0:400] description;
reg test_result;
reg [0:400] description;
begin
tests_done = tests_done + 1;
if(test_result) $display("ok - %s",description);
else begin
$display("not ok - %s",description);
tests_failed = tests_failed + 1;
end
end
endtask
task check_value;
parameter VALUE_WIDTH = 32;
input[VALUE_WIDTH-1:0] value,corr_value;
input[0:400] description;
reg[VALUE_WIDTH-1:0] value,corr_value;
reg[0:400] description;
begin
tests_done = tests_done + 1;
if(value === corr_value) $display("ok - %s",description);
else begin
$display("not ok - %s # found %h, expected %h",description,value,corr_value);
tests_failed = tests_failed + 1;
end
end
endtask
task print_report;
begin
if(tests_failed == 0) $display("\n#################\n# All tests passed!\n");
else $display("\n#################\n# Failed %0d/%0d tests\n",tests_failed,tests_done );
end
endtask
endmodule
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 1
(* X_CORE_INFO = "axi_register_slice_v2_1_axi_register_slice,Vivado 2013.4" *)
(* CHECK_LICENSE_TYPE = "system_m00_regslice_8,axi_register_slice_v2_1_axi_register_slice,{}" *)
(* CORE_GENERATION_INFO = "system_m00_regslice_8,axi_register_slice_v2_1_axi_register_slice,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_register_slice,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_AXI_PROTOCOL=2,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=9,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_REG_CONFIG_AW=7,C_REG_CONFIG_W=7,C_REG_CONFIG_B=7,C_REG_CONFIG_AR=7,C_REG_CONFIG_R=7}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_m00_regslice_8 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [8 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [8 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [8 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [8 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(9),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(7),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(7)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// ================================================================================
// Altera Avalon Half Rate Bridge
//
// Interface between two Avalon bus segments where master interface is
// clocked at twice the rate and synchronous to the slave interface
// ================================================================================
`timescale 1ns/1ns
module altera_avalon_half_rate_bridge (
avs_reset_n,
avm_reset_n,
// Avalon slave
avs_clk,
avs_chipselect,
avs_address,
avs_write,
avs_read,
avs_byteenable,
avs_writedata,
avs_readdata,
avs_waitrequest,
avs_readdatavalid,
// Avalon master
avm_clk,
avm_burstcount,
avm_address,
avm_write,
avm_read,
avm_byteenable,
avm_writedata,
avm_readdata,
avm_waitrequest,
avm_readdatavalid
);
localparam ENABLE_BURSTING_MASTER = 1;
parameter AVM_DATA_WIDTH = 32;
parameter AVM_ADDR_WIDTH = 28;
parameter AVM_BYTE_WIDTH = 4;
parameter AVS_DATA_WIDTH = 64;
parameter AVS_ADDR_WIDTH = 25;
parameter AVS_BYTE_WIDTH = 8;
// constant function to get number of bits from size
// e.g. burstlength 8 requires 4 bit burstcount [3:0]
function integer log2 (input integer size);
begin
for(log2 = 0; size > 0; log2 = log2 + 1)
size = size >> 1;
log2 = log2 - 1;
end
endfunction
// Avalon slave
input avs_reset_n; // Active low asynch reset
input avm_reset_n;
input avs_clk;
input avs_chipselect;
input [AVS_ADDR_WIDTH-1:0] avs_address;
input avs_write;
input avs_read;
input [AVS_BYTE_WIDTH-1:0] avs_byteenable;
input [AVS_DATA_WIDTH-1:0] avs_writedata;
output [AVS_DATA_WIDTH-1:0] avs_readdata;
output avs_waitrequest;
output avs_readdatavalid;
// Avalon master
input avm_clk; // Must be 2x and synchronous to avs_clk
input [AVM_DATA_WIDTH-1:0] avm_readdata;
input avm_waitrequest;
input avm_readdatavalid;
output [AVM_ADDR_WIDTH-1:0] avm_address;
output avm_write;
output avm_read;
output [AVM_BYTE_WIDTH-1:0] avm_byteenable;
output [AVM_DATA_WIDTH-1:0] avm_writedata;
output [1:0] avm_burstcount;
reg avs_waitrequest;
wire [2:0] avm_nxt_wr_txfers;
wire [2:0] avm_nxt_rd_txfers;
reg avm_read;
reg avm_write;
reg [AVM_ADDR_WIDTH-1:0] avm_address;
reg [AVM_BYTE_WIDTH-1:0] avm_byteenable;
reg [AVM_DATA_WIDTH-1:0] avm_writedata;
wire [1:0] avm_burstcount = 2'd2;
wire [AVM_BYTE_WIDTH:0] avm_addr_offset;
generate
if (ENABLE_BURSTING_MASTER)
assign avm_addr_offset = 0;
else
assign avm_addr_offset = (1'b1<<((log2(AVM_BYTE_WIDTH))));
endgenerate
//---------------------------------------------------------------------------
// AVS Control
//---------------------------------------------------------------------------
wire [2:0] avm_nxt_txfers;
always @(posedge avs_clk or negedge avs_reset_n)
if (~avs_reset_n)
avs_waitrequest <= 1'b1;
else
avs_waitrequest <= (avm_nxt_txfers >= 4'b011);
reg avs_toggle;
always @(posedge avs_clk or negedge avs_reset_n)
if (~avs_reset_n)
avs_toggle <= 1'b0;
else
avs_toggle <= ~avs_toggle;
reg avm_toggle;
reg avm_toggle_r;
always @(posedge avm_clk or negedge avm_reset_n)
if (~avm_reset_n)
begin
avm_toggle <= 1'b0;
avm_toggle_r <= 1'b0;
end
else
begin
avm_toggle <= avs_toggle;
avm_toggle_r <= avm_toggle;
end
wire avs_clk_ph = avm_toggle ^ avm_toggle_r;
//---------------------------------------------------------------------------
// Write path
//---------------------------------------------------------------------------
// Buffers can hold two avs transfers equivalent to four avm transfers
reg [AVS_DATA_WIDTH-1:0] avs_writedata_r;
reg [AVS_BYTE_WIDTH-1:0] avs_byteenable_r;
reg [AVM_ADDR_WIDTH-1:0] avs_addr_r;
reg [AVS_DATA_WIDTH-1:0] avs_skid;
reg [AVS_BYTE_WIDTH-1:0] avs_byte_skid;
reg [AVM_ADDR_WIDTH-1:0] avs_addr_skid;
always @(posedge avs_clk or negedge avs_reset_n)
if (~avs_reset_n)
begin
avs_writedata_r <= {AVS_DATA_WIDTH{1'b0}};
avs_byteenable_r <= {AVS_BYTE_WIDTH{1'b0}};
avs_addr_r <= {AVM_ADDR_WIDTH{1'b0}};
avs_skid <= {AVS_DATA_WIDTH{1'b0}};
avs_byte_skid <= {AVS_BYTE_WIDTH{1'b0}};
avs_addr_skid <= {AVM_ADDR_WIDTH{1'b0}};
end
else if (avs_chipselect & ~avs_waitrequest)
begin
avs_writedata_r <= avs_writedata;
avs_byteenable_r <= avs_byteenable;
avs_addr_r <= {avs_address, {log2(AVS_BYTE_WIDTH){1'b0}}};
avs_skid <= avs_writedata_r;
avs_byte_skid <= avs_byteenable_r;
avs_addr_skid <= avs_addr_r;
end
// Count number of oustanding avm write transfers
reg [2:0] avm_wr_txfers;
// decrement by 1 for every avm transfer
wire wr_txfers_dec = avm_write & ~avm_waitrequest;
// increment by 2 for every avs transfer
wire wr_txfers_inc2 = avs_write & ~avs_waitrequest & avs_clk_ph;
assign avm_nxt_wr_txfers = avm_wr_txfers + (wr_txfers_inc2 ? 3'b010 : 3'b0)
- (wr_txfers_dec ? 3'b001 : 3'b0);
always @(posedge avm_clk or negedge avm_reset_n)
if (~avm_reset_n)
avm_wr_txfers <= 3'b0;
else
avm_wr_txfers <= avm_nxt_wr_txfers;
//---------------------------------------------------------------------------
// Read path
//---------------------------------------------------------------------------
reg avs_readdatavalid;
reg [AVS_DATA_WIDTH-1:0] avs_readdata;
// Count number of oustanding avm read requests
reg [2:0] avm_rd_txfers;
// decrement for every avm transfer
wire rd_txfers_dec = avm_read & ~avm_waitrequest;
// increment by 2 for every avs transfer
wire rd_txfers_inc2 = avs_read & ~avs_waitrequest & avs_clk_ph;
generate
if (ENABLE_BURSTING_MASTER)
// decrement by 2 for each avm read if bursting is enabled
assign avm_nxt_rd_txfers = avm_rd_txfers + (rd_txfers_inc2 ? 3'b010 : 3'b0)
- (rd_txfers_dec ? 3'b010 : 3'b0);
else
assign avm_nxt_rd_txfers = avm_rd_txfers + (rd_txfers_inc2 ? 3'b010 : 3'b0)
- (rd_txfers_dec ? 3'b001 : 3'b0);
endgenerate
always @(posedge avm_clk or negedge avm_reset_n)
if (~avm_reset_n)
avm_rd_txfers <= 3'b0;
else
avm_rd_txfers <= avm_nxt_rd_txfers;
// Count number of oustanding avm read data transfers
reg [2:0] avm_rd_data_txfers;
// decrement by 2 for every avs transfer
wire rd_data_txfers_dec2 = avs_readdatavalid & avs_clk_ph;
// increment by 1 for every avm transfer
wire rd_data_txfers_inc = avm_readdatavalid;
wire [2:0] avm_nxt_rd_data_txfers = avm_rd_data_txfers + (rd_data_txfers_inc ? 3'b001 : 3'b0)
- (rd_data_txfers_dec2 ? 3'b010 : 3'b0);
assign avm_nxt_txfers = avm_nxt_rd_txfers + avm_nxt_wr_txfers;
wire [2:0] avm_txfers = avm_rd_txfers + avm_wr_txfers;
always @(posedge avm_clk or negedge avm_reset_n)
if (~avm_reset_n)
avm_rd_data_txfers <= 3'b0;
else
avm_rd_data_txfers <= avm_nxt_rd_data_txfers;
always @(posedge avs_clk or negedge avs_reset_n)
if (~avs_reset_n)
avs_readdatavalid <= 1'b0;
else
avs_readdatavalid <= (avm_nxt_rd_data_txfers >= 3'b010);
reg [AVS_DATA_WIDTH-1:0] avm_readdata_r;
reg [AVS_DATA_WIDTH-1:0] avm_skid;
always @(posedge avm_clk or negedge avm_reset_n)
if (~avm_reset_n)
begin
avm_readdata_r <= {AVS_DATA_WIDTH{1'b0}};
avm_skid <= {AVS_DATA_WIDTH{1'b0}};
end
else if (avm_readdatavalid & avm_nxt_rd_data_txfers[0])
begin
avm_readdata_r[AVM_DATA_WIDTH-1:0] <= avm_readdata;
avm_skid <= avm_readdata_r;
end
else if (avm_readdatavalid)
begin
avm_readdata_r[AVS_DATA_WIDTH-1:AVM_DATA_WIDTH] <= avm_readdata;
end
always @(avm_readdata_r, avm_rd_data_txfers, avm_skid)
case (avm_rd_data_txfers)
3'd4, 3'd3: avs_readdata = avm_skid;
default: avs_readdata = avm_readdata_r;
endcase
//---------------------------------------------------------------------------
// AVM control
//---------------------------------------------------------------------------
reg [5:0] avm_state;
localparam AVM_IDLE = 6'b000001,
AVM_WRITE1 = 6'b000010,
AVM_READ1 = 6'b000100;
always @(posedge avm_clk or negedge avm_reset_n)
if (~avm_reset_n)
begin
avm_write <= 1'b0;
avm_read <= 1'b0;
avm_state <= AVM_IDLE;
end
else
case (avm_state)
AVM_IDLE:
if (|(avm_nxt_wr_txfers))
begin
avm_write <= 1'b1;
avm_state <= AVM_WRITE1;
end
else if (|(avm_nxt_rd_txfers))
begin
avm_read <= 1'b1;
avm_state <= AVM_READ1;
end
AVM_WRITE1:
if (~(|avm_nxt_wr_txfers) & ~(|avm_nxt_rd_txfers) & ~avm_waitrequest)
begin
avm_write <= 1'b0;
avm_state <= AVM_IDLE;
end
else if (~(|avm_nxt_wr_txfers) & (|avm_nxt_rd_txfers) & ~avm_waitrequest)
begin
avm_write <= 1'b0;
avm_read <= 1'b1;
avm_state <= AVM_READ1;
end
AVM_READ1:
if (~(|avm_nxt_rd_txfers) & ~(|avm_nxt_wr_txfers) & ~avm_waitrequest)
begin
avm_read <= 1'b0;
avm_state <= AVM_IDLE;
end
else if (~(|avm_nxt_rd_txfers) & (|avm_nxt_wr_txfers) & ~avm_waitrequest)
begin
avm_read <= 1'b0;
avm_write <= 1'b1;
avm_state <= AVM_WRITE1;
end
default:
avm_state <= AVM_IDLE;
endcase
// Write data is selected from the buffers depending on how many transfers
// are outstanding
always @(avs_writedata_r, avs_skid, avm_txfers)
case (avm_txfers)
3'd4: avm_writedata <= avs_skid[AVM_DATA_WIDTH-1:0];
3'd3: avm_writedata <= avs_skid[AVS_DATA_WIDTH-1:AVM_DATA_WIDTH];
3'd2: avm_writedata <= avs_writedata_r[AVM_DATA_WIDTH-1:0];
3'd1: avm_writedata <= avs_writedata_r[AVS_DATA_WIDTH-1:AVM_DATA_WIDTH];
default: avm_writedata <= {AVM_DATA_WIDTH{1'b0}};
endcase
// Similarly for byte enables
always @(avm_state, avs_byteenable_r, avs_byte_skid, avm_txfers)
case (avm_txfers)
3'd4: avm_byteenable <= avs_byte_skid[AVM_BYTE_WIDTH-1:0];
3'd3: avm_byteenable <= avs_byte_skid[AVS_BYTE_WIDTH-1:AVM_BYTE_WIDTH];
3'd2: avm_byteenable <= avs_byteenable_r[AVM_BYTE_WIDTH-1:0];
3'd1: avm_byteenable <= avs_byteenable_r[AVS_BYTE_WIDTH-1:AVM_BYTE_WIDTH];
default: avm_byteenable <= {AVM_BYTE_WIDTH{1'b0}};
endcase
// And address
always @(avm_state, avs_addr_r, avs_addr_skid, avm_txfers)
case (avm_txfers)
3'd4: avm_address <= avs_addr_skid;
3'd3: avm_address <= avs_addr_skid | avm_addr_offset;
3'd2: avm_address <= avs_addr_r;
3'd1: avm_address <= avs_addr_r | avm_addr_offset;
default: avm_address <= {AVM_ADDR_WIDTH{1'b0}};
endcase
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// [16] is SV syntax for [15:0]
reg [7:0] memory8_16 [16];
reg m_we;
reg [3:1] m_addr;
reg [15:0] m_data;
always @ (posedge clk) begin
// Load instructions from cache
memory8_16[{m_addr,1'd0}] <= 8'hfe;
if (m_we) begin
{memory8_16[{m_addr,1'd1}],
memory8_16[{m_addr,1'd0}]} <= m_data;
end
end
reg [7:0] memory8_16_4;
reg [7:0] memory8_16_5;
// Test complicated sensitivity lists
always @ (memory8_16[4][7:1] or memory8_16[5]) begin
memory8_16_4 = memory8_16[4];
memory8_16_5 = memory8_16[5];
end
always @ (posedge clk) begin
m_we <= 0;
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
m_we <= 1'b1;
m_addr <= 3'd2;
m_data <= 16'h55_44;
end
if (cyc==2) begin
m_we <= 1'b1;
m_addr <= 3'd3;
m_data <= 16'h77_66;
end
if (cyc==3) begin
m_we <= 0; // Check we really don't write this
m_addr <= 3'd3;
m_data <= 16'h0bad;
end
if (cyc==5) begin
if (memory8_16_4 != 8'h44) $stop;
if (memory8_16_5 != 8'h55) $stop;
if (memory8_16[6] != 8'hfe) $stop;
if (memory8_16[7] != 8'h77) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
`timescale 1ns / 1ps
/*
* Copyright 2015 Forest Crossman
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
*/
`include "ipcore_dir/osdvu/uart.v"
module uart_demo(
input CLK_100MHz,
input Rx,
output Tx
);
wire reset;
reg transmit;
reg [7:0] tx_byte;
wire received;
wire [7:0] rx_byte;
wire is_receiving;
wire is_transmitting;
wire recv_error;
uart #(
.baud_rate(19200), // This must always be 19200
.sys_clk_freq(100000000) // The master clock frequency
)
uart0(
.clk(CLK_100MHz), // The master clock for this module
.rst(reset), // Synchronous reset
.rx(Rx), // Incoming serial line
.tx(Tx), // Outgoing serial line
.transmit(transmit), // Signal to transmit
.tx_byte(tx_byte), // Byte to transmit
.received(received), // Indicated that a byte has been received
.rx_byte(rx_byte), // Byte received
.is_receiving(is_receiving), // Low when receive line is idle
.is_transmitting(is_transmitting),// Low when transmit line is idle
.recv_error(recv_error) // Indicates error in receiving packet.
);
always @(posedge CLK_100MHz) begin
if (received) begin
tx_byte <= rx_byte;
transmit <= 1;
end
if (is_transmitting) begin
transmit <= 0;
end
end
endmodule
|
//==============================================================================
// File: $URL: svn+ssh://[email protected]/public/Projects/GateLib/branches/dev/Publications/Tutorials/Publications/EECS150/Labs/ChipScopeSerial/Framework/IORegister.v $
// Version: $Revision: 26904 $
// Author: Greg Gibeling (http://www.gdgib.com)
// Copyright: Copyright 2003-2010 UC Berkeley
//==============================================================================
//==============================================================================
// Section: License
//==============================================================================
// Copyright (c) 2005-2010, Regents of the University of California
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer
// in the documentation and/or other materials provided with the
// distribution.
// - Neither the name of the University of California, Berkeley nor the
// names of its contributors may be used to endorse or promote
// products derived from this software without specific prior
// written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//==============================================================================
//------------------------------------------------------------------------------
// Module: IORegister
// Desc: A register which should be packed in to IO pads.
// Author: <a href="http://www.gdgib.com/">Greg Gibeling</a>
// Version: $Revision: 26904 $
//------------------------------------------------------------------------------
module IORegister(Clock, Reset, Set, Enable, In, Out);
//--------------------------------------------------------------------------
// Parameters
//--------------------------------------------------------------------------
parameter Width = 32,
Initial = {Width{1'bx}},
AsyncReset = 0,
AsyncSet = 0,
ResetValue = {Width{1'b0}},
SetValue = {Width{1'b1}};
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Inputs & Outputs
//--------------------------------------------------------------------------
input Clock, Enable, Reset, Set;
input [Width-1:0] In;
output reg [Width-1:0] Out = Initial /* synthesis syn_useioff = 1 iob = true useioff = 1 */;
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Behavioral Register
//--------------------------------------------------------------------------
generate if (AsyncReset) begin:AR
if (AsyncSet) begin:AS
always @ (posedge Clock or posedge Reset or posedge Set) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end else begin:SS
always @ (posedge Clock or posedge Reset) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end
end else begin:SR
if (AsyncSet) begin:AS
always @ (posedge Clock or posedge Set) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end else begin:SS
always @ (posedge Clock) begin
if (Reset) Out <= ResetValue;
else if (Set) Out <= SetValue;
else if (Enable) Out <= In;
end
end
end endgenerate
//--------------------------------------------------------------------------
endmodule
//------------------------------------------------------------------------------
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9122 (
// dac interface
dac_clk_in_p,
dac_clk_in_n,
dac_clk_out_p,
dac_clk_out_n,
dac_frame_out_p,
dac_frame_out_n,
dac_data_out_p,
dac_data_out_n,
// master/slave
dac_sync_out,
dac_sync_in,
// dma interface
dac_div_clk,
dac_valid_0,
dac_enable_0,
dac_ddata_0,
dac_valid_1,
dac_enable_1,
dac_ddata_1,
dac_dovf,
dac_dunf,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rdata,
s_axi_rresp,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_SERDES_DDR_N = 1;
parameter PCORE_MMCM_BUFIO_N = 1;
parameter PCORE_DAC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
// dac interface
input dac_clk_in_p;
input dac_clk_in_n;
output dac_clk_out_p;
output dac_clk_out_n;
output dac_frame_out_p;
output dac_frame_out_n;
output [15:0] dac_data_out_p;
output [15:0] dac_data_out_n;
// master/slave
output dac_sync_out;
input dac_sync_in;
// dma interface
output dac_div_clk;
output dac_valid_0;
output dac_enable_0;
input [63:0] dac_ddata_0;
output dac_valid_1;
output dac_enable_1;
input [63:0] dac_ddata_1;
input dac_dovf;
input dac_dunf;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [31:0] s_axi_rdata;
output [ 1:0] s_axi_rresp;
input s_axi_rready;
// internal clocks and resets
wire dac_rst;
wire mmcm_rst;
wire up_clk;
wire up_rstn;
// internal signals
wire dac_frame_i0_s;
wire [15:0] dac_data_i0_s;
wire dac_frame_i1_s;
wire [15:0] dac_data_i1_s;
wire dac_frame_i2_s;
wire [15:0] dac_data_i2_s;
wire dac_frame_i3_s;
wire [15:0] dac_data_i3_s;
wire dac_frame_q0_s;
wire [15:0] dac_data_q0_s;
wire dac_frame_q1_s;
wire [15:0] dac_data_q1_s;
wire dac_frame_q2_s;
wire [15:0] dac_data_q2_s;
wire dac_frame_q3_s;
wire [15:0] dac_data_q3_s;
wire dac_status_s;
wire up_drp_sel_s;
wire up_drp_wr_s;
wire [11:0] up_drp_addr_s;
wire [15:0] up_drp_wdata_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
wire up_drp_locked_s;
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_wack_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
wire [31:0] up_rdata_s;
wire up_rack_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// device interface
axi_ad9122_if #(
.PCORE_DEVICE_TYPE (PCORE_DEVICE_TYPE),
.PCORE_SERDES_DDR_N (PCORE_SERDES_DDR_N),
.PCORE_MMCM_BUFIO_N (PCORE_MMCM_BUFIO_N))
i_if (
.dac_clk_in_p (dac_clk_in_p),
.dac_clk_in_n (dac_clk_in_n),
.dac_clk_out_p (dac_clk_out_p),
.dac_clk_out_n (dac_clk_out_n),
.dac_frame_out_p (dac_frame_out_p),
.dac_frame_out_n (dac_frame_out_n),
.dac_data_out_p (dac_data_out_p),
.dac_data_out_n (dac_data_out_n),
.dac_rst (dac_rst),
.dac_clk (),
.dac_div_clk (dac_div_clk),
.dac_status (dac_status_s),
.dac_frame_i0 (dac_frame_i0_s),
.dac_data_i0 (dac_data_i0_s),
.dac_frame_i1 (dac_frame_i1_s),
.dac_data_i1 (dac_data_i1_s),
.dac_frame_i2 (dac_frame_i2_s),
.dac_data_i2 (dac_data_i2_s),
.dac_frame_i3 (dac_frame_i3_s),
.dac_data_i3 (dac_data_i3_s),
.dac_frame_q0 (dac_frame_q0_s),
.dac_data_q0 (dac_data_q0_s),
.dac_frame_q1 (dac_frame_q1_s),
.dac_data_q1 (dac_data_q1_s),
.dac_frame_q2 (dac_frame_q2_s),
.dac_data_q2 (dac_data_q2_s),
.dac_frame_q3 (dac_frame_q3_s),
.dac_data_q3 (dac_data_q3_s),
.mmcm_rst (mmcm_rst),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s));
// core
axi_ad9122_core #(.PCORE_ID(PCORE_ID), .DP_DISABLE(PCORE_DAC_DP_DISABLE)) i_core (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_frame_i0 (dac_frame_i0_s),
.dac_data_i0 (dac_data_i0_s),
.dac_frame_i1 (dac_frame_i1_s),
.dac_data_i1 (dac_data_i1_s),
.dac_frame_i2 (dac_frame_i2_s),
.dac_data_i2 (dac_data_i2_s),
.dac_frame_i3 (dac_frame_i3_s),
.dac_data_i3 (dac_data_i3_s),
.dac_frame_q0 (dac_frame_q0_s),
.dac_data_q0 (dac_data_q0_s),
.dac_frame_q1 (dac_frame_q1_s),
.dac_data_q1 (dac_data_q1_s),
.dac_frame_q2 (dac_frame_q2_s),
.dac_data_q2 (dac_data_q2_s),
.dac_frame_q3 (dac_frame_q3_s),
.dac_data_q3 (dac_data_q3_s),
.dac_status (dac_status_s),
.dac_sync_out (dac_sync_out),
.dac_sync_in (dac_sync_in),
.dac_valid_0 (dac_valid_0),
.dac_enable_0 (dac_enable_0),
.dac_ddata_0 (dac_ddata_0),
.dac_valid_1 (dac_valid_1),
.dac_enable_1 (dac_enable_1),
.dac_ddata_1 (dac_ddata_1),
.dac_dovf (dac_dovf),
.dac_dunf (dac_dunf),
.mmcm_rst (mmcm_rst),
.up_drp_sel (up_drp_sel_s),
.up_drp_wr (up_drp_wr_s),
.up_drp_addr (up_drp_addr_s),
.up_drp_wdata (up_drp_wdata_s),
.up_drp_rdata (up_drp_rdata_s),
.up_drp_ready (up_drp_ready_s),
.up_drp_locked (up_drp_locked_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s),
.up_rack (up_rack_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_pio_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
bidir_port,
readdata
)
;
inout [ 3: 0] bidir_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire [ 3: 0] bidir_port;
wire clk_en;
reg [ 3: 0] data_dir;
wire [ 3: 0] data_in;
reg [ 3: 0] data_out;
wire [ 3: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({4 {(address == 0)}} & data_in) |
({4 {(address == 1)}} & data_dir);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[3 : 0];
end
assign bidir_port[0] = data_dir[0] ? data_out[0] : 1'bZ;
assign bidir_port[1] = data_dir[1] ? data_out[1] : 1'bZ;
assign bidir_port[2] = data_dir[2] ? data_out[2] : 1'bZ;
assign bidir_port[3] = data_dir[3] ? data_out[3] : 1'bZ;
assign data_in = bidir_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_dir <= 0;
else if (chipselect && ~write_n && (address == 1))
data_dir <= writedata[3 : 0];
end
endmodule
|
`include "core.h"
`default_nettype none
module pipeline_control_spr_exchange(
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//System Register
input wire [31:0] iSYSREG_SPR,
input wire [31:0] iSYSREG_TISR,
input wire [31:0] iSYSREG_TIDR,
//Request
input wire iRD_START,
input wire iRD_KERNEL, //0:User Mode(Kernel -> User) | 1 : Kernel Mode(User -> Kernel)
//FInish
output wire oFINISH,
output wire [31:0] oFINISH_SPR,
//Load Store
output wire oLDST_USE,
output wire oLDST_REQ,
input wire iLDST_BUSY,
output wire [1:0] oLDST_ORDER, //00=Byte Order 01=2Byte Order 10= Word Order 11= None
output wire oLDST_RW, //0=Read 1=Write
output wire [13:0] oLDST_ASID,
output wire [1:0] oLDST_MMUMOD,
output wire [31:0] oLDST_PDT,
output wire [31:0] oLDST_ADDR,
output wire [31:0] oLDST_DATA,
input wire iLDST_REQ,
input wire [31:0] iLDST_DATA
);
/***************************************************************************
State
***************************************************************************/
localparam L_PARAM_IDLE = 3'h0;
localparam L_PARAM_LOAD_REQ = 3'h1;
localparam L_PARAM_LOAD_ACK = 3'h2;
localparam L_PARAM_STORE_REQ = 3'h3;
localparam L_PARAM_STORE_ACK = 3'h4;
reg [2:0] state;
reg [2:0] b_state;
always@*begin
case(b_state)
L_PARAM_IDLE:
begin
if(iRD_START)begin
state = L_PARAM_LOAD_REQ;
end
else begin
state = L_PARAM_IDLE;
end
end
L_PARAM_LOAD_REQ:
begin
if(!iLDST_BUSY)begin
state = L_PARAM_LOAD_ACK;
end
else begin
state = L_PARAM_LOAD_REQ;
end
end
L_PARAM_LOAD_ACK:
begin
//Get Check
if(iLDST_REQ)begin
state = L_PARAM_STORE_REQ;
end
else begin
state = L_PARAM_LOAD_ACK;
end
end
L_PARAM_STORE_REQ:
begin
if(!iLDST_BUSY)begin
state = L_PARAM_STORE_ACK;
end
else begin
state = L_PARAM_STORE_REQ;
end
end
L_PARAM_STORE_ACK:
begin
//Get Check
if(iLDST_REQ)begin
state = L_PARAM_IDLE;
end
else begin
state = L_PARAM_STORE_ACK;
end
end
default:
begin
state = L_PARAM_IDLE;
end
endcase
end
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_state <= L_PARAM_IDLE;
end
else if(iRESET_SYNC)begin
b_state <= L_PARAM_IDLE;
end
else begin
b_state <= state;
end
end
reg b_finish;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_finish <= 1'b0;
end
else if(iRESET_SYNC)begin
b_finish <= 1'b0;
end
else begin
b_finish <= (state == L_PARAM_STORE_ACK) && iLDST_REQ;
end
end
/***************************************************************************
Load Data Buffer
***************************************************************************/
reg [31:0] b_load_data;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_load_data <= 32'h0;
end
else if(iRESET_SYNC)begin
b_load_data <= 32'h0;
end
else begin
if((state == L_PARAM_LOAD_ACK) && iLDST_REQ)begin
b_load_data <= iLDST_DATA;
end
end
end
/***************************************************************************
Load Store Pipe
***************************************************************************/
reg b_ldst_use;
reg b_ldst_req;
reg [31:0] b_ldst_data;
wire [31:0] uspr_addr = iSYSREG_TISR + {iSYSREG_TIDR[13:0], 8'h0} + `TST_USPR;
wire [31:0] kspr_addr = iSYSREG_TISR + {iSYSREG_TIDR[13:0], 8'h0} + `TST_KSPR;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_ldst_use <= 1'b0;
b_ldst_req <= 1'b0;
b_ldst_data <= 32'h0;
end
else if(iRESET_SYNC)begin
b_ldst_use <= 1'b0;
b_ldst_req <= 1'b0;
b_ldst_data <= 32'h0;
end
else begin
b_ldst_use <= state != L_PARAM_IDLE;
b_ldst_req <= state == L_PARAM_STORE_REQ || state == L_PARAM_LOAD_REQ;
b_ldst_data <= iSYSREG_SPR;
end
end
reg [31:0] b_ldst_addr;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_ldst_addr <= 32'h0;
end
else if(iRESET_SYNC)begin
b_ldst_addr <= 32'h0;
end
else begin
if(iRD_KERNEL)begin
if(state == L_PARAM_STORE_REQ)begin
b_ldst_addr <= uspr_addr;
end
else begin
b_ldst_addr <= kspr_addr;
end
end
else begin
if(state == L_PARAM_STORE_REQ)begin
b_ldst_addr <= kspr_addr;
end
else begin
b_ldst_addr <= uspr_addr;
end
end
end
end
/***************************************************************************
Assign
***************************************************************************/
assign oFINISH = b_finish;
assign oFINISH_SPR = b_load_data;
assign oLDST_USE = b_ldst_use;
assign oLDST_REQ = b_ldst_req;
assign oLDST_ORDER = 2'h2; //00=Byte Order 01=2Byte Order 10= Word Order 11= None
assign oLDST_RW = 1'b0; //0=Read 1=Write
assign oLDST_ASID = 14'h0;
assign oLDST_MMUMOD = 2'h0;
assign oLDST_PDT = 32'h0;
assign oLDST_ADDR = b_ldst_addr;
assign oLDST_DATA = b_ldst_data;
endmodule
`default_nettype wire |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 36Kb FIFO (First-In-First-Out) Block RAM Memory
// /___/ /\ Filename : FIFO36E2.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 11/30/2012 - intial
// 12/12/2012 - yaml update, 691724 and 691715
// 02/07/2013 - 699628 - correction to DO_PIPELINED mode
// 02/28/2013 - update to keep in sync with RAMB models
// 03/18/2013 - 707083 reads should clear FULL when RD & WR in CDC.
// 03/22/2013 - sync5 yaml update, port ordering, *RSTBUSY
// 03/25/2013 - 707652 - RST = 1 n enters RST sequence but does not hold it there.
// 03/25/2013 - 707719 - Add sync5 cascade feature
// 03/27/2013 - 708820 - FULL flag deassert during WREN ind clocks.
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module FIFO36E2 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CASCADE_ORDER = "NONE",
parameter CLOCK_DOMAINS = "INDEPENDENT",
parameter EN_ECC_PIPE = "FALSE",
parameter EN_ECC_READ = "FALSE",
parameter EN_ECC_WRITE = "FALSE",
parameter FIRST_WORD_FALL_THROUGH = "FALSE",
parameter [71:0] INIT = 72'h000000000000000000,
parameter [0:0] IS_RDCLK_INVERTED = 1'b0,
parameter [0:0] IS_RDEN_INVERTED = 1'b0,
parameter [0:0] IS_RSTREG_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter [0:0] IS_WRCLK_INVERTED = 1'b0,
parameter [0:0] IS_WREN_INVERTED = 1'b0,
parameter integer PROG_EMPTY_THRESH = 256,
parameter integer PROG_FULL_THRESH = 256,
parameter RDCOUNT_TYPE = "RAW_PNTR",
parameter integer READ_WIDTH = 4,
parameter REGISTER_MODE = "UNREGISTERED",
parameter RSTREG_PRIORITY = "RSTREG",
parameter SLEEP_ASYNC = "FALSE",
parameter [71:0] SRVAL = 72'h000000000000000000,
parameter WRCOUNT_TYPE = "RAW_PNTR",
parameter integer WRITE_WIDTH = 4
)(
output [63:0] CASDOUT,
output [7:0] CASDOUTP,
output CASNXTEMPTY,
output CASPRVRDEN,
output DBITERR,
output [63:0] DOUT,
output [7:0] DOUTP,
output [7:0] ECCPARITY,
output EMPTY,
output FULL,
output PROGEMPTY,
output PROGFULL,
output [13:0] RDCOUNT,
output RDERR,
output RDRSTBUSY,
output SBITERR,
output [13:0] WRCOUNT,
output WRERR,
output WRRSTBUSY,
input [63:0] CASDIN,
input [7:0] CASDINP,
input CASDOMUX,
input CASDOMUXEN,
input CASNXTRDEN,
input CASOREGIMUX,
input CASOREGIMUXEN,
input CASPRVEMPTY,
input [63:0] DIN,
input [7:0] DINP,
input INJECTDBITERR,
input INJECTSBITERR,
input RDCLK,
input RDEN,
input REGCE,
input RST,
input RSTREG,
input SLEEP,
input WRCLK,
input WREN
);
// define constants
localparam MODULE_NAME = "FIFO36E2";
// Parameter encodings and registers
localparam CASCADE_ORDER_FIRST = 1;
localparam CASCADE_ORDER_LAST = 2;
localparam CASCADE_ORDER_MIDDLE = 3;
localparam CASCADE_ORDER_NONE = 0;
localparam CASCADE_ORDER_PARALLEL = 4;
localparam CLOCK_DOMAINS_COMMON = 1;
localparam CLOCK_DOMAINS_INDEPENDENT = 0;
localparam EN_ECC_PIPE_FALSE = 0;
localparam EN_ECC_PIPE_TRUE = 1;
localparam EN_ECC_READ_FALSE = 0;
localparam EN_ECC_READ_TRUE = 1;
localparam EN_ECC_WRITE_FALSE = 0;
localparam EN_ECC_WRITE_TRUE = 1;
localparam FIRST_WORD_FALL_THROUGH_FALSE = 0;
localparam FIRST_WORD_FALL_THROUGH_TRUE = 1;
localparam RDCOUNT_TYPE_EXTENDED_DATACOUNT = 1;
localparam RDCOUNT_TYPE_RAW_PNTR = 0;
localparam RDCOUNT_TYPE_SIMPLE_DATACOUNT = 2;
localparam RDCOUNT_TYPE_SYNC_PNTR = 3;
localparam READ_WIDTH_18 = 16;
localparam READ_WIDTH_36 = 32;
localparam READ_WIDTH_4 = 4;
localparam READ_WIDTH_72 = 64;
localparam READ_WIDTH_9 = 8;
localparam REGISTER_MODE_DO_PIPELINED = 1;
localparam REGISTER_MODE_REGISTERED = 2;
localparam REGISTER_MODE_UNREGISTERED = 0;
localparam RSTREG_PRIORITY_REGCE = 1;
localparam RSTREG_PRIORITY_RSTREG = 0;
localparam SLEEP_ASYNC_FALSE = 0;
localparam SLEEP_ASYNC_TRUE = 1;
localparam WRCOUNT_TYPE_EXTENDED_DATACOUNT = 1;
localparam WRCOUNT_TYPE_RAW_PNTR = 0;
localparam WRCOUNT_TYPE_SIMPLE_DATACOUNT = 2;
localparam WRCOUNT_TYPE_SYNC_PNTR = 3;
localparam WRITE_WIDTH_18 = 16;
localparam WRITE_WIDTH_36 = 32;
localparam WRITE_WIDTH_4 = 4;
localparam WRITE_WIDTH_72 = 64;
localparam WRITE_WIDTH_9 = 8;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "FIFO36E2_dr.v"
`else
localparam [64:1] CASCADE_ORDER_REG = CASCADE_ORDER;
localparam [88:1] CLOCK_DOMAINS_REG = CLOCK_DOMAINS;
localparam [40:1] EN_ECC_PIPE_REG = EN_ECC_PIPE;
localparam [40:1] EN_ECC_READ_REG = EN_ECC_READ;
localparam [40:1] EN_ECC_WRITE_REG = EN_ECC_WRITE;
localparam [40:1] FIRST_WORD_FALL_THROUGH_REG = FIRST_WORD_FALL_THROUGH;
localparam [71:0] INIT_REG = INIT;
localparam [0:0] IS_RDCLK_INVERTED_REG = IS_RDCLK_INVERTED;
localparam [0:0] IS_RDEN_INVERTED_REG = IS_RDEN_INVERTED;
localparam [0:0] IS_RSTREG_INVERTED_REG = IS_RSTREG_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam [0:0] IS_WRCLK_INVERTED_REG = IS_WRCLK_INVERTED;
localparam [0:0] IS_WREN_INVERTED_REG = IS_WREN_INVERTED;
localparam [12:0] PROG_EMPTY_THRESH_REG = PROG_EMPTY_THRESH;
localparam [12:0] PROG_FULL_THRESH_REG = PROG_FULL_THRESH;
localparam [144:1] RDCOUNT_TYPE_REG = RDCOUNT_TYPE;
localparam [6:0] READ_WIDTH_REG = READ_WIDTH;
localparam [96:1] REGISTER_MODE_REG = REGISTER_MODE;
localparam [48:1] RSTREG_PRIORITY_REG = RSTREG_PRIORITY;
localparam [40:1] SLEEP_ASYNC_REG = SLEEP_ASYNC;
localparam [71:0] SRVAL_REG = SRVAL;
localparam [144:1] WRCOUNT_TYPE_REG = WRCOUNT_TYPE;
localparam [6:0] WRITE_WIDTH_REG = WRITE_WIDTH;
`endif
wire [2:0] CASCADE_ORDER_BIN;
wire CLOCK_DOMAINS_BIN;
wire EN_ECC_PIPE_BIN;
wire EN_ECC_READ_BIN;
wire EN_ECC_WRITE_BIN;
wire FIRST_WORD_FALL_THROUGH_BIN;
wire [71:0] INIT_BIN;
wire IS_RDCLK_INVERTED_BIN;
wire IS_RDEN_INVERTED_BIN;
wire IS_RSTREG_INVERTED_BIN;
wire IS_RST_INVERTED_BIN;
wire IS_WRCLK_INVERTED_BIN;
wire IS_WREN_INVERTED_BIN;
wire [12:0] PROG_EMPTY_THRESH_BIN;
wire [12:0] PROG_FULL_THRESH_BIN;
wire [1:0] RDCOUNT_TYPE_BIN;
wire [6:0] READ_WIDTH_BIN;
wire [1:0] REGISTER_MODE_BIN;
wire RSTREG_PRIORITY_BIN;
wire SLEEP_ASYNC_BIN;
wire [71:0] SRVAL_BIN;
wire [1:0] WRCOUNT_TYPE_BIN;
wire [6:0] WRITE_WIDTH_BIN;
reg INIT_MEM = 0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR || INIT_MEM;
wire CASNXTEMPTY_out;
wire CASPRVRDEN_out;
wire DBITERR_out;
wire EMPTY_out;
wire FULL_out;
wire PROGEMPTY_out;
wire PROGFULL_out;
wire RDERR_out;
wire RDRSTBUSY_out;
wire SBITERR_out;
wire WRERR_out;
wire WRRSTBUSY_out;
wire [13:0] RDCOUNT_out;
wire [13:0] WRCOUNT_out;
wire [63:0] CASDOUT_out;
reg [63:0] DOUT_out;
wire [7:0] CASDOUTP_out;
reg [7:0] DOUTP_out;
wire [7:0] ECCPARITY_out;
wire CASDOMUXEN_in;
wire CASDOMUX_in;
wire CASNXTRDEN_in;
wire CASOREGIMUXEN_in;
wire CASOREGIMUX_in;
wire CASPRVEMPTY_in;
wire INJECTDBITERR_in;
wire INJECTSBITERR_in;
wire RDCLK_in;
wire RDEN_in;
wire REGCE_in;
wire RSTREG_in;
wire RST_in;
wire RST_in_pulse;
wire SLEEP_in;
wire WRCLK_in;
wire WREN_in;
wire [63:0] CASDIN_in;
reg [63:0] DIN_in;
wire [7:0] CASDINP_in;
reg [7:0] DINP_in;
`ifdef XIL_TIMING
wire CASDOMUXEN_delay;
wire CASDOMUX_delay;
wire CASNXTRDEN_delay;
wire CASOREGIMUXEN_delay;
wire CASOREGIMUX_delay;
wire CASPRVEMPTY_delay;
wire INJECTDBITERR_delay;
wire INJECTSBITERR_delay;
wire RDCLK_delay;
wire RDEN_delay;
wire REGCE_delay;
wire RSTREG_delay;
wire RST_delay;
wire SLEEP_delay;
wire WRCLK_delay;
wire WREN_delay;
wire [63:0] CASDIN_delay;
wire [63:0] DIN_delay;
wire [7:0] CASDINP_delay;
wire [7:0] DINP_delay;
`endif
assign CASDOUT = CASDOUT_out;
assign CASDOUTP = CASDOUTP_out;
assign CASNXTEMPTY = CASNXTEMPTY_out;
assign CASPRVRDEN = CASPRVRDEN_out;
assign DBITERR = DBITERR_out;
assign DOUT = DOUT_out;
assign DOUTP = DOUTP_out;
assign ECCPARITY = ECCPARITY_out;
assign EMPTY = EMPTY_out;
assign FULL = FULL_out;
assign PROGEMPTY = PROGEMPTY_out;
assign PROGFULL = PROGFULL_out;
assign RDCOUNT = RDCOUNT_out;
assign RDERR = RDERR_out;
assign RDRSTBUSY = RDRSTBUSY_out;
assign SBITERR = SBITERR_out;
assign WRCOUNT = WRCOUNT_out;
assign WRERR = WRERR_out;
assign WRRSTBUSY = WRRSTBUSY_out;
`ifdef XIL_TIMING
assign CASDINP_in[0] = (CASDINP[0] !== 1'bz) && CASDINP_delay[0]; // rv 0
assign CASDINP_in[1] = (CASDINP[1] !== 1'bz) && CASDINP_delay[1]; // rv 0
assign CASDINP_in[2] = (CASDINP[2] !== 1'bz) && CASDINP_delay[2]; // rv 0
assign CASDINP_in[3] = (CASDINP[3] !== 1'bz) && CASDINP_delay[3]; // rv 0
assign CASDINP_in[4] = (CASDINP[4] !== 1'bz) && CASDINP_delay[4]; // rv 0
assign CASDINP_in[5] = (CASDINP[5] !== 1'bz) && CASDINP_delay[5]; // rv 0
assign CASDINP_in[6] = (CASDINP[6] !== 1'bz) && CASDINP_delay[6]; // rv 0
assign CASDINP_in[7] = (CASDINP[7] !== 1'bz) && CASDINP_delay[7]; // rv 0
assign CASDIN_in[0] = (CASDIN[0] !== 1'bz) && CASDIN_delay[0]; // rv 0
assign CASDIN_in[10] = (CASDIN[10] !== 1'bz) && CASDIN_delay[10]; // rv 0
assign CASDIN_in[11] = (CASDIN[11] !== 1'bz) && CASDIN_delay[11]; // rv 0
assign CASDIN_in[12] = (CASDIN[12] !== 1'bz) && CASDIN_delay[12]; // rv 0
assign CASDIN_in[13] = (CASDIN[13] !== 1'bz) && CASDIN_delay[13]; // rv 0
assign CASDIN_in[14] = (CASDIN[14] !== 1'bz) && CASDIN_delay[14]; // rv 0
assign CASDIN_in[15] = (CASDIN[15] !== 1'bz) && CASDIN_delay[15]; // rv 0
assign CASDIN_in[16] = (CASDIN[16] !== 1'bz) && CASDIN_delay[16]; // rv 0
assign CASDIN_in[17] = (CASDIN[17] !== 1'bz) && CASDIN_delay[17]; // rv 0
assign CASDIN_in[18] = (CASDIN[18] !== 1'bz) && CASDIN_delay[18]; // rv 0
assign CASDIN_in[19] = (CASDIN[19] !== 1'bz) && CASDIN_delay[19]; // rv 0
assign CASDIN_in[1] = (CASDIN[1] !== 1'bz) && CASDIN_delay[1]; // rv 0
assign CASDIN_in[20] = (CASDIN[20] !== 1'bz) && CASDIN_delay[20]; // rv 0
assign CASDIN_in[21] = (CASDIN[21] !== 1'bz) && CASDIN_delay[21]; // rv 0
assign CASDIN_in[22] = (CASDIN[22] !== 1'bz) && CASDIN_delay[22]; // rv 0
assign CASDIN_in[23] = (CASDIN[23] !== 1'bz) && CASDIN_delay[23]; // rv 0
assign CASDIN_in[24] = (CASDIN[24] !== 1'bz) && CASDIN_delay[24]; // rv 0
assign CASDIN_in[25] = (CASDIN[25] !== 1'bz) && CASDIN_delay[25]; // rv 0
assign CASDIN_in[26] = (CASDIN[26] !== 1'bz) && CASDIN_delay[26]; // rv 0
assign CASDIN_in[27] = (CASDIN[27] !== 1'bz) && CASDIN_delay[27]; // rv 0
assign CASDIN_in[28] = (CASDIN[28] !== 1'bz) && CASDIN_delay[28]; // rv 0
assign CASDIN_in[29] = (CASDIN[29] !== 1'bz) && CASDIN_delay[29]; // rv 0
assign CASDIN_in[2] = (CASDIN[2] !== 1'bz) && CASDIN_delay[2]; // rv 0
assign CASDIN_in[30] = (CASDIN[30] !== 1'bz) && CASDIN_delay[30]; // rv 0
assign CASDIN_in[31] = (CASDIN[31] !== 1'bz) && CASDIN_delay[31]; // rv 0
assign CASDIN_in[32] = (CASDIN[32] !== 1'bz) && CASDIN_delay[32]; // rv 0
assign CASDIN_in[33] = (CASDIN[33] !== 1'bz) && CASDIN_delay[33]; // rv 0
assign CASDIN_in[34] = (CASDIN[34] !== 1'bz) && CASDIN_delay[34]; // rv 0
assign CASDIN_in[35] = (CASDIN[35] !== 1'bz) && CASDIN_delay[35]; // rv 0
assign CASDIN_in[36] = (CASDIN[36] !== 1'bz) && CASDIN_delay[36]; // rv 0
assign CASDIN_in[37] = (CASDIN[37] !== 1'bz) && CASDIN_delay[37]; // rv 0
assign CASDIN_in[38] = (CASDIN[38] !== 1'bz) && CASDIN_delay[38]; // rv 0
assign CASDIN_in[39] = (CASDIN[39] !== 1'bz) && CASDIN_delay[39]; // rv 0
assign CASDIN_in[3] = (CASDIN[3] !== 1'bz) && CASDIN_delay[3]; // rv 0
assign CASDIN_in[40] = (CASDIN[40] !== 1'bz) && CASDIN_delay[40]; // rv 0
assign CASDIN_in[41] = (CASDIN[41] !== 1'bz) && CASDIN_delay[41]; // rv 0
assign CASDIN_in[42] = (CASDIN[42] !== 1'bz) && CASDIN_delay[42]; // rv 0
assign CASDIN_in[43] = (CASDIN[43] !== 1'bz) && CASDIN_delay[43]; // rv 0
assign CASDIN_in[44] = (CASDIN[44] !== 1'bz) && CASDIN_delay[44]; // rv 0
assign CASDIN_in[45] = (CASDIN[45] !== 1'bz) && CASDIN_delay[45]; // rv 0
assign CASDIN_in[46] = (CASDIN[46] !== 1'bz) && CASDIN_delay[46]; // rv 0
assign CASDIN_in[47] = (CASDIN[47] !== 1'bz) && CASDIN_delay[47]; // rv 0
assign CASDIN_in[48] = (CASDIN[48] !== 1'bz) && CASDIN_delay[48]; // rv 0
assign CASDIN_in[49] = (CASDIN[49] !== 1'bz) && CASDIN_delay[49]; // rv 0
assign CASDIN_in[4] = (CASDIN[4] !== 1'bz) && CASDIN_delay[4]; // rv 0
assign CASDIN_in[50] = (CASDIN[50] !== 1'bz) && CASDIN_delay[50]; // rv 0
assign CASDIN_in[51] = (CASDIN[51] !== 1'bz) && CASDIN_delay[51]; // rv 0
assign CASDIN_in[52] = (CASDIN[52] !== 1'bz) && CASDIN_delay[52]; // rv 0
assign CASDIN_in[53] = (CASDIN[53] !== 1'bz) && CASDIN_delay[53]; // rv 0
assign CASDIN_in[54] = (CASDIN[54] !== 1'bz) && CASDIN_delay[54]; // rv 0
assign CASDIN_in[55] = (CASDIN[55] !== 1'bz) && CASDIN_delay[55]; // rv 0
assign CASDIN_in[56] = (CASDIN[56] !== 1'bz) && CASDIN_delay[56]; // rv 0
assign CASDIN_in[57] = (CASDIN[57] !== 1'bz) && CASDIN_delay[57]; // rv 0
assign CASDIN_in[58] = (CASDIN[58] !== 1'bz) && CASDIN_delay[58]; // rv 0
assign CASDIN_in[59] = (CASDIN[59] !== 1'bz) && CASDIN_delay[59]; // rv 0
assign CASDIN_in[5] = (CASDIN[5] !== 1'bz) && CASDIN_delay[5]; // rv 0
assign CASDIN_in[60] = (CASDIN[60] !== 1'bz) && CASDIN_delay[60]; // rv 0
assign CASDIN_in[61] = (CASDIN[61] !== 1'bz) && CASDIN_delay[61]; // rv 0
assign CASDIN_in[62] = (CASDIN[62] !== 1'bz) && CASDIN_delay[62]; // rv 0
assign CASDIN_in[63] = (CASDIN[63] !== 1'bz) && CASDIN_delay[63]; // rv 0
assign CASDIN_in[6] = (CASDIN[6] !== 1'bz) && CASDIN_delay[6]; // rv 0
assign CASDIN_in[7] = (CASDIN[7] !== 1'bz) && CASDIN_delay[7]; // rv 0
assign CASDIN_in[8] = (CASDIN[8] !== 1'bz) && CASDIN_delay[8]; // rv 0
assign CASDIN_in[9] = (CASDIN[9] !== 1'bz) && CASDIN_delay[9]; // rv 0
assign CASDOMUXEN_in = (CASDOMUXEN === 1'bz) || CASDOMUXEN_delay; // rv 1
assign CASDOMUX_in = (CASDOMUX !== 1'bz) && CASDOMUX_delay; // rv 0
assign CASNXTRDEN_in = (CASNXTRDEN !== 1'bz) && CASNXTRDEN_delay; // rv 0
assign CASOREGIMUXEN_in = (CASOREGIMUXEN === 1'bz) || CASOREGIMUXEN_delay; // rv 1
assign CASOREGIMUX_in = (CASOREGIMUX !== 1'bz) && CASOREGIMUX_delay; // rv 0
assign CASPRVEMPTY_in = (CASPRVEMPTY !== 1'bz) && CASPRVEMPTY_delay; // rv 0
always @ (*) DINP_in = DINP_delay;
always @ (*) DIN_in = DIN_delay;
assign INJECTDBITERR_in = (INJECTDBITERR !== 1'bz) && INJECTDBITERR_delay; // rv 0
assign INJECTSBITERR_in = (INJECTSBITERR !== 1'bz) && INJECTSBITERR_delay; // rv 0
assign RDCLK_in = (RDCLK !== 1'bz) && (RDCLK_delay ^ IS_RDCLK_INVERTED_BIN); // rv 0
assign RDEN_in = (RDEN !== 1'bz) && (RDEN_delay ^ IS_RDEN_INVERTED_BIN); // rv 0
assign REGCE_in = (REGCE === 1'bz) || REGCE_delay; // rv 1
assign RSTREG_in = (RSTREG !== 1'bz) && (RSTREG_delay ^ IS_RSTREG_INVERTED_BIN); // rv 0
assign RST_in = (RST !== 1'bz) && (RST_delay ^ IS_RST_INVERTED_BIN); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0
assign WRCLK_in = (WRCLK !== 1'bz) && (WRCLK_delay ^ IS_WRCLK_INVERTED_BIN); // rv 0
assign WREN_in = (WREN !== 1'bz) && (WREN_delay ^ IS_WREN_INVERTED_BIN); // rv 0
`else
assign CASDINP_in[0] = (CASDINP[0] !== 1'bz) && CASDINP[0]; // rv 0
assign CASDINP_in[1] = (CASDINP[1] !== 1'bz) && CASDINP[1]; // rv 0
assign CASDINP_in[2] = (CASDINP[2] !== 1'bz) && CASDINP[2]; // rv 0
assign CASDINP_in[3] = (CASDINP[3] !== 1'bz) && CASDINP[3]; // rv 0
assign CASDINP_in[4] = (CASDINP[4] !== 1'bz) && CASDINP[4]; // rv 0
assign CASDINP_in[5] = (CASDINP[5] !== 1'bz) && CASDINP[5]; // rv 0
assign CASDINP_in[6] = (CASDINP[6] !== 1'bz) && CASDINP[6]; // rv 0
assign CASDINP_in[7] = (CASDINP[7] !== 1'bz) && CASDINP[7]; // rv 0
assign CASDIN_in[0] = (CASDIN[0] !== 1'bz) && CASDIN[0]; // rv 0
assign CASDIN_in[10] = (CASDIN[10] !== 1'bz) && CASDIN[10]; // rv 0
assign CASDIN_in[11] = (CASDIN[11] !== 1'bz) && CASDIN[11]; // rv 0
assign CASDIN_in[12] = (CASDIN[12] !== 1'bz) && CASDIN[12]; // rv 0
assign CASDIN_in[13] = (CASDIN[13] !== 1'bz) && CASDIN[13]; // rv 0
assign CASDIN_in[14] = (CASDIN[14] !== 1'bz) && CASDIN[14]; // rv 0
assign CASDIN_in[15] = (CASDIN[15] !== 1'bz) && CASDIN[15]; // rv 0
assign CASDIN_in[16] = (CASDIN[16] !== 1'bz) && CASDIN[16]; // rv 0
assign CASDIN_in[17] = (CASDIN[17] !== 1'bz) && CASDIN[17]; // rv 0
assign CASDIN_in[18] = (CASDIN[18] !== 1'bz) && CASDIN[18]; // rv 0
assign CASDIN_in[19] = (CASDIN[19] !== 1'bz) && CASDIN[19]; // rv 0
assign CASDIN_in[1] = (CASDIN[1] !== 1'bz) && CASDIN[1]; // rv 0
assign CASDIN_in[20] = (CASDIN[20] !== 1'bz) && CASDIN[20]; // rv 0
assign CASDIN_in[21] = (CASDIN[21] !== 1'bz) && CASDIN[21]; // rv 0
assign CASDIN_in[22] = (CASDIN[22] !== 1'bz) && CASDIN[22]; // rv 0
assign CASDIN_in[23] = (CASDIN[23] !== 1'bz) && CASDIN[23]; // rv 0
assign CASDIN_in[24] = (CASDIN[24] !== 1'bz) && CASDIN[24]; // rv 0
assign CASDIN_in[25] = (CASDIN[25] !== 1'bz) && CASDIN[25]; // rv 0
assign CASDIN_in[26] = (CASDIN[26] !== 1'bz) && CASDIN[26]; // rv 0
assign CASDIN_in[27] = (CASDIN[27] !== 1'bz) && CASDIN[27]; // rv 0
assign CASDIN_in[28] = (CASDIN[28] !== 1'bz) && CASDIN[28]; // rv 0
assign CASDIN_in[29] = (CASDIN[29] !== 1'bz) && CASDIN[29]; // rv 0
assign CASDIN_in[2] = (CASDIN[2] !== 1'bz) && CASDIN[2]; // rv 0
assign CASDIN_in[30] = (CASDIN[30] !== 1'bz) && CASDIN[30]; // rv 0
assign CASDIN_in[31] = (CASDIN[31] !== 1'bz) && CASDIN[31]; // rv 0
assign CASDIN_in[32] = (CASDIN[32] !== 1'bz) && CASDIN[32]; // rv 0
assign CASDIN_in[33] = (CASDIN[33] !== 1'bz) && CASDIN[33]; // rv 0
assign CASDIN_in[34] = (CASDIN[34] !== 1'bz) && CASDIN[34]; // rv 0
assign CASDIN_in[35] = (CASDIN[35] !== 1'bz) && CASDIN[35]; // rv 0
assign CASDIN_in[36] = (CASDIN[36] !== 1'bz) && CASDIN[36]; // rv 0
assign CASDIN_in[37] = (CASDIN[37] !== 1'bz) && CASDIN[37]; // rv 0
assign CASDIN_in[38] = (CASDIN[38] !== 1'bz) && CASDIN[38]; // rv 0
assign CASDIN_in[39] = (CASDIN[39] !== 1'bz) && CASDIN[39]; // rv 0
assign CASDIN_in[3] = (CASDIN[3] !== 1'bz) && CASDIN[3]; // rv 0
assign CASDIN_in[40] = (CASDIN[40] !== 1'bz) && CASDIN[40]; // rv 0
assign CASDIN_in[41] = (CASDIN[41] !== 1'bz) && CASDIN[41]; // rv 0
assign CASDIN_in[42] = (CASDIN[42] !== 1'bz) && CASDIN[42]; // rv 0
assign CASDIN_in[43] = (CASDIN[43] !== 1'bz) && CASDIN[43]; // rv 0
assign CASDIN_in[44] = (CASDIN[44] !== 1'bz) && CASDIN[44]; // rv 0
assign CASDIN_in[45] = (CASDIN[45] !== 1'bz) && CASDIN[45]; // rv 0
assign CASDIN_in[46] = (CASDIN[46] !== 1'bz) && CASDIN[46]; // rv 0
assign CASDIN_in[47] = (CASDIN[47] !== 1'bz) && CASDIN[47]; // rv 0
assign CASDIN_in[48] = (CASDIN[48] !== 1'bz) && CASDIN[48]; // rv 0
assign CASDIN_in[49] = (CASDIN[49] !== 1'bz) && CASDIN[49]; // rv 0
assign CASDIN_in[4] = (CASDIN[4] !== 1'bz) && CASDIN[4]; // rv 0
assign CASDIN_in[50] = (CASDIN[50] !== 1'bz) && CASDIN[50]; // rv 0
assign CASDIN_in[51] = (CASDIN[51] !== 1'bz) && CASDIN[51]; // rv 0
assign CASDIN_in[52] = (CASDIN[52] !== 1'bz) && CASDIN[52]; // rv 0
assign CASDIN_in[53] = (CASDIN[53] !== 1'bz) && CASDIN[53]; // rv 0
assign CASDIN_in[54] = (CASDIN[54] !== 1'bz) && CASDIN[54]; // rv 0
assign CASDIN_in[55] = (CASDIN[55] !== 1'bz) && CASDIN[55]; // rv 0
assign CASDIN_in[56] = (CASDIN[56] !== 1'bz) && CASDIN[56]; // rv 0
assign CASDIN_in[57] = (CASDIN[57] !== 1'bz) && CASDIN[57]; // rv 0
assign CASDIN_in[58] = (CASDIN[58] !== 1'bz) && CASDIN[58]; // rv 0
assign CASDIN_in[59] = (CASDIN[59] !== 1'bz) && CASDIN[59]; // rv 0
assign CASDIN_in[5] = (CASDIN[5] !== 1'bz) && CASDIN[5]; // rv 0
assign CASDIN_in[60] = (CASDIN[60] !== 1'bz) && CASDIN[60]; // rv 0
assign CASDIN_in[61] = (CASDIN[61] !== 1'bz) && CASDIN[61]; // rv 0
assign CASDIN_in[62] = (CASDIN[62] !== 1'bz) && CASDIN[62]; // rv 0
assign CASDIN_in[63] = (CASDIN[63] !== 1'bz) && CASDIN[63]; // rv 0
assign CASDIN_in[6] = (CASDIN[6] !== 1'bz) && CASDIN[6]; // rv 0
assign CASDIN_in[7] = (CASDIN[7] !== 1'bz) && CASDIN[7]; // rv 0
assign CASDIN_in[8] = (CASDIN[8] !== 1'bz) && CASDIN[8]; // rv 0
assign CASDIN_in[9] = (CASDIN[9] !== 1'bz) && CASDIN[9]; // rv 0
assign CASDOMUXEN_in = (CASDOMUXEN === 1'bz) || CASDOMUXEN; // rv 1
assign CASDOMUX_in = (CASDOMUX !== 1'bz) && CASDOMUX; // rv 0
assign CASNXTRDEN_in = (CASNXTRDEN !== 1'bz) && CASNXTRDEN; // rv 0
assign CASOREGIMUXEN_in = (CASOREGIMUXEN === 1'bz) || CASOREGIMUXEN; // rv 1
assign CASOREGIMUX_in = (CASOREGIMUX !== 1'bz) && CASOREGIMUX; // rv 0
assign CASPRVEMPTY_in = (CASPRVEMPTY !== 1'bz) && CASPRVEMPTY; // rv 0
always @ (*) DINP_in = DINP;
always @ (*) DIN_in = DIN;
assign INJECTDBITERR_in = (INJECTDBITERR !== 1'bz) && INJECTDBITERR; // rv 0
assign INJECTSBITERR_in = (INJECTSBITERR !== 1'bz) && INJECTSBITERR; // rv 0
assign RDCLK_in = (RDCLK !== 1'bz) && (RDCLK ^ IS_RDCLK_INVERTED_BIN); // rv 0
assign RDEN_in = (RDEN !== 1'bz) && (RDEN ^ IS_RDEN_INVERTED_BIN); // rv 0
assign REGCE_in = (REGCE === 1'bz) || REGCE; // rv 1
assign RSTREG_in = (RSTREG !== 1'bz) && (RSTREG ^ IS_RSTREG_INVERTED_BIN); // rv 0
assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_BIN); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0
assign WRCLK_in = (WRCLK !== 1'bz) && (WRCLK ^ IS_WRCLK_INVERTED_BIN); // rv 0
assign WREN_in = (WREN !== 1'bz) && (WREN ^ IS_WREN_INVERTED_BIN); // rv 0
`endif
// internal variables, signals, busses
localparam integer ADDR_WIDTH = 15;
localparam integer INIT_WIDTH = 72;
localparam integer D_WIDTH = 64;
localparam integer DP_WIDTH = 8;
localparam mem_width = 1;
localparam memp_width = 1;
localparam mem_size = 32768;
localparam mem_depth = mem_size;
localparam memp_depth = mem_size/8;
localparam mem_pad = 64;
localparam memp_pad = 8;
localparam encode = 1'b1;
localparam decode = 1'b0;
integer i=0;
integer j=0;
integer k=0;
integer ra=0;
integer raa=0;
integer raw=0;
integer wb=0;
integer rd_loops_a = 1;
integer wr_loops_b = 1;
localparam max_rd_loops = D_WIDTH;
localparam max_wr_loops = D_WIDTH;
integer rdcount_adj = 0;
integer wrcount_adj = 0;
integer wr_adj = 0;
wire RDEN_int;
wire RDEN_lat;
wire WREN_int;
wire WREN_lat;
wire RDEN_reg;
reg fill_lat=0;
reg fill_reg=0;
wire WREN_ecc;
wire RDEN_ecc;
reg fill_ecc=0;
wire SLEEP_A_int;
wire SLEEP_B_int;
reg [1:0] SLEEP_A_reg = 2'b0;
reg [1:0] SLEEP_B_reg = 2'b0;
wire RSTREG_A_int;
wire REGCE_A_int;
wire [7:0] DINP_int;
reg CASDOMUXA_reg = 1'b0;
reg CASOREGIMUXA_reg = 1'b0;
wire INJECTDBITERR_int;
wire INJECTSBITERR_int;
wire prog_empty;
reg prog_empty_cc = 1;
reg ram_full_c = 0;
wire ram_empty;
reg ram_empty_i = 1;
reg ram_empty_c = 1;
reg o_lat_empty = 1;
reg o_reg_empty = 1;
reg o_ecc_empty = 1;
wire [1:0] output_stages;
reg [6:0] error_bit = 7'b0;
reg [DP_WIDTH-1:0] eccparity_reg = 8'h00;
wire o_stages_full;
wire o_stages_empty;
reg o_stages_full_sync=0;
reg o_stages_full_sync1=0;
reg o_stages_full_sync2=0;
reg o_stages_full_sync3=0;
wire prog_full;
reg prog_full_reg = 1'b0;
reg rderr_reg = 1'b0;
reg wrerr_reg = 1'b0;
wire [INIT_WIDTH-1:0] INIT_A_int;
wire [INIT_WIDTH-1:0] SRVAL_A_int;
wire mem_wr_en_b;
reg mem_wr_en_b_wf = 1'b0;
wire [D_WIDTH-1:0] mem_we_b;
wire [DP_WIDTH-1:0] memp_we_b;
wire [D_WIDTH-1:0] mem_rm_douta;
wire [DP_WIDTH-1:0] memp_rm_douta;
wire mem_rd_en_a;
wire mem_rst_a;
reg mem_is_rst_a = 1'b0;
reg first_read = 1'b0;
reg rdcount_en = 1'b0;
reg mem [0 : mem_depth+mem_pad-1];
reg [D_WIDTH-1 : 0] ram_rd_a;
reg [D_WIDTH-1 : 0] mem_wr_b;
reg wr_b_event = 1'b0;
reg [D_WIDTH-1 : 0] mem_rd_b_rf;
reg [D_WIDTH-1 : 0] mem_rd_b_wf;
reg [D_WIDTH-1 : 0] mem_a_reg;
reg [D_WIDTH-1 : 0] mem_a_reg_mux;
reg [D_WIDTH-1 : 0] mem_a_lat;
reg [D_WIDTH-1 : 0] mem_a_pipe;
reg memp [0 : memp_depth+memp_pad-1];
reg [DP_WIDTH-1 : 0] ramp_rd_a;
wire [DP_WIDTH-1 : 0] memp_wr_b;
reg [DP_WIDTH-1 : 0] memp_rd_b_rf;
reg [DP_WIDTH-1 : 0] memp_rd_b_wf;
reg [DP_WIDTH-1 : 0] memp_a_reg;
reg [DP_WIDTH-1 : 0] memp_a_reg_mux;
reg [DP_WIDTH-1 : 0] memp_a_lat;
reg [DP_WIDTH-1 : 0] memp_a_out;
reg [DP_WIDTH-1 : 0] memp_a_pipe;
wire dbit_int;
wire sbit_int;
reg dbit_lat = 0;
reg sbit_lat = 0;
reg dbit_pipe = 0;
reg sbit_pipe = 0;
reg dbit_reg = 0;
reg sbit_reg = 0;
reg dbit_ecc;
reg sbit_ecc;
wire [ADDR_WIDTH-1:0] wr_addr_b_mask;
reg [ADDR_WIDTH-1:0] rd_addr_a = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b = 0;
reg [ADDR_WIDTH-1:0] rd_addr_a_wr = 0;
reg [ADDR_WIDTH-1:0] wr_addr_b_rd = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr2 = 0;
reg [ADDR_WIDTH-1:0] rd_addr_sync_wr1 = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd2 = 0;
reg [ADDR_WIDTH-1:0] wr_addr_sync_rd1 = 0;
wire [ADDR_WIDTH-1:0] rd_addr_wr;
wire [ADDR_WIDTH-1:0] next_rd_addr_wr;
wire [ADDR_WIDTH-1:0] wr_addr_rd;
wire [ADDR_WIDTH-1:0] next_wr_addr_rd;
wire [ADDR_WIDTH:0] wr_simple_raw;
// wire [ADDR_WIDTH:0] rd_simple_raw;
wire [ADDR_WIDTH-1:0] wr_simple;
wire [ADDR_WIDTH:0] rd_simple;
reg [ADDR_WIDTH-1:0] rd_simple_cc = 0;
reg [ADDR_WIDTH-1:0] wr_simple_sync = 0;
reg [ADDR_WIDTH-1:0] rd_simple_sync = 0;
//reset logic variables
reg RST_in_p1 = 1'b0;
reg WRRST_int = 1'b0;
reg RST_sync = 1'b0;
reg WRRST_done = 1'b0;
reg WRRST_done1 = 1'b0;
reg WRRST_done2 = 1'b0;
wire RDRST_int;
reg RDRST_done = 1'b0;
reg RDRST_done1 = 1'b0;
reg RDRST_done2 = 1'b0;
wire WRRST_done_wr;
reg WRRST_in_sync_rd = 1'b0;
reg WRRST_in_sync_rd1 = 1'b0;
reg WRRSTBUSY_dly = 1'b0;
reg WRRSTBUSY_dly1 = 1'b0;
reg RDRSTBUSY_dly = 1'b0;
reg RDRSTBUSY_dly1 = 1'b0;
reg RDRSTBUSY_dly2 = 1'b0;
reg [7:0] synd_wr;
reg [7:0] synd_rd;
reg [7:0] synd_ecc;
reg sdp_mode = 1'b1;
reg sdp_mode_wr = 1'b1;
reg sdp_mode_rd = 1'b1;
// full/empty variables
wire [ADDR_WIDTH-1:0] full_count;
wire [ADDR_WIDTH-1:0] next_full_count;
wire [ADDR_WIDTH-1:0] full_count_masked;
wire [8:0] m_full;
wire [8:0] m_full_raw;
wire [5:0] n_empty;
wire [5:0] unr_ratio;
wire [ADDR_WIDTH+1:0] prog_full_val;
wire [ADDR_WIDTH+1:0] prog_empty_val;
reg ram_full_i;
wire ram_one_from_full_i;
wire ram_two_from_full_i;
wire ram_one_from_full;
wire ram_two_from_full;
wire ram_one_read_from_not_full;
wire [ADDR_WIDTH-1:0] empty_count;
wire [ADDR_WIDTH-1:0] next_empty_count;
wire ram_one_read_from_empty_i;
wire ram_one_read_from_empty;
wire ram_one_write_from_not_empty;
wire ram_one_write_from_not_empty_i;
reg en_clk_sync = 1'b0;
// define tasks, functions
function [7:0] fn_ecc (
input encode,
input [63:0] d_i,
input [7:0] dp_i
);
reg ecc_7;
begin
fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^
d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^
d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^
d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^
d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^
d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^
d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63];
fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^
d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^
d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^
d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^
d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^
d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^
d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63];
fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^
d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^
d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^
d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^
d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^
d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^
d_i[62] ^ d_i[63];
ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^
d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^
d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^
d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^
d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^
d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^
d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^
d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^
d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^
d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^
d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^
d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^
d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
if (encode) begin
fn_ecc[7] = ecc_7 ^
fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^
fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6];
end
else begin
fn_ecc[7] = ecc_7 ^
dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^
dp_i[4] ^ dp_i[5] ^ dp_i[6];
end
end
endfunction // fn_ecc
function [71:0] fn_cor_bit (
input [6:0] error_bit,
input [63:0] d_i,
input [7:0] dp_i
);
reg [71:0] cor_int;
begin
cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4],
d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0],
dp_i[7]};
cor_int[error_bit] = ~cor_int[error_bit];
fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16],
cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65],
cor_int[63:33], cor_int[31:17], cor_int[15:9],
cor_int[7:5], cor_int[3]};
end
endfunction // fn_cor_bit
reg cas_warning = 1'b0;
task is_cas_connected;
integer i;
begin
for (i=0;i<=63;i=i+1) begin
if (CASDIN[i] === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDIN[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
for (i=0;i<=7;i=i+1) begin
if (CASDINP[i] === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDINP[%2d] signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME, i);
end
end
if (CASDOMUX === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDOMUX signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASDOMUXEN === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASDOMUXEN signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASNXTRDEN === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASNXTRDEN signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASOREGIMUX === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASOREGIMUX signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
if (CASOREGIMUXEN === 1'bz) begin
cas_warning = 1'b1;
$display("Warning: [Unisim %s-130] CASOREGIMUXEN signal is unconnected in CASCADE mode Instance: %m", MODULE_NAME);
end
end
endtask // is_cas_connected
assign RDEN_int = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ?
CASNXTRDEN_in && ~SLEEP_A_int : RDEN_in;
assign WREN_int = ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ?
~(CASPRVEMPTY_in || FULL_out || SLEEP_B_int) : WREN_in;
assign DINP_int = ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ? CASDINP_in : DINP_in;
assign mem_wr_en_b = WREN_int && ~FULL_out && ~WRRSTBUSY_out;
assign mem_rd_en_a = (RDEN_int ||
((fill_lat || fill_reg || fill_ecc) && ~SLEEP_A_int)) &&
~ram_empty && ~RDRST_int;
assign INJECTDBITERR_int = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) ? 1'b0 :
INJECTDBITERR_in;
assign INJECTSBITERR_int = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) ? 1'b0 :
INJECTSBITERR_in || INJECTDBITERR_in;
wire [35:0] bit_err_pat;
assign bit_err_pat = INJECTDBITERR_int ? 36'h400000004 : INJECTSBITERR_int ? 36'h000000004 : 36'h0;
always @ (*) begin
if (INJECTDBITERR_int || INJECTSBITERR_int) begin
if ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE))
mem_wr_b = CASDIN_in ^ {bit_err_pat, 28'h0};
else
mem_wr_b = DIN_in ^ {bit_err_pat, 28'h0};
end
else begin
if ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE))
mem_wr_b = CASDIN_in;
else
mem_wr_b = DIN_in;
end
end
assign memp_wr_b = (EN_ECC_WRITE_BIN == EN_ECC_WRITE_TRUE) ? synd_wr : DINP_int;
//victor DRC
reg sleep_is_asserted;
reg sleep_is_deasserted;
reg RDEN_p1;
reg RDEN_p2;
reg RDEN_p3;
reg RDEN_p4;
reg RDEN_p5;
reg RDEN_p6;
reg WREN_p1;
reg WREN_p2;
reg WREN_p3;
reg SLEEPA_p1;
reg SLEEPA_p2;
reg SLEEPB_p1;
reg SLEEPB_p2;
always @(SLEEP_in) begin
sleep_is_asserted <= 1'b0;
sleep_is_deasserted <= 1'b0;
if (SLEEP_in == 1'b1)
sleep_is_asserted <= 1'b1;
else if (SLEEP_in == 1'b0)
sleep_is_deasserted <= 1'b1;
end
//victor drc #5
always @(posedge RDCLK_in) begin
if (sleep_is_asserted && RDEN_in) begin
$display("Error: [Unisim %s-23] DRC : RDEN must be LOW in the clock cycle when SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
always @(posedge WRCLK_in) begin
if (sleep_is_asserted && WREN_in) begin
$display("Error: [Unisim %s-23] DRC : WREN must be LOW in the clock cycle when SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
always @(posedge RDCLK_in) begin
if (glblGSR) begin
RDEN_p1 <= 1'b0;
RDEN_p2 <= 1'b0;
RDEN_p3 <= 1'b0;
RDEN_p4 <= 1'b0;
RDEN_p5 <= 1'b0;
RDEN_p6 <= 1'b0;
end
else begin
RDEN_p1 <= RDEN_in;
RDEN_p2 <= RDEN_p1;
RDEN_p3 <= RDEN_p2;
RDEN_p4 <= RDEN_p3;
RDEN_p5 <= RDEN_p4;
RDEN_p6 <= RDEN_p5;
end
end
always @(posedge WRCLK_in) begin
if (glblGSR) begin
WREN_p1 <= 1'b0;
WREN_p2 <= 1'b0;
WREN_p3 <= 1'b0;
end
else begin
WREN_p1 <= WREN_in;
WREN_p2 <= WREN_p1;
WREN_p3 <= WREN_p2;
end
end
always @(posedge RDCLK_in or posedge WRCLK_in) begin
if (FIRST_WORD_FALL_THROUGH_REG == "FALSE") begin
if (sleep_is_asserted && RDEN_p1)
$display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, RDEN must be LOW at least one RDCLK cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
if (sleep_is_asserted && WREN_p1)
$display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, WREN must be LOW at least one WRCLK cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
always @(posedge RDCLK_in or posedge WRCLK_in) begin
if ((FIRST_WORD_FALL_THROUGH_REG == "TRUE") && (CLOCK_DOMAINS_REG == "COMMON")) begin
if (sleep_is_asserted && RDEN_p1)
$display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, RDEN must be LOW at least one cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
if (sleep_is_asserted && WREN_p3)
$display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, WREN must be LOW at least three cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
always @(posedge RDCLK_in or posedge WRCLK_in) begin
if ((FIRST_WORD_FALL_THROUGH_REG == "TRUE") && (CLOCK_DOMAINS_REG == "INDEPENDENT")) begin
if (sleep_is_asserted && RDEN_p1)
$display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, RDEN must be LOW at least one cycle before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
if (sleep_is_asserted && WREN_p3 && RDEN_p6)
$display("Error: [Unisim %s-23] DRC : When FWFT = FALSE, WREN must be LOW at least one WRCLK plus six RDCLK cycles before SLEEP is going from LOW to HIGH. Instance: %m", MODULE_NAME);
end
end
//victor drc #6
always @(posedge RDCLK_in) begin
if (glblGSR) begin
SLEEPA_p1 <= 1'b0;
SLEEPA_p2 <= 1'b0;
end
else begin
SLEEPA_p1 <= SLEEP_in;
SLEEPA_p2 <= SLEEPA_p1;
end
end
always @(posedge WRCLK_in) begin
if (glblGSR) begin
SLEEPB_p1 <= 1'b0;
SLEEPB_p2 <= 1'b0;
end
else begin
SLEEPB_p1 <= SLEEP_in;
SLEEPB_p2 <= SLEEPB_p1;
end
end
always @(RDEN_in) begin
if (RDEN_in && SLEEPA_p2)
$display("Error: [Unisim %s-23] DRC : RDEN can be asserted at least 2 cycles RDCLK after SLEEP signal has been de-asserted. Instance: %m", MODULE_NAME);
end
always @(WREN_in) begin
if (WREN_in && SLEEPB_p2)
$display("Error: [Unisim %s-23] DRC : WREN can be asserted at least 2 cycles WRCLK after SLEEP signal has been de-asserted. Instance: %m", MODULE_NAME);
end
assign CASCADE_ORDER_BIN =
(CASCADE_ORDER_REG == "NONE") ? CASCADE_ORDER_NONE :
(CASCADE_ORDER_REG == "FIRST") ? CASCADE_ORDER_FIRST :
(CASCADE_ORDER_REG == "LAST") ? CASCADE_ORDER_LAST :
(CASCADE_ORDER_REG == "MIDDLE") ? CASCADE_ORDER_MIDDLE :
(CASCADE_ORDER_REG == "PARALLEL") ? CASCADE_ORDER_PARALLEL :
CASCADE_ORDER_NONE;
assign CLOCK_DOMAINS_BIN =
(CLOCK_DOMAINS_REG == "INDEPENDENT") ? CLOCK_DOMAINS_INDEPENDENT :
(CLOCK_DOMAINS_REG == "COMMON") ? CLOCK_DOMAINS_COMMON :
CLOCK_DOMAINS_INDEPENDENT;
assign EN_ECC_PIPE_BIN =
(EN_ECC_PIPE_REG == "FALSE") ? EN_ECC_PIPE_FALSE :
(EN_ECC_PIPE_REG == "TRUE") ? EN_ECC_PIPE_TRUE :
EN_ECC_PIPE_FALSE;
assign EN_ECC_READ_BIN =
(EN_ECC_READ_REG == "FALSE") ? EN_ECC_READ_FALSE :
(EN_ECC_READ_REG == "TRUE") ? EN_ECC_READ_TRUE :
EN_ECC_READ_FALSE;
assign EN_ECC_WRITE_BIN =
(EN_ECC_WRITE_REG == "FALSE") ? EN_ECC_WRITE_FALSE :
(EN_ECC_WRITE_REG == "TRUE") ? EN_ECC_WRITE_TRUE :
EN_ECC_WRITE_FALSE;
assign FIRST_WORD_FALL_THROUGH_BIN =
(FIRST_WORD_FALL_THROUGH_REG == "FALSE") ? FIRST_WORD_FALL_THROUGH_FALSE :
(FIRST_WORD_FALL_THROUGH_REG == "TRUE") ? FIRST_WORD_FALL_THROUGH_TRUE :
FIRST_WORD_FALL_THROUGH_FALSE;
assign INIT_BIN = INIT_REG;
assign IS_RDCLK_INVERTED_BIN = IS_RDCLK_INVERTED_REG;
assign IS_RDEN_INVERTED_BIN = IS_RDEN_INVERTED_REG;
assign IS_RSTREG_INVERTED_BIN = IS_RSTREG_INVERTED_REG;
assign IS_RST_INVERTED_BIN = IS_RST_INVERTED_REG;
assign IS_WRCLK_INVERTED_BIN = IS_WRCLK_INVERTED_REG;
assign IS_WREN_INVERTED_BIN = IS_WREN_INVERTED_REG;
assign PROG_EMPTY_THRESH_BIN = PROG_EMPTY_THRESH_REG;
assign PROG_FULL_THRESH_BIN = PROG_FULL_THRESH_REG;
assign RDCOUNT_TYPE_BIN =
(RDCOUNT_TYPE_REG == "RAW_PNTR") ? RDCOUNT_TYPE_RAW_PNTR :
(RDCOUNT_TYPE_REG == "EXTENDED_DATACOUNT") ? RDCOUNT_TYPE_EXTENDED_DATACOUNT :
(RDCOUNT_TYPE_REG == "SIMPLE_DATACOUNT") ? RDCOUNT_TYPE_SIMPLE_DATACOUNT :
(RDCOUNT_TYPE_REG == "SYNC_PNTR") ? RDCOUNT_TYPE_SYNC_PNTR :
RDCOUNT_TYPE_RAW_PNTR;
assign READ_WIDTH_BIN =
(READ_WIDTH_REG == 4) ? READ_WIDTH_4 :
(READ_WIDTH_REG == 9) ? READ_WIDTH_9 :
(READ_WIDTH_REG == 18) ? READ_WIDTH_18 :
(READ_WIDTH_REG == 36) ? READ_WIDTH_36 :
(READ_WIDTH_REG == 72) ? READ_WIDTH_72 :
READ_WIDTH_4;
assign REGISTER_MODE_BIN =
(REGISTER_MODE_REG == "UNREGISTERED") ? REGISTER_MODE_UNREGISTERED :
(REGISTER_MODE_REG == "DO_PIPELINED") ? REGISTER_MODE_DO_PIPELINED :
(REGISTER_MODE_REG == "REGISTERED") ? REGISTER_MODE_REGISTERED :
REGISTER_MODE_UNREGISTERED;
assign RSTREG_PRIORITY_BIN =
(RSTREG_PRIORITY_REG == "RSTREG") ? RSTREG_PRIORITY_RSTREG :
(RSTREG_PRIORITY_REG == "REGCE") ? RSTREG_PRIORITY_REGCE :
RSTREG_PRIORITY_RSTREG;
assign SLEEP_ASYNC_BIN =
(SLEEP_ASYNC_REG == "FALSE") ? SLEEP_ASYNC_FALSE :
(SLEEP_ASYNC_REG == "TRUE") ? SLEEP_ASYNC_TRUE :
SLEEP_ASYNC_FALSE;
assign SRVAL_BIN = SRVAL_REG;
assign WRCOUNT_TYPE_BIN =
(WRCOUNT_TYPE_REG == "RAW_PNTR") ? WRCOUNT_TYPE_RAW_PNTR :
(WRCOUNT_TYPE_REG == "EXTENDED_DATACOUNT") ? WRCOUNT_TYPE_EXTENDED_DATACOUNT :
(WRCOUNT_TYPE_REG == "SIMPLE_DATACOUNT") ? WRCOUNT_TYPE_SIMPLE_DATACOUNT :
(WRCOUNT_TYPE_REG == "SYNC_PNTR") ? WRCOUNT_TYPE_SYNC_PNTR :
WRCOUNT_TYPE_RAW_PNTR;
assign WRITE_WIDTH_BIN =
(WRITE_WIDTH_REG == 4) ? WRITE_WIDTH_4 :
(WRITE_WIDTH_REG == 9) ? WRITE_WIDTH_9 :
(WRITE_WIDTH_REG == 18) ? WRITE_WIDTH_18 :
(WRITE_WIDTH_REG == 36) ? WRITE_WIDTH_36 :
(WRITE_WIDTH_REG == 72) ? WRITE_WIDTH_72 :
WRITE_WIDTH_4;
initial begin
#1;
trig_attr = 1'b1;
#100;
trig_attr = 1'b0;
end
always @ (posedge trig_attr) begin
INIT_MEM <= #100 1'b1;
INIT_MEM <= #200 1'b0;
if ((attr_test == 1'b1) ||
((CASCADE_ORDER_REG != "NONE") &&
(CASCADE_ORDER_REG != "FIRST") &&
(CASCADE_ORDER_REG != "LAST") &&
(CASCADE_ORDER_REG != "MIDDLE") &&
(CASCADE_ORDER_REG != "PARALLEL"))) begin
$display("Error: [Unisim %s-101] CASCADE_ORDER attribute is set to %s. Legal values for this attribute are NONE, FIRST, LAST, MIDDLE or PARALLEL. Instance: %m", MODULE_NAME, CASCADE_ORDER_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLOCK_DOMAINS_REG != "INDEPENDENT") &&
(CLOCK_DOMAINS_REG != "COMMON"))) begin
$display("Error: [Unisim %s-103] CLOCK_DOMAINS attribute is set to %s. Legal values for this attribute are INDEPENDENT or COMMON. Instance: %m", MODULE_NAME, CLOCK_DOMAINS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_PIPE_REG != "FALSE") &&
(EN_ECC_PIPE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-108] EN_ECC_PIPE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_PIPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_READ_REG != "FALSE") &&
(EN_ECC_READ_REG != "TRUE"))) begin
$display("Error: [Unisim %s-109] EN_ECC_READ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_READ_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_WRITE_REG != "FALSE") &&
(EN_ECC_WRITE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-110] EN_ECC_WRITE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WRITE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FIRST_WORD_FALL_THROUGH_REG != "FALSE") &&
(FIRST_WORD_FALL_THROUGH_REG != "TRUE"))) begin
$display("Error: [Unisim %s-106] FIRST_WORD_FALL_THROUGH attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FIRST_WORD_FALL_THROUGH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PROG_EMPTY_THRESH_REG < 1) || (PROG_EMPTY_THRESH_REG > 8191))) begin
$display("Error: [Unisim %s-114] PROG_EMPTY_THRESH attribute is set to %d. Legal values for this attribute are 1 to 8191. Instance: %m", MODULE_NAME, PROG_EMPTY_THRESH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PROG_FULL_THRESH_REG < 1) || (PROG_FULL_THRESH_REG > 8191))) begin
$display("Error: [Unisim %s-115] PROG_FULL_THRESH attribute is set to %d. Legal values for this attribute are 1 to 8191. Instance: %m", MODULE_NAME, PROG_FULL_THRESH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RDCOUNT_TYPE_REG != "RAW_PNTR") &&
(RDCOUNT_TYPE_REG != "EXTENDED_DATACOUNT") &&
(RDCOUNT_TYPE_REG != "SIMPLE_DATACOUNT") &&
(RDCOUNT_TYPE_REG != "SYNC_PNTR"))) begin
$display("Error: [Unisim %s-116] RDCOUNT_TYPE attribute is set to %s. Legal values for this attribute are RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT or SYNC_PNTR. Instance: %m", MODULE_NAME, RDCOUNT_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((READ_WIDTH_REG != 4) &&
(READ_WIDTH_REG != 9) &&
(READ_WIDTH_REG != 18) &&
(READ_WIDTH_REG != 36) &&
(READ_WIDTH_REG != 72))) begin
$display("Error: [Unisim %s-117] READ_WIDTH attribute is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72. Instance: %m", MODULE_NAME, READ_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((REGISTER_MODE_REG != "UNREGISTERED") &&
(REGISTER_MODE_REG != "DO_PIPELINED") &&
(REGISTER_MODE_REG != "REGISTERED"))) begin
$display("Error: [Unisim %s-118] REGISTER_MODE attribute is set to %s. Legal values for this attribute are UNREGISTERED, DO_PIPELINED or REGISTERED. Instance: %m", MODULE_NAME, REGISTER_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RSTREG_PRIORITY_REG != "RSTREG") &&
(RSTREG_PRIORITY_REG != "REGCE"))) begin
$display("Error: [Unisim %s-119] RSTREG_PRIORITY attribute is set to %s. Legal values for this attribute are RSTREG or REGCE. Instance: %m", MODULE_NAME, RSTREG_PRIORITY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SLEEP_ASYNC_REG != "FALSE") &&
(SLEEP_ASYNC_REG != "TRUE"))) begin
$display("Error: [Unisim %s-273] SLEEP_ASYNC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SLEEP_ASYNC_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRCOUNT_TYPE_REG != "RAW_PNTR") &&
(WRCOUNT_TYPE_REG != "EXTENDED_DATACOUNT") &&
(WRCOUNT_TYPE_REG != "SIMPLE_DATACOUNT") &&
(WRCOUNT_TYPE_REG != "SYNC_PNTR"))) begin
$display("Error: [Unisim %s-122] WRCOUNT_TYPE attribute is set to %s. Legal values for this attribute are RAW_PNTR, EXTENDED_DATACOUNT, SIMPLE_DATACOUNT or SYNC_PNTR. Instance: %m", MODULE_NAME, WRCOUNT_TYPE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((WRITE_WIDTH_REG != 4) &&
(WRITE_WIDTH_REG != 9) &&
(WRITE_WIDTH_REG != 18) &&
(WRITE_WIDTH_REG != 36) &&
(WRITE_WIDTH_REG != 72))) begin
$display("Error: [Unisim %s-123] WRITE_WIDTH attribute is set to %d. Legal values for this attribute are 4, 9, 18, 36 or 72. Instance: %m", MODULE_NAME, WRITE_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(PROG_EMPTY_THRESH_REG < 1) ||
(PROG_EMPTY_THRESH_REG >= mem_depth/READ_WIDTH_BIN)) begin
$display("Error: [Unisim %s-124] PROG_EMPTY_THRESH is set to %d. When READ_WIDTH is set to %d PROG_EMPTY_THRESH must be greater than 0 and less than %d. Instance: %m", MODULE_NAME, PROG_EMPTY_THRESH_REG, READ_WIDTH_REG, mem_depth/READ_WIDTH_BIN);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(PROG_FULL_THRESH_REG < 1) ||
(PROG_FULL_THRESH_REG >= mem_depth/WRITE_WIDTH_BIN)) begin
$display("Error: [Unisim %s-125] PROG_FULL_THRESH is set to %d. When WRITE_WIDTH is set to %d PROG_FULL_THRESH must be greater than 0 and less than %d. Instance: %m", MODULE_NAME, PROG_FULL_THRESH_REG, WRITE_WIDTH_REG, mem_depth/WRITE_WIDTH_BIN);
attr_err = 1'b1;
end
if ((CASCADE_ORDER_REG == "LAST") ||
(CASCADE_ORDER_REG == "MIDDLE") ||
(CASCADE_ORDER_REG == "PARALLEL")) begin
is_cas_connected;
if (cas_warning) $display("Warning: [Unisim %s-126] CASCADE_ORDER attribute is set to %s and some or all of the CASCADE signals are unconnected. Simulation behavior may not match hardware under these circumstances. Please check that all CASCADE signals are properly connected. Instance: %m", MODULE_NAME, CASCADE_ORDER_REG);
end
if (attr_err == 1'b1) #100 $finish;
end
initial begin
INIT_MEM <= #100 1'b1;
INIT_MEM <= #200 1'b0;
end
assign output_stages =
((EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) &&
(REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) &&
(FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b11 :
((EN_ECC_PIPE_BIN != EN_ECC_PIPE_TRUE) &&
(REGISTER_MODE_BIN != REGISTER_MODE_REGISTERED) &&
(FIRST_WORD_FALL_THROUGH_BIN != FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b00 :
((EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) ^
(REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ^
(FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)) ? 2'b01 : 2'b10;
assign wr_addr_b_mask =
(WRITE_WIDTH_REG == 4) ? {{ADDR_WIDTH-6{1'b1}}, 6'h3c} :
(WRITE_WIDTH_REG == 9) ? {{ADDR_WIDTH-6{1'b1}}, 6'h38} :
(WRITE_WIDTH_REG == 18) ? {{ADDR_WIDTH-6{1'b1}}, 6'h30} :
(WRITE_WIDTH_REG == 36) ? {{ADDR_WIDTH-6{1'b1}}, 6'h20} :
(WRITE_WIDTH_REG == 72) ? {{ADDR_WIDTH-6{1'b1}}, 6'h00} :
{{ADDR_WIDTH-6{1'b1}}, 6'h3f};
always @(READ_WIDTH_BIN) rd_loops_a <= READ_WIDTH_BIN;
always @(WRITE_WIDTH_BIN) wr_loops_b <= WRITE_WIDTH_BIN;
always @ (posedge RDCLK_in) begin
if (glblGSR) begin
SLEEP_A_reg <= 2'b0;
end
else begin
SLEEP_A_reg <= {SLEEP_A_reg[0], SLEEP_in};
end
end
always @ (posedge WRCLK_in) begin
if (glblGSR) begin
SLEEP_B_reg <= 2'b0;
end
else begin
SLEEP_B_reg <= {SLEEP_B_reg[0], SLEEP_in};
end
end
assign SLEEP_A_int = SLEEP_A_reg[1] || SLEEP_A_reg[0] || SLEEP_in;
assign SLEEP_B_int = SLEEP_B_reg[1] || SLEEP_B_reg[0] || SLEEP_in;
assign REGCE_A_int = (REGISTER_MODE_BIN != REGISTER_MODE_DO_PIPELINED) ? RDEN_reg :
REGCE_in;
assign RSTREG_A_int = (REGISTER_MODE_BIN != REGISTER_MODE_DO_PIPELINED) ? RDRST_int :
(RSTREG_PRIORITY_BIN == RSTREG_PRIORITY_RSTREG) ? RSTREG_in :
(RSTREG_in && REGCE_in);
assign RDEN_lat = RDEN_int || ((fill_reg || fill_ecc || fill_lat) && ~SLEEP_A_int);
assign WREN_lat = mem_rd_en_a;
assign RDEN_ecc = (RDEN_int || fill_reg) && (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE);
assign WREN_ecc = (RDEN_int || fill_reg || fill_ecc) && ~o_lat_empty &&
(EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) && first_read;
assign RDEN_reg = RDEN_int || fill_reg ;
always @ (*) begin
if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg)
DOUT_out = CASDIN_in;
else if ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED))
DOUT_out = mem_a_reg ^ mem_rm_douta;
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE)
DOUT_out = mem_a_pipe ^ mem_rm_douta;
else
DOUT_out = mem_a_lat ^ mem_rm_douta;
end
always @ (*) begin
if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) && CASDOMUXA_reg)
DOUTP_out = CASDINP_in;
else if ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED))
DOUTP_out = memp_a_reg ^ memp_rm_douta;
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE)
DOUTP_out = memp_a_pipe ^ memp_rm_douta;
else
DOUTP_out = memp_a_lat ^ memp_rm_douta;
end
assign ECCPARITY_out = eccparity_reg;
always @ (*) begin
if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) dbit_ecc = dbit_pipe;
else dbit_ecc = dbit_lat;
end
always @ (*) begin
if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) sbit_ecc = sbit_pipe;
else sbit_ecc = sbit_lat;
end
assign DBITERR_out = ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) ? dbit_reg : dbit_ecc;
assign SBITERR_out = ((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(REGISTER_MODE_BIN == REGISTER_MODE_DO_PIPELINED)) ? sbit_reg : sbit_ecc;
assign INIT_A_int =
(READ_WIDTH_BIN <= READ_WIDTH_9) ? {{8{INIT_BIN[8]}}, {8{INIT_BIN[7:0]}}} :
(READ_WIDTH_BIN == READ_WIDTH_18) ? {{4{INIT_BIN[17:16]}}, {4{INIT_BIN[15:0]}}} :
(READ_WIDTH_BIN == READ_WIDTH_36) ? {{2{INIT_BIN[35:32]}}, {2{INIT_BIN[31:0]}}} :
INIT_BIN;
assign SRVAL_A_int =
(READ_WIDTH_BIN <= READ_WIDTH_9) ? {{8{SRVAL_BIN[8]}}, {8{SRVAL_BIN[7:0]}}} :
(READ_WIDTH_BIN == READ_WIDTH_18) ? {{4{SRVAL_BIN[17:16]}}, {4{SRVAL_BIN[15:0]}}} :
(READ_WIDTH_BIN == READ_WIDTH_36) ? {{2{SRVAL_BIN[35:32]}}, {2{SRVAL_BIN[31:0]}}} :
SRVAL_BIN;
assign rd_addr_wr = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? rd_addr_a : rd_addr_sync_wr;
assign wr_addr_rd = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? wr_addr_b : wr_addr_sync_rd;
// in clock domains common what is important is the result of the next clock edge.
assign next_rd_addr_wr = (mem_rd_en_a == 1'b1) ? rd_addr_a + rd_loops_a : rd_addr_a;
assign next_wr_addr_rd = (mem_wr_en_b == 1'b1) ? wr_addr_b + wr_loops_b : wr_addr_b;
assign o_stages_empty =
(output_stages==2'b00) ? ram_empty :
(output_stages==2'b01) ? o_lat_empty :
(output_stages==2'b11) ? o_reg_empty : //3 FWFT + ECC + REG
((output_stages==2'b10) && (EN_ECC_PIPE_BIN == EN_ECC_PIPE_FALSE)) ?
o_reg_empty : // 2 FWFT + REG
o_ecc_empty ; // 2 FWFT + ECC // 2 REG + ECC
assign o_stages_full = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ~o_stages_empty : o_stages_full_sync;
// cascade out
assign CASDOUT_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUT_out : {D_WIDTH-1{1'b0}};
assign CASDOUTP_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ?
DOUTP_out : {DP_WIDTH-1{1'b0}};
assign CASNXTEMPTY_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_FIRST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ?
EMPTY_out || SLEEP_A_int : 1'b0;
assign CASPRVRDEN_out = ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) ?
~(CASPRVEMPTY_in || FULL_out || SLEEP_B_int) : 1'b0;
// start model internals
// integers / constants
always begin
if (rd_loops_a>=wr_loops_b) wr_adj = rd_loops_a/wr_loops_b;
else wr_adj = 1;
@(wr_loops_b or rd_loops_a);
end
always begin
if (((wr_loops_b>=rd_loops_a) && (output_stages==0)) ||
((wr_loops_b>=output_stages*rd_loops_a) && (output_stages>0)))
wrcount_adj = 1;
else if ((output_stages>1) ||
(FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE))
wrcount_adj = output_stages*wr_adj;
else
wrcount_adj = 0;
if (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SIMPLE_DATACOUNT)
rdcount_adj = 0;
else if (RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT)
rdcount_adj = output_stages;
@(wr_adj or output_stages or wr_loops_b or rd_loops_a or FIRST_WORD_FALL_THROUGH_BIN or RDCOUNT_TYPE_BIN);
end
// reset logic
assign RDRSTBUSY_out = RDRST_int;
assign WRRSTBUSY_out = WRRST_int || WRRSTBUSY_dly;
assign mem_rst_a = RDRST_int;
//vc capture a reset event, does not matter how long the user keep it asserted
always @ (posedge WRCLK_in) begin
RST_in_p1 <= RST_in;
end
assign RST_in_pulse = RST_in & ~RST_in_p1;
// RST_in sampled by WRCLK cleared by WR done
//vc RST_sync is not used
always @ (posedge WRCLK_in) begin
if (RST_in && ~RST_sync) begin
RST_sync <= 1'b1;
end
else if (WRRST_done) begin
RST_sync <= 1'b0;
end
end
assign WRRST_done_wr = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? WRRST_int : WRRST_done;
always @ (posedge WRCLK_in) begin
//vc old method would repeat reset sequence
//if (RST_in && ~WRRSTBUSY_out) begin
if (RST_in_pulse && ~WRRSTBUSY_out) begin
WRRST_int <= #1 1'b1;
end
else if (WRRST_done_wr) begin
WRRST_int <= #1 1'b0;
end
end
// WRRST_int sampled by RDCLK twice => RDRST_int in CDI
assign RDRST_int = (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON) ? WRRST_int: WRRST_in_sync_rd;
always @ (posedge RDCLK_in) begin
if (glblGSR) begin
WRRST_in_sync_rd1 <= 1'b0;
WRRST_in_sync_rd <= 1'b0;
end
else begin
WRRST_in_sync_rd1 <= #1 WRRST_int;
WRRST_in_sync_rd <= #1 WRRST_in_sync_rd1;
end
end
// 3 rdclks to be done RD side
always @ (posedge RDCLK_in) begin
if (glblGSR || ~RDRST_int || (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON)) begin
RDRST_done2 <= 1'b0;
RDRST_done1 <= 1'b0;
RDRST_done <= 1'b0;
end
else begin
RDRST_done2 <= RDRST_int;
RDRST_done1 <= RDRST_done2;
RDRST_done <= RDRST_done1;
end
end
// 3 wrclks to be done WR side after RDRST_done
always @ (posedge WRCLK_in) begin
if (glblGSR || WRRST_done || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON)) begin
WRRST_done2 <= 1'b0;
WRRST_done1 <= 1'b0;
WRRST_done <= 1'b0;
end
else if (WRRST_int) begin
WRRST_done2 <= RDRST_done;
WRRST_done1 <= WRRST_done2;
WRRST_done <= WRRST_done1;
end
end
// bug fix - 3 rd 2 wr. rtl verified
always @ (posedge RDCLK_in) begin
if (glblGSR || (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON)) begin
RDRSTBUSY_dly2 <= 1'b0;
RDRSTBUSY_dly1 <= 1'b0;
RDRSTBUSY_dly <= 1'b0;
end
else begin
RDRSTBUSY_dly2 <= RDRST_int;
RDRSTBUSY_dly1 <= RDRSTBUSY_dly2;
RDRSTBUSY_dly <= RDRSTBUSY_dly1;
end
end
always @ (posedge WRCLK_in) begin
if (glblGSR || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON)) begin
WRRSTBUSY_dly1 <= 1'b0;
WRRSTBUSY_dly <= 1'b0;
end
else begin
WRRSTBUSY_dly1 <= RDRSTBUSY_dly;
WRRSTBUSY_dly <= WRRSTBUSY_dly1;
end
end
// cascade control
always @ (posedge RDCLK_in) begin
if (glblGSR) CASDOMUXA_reg <= 1'b0;
else CASDOMUXA_reg <= CASDOMUX_in; // EN tied to 1 in FIFO
end
always @ (posedge RDCLK_in) begin
if (glblGSR) CASOREGIMUXA_reg <= 1'b0;
else CASOREGIMUXA_reg <= CASOREGIMUX_in; // EN tied to 1 in FIFO
end
// output register
always @ (*) begin
if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXA_reg) mem_a_reg_mux = CASDIN_in;
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) mem_a_reg_mux = mem_a_pipe;
else mem_a_reg_mux = mem_a_lat;
end
always @ (*) begin
if (((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_PARALLEL) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE)) &&
CASOREGIMUXA_reg) memp_a_reg_mux = CASDINP_in;
else if (EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) memp_a_reg_mux = memp_a_pipe;
else memp_a_reg_mux = memp_a_lat;
end
always @ (posedge RDCLK_in or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_reg, mem_a_reg} <= #100 INIT_A_int;
end
else if (RSTREG_A_int) begin
{memp_a_reg, mem_a_reg} <= #100 SRVAL_A_int;
end
else if (REGCE_A_int) begin
mem_a_reg <= #100 mem_a_reg_mux;
memp_a_reg <= #100 memp_a_reg_mux;
end
end
// bit err reg
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || mem_rst_a) begin
dbit_reg <= 1'b0;
sbit_reg <= 1'b0;
end
else if (REGCE_A_int) begin
dbit_reg <= dbit_ecc;
sbit_reg <= sbit_ecc;
end
end
// ecc pipe register
always @ (posedge RDCLK_in or posedge INIT_MEM or glblGSR) begin
if (glblGSR || INIT_MEM) begin
{memp_a_pipe, mem_a_pipe} <= #100 INIT_A_int;
dbit_pipe <= #100 1'b0;
sbit_pipe <= #100 1'b0;
end
else if (mem_rst_a) begin
{memp_a_pipe, mem_a_pipe} <= #100 SRVAL_A_int;
dbit_pipe <= #100 1'b0;
sbit_pipe <= #100 1'b0;
end
else if (WREN_ecc) begin
mem_a_pipe <= #100 mem_a_lat;
memp_a_pipe <= #100 memp_a_lat;
dbit_pipe <= #100 dbit_lat;
sbit_pipe <= #100 sbit_lat;
end
end
wire fifo_cc_count;
assign fifo_cc_count = (WRITE_WIDTH_BIN==READ_WIDTH_BIN) && (CLOCK_DOMAINS_BIN==CLOCK_DOMAINS_COMMON);
// RDCOUNT sync to RDCLK
// assign rd_simple_raw = {1'b1, wr_addr_rd}-{1'b0, rd_addr_a};
assign rd_simple = {1'b1, wr_addr_rd}-{1'b0, rd_addr_a};
// assign rd_simple = rd_simple_raw[ADDR_WIDTH-1:0];
assign RDCOUNT_out =
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_RAW_PNTR) ? (rd_addr_a/(rd_loops_a)) :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SYNC_PNTR) ? (rd_addr_wr/(rd_loops_a)) :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_SIMPLE_DATACOUNT) ? rd_simple_sync :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT) && ~fifo_cc_count ? rd_simple_sync :
(RDCOUNT_TYPE_BIN == RDCOUNT_TYPE_EXTENDED_DATACOUNT) && fifo_cc_count ? rd_simple_cc :
(rd_addr_a/rd_loops_a);
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int)
rd_simple_cc <= 0;
else if (fifo_cc_count)
if ((RDEN_int && ~EMPTY_out) && ~mem_wr_en_b)
rd_simple_cc <= rd_simple_cc - 1;
else if ((~RDEN_int || EMPTY_out) && mem_wr_en_b)
rd_simple_cc <= rd_simple_cc + 1;
end
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int)
rd_simple_sync <= 0;
else if (rdcount_en)
if (rd_simple[ADDR_WIDTH-1:0] == {ADDR_WIDTH-1{1'b0}})
rd_simple_sync <= {FULL_out, rd_simple[ADDR_WIDTH-2:0]}/rd_loops_a + rdcount_adj;
else
rd_simple_sync <= rd_simple[ADDR_WIDTH-1:0]/rd_loops_a + rdcount_adj;
end
// WRCOUNT sync to WRCLK
assign wr_simple_raw = {1'b1, wr_addr_b}-{1'b0,rd_addr_wr};
assign wr_simple = wr_simple_raw[ADDR_WIDTH-1:0];
assign WRCOUNT_out =
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_RAW_PNTR) ? wr_addr_b/wr_loops_b :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SYNC_PNTR) ? wr_addr_rd/wr_loops_b :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SIMPLE_DATACOUNT) ? wr_simple_sync :
(WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_EXTENDED_DATACOUNT) ? wr_simple_sync :
wr_addr_b/wr_loops_b;
always @ (posedge WRCLK_in or glblGSR) begin
if (glblGSR || WRRSTBUSY_out)
wr_simple_sync <= 0;
else if (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_SIMPLE_DATACOUNT)
wr_simple_sync <= wr_simple/wr_loops_b;
else if (WRCOUNT_TYPE_BIN == WRCOUNT_TYPE_EXTENDED_DATACOUNT)
wr_simple_sync <= (wr_simple/wr_loops_b) + wrcount_adj;
end
// with any output stage or FWFT fill the ouptut latch
// when ram not empty and o_latch empty
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int) begin
o_lat_empty <= 1;
end
else if (RDEN_lat) begin
o_lat_empty <= ram_empty;
end
else if (WREN_lat == 1) begin
o_lat_empty <= 0;
end
end
always @ (negedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int || SLEEP_A_int) begin
fill_lat <= 0;
end
else if (o_lat_empty == 1) begin
if (output_stages>0) begin
fill_lat <= ~ram_empty;
end
end
else begin
fill_lat <= 0;
end
end
// FWFT and
// REGISTERED not ECC_PIPE fill the ouptut register when o_latch not empty.
// REGISTERED and ECC_PIPE fill the ouptut register when o_ecc not empty.
// Empty on external read and prev stage also empty
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int) begin
o_reg_empty <= 1;
end
else if ((o_lat_empty == 0) && RDEN_reg &&
(EN_ECC_PIPE_BIN == EN_ECC_PIPE_FALSE)) begin
o_reg_empty <= 0;
end
else if ((o_ecc_empty == 0) && RDEN_reg &&
(EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE)) begin
o_reg_empty <= 0;
end
else if ((o_lat_empty == 1) && RDEN_reg &&
(EN_ECC_PIPE_BIN == EN_ECC_PIPE_FALSE)) begin
o_reg_empty <= 1;
end
else if ((o_ecc_empty == 1) && RDEN_reg &&
(EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE)) begin
o_reg_empty <= 1;
end
end
always @ (negedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int || SLEEP_A_int) begin
fill_reg <= 0;
end
else if ((o_lat_empty == 0) && (o_reg_empty == 1) &&
(EN_ECC_PIPE_BIN == EN_ECC_PIPE_FALSE) &&
(output_stages==2)) begin
fill_reg <= 1;
end
else if ((o_ecc_empty == 0) && (o_reg_empty == 1) &&
(output_stages==3)) begin
fill_reg <= first_read;
end
else begin
fill_reg <= 0;
end
end
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int) begin
o_ecc_empty <= 1;
end
else if (RDEN_ecc || WREN_ecc) begin
o_ecc_empty <= o_lat_empty;
end
end
always @ (negedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int || SLEEP_A_int) begin
fill_ecc <= 0;
end
else if ((o_lat_empty == 0) && (o_ecc_empty == 1) && first_read &&
((EN_ECC_PIPE_BIN == EN_ECC_PIPE_TRUE) &&
((REGISTER_MODE_BIN == REGISTER_MODE_REGISTERED) ||
(FIRST_WORD_FALL_THROUGH_BIN == FIRST_WORD_FALL_THROUGH_TRUE)))) begin
fill_ecc <= 1;
end
else begin
fill_ecc <= 0;
end
end
// read engine
always @ (rd_addr_a or mem_rd_en_a or mem_rst_a or wr_b_event or INIT_MEM) begin
if ((mem_rd_en_a || INIT_MEM) && ~mem_rst_a) begin
for (raa=0;raa<rd_loops_a;raa=raa+1) begin
ram_rd_a[raa] = mem [rd_addr_a+raa];
end
if (rd_loops_a >= 8) begin
for (raa=0;raa<rd_loops_a/8;raa=raa+1) begin
ramp_rd_a[raa] = memp [(rd_addr_a/8)+raa];
end
end
end
end
assign RDERR_out = rderr_reg;
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR)
rderr_reg <= 1'b0;
else if (RDEN_int && (EMPTY_out || RDRST_int))
rderr_reg <= 1'b1;
else
rderr_reg <= 1'b0;
end
always @(posedge RDCLK_in or posedge INIT_MEM or posedge glblGSR) begin
if (glblGSR || INIT_MEM) begin
mem_is_rst_a <= 1'b0;
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= #100 INIT_A_int >> ra;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= #100 INIT_A_int >> (D_WIDTH+ra);
end
end
first_read <= 1'b0;
rdcount_en <= 1'b0;
end
else if (SLEEP_A_int && mem_rd_en_a) begin
$display("Error: [Unisim %s-23] DRC : READ on port A attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0);
mem_is_rst_a <= 1'b0;
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= #100 1'bx;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= #100 1'bx;
end
end
end
else if (mem_rst_a) begin
if (~mem_is_rst_a) begin
mem_is_rst_a <= 1'b1;
for (ra=0;ra<rd_loops_a;ra=ra+1) begin
mem_a_lat[ra] <= #100 SRVAL_A_int >> ra;
if (ra<rd_loops_a/8) begin
memp_a_lat[ra] <= #100 SRVAL_A_int >> (D_WIDTH+ra);
end
end
end
end
else if (WREN_lat) begin
mem_is_rst_a <= 1'b0;
if ((EN_ECC_READ_BIN == EN_ECC_READ_TRUE) && sbit_int) begin
{memp_a_lat, mem_a_lat} <= #100 fn_cor_bit(synd_ecc[6:0], ram_rd_a, ramp_rd_a);
end
else begin
mem_a_lat <= #100 ram_rd_a;
memp_a_lat <= #100 ramp_rd_a;
end
first_read <= 1'b1;
rdcount_en <= 1'b1;
end
else if (RDEN_int) begin
rdcount_en <= 1'b1;
end
end
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int) begin
rd_addr_a <= {ADDR_WIDTH-1{1'b0}};
rd_addr_a_wr <= {ADDR_WIDTH-1{1'b0}};
wr_addr_sync_rd2 <= {ADDR_WIDTH-1{1'b0}};
wr_addr_sync_rd1 <= {ADDR_WIDTH-1{1'b0}};
wr_addr_sync_rd <= {ADDR_WIDTH-1{1'b0}};
end
else begin
if (mem_rd_en_a) begin
rd_addr_a <= rd_addr_a + rd_loops_a;
end
rd_addr_a_wr <= rd_addr_a;
wr_addr_sync_rd2 <= wr_addr_b_rd;
wr_addr_sync_rd1 <= wr_addr_sync_rd2;
wr_addr_sync_rd <= wr_addr_sync_rd1;
end
end
// write engine
always @ (posedge WRCLK_in or posedge INIT_MEM) begin
if (INIT_MEM == 1'b1) begin
// initialize memory
for (i=0;i<mem_depth;i=i+1) begin
mem [i] <= 1'b0;
end
// initialize memory p
for (i=0;i<memp_depth;i=i+1) begin
memp [i] <= 1'b0;
end
end
else if (mem_wr_en_b && ~glblGSR) begin
if (SLEEP_B_int) begin
$display("Error: [Unisim %s-26] DRC : WRITE on port B attempted while in SLEEP mode at time %.3f ns. Instance: %m.", MODULE_NAME, $time/1000.0);
end
else begin
for (wb=0;wb<wr_loops_b;wb=wb+1) begin
mem [wr_addr_b+wb] <= mem_wr_b[wb];
end
if (WRITE_WIDTH_BIN > WRITE_WIDTH_4) begin
for (wb=0;wb<wr_loops_b/8;wb=wb+1) begin
memp [(wr_addr_b/8)+wb] <= memp_wr_b[wb];
end
end
wr_b_event <= ~wr_b_event;
end
end
end
assign mem_rm_douta = {D_WIDTH{1'b0}};
assign memp_rm_douta = {DP_WIDTH{1'b0}};
// assign mem_we_b = {{D_WIDTH{1'b1}}};
// assign memp_we_b = (WRITE_WIDTH_BIN > WRITE_WIDTH_4) ? {{DP_WIDTH{1'b1}}} : {{DP_WIDTH{1'b0}}};
assign WRERR_out = wrerr_reg;
always @ (posedge WRCLK_in or glblGSR) begin
if (glblGSR)
wrerr_reg <= 1'b0;
else if (WREN_int && (FULL_out || WRRSTBUSY_out))
wrerr_reg <= 1'b1;
else
wrerr_reg <= 1'b0;
end
always @ (posedge WRCLK_in or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
wr_addr_b <= {ADDR_WIDTH-1{1'b0}};
wr_addr_b_rd <= {ADDR_WIDTH-1{1'b0}};
o_stages_full_sync2 <= 1'b0;
o_stages_full_sync1 <= 1'b0;
o_stages_full_sync <= 1'b0;
rd_addr_sync_wr2 <= {ADDR_WIDTH-1{1'b0}};
rd_addr_sync_wr1 <= {ADDR_WIDTH-1{1'b0}};
rd_addr_sync_wr <= {ADDR_WIDTH-1{1'b0}};
end
else begin
if (mem_wr_en_b) begin
wr_addr_b <= wr_addr_b + wr_loops_b;
end
wr_addr_b_rd <= wr_addr_b;
o_stages_full_sync2 <= ~o_stages_empty;
o_stages_full_sync1 <= o_stages_full_sync2;
o_stages_full_sync <= o_stages_full_sync1;
rd_addr_sync_wr2 <= rd_addr_a_wr;
rd_addr_sync_wr1 <= rd_addr_sync_wr2;
rd_addr_sync_wr <= rd_addr_sync_wr1;
end
end
// full flag
assign prog_full = ((full_count_masked <= prog_full_val) && ((full_count > 0) || FULL_out));
assign prog_full_val = mem_depth - (PROG_FULL_THRESH_BIN * wr_loops_b) + m_full;
assign unr_ratio = (wr_loops_b>=rd_loops_a) ? wr_loops_b/rd_loops_a - 1 : 0;
assign m_full = (output_stages == 0) ? 0 : ((((m_full_raw-1)/wr_loops_b)+1)*wr_loops_b);
assign m_full_raw = output_stages*rd_loops_a;
assign n_empty = output_stages;
assign prog_empty_val = (PROG_EMPTY_THRESH_BIN - n_empty + 1)*rd_loops_a;
assign full_count_masked = full_count & wr_addr_b_mask;
assign full_count = {1'b1, rd_addr_wr} - {1'b0, wr_addr_b};
assign next_full_count = {1'b1, next_rd_addr_wr} - {1'b0, next_wr_addr_rd};
assign FULL_out = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ram_full_c : ram_full_i;
// ram_full independent clocks is one_from_full common clocks
assign ram_one_from_full_i = ((full_count < 2*wr_loops_b) && (full_count > 0));
assign ram_two_from_full_i = ((full_count < 3*wr_loops_b) && (full_count > 0));
assign ram_one_from_full = (next_full_count < wr_loops_b) && ~ram_full_c;
assign ram_two_from_full = (next_full_count < 2*wr_loops_b) && ~ram_full_c;
// when full common clocks, next read makes it not full
// assign ram_one_read_from_not_full = ((full_count + rd_loops_a >= wr_loops_b) && ram_full_c);
assign ram_one_read_from_not_full = (next_full_count >= wr_loops_b) && ram_full_c;
always @ (posedge WRCLK_in or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
ram_full_c <= 1'b0;
end
else if (mem_wr_en_b &&
(mem_rd_en_a && (rd_loops_a < wr_loops_b)) &&
ram_one_from_full) begin
ram_full_c <= 1'b1;
end
else if (mem_wr_en_b && ~mem_rd_en_a && ram_one_from_full) begin
ram_full_c <= 1'b1;
end
else if (mem_rd_en_a && ram_one_read_from_not_full) begin
ram_full_c <= 1'b0;
end
else begin
ram_full_c <= ram_full_c;
end
end
always @ (posedge WRCLK_in or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
ram_full_i <= 1'b0;
end
else if (mem_wr_en_b && ram_two_from_full_i && ~ram_full_i) begin
ram_full_i <= 1'b1;
end
else if (~ram_one_from_full_i) begin
ram_full_i <= 1'b0;
end
else begin
ram_full_i <= ram_full_i;
end
end
assign PROGFULL_out = prog_full_reg;
always @ (posedge WRCLK_in or glblGSR) begin
if (glblGSR || WRRSTBUSY_out) begin
prog_full_reg <= 1'b0;
end
else begin
prog_full_reg <= prog_full;
end
end
// empty flag
assign empty_count = {1'b1, wr_addr_rd} - {1'b0, rd_addr_a};
assign next_empty_count = {1'b1, next_wr_addr_rd} - {1'b0, next_rd_addr_wr};
assign EMPTY_out = o_stages_empty;
assign ram_empty = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? ram_empty_c : ram_empty_i;
assign ram_one_read_from_empty_i = (empty_count < 2*rd_loops_a) && (empty_count >= rd_loops_a) && ~ram_empty;
assign ram_one_read_from_empty = (next_empty_count < rd_loops_a) && ~ram_empty;
assign ram_one_write_from_not_empty = (next_empty_count >= rd_loops_a) && ram_empty;
assign ram_one_write_from_not_empty_i = (rd_loops_a < wr_loops_b) ? EMPTY_out : ((empty_count + wr_loops_b) >= rd_loops_a);
assign prog_empty = ((empty_count < prog_empty_val) || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON && ram_empty)) && (~FULL_out || (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_INDEPENDENT));
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int)
ram_empty_c <= 1'b1;
// RD only makes empty
else if (~mem_wr_en_b &&
mem_rd_en_a &&
(ram_one_read_from_empty || ram_empty_c))
ram_empty_c <= 1'b1;
// RD and WR when one read from empty and RD more than WR makes empty
else if (mem_wr_en_b &&
(mem_rd_en_a && (rd_loops_a > wr_loops_b)) &&
(ram_one_read_from_empty || ram_empty_c))
ram_empty_c <= 1'b1;
// CR701309 CC WR when empty always makes not empty. simultaneous RD gets ERR
else if ( mem_wr_en_b && (ram_one_write_from_not_empty && ram_empty_c))
ram_empty_c <= 1'b0;
else
ram_empty_c <= ram_empty_c;
end
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int)
ram_empty_i <= 1'b1;
else if (mem_rd_en_a && ram_one_read_from_empty_i) // RDEN_in ?
ram_empty_i <= 1'b1;
else if (empty_count < rd_loops_a)
ram_empty_i <= 1'b1;
else
ram_empty_i <= 1'b0;
end
// assign PROGEMPTY_out = (CLOCK_DOMAINS_BIN == CLOCK_DOMAINS_COMMON) ? prog_empty_cc : prog_empty;
assign PROGEMPTY_out = prog_empty_cc;
always @ (posedge RDCLK_in or glblGSR) begin
if (glblGSR || RDRST_int)
prog_empty_cc <= 1'b1;
else
prog_empty_cc <= prog_empty;
end
// eccparity is flopped
always @ (*) begin
if (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE) synd_wr = 8'b0;
else begin
if ((CASCADE_ORDER_BIN == CASCADE_ORDER_LAST) ||
(CASCADE_ORDER_BIN == CASCADE_ORDER_MIDDLE))
synd_wr = fn_ecc(encode, CASDIN_in, CASDINP_in);
else
synd_wr = fn_ecc(encode, DIN_in, DINP_in);
end
end
always @ (*) begin
if (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) synd_rd = fn_ecc(decode, ram_rd_a, ramp_rd_a);
else synd_rd = 8'b0;
end
always @ (*) begin
if (EN_ECC_READ_BIN == EN_ECC_READ_TRUE) synd_ecc = synd_rd ^ ramp_rd_a;
else synd_ecc = 8'b0;
end
assign sbit_int = (|synd_ecc && synd_ecc[7]);
assign dbit_int = (|synd_ecc && ~synd_ecc[7]);
always @(posedge RDCLK_in) begin
if (mem_rst_a) begin
sbit_lat <= 1'b0;
dbit_lat <= 1'b0;
error_bit <= 7'b0;
end
else if (mem_rd_en_a && (EN_ECC_READ_BIN == EN_ECC_READ_TRUE)) begin
sbit_lat <= sbit_int;
dbit_lat <= dbit_int;
error_bit <= synd_ecc[6:0];
end
end
// assign {memp_a_ecc_cor, mem_a_ecc_cor} = sbit_int ?
// fn_cor_bit(synd_ecc[6:0], mem_rd_a, memp_rd_a) :
// {memp_rd_a, mem_rd_a};
always @ (posedge WRCLK_in or glblGSR) begin
if(glblGSR || (EN_ECC_WRITE_BIN == EN_ECC_WRITE_FALSE))
eccparity_reg <= 8'h00;
else if (mem_wr_en_b)
eccparity_reg <= synd_wr;
end
`ifdef XIL_TIMING
reg notifier;
wire rdclk_en_n;
wire rdclk_en_p;
wire wrclk_en_n;
wire wrclk_en_p;
assign rdclk_en_n = IS_RDCLK_INVERTED_BIN;
assign rdclk_en_p = ~IS_RDCLK_INVERTED_BIN;
assign wrclk_en_n = IS_WRCLK_INVERTED_BIN;
assign wrclk_en_p = ~IS_WRCLK_INVERTED_BIN;
`endif
specify
(CASDIN *> CASDOUT) = (0:0:0, 0:0:0);
(CASDIN *> DOUT) = (0:0:0, 0:0:0);
(CASDINP *> CASDOUTP) = (0:0:0, 0:0:0);
(CASDINP *> DOUTP) = (0:0:0, 0:0:0);
(CASPRVEMPTY => CASPRVRDEN) = (0:0:0, 0:0:0);
(RDCLK *> CASDOUT) = (100:100:100, 100:100:100);
(RDCLK *> CASDOUTP) = (100:100:100, 100:100:100);
(RDCLK *> DOUT) = (100:100:100, 100:100:100);
(RDCLK *> DOUTP) = (100:100:100, 100:100:100);
(RDCLK *> RDCOUNT) = (100:100:100, 100:100:100);
(RDCLK *> WRCOUNT) = (100:100:100, 100:100:100);
(RDCLK => CASNXTEMPTY) = (100:100:100, 100:100:100);
(RDCLK => DBITERR) = (100:100:100, 100:100:100);
(RDCLK => EMPTY) = (100:100:100, 100:100:100);
(RDCLK => PROGEMPTY) = (100:100:100, 100:100:100);
(RDCLK => RDERR) = (100:100:100, 100:100:100);
(RDCLK => RDRSTBUSY) = (100:100:100, 100:100:100);
(RDCLK => SBITERR) = (100:100:100, 100:100:100);
(WRCLK *> CASDOUT) = (100:100:100, 100:100:100);
(WRCLK *> CASDOUTP) = (100:100:100, 100:100:100);
(WRCLK *> DOUT) = (100:100:100, 100:100:100);
(WRCLK *> DOUTP) = (100:100:100, 100:100:100);
(WRCLK *> ECCPARITY) = (100:100:100, 100:100:100);
(WRCLK *> RDCOUNT) = (100:100:100, 100:100:100);
(WRCLK *> WRCOUNT) = (100:100:100, 100:100:100);
(WRCLK => CASPRVRDEN) = (100:100:100, 100:100:100);
(WRCLK => FULL) = (100:100:100, 100:100:100);
(WRCLK => PROGFULL) = (100:100:100, 100:100:100);
(WRCLK => RDRSTBUSY) = (100:100:100, 100:100:100);
(WRCLK => WRERR) = (100:100:100, 100:100:100);
(WRCLK => WRRSTBUSY) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge RDCLK, 0:0:0, notifier);
$period (negedge WRCLK, 0:0:0, notifier);
$period (posedge RDCLK, 0:0:0, notifier);
$period (posedge WRCLK, 0:0:0, notifier);
$setuphold (negedge RDCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDIN_delay);
$setuphold (negedge RDCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDINP_delay);
$setuphold (negedge RDCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUX_delay);
$setuphold (negedge RDCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge RDCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge RDCLK, negedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (negedge RDCLK, negedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (negedge RDCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge RDCLK, negedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DIN_delay);
$setuphold (negedge RDCLK, negedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DINP_delay);
$setuphold (negedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RDEN_delay);
$setuphold (negedge RDCLK, negedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, REGCE_delay);
$setuphold (negedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RSTREG_delay);
$setuphold (negedge RDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, SLEEP_delay);
$setuphold (negedge RDCLK, negedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, WREN_delay);
$setuphold (negedge RDCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDIN_delay);
$setuphold (negedge RDCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDINP_delay);
$setuphold (negedge RDCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUX_delay);
$setuphold (negedge RDCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge RDCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge RDCLK, posedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (negedge RDCLK, posedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (negedge RDCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge RDCLK, posedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DIN_delay);
$setuphold (negedge RDCLK, posedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, DINP_delay);
$setuphold (negedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RDEN_delay);
$setuphold (negedge RDCLK, posedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, REGCE_delay);
$setuphold (negedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, RSTREG_delay);
$setuphold (negedge RDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, SLEEP_delay);
$setuphold (negedge RDCLK, posedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_n,rdclk_en_n, RDCLK_delay, WREN_delay);
$setuphold (negedge WRCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDIN_delay);
$setuphold (negedge WRCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDINP_delay);
$setuphold (negedge WRCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUX_delay);
$setuphold (negedge WRCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge WRCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge WRCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge WRCLK, negedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DIN_delay);
$setuphold (negedge WRCLK, negedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DINP_delay);
$setuphold (negedge WRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge WRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge WRCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RDEN_delay);
$setuphold (negedge WRCLK, negedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RST_delay);
$setuphold (negedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, WREN_delay);
$setuphold (negedge WRCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDIN_delay);
$setuphold (negedge WRCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDINP_delay);
$setuphold (negedge WRCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUX_delay);
$setuphold (negedge WRCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (negedge WRCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (negedge WRCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (negedge WRCLK, posedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DIN_delay);
$setuphold (negedge WRCLK, posedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, DINP_delay);
$setuphold (negedge WRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, INJECTDBITERR_delay);
$setuphold (negedge WRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, INJECTSBITERR_delay);
$setuphold (negedge WRCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RDEN_delay);
$setuphold (negedge WRCLK, posedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, RST_delay);
$setuphold (negedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_n,wrclk_en_n, WRCLK_delay, WREN_delay);
$setuphold (posedge RDCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDIN_delay);
$setuphold (posedge RDCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDINP_delay);
$setuphold (posedge RDCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUX_delay);
$setuphold (posedge RDCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge RDCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge RDCLK, negedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (posedge RDCLK, negedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (posedge RDCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge RDCLK, negedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DIN_delay);
$setuphold (posedge RDCLK, negedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DINP_delay);
$setuphold (posedge RDCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RDEN_delay);
$setuphold (posedge RDCLK, negedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, REGCE_delay);
$setuphold (posedge RDCLK, negedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RSTREG_delay);
$setuphold (posedge RDCLK, negedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, SLEEP_delay);
$setuphold (posedge RDCLK, negedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, WREN_delay);
$setuphold (posedge RDCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDIN_delay);
$setuphold (posedge RDCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDINP_delay);
$setuphold (posedge RDCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUX_delay);
$setuphold (posedge RDCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge RDCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge RDCLK, posedge CASOREGIMUX, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUX_delay);
$setuphold (posedge RDCLK, posedge CASOREGIMUXEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASOREGIMUXEN_delay);
$setuphold (posedge RDCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge RDCLK, posedge DIN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DIN_delay);
$setuphold (posedge RDCLK, posedge DINP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, DINP_delay);
$setuphold (posedge RDCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RDEN_delay);
$setuphold (posedge RDCLK, posedge REGCE, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, REGCE_delay);
$setuphold (posedge RDCLK, posedge RSTREG, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, RSTREG_delay);
$setuphold (posedge RDCLK, posedge SLEEP, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, SLEEP_delay);
$setuphold (posedge RDCLK, posedge WREN, 0:0:0, 0:0:0, notifier,rdclk_en_p,rdclk_en_p, RDCLK_delay, WREN_delay);
$setuphold (posedge WRCLK, negedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDIN_delay);
$setuphold (posedge WRCLK, negedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDINP_delay);
$setuphold (posedge WRCLK, negedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUX_delay);
$setuphold (posedge WRCLK, negedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge WRCLK, negedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge WRCLK, negedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge WRCLK, negedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DIN_delay);
$setuphold (posedge WRCLK, negedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DINP_delay);
$setuphold (posedge WRCLK, negedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge WRCLK, negedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge WRCLK, negedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RDEN_delay);
$setuphold (posedge WRCLK, negedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RST_delay);
$setuphold (posedge WRCLK, negedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, WREN_delay);
$setuphold (posedge WRCLK, posedge CASDIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDIN_delay);
$setuphold (posedge WRCLK, posedge CASDINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDINP_delay);
$setuphold (posedge WRCLK, posedge CASDOMUX, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUX_delay);
$setuphold (posedge WRCLK, posedge CASDOMUXEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASDOMUXEN_delay);
$setuphold (posedge WRCLK, posedge CASNXTRDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASNXTRDEN_delay);
$setuphold (posedge WRCLK, posedge CASPRVEMPTY, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, CASPRVEMPTY_delay);
$setuphold (posedge WRCLK, posedge DIN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DIN_delay);
$setuphold (posedge WRCLK, posedge DINP, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, DINP_delay);
$setuphold (posedge WRCLK, posedge INJECTDBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, INJECTDBITERR_delay);
$setuphold (posedge WRCLK, posedge INJECTSBITERR, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, INJECTSBITERR_delay);
$setuphold (posedge WRCLK, posedge RDEN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RDEN_delay);
$setuphold (posedge WRCLK, posedge RST, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, RST_delay);
$setuphold (posedge WRCLK, posedge WREN, 0:0:0, 0:0:0, notifier,wrclk_en_p,wrclk_en_p, WRCLK_delay, WREN_delay);
$width (negedge RDCLK, 0:0:0, 0, notifier);
$width (negedge WRCLK, 0:0:0, 0, notifier);
$width (posedge RDCLK, 0:0:0, 0, notifier);
$width (posedge WRCLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(* Evgeny Makarov, INRIA, 2007 *)
(************************************************************************)
(** This file defined the strong (course-of-value, well-founded) recursion
and proves its properties *)
Require Export NSub.
Ltac f_equiv' := repeat progress (f_equiv; try intros ? ? ?; auto).
Module NStrongRecProp (Import N : NAxiomsRecSig').
Include NSubProp N.
Section StrongRecursion.
Variable A : Type.
Variable Aeq : relation A.
Variable Aeq_equiv : Equivalence Aeq.
(** [strong_rec] allows to define a recursive function [phi] given by
an equation [phi(n) = F(phi)(n)] where recursive calls to [phi]
in [F] are made on strictly lower numbers than [n].
For [strong_rec a F n]:
- Parameter [a:A] is a default value used internally, it has no
effect on the final result.
- Parameter [F:(N->A)->N->A] is the step function:
[F f n] should return [phi(n)] when [f] is a function
that coincide with [phi] for numbers strictly less than [n].
*)
Definition strong_rec (a : A) (f : (N.t -> A) -> N.t -> A) (n : N.t) : A :=
recursion (fun _ => a) (fun _ => f) (S n) n.
(** For convenience, we use in proofs an intermediate definition
between [recursion] and [strong_rec]. *)
Definition strong_rec0 (a : A) (f : (N.t -> A) -> N.t -> A) : N.t -> N.t -> A :=
recursion (fun _ => a) (fun _ => f).
Lemma strong_rec_alt : forall a f n,
strong_rec a f n = strong_rec0 a f (S n) n.
Proof.
reflexivity.
Qed.
Instance strong_rec0_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> N.eq ==> Aeq)
strong_rec0.
Proof.
unfold strong_rec0; f_equiv'.
Qed.
Instance strong_rec_wd :
Proper (Aeq ==> ((N.eq ==> Aeq) ==> N.eq ==> Aeq) ==> N.eq ==> Aeq) strong_rec.
Proof.
intros a a' Eaa' f f' Eff' n n' Enn'.
rewrite !strong_rec_alt; f_equiv'.
Qed.
Section FixPoint.
Variable f : (N.t -> A) -> N.t -> A.
Variable f_wd : Proper ((N.eq==>Aeq)==>N.eq==>Aeq) f.
Lemma strong_rec0_0 : forall a m,
(strong_rec0 a f 0 m) = a.
Proof.
intros. unfold strong_rec0. rewrite recursion_0; auto.
Qed.
Lemma strong_rec0_succ : forall a n m,
Aeq (strong_rec0 a f (S n) m) (f (strong_rec0 a f n) m).
Proof.
intros. unfold strong_rec0.
f_equiv.
rewrite recursion_succ; f_equiv'.
reflexivity.
Qed.
Lemma strong_rec_0 : forall a,
Aeq (strong_rec a f 0) (f (fun _ => a) 0).
Proof.
intros. rewrite strong_rec_alt, strong_rec0_succ; f_equiv'.
rewrite strong_rec0_0. reflexivity.
Qed.
(* We need an assumption saying that for every n, the step function (f h n)
calls h only on the segment [0 ... n - 1]. This means that if h1 and h2
coincide on values < n, then (f h1 n) coincides with (f h2 n) *)
Hypothesis step_good :
forall (n : N.t) (h1 h2 : N.t -> A),
(forall m : N.t, m < n -> Aeq (h1 m) (h2 m)) -> Aeq (f h1 n) (f h2 n).
Lemma strong_rec0_more_steps : forall a k n m, m < n ->
Aeq (strong_rec0 a f n m) (strong_rec0 a f (n+k) m).
Proof.
intros a k n. pattern n.
apply induction; clear n.
intros n n' Hn; setoid_rewrite Hn; auto with *.
intros m Hm. destruct (nlt_0_r _ Hm).
intros n IH m Hm.
rewrite lt_succ_r in Hm.
rewrite add_succ_l.
rewrite 2 strong_rec0_succ.
apply step_good.
intros m' Hm'.
apply IH.
apply lt_le_trans with m; auto.
Qed.
Lemma strong_rec0_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec0 a f (S n) n) (f (fun n => strong_rec0 a f (S n) n) n).
Proof.
intros.
rewrite strong_rec0_succ.
apply step_good.
intros m Hm.
symmetry.
setoid_replace n with (S m + (n - S m)).
apply strong_rec0_more_steps.
apply lt_succ_diag_r.
rewrite add_comm.
symmetry.
apply sub_add.
rewrite le_succ_l; auto.
Qed.
Theorem strong_rec_fixpoint : forall (a : A) (n : N.t),
Aeq (strong_rec a f n) (f (strong_rec a f) n).
Proof.
intros.
transitivity (f (fun n => strong_rec0 a f (S n) n) n).
rewrite strong_rec_alt.
apply strong_rec0_fixpoint.
f_equiv.
intros x x' Hx; rewrite strong_rec_alt, Hx; auto with *.
Qed.
(** NB: without the [step_good] hypothesis, we have proved that
[strong_rec a f 0] is [f (fun _ => a) 0]. Now we can prove
that the first argument of [f] is arbitrary in this case...
*)
Theorem strong_rec_0_any : forall (a : A)(any : N.t->A),
Aeq (strong_rec a f 0) (f any 0).
Proof.
intros.
rewrite strong_rec_fixpoint.
apply step_good.
intros m Hm. destruct (nlt_0_r _ Hm).
Qed.
(** ... and that first argument of [strong_rec] is always arbitrary. *)
Lemma strong_rec_any_fst_arg : forall a a' n,
Aeq (strong_rec a f n) (strong_rec a' f n).
Proof.
intros a a' n.
generalize (le_refl n).
set (k:=n) at -2. clearbody k. revert k. pattern n.
apply induction; clear n.
(* compat *)
intros n n' Hn. setoid_rewrite Hn; auto with *.
(* 0 *)
intros k Hk. rewrite le_0_r in Hk.
rewrite Hk, strong_rec_0. symmetry. apply strong_rec_0_any.
(* S *)
intros n IH k Hk.
rewrite 2 strong_rec_fixpoint.
apply step_good.
intros m Hm.
apply IH.
rewrite succ_le_mono.
apply le_trans with k; auto.
rewrite le_succ_l; auto.
Qed.
End FixPoint.
End StrongRecursion.
Arguments strong_rec [A] a f n.
End NStrongRecProp.
|
/* sd_card.v */
/* 2012, [email protected] */
module sd_card #(
parameter FNAME=""
)(
input wire sck,
input wire ss,
input wire mosi,
output wire miso
);
`define SEEK_SET 0
`define SEEK_CUR 1
`define SEEK_END 2
// file I/O
integer res;
integer file;
initial begin
file = $fopen(FNAME, "rb+");
if (!file) $display("ERR : SD_CARD : cannot open file %s!", FNAME);
end
// commands
localparam [7:0]
CMD0 = 8'h40,
CMD8 = 8'h48,
CMD55 = 8'h77,
CMD41 = 8'h69,
CMD58 = 8'h7a,
CMD17 = 8'h51;
// transmit / receive
reg [ 2:0] trxcnt = 3'h0;
reg [ 7:0] tx = 8'hff;
reg [ 7:0] rx = 8'hff;
wire trxdone;
always @ (posedge sck) if (!ss) rx <= #1 {rx[6:0], mosi};
always @ (negedge sck) if (!ss) tx <= #1 {tx[6:0], 1'b1};
always @ (posedge sck) if (!ss) trxcnt <= #1 trxcnt + 1;
assign miso = tx[7];
assign trxdone = (trxcnt == 3'd7);
// receive
localparam [3:0] RX_CMD=0, RX_DAT1=1, RX_DAT2=2, RX_DAT3=3, RX_DAT4=4, RX_CRC=5;
reg [ 3:0] cmdstate = RX_CMD;
reg [ 7:0] rcmd = 8'hff;
reg [31:0] rarg;
reg [ 7:0] rcrc;
reg cmddone=0;
always begin
@ (posedge sck);
if (trxdone) begin
#2;
case (cmdstate)
RX_CMD : begin cmddone=0; rcmd = 8'hff; if(rx != 8'hff) begin rcmd = rx; cmdstate = RX_DAT1; end end
RX_DAT1 : begin rarg[31:24] = rx; cmdstate = RX_DAT2; end
RX_DAT2 : begin rarg[23:16] = rx; cmdstate = RX_DAT3; end
RX_DAT3 : begin rarg[15: 8] = rx; cmdstate = RX_DAT4; end
RX_DAT4 : begin rarg[ 7: 0] = rx; cmdstate = RX_CRC; end
RX_CRC : begin rcrc[ 7: 0] = rx; cmdstate = RX_CMD; cmddone=1; end
endcase
end
end
// transmit
integer readlen=512;
localparam [3:0] TX_IDLE=0, TX_DLY=1, TX_TRAN=2;
reg [ 3:0] txstate = TX_IDLE;
reg [ 7:0] txdat [0:512+5-1];
reg txact = 1'h0;
reg [10:0] txlen;
integer i;
always begin
@ (negedge sck);
if (trxcnt == 3'd0) begin
#2;
case (txstate)
TX_IDLE : begin if (txact) begin txstate=TX_TRAN; i=0; end end
TX_DLY : begin txstate=TX_TRAN; end
TX_TRAN : begin if (txlen) begin tx=txdat[i]; i=i+1; txlen=txlen-1; txstate = TX_TRAN; end else begin txact=0; txstate=TX_IDLE; end end
endcase
end
end
// state
localparam [3:0] ST_IDLE=0, ST_READ=3;
reg [ 3:0] state = ST_IDLE;
reg rdy = 0;
always begin
@ (posedge sck);
if (trxdone && !txact && cmddone) begin
#2;
case (rcmd)
CMD0 : begin txact=1; txlen=1; txdat[0]=8'h01; end
CMD8 : begin txact=1; txlen=5; txdat[0]=8'h01; txdat[1]=00; txdat[2]=8'h00; txdat[3]=8'h01; txdat[4]=8'haa; end
CMD55 : begin txact=1; txlen=1; txdat[0]=8'h01; end
CMD41 : begin txact=1; txlen=1; txdat[0]=8'h00; end
CMD58 : begin txact=1; txlen=5; txdat[0]=8'h00; txdat[1]=00; txdat[2]=8'h00; txdat[3]=8'h00; txdat[4]=8'h00; end
CMD17 : begin txact=1; txlen=readlen+5; read_data(rarg); end
endcase
end
end
// read data
task read_data;
input [31:0] adr;
integer i;
begin
txdat[0]=8'h00;
txdat[1]=8'hff;
txdat[2]=8'hfe;
res = $fseek(file, adr, `SEEK_SET);
//for(i=3; i<readlen+3; i=i+1) res = $fread(txdat[i], file);
res = $fread(txdat, file, 3, readlen);
txdat[515]=8'hff;
txdat[516]=8'hff;
end
endtask
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
`include "verilated.v"
module t_case_write1_tasks ();
// verilator lint_off WIDTH
// verilator lint_off CASEINCOMPLETE
parameter STRLEN = 78;
task ozonerab;
input [6:0] rab;
inout [STRLEN*8:1] foobar;
// verilator no_inline_task
begin
case (rab[6:0])
7'h00 : foobar = {foobar, " 0"};
7'h01 : foobar = {foobar, " 1"};
7'h02 : foobar = {foobar, " 2"};
7'h03 : foobar = {foobar, " 3"};
7'h04 : foobar = {foobar, " 4"};
7'h05 : foobar = {foobar, " 5"};
7'h06 : foobar = {foobar, " 6"};
7'h07 : foobar = {foobar, " 7"};
7'h08 : foobar = {foobar, " 8"};
7'h09 : foobar = {foobar, " 9"};
7'h0a : foobar = {foobar, " 10"};
7'h0b : foobar = {foobar, " 11"};
7'h0c : foobar = {foobar, " 12"};
7'h0d : foobar = {foobar, " 13"};
7'h0e : foobar = {foobar, " 14"};
7'h0f : foobar = {foobar, " 15"};
7'h10 : foobar = {foobar, " 16"};
7'h11 : foobar = {foobar, " 17"};
7'h12 : foobar = {foobar, " 18"};
7'h13 : foobar = {foobar, " 19"};
7'h14 : foobar = {foobar, " 20"};
7'h15 : foobar = {foobar, " 21"};
7'h16 : foobar = {foobar, " 22"};
7'h17 : foobar = {foobar, " 23"};
7'h18 : foobar = {foobar, " 24"};
7'h19 : foobar = {foobar, " 25"};
7'h1a : foobar = {foobar, " 26"};
7'h1b : foobar = {foobar, " 27"};
7'h1c : foobar = {foobar, " 28"};
7'h1d : foobar = {foobar, " 29"};
7'h1e : foobar = {foobar, " 30"};
7'h1f : foobar = {foobar, " 31"};
7'h20 : foobar = {foobar, " 32"};
7'h21 : foobar = {foobar, " 33"};
7'h22 : foobar = {foobar, " 34"};
7'h23 : foobar = {foobar, " 35"};
7'h24 : foobar = {foobar, " 36"};
7'h25 : foobar = {foobar, " 37"};
7'h26 : foobar = {foobar, " 38"};
7'h27 : foobar = {foobar, " 39"};
7'h28 : foobar = {foobar, " 40"};
7'h29 : foobar = {foobar, " 41"};
7'h2a : foobar = {foobar, " 42"};
7'h2b : foobar = {foobar, " 43"};
7'h2c : foobar = {foobar, " 44"};
7'h2d : foobar = {foobar, " 45"};
7'h2e : foobar = {foobar, " 46"};
7'h2f : foobar = {foobar, " 47"};
7'h30 : foobar = {foobar, " 48"};
7'h31 : foobar = {foobar, " 49"};
7'h32 : foobar = {foobar, " 50"};
7'h33 : foobar = {foobar, " 51"};
7'h34 : foobar = {foobar, " 52"};
7'h35 : foobar = {foobar, " 53"};
7'h36 : foobar = {foobar, " 54"};
7'h37 : foobar = {foobar, " 55"};
7'h38 : foobar = {foobar, " 56"};
7'h39 : foobar = {foobar, " 57"};
7'h3a : foobar = {foobar, " 58"};
7'h3b : foobar = {foobar, " 59"};
7'h3c : foobar = {foobar, " 60"};
7'h3d : foobar = {foobar, " 61"};
7'h3e : foobar = {foobar, " 62"};
7'h3f : foobar = {foobar, " 63"};
7'h40 : foobar = {foobar, " 64"};
7'h41 : foobar = {foobar, " 65"};
7'h42 : foobar = {foobar, " 66"};
7'h43 : foobar = {foobar, " 67"};
7'h44 : foobar = {foobar, " 68"};
7'h45 : foobar = {foobar, " 69"};
7'h46 : foobar = {foobar, " 70"};
7'h47 : foobar = {foobar, " 71"};
7'h48 : foobar = {foobar, " 72"};
7'h49 : foobar = {foobar, " 73"};
7'h4a : foobar = {foobar, " 74"};
7'h4b : foobar = {foobar, " 75"};
7'h4c : foobar = {foobar, " 76"};
7'h4d : foobar = {foobar, " 77"};
7'h4e : foobar = {foobar, " 78"};
7'h4f : foobar = {foobar, " 79"};
7'h50 : foobar = {foobar, " 80"};
7'h51 : foobar = {foobar, " 81"};
7'h52 : foobar = {foobar, " 82"};
7'h53 : foobar = {foobar, " 83"};
7'h54 : foobar = {foobar, " 84"};
7'h55 : foobar = {foobar, " 85"};
7'h56 : foobar = {foobar, " 86"};
7'h57 : foobar = {foobar, " 87"};
7'h58 : foobar = {foobar, " 88"};
7'h59 : foobar = {foobar, " 89"};
7'h5a : foobar = {foobar, " 90"};
7'h5b : foobar = {foobar, " 91"};
7'h5c : foobar = {foobar, " 92"};
7'h5d : foobar = {foobar, " 93"};
7'h5e : foobar = {foobar, " 94"};
7'h5f : foobar = {foobar, " 95"};
7'h60 : foobar = {foobar, " 96"};
7'h61 : foobar = {foobar, " 97"};
7'h62 : foobar = {foobar, " 98"};
7'h63 : foobar = {foobar, " 99"};
7'h64 : foobar = {foobar, " 100"};
7'h65 : foobar = {foobar, " 101"};
7'h66 : foobar = {foobar, " 102"};
7'h67 : foobar = {foobar, " 103"};
7'h68 : foobar = {foobar, " 104"};
7'h69 : foobar = {foobar, " 105"};
7'h6a : foobar = {foobar, " 106"};
7'h6b : foobar = {foobar, " 107"};
7'h6c : foobar = {foobar, " 108"};
7'h6d : foobar = {foobar, " 109"};
7'h6e : foobar = {foobar, " 110"};
7'h6f : foobar = {foobar, " 111"};
7'h70 : foobar = {foobar, " 112"};
7'h71 : foobar = {foobar, " 113"};
7'h72 : foobar = {foobar, " 114"};
7'h73 : foobar = {foobar, " 115"};
7'h74 : foobar = {foobar, " 116"};
7'h75 : foobar = {foobar, " 117"};
7'h76 : foobar = {foobar, " 118"};
7'h77 : foobar = {foobar, " 119"};
7'h78 : foobar = {foobar, " 120"};
7'h79 : foobar = {foobar, " 121"};
7'h7a : foobar = {foobar, " 122"};
7'h7b : foobar = {foobar, " 123"};
7'h7c : foobar = {foobar, " 124"};
7'h7d : foobar = {foobar, " 125"};
7'h7e : foobar = {foobar, " 126"};
7'h7f : foobar = {foobar, " 127"};
default:foobar = {foobar, " 128"};
endcase
end
endtask
task ozonerb;
input [5:0] rb;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rb[5:0])
6'h10,
6'h17,
6'h1e,
6'h1f: foobar = {foobar, " 129"};
default: ozonerab({1'b1, rb}, foobar);
endcase
end
endtask
task ozonef3f4_iext;
input [1:0] foo;
input [15:0] im16;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 :
begin
skyway({4{im16[15]}}, foobar);
skyway({4{im16[15]}}, foobar);
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
foobar = {foobar, " 130"};
end
2'h1 :
begin
foobar = {foobar, " 131"};
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
end
2'h2 :
begin
skyway({4{im16[15]}}, foobar);
skyway({4{im16[15]}}, foobar);
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
foobar = {foobar, " 132"};
end
2'h3 :
begin
foobar = {foobar, " 133"};
skyway(im16[15:12], foobar);
skyway(im16[11: 8], foobar);
skyway(im16[ 7: 4], foobar);
skyway(im16[ 3:0], foobar);
end
endcase
end
endtask
task skyway;
input [ 3:0] hex;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (hex)
4'h0 : foobar = {foobar, " 134"};
4'h1 : foobar = {foobar, " 135"};
4'h2 : foobar = {foobar, " 136"};
4'h3 : foobar = {foobar, " 137"};
4'h4 : foobar = {foobar, " 138"};
4'h5 : foobar = {foobar, " 139"};
4'h6 : foobar = {foobar, " 140"};
4'h7 : foobar = {foobar, " 141"};
4'h8 : foobar = {foobar, " 142"};
4'h9 : foobar = {foobar, " 143"};
4'ha : foobar = {foobar, " 144"};
4'hb : foobar = {foobar, " 145"};
4'hc : foobar = {foobar, " 146"};
4'hd : foobar = {foobar, " 147"};
4'he : foobar = {foobar, " 148"};
4'hf : foobar = {foobar, " 149"};
endcase
end
endtask
task ozonesr;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[11: 9])
3'h0 : foobar = {foobar, " 158"};
3'h1 : foobar = {foobar, " 159"};
3'h2 : foobar = {foobar, " 160"};
3'h3 : foobar = {foobar, " 161"};
3'h4 : foobar = {foobar, " 162"};
3'h5 : foobar = {foobar, " 163"};
3'h6 : foobar = {foobar, " 164"};
3'h7 : foobar = {foobar, " 165"};
endcase
end
endtask
task ozonejk;
input k;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
if (k)
foobar = {foobar, " 166"};
else
foobar = {foobar, " 167"};
end
endtask
task ozoneae;
input [ 2:0] ae;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ae)
3'b000 : foobar = {foobar, " 168"};
3'b001 : foobar = {foobar, " 169"};
3'b010 : foobar = {foobar, " 170"};
3'b011 : foobar = {foobar, " 171"};
3'b100 : foobar = {foobar, " 172"};
3'b101 : foobar = {foobar, " 173"};
3'b110 : foobar = {foobar, " 174"};
3'b111 : foobar = {foobar, " 175"};
endcase
end
endtask
task ozoneaee;
input [ 2:0] aee;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (aee)
3'b001,
3'b011,
3'b101,
3'b111 : foobar = {foobar, " 176"};
3'b000 : foobar = {foobar, " 177"};
3'b010 : foobar = {foobar, " 178"};
3'b100 : foobar = {foobar, " 179"};
3'b110 : foobar = {foobar, " 180"};
endcase
end
endtask
task ozoneape;
input [ 2:0] ape;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ape)
3'b001,
3'b011,
3'b101,
3'b111 : foobar = {foobar, " 181"};
3'b000 : foobar = {foobar, " 182"};
3'b010 : foobar = {foobar, " 183"};
3'b100 : foobar = {foobar, " 184"};
3'b110 : foobar = {foobar, " 185"};
endcase
end
endtask
task ozonef1;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
if (foo[26])
foobar = {foobar, " 186"};
else
foobar = {foobar, " 187"};
4'h1 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 188"};
2'b01 : foobar = {foobar, " 189"};
2'b10 : foobar = {foobar, " 190"};
2'b11 : foobar = {foobar, " 191"};
endcase
4'h2 : foobar = {foobar, " 192"};
4'h3 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 193"};
2'b01 : foobar = {foobar, " 194"};
2'b10 : foobar = {foobar, " 195"};
2'b11 : foobar = {foobar, " 196"};
endcase
4'h4 :
if (foo[26])
foobar = {foobar, " 197"};
else
foobar = {foobar, " 198"};
4'h5 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 199"};
2'b01 : foobar = {foobar, " 200"};
2'b10 : foobar = {foobar, " 201"};
2'b11 : foobar = {foobar, " 202"};
endcase
4'h6 : foobar = {foobar, " 203"};
4'h7 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 204"};
2'b01 : foobar = {foobar, " 205"};
2'b10 : foobar = {foobar, " 206"};
2'b11 : foobar = {foobar, " 207"};
endcase
4'h8 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 208"};
2'b01 : foobar = {foobar, " 209"};
2'b10 : foobar = {foobar, " 210"};
2'b11 : foobar = {foobar, " 211"};
endcase
4'h9 :
case (foo[26:25])
2'b00 : foobar = {foobar, " 212"};
2'b01 : foobar = {foobar, " 213"};
2'b10 : foobar = {foobar, " 214"};
2'b11 : foobar = {foobar, " 215"};
endcase
4'ha :
if (foo[25])
foobar = {foobar, " 216"};
else
foobar = {foobar, " 217"};
4'hb :
if (foo[25])
foobar = {foobar, " 218"};
else
foobar = {foobar, " 219"};
4'hc :
if (foo[26])
foobar = {foobar, " 220"};
else
foobar = {foobar, " 221"};
4'hd :
case (foo[26:25])
2'b00 : foobar = {foobar, " 222"};
2'b01 : foobar = {foobar, " 223"};
2'b10 : foobar = {foobar, " 224"};
2'b11 : foobar = {foobar, " 225"};
endcase
4'he :
case (foo[26:25])
2'b00 : foobar = {foobar, " 226"};
2'b01 : foobar = {foobar, " 227"};
2'b10 : foobar = {foobar, " 228"};
2'b11 : foobar = {foobar, " 229"};
endcase
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar, " 230"};
2'b01 : foobar = {foobar, " 231"};
2'b10 : foobar = {foobar, " 232"};
2'b11 : foobar = {foobar, " 233"};
endcase
endcase
end
endtask
task ozonef1e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[27:21])
7'h00:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 234"};
foobar = {foobar, " 235"};
end
7'h01:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 236"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 237"};
foobar = {foobar, " 238"};
end
7'h02:
foobar = {foobar, " 239"};
7'h03:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 240"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 241"};
foobar = {foobar, " 242"};
end
7'h04:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 243"};
foobar = {foobar," 244"};
end
7'h05:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 245"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 246"};
end
7'h06:
foobar = {foobar, " 247"};
7'h07:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 248"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 249"};
end
7'h08:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 250"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 251"};
end
7'h09:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 252"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 253"};
end
7'h0a:
begin
ozoneae(foo[17:15], foobar);
foobar = {foobar," 254"};
end
7'h0b:
begin
ozoneae(foo[17:15], foobar);
foobar = {foobar," 255"};
end
7'h0c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 256"};
end
7'h0d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 257"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 258"};
end
7'h0e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 259"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 260"};
end
7'h0f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 261"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 262"};
end
7'h10:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 263"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 264"};
foobar = {foobar, " 265"};
foobar = {foobar, " 266"};
end
7'h11:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 267"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 268"};
foobar = {foobar, " 269"};
foobar = {foobar, " 270"};
end
7'h12:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 271"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 272"};
foobar = {foobar, " 273"};
foobar = {foobar, " 274"};
end
7'h13:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 275"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 276"};
foobar = {foobar, " 277"};
foobar = {foobar, " 278"};
end
7'h14:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 279"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 280"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 281"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 282"};
foobar = {foobar, " 283"};
foobar = {foobar, " 284"};
end
7'h15:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 285"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 286"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 287"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 288"};
foobar = {foobar, " 289"};
foobar = {foobar, " 290"};
end
7'h16:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 291"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 292"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 293"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 294"};
foobar = {foobar, " 295"};
foobar = {foobar, " 296"};
end
7'h17:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 297"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 298"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 299"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 300"};
foobar = {foobar, " 301"};
foobar = {foobar, " 302"};
end
7'h18:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 303"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 304"};
foobar = {foobar, " 305"};
foobar = {foobar, " 306"};
end
7'h19:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 307"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 308"};
foobar = {foobar, " 309"};
foobar = {foobar, " 310"};
end
7'h1a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 311"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 312"};
foobar = {foobar, " 313"};
foobar = {foobar, " 314"};
end
7'h1b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 315"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 316"};
foobar = {foobar, " 317"};
foobar = {foobar, " 318"};
end
7'h1c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 319"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 320"};
foobar = {foobar, " 321"};
foobar = {foobar, " 322"};
end
7'h1d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 323"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 324"};
foobar = {foobar, " 325"};
foobar = {foobar, " 326"};
end
7'h1e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 327"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 328"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 329"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 330"};
foobar = {foobar, " 331"};
foobar = {foobar, " 332"};
end
7'h1f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 333"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 334"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 335"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 336"};
foobar = {foobar, " 337"};
foobar = {foobar, " 338"};
end
7'h20:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 339"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 340"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 341"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 342"};
foobar = {foobar, " 343"};
foobar = {foobar, " 344"};
end
7'h21:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 345"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 346"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 347"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 348"};
foobar = {foobar, " 349"};
foobar = {foobar, " 350"};
end
7'h22:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 351"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 352"};
foobar = {foobar, " 353"};
foobar = {foobar, " 354"};
end
7'h23:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 355"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 356"};
foobar = {foobar, " 357"};
foobar = {foobar, " 358"};
end
7'h24:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 359"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 360"};
foobar = {foobar, " 361"};
foobar = {foobar, " 362"};
end
7'h25:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 363"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 364"};
foobar = {foobar, " 365"};
foobar = {foobar, " 366"};
end
7'h26:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 367"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 368"};
foobar = {foobar, " 369"};
foobar = {foobar, " 370"};
end
7'h27:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 371"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 372"};
foobar = {foobar, " 373"};
foobar = {foobar, " 374"};
end
7'h28:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 375"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 376"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 377"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 378"};
foobar = {foobar, " 379"};
foobar = {foobar, " 380"};
end
7'h29:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 381"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 382"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 383"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 384"};
foobar = {foobar, " 385"};
foobar = {foobar, " 386"};
end
7'h2a:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 387"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 388"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 389"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 390"};
foobar = {foobar, " 391"};
foobar = {foobar, " 392"};
end
7'h2b:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 393"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 394"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 395"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 396"};
foobar = {foobar, " 397"};
foobar = {foobar, " 398"};
end
7'h2c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 399"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 400"};
foobar = {foobar, " 401"};
foobar = {foobar, " 402"};
end
7'h2d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 403"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 404"};
foobar = {foobar, " 405"};
foobar = {foobar, " 406"};
end
7'h2e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 407"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 408"};
foobar = {foobar, " 409"};
foobar = {foobar, " 410"};
end
7'h2f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 411"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 412"};
foobar = {foobar, " 413"};
foobar = {foobar, " 414"};
end
7'h30:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 415"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 416"};
foobar = {foobar, " 417"};
foobar = {foobar, " 418"};
end
7'h31:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 419"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 420"};
foobar = {foobar, " 421"};
foobar = {foobar, " 422"};
end
7'h32:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 423"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 424"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 425"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 426"};
foobar = {foobar, " 427"};
foobar = {foobar, " 428"};
end
7'h33:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 429"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 430"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 431"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 432"};
foobar = {foobar, " 433"};
foobar = {foobar, " 434"};
end
7'h34:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 435"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 436"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 437"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 438"};
foobar = {foobar, " 439"};
foobar = {foobar, " 440"};
end
7'h35:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 441"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 442"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 443"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 444"};
foobar = {foobar, " 445"};
foobar = {foobar, " 446"};
end
7'h36:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 447"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 448"};
foobar = {foobar, " 449"};
foobar = {foobar, " 450"};
end
7'h37:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 451"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 452"};
foobar = {foobar, " 453"};
foobar = {foobar, " 454"};
end
7'h38:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 455"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 456"};
foobar = {foobar, " 457"};
end
7'h39:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 458"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 459"};
foobar = {foobar, " 460"};
end
7'h3a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 461"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 462"};
foobar = {foobar, " 463"};
end
7'h3b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 464"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 465"};
foobar = {foobar, " 466"};
end
7'h3c:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 467"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 468"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 469"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 470"};
foobar = {foobar, " 471"};
end
7'h3d:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 472"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 473"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 474"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 475"};
foobar = {foobar, " 476"};
end
7'h3e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 477"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 478"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 479"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 480"};
foobar = {foobar, " 481"};
end
7'h3f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 482"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 483"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 484"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 485"};
foobar = {foobar, " 486"};
end
7'h40:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 487"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 488"};
foobar = {foobar, " 489"};
foobar = {foobar, " 490"};
end
7'h41:
begin
foobar = {foobar, " 491"};
foobar = {foobar, " 492"};
end
7'h42:
begin
foobar = {foobar, " 493"};
foobar = {foobar, " 494"};
end
7'h43:
begin
foobar = {foobar, " 495"};
foobar = {foobar, " 496"};
end
7'h44:
begin
foobar = {foobar, " 497"};
foobar = {foobar, " 498"};
end
7'h45:
foobar = {foobar, " 499"};
7'h46:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 500"};
foobar = {foobar, " 501"};
foobar = {foobar, " 502"};
end
7'h47:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 503"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 504"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 505"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 506"};
foobar = {foobar, " 507"};
foobar = {foobar, " 508"};
end
7'h48:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 509"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 510"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 511"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 512"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 513"};
end
7'h49:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 514"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 515"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 516"};
end
7'h4a:
foobar = {foobar," 517"};
7'h4b:
foobar = {foobar, " 518"};
7'h4c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 519"};
foobar = {foobar, " 520"};
foobar = {foobar, " 521"};
end
7'h4d:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 522"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 523"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 524"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 525"};
foobar = {foobar, " 526"};
foobar = {foobar, " 527"};
end
7'h4e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 528"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 529"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 530"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 531"};
end
7'h4f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 532"};
end
7'h50:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 533"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 534"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 535"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 536"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 537"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 538"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 539"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 540"};
end
7'h51:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 541"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 542"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 543"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 544"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 545"};
end
7'h52:
foobar = {foobar, " 546"};
7'h53:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 547"};
end
7'h54:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 548"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 549"};
end
7'h55:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 550"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 551"};
end
7'h56:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 552"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 553"};
foobar = {foobar, " 554"};
end
7'h57:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 555"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 556"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 557"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 558"};
end
7'h58:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 559"};
end
7'h59:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 560"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 561"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 562"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 563"};
end
7'h5a:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 564"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 565"};
end
7'h5b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 566"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 567"};
end
7'h5c:
begin
foobar = {foobar," 568"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 569"};
foobar = {foobar," 570"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 571"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 572"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar, " 573"};
end
7'h5d:
begin
foobar = {foobar," 574"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 575"};
foobar = {foobar," 576"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 577"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 578"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar, " 579"};
end
7'h5e:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 580"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 581"};
end
7'h5f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 582"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 583"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 584"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 585"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 586"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 587"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 588"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 589"};
end
7'h60:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 590"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 591"};
end
7'h61:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 592"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 593"};
end
7'h62:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 594"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 595"};
end
7'h63:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 596"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 597"};
end
7'h64:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 598"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 599"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 600"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 601"};
end
7'h65:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 602"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 603"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 604"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 605"};
end
7'h66:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 606"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 607"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 608"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 609"};
end
7'h67:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 610"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 611"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 612"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 613"};
end
7'h68:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 614"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 615"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 616"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 617"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 618"};
ozoneape(foo[17:15], foobar);
end
7'h69:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 619"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 620"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 621"};
end
7'h6a:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 622"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 623"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 624"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 625"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 626"};
ozoneae(foo[17:15], foobar);
end
7'h6b:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 627"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 628"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 629"};
end
7'h6c:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 630"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 631"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 632"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 633"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 634"};
ozoneae(foo[17:15], foobar);
end
7'h6d:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 635"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 636"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 637"};
end
7'h6e:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 638"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 639"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 640"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 641"};
end
7'h6f:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 642"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 643"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 644"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 645"};
end
7'h70:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 646"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 647"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 648"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 649"};
end
7'h71:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 650"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 651"};
end
7'h72:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 652"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 653"};
end
7'h73:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 654"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 655"};
ozoneae(foo[17:15], foobar);
end
7'h74:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 656"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 657"};
ozoneae(foo[17:15], foobar);
end
7'h75:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 658"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 659"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 660"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 661"};
foobar = {foobar, " 662"};
foobar = {foobar, " 663"};
end
7'h76:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 664"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 665"};
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 666"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 667"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 668"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 669"};
end
7'h77:
begin
ozoneaee(foo[20:18], foobar);
foobar = {foobar," 670"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 671"};
ozoneaee(foo[17:15], foobar);
foobar = {foobar," 672"};
ozoneape(foo[20:18], foobar);
foobar = {foobar," 673"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 674"};
ozoneape(foo[17:15], foobar);
foobar = {foobar," 675"};
end
7'h78,
7'h79,
7'h7a,
7'h7b,
7'h7c,
7'h7d,
7'h7e,
7'h7f:
foobar = {foobar," 676"};
endcase
end
endtask
task ozonef2;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[24:21])
4'h0 :
case (foo[26:25])
2'b00 : foobar = {foobar," 677"};
2'b01 : foobar = {foobar," 678"};
2'b10 : foobar = {foobar," 679"};
2'b11 : foobar = {foobar," 680"};
endcase
4'h1 :
case (foo[26:25])
2'b00 : foobar = {foobar," 681"};
2'b01 : foobar = {foobar," 682"};
2'b10 : foobar = {foobar," 683"};
2'b11 : foobar = {foobar," 684"};
endcase
4'h2 :
case (foo[26:25])
2'b00 : foobar = {foobar," 685"};
2'b01 : foobar = {foobar," 686"};
2'b10 : foobar = {foobar," 687"};
2'b11 : foobar = {foobar," 688"};
endcase
4'h3 :
case (foo[26:25])
2'b00 : foobar = {foobar," 689"};
2'b01 : foobar = {foobar," 690"};
2'b10 : foobar = {foobar," 691"};
2'b11 : foobar = {foobar," 692"};
endcase
4'h4 :
case (foo[26:25])
2'b00 : foobar = {foobar," 693"};
2'b01 : foobar = {foobar," 694"};
2'b10 : foobar = {foobar," 695"};
2'b11 : foobar = {foobar," 696"};
endcase
4'h5 :
case (foo[26:25])
2'b00 : foobar = {foobar," 697"};
2'b01 : foobar = {foobar," 698"};
2'b10 : foobar = {foobar," 699"};
2'b11 : foobar = {foobar," 700"};
endcase
4'h6 :
case (foo[26:25])
2'b00 : foobar = {foobar," 701"};
2'b01 : foobar = {foobar," 702"};
2'b10 : foobar = {foobar," 703"};
2'b11 : foobar = {foobar," 704"};
endcase
4'h7 :
case (foo[26:25])
2'b00 : foobar = {foobar," 705"};
2'b01 : foobar = {foobar," 706"};
2'b10 : foobar = {foobar," 707"};
2'b11 : foobar = {foobar," 708"};
endcase
4'h8 :
if (foo[26])
foobar = {foobar," 709"};
else
foobar = {foobar," 710"};
4'h9 :
case (foo[26:25])
2'b00 : foobar = {foobar," 711"};
2'b01 : foobar = {foobar," 712"};
2'b10 : foobar = {foobar," 713"};
2'b11 : foobar = {foobar," 714"};
endcase
4'ha :
case (foo[26:25])
2'b00 : foobar = {foobar," 715"};
2'b01 : foobar = {foobar," 716"};
2'b10 : foobar = {foobar," 717"};
2'b11 : foobar = {foobar," 718"};
endcase
4'hb :
case (foo[26:25])
2'b00 : foobar = {foobar," 719"};
2'b01 : foobar = {foobar," 720"};
2'b10 : foobar = {foobar," 721"};
2'b11 : foobar = {foobar," 722"};
endcase
4'hc :
if (foo[26])
foobar = {foobar," 723"};
else
foobar = {foobar," 724"};
4'hd :
case (foo[26:25])
2'b00 : foobar = {foobar," 725"};
2'b01 : foobar = {foobar," 726"};
2'b10 : foobar = {foobar," 727"};
2'b11 : foobar = {foobar," 728"};
endcase
4'he :
case (foo[26:25])
2'b00 : foobar = {foobar," 729"};
2'b01 : foobar = {foobar," 730"};
2'b10 : foobar = {foobar," 731"};
2'b11 : foobar = {foobar," 732"};
endcase
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar," 733"};
2'b01 : foobar = {foobar," 734"};
2'b10 : foobar = {foobar," 735"};
2'b11 : foobar = {foobar," 736"};
endcase
endcase
end
endtask
task ozonef2e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
casez (foo[25:21])
5'h00 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 737"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 738"};
end
5'h01 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 739"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 740"};
end
5'h02 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 741"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 742"};
end
5'h03 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 743"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 744"};
end
5'h04 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 745"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 746"};
end
5'h05 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 747"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 748"};
end
5'h06 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 749"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 750"};
end
5'h07 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 751"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 752"};
end
5'h08 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 753"};
if (foo[ 6])
foobar = {foobar," 754"};
else
foobar = {foobar," 755"};
end
5'h09 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 756"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 757"};
end
5'h0a :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 758"};
ozoneae(foo[17:15], foobar);
end
5'h0b :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 759"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 760"};
end
5'h0c :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 761"};
end
5'h0d :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 762"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 763"};
end
5'h0e :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 764"};
ozoneae(foo[17:15], foobar);
end
5'h0f :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 765"};
ozoneae(foo[17:15], foobar);
end
5'h10 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 766"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 767"};
end
5'h11 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 768"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 769"};
end
5'h18 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 770"};
if (foo[ 6])
foobar = {foobar," 771"};
else
foobar = {foobar," 772"};
end
5'h1a :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 773"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 774"};
end
5'h1b :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 775"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 776"};
if (foo[ 6])
foobar = {foobar," 777"};
else
foobar = {foobar," 778"};
foobar = {foobar," 779"};
end
5'h1c :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 780"};
end
5'h1d :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 781"};
if (foo[ 6])
foobar = {foobar," 782"};
else
foobar = {foobar," 783"};
foobar = {foobar," 784"};
end
5'h1e :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 785"};
if (foo[ 6])
foobar = {foobar," 786"};
else
foobar = {foobar," 787"};
foobar = {foobar," 788"};
end
5'h1f :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 789"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 790"};
if (foo[ 6])
foobar = {foobar," 791"};
else
foobar = {foobar," 792"};
foobar = {foobar," 793"};
end
default :
foobar = {foobar," 794"};
endcase
end
endtask
task ozonef3e;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[25:21])
5'h00,
5'h01,
5'h02:
begin
ozoneae(foo[20:18], foobar);
case (foo[22:21])
2'h0: foobar = {foobar," 795"};
2'h1: foobar = {foobar," 796"};
2'h2: foobar = {foobar," 797"};
endcase
ozoneae(foo[17:15], foobar);
foobar = {foobar," 798"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
foobar = {foobar," 799"};
end
5'h08,
5'h09,
5'h0d,
5'h0e,
5'h0f:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 800"};
ozoneae(foo[17:15], foobar);
case (foo[23:21])
3'h0: foobar = {foobar," 801"};
3'h1: foobar = {foobar," 802"};
3'h5: foobar = {foobar," 803"};
3'h6: foobar = {foobar," 804"};
3'h7: foobar = {foobar," 805"};
endcase
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
end
5'h0a,
5'h0b:
begin
ozoneae(foo[17:15], foobar);
if (foo[21])
foobar = {foobar," 806"};
else
foobar = {foobar," 807"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
end
5'h0c:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 808"};
if (foo[ 9])
ozoneae(foo[ 8: 6], foobar);
else
ozonef3e_te(foo[ 8: 6], foobar);
foobar = {foobar," 809"};
ozoneae(foo[17:15], foobar);
end
5'h10,
5'h11,
5'h12,
5'h13:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 810"};
ozoneae(foo[17:15], foobar);
case (foo[22:21])
2'h0,
2'h2:
foobar = {foobar," 811"};
2'h1,
2'h3:
foobar = {foobar," 812"};
endcase
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar," 813"};
ozoneae((foo[20:18]+1), foobar);
foobar = {foobar," 814"};
ozoneae((foo[17:15]+1), foobar);
case (foo[22:21])
2'h0,
2'h3:
foobar = {foobar," 815"};
2'h1,
2'h2:
foobar = {foobar," 816"};
endcase
ozoneae((foo[ 8: 6]+1), foobar);
end
5'h18:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar," 817"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 818"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar," 819"};
ozoneae(foo[20:18], foobar);
foobar = {foobar," 820"};
ozoneae(foo[17:15], foobar);
foobar = {foobar," 821"};
ozoneae(foo[ 8: 6], foobar);
end
default :
foobar = {foobar," 822"};
endcase
end
endtask
task ozonef3e_te;
input [ 2:0] te;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (te)
3'b100 : foobar = {foobar, " 823"};
3'b101 : foobar = {foobar, " 824"};
3'b110 : foobar = {foobar, " 825"};
default: foobar = {foobar, " 826"};
endcase
end
endtask
task ozonearm;
input [ 2:0] ate;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ate)
3'b000 : foobar = {foobar, " 827"};
3'b001 : foobar = {foobar, " 828"};
3'b010 : foobar = {foobar, " 829"};
3'b011 : foobar = {foobar, " 830"};
3'b100 : foobar = {foobar, " 831"};
3'b101 : foobar = {foobar, " 832"};
3'b110 : foobar = {foobar, " 833"};
3'b111 : foobar = {foobar, " 834"};
endcase
end
endtask
task ozonebmuop;
input [ 4:0] f4;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (f4[ 4:0])
5'h00,
5'h04 :
foobar = {foobar, " 835"};
5'h01,
5'h05 :
foobar = {foobar, " 836"};
5'h02,
5'h06 :
foobar = {foobar, " 837"};
5'h03,
5'h07 :
foobar = {foobar, " 838"};
5'h08,
5'h18 :
foobar = {foobar, " 839"};
5'h09,
5'h19 :
foobar = {foobar, " 840"};
5'h0a,
5'h1a :
foobar = {foobar, " 841"};
5'h0b :
foobar = {foobar, " 842"};
5'h1b :
foobar = {foobar, " 843"};
5'h0c,
5'h1c :
foobar = {foobar, " 844"};
5'h0d,
5'h1d :
foobar = {foobar, " 845"};
5'h1e :
foobar = {foobar, " 846"};
endcase
end
endtask
task ozonef3;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
reg nacho;
// verilator no_inline_task
begin : f3_body
nacho = 1'b0;
case (foo[24:21])
4'h0:
case (foo[26:25])
2'b00 : foobar = {foobar, " 847"};
2'b01 : foobar = {foobar, " 848"};
2'b10 : foobar = {foobar, " 849"};
2'b11 : foobar = {foobar, " 850"};
endcase
4'h1:
case (foo[26:25])
2'b00 : foobar = {foobar, " 851"};
2'b01 : foobar = {foobar, " 852"};
2'b10 : foobar = {foobar, " 853"};
2'b11 : foobar = {foobar, " 854"};
endcase
4'h2:
case (foo[26:25])
2'b00 : foobar = {foobar, " 855"};
2'b01 : foobar = {foobar, " 856"};
2'b10 : foobar = {foobar, " 857"};
2'b11 : foobar = {foobar, " 858"};
endcase
4'h8,
4'h9,
4'hd,
4'he,
4'hf :
case (foo[26:25])
2'b00 : foobar = {foobar, " 859"};
2'b01 : foobar = {foobar, " 860"};
2'b10 : foobar = {foobar, " 861"};
2'b11 : foobar = {foobar, " 862"};
endcase
4'ha,
4'hb :
if (foo[25])
foobar = {foobar, " 863"};
else
foobar = {foobar, " 864"};
4'hc :
if (foo[26])
foobar = {foobar, " 865"};
else
foobar = {foobar, " 866"};
default :
begin
foobar = {foobar, " 867"};
nacho = 1'b1;
end
endcase
if (~nacho)
begin
case (foo[24:21])
4'h8 :
foobar = {foobar, " 868"};
4'h9 :
foobar = {foobar, " 869"};
4'ha,
4'he :
foobar = {foobar, " 870"};
4'hb,
4'hf :
foobar = {foobar, " 871"};
4'hd :
foobar = {foobar, " 872"};
endcase
if (foo[20])
case (foo[18:16])
3'b000 : foobar = {foobar, " 873"};
3'b100 : foobar = {foobar, " 874"};
default: foobar = {foobar, " 875"};
endcase
else
ozoneae(foo[18:16], foobar);
if (foo[24:21] === 4'hc)
if (foo[25])
foobar = {foobar, " 876"};
else
foobar = {foobar, " 877"};
case (foo[24:21])
4'h0,
4'h1,
4'h2:
foobar = {foobar, " 878"};
endcase
end
end
endtask
task ozonerx;
input [ 31:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[19:18])
2'h0 : foobar = {foobar, " 879"};
2'h1 : foobar = {foobar, " 880"};
2'h2 : foobar = {foobar, " 881"};
2'h3 : foobar = {foobar, " 882"};
endcase
case (foo[17:16])
2'h1 : foobar = {foobar, " 883"};
2'h2 : foobar = {foobar, " 884"};
2'h3 : foobar = {foobar, " 885"};
endcase
end
endtask
task ozonerme;
input [ 2:0] rme;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rme)
3'h0 : foobar = {foobar, " 886"};
3'h1 : foobar = {foobar, " 887"};
3'h2 : foobar = {foobar, " 888"};
3'h3 : foobar = {foobar, " 889"};
3'h4 : foobar = {foobar, " 890"};
3'h5 : foobar = {foobar, " 891"};
3'h6 : foobar = {foobar, " 892"};
3'h7 : foobar = {foobar, " 893"};
endcase
end
endtask
task ozoneye;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = {foobar, " 894"};
ozonerme(ye[5:3],foobar);
case ({ye[ 2:0], l})
4'h2,
4'ha: foobar = {foobar, " 895"};
4'h4,
4'hb: foobar = {foobar, " 896"};
4'h6,
4'he: foobar = {foobar, " 897"};
4'h8,
4'hc: foobar = {foobar, " 898"};
endcase
end
endtask
task ozonef1e_ye;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = {foobar, " 899"};
ozonerme(ye[5:3],foobar);
ozonef1e_inc_dec(ye[5:0], l ,foobar);
end
endtask
task ozonef1e_h;
input [ 2:0] e;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
if (e[ 2:0] <= 3'h4)
foobar = {foobar, " 900"};
end
endtask
task ozonef1e_inc_dec;
input [5:0] ye;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case ({ye[ 2:0], l})
4'h2,
4'h3,
4'ha: foobar = {foobar, " 901"};
4'h4,
4'h5,
4'hb: foobar = {foobar, " 902"};
4'h6,
4'h7,
4'he: foobar = {foobar, " 903"};
4'h8,
4'h9,
4'hc: foobar = {foobar, " 904"};
4'hf: foobar = {foobar, " 905"};
endcase
end
endtask
task ozonef1e_hl;
input [ 2:0] e;
input l;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case ({e[ 2:0], l})
4'h0,
4'h2,
4'h4,
4'h6,
4'h8: foobar = {foobar, " 906"};
4'h1,
4'h3,
4'h5,
4'h7,
4'h9: foobar = {foobar, " 907"};
endcase
end
endtask
task ozonexe;
input [ 3:0] xe;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (xe[3])
1'b0 : foobar = {foobar, " 908"};
1'b1 : foobar = {foobar, " 909"};
endcase
case (xe[ 2:0])
3'h1,
3'h5: foobar = {foobar, " 910"};
3'h2,
3'h6: foobar = {foobar, " 911"};
3'h3,
3'h7: foobar = {foobar, " 912"};
3'h4: foobar = {foobar, " 913"};
endcase
end
endtask
task ozonerp;
input [ 2:0] rp;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (rp)
3'h0 : foobar = {foobar, " 914"};
3'h1 : foobar = {foobar, " 915"};
3'h2 : foobar = {foobar, " 916"};
3'h3 : foobar = {foobar, " 917"};
3'h4 : foobar = {foobar, " 918"};
3'h5 : foobar = {foobar, " 919"};
3'h6 : foobar = {foobar, " 920"};
3'h7 : foobar = {foobar, " 921"};
endcase
end
endtask
task ozonery;
input [ 3:0] ry;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (ry)
4'h0 : foobar = {foobar, " 922"};
4'h1 : foobar = {foobar, " 923"};
4'h2 : foobar = {foobar, " 924"};
4'h3 : foobar = {foobar, " 925"};
4'h4 : foobar = {foobar, " 926"};
4'h5 : foobar = {foobar, " 927"};
4'h6 : foobar = {foobar, " 928"};
4'h7 : foobar = {foobar, " 929"};
4'h8 : foobar = {foobar, " 930"};
4'h9 : foobar = {foobar, " 931"};
4'ha : foobar = {foobar, " 932"};
4'hb : foobar = {foobar, " 933"};
4'hc : foobar = {foobar, " 934"};
4'hd : foobar = {foobar, " 935"};
4'he : foobar = {foobar, " 936"};
4'hf : foobar = {foobar, " 937"};
endcase
end
endtask
task ozonearx;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[1:0])
2'h0 : foobar = {foobar, " 938"};
2'h1 : foobar = {foobar, " 939"};
2'h2 : foobar = {foobar, " 940"};
2'h3 : foobar = {foobar, " 941"};
endcase
end
endtask
task ozonef3f4imop;
input [ 4:0] f3f4iml;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
casez (f3f4iml)
5'b000??: foobar = {foobar, " 942"};
5'b001??: foobar = {foobar, " 943"};
5'b?10??: foobar = {foobar, " 944"};
5'b0110?: foobar = {foobar, " 945"};
5'b01110: foobar = {foobar, " 946"};
5'b01111: foobar = {foobar, " 947"};
5'b10???: foobar = {foobar, " 948"};
5'b11100: foobar = {foobar, " 949"};
5'b11101: foobar = {foobar, " 950"};
5'b11110: foobar = {foobar, " 951"};
5'b11111: foobar = {foobar, " 952"};
endcase
end
endtask
task ozonecon;
input [ 4:0] con;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (con)
5'h00 : foobar = {foobar, " 953"};
5'h01 : foobar = {foobar, " 954"};
5'h02 : foobar = {foobar, " 955"};
5'h03 : foobar = {foobar, " 956"};
5'h04 : foobar = {foobar, " 957"};
5'h05 : foobar = {foobar, " 958"};
5'h06 : foobar = {foobar, " 959"};
5'h07 : foobar = {foobar, " 960"};
5'h08 : foobar = {foobar, " 961"};
5'h09 : foobar = {foobar, " 962"};
5'h0a : foobar = {foobar, " 963"};
5'h0b : foobar = {foobar, " 964"};
5'h0c : foobar = {foobar, " 965"};
5'h0d : foobar = {foobar, " 966"};
5'h0e : foobar = {foobar, " 967"};
5'h0f : foobar = {foobar, " 968"};
5'h10 : foobar = {foobar, " 969"};
5'h11 : foobar = {foobar, " 970"};
5'h12 : foobar = {foobar, " 971"};
5'h13 : foobar = {foobar, " 972"};
5'h14 : foobar = {foobar, " 973"};
5'h15 : foobar = {foobar, " 974"};
5'h16 : foobar = {foobar, " 975"};
5'h17 : foobar = {foobar, " 976"};
5'h18 : foobar = {foobar, " 977"};
5'h19 : foobar = {foobar, " 978"};
5'h1a : foobar = {foobar, " 979"};
5'h1b : foobar = {foobar, " 980"};
5'h1c : foobar = {foobar, " 981"};
5'h1d : foobar = {foobar, " 982"};
5'h1e : foobar = {foobar, " 983"};
5'h1f : foobar = {foobar, " 984"};
endcase
end
endtask
task ozonedr;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[ 9: 6])
4'h0 : foobar = {foobar, " 985"};
4'h1 : foobar = {foobar, " 986"};
4'h2 : foobar = {foobar, " 987"};
4'h3 : foobar = {foobar, " 988"};
4'h4 : foobar = {foobar, " 989"};
4'h5 : foobar = {foobar, " 990"};
4'h6 : foobar = {foobar, " 991"};
4'h7 : foobar = {foobar, " 992"};
4'h8 : foobar = {foobar, " 993"};
4'h9 : foobar = {foobar, " 994"};
4'ha : foobar = {foobar, " 995"};
4'hb : foobar = {foobar, " 996"};
4'hc : foobar = {foobar, " 997"};
4'hd : foobar = {foobar, " 998"};
4'he : foobar = {foobar, " 999"};
4'hf : foobar = {foobar, " 1000"};
endcase
end
endtask
task ozoneshift;
input [ 15:0] foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo[ 4: 3])
2'h0 : foobar = {foobar, " 1001"};
2'h1 : foobar = {foobar, " 1002"};
2'h2 : foobar = {foobar, " 1003"};
2'h3 : foobar = {foobar, " 1004"};
endcase
end
endtask
task ozoneacc;
input foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 : foobar = {foobar, " 1005"};
2'h1 : foobar = {foobar, " 1006"};
endcase
end
endtask
task ozonehl;
input foo;
inout [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
case (foo)
2'h0 : foobar = {foobar, " 1007"};
2'h1 : foobar = {foobar, " 1008"};
endcase
end
endtask
task dude;
inout [STRLEN*8: 1] foobar;
reg [ 7:0] temp;
integer i;
reg nacho;
// verilator no_inline_task
begin : justify_block
nacho = 1'b0;
for (i=STRLEN-1; i>1; i=i-1)
begin
temp = foobar>>((STRLEN-1)*8);
if (temp || nacho)
nacho = 1'b1;
else
begin
foobar = foobar<<8;
foobar[8:1] = 32;
end
end
end
endtask
task big_case;
input [ 31:0] fd;
input [ 31:0] foo;
reg [STRLEN*8: 1] foobar;
// verilator no_inline_task
begin
foobar = " 1009";
if (&foo === 1'bx)
$fwrite(fd, " 1010");
else
casez ( {foo[31:26], foo[19:15], foo[5:0]} )
17'b00_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1011"};
ozoneacc(~foo[26], foobar);
ozonehl(foo[20], foobar);
foobar = {foobar, " 1012"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1013:%s", foobar);
end
17'b01_001?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1014"};
ozonerx(foo, foobar);
foobar = {foobar, " 1015"};
foobar = {foobar, " 1016"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1017:%s", foobar);
end
17'b10_100?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1018"};
ozonerx(foo, foobar);
foobar = {foobar, " 1019"};
foobar = {foobar, " 1020"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1021:%s", foobar);
end
17'b10_101?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1022"};
if (foo[20])
begin
foobar = {foobar, " 1023"};
ozoneacc(foo[18], foobar);
foobar = {foobar, " 1024"};
foobar = {foobar, " 1025"};
if (foo[19])
foobar = {foobar, " 1026"};
else
foobar = {foobar, " 1027"};
end
else
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1028:%s", foobar);
end
17'b10_110?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1029"};
foobar = {foobar, " 1030"};
ozonehl(foo[20], foobar);
foobar = {foobar, " 1031"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1032:%s", foobar);
end
17'b10_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1033"};
foobar = {foobar, " 1034"};
ozonehl(foo[20], foobar);
foobar = {foobar, " 1035"};
ozonerx(foo, foobar);
dude(foobar);
$fwrite (fd, " 1036:%s", foobar);
end
17'b11_001?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1037"};
ozonerx(foo, foobar);
foobar = {foobar, " 1038"};
foobar = {foobar, " 1039"};
ozonehl(foo[20], foobar);
dude(foobar);
$fwrite (fd, " 1040:%s", foobar);
end
17'b11_111?_?_????_??_???? :
begin
ozonef1(foo, foobar);
foobar = {foobar, " 1041"};
foobar = {foobar, " 1042"};
ozonerx(foo, foobar);
foobar = {foobar, " 1043"};
if (foo[20])
foobar = {foobar, " 1044"};
else
foobar = {foobar, " 1045"};
dude(foobar);
$fwrite (fd, " 1046:%s", foobar);
end
17'b00_10??_?_????_?1_1111 :
casez (foo[11: 5])
7'b??_0_010_0:
begin
foobar = " 1047";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1048"};
ozonef1e(foo, foobar);
dude(foobar);
$fwrite (fd, " 1049:%s", foobar);
end
7'b00_?_110_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1050"};
case ({foo[ 9],foo[ 5]})
2'b00:
begin
foobar = {foobar, " 1051"};
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
end
2'b01:
begin
foobar = {foobar, " 1052"};
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
end
2'b10:
begin
foobar = {foobar, " 1053"};
ozoneae(foo[14:12], foobar);
end
2'b11: foobar = {foobar, " 1054"};
endcase
dude(foobar);
$fwrite (fd, " 1055:%s", foobar);
end
7'b01_?_110_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1056"};
case ({foo[ 9],foo[ 5]})
2'b00:
begin
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
foobar = {foobar, " 1057"};
end
2'b01:
begin
ozoneae(foo[14:12], foobar);
ozonehl(foo[ 5], foobar);
foobar = {foobar, " 1058"};
end
2'b10:
begin
ozoneae(foo[14:12], foobar);
foobar = {foobar, " 1059"};
end
2'b11: foobar = {foobar, " 1060"};
endcase
dude(foobar);
$fwrite (fd, " 1061:%s", foobar);
end
7'b10_0_110_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1062"};
foobar = {foobar, " 1063"};
if (foo[12])
foobar = {foobar, " 1064"};
else
ozonerab({4'b1001, foo[14:12]}, foobar);
dude(foobar);
$fwrite (fd, " 1065:%s", foobar);
end
7'b10_0_110_1:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1066"};
if (foo[12])
foobar = {foobar, " 1067"};
else
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1068"};
dude(foobar);
$fwrite (fd, " 1069:%s", foobar);
end
7'b??_?_000_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1070"};
foobar = {foobar, " 1071"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1072"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1073:%s", foobar);
end
7'b??_?_100_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1074"};
foobar = {foobar, " 1075"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1076"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1077:%s", foobar);
end
7'b??_?_001_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1078"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1079"};
foobar = {foobar, " 1080"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1081:%s", foobar);
end
7'b??_?_011_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1082"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1083"};
foobar = {foobar, " 1084"};
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1085:%s", foobar);
end
7'b??_?_101_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1086"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1087:%s", foobar);
end
endcase
17'b00_10??_?_????_?0_0110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1088"};
ozoneae(foo[ 8: 6], foobar);
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
foobar = {foobar, " 1089"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1090:%s", foobar);
end
17'b00_10??_?_????_00_0111 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1091"};
if (foo[ 6])
foobar = {foobar, " 1092"};
else
ozonerab({4'b1001, foo[ 8: 6]}, foobar);
foobar = {foobar, " 1093"};
foobar = {foobar, " 1094"};
ozonerme(foo[14:12],foobar);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0,foobar);
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1095"};
endcase
dude(foobar);
$fwrite (fd, " 1096:%s", foobar);
end
17'b00_10??_?_????_?0_0100 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1097"};
ozonef1e_ye(foo[14:9],foo[ 5],foobar);
foobar = {foobar, " 1098"};
ozoneae(foo[ 8: 6], foobar);
ozonef1e_hl(foo[11:9],foo[ 5],foobar);
dude(foobar);
$fwrite (fd, " 1099:%s", foobar);
end
17'b00_10??_?_????_10_0111 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1100"};
foobar = {foobar, " 1101"};
ozonerme(foo[14:12],foobar);
case (foo[11: 9])
3'h2,
3'h5,
3'h6,
3'h7:
ozonef1e_inc_dec(foo[14:9],1'b0,foobar);
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1102"};
endcase
foobar = {foobar, " 1103"};
if (foo[ 6])
foobar = {foobar, " 1104"};
else
ozonerab({4'b1001, foo[ 8: 6]}, foobar);
dude(foobar);
$fwrite (fd, " 1105:%s", foobar);
end
17'b00_10??_?_????_?0_1110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1106"};
case (foo[11:9])
3'h2:
begin
foobar = {foobar, " 1107"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1108"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1109"};
end
3'h6:
begin
foobar = {foobar, " 1110"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1111"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1112"};
end
3'h0:
begin
foobar = {foobar, " 1113"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1114"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1115"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1116"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h1:
begin
foobar = {foobar, " 1117"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1118"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1119"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1120"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h4:
begin
foobar = {foobar, " 1121"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1122"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1123"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1124"};
else
ozonexe(foo[ 8: 5], foobar);
end
3'h5:
begin
foobar = {foobar, " 1125"};
if (foo[14:12] == 3'h0)
foobar = {foobar, " 1126"};
else
ozonerme(foo[14:12],foobar);
foobar = {foobar, " 1127"};
if (foo[ 7: 5] >= 3'h5)
foobar = {foobar, " 1128"};
else
ozonexe(foo[ 8: 5], foobar);
end
endcase
dude(foobar);
$fwrite (fd, " 1129:%s", foobar);
end
17'b00_10??_?_????_?0_1111 :
casez (foo[14: 9])
6'b001_10_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1130"};
foobar = {foobar, " 1131"};
ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar);
foobar = {foobar, " 1132"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1133:%s", foobar);
end
6'b???_11_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1134"};
ozoneae(foo[14:12], foobar);
ozonef1e_hl(foo[ 7: 5],foo[ 9],foobar);
foobar = {foobar, " 1135"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1136:%s", foobar);
end
6'b000_10_1,
6'b010_10_1,
6'b100_10_1,
6'b110_10_1:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1137"};
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1138"};
if ((foo[ 7: 5] >= 3'h1) & (foo[ 7: 5] <= 3'h3))
foobar = {foobar, " 1139"};
else
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1140:%s", foobar);
end
6'b000_10_0,
6'b010_10_0,
6'b100_10_0,
6'b110_10_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1141"};
foobar = {foobar, " 1142"};
ozonerab({4'b1001, foo[14:12]}, foobar);
foobar = {foobar, " 1143"};
foobar = {foobar, " 1144"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1145"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1146:%s", foobar);
end
6'b???_00_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1147"};
if (foo[ 9])
begin
foobar = {foobar, " 1148"};
ozoneae(foo[14:12], foobar);
end
else
begin
foobar = {foobar, " 1149"};
ozoneae(foo[14:12], foobar);
foobar = {foobar, " 1150"};
end
foobar = {foobar, " 1151"};
foobar = {foobar, " 1152"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1153"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1154:%s", foobar);
end
6'b???_01_?:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1155"};
ozoneae(foo[14:12], foobar);
if (foo[ 9])
foobar = {foobar, " 1156"};
else
foobar = {foobar, " 1157"};
foobar = {foobar, " 1158"};
foobar = {foobar, " 1159"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1160"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1161:%s", foobar);
end
6'b011_10_0:
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1162"};
case (foo[ 8: 5])
4'h0: foobar = {foobar, " 1163"};
4'h1: foobar = {foobar, " 1164"};
4'h2: foobar = {foobar, " 1165"};
4'h3: foobar = {foobar, " 1166"};
4'h4: foobar = {foobar, " 1167"};
4'h5: foobar = {foobar, " 1168"};
4'h8: foobar = {foobar, " 1169"};
4'h9: foobar = {foobar, " 1170"};
4'ha: foobar = {foobar, " 1171"};
4'hb: foobar = {foobar, " 1172"};
4'hc: foobar = {foobar, " 1173"};
4'hd: foobar = {foobar, " 1174"};
default: foobar = {foobar, " 1175"};
endcase
dude(foobar);
$fwrite (fd, " 1176:%s", foobar);
end
default: foobar = {foobar, " 1177"};
endcase
17'b00_10??_?_????_?0_110? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1178"};
foobar = {foobar, " 1179"};
ozonef1e_hl(foo[11:9], foo[0], foobar);
foobar = {foobar, " 1180"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1181"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1182"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1183:%s", foobar);
end
17'b00_10??_?_????_?1_110? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1184"};
foobar = {foobar, " 1185"};
ozonef1e_hl(foo[11:9],foo[0],foobar);
foobar = {foobar, " 1186"};
ozonef1e_ye(foo[14:9],foo[ 0],foobar);
foobar = {foobar, " 1187"};
foobar = {foobar, " 1188"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1189"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1190:%s", foobar);
end
17'b00_10??_?_????_?0_101? :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1191"};
ozonef1e_ye(foo[14:9],foo[ 0],foobar);
foobar = {foobar, " 1192"};
foobar = {foobar, " 1193"};
ozonef1e_hl(foo[11:9],foo[0],foobar);
foobar = {foobar, " 1194"};
foobar = {foobar, " 1195"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1196"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1197:%s", foobar);
end
17'b00_10??_?_????_?0_1001 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1198"};
foobar = {foobar, " 1199"};
ozonef1e_h(foo[11:9],foobar);
foobar = {foobar, " 1200"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1201"};
case (foo[ 7: 5])
3'h1,
3'h2,
3'h3:
foobar = {foobar, " 1202"};
default:
begin
foobar = {foobar, " 1203"};
foobar = {foobar, " 1204"};
ozonexe(foo[ 8: 5], foobar);
end
endcase
dude(foobar);
$fwrite (fd, " 1205:%s", foobar);
end
17'b00_10??_?_????_?0_0101 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1206"};
case (foo[11: 9])
3'h1,
3'h3,
3'h4:
foobar = {foobar, " 1207"};
default:
begin
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1208"};
foobar = {foobar, " 1209"};
end
endcase
foobar = {foobar, " 1210"};
foobar = {foobar, " 1211"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1212"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1213:%s", foobar);
end
17'b00_10??_?_????_?1_1110 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1214"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1215"};
foobar = {foobar, " 1216"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1217"};
foobar = {foobar, " 1218"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1219"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1220:%s", foobar);
end
17'b00_10??_?_????_?0_1000 :
begin
ozonef1e(foo, foobar);
foobar = {foobar, " 1221"};
ozonef1e_ye(foo[14:9],1'b0,foobar);
foobar = {foobar, " 1222"};
foobar = {foobar, " 1223"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1224"};
foobar = {foobar, " 1225"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1226"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite (fd, " 1227:%s", foobar);
end
17'b10_01??_?_????_??_???? :
begin
if (foo[27])
foobar = " 1228";
else
foobar = " 1229";
ozonecon(foo[20:16], foobar);
foobar = {foobar, " 1230"};
ozonef2(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1231:%s", foobar);
end
17'b00_1000_?_????_01_0011 :
if (~|foo[ 9: 8])
begin
if (foo[ 7])
foobar = " 1232";
else
foobar = " 1233";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1234"};
ozonef2e(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1235:%s", foobar);
end
else
begin
foobar = " 1236";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1237"};
ozonef3e(foo[31:0], foobar);
dude(foobar);
$fwrite (fd, " 1238:%s", foobar);
end
17'b11_110?_1_????_??_???? :
begin
ozonef3(foo[31:0], foobar);
dude(foobar);
$fwrite(fd, " 1239:%s", foobar);
end
17'b11_110?_0_????_??_???? :
begin : f4_body
casez (foo[24:20])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite (fd, " 1240");
end
5'b0_00??:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1241"};
ozoneacc(foo[25], foobar);
ozonebmuop(foo[24:20], foobar);
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1242"};
dude(foobar);
$fwrite(fd, " 1243:%s", foobar);
end
5'b0_01??:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1244"};
ozoneacc(foo[25], foobar);
ozonebmuop(foo[24:20], foobar);
ozonearm(foo[18:16], foobar);
dude(foobar);
$fwrite(fd, " 1245:%s", foobar);
end
5'b0_1011:
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1246"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1247"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1248"};
dude(foobar);
$fwrite(fd, " 1249:%s", foobar);
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1250"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1251"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1252"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1253"};
dude(foobar);
$fwrite(fd, " 1254:%s", foobar);
end
5'b0_1111 :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1255"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1256"};
ozoneae(foo[18:16], foobar);
dude(foobar);
$fwrite(fd, " 1257:%s", foobar);
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneacc(foo[26], foobar);
foobar = {foobar, " 1258"};
ozonebmuop(foo[24:20], foobar);
foobar = {foobar, " 1259"};
ozoneacc(foo[25], foobar);
foobar = {foobar, " 1260"};
ozonearm(foo[18:16], foobar);
foobar = {foobar, " 1261"};
dude(foobar);
$fwrite(fd, " 1262:%s", foobar);
end
endcase
end
17'b11_100?_?_????_??_???? :
casez (foo[23:19])
5'b111??,
5'b0111?:
begin
ozoneae(foo[26:24], foobar);
foobar = {foobar, " 1263"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1264"};
ozoneae(foo[18:16], foobar);
foobar = {foobar, " 1265"};
skyway(foo[15:12], foobar);
skyway(foo[11: 8], foobar);
skyway(foo[ 7: 4], foobar);
skyway(foo[ 3:0], foobar);
foobar = {foobar, " 1266"};
dude(foobar);
$fwrite(fd, " 1267:%s", foobar);
end
5'b?0???,
5'b110??:
begin
ozoneae(foo[26:24], foobar);
foobar = {foobar, " 1268"};
if (foo[23:21] == 3'b100)
foobar = {foobar, " 1269"};
ozoneae(foo[18:16], foobar);
if (foo[19])
foobar = {foobar, " 1270"};
else
foobar = {foobar, " 1271"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1272"};
ozonef3f4_iext(foo[20:19], foo[15:0], foobar);
dude(foobar);
$fwrite(fd, " 1273:%s", foobar);
end
5'b010??,
5'b0110?:
begin
ozoneae(foo[18:16], foobar);
if (foo[19])
foobar = {foobar, " 1274"};
else
foobar = {foobar, " 1275"};
ozonef3f4imop(foo[23:19], foobar);
foobar = {foobar, " 1276"};
ozonef3f4_iext(foo[20:19], foo[15:0], foobar);
dude(foobar);
$fwrite(fd, " 1277:%s", foobar);
end
endcase
17'b00_1000_?_????_11_0011 :
begin
foobar = " 1278";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1279"};
casez (foo[25:21])
5'b0_1110,
5'b1_0???,
5'b1_1111:
begin
$fwrite(fd, " 1280");
end
5'b0_00??:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1281"};
ozoneae(foo[17:15], foobar);
ozonebmuop(foo[25:21], foobar);
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1282"};
dude(foobar);
$fwrite(fd, " 1283:%s", foobar);
end
5'b0_01??:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1284"};
ozoneae(foo[17:15], foobar);
ozonebmuop(foo[25:21], foobar);
ozonearm(foo[ 8: 6], foobar);
dude(foobar);
$fwrite(fd, " 1285:%s", foobar);
end
5'b0_1011:
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1286"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1287"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1288"};
dude(foobar);
$fwrite(fd, " 1289:%s", foobar);
end
5'b0_100?,
5'b0_1010,
5'b0_110? :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1290"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1291"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1292"};
ozoneae(foo[ 8: 6], foobar);
foobar = {foobar, " 1293"};
dude(foobar);
$fwrite(fd, " 1294:%s", foobar);
end
5'b0_1111 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1295"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1296"};
ozoneae(foo[ 8: 6], foobar);
dude(foobar);
$fwrite(fd, " 1297:%s", foobar);
end
5'b1_10??,
5'b1_110?,
5'b1_1110 :
begin
ozoneae(foo[20:18], foobar);
foobar = {foobar, " 1298"};
ozonebmuop(foo[25:21], foobar);
foobar = {foobar, " 1299"};
ozoneae(foo[17:15], foobar);
foobar = {foobar, " 1300"};
ozonearm(foo[ 8: 6], foobar);
foobar = {foobar, " 1301"};
dude(foobar);
$fwrite(fd, " 1302:%s", foobar);
end
endcase
end
17'b00_0010_?_????_??_???? :
begin
$fwrite(fd, " 1304a:%x;%x", foobar, foo[25:20]);
ozonerab({1'b0, foo[25:20]}, foobar);
$fwrite(fd, " 1304b:%x", foobar);
foobar = {foobar, " 1303"};
$fwrite(fd, " 1304c:%x;%x", foobar, foo[19:16]);
skyway(foo[19:16], foobar);
$fwrite(fd, " 1304d:%x", foobar);
dude(foobar);
$fwrite(fd, " 1304e:%x", foobar);
$fwrite(fd, " 1304:%s", foobar);
end
17'b00_01??_?_????_??_???? :
begin
if (foo[27])
begin
foobar = {foobar, " 1305"};
if (foo[26])
foobar = {foobar, " 1306"};
else
foobar = {foobar, " 1307"};
skyway(foo[19:16], foobar);
foobar = {foobar, " 1308"};
ozonerab({1'b0, foo[25:20]}, foobar);
end
else
begin
ozonerab({1'b0, foo[25:20]}, foobar);
foobar = {foobar, " 1309"};
if (foo[26])
foobar = {foobar, " 1310"};
else
foobar = {foobar, " 1311"};
skyway(foo[19:16], foobar);
foobar = {foobar, " 1312"};
end
dude(foobar);
$fwrite(fd, " 1313:%s", foobar);
end
17'b01_000?_?_????_??_???? :
begin
if (foo[26])
begin
ozonerb(foo[25:20], foobar);
foobar = {foobar, " 1314"};
ozoneae(foo[18:16], foobar);
ozonehl(foo[19], foobar);
end
else
begin
ozoneae(foo[18:16], foobar);
ozonehl(foo[19], foobar);
foobar = {foobar, " 1315"};
ozonerb(foo[25:20], foobar);
end
dude(foobar);
$fwrite(fd, " 1316:%s", foobar);
end
17'b01_10??_?_????_??_???? :
begin
if (foo[27])
begin
ozonerab({1'b0, foo[25:20]}, foobar);
foobar = {foobar, " 1317"};
ozonerx(foo, foobar);
end
else
begin
ozonerx(foo, foobar);
foobar = {foobar, " 1318"};
ozonerab({1'b0, foo[25:20]}, foobar);
end
dude(foobar);
$fwrite(fd, " 1319:%s", foobar);
end
17'b11_101?_?_????_??_???? :
begin
ozonerab (foo[26:20], foobar);
foobar = {foobar, " 1320"};
skyway(foo[19:16], foobar);
skyway(foo[15:12], foobar);
skyway(foo[11: 8], foobar);
skyway(foo[ 7: 4], foobar);
skyway(foo[ 3: 0], foobar);
dude(foobar);
$fwrite(fd, " 1321:%s", foobar);
end
17'b11_0000_?_????_??_???? :
begin
casez (foo[25:23])
3'b00?:
begin
ozonerab(foo[22:16], foobar);
foobar = {foobar, " 1322"};
end
3'b01?:
begin
foobar = {foobar, " 1323"};
if (foo[22:16]>=7'h60)
foobar = {foobar, " 1324"};
else
ozonerab(foo[22:16], foobar);
end
3'b110:
foobar = {foobar, " 1325"};
3'b10?:
begin
foobar = {foobar, " 1326"};
if (foo[22:16]>=7'h60)
foobar = {foobar, " 1327"};
else
ozonerab(foo[22:16], foobar);
end
3'b111:
begin
foobar = {foobar, " 1328"};
ozonerab(foo[22:16], foobar);
foobar = {foobar, " 1329"};
end
endcase
dude(foobar);
$fwrite(fd, " 1330:%s", foobar);
end
17'b00_10??_?_????_?1_0000 :
begin
if (foo[27])
begin
foobar = {foobar, " 1331"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1332"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
foobar = {foobar, " 1333"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1334"};
else
ozonerab(foo[26:20], foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1335"};
foobar = {foobar, " 1336"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1337"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
foobar = {foobar, " 1338"};
end
dude(foobar);
$fwrite(fd, " 1339:%s", foobar);
end
17'b00_101?_1_0000_?1_0010 :
if (~|foo[11: 7])
begin
if (foo[ 6])
begin
foobar = {foobar, " 1340"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1341"};
ozonejk(foo[ 5], foobar);
foobar = {foobar, " 1342"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1343"};
else
ozonerab(foo[26:20], foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1344"};
foobar = {foobar, " 1345"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1346"};
ozonejk(foo[ 5], foobar);
foobar = {foobar, " 1347"};
end
dude(foobar);
$fwrite(fd, " 1348:%s", foobar);
end
else
$fwrite(fd, " 1349");
17'b00_100?_0_0011_?1_0101 :
if (~|foo[ 8: 7])
begin
if (foo[6])
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1350"};
ozoneye(foo[14: 9],foo[ 5], foobar);
end
else
begin
ozoneye(foo[14: 9],foo[ 5], foobar);
foobar = {foobar, " 1351"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1352"};
else
ozonerab(foo[26:20], foobar);
end
dude(foobar);
$fwrite(fd, " 1353:%s", foobar);
end
else
$fwrite(fd, " 1354");
17'b00_1001_0_0000_?1_0010 :
if (~|foo[25:20])
begin
ozoneye(foo[14: 9],1'b0, foobar);
foobar = {foobar, " 1355"};
ozonef1e_h(foo[11: 9],foobar);
foobar = {foobar, " 1356"};
ozonef1e_h(foo[ 7: 5],foobar);
foobar = {foobar, " 1357"};
ozonexe(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1358:%s", foobar);
end
else
$fwrite(fd, " 1359");
17'b00_101?_0_????_?1_0010 :
if (~foo[13])
begin
if (foo[12])
begin
foobar = {foobar, " 1360"};
if (foo[26:20]>=7'h60)
foobar = {foobar, " 1361"};
else
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1362"};
foobar = {foobar, " 1363"};
skyway({1'b0,foo[18:16]}, foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1364:%s", foobar);
end
else
begin
ozonerab(foo[26:20], foobar);
foobar = {foobar, " 1365"};
foobar = {foobar, " 1366"};
skyway({1'b0,foo[18:16]}, foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1367:%s", foobar);
end
end
else
$fwrite(fd, " 1368");
17'b01_01??_?_????_??_???? :
begin
ozonerab({1'b0,foo[27:26],foo[19:16]}, foobar);
foobar = {foobar, " 1369"};
ozonerab({1'b0,foo[25:20]}, foobar);
dude(foobar);
$fwrite(fd, " 1370:%s", foobar);
end
17'b00_100?_?_???0_11_0101 :
if (~foo[6])
begin
foobar = " 1371";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1372"};
ozonerab({foo[ 9: 7],foo[19:16]}, foobar);
foobar = {foobar, " 1373"};
ozonerab({foo[26:20]}, foobar);
dude(foobar);
$fwrite(fd, " 1374:%s", foobar);
end
else
$fwrite(fd, " 1375");
17'b00_1000_?_????_?1_0010 :
if (~|foo[25:24])
begin
ozonery(foo[23:20], foobar);
foobar = {foobar, " 1376"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1377"};
skyway(foo[19:16], foobar);
skyway({foo[15],foo[11: 9]}, foobar);
skyway(foo[ 8: 5], foobar);
dude(foobar);
$fwrite(fd, " 1378:%s", foobar);
end
else if ((foo[25:24] == 2'b10) & ~|foo[19:15] & ~|foo[11: 6])
begin
ozonery(foo[23:20], foobar);
foobar = {foobar, " 1379"};
ozonerp(foo[14:12], foobar);
foobar = {foobar, " 1380"};
ozonejk(foo[ 5], foobar);
dude(foobar);
$fwrite(fd, " 1381:%s", foobar);
end
else
$fwrite(fd, " 1382");
17'b11_01??_?_????_??_????,
17'b10_00??_?_????_??_???? :
if (foo[30])
$fwrite(fd, " 1383:%s", foo[27:16]);
else
$fwrite(fd, " 1384:%s", foo[27:16]);
17'b00_10??_?_????_01_1000 :
if (~foo[6])
begin
if (foo[7])
$fwrite(fd, " 1385:%s", foo[27: 8]);
else
$fwrite(fd, " 1386:%s", foo[27: 8]);
end
else
$fwrite(fd, " 1387");
17'b00_10??_?_????_11_1000 :
begin
foobar = " 1388";
ozonecon(foo[14:10], foobar);
foobar = {foobar, " 1389"};
if (foo[15])
foobar = {foobar, " 1390"};
else
foobar = {foobar, " 1391"};
skyway(foo[27:24], foobar);
skyway(foo[23:20], foobar);
skyway(foo[19:16], foobar);
skyway(foo[ 9: 6], foobar);
dude(foobar);
$fwrite(fd, " 1392:%s", foobar);
end
17'b11_0001_?_????_??_???? :
casez (foo[25:22])
4'b01?? :
begin
foobar = " 1393";
ozonecon(foo[20:16], foobar);
case (foo[23:21])
3'h0 : foobar = {foobar, " 1394"};
3'h1 : foobar = {foobar, " 1395"};
3'h2 : foobar = {foobar, " 1396"};
3'h3 : foobar = {foobar, " 1397"};
3'h4 : foobar = {foobar, " 1398"};
3'h5 : foobar = {foobar, " 1399"};
3'h6 : foobar = {foobar, " 1400"};
3'h7 : foobar = {foobar, " 1401"};
endcase
dude(foobar);
$fwrite(fd, " 1402:%s", foobar);
end
4'b0000 :
$fwrite(fd, " 1403:%s", foo[21:16]);
4'b0010 :
if (~|foo[21:16])
$fwrite(fd, " 1404");
4'b1010 :
if (~|foo[21:17])
begin
if (foo[16])
$fwrite(fd, " 1405");
else
$fwrite(fd, " 1406");
end
default :
$fwrite(fd, " 1407");
endcase
17'b01_11??_?_????_??_???? :
if (foo[27:23] === 5'h00)
$fwrite(fd, " 1408:%s", foo[22:16]);
else
$fwrite(fd, " 1409:%s", foo[22:16]);
default: $fwrite(fd, " 1410");
endcase
end
endtask
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\",\",\\4,\");\");" nil nil nil)
//(query-replace-regexp "\\([a-z0-9_]+\\) *( *\\([][a-z0-9_~': ]+\\) *, *\\([][a-z0-9'~: ]+\\) *);" "$c(\"\\1(\",\\2,\",\",\\3,\");\");" nil nil nil)
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 20:16:32 09/26/2015
// Design Name: DataUnit
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/MultiplicationUnit/DataUnitTest.v
// Project Name: DataUnit
////////////////////////////////////////////////////////////////////////////////
module DataUnitTest;
reg [3:0] Multiplicant;
reg [3:0] Multiplier;
reg [2:0] Shift1;
reg [2:0] Shift0;
reg reset, clock;
wire [7:0] Product;
DataUnit uut(Product, Multiplicant, Multiplier, Shift1, Shift0, reset, clock);
always #5 clock = ~clock;
initial begin
reset = 0; clock = 0;
Multiplicant = 3; Multiplier = 7;
Shift1 = 3'b101; Shift0 = 3'b101; #1;
reset = 1; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b011; Shift0 = 3'b000; #10;
reset = 0; #10;
reset = 1; Multiplicant = 5; Multiplier = 5;
Shift1 = 3'b101; Shift0 = 3'b101; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b011; Shift0 = 3'b000; #10;
reset = 0; #10;
reset = 1; Multiplicant = 12; Multiplier = 6;
Shift1 = 3'b101; Shift0 = 3'b101; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b011; Shift0 = 3'b000; #10;
reset = 0; #10;
reset = 1; Multiplicant = 0; Multiplier = 15;
Shift1 = 3'b101; Shift0 = 3'b101; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b011; Shift0 = 3'b000; #10;
reset = 0; #10;
reset = 1; Multiplicant = 12; Multiplier = 12;
Shift1 = 3'b101; Shift0 = 3'b101; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b111; Shift0 = 3'b000; #10;
Shift1 = 3'b010; Shift0 = 3'b010; #10;
Shift1 = 3'b011; Shift0 = 3'b000; #10;
$stop;
end
endmodule
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(**************************************************************)
(* FSetDecide.v *)
(* *)
(* Author: Aaron Bohannon *)
(**************************************************************)
(** This file implements a decision procedure for a certain
class of propositions involving finite sets. *)
Require Import Decidable Setoid DecidableTypeEx FSetFacts.
(** First, a version for Weak Sets in functorial presentation *)
Module WDecide_fun (E : DecidableType)(Import M : WSfun E).
Module F := FSetFacts.WFacts_fun E M.
(** * Overview
This functor defines the tactic [fsetdec], which will
solve any valid goal of the form
<<
forall s1 ... sn,
forall x1 ... xm,
P1 -> ... -> Pk -> P
>>
where [P]'s are defined by the grammar:
<<
P ::=
| Q
| Empty F
| Subset F F'
| Equal F F'
Q ::=
| E.eq X X'
| In X F
| Q /\ Q'
| Q \/ Q'
| Q -> Q'
| Q <-> Q'
| ~ Q
| True
| False
F ::=
| S
| empty
| singleton X
| add X F
| remove X F
| union F F'
| inter F F'
| diff F F'
X ::= x1 | ... | xm
S ::= s1 | ... | sn
>>
The tactic will also work on some goals that vary slightly from
the above form:
- The variables and hypotheses may be mixed in any order and may
have already been introduced into the context. Moreover,
there may be additional, unrelated hypotheses mixed in (these
will be ignored).
- A conjunction of hypotheses will be handled as easily as
separate hypotheses, i.e., [P1 /\ P2 -> P] can be solved iff
[P1 -> P2 -> P] can be solved.
- [fsetdec] should solve any goal if the FSet-related hypotheses
are contradictory.
- [fsetdec] will first perform any necessary zeta and beta
reductions and will invoke [subst] to eliminate any Coq
equalities between finite sets or their elements.
- If [E.eq] is convertible with Coq's equality, it will not
matter which one is used in the hypotheses or conclusion.
- The tactic can solve goals where the finite sets or set
elements are expressed by Coq terms that are more complicated
than variables. However, non-local definitions are not
expanded, and Coq equalities between non-variable terms are
not used. For example, this goal will be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2)
>>
This one will not be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2)
>>
*)
(** * Facts and Tactics for Propositional Logic
These lemmas and tactics are in a module so that they do
not affect the namespace if you import the enclosing
module [Decide]. *)
Module FSetLogicalFacts.
Export Decidable.
Export Setoid.
(** ** Lemmas and Tactics About Decidable Propositions *)
(** ** Propositional Equivalences Involving Negation
These are all written with the unfolded form of
negation, since I am not sure if setoid rewriting will
always perform conversion. *)
(** ** Tactics for Negations *)
Tactic Notation "fold" "any" "not" :=
repeat (
match goal with
| H: context [?P -> False] |- _ =>
fold (~ P) in H
| |- context [?P -> False] =>
fold (~ P)
end).
(** [push not using db] will pushes all negations to the
leaves of propositions in the goal, using the lemmas in
[db] to assist in checking the decidability of the
propositions involved. If [using db] is omitted, then
[core] will be used. Additional versions are provided
to manipulate the hypotheses or the hypotheses and goal
together.
XXX: This tactic and the similar subsequent ones should
have been defined using [autorewrite]. However, dealing
with multiples rewrite sites and side-conditions is
done more cleverly with the following explicit
analysis of goals. *)
Ltac or_not_l_iff P Q tac :=
(rewrite (or_not_l_iff_1 P Q) by tac) ||
(rewrite (or_not_l_iff_2 P Q) by tac).
Ltac or_not_r_iff P Q tac :=
(rewrite (or_not_r_iff_1 P Q) by tac) ||
(rewrite (or_not_r_iff_2 P Q) by tac).
Ltac or_not_l_iff_in P Q H tac :=
(rewrite (or_not_l_iff_1 P Q) in H by tac) ||
(rewrite (or_not_l_iff_2 P Q) in H by tac).
Ltac or_not_r_iff_in P Q H tac :=
(rewrite (or_not_r_iff_1 P Q) in H by tac) ||
(rewrite (or_not_r_iff_2 P Q) in H by tac).
Tactic Notation "push" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [?P \/ ?Q -> False] => rewrite (not_or_iff P Q)
| |- context [?P /\ ?Q -> False] => rewrite (not_and_iff P Q)
| |- context [(?P -> ?Q) -> False] => rewrite (not_imp_iff P Q) by dec
end);
fold any not.
Tactic Notation "push" "not" :=
push not using core.
Tactic Notation
"push" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [?P \/ ?Q -> False] |- _ => rewrite (not_or_iff P Q) in H
| H: context [?P /\ ?Q -> False] |- _ => rewrite (not_and_iff P Q) in H
| H: context [(?P -> ?Q) -> False] |- _ =>
rewrite (not_imp_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "push" "not" "in" "*" "|-" :=
push not in * |- using core.
Tactic Notation "push" "not" "in" "*" "using" ident(db) :=
push not using db; push not in * |- using db.
Tactic Notation "push" "not" "in" "*" :=
push not in * using core.
(** A simple test case to see how this works. *)
Lemma test_push : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ ((R -> P) \/ (Q -> R))) ->
(~ (P /\ R)) ->
(~ (P -> R)) ->
True.
Proof.
intros. push not in *.
(* note that ~(R->P) remains (since R isnt decidable) *)
tauto.
Qed.
(** [pull not using db] will pull as many negations as
possible toward the top of the propositions in the goal,
using the lemmas in [db] to assist in checking the
decidability of the propositions involved. If [using
db] is omitted, then [core] will be used. Additional
versions are provided to manipulate the hypotheses or
the hypotheses and goal together. *)
Tactic Notation "pull" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [(?P -> False) /\ (?Q -> False)] =>
rewrite <- (not_or_iff P Q)
| |- context [?P -> ?Q -> False] => rewrite <- (not_and_iff P Q)
| |- context [?P /\ (?Q -> False)] => rewrite <- (not_imp_iff P Q) by dec
| |- context [(?Q -> False) /\ ?P] =>
rewrite <- (not_imp_rev_iff P Q) by dec
end);
fold any not.
Tactic Notation "pull" "not" :=
pull not using core.
Tactic Notation
"pull" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [(?P -> False) /\ (?Q -> False)] |- _ =>
rewrite <- (not_or_iff P Q) in H
| H: context [?P -> ?Q -> False] |- _ =>
rewrite <- (not_and_iff P Q) in H
| H: context [?P /\ (?Q -> False)] |- _ =>
rewrite <- (not_imp_iff P Q) in H by dec
| H: context [(?Q -> False) /\ ?P] |- _ =>
rewrite <- (not_imp_rev_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "pull" "not" "in" "*" "|-" :=
pull not in * |- using core.
Tactic Notation "pull" "not" "in" "*" "using" ident(db) :=
pull not using db; pull not in * |- using db.
Tactic Notation "pull" "not" "in" "*" :=
pull not in * using core.
(** A simple test case to see how this works. *)
Lemma test_pull : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ (R -> P) /\ ~ (Q -> R)) ->
(~ P \/ ~ R) ->
(P /\ ~ R) ->
(~ R /\ P) ->
True.
Proof.
intros. pull not in *. tauto.
Qed.
End FSetLogicalFacts.
Import FSetLogicalFacts.
(** * Auxiliary Tactics
Again, these lemmas and tactics are in a module so that
they do not affect the namespace if you import the
enclosing module [Decide]. *)
Module FSetDecideAuxiliary.
(** ** Generic Tactics
We begin by defining a few generic, useful tactics. *)
(** remove logical hypothesis inter-dependencies (fix #2136). *)
Ltac no_logical_interdep :=
match goal with
| H : ?P |- _ =>
match type of P with
| Prop =>
match goal with H' : context [ H ] |- _ => clear dependent H' end
| _ => fail
end; no_logical_interdep
| _ => idtac
end.
(** [if t then t1 else t2] executes [t] and, if it does not
fail, then [t1] will be applied to all subgoals
produced. If [t] fails, then [t2] is executed. *)
Tactic Notation
"if" tactic(t)
"then" tactic(t1)
"else" tactic(t2) :=
first [ t; first [ t1 | fail 2 ] | t2 ].
Ltac abstract_term t :=
if (is_var t) then fail "no need to abstract a variable"
else (let x := fresh "x" in set (x := t) in *; try clearbody x).
Ltac abstract_elements :=
repeat
(match goal with
| |- context [ singleton ?t ] => abstract_term t
| _ : context [ singleton ?t ] |- _ => abstract_term t
| |- context [ add ?t _ ] => abstract_term t
| _ : context [ add ?t _ ] |- _ => abstract_term t
| |- context [ remove ?t _ ] => abstract_term t
| _ : context [ remove ?t _ ] |- _ => abstract_term t
| |- context [ In ?t _ ] => abstract_term t
| _ : context [ In ?t _ ] |- _ => abstract_term t
end).
(** [prop P holds by t] succeeds (but does not modify the
goal or context) if the proposition [P] can be proved by
[t] in the current context. Otherwise, the tactic
fails. *)
Tactic Notation "prop" constr(P) "holds" "by" tactic(t) :=
let H := fresh in
assert P as H by t;
clear H.
(** This tactic acts just like [assert ... by ...] but will
fail if the context already contains the proposition. *)
Tactic Notation "assert" "new" constr(e) "by" tactic(t) :=
match goal with
| H: e |- _ => fail 1
| _ => assert e by t
end.
(** [subst++] is similar to [subst] except that
- it never fails (as [subst] does on recursive
equations),
- it substitutes locally defined variable for their
definitions,
- it performs beta reductions everywhere, which may
arise after substituting a locally defined function
for its definition.
*)
Tactic Notation "subst" "++" :=
repeat (
match goal with
| x : _ |- _ => subst x
end);
cbv zeta beta in *.
(** [decompose records] calls [decompose record H] on every
relevant hypothesis [H]. *)
Tactic Notation "decompose" "records" :=
repeat (
match goal with
| H: _ |- _ => progress (decompose record H); clear H
end).
(** ** Discarding Irrelevant Hypotheses
We will want to clear the context of any
non-FSet-related hypotheses in order to increase the
speed of the tactic. To do this, we will need to be
able to decide which are relevant. We do this by making
a simple inductive definition classifying the
propositions of interest. *)
Inductive FSet_elt_Prop : Prop -> Prop :=
| eq_Prop : forall (S : Type) (x y : S),
FSet_elt_Prop (x = y)
| eq_elt_prop : forall x y,
FSet_elt_Prop (E.eq x y)
| In_elt_prop : forall x s,
FSet_elt_Prop (In x s)
| True_elt_prop :
FSet_elt_Prop True
| False_elt_prop :
FSet_elt_Prop False
| conj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P /\ Q)
| disj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P \/ Q)
| impl_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P -> Q)
| not_elt_prop : forall P,
FSet_elt_Prop P ->
FSet_elt_Prop (~ P).
Inductive FSet_Prop : Prop -> Prop :=
| elt_FSet_Prop : forall P,
FSet_elt_Prop P ->
FSet_Prop P
| Empty_FSet_Prop : forall s,
FSet_Prop (Empty s)
| Subset_FSet_Prop : forall s1 s2,
FSet_Prop (Subset s1 s2)
| Equal_FSet_Prop : forall s1 s2,
FSet_Prop (Equal s1 s2).
(** Here is the tactic that will throw away hypotheses that
are not useful (for the intended scope of the [fsetdec]
tactic). *)
Hint Constructors FSet_elt_Prop FSet_Prop : FSet_Prop.
Ltac discard_nonFSet :=
repeat (
match goal with
| H : context [ @Logic.eq ?T ?x ?y ] |- _ =>
if (change T with E.t in H) then fail
else if (change T with t in H) then fail
else clear H
| H : ?P |- _ =>
if prop (FSet_Prop P) holds by
(auto 100 with FSet_Prop)
then fail
else clear H
end).
(** ** Turning Set Operators into Propositional Connectives
The lemmas from [FSetFacts] will be used to break down
set operations into propositional formulas built over
the predicates [In] and [E.eq] applied only to
variables. We are going to use them with [autorewrite].
*)
Hint Rewrite
F.empty_iff F.singleton_iff F.add_iff F.remove_iff
F.union_iff F.inter_iff F.diff_iff
: set_simpl.
Lemma eq_refl_iff (x : E.t) : E.eq x x <-> True.
Proof.
now split.
Qed.
Hint Rewrite eq_refl_iff : set_eq_simpl.
(** ** Decidability of FSet Propositions *)
(** [In] is decidable. *)
Lemma dec_In : forall x s,
decidable (In x s).
Proof.
red; intros; generalize (F.mem_iff s x); case (mem x s); intuition.
Qed.
(** [E.eq] is decidable. *)
Lemma dec_eq : forall (x y : E.t),
decidable (E.eq x y).
Proof.
red; intros x y; destruct (E.eq_dec x y); auto.
Qed.
(** The hint database [FSet_decidability] will be given to
the [push_neg] tactic from the module [Negation]. *)
Hint Resolve dec_In dec_eq : FSet_decidability.
(** ** Normalizing Propositions About Equality
We have to deal with the fact that [E.eq] may be
convertible with Coq's equality. Thus, we will find the
following tactics useful to replace one form with the
other everywhere. *)
(** The next tactic, [Logic_eq_to_E_eq], mentions the term
[E.t]; thus, we must ensure that [E.t] is used in favor
of any other convertible but syntactically distinct
term. *)
Ltac change_to_E_t :=
repeat (
match goal with
| H : ?T |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
| H : forall x : ?T, _ |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
end).
(** These two tactics take us from Coq's built-in equality
to [E.eq] (and vice versa) when possible. *)
Ltac Logic_eq_to_E_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change (@Logic.eq E.t) with E.eq in H)
| |- _ =>
progress (change (@Logic.eq E.t) with E.eq)
end).
Ltac E_eq_to_Logic_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change E.eq with (@Logic.eq E.t) in H)
| |- _ =>
progress (change E.eq with (@Logic.eq E.t))
end).
(** This tactic works like the built-in tactic [subst], but
at the level of set element equality (which may not be
the convertible with Coq's equality). *)
Ltac substFSet :=
repeat (
match goal with
| H: E.eq ?x ?x |- _ => clear H
| H: E.eq ?x ?y |- _ => rewrite H in *; clear H
end);
autorewrite with set_eq_simpl in *.
(** ** Considering Decidability of Base Propositions
This tactic adds assertions about the decidability of
[E.eq] and [In] to the context. This is necessary for
the completeness of the [fsetdec] tactic. However, in
order to minimize the cost of proof search, we should be
careful to not add more than we need. Once negations
have been pushed to the leaves of the propositions, we
only need to worry about decidability for those base
propositions that appear in a negated form. *)
Ltac assert_decidability :=
(** We actually don't want these rules to fire if the
syntactic context in the patterns below is trivially
empty, but we'll just do some clean-up at the
afterward. *)
repeat (
match goal with
| H: context [~ E.eq ?x ?y] |- _ =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| H: context [~ In ?x ?s] |- _ =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
| |- context [~ E.eq ?x ?y] =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| |- context [~ In ?x ?s] =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
end);
(** Now we eliminate the useless facts we added (because
they would likely be very harmful to performance). *)
repeat (
match goal with
| _: ~ ?P, H : ?P \/ ~ ?P |- _ => clear H
end).
(** ** Handling [Empty], [Subset], and [Equal]
This tactic instantiates universally quantified
hypotheses (which arise from the unfolding of [Empty],
[Subset], and [Equal]) for each of the set element
expressions that is involved in some membership or
equality fact. Then it throws away those hypotheses,
which should no longer be needed. *)
Ltac inst_FSet_hypotheses :=
repeat (
match goal with
| H : forall a : E.t, _,
_ : context [ In ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ In ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq _ ?x ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq _ ?x ] =>
let P := type of (H x) in
assert new P by (exact (H x))
end);
repeat (
match goal with
| H : forall a : E.t, _ |- _ =>
clear H
end).
(** ** The Core [fsetdec] Auxiliary Tactics *)
(** Here is the crux of the proof search. Recursion through
[intuition]! (This will terminate if I correctly
understand the behavior of [intuition].) *)
Ltac fsetdec_rec := progress substFSet; intuition fsetdec_rec.
(** If we add [unfold Empty, Subset, Equal in *; intros;] to
the beginning of this tactic, it will satisfy the same
specification as the [fsetdec] tactic; however, it will
be much slower than necessary without the pre-processing
done by the wrapper tactic [fsetdec]. *)
Ltac fsetdec_body :=
autorewrite with set_eq_simpl in *;
inst_FSet_hypotheses;
autorewrite with set_simpl set_eq_simpl in *;
push not in * using FSet_decidability;
substFSet;
assert_decidability;
auto;
(intuition fsetdec_rec) ||
fail 1
"because the goal is beyond the scope of this tactic".
End FSetDecideAuxiliary.
Import FSetDecideAuxiliary.
(** * The [fsetdec] Tactic
Here is the top-level tactic (the only one intended for
clients of this library). It's specification is given at
the top of the file. *)
Ltac fsetdec :=
(** We first unfold any occurrences of [iff]. *)
unfold iff in *;
(** We fold occurrences of [not] because it is better for
[intros] to leave us with a goal of [~ P] than a goal of
[False]. *)
fold any not; intros;
(** We don't care about the value of elements : complex ones are
abstracted as new variables (avoiding potential dependencies,
see bug #2464) *)
abstract_elements;
(** We remove dependencies to logical hypothesis. This way,
later "clear" will work nicely (see bug #2136) *)
no_logical_interdep;
(** Now we decompose conjunctions, which will allow the
[discard_nonFSet] and [assert_decidability] tactics to
do a much better job. *)
decompose records;
discard_nonFSet;
(** We unfold these defined propositions on finite sets. If
our goal was one of them, then have one more item to
introduce now. *)
unfold Empty, Subset, Equal in *; intros;
(** We now want to get rid of all uses of [=] in favor of
[E.eq]. However, the best way to eliminate a [=] is in
the context is with [subst], so we will try that first.
In fact, we may as well convert uses of [E.eq] into [=]
when possible before we do [subst] so that we can even
more mileage out of it. Then we will convert all
remaining uses of [=] back to [E.eq] when possible. We
use [change_to_E_t] to ensure that we have a canonical
name for set elements, so that [Logic_eq_to_E_eq] will
work properly. *)
change_to_E_t; E_eq_to_Logic_eq; subst++; Logic_eq_to_E_eq;
(** The next optimization is to swap a negated goal with a
negated hypothesis when possible. Any swap will improve
performance by eliminating the total number of
negations, but we will get the maximum benefit if we
swap the goal with a hypotheses mentioning the same set
element, so we try that first. If we reach the fourth
branch below, we attempt any swap. However, to maintain
completeness of this tactic, we can only perform such a
swap with a decidable proposition; hence, we first test
whether the hypothesis is an [FSet_elt_Prop], noting
that any [FSet_elt_Prop] is decidable. *)
pull not using FSet_decidability;
unfold not in *;
match goal with
| H: (In ?x ?r) -> False |- (In ?x ?s) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?x ?y) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?y ?x) -> False =>
contradict H; fsetdec_body
| H: ?P -> False |- ?Q -> False =>
if prop (FSet_elt_Prop P) holds by
(auto 100 with FSet_Prop)
then (contradict H; fsetdec_body)
else fsetdec_body
| |- _ =>
fsetdec_body
end.
(** * Examples *)
Module FSetDecideTestCases.
Lemma test_eq_trans_1 : forall x y z s,
E.eq x y ->
~ ~ E.eq z y ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_trans_2 : forall x y z r s,
In x (singleton y) ->
~ In z r ->
~ ~ In z (add y r) ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_1 : forall w x y z s,
E.eq x w ->
~ ~ E.eq x y ->
~ E.eq y z ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_2 : forall w x y z r1 r2 s,
In x (singleton w) ->
~ In x r1 ->
In x (add y r1) ->
In y r2 ->
In y (remove z r2) ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_In_singleton : forall x,
In x (singleton x).
Proof. fsetdec. Qed.
Lemma test_add_In : forall x y s,
In x (add y s) ->
~ E.eq x y ->
In x s.
Proof. fsetdec. Qed.
Lemma test_Subset_add_remove : forall x s,
s [<=] (add x (remove x s)).
Proof. fsetdec. Qed.
Lemma test_eq_disjunction : forall w x y z,
In w (add x (add y (singleton z))) ->
E.eq w x \/ E.eq w y \/ E.eq w z.
Proof. fsetdec. Qed.
Lemma test_not_In_disj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ (In x s1 \/ In x s4 \/ E.eq y x).
Proof. fsetdec. Qed.
Lemma test_not_In_conj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ In x s1 /\ ~ In x s4 /\ ~ E.eq y x.
Proof. fsetdec. Qed.
Lemma test_iff_conj : forall a x s s',
(In a s' <-> E.eq x a \/ In a s) ->
(In a s' <-> In a (add x s)).
Proof. fsetdec. Qed.
Lemma test_set_ops_1 : forall x q r s,
(singleton x) [<=] s ->
Empty (union q r) ->
Empty (inter (diff s q) (diff s r)) ->
~ In x s.
Proof. fsetdec. Qed.
Lemma eq_chain_test : forall x1 x2 x3 x4 s1 s2 s3 s4,
Empty s1 ->
In x2 (add x1 s1) ->
In x3 s2 ->
~ In x3 (remove x2 s2) ->
~ In x4 s3 ->
In x4 (add x3 s3) ->
In x1 s4 ->
Subset (add x4 s4) s4.
Proof. fsetdec. Qed.
Lemma test_too_complex : forall x y z r s,
E.eq x y ->
(In x (singleton y) -> r [<=] s) ->
In z r ->
In z s.
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until s; intros Heq H Hr; lapply H; fsetdec.
Qed.
Lemma function_test_1 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2).
Proof. fsetdec. Qed.
Lemma function_test_2 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2).
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until 3. intros g_eq. rewrite <- g_eq. fsetdec.
Qed.
Lemma test_baydemir :
forall (f : t -> t),
forall (s : t),
forall (x y : elt),
In x (add y (f s)) ->
~ E.eq x y ->
In x (f s).
Proof.
fsetdec.
Qed.
End FSetDecideTestCases.
End WDecide_fun.
Require Import FSetInterface.
(** Now comes variants for self-contained weak sets and for full sets.
For these variants, only one argument is necessary. Thanks to
the subtyping [WS<=S], the [Decide] functor which is meant to be
used on modules [(M:S)] can simply be an alias of [WDecide]. *)
Module WDecide (M:WS) := !WDecide_fun M.E M.
Module Decide := WDecide.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer _mode;
reg _guard1;
reg [127:0] r_wide0;
reg _guard2;
wire [63:0] r_wide1;
reg _guard3;
reg _guard4;
reg _guard5;
reg _guard6;
assign r_wide1 = r_wide0[127:64];
// surefire lint_off STMINI
initial _mode = 0;
always @ (posedge clk) begin
if (_mode==0) begin
$write("[%0t] t_equal: Running\n", $time);
_guard1 <= 0;
_guard2 <= 0;
_guard3 <= 0;
_guard4 <= 0;
_guard5 <= 0;
_guard6 <= 0;
_mode<=1;
r_wide0 <= {32'h aa111111,32'hbb222222,32'hcc333333,32'hdd444444};
end
else if (_mode==1) begin
_mode<=2;
//
if (5'd10 != 5'b1010) $stop;
if (5'd10 != 5'd10) $stop;
if (5'd10 != 5'd1_0) $stop;
if (5'd10 != 5'ha) $stop;
if (5'd10 != 5'o12) $stop;
if (5'd10 != 5'o1_2) $stop;
if (5'd10 != 5'B 1010) $stop;
if (5'd10 != 5'B 10_10) $stop;
if (5'd10 != 5'D10) $stop;
if (5'd10 != 5'H a) $stop;
if (5'd10 != 5 'O 12) $stop;
if (24'h29cbb8 != 24'o12345670) $stop;
if (24'h29__cbb8 != 24'o123456__70) $stop;
if (6'b111xxx !== 6'o7x) $stop;
if (6'b111??? !== 6'o7?) $stop;
if (6'b111zzz !== 6'o7z) $stop;
//
if (r_wide0 !== {32'haa111111,32'hbb222222,32'hcc333333,32'hdd444444}) $stop;
if (r_wide1 !== {32'haa111111,32'hbb222222}) $stop;
if (|{_guard1,_guard2,_guard3,_guard4,_guard5,_guard6}) begin
$write("Guard error %x %x %x %x %x\n",_guard1,_guard2,_guard3,_guard4,_guard5);
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Module: meter_lite
//
// Description:
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module meter_lite#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2
)(
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
output out_wr,
input out_rdy,
input [31:0] data_meter_i,
input [31:0] addr_meter_i,
input req_meter_i,
input rw_meter_i,
output ack_meter_o,
output [31:0] data_meter_o,
input clk,
input reset
);
localparam NUM_QUEUES = 4;
wire [DATA_WIDTH-1:0] rate_limiter_in_data [NUM_QUEUES - 1 : 0];
wire [CTRL_WIDTH-1:0] rate_limiter_in_ctrl [NUM_QUEUES - 1 : 0];
wire [NUM_QUEUES - 1 : 0] rate_limiter_in_wr;
wire [NUM_QUEUES - 1 : 0] rate_limiter_in_rdy;
wire [DATA_WIDTH-1:0] rate_limiter_pass_data;
wire [CTRL_WIDTH-1:0] rate_limiter_pass_ctrl;
wire rate_limiter_pass_wr;
wire rate_limiter_pass_rdy;
wire [DATA_WIDTH-1:0] rate_limiter_out_data [NUM_QUEUES - 1 : 0];
wire [CTRL_WIDTH-1:0] rate_limiter_out_ctrl [NUM_QUEUES - 1 : 0];
wire [NUM_QUEUES - 1 : 0] rate_limiter_out_wr;
wire [NUM_QUEUES - 1 : 0] rate_limiter_out_rdy;
wire [19:0] token_interval ;
wire [7:0] token_increment ;
wire [NUM_QUEUES-1:0] token_interval_vld;
wire [NUM_QUEUES-1:0] token_increment_vld;
wire [31:0] pass_pkt_counter_0 ;
wire [31:0] pass_pkt_counter_1 ;
wire [31:0] pass_pkt_counter_2 ;
wire [31:0] pass_pkt_counter_3 ;
wire [31:0] pass_pkt_counter_4 ;
wire [31:0] pass_byte_counter_0 ;
wire [31:0] pass_byte_counter_1 ;
wire [31:0] pass_byte_counter_2 ;
wire [31:0] pass_byte_counter_3 ;
wire [31:0] pass_byte_counter_4 ;
wire [31:0] drop_pkt_counter_0 ;
wire [31:0] drop_pkt_counter_1 ;
wire [31:0] drop_pkt_counter_2 ;
wire [31:0] drop_pkt_counter_3 ;
wire [31:0] drop_pkt_counter_4 ;
wire [31:0] drop_byte_counter_0 ;
wire [31:0] drop_byte_counter_1 ;
wire [31:0] drop_byte_counter_2 ;
wire [31:0] drop_byte_counter_3 ;
wire [31:0] drop_byte_counter_4 ;
queue_splitter #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.NUM_QUEUES(NUM_QUEUES+1)
) queue_splitter (
// --- Interface to the previous module
.in_data (in_data),
.in_ctrl (in_ctrl),
.in_rdy (in_rdy),
.in_wr (in_wr),
.out_data_0 (rate_limiter_in_data[0]),
.out_ctrl_0 (rate_limiter_in_ctrl[0]),
.out_wr_0 (rate_limiter_in_wr[0]),
.out_rdy_0 (rate_limiter_in_rdy[0]),
.out_data_1 (rate_limiter_in_data[1]),
.out_ctrl_1 (rate_limiter_in_ctrl[1]),
.out_wr_1 (rate_limiter_in_wr[1]),
.out_rdy_1 (rate_limiter_in_rdy[1]),
.out_data_2 (rate_limiter_in_data[2]),
.out_ctrl_2 (rate_limiter_in_ctrl[2]),
.out_wr_2 (rate_limiter_in_wr[2]),
.out_rdy_2 (rate_limiter_in_rdy[2]),
.out_data_3 (rate_limiter_in_data[3]),
.out_ctrl_3 (rate_limiter_in_ctrl[3]),
.out_wr_3 (rate_limiter_in_wr[3]),
.out_rdy_3 (rate_limiter_in_rdy[3]),
.out_data_4 (rate_limiter_pass_data),
.out_ctrl_4 (rate_limiter_pass_ctrl),
.out_wr_4 (rate_limiter_pass_wr),
.out_rdy_4 (rate_limiter_pass_rdy),
// --- Misc
.clk (clk),
.reset (reset),
.pass_pkt_counter_0 (pass_pkt_counter_0 ),
.pass_pkt_counter_1 (pass_pkt_counter_1 ),
.pass_pkt_counter_2 (pass_pkt_counter_2 ),
.pass_pkt_counter_3 (pass_pkt_counter_3 ),
.pass_pkt_counter_4 (pass_pkt_counter_4 ),
.pass_byte_counter_0 (pass_byte_counter_0),
.pass_byte_counter_1 (pass_byte_counter_1),
.pass_byte_counter_2 (pass_byte_counter_2),
.pass_byte_counter_3 (pass_byte_counter_3),
.pass_byte_counter_4 (pass_byte_counter_4),
.drop_pkt_counter_0 (drop_pkt_counter_0 ),
.drop_pkt_counter_1 (drop_pkt_counter_1 ),
.drop_pkt_counter_2 (drop_pkt_counter_2 ),
.drop_pkt_counter_3 (drop_pkt_counter_3 ),
.drop_pkt_counter_4 (drop_pkt_counter_4 ),
.drop_byte_counter_0 (drop_byte_counter_0),
.drop_byte_counter_1 (drop_byte_counter_1),
.drop_byte_counter_2 (drop_byte_counter_2),
.drop_byte_counter_3 (drop_byte_counter_3),
.drop_byte_counter_4 (drop_byte_counter_4)
);
generate
genvar i;
for (i = 0; i < NUM_QUEUES; i = i + 1) begin : rate_limiter_modules
rate_limiter #(
.DATA_WIDTH (DATA_WIDTH),
.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH),
.RATE_LIMIT_BLOCK_TAG ( i),
.DEFAULT_TOKEN_INTERVAL (1 + i)
) rate_limiter
(
.out_data (rate_limiter_out_data[i]),
.out_ctrl (rate_limiter_out_ctrl[i]),
.out_wr (rate_limiter_out_wr[i]),
.out_rdy (rate_limiter_out_rdy[i]),
.in_data (rate_limiter_in_data[i]),
.in_ctrl (rate_limiter_in_ctrl[i]),
.in_wr (rate_limiter_in_wr[i]),
.in_rdy (rate_limiter_in_rdy[i]),
.token_interval_vld (token_interval_vld[i]),
.token_increment_vld (token_increment_vld[i]),
.token_interval_reg (token_interval ),
.token_increment_reg (token_increment ),
// --- Misc
.clk (clk),
.reset (reset)
);
end
endgenerate
rate_limiter_regs
#(
.NUM_QUEUES(NUM_QUEUES)
)
rate_limiter_regs
(
.data_meter_i (data_meter_i) ,
.addr_meter_i (addr_meter_i) ,
.req_meter_i (req_meter_i ) ,
.rw_meter_i (rw_meter_i ) ,
.ack_meter_o (ack_meter_o ) ,
.data_meter_o (data_meter_o) ,
// Outputs
.token_interval (token_interval),
.token_increment (token_increment),
.token_interval_vld (token_interval_vld),
.token_increment_vld (token_increment_vld),
//.include_overhead (include_overhead),
// Inputs
.clk (clk),
.reset (reset),
.pass_pkt_counter_0 (pass_pkt_counter_0 ),
.pass_pkt_counter_1 (pass_pkt_counter_1 ),
.pass_pkt_counter_2 (pass_pkt_counter_2 ),
.pass_pkt_counter_3 (pass_pkt_counter_3 ),
.pass_pkt_counter_4 (pass_pkt_counter_4 ),
.pass_byte_counter_0 (pass_byte_counter_0),
.pass_byte_counter_1 (pass_byte_counter_1),
.pass_byte_counter_2 (pass_byte_counter_2),
.pass_byte_counter_3 (pass_byte_counter_3),
.pass_byte_counter_4 (pass_byte_counter_4),
.drop_pkt_counter_0 (drop_pkt_counter_0 ),
.drop_pkt_counter_1 (drop_pkt_counter_1 ),
.drop_pkt_counter_2 (drop_pkt_counter_2 ),
.drop_pkt_counter_3 (drop_pkt_counter_3 ),
.drop_pkt_counter_4 (drop_pkt_counter_4 ),
.drop_byte_counter_0 (drop_byte_counter_0),
.drop_byte_counter_1 (drop_byte_counter_1),
.drop_byte_counter_2 (drop_byte_counter_2),
.drop_byte_counter_3 (drop_byte_counter_3),
.drop_byte_counter_4 (drop_byte_counter_4)
);
queue_aggr #(
.NUM_QUEUES(NUM_QUEUES+1),
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH)
) queue_aggr (
.out_data (out_data),
.out_ctrl (out_ctrl),
.out_wr (out_wr),
.out_rdy (out_rdy),
// --- Interface to the input queues
.in_data_0 (rate_limiter_out_data[0]),
.in_ctrl_0 (rate_limiter_out_ctrl[0]),
.in_wr_0 (rate_limiter_out_wr[0]),
.in_rdy_0 (rate_limiter_out_rdy[0]),
.in_data_1 (rate_limiter_out_data[1]),
.in_ctrl_1 (rate_limiter_out_ctrl[1]),
.in_wr_1 (rate_limiter_out_wr[1]),
.in_rdy_1 (rate_limiter_out_rdy[1]),
.in_data_2 (rate_limiter_out_data[2]),
.in_ctrl_2 (rate_limiter_out_ctrl[2]),
.in_wr_2 (rate_limiter_out_wr[2]),
.in_rdy_2 (rate_limiter_out_rdy[2]),
.in_data_3 (rate_limiter_out_data[3]),
.in_ctrl_3 (rate_limiter_out_ctrl[3]),
.in_wr_3 (rate_limiter_out_wr[3]),
.in_rdy_3 (rate_limiter_out_rdy[3]),
.in_data_4 (rate_limiter_pass_data),
.in_ctrl_4 (rate_limiter_pass_ctrl),
.in_wr_4 (rate_limiter_pass_wr),
.in_rdy_4 (rate_limiter_pass_rdy),
/*
.in_data_5 (in_data_5),
.in_ctrl_5 (in_ctrl_5),
.in_wr_5 (in_wr_5),
.in_rdy_5 (in_rdy_5),
.in_data_6 (in_data_6),
.in_ctrl_6 (in_ctrl_6),
.in_wr_6 (in_wr_6),
.in_rdy_6 (in_rdy_6),
.in_data_7 (in_data_7),
.in_ctrl_7 (in_ctrl_7),
.in_wr_7 (in_wr_7),
.in_rdy_7 (in_rdy_7),
*/
// --- Misc
.reset (reset),
.clk (clk)
);
endmodule // meter_lite
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
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// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
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//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_pcie_bram_7x.v
// Version : 1.3
// Description : single bram wrapper for the mb pcie block
// The bram A port is the write port
// the B port is the read port
//
//
//-----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_3_pcie_bram_7x
#(
parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1, // PCIe Link Speed : 1 - 2.5 GT/s; 2 - 5.0 GT/s
parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08, // PCIe Link Width : 1 / 2 / 4 / 8
parameter IMPL_TARGET = "HARD", // the implementation target : HARD, SOFT
parameter DOB_REG = 0, // 1 - use the output register;
// 0 - don't use the output register
parameter WIDTH = 0 // supported WIDTH's : 4, 9, 18, 36 - uses RAMB36
// 72 - uses RAMB36SDP
)
(
input user_clk_i,// user clock
input reset_i, // bram reset
input wen_i, // write enable
input [12:0] waddr_i, // write address
input [WIDTH - 1:0] wdata_i, // write data
input ren_i, // read enable
input rce_i, // output register clock enable
input [12:0] raddr_i, // read address
output [WIDTH - 1:0] rdata_o // read data
);
// map the address bits
localparam ADDR_MSB = ((WIDTH == 4) ? 12 :
(WIDTH == 9) ? 11 :
(WIDTH == 18) ? 10 :
(WIDTH == 36) ? 9 :
8
);
// set the width of the tied off low address bits
localparam ADDR_LO_BITS = ((WIDTH == 4) ? 2 :
(WIDTH == 9) ? 3 :
(WIDTH == 18) ? 4 :
(WIDTH == 36) ? 5 :
0 // for WIDTH 72 use RAMB36SDP
);
// map the data bits
localparam D_MSB = ((WIDTH == 4) ? 3 :
(WIDTH == 9) ? 7 :
(WIDTH == 18) ? 15 :
(WIDTH == 36) ? 31 :
63
);
// map the data parity bits
localparam DP_LSB = D_MSB + 1;
localparam DP_MSB = ((WIDTH == 4) ? 4 :
(WIDTH == 9) ? 8 :
(WIDTH == 18) ? 17 :
(WIDTH == 36) ? 35 :
71
);
localparam DPW = DP_MSB - DP_LSB + 1;
localparam WRITE_MODE = ((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (LINK_CAP_MAX_LINK_WIDTH == 6'h08)) ?
"WRITE_FIRST" : "NO_CHANGE";
localparam DEVICE = (IMPL_TARGET == "HARD") ? "7SERIES" : "VIRTEX6";
localparam BRAM_SIZE = "36Kb";
localparam WE_WIDTH =(DEVICE == "VIRTEX5" || DEVICE == "VIRTEX6" || DEVICE == "7SERIES") ?
((WIDTH <= 9) ? 1 :
(WIDTH > 9 && WIDTH <= 18) ? 2 :
(WIDTH > 18 && WIDTH <= 36) ? 4 :
(WIDTH > 36 && WIDTH <= 72) ? 8 :
(BRAM_SIZE == "18Kb") ? 4 : 8 ) : 8;
//synthesis translate_off
initial begin
//$display("[%t] %m DOB_REG %0d WIDTH %0d ADDR_MSB %0d ADDR_LO_BITS %0d DP_MSB %0d DP_LSB %0d D_MSB %0d",
// $time, DOB_REG, WIDTH, ADDR_MSB, ADDR_LO_BITS, DP_MSB, DP_LSB, D_MSB);
case (WIDTH)
4,9,18,36,72:;
default:
begin
$display("[%t] %m Error WIDTH %0d not supported", $time, WIDTH);
$finish;
end
endcase // case (WIDTH)
end
//synthesis translate_on
generate
if ((LINK_CAP_MAX_LINK_WIDTH == 6'h08 && LINK_CAP_MAX_LINK_SPEED == 4'h2) || (WIDTH == 72)) begin : use_sdp
BRAM_SDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DO_REG (DOB_REG),
.READ_WIDTH (WIDTH),
.WRITE_WIDTH (WIDTH),
.WRITE_MODE (WRITE_MODE)
)
ramb36sdp(
.DO (rdata_o[WIDTH-1:0]),
.DI (wdata_i[WIDTH-1:0]),
.RDADDR (raddr_i[ADDR_MSB:0]),
.RDCLK (user_clk_i),
.RDEN (ren_i),
.REGCE (rce_i),
.RST (reset_i),
.WE ({WE_WIDTH{1'b1}}),
.WRADDR (waddr_i[ADDR_MSB:0]),
.WRCLK (user_clk_i),
.WREN (wen_i)
);
end // block: use_sdp
else if (WIDTH <= 36) begin : use_tdp
// use RAMB36's if the width is 4, 9, 18, or 36
BRAM_TDP_MACRO #(
.DEVICE (DEVICE),
.BRAM_SIZE (BRAM_SIZE),
.DOA_REG (0),
.DOB_REG (DOB_REG),
.READ_WIDTH_A (WIDTH),
.READ_WIDTH_B (WIDTH),
.WRITE_WIDTH_A (WIDTH),
.WRITE_WIDTH_B (WIDTH),
.WRITE_MODE_A (WRITE_MODE)
)
ramb36(
.DOA (),
.DOB (rdata_o[WIDTH-1:0]),
.ADDRA (waddr_i[ADDR_MSB:0]),
.ADDRB (raddr_i[ADDR_MSB:0]),
.CLKA (user_clk_i),
.CLKB (user_clk_i),
.DIA (wdata_i[WIDTH-1:0]),
.DIB ({WIDTH{1'b0}}),
.ENA (wen_i),
.ENB (ren_i),
.REGCEA (1'b0),
.REGCEB (rce_i),
.RSTA (reset_i),
.RSTB (reset_i),
.WEA ({WE_WIDTH{1'b1}}),
.WEB ({WE_WIDTH{1'b0}})
);
end // block: use_tdp
endgenerate
endmodule // pcie_bram_7x
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FPU ////
//// Floating Point Unit (Double precision) ////
//// ////
//// Author: David Lundgren ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 David Lundgren ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// fpu_op, add = 0, subtract = 1
// rmode = 00 (nearest), 01 (to zero), 10 (+ infinity), 11 (- infinity)
`timescale 1ns / 100ps
module fpu_addsub( clk, rst, enable, fpu_op, rmode, opa, opb, out, ready);
input clk;
input rst;
input enable;
input fpu_op;
input [1:0] rmode;
input [63:0] opa, opb;
output [63:0] out;
output ready;
reg [63:0] outfp, out;
reg [1:0] rm_1, rm_2, rm_3, rm_4, rm_5, rm_6, rm_7, rm_8, rm_9;
reg [1:0] rm_10, rm_11, rm_12, rm_13, rm_14, rm_15, rm_16;
reg sign, sign_a, sign_b, fpu_op_1, fpu_op_2, fpu_op_3, fpu_op_final;
reg fpuf_2, fpuf_3, fpuf_4, fpuf_5, fpuf_6, fpuf_7, fpuf_8, fpuf_9, fpuf_10;
reg fpuf_11, fpuf_12, fpuf_13, fpuf_14, fpuf_15, fpuf_16;
reg fpuf_17, fpuf_18, fpuf_19, fpuf_20, fpuf_21;
reg sign_a2, sign_a3, sign_b2, sign_b3, sign_2, sign_3, sign_4, sign_5, sign_6;
reg sign_7, sign_8, sign_9, sign_10, sign_11, sign_12;
reg sign_13, sign_14, sign_15, sign_16, sign_17, sign_18, sign_19;
reg [10:0] exponent_a, exponent_b, expa_2, expb_2, expa_3, expb_3;
reg [51:0] mantissa_a, mantissa_b, mana_2, mana_3, manb_2, manb_3;
reg expa_et_inf, expb_et_inf, input_is_inf, in_inf2, in_inf3, in_inf4, in_inf5;
reg in_inf6, in_inf7, in_inf8, in_inf9, in_inf10, in_inf11, in_inf12, in_inf13;
reg in_inf14, in_inf15, in_inf16, in_inf17, in_inf18, in_inf19, in_inf20;
reg in_inf21, expa_gt_expb, expa_et_expb, mana_gtet_manb, a_gtet_b;
reg [10:0] exponent_small, exponent_large, expl_2, expl_3, expl_4;
reg [10:0] expl_5, expl_6, expl_7, expl_8, expl_9, expl_10, expl_11;
reg [51:0] mantissa_small, mantissa_large;
reg [51:0] mantissa_small_2, mantissa_large_2;
reg [51:0] mantissa_small_3, mantissa_large_3;
reg exp_small_et0, exp_large_et0, exp_small_et0_2, exp_large_et0_2;
reg [10:0] exponent_diff, exponent_diff_2, exponent_diff_3;
reg [107:0] bits_shifted_out, bits_shifted_out_2;
reg bits_shifted;
reg [55:0] large_add, large_add_2, large_add_3, small_add;
reg [55:0] small_shift, small_shift_2, small_shift_3, small_shift_4;
reg [55:0] large_add_4, large_add_5;
reg small_shift_nonzero;
reg small_is_nonzero, small_is_nonzero_2, small_is_nonzero_3;
reg small_fraction_enable;
wire [55:0] small_shift_LSB = { 55'b0, 1'b1 };
reg [55:0] sum, sum_2, sum_3, sum_4, sum_5;
reg [55:0] sum_6, sum_7, sum_8, sum_9, sum_10, sum_11;
reg sum_overflow, sumround_overflow, sum_lsb, sum_lsb_2;
reg [10:0] exponent_add, exp_add_2, exponent_sub, exp_sub_2;
reg [10:0] exp_sub_3, exp_sub_4, exp_sub_5, exp_sub_6, exp_sub_7;
reg [10:0] exp_sub_8, exp_add_3, exp_add_4, exp_add_5, exp_add_6;
reg [10:0] exp_add_7, exp_add_8, exp_add_9;
reg [5:0] diff_shift, diff_shift_2;
reg [55:0] diff, diff_2, diff_3, diff_4, diff_5;
reg [55:0] diff_6, diff_7, diff_8, diff_9, diff_10, diff_11;
reg diffshift_gt_exponent, diffshift_et_55, diffround_overflow;
reg round_nearest_mode, round_posinf_mode, round_neginf_mode;
reg round_nearest_trigger, round_nearest_exception;
reg round_nearest_enable, round_posinf_trigger, round_posinf_enable;
reg round_neginf_trigger, round_neginf_enable, round_enable;
reg ready, count_ready, count_ready_0;
reg [4:0] count;
always @(posedge clk)
begin
if (rst) begin
fpu_op_1 <= 0; fpu_op_final <= 0; fpu_op_2 <= 0;
fpu_op_3 <= 0; fpuf_2 <= 0; fpuf_3 <= 0; fpuf_4 <= 0;
fpuf_5 <= 0; fpuf_6 <= 0; fpuf_7 <= 0; fpuf_8 <= 0; fpuf_9 <= 0;
fpuf_10 <= 0; fpuf_11 <= 0; fpuf_12 <= 0; fpuf_13 <= 0; fpuf_14 <= 0;
fpuf_15 <= 0; fpuf_16 <= 0; fpuf_17 <= 0; fpuf_18 <= 0; fpuf_19 <= 0;
fpuf_20 <= 0; fpuf_21 <= 0;
rm_1 <= 0; rm_2 <= 0; rm_3 <= 0; rm_4 <= 0; rm_5 <= 0;
rm_6 <= 0; rm_7 <= 0; rm_8 <= 0; rm_9 <= 0; rm_10 <= 0; rm_11 <= 0;
rm_12 <= 0; rm_13 <= 0; rm_14 <= 0; rm_15 <= 0; rm_16 <= 0; sign_a <= 0;
sign_b <= 0; sign_a2 <= 0; sign_b2 <= 0; sign_a3 <= 0; sign_b3 <= 0;
exponent_a <= 0; exponent_b <= 0; expa_2 <= 0; expa_3 <= 0;
expb_2 <= 0; expb_3 <= 0; mantissa_a <= 0; mantissa_b <= 0; mana_2 <= 0; mana_3 <= 0;
manb_2 <= 0; manb_3 <= 0; expa_et_inf <= 0; expb_et_inf <= 0;
input_is_inf <= 0; in_inf2 <= 0; in_inf3 <= 0; in_inf4 <= 0; in_inf5 <= 0;
in_inf6 <= 0; in_inf7 <= 0; in_inf8 <= 0; in_inf9 <= 0; in_inf10 <= 0;
in_inf11 <= 0; in_inf12 <= 0; in_inf13 <= 0; in_inf14 <= 0; in_inf15 <= 0;
in_inf16 <= 0; in_inf17 <= 0; in_inf18 <= 0; in_inf19 <= 0; in_inf20 <= 0;
in_inf21 <= 0; expa_gt_expb <= 0; expa_et_expb <= 0; mana_gtet_manb <= 0;
a_gtet_b <= 0; sign <= 0; sign_2 <= 0; sign_3 <= 0; sign_4 <= 0; sign_5 <= 0;
sign_6 <= 0; sign_7 <= 0; sign_8 <= 0; sign_9 <= 0;
sign_10 <= 0; sign_11 <= 0; sign_12 <= 0; sign_13 <= 0; sign_14 <= 0;
sign_15 <= 0; sign_16 <= 0; sign_17 <= 0; sign_18 <= 0; sign_19 <= 0;
exponent_small <= 0; exponent_large <= 0; expl_2 <= 0;
expl_3 <= 0; expl_4 <= 0; expl_5 <= 0; expl_6 <= 0; expl_7 <= 0;
expl_8 <= 0; expl_9 <= 0; expl_10 <= 0; expl_11 <= 0;
exp_small_et0 <= 0; exp_large_et0 <= 0;
exp_small_et0_2 <= 0; exp_large_et0_2 <= 0;
mantissa_small <= 0; mantissa_large <= 0;
mantissa_small_2 <= 0; mantissa_large_2 <= 0;
mantissa_small_3 <= 0; mantissa_large_3 <= 0;
exponent_diff <= 0; exponent_diff_2 <= 0; exponent_diff_3 <= 0;
bits_shifted_out <= 0;
bits_shifted_out_2 <= 0; bits_shifted <= 0;
large_add <= 0; large_add_2 <= 0;
large_add_3 <= 0; large_add_4 <= 0; large_add_5 <= 0; small_add <= 0;
small_shift <= 0; small_shift_2 <= 0; small_shift_3 <= 0;
small_shift_4 <= 0; small_shift_nonzero <= 0;
small_is_nonzero <= 0; small_is_nonzero_2 <= 0; small_is_nonzero_3 <= 0;
small_fraction_enable <= 0;
sum <= 0; sum_2 <= 0; sum_overflow <= 0; sum_3 <= 0; sum_4 <= 0;
sum_5 <= 0; sum_6 <= 0; sum_7 <= 0; sum_8 <= 0; sum_9 <= 0; sum_10 <= 0;
sum_11 <= 0; sumround_overflow <= 0; sum_lsb <= 0; sum_lsb_2 <= 0;
exponent_add <= 0; exp_add_2 <= 0; exp_add_3 <= 0; exp_add_4 <= 0;
exp_add_5 <= 0; exp_add_6 <= 0; exp_add_7 <= 0; exp_add_8 <= 0;
exp_add_9 <= 0; diff_shift_2 <= 0; diff <= 0;
diffshift_gt_exponent <= 0; diffshift_et_55 <= 0; diff_2 <= 0;
diff_3 <= 0; diff_4 <= 0; diff_5 <= 0; diff_6 <= 0; diff_7 <= 0; diff_8 <= 0;
diff_9 <= 0; diff_10 <= 0;
diff_11 <= 0; diffround_overflow <= 0; exponent_sub <= 0;
exp_sub_2 <= 0; exp_sub_3 <= 0; exp_sub_4 <= 0; exp_sub_5 <= 0;
exp_sub_6 <= 0; exp_sub_7 <= 0; exp_sub_8 <= 0; outfp <= 0;
round_nearest_mode <= 0; round_posinf_mode <= 0; round_neginf_mode <= 0; round_nearest_trigger <= 0;
round_nearest_exception <= 0; round_nearest_enable <= 0; round_posinf_trigger <= 0; round_posinf_enable <= 0;
round_neginf_trigger <= 0; round_neginf_enable <= 0; round_enable <= 0;
end
else if (enable) begin
fpu_op_1 <= fpu_op; fpu_op_final <= fpu_op_1 ^ (sign_a ^ sign_b);
fpuf_2 <= fpu_op_final; fpuf_3 <= fpuf_2; fpuf_4 <= fpuf_3;
fpuf_5 <= fpuf_4; fpuf_6 <= fpuf_5; fpuf_7 <= fpuf_6; fpuf_8 <= fpuf_7;
fpuf_9 <= fpuf_8; fpuf_10 <= fpuf_9; fpuf_11 <= fpuf_10; fpuf_12 <= fpuf_11;
fpuf_13 <= fpuf_12; fpuf_14 <= fpuf_13; fpuf_15 <= fpuf_14;
fpuf_16 <= fpuf_15; fpuf_17 <= fpuf_16; fpuf_18 <= fpuf_17;
fpuf_19 <= fpuf_18; fpuf_20 <= fpuf_19; fpuf_21 <= fpuf_20;
fpu_op_2 <= fpu_op_1; fpu_op_3 <= fpu_op_2;
rm_1 <= rmode; rm_2 <= rm_1; rm_3 <= rm_2; rm_4 <= rm_3;
rm_5 <= rm_4; rm_6 <= rm_5; rm_7 <= rm_6; rm_8 <= rm_7; rm_9 <= rm_8;
rm_10 <= rm_9; rm_11 <= rm_10; rm_12 <= rm_11; rm_13 <= rm_12;
rm_14 <= rm_13; rm_15 <= rm_14; rm_16 <= rm_15;
sign_a <= opa[63]; sign_b <= opb[63]; sign_a2 <= sign_a;
sign_b2 <= sign_b; sign_a3 <= sign_a2; sign_b3 <= sign_b2;
exponent_a <= opa[62:52]; expa_2 <= exponent_a; expa_3 <= expa_2;
exponent_b <= opb[62:52]; expb_2 <= exponent_b; expb_3 <= expb_2;
mantissa_a <= opa[51:0]; mana_2 <= mantissa_a; mana_3 <= mana_2;
mantissa_b <= opb[51:0]; manb_2 <= mantissa_b; manb_3 <= manb_2;
expa_et_inf <= exponent_a == 2047;
expb_et_inf <= exponent_b == 2047;
input_is_inf <= expa_et_inf | expb_et_inf; in_inf2 <= input_is_inf;
in_inf3 <= in_inf2; in_inf4 <= in_inf3; in_inf5 <= in_inf4; in_inf6 <= in_inf5;
in_inf7 <= in_inf6; in_inf8 <= in_inf7; in_inf9 <= in_inf8; in_inf10 <= in_inf9;
in_inf11 <= in_inf10; in_inf12 <= in_inf11; in_inf13 <= in_inf12;
in_inf14 <= in_inf13; in_inf15 <= in_inf14; in_inf16 <= in_inf15;
in_inf17 <= in_inf16; in_inf18 <= in_inf17; in_inf19 <= in_inf18;
in_inf20 <= in_inf19; in_inf21 <= in_inf20;
expa_gt_expb <= exponent_a > exponent_b;
expa_et_expb <= exponent_a == exponent_b;
mana_gtet_manb <= mantissa_a >= mantissa_b;
a_gtet_b <= expa_gt_expb | (expa_et_expb & mana_gtet_manb);
sign <= a_gtet_b ? sign_a3 :!sign_b3 ^ (fpu_op_3 == 0);
sign_2 <= sign; sign_3 <= sign_2; sign_4 <= sign_3; sign_5 <= sign_4;
sign_6 <= sign_5; sign_7 <= sign_6; sign_8 <= sign_7; sign_9 <= sign_8;
sign_10 <= sign_9; sign_11 <= sign_10; sign_12 <= sign_11;
sign_13 <= sign_12; sign_14 <= sign_13; sign_15 <= sign_14;
sign_16 <= sign_15; sign_17 <= sign_16; sign_18 <= sign_17;
sign_19 <= sign_18;
exponent_small <= a_gtet_b ? expb_3 : expa_3;
exponent_large <= a_gtet_b ? expa_3 : expb_3;
expl_2 <= exponent_large; expl_3 <= expl_2; expl_4 <= expl_3;
expl_5 <= expl_4; expl_6 <= expl_5; expl_7 <= expl_6; expl_8 <= expl_7;
expl_9 <= expl_8; expl_10 <= expl_9; expl_11 <= expl_10;
exp_small_et0 <= exponent_small == 0;
exp_large_et0 <= exponent_large == 0;
exp_small_et0_2 <= exp_small_et0;
exp_large_et0_2 <= exp_large_et0;
mantissa_small <= a_gtet_b ? manb_3 : mana_3;
mantissa_large <= a_gtet_b ? mana_3 : manb_3;
mantissa_small_2 <= mantissa_small;
mantissa_large_2 <= mantissa_large;
mantissa_small_3 <= exp_small_et0 ? 0 : mantissa_small_2;
mantissa_large_3 <= exp_large_et0 ? 0 : mantissa_large_2;
exponent_diff <= exponent_large - exponent_small;
exponent_diff_2 <= exponent_diff;
exponent_diff_3 <= exponent_diff_2;
bits_shifted_out <= exp_small_et0 ? 108'b0 : { 1'b1, mantissa_small_2, 55'b0 };
bits_shifted_out_2 <= bits_shifted_out >> exponent_diff_2;
bits_shifted <= |bits_shifted_out_2[52:0];
large_add <= { 1'b0, !exp_large_et0_2, mantissa_large_3, 2'b0};
large_add_2 <= large_add; large_add_3 <= large_add_2;
large_add_4 <= large_add_3; large_add_5 <= large_add_4;
small_add <= { 1'b0, !exp_small_et0_2, mantissa_small_3, 2'b0};
small_shift <= small_add >> exponent_diff_3;
small_shift_2 <= { small_shift[55:1], (bits_shifted | small_shift[0]) };
small_shift_3 <= small_shift_2;
small_fraction_enable <= small_is_nonzero_3 & !small_shift_nonzero;
small_shift_4 <= small_fraction_enable ? small_shift_LSB : small_shift_3;
small_shift_nonzero <= |small_shift[54:0];
small_is_nonzero <= !exp_small_et0_2;
small_is_nonzero_2 <= small_is_nonzero; small_is_nonzero_3 <= small_is_nonzero_2;
sum <= large_add_5 + small_shift_4;
sum_overflow <= sum[55];
sum_2 <= sum; sum_lsb <= sum[0];
sum_3 <= sum_overflow ? sum_2 >> 1 : sum_2; sum_lsb_2 <= sum_lsb;
sum_4 <= { sum_3[55:1], sum_lsb_2 | sum_3[0] };
sum_5 <= sum_4; sum_6 <= sum_5; sum_7 <= sum_6; sum_8 <= sum_7;
exponent_add <= sum_overflow ? expl_10 + 1: expl_10;
exp_add_2 <= exponent_add;
diff_shift_2 <= diff_shift;
diff <= large_add_5 - small_shift_4; diff_2 <= diff; diff_3 <= diff_2;
diffshift_gt_exponent <= diff_shift > expl_10;
diffshift_et_55 <= diff_shift_2 == 55;
diff_4 <= diffshift_gt_exponent ? diff_3 << expl_11 : diff_3 << diff_shift_2;
diff_5 <= diff_4; diff_6 <= diff_5; diff_7 <= diff_6; diff_8 <= diff_7;
exponent_sub <= diffshift_gt_exponent ? 0 : (expl_11 - diff_shift_2);
exp_sub_2 <= diffshift_et_55 ? 0 : exponent_sub;
round_nearest_mode <= rm_16 == 2'b00;
round_posinf_mode <= rm_16 == 2'b10;
round_neginf_mode <= rm_16 == 2'b11;
round_nearest_trigger <= fpuf_15 ? diff_5[1] : sum_5[1];
round_nearest_exception <= fpuf_15 ? !diff_5[0] & !diff_5[2] : !sum_5[0] & !sum_5[2];
round_nearest_enable <= round_nearest_mode & round_nearest_trigger & !round_nearest_exception;
round_posinf_trigger <= fpuf_15 ? |diff_5[1:0] & !sign_13 : |sum_5[1:0] & !sign_13;
round_posinf_enable <= round_posinf_mode & round_posinf_trigger;
round_neginf_trigger <= fpuf_15 ? |diff_5[1:0] & sign_13 : |sum_5[1:0] & sign_13;
round_neginf_enable <= round_neginf_mode & round_neginf_trigger;
round_enable <= round_posinf_enable | round_neginf_enable | round_nearest_enable;
sum_9 <= round_enable ? sum_8 + 4 : sum_8;
sumround_overflow <= sum_9[55]; sum_10 <= sum_9;
sum_11 <= sumround_overflow ? sum_10 >> 1 : sum_10;
diff_9 <= round_enable ? diff_8 + 4 : diff_8;
diffround_overflow <= diff_9[55]; diff_10 <= diff_9;
diff_11 <= diffround_overflow ? diff_10 >> 1 : diff_10;
exp_add_3 <= exp_add_2; exp_add_4 <= exp_add_3; exp_add_5 <= exp_add_4;
exp_add_6 <= exp_add_5; exp_add_7 <= exp_add_6; exp_add_8 <= exp_add_7;
exp_add_9 <= sumround_overflow ? exp_add_8 + 1 : exp_add_8;
exp_sub_3 <= exp_sub_2; exp_sub_4 <= exp_sub_3; exp_sub_5 <= exp_sub_4;
exp_sub_6 <= exp_sub_5; exp_sub_7 <= exp_sub_6;
exp_sub_8 <= diffround_overflow ? exp_sub_7 + 1 : exp_sub_7;
outfp <= fpuf_21 ? {sign_19, exp_sub_8, diff_11[53:2]} : {sign_19, exp_add_9, sum_11[53:2]};
end
end
always @(posedge clk)
casex(diff[54:0])
55'b1??????????????????????????????????????????????????????: diff_shift <= 0;
55'b01?????????????????????????????????????????????????????: diff_shift <= 1;
55'b001????????????????????????????????????????????????????: diff_shift <= 2;
55'b0001???????????????????????????????????????????????????: diff_shift <= 3;
55'b00001??????????????????????????????????????????????????: diff_shift <= 4;
55'b000001?????????????????????????????????????????????????: diff_shift <= 5;
55'b0000001????????????????????????????????????????????????: diff_shift <= 6;
55'b00000001???????????????????????????????????????????????: diff_shift <= 7;
55'b000000001??????????????????????????????????????????????: diff_shift <= 8;
55'b0000000001?????????????????????????????????????????????: diff_shift <= 9;
55'b00000000001????????????????????????????????????????????: diff_shift <= 10;
55'b000000000001???????????????????????????????????????????: diff_shift <= 11;
55'b0000000000001??????????????????????????????????????????: diff_shift <= 12;
55'b00000000000001?????????????????????????????????????????: diff_shift <= 13;
55'b000000000000001????????????????????????????????????????: diff_shift <= 14;
55'b0000000000000001???????????????????????????????????????: diff_shift <= 15;
55'b00000000000000001??????????????????????????????????????: diff_shift <= 16;
55'b000000000000000001?????????????????????????????????????: diff_shift <= 17;
55'b0000000000000000001????????????????????????????????????: diff_shift <= 18;
55'b00000000000000000001???????????????????????????????????: diff_shift <= 19;
55'b000000000000000000001??????????????????????????????????: diff_shift <= 20;
55'b0000000000000000000001?????????????????????????????????: diff_shift <= 21;
55'b00000000000000000000001????????????????????????????????: diff_shift <= 22;
55'b000000000000000000000001???????????????????????????????: diff_shift <= 23;
55'b0000000000000000000000001??????????????????????????????: diff_shift <= 24;
55'b00000000000000000000000001?????????????????????????????: diff_shift <= 25;
55'b000000000000000000000000001????????????????????????????: diff_shift <= 26;
55'b0000000000000000000000000001???????????????????????????: diff_shift <= 27;
55'b00000000000000000000000000001??????????????????????????: diff_shift <= 28;
55'b000000000000000000000000000001?????????????????????????: diff_shift <= 29;
55'b0000000000000000000000000000001????????????????????????: diff_shift <= 30;
55'b00000000000000000000000000000001???????????????????????: diff_shift <= 31;
55'b000000000000000000000000000000001??????????????????????: diff_shift <= 32;
55'b0000000000000000000000000000000001?????????????????????: diff_shift <= 33;
55'b00000000000000000000000000000000001????????????????????: diff_shift <= 34;
55'b000000000000000000000000000000000001???????????????????: diff_shift <= 35;
55'b0000000000000000000000000000000000001??????????????????: diff_shift <= 36;
55'b00000000000000000000000000000000000001?????????????????: diff_shift <= 37;
55'b000000000000000000000000000000000000001????????????????: diff_shift <= 38;
55'b0000000000000000000000000000000000000001???????????????: diff_shift <= 39;
55'b00000000000000000000000000000000000000001??????????????: diff_shift <= 40;
55'b000000000000000000000000000000000000000001?????????????: diff_shift <= 41;
55'b0000000000000000000000000000000000000000001????????????: diff_shift <= 42;
55'b00000000000000000000000000000000000000000001???????????: diff_shift <= 43;
55'b000000000000000000000000000000000000000000001??????????: diff_shift <= 44;
55'b0000000000000000000000000000000000000000000001?????????: diff_shift <= 45;
55'b00000000000000000000000000000000000000000000001????????: diff_shift <= 46;
55'b000000000000000000000000000000000000000000000001???????: diff_shift <= 47;
55'b0000000000000000000000000000000000000000000000001??????: diff_shift <= 48;
55'b00000000000000000000000000000000000000000000000001?????: diff_shift <= 49;
55'b000000000000000000000000000000000000000000000000001????: diff_shift <= 50;
55'b0000000000000000000000000000000000000000000000000001???: diff_shift <= 51;
55'b00000000000000000000000000000000000000000000000000001??: diff_shift <= 52;
55'b000000000000000000000000000000000000000000000000000001?: diff_shift <= 53;
55'b0000000000000000000000000000000000000000000000000000001: diff_shift <= 54;
55'b0000000000000000000000000000000000000000000000000000000: diff_shift <= 55;
endcase
always @(posedge clk)
begin
if (rst) begin
ready <= 0;
count_ready_0 <= 0;
count_ready <= 0;
end
else if (enable) begin
ready <= count_ready;
count_ready_0 <= count == 21;
count_ready <= count == 22;
end
end
always @(posedge clk)
begin
if (rst)
count <= 0;
else if (enable & !count_ready_0 & !count_ready)
count <= count + 1;
end
always @(posedge clk)
begin
if (rst)
out <= 0;
else if (enable & count_ready)
out <= in_inf21 ? { outfp[63], 11'b11111111111, 52'b0 } : outfp;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=0;
reg [63:0] crc;
reg [63:0] sum;
wire r1_en /*verilator public*/ = crc[12];
wire [1:0] r1_ad /*verilator public*/ = crc[9:8];
wire r2_en /*verilator public*/ = 1'b1;
wire [1:0] r2_ad /*verilator public*/ = crc[11:10];
wire w1_en /*verilator public*/ = crc[5];
wire [1:0] w1_a /*verilator public*/ = crc[1:0];
wire [63:0] w1_d /*verilator public*/ = {2{crc[63:32]}};
wire w2_en /*verilator public*/ = crc[4];
wire [1:0] w2_a /*verilator public*/ = crc[3:2];
wire [63:0] w2_d /*verilator public*/ = {2{~crc[63:32]}};
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [63:0] r1_d_d2r; // From file of file.v
wire [63:0] r2_d_d2r; // From file of file.v
// End of automatics
file file (/*AUTOINST*/
// Outputs
.r1_d_d2r (r1_d_d2r[63:0]),
.r2_d_d2r (r2_d_d2r[63:0]),
// Inputs
.clk (clk),
.r1_en (r1_en),
.r1_ad (r1_ad[1:0]),
.r2_en (r2_en),
.r2_ad (r2_ad[1:0]),
.w1_en (w1_en),
.w1_a (w1_a[1:0]),
.w1_d (w1_d[63:0]),
.w2_en (w2_en),
.w2_a (w2_a[1:0]),
.w2_d (w2_d[63:0]));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d EN=%b%b%b%b R0=%x R1=%x\n",$time, cyc, r1_en,r2_en,w1_en,w2_en, r1_d_d2r, r2_d_d2r);
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= {r1_d_d2r ^ r2_d_d2r} ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
// We've manually verified all X's are out of the design by this point
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== 64'h5e9ea8c33a97f81e) $stop;
$finish;
end
end
endmodule
module file (/*AUTOARG*/
// Outputs
r1_d_d2r, r2_d_d2r,
// Inputs
clk, r1_en, r1_ad, r2_en, r2_ad, w1_en, w1_a, w1_d, w2_en, w2_a, w2_d
);
input clk;
input r1_en;
input [1:0] r1_ad;
output [63:0] r1_d_d2r;
input r2_en;
input [1:0] r2_ad;
output [63:0] r2_d_d2r;
input w1_en;
input [1:0] w1_a;
input [63:0] w1_d;
input w2_en;
input [1:0] w2_a;
input [63:0] w2_d;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [63:0] r1_d_d2r;
reg [63:0] r2_d_d2r;
// End of automatics
// Writes
wire [3:0] m_w1_onehotwe = ({4{w1_en}} & (4'b1 << w1_a));
wire [3:0] m_w2_onehotwe = ({4{w2_en}} & (4'b1 << w2_a));
wire [63:0] rg0_wrdat = m_w1_onehotwe[0] ? w1_d : w2_d;
wire [63:0] rg1_wrdat = m_w1_onehotwe[1] ? w1_d : w2_d;
wire [63:0] rg2_wrdat = m_w1_onehotwe[2] ? w1_d : w2_d;
wire [63:0] rg3_wrdat = m_w1_onehotwe[3] ? w1_d : w2_d;
wire [3:0] m_w_onehotwe = m_w1_onehotwe | m_w2_onehotwe;
// Storage
reg [63:0] m_rg0_r;
reg [63:0] m_rg1_r;
reg [63:0] m_rg2_r;
reg [63:0] m_rg3_r;
always @ (posedge clk) begin
if (m_w_onehotwe[0]) m_rg0_r <= rg0_wrdat;
if (m_w_onehotwe[1]) m_rg1_r <= rg1_wrdat;
if (m_w_onehotwe[2]) m_rg2_r <= rg2_wrdat;
if (m_w_onehotwe[3]) m_rg3_r <= rg3_wrdat;
end
// Reads
reg [1:0] m_r1_ad_d1r;
reg [1:0] m_r2_ad_d1r;
reg [1:0] m_ren_d1r;
always @ (posedge clk) begin
if (r1_en) m_r1_ad_d1r <= r1_ad;
if (r2_en) m_r2_ad_d1r <= r2_ad;
m_ren_d1r <= {r2_en, r1_en};
end
// Scheme1: shift...
wire [3:0] m_r1_onehot_d1 = (4'b1 << m_r1_ad_d1r);
// Scheme2: bit mask
reg [3:0] m_r2_onehot_d1;
always @* begin
m_r2_onehot_d1 = 4'd0;
m_r2_onehot_d1[m_r2_ad_d1r] = 1'b1;
end
wire [63:0] m_r1_d_d1 = (({64{m_r1_onehot_d1[0]}} & m_rg0_r) |
({64{m_r1_onehot_d1[1]}} & m_rg1_r) |
({64{m_r1_onehot_d1[2]}} & m_rg2_r) |
({64{m_r1_onehot_d1[3]}} & m_rg3_r));
wire [63:0] m_r2_d_d1 = (({64{m_r2_onehot_d1[0]}} & m_rg0_r) |
({64{m_r2_onehot_d1[1]}} & m_rg1_r) |
({64{m_r2_onehot_d1[2]}} & m_rg2_r) |
({64{m_r2_onehot_d1[3]}} & m_rg3_r));
always @ (posedge clk) begin
if (m_ren_d1r[0]) r1_d_d2r <= m_r1_d_d1;
if (m_ren_d1r[1]) r2_d_d2r <= m_r2_d_d1;
end
endmodule
|
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we begin a new direction that will continue for
the rest of the course. Up to now most of our attention has been
focused on various aspects of Coq itself, while from now on we'll
mostly be using Coq to formalize other things. (We'll continue to
pause from time to time to introduce a few additional aspects of
Coq.)
Our first case study is a _simple imperative programming language_
called Imp, embodying a tiny core fragment of conventional
mainstream languages such as C and Java. Here is a familiar
mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, a widely used logic for
reasoning about imperative programs. *)
(* ####################################################### *)
(** *** Sflib *)
(** A minor technical point: Instead of asking Coq to import our
earlier definitions from chapter [Logic], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. This change should be nearly invisible, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing it is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
Require Export SfLib.
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** *** *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| not b
| b and b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations:
informal ones for communicating between humans and formal ones for
carrying out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
induction a; crush.
- Case "plus". destruct a1; crush. destruct n; crush.
Qed.
Hint Rewrite optimize_0plus_sound.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem ev100 : ev 100.
Proof.
repeat (apply ev_SS). (* applies ev_SS 50 times,
until [apply ev_SS] fails *)
apply ev_0.
Qed.
(* Print ev100. *)
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem ev100' : ev 100.
Proof.
repeat (apply ev_0). (* doesn't fail, applies ev_0 zero times *)
repeat (apply ev_SS). apply ev_0. (* we can continue the proof *)
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not! *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* this just does [reflexivity] *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* just [reflexivity] would have failed *)
apply HP. (* we can still finish the proof in some other way *)
Qed.
(** Using [try] in a completely manual proof is a bit silly, but
we'll see below that [try] is very useful for doing automated
proofs in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most commonly used form, the [;] tactical takes two tactics
as argument: [T;T'] first performs the tactic [T] and then
performs the tactic [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
Case "n=0". simpl. reflexivity.
Case "n=Sn'". simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* and do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* The remaining cases -- ANum and APlus -- are different *)
Case "ANum". reflexivity.
Case "APlus".
destruct a1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs.
Here is an informal proof of this theorem that matches the
structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We
must show
aeval (optimize_0plus (APlus a1 a2))
= aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [a = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
Case "APlus".
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical has a more general than the simple [T;T'] we've
seen above, which is sometimes also useful. If [T], [T1], ...,
[Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
*)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [a] is a variable of type [aexp], then doing
aexp_cases (induction a) Case
will perform an induction on [a] (the same as if we had just typed
[induction a]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
aexp_cases (induction a) Case;
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
Case "APlus".
aexp_cases (destruct a1) SCase;
try (simpl; simpl in IHa1;
rewrite IHa1; rewrite IHa2; reflexivity).
SCase "ANum". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp :=
match b with
| BEq a b => BEq (optimize_0plus a) (optimize_0plus b)
| BLe a b => BLe (optimize_0plus a) (optimize_0plus b)
| BNot b => BNot (optimize_0plus_b b)
| BAnd a b => BAnd (optimize_0plus_b a) (optimize_0plus_b b)
| b => b
end.
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof. induction b; crush. Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
*)
Theorem le_proc : forall n m, {n <= m} + {m <= n}.
Proof. induction n; destruct m; crush. destruct (IHn m); crush. Defined.
Theorem eq_nat_proc : forall n m : nat, {n = m} + {n <> m}.
Proof. induction n; destruct m; crush. destruct (IHn m); crush. Defined.
Fixpoint optimize_precompute_le (b : bexp) : bexp :=
match b with
| BLe a a0 => match ble_nat (aeval a) (aeval a0) with
| true => BTrue
| false => BFalse
end
| BNot b' => BNot (optimize_precompute_le b')
| BAnd b0_1 b0_2 => BAnd (optimize_precompute_le b0_1) (optimize_precompute_le b0_2)
| _ => b
end.
Lemma ble_nat_Sn_m : forall n m, ble_nat (S n) m = true -> ble_nat n m = true.
Proof. induction n; destruct m; crush. Qed.
Hint Resolve ble_nat_Sn_m.
Lemma ble_nat_n_Sm : forall n m, ble_nat n m = true -> ble_nat n (S m) = true.
induction n; crush. Qed.
Hint Resolve ble_nat_n_Sm.
Hint Rewrite ble_nat_refl.
Theorem true_ble_nat : forall a b, a <= b -> ble_nat a b = true.
induction 1; crush. Qed.
Hint Resolve true_ble_nat.
Theorem ble_nat_true : forall a b, ble_nat a b = true -> a <= b.
induction a; destruct b; crush. Qed.
Hint Resolve ble_nat_true.
Theorem eq_nat_proc_refl : forall n, exists p, eq_nat_proc n n = left p.
Proof. intros; destruct (eq_nat_proc n n) as [H|H]; destruct H; eauto. Qed.
Hint Rewrite eq_nat_proc_refl.
Lemma n_neq_Sn : forall n, n <> S n.
induction n; crush. Qed.
Lemma Sn_nle_n : forall n, ~ (S n <= n).
induction n; crush. Qed.
Lemma n_le_m_neq_Sm : forall n m, n <= m -> n <> S m.
induction n; crush. Qed.
Theorem optimize_precompute_le_sound : forall b,
beval b = beval (optimize_precompute_le b).
Proof. induction b; crush.
- Case "ble_nat a a0". destruct (ble_nat (aeval a) (aeval a0)); crush.
Qed.
(** [] *)
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Liebniz wrote, "It is unworthy of excellent men to lose
hours like slaves in the labor of calculation which could be
relegated to anyone else if machines were used." We recommend
using the omega tactic whenever possible. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c]. *)
(** We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoints]. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in [.v] files.) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
Hint Constructors aevalR.
Tactic Notation "aevalR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_ANum" | Case_aux c "E_APlus"
| Case_aux c "E_AMinus" | Case_aux c "E_AMult" ].
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient write the rules for
[aevalR] and similar relations in the more readable graphical form
of _inference rules_, where the premises above the line justify
the conclusion below the line (we have already seen them in the
Prop chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
*)
(** Formally, there is nothing very deep about inference rules:
they are just implications. You can read the rule name on the
right as the name of the constructor and read each of the
linebreaks between the premises above the line and the line itself
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration (informally, this is either elided or else indicated
by saying something like "Let [aevalR] be the smallest relation
closed under the following rules..."). *)
(** For example, [||] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
*)
(* ####################################################### *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof. split.
- induction 1; crush.
- generalize dependent n; aexp_cases (induction a) Case; crush.
Qed.
Hint Rewrite aeval_iff_aevalR.
(** Note: if you're reading the HTML file, you'll see an empty square box instead
of a proof for this theorem.
You can click on this box to "unfold" the text to see the proof.
Click on the unfolded to text to "fold" it back up to a box. We'll be using
this style frequently from now on to help keep the HTML easier to read.
The full proofs always appear in the .v files. *)
(** We can make the proof quite a bit shorter by making more
use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof. split.
Case "->". intros H; induction H; subst; reflexivity.
Case "<-". generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
Reserved Notation "e '//' n" (at level 40, left associativity).
Inductive bevalR : bexp -> bool -> Prop :=
| E_BTrue : BTrue // true
| E_BFalse : BFalse // false
| E_BEq : forall (a b : aexp) (n m : nat),
a || n -> b || m -> BEq a b // beq_nat n m
| E_BLe : forall (a b : aexp) (n m : nat),
a || n -> b || m -> BLe a b // ble_nat n m
| E_BNot : forall (be : bexp) (b : bool), be // b -> BNot be // negb b
| E_Band : forall (be1 be2 : bexp) (b1 b2 : bool),
be1 // b1 -> be2 // b2 -> BAnd be1 be2 // andb b1 b2
where "a '//' b" := (bevalR a b) : type_scope.
Hint Constructors bevalR.
Theorem bevalR_iff : forall be b, be // b <-> beval be = b.
Proof. split; intros.
- induction H; crush.
- generalize dependent b; induction be; crush.
+ apply E_BEq; crush.
+ apply E_BLe; crush.
Qed.
(** [] *)
End AExp.
(* ####################################################### *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computations mechanism.
However, there are circumstances where relational definitions of
evaluation are preferable to functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations by considering also a division operation:*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp
| ADiv : aexp -> aexp -> aexp. (* <--- new *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
| E_ADiv : forall (a1 a2: aexp) (n1 n2 n3: nat),
(a1 || n1) -> (a2 || n2) -> (mult n2 n3 = n1) -> (ADiv a1 a2) || n3
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
(** *** Adding nondeterminism *)
(* /TERSE *)
(** Suppose, instead, that we want to extend the arithmetic operations
by a nondeterministic number generator [any]:*)
Inductive aexp : Type :=
| AAny : aexp (* <--- NEW *)
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Again, extending [aeval] would be tricky (because evaluation is
_not_ a deterministic function from expressions to numbers), but
extending [aevalR] is no problem: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any : forall (n:nat),
AAny || n (* <--- new *)
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ##################################################### *)
(** ** Identifiers *)
(** To begin, we'll need to formalize _identifiers_ such as program
variables. We could use strings for this -- or, in a real
compiler, fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers. *)
(** (We hide this section in a module because these definitions are
actually in [SfLib], but we want to repeat them here so that we
can explain them.) *)
Module Id.
(** We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. We use [sumbool] to define a computable
equality operator on [Id]. *)
Inductive id : Type :=
Id : nat -> id.
Theorem eq_id_dec : forall id1 id2 : id, {id1 = id2} + {id1 <> id2}.
Proof. intros; destruct id1, id2.
destruct (eq_nat_dec n n0); [left | right]; crush.
Defined.
(** The following lemmas will be useful for rewriting terms involving [eq_id_dec]. *)
Lemma eq_id : forall (T:Type) x (p q:T),
(if eq_id_dec x x then p else q) = p.
Proof. intros; destruct (eq_id_dec x x); crush. Qed.
(** **** Exercise: 1 star, optional (neq_id) *)
Lemma neq_id : forall (T:Type) x y (p q:T), x <> y ->
(if eq_id_dec x y then p else q) = q.
Proof. intros; destruct (eq_id_dec x y); crush. Qed.
Hint Rewrite eq_id neq_id.
(** [] *)
End Id.
(* ####################################################### *)
(** ** States *)
(** A _state_ represents the current values of _all_ the variables at
some point in the execution of a program. *)
(** For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going to mention a finite number of them.
The state captures all of the information stored in memory. For Imp
programs, because each variable stores only a natural number, we
can represent the state as a mapping from identifiers to [nat].
For more complex programming languages, the state might have more
structure.
*)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (x : id) (n : nat) : state :=
fun x' => if eq_id_dec x x' then n else st x'.
(** For proofs involving states, we'll need several simple properties
of [update]. *)
(** **** Exercise: 1 star (update_eq) *)
Theorem update_eq : forall n x st,
(update st x n) x = n.
Proof. intros; unfold update; rewrite eq_id; crush. Qed.
Hint Rewrite update_eq.
(** [] *)
(** **** Exercise: 1 star (update_neq) *)
Theorem update_neq : forall x2 x1 n st,
x2 <> x1 ->
(update st x2 n) x1 = (st x1).
Proof. unfold update; intros; rewrite neq_id; crush. Qed.
Hint Rewrite update_neq.
(** [] *)
(** **** Exercise: 1 star (update_example) *)
(** Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (update_shadow) *)
Theorem update_shadow : forall n1 n2 x1 x2 (st : state),
(update (update st x2 n1) x2 n2) x1 = (update st x2 n2) x1.
Proof. intros; unfold update; destruct (eq_id_dec x2 x1); reflexivity. Qed.
(** [] *)
Hint Rewrite update_shadow.
(** **** Exercise: 2 stars (update_same) *)
Theorem update_same : forall n1 x1 x2 (st : state),
st x1 = n1 ->
(update st x1 n1) x2 = st x2.
Proof. intros; unfold update; destruct (eq_id_dec x1 x2); crush. Qed.
Hint Rewrite update_same.
(** [] *)
(** **** Exercise: 3 stars (update_permute) *)
Theorem update_permute : forall n1 n2 x1 x2 x3 st,
x2 <> x1 ->
(update (update st x2 n1) x1 n2) x3 = (update (update st x1 n2) x2 n1) x3.
Proof. intros; unfold update.
destruct (eq_id_dec x1 x3), (eq_id_dec x2 x3); crush.
Qed.
(** [] *)
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "AId" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq"
| Case_aux c "BLe" | Case_aux c "BNot" | Case_aux c "BAnd" ].
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (often called _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar:
c ::= SKIP
| x ::= a
| c ;; c
| WHILE b DO c END
| IFB b THEN c ELSE c FI
END
]]
*)
(**
For example, here's the factorial function in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;;
Y ::= ANum 1;;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);;
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;;
X ::= AMinus (AId X) (ANum 1).
(** *** Loops *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;;
Z ::= ANum 5 ;;
subtract_slowly.
(** *** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky... *)
(* #################################### *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| x ::= a1 =>
update st x (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the [WHILE] case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b1)
then ceval_fun st (c1; WHILE b DO c END)
else st
end.
>>
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it doesn't always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) Coq program showing what would go wrong if Coq
allowed non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become provable
(e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks (see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] above. *)
(** This is an important change. Besides freeing us from the awkward
workarounds that would be needed to define evaluation as a
function, it gives us a lot more flexibility in the definition.
For example, if we added concurrency features to the language,
we'd want the definition of evaluation to be non-deterministic --
i.e., not only would it not be total, it would not even be a
partial function! *)
(** We'll use the notation [c / st || st'] for our [ceval] relation:
[c / st || st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
*)
(** *** Operational Semantics
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
x := a1 / st || (update st x n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b DO c END / st || st
beval st b1 = true
c / st || st'
WHILE b DO c END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b DO c END / st || st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || (update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ;; c2) / st || st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st || st' ->
(WHILE b DO c END) / st' || st'' ->
(WHILE b DO c END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop" ].
Hint Constructors ceval.
(** *** *)
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
Case "assignment command".
apply E_Ass. reflexivity.
Case "if command".
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0;; Y ::= ANum 1;; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof. eauto 10. Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com :=
(Y ::= ANum 0;;
WHILE BNot (BEq (AId X) (ANum 0))
DO Y ::= APlus (AId X) (AId Y);; X ::= AMinus (AId X) (ANum 1)
END).
Theorem pup_to_2_ceval :
pup_to_n / (update empty_state X 2) ||
update (update (update (update (update (update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof. apply E_Seq with (update (update empty_state X 2) Y 0).
constructor. reflexivity.
eapply E_WhileLoop. reflexivity.
eapply E_Seq. eapply E_Ass. reflexivity.
eapply E_Ass. reflexivity.
eapply E_WhileLoop. reflexivity.
eapply E_Seq. eapply E_Ass. reflexivity.
eapply E_Ass. reflexivity.
simpl.
eapply E_WhileEnd. reflexivity.
Qed.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof. introv E1 E2; generalize dependent st2.
ceval_cases (induction E1) Case; intros; inverts E2; crush.
- Case "E_Seq". apply IHE1_1 in H1; crush.
- Case "E_WhileLoop". apply IHE1_1 in H3; crush.
Qed.
Hint Rewrite ceval_deterministic.
(* ####################################################### *)
(** * Reasoning About Imp Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. *)
(* This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX. intro Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply update_eq. Qed.
(** **** Exercise: 3 stars (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
(* What ix XtimesYinZ? What operation is that supposed to be? *)
(** [] *)
(** **** Exercise: 3 stars (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof. remember loop; induction 1; inverts Heqc; crush. Qed.
(** [] *)
(** **** Exercise: 3 stars (no_whilesR) *)
(** Consider the definition of the [no_whiles] property below: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ;; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** This property yields [true] just on programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
| NW_S : no_whilesR SKIP
| NW_A : forall x y, no_whilesR (x ::= y)
| NW_Seq : forall c1 c2,
no_whilesR c1 -> no_whilesR c2 -> no_whilesR (c1 ;; c2)
| NW_If : forall c1 c2 c3,
no_whilesR c2 -> no_whilesR c3 -> no_whilesR (IFB c1 THEN c2 ELSE c3 FI).
Hint Constructors no_whilesR.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof. split.
- induction c; crush; destruct (no_whiles c1), (no_whiles c2); crush.
- induction 1; crush.
Qed.
(** [] *)
(** **** Exercise: 4 stars (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
Theorem no_whiles_terminates :
forall c st, no_whilesR c -> exists st', c / st || st'.
Proof. intros. generalize dependent st. induction H as [|i a| |]; crush;
try (eapply ex_intro; eauto; crush; fail).
- Case "c1 ;; c2".
destruct (IHno_whilesR1 st) as [st']; destruct (IHno_whilesR2 st') as [st''].
exists st''; apply E_Seq with (st' := st'); crush.
- Case "IFB c1 THEN c2 ELSE c3 FI".
destruct (IHno_whilesR1 st) as [st1 H1];
destruct (IHno_whilesR2 st) as [st2 H2].
destruct (beval st c1) eqn:be; [exists st1 | exists st2]; crush.
Qed.
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Definition s_step (st : state) (stack : list nat) (i : sinstr) : list nat :=
match i with
| SPush n => n :: stack
| SLoad i => st i :: stack
| SPlus => match stack with
| x :: y :: ss => y + x :: ss
| s => s
end
| SMinus => match stack with
| x :: y :: ss => y - x :: ss
| s => s
end
| SMult => match stack with
| x :: y :: ss => y * x :: ss
| s => s
end
end.
Definition s_execute (st : state) : list sinstr -> list nat -> list nat :=
fold_left (s_step st).
Example s_execute1 :
s_execute empty_state [SPush 5; SPush 3; SPush 1; SMinus] []
= [2; 5].
Proof. reflexivity. Qed.
Example s_execute2 :
s_execute (update empty_state X 3)
[SPush 4; SLoad X; SMult; SPlus] [3;4]
= [15; 4].
Proof. reflexivity. Qed.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
match e with
| ANum n => [SPush n]
| AId i => [SLoad i]
| APlus a1 a2 => (s_compile a1) ++ (s_compile a2) ++ [SPlus]
| AMinus a1 a2 => (s_compile a1) ++ (s_compile a2) ++ [SMinus]
| AMult a1 a2 => (s_compile a1) ++ (s_compile a2) ++ [SMult]
end.
(** After you've defined [s_compile], uncomment the following to test
that it works. *)
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (stack_compiler_correct) *)
(** The task of this exercise is to prove the correctness of the
calculator implemented in the previous exercise. Remember that
the specification left unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
less than two elements. (In order to make your correctness proof
easier you may find it useful to go back and change your
implementation!)
Prove the following theorem, stating that the [compile] function
behaves correctly. You will need to start by stating a more
general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
Lemma s_compile_correct' :
forall (st : state) (e : aexp) (xs : list nat) (ss : list sinstr),
s_execute st (s_compile e ++ ss) xs = s_execute st ss (aeval st e :: xs).
Proof. induction e; crush. Qed.
Hint Rewrite s_compile_correct'.
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st (s_compile e) [] = [ aeval st e ].
Proof. induction e; crush. Qed.
(** [] *)
(** **** Exercise: 5 stars, advanced (break_imp) *)
Module BreakImp.
(** Imperative languages such as C or Java often have a [break] or
similar statement for interrupting the execution of loops. In this
exercise we will consider how to add [break] to Imp.
First, we need to enrich the language of commands with an
additional case. *)
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "BREAK" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop (if any) should terminate. If there aren't any
enclosing loops, then the whole program simply terminates. The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop where it occurs. Thus, after
executing the following piece of code...
X ::= 0;
Y ::= 1;
WHILE 0 <> Y DO
WHILE TRUE DO
BREAK
END;
X ::= 1;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive status : Type :=
| SContinue : status
| SBreak : status.
Reserved Notation "c1 '/' st '||' s '/' st'"
(at level 40, st, s at level 39).
(** Intuitively, [c / st || s / st'] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that any surrounding loop (or the whole program) should exit
immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[c / st || s / st']" relation is very
similar to the one we gave above for the regular evaluation
relation ([c / st || s / st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change, and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged, but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [IF b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state should be the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal that was
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> status -> state -> Prop :=
| E_Skip : forall st,
CSkip / st || SContinue / st
| E_Ass : forall st a1 n x,
aeval st a1 = n -> (x ::= a1) / st || SContinue / update st x n
| E_Brk : forall st, CBreak / st || SBreak / st
| E_SeqBrk : forall c1 c2 st st',
c1 / st || SBreak / st' ->
(c1 ; c2) / st || SBreak / st'
| E_Seq : forall c1 c2 st st' st'' s,
c1 / st || SContinue / st' ->
c2 / st' || s / st'' ->
(c1 ; c2) / st || s / st''
| E_IfTrue : forall st st' b c1 c2 s,
beval st b = true ->
c1 / st || s / st' ->
IFB b THEN c1 ELSE c2 FI / st || s / st'
| E_IfFalse : forall st st' b c1 c2 s,
beval st b = false ->
c2 / st || s / st' ->
IFB b THEN c1 ELSE c2 FI / st || s / st'
| E_WhileEnd : forall b st c,
beval st b = false -> WHILE b DO c END / st || SContinue / st
| E_WhileBrk : forall st st' b c,
beval st b = true ->
c / st || SBreak / st' ->
WHILE b DO c END / st || SContinue / st'
| E_WhileLoop : forall st st' st'' b c s,
beval st b = true ->
c / st || SContinue / st' ->
WHILE b DO c END / st' || s / st'' ->
WHILE b DO c END / st || SContinue / st''
where "c1 '/' st '||' s '/' st'" := (ceval c1 st s st').
Hint Constructors ceval.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" |
Case_aux c "E_Ass" |
Case_aux c "E_Brk" |
Case_aux c "E_SeqBrk" |
Case_aux c "E_Seq" |
Case_aux c "E_IfTrue" |
Case_aux c "E_IfFalse" |
Case_aux c "E_WhileEnd" |
Case_aux c "E_WhileBrk" |
Case_aux c "E_WhileLoop" ].
(** Now the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
(BREAK; c) / st || s / st' ->
st = st'.
Proof. introv H; repeat inverts H as H; crush. Qed.
Theorem while_continue : forall b c st st' s,
(WHILE b DO c END) / st || s / st' ->
s = SContinue.
Proof. intros; inversion H; reflexivity. Qed.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'.
Proof. crush. Qed.
Theorem while_skip_no_term : forall b st st',
beval st b = true ->
~ (WHILE b DO SKIP END / st || SContinue / st').
introv H contra. remember (WHILE b DO SKIP END) as loopdef eqn:whb;
ceval_cases (induction contra) Case; inverts whb;
try match goal with
| [ cont : SKIP / ?st || _ / ?st' |- _ ] => inverts cont
| [ cont : WHILE b DO SKIP END / _ || _ / _ |- _ ] => inverts cont
end; crush.
Qed.
Hint Immediate while_skip_no_term.
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
Theorem while_break_true : forall b c st st',
(WHILE b DO c END) / st || SContinue / st' ->
exists st, c / st || SBreak / st' \/ beval st b = false.
introv Hc; remember (WHILE b DO c END) as loopdef eqn:whb.
ceval_cases (induction Hc) Case; crush; exists st; crush.
Qed.
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
Theorem ceval_deterministic: forall c st st1 st2 s1 s2,
c / st || s1 / st1 ->
c / st || s2 / st2 ->
st1 = st2 /\ s1 = s2.
introv E1 E2; generalize dependent st2; generalize dependent s2.
ceval_cases (induction E1) Case; intros; inverts E2;
repeat match goal with
| [ p1 : ?c / ?st || ?s1 / ?st1,
p2 : ?c / ?st || ?s2 / ?st2,
IH : forall s2 st2, ?c / ?st || s2 / st2 -> ?st1 = st2 /\ ?s1 = s2 |- _] =>
apply IH in p2
| _ => crush
end.
Qed.
End BreakImp.
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
Fixpoint beval_short (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b => negb (beval_short st b)
| BAnd b1 b2 => if beval_short st b1 then beval_short st b2 else false
end.
Theorem beval_short_correct : forall st b, beval st b = beval_short st b.
induction b; crush. Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE *)
(** [] *)
(* <$Date: 2014-02-22 09:43:41 -0500 (Sat, 22 Feb 2014) $ *)
|
/*
* Copyright 2015, Stephen A. Rodgers. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
`default_nettype none
module mux64to8 (inword, sel, outbyte);
input [63:0] inword;
input [2:0] sel;
output reg [7:0] outbyte;
always @(*) begin
case(sel)
3'h0:
outbyte <= inword[7:0];
3'h1:
outbyte <= inword[15:8];
3'h2:
outbyte <= inword[23:16];
3'h3:
outbyte <= inword[31:24];
3'h4:
outbyte <= inword[39:32];
3'h5:
outbyte <= inword[47:40];
3'h6:
outbyte <= inword[55:48];
3'h7:
outbyte <= inword[63:56];
default:
outbyte <= 8'bxxxxxxxx;
endcase
end
endmodule
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test while loops in VHDL.
module vhdl_while_test;
logic start;
int out;
vhdl_while dut(start, out);
initial begin
start = 1;
#1;
if(out !== 10) begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_down_converter(clock, resetn, i_start,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATAIN_WIDTH = 32;
parameter DATAOUT_WIDTH = 8;
input clock, resetn, i_start;
input [DATAIN_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATAOUT_WIDTH-1:0] o_dataout;
input i_dataout_stall;
output o_dataout_valid;
// Specify state machine states.
parameter s_IDLE = 3'b100;
parameter s_SEND_B1 = 3'b000;
parameter s_SEND_B2 = 3'b001;
parameter s_SEND_B3 = 3'b010;
parameter s_SEND_B4 = 3'b011;
// State and next_state variables
reg [2:0] present_state, next_state;
reg [DATAIN_WIDTH-1:0] data_to_send;
wire latch_new_data;
// Simple state machine to output 1 byte per cycle
always@(*)
begin
case (present_state)
s_IDLE: if (i_datain_valid)
next_state <= s_SEND_B1;
else
next_state <= s_IDLE;
s_SEND_B1: if (!i_dataout_stall)
next_state <= s_SEND_B2;
else
next_state <= s_SEND_B1;
s_SEND_B2: if (!i_dataout_stall)
next_state <= s_SEND_B3;
else
next_state <= s_SEND_B2;
s_SEND_B3: if (!i_dataout_stall)
next_state <= s_SEND_B4;
else
next_state <= s_SEND_B3;
s_SEND_B4: if (!i_dataout_stall)
next_state <= i_datain_valid ? s_SEND_B1 : s_IDLE;
else
next_state <= s_SEND_B4;
default: next_state <= 3'bxxx;
endcase
end
// Simple state machine to output 1 byte per cycle
always@(posedge clock or negedge resetn)
begin
if (~resetn)
data_to_send <= {DATAIN_WIDTH{1'b0}};
else
data_to_send <= (latch_new_data & i_datain_valid) ?
i_datain : data_to_send;
end
// State assignment
always@(posedge clock or negedge resetn)
begin
if (~resetn)
present_state <= s_IDLE;
else
present_state <= (i_start) ? next_state : s_IDLE;
end
//assign o_dataout = (present_state == s_SEND_B1) ? data_to_send[DATAOUT_WIDTH-1:0] :
// ((present_state == s_SEND_B2) ? data_to_send[2*DATAOUT_WIDTH-1:DATAOUT_WIDTH] :
// ((present_state == s_SEND_B3) ? data_to_send[3*DATAOUT_WIDTH-1:2*DATAOUT_WIDTH] :
// data_to_send[4*DATAOUT_WIDTH-1:3*DATAOUT_WIDTH] ));
assign o_dataout = data_to_send[present_state[1:0]*DATAOUT_WIDTH +: DATAOUT_WIDTH];
//assign o_dataout_valid = (present_state != s_IDLE);
assign o_dataout_valid = ~present_state[2] & i_start;
//we latch data in the idle state, or if we're in the send_b4 state,
// and downstream is not stalling back
assign latch_new_data = (present_state == s_IDLE) ||
((present_state == s_SEND_B4) & ~i_dataout_stall);
// we want to lower the stall to the inputs when we want to latch new data
assign o_datain_stall = (i_start) ? ~latch_new_data : 1'b0;
endmodule
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_fifo #(parameter WDT = 32, DEPTH = 8) (
input wire i_clk,
input wire i_reset,
input wire i_write_inhibit,
input wire i_clear_from_writeback,
input wire i_data_stall,
input wire i_clear_from_alu,
input wire i_stall_from_shifter,
input wire i_stall_from_issue,
input wire i_stall_from_decode,
input wire i_clear_from_decode,
input wire [WDT-1:0] i_instr, // Instruction + other bits.
input wire i_valid, // Above is valid. Write enable basically.
output reg [WDT-1:0] o_instr, // Instruction output.
output reg o_valid, // Output valid.
output wire o_wb_stb,
output wire o_wb_cyc // Wishbone request.
);
reg clear, rd_en;
wire [WDT-1:0] instr;
wire valid;
assign o_wb_cyc = o_wb_stb;
always @*
begin
if ( i_clear_from_writeback ) clear = 1'd1;
else if ( i_data_stall ) clear = 1'd0;
else if ( i_clear_from_alu ) clear = 1'd1;
else if ( i_stall_from_shifter ) clear = 1'd0;
else if ( i_stall_from_issue ) clear = 1'd0;
else if ( i_stall_from_decode ) clear = 1'd0;
else if ( i_clear_from_decode ) clear = 1'd1;
else clear = 1'd0;
end
always @*
begin
if ( i_clear_from_writeback) rd_en = 1'd0;
else if ( i_data_stall ) rd_en = 1'd0;
else if ( i_clear_from_alu ) rd_en = 1'd0;
else if ( i_stall_from_shifter ) rd_en = 1'd0;
else if ( i_stall_from_issue ) rd_en = 1'd0;
else if ( i_stall_from_decode ) rd_en = 1'd0;
else if ( i_clear_from_decode ) rd_en = 1'd0;
else rd_en = 1'd1;
end
zap_sync_fifo #(.WIDTH(WDT), .DEPTH(DEPTH), .FWFT(1)) USF (
.i_clk (i_clk),
.i_reset (i_reset || clear),
.i_ack ( rd_en ),
.i_wr_en ( i_valid && !i_write_inhibit ),
.i_data (i_instr),
.o_data (instr),
.o_empty_n (valid),
.o_full_n (o_wb_stb),
.o_full_n_nxt (),
.o_empty (),
.o_data_nxt (),
.o_full ()
);
// Pipeline register.
always @ (posedge i_clk)
begin
if ( i_reset || clear )
begin
o_valid <= 1'd0;
end
else if ( rd_en )
begin
o_valid <= valid;
o_instr <= instr;
end
end
endmodule
`default_nettype wire
|
/*
* Copyright (c) 1998 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This demonstrates proper handling of unknown values in decimal output.
*/
module main();
initial
begin
$display("4'bxxxx = %d", 4'bxxxx);
$display("4'bzzxx = %d", 4'bzzxx);
$display("4'bzzzz = %d", 4'bzzzz);
$display("4'b00zz = %d", 4'b00zz);
$display("4'b0000 = %d", 4'b0000);
$display("4'b0011 = %d", 4'b0011);
$finish ;
end
endmodule
|
/* salsaengine.v
*
* Copyright (c) 2013 kramble
* Parts copyright (c) 2011 [email protected]
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
// NB HALFRAM no longer applies, configure via parameters ADDRBITS, THREADS
// Bracket this config option in SIM so we don't accidentally leave it set in a live build
`ifdef SIM
//`define ONETHREAD // Start one thread only (for SIMULATION less confusing and faster startup)
`endif
`timescale 1ns/1ps
module salsaengine (hash_clk, reset, din, dout, shift, start, busy, result );
input hash_clk;
input reset; // NB pbkdf_clk domain (need a long reset (at least THREADS+4) to initialize correctly, this is done in pbkdfengine (15 cycles)
input shift;
input start; // NB pbkdf_clk domain
output busy;
output reg result = 1'b0;
parameter SBITS = 8; // Shift data path width
input [SBITS-1:0] din;
output [SBITS-1:0] dout;
// Configure ADDRBITS to allocate RAM for core (automatically sets LOOKAHEAD_GAP)
// NB do not use ADDRBITS > 13 for THREADS=8 since this corresponds to more than a full scratchpad
// These settings are now overriden in ltcminer_icarus.v determined by LOCAL_MINERS ...
// parameter ADDRBITS = 13; // 8MBit RAM allocated to core, full scratchpad (will not fit LX150)
parameter ADDRBITS = 12; // 4MBit RAM allocated to core, half scratchpad
// parameter ADDRBITS = 11; // 2MBit RAM allocated to core, quarter scratchpad
// parameter ADDRBITS = 10; // 1MBit RAM allocated to core, eighth scratchpad
// Do not change THREADS - this must match the salsa pipeline (code is untested for other values)
parameter THREADS = 16; // NB Phase has THREADS+1 cycles
function integer clog2; // Courtesy of razorfishsl, replaces $clog2()
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
parameter THREADS_BITS = clog2(THREADS);
// Workaround for range-reversal error in inactive code when ADDRBITS=13
parameter ADDRBITSX = (ADDRBITS == 13) ? ADDRBITS-1 : ADDRBITS;
reg [THREADS_BITS:0]phase = 0;
reg [THREADS_BITS:0]phase_d = THREADS+1;
reg reset_d=0, fsmreset=0, start_d=0, fsmstart=0;
always @ (posedge hash_clk) // Phase control and sync
begin
phase <= (phase == THREADS) ? 0 : phase + 1;
phase_d <= phase;
reset_d <= reset; // Synchronise to hash_clk domain
fsmreset <= reset_d;
start_d <= start;
fsmstart <= start_d;
end
// Salsa Mix FSM (handles both loading of the scratchpad ROM and the subsequent processing)
parameter XSnull = 0, XSload = 1, XSmix = 2, XSram = 4; // One-hot since these map directly to mux contrls
reg [2:0] XCtl = XSnull;
parameter R_IDLE=0, R_START=1, R_WRITE=2, R_MIX=3, R_INT=4, R_WAIT=5;
reg [2:0] mstate = R_IDLE;
reg [10:0] cycle = 11'd0;
reg doneROM = 1'd0; // Yes ROM, as its referred thus in the salsa docs
reg addrsourceMix = 1'b0;
reg datasourceLoad = 1'b0;
reg addrsourceSave = 1'b0;
reg resultsourceRam = 1'b0;
reg xoren = 1'b1;
reg [THREADS_BITS+1:0] intcycles = 0; // Number of interpolation cycles required ... How many do we need? Say THREADS_BITS+1
wire [511:0] Xmix;
reg [511:0] X0;
reg [511:0] X1;
wire [511:0] X0in;
wire [511:0] X1in;
wire [511:0] X0out;
reg [1023:0] salsaShiftReg;
reg [31:0] nonce_sr; // In series with salsaShiftReg
assign dout = salsaShiftReg[1023:1024-SBITS];
// sstate is implemented in ram (alternatively could use a rotating shift register)
reg [THREADS_BITS+30:0] sstate [THREADS-1:0]; // NB initialized via a long reset (see pbkdfengine)
// List components of sstate here for ease of maintenance ...
wire [2:0] mstate_in;
wire [10:0] cycle_in;
wire [9:0] writeaddr_in;
wire doneROM_in;
wire addrsourceMix_in;
wire addrsourceSave_in;
wire [THREADS_BITS+1:0] intcycles_in; // How many do we need? Say THREADS_BITS+1
wire [9:0] writeaddr_next = writeaddr_in + 10'd1;
reg [31:0] snonce [THREADS-1:0]; // Nonce store. Note bidirectional loading below, this will either implement
// as registers or dual-port ram, so do NOT integrate with sstate.
// NB no busy_in or result_in as these flag are NOT saved on a per-thread basis
// Convert salsaShiftReg to little-endian word format to match scrypt.c as its easier to debug it
// this way rather than recoding the SMix salsa to work with original buffer
wire [1023:0] X;
`define IDX(x) (((x)+1)*(32)-1):((x)*(32))
genvar i;
generate
for (i = 0; i < 32; i = i + 1) begin : Xrewire
wire [31:0] tmp;
assign tmp = salsaShiftReg[`IDX(i)];
assign X[`IDX(i)] = { tmp[7:0], tmp[15:8], tmp[23:16], tmp[31:24] };
end
endgenerate
// NB writeaddr is cycle counter in R_WRITE so use full size regardless of RAM size
(* S = "TRUE" *) reg [9:0] writeaddr = 10'd0;
// ALTRAM Max is 256 bit width, so use four
// Ram is registered on inputs vis ram_addr, ram_din and ram_wren
// Output is unregistered, OLD data on write (less delay than NEW??)
wire [9:0] Xaddr;
wire [ADDRBITS-1:0]rd_addr;
wire [ADDRBITS-1:0]wr_addr1;
wire [ADDRBITS-1:0]wr_addr2;
wire [ADDRBITS-1:0]wr_addr3;
wire [ADDRBITS-1:0]wr_addr4;
wire [255:0]ram1_din;
wire [255:0]ram1_dout;
wire [255:0]ram2_din;
wire [255:0]ram2_dout;
wire [255:0]ram3_din;
wire [255:0]ram3_dout;
wire [255:0]ram4_din;
wire [255:0]ram4_dout;
wire [1023:0]ramout;
(* S = "TRUE" *) reg ram_wren = 1'b0;
wire ram_clk;
assign ram_clk = hash_clk; // Uses same clock as hasher for now
// Top ram address is reserved for X0Save/X1save, so adjust
wire [15:0] memtop = 16'hfffe; // One less than the top memory location (per THREAD bank)
wire [ADDRBITS-THREADS_BITS-1:0] adj_addr;
if (ADDRBITS < 13)
assign adj_addr = (Xaddr[9:THREADS_BITS+10-ADDRBITS] == memtop[9:THREADS_BITS+10-ADDRBITS]) ?
memtop[ADDRBITS-THREADS_BITS-1:0] : Xaddr[9:THREADS_BITS+10-ADDRBITS];
else
assign adj_addr = Xaddr;
wire [THREADS_BITS-1:0] phase_addr;
assign phase_addr = phase[THREADS_BITS-1:0];
// TODO can we remove the +1 and adjust the wr_addr to use the same prefix via phase_d?
assign rd_addr = { phase_addr+1, addrsourceSave_in ? memtop[ADDRBITS-THREADS_BITS:1] : adj_addr }; // LSB are ignored
wire [9:0] writeaddr_adj = addrsourceMix ? memtop[10:1] : writeaddr;
assign wr_addr1 = { phase_addr, writeaddr_adj[9:THREADS_BITS+10-ADDRBITS] };
assign wr_addr2 = { phase_addr, writeaddr_adj[9:THREADS_BITS+10-ADDRBITS] };
assign wr_addr3 = { phase_addr, writeaddr_adj[9:THREADS_BITS+10-ADDRBITS] };
assign wr_addr4 = { phase_addr, writeaddr_adj[9:THREADS_BITS+10-ADDRBITS] };
// Duplicate address to reduce fanout (its a ridiculous kludge, but seems to be the approved method)
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_1 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_2 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_3 = 0;
(* S = "TRUE" *) reg [ADDRBITS-1:0] rd_addr_z_4 = 0;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr1 = rd_addr | rd_addr_z_1;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr2 = rd_addr | rd_addr_z_2;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr3 = rd_addr | rd_addr_z_3;
(* S = "TRUE" *) wire [ADDRBITS-1:0] rd_addr4 = rd_addr | rd_addr_z_4;
ram # (.ADDRBITS(ADDRBITS)) ram1_blk (rd_addr1, wr_addr1, ram_clk, ram1_din, ram_wren, ram1_dout);
ram # (.ADDRBITS(ADDRBITS)) ram2_blk (rd_addr2, wr_addr2, ram_clk, ram2_din, ram_wren, ram2_dout);
ram # (.ADDRBITS(ADDRBITS)) ram3_blk (rd_addr3, wr_addr3, ram_clk, ram3_din, ram_wren, ram3_dout);
ram # (.ADDRBITS(ADDRBITS)) ram4_blk (rd_addr4, wr_addr4, ram_clk, ram4_din, ram_wren, ram4_dout);
assign ramout = { ram4_dout, ram3_dout, ram2_dout, ram1_dout }; // Unregistered output
assign { ram4_din, ram3_din, ram2_din, ram1_din } = datasourceLoad ? X : { Xmix, X0out}; // Registered input
// Salsa unit
salsa salsa_blk (hash_clk, X0, X1, Xmix, X0out, Xaddr);
// Main multiplexer
wire [511:0] Zbits;
assign Zbits = {512{xoren}}; // xoren enables xor from ram (else we load from ram)
// With luck the synthesizer will interpret this correctly as one-hot control ...
// DEBUG using default state of 0 for XSnull so as to show up issues with preserved values (previously held value X0/X1)
// assign X0in = (XCtl==XSmix) ? X0out : (XCtl==XSram) ? (X0out & Zbits) ^ ramout[511:0] : (XCtl==XSload) ? X[511:0] : 0;
// assign X1in = (XCtl==XSmix) ? Xmix : (XCtl==XSram) ? (Xmix & Zbits) ^ ramout[1023:512] : (XCtl==XSload) ? X[1023:512] : 0;
// Now using explicit control signals (rather than relying on synthesizer to map correctly)
// XSMix is now the default (XSnull is unused as this mapped onto zero in the DEBUG version above) - TODO amend FSM accordingly
assign X0in = XCtl[2] ? (X0out & Zbits) ^ ramout[511:0] : XCtl[0] ? X[511:0] : X0out;
assign X1in = XCtl[2] ? (Xmix & Zbits) ^ ramout[1023:512] : XCtl[0] ? X[1023:512] : Xmix;
// Salsa FSM - TODO may want to move this into a separate function (for floorplanning), see hashvariant-C
// Hold separate state for each thread (a bit of a kludge to avoid rewriting FSM from scratch)
// NB must ensure shift and result do NOT overlap by carefully controlling timing of start signal
// NB Phase has THREADS+1 cycles, but we do not save the state for (phase==THREADS) as it is never active
assign { mstate_in, writeaddr_in, cycle_in, doneROM_in, addrsourceMix_in, addrsourceSave_in, intcycles_in} =
(phase == THREADS ) ? 0 : sstate[phase];
// Interface FSM ensures threads start evenly (required for correct salsa FSM operation)
reg busy_flag = 1'b0;
`ifdef ONETHREAD
// TEST CONTROLLER ... just allow a single thread to run (busy is currently a common flag)
// NB the thread automatically restarts after it completes, so its a slight misnomer to say it starts once.
reg start_once = 1'b0;
wire start_flag;
assign start_flag = fsmstart & ~start_once;
assign busy = busy_flag; // Ack to pbkdfengine
`else
// NB start_flag only has effect when a thread is at R_IDLE, ie after reset, normally a thread will automatically
// restart on completion. We need to spread the R_IDLE starts evenly to ensure proper ooperation. NB the pbkdf
// engine requires busy and result, but this looks alter itself in the salsa FSM, even though these are global
// flags. Reset periodically (on loadnonce in pbkdfengine) to ensure it stays in sync.
reg [15:0] start_count = 0;
// TODO automatic configuration (currently assumes THREADS 8 or 16, and ADDRBITS 12,11,10 calculated as follows...)
// For THREADS=8, lookup_gap=2 salsa takes on average 9*(1024+(1024*1.5)) = 23040 clocks, generically 9*1024*(lookup_gap/2+1.5)
// For THREADS=16, use 17*1024*(lookup_gap/2+1.5), where lookupgap is double that for THREADS=8
parameter START_INTERVAL = (THREADS==16) ? ((ADDRBITS==12) ? 60928 : (ADDRBITS==11) ? 95744 : 165376) / THREADS : // 16 threads
((ADDRBITS==12) ? 23040 : (ADDRBITS==11) ? 36864 : 50688) / THREADS ; // 8 threads
reg start_flag = 1'b0;
assign busy = busy_flag; // Ack to pbkdfengine - this will toggle on transtion through R_START
`endif
always @ (posedge hash_clk)
begin
X0 <= X0in;
X1 <= X1in;
if (phase_d != THREADS)
sstate[phase_d] <= fsmreset ? 0 : { mstate, writeaddr, cycle, doneROM, addrsourceMix, addrsourceSave, intcycles };
mstate <= mstate_in; // Set defaults (overridden below as necessary)
writeaddr <= writeaddr_in;
cycle <= cycle_in;
intcycles <= intcycles_in;
doneROM <= doneROM_in;
addrsourceMix <= addrsourceMix_in;
addrsourceSave <= addrsourceSave_in; // Overwritten below, but addrsourceSave_in is used above
// Duplicate address to reduce fanout (its a ridiculous kludge, but seems to be the approved method)
rd_addr_z_1 <= {ADDRBITS{fsmreset}};
rd_addr_z_2 <= {ADDRBITS{fsmreset}};
rd_addr_z_3 <= {ADDRBITS{fsmreset}};
rd_addr_z_4 <= {ADDRBITS{fsmreset}};
XCtl <= XSnull; // Default states
addrsourceSave <= 0; // NB addrsourceSave_in is the active control so this DOES need to be in sstate
datasourceLoad <= 0; // Does not need to be saved in sstate
resultsourceRam <= 0; // Does not need to be saved in sstate
ram_wren <= 0;
xoren <= 1;
// Interface FSM ensures threads start evenly (required for correct salsa FSM operation)
`ifdef ONETHREAD
if (fsmstart && phase!=THREADS)
start_once <= 1'b1;
if (fsmreset)
start_once <= 1'b0;
`else
start_count <= start_count + 1;
// start_flag <= 1'b0; // Done below when we transition out of R_IDLE
if (fsmreset || start_count == START_INTERVAL)
begin
start_count <= 0;
if (~fsmreset && fsmstart)
start_flag <= 1'b1;
end
`endif
// Could use explicit mux for this ...
if (shift)
begin
salsaShiftReg <= { salsaShiftReg[1023-SBITS:0], nonce_sr[31:32-SBITS] };
nonce_sr <= { nonce_sr[31-SBITS:0], din};
end
else
if (XCtl==XSload && phase_d != THREADS) // Set at end of previous hash - this is executed regardless of phase
begin
salsaShiftReg <= resultsourceRam ? ramout : { Xmix, X0out }; // Simultaneously with XSload
nonce_sr <= snonce[phase_d]; // NB bidirectional load
snonce[phase_d] <= nonce_sr;
end
if (fsmreset == 1'b1)
begin
mstate <= R_IDLE; // This will propagate to all sstate slots as we hold reset for 10 cycles
busy_flag <= 1'b0;
result <= 1'b0;
end
else
begin
case (mstate_in)
R_IDLE: begin
// R_IDLE only applies after reset. Normally each thread will reenter at S_START and
// assumes that input data is waiting (this relies on the threads being started evenly,
// hence the interface FSM at the top of this file)
if (phase!=THREADS && start_flag) // Ensure (phase==THREADS) slot is never active
begin
XCtl <= XSload; // First time only (normally done at end of previous salsa cycle=1023)
`ifndef ONETHREAD
start_flag <= 1'b0;
`endif
busy_flag <= 1'b0; // Toggle the busy flag low to ack pbkdfengine (its usually already set
// since other threads are running)
writeaddr <= 0; // Preset to write X on next cycle
addrsourceMix <= 1'b0;
datasourceLoad <= 1'b1;
ram_wren <= 1'b1;
mstate <= R_START;
end
end
R_START: begin // Reentry point after thread completion. ASSUMES new data is ready.
XCtl <= XSmix;
writeaddr <= writeaddr_next;
cycle <= 0;
if (ADDRBITS == 13)
ram_wren <= 1'b1; // Full scratchpad needs to write to addr=001 next cycle
doneROM <= 1'b0;
busy_flag <= 1'b1;
result <= 1'b0;
mstate <= R_WRITE;
end
R_WRITE: begin
XCtl <= XSmix;
writeaddr <= writeaddr_next;
if (writeaddr_in==1022)
doneROM <= 1'b1; // Need to do one more cycle to update X0,X1
else
if (~doneROM_in)
begin
if (ADDRBITS < 13)
ram_wren <= ~|writeaddr_next[THREADS_BITS+9-ADDRBITSX:0]; // Only write non-interpolated addresses
else
ram_wren <= 1'b1;
end
if (doneROM_in)
begin
addrsourceMix <= 1'b1; // Remains set for duration of R_MIX
mstate <= R_MIX;
XCtl <= XSram; // Load from ram next cycle
// Need this to cover the case of the initial read being interpolated
// NB CODE IS REPLICATED IN R_MIX
if (ADDRBITS < 13)
begin
intcycles <= { {THREADS_BITS+12-ADDRBITSX{1'b0}}, Xaddr[THREADS_BITS+9-ADDRBITSX:0] }; // Interpolated addresses
if ( Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] ) // Highest address reserved
intcycles <= { {THREADS_BITS+11-ADDRBITSX{1'b0}}, 1'b1, Xaddr[THREADS_BITS+9-ADDRBITSX:0] };
if ( (Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1]) || |Xaddr[THREADS_BITS+9-ADDRBITSX:0] )
begin
ram_wren <= 1'b1;
xoren <= 0; // Will do direct load from ram, not xor
mstate <= R_INT; // Interpolate
end
// If intcycles will be set to 1, need to preset for readback
if (
( Xaddr[THREADS_BITS+9-ADDRBITSX:0] == 1 ) &&
!( Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] )
)
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
end
// END REPLICATED BLOCK
end
end
R_MIX: begin
// NB There is an extra step here cf R_WRITE above to read ram data hence 9 not 8 stages.
XCtl <= XSmix;
cycle <= cycle_in + 11'd1;
if (cycle_in==1023)
begin
busy_flag <= 1'b0; // Will hold at 0 for 9 clocks until set at R_START
if (fsmstart) // Check data input is ready
begin
XCtl <= XSload; // Initial load else we overwrite input NB This is
// executed on the next cycle, regardless of phase
// Flag the SHA256 FSM to start final PBKDF2_SHA256_80_128_32
result <= 1'b1;
mstate <= R_START; // Restart immediately
writeaddr <= 0; // Preset to write X on next cycle
datasourceLoad <= 1'b1;
addrsourceMix <= 1'b0;
ram_wren <= 1'b1;
end
else
begin
// mstate <= R_IDLE; // Wait for start_flag
mstate <= R_WAIT;
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
ram_wren <= 1'b1; // Save result
end
end
else
begin
XCtl <= XSram; // Load from ram next cycle
// NB CODE IS REPLICATED IN R_WRITE
if (ADDRBITS < 13)
begin
intcycles <= { {THREADS_BITS+12-ADDRBITSX{1'b0}}, Xaddr[THREADS_BITS+9-ADDRBITSX:0] }; // Interpolated addresses
if ( Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] ) // Highest address reserved
intcycles <= { {THREADS_BITS+11-ADDRBITSX{1'b0}}, 1'b1, Xaddr[THREADS_BITS+9-ADDRBITSX:0] };
if ( (Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1]) || |Xaddr[THREADS_BITS+9-ADDRBITSX:0] )
begin
ram_wren <= 1'b1;
xoren <= 0; // Will do direct load from ram, not xor
mstate <= R_INT; // Interpolate
end
// If intcycles will be set to 1, need to preset for readback
if (
( Xaddr[THREADS_BITS+9-ADDRBITSX:0] == 1 ) &&
!( Xaddr[9:THREADS_BITS+10-ADDRBITSX] == memtop[ADDRBITSX-THREADS_BITS:1] )
)
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
end
// END REPLICATED BLOCK
end
end
R_WAIT: begin
if (fsmstart) // Check data input is ready
begin
XCtl <= XSload; // Initial load else we overwrite input NB This is
// executed on the next cycle, regardless of phase
// Flag the SHA256 FSM to start final PBKDF2_SHA256_80_128_32
result <= 1'b1;
mstate <= R_START; // Restart immediately
writeaddr <= 0; // Preset to write X on next cycle
datasourceLoad <= 1'b1;
resultsourceRam <= 1'b1;
addrsourceMix <= 1'b0;
ram_wren <= 1'b1;
end
else
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
end
R_INT: begin
// Interpolate scratchpad for odd addresses
XCtl <= XSmix;
intcycles <= intcycles_in - 1;
if (intcycles_in==2)
addrsourceSave <= 1'b1; // Preset to read saved data (9 clocks later)
if (intcycles_in==1)
begin
XCtl <= XSram; // Setup to XOR from saved X0/X1 in ram at next cycle
mstate <= R_MIX;
end
// Else mstate remains at R_INT so we continue interpolating
end
endcase
end
`ifdef SIM
// Print the final Xmix for each cycle to compare with scrypt.c (debugging)
if (mstate==R_MIX)
$display ("phase %d cycle %d Xmix %08x\n", phase, cycle-1, Xmix[511:480]);
`endif
end // always @(posedge hash_clk)
endmodule |
// Basic Components; muxes, flip-flops, etc.
//
// Author: Ivan Castellanos
// email: [email protected]
// VLSI Computer Architecture Research Group,
// Oklahoma Stata University
//Reduced Full Adder Cell (for CLA, 8 gates instead of 9)
module rfa (sum, g, p, a, b, cin);
output sum;
output g;
output p;
input a;
input b;
input cin;
//xor x1(sum, a, b, cin);
assign sum = a ^ b ^ cin;
//and a1(g, a, b);
assign g = a & b;
//or o1(p, a, b);
assign p = a | b;
endmodule
//17-bit Register with reset
module dffr_17 (q, d, clk, reset);
output [16:0] q;
input [16:0] d;
input clk, reset;
reg [16:0] q;
always @ (posedge clk or negedge reset)
if (reset == 0)
q <= 0;
else
q <= d;
endmodule
//Basic adders for Multiplier
module FA (Sum, Cout, A, B, Cin);
input A;
input B;
input Cin;
output Sum;
output Cout;
wire w1;
wire w2;
wire w3;
wire w4;
xor x1(w1, A, B);
xor x2(Sum, w1, Cin);
nand n1(w2, A, B);
nand n2(w3, A, Cin);
nand n3(w4, B, Cin);
//nand n4(Cout, w2, w3, w4);
assign Cout = ~ (w2 & w3 & w4);
endmodule // FA
module MFA (Sum, Cout, A, B, Sin, Cin);
input A;
input B;
input Sin;
input Cin;
output Sum;
output Cout;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
and a1(w0, A, B);
xor x1(w1, w0, Sin);
xor x2(Sum, w1, Cin);
nand n1(w2, w0, Sin);
nand n2(w3, w0, Cin);
nand n3(w4, Sin, Cin);
//nand n4(Cout, w2, w3, w4);
assign Cout = ~ (w2 & w3 & w4);
endmodule // MFA
module NMFA (Sum, Cout, A, B, Sin, Cin);
input A;
input B;
input Sin;
input Cin;
output Sum;
output Cout;
wire w0;
wire w1;
wire w2;
wire w3;
wire w4;
nand n0(w0, A, B);
xor x1(w1, w0, Sin);
xor x2(Sum, w1, Cin);
nand n1(w2, w0, Sin);
nand n2(w3, w0, Cin);
nand n3(w4, Sin, Cin);
//nand n4(Cout, w2, w3, w4);
assign Cout = ~ (w2 & w3 & w4);
endmodule // NMFA
module MHA (Sum, Cout, A, B, Sin);
input A;
input B;
input Sin;
output Sum;
output Cout;
wire w1;
and a0(w1, A, B);
xor x1(Sum, w1, Sin);
and a1(Cout, w1, Sin);
endmodule // MHA
// 16-Bit Carry Look Ahead adder, test design for Standard Cell/Custom Design
//
// Author: Ivan Castellanos
// email: [email protected]
// VLSI Computer Architecture Research Group,
// Oklahoma Stata University
module cla16(sum, a, b);
output [16:0] sum;
input [15:0] a,b;
wire [14:0] carry;
wire [15:0] g, p;
wire [4:0] gout, pout;
rfa rfa0(sum[0], g[0], p[0], a[0], b[0], 1'b0);
rfa rfa1(sum[1], g[1], p[1], a[1], b[1], carry[0]);
rfa rfa2(sum[2], g[2], p[2], a[2], b[2], carry[1]);
rfa rfa3(sum[3], g[3], p[3], a[3], b[3], carry[2]);
bclg4 bclg30(carry[2:0], gout[0], pout[0], g[3:0], p[3:0], 1'b0);
rfa rfa4(sum[4], g[4], p[4], a[4], b[4], carry[3]);
rfa rfa5(sum[5], g[5], p[5], a[5], b[5], carry[4]);
rfa rfa6(sum[6], g[6], p[6], a[6], b[6], carry[5]);
rfa rfa7(sum[7], g[7], p[7], a[7], b[7], carry[6]);
bclg4 bclg74(carry[6:4], gout[1], pout[1], g[7:4], p[7:4], carry[3]);
rfa rfa8(sum[8], g[8], p[8], a[8], b[8], carry[7]);
rfa rfa9(sum[9], g[9], p[9], a[9], b[9], carry[8]);
rfa rfa10(sum[10], g[10], p[10], a[10], b[10], carry[9]);
rfa rfa11(sum[11], g[11], p[11], a[11], b[11], carry[10]);
bclg4 bclg118(carry[10:8], gout[2], pout[2], g[11:8], p[11:8], carry[7]);
rfa rfa12(sum[12], g[12], p[12], a[12], b[12], carry[11]);
rfa rfa13(sum[13], g[13], p[13], a[13], b[13], carry[12]);
rfa rfa14(sum[14], g[14], p[14], a[14], b[14], carry[13]);
rfa rfa15(sum[15], g[15], p[15], a[15], b[15], carry[14]);
bclg4 bclg1512(carry[14:12], gout[3], pout[3], g[15:12], p[15:12], carry[11]);
bclg4 bclg_150({carry[11], carry[7], carry[3]}, gout[4], pout[4], {gout[3], gout[2], gout[1], gout[0]}, {pout[3], pout[2], pout[1], pout[0]}, 1'b0);
assign sum[16] = gout[4];
endmodule
// 4-bit Block Carry Look-Ahead Generator
module bclg4 (cout, gout, pout, g, p, cin);
output [2:0] cout;
output gout;
output pout;
input [3:0] g;
input [3:0] p;
input cin;
wire a1_out, a2_out, a3_out, a4_out, a5_out, a6_out;
wire a7_out, a8_out, a9_out;
and a1(a1_out, p[0], cin);
or o1(cout[0], g[0], a1_out);
and a2(a2_out, p[1], g[0]);
//and a3(a3_out, p[1], p[0], cin);
assign a3_out = p[1] & p[0] & cin;
//or o2(cout[1], g[1], a2_out, a3_out);
assign cout[1] = g[1] | a2_out | a2_out;
and a4(a4_out, p[2], g[1]);
//and a5(a5_out, p[2], p[1], g[0]);
assign a5_out = p[2] & p[1] & g[0];
//and a6(a6_out, p[2], p[1], p[0], cin);
assign a6_out = p[2]& p[1]& p[0]& cin;
//or o3(cout[2], g[2], a4_out, a5_out, a6_out);
assign cout[2] = g[2] | a4_out | a5_out | a6_out;
and a7(a7_out, p[3], g[2]);
//and a8(a8_out, p[3], p[2], g[1]);
assign a8_out = p[3] & p[2] & g[1];
//and a9(a9_out, p[3], p[2], p[1], g[0]);
assign a9_out = p[3] & p[2] & p[1] & g[0];
//or o4(gout, g[3], a7_out, a8_out, a9_out);
assign gout= g[3]| a7_out| a8_out| a9_out;
//and a10(pout, p[0], p[1], p[2], p[3]);
assign pout= p[0]& p[1]& p[2]& p[3];
endmodule
//Ivan Castellanos
module multi (P, A, B);
input [7:0] A;
input [7:0] B;
output [15:0] P;
//row b0
wire wa10,wa20,wa30,wa40,wa50,wa60,wn70;
//row b1
wire wmhc01,wmhc11,wmhc21,wmhc31,wmhc41,wmhc51,wmhc61;
wire wmhs11,wmhs21,wmhs31,wmhs41,wmhs51,wmhs61,wn71;
//row b2
wire wmfc02,wmfc12,wmfc22,wmfc32,wmfc42,wmfc52,wmfc62;
wire wmfs12,wmfs22,wmfs32,wmfs42,wmfs52,wmfs62,wn72;
//row b3
wire wmfc03,wmfc13,wmfc23,wmfc33,wmfc43,wmfc53,wmfc63;
wire wmfs13,wmfs23,wmfs33,wmfs43,wmfs53,wmfs63,wn73;
//row b4
wire wmfc04,wmfc14,wmfc24,wmfc34,wmfc44,wmfc54,wmfc64;
wire wmfs14,wmfs24,wmfs34,wmfs44,wmfs54,wmfs64,wn74;
//row b5
wire wmfc05,wmfc15,wmfc25,wmfc35,wmfc45,wmfc55,wmfc65;
wire wmfs15,wmfs25,wmfs35,wmfs45,wmfs55,wmfs65,wn75;
//row b6
wire wmfc06,wmfc16,wmfc26,wmfc36,wmfc46,wmfc56,wmfc66;
wire wmfs16,wmfs26,wmfs36,wmfs46,wmfs56,wmfs66,wn76;
//row b7
wire wnmfc07,wnmfc17,wnmfc27,wnmfc37,wnmfc47,wnmfc57,wnmfc67;
wire wnmfs17,wnmfs27,wnmfs37,wnmfs47,wnmfs57,wnmfs67,wa77;
//row b8
wire wfac08,wfac18,wfac28,wfac38,wfac48,wfac58,wfac68;
//Row bo Implementation
and a00(P[0] , A[0], B[0]);
and a10(wa10 ,A[1], B[0]);
and a20(wa20 ,A[2], B[0]);
and a30(wa30 ,A[3], B[0]);
and a40(wa40 ,A[4], B[0]);
and a50(wa50 ,A[5], B[0]);
and a60(wa60 ,A[6], B[0]);
nand n70(wn70 ,A[7], B[0]);
//Row b1
MHA mha01(.Sum(P[1]), .Cout(wmhc01), .A(A[0]), .B(B[1]), .Sin(wa10));
MHA mha11(.Sum(wmhs11), .Cout(wmhc11), .A(A[1]), .B(B[1]), .Sin(wa20));
MHA mha21(.Sum(wmhs21), .Cout(wmhc21), .A(A[2]), .B(B[1]), .Sin(wa30));
MHA mha31(.Sum(wmhs31), .Cout(wmhc31), .A(A[3]), .B(B[1]), .Sin(wa40));
MHA mha41(.Sum(wmhs41), .Cout(wmhc41), .A(A[4]), .B(B[1]), .Sin(wa50));
MHA mha51(.Sum(wmhs51), .Cout(wmhc51), .A(A[5]), .B(B[1]), .Sin(wa60));
MHA mha61(.Sum(wmhs61), .Cout(wmhc61), .A(A[6]), .B(B[1]), .Sin(wn70));
nand n71(wn71, A[7], B[1]);
//Row b2
MFA mfa02(.Sum(P[2]), .Cout(wmfc02), .A(A[0]), .B(B[2]), .Sin(wmhs11), .Cin(wmhc01));
MFA mfa12(.Sum(wmfs12), .Cout(wmfc12), .A(A[1]), .B(B[2]), .Sin(wmhs21), .Cin(wmhc11));
MFA mfa22(.Sum(wmfs22), .Cout(wmfc22), .A(A[2]), .B(B[2]), .Sin(wmhs31), .Cin(wmhc21));
MFA mfa32(.Sum(wmfs32), .Cout(wmfc32), .A(A[3]), .B(B[2]), .Sin(wmhs41), .Cin(wmhc31));
MFA mfa42(.Sum(wmfs42), .Cout(wmfc42), .A(A[4]), .B(B[2]), .Sin(wmhs51), .Cin(wmhc41));
MFA mfa52(.Sum(wmfs52), .Cout(wmfc52), .A(A[5]), .B(B[2]), .Sin(wmhs61), .Cin(wmhc51));
MFA mfa62(.Sum(wmfs62), .Cout(wmfc62), .A(A[6]), .B(B[2]), .Sin(wn71), .Cin(wmhc61));
nand n72(wn72, A[7], B[2]);
//Row b3
MFA mfa03(.Sum(P[3]), .Cout(wmfc03), .A(A[0]), .B(B[3]), .Sin(wmfs12), .Cin(wmfc02));
MFA mfa13(.Sum(wmfs13), .Cout(wmfc13), .A(A[1]), .B(B[3]), .Sin(wmfs22), .Cin(wmfc12));
MFA mfa23(.Sum(wmfs23), .Cout(wmfc23), .A(A[2]), .B(B[3]), .Sin(wmfs32), .Cin(wmfc22));
MFA mfa33(.Sum(wmfs33), .Cout(wmfc33), .A(A[3]), .B(B[3]), .Sin(wmfs42), .Cin(wmfc32));
MFA mfa43(.Sum(wmfs43), .Cout(wmfc43), .A(A[4]), .B(B[3]), .Sin(wmfs52), .Cin(wmfc42));
MFA mfa53(.Sum(wmfs53), .Cout(wmfc53), .A(A[5]), .B(B[3]), .Sin(wmfs62), .Cin(wmfc52));
MFA mfa63(.Sum(wmfs63), .Cout(wmfc63), .A(A[6]), .B(B[3]), .Sin(wn72), .Cin(wmfc62));
nand n73(wn73, A[7], B[3]);
//Row b4
MFA mfa04(.Sum(P[4]), .Cout(wmfc04), .A(A[0]), .B(B[4]), .Sin(wmfs13), .Cin(wmfc03));
MFA mfa14(.Sum(wmfs14), .Cout(wmfc14), .A(A[1]), .B(B[4]), .Sin(wmfs23), .Cin(wmfc13));
MFA mfa24(.Sum(wmfs24), .Cout(wmfc24), .A(A[2]), .B(B[4]), .Sin(wmfs33), .Cin(wmfc23));
MFA mfa34(.Sum(wmfs34), .Cout(wmfc34), .A(A[3]), .B(B[4]), .Sin(wmfs43), .Cin(wmfc33));
MFA mfa44(.Sum(wmfs44), .Cout(wmfc44), .A(A[4]), .B(B[4]), .Sin(wmfs53), .Cin(wmfc43));
MFA mfa54(.Sum(wmfs54), .Cout(wmfc54), .A(A[5]), .B(B[4]), .Sin(wmfs63), .Cin(wmfc53));
MFA mfa64(.Sum(wmfs64), .Cout(wmfc64), .A(A[6]), .B(B[4]), .Sin(wn73), .Cin(wmfc63));
nand n74(wn74, A[7], B[4]);
//Row b5
MFA mfa05(.Sum(P[5]), .Cout(wmfc05), .A(A[0]), .B(B[5]), .Sin(wmfs14), .Cin(wmfc04));
MFA mfa15(.Sum(wmfs15), .Cout(wmfc15), .A(A[1]), .B(B[5]), .Sin(wmfs24), .Cin(wmfc14));
MFA mfa25(.Sum(wmfs25), .Cout(wmfc25), .A(A[2]), .B(B[5]), .Sin(wmfs34), .Cin(wmfc24));
MFA mfa35(.Sum(wmfs35), .Cout(wmfc35), .A(A[3]), .B(B[5]), .Sin(wmfs44), .Cin(wmfc34));
MFA mfa45(.Sum(wmfs45), .Cout(wmfc45), .A(A[4]), .B(B[5]), .Sin(wmfs54), .Cin(wmfc44));
MFA mfa55(.Sum(wmfs55), .Cout(wmfc55), .A(A[5]), .B(B[5]), .Sin(wmfs64), .Cin(wmfc54));
MFA mfa65(.Sum(wmfs65), .Cout(wmfc65), .A(A[6]), .B(B[5]), .Sin(wn74), .Cin(wmfc64));
nand n75(wn75, A[7], B[5]);
//Row b6
MFA mfa06(.Sum(P[6]), .Cout(wmfc06), .A(A[0]), .B(B[6]), .Sin(wmfs15), .Cin(wmfc05));
MFA mfa16(.Sum(wmfs16), .Cout(wmfc16), .A(A[1]), .B(B[6]), .Sin(wmfs25), .Cin(wmfc15));
MFA mfa26(.Sum(wmfs26), .Cout(wmfc26), .A(A[2]), .B(B[6]), .Sin(wmfs35), .Cin(wmfc25));
MFA mfa36(.Sum(wmfs36), .Cout(wmfc36), .A(A[3]), .B(B[6]), .Sin(wmfs45), .Cin(wmfc35));
MFA mfa46(.Sum(wmfs46), .Cout(wmfc46), .A(A[4]), .B(B[6]), .Sin(wmfs55), .Cin(wmfc45));
MFA mfa56(.Sum(wmfs56), .Cout(wmfc56), .A(A[5]), .B(B[6]), .Sin(wmfs65), .Cin(wmfc55));
MFA mfa66(.Sum(wmfs66), .Cout(wmfc66), .A(A[6]), .B(B[6]), .Sin(wn75), .Cin(wmfc65));
nand n76(wn76, A[7], B[6]);
//Row b7
NMFA nmfa07(.Sum(P[7]), .Cout(wnmfc07), .A(A[0]), .B(B[7]), .Sin(wmfs16), .Cin(wmfc06));
NMFA nmfa17(.Sum(wnmfs17), .Cout(wnmfc17), .A(A[1]), .B(B[7]), .Sin(wmfs26), .Cin(wmfc16));
NMFA nmfa27(.Sum(wnmfs27), .Cout(wnmfc27), .A(A[2]), .B(B[7]), .Sin(wmfs36), .Cin(wmfc26));
NMFA nmfa37(.Sum(wnmfs37), .Cout(wnmfc37), .A(A[3]), .B(B[7]), .Sin(wmfs46), .Cin(wmfc36));
NMFA nmfa47(.Sum(wnmfs47), .Cout(wnmfc47), .A(A[4]), .B(B[7]), .Sin(wmfs56), .Cin(wmfc46));
NMFA nmfa57(.Sum(wnmfs57), .Cout(wnmfc57), .A(A[5]), .B(B[7]), .Sin(wmfs66), .Cin(wmfc56));
NMFA nmfa67(.Sum(wnmfs67), .Cout(wnmfc67), .A(A[6]), .B(B[7]), .Sin(wn76), .Cin(wmfc66));
and a77(wa77, A[7], B[7]);
//Row b8
FA fa08(.Sum(P[8]), .Cout(wfac08), .A(wnmfc07), .B(wnmfs17), .Cin(1'b1));
FA fa18(.Sum(P[9]), .Cout(wfac18), .A(wnmfc17), .B(wnmfs27), .Cin(wfac08));
FA fa28(.Sum(P[10]), .Cout(wfac28), .A(wnmfc27), .B(wnmfs37), .Cin(wfac18));
FA fa38(.Sum(P[11]), .Cout(wfac38), .A(wnmfc37), .B(wnmfs47), .Cin(wfac28));
FA fa48(.Sum(P[12]), .Cout(wfac48), .A(wnmfc47), .B(wnmfs57), .Cin(wfac38));
FA fa58(.Sum(P[13]), .Cout(wfac58), .A(wnmfc57), .B(wnmfs67), .Cin(wfac48));
FA fa68(.Sum(P[14]), .Cout(wfac68), .A(wnmfc67), .B(wa77), .Cin(wfac58));
not inv1(P[15], wfac68);
endmodule // multi
// 16-Bit Multiply Add Unit, test design for Standard Cell/Custom Design
// F = Accumulation ( A * B )
// Author: Ivan Castellanos
// email: [email protected]
// VLSI Computer Architecture Research Group,
// Oklahoma Stata University
module multiplyadd(result, a, b, reset, clk);
output [16:0] result;
input [7:0] a;
input [7:0] b;
input reset;
input clk;
wire [15:0] multiplication;
wire [16:0] sum;
// Custom cell block:
multi multi_module(multiplication, a, b);
cla16 cla16_module(sum, multiplication, result[15:0]);
// Output register is 17-bits long to include Carry out in the result.
dffr_17 accu_output(result, sum, clk, reset);
endmodule
|
//==================================================================================================
// Filename : tb_CORDIC_Arch3.v
// Created On : 2016-10-03 23:39:40
// Last Modified : 2016-10-29 01:07:38
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//==================================================================================================
// Filename : testbench_CORDICArch2.v
// Created On : 2016-10-03 23:33:09
// Last Modified : 2016-10-03 23:33:09
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns/1ps
module testbench_CORDIC_Arch3 (); /* this is automatically generated */
parameter PERIOD = 10;
//ESTAS SON DEFINICIONES QUE SE REALIZAN EN LOS COMANDOS O CONFIGURACIONES
//DEL SIMULADOR O EL SINTETIZADOR
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk; // Reloj del sistema.
reg rst; // Señal de reset del sistema.
reg beg_fsm_cordic; // Señal de inicio de la maquina de estados del módulo CORDIC.
reg ack_cordic; // Señal de acknowledge proveniente de otro módulo que indica que ha recibido el resultado del modulo CORDIC.
reg operation; // Señal que indica si se realiza la operacion seno(1'b1) o coseno(1'b0).
//reg [1:0] r_mode;
reg [W-1:0] data_in; // Dato de entrada, contiene el angulo que se desea calcular en radianes.
reg [1:0] shift_region_flag; // Señal que indica si el ángulo a calcular esta fuera del rango de calculo del algoritmo CORDIC.
//Output Signals
wire ready_cordic; // Señal de salida que indica que se ha completado el calculo del seno/coseno.
wire [W-1:0] data_output; // Bus de datos con el valor final del angulo calculado.
wire overflow_flag; // Bandera de overflow de la operacion.
wire underflow_flag; // Bandera de underflow de la operacion.
wire zero_flag;
wire busy;
`ifdef SINGLE
CORDIC_Arch3_W32_EW8_SW23_SWR26_EWR5 inst_CORDIC_Arch3 (
`endif
`ifdef DOUBLE
CORDIC_Arch3_W64_EW11_SW52_SWR55_EWR6 inst_CORDIC_Arch3 (
`endif
.clk (clk),
.rst (rst),
.beg_fsm_cordic (beg_fsm_cordic),
.ack_cordic (ack_cordic),
.operation (operation),
.data_in (data_in),
.shift_region_flag (shift_region_flag),
.ready_cordic (ready_cordic),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.zero_flag (zero_flag),
.busy (busy),
.data_output (data_output)
);
reg [W-1:0] Array_IN [0:((2**PERIOD)-1)];
//reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
integer Cont_CLK;
integer Recept;
initial begin
clk = 0;
beg_fsm_cordic = 0;
ack_cordic = 0;
operation = 0;
data_in = 0;
shift_region_flag = 2'b00;
rst = 1;
//Depending upong the sumulator, this directive will
//understand that if the macro is defined (e.g. RMODE00)
//then the following code will be added to the compilation
//simulation or sinthesis.
//This is added in order to simulate the accuracy change of the system.
//Abre el archivo testbench
FileSaveData = $fopen("ResultadoXilinxFLM.txt","w");
//Inicializa las variables del testbench
contador = 0;
Cont_CLK = 0;
Recept = 1;
#100 rst = 0;
// #15
// data_in = 32'h3f25514d; //37 grados
// shift_region_flag = 2'b00;
// #5
// beg_fsm_cordic = 1;
// #10
// beg_fsm_cordic = 0;
end
initial begin
`ifdef SINGLE
$readmemh("CORDIC32_input_angles_hex.txt", Array_IN);
`endif
`ifdef DOUBLE
$readmemh("CORDIC64_input_angles_hex.txt", Array_IN);
`endif
end
// clock
initial forever #5 clk = ~clk;
always @(negedge clk) begin
//#(PERIOD/3);
if(rst) begin
contador = 0;
Cont_CLK = 0;
end
else begin
if (contador == (2**PERIOD)) begin
$fclose(FileSaveData);
$finish;
end
else begin
if(Cont_CLK ==1) begin
contador = contador + 1;
beg_fsm_cordic = 0;
data_in = Array_IN[contador];
#40;
Cont_CLK = Cont_CLK + 1;
ack_cordic = 0;
#40;
end
else if(Cont_CLK ==2) begin
ack_cordic = 0;
beg_fsm_cordic = 1;
Cont_CLK = Cont_CLK +1 ;
#40;
end
else begin
ack_cordic = 0;
Cont_CLK = Cont_CLK + 1;
beg_fsm_cordic = 0;
#40;
end
if(ready_cordic==1) begin
ack_cordic = 1;
Cont_CLK = 0;
#15;
end
if(ready_cordic==1 && ack_cordic) begin
Cont_CLK = 0;
#15;
end
end
end
end
// Recepción de datos y almacenamiento en archivo*************
always @(negedge clk) begin
// #(PERIOD/3);
if(ready_cordic) begin
if(Recept == 1) begin
$fwrite(FileSaveData,"%h\n",data_output);
Recept = 0;
end
end
else begin
Recept = 1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUFLP_TB_V
`define SKY130_FD_SC_LP__CLKBUFLP_TB_V
/**
* clkbuflp: Clock tree buffer, Low Power.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkbuflp.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__clkbuflp dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUFLP_TB_V
|
// -- (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.
// --
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//-----------------------------------------------------------------------------
//
// Clock converter module
// Asynchronous clock converter when asynchronous M:N conversion
// Bypass when synchronous and ratio between S and M clock is 1:1
// Synchronous clock converter (S:M or M:S must be integer ratio)
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi_clock_conv
// fifo_generator
// axic_sync_clock_converter
// axic_sample_cycle_ratio
//
// PROTECTED NAMES:
// Instance names "asyncfifo_*" are pattern-matched in core-level UCF.
// Signal names "*_resync" are pattern-matched in core-level UCF.
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_clock_converter_v2_1_axi_clock_converter #
(parameter C_FAMILY = "virtex7",
parameter integer C_AXI_ID_WIDTH = 5, // Width of all ID signals on SI and MI side.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32, // Width of s_axi_awaddr, s_axi_araddr, m_axi_awaddr and
// m_axi_araddr.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 32, // Width of WDATA and RDATA (either side).
// Format: Bit32;
// Range: 'h00000020, 'h00000040, 'h00000080, 'h00000100.
parameter integer C_S_AXI_ACLK_RATIO = 1, // Clock frequency ratio of SI w.r.t. MI.
parameter integer C_M_AXI_ACLK_RATIO = 1, // (Slowest of all clock inputs should have ratio=1.)
// S:M or M:S must be integer ratio.
// Format: Bit32; Range: >='h00000001.
parameter integer C_AXI_IS_ACLK_ASYNC = 1, // Indicates whether S and M clocks are asynchronous.
// FUTURE FEATURE
// Format: Bit1. Range = 1'b0.
parameter integer C_AXI_PROTOCOL = 0, // Protocol of this SI/MI slot.
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 1, // 1 = Propagate all USER signals, 0 = Do not propagate.
parameter integer C_AXI_AWUSER_WIDTH = 1, // Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1, // Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1, // Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1, // Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1, // Width of BUSER signals.
// Range: >= 1.
parameter integer C_AXI_SUPPORTS_WRITE = 1, // Implement AXI write channels
parameter integer C_AXI_SUPPORTS_READ = 1, // Implement AXI read channels
parameter integer C_SYNCHRONIZER_STAGE = 3
)
(
// Slave Interface System Signals
(* KEEP = "TRUE" *) input wire s_axi_aclk,
(* KEEP = "TRUE" *) input wire s_axi_aresetn,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface System Signals
(* KEEP = "TRUE" *) input wire m_axi_aclk,
(* KEEP = "TRUE" *) input wire m_axi_aresetn,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
input wire m_axi_rvalid,
output wire m_axi_rready);
localparam integer P_AXI4 = 0;
localparam integer P_AXI3 = 1;
localparam integer P_AXILITE = 2;
localparam integer P_LIGHT_WT = 0;
localparam integer P_FULLY_REG = 1;
localparam integer P_LUTRAM_ASYNC = 12;
// Sample cycle ratio
localparam P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);
localparam integer P_ROUNDING_OFFSET = P_SI_LT_MI ? (C_S_AXI_ACLK_RATIO/2) : (C_M_AXI_ACLK_RATIO/2);
localparam integer P_ACLK_RATIO = P_SI_LT_MI ?
((C_M_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_S_AXI_ACLK_RATIO) :
((C_S_AXI_ACLK_RATIO + P_ROUNDING_OFFSET) / C_M_AXI_ACLK_RATIO);
// Write Address Port bit positions
localparam integer C_AWUSER_RIGHT = 0;
localparam integer C_AWUSER_WIDTH = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_AWUSER_WIDTH : 0;
localparam integer C_AWQOS_RIGHT = C_AWUSER_RIGHT + C_AWUSER_WIDTH;
localparam integer C_AWQOS_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;
localparam integer C_AWREGION_RIGHT = C_AWQOS_RIGHT + C_AWQOS_WIDTH;
localparam integer C_AWREGION_WIDTH = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;
localparam integer C_AWPROT_RIGHT = C_AWREGION_RIGHT + C_AWREGION_WIDTH;
localparam integer C_AWPROT_WIDTH = 3;
localparam integer C_AWCACHE_RIGHT = C_AWPROT_RIGHT + C_AWPROT_WIDTH;
localparam integer C_AWCACHE_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;
localparam integer C_AWLOCK_RIGHT = C_AWCACHE_RIGHT + C_AWCACHE_WIDTH;
localparam integer C_AWLOCK_WIDTH = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ? 2 : 0;
localparam integer C_AWBURST_RIGHT = C_AWLOCK_RIGHT + C_AWLOCK_WIDTH;
localparam integer C_AWBURST_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;
localparam integer C_AWSIZE_RIGHT = C_AWBURST_RIGHT + C_AWBURST_WIDTH;
localparam integer C_AWSIZE_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;
localparam integer C_AWLEN_RIGHT = C_AWSIZE_RIGHT + C_AWSIZE_WIDTH;
localparam integer C_AWLEN_WIDTH = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;
localparam integer C_AWADDR_RIGHT = C_AWLEN_RIGHT + C_AWLEN_WIDTH;
localparam integer C_AWADDR_WIDTH = C_AXI_ADDR_WIDTH;
localparam integer C_AWID_RIGHT = C_AWADDR_RIGHT + C_AWADDR_WIDTH;
localparam integer C_AWID_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;
localparam integer C_AW_WIDTH = C_AWID_RIGHT + C_AWID_WIDTH;
localparam integer C_FIFO_AW_WIDTH = C_AWUSER_WIDTH+C_AWQOS_WIDTH+C_AWQOS_WIDTH+3+C_AWCACHE_WIDTH+C_AWLOCK_WIDTH+C_AWBURST_WIDTH+C_AWSIZE_WIDTH+C_AWLEN_WIDTH+C_AXI_ADDR_WIDTH+C_AWID_WIDTH;
// Write Data Port bit positions
localparam integer C_WUSER_RIGHT = 0;
localparam integer C_WUSER_WIDTH = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_WUSER_WIDTH : 0;
localparam integer C_WLAST_RIGHT = C_WUSER_RIGHT + C_WUSER_WIDTH;
localparam integer C_WLAST_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;
localparam integer C_WSTRB_RIGHT = C_WLAST_RIGHT + C_WLAST_WIDTH;
localparam integer C_WSTRB_WIDTH = C_AXI_DATA_WIDTH/8;
localparam integer C_WDATA_RIGHT = C_WSTRB_RIGHT + C_WSTRB_WIDTH;
localparam integer C_WDATA_WIDTH = C_AXI_DATA_WIDTH;
localparam integer C_WID_RIGHT = C_WDATA_RIGHT + C_WDATA_WIDTH;
localparam integer C_WID_WIDTH = (C_AXI_PROTOCOL == P_AXI3) ? C_AXI_ID_WIDTH : 0;
localparam integer C_W_WIDTH = C_WID_RIGHT + C_WID_WIDTH;
localparam integer C_FIFO_W_WIDTH = C_WUSER_WIDTH + C_WLAST_WIDTH + C_AXI_DATA_WIDTH/8 + C_AXI_DATA_WIDTH + C_WID_WIDTH;
// Write Response Port bit positions
localparam integer C_BUSER_RIGHT = 0;
localparam integer C_BUSER_WIDTH = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_BUSER_WIDTH : 0;
localparam integer C_BRESP_RIGHT = C_BUSER_RIGHT + C_BUSER_WIDTH;
localparam integer C_BRESP_WIDTH = 2;
localparam integer C_BID_RIGHT = C_BRESP_RIGHT + C_BRESP_WIDTH;
localparam integer C_BID_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;
localparam integer C_B_WIDTH = C_BID_RIGHT + C_BID_WIDTH;
localparam integer C_FIFO_B_WIDTH = C_BUSER_WIDTH + 2 + C_BID_WIDTH;
// Read Address Port bit positions
localparam integer C_ARUSER_RIGHT = 0;
localparam integer C_ARUSER_WIDTH = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_ARUSER_WIDTH : 0;
localparam integer C_ARQOS_RIGHT = C_ARUSER_RIGHT + C_ARUSER_WIDTH;
localparam integer C_ARQOS_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;
localparam integer C_ARREGION_RIGHT = C_ARQOS_RIGHT + C_ARQOS_WIDTH;
localparam integer C_ARREGION_WIDTH = (C_AXI_PROTOCOL == P_AXI4) ? 4 : 0;
localparam integer C_ARPROT_RIGHT = C_ARREGION_RIGHT + C_ARREGION_WIDTH;
localparam integer C_ARPROT_WIDTH = 3;
localparam integer C_ARCACHE_RIGHT = C_ARPROT_RIGHT + C_ARPROT_WIDTH;
localparam integer C_ARCACHE_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? 4 : 0;
localparam integer C_ARLOCK_RIGHT = C_ARCACHE_RIGHT + C_ARCACHE_WIDTH;
localparam integer C_ARLOCK_WIDTH = (C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ? 2 : 0;
localparam integer C_ARBURST_RIGHT = C_ARLOCK_RIGHT + C_ARLOCK_WIDTH;
localparam integer C_ARBURST_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? 2 : 0;
localparam integer C_ARSIZE_RIGHT = C_ARBURST_RIGHT + C_ARBURST_WIDTH;
localparam integer C_ARSIZE_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? 3 : 0;
localparam integer C_ARLEN_RIGHT = C_ARSIZE_RIGHT + C_ARSIZE_WIDTH;
localparam integer C_ARLEN_WIDTH = (C_AXI_PROTOCOL == P_AXI4) ? 8 : (C_AXI_PROTOCOL == P_AXI3) ? 4 : 0;
localparam integer C_ARADDR_RIGHT = C_ARLEN_RIGHT + C_ARLEN_WIDTH;
localparam integer C_ARADDR_WIDTH = C_AXI_ADDR_WIDTH;
localparam integer C_ARID_RIGHT = C_ARADDR_RIGHT + C_ARADDR_WIDTH;
localparam integer C_ARID_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;
localparam integer C_AR_WIDTH = C_ARID_RIGHT + C_ARID_WIDTH;
localparam integer C_FIFO_AR_WIDTH = C_ARUSER_WIDTH+C_ARQOS_WIDTH+C_ARQOS_WIDTH+3+C_ARCACHE_WIDTH+C_ARLOCK_WIDTH+C_ARBURST_WIDTH+C_ARSIZE_WIDTH+C_ARLEN_WIDTH+C_AXI_ADDR_WIDTH+C_ARID_WIDTH;
// Read Data Ports bit positions
localparam integer C_RUSER_RIGHT = 0;
localparam integer C_RUSER_WIDTH = (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? C_AXI_RUSER_WIDTH : 0;
localparam integer C_RLAST_RIGHT = C_RUSER_RIGHT + C_RUSER_WIDTH;
localparam integer C_RLAST_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0;
localparam integer C_RRESP_RIGHT = C_RLAST_RIGHT + C_RLAST_WIDTH;
localparam integer C_RRESP_WIDTH = 2;
localparam integer C_RDATA_RIGHT = C_RRESP_RIGHT + C_RRESP_WIDTH;
localparam integer C_RDATA_WIDTH = C_AXI_DATA_WIDTH;
localparam integer C_RID_RIGHT = C_RDATA_RIGHT + C_RDATA_WIDTH;
localparam integer C_RID_WIDTH = (C_AXI_PROTOCOL != P_AXILITE) ? C_AXI_ID_WIDTH : 0;
localparam integer C_R_WIDTH = C_RID_RIGHT + C_RID_WIDTH;
localparam integer C_FIFO_R_WIDTH = C_RUSER_WIDTH + C_RLAST_WIDTH + 2 + C_AXI_DATA_WIDTH + C_RID_WIDTH;
generate
if ((C_AXI_IS_ACLK_ASYNC == 0) && (P_ACLK_RATIO == 1)) begin : gen_bypass
// Write address port
assign m_axi_awid = s_axi_awid;
assign m_axi_awaddr = s_axi_awaddr;
assign m_axi_awlen = s_axi_awlen;
assign m_axi_awsize = s_axi_awsize;
assign m_axi_awburst = s_axi_awburst;
assign m_axi_awlock = s_axi_awlock;
assign m_axi_awcache = s_axi_awcache;
assign m_axi_awprot = s_axi_awprot;
assign m_axi_awregion = s_axi_awregion;
assign m_axi_awqos = s_axi_awqos;
assign m_axi_awuser = s_axi_awuser;
assign m_axi_awvalid = s_axi_awvalid;
assign s_axi_awready = m_axi_awready;
// Write Data Port
assign m_axi_wid = s_axi_wid;
assign m_axi_wdata = s_axi_wdata;
assign m_axi_wstrb = s_axi_wstrb;
assign m_axi_wlast = s_axi_wlast;
assign m_axi_wuser = s_axi_wuser;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_wready = m_axi_wready;
// Write Response Port
assign s_axi_bid = m_axi_bid;
assign s_axi_bresp = m_axi_bresp;
assign s_axi_buser = m_axi_buser;
assign s_axi_bvalid = m_axi_bvalid;
assign m_axi_bready = s_axi_bready;
// Read Address Port
assign m_axi_arid = s_axi_arid;
assign m_axi_araddr = s_axi_araddr;
assign m_axi_arlen = s_axi_arlen;
assign m_axi_arsize = s_axi_arsize;
assign m_axi_arburst = s_axi_arburst;
assign m_axi_arlock = s_axi_arlock;
assign m_axi_arcache = s_axi_arcache;
assign m_axi_arprot = s_axi_arprot;
assign m_axi_arregion = s_axi_arregion;
assign m_axi_arqos = s_axi_arqos;
assign m_axi_aruser = s_axi_aruser;
assign m_axi_arvalid = s_axi_arvalid;
assign s_axi_arready = m_axi_arready;
// Read Data Port
assign s_axi_rid = m_axi_rid;
assign s_axi_rdata = m_axi_rdata;
assign s_axi_rresp = m_axi_rresp;
assign s_axi_rlast = m_axi_rlast;
assign s_axi_ruser = m_axi_ruser;
assign s_axi_rvalid = m_axi_rvalid;
assign m_axi_rready = s_axi_rready;
end else begin : gen_clock_conv
wire fast_aclk;
wire slow_aclk;
wire sample_cycle;
wire sample_cycle_early;
// Write Address Port FIFO data read and write
wire [C_AW_WIDTH-1:0] s_aw_mesg ;
wire [C_AW_WIDTH-1:0] m_aw_mesg ;
// Write Data Port FIFO data read and write
wire [C_W_WIDTH-1:0] s_w_mesg;
wire [C_W_WIDTH-1:0] m_w_mesg;
// Write Response Port FIFO data read and write
wire [C_B_WIDTH-1:0] s_b_mesg;
wire [C_B_WIDTH-1:0] m_b_mesg;
// Read Address Port FIFO data read and write
wire [C_AR_WIDTH-1:0] s_ar_mesg;
wire [C_AR_WIDTH-1:0] m_ar_mesg;
// Read Data Ports FIFO data read and write
wire [C_R_WIDTH-1:0] s_r_mesg;
wire [C_R_WIDTH-1:0] m_r_mesg;
wire async_conv_reset_n;
assign async_conv_reset_n = ~(~s_axi_aresetn | ~m_axi_aresetn);
wire [C_AXI_ID_WIDTH-1:0] si_cc_awid ;
wire [C_AXI_ADDR_WIDTH-1:0] si_cc_awaddr ;
wire [((C_AXI_PROTOCOL==0)?8:4)-1:0] si_cc_awlen ;
wire [3-1:0] si_cc_awsize ;
wire [2-1:0] si_cc_awburst ;
wire [((C_AXI_PROTOCOL==0)?1:2)-1:0] si_cc_awlock ;
wire [4-1:0] si_cc_awcache ;
wire [3-1:0] si_cc_awprot ;
wire [4-1:0] si_cc_awregion ;
wire [4-1:0] si_cc_awqos ;
wire [C_AXI_AWUSER_WIDTH-1:0] si_cc_awuser ;
wire si_cc_awvalid ;
wire si_cc_awready ;
wire [C_AXI_ID_WIDTH-1:0] si_cc_wid ;
wire [C_AXI_DATA_WIDTH-1:0] si_cc_wdata ;
wire [C_AXI_DATA_WIDTH/8-1:0] si_cc_wstrb ;
wire si_cc_wlast ;
wire [C_AXI_WUSER_WIDTH-1:0] si_cc_wuser ;
wire si_cc_wvalid ;
wire si_cc_wready ;
wire [C_AXI_ID_WIDTH-1:0] si_cc_bid ;
wire [2-1:0] si_cc_bresp ;
wire [C_AXI_BUSER_WIDTH-1:0] si_cc_buser ;
wire si_cc_bvalid ;
wire si_cc_bready ;
wire [C_AXI_ID_WIDTH-1:0] si_cc_arid ;
wire [C_AXI_ADDR_WIDTH-1:0] si_cc_araddr ;
wire [((C_AXI_PROTOCOL==0)?8:4)-1:0] si_cc_arlen ;
wire [3-1:0] si_cc_arsize ;
wire [2-1:0] si_cc_arburst ;
wire [((C_AXI_PROTOCOL==0)?1:2)-1:0] si_cc_arlock ;
wire [4-1:0] si_cc_arcache ;
wire [3-1:0] si_cc_arprot ;
wire [4-1:0] si_cc_arregion ;
wire [4-1:0] si_cc_arqos ;
wire [C_AXI_ARUSER_WIDTH-1:0] si_cc_aruser ;
wire si_cc_arvalid ;
wire si_cc_arready ;
wire [C_AXI_ID_WIDTH-1:0] si_cc_rid ;
wire [C_AXI_DATA_WIDTH-1:0] si_cc_rdata ;
wire [2-1:0] si_cc_rresp ;
wire si_cc_rlast ;
wire [C_AXI_RUSER_WIDTH-1:0] si_cc_ruser ;
wire si_cc_rvalid ;
wire si_cc_rready ;
wire [C_AXI_ID_WIDTH-1:0] cc_mi_awid ;
wire [C_AXI_ADDR_WIDTH-1:0] cc_mi_awaddr ;
wire [((C_AXI_PROTOCOL==0)?8:4)-1:0] cc_mi_awlen ;
wire [3-1:0] cc_mi_awsize ;
wire [2-1:0] cc_mi_awburst ;
wire [((C_AXI_PROTOCOL==0)?1:2)-1:0] cc_mi_awlock ;
wire [4-1:0] cc_mi_awcache ;
wire [3-1:0] cc_mi_awprot ;
wire [4-1:0] cc_mi_awregion ;
wire [4-1:0] cc_mi_awqos ;
wire [C_AXI_AWUSER_WIDTH-1:0] cc_mi_awuser ;
wire cc_mi_awvalid ;
wire cc_mi_awready ;
wire [C_AXI_ID_WIDTH-1:0] cc_mi_wid ;
wire [C_AXI_DATA_WIDTH-1:0] cc_mi_wdata ;
wire [C_AXI_DATA_WIDTH/8-1:0] cc_mi_wstrb ;
wire cc_mi_wlast ;
wire [C_AXI_WUSER_WIDTH-1:0] cc_mi_wuser ;
wire cc_mi_wvalid ;
wire cc_mi_wready ;
wire [C_AXI_ID_WIDTH-1:0] cc_mi_bid ;
wire [2-1:0] cc_mi_bresp ;
wire [C_AXI_BUSER_WIDTH-1:0] cc_mi_buser ;
wire cc_mi_bvalid ;
wire cc_mi_bready ;
wire [C_AXI_ID_WIDTH-1:0] cc_mi_arid ;
wire [C_AXI_ADDR_WIDTH-1:0] cc_mi_araddr ;
wire [((C_AXI_PROTOCOL==0)?8:4)-1:0] cc_mi_arlen ;
wire [3-1:0] cc_mi_arsize ;
wire [2-1:0] cc_mi_arburst ;
wire [((C_AXI_PROTOCOL==0)?1:2)-1:0] cc_mi_arlock ;
wire [4-1:0] cc_mi_arcache ;
wire [3-1:0] cc_mi_arprot ;
wire [4-1:0] cc_mi_arregion ;
wire [4-1:0] cc_mi_arqos ;
wire [C_AXI_ARUSER_WIDTH-1:0] cc_mi_aruser ;
wire cc_mi_arvalid ;
wire cc_mi_arready ;
wire [C_AXI_ID_WIDTH-1:0] cc_mi_rid ;
wire [C_AXI_DATA_WIDTH-1:0] cc_mi_rdata ;
wire [2-1:0] cc_mi_rresp ;
wire cc_mi_rlast ;
wire [C_AXI_RUSER_WIDTH-1:0] cc_mi_ruser ;
wire cc_mi_rvalid ;
wire cc_mi_rready ;
// Tie-offs
assign si_cc_awid = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awid : 0 ;
assign si_cc_awaddr = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awaddr : 0 ;
assign si_cc_awlen = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL==P_AXI4 ) ? s_axi_awlen : {4'b0000, s_axi_awlen[3:0]}) : 0 ;
assign si_cc_awsize = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awsize : 0 ;
assign si_cc_awburst = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awburst : 0 ;
assign si_cc_awlock = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_awlock : {1'b0, s_axi_awlock[0]}) : 0 ;
assign si_cc_awcache = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awcache : 0 ;
assign si_cc_awprot = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awprot : 0 ;
assign si_cc_awqos = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_awqos : 0 ;
assign si_cc_awregion = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_awregion : 0 ;
assign si_cc_awuser = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_awuser : 0 ;
assign si_cc_awvalid = (C_AXI_SUPPORTS_WRITE ) ? s_axi_awvalid : 0 ;
assign si_cc_wid = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? s_axi_wid : 0 ;
assign si_cc_wdata = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wdata : 0 ;
assign si_cc_wstrb = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wstrb : 0 ;
assign si_cc_wlast = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_wlast : 1'b0 ;
assign si_cc_wuser = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_wuser : 0 ;
assign si_cc_wvalid = (C_AXI_SUPPORTS_WRITE ) ? s_axi_wvalid : 0 ;
assign si_cc_bready = (C_AXI_SUPPORTS_WRITE ) ? s_axi_bready : 0 ;
assign si_cc_arid = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arid : 0 ;
assign si_cc_araddr = (C_AXI_SUPPORTS_READ ) ? s_axi_araddr : 0 ;
assign si_cc_arlen = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL==P_AXI4 ) ? s_axi_arlen : {4'b0000, s_axi_arlen[3:0]}) : 0 ;
assign si_cc_arsize = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arsize : 0 ;
assign si_cc_arburst = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arburst : 0 ;
assign si_cc_arlock = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? s_axi_arlock : {1'b0, s_axi_arlock[0]}) : 0 ;
assign si_cc_arcache = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arcache : 0 ;
assign si_cc_arprot = (C_AXI_SUPPORTS_READ ) ? s_axi_arprot : 0 ;
assign si_cc_arqos = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? s_axi_arqos : 0 ;
assign si_cc_arregion = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? s_axi_arregion : 0 ;
assign si_cc_aruser = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? s_axi_aruser : 0 ;
assign si_cc_arvalid = (C_AXI_SUPPORTS_READ ) ? s_axi_arvalid : 0 ;
assign si_cc_rready = (C_AXI_SUPPORTS_READ ) ? s_axi_rready : 0 ;
assign s_axi_awready = (C_AXI_SUPPORTS_WRITE ) ? si_cc_awready : 0 ;
assign s_axi_wready = (C_AXI_SUPPORTS_WRITE ) ? si_cc_wready : 0 ;
assign s_axi_bid = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_bid : 0 ;
assign s_axi_bresp = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bresp : 0 ;
assign s_axi_buser = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_buser : 0 ;
assign s_axi_bvalid = (C_AXI_SUPPORTS_WRITE ) ? si_cc_bvalid : 0 ;
assign s_axi_arready = (C_AXI_SUPPORTS_READ ) ? si_cc_arready : 0 ;
assign s_axi_rid = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rid : 0 ;
assign s_axi_rdata = (C_AXI_SUPPORTS_READ ) ? si_cc_rdata : 0 ;
assign s_axi_rresp = (C_AXI_SUPPORTS_READ ) ? si_cc_rresp : 0 ;
assign s_axi_rlast = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? si_cc_rlast : 0 ;
assign s_axi_ruser = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? si_cc_ruser : 0 ;
assign s_axi_rvalid = (C_AXI_SUPPORTS_READ ) ? si_cc_rvalid : 0 ;
assign m_axi_awid = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awid : 0 ;
assign m_axi_awaddr = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awaddr : 0 ;
assign m_axi_awlen = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL==P_AXI4 ) ? cc_mi_awlen : cc_mi_awlen[3:0]) : 0 ;
assign m_axi_awsize = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awsize : 0 ;
assign m_axi_awburst = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awburst : 0 ;
assign m_axi_awlock = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_awlock : cc_mi_awlock[0]) : 0 ;
assign m_axi_awcache = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awcache : 0 ;
assign m_axi_awprot = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awprot : 0 ;
assign m_axi_awregion = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_awregion : 0 ;
assign m_axi_awqos = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_awqos : 0 ;
assign m_axi_awuser = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_awuser : 0 ;
assign m_axi_awvalid = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_awvalid : 0 ;
assign m_axi_wid = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL==P_AXI3) ) ? cc_mi_wid : 0 ;
assign m_axi_wdata = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wdata : 0 ;
assign m_axi_wstrb = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wstrb : 0 ;
assign m_axi_wlast = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_wlast : 0 ;
assign m_axi_wuser = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_wuser : 0 ;
assign m_axi_wvalid = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_wvalid : 0 ;
assign m_axi_bready = (C_AXI_SUPPORTS_WRITE ) ? cc_mi_bready : 0 ;
assign m_axi_arid = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arid : 0 ;
assign m_axi_araddr = (C_AXI_SUPPORTS_READ ) ? cc_mi_araddr : 0 ;
assign m_axi_arlen = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE)) ? ((C_AXI_PROTOCOL==P_AXI4 ) ? cc_mi_arlen : cc_mi_arlen[3:0]) : 0 ;
assign m_axi_arsize = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arsize : 0 ;
assign m_axi_arburst = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arburst : 0 ;
assign m_axi_arlock = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? ((C_AXI_PROTOCOL==P_AXI3) ? cc_mi_arlock : cc_mi_arlock[0]) : 0 ;
assign m_axi_arcache = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arcache : 0 ;
assign m_axi_arprot = (C_AXI_SUPPORTS_READ ) ? cc_mi_arprot : 0 ;
assign m_axi_arregion = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL==P_AXI4) ) ? cc_mi_arregion : 0 ;
assign m_axi_arqos = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? cc_mi_arqos : 0 ;
assign m_axi_aruser = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? cc_mi_aruser : 0 ;
assign m_axi_arvalid = (C_AXI_SUPPORTS_READ ) ? cc_mi_arvalid : 0 ;
assign m_axi_rready = (C_AXI_SUPPORTS_READ ) ? cc_mi_rready : 0 ;
assign cc_mi_awready = (C_AXI_SUPPORTS_WRITE ) ? m_axi_awready : 0 ;
assign cc_mi_wready = (C_AXI_SUPPORTS_WRITE ) ? m_axi_wready : 0 ;
assign cc_mi_bid = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_bid : 0 ;
assign cc_mi_bresp = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bresp : 0 ;
assign cc_mi_buser = (C_AXI_SUPPORTS_WRITE && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_buser : 0 ;
assign cc_mi_bvalid = (C_AXI_SUPPORTS_WRITE ) ? m_axi_bvalid : 0 ;
assign cc_mi_arready = (C_AXI_SUPPORTS_READ ) ? m_axi_arready : 0 ;
assign cc_mi_rid = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rid : 0 ;
assign cc_mi_rdata = (C_AXI_SUPPORTS_READ ) ? m_axi_rdata : 0 ;
assign cc_mi_rresp = (C_AXI_SUPPORTS_READ ) ? m_axi_rresp : 0 ;
assign cc_mi_rlast = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) ) ? m_axi_rlast : 1'b0 ;
assign cc_mi_ruser = (C_AXI_SUPPORTS_READ && (C_AXI_PROTOCOL!=P_AXILITE) && (C_AXI_SUPPORTS_USER_SIGNALS!=0) ) ? m_axi_ruser : 0 ;
assign cc_mi_rvalid = (C_AXI_SUPPORTS_READ ) ? m_axi_rvalid : 0 ;
if (C_AXI_IS_ACLK_ASYNC) begin : gen_async_conv
fifo_generator_v12_0 #(
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE((C_AXI_PROTOCOL == P_AXI4) ? 1 : (C_AXI_PROTOCOL == P_AXI3) ? 3 : 2),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH(C_AXI_DATA_WIDTH),
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
.C_AXI_ARUSER_WIDTH(C_AXI_ARUSER_WIDTH),
.C_AXI_AWUSER_WIDTH(C_AXI_AWUSER_WIDTH),
.C_AXI_BUSER_WIDTH(C_AXI_BUSER_WIDTH),
.C_AXI_RUSER_WIDTH(C_AXI_RUSER_WIDTH),
.C_AXI_WUSER_WIDTH(C_AXI_WUSER_WIDTH),
.C_HAS_AXI_ID((C_AXI_PROTOCOL != P_AXILITE) ? 1 : 0),
.C_AXI_LEN_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 8 : 4),
.C_AXI_LOCK_WIDTH((C_AXI_PROTOCOL == P_AXI4) ? 1 : 2),
.C_HAS_AXI_ARUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),
.C_HAS_AXI_AWUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),
.C_HAS_AXI_BUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),
.C_HAS_AXI_RUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),
.C_HAS_AXI_WUSER((C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) ? 1 : 0),
.C_DIN_WIDTH_RACH(C_FIFO_AR_WIDTH),
.C_DIN_WIDTH_RDCH(C_FIFO_R_WIDTH),
.C_DIN_WIDTH_WACH(C_FIFO_AW_WIDTH),
.C_DIN_WIDTH_WDCH(C_FIFO_W_WIDTH),
.C_DIN_WIDTH_WRCH(C_FIFO_B_WIDTH),
.C_HAS_AXI_RD_CHANNEL(C_AXI_SUPPORTS_READ),
.C_HAS_AXI_WR_CHANNEL(C_AXI_SUPPORTS_WRITE),
.C_RACH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),
.C_RDCH_TYPE(C_AXI_SUPPORTS_READ ? 0 : 2),
.C_WACH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),
.C_WDCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),
.C_WRCH_TYPE(C_AXI_SUPPORTS_WRITE ? 0 : 2),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(12),
.C_IMPLEMENTATION_TYPE_WDCH(12),
.C_IMPLEMENTATION_TYPE_WRCH(12),
.C_IMPLEMENTATION_TYPE_RACH(12),
.C_IMPLEMENTATION_TYPE_RDCH(12),
.C_IMPLEMENTATION_TYPE_AXIS(11),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(16),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(4),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
)
asyncfifo_axi (
.s_aclk(s_axi_aclk),
.m_aclk(m_axi_aclk),
.s_aresetn(async_conv_reset_n),
.s_axi_awid (si_cc_awid),
.s_axi_awaddr (si_cc_awaddr),
.s_axi_awlen (si_cc_awlen),
.s_axi_awsize (si_cc_awsize),
.s_axi_awburst (si_cc_awburst),
.s_axi_awlock (si_cc_awlock),
.s_axi_awcache (si_cc_awcache),
.s_axi_awprot (si_cc_awprot),
.s_axi_awqos (si_cc_awqos),
.s_axi_awregion (si_cc_awregion),
.s_axi_awuser (si_cc_awuser),
.s_axi_awvalid (si_cc_awvalid),
.s_axi_awready (si_cc_awready),
.s_axi_wid (si_cc_wid),
.s_axi_wdata (si_cc_wdata),
.s_axi_wstrb (si_cc_wstrb),
.s_axi_wlast (si_cc_wlast),
.s_axi_wuser (si_cc_wuser),
.s_axi_wvalid (si_cc_wvalid),
.s_axi_wready (si_cc_wready),
.s_axi_bid (si_cc_bid),
.s_axi_bresp (si_cc_bresp),
.s_axi_buser (si_cc_buser),
.s_axi_bvalid (si_cc_bvalid),
.s_axi_bready (si_cc_bready),
.m_axi_awid (cc_mi_awid),
.m_axi_awaddr (cc_mi_awaddr),
.m_axi_awlen (cc_mi_awlen),
.m_axi_awsize (cc_mi_awsize),
.m_axi_awburst (cc_mi_awburst),
.m_axi_awlock (cc_mi_awlock),
.m_axi_awcache (cc_mi_awcache),
.m_axi_awprot (cc_mi_awprot),
.m_axi_awqos (cc_mi_awqos),
.m_axi_awregion (cc_mi_awregion),
.m_axi_awuser (cc_mi_awuser),
.m_axi_awvalid (cc_mi_awvalid),
.m_axi_awready (cc_mi_awready),
.m_axi_wid (cc_mi_wid),
.m_axi_wdata (cc_mi_wdata),
.m_axi_wstrb (cc_mi_wstrb),
.m_axi_wlast (cc_mi_wlast),
.m_axi_wuser (cc_mi_wuser),
.m_axi_wvalid (cc_mi_wvalid),
.m_axi_wready (cc_mi_wready),
.m_axi_bid (cc_mi_bid),
.m_axi_bresp (cc_mi_bresp),
.m_axi_buser (cc_mi_buser),
.m_axi_bvalid (cc_mi_bvalid),
.m_axi_bready (cc_mi_bready),
.s_axi_arid (si_cc_arid),
.s_axi_araddr (si_cc_araddr),
.s_axi_arlen (si_cc_arlen),
.s_axi_arsize (si_cc_arsize),
.s_axi_arburst (si_cc_arburst),
.s_axi_arlock (si_cc_arlock),
.s_axi_arcache (si_cc_arcache),
.s_axi_arprot (si_cc_arprot),
.s_axi_arqos (si_cc_arqos),
.s_axi_arregion (si_cc_arregion),
.s_axi_aruser (si_cc_aruser),
.s_axi_arvalid (si_cc_arvalid),
.s_axi_arready (si_cc_arready),
.s_axi_rid (si_cc_rid),
.s_axi_rdata (si_cc_rdata),
.s_axi_rresp (si_cc_rresp),
.s_axi_rlast (si_cc_rlast),
.s_axi_ruser (si_cc_ruser),
.s_axi_rvalid (si_cc_rvalid),
.s_axi_rready (si_cc_rready),
.m_axi_arid (cc_mi_arid),
.m_axi_araddr (cc_mi_araddr),
.m_axi_arlen (cc_mi_arlen),
.m_axi_arsize (cc_mi_arsize),
.m_axi_arburst (cc_mi_arburst),
.m_axi_arlock (cc_mi_arlock),
.m_axi_arcache (cc_mi_arcache),
.m_axi_arprot (cc_mi_arprot),
.m_axi_arqos (cc_mi_arqos),
.m_axi_arregion (cc_mi_arregion),
.m_axi_aruser (cc_mi_aruser),
.m_axi_arvalid (cc_mi_arvalid),
.m_axi_arready (cc_mi_arready),
.m_axi_rid (cc_mi_rid),
.m_axi_rdata (cc_mi_rdata),
.m_axi_rresp (cc_mi_rresp),
.m_axi_rlast (cc_mi_rlast),
.m_axi_ruser (cc_mi_ruser),
.m_axi_rvalid (cc_mi_rvalid),
.m_axi_rready (cc_mi_rready),
.m_aclk_en(1'b1),
.s_aclk_en(1'b1),
.almost_empty(),
.almost_full(),
.axis_data_count(),
.axis_dbiterr(),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(),
.axis_prog_empty(),
.axis_prog_empty_thresh(10'b0),
.axis_prog_full(),
.axis_prog_full_thresh(10'b0),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_underflow(),
.axis_wr_data_count(),
.axi_ar_data_count(),
.axi_ar_dbiterr(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(),
.axi_ar_prog_empty(),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_prog_full(),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_underflow(),
.axi_ar_wr_data_count(),
.axi_aw_data_count(),
.axi_aw_dbiterr(),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(),
.axi_aw_prog_empty(),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_prog_full(),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_underflow(),
.axi_aw_wr_data_count(),
.axi_b_data_count(),
.axi_b_dbiterr(),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(),
.axi_b_prog_empty(),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_prog_full(),
.axi_b_prog_full_thresh(4'b0),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_underflow(),
.axi_b_wr_data_count(),
.axi_r_data_count(),
.axi_r_dbiterr(),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(),
.axi_r_prog_empty(),
.axi_r_prog_empty_thresh(4'b0),
.axi_r_prog_full(),
.axi_r_prog_full_thresh(4'b0),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_underflow(),
.axi_r_wr_data_count(),
.axi_w_data_count(),
.axi_w_dbiterr(),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(),
.axi_w_prog_empty(),
.axi_w_prog_empty_thresh(4'b0),
.axi_w_prog_full(),
.axi_w_prog_full_thresh(4'b0),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_underflow(),
.axi_w_wr_data_count(),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(),
.dbiterr(),
.din(18'b0),
.dout(),
.empty(),
.full(),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_axis_tdata(),
.m_axis_tdest(),
.m_axis_tid(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tready(1'b0),
.m_axis_tstrb(),
.m_axis_tuser(),
.m_axis_tvalid(),
.overflow(),
.prog_empty(),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full(),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.rd_clk(1'b0),
.rd_data_count(),
.rd_en(1'b0),
.rd_rst(1'b0),
.rst(1'b0),
.sbiterr(),
.srst(1'b0),
.s_axis_tdata(8'b0),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(),
.s_axis_tstrb(1'b0),
.s_axis_tuser(4'b0),
.s_axis_tvalid(1'b0),
.underflow(),
.valid(),
.wr_ack(),
.wr_clk(1'b0),
.wr_data_count(),
.wr_en(1'b0),
.wr_rst(1'b0),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
end else begin : gen_sync_conv
assign {fast_aclk, slow_aclk} = P_SI_LT_MI ? {m_axi_aclk, s_axi_aclk} : {s_axi_aclk, m_axi_aclk};
// Sample cycle used to determine when to assert a signal on a fast clock
// to be flopped onto a slow clock.
axi_clock_converter_v2_1_axic_sample_cycle_ratio #(
.C_RATIO ( P_ACLK_RATIO )
)
axic_sample_cycle_inst (
.SLOW_ACLK ( slow_aclk ) ,
.FAST_ACLK ( fast_aclk ) ,
.SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,
.SAMPLE_CYCLE ( sample_cycle )
);
////////////////////////////////////////////////////////////////////////////////
// AXI write channels
////////////////////////////////////////////////////////////////////////////////
if (C_AXI_SUPPORTS_WRITE) begin : gen_conv_write_ch
// Write Address Port
assign s_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH] = si_cc_awaddr ;
assign s_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH] = si_cc_awprot ;
assign cc_mi_awaddr = m_aw_mesg[C_AWADDR_RIGHT+:C_AWADDR_WIDTH];
assign cc_mi_awprot = m_aw_mesg[C_AWPROT_RIGHT+:C_AWPROT_WIDTH];
if (C_AXI_PROTOCOL == P_AXI4) begin : gen_aw_axi4
assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH] = si_cc_awid ;
assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH] = si_cc_awlen ;
assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH] = si_cc_awsize ;
assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH] = si_cc_awburst ;
assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH] = si_cc_awlock[0] ;
assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH] = si_cc_awcache ;
assign s_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH] = si_cc_awregion ;
assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH] = si_cc_awqos ;
assign cc_mi_awid = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];
assign cc_mi_awlen = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];
assign cc_mi_awsize = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];
assign cc_mi_awburst = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];
assign cc_mi_awlock = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];
assign cc_mi_awcache = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];
assign cc_mi_awregion = m_aw_mesg[C_AWREGION_RIGHT+:C_AWREGION_WIDTH];
assign cc_mi_awqos = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];
end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_aw_axi3
assign s_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH] = si_cc_awid ;
assign s_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH] = si_cc_awlen[3:0] ;
assign s_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH] = si_cc_awsize ;
assign s_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH] = si_cc_awburst ;
assign s_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH] = si_cc_awlock ;
assign s_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH] = si_cc_awcache ;
assign s_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH] = si_cc_awqos ;
assign cc_mi_awid = m_aw_mesg[C_AWID_RIGHT+:C_AWID_WIDTH];
assign cc_mi_awlen = m_aw_mesg[C_AWLEN_RIGHT+:C_AWLEN_WIDTH];
assign cc_mi_awsize = m_aw_mesg[C_AWSIZE_RIGHT+:C_AWSIZE_WIDTH];
assign cc_mi_awburst = m_aw_mesg[C_AWBURST_RIGHT+:C_AWBURST_WIDTH];
assign cc_mi_awlock = m_aw_mesg[C_AWLOCK_RIGHT+:C_AWLOCK_WIDTH];
assign cc_mi_awcache = m_aw_mesg[C_AWCACHE_RIGHT+:C_AWCACHE_WIDTH];
assign cc_mi_awqos = m_aw_mesg[C_AWQOS_RIGHT+:C_AWQOS_WIDTH];
end
if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_aw_user
assign s_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH] = si_cc_awuser;
assign cc_mi_awuser = m_aw_mesg[C_AWUSER_RIGHT+:C_AWUSER_WIDTH];
end
axi_clock_converter_v2_1_axic_sync_clock_converter #(
.C_FAMILY ( C_FAMILY ) ,
.C_PAYLOAD_WIDTH ( C_AW_WIDTH ) ,
.C_S_ACLK_RATIO ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,
.C_M_ACLK_RATIO ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,
.C_MODE(P_LIGHT_WT)
)
aw_sync_clock_converter (
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early),
.S_ACLK ( s_axi_aclk ) ,
.S_ARESETN ( s_axi_aresetn ) ,
.S_PAYLOAD ( s_aw_mesg ) ,
.S_VALID ( si_cc_awvalid ) ,
.S_READY ( si_cc_awready ) ,
.M_ACLK ( m_axi_aclk ) ,
.M_ARESETN ( m_axi_aresetn ) ,
.M_PAYLOAD ( m_aw_mesg ) ,
.M_VALID ( cc_mi_awvalid ) ,
.M_READY ( cc_mi_awready )
);
// Write Data Port
assign s_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH] = si_cc_wdata;
assign s_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH] = si_cc_wstrb;
assign cc_mi_wdata = m_w_mesg[C_WDATA_RIGHT+:C_WDATA_WIDTH];
assign cc_mi_wstrb = m_w_mesg[C_WSTRB_RIGHT+:C_WSTRB_WIDTH];
if (C_AXI_PROTOCOL == P_AXI4) begin : gen_w_axi4
assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;
assign cc_mi_wlast = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];
end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_w_axi3
assign s_w_mesg[C_WID_RIGHT+:C_WID_WIDTH] = si_cc_wid;
assign s_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH] = si_cc_wlast;
assign cc_mi_wid = m_w_mesg[C_WID_RIGHT+:C_WID_WIDTH];
assign cc_mi_wlast = m_w_mesg[C_WLAST_RIGHT+:C_WLAST_WIDTH];
end
if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_w_user
assign s_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH] = si_cc_wuser;
assign cc_mi_wuser = m_w_mesg[C_WUSER_RIGHT+:C_WUSER_WIDTH];
end
axi_clock_converter_v2_1_axic_sync_clock_converter #(
.C_FAMILY ( C_FAMILY ) ,
.C_PAYLOAD_WIDTH ( C_W_WIDTH ) ,
.C_S_ACLK_RATIO ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,
.C_M_ACLK_RATIO ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,
.C_MODE ((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)
)
w_sync_clock_converter (
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early),
.S_ACLK ( s_axi_aclk ) ,
.S_ARESETN ( s_axi_aresetn ) ,
.S_PAYLOAD ( s_w_mesg ) ,
.S_VALID ( si_cc_wvalid ) ,
.S_READY ( si_cc_wready ) ,
.M_ACLK ( m_axi_aclk ) ,
.M_ARESETN ( m_axi_aresetn ) ,
.M_PAYLOAD ( m_w_mesg ) ,
.M_VALID ( cc_mi_wvalid ) ,
.M_READY ( cc_mi_wready )
);
// Write Response Port
assign m_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH] = cc_mi_bresp;
assign si_cc_bresp = s_b_mesg[C_BRESP_RIGHT+:C_BRESP_WIDTH];
if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_b_axi
assign m_b_mesg[C_BID_RIGHT+:C_BID_WIDTH] = cc_mi_bid;
assign si_cc_bid = s_b_mesg[C_BID_RIGHT+:C_BID_WIDTH];
end
if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_b_user
assign m_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH] = cc_mi_buser;
assign si_cc_buser = s_b_mesg[C_BUSER_RIGHT+:C_BUSER_WIDTH];
end
axi_clock_converter_v2_1_axic_sync_clock_converter #(
.C_FAMILY ( C_FAMILY ) ,
.C_PAYLOAD_WIDTH ( C_B_WIDTH ) ,
.C_M_ACLK_RATIO ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,
.C_S_ACLK_RATIO ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,
.C_MODE(P_LIGHT_WT)
)
b_sync_clock_converter (
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early),
.S_ACLK ( m_axi_aclk ) ,
.S_ARESETN ( m_axi_aresetn ) ,
.S_PAYLOAD ( m_b_mesg ) ,
.S_VALID ( cc_mi_bvalid ) ,
.S_READY ( cc_mi_bready ) ,
.M_ACLK ( s_axi_aclk ) ,
.M_ARESETN ( s_axi_aresetn ) ,
.M_PAYLOAD ( s_b_mesg ) ,
.M_VALID ( si_cc_bvalid ) ,
.M_READY ( si_cc_bready )
);
end else begin : gen_tieoff_write_ch
// Write address port
assign cc_mi_awid = {C_AXI_ID_WIDTH{1'b0}};
assign cc_mi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign cc_mi_awlen = {8{1'b0}};
assign cc_mi_awsize = {3{1'b0}};
assign cc_mi_awburst = {2{1'b0}};
assign cc_mi_awlock = {2{1'b0}};
assign cc_mi_awcache = {4{1'b0}};
assign cc_mi_awprot = {3{1'b0}};
assign cc_mi_awregion = {4{1'b0}};
assign cc_mi_awqos = {4{1'b0}};
assign cc_mi_awuser = {C_AXI_AWUSER_WIDTH{1'b0}};
assign cc_mi_awvalid = 1'b0;
assign si_cc_awready = 1'b0;
// Write data port
assign cc_mi_wid = {C_AXI_ID_WIDTH{1'b0}};
assign cc_mi_wdata = {C_AXI_DATA_WIDTH{1'b0}};
assign cc_mi_wstrb = {C_AXI_DATA_WIDTH/8{1'b0}};
assign cc_mi_wlast = 1'b0;
assign cc_mi_wuser = {C_AXI_WUSER_WIDTH{1'b0}};
assign cc_mi_wvalid = 1'b0;
assign si_cc_wready = 1'b0;
// Write response port
assign si_cc_bid = {C_AXI_ID_WIDTH{1'b0}};
assign si_cc_bresp = {2{1'b0}};
assign si_cc_buser = {C_AXI_BUSER_WIDTH{1'b0}};
assign si_cc_bvalid = 1'b0;
assign cc_mi_bready = 1'b0;
end
////////////////////////////////////////////////////////////////////////////////
// AXI read channels
////////////////////////////////////////////////////////////////////////////////
if (C_AXI_SUPPORTS_READ) begin : gen_conv_read_ch
// Read Address Port
assign s_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH] = si_cc_araddr ;
assign s_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH] = si_cc_arprot ;
assign cc_mi_araddr = m_ar_mesg[C_ARADDR_RIGHT+:C_ARADDR_WIDTH];
assign cc_mi_arprot = m_ar_mesg[C_ARPROT_RIGHT+:C_ARPROT_WIDTH];
if (C_AXI_PROTOCOL == P_AXI4) begin : gen_ar_axi4
assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH] = si_cc_arid ;
assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH] = si_cc_arlen ;
assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH] = si_cc_arsize ;
assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH] = si_cc_arburst ;
assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH] = si_cc_arlock[0] ;
assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH] = si_cc_arcache ;
assign s_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH] = si_cc_arregion ;
assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH] = si_cc_arqos ;
assign cc_mi_arid = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];
assign cc_mi_arlen = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];
assign cc_mi_arsize = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];
assign cc_mi_arburst = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];
assign cc_mi_arlock = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];
assign cc_mi_arcache = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];
assign cc_mi_arregion = m_ar_mesg[C_ARREGION_RIGHT+:C_ARREGION_WIDTH];
assign cc_mi_arqos = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];
end else if (C_AXI_PROTOCOL == P_AXI3) begin : gen_ar_axi3
assign s_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH] = si_cc_arid ;
assign s_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH] = si_cc_arlen[3:0] ;
assign s_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH] = si_cc_arsize ;
assign s_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH] = si_cc_arburst ;
assign s_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH] = si_cc_arlock ;
assign s_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH] = si_cc_arcache ;
assign s_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH] = si_cc_arqos ;
assign cc_mi_arid = m_ar_mesg[C_ARID_RIGHT+:C_ARID_WIDTH];
assign cc_mi_arlen = m_ar_mesg[C_ARLEN_RIGHT+:C_ARLEN_WIDTH];
assign cc_mi_arsize = m_ar_mesg[C_ARSIZE_RIGHT+:C_ARSIZE_WIDTH];
assign cc_mi_arburst = m_ar_mesg[C_ARBURST_RIGHT+:C_ARBURST_WIDTH];
assign cc_mi_arlock = m_ar_mesg[C_ARLOCK_RIGHT+:C_ARLOCK_WIDTH];
assign cc_mi_arcache = m_ar_mesg[C_ARCACHE_RIGHT+:C_ARCACHE_WIDTH];
assign cc_mi_arqos = m_ar_mesg[C_ARQOS_RIGHT+:C_ARQOS_WIDTH];
end
if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_ar_user
assign s_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH] = si_cc_aruser;
assign cc_mi_aruser = m_ar_mesg[C_ARUSER_RIGHT+:C_ARUSER_WIDTH];
end
axi_clock_converter_v2_1_axic_sync_clock_converter #(
.C_FAMILY ( C_FAMILY ) ,
.C_PAYLOAD_WIDTH ( C_AR_WIDTH ) ,
.C_S_ACLK_RATIO ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,
.C_M_ACLK_RATIO ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,
.C_MODE(P_LIGHT_WT)
)
ar_sync_clock_converter (
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early),
.S_ACLK ( s_axi_aclk ) ,
.S_ARESETN ( s_axi_aresetn ) ,
.S_PAYLOAD ( s_ar_mesg ) ,
.S_VALID ( si_cc_arvalid ) ,
.S_READY ( si_cc_arready ) ,
.M_ACLK ( m_axi_aclk ) ,
.M_ARESETN ( m_axi_aresetn ) ,
.M_PAYLOAD ( m_ar_mesg ) ,
.M_VALID ( cc_mi_arvalid ) ,
.M_READY ( cc_mi_arready )
);
// Read Data Port
assign m_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH] = cc_mi_rdata;
assign m_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH] = cc_mi_rresp;
assign si_cc_rdata = s_r_mesg[C_RDATA_RIGHT+:C_RDATA_WIDTH];
assign si_cc_rresp = s_r_mesg[C_RRESP_RIGHT+:C_RRESP_WIDTH];
if (C_AXI_PROTOCOL != P_AXILITE) begin : gen_r_axi
assign m_r_mesg[C_RID_RIGHT+:C_RID_WIDTH] = cc_mi_rid;
assign m_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH] = cc_mi_rlast;
assign si_cc_rid = s_r_mesg[C_RID_RIGHT+:C_RID_WIDTH];
assign si_cc_rlast = s_r_mesg[C_RLAST_RIGHT+:C_RLAST_WIDTH];
end
if (C_AXI_SUPPORTS_USER_SIGNALS && (C_AXI_PROTOCOL != P_AXILITE)) begin : gen_r_user
assign m_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH] = cc_mi_ruser;
assign si_cc_ruser = s_r_mesg[C_RUSER_RIGHT+:C_RUSER_WIDTH];
end
axi_clock_converter_v2_1_axic_sync_clock_converter #(
.C_FAMILY ( C_FAMILY ) ,
.C_PAYLOAD_WIDTH ( C_R_WIDTH ) ,
.C_M_ACLK_RATIO ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,
.C_S_ACLK_RATIO ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,
.C_MODE((C_AXI_PROTOCOL == P_AXILITE) ? P_LIGHT_WT : P_FULLY_REG)
)
r_sync_clock_converter (
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early),
.S_ACLK ( m_axi_aclk ) ,
.S_ARESETN ( m_axi_aresetn ) ,
.S_PAYLOAD ( m_r_mesg ) ,
.S_VALID ( cc_mi_rvalid ) ,
.S_READY ( cc_mi_rready ) ,
.M_ACLK ( s_axi_aclk ) ,
.M_ARESETN ( s_axi_aresetn ) ,
.M_PAYLOAD ( s_r_mesg ) ,
.M_VALID ( si_cc_rvalid ) ,
.M_READY ( si_cc_rready )
);
end else begin : gen_tieoff_read_ch
// Read Address Port
assign cc_mi_arid = {C_AXI_ID_WIDTH{1'b0}};
assign cc_mi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign cc_mi_arlen = {8{1'b0}};
assign cc_mi_arsize = {3{1'b0}};
assign cc_mi_arburst = {2{1'b0}};
assign cc_mi_arlock = {2{1'b0}};
assign cc_mi_arcache = {4{1'b0}};
assign cc_mi_arprot = {3{1'b0}};
assign cc_mi_arregion = {4{1'b0}};
assign cc_mi_arqos = {4{1'b0}};
assign cc_mi_aruser = {C_AXI_ARUSER_WIDTH{1'b0}};
assign cc_mi_arvalid = 1'b0;
assign si_cc_arready = 1'b0;
// Read data port
assign si_cc_rid = {C_AXI_ID_WIDTH{1'b0}};
assign si_cc_rdata = {C_AXI_DATA_WIDTH{1'b0}};
assign si_cc_rresp = {2{1'b0}};
assign si_cc_rlast = 1'b0;
assign si_cc_ruser = {C_AXI_RUSER_WIDTH{1'b0}};
assign si_cc_rvalid = 1'b0;
assign cc_mi_rready = 1'b0;
end
end
end
endgenerate
endmodule
|
`include "macro.v"
module ex(
input wire reset,
input wire[`REGS_DATA_BUS] operand_hi,
input wire[`REGS_DATA_BUS] operand_lo,
input wire wb_write_hilo_enable,
input wire[`REGS_DATA_BUS] wb_write_hi_data,
input wire[`REGS_DATA_BUS] wb_write_lo_data,
input wire mem_write_hilo_enable,
input wire[`REGS_DATA_BUS] mem_write_hi_data,
input wire[`REGS_DATA_BUS] mem_write_lo_data,
input wire[`DOUBLE_REGS_DATA_BUS] ex_div_result,
input wire ex_div_is_ended,
input wire[`ALU_OPERATOR_BUS] operator,
input wire[`ALU_CATEGORY_BUS] category,
input wire[`REGS_DATA_BUS] operand1,
input wire[`REGS_DATA_BUS] operand2,
input wire[`REGS_ADDR_BUS] input_write_addr,
input wire input_write_enable,
input wire[`DOUBLE_REGS_DATA_BUS] last_result,
input wire[`CYCLE_BUS] last_cycle,
input wire[`REGS_DATA_BUS] return_target,
input wire is_curr_in_delayslot,
input wire[`REGS_DATA_BUS] instruction,
output reg[`REGS_DATA_BUS] to_div_operand1,
output reg[`REGS_DATA_BUS] to_div_operand2,
output reg to_div_is_start,
output reg to_div_is_signed,
output reg write_hilo_enable,
output reg[`REGS_DATA_BUS] write_hi_data,
output reg[`REGS_DATA_BUS] write_lo_data,
output reg[`REGS_ADDR_BUS] write_addr,
output reg write_enable,
output reg[`REGS_DATA_BUS] write_data,
output reg[`DOUBLE_REGS_DATA_BUS] current_result,
output reg[`CYCLE_BUS] current_cycle,
output reg stall_signal,
output wire[`ALU_OPERATOR_BUS] broadcast_alu_operator,
output wire[`REGS_DATA_BUS] broadcast_alu_operand2,
output wire[`REGS_DATA_BUS] broadcast_ram_addr
);
assign broadcast_alu_operator = operator;
assign broadcast_alu_operand2 = operand2;
assign broadcast_ram_addr = operand1 + {{16{instruction[15]}}, instruction[15 : 0]};
reg[`REGS_DATA_BUS] logic_result;
reg[`REGS_DATA_BUS] shift_result;
reg[`REGS_DATA_BUS] move_result;
reg[`REGS_DATA_BUS] arithmetic_result;
reg[`DOUBLE_REGS_DATA_BUS] mult_result;
reg[`REGS_DATA_BUS] hi_result_0;
reg[`REGS_DATA_BUS] lo_result_0;
reg[`REGS_DATA_BUS] hi_result_1;
reg[`REGS_DATA_BUS] lo_result_1;
wire is_overflow;
wire[`REGS_DATA_BUS] operand2_mux;
wire[`REGS_DATA_BUS] addition_sum;
wire[`REGS_DATA_BUS] operand1_not;
wire[`REGS_DATA_BUS] opdata1_mult;
wire[`REGS_DATA_BUS] opdata2_mult;
reg stall_signal_from_div;
reg stall_signal_from_mul;
assign operand2_mux = (operator == `OPERATOR_SUB
|| operator == `OPERATOR_SUBU
|| operator == `OPERATOR_SLT) ?
(~operand2) + 1 : operand2;
assign operand1_not = ~operand1;
assign addition_sum = operand1 + operand2_mux;
assign is_overflow = ((!operand1[31] && !operand2_mux[31]) && addition_sum[31])
|| (operand1[31] && operand2_mux[31]) && (!addition_sum[31]);
assign opdata1_mult = ((operator == `OPERATOR_MUL || operator == `OPERATOR_MULT || operator == `OPERATOR_MADD || operator == `OPERATOR_MSUB) && operand1[31]) ? (~operand1 + 1) : operand1;
assign opdata2_mult = ((operator == `OPERATOR_MUL || operator == `OPERATOR_MULT || operator == `OPERATOR_MADD || operator == `OPERATOR_MSUB) && operand2[31]) ? (~operand2 + 1) : operand2;
always @ (*) begin
if (reset == `ENABLE) begin
mult_result <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used here, but 0 is used
end else if (operator == `OPERATOR_MUL || operator == `OPERATOR_MULT
|| operator == `OPERATOR_MADD || operator == `OPERATOR_MSUB) begin
if (operand1[31] ^ operand2[31] == 1'b1) begin // if the answer is negative
mult_result <= ~(opdata1_mult * opdata2_mult) + 1;
end else begin
mult_result <= opdata1_mult * opdata2_mult;
end
end else begin // operator == `OPERATOR_MULTU
mult_result <= operand1 * operand2;
end
end
always @ (*) begin
stall_signal <= stall_signal_from_div || stall_signal_from_mul;
end
always @ (*) begin
if (reset == `ENABLE) begin
to_div_operand1 <= 0; // FIXME: ZERO_WORD should be used here
to_div_operand2 <= 0; // FIXME: ZERO_WORD should be used here
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
end else begin
to_div_operand1 <= 0; // FIXME: ZERO_WORD should be used here
to_div_operand2 <= 0; // FIXME: ZERO_WORD should be used here
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
case (operator)
`OPERATOR_DIV: begin
if (ex_div_is_ended == `FALSE) begin
to_div_operand1 <= operand1;
to_div_operand2 <= operand2;
to_div_is_start <= `TRUE;
to_div_is_signed <= `TRUE;
stall_signal_from_div <= `ENABLE;
end else if (ex_div_is_ended == `TRUE) begin
to_div_operand1 <= operand1;
to_div_operand2 <= operand2;
to_div_is_start <= `FALSE;
to_div_is_signed <= `TRUE;
stall_signal_from_div <= `DISABLE;
end else begin
to_div_operand1 <= 0; // FIXME: ZERO_WORD should be used here
to_div_operand2 <= 0; // FIXME: ZERO_WORD should be used here
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
end
end
`OPERATOR_DIVU: begin
if (ex_div_is_ended == `FALSE) begin
to_div_operand1 <= operand1;
to_div_operand2 <= operand2;
to_div_is_start <= `TRUE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `ENABLE;
end else if (ex_div_is_ended == `TRUE) begin
to_div_operand1 <= operand1;
to_div_operand2 <= operand2;
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
end else begin
to_div_operand1 <= 0; // FIXME: ZERO_WORD should be used here
to_div_operand2 <= 0; // FIXME: ZERO_WORD should be used here
to_div_is_start <= `FALSE;
to_div_is_signed <= `FALSE;
stall_signal_from_div <= `DISABLE;
end
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
current_result <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used here, but 0 is used
current_cycle <= 0; // FIXME: 2'b00 should be used here, but 0 is used
stall_signal_from_mul <= `DISABLE;
end else begin
case (operator)
`OPERATOR_MADD, `OPERATOR_MADDU: begin
if (last_cycle == 0) begin // FIXME: 2'b00 should be used here, but 0 is used
current_result <= mult_result;
current_cycle <= 1; // FIXME: 2'b01 should be used here, but 1 is used
{hi_result_1, lo_result_1} <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used here, but 0 is used
stall_signal_from_mul <= `ENABLE;
end else if (last_cycle == 1) begin // FIXME: 2'b01 should be used here, but 0 is used
current_result <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used here, but 0 is used
current_cycle <= 2; // FIXME: 2'b10 should be used here, but 2 is used
{hi_result_1, lo_result_1} <= last_result + {hi_result_0, lo_result_0};
stall_signal_from_mul <= `DISABLE;
end
end
`OPERATOR_MSUB, `OPERATOR_MSUBU: begin
if (last_cycle == 0) begin // FIXME: 2'b00 should be used here, but 0 is used
current_result <= ~mult_result + 1;
current_cycle <= 1; // FIXME: 2'b01 should be used here, but 1 is used
{hi_result_1, lo_result_1} <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used here, but 0 is used
// TODO: check whether it is valid(added by myself)
stall_signal_from_mul <= `ENABLE;
end else if (last_cycle == 1) begin
current_result <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used here, but 0 is used
current_cycle <= 2; // FIXME: 2'b10 should be used here, but 2 is used
{hi_result_1, lo_result_1} <= last_result + {hi_result_0, lo_result_0};
stall_signal_from_mul <= `DISABLE;
end
end
default: begin
current_result <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used here, but 0 is used
current_cycle <= 0; // FIXME: 2'b00 should be used here, but 0 is used
stall_signal_from_mul <= `DISABLE;
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
arithmetic_result <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used here, but 0 is used
end else begin
case (operator)
`OPERATOR_SLT, `OPERATOR_SLTU: begin
arithmetic_result <=
((operand1[31] && !operand2[31])
|| (!operand1[31] && !operand2[31] && addition_sum[31])
|| (operand1[31] && operand2[31] && addition_sum[31]));
end
`OPERATOR_SLTU: begin
arithmetic_result <= (operand1 < operand2);
end
`OPERATOR_ADD, `OPERATOR_ADDU,
`OPERATOR_SUB, `OPERATOR_SUBU,
`OPERATOR_ADDI, `OPERATOR_ADDIU: begin
arithmetic_result <= addition_sum;
end
`OPERATOR_CLZ: begin
arithmetic_result <=
operand1[31] ? 0 : operand1[30] ? 1 : operand1[29] ? 2 :
operand1[28] ? 3 : operand1[27] ? 4 : operand1[26] ? 5 :
operand1[25] ? 6 : operand1[24] ? 7 : operand1[23] ? 8 :
operand1[22] ? 9 : operand1[21] ? 10 : operand1[20] ? 11 :
operand1[19] ? 12 : operand1[18] ? 13 : operand1[17] ? 14 :
operand1[16] ? 15 : operand1[15] ? 16 : operand1[14] ? 17 :
operand1[13] ? 18 : operand1[12] ? 19 : operand1[11] ? 20 :
operand1[10] ? 21 : operand1[9] ? 22 : operand1[8] ? 23 :
operand1[7] ? 24 : operand1[6] ? 25 : operand1[5] ? 26 :
operand1[4] ? 27 : operand1[3] ? 28 : operand1[2] ? 29 :
operand1[1] ? 30 : operand1[0] ? 31 : 32;
end
`OPERATOR_CLO: begin
arithmetic_result <=
operand1_not[31] ? 0 : operand1_not[30] ? 1 : operand1_not[29] ? 2 :
operand1_not[28] ? 3 : operand1_not[27] ? 4 : operand1_not[26] ? 5 :
operand1_not[25] ? 6 : operand1_not[24] ? 7 : operand1_not[23] ? 8 :
operand1_not[22] ? 9 : operand1_not[21] ? 10 : operand1_not[20] ? 11 :
operand1_not[19] ? 12 : operand1_not[18] ? 13 : operand1_not[17] ? 14 :
operand1_not[16] ? 15 : operand1_not[15] ? 16 : operand1_not[14] ? 17 :
operand1_not[13] ? 18 : operand1_not[12] ? 19 : operand1_not[11] ? 20 :
operand1_not[10] ? 21 : operand1_not[9] ? 22 : operand1_not[8] ? 23 :
operand1_not[7] ? 24 : operand1_not[6] ? 25 : operand1_not[5] ? 26 :
operand1_not[4] ? 27 : operand1_not[3] ? 28 : operand1_not[2] ? 29 :
operand1_not[1] ? 30 : operand1_not[0] ? 31 : 32;
end
default: begin
arithmetic_result <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used here, but 0 is used
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
{hi_result_0, lo_result_0} <= 0; // FIXME: {`ZERO_WORD, `ZERO_WORD} should be used here, but 0 is used
end else if (mem_write_hilo_enable == `ENABLE) begin
{hi_result_0, lo_result_0} <= {mem_write_hi_data, mem_write_lo_data};
end else if (wb_write_hilo_enable == `ENABLE) begin
{hi_result_0, lo_result_0} <= {wb_write_hi_data, wb_write_lo_data};
end else begin
{hi_result_0, lo_result_0} <= {operand_hi, operand_lo};
end
end
always @ (*) begin
if (reset == `ENABLE) begin
move_result <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
end else begin
move_result <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
case (operator)
`INST_MFHI_OPERATOR: begin
move_result <= hi_result_0;
end
`INST_MFLO_OPERATOR: begin
move_result <= lo_result_0;
end
`INST_MOVZ_OPERATOR: begin
move_result <= operand1;
end
`INST_MOVN_OPERATOR: begin
move_result <= operand1;
end
default: begin
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
logic_result <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
end else begin
case (operator)
`OPERATOR_OR: begin
logic_result <= operand1 | operand2;
end
`OPERATOR_AND: begin
logic_result <= operand1 & operand2;
end
`OPERATOR_NOR: begin
logic_result <= ~(operand1 | operand2);
end
`OPERATOR_XOR: begin
logic_result <= operand1 ^ operand2;
end
default: begin
logic_result <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
end
endcase
end
end
always @ (*) begin
if (reset == `ENABLE) begin
shift_result <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
end else begin
case (operator)
`OPERATOR_SLL: begin
shift_result <= operand2 << operand1[4 : 0];
end
`OPERATOR_SRL: begin
shift_result <= operand2 >> operand1[4 : 0];
end
`OPERATOR_SRA: begin
shift_result <= ({32{operand2[31]}} << (6'd32 - {1'b0, operand1[4 : 0]}))
| operand2 >> operand1[4 : 0];
end
default: begin
shift_result <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
end
endcase
end
end
always @ (*) begin
write_addr <= input_write_addr;
if ((operator == `OPERATOR_ADD || operator == `OPERATOR_ADDI
|| operator ==`OPERATOR_SUB) && is_overflow == 1'b1) begin
write_enable <= `DISABLE;
end else begin
write_enable <= input_write_enable;
end
case (category)
`CATEGORY_LOGIC: begin
write_data <= logic_result;
end
`CATEGORY_SHIFT: begin
write_data <= shift_result;
end
`CATEGORY_MOVE: begin
write_data <= move_result;
end
`CATEGORY_ARITHMETIC: begin
write_data <= arithmetic_result;
end
`CATEGORY_MULTIPLY: begin
write_data <= mult_result;
end
`CATEGORY_FORK: begin
write_data <= return_target;
end
default: begin
write_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
end
endcase
end
always @ (*) begin
if (reset == `ENABLE) begin
write_hilo_enable <= `DISABLE;
write_hi_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
write_lo_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
end else if (operator == `OPERATOR_DIV || operator == `OPERATOR_DIVU) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= ex_div_result[63 : 32];
write_lo_data <= ex_div_result[31 : 0];
end else if (operator == `OPERATOR_MSUB || operator == `OPERATOR_MSUBU
|| operator == `OPERATOR_MADD || operator == `OPERATOR_MADDU) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= hi_result_1;
write_lo_data <= lo_result_1;
end else if (operator == `OPERATOR_MULT || operator == `OPERATOR_MULTU) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= mult_result[63 : 32];
write_lo_data <= mult_result[31 : 0];
end else if (operator == `OPERATOR_MTHI) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= operand1;
write_lo_data <= lo_result_0;
end else if (operator == `OPERATOR_MTLO) begin
write_hilo_enable <= `ENABLE;
write_hi_data <= hi_result_0;
write_lo_data <= operand1;
end else begin
write_hilo_enable <= `DISABLE;
write_hi_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
write_lo_data <= 0; // FIXME: ZERO_WORD should be used here, but 0 is used
end
end
endmodule // ex
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
/*verilator public_module*/
input clk;
// No verilator_public needed, because it's outside the "" in the $c statement
reg [7:0] cyc; initial cyc=0;
reg c_worked;
reg [8:0] c_wider;
wire one = 1'b1;
always @ (posedge clk) begin
cyc <= cyc+8'd1;
// coverage testing
if (one) begin end
if (!one) begin end
if (cyc[0]) begin end if (!cyc[0]) begin end // multiple on a line
if (cyc == 8'd1) begin
c_worked <= 0;
end
if (cyc == 8'd2) begin
`ifdef VERILATOR
$c("VL_PRINTF(\"Calling $c, calling $c...\\n\");");
$c("VL_PRINTF(\"Cyc=%d\\n\",",cyc,");");
c_worked <= $c("my_function()");
c_wider <= $c9("0x10");
`else
c_worked <= 1'b1;
c_wider <= 9'h10;
`endif
end
if (cyc == 8'd3) begin
if (c_worked !== 1'b1) $stop;
if (c_wider !== 9'h10) $stop;
$finish;
end
end
`ifdef verilator
`systemc_header
#define DID_INT_HEADER 1
`systemc_interface
#ifndef DID_INT_HEADER
#error "`systemc_header didn't work"
#endif
bool m_did_ctor;
vluint32_t my_function() {
if (!m_did_ctor) vl_fatal(__FILE__,__LINE__,__FILE__,"`systemc_ctor didn't work");
return 1;
}
`systemc_imp_header
#define DID_IMP_HEADER 1
`systemc_implementation
#ifndef DID_IMP_HEADER
#error "`systemc_imp_header didn't work"
#endif
`systemc_ctor
m_did_ctor = 1;
`systemc_dtor
printf("In systemc_dtor\n");
printf("*-* All Finished *-*\n");
`verilog
// Test verilator comment after a endif
`endif // verilator
endmodule
|
module LCDDisplay(clk_i, func_i, data_i, en_o, func_o, data_o);
input clk_i;
input [2:0] func_i;
input [127:0] data_i; // array of 16 chars
reg [7:0] data_c [0:31];
// consult LCD's datasheet about the output format
output reg en_o;
output [1:0] func_o;
output [7:0] data_o;
reg [1:0] func_o_0;
reg [1:0] func_o_1;
assign func_o = func_o_0 | func_o_1;
reg [7:0] data_o_0;
reg [7:0] data_o_1;
assign data_o = data_o_0 | data_o_1;
`define IDLE 1'b0
`define BUSY 1'b1
`define SPACE 8'b00100000
integer i;
reg state;
reg [1:0] lcd_clr_state;
integer lcd_clr_cyc;
reg [2:0] lcd_wrt_state;
integer lcd_wrt_cyc;
reg [6:0] ddram_addr;
integer cursor_pos;
initial begin
state = `BUSY;
for (i = 0; i < 31; i = i + 1) begin
data_c[i] = `SPACE;
end
en_o = 0;
func_o_0 = 2'b00;
func_o_1 = 2'b00;
data_o_0 = 8'b0;
data_o_1 = 8'b0;
lcd_clr_state = 2'b00;
lcd_wrt_state = 3'b000;
state = `IDLE;
end
`define NOP 3'b000
`define K0 3'b100
`define K1 3'b101
`define K2 3'b110
`define K3 3'b111
`define EN_PULSE_WIDTH 20
always@(negedge clk_i) begin
if (state == `IDLE) begin
case (func_i)
`K0: begin
for (i = 0; i < 31; i = i + 1) begin
data_c[i] <= `SPACE;
end
lcd_clr_state <= 2'b01;
state <= `BUSY;
end
`K2: begin
for (i = 0; i < 16; i = i + 1) begin
data_c[i + 16] <= data_c[i];
end
data_c[0] <= data_i[7:0];
data_c[1] <= data_i[15:8];
data_c[2] <= data_i[23:16];
data_c[3] <= data_i[31:24];
data_c[4] <= data_i[39:32];
data_c[5] <= data_i[47:40];
data_c[6] <= data_i[55:48];
data_c[7] <= data_i[63:56];
data_c[8] <= data_i[71:64];
data_c[9] <= data_i[79:72];
data_c[10] <= data_i[87:80];
data_c[11] <= data_i[95:88];
data_c[12] <= data_i[103:96];
data_c[13] <= data_i[111:104];
data_c[14] <= data_i[119:112];
data_c[15] <= data_i[127:120];
cursor_pos <= 0;
ddram_addr <= 7'b0000000;
lcd_wrt_state <= 3'b001;
state <= `BUSY;
end
endcase
end else begin
// BUSY state
case (lcd_clr_state)
2'b00: begin
// DO NOTHING
end
2'b01: begin
en_o <= 1;
func_o_0 <= 2'b00;
data_o_0 <= 8'b00000001;
lcd_clr_state <= 2'b10;
lcd_clr_cyc <= 0;
end
2'b10: begin
if (lcd_clr_cyc != 8000) begin
if (lcd_clr_cyc == `EN_PULSE_WIDTH) begin
en_o <= 0;
end
lcd_clr_cyc <= lcd_clr_cyc + 1;
end else begin
data_o_0 <= 8'b0;
func_o_0 <= 2'b00;
lcd_clr_state <= 2'b00;
state <= `IDLE;
end
end
endcase
case (lcd_wrt_state)
3'b000: begin
// DO NOTHING
end
3'b001: begin
if (ddram_addr == 7'h50) begin
data_o_1 <= 8'b0;
func_o_1 <= 2'b00;
lcd_wrt_state <= 3'b000;
state <= `IDLE;
end else begin
en_o <= 1;
func_o_1 <= 2'b00;
data_o_1 <= {1'b1, ddram_addr};
if (ddram_addr == 7'h0F) begin
ddram_addr <= 7'h40;
end else begin
ddram_addr <= ddram_addr + 7'b1;
end
lcd_wrt_state <= 3'b010;
lcd_wrt_cyc <= 0;
end
end
3'b010: begin
if (lcd_wrt_cyc != 250) begin
if (lcd_wrt_cyc == `EN_PULSE_WIDTH) begin
en_o <= 0;
end
lcd_wrt_cyc <= lcd_wrt_cyc + 1;
end else begin
lcd_wrt_state <= 3'b011;
end
end
3'b011: begin
en_o <= 1;
func_o_1 <= 2'b10;
data_o_1 <= data_c[cursor_pos];
cursor_pos <= cursor_pos + 1;
lcd_wrt_state <= 3'b100;
lcd_wrt_cyc <= 0;
end
3'b100: begin
if (lcd_wrt_cyc != 250) begin
if (lcd_wrt_cyc == `EN_PULSE_WIDTH) begin
en_o <= 0;
end
lcd_wrt_cyc <= lcd_wrt_cyc + 1;
end else begin
lcd_wrt_state <= 3'b001;
end
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:28:12 05/24/2015
// Design Name: binary_to_BCD_eight_bit
// Module Name: D:/Digilent/Data/Xilinx/Projects/ISE_12_4/Binary_to_BCD_Eight_Bit/binary_to_BCD_eight_bit_tb.v
// Project Name: Binary_to_BCD_Eight_Bit
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: binary_to_BCD_eight_bit
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module binary_to_BCD_eight_bit_tb;
// Inputs
reg [7:0] in;
// Outputs
wire [3:0] ones;
wire [3:0] tens;
wire [1:0] hundreds;
// Instantiate the Unit Under Test (UUT)
binary_to_BCD_eight_bit uut (
.in(in),
.ones(ones),
.tens(tens),
.hundreds(hundreds)
);
initial begin
// Initialize Inputs
in = 0;
for (in =0;in< 256;in = in +1) begin
#10
$display(" in = %d hundreds = %d tens = %d ones = %d",in, hundreds, tens, ones);
end
// Add stimulus here
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [9:0] in = crc[9:0];
/*AUTOWIRE*/
Test test (/*AUTOINST*/
// Inputs
.clk (clk),
.in (in[9:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {64'h0};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Inputs
clk, in
);
input clk;
input [9:0] in;
reg a [9:0];
integer ai;
always @* begin
for (ai=0;ai<10;ai=ai+1) begin
a[ai]=in[ai];
end
end
reg [1:0] b [9:0];
integer j;
generate
genvar i;
for (i=0; i<2; i=i+1) begin
always @(posedge clk) begin
for (j=0; j<10; j=j+1) begin
if (a[j])
b[i][j] <= 1'b0;
else
b[i][j] <= 1'b1;
end
end
end
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_fifo.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2002/04/22 13:45:52 mohor
// Generic ram or Xilinx ram can be used in fifo (selectable by setting
// XILINX_SPARTAN6_FPGA in eth_defines.v).
//
// Revision 1.2 2002/03/25 13:33:04 mohor
// When clear and read/write are active at the same time, cnt and pointers are
// set to 1.
//
// Revision 1.1 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
//
`include "eth_defines.v"
`include "timescale.v"
module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
parameter DATA_WIDTH = 32;
parameter DEPTH = 8;
parameter CNT_WIDTH = 4;
parameter Tp = 1;
input clk;
input reset;
input write;
input read;
input clear;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
output almost_full;
output full;
output almost_empty;
output empty;
output [CNT_WIDTH-1:0] cnt;
`ifndef XILINX_SPARTAN6_FPGA
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
reg [DATA_WIDTH-1:0] data_out;
`endif
reg [CNT_WIDTH-1:0] cnt;
reg [CNT_WIDTH-2:0] read_pointer;
reg [CNT_WIDTH-2:0] write_pointer;
always @ (posedge clk or posedge reset)
begin
if(reset)
cnt <=#Tp 0;
else
if(clear)
cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write};
else
if(read ^ write)
if(read)
cnt <=#Tp cnt - 1'b1;
else
cnt <=#Tp cnt + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
read_pointer <=#Tp 0;
else
if(clear)
read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read};
else
if(read & ~empty)
read_pointer <=#Tp read_pointer + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
write_pointer <=#Tp 0;
else
if(clear)
write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write};
else
if(write & ~full)
write_pointer <=#Tp write_pointer + 1'b1;
end
assign empty = ~(|cnt);
assign almost_empty = cnt == 1;
assign full = cnt == DEPTH;
assign almost_full = &cnt[CNT_WIDTH-2:0];
`ifdef XILINX_SPARTAN6_FPGA
xilinx_dist_ram_16x32 fifo
( .data_out(data_out),
.we(write & ~full),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.wclk(clk)
);
`else
always @ (posedge clk)
begin
if(write & clear)
fifo[0] <=#Tp data_in;
else
if(write & ~full)
fifo[write_pointer] <=#Tp data_in;
end
always @ (posedge clk)
begin
if(clear)
data_out <=#Tp fifo[0];
else
data_out <=#Tp fifo[read_pointer];
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O31A_BLACKBOX_V
`define SKY130_FD_SC_LS__O31A_BLACKBOX_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o31a (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O31A_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A2BB2O_BLACKBOX_V
`define SKY130_FD_SC_LS__A2BB2O_BLACKBOX_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A2BB2O_BLACKBOX_V
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Low latency FIFO
// One cycle latency from all inputs to all outputs
// Storage implemented in registers, not memory.
module acl_iface_ll_fifo(clk, reset, data_in, write, data_out, read, empty, full);
/* Parameters */
parameter WIDTH = 32;
parameter DEPTH = 32;
/* Ports */
input clk;
input reset;
input [WIDTH-1:0] data_in;
input write;
output [WIDTH-1:0] data_out;
input read;
output empty;
output full;
/* Architecture */
// One-hot write-pointer bit (indicates next position to write at),
// last bit indicates the FIFO is full
reg [DEPTH:0] wptr;
// Replicated copy of the stall / valid logic
reg [DEPTH:0] wptr_copy /* synthesis dont_merge */;
// FIFO data registers
reg [DEPTH-1:0][WIDTH-1:0] data;
// Write pointer updates:
wire wptr_hold; // Hold the value
wire wptr_dir; // Direction to shift
// Data register updates:
wire [DEPTH-1:0] data_hold; // Hold the value
wire [DEPTH-1:0] data_new; // Write the new data value in
// Write location is constant unless the occupancy changes
assign wptr_hold = !(read ^ write);
assign wptr_dir = read;
// Hold the value unless we are reading, or writing to this
// location
genvar i;
generate
for(i = 0; i < DEPTH; i++)
begin : data_mux
assign data_hold[i] = !(read | (write & wptr[i]));
assign data_new[i] = !read | wptr[i+1];
end
endgenerate
// The data registers
generate
for(i = 0; i < DEPTH-1; i++)
begin : data_reg
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data[i] <= {WIDTH{1'b0}};
else
data[i] <= data_hold[i] ? data[i] :
data_new[i] ? data_in : data[i+1];
end
end
endgenerate
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data[DEPTH-1] <= {WIDTH{1'b0}};
else
data[DEPTH-1] <= data_hold[DEPTH-1] ? data[DEPTH-1] : data_in;
end
// The write pointer
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
wptr <= {{DEPTH{1'b0}}, 1'b1};
wptr_copy <= {{DEPTH{1'b0}}, 1'b1};
end
else
begin
wptr <= wptr_hold ? wptr :
wptr_dir ? {1'b0, wptr[DEPTH:1]} : {wptr[DEPTH-1:0], 1'b0};
wptr_copy <= wptr_hold ? wptr_copy :
wptr_dir ? {1'b0, wptr_copy[DEPTH:1]} : {wptr_copy[DEPTH-1:0], 1'b0};
end
end
// Outputs
assign empty = wptr_copy[0];
assign full = wptr_copy[DEPTH];
assign data_out = data[0];
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version:%version
// \ \ Application: MIG
// / / Filename: clk_ibuf.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created:Mon Aug 3 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ns/1ps
module mig_7series_v1_9_clk_ibuf #
(
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
parameter DIFF_TERM_SYSCLK = "TRUE"
// Differential Termination
)
(
// Clock inputs
input sys_clk_p, // System clock diff input
input sys_clk_n,
input sys_clk_i,
output mmcm_clk
);
(* KEEP = "TRUE" *) wire sys_clk_ibufg /* synthesis syn_keep = 1 */;
generate
if (SYSCLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_SYSCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_sys_clk
(
.I (sys_clk_i),
.O (sys_clk_ibufg)
);
end else if (SYSCLK_TYPE == "NO_BUFFER") begin: internal_clk
//***********************************************************************
// System clock is driven from FPGA internal clock (clock from fabric)
//***********************************************************************
assign sys_clk_ibufg = sys_clk_i;
end
endgenerate
assign mmcm_clk = sys_clk_ibufg;
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_generic_ddio(
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
input [WIDTH-1:0] clk_fr;
output [DATA_OUT_WIDTH-1:0] dataout;
generate
genvar pin;
for (pin = 0; pin < WIDTH; pin = pin + 1)
begin:acblock
wire fr_data_hi;
wire fr_data_lo;
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_hi (
.datainhi(datain[pin * 4]),
.datainlo(datain[pin * 4 + 2]),
.dataout(fr_data_hi),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_lo (
.datainhi(datain[pin * 4 + 1]),
.datainlo(datain[pin * 4 + 3]),
.dataout(fr_data_lo),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.async_mode("none"),
.half_rate_mode("false"),
.sync_mode("none"),
.use_new_clocking_model("true")
) ddio_out (
.datainhi(fr_data_hi),
.datainlo(fr_data_lo),
.dataout(dataout[pin]),
.clkhi (clk_fr[pin]),
.clklo (clk_fr[pin]),
.muxsel (clk_fr[pin])
);
end
endgenerate
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_mult32u (
enable,
clock,
dataa,
datab,
result);
parameter INPUT1_WIDTH = 32;
parameter INPUT2_WIDTH = 32;
input enable;
input clock;
input [INPUT1_WIDTH - 1 : 0] dataa;
input [INPUT2_WIDTH - 1 : 0] datab;
output reg[31:0] result;
wire [INPUT1_WIDTH + INPUT2_WIDTH - 1 : 0] sub_wire0;
lpm_mult lpm_mult_component (
.clock (clock),
.datab (datab),
.clken (enable),
.dataa (dataa),
.result (sub_wire0),
.aclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=9",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = INPUT1_WIDTH,
lpm_mult_component.lpm_widthb = INPUT2_WIDTH,
lpm_mult_component.lpm_widthp = INPUT1_WIDTH + INPUT2_WIDTH;
always@(posedge clock)
begin
if (enable)
result <= {0, sub_wire0[INPUT1_WIDTH + INPUT2_WIDTH - 1 : 0]};
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ddr3_int_phy_alt_mem_phy_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddr3_int_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
c5,
locked,
phasedone);
input areset;
input inclk0;
input [3:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [3:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [6:0] sub_wire0;
wire sub_wire5;
wire sub_wire8;
wire [0:0] sub_wire11 = 1'h0;
wire [4:4] sub_wire7 = sub_wire0[4:4];
wire [0:0] sub_wire6 = sub_wire0[0:0];
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [5:5] sub_wire2 = sub_wire0[5:5];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c5 = sub_wire2;
wire c2 = sub_wire3;
wire c3 = sub_wire4;
wire locked = sub_wire5;
wire c0 = sub_wire6;
wire c4 = sub_wire7;
wire phasedone = sub_wire8;
wire sub_wire9 = inclk0;
wire [1:0] sub_wire10 = {sub_wire11, sub_wire9};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire10),
.phasecounterselect (phasecounterselect),
.phasestep (phasestep),
.scanclk (scanclk),
.phaseupdown (phaseupdown),
.clk (sub_wire0),
.locked (sub_wire5),
.phasedone (sub_wire8),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 6,
altpll_component.clk0_phase_shift = "556",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 12,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 1,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 12,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 1,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 12,
altpll_component.clk3_phase_shift = "-833",
altpll_component.clk4_divide_by = 1,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 12,
altpll_component.clk4_phase_shift = "0",
altpll_component.clk5_divide_by = 1,
altpll_component.clk5_duty_cycle = 50,
altpll_component.clk5_multiply_by = 12,
altpll_component.clk5_phase_shift = "0",
altpll_component.inclk0_input_frequency = 40000,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_USED",
altpll_component.port_phasedone = "PORT_USED",
altpll_component.port_phasestep = "PORT_USED",
altpll_component.port_phaseupdown = "PORT_USED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_USED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.vco_frequency_control = "MANUAL_PHASE",
altpll_component.vco_phase_shift_step = 104,
altpll_component.width_clock = 7;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "150.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "300.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "300.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "104.00000000"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "150.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "300.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "30.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll_siii.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK5 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLK5 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "556"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-833"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "12"
// Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
// Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "104"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: phasecounterselect 0 0 4 0 INPUT GND "phasecounterselect[3..0]"
// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @phasecounterselect 0 0 4 0 phasecounterselect 0 0 4 0
// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_int_phy_alt_mem_phy_pll_bb.v TRUE
|
module FSM (
input Reset_n_i,
input Clk_i,
input In0_i,
input In1_i,
input In2_i,
input In3_i,
input In4_i,
input In5_i,
input In6_i,
input In7_i,
output Out0_o,
output Out1_o,
output Out2_o,
output Out3_o,
output Out4_o,
output Out5_o,
output Out6_o,
output Out7_o,
output Out8_o,
output Out9_o,
output Out10_o,
output Out11_o,
output Out12_o,
output Out13_o,
output Out14_o,
input CfgMode_i,
input CfgClk_i,
input CfgShift_i,
input CfgDataIn_i,
output CfgDataOut_o
);
wire [7:0] Input_s;
wire [14:0] Output_s;
wire ScanEnable_s;
wire ScanClk_s;
wire ScanDataIn_s;
wire ScanDataOut_s;
TRFSM #(
.InputWidth(8),
.OutputWidth(15),
.StateWidth(5),
.UseResetRow(0),
.NumRows0(5),
.NumRows1(10),
.NumRows2(10),
.NumRows3(5),
.NumRows4(5),
.NumRows5(0),
.NumRows6(0),
.NumRows7(0),
.NumRows8(0),
.NumRows9(0)
) TRFSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.Input_i(Input_s),
.Output_o(Output_s),
.CfgMode_i(CfgMode_i),
.CfgClk_i(CfgClk_i),
.CfgShift_i(CfgShift_i),
.CfgDataIn_i(CfgDataIn_i),
.CfgDataOut_o(CfgDataOut_o),
.ScanEnable_i(ScanEnable_s),
.ScanClk_i(ScanClk_s),
.ScanDataIn_i(ScanDataIn_s),
.ScanDataOut_o(ScanDataOut_s)
);
assign Input_s = { In7_i, In6_i, In5_i, In4_i, In3_i, In2_i, In1_i, In0_i };
assign Out0_o = Output_s[0];
assign Out1_o = Output_s[1];
assign Out2_o = Output_s[2];
assign Out3_o = Output_s[3];
assign Out4_o = Output_s[4];
assign Out5_o = Output_s[5];
assign Out6_o = Output_s[6];
assign Out7_o = Output_s[7];
assign Out8_o = Output_s[8];
assign Out9_o = Output_s[9];
assign Out10_o = Output_s[10];
assign Out11_o = Output_s[11];
assign Out12_o = Output_s[12];
assign Out13_o = Output_s[13];
assign Out14_o = Output_s[14];
assign ScanEnable_s = 1'b0;
assign ScanClk_s = 1'b0;
assign ScanDataIn_s = 1'b0;
endmodule
|
module var24_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, V, W, X;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29
+ T * 9'd23
+ U * 9'd24
+ V * 9'd3
+ W * 9'd18
+ X * 9'd5;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1
+ T * 9'd22
+ U * 9'd26
+ V * 9'd15
+ W * 9'd0
+ X * 9'd21;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28
+ T * 9'd13
+ U * 9'd18
+ V * 9'd16
+ W * 9'd26
+ X * 9'd3;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_ic_mem_router_reorder #(
parameter integer DATA_W = 256, // > 0
parameter integer BURSTCOUNT_W = 1, // > 0
parameter integer ADDRESS_W = 32, // > 0 (word address)
parameter integer BYTEENA_W = DATA_W / 8, // > 0
parameter integer NUM_BANKS = 8, // > 1
parameter integer BANK_SEL_BIT = ADDRESS_W-$clog2(NUM_BANKS), // ADDRESS_W-$clog2(NUM_BANKS) > x >= BURSTCOUNT_W
parameter integer BANK_MAX_PENDING_READS = 2*2**BURSTCOUNT_W-4, // > 0
parameter integer BANK_MAX_PENDING_WRITES = 2047, // > 0
// Can override actual FIFO Depths here
// +3 : bank data FIFO latency
// +1 : do not stall when pipeline is full
parameter READ_DATA_FIFO_DEPTH = BANK_MAX_PENDING_READS + 3 + 1,
// +1 : do not stall when pipeline is full
parameter WRITE_ACK_FIFO_DEPTH = BANK_MAX_PENDING_WRITES * NUM_BANKS + 1
)
(
input logic clock,
input logic resetn,
// Bank select (one-hot)
input logic [NUM_BANKS-1:0] bank_select,
// Master
input logic m_arb_request,
input logic m_arb_read,
input logic m_arb_write,
input logic [DATA_W-1:0] m_arb_writedata,
input logic [BURSTCOUNT_W-1:0] m_arb_burstcount,
input logic [ADDRESS_W-1:0] m_arb_address,
input logic [BYTEENA_W-1:0] m_arb_byteenable,
output logic m_arb_stall,
output logic m_wrp_ack,
output logic m_rrp_datavalid,
output logic [DATA_W-1:0] m_rrp_data,
// To each bank
output logic b_arb_request [NUM_BANKS],
output logic b_arb_read [NUM_BANKS],
output logic b_arb_write [NUM_BANKS],
output logic [DATA_W-1:0] b_arb_writedata [NUM_BANKS],
output logic [BURSTCOUNT_W-1:0] b_arb_burstcount [NUM_BANKS],
output logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] b_arb_address [NUM_BANKS],
output logic [BYTEENA_W-1:0] b_arb_byteenable [NUM_BANKS],
input logic b_arb_stall [NUM_BANKS],
input logic b_wrp_ack [NUM_BANKS], // MUST BE USED OR WILL HANG! Set to 1
input logic b_rrp_datavalid [NUM_BANKS],
input logic [DATA_W-1:0] b_rrp_data [NUM_BANKS]
);
// READ_BANK_SELECT_FIFO_DEPTH = max( NUM_BANKS, READ_DATA_FIFO_DEPTH );
localparam READ_BANK_SELECT_FIFO_DEPTH = NUM_BANKS > READ_DATA_FIFO_DEPTH ? NUM_BANKS : READ_DATA_FIFO_DEPTH;
genvar i;
logic [NUM_BANKS-1:0] m_arb_bank_sel;
logic [ADDRESS_W-$clog2(NUM_BANKS)-1:0] m_arb_bank_address;
// Split address into bank_sel and bank_address (within a bank)
acl_address_to_bankaddress #(
.ADDRESS_W( ADDRESS_W ),
.NUM_BANKS( NUM_BANKS ),
.BANK_SEL_BIT( BANK_SEL_BIT))
a2b (
.address(m_arb_address),
.bank_sel(m_arb_bank_sel),
.bank_address(m_arb_bank_address));
// Request. We stall request and read/write since we never need to lock
// the bus. This is because we only accept writes when we guarantee we
// have space for it all. And reads are one cycle transactions that
// never need locking.
generate
begin:req
integer req_b;
logic stall;
always_comb
begin
stall = 1'b0;
for( req_b = 0; req_b < NUM_BANKS; req_b = req_b + 1 )
begin:bank
b_arb_request[req_b] = m_arb_request & m_arb_bank_sel[req_b] & ~(rrp.stall | wrp.stall);
b_arb_read[req_b] = m_arb_read & m_arb_bank_sel[req_b] & ~(rrp.stall | wrp.stall);
b_arb_write[req_b] = m_arb_write & m_arb_bank_sel[req_b] & ~(rrp.stall | wrp.stall);
b_arb_writedata[req_b] = m_arb_writedata;
b_arb_burstcount[req_b] = m_arb_burstcount;
b_arb_address[req_b] = m_arb_bank_address;
b_arb_byteenable[req_b] = m_arb_byteenable;
stall |= b_arb_stall[req_b] & m_arb_bank_sel[req_b];
end
end
end
endgenerate
// Read return path. Need to handle the two problems:
// 1) Data is returned in a different bank order than the order in which
// the banks were issued.
// 2) Multiple data words arrive in the same cycle (from different banks).
generate
begin:rrp
integer rrp_b;
logic stall;
logic [NUM_BANKS-1:0] bs_in, bs_out, bank_df_valid, bank_df_no_free;
logic [BURSTCOUNT_W-1:0] bs_burstcount, bs_burstcounter;
logic bs_read, bs_write, bs_full, bs_empty, bs_valid;
logic bs_doneburst /* synthesis keep = 1 */;
logic [DATA_W-1:0] bank_df_out [NUM_BANKS];
// Bank select FIFO. Tracks which bank the next valid read data
// should come from. Data is assumed to be one-hot encoded.
acl_ll_fifo #(
.DEPTH(READ_BANK_SELECT_FIFO_DEPTH),
.WIDTH(BURSTCOUNT_W+NUM_BANKS)
)
bs_fifo (
.clk( clock ),
.reset( ~resetn ),
.data_in( {m_arb_burstcount,bs_in} ),
.write( bs_write ),
.data_out( {bs_burstcount,bs_out} ),
.read( bs_doneburst && bs_read ),
.empty( bs_empty ),
.full( bs_full )
);
assign bs_doneburst = (bs_burstcounter == bs_burstcount);
always @( posedge clock or negedge resetn )
if (!resetn)
bs_burstcounter <= 'b01;
else if (bs_doneburst && bs_read)
bs_burstcounter <= 'b01;
else if (bs_read)
bs_burstcounter <= bs_burstcounter + 'b01;
// Bank select FIFO assignments.
assign bs_in = m_arb_bank_sel;
assign bs_write = m_arb_read & ~(req.stall | stall);
assign bs_read = bs_valid & |(bs_out & bank_df_valid);
assign bs_valid = ~bs_empty;
// Per-bank logic.
for( i = 0; i < NUM_BANKS; i = i + 1 )
begin:bank
// Data FIFO.
logic [DATA_W-1:0] df_in, df_out;
logic df_read, df_write, df_full, df_empty;
scfifo #(
.lpm_width( DATA_W ),
.lpm_widthu( $clog2(READ_DATA_FIFO_DEPTH) ),
.lpm_numwords( READ_DATA_FIFO_DEPTH ),
.add_ram_output_register( "ON" ),
.lpm_showahead( "ON" ),
.intended_device_family( "stratixiv" )
)
data_fifo (
.aclr( ~resetn ),
.clock( clock ),
.empty( df_empty ),
.full( df_full ),
.data( df_in ),
.q( df_out ),
.wrreq( df_write ),
.rdreq( df_read ),
.sclr(),
.usedw(),
.almost_full(),
.almost_empty()
);
// Number of free entries in the data FIFO minus one.
// This means that the data FIFO will be full if df_free == -1.
// This allows for a single-bit to indicate no more free entries.
//
// The range of values that need to be stored in this counter is
// [-1, READ_DATA_FIFO_DEPTH - 1]. Initial value is
// READ_DATA_FIFO_DEPTH - 1.
logic [$clog2(READ_DATA_FIFO_DEPTH):0] df_free;
logic incr_df_free, decr_df_free;
// Data FIFO assignments.
assign df_in = b_rrp_data[i];
assign df_write = b_rrp_datavalid[i];
assign df_read = bs_valid & bs_out[i] & bank_df_valid[i];
assign bank_df_valid[i] = ~df_empty;
assign bank_df_out[i] = df_out;
// Logic to track number of free entries in the data FIFO.
always @( posedge clock or negedge resetn )
if( !resetn )
df_free <= READ_DATA_FIFO_DEPTH - 1;
else
df_free <= df_free + incr_df_free - ((decr_df_free) ? m_arb_burstcount : 1'b0);
assign incr_df_free = df_read;
assign decr_df_free = m_arb_read & bs_in[i] & ~(req.stall | bs_full | bank_df_no_free[i]);
// If MSB is high, then df_free == -1 and that means all data FIFO
// entries are in use.
assign bank_df_no_free[i] = df_free < (2**(BURSTCOUNT_W-1));
//assign bank_df_no_free[i] = df_free[$bits(df_free) - 1];
end
// Stall the current read request if the bank select FIFO is full or
// if the bank data FIFO has no free entries.
assign stall = m_arb_read & (bs_full | |(bs_in & bank_df_no_free));
// RRP output signals.
logic [DATA_W-1:0] rrp_data;
always_comb
begin
rrp_data = '0;
for( rrp_b = 0; rrp_b < NUM_BANKS; rrp_b = rrp_b + 1 )
rrp_data |= bs_out[rrp_b] ? bank_df_out[rrp_b] : '0;
end
always @( posedge clock or negedge resetn )
if( !resetn )
m_rrp_datavalid <= 1'b0;
else
m_rrp_datavalid <= bs_read;
always @( posedge clock )
m_rrp_data <= rrp_data;
end
endgenerate
// Write return path. Need to handle two problems:
// 1) Multiple write acks arrive in the same cycle (from different banks).
// 2) Order of writeacks must be restored
// Solution: Use bank select fifo to select between two wrack counters
generate
begin:wrp
logic stall;
logic [NUM_BANKS-1:0] has_acks;
logic bs_no_burst_free /* synthesis keep = 1 */;
logic [NUM_BANKS-1:0] bs_in, bs_out, bank_df_no_free;
logic [BURSTCOUNT_W-1:0] bs_burstcounter;
logic bs_read, bs_write, bs_full, bs_empty, bs_valid;
logic bs_doneburst /* synthesis keep = 1 */;
logic bs_notmidburst /* synthesis keep = 1 */;
logic [DATA_W-1:0] bank_df_out [NUM_BANKS];
logic [$clog2(WRITE_ACK_FIFO_DEPTH)-1:0] bs_free;
// Bank select FIFO. Tracks which bank the next valid wrack
// should come from.
acl_ll_fifo #(
.DEPTH(WRITE_ACK_FIFO_DEPTH),
.WIDTH(NUM_BANKS)
)
bs_fifo (
.clk( clock ),
.reset( ~resetn ),
.data_in( bs_in ),
.write( bs_write ),
.data_out( bs_out ),
.read( bs_read ),
.empty( bs_empty ),
.full( bs_full )
);
assign bs_doneburst = (bs_burstcounter == m_arb_burstcount);
always @( posedge clock or negedge resetn )
if (!resetn)
bs_burstcounter <= 'b01;
else if (bs_doneburst && bs_write)
bs_burstcounter <= 'b01;
else if (bs_write)
bs_burstcounter <= bs_burstcounter + 'b01;
always @( posedge clock or negedge resetn )
if (!resetn)
bs_notmidburst <= 'b01;
else if (bs_write)
bs_notmidburst <= bs_doneburst;
// The range of values stored by this counter is
// [-1, WRITE_ACK_FIFO_DEPTH - 1]. Initial value is -1.
always @( posedge clock or negedge resetn )
if (!resetn)
bs_free <= WRITE_ACK_FIFO_DEPTH-1;
else
bs_free <= bs_free + bs_read - bs_write;
// Bank select FIFO assignments.
assign bs_in = m_arb_bank_sel;
assign bs_write = m_arb_write & ~(req.stall | stall);
assign bs_read = bs_valid & |(bs_out & has_acks);
assign bs_valid = ~bs_empty;
for( i = 0; i < NUM_BANKS; i = i + 1 )
begin:bank
// "FIFO" of acks to send out. This is just a counter that counts
// the number of wrp acks still left to send out, minus one (so a value
// of -1 indicates no wrp acks left to send out). This allows for
// a single bit to mean zero.
//
// The range of values stored by this counter is
// [-1, WRITE_ACK_FIFO_DEPTH - 1]. Initial value is -1.
logic [$clog2(WRITE_ACK_FIFO_DEPTH):0] ack_counter;
logic decr_ack_counter;
logic ack_counter_incr;
// Logic for ack counter.
always @( posedge clock or negedge resetn )
if( !resetn )
ack_counter <= {$bits(ack_counter){1'b1}}; // -1
else
ack_counter <= ack_counter + ack_counter_incr - decr_ack_counter;
assign decr_ack_counter = bs_valid & bs_out[i] & has_acks[i];
assign has_acks[i] = ~ack_counter[$bits(ack_counter) - 1];
assign ack_counter_incr = b_wrp_ack[i];
end
assign bs_no_burst_free = bs_free < (2**(BURSTCOUNT_W-1)-1);
// Stall if the current request is a write and the bank select fifo is
// full or can not accomodate a full write burst. We must guarantee
// that we can fit the full burst otherwise we'll need to retain the
// bus lock (causing deadlock) or risk the arbitration switching
// masters if we deassert request in the middle of the write burst.
assign stall = m_arb_write & (bs_full | //bs_full should never happen
(bs_no_burst_free&&bs_notmidburst));
// Wrp ack signal.
assign m_wrp_ack = bs_valid & |(bs_out & has_acks);
end
endgenerate
// Stall signal.
assign m_arb_stall = req.stall | rrp.stall | wrp.stall;
endmodule
|
/*
Copyright (c) 2021 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA top-level module
*/
module fpga (
/*
* Clock: 100 MHz
* Reset: Push button, active low
*/
input wire clk_sys_100m_p,
input wire cpu_resetn,
/*
* GPIO
*/
output wire [3:0] user_led,
/*
* Ethernet: QSFP28
*/
output wire [3:0] qsfp0_tx_p,
input wire [3:0] qsfp0_rx_p,
input wire refclk_qsfp0_p,
output wire qsfp0_modsel_l,
output wire qsfp0_reset_l,
input wire qsfp0_modprs_l,
output wire qsfp0_lpmode,
input wire qsfp0_int_l,
output wire [3:0] qsfp1_tx_p,
input wire [3:0] qsfp1_rx_p,
input wire refclk_qsfp1_p,
output wire qsfp1_modsel_l,
output wire qsfp1_reset_l,
input wire qsfp1_modprs_l,
output wire qsfp1_lpmode,
input wire qsfp1_int_l
);
// Clock and reset
wire ninit_done;
reset_release reset_release_inst (
.ninit_done (ninit_done)
);
wire clk_100mhz = clk_sys_100m_p;
wire rst_100mhz;
sync_reset #(
.N(4)
)
sync_reset_100mhz_inst (
.clk(clk_100mhz),
.rst(~cpu_resetn || ninit_done),
.out(rst_100mhz)
);
// XGMII 10G PHY
assign qsfp0_modsel_l = 1'b0;
assign qsfp0_reset_l = 1'b1;
assign qsfp0_lpmode = 1'b0;
wire qsfp0_tx_clk_1_int;
wire qsfp0_tx_rst_1_int;
wire [63:0] qsfp0_txd_1_int;
wire [7:0] qsfp0_txc_1_int;
wire qsfp0_rx_clk_1_int;
wire qsfp0_rx_rst_1_int;
wire [63:0] qsfp0_rxd_1_int;
wire [7:0] qsfp0_rxc_1_int;
wire qsfp0_tx_clk_2_int;
wire qsfp0_tx_rst_2_int;
wire [63:0] qsfp0_txd_2_int;
wire [7:0] qsfp0_txc_2_int;
wire qsfp0_rx_clk_2_int;
wire qsfp0_rx_rst_2_int;
wire [63:0] qsfp0_rxd_2_int;
wire [7:0] qsfp0_rxc_2_int;
wire qsfp0_tx_clk_3_int;
wire qsfp0_tx_rst_3_int;
wire [63:0] qsfp0_txd_3_int;
wire [7:0] qsfp0_txc_3_int;
wire qsfp0_rx_clk_3_int;
wire qsfp0_rx_rst_3_int;
wire [63:0] qsfp0_rxd_3_int;
wire [7:0] qsfp0_rxc_3_int;
wire qsfp0_tx_clk_4_int;
wire qsfp0_tx_rst_4_int;
wire [63:0] qsfp0_txd_4_int;
wire [7:0] qsfp0_txc_4_int;
wire qsfp0_rx_clk_4_int;
wire qsfp0_rx_rst_4_int;
wire [63:0] qsfp0_rxd_4_int;
wire [7:0] qsfp0_rxc_4_int;
assign qsfp1_modsel_l = 1'b0;
assign qsfp1_reset_l = 1'b1;
assign qsfp1_lpmode = 1'b0;
wire qsfp1_tx_clk_1_int;
wire qsfp1_tx_rst_1_int;
wire [63:0] qsfp1_txd_1_int;
wire [7:0] qsfp1_txc_1_int;
wire qsfp1_rx_clk_1_int;
wire qsfp1_rx_rst_1_int;
wire [63:0] qsfp1_rxd_1_int;
wire [7:0] qsfp1_rxc_1_int;
wire qsfp1_tx_clk_2_int;
wire qsfp1_tx_rst_2_int;
wire [63:0] qsfp1_txd_2_int;
wire [7:0] qsfp1_txc_2_int;
wire qsfp1_rx_clk_2_int;
wire qsfp1_rx_rst_2_int;
wire [63:0] qsfp1_rxd_2_int;
wire [7:0] qsfp1_rxc_2_int;
wire qsfp1_tx_clk_3_int;
wire qsfp1_tx_rst_3_int;
wire [63:0] qsfp1_txd_3_int;
wire [7:0] qsfp1_txc_3_int;
wire qsfp1_rx_clk_3_int;
wire qsfp1_rx_rst_3_int;
wire [63:0] qsfp1_rxd_3_int;
wire [7:0] qsfp1_rxc_3_int;
wire qsfp1_tx_clk_4_int;
wire qsfp1_tx_rst_4_int;
wire [63:0] qsfp1_txd_4_int;
wire [7:0] qsfp1_txc_4_int;
wire qsfp1_rx_clk_4_int;
wire qsfp1_rx_rst_4_int;
wire [63:0] qsfp1_rxd_4_int;
wire [7:0] qsfp1_rxc_4_int;
assign clk_156mhz_int = qsfp0_tx_clk_1_int;
assign rst_156mhz_int = qsfp0_tx_rst_1_int;
wire qsfp0_rx_block_lock_1;
wire qsfp0_rx_block_lock_2;
wire qsfp0_rx_block_lock_3;
wire qsfp0_rx_block_lock_4;
wire qsfp1_rx_block_lock_1;
wire qsfp1_rx_block_lock_2;
wire qsfp1_rx_block_lock_3;
wire qsfp1_rx_block_lock_4;
eth_xcvr_phy_quad_wrapper qsfp0_eth_xcvr_phy_quad (
.xcvr_ctrl_clk(clk_100mhz),
.xcvr_ctrl_rst(rst_100mhz),
.xcvr_ref_clk(refclk_qsfp0_p),
.xcvr_tx_serial_data(qsfp0_tx_p),
.xcvr_rx_serial_data(qsfp0_rx_p),
.phy_1_tx_clk(qsfp0_tx_clk_1_int),
.phy_1_tx_rst(qsfp0_tx_rst_1_int),
.phy_1_xgmii_txd(qsfp0_txd_1_int),
.phy_1_xgmii_txc(qsfp0_txc_1_int),
.phy_1_rx_clk(qsfp0_rx_clk_1_int),
.phy_1_rx_rst(qsfp0_rx_rst_1_int),
.phy_1_xgmii_rxd(qsfp0_rxd_1_int),
.phy_1_xgmii_rxc(qsfp0_rxc_1_int),
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
.phy_2_xgmii_txd(qsfp0_txd_2_int),
.phy_2_xgmii_txc(qsfp0_txc_2_int),
.phy_2_rx_clk(qsfp0_rx_clk_2_int),
.phy_2_rx_rst(qsfp0_rx_rst_2_int),
.phy_2_xgmii_rxd(qsfp0_rxd_2_int),
.phy_2_xgmii_rxc(qsfp0_rxc_2_int),
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
.phy_3_xgmii_txd(qsfp0_txd_3_int),
.phy_3_xgmii_txc(qsfp0_txc_3_int),
.phy_3_rx_clk(qsfp0_rx_clk_3_int),
.phy_3_rx_rst(qsfp0_rx_rst_3_int),
.phy_3_xgmii_rxd(qsfp0_rxd_3_int),
.phy_3_xgmii_rxc(qsfp0_rxc_3_int),
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
.phy_4_xgmii_txd(qsfp0_txd_4_int),
.phy_4_xgmii_txc(qsfp0_txc_4_int),
.phy_4_rx_clk(qsfp0_rx_clk_4_int),
.phy_4_rx_rst(qsfp0_rx_rst_4_int),
.phy_4_xgmii_rxd(qsfp0_rxd_4_int),
.phy_4_xgmii_rxc(qsfp0_rxc_4_int),
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber()
);
eth_xcvr_phy_quad_wrapper qsfp1_eth_xcvr_phy_quad (
.xcvr_ctrl_clk(clk_100mhz),
.xcvr_ctrl_rst(rst_100mhz),
.xcvr_ref_clk(refclk_qsfp1_p),
.xcvr_tx_serial_data(qsfp1_tx_p),
.xcvr_rx_serial_data(qsfp1_rx_p),
.phy_1_tx_clk(qsfp1_tx_clk_1_int),
.phy_1_tx_rst(qsfp1_tx_rst_1_int),
.phy_1_xgmii_txd(qsfp1_txd_1_int),
.phy_1_xgmii_txc(qsfp1_txc_1_int),
.phy_1_rx_clk(qsfp1_rx_clk_1_int),
.phy_1_rx_rst(qsfp1_rx_rst_1_int),
.phy_1_xgmii_rxd(qsfp1_rxd_1_int),
.phy_1_xgmii_rxc(qsfp1_rxc_1_int),
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
.phy_2_xgmii_txd(qsfp1_txd_2_int),
.phy_2_xgmii_txc(qsfp1_txc_2_int),
.phy_2_rx_clk(qsfp1_rx_clk_2_int),
.phy_2_rx_rst(qsfp1_rx_rst_2_int),
.phy_2_xgmii_rxd(qsfp1_rxd_2_int),
.phy_2_xgmii_rxc(qsfp1_rxc_2_int),
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
.phy_3_xgmii_txd(qsfp1_txd_3_int),
.phy_3_xgmii_txc(qsfp1_txc_3_int),
.phy_3_rx_clk(qsfp1_rx_clk_3_int),
.phy_3_rx_rst(qsfp1_rx_rst_3_int),
.phy_3_xgmii_rxd(qsfp1_rxd_3_int),
.phy_3_xgmii_rxc(qsfp1_rxc_3_int),
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
.phy_4_xgmii_txd(qsfp1_txd_4_int),
.phy_4_xgmii_txc(qsfp1_txc_4_int),
.phy_4_rx_clk(qsfp1_rx_clk_4_int),
.phy_4_rx_rst(qsfp1_rx_rst_4_int),
.phy_4_xgmii_rxd(qsfp1_rxd_4_int),
.phy_4_xgmii_rxc(qsfp1_rxc_4_int),
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber()
);
fpga_core
core_inst (
/*
* Clock: 156.25 MHz
* Synchronous reset
*/
.clk(clk_156mhz_int),
.rst(rst_156mhz_int),
/*
* GPIO
*/
.user_led(user_led),
/*
* Ethernet: QSFP28
*/
.qsfp0_tx_clk_1(qsfp0_tx_clk_1_int),
.qsfp0_tx_rst_1(qsfp0_tx_rst_1_int),
.qsfp0_txd_1(qsfp0_txd_1_int),
.qsfp0_txc_1(qsfp0_txc_1_int),
.qsfp0_rx_clk_1(qsfp0_rx_clk_1_int),
.qsfp0_rx_rst_1(qsfp0_rx_rst_1_int),
.qsfp0_rxd_1(qsfp0_rxd_1_int),
.qsfp0_rxc_1(qsfp0_rxc_1_int),
.qsfp0_tx_clk_2(qsfp0_tx_clk_2_int),
.qsfp0_tx_rst_2(qsfp0_tx_rst_2_int),
.qsfp0_txd_2(qsfp0_txd_2_int),
.qsfp0_txc_2(qsfp0_txc_2_int),
.qsfp0_rx_clk_2(qsfp0_rx_clk_2_int),
.qsfp0_rx_rst_2(qsfp0_rx_rst_2_int),
.qsfp0_rxd_2(qsfp0_rxd_2_int),
.qsfp0_rxc_2(qsfp0_rxc_2_int),
.qsfp0_tx_clk_3(qsfp0_tx_clk_3_int),
.qsfp0_tx_rst_3(qsfp0_tx_rst_3_int),
.qsfp0_txd_3(qsfp0_txd_3_int),
.qsfp0_txc_3(qsfp0_txc_3_int),
.qsfp0_rx_clk_3(qsfp0_rx_clk_3_int),
.qsfp0_rx_rst_3(qsfp0_rx_rst_3_int),
.qsfp0_rxd_3(qsfp0_rxd_3_int),
.qsfp0_rxc_3(qsfp0_rxc_3_int),
.qsfp0_tx_clk_4(qsfp0_tx_clk_4_int),
.qsfp0_tx_rst_4(qsfp0_tx_rst_4_int),
.qsfp0_txd_4(qsfp0_txd_4_int),
.qsfp0_txc_4(qsfp0_txc_4_int),
.qsfp0_rx_clk_4(qsfp0_rx_clk_4_int),
.qsfp0_rx_rst_4(qsfp0_rx_rst_4_int),
.qsfp0_rxd_4(qsfp0_rxd_4_int),
.qsfp0_rxc_4(qsfp0_rxc_4_int),
.qsfp1_tx_clk_1(qsfp1_tx_clk_1_int),
.qsfp1_tx_rst_1(qsfp1_tx_rst_1_int),
.qsfp1_txd_1(qsfp1_txd_1_int),
.qsfp1_txc_1(qsfp1_txc_1_int),
.qsfp1_rx_clk_1(qsfp1_rx_clk_1_int),
.qsfp1_rx_rst_1(qsfp1_rx_rst_1_int),
.qsfp1_rxd_1(qsfp1_rxd_1_int),
.qsfp1_rxc_1(qsfp1_rxc_1_int),
.qsfp1_tx_clk_2(qsfp1_tx_clk_2_int),
.qsfp1_tx_rst_2(qsfp1_tx_rst_2_int),
.qsfp1_txd_2(qsfp1_txd_2_int),
.qsfp1_txc_2(qsfp1_txc_2_int),
.qsfp1_rx_clk_2(qsfp1_rx_clk_2_int),
.qsfp1_rx_rst_2(qsfp1_rx_rst_2_int),
.qsfp1_rxd_2(qsfp1_rxd_2_int),
.qsfp1_rxc_2(qsfp1_rxc_2_int),
.qsfp1_tx_clk_3(qsfp1_tx_clk_3_int),
.qsfp1_tx_rst_3(qsfp1_tx_rst_3_int),
.qsfp1_txd_3(qsfp1_txd_3_int),
.qsfp1_txc_3(qsfp1_txc_3_int),
.qsfp1_rx_clk_3(qsfp1_rx_clk_3_int),
.qsfp1_rx_rst_3(qsfp1_rx_rst_3_int),
.qsfp1_rxd_3(qsfp1_rxd_3_int),
.qsfp1_rxc_3(qsfp1_rxc_3_int),
.qsfp1_tx_clk_4(qsfp1_tx_clk_4_int),
.qsfp1_tx_rst_4(qsfp1_tx_rst_4_int),
.qsfp1_txd_4(qsfp1_txd_4_int),
.qsfp1_txc_4(qsfp1_txc_4_int),
.qsfp1_rx_clk_4(qsfp1_rx_clk_4_int),
.qsfp1_rx_rst_4(qsfp1_rx_rst_4_int),
.qsfp1_rxd_4(qsfp1_rxd_4_int),
.qsfp1_rxc_4(qsfp1_rxc_4_int)
);
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
* This is a variant of the staging reg - which allows you to add an
* pre-initialized value; useful for feedback channels
*/
module init_reg
(
clk, reset, i_init, i_data, i_valid, o_stall, o_data, o_valid, i_stall
);
/*************
* Parameters *
*************/
parameter WIDTH = 32;
parameter INIT = 0;
parameter INIT_VAL = 32'h0000000000000000;
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
input i_init;
// Upstream interface
input [WIDTH-1:0] i_data;
input i_valid;
output o_stall;
// Downstream interface
output [WIDTH-1:0] o_data;
output o_valid;
input i_stall;
/***************
* Architecture *
***************/
reg [WIDTH-1:0] r_data;
reg r_valid;
// Upstream
assign o_stall = r_valid;
// Downstream
assign o_data = (r_valid) ? r_data : i_data;
assign o_valid = (r_valid) ? r_valid : i_valid;
// Storage reg
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_valid <= INIT;
r_data <= INIT_VAL;
end
else if (i_init)
begin
r_valid <= INIT;
r_data <= INIT_VAL;
end
else
begin
if (~r_valid) r_data <= i_data;
r_valid <= i_stall && (r_valid || i_valid);
end
end
endmodule
//===----------------------------------------------------------------------===//
//
// Avalon Streaming Read Unit
//
//===----------------------------------------------------------------------===//
module st_read (
clock,
resetn,
i_init,
// input stream from kernel pipeline
// this triggers the read request from the fifo
i_predicate,
i_valid,
o_stall,
// downstream (ouput), to kernel pipeline
o_valid,
i_stall,
o_data,
o_datavalid, // used only in non-blocking case
// input data from inter kernel pipeline
i_fifodata,
i_fifovalid,
o_fifoready,
i_fifosize,
// profiler
profile_i_valid,
profile_i_stall,
profile_o_stall,
profile_total_req,
profile_fifo_stall,
profile_total_fifo_size, profile_total_fifo_size_incr
);
parameter DATA_WIDTH = 32;
parameter INIT = 0;
parameter INIT_VAL = 64'h0000000000000000;
parameter NON_BLOCKING = 1'b0;
parameter FIFOSIZE_WIDTH=32;
parameter ACL_PROFILE=0; // Set to 1 to enable stall/valid profiling
parameter ACL_PROFILE_INCREMENT_WIDTH=32;
input clock, resetn, i_stall, i_valid, i_fifovalid;
// init reinitializes the init fifo
input i_init;
output o_stall, o_valid, o_fifoready;
input i_predicate;
output o_datavalid;
output [DATA_WIDTH-1:0] o_data;
input [DATA_WIDTH-1:0] i_fifodata;
input [FIFOSIZE_WIDTH-1:0] i_fifosize;
// profiler
output profile_i_valid;
output profile_i_stall;
output profile_o_stall;
output profile_total_req;
output profile_fifo_stall;
output profile_total_fifo_size;
output [ACL_PROFILE_INCREMENT_WIDTH-1:0] profile_total_fifo_size_incr;
wire feedback_downstream, data_downstream;
wire nop = i_predicate;
wire initvalid;
wire initready;
assign feedback_downstream = i_valid & ~nop & initvalid;
assign data_downstream = i_valid & nop;
assign o_datavalid = feedback_downstream;
wire init_reset;
wire r_o_stall;
wire init_val;
generate
if ( INIT ) begin
assign init_reset = ~resetn;
assign init_val = i_init;
init_reg
#( .WIDTH ( DATA_WIDTH ),
.INIT ( INIT ),
.INIT_VAL ( INIT_VAL ) )
reg_data (
.clk ( clock ),
.reset ( init_reset ),
.i_init ( init_val ),
.i_data ( i_fifodata ),
.i_valid ( i_fifovalid ),
.o_valid ( initvalid ),
.o_data ( o_data ),
.o_stall ( r_o_stall ),
.i_stall ( ~initready )
);
end
else begin
assign init_reset = ~resetn;
assign init_val = 1'b0;
assign o_data = i_fifodata;
assign initvalid = i_fifovalid;
assign r_o_stall = ~initready;
end
endgenerate
assign o_fifoready = ~r_o_stall;
assign o_valid = feedback_downstream | data_downstream | ( i_valid & NON_BLOCKING );
assign o_data_valid = feedback_downstream;
// assign o_data = i_fifodata ;
// stall upstream if
// downstream is stalling (i_stall)
// I'm waiting for data from fifo, don't stall if this read is
// predicated
assign o_stall = ( i_valid & ~nop & ~initvalid & ~NON_BLOCKING) | i_stall;
// don't accept data if:
// downstream cannot accept data (i_stall)
// data from upstream is selected (data_downstream)
// no thread exists to read data (~i_valid)
// TODO: I should never set o_fifoready is this is
// a fifo peek operation
assign initready = ~(i_stall | data_downstream | ~i_valid);
generate
if(ACL_PROFILE==1)
begin
assign profile_i_valid = ( i_valid & ~o_stall );
assign profile_i_stall = ( o_valid & i_stall );
assign profile_o_stall = ( i_valid & o_stall );
assign profile_total_req = ( i_valid & ~o_stall & ~nop );
assign profile_fifo_stall = ( i_valid & ~nop & ~initvalid );
// use fifosize value when we actually receive the data
assign profile_total_fifo_size = ( i_fifovalid & o_fifoready );
assign profile_total_fifo_size_incr = i_fifosize;
end
else
begin
assign profile_i_valid = 1'b0;
assign profile_i_stall = 1'b0;
assign profile_o_stall = 1'b0;
assign profile_total_req = 1'b0;
assign profile_fifo_stall = 1'b0;
assign profile_total_fifo_size = 1'b0;
assign profile_total_fifo_size_incr = {ACL_PROFILE_INCREMENT_WIDTH{1'b0}};
end
endgenerate
endmodule
//===----------------------------------------------------------------------===//
//
// Avalon Streaming Write Unit
// downstream are signals that continue into our "normal" pipeline.
//
//===----------------------------------------------------------------------===//
module st_write (
clock,
resetn,
// interface from kernel pipeline, input stream
i_predicate,
i_data,
i_valid,
o_stall,
// interface to kernel pipeline, downstream
o_valid,
o_ack,
i_stall,
// data_out,
// interface to kernel channel fifo, avalon master
o_fifodata,
o_fifovalid,
i_fifoready,
i_fifosize,
// profiler
profile_i_valid,
profile_i_stall,
profile_o_stall,
profile_total_req,
profile_fifo_stall,
profile_total_fifo_size, profile_total_fifo_size_incr
);
parameter DATA_WIDTH = 32;
parameter NON_BLOCKING = 1'b0;
parameter FIFOSIZE_WIDTH=32;
parameter EFI_LATENCY = 1;
parameter ACL_PROFILE=0; // Set to 1 to enable stall/valid profiling
parameter ACL_PROFILE_INCREMENT_WIDTH=32;
input clock, resetn, i_stall, i_valid, i_fifoready;
output o_stall, o_valid, o_fifovalid;
input [DATA_WIDTH-1:0] i_data;
input i_predicate;
output [DATA_WIDTH-1:0] o_fifodata;
output o_ack;
input [FIFOSIZE_WIDTH-1:0] i_fifosize;
// profiler
output profile_i_valid;
output profile_i_stall;
output profile_o_stall;
output profile_total_req;
output profile_fifo_stall;
output profile_total_fifo_size;
output [ACL_PROFILE_INCREMENT_WIDTH-1:0] profile_total_fifo_size_incr;
wire nop;
assign nop = i_predicate;
wire fifo_stall;
generate
if (EFI_LATENCY == 0) begin
// if latency is 0 - this will create a combinational cycle with
// the stall-valid logic since I
// connect directly to the EFI st_read as will the
// efi_module path.
// efi_st_write-> efi_mod
// ^ |
// | |
// efi_st_read <-----|
//
// This modification breaks
// the cycle and works because the fifo path will stall back
// appropriately if the st_read is being stalled (i.e. I don't have
// to check the pipeline stall for o_stall).
// efi_st_write-> efi_mod
// |
// |
// efi_st_read <-----|
assign o_valid = i_valid;
assign o_stall = (nop & i_stall) | ( (fifo_stall & (~nop) & i_valid & !NON_BLOCKING) );
assign o_fifovalid = i_valid & ~nop;
end
else begin
assign o_valid = i_valid & (i_fifoready | nop | NON_BLOCKING);
assign o_stall = i_stall | (fifo_stall & (~nop) & i_valid & !NON_BLOCKING) ;
assign o_fifovalid = i_valid & ~nop & ~i_stall;
end
endgenerate
assign o_ack = o_fifovalid & i_fifoready;
assign fifo_stall = ~i_fifoready;
assign o_fifodata = i_data;
generate
if(ACL_PROFILE==1)
begin
assign profile_i_valid = ( i_valid & ~o_stall );
assign profile_i_stall = ( o_valid & i_stall );
assign profile_o_stall = ( i_valid & o_stall );
assign profile_total_req = ( i_valid & ~o_stall & ~nop );
assign profile_fifo_stall = (fifo_stall & (~nop) & i_valid) ;
// use fifosize value when we actually send the data
assign profile_total_fifo_size = ( o_fifovalid & i_fifoready );
assign profile_total_fifo_size_incr = i_fifosize;
end
else
begin
assign profile_i_valid = 1'b0;
assign profile_i_stall = 1'b0;
assign profile_o_stall = 1'b0;
assign profile_total_req = 1'b0;
assign profile_fifo_stall = 1'b0;
assign profile_total_fifo_size = 1'b0;
assign profile_total_fifo_size_incr = {ACL_PROFILE_INCREMENT_WIDTH{1'b0}};
end
endgenerate
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 400.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "2500 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "true";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "true";
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_uitofp(clock, resetn,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATA_WIDTH = 32;
parameter LATENCY = 6;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATA_WIDTH-1:0] o_dataout;
input i_dataout_stall;
output o_dataout_valid;
reg [LATENCY-1:0] shift_reg_valid;
wire [DATA_WIDTH-1:0] fifo_dataout;
wire fifo_dataout_valid;
wire is_stalled;
wire is_fifo_stalled;
vfabric_buffered_fifo fifo_in ( .clock(clock), .resetn(resetn),
.data_in(i_datain), .data_out(fifo_dataout), .valid_in(i_datain_valid),
.valid_out( fifo_dataout_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datain_stall) );
defparam fifo_in.DATA_WIDTH = DATA_WIDTH;
defparam fifo_in.DEPTH = FIFO_DEPTH;
acl_fp_uitofp uitofp( .clock(clock), .enable(~is_stalled),
.dataa(fifo_dataout), .result(o_dataout));
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
shift_reg_valid <= {LATENCY{1'b0}};
end
else
begin
if(~is_stalled)
shift_reg_valid <= { fifo_dataout_valid, shift_reg_valid[LATENCY-1:1] };
end
end
assign is_stalled = (shift_reg_valid[0] & i_dataout_stall);
assign is_fifo_stalled = (shift_reg_valid[0] & i_dataout_stall) | ~fifo_dataout_valid;
assign o_dataout_valid = shift_reg_valid[0];
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pipe_reset.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_reset.v
// Description : PIPE Reset Module for 7 Series Transceiver
// Version : 20.2
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Reset Module -------------------------------------------------
module pcie_7x_v1_11_0_pipe_reset #
(
//---------- Global ------------------------------------
parameter PCIE_SIM_SPEEDUP = "FALSE", // PCIe sim speedup
parameter PCIE_GT_DEVICE = "GTX",
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_POWER_SAVING = "TRUE", // PCIe power saving
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable
parameter PCIE_LANE = 1, // PCIe number of lanes
//---------- Local -------------------------------------
parameter CFG_WAIT_MAX = 6'd63, // Configuration wait max
parameter BYPASS_RXCDRLOCK = 1 // Bypass RXCDRLOCK
)
(
//---------- Input -------------------------------------
input RST_CLK,
input RST_RXUSRCLK,
input RST_DCLK,
input RST_RST_N,
input [PCIE_LANE-1:0] RST_DRP_DONE,
input [PCIE_LANE-1:0] RST_RXPMARESETDONE,
input [PCIE_LANE-1:0] RST_CPLLLOCK,
input RST_QPLL_IDLE,
input [PCIE_LANE-1:0] RST_RATE_IDLE,
input [PCIE_LANE-1:0] RST_RXCDRLOCK,
input RST_MMCM_LOCK,
input [PCIE_LANE-1:0] RST_RESETDONE,
input [PCIE_LANE-1:0] RST_PHYSTATUS,
input [PCIE_LANE-1:0] RST_TXSYNC_DONE,
//---------- Output ------------------------------------
output RST_CPLLRESET,
output RST_CPLLPD,
output reg RST_DRP_START,
output reg RST_DRP_X16X20_MODE,
output reg RST_DRP_X16,
output RST_RXUSRCLK_RESET,
output RST_DCLK_RESET,
output RST_GTRESET,
output RST_USERRDY,
output RST_TXSYNC_START,
output RST_IDLE,
output [4:0] RST_FSM
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] drp_done_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxpmaresetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] cplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qpll_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rate_idle_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] rxcdrlock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg mmcm_lock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] resetdone_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] phystatus_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] txsync_done_reg2;
//---------- Internal Signal ---------------------------
reg [ 5:0] cfg_wait_cnt = 6'd0;
//---------- Output Register ---------------------------
reg cpllreset = 1'd0;
reg cpllpd = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg1 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rxusrclk_rst_reg2 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg1 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg dclk_rst_reg2 = 1'd0;
reg gtreset = 1'd0;
reg userrdy = 1'd0;
reg [4:0] fsm = 5'h2;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 5'h0;
localparam FSM_CFG_WAIT = 5'h1;
localparam FSM_CPLLRESET = 5'h2;
localparam FSM_DRP_X16_START = 5'h3;
localparam FSM_DRP_X16_DONE = 5'h4;
localparam FSM_CPLLLOCK = 5'h5;
localparam FSM_DRP = 5'h6;
localparam FSM_GTRESET = 5'h7;
localparam FSM_RXPMARESETDONE_1 = 5'h8;
localparam FSM_RXPMARESETDONE_2 = 5'h9;
localparam FSM_DRP_X20_START = 5'hA;
localparam FSM_DRP_X20_DONE = 5'hB;
localparam FSM_MMCM_LOCK = 5'hC;
localparam FSM_RESETDONE = 5'hD;
localparam FSM_CPLL_PD = 5'hE;
localparam FSM_TXSYNC_START = 5'hF;
localparam FSM_TXSYNC_DONE = 5'h10;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
//---------- 1st Stage FF --------------------------
drp_done_reg1 <= {PCIE_LANE{1'd0}};
rxpmaresetdone_reg1 <= {PCIE_LANE{1'd0}};
cplllock_reg1 <= {PCIE_LANE{1'd0}};
qpll_idle_reg1 <= 1'd0;
rate_idle_reg1 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg1 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg1 <= 1'd0;
resetdone_reg1 <= {PCIE_LANE{1'd0}};
phystatus_reg1 <= {PCIE_LANE{1'd0}};
txsync_done_reg1 <= {PCIE_LANE{1'd0}};
//---------- 2nd Stage FF --------------------------
drp_done_reg2 <= {PCIE_LANE{1'd0}};
rxpmaresetdone_reg2 <= {PCIE_LANE{1'd0}};
cplllock_reg2 <= {PCIE_LANE{1'd0}};
qpll_idle_reg2 <= 1'd0;
rate_idle_reg2 <= {PCIE_LANE{1'd0}};
rxcdrlock_reg2 <= {PCIE_LANE{1'd0}};
mmcm_lock_reg2 <= 1'd0;
resetdone_reg2 <= {PCIE_LANE{1'd0}};
phystatus_reg2 <= {PCIE_LANE{1'd0}};
txsync_done_reg2 <= {PCIE_LANE{1'd0}};
end
else
begin
//---------- 1st Stage FF --------------------------
drp_done_reg1 <= RST_DRP_DONE;
rxpmaresetdone_reg1 <= RST_RXPMARESETDONE;
cplllock_reg1 <= RST_CPLLLOCK;
qpll_idle_reg1 <= RST_QPLL_IDLE;
rate_idle_reg1 <= RST_RATE_IDLE;
rxcdrlock_reg1 <= RST_RXCDRLOCK;
mmcm_lock_reg1 <= RST_MMCM_LOCK;
resetdone_reg1 <= RST_RESETDONE;
phystatus_reg1 <= RST_PHYSTATUS;
txsync_done_reg1 <= RST_TXSYNC_DONE;
//---------- 2nd Stage FF --------------------------
drp_done_reg2 <= drp_done_reg1;
rxpmaresetdone_reg2 <= rxpmaresetdone_reg1;
cplllock_reg2 <= cplllock_reg1;
qpll_idle_reg2 <= qpll_idle_reg1;
rate_idle_reg2 <= rate_idle_reg1;
rxcdrlock_reg2 <= rxcdrlock_reg1;
mmcm_lock_reg2 <= mmcm_lock_reg1;
resetdone_reg2 <= resetdone_reg1;
phystatus_reg2 <= phystatus_reg1;
txsync_done_reg2 <= txsync_done_reg1;
end
end
//---------- Configuration Reset Wait Counter ----------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
cfg_wait_cnt <= 6'd0;
else
//---------- Increment Configuration Reset Wait Counter
if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt < CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt + 6'd1;
//---------- Hold Configuration Reset Wait Counter -
else if ((fsm == FSM_CFG_WAIT) && (cfg_wait_cnt == CFG_WAIT_MAX))
cfg_wait_cnt <= cfg_wait_cnt;
//---------- Reset Configuration Reset Wait Counter
else
cfg_wait_cnt <= 6'd0;
end
//---------- PIPE Reset FSM ----------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (!RST_RST_N)
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
end
//---------- Wait for Configuration Reset Delay ---
FSM_CFG_WAIT :
begin
fsm <= ((cfg_wait_cnt == CFG_WAIT_MAX) ? FSM_CPLLRESET : FSM_CFG_WAIT);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Hold CPLL and GTX Channel in Reset ----
FSM_CPLLRESET :
begin
fsm <= ((&(~cplllock_reg2) && (&(~resetdone_reg2))) ? FSM_CPLLLOCK : FSM_CPLLRESET);
cpllreset <= 1'd1;
cpllpd <= cpllpd;
gtreset <= 1'd1;
userrdy <= userrdy;
end
//---------- Wait for CPLL Lock --------------------
FSM_CPLLLOCK :
begin
fsm <= (&cplllock_reg2 ? FSM_DRP : FSM_CPLLLOCK);
cpllreset <= 1'd0;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP Done to Setup Gen1 -------
FSM_DRP :
begin
fsm <= (&rate_idle_reg2 ? ((PCIE_GT_DEVICE == "GTX") ? FSM_GTRESET : FSM_DRP_X16_START) : FSM_DRP);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start DRP x16 -------------------------
FSM_DRP_X16_START :
begin
fsm <= &(~drp_done_reg2) ? FSM_DRP_X16_DONE : FSM_DRP_X16_START;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP x16 Done -----------------
FSM_DRP_X16_DONE :
begin
fsm <= (&drp_done_reg2) ? FSM_GTRESET : FSM_DRP_X16_DONE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Release GTX Channel Reset -------------
FSM_GTRESET :
begin
fsm <= (PCIE_GT_DEVICE == "GTX") ? FSM_MMCM_LOCK : FSM_RXPMARESETDONE_1;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= 1'b0;
userrdy <= userrdy;
end
//---------- Wait for RXPMARESETDONE Assertion -----
FSM_RXPMARESETDONE_1 :
begin
fsm <= (&rxpmaresetdone_reg2 || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_RXPMARESETDONE_2 : FSM_RXPMARESETDONE_1;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for RXPMARESETDONE De-assertion --
FSM_RXPMARESETDONE_2 :
begin
fsm <= (&(~rxpmaresetdone_reg2) || (PCIE_SIM_SPEEDUP == "TRUE")) ? FSM_DRP_X20_START : FSM_RXPMARESETDONE_2;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start DRP x20 -------------------------
FSM_DRP_X20_START :
begin
fsm <= &(~drp_done_reg2) ? FSM_DRP_X20_DONE : FSM_DRP_X20_START;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for DRP x20 Done -----------------
FSM_DRP_X20_DONE :
begin
fsm <= (&drp_done_reg2) ? FSM_MMCM_LOCK : FSM_DRP_X20_DONE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for MMCM and RX CDR Lock ---------
FSM_MMCM_LOCK :
begin
if (mmcm_lock_reg2 && (&rxcdrlock_reg2 || (BYPASS_RXCDRLOCK == 1)) && (qpll_idle_reg2 || (PCIE_PLL_SEL == "CPLL")))
begin
fsm <= FSM_RESETDONE;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= 1'd1;
end
else
begin
fsm <= FSM_MMCM_LOCK;
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= 1'd0;
end
end
//---------- Wait for [TX/RX]RESETDONE and PHYSTATUS
FSM_RESETDONE :
begin
fsm <= (&resetdone_reg2 && (&(~phystatus_reg2)) ? FSM_CPLL_PD : FSM_RESETDONE);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Power-Down CPLL if QPLL is Used for Gen1/Gen2
FSM_CPLL_PD :
begin
fsm <= ((PCIE_TXBUF_EN == "TRUE") ? FSM_IDLE : FSM_TXSYNC_START);
cpllreset <= cpllreset;
cpllpd <= (PCIE_PLL_SEL == "QPLL");
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Start TX Sync -------------------------
FSM_TXSYNC_START :
begin
fsm <= (&(~txsync_done_reg2) ? FSM_TXSYNC_DONE : FSM_TXSYNC_START);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Wait for TX Sync Done -----------------
FSM_TXSYNC_DONE :
begin
fsm <= (&txsync_done_reg2 ? FSM_IDLE : FSM_TXSYNC_DONE);
cpllreset <= cpllreset;
cpllpd <= cpllpd;
gtreset <= gtreset;
userrdy <= userrdy;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_CFG_WAIT;
cpllreset <= 1'd0;
cpllpd <= 1'd0;
gtreset <= 1'd0;
userrdy <= 1'd0;
end
endcase
end
end
//---------- RXUSRCLK Reset Synchronizer ---------------------------------------
always @ (posedge RST_RXUSRCLK)
begin
if (cpllreset)
begin
rxusrclk_rst_reg1 <= 1'd1;
rxusrclk_rst_reg2 <= 1'd1;
end
else
begin
rxusrclk_rst_reg1 <= 1'd0;
rxusrclk_rst_reg2 <= rxusrclk_rst_reg1;
end
end
//---------- DCLK Reset Synchronizer -------------------------------------------
always @ (posedge RST_DCLK)
begin
if (fsm == FSM_CFG_WAIT)
begin
dclk_rst_reg1 <= 1'd1;
dclk_rst_reg2 <= dclk_rst_reg1;
end
else
begin
dclk_rst_reg1 <= 1'd0;
dclk_rst_reg2 <= dclk_rst_reg1;
end
end
//---------- PIPE Reset Output -------------------------------------------------
assign RST_CPLLRESET = cpllreset;
assign RST_CPLLPD = ((PCIE_POWER_SAVING == "FALSE") ? 1'd0 : cpllpd);
assign RST_RXUSRCLK_RESET = rxusrclk_rst_reg2;
assign RST_DCLK_RESET = dclk_rst_reg2;
assign RST_GTRESET = gtreset;
assign RST_USERRDY = userrdy;
assign RST_TXSYNC_START = (fsm == FSM_TXSYNC_START);
assign RST_IDLE = (fsm == FSM_IDLE);
assign RST_FSM = fsm;
//--------------------------------------------------------------------------------------------------
// Register Output
//--------------------------------------------------------------------------------------------------
always @ (posedge RST_CLK)
begin
if (!RST_RST_N)
begin
RST_DRP_START <= 1'd0;
RST_DRP_X16X20_MODE <= 1'd0;
RST_DRP_X16 <= 1'd0;
end
else
begin
RST_DRP_START <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X20_START);
RST_DRP_X16X20_MODE <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE) || (fsm == FSM_DRP_X20_START) || (fsm == FSM_DRP_X20_DONE);
RST_DRP_X16 <= (fsm == FSM_DRP_X16_START) || (fsm == FSM_DRP_X16_DONE);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O22AI_1_V
`define SKY130_FD_SC_LS__O22AI_1_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22ai_1 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o22ai_1 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O22AI_1_V
|
// part of NeoGS project (c) 2007-2008 NedoPC
//
// SPI mode 0 8-bit master module
//
// short diagram for speed=0 (Fclk/Fspi=2, no rdy shown)
//
// clock: ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ (positive edges)
// counter: |00|00|10|11|12|13|14|15|16|17|18|19|1A|1B|1C|1D|1E|1F|00|00|00 // internal!
// sck: ___________/``\__/``\__/``\__/``\__/``\__/``\__/``\__/``\_______
// sdo: --------< do7 X do6 X do5 X do4 X do3 X do2 X do1 X do0 >-------
// sdi: --------< di7 X di6 X di5 X di4 X di3 X di2 X di1 X di0 >-------
// bsync: ________/`````\_________________________________________________
// start: _____/``\_______________________________________________________
// din: -----<IN>-------------------------------------------------------
// dout: old old old old old old old old old old old old old | new new new
//
// data on sdo must be latched by slave on rising sck edge. data on sdo changes on falling edge of sck
//
// data from sdi is latched by master on positive edge of sck, while slave changes it on falling edge.
// WARNING: slave must emit valid di7 bit BEFORE first pulse on sck!
//
// bsync is 1 while do7 is outting, otherwise it is 0
//
// start is synchronous pulse, which starts all transfer and also latches din data on the same clock edge
// as it is registered high. start can be given anytime (only when speed=0),
// so it is functioning then as synchronous reset. when speed!=0, there is global enable for majority of
// flipflops in the module, so start can't be accepted at any time
//
// dout updates with freshly received data at the clock edge in which sck goes high for the last time, thus
// latching last bit on sdi.
//
// sdo emits last bit shifted out after the transfer end
//
// when speed=0, data transfer rate could be as fast as one byte every 16 clock pulses. To achieve that,
// start must be pulsed high simultaneously with the last high pulse of sck
//
// speed[1:0] determines Fclk/Fspi
//
// speed | Fclk/Fspi
// ------+----------
// 2'b00 | 2
// 2'b01 | 4
// 2'b10 | 8
// 2'b11 | 16
//
// for speed=0 you can start new transfer as fast as every 16 clocks
// for speed=1 - every 34 clocks.
// alternatively, you can check rdy output: it goes to 0 after start pulse and when it goes back to 1, you can
// issue another start at the next clock cycle. See spi2_modelled.png and .zip (modelsim project)
//
// warning: if using rdy-driven transfers and speed=0, new transfer will be started every 18 clocks.
// it is recommended to use rdy-driven transfers when speed!=0
//
// warning: this module does not contain asynchronous reset. Provided clock is stable, start=0
// and speed=0, module returns to initial ready state after maximum of 18+8=26 clocks. To reset module
// to the known state from any operational state, set speed=0 and start=1 for 8 clocks
// (that starts Fclk/Fspi=2 speed transfer for sure), then remain start=0, speed=0 for at least 18 clocks.
module spi2(
clock, // system clock
sck, // SPI bus pins...
sdo, //
sdi, //
bsync, // ...and bsync for vs1001
start, // positive strobe that starts transfer
rdy, // ready (idle) - when module can accept data
speed, // =2'b00 - sck full speed (1/2 of clock), =2'b01 - half (1/4 of clock), =2'b10 - one fourth (1/8 of clock), =2'b11 - one eighth (1/16 of clock)
din, // input
dout // and output 8bit busses
);
input clock;
output sck;
wire sck;
output sdo;
input sdi;
output reg bsync;
input start;
output rdy;
input [1:0] speed;
input [7:0] din;
output reg [7:0] dout;
// internal regs
reg [4:0] counter; // governs transmission
wire enable_n; // =1 when transmission in progress
reg [6:0] shiftin; // shifting in data from sdi before emitting it on dout
reg [7:0] shiftout; // shifting out data to the sdo
wire ena_shout_load; // enable load of shiftout register
wire g_ena;
reg [2:0] wcnt;
initial // for simulation only!
begin
counter = 5'b10000;
shiftout = 8'd0;
shiftout = 7'd0;
bsync = 1'd0;
dout = 1'b0;
end
// rdy is enable_n
assign rdy = enable_n;
// sck is low bit of counter
assign sck = counter[0];
// enable_n is high bit of counter
assign enable_n = counter[4];
// sdo is high bit of shiftout
assign sdo = shiftout[7];
assign ena_shout_load = (start | sck) & g_ena;
always @(posedge clock)
begin
if( g_ena )
begin
if( start )
begin
counter <= 5'b00000; // enable_n = 0; sck = 0;
bsync <= 1'b1; // begin bsync pulse
end
else
begin
if( !sck ) // on the rising edge of sck
begin
shiftin[6:0] <= { shiftin[5:0], sdi };
if( (&counter[3:1]) && (!enable_n) )
dout <= { shiftin[6:0], sdi }; // update dout at the last sck rising edge
end
else // on the falling edge of sck
begin
bsync <= 1'b0;
end
if( !enable_n )
counter <= counter + 5'd1;
end
end
end
// shiftout treatment is done so just to save LCELLs in acex1k
always @(posedge clock)
begin
if( ena_shout_load )
begin
if( start )
shiftout <= din;
else // sck
shiftout[7:0] <= { shiftout[6:0], shiftout[0] }; // last bit remains after end of exchange
end
end
// slow speeds - governed by g_ena
always @(posedge clock)
begin
if( speed!=2'b00 )
begin
if( start )
wcnt <= 3'b001;
else if( enable_n )
wcnt <= 3'b000;
else
wcnt <= wcnt + 3'd1;
end
else
wcnt <= 3'b000;
end
assign g_ena = (speed==2'b00) ? 1'b1 :
(speed==2'b01) ? (wcnt[0] == 1'b0 ) :
(speed==2'b10) ? (wcnt[1:0]== 2'b00 ) :
(wcnt[2:0]== 3'b000 ) ;
endmodule
|
//-------------------------------------------------------------------------------------------------
// SPI slave module: The SPI bus is over-sampled using the FPGA clock to allow the SPI logic run
// in the FPGA clock domain. Note FPGA FPGA clock must be at least 2x the SPI. Clock to synchronize
// the SPI signals using the FPGA clock and shift registers.
//
// SPI Interface structure: 24 bit SPI interface, Bits are sent in most to least significant order
// KeyPad, then address and finally data bits as follows:
//
// 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
//+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
//|KP4|KP3|KP2|KP1|KP0|SEL|RST|KEY|IS3|IS2|IS1|IS0|OS3|OS2|OS1|OS0| D7| D6| D5| D4| D3| D2| D1| D0|
//+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
// 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
//
// KeyPad bits have are defined as KP5 - KP1
//-------------------------------------------------------------------------------------------------
module SPI_24_slave(
input clk, // System Clock
input SCK, // SPI Clock Input pin
input SSEL, // SPI Select Input pin
input MOSI, // SPI Serial Input pin
output MISO, // SPI output signal
input data_ready, // Signal that data is ready to be sent out
input [7:0] DataOut, // SPI data to send out
output reg [7:0] DataIn, // SPI data received
output reg [4:0] KeyPad, // Wires to register holding KeyPad
output [3:0] OutSel, // Panel
output [3:0] InSel, // Panel
output KEY, // Keyboard valid signal.
output RST, // Panel
output SEL, // Panel
output reg kbd_received, // KeyPad bits received
output reg pnl_received, // Panel bits received
output reg data_received, // Data bits received
output SPI_Start, // SPI Message start signal
output SPI_Active, // SPI active Signal
output SPI_End // SPI message end signal
);
//-----------------------------------------------------------------------------
// Assign outputs
//-----------------------------------------------------------------------------
assign OutSel = Panel[3:0];
assign InSel = Panel[7:4];
assign KEY = Panel[8 ];
assign RST = Panel[9 ];
assign SEL = Panel[10 ];
//-----------------------------------------------------------------------------
// Find Rising edge of data ready line using a 3-bits shift register
//-----------------------------------------------------------------------------
reg [2:0] DRedge;
always @(posedge clk) DRedge <= {DRedge[1:0], data_ready};
wire DR_risingedge = (DRedge[2:1] == 2'b01); // now we can detect DR rising edge
//-----------------------------------------------------------------------------
// Sync SCK to the FPGA clock using a 3-bits shift register
//-----------------------------------------------------------------------------
reg [2:0] SCKr;
always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1] == 2'b01); // now we can detect SCK rising edges
//-----------------------------------------------------------------------------
// Sync SSEL to the FPGA clock using a 3-bits shift register
//-----------------------------------------------------------------------------
reg [2:0] SSELr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
assign SPI_Active = ~SSELr[1]; // SSEL is active low
assign SPI_Start = (SSELr[2:1] == 2'b10); // Message starts at falling edge
assign SPI_End = (SSELr[2:1] == 2'b01); // Message stops at rising edge
//-----------------------------------------------------------------------------
// Debouner for MOSI
//-----------------------------------------------------------------------------
reg [1:0] MOSIr;
always @(posedge clk) MOSIr <= {MOSIr[0], MOSI};
wire MOSI_data = MOSIr[1];
//-----------------------------------------------------------------------------
// SPI Transceiver:
// This is a 24 8-bit SPI format, 16 bits for Address and 8 Bits data.
// FPGA is only one slave on the SPI bus so we don't bother with
// a tri-state buffer for MISO otherwise we would need to tri-state MISO when SSEL is inactive
//-----------------------------------------------------------------------------
reg [4:0] bitcnt; // Count the bits being exchanged up to 32
reg [10:0] Panel; // Wires to register holding Panel
reg [7:0] databits; // Shift register of output data
wire rcv_addr = (bitcnt > 5'd4); // Receiving address
wire rcv_data = (bitcnt > 5'd15); // Sending and receiving data
assign MISO = rcv_data ? databits[7] : 1'b0; // send MSB first
always @(posedge clk) begin
if(DR_risingedge) databits <= DataOut; // when SPI is selected, load data into shift register
if(~SPI_Active) begin // If SPI is not active
bitcnt <= 5'h00; // Then reset the bit count and
databits <= 8'h00; // Send 0s
// Panel <= 11'h0000; // Default
end
else begin
if(SCK_risingedge) begin
bitcnt <= bitcnt + 5'd1; // Increment the Bit Counter
if(rcv_data) begin
DataIn <= {DataIn[6:0], MOSI_data}; // Input shift-left register
databits <= {databits[6:0], 1'b0}; // Output shift-left register
end
else begin
if(rcv_addr) Panel <= {Panel[9:0], MOSI_data}; // Panel Input shift-left register
else KeyPad <= {KeyPad[3:0], MOSI_data}; // KeyPad Input shift-left register
end
end
end
end
always @(posedge clk) begin
kbd_received <= SPI_Active && SCK_risingedge && (bitcnt == 5'd4 );
pnl_received <= SPI_Active && SCK_risingedge && (bitcnt == 5'd15);
data_received <= SPI_Active && SCK_risingedge && (bitcnt == 5'd23);
end
//-----------------------------------------------------------------------------
endmodule
//-----------------------------------------------------------------------------
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: pipeline.v
// Version: 1.00
// Verilog Standard: Verilog-2001
// Description: Standard 0-delay pipeline implementation. Takes WR_DATA on
// WR_READY and WR_VALID. RD_DATA is read on RD_READY and
// RD_VALID. C_DEPTH specifies the latency between RD and WR ports
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
module pipeline
#(
parameter C_DEPTH = 10,
parameter C_WIDTH = 10,
parameter C_USE_MEMORY = 1
)
(
input CLK,
input RST_IN,
input [C_WIDTH-1:0] WR_DATA,
input WR_DATA_VALID,
output WR_DATA_READY,
output [C_WIDTH-1:0] RD_DATA,
output RD_DATA_VALID,
input RD_DATA_READY
);
generate
if (C_USE_MEMORY & C_DEPTH > 2) begin
mem_pipeline
#(
.C_PIPELINE_INPUT (1),
.C_PIPELINE_OUTPUT (1),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH (C_DEPTH),
.C_WIDTH (C_WIDTH))
pipeline_inst
(/*AUTOINST*/
// Outputs
.WR_DATA_READY (WR_DATA_READY),
.RD_DATA (RD_DATA[C_WIDTH-1:0]),
.RD_DATA_VALID (RD_DATA_VALID),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (WR_DATA[C_WIDTH-1:0]),
.WR_DATA_VALID (WR_DATA_VALID),
.RD_DATA_READY (RD_DATA_READY));
end else begin
reg_pipeline
#(/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH (C_DEPTH),
.C_WIDTH (C_WIDTH))
pipeline_inst
(/*AUTOINST*/
// Outputs
.WR_DATA_READY (WR_DATA_READY),
.RD_DATA (RD_DATA[C_WIDTH-1:0]),
.RD_DATA_VALID (RD_DATA_VALID),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (WR_DATA[C_WIDTH-1:0]),
.WR_DATA_VALID (WR_DATA_VALID),
.RD_DATA_READY (RD_DATA_READY));
end
endgenerate
endmodule // pipeline
module mem_pipeline
#(
parameter C_DEPTH = 10,
parameter C_WIDTH = 10,
parameter C_PIPELINE_INPUT = 0,
parameter C_PIPELINE_OUTPUT = 1
)
(
input CLK,
input RST_IN,
input [C_WIDTH-1:0] WR_DATA,
input WR_DATA_VALID,
output WR_DATA_READY,
output [C_WIDTH-1:0] RD_DATA,
output RD_DATA_VALID,
input RD_DATA_READY
);
localparam C_INPUT_REGISTERS = C_PIPELINE_INPUT?1:0;
localparam C_OUTPUT_REGISTERS = C_PIPELINE_OUTPUT?1:0;
wire RST;
wire [C_WIDTH-1:0] wRdData;
wire wRdDataValid;
wire wRdDataReady;
wire [C_WIDTH-1:0] wWrData;
wire wWrDataValid;
wire wWrDataReady;
assign RST = RST_IN;
reg_pipeline
#(
// Parameters
.C_DEPTH (C_INPUT_REGISTERS),
/*AUTOINSTPARAM*/
// Parameters
.C_WIDTH (C_WIDTH))
reg_in
(
// Outputs
.RD_DATA (wRdData),
.RD_DATA_VALID (wRdDataValid),
// Inputs
.RD_DATA_READY (wRdDataReady),
/*AUTOINST*/
// Outputs
.WR_DATA_READY (WR_DATA_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA (WR_DATA[C_WIDTH-1:0]),
.WR_DATA_VALID (WR_DATA_VALID));
fifo
#(
// Parameters
.C_WIDTH (C_WIDTH),
.C_DEPTH (C_DEPTH - C_PIPELINE_INPUT - C_PIPELINE_OUTPUT),
.C_DELAY (C_DEPTH - C_PIPELINE_INPUT - C_PIPELINE_OUTPUT)
/*AUTOINSTPARAM*/)
fifo_inst
(
// Outputs
.RD_DATA (wWrData),
.WR_READY (wRdDataReady),
.RD_VALID (wWrDataValid),
// Inputs
.WR_DATA (wRdData),
.WR_VALID (wRdDataValid),
.RD_READY (wWrDataReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST (RST));
reg_pipeline
#(
// Parameters
.C_DEPTH (C_OUTPUT_REGISTERS),
.C_WIDTH (C_WIDTH)
/*AUTOINSTPARAM*/)
reg_OUT
(
// Outputs
.WR_DATA_READY (wWrDataReady),
// Inputs
.WR_DATA (wWrData),
.WR_DATA_VALID (wWrDataValid),
/*AUTOINST*/
// Outputs
.RD_DATA (RD_DATA[C_WIDTH-1:0]),
.RD_DATA_VALID (RD_DATA_VALID),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.RD_DATA_READY (RD_DATA_READY));
endmodule // mem_pipeline
/* verilator lint_off UNOPTFLAT */
module reg_pipeline
#(
parameter C_DEPTH = 10,
parameter C_WIDTH = 10
)
(
input CLK,
input RST_IN,
input [C_WIDTH-1:0] WR_DATA,
input WR_DATA_VALID,
output WR_DATA_READY,
output [C_WIDTH-1:0] RD_DATA,
output RD_DATA_VALID,
input RD_DATA_READY
);
genvar i;
wire wReady [C_DEPTH:0];
reg [C_WIDTH-1:0] _rData [C_DEPTH:1], rData [C_DEPTH:0];
reg _rValid [C_DEPTH:1], rValid [C_DEPTH:0];
// Read interface
assign wReady[C_DEPTH] = RD_DATA_READY;
assign RD_DATA = rData[C_DEPTH];
assign RD_DATA_VALID = rValid[C_DEPTH];
// Write interface
assign WR_DATA_READY = wReady[0];
always @(*) begin
rData[0] = WR_DATA;
rValid[0] = WR_DATA_VALID;
end
generate
for( i = 1 ; i <= C_DEPTH; i = i + 1 ) begin : gen_stages
assign #1 wReady[i-1] = ~rValid[i] | wReady[i];
// Data Registers
always @(*) begin
_rData[i] = rData[i-1];
end
// Enable the data register when the corresponding stage is ready
always @(posedge CLK) begin
if(wReady[i-1]) begin
rData[i] <= #1 _rData[i];
end
end
// Valid Registers
always @(*) begin
if(RST_IN) begin
_rValid[i] = 1'b0;
end else begin
_rValid[i] = rValid[i-1] | (rValid[i] & ~wReady[i]);
end
end
// Always enable the valid registers
always @(posedge CLK) begin
rValid[i] <= #1 _rValid[i];
end
end
endgenerate
endmodule
/* verilator lint_on UNOPTFLAT */
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MEMC
// / / Filename: mcb_traffic_gen.v
// /___/ /\ Date Last Modified: $Date:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Virtex7
//Design Name: s7ven_data_gen
//Purpose: This is top level module of memory traffic generator which can
// generate different CMD_PATTERN and DATA_PATTERN to Virtex 7
// hard memory controller core.
// Supported Data pattern: 0 : Reserved.
// 1 : FIXED_DATA_MODE.
// 2 : ADDR_DATA_MODE
// 3 : HAMMER_DATA_MODE
// 4 : NEIGHBOR_DATA_MODE
// 5 : WALKING1_DATA_MODE
// 6 : WALKING0_DATA_MODE
// 7 : TRUE_PRBS_MODE
//
//
//Reference:
//Revision History: 1.1
// 06/2011 Rewrite PRBS code.
//*****************************************************************************
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
module mig_7series_v4_0_s7ven_data_gen #
( parameter DMODE = "WRITE",
parameter nCK_PER_CLK = 2, // 2: Memc core speed 1/2 of memory clock speed.
// User data bus width = 4 x DQs data width.
// 4: memc core speed 1/4 of memory clock speed.
// User data bus width = 8 x DQs data width.
parameter MEM_TYPE = "DDR3",
parameter TCQ = 100,
parameter BL_WIDTH = 6, // USER_Interface Command Burst Length
parameter FAMILY = "SPARTAN6",
parameter EYE_TEST = "FALSE",
parameter ADDR_WIDTH = 32,
parameter MEM_BURST_LEN = 8,
parameter START_ADDR = 32'h00000000,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 72,
parameter COLUMN_WIDTH = 10,
parameter SEL_VICTIM_LINE = 3 // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
// parameter [287:0] ALL_1 = {288{1'b1}},
// parameter [287:0] ALL_0 = {288{1'b0}}
)
(
input clk_i, //
input rst_i,
input [31:0] prbs_fseed_i,
input mode_load_i,
input mem_init_done_i,
input wr_data_mask_gen_i,
input [3:0] data_mode_i, // "00" = bram;
input data_rdy_i,
input cmd_startA,
input cmd_startB,
input cmd_startC,
input cmd_startD,
input cmd_startE,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern.
input [31:0] fixed_data_i,
input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
input [BL_WIDTH:0] user_burst_cnt, // generated burst length for control the burst data
input fifo_rdy_i, // connect from mcb_wr_full when used as wr_data_gen
// connect from mcb_rd_empty when used as rd_data_gen
// When both data_rdy and data_valid is asserted, the ouput data is valid.
// input [(DWIDTH/8)-1:0] wr_mask_count;
output [(NUM_DQ_PINS*nCK_PER_CLK*2/8)-1:0] data_mask_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o , // generated data pattern
output reg [31:0] tg_st_addr_o,
output bram_rd_valid_o
);
//
localparam PRBS_WIDTH = 8;//BL_WIDTH;
localparam TAPS_VALUE = (BL_WIDTH == 8) ? 8'b10001110 :
// (BL_WIDTH == 10) ? 10'b1000000100:
8'b10001110 ;
wire [31:0] prbs_data;
reg [35:0] acounts;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] fdata;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] bdata;
wire [31:0] bram_data;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] adata_tmp;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] adata;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] hammer_data;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w1data;
reg [NUM_DQ_PINS*2-1:0] hdata;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w0data;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data;
reg burst_count_reached2;
reg data_valid;
reg [2:0] walk_cnt;
reg [ADDR_WIDTH-1:0] user_address;
reg [ADDR_WIDTH-1:0] m_addr_r; // generated address used to determine data pattern.
reg sel_w1gen_logic;
//reg [7:0] BLANK;
reg [4*NUM_DQ_PINS -1 :0] sel_victimline_r;
reg data_clk_en,data_clk_en2 /* synthesis syn_maxfan = 10 */;
wire [NUM_DQ_PINS*2*nCK_PER_CLK-1:0] full_prbs_data2;
wire [NUM_DQ_PINS*2*nCK_PER_CLK-1:0] psuedo_prbs_data;
wire [127:0] prbs_shift_value;
reg next_calib_data;
reg [2*nCK_PER_CLK*NUM_DQ_PINS-1:0 ] calib_data;
wire [2*nCK_PER_CLK*NUM_DQ_PINS/8 -1:0] w1data_group;
wire [31:0] mcb_prbs_data;
wire [NUM_DQ_PINS-1:0] prbsdata_rising_0;
wire [NUM_DQ_PINS-1:0] prbsdata_falling_0;
wire [NUM_DQ_PINS-1:0] prbsdata_rising_1;
wire [NUM_DQ_PINS-1:0] prbsdata_falling_1;
wire [NUM_DQ_PINS-1:0] prbsdata_rising_2;
wire [NUM_DQ_PINS-1:0] prbsdata_falling_2;
wire [NUM_DQ_PINS-1:0] prbsdata_rising_3;
wire [NUM_DQ_PINS-1:0] prbsdata_falling_3 ;
wire [BL_WIDTH-1:0] prbs_o0,prbs_o1,prbs_o2,prbs_o3,prbs_o4,prbs_o5,prbs_o6,prbs_o7;
wire [BL_WIDTH-1:0] prbs_o8,prbs_o9,prbs_o10,prbs_o11,prbs_o12,prbs_o13,prbs_o14,prbs_o15;
//wire [nCK_PER_CLK * 32 -1 :0] prbs_shift_value;
wire [32*NUM_DQ_PINS-1:0] ReSeedcounter;
reg [3:0] htstpoint ;
reg data_clk_en2_r;
reg [NUM_DQ_PINS-1:0] wdatamask_ripplecnt;
//wire [4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] ALL_1 =
reg mode_load_r;
reg user_burst_cnt_larger_1_r;
reg user_burst_cnt_larger_bram;
integer i,j,k;
localparam NUM_WIDTH = 2*nCK_PER_CLK*NUM_DQ_PINS;
localparam USER_BUS_DWIDTH = (nCK_PER_CLK == 2) ? NUM_DQ_PINS*4 : NUM_DQ_PINS*8;
// MODIFIED richc 061711
//wire [PRBS_WIDTH-1:0] prbs_seed;
wire [2*nCK_PER_CLK-1:0] prbs_out [NUM_DQ_PINS-1:0];
wire [PRBS_WIDTH-1:0] prbs_seed [NUM_DQ_PINS-1:0];
//*********************************************************************************************
localparam BRAM_DATAL_MODE = 4'b0000;
localparam FIXED_DATA_MODE = 4'b0001;
localparam ADDR_DATA_MODE = 4'b0010;
localparam HAMMER_DATA_MODE = 4'b0011;
localparam NEIGHBOR_DATA_MODE = 4'b0100;
localparam WALKING1_DATA_MODE = 4'b0101;
localparam WALKING0_DATA_MODE = 4'b0110;
localparam PRBS_DATA_MODE = 4'b0111;
assign data_o = data;
generate
if (nCK_PER_CLK == 4)
begin: full_prbs_data64
//always @ (prbsdata_falling_3,prbsdata_rising_3,prbsdata_falling_2,prbsdata_rising_2,prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0)
assign full_prbs_data2 = {prbsdata_falling_3,prbsdata_rising_3,prbsdata_falling_2,prbsdata_rising_2,prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0};
end
else
begin: full_prbs_data32
assign full_prbs_data2 = {prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0};
end
endgenerate
generate
genvar p;
for (p = 0; p < NUM_DQ_PINS*nCK_PER_CLK*2/32; p = p+1)
begin
assign psuedo_prbs_data[p*32+31:p*32] = mcb_prbs_data;
end
endgenerate
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w1data_o;
reg [3:0] data_mode_rr_a;
reg [3:0] data_mode_rr_c;
// write data mask generation.
// Only support data pattern = address data mode.
// When wdatamask_ripple_cnt is asserted, the corresponding wr_data word will be jammed with 8'hff.
assign data_mask_o = (wr_data_mask_gen_i == 1'b1 && mem_init_done_i) ? wdatamask_ripplecnt :{ NUM_DQ_PINS*nCK_PER_CLK*2/8{1'b0}};
always @ (posedge clk_i)
begin
if (rst_i || ~wr_data_mask_gen_i || ~mem_init_done_i)
wdatamask_ripplecnt <= 'b0;
else if (cmd_startA)
//wdatamask_ripplecnt <= {15'd0,1'b1};
wdatamask_ripplecnt <= {{NUM_DQ_PINS-1{1'b0}},1'b1};
else if (user_burst_cnt_larger_1_r && data_rdy_i)
wdatamask_ripplecnt <= {wdatamask_ripplecnt[NUM_DQ_PINS-2:0],wdatamask_ripplecnt[NUM_DQ_PINS-1]};
end
generate
genvar n;
for (n = 0; n < NUM_DQ_PINS*nCK_PER_CLK*2/8; n = n+1)
begin
if (MEM_TYPE == "QDR2PLUS")
assign adata = adata_tmp;// QDR not supporting masking
else
assign adata[n*8+7:n*8] = adata_tmp[n*8+7:n*8]| {8{wdatamask_ripplecnt[NUM_DQ_PINS-1]}};
end
endgenerate
always @ (posedge clk_i)
begin
data_mode_rr_a <= #TCQ data_mode_i;
data_mode_rr_c <= #TCQ data_mode_i;
end
assign bdata = {USER_BUS_DWIDTH/32{bram_data[31:0]}};
// selected data pattern go through "data" mux to user data bus.
// 72 pin 1: failed
always @ (bdata,calib_data,hammer_data,adata,data_mode_rr_a,w1data,full_prbs_data2,psuedo_prbs_data)
begin
case(data_mode_rr_a) //
// Simple Data Pattern for bring up
// 0: Reserved
// 1: 32 bits fixed_data from user defined inputs.
// The data from this static pattern is concatenated together multiple times
// to make up the required number of bits as needed.
// 2: 32 bits address as data
// The data from this pattern is concatenated together multiple times
// to make up the required number of bits as needed.
// 4: simple 8data pattern and repeats every 8 words. The pattern is embedded in RAM.
// 5,6: Walkign 1,0 data.
// a Calibration data pattern
// 0,1,2,3,4,9: use bram to implemnt.
4'b0000,4'b0001,4'b0100,4'b1001: data = bdata;
4'b0010: data = adata; // address as data
4'b0011: data = hammer_data;
4'b0101, 4'b110: data = w1data; // walking 1 or walking 0 data
// when vio_instr_mode_value set to 4'hf,the init_mem_pattern_ctr module
// will automatically set the data_mode_o to 0x8
4'b1010: data =calib_data;
// Characterization Mode
// 2: Address as data
// 3: hammer data with option to select VICTIM line which output is always high.
// 7: Hammer PRBS. Only valid in V6,V7 family
// 9: Slow 2 MHz hammer pattern.
4'b0111: data = full_prbs_data2;//{prbs_data,prbs_data,prbs_data,prbs_data}; // "011" = prbs
4'b1000: data = psuedo_prbs_data;//{prbs_data,prbs_data,prbs_data,prbs_data}; // "011" = prbs
default : begin
// for (i=0; i <= 4*NUM_DQ_PINS - 1; i= i+1) begin: neighbor_data
// data = begin
// for (
data = adata;
end
endcase
end
// phy calibration data pattern
//
generate
if (nCK_PER_CLK == 2)
begin: calib_data32
always @ (posedge clk_i)
if (rst_i) begin
next_calib_data <= 1'b0;
calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}};
end
else if (cmd_startA)
begin
calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}};
next_calib_data <=#TCQ 1'b1;
// calib_data <= 'b0;
end
else if (fifo_rdy_i)
begin
next_calib_data <= #TCQ ~next_calib_data;
if (next_calib_data )
calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h66}},{(NUM_DQ_PINS/8){8'h99}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h55}}};
else
calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}};
end
end
else
begin: calib_data64 // when nCK_PER_LK =4 has not verified
always @ (posedge clk_i)
if (rst_i) begin
next_calib_data <= 1'b0;
calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}};
end
else if (cmd_startA)
begin
calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}};
next_calib_data <=#TCQ 1'b1;
// calib_data <= 'b0;
end
else if (fifo_rdy_i)
begin
next_calib_data <= #TCQ ~next_calib_data;
if (next_calib_data )
calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h6666}},{(NUM_DQ_PINS/8){16'h9999}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h5555}}};
else
calib_data <= #TCQ {{(NUM_DQ_PINS/8){16'h5555}},{(NUM_DQ_PINS/8){16'haaaa}},{(NUM_DQ_PINS/8){16'h0000}},{(NUM_DQ_PINS/8){16'hffff}}};
end
end
endgenerate
/*
always @ (posedge clk_i)
begin calib_data <= 'b0;
end
*/
//**************************************************************************
// Pattern bram generates fixed input, hammer, simple 8 repeat data pattern.
//**************************************************************************
function integer logb2;
input [31:0] number;
integer i;
begin
i = number;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
mig_7series_v4_0_vio_init_pattern_bram #
( .MEM_BURST_LEN (MEM_BURST_LEN),
.START_ADDR (START_ADDR),
.NUM_DQ_PINS (NUM_DQ_PINS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE)
)
vio_init_pattern_bram
(
.clk_i (clk_i ),
.rst_i (rst_i ),
// BL8 : least 3 address bits are always zero.
// BL4 " least 2 address bits are always zero.
// for walking 1's or 0's, the least 8 address bits are always zero.
.cmd_addr (addr_i),
.cmd_start (cmd_startB),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_rr_a),
//.w1data (w1data),
.data0 (simple_data0 ),
.data1 (simple_data1 ),
.data2 (simple_data2 ),
.data3 (simple_data3 ),
.data4 (simple_data4 ),
.data5 (simple_data5 ),
.data6 (simple_data6 ),
.data7 (simple_data7 ),
.data8 (fixed_data_i ),
.bram_rd_valid_o (bram_rd_valid_o),
.bram_rd_rdy_i (user_burst_cnt_larger_bram & (data_rdy_i | cmd_startB)),
.dout_o (bram_data)
);
//**************************************************************
// Functions to be used byg Walking 1 and Walking 0 circuits.
//**************************************************************
function [2*nCK_PER_CLK*NUM_DQ_PINS-1:0] Data_Gen (input integer i );
integer j;
begin
j = i/2;
Data_Gen = {2*nCK_PER_CLK*NUM_DQ_PINS{1'b0}};
if(i %2 == 1) begin
if (nCK_PER_CLK == 2) begin
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000;
end
else begin
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000;
Data_Gen[(4*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;
Data_Gen[(5*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;
Data_Gen[(6*NUM_DQ_PINS+j*8)+:8] = 8'b00000100;
Data_Gen[(7*NUM_DQ_PINS+j*8)+:8] = 8'b00001000;
end
end else begin
if (nCK_PER_CLK == 2) begin
if (MEM_TYPE == "QDR2PLUS") begin
//QDR sends the high order data bit out first to memory.
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00001000;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000100;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;
end else begin
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000;
end
end
else begin
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000;
Data_Gen[(4*NUM_DQ_PINS+j*8)+:8] = 8'b00010000;
Data_Gen[(5*NUM_DQ_PINS+j*8)+:8] = 8'b00100000;
Data_Gen[(6*NUM_DQ_PINS+j*8)+:8] = 8'b01000000;
Data_Gen[(7*NUM_DQ_PINS+j*8)+:8] = 8'b10000000;
end
end
end
endfunction
function [2*nCK_PER_CLK*NUM_DQ_PINS-1:0] Data_GenW0 (input integer i);
integer j;
begin
j = i/2;
Data_GenW0 = {2*nCK_PER_CLK*NUM_DQ_PINS{1'b1}};
if(i %2 == 1) begin
if (nCK_PER_CLK == 2) begin
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111;
end
else begin
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111;
Data_GenW0[(4*NUM_DQ_PINS+j*8)+:8] = 8'b11111110;
Data_GenW0[(5*NUM_DQ_PINS+j*8)+:8] = 8'b11111101;
Data_GenW0[(6*NUM_DQ_PINS+j*8)+:8] = 8'b11111011;
Data_GenW0[(7*NUM_DQ_PINS+j*8)+:8] = 8'b11110111;
end
end else begin
if (nCK_PER_CLK == 2) begin
if (MEM_TYPE == "QDR2PLUS") begin
//QDR sends the high order data bit out first to memory.
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11110111;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111011;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111101;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11111110;
end else begin
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111;
end
end
else begin
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111;
Data_GenW0[(4*NUM_DQ_PINS+j*8)+:8] = 8'b11101111;
Data_GenW0[(5*NUM_DQ_PINS+j*8)+:8] = 8'b11011111;
Data_GenW0[(6*NUM_DQ_PINS+j*8)+:8] = 8'b10111111;
Data_GenW0[(7*NUM_DQ_PINS+j*8)+:8] = 8'b01111111;
end
end
end
endfunction
always @ (posedge clk_i) begin
if (data_mode_rr_c[2:0] == 3'b101 || data_mode_rr_c[2:0] == 3'b100 || data_mode_rr_c[2:0] == 3'b110) // WALKING ONES
sel_w1gen_logic <= #TCQ 1'b1;
else
sel_w1gen_logic <= #TCQ 1'b0;
end
generate
genvar m;
for (m=0; m < (2*nCK_PER_CLK*NUM_DQ_PINS/8) - 1; m= m+1)
begin: w1_gp
assign w1data_group[m] = ( (w1data[(m*8+7):m*8]) != 8'h00);
end
endgenerate
generate
if ((NUM_DQ_PINS == 8 ) &&(DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL"))
begin : WALKING_ONE_8_PATTERN
if (nCK_PER_CLK == 2) begin : WALKING_ONE_8_PATTERN_NCK_2
always @ (posedge clk_i) begin
if( (fifo_rdy_i) || cmd_startC )
if (cmd_startC ) begin
if (sel_w1gen_logic) begin
if (data_mode_i == 4'b0101)
w1data <= #TCQ Data_Gen(32'b0);
else
w1data <= #TCQ Data_GenW0(32'b0);
end
end
else if (fifo_rdy_i) begin
w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]};
w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]};
w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]};
w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]};
end
end // end of always
end // end of nCK_PER_CLK == 2
else
begin: WALKING_ONE_8_PATTERN_NCK_4
always @ (posedge clk_i) begin
if( (fifo_rdy_i) || cmd_startC )
if (cmd_startC ) begin
if (sel_w1gen_logic) begin
if (data_mode_i == 4'b0101)
w1data <= #TCQ Data_Gen(32'b0);
else
w1data <= #TCQ Data_GenW0(32'b0);
end
end
else if (fifo_rdy_i ) begin
w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS] <= #TCQ w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS ];
w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS] <= #TCQ w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS ];
w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS] <= #TCQ w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS ];
w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS] <= #TCQ w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS ];
w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS ];
w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS ];
w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS ];
w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS ];
end
end // end of always
end // end of nCK_PER_CLK == 4
end
else if ((NUM_DQ_PINS != 8 ) &&(DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL"))
begin : WALKING_ONE_64_PATTERN
if (nCK_PER_CLK == 2) begin : WALKING_ONE_64_PATTERN_NCK_2
always @ (posedge clk_i) begin
if( (fifo_rdy_i) || cmd_startC )
if (cmd_startC ) begin
if (sel_w1gen_logic) begin
if (data_mode_i == 4'b0101)
w1data <= #TCQ Data_Gen(32'b0);
else
w1data <= #TCQ Data_GenW0(32'b0);
end
end
else if (fifo_rdy_i) begin
w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]};
w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]};
w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]};
w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]};
end
end // end of always
end //end of nCK_PER_CLK == 2
else
begin: WALKING_ONE_64_PATTERN_NCK_4
always @ (posedge clk_i) begin
if( (fifo_rdy_i) || cmd_startC )
if (cmd_startC ) begin
if (sel_w1gen_logic) begin
if (data_mode_i == 4'b0101)
w1data <= #TCQ Data_Gen(32'b0);
else
w1data <= #TCQ Data_GenW0(32'b0);
end
end
else if (fifo_rdy_i) begin
w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS] <= #TCQ {w1data[8*NUM_DQ_PINS - 9:7*NUM_DQ_PINS ],w1data[8*NUM_DQ_PINS - 1:8*NUM_DQ_PINS - 8]};
w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS] <= #TCQ {w1data[7*NUM_DQ_PINS - 9:6*NUM_DQ_PINS ],w1data[7*NUM_DQ_PINS - 1:7*NUM_DQ_PINS - 8]};
w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS] <= #TCQ {w1data[6*NUM_DQ_PINS - 9:5*NUM_DQ_PINS ],w1data[6*NUM_DQ_PINS - 1:6*NUM_DQ_PINS - 8]};
w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS] <= #TCQ {w1data[5*NUM_DQ_PINS - 9:4*NUM_DQ_PINS ],w1data[5*NUM_DQ_PINS - 1:5*NUM_DQ_PINS - 8]};
w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 9:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 8]};
w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 9:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 8]};
w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 9:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 8]};
w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 9:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 8]};
end
end // end of always
end //end of nCK_PER_CLK == 4
end
else
begin: NO_WALKING_PATTERN
always @ (posedge clk_i)
w1data <= 'b0;
end
endgenerate
// HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine
// the position of the pin driving oppsite polarity
// addr_i[6:2] = 5'h0f ; 32 bit data port
// => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
// Only generate NUM_DQ_PINS width of hdata and will do concatenation in above level.
always @ (posedge clk_i)
begin
for (i= 0; i <= 2*NUM_DQ_PINS - 1; i= i+1) //begin: hammer_data
if ( i >= NUM_DQ_PINS )
if (SEL_VICTIM_LINE == NUM_DQ_PINS)
hdata[i] <= 1'b0;
else if (
((i == SEL_VICTIM_LINE-1) ||
(i-NUM_DQ_PINS) == SEL_VICTIM_LINE ))//||
hdata[i] <= 1'b1;
else
hdata[i] <= 1'b0;
else
hdata[i] <= 1'b1;
end
generate
if (nCK_PER_CLK == 2)
begin : HAMMER_2
assign hammer_data = {2{hdata[2*NUM_DQ_PINS - 1:0]}};
end
else
begin : HAMMER_4
assign hammer_data = {4{hdata[2*NUM_DQ_PINS - 1:0]}};
end
endgenerate
// ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
// Dataport 32 bit width with starting addr_i = 32'h12345678, burst length 8
// => the 1st data pattern : 32'h12345680
// => the 2nd data pattern : 32'h12345688
// => the 3rd data pattern : 32'h12345690
// => the 4th data pattern : 32'h12345698
generate
reg COut_a;
if (DATA_PATTERN == "DGEN_ADDR" || DATA_PATTERN == "DGEN_ALL")
begin : ADDRESS_PATTERN
always @ (posedge clk_i)
begin
if (cmd_startD)
/// 35:0
acounts <= #TCQ {4'b0000,addr_i} ;
else if (user_burst_cnt_larger_1_r && data_rdy_i ) begin
if (nCK_PER_CLK == 2)
if (FAMILY == "VIRTEX6")
if (MEM_TYPE == "QDR2PLUS")
{COut_a,acounts} <= #TCQ acounts + 1;
else
{COut_a,acounts} <= #TCQ acounts + 4;
else begin // "SPARTAN6"
if (DWIDTH == 32)
{COut_a,acounts} <= #TCQ acounts + 4;
else if (DWIDTH == 64)
{COut_a,acounts} <= #TCQ acounts + 8;
else if (DWIDTH == 64)
{COut_a,acounts} <= #TCQ acounts + 16;
end
else
{COut_a,acounts} <= #TCQ acounts + 8;
end
else
acounts <= #TCQ acounts;
end
assign adata_tmp = {USER_BUS_DWIDTH/32{acounts[31:0]}};
end
else
begin: NO_ADDRESS_PATTERN
assign adata_tmp = 'b0;
end
endgenerate
always @ (posedge clk_i)
begin
if (cmd_startD)
tg_st_addr_o <= addr_i;
end
// PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
// Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
//
// this user_burst_cnt_larger_bram is used by vio_init_pattern_bram module
// only
always @ (posedge clk_i)
if (user_burst_cnt > 6'd1 || cmd_startE)
user_burst_cnt_larger_bram <= 1'b1;
else
user_burst_cnt_larger_bram <= 1'b0;
generate
if (DMODE == "WRITE")
begin: wr_ubr
always @ (posedge clk_i)
if (user_burst_cnt > 6'd1 || cmd_startE)
user_burst_cnt_larger_1_r <= 1'b1;
else
user_burst_cnt_larger_1_r <= 1'b0;
end
else
begin: rd_ubr
always @ (posedge clk_i)
if (user_burst_cnt >= 6'd1 || cmd_startE)
user_burst_cnt_larger_1_r <= 1'b1;
else if (ReSeedcounter[31:0] == 255)
user_burst_cnt_larger_1_r <= 1'b0;
end
endgenerate
generate
// When doing eye_test, traffic gen only does write and want to
// keep the prbs random and address is fixed at a location.
if (EYE_TEST == "TRUE")
begin : d_clk_en1
always @(data_clk_en)
data_clk_en = 1'b1;//fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end
else if (DMODE == "WRITE")
begin: wr_dataclken
always @ (data_rdy_i , user_burst_cnt_larger_1_r,ReSeedcounter[31:0])
begin
if ( data_rdy_i && (user_burst_cnt_larger_1_r || ReSeedcounter[31:0] == 255 ))
data_clk_en = 1'b1;
else
data_clk_en = 1'b0;
end
always @ (data_rdy_i , user_burst_cnt_larger_1_r,ReSeedcounter)
begin
if ( data_rdy_i && (user_burst_cnt_larger_1_r || ReSeedcounter[31:0] == 255 ))
data_clk_en2 = 1'b1;
else
data_clk_en2 = 1'b0;
end
end else // (DMODE == "READ")
begin: rd_dataclken
always @ (fifo_rdy_i, data_rdy_i , user_burst_cnt_larger_1_r)
begin
if (fifo_rdy_i && data_rdy_i && user_burst_cnt_larger_1_r )
data_clk_en <= 1'b1;
else
data_clk_en <= 1'b0;
end
always @ (fifo_rdy_i, data_rdy_i , user_burst_cnt_larger_1_r)
begin
if (fifo_rdy_i && data_rdy_i && user_burst_cnt_larger_1_r )
data_clk_en2 <= 1'b1;
else
data_clk_en2 <= 1'b0;
end
end
endgenerate
generate
if (DATA_PATTERN == "DGEN_PRBS" || DATA_PATTERN == "DGEN_ALL")
begin : PSUEDO_PRBS_PATTERN
// PRBS DATA GENERATION
// xor all the tap positions before feedback to 1st stage.
always @ (posedge clk_i)
m_addr_r <= m_addr_i;
mig_7series_v4_0_data_prbs_gen #
(
.PRBS_WIDTH (32),
.SEED_WIDTH (32),
.EYE_TEST (EYE_TEST)
)
data_prbs_gen
(
.clk_i (clk_i),
.rst_i (rst_i),
.clk_en (data_clk_en),
.prbs_seed_init (cmd_startE),
.prbs_seed_i (m_addr_i[31:0]),
.prbs_o (mcb_prbs_data)
);
end
else
begin:NO_PSUEDO_PRBS_PATTERN
assign mcb_prbs_data = 'b0;
end
endgenerate
//***************************************************************************
// "Full pseudo-PRBS" data generation
//***************************************************************************
genvar r;
// Assign initial seed (used for 1st data bit); use alternating 1/0 pat
assign prbs_seed[0] = {(PRBS_WIDTH/2){2'b10}};
// Generate seeds for all other data bits, each one is staggered in time
// by one LFSR shift from the preceeding bit
generate
if (PRBS_WIDTH == 8) begin: gen_seed_prbs8
for (r = 1; r < NUM_DQ_PINS; r = r + 1) begin: gen_loop_seed_prbs
// PRBS 8 - feedback uses taps [7,5,4,3]
assign prbs_seed[r] = {prbs_seed[r-1][PRBS_WIDTH-2:0],
~(prbs_seed[r-1][7] ^ prbs_seed[r-1][5] ^
prbs_seed[r-1][4] ^ prbs_seed[r-1][3])};
end
end else if (PRBS_WIDTH == 10) begin: gen_next_lfsr_prbs10
// PRBS 10 - feedback uses taps [9,6]
for (r = 1; r < NUM_DQ_PINS; r = r + 1) begin: gen_loop_seed_prbs
assign prbs_seed[r] = {prbs_seed[r-1][PRBS_WIDTH-2:0],
~(prbs_seed[r-1][9] ^ prbs_seed[r-1][6])};
end
end
endgenerate
// Instantiate one PRBS per data bit. Note this is only temporary -
// eventually it will be far more efficient to use a large shift register
// that is initialized with 2*CK_PER_CLK*NUM_DQ_PINS worth of LFSR cycles
// rather than individual PRBS generators. For now this is done because
// not sure if current logic allows for the initial delay required to fill
// this large shift register
generate
for (r = 0; r < NUM_DQ_PINS; r = r + 1) begin: gen_prbs_modules
mig_7series_v4_0_tg_prbs_gen #
(.nCK_PER_CLK (nCK_PER_CLK),
.TCQ (TCQ),
.PRBS_WIDTH (PRBS_WIDTH)
)
u_data_prbs_gen
(
.clk_i (clk_i),
.rst_i (rst_i),
.clk_en_i (data_clk_en),
.prbs_seed_i (prbs_seed[r]),
.prbs_o (prbs_out[r]),
.ReSeedcounter_o (ReSeedcounter[32*r+:32])
);
end
endgenerate
generate
for (r = 0; r < NUM_DQ_PINS; r = r + 1) begin: gen_prbs_rise_fall_data
if (nCK_PER_CLK == 2) begin: gen_ck_per_clk2
assign prbsdata_rising_0[r] = prbs_out[r][0];
assign prbsdata_falling_0[r] = prbs_out[r][1];
assign prbsdata_rising_1[r] = prbs_out[r][2];
assign prbsdata_falling_1[r] = prbs_out[r][3];
end else if (nCK_PER_CLK == 4) begin: gen_ck_per_clk4
assign prbsdata_rising_0[r] = prbs_out[r][0];
assign prbsdata_falling_0[r] = prbs_out[r][1];
assign prbsdata_rising_1[r] = prbs_out[r][2];
assign prbsdata_falling_1[r] = prbs_out[r][3];
assign prbsdata_rising_2[r] = prbs_out[r][4];
assign prbsdata_falling_2[r] = prbs_out[r][5];
assign prbsdata_rising_3[r] = prbs_out[r][6];
assign prbsdata_falling_3[r] = prbs_out[r][7];
end
end
endgenerate
//***************************************************************************
//***debug PRBS in ddr3 hware
//assign dbg_prbs_tpts[15:0] = {prbs_shift_value3 ,prbs_shift_value2,prbs_shift_value1,prbs_shift_value0};
//assign dbg_prbs_tpts[21:16] = prbs_mux_counter[5:0];
//assign dbg_prbs_tpts[22] = data_clk_en2;
//assign dbg_prbs_tpts[23] = mode_load_r1 ;
//assign dbg_prbs_tpts[24] = mode_has_loaded;
//fifo_rdy_i && data_rdy_i
//assign dbg_prbs_tpts[25] = data_rdy_i;
//assign dbg_prbs_tpts[26] = fifo_rdy_i;
//assign dbg_prbs_tpts[31:27] = 'b0;
//assign dbg_prbs_tpts[63:32] = ReSeedcounter[31:0];
//assign dbg_prbs_tpts[64+:10] = user_burst_cnt[9:0];
//assign dbg_prbs_tpts[74] = user_burst_cnt_larger_1_r;
//assign dbg_prbs_tpts[127:75] = 'b0;
endmodule
|
`timescale 1ns/10ps
module soc_system_pll_0(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(2),
.output_clock_frequency0("100.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("100.000000 MHz"),
.phase_shift1("-3750 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/12.1sp1/ip/avalon_st/altera_avalon_st_handshake_clock_crosser/altera_avalon_st_handshake_clock_crosser.v $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
//------------------------------------------------------------------------------
// Clock crosser module with handshaking mechanism
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_handshake_clock_crosser
#(
parameter DATA_WIDTH = 8,
BITS_PER_SYMBOL = 8,
USE_PACKETS = 0,
// ------------------------------
// Optional signal widths
// ------------------------------
USE_CHANNEL = 0,
CHANNEL_WIDTH = 1,
USE_ERROR = 0,
ERROR_WIDTH = 1,
VALID_SYNC_DEPTH = 2,
READY_SYNC_DEPTH = 2,
USE_OUTPUT_PIPELINE = 1,
// ------------------------------
// Derived parameters
// ------------------------------
SYMBOLS_PER_BEAT = DATA_WIDTH / BITS_PER_SYMBOL,
EMPTY_WIDTH = log2ceil(SYMBOLS_PER_BEAT)
)
(
input in_clk,
input in_reset,
input out_clk,
input out_reset,
output in_ready,
input in_valid,
input [DATA_WIDTH - 1 : 0] in_data,
input [CHANNEL_WIDTH - 1 : 0] in_channel,
input [ERROR_WIDTH - 1 : 0] in_error,
input in_startofpacket,
input in_endofpacket,
input [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] in_empty,
input out_ready,
output out_valid,
output [DATA_WIDTH - 1 : 0] out_data,
output [CHANNEL_WIDTH - 1 : 0] out_channel,
output [ERROR_WIDTH - 1 : 0] out_error,
output out_startofpacket,
output out_endofpacket,
output [(EMPTY_WIDTH ? (EMPTY_WIDTH - 1) : 0) : 0] out_empty
);
// ------------------------------
// Payload-specific widths
// ------------------------------
localparam PACKET_WIDTH = (USE_PACKETS) ? 2 + EMPTY_WIDTH : 0;
localparam PCHANNEL_W = (USE_CHANNEL) ? CHANNEL_WIDTH : 0;
localparam PERROR_W = (USE_ERROR) ? ERROR_WIDTH : 0;
localparam PAYLOAD_WIDTH = DATA_WIDTH +
PACKET_WIDTH +
PCHANNEL_W +
EMPTY_WIDTH +
PERROR_W;
wire [PAYLOAD_WIDTH - 1: 0] in_payload;
wire [PAYLOAD_WIDTH - 1: 0] out_payload;
// ------------------------------
// Assign in_data and other optional sink interface
// signals to in_payload.
// ------------------------------
assign in_payload[DATA_WIDTH - 1 : 0] = in_data;
generate
// optional packet inputs
if (PACKET_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH - 1 :
DATA_WIDTH
] = {in_startofpacket, in_endofpacket};
end
// optional channel input
if (USE_CHANNEL) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
] = in_channel;
end
// optional empty input
if (EMPTY_WIDTH) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
] = in_empty;
end
// optional error input
if (USE_ERROR) begin
assign in_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
] = in_error;
end
endgenerate
// --------------------------------------------------
// Pipe the input payload to our inner module which handles the
// actual clock crossing
// --------------------------------------------------
altera_avalon_st_clock_crosser
#(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (PAYLOAD_WIDTH),
.FORWARD_SYNC_DEPTH (VALID_SYNC_DEPTH),
.BACKWARD_SYNC_DEPTH (READY_SYNC_DEPTH),
.USE_OUTPUT_PIPELINE (USE_OUTPUT_PIPELINE)
) clock_xer (
.in_clk (in_clk ),
.in_reset (in_reset ),
.in_ready (in_ready ),
.in_valid (in_valid ),
.in_data (in_payload ),
.out_clk (out_clk ),
.out_reset (out_reset ),
.out_ready (out_ready ),
.out_valid (out_valid ),
.out_data (out_payload )
);
// --------------------------------------------------
// Split out_payload into the output signals.
// --------------------------------------------------
assign out_data = out_payload[DATA_WIDTH - 1 : 0];
generate
// optional packet outputs
if (USE_PACKETS) begin
assign {out_startofpacket, out_endofpacket} =
out_payload[DATA_WIDTH + PACKET_WIDTH - 1 : DATA_WIDTH];
end else begin
// avoid a "has no driver" warning.
assign {out_startofpacket, out_endofpacket} = 2'b0;
end
// optional channel output
if (USE_CHANNEL) begin
assign out_channel = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W - 1 :
DATA_WIDTH + PACKET_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_channel = 1'b0;
end
// optional empty output
if (EMPTY_WIDTH) begin
assign out_empty = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W
];
end else begin
// avoid a "has no driver" warning.
assign out_empty = 1'b0;
end
// optional error output
if (USE_ERROR) begin
assign out_error = out_payload[
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH + PERROR_W - 1 :
DATA_WIDTH + PACKET_WIDTH + PCHANNEL_W + EMPTY_WIDTH
];
end else begin
// avoid a "has no driver" warning.
assign out_error = 1'b0;
end
endgenerate
// --------------------------------------------------
// Calculates the log2ceil of the input value.
// --------------------------------------------------
function integer log2ceil;
input integer val;
integer i;
begin
i = 1;
log2ceil = 0;
while (i < val) begin
log2ceil = log2ceil + 1;
i = i << 1;
end
end
endfunction
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_BEHAVIORAL_PP_V |
// The IEEE standard allows the out-of-bounds part-selects to be flagged as
// compile-time errors. If they are not, this test should pass.
module top;
wire [3:0][3:0] array1;
wire [3:0][3:0] array2;
wire [3:0][3:0] array3;
wire [3:0][3:0] array4;
wire [3:0][3:0] array5;
wire [3:0][3:0] array6;
assign array1[-2+:2] = 8'h00;
assign array1[ 0+:2] = 8'h21;
assign array1[ 2+:2] = 8'h43;
assign array1[ 4+:2] = 8'h55;
assign array1[-1+:2] = 8'h10;
assign array2[ 1+:2] = 8'h32;
assign array2[ 3+:2] = 8'h54;
assign array3[-1-:2] = 8'h00;
assign array3[ 1-:2] = 8'h21;
assign array3[ 3-:2] = 8'h43;
assign array3[ 5-:2] = 8'h55;
assign array4[ 0-:2] = 8'h10;
assign array4[ 2-:2] = 8'h32;
assign array4[ 4-:2] = 8'h54;
assign array5[-1:-2] = 8'h00;
assign array5[ 1:0 ] = 8'h21;
assign array5[ 3:2 ] = 8'h43;
assign array5[ 5:4 ] = 8'h55;
assign array6[ 0:-1] = 8'h10;
assign array6[ 2:1 ] = 8'h32;
assign array6[ 4:3 ] = 8'h54;
reg failed = 0;
initial begin
$display("%h", array1);
if (array1 !== 16'h4321) failed = 1;
$display("%h", array2);
if (array2 !== 16'h4321) failed = 1;
$display("%h", array3);
if (array3 !== 16'h4321) failed = 1;
$display("%h", array4);
if (array4 !== 16'h4321) failed = 1;
$display("%h", array5);
if (array5 !== 16'h4321) failed = 1;
$display("%h", array6);
if (array6 !== 16'h4321) failed = 1;
if (failed)
$display("FAILED");
else
$display("PASSED");
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_axi_basic_tx_pipeline.v
// Version : 1.3
// //
// Description: //
// AXI to TRN TX pipeline. Converts transmitted data from AXI protocol to //
// TRN. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// axi_basic_tx_pipeline //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_3_axi_basic_tx_pipeline #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
output trn_tecrc_gen, // TX ECRC generate
input trn_lnk_up, // PCIe link up
// System
//-----------
input tready_thrtl, // TREADY from thrtl ctl
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Input register stage
reg [C_DATA_WIDTH-1:0] reg_tdata;
reg reg_tvalid;
reg [KEEP_WIDTH-1:0] reg_tkeep;
reg [3:0] reg_tuser;
reg reg_tlast;
reg reg_tready;
// Pipeline utility signals
reg trn_in_packet;
reg axi_in_packet;
reg flush_axi;
wire disable_trn;
reg reg_disable_trn;
wire axi_beat_live = s_axis_tx_tvalid && s_axis_tx_tready;
wire axi_end_packet = axi_beat_live && s_axis_tx_tlast;
//----------------------------------------------------------------------------//
// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN. //
// 128-bit: 64-bit: 32-bit: //
// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0 //
// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0 //
// TRN DW2 maps to AXI DW1 //
// TRN DW3 maps to AXI DW0 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : td_DW_swap_128
assign trn_td = {reg_tdata[31:0],
reg_tdata[63:32],
reg_tdata[95:64],
reg_tdata[127:96]};
end
else if(C_DATA_WIDTH == 64) begin : td_DW_swap_64
assign trn_td = {reg_tdata[31:0], reg_tdata[63:32]};
end
else begin : td_DW_swap_32
assign trn_td = reg_tdata;
end
endgenerate
//----------------------------------------------------------------------------//
// Create trn_tsof. If we're not currently in a packet and TVALID goes high, //
// assert TSOF. //
//----------------------------------------------------------------------------//
assign trn_tsof = reg_tvalid && !trn_in_packet;
//----------------------------------------------------------------------------//
// Create trn_in_packet. This signal tracks if the TRN interface is currently //
// in the middle of a packet, which is needed to generate trn_tsof //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_in_packet <= #TCQ 1'b0;
end
else begin
if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof) begin
trn_in_packet <= #TCQ 1'b1;
end
else if((trn_in_packet && trn_teof && trn_tsrc_rdy) || !trn_lnk_up) begin
trn_in_packet <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create axi_in_packet. This signal tracks if the AXI interface is currently //
// in the middle of a packet, which is needed in case the link goes down. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
axi_in_packet <= #TCQ 1'b0;
end
else begin
if(axi_beat_live && !s_axis_tx_tlast) begin
axi_in_packet <= #TCQ 1'b1;
end
else if(axi_beat_live) begin
axi_in_packet <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create disable_trn. This signal asserts when the link goes down and //
// triggers the deassertiong of trn_tsrc_rdy. The deassertion of disable_trn //
// depends on C_PM_PRIORITY, as described below. //
//----------------------------------------------------------------------------//
generate
// In the C_PM_PRIORITY pipeline, we disable the TRN interfacefrom the time
// the link goes down until the the AXI interface is ready to accept packets
// again (via assertion of TREADY). By waiting for TREADY, we allow the
// previous value buffer to fill, so we're ready for any throttling by the
// user or the block.
if(C_PM_PRIORITY == "TRUE") begin : pm_priority_trn_flush
always @(posedge user_clk) begin
if(user_rst) begin
reg_disable_trn <= #TCQ 1'b1;
end
else begin
// When the link goes down, disable the TRN interface.
if(!trn_lnk_up)
begin
reg_disable_trn <= #TCQ 1'b1;
end
// When the link comes back up and the AXI interface is ready, we can
// release the pipeline and return to normal operation.
else if(!flush_axi && s_axis_tx_tready) begin
reg_disable_trn <= #TCQ 1'b0;
end
end
end
assign disable_trn = reg_disable_trn;
end
// In the throttle-controlled pipeline, we don't have a previous value buffer.
// The throttle control mechanism handles TREADY, so all we need to do is
// detect when the link goes down and disable the TRN interface until the link
// comes back up and the AXI interface is finished flushing any packets.
else begin : thrtl_ctl_trn_flush
always @(posedge user_clk) begin
if(user_rst) begin
reg_disable_trn <= #TCQ 1'b0;
end
else begin
// If the link is down and AXI is in packet, disable TRN and look for
// the end of the packet
if(axi_in_packet && !trn_lnk_up && !axi_end_packet)
begin
reg_disable_trn <= #TCQ 1'b1;
end
// AXI packet is ending, so we're done flushing
else if(axi_end_packet) begin
reg_disable_trn <= #TCQ 1'b0;
end
end
end
// Disable the TRN interface if link is down or we're still flushing the AXI
// interface.
assign disable_trn = reg_disable_trn || !trn_lnk_up;
end
endgenerate
//----------------------------------------------------------------------------//
// Convert STRB to RREM. Here, we are converting the encoding method for the //
// location of the EOF from AXI (tkeep) to TRN flavor (rrem). //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : tkeep_to_trem_128
//---------------------------------------//
// Conversion table: //
// trem | tkeep //
// [1] [0] | [15:12] [11:8] [7:4] [3:0] //
// ------------------------------------- //
// 1 1 | D3 D2 D1 D0 //
// 1 0 | -- D2 D1 D0 //
// 0 1 | -- -- D1 D0 //
// 0 0 | -- -- -- D0 //
//---------------------------------------//
wire axi_DW_1 = reg_tkeep[7];
wire axi_DW_2 = reg_tkeep[11];
wire axi_DW_3 = reg_tkeep[15];
assign trn_trem[1] = axi_DW_2;
assign trn_trem[0] = axi_DW_3 || (axi_DW_1 && !axi_DW_2);
end
else if(C_DATA_WIDTH == 64) begin : tkeep_to_trem_64
assign trn_trem = reg_tkeep[7];
end
else begin : tkeep_to_trem_32
assign trn_trem = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------//
// Create remaining TRN signals //
//----------------------------------------------------------------------------//
assign trn_teof = reg_tlast;
assign trn_tecrc_gen = reg_tuser[0];
assign trn_terrfwd = reg_tuser[1];
assign trn_tstr = reg_tuser[2];
assign trn_tsrc_dsc = reg_tuser[3];
//----------------------------------------------------------------------------//
// Pipeline stage //
//----------------------------------------------------------------------------//
// We need one of two approaches for the pipeline stage depending on the
// C_PM_PRIORITY parameter.
generate
reg reg_tsrc_rdy;
// If set to FALSE, that means the user wants to use the TX packet boundary
// throttling feature. Since all Block throttling will now be predicted, we
// can use a simple straight-through pipeline.
if(C_PM_PRIORITY == "FALSE") begin : throttle_ctl_pipeline
always @(posedge user_clk) begin
if(user_rst) begin
reg_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
reg_tvalid <= #TCQ 1'b0;
reg_tkeep <= #TCQ {KEEP_WIDTH{1'b0}};
reg_tlast <= #TCQ 1'b0;
reg_tuser <= #TCQ 4'h0;
reg_tsrc_rdy <= #TCQ 1'b0;
end
else begin
reg_tdata <= #TCQ s_axis_tx_tdata;
reg_tvalid <= #TCQ s_axis_tx_tvalid;
reg_tkeep <= #TCQ s_axis_tx_tkeep;
reg_tlast <= #TCQ s_axis_tx_tlast;
reg_tuser <= #TCQ s_axis_tx_tuser;
// Hold trn_tsrc_rdy low when flushing a packet.
reg_tsrc_rdy <= #TCQ axi_beat_live && !disable_trn;
end
end
assign trn_tsrc_rdy = reg_tsrc_rdy;
// With TX packet boundary throttling, TREADY is pipelined in
// axi_basic_tx_thrtl_ctl and wired through here.
assign s_axis_tx_tready = tready_thrtl;
end
//**************************************************************************//
// If C_PM_PRIORITY is set to TRUE, that means the user prefers to have all PM
// functionality intact isntead of TX packet boundary throttling. Now the
// Block could back-pressure at any time, which creates the standard problem
// of potential data loss due to the handshaking latency. Here we need a
// previous value buffer, just like the RX data path.
else begin : pm_prioity_pipeline
reg [C_DATA_WIDTH-1:0] tdata_prev;
reg tvalid_prev;
reg [KEEP_WIDTH-1:0] tkeep_prev;
reg tlast_prev;
reg [3:0] tuser_prev;
reg reg_tdst_rdy;
wire data_hold;
reg data_prev;
//------------------------------------------------------------------------//
// Previous value buffer //
// --------------------- //
// We are inserting a pipeline stage in between AXI and TRN, which causes //
// some issues with handshaking signals trn_tsrc_rdy/s_axis_tx_tready. //
// The added cycle of latency in the path causes the Block to fall behind //
// the AXI interface whenever it throttles. //
// //
// To avoid loss of data, we must keep the previous value of all //
// s_axis_tx_* signals in case the Block throttles. //
//------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
tdata_prev <= #TCQ {C_DATA_WIDTH{1'b0}};
tvalid_prev <= #TCQ 1'b0;
tkeep_prev <= #TCQ {KEEP_WIDTH{1'b0}};
tlast_prev <= #TCQ 1'b0;
tuser_prev <= #TCQ 4'h 0;
end
else begin
// prev buffer works by checking s_axis_tx_tready. When
// s_axis_tx_tready is asserted, a new value is present on the
// interface.
if(!s_axis_tx_tready) begin
tdata_prev <= #TCQ tdata_prev;
tvalid_prev <= #TCQ tvalid_prev;
tkeep_prev <= #TCQ tkeep_prev;
tlast_prev <= #TCQ tlast_prev;
tuser_prev <= #TCQ tuser_prev;
end
else begin
tdata_prev <= #TCQ s_axis_tx_tdata;
tvalid_prev <= #TCQ s_axis_tx_tvalid;
tkeep_prev <= #TCQ s_axis_tx_tkeep;
tlast_prev <= #TCQ s_axis_tx_tlast;
tuser_prev <= #TCQ s_axis_tx_tuser;
end
end
end
// Create special buffer which locks in the proper value of TDATA depending
// on whether the user is throttling or not. This buffer has three states:
//
// HOLD state: TDATA maintains its current value
// - the Block has throttled the PCIe block
// PREVIOUS state: the buffer provides the previous value on TDATA
// - the Block has finished throttling, and is a little
// behind the user
// CURRENT state: the buffer passes the current value on TDATA
// - the Block is caught up and ready to receive the
// latest data from the user
always @(posedge user_clk) begin
if(user_rst) begin
reg_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
reg_tvalid <= #TCQ 1'b0;
reg_tkeep <= #TCQ {KEEP_WIDTH{1'b0}};
reg_tlast <= #TCQ 1'b0;
reg_tuser <= #TCQ 4'h0;
reg_tdst_rdy <= #TCQ 1'b0;
end
else begin
reg_tdst_rdy <= #TCQ trn_tdst_rdy;
if(!data_hold) begin
// PREVIOUS state
if(data_prev) begin
reg_tdata <= #TCQ tdata_prev;
reg_tvalid <= #TCQ tvalid_prev;
reg_tkeep <= #TCQ tkeep_prev;
reg_tlast <= #TCQ tlast_prev;
reg_tuser <= #TCQ tuser_prev;
end
// CURRENT state
else begin
reg_tdata <= #TCQ s_axis_tx_tdata;
reg_tvalid <= #TCQ s_axis_tx_tvalid;
reg_tkeep <= #TCQ s_axis_tx_tkeep;
reg_tlast <= #TCQ s_axis_tx_tlast;
reg_tuser <= #TCQ s_axis_tx_tuser;
end
end
// else HOLD state
end
end
// Logic to instruct pipeline to hold its value
assign data_hold = trn_tsrc_rdy && !trn_tdst_rdy;
// Logic to instruct pipeline to use previous bus values. Always use
// previous value after holding a value.
always @(posedge user_clk) begin
if(user_rst) begin
data_prev <= #TCQ 1'b0;
end
else begin
data_prev <= #TCQ data_hold;
end
end
//------------------------------------------------------------------------//
// Create trn_tsrc_rdy. If we're flushing the TRN hold trn_tsrc_rdy low. //
//------------------------------------------------------------------------//
assign trn_tsrc_rdy = reg_tvalid && !disable_trn;
//------------------------------------------------------------------------//
// Create TREADY //
//------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
reg_tready <= #TCQ 1'b0;
end
else begin
// If the link went down and we need to flush a packet in flight, hold
// TREADY high
if(flush_axi && !axi_end_packet) begin
reg_tready <= #TCQ 1'b1;
end
// If the link is up, TREADY is as follows:
// TREADY = 1 when trn_tsrc_rdy == 0
// - While idle, keep the pipeline primed and ready for the next
// packet
//
// TREADY = trn_tdst_rdy when trn_tsrc_rdy == 1
// - While in packet, throttle pipeline based on state of TRN
else if(trn_lnk_up) begin
reg_tready <= #TCQ trn_tdst_rdy || !trn_tsrc_rdy;
end
// If the link is down and we're not flushing a packet, hold TREADY low
// wait for link to come back up
else begin
reg_tready <= #TCQ 1'b0;
end
end
end
assign s_axis_tx_tready = reg_tready;
end
//--------------------------------------------------------------------------//
// Create flush_axi. This signal detects if the link goes down while the //
// AXI interface is in packet. In this situation, we need to flush the //
// packet through the AXI interface and discard it. //
//--------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
flush_axi <= #TCQ 1'b0;
end
else begin
// If the AXI interface is in packet and the link goes down, purge it.
if(axi_in_packet && !trn_lnk_up && !axi_end_packet) begin
flush_axi <= #TCQ 1'b1;
end
// The packet is finished, so we're done flushing.
else if(axi_end_packet) begin
flush_axi <= #TCQ 1'b0;
end
end
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:43:44 11/18/2013
// Design Name:
// Module Name: text_editor_keyboard_controller
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module text_editor_keyboard_controller(
input sys_Clk,
input PS2_Clk,
input Reset,
inout PS2KeyboardData,
inout PS2KeyboardClk,
output reg [7:0] KeyData,
output reg KeyReleased
);
/************************************************************************
* LOCAL SIGNALS *
************************************************************************/
reg [1:0] state;
localparam
I = 2'b00,
BAT = 2'b01,
DATA = 2'b10,
UNK = 2'bXX;
wire [7:0] received_data;
wire received_data_en;
reg [7:0] previous_word;
reg send_command;
reg [7:0] the_command;
wire command_sent;
/************************************************************************
* PS2 KEYBOARD *
************************************************************************/
PS2_Controller PS2_Keyboard_Controller(
// Inputs
.CLOCK_50(PS2_Clk),
.reset(Reset),
.the_command(the_command),
.send_command(send_command),
// Bidirectionals
.PS2_CLK(PS2KeyboardClk), // PS2 Clock
.PS2_DAT(PS2KeyboardData), // PS2 Data
// Outputs
.command_was_sent(command_sent),
.error_communication_timed_out( ),
.received_data(received_data),
.received_data_en(received_data_en) // If 1 - new data has been received
);
/************************************************************************
* STATE MACHINE *
************************************************************************/
always @ (posedge sys_Clk, posedge Reset) begin: STATE_MACHINE
if(Reset) begin
state <= I;
previous_word <= 8'hXX;
send_command <= 1'bX;
the_command <= 8'hXX;
KeyData <= 8'hXX;
end else
case(state)
I: begin
state <= BAT;
KeyData <= 8'h00;
previous_word <= 8'h00;
KeyReleased <= 1'b0;
send_command <= 1'b1;
the_command <= 8'hFF; // RESET KEYBOARD
end
BAT: begin
if (command_sent) begin
send_command <= 1'b0;
end
case (received_data)
8'hAA: begin // SUCCESSFUL POST
state <= DATA;
end
8'hFC: begin
send_command <= 1'b1; // TRY TO POST AGAIN
end
default: begin
end
endcase
end
DATA: begin
if (command_sent) begin
send_command <= 1'b0;
end
if (KeyReleased) begin
KeyReleased <= 1'b0;
end
if (received_data_en) begin
previous_word <= received_data;
case(received_data)
8'hF0: begin
// Key Released
end
8'hFA: begin
// Acknowledge
end
8'hAA: begin
// Self Test Passed
end
8'hEE: begin
// Echo Response
end
8'hFE: begin
// Resend Request
end
8'h00: begin
// Error
end
8'hFF: begin
// Error
end
8'h12: begin
// Shift
end
8'h59: begin
// Shift
end
8'h58: begin
// Caps
end
8'h0D: begin
// Tab
end
8'h14: begin
// Ctrl
end
8'h11: begin
// Alt
end
8'hE0: begin
// Extra
end
8'h5A: begin
// Enter
end
default: begin
if (previous_word == 8'hF0) begin // IF PREV WORD WAS KEY RELEASED SCAN CODE
KeyData <= received_data;
KeyReleased <= 1'b1;
end
end
endcase
end
end
default:
state <= UNK;
endcase
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_app_7x.v
// Version : 1.3
//--
//-- Description: PCI Express Endpoint sample application
//-- design.
//--
//------------------------------------------------------------------------------
`timescale 1ps / 1ps
`define PCI_EXP_EP_OUI 24'h000A35
`define PCI_EXP_EP_DSN_1 {{8'h1},`PCI_EXP_EP_OUI}
`define PCI_EXP_EP_DSN_2 32'h00000001
module pcie_app_7x#(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width
parameter TCQ = 1
)(
input user_clk,
input user_reset,
input user_lnk_up,
// Tx
input [5:0] tx_buf_av,
input tx_cfg_req,
input tx_err_drop,
output tx_cfg_gnt,
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output [3:0] s_axis_tx_tuser,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
// Rx
output rx_np_ok,
output rx_np_req,
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
// Flow Control
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
// CFG
output cfg_err_cor,
output cfg_err_ur,
output cfg_err_ecrc,
output cfg_err_cpl_timeout,
output cfg_err_cpl_unexpect,
output cfg_err_cpl_abort,
output cfg_err_atomic_egress_blocked,
output cfg_err_internal_cor,
output cfg_err_malformed,
output cfg_err_mc_blocked,
output cfg_err_poisoned,
output cfg_err_norecovery,
output cfg_err_acs,
output cfg_err_internal_uncor,
output cfg_pm_halt_aspm_l0s,
output cfg_pm_halt_aspm_l1,
output cfg_pm_force_state_en,
output [1:0] cfg_pm_force_state,
output cfg_err_posted,
output cfg_err_locked,
output [47:0] cfg_err_tlp_cpl_header,
input cfg_err_cpl_rdy,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_turnoff_ok,
input cfg_to_turnoff,
output cfg_trn_pending,
output cfg_pm_wake,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number,
input [15:0] cfg_status,
input [15:0] cfg_command,
input [15:0] cfg_dstatus,
input [15:0] cfg_dcommand,
input [15:0] cfg_lstatus,
input [15:0] cfg_lcommand,
input [15:0] cfg_dcommand2,
input [2:0] cfg_pcie_link_state,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
output [1:0] pl_directed_link_change,
input [5:0] pl_ltssm_state,
output [1:0] pl_directed_link_width,
output pl_directed_link_speed,
output pl_directed_link_auton,
output pl_upstream_prefer_deemph,
input [1:0] pl_sel_lnk_width,
input pl_sel_lnk_rate,
input pl_link_gen2_cap,
input pl_link_partner_gen2_supported,
input [2:0] pl_initial_link_width,
input pl_link_upcfg_cap,
input [1:0] pl_lane_reversal_mode,
input pl_received_hot_rst,
output [127:0] cfg_err_aer_headerlog,
output [4:0] cfg_aer_interrupt_msgnum,
input cfg_err_aer_headerlog_set,
input cfg_aer_ecrc_check_en,
input cfg_aer_ecrc_gen_en,
output [31:0] cfg_mgmt_di,
output [3:0] cfg_mgmt_byte_en,
output [9:0] cfg_mgmt_dwaddr,
output cfg_mgmt_wr_en,
output cfg_mgmt_rd_en,
output cfg_mgmt_wr_readonly,
output [63:0] cfg_dsn
);
//----------------------------------------------------------------------------------------------------------------//
// PCIe Block EP Tieoffs - Example PIO doesn't support the following inputs //
//----------------------------------------------------------------------------------------------------------------//
assign fc_sel = 3'b0;
assign rx_np_ok = 1'b1; // Allow Reception of Non-posted Traffic
assign rx_np_req = 1'b1; // Always request Non-posted Traffic if available
assign s_axis_tx_tuser[0] = 1'b0; // Unused for V6
assign s_axis_tx_tuser[1] = 1'b0; // Error forward packet
assign s_axis_tx_tuser[2] = 1'b0; // Stream packet
assign tx_cfg_gnt = 1'b1; // Always allow transmission of Config traffic within block
assign cfg_err_cor = 1'b0; // Never report Correctable Error
assign cfg_err_ur = 1'b0; // Never report UR
assign cfg_err_ecrc = 1'b0; // Never report ECRC Error
assign cfg_err_cpl_timeout = 1'b0; // Never report Completion Timeout
assign cfg_err_cpl_abort = 1'b0; // Never report Completion Abort
assign cfg_err_cpl_unexpect = 1'b0; // Never report unexpected completion
assign cfg_err_posted = 1'b0; // Never qualify cfg_err_* inputs
assign cfg_err_locked = 1'b0; // Never qualify cfg_err_ur or cfg_err_cpl_abort
assign cfg_pm_wake = 1'b0; // Never direct the core to send a PM_PME Message
assign cfg_trn_pending = 1'b0; // Never set the transaction pending bit in the Device Status Register
assign cfg_err_atomic_egress_blocked = 1'b0; // Never report Atomic TLP blocked
assign cfg_err_internal_cor = 1'b0; // Never report internal error occurred
assign cfg_err_malformed = 1'b0; // Never report malformed error
assign cfg_err_mc_blocked = 1'b0; // Never report multi-cast TLP blocked
assign cfg_err_poisoned = 1'b0; // Never report poisoned TLP received
assign cfg_err_norecovery = 1'b0; // Never qualify cfg_err_poisoned or cfg_err_cpl_timeout
assign cfg_err_acs = 1'b0; // Never report an ACS violation
assign cfg_err_internal_uncor = 1'b0; // Never report internal uncorrectable error
assign cfg_pm_halt_aspm_l0s = 1'b0; // Allow entry into L0s
assign cfg_pm_halt_aspm_l1 = 1'b0; // Allow entry into L1
assign cfg_pm_force_state_en = 1'b0; // Do not qualify cfg_pm_force_state
assign cfg_pm_force_state = 2'b00; // Do not move force core into specific PM state
assign cfg_err_aer_headerlog = 128'h0; // Zero out the AER Header Log
assign cfg_aer_interrupt_msgnum = 5'b00000; // Zero out the AER Root Error Status Register
assign cfg_interrupt_stat = 1'b0; // Never set the Interrupt Status bit
assign cfg_pciecap_interrupt_msgnum = 5'b00000; // Zero out Interrupt Message Number
assign cfg_interrupt_assert = 1'b0; // Always drive interrupt de-assert
assign cfg_interrupt = 1'b0; // Never drive interrupt by qualifying cfg_interrupt_assert
assign cfg_dwaddr = 0; // Zero out address port of configuration access interface
assign pl_directed_link_change = 2'b00; // Never initiate link change
assign pl_directed_link_width = 2'b000; // Zero out directed link width
assign pl_directed_link_speed = 1'b0; // Zero out directed link speed
assign pl_directed_link_auton = 1'b0; // Zero out link autonomous input
assign pl_upstream_prefer_deemph = 1'b1; // Zero out preferred de-emphasis of upstream port
assign cfg_interrupt_di = 8'b0; // Do not set interrupt fields
assign cfg_err_tlp_cpl_header = 48'h0; // Zero out the header information
assign cfg_mgmt_di = 32'h0; // Zero out CFG MGMT input data bus
assign cfg_mgmt_byte_en = 4'h0; // Zero out CFG MGMT byte enables
assign cfg_mgmt_dwaddr = 10'h0; // Zero out CFG MGMT 10-bit address port
assign cfg_mgmt_wr_en = 1'b0; // Do not write CFG space
assign cfg_mgmt_rd_en = 1'b0; // Do not read CFG space
assign cfg_mgmt_wr_readonly = 1'b0; // Never treat RO bit as RW
assign cfg_dsn = {`PCI_EXP_EP_DSN_2, `PCI_EXP_EP_DSN_1}; // Assign the input DSN
//----------------------------------------------------------------------------------------------------------------//
// Programmable I/O Module //
//----------------------------------------------------------------------------------------------------------------//
wire [15:0] cfg_completer_id = { cfg_bus_number, cfg_device_number, cfg_function_number };
wire cfg_bus_mstr_enable = cfg_command[2];
PIO #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH ),
.TCQ( TCQ )
) PIO (
.user_clk ( user_clk ), // I
.user_reset ( user_reset ), // I
.user_lnk_up ( user_lnk_up ), // I
.s_axis_tx_tready ( s_axis_tx_tready ), // I
.s_axis_tx_tdata ( s_axis_tx_tdata ), // O
.s_axis_tx_tkeep ( s_axis_tx_tkeep ), // O
.s_axis_tx_tlast ( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid ( s_axis_tx_tvalid ), // O
.tx_src_dsc ( s_axis_tx_tuser[3] ), // O
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tkeep( m_axis_rx_tkeep ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
.cfg_to_turnoff ( cfg_to_turnoff ), // I
.cfg_turnoff_ok ( cfg_turnoff_ok ), // O
.cfg_completer_id ( cfg_completer_id ) // I [15:0]
);
endmodule // pcie_app
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 5
(* X_CORE_INFO = "axi_crossbar_v2_1_axi_crossbar,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "system_xbar_1,axi_crossbar_v2_1_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "system_xbar_1,axi_crossbar_v2_1_axi_crossbar,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=2,C_NUM_MASTER_SLOTS=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_PROTOCOL=0,C_NUM_ADDR_RANGES=3,C_M_AXI_BASE_ADDR=0x00000000fc00000000000000e00000000000000000000000,C_M_AXI_ADDR_WIDTH=0x00000018000000160000001f,C_S_AXI_BASE_ID=0x0000000100000000,C_S_AXI_THREAD_ID_WIDTH=0x0000000000000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000002,C_M_AXI_READ_CONNECTIVITY=0x00000001,C_R_REGISTER=0,C_S_AXI_SINGLE_THREAD=0x0000000000000000,C_S_AXI_WRITE_ACCEPTANCE=0x0000000200000002,C_S_AXI_READ_ACCEPTANCE=0x0000000200000002,C_M_AXI_WRITE_ISSUING=0x00000008,C_M_AXI_READ_ISSUING=0x00000008,C_S_AXI_ARB_PRIORITY=0x0000000000000000,C_M_AXI_SECURE=0x00000000,C_CONNECTIVITY_MODE=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_xbar_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64]" *)
input wire [127 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8]" *)
input wire [15 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64]" *)
output wire [127 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
output wire [0 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
input wire [0 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
output wire [0 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
output wire [0 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
input wire [0 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
input wire [0 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
output wire [0 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
output wire [0 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
input wire [0 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
input wire [0 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
input wire [0 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
output wire [0 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(2),
.C_NUM_MASTER_SLOTS(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(3),
.C_M_AXI_BASE_ADDR(192'H00000000fc00000000000000e00000000000000000000000),
.C_M_AXI_ADDR_WIDTH(96'H00000018000000160000001f),
.C_S_AXI_BASE_ID(64'H0000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(64'H0000000000000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(32'H00000002),
.C_M_AXI_READ_CONNECTIVITY(32'H00000001),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(64'H0000000000000000),
.C_S_AXI_WRITE_ACCEPTANCE(64'H0000000200000002),
.C_S_AXI_READ_ACCEPTANCE(64'H0000000200000002),
.C_M_AXI_WRITE_ISSUING(32'H00000008),
.C_M_AXI_READ_ISSUING(32'H00000008),
.C_S_AXI_ARB_PRIORITY(64'H0000000000000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(2'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(2'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(2'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(2'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR2B_4_V
`define SKY130_FD_SC_HS__NOR2B_4_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog wrapper for nor2b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor2b_4 (
Y ,
A ,
B_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor2b_4 (
Y ,
A ,
B_N
);
output Y ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor2b base (
.Y(Y),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR2B_4_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// Parameterized FIFO with input and output registers and ACL pipeline
// protocol ports.
//
//===----------------------------------------------------------------------===//
module acl_fifo (
clock,
resetn,
data_in,
data_out,
valid_in,
valid_out,
stall_in,
stall_out,
usedw,
empty,
full,
almost_full);
function integer my_local_log;
input [31:0] value;
for (my_local_log=0; value>0; my_local_log=my_local_log+1)
value = value>>1;
endfunction
parameter DATA_WIDTH = 32;
parameter DEPTH = 256;
parameter NUM_BITS_USED_WORDS = DEPTH == 1 ? 1 : my_local_log(DEPTH-1);
parameter ALMOST_FULL_VALUE = 0;
input clock, stall_in, valid_in, resetn;
output stall_out, valid_out;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
output [NUM_BITS_USED_WORDS-1:0] usedw;
output empty, full, almost_full;
// add a register stage prior to the acl_fifo.
//reg [DATA_WIDTH-1:0] data_input /* synthesis preserve */;
//reg valid_input /* synthesis preserve */;
//always@(posedge clock or negedge resetn)
//begin
// if (~resetn)
// begin
// data_input <= {DATA_WIDTH{1'bx}};
// valid_input <= 1'b0;
// end
// else if (~valid_input | ~full)
// begin
// valid_input <= valid_in;
// data_input <= data_in;
// end
//end
scfifo scfifo_component (
.clock (clock),
.data (data_in),
.rdreq ((~stall_in) & (~empty)),
.sclr (),
.wrreq (valid_in & (~full)),
.empty (empty),
.full (full),
.q (data_out),
.aclr (~resetn),
.almost_empty (),
.almost_full (almost_full),
.usedw (usedw));
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Stratix IV",
scfifo_component.lpm_numwords = DEPTH,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = DATA_WIDTH,
scfifo_component.lpm_widthu = NUM_BITS_USED_WORDS,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON",
scfifo_component.almost_full_value = ALMOST_FULL_VALUE;
assign stall_out = full;
assign valid_out = ~empty;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: riffa_wrapper_7V3.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: RIFFA wrapper for the ADM-PCIe-7V3 Development board
// from Alpha Data
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "trellis.vh"
`include "riffa.vh"
`include "ultrascale.vh"
`include "functions.vh"
`timescale 1ps / 1ps
module riffa_wrapper_adm7V3
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Bit-Width from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
// 4-Byte Name for this FPGA
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5,
parameter C_FPGA_ID = "7V30")
(//Interface: CQ Ultrascale (RXR)
input M_AXIS_CQ_TVALID,
input M_AXIS_CQ_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_CQ_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_CQ_TKEEP,
input [`SIG_CQ_TUSER_W-1:0] M_AXIS_CQ_TUSER,
output M_AXIS_CQ_TREADY,
//Interface: RC Ultrascale (RXC)
input M_AXIS_RC_TVALID,
input M_AXIS_RC_TLAST,
input [C_PCI_DATA_WIDTH-1:0] M_AXIS_RC_TDATA,
input [(C_PCI_DATA_WIDTH/32)-1:0] M_AXIS_RC_TKEEP,
input [`SIG_RC_TUSER_W-1:0] M_AXIS_RC_TUSER,
output M_AXIS_RC_TREADY,
//Interface: CC Ultrascale (TXC)
input S_AXIS_CC_TREADY,
output S_AXIS_CC_TVALID,
output S_AXIS_CC_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_CC_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_CC_TKEEP,
output [`SIG_CC_TUSER_W-1:0] S_AXIS_CC_TUSER,
//Interface: RQ Ultrascale (TXR)
input S_AXIS_RQ_TREADY,
output S_AXIS_RQ_TVALID,
output S_AXIS_RQ_TLAST,
output [C_PCI_DATA_WIDTH-1:0] S_AXIS_RQ_TDATA,
output [(C_PCI_DATA_WIDTH/32)-1:0] S_AXIS_RQ_TKEEP,
output [`SIG_RQ_TUSER_W-1:0] S_AXIS_RQ_TUSER,
input USER_CLK,
input USER_RESET,
output [3:0] CFG_INTERRUPT_INT,
output [1:0] CFG_INTERRUPT_PENDING,
input [1:0] CFG_INTERRUPT_MSI_ENABLE,
input CFG_INTERRUPT_MSI_MASK_UPDATE,
input [31:0] CFG_INTERRUPT_MSI_DATA,
output [3:0] CFG_INTERRUPT_MSI_SELECT,
output [31:0] CFG_INTERRUPT_MSI_INT,
output [63:0] CFG_INTERRUPT_MSI_PENDING_STATUS,
input CFG_INTERRUPT_MSI_SENT,
input CFG_INTERRUPT_MSI_FAIL,
output [2:0] CFG_INTERRUPT_MSI_ATTR,
output CFG_INTERRUPT_MSI_TPH_PRESENT,
output [1:0] CFG_INTERRUPT_MSI_TPH_TYPE,
output [8:0] CFG_INTERRUPT_MSI_TPH_ST_TAG,
output [2:0] CFG_INTERRUPT_MSI_FUNCTION_NUMBER,
input [7:0] CFG_FC_CPLH,
input [11:0] CFG_FC_CPLD,
output [2:0] CFG_FC_SEL,
input [3:0] CFG_NEGOTIATED_WIDTH, // CONFIG_LINK_WIDTH
input [2:0] CFG_CURRENT_SPEED, // CONFIG_LINK_RATE
input [2:0] CFG_MAX_PAYLOAD, // CONFIG_MAX_PAYLOAD
input [2:0] CFG_MAX_READ_REQ, // CONFIG_MAX_READ_REQUEST
input [7:0] CFG_FUNCTION_STATUS, // [2] = CONFIG_BUS_MASTER_ENABLE
input [1:0] CFG_RCB_STATUS,
output PCIE_CQ_NP_REQ,
// RIFFA Interface Signals
output RST_OUT,
input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock
output [C_NUM_CHNL-1:0] CHNL_RX, // Channel read receive signal
input [C_NUM_CHNL-1:0] CHNL_RX_ACK, // Channel read received signal
output [C_NUM_CHNL-1:0] CHNL_RX_LAST, // Channel last read
output [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_RX_LEN, // Channel read length
output [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_RX_OFF, // Channel read offset
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA, // Channel read data
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID, // Channel read data valid
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN, // Channel read data has been recieved
input [C_NUM_CHNL-1:0] CHNL_TX_CLK, // Channel write clock
input [C_NUM_CHNL-1:0] CHNL_TX, // Channel write receive signal
output [C_NUM_CHNL-1:0] CHNL_TX_ACK, // Channel write acknowledgement signal
input [C_NUM_CHNL-1:0] CHNL_TX_LAST, // Channel last write
input [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] CHNL_TX_LEN, // Channel write length (in 32 bit words)
input [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] CHNL_TX_OFF, // Channel write offset
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved
localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver
localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2;
// ALTERA, XILINX or ULTRASCALE
localparam C_VENDOR = "ULTRASCALE";
localparam C_KEEP_WIDTH = C_PCI_DATA_WIDTH / 32;
localparam C_PIPELINE_OUTPUT = 1;
localparam C_PIPELINE_INPUT = 1;
localparam C_DEPTH_PACKETS = 4;
wire clk;
wire rst_in;
wire done_txc_rst;
wire done_txr_rst;
wire done_rxr_rst;
wire done_rxc_rst;
// Interface: RXC Engine
wire [C_PCI_DATA_WIDTH-1:0] rxc_data;
wire rxc_data_valid;
wire rxc_data_start_flag;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset;
wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe;
wire rxc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset;
wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe;
wire [`SIG_TAG_W-1:0] rxc_meta_tag;
wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr;
wire [`SIG_TYPE_W-1:0] rxc_meta_type;
wire [`SIG_LEN_W-1:0] rxc_meta_length;
wire [`SIG_BYTECNT_W-1:0] rxc_meta_bytes_remaining;
wire [`SIG_CPLID_W-1:0] rxc_meta_completer_id;
wire rxc_meta_ep;
// Interface: RXR Engine
wire [C_PCI_DATA_WIDTH-1:0] rxr_data;
wire rxr_data_valid;
wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable;
wire rxr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset;
wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe;
wire rxr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset;
wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe;
wire [`SIG_TC_W-1:0] rxr_meta_tc;
wire [`SIG_ATTR_W-1:0] rxr_meta_attr;
wire [`SIG_TAG_W-1:0] rxr_meta_tag;
wire [`SIG_TYPE_W-1:0] rxr_meta_type;
wire [`SIG_ADDR_W-1:0] rxr_meta_addr;
wire [`SIG_BARDECODE_W-1:0] rxr_meta_bar_decoded;
wire [`SIG_REQID_W-1:0] rxr_meta_requester_id;
wire [`SIG_LEN_W-1:0] rxr_meta_length;
wire rxr_meta_ep;
// interface: TXC Engine
wire txc_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txc_data;
wire txc_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset;
wire txc_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset;
wire txc_data_ready;
wire txc_meta_valid;
wire [`SIG_FBE_W-1:0] txc_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txc_meta_ldwbe;
wire [`SIG_LOWADDR_W-1:0] txc_meta_addr;
wire [`SIG_TYPE_W-1:0] txc_meta_type;
wire [`SIG_LEN_W-1:0] txc_meta_length;
wire [`SIG_BYTECNT_W-1:0] txc_meta_byte_count;
wire [`SIG_TAG_W-1:0] txc_meta_tag;
wire [`SIG_REQID_W-1:0] txc_meta_requester_id;
wire [`SIG_TC_W-1:0] txc_meta_tc;
wire [`SIG_ATTR_W-1:0] txc_meta_attr;
wire txc_meta_ep;
wire txc_meta_ready;
wire txc_sent;
// Interface: TXR Engine
wire txr_data_valid;
wire [C_PCI_DATA_WIDTH-1:0] txr_data;
wire txr_data_start_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset;
wire txr_data_end_flag;
wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset;
wire txr_data_ready;
wire txr_meta_valid;
wire [`SIG_FBE_W-1:0] txr_meta_fdwbe;
wire [`SIG_LBE_W-1:0] txr_meta_ldwbe;
wire [`SIG_ADDR_W-1:0] txr_meta_addr;
wire [`SIG_LEN_W-1:0] txr_meta_length;
wire [`SIG_TAG_W-1:0] txr_meta_tag;
wire [`SIG_TC_W-1:0] txr_meta_tc;
wire [`SIG_ATTR_W-1:0] txr_meta_attr;
wire [`SIG_TYPE_W-1:0] txr_meta_type;
wire txr_meta_ep;
wire txr_meta_ready;
wire txr_sent;
// Unconnected Wires (Used in classic interface)
wire wRxTlpReady_nc;
wire [C_PCI_DATA_WIDTH-1:0] wRxTlp_nc = 0;
wire wRxTlpEndFlag_nc = 0;
wire [`SIG_OFFSET_W-1:0] wRxTlpEndOffset_nc = 0;
wire wRxTlpStartFlag_nc = 0;
wire [`SIG_OFFSET_W-1:0] wRxTlpStartOffset_nc = 0;
wire wRxTlpValid_nc = 0;
wire [`SIG_BARDECODE_W-1:0] wRxTlpBarDecode_nc = 0;
wire wTxTlpReady_nc = 0;
wire [C_PCI_DATA_WIDTH-1:0] wTxTlp_nc;
wire wTxTlpEndFlag_nc;
wire [`SIG_OFFSET_W-1:0] wTxTlpEndOffset_nc;
wire wTxTlpStartFlag_nc;
wire [`SIG_OFFSET_W-1:0] wTxTlpStartOffset_nc;
wire wTxTlpValid_nc;
//--------------------------------------------------------------------------
// Interface: Configuration
wire config_bus_master_enable;
wire [`SIG_CPLID_W-1:0] config_completer_id;
wire config_cpl_boundary_sel;
wire config_interrupt_msienable;
wire [`SIG_LINKRATE_W-1:0] config_link_rate;
wire [`SIG_LINKWIDTH_W-1:0] config_link_width;
wire [`SIG_MAXPAYLOAD_W-1:0] config_max_payload_size;
wire [`SIG_MAXREAD_W-1:0] config_max_read_request_size;
wire [`SIG_FC_CPLD_W-1:0] config_max_cpl_data;
wire [`SIG_FC_CPLH_W-1:0] config_max_cpl_hdr;
wire intr_msi_request;
wire intr_msi_rdy;
genvar chnl;
assign clk = USER_CLK;
assign rst_in = USER_RESET;
assign config_completer_id = 0; // Not used in ULTRASCALE implementation
assign config_bus_master_enable = CFG_FUNCTION_STATUS[2];
assign config_link_width = {2'b00,CFG_NEGOTIATED_WIDTH}; // CONFIG_LINK_WIDTH
assign config_link_rate = CFG_CURRENT_SPEED[2]? 2'b11 : CFG_CURRENT_SPEED[2] ? 2'b10 : 2'b01;
assign config_max_payload_size = CFG_MAX_PAYLOAD; // CONFIG_MAX_PAYLOAD
assign config_max_read_request_size = CFG_MAX_READ_REQ; // CONFIG_MAX_READ_REQUEST
assign config_cpl_boundary_sel = CFG_RCB_STATUS[0];
assign config_interrupt_msienable = CFG_INTERRUPT_MSI_ENABLE[0];
assign config_max_cpl_data = CFG_FC_CPLD;
assign config_max_cpl_hdr = CFG_FC_CPLH;
assign CFG_FC_SEL = 3'b001; // Always display credit maximum for the signals below
assign CFG_INTERRUPT_MSI_INT = {31'b0,intr_msi_request};
assign CFG_INTERRUPT_MSI_SELECT = 0;
assign CFG_INTERRUPT_INT = 0;
assign CFG_INTERRUPT_PENDING = 0;
assign CFG_INTERRUPT_MSI_SELECT = 0;
assign CFG_INTERRUPT_MSI_PENDING_STATUS = {63'b0,intr_msi_request};
assign CFG_INTERRUPT_MSI_ATTR = 0;
assign CFG_INTERRUPT_MSI_TPH_PRESENT = 0;
assign CFG_INTERRUPT_MSI_TPH_ST_TAG = 0;
assign CFG_INTERRUPT_MSI_TPH_TYPE = 0;
assign CFG_INTERRUPT_MSI_FUNCTION_NUMBER = 0;
assign intr_msi_rdy = CFG_INTERRUPT_MSI_SENT & ~CFG_INTERRUPT_MSI_FAIL;
assign PCIE_CQ_NP_REQ = 1;
engine_layer
#(// Parameters
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_BYTES/4),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
engine_layer_inst
(// Outputs
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.RST_LOGIC (RST_OUT),
// Unconnected Outputs
.TX_TLP (wTxTlp_nc),
.TX_TLP_VALID (wTxTlpValid_nc),
.TX_TLP_START_FLAG (wTxTlpStartFlag_nc),
.TX_TLP_START_OFFSET (wTxTlpStartOffset_nc),
.TX_TLP_END_FLAG (wTxTlpEndFlag_nc),
.TX_TLP_END_OFFSET (wTxTlpEndOffset_nc),
.RX_TLP_READY (wRxTlpReady_nc),
// Inputs
.CLK_BUS (clk),
.RST_BUS (rst_in),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
// Unconnected Inputs
.RX_TLP (wRxTlp_nc),
.RX_TLP_VALID (wRxTlpValid_nc),
.RX_TLP_START_FLAG (wRxTlpStartFlag_nc),
.RX_TLP_START_OFFSET (wRxTlpStartOffset_nc),
.RX_TLP_END_FLAG (wRxTlpEndFlag_nc),
.RX_TLP_END_OFFSET (wRxTlpEndOffset_nc),
.RX_TLP_BAR_DECODE (wRxTlpBarDecode_nc),
.TX_TLP_READY (wTxTlpReady_nc),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.DONE_RXR_RST (done_rxc_rst),
.DONE_RXC_RST (done_rxr_rstsudo),
/*AUTOINST*/
// Outputs
.M_AXIS_CQ_TREADY (M_AXIS_CQ_TREADY),
.M_AXIS_RC_TREADY (M_AXIS_RC_TREADY),
.S_AXIS_CC_TVALID (S_AXIS_CC_TVALID),
.S_AXIS_CC_TLAST (S_AXIS_CC_TLAST),
.S_AXIS_CC_TDATA (S_AXIS_CC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (S_AXIS_CC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (S_AXIS_CC_TUSER[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (S_AXIS_RQ_TVALID),
.S_AXIS_RQ_TLAST (S_AXIS_RQ_TLAST),
.S_AXIS_RQ_TDATA (S_AXIS_RQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (S_AXIS_RQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (S_AXIS_RQ_TUSER[`SIG_RQ_TUSER_W-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (M_AXIS_CQ_TVALID),
.M_AXIS_CQ_TLAST (M_AXIS_CQ_TLAST),
.M_AXIS_CQ_TDATA (M_AXIS_CQ_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (M_AXIS_CQ_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (M_AXIS_CQ_TUSER[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (M_AXIS_RC_TVALID),
.M_AXIS_RC_TLAST (M_AXIS_RC_TLAST),
.M_AXIS_RC_TDATA (M_AXIS_RC_TDATA[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (M_AXIS_RC_TKEEP[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (M_AXIS_RC_TUSER[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (S_AXIS_CC_TREADY),
.S_AXIS_RQ_TREADY (S_AXIS_RQ_TREADY));
riffa
#(.C_TAG_WIDTH (C_LOG_NUM_TAGS),/* TODO: Standardize declaration*/
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_FPGA_NAME (C_FPGA_NAME),
.C_FPGA_ID (C_FPGA_ID),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
riffa_inst
(// Outputs
.TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_VALID (txc_data_valid),
.TXC_DATA_START_FLAG (txc_data_start_flag),
.TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (txc_data_end_flag),
.TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (txc_meta_valid),
.TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (txc_meta_addr[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (txc_meta_type[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (txc_meta_length[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (txc_meta_byte_count[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (txc_meta_tag[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (txc_meta_requester_id[`SIG_REQID_W-1:0]),
.TXC_META_TC (txc_meta_tc[`SIG_TC_W-1:0]),
.TXC_META_ATTR (txc_meta_attr[`SIG_ATTR_W-1:0]),
.TXC_META_EP (txc_meta_ep),
.TXR_DATA_VALID (txr_data_valid),
.TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (txr_data_start_flag),
.TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (txr_data_end_flag),
.TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (txr_meta_valid),
.TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (txr_meta_addr[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (txr_meta_length[`SIG_LEN_W-1:0]),
.TXR_META_TAG (txr_meta_tag[`SIG_TAG_W-1:0]),
.TXR_META_TC (txr_meta_tc[`SIG_TC_W-1:0]),
.TXR_META_ATTR (txr_meta_attr[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (txr_meta_type[`SIG_TYPE_W-1:0]),
.TXR_META_EP (txr_meta_ep),
.INTR_MSI_REQUEST (intr_msi_request),
// Inputs
.CLK (clk),
.RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (rxr_data_valid),
.RXR_DATA_START_FLAG (rxr_data_start_flag),
.RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_DATA_END_FLAG (rxr_data_end_flag),
.RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]),
.RXR_META_ATTR (rxr_meta_attr[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (rxr_meta_tag[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (rxr_meta_type[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (rxr_meta_addr[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (rxr_meta_bar_decoded[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (rxr_meta_requester_id[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (rxr_meta_length[`SIG_LEN_W-1:0]),
.RXR_META_EP (rxr_meta_ep),
.RXC_DATA_VALID (rxc_data_valid),
.RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]),
.RXC_DATA_START_FLAG (rxc_data_start_flag),
.RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_DATA_END_FLAG (rxc_data_end_flag),
.RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]),
.RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]),
.RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),
.RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]),
.RXC_META_TYPE (rxc_meta_type[`SIG_TYPE_W-1:0]),
.RXC_META_LENGTH (rxc_meta_length[`SIG_LEN_W-1:0]),
.RXC_META_BYTES_REMAINING (rxc_meta_bytes_remaining[`SIG_BYTECNT_W-1:0]),
.RXC_META_COMPLETER_ID (rxc_meta_completer_id[`SIG_CPLID_W-1:0]),
.RXC_META_EP (rxc_meta_ep),
.TXC_DATA_READY (txc_data_ready),
.TXC_META_READY (txc_meta_ready),
.TXC_SENT (txc_sent),
.TXR_DATA_READY (txr_data_ready),
.TXR_META_READY (txr_meta_ready),
.TXR_SENT (txr_sent),
.CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]),
.CONFIG_BUS_MASTER_ENABLE (config_bus_master_enable),
.CONFIG_LINK_WIDTH (config_link_width[`SIG_LINKWIDTH_W-1:0]),
.CONFIG_LINK_RATE (config_link_rate[`SIG_LINKRATE_W-1:0]),
.CONFIG_MAX_READ_REQUEST_SIZE (config_max_read_request_size[`SIG_MAXREAD_W-1:0]),
.CONFIG_MAX_PAYLOAD_SIZE (config_max_payload_size[`SIG_MAXPAYLOAD_W-1:0]),
.CONFIG_INTERRUPT_MSIENABLE (config_interrupt_msienable),
.CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel),
.CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]),
.CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]),
.INTR_MSI_RDY (intr_msi_rdy),
.DONE_TXC_RST (done_txc_rst),
.DONE_TXR_RST (done_txr_rst),
.RST_BUS (rst_in),
/*AUTOINST*/
// Outputs
.RST_OUT (RST_OUT),
.CHNL_RX (CHNL_RX[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (CHNL_RX_LAST[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (CHNL_RX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_RX_OFF (CHNL_RX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_RX_DATA (CHNL_RX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (CHNL_RX_DATA_VALID[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (CHNL_TX_ACK[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (CHNL_TX_DATA_REN[C_NUM_CHNL-1:0]),
// Inputs
.CHNL_RX_CLK (CHNL_RX_CLK[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (CHNL_RX_ACK[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (CHNL_RX_DATA_REN[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (CHNL_TX_CLK[C_NUM_CHNL-1:0]),
.CHNL_TX (CHNL_TX[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (CHNL_TX_LAST[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (CHNL_TX_LEN[(C_NUM_CHNL*32)-1:0]),
.CHNL_TX_OFF (CHNL_TX_OFF[(C_NUM_CHNL*31)-1:0]),
.CHNL_TX_DATA (CHNL_TX_DATA[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (CHNL_TX_DATA_VALID[C_NUM_CHNL-1:0]));
endmodule
// Local Variables:
// verilog-library-directories:("../../riffa_hdl/")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A31OI_PP_BLACKBOX_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_1_V
`define SKY130_FD_SC_HDLL__OR3_1_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O22A_TB_V
`define SKY130_FD_SC_HDLL__O22A_TB_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__o22a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hdll__o22a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O22A_TB_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Address AXI3 Slave Converter
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// a_axi3_conv
// axic_fifo
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_a_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AUSER_WIDTH = 1,
parameter integer C_AXI_CHANNEL = 0,
// 0 = AXI AW Channel.
// 1 = AXI AR Channel.
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1,
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
parameter integer C_SINGLE_THREAD = 1
// 0 = Ignore ID when propagating transactions (assume all responses are in order).
// 1 = Enforce single-threading (one ID at a time) when any outstanding or
// requested transaction requires splitting.
// While no split is ongoing any new non-split transaction will pass immediately regardless
// off ID.
// A split transaction will stall if there are multiple ID (non-split) transactions
// ongoing, once it has been forwarded only transactions with the same ID is allowed
// (split or not) until all ongoing split transactios has been completed.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface (W/R)
output wire cmd_valid,
output wire cmd_split,
output wire [C_AXI_ID_WIDTH-1:0] cmd_id,
output wire [4-1:0] cmd_length,
input wire cmd_ready,
// Command Interface (B)
output wire cmd_b_valid,
output wire cmd_b_split,
output wire [4-1:0] cmd_b_repeat,
input wire cmd_b_ready,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR,
input wire [8-1:0] S_AXI_ALEN,
input wire [3-1:0] S_AXI_ASIZE,
input wire [2-1:0] S_AXI_ABURST,
input wire [1-1:0] S_AXI_ALOCK,
input wire [4-1:0] S_AXI_ACACHE,
input wire [3-1:0] S_AXI_APROT,
input wire [4-1:0] S_AXI_AQOS,
input wire [C_AXI_AUSER_WIDTH-1:0] S_AXI_AUSER,
input wire S_AXI_AVALID,
output wire S_AXI_AREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR,
output wire [4-1:0] M_AXI_ALEN,
output wire [3-1:0] M_AXI_ASIZE,
output wire [2-1:0] M_AXI_ABURST,
output wire [2-1:0] M_AXI_ALOCK,
output wire [4-1:0] M_AXI_ACACHE,
output wire [3-1:0] M_AXI_APROT,
output wire [4-1:0] M_AXI_AQOS,
output wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER,
output wire M_AXI_AVALID,
input wire M_AXI_AREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for burst types.
localparam [2-1:0] C_FIX_BURST = 2'b00;
localparam [2-1:0] C_INCR_BURST = 2'b01;
localparam [2-1:0] C_WRAP_BURST = 2'b10;
// Depth for command FIFO.
localparam integer C_FIFO_DEPTH_LOG = 5;
// Constants used to generate size mask.
localparam [C_AXI_ADDR_WIDTH+8-1:0] C_SIZE_MASK = {{C_AXI_ADDR_WIDTH{1'b1}}, 8'b0000_0000};
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Access decoding related signals.
wire access_is_incr;
wire [4-1:0] num_transactions;
wire incr_need_to_split;
reg [C_AXI_ADDR_WIDTH-1:0] next_mi_addr;
reg split_ongoing;
reg [4-1:0] pushed_commands;
reg [16-1:0] addr_step;
reg [16-1:0] first_step;
wire [8-1:0] first_beats;
reg [C_AXI_ADDR_WIDTH-1:0] size_mask;
// Access decoding related signals for internal pipestage.
reg access_is_incr_q;
reg incr_need_to_split_q;
wire need_to_split_q;
reg [4-1:0] num_transactions_q;
reg [16-1:0] addr_step_q;
reg [16-1:0] first_step_q;
reg [C_AXI_ADDR_WIDTH-1:0] size_mask_q;
// Command buffer help signals.
reg [C_FIFO_DEPTH_LOG:0] cmd_depth;
reg cmd_empty;
reg [C_AXI_ID_WIDTH-1:0] queue_id;
wire id_match;
wire cmd_id_check;
wire s_ready;
wire cmd_full;
wire allow_this_cmd;
wire allow_new_cmd;
wire cmd_push;
reg cmd_push_block;
reg [C_FIFO_DEPTH_LOG:0] cmd_b_depth;
reg cmd_b_empty;
wire cmd_b_full;
wire cmd_b_push;
reg cmd_b_push_block;
wire pushed_new_cmd;
wire last_incr_split;
wire last_split;
wire first_split;
wire no_cmd;
wire allow_split_cmd;
wire almost_empty;
wire no_b_cmd;
wire allow_non_split_cmd;
wire almost_b_empty;
reg multiple_id_non_split;
reg split_in_progress;
// Internal Command Interface signals (W/R).
wire cmd_split_i;
wire [C_AXI_ID_WIDTH-1:0] cmd_id_i;
reg [4-1:0] cmd_length_i;
// Internal Command Interface signals (B).
wire cmd_b_split_i;
wire [4-1:0] cmd_b_repeat_i;
// Throttling help signals.
wire mi_stalling;
reg command_ongoing;
// Internal SI-side signals.
reg [C_AXI_ID_WIDTH-1:0] S_AXI_AID_Q;
reg [C_AXI_ADDR_WIDTH-1:0] S_AXI_AADDR_Q;
reg [8-1:0] S_AXI_ALEN_Q;
reg [3-1:0] S_AXI_ASIZE_Q;
reg [2-1:0] S_AXI_ABURST_Q;
reg [2-1:0] S_AXI_ALOCK_Q;
reg [4-1:0] S_AXI_ACACHE_Q;
reg [3-1:0] S_AXI_APROT_Q;
reg [4-1:0] S_AXI_AQOS_Q;
reg [C_AXI_AUSER_WIDTH-1:0] S_AXI_AUSER_Q;
reg S_AXI_AREADY_I;
// Internal MI-side signals.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_AID_I;
reg [C_AXI_ADDR_WIDTH-1:0] M_AXI_AADDR_I;
reg [8-1:0] M_AXI_ALEN_I;
wire [3-1:0] M_AXI_ASIZE_I;
wire [2-1:0] M_AXI_ABURST_I;
reg [2-1:0] M_AXI_ALOCK_I;
wire [4-1:0] M_AXI_ACACHE_I;
wire [3-1:0] M_AXI_APROT_I;
wire [4-1:0] M_AXI_AQOS_I;
wire [C_AXI_AUSER_WIDTH-1:0] M_AXI_AUSER_I;
wire M_AXI_AVALID_I;
wire M_AXI_AREADY_I;
reg [1:0] areset_d; // Reset delay register
always @(posedge ACLK) begin
areset_d <= {areset_d[0], ARESET};
end
/////////////////////////////////////////////////////////////////////////////
// Capture SI-Side signals.
//
/////////////////////////////////////////////////////////////////////////////
// Register SI-Side signals.
always @ (posedge ACLK) begin
if ( ARESET ) begin
S_AXI_AID_Q <= {C_AXI_ID_WIDTH{1'b0}};
S_AXI_AADDR_Q <= {C_AXI_ADDR_WIDTH{1'b0}};
S_AXI_ALEN_Q <= 8'b0;
S_AXI_ASIZE_Q <= 3'b0;
S_AXI_ABURST_Q <= 2'b0;
S_AXI_ALOCK_Q <= 2'b0;
S_AXI_ACACHE_Q <= 4'b0;
S_AXI_APROT_Q <= 3'b0;
S_AXI_AQOS_Q <= 4'b0;
S_AXI_AUSER_Q <= {C_AXI_AUSER_WIDTH{1'b0}};
end else begin
if ( S_AXI_AREADY_I ) begin
S_AXI_AID_Q <= S_AXI_AID;
S_AXI_AADDR_Q <= S_AXI_AADDR;
S_AXI_ALEN_Q <= S_AXI_ALEN;
S_AXI_ASIZE_Q <= S_AXI_ASIZE;
S_AXI_ABURST_Q <= S_AXI_ABURST;
S_AXI_ALOCK_Q <= S_AXI_ALOCK;
S_AXI_ACACHE_Q <= S_AXI_ACACHE;
S_AXI_APROT_Q <= S_AXI_APROT;
S_AXI_AQOS_Q <= S_AXI_AQOS;
S_AXI_AUSER_Q <= S_AXI_AUSER;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Decode the Incoming Transaction.
//
// Extract transaction type and the number of splits that may be needed.
//
// Calculate the step size so that the address for each part of a split can
// can be calculated.
//
/////////////////////////////////////////////////////////////////////////////
// Transaction burst type.
assign access_is_incr = ( S_AXI_ABURST == C_INCR_BURST );
// Get number of transactions for split INCR.
assign num_transactions = S_AXI_ALEN[4 +: 4];
assign first_beats = {3'b0, S_AXI_ALEN[0 +: 4]} + 7'b01;
// Generate address increment of first split transaction.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: first_step = first_beats << 0;
3'b001: first_step = first_beats << 1;
3'b010: first_step = first_beats << 2;
3'b011: first_step = first_beats << 3;
3'b100: first_step = first_beats << 4;
3'b101: first_step = first_beats << 5;
3'b110: first_step = first_beats << 6;
3'b111: first_step = first_beats << 7;
endcase
end
// Generate address increment for remaining split transactions.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: addr_step = 16'h0010;
3'b001: addr_step = 16'h0020;
3'b010: addr_step = 16'h0040;
3'b011: addr_step = 16'h0080;
3'b100: addr_step = 16'h0100;
3'b101: addr_step = 16'h0200;
3'b110: addr_step = 16'h0400;
3'b111: addr_step = 16'h0800;
endcase
end
// Generate address mask bits to remove split transaction unalignment.
always @ *
begin
case (S_AXI_ASIZE)
3'b000: size_mask = C_SIZE_MASK[8 +: C_AXI_ADDR_WIDTH];
3'b001: size_mask = C_SIZE_MASK[7 +: C_AXI_ADDR_WIDTH];
3'b010: size_mask = C_SIZE_MASK[6 +: C_AXI_ADDR_WIDTH];
3'b011: size_mask = C_SIZE_MASK[5 +: C_AXI_ADDR_WIDTH];
3'b100: size_mask = C_SIZE_MASK[4 +: C_AXI_ADDR_WIDTH];
3'b101: size_mask = C_SIZE_MASK[3 +: C_AXI_ADDR_WIDTH];
3'b110: size_mask = C_SIZE_MASK[2 +: C_AXI_ADDR_WIDTH];
3'b111: size_mask = C_SIZE_MASK[1 +: C_AXI_ADDR_WIDTH];
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Transfer SI-Side signals to internal Pipeline Stage.
//
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
if ( ARESET ) begin
access_is_incr_q <= 1'b0;
incr_need_to_split_q <= 1'b0;
num_transactions_q <= 4'b0;
addr_step_q <= 16'b0;
first_step_q <= 16'b0;
size_mask_q <= {C_AXI_ADDR_WIDTH{1'b0}};
end else begin
if ( S_AXI_AREADY_I ) begin
access_is_incr_q <= access_is_incr;
incr_need_to_split_q <= incr_need_to_split;
num_transactions_q <= num_transactions;
addr_step_q <= addr_step;
first_step_q <= first_step;
size_mask_q <= size_mask;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Generate Command Information.
//
// Detect if current transation needs to be split, and keep track of all
// the generated split transactions.
//
//
/////////////////////////////////////////////////////////////////////////////
// Detect when INCR must be split.
assign incr_need_to_split = access_is_incr & ( num_transactions != 0 ) &
( C_SUPPORT_SPLITTING == 1 ) &
( C_SUPPORT_BURSTS == 1 );
// Detect when a command has to be split.
assign need_to_split_q = incr_need_to_split_q;
// Handle progress of split transactions.
always @ (posedge ACLK) begin
if ( ARESET ) begin
split_ongoing <= 1'b0;
end else begin
if ( pushed_new_cmd ) begin
split_ongoing <= need_to_split_q & ~last_split;
end
end
end
// Keep track of number of transactions generated.
always @ (posedge ACLK) begin
if ( ARESET ) begin
pushed_commands <= 4'b0;
end else begin
if ( S_AXI_AREADY_I ) begin
pushed_commands <= 4'b0;
end else if ( pushed_new_cmd ) begin
pushed_commands <= pushed_commands + 4'b1;
end
end
end
// Detect last part of a command, split or not.
assign last_incr_split = access_is_incr_q & ( num_transactions_q == pushed_commands );
assign last_split = last_incr_split | ~access_is_incr_q |
( C_SUPPORT_SPLITTING == 0 ) |
( C_SUPPORT_BURSTS == 0 );
assign first_split = (pushed_commands == 4'b0);
// Calculate base for next address.
always @ (posedge ACLK) begin
if ( ARESET ) begin
next_mi_addr = {C_AXI_ADDR_WIDTH{1'b0}};
end else if ( pushed_new_cmd ) begin
next_mi_addr = M_AXI_AADDR_I + (first_split ? first_step_q : addr_step_q);
end
end
/////////////////////////////////////////////////////////////////////////////
// Translating Transaction.
//
// Set Split transaction information on all part except last for a transaction
// that needs splitting.
// The B Channel will only get one command for a Split transaction and in
// the Split bflag will be set in that case.
//
// The AWID is extracted and applied to all commands generated for the current
// incomming SI-Side transaction.
//
// The address is increased for each part of a Split transaction, the amount
// depends on the siSIZE for the transaction.
//
// The length has to be changed for Split transactions. All part except tha
// last one will have 0xF, the last one uses the 4 lsb bits from the SI-side
// transaction as length.
//
// Non-Split has untouched address and length information.
//
// Exclusive access are diasabled for a Split transaction because it is not
// possible to guarantee concistency between all the parts.
//
/////////////////////////////////////////////////////////////////////////////
// Assign Split signals.
assign cmd_split_i = need_to_split_q & ~last_split;
assign cmd_b_split_i = need_to_split_q & ~last_split;
// Copy AW ID to W.
assign cmd_id_i = S_AXI_AID_Q;
// Set B Responses to merge.
assign cmd_b_repeat_i = num_transactions_q;
// Select new size or remaining size.
always @ *
begin
if ( split_ongoing & access_is_incr_q ) begin
M_AXI_AADDR_I = next_mi_addr & size_mask_q;
end else begin
M_AXI_AADDR_I = S_AXI_AADDR_Q;
end
end
// Generate the base length for each transaction.
always @ *
begin
if ( first_split | ~need_to_split_q ) begin
M_AXI_ALEN_I = S_AXI_ALEN_Q[0 +: 4];
cmd_length_i = S_AXI_ALEN_Q[0 +: 4];
end else begin
M_AXI_ALEN_I = 4'hF;
cmd_length_i = 4'hF;
end
end
// Kill Exclusive for Split transactions.
always @ *
begin
if ( need_to_split_q ) begin
M_AXI_ALOCK_I = 2'b00;
end else begin
M_AXI_ALOCK_I = {1'b0, S_AXI_ALOCK_Q};
end
end
/////////////////////////////////////////////////////////////////////////////
// Forward the command to the MI-side interface.
//
// It is determined that this is an allowed command/access when there is
// room in the command queue (and it passes ID and Split checks as required).
//
/////////////////////////////////////////////////////////////////////////////
// Move SI-side transaction to internal pipe stage.
always @ (posedge ACLK) begin
if (ARESET) begin
command_ongoing <= 1'b0;
S_AXI_AREADY_I <= 1'b0;
end else begin
if (areset_d == 2'b10) begin
S_AXI_AREADY_I <= 1'b1;
end else begin
if ( S_AXI_AVALID & S_AXI_AREADY_I ) begin
command_ongoing <= 1'b1;
S_AXI_AREADY_I <= 1'b0;
end else if ( pushed_new_cmd & last_split ) begin
command_ongoing <= 1'b0;
S_AXI_AREADY_I <= 1'b1;
end
end
end
end
// Generate ready signal.
assign S_AXI_AREADY = S_AXI_AREADY_I;
// Only allowed to forward translated command when command queue is ok with it.
assign M_AXI_AVALID_I = allow_new_cmd & command_ongoing;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_AVALID_I & ~M_AXI_AREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Simple transfer of paramters that doesn't need to be adjusted.
//
// ID - Transaction still recognized with the same ID.
// CACHE - No need to change the chache features. Even if the modyfiable
// bit is overridden (forcefully) there is no need to let downstream
// component beleive it is ok to modify it further.
// PROT - Security level of access is not changed when upsizing.
// QOS - Quality of Service is static 0.
// USER - User bits remains the same.
//
/////////////////////////////////////////////////////////////////////////////
assign M_AXI_AID_I = S_AXI_AID_Q;
assign M_AXI_ASIZE_I = S_AXI_ASIZE_Q;
assign M_AXI_ABURST_I = S_AXI_ABURST_Q;
assign M_AXI_ACACHE_I = S_AXI_ACACHE_Q;
assign M_AXI_APROT_I = S_AXI_APROT_Q;
assign M_AXI_AQOS_I = S_AXI_AQOS_Q;
assign M_AXI_AUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_AUSER_Q : {C_AXI_AUSER_WIDTH{1'b0}};
/////////////////////////////////////////////////////////////////////////////
// Control command queue to W/R channel.
//
// Commands can be pushed into the Cmd FIFO even if MI-side is stalling.
// A flag is set if MI-side is stalling when Command is pushed to the
// Cmd FIFO. This will prevent multiple push of the same Command as well as
// keeping the MI-side Valid signal if the Allow Cmd requirement has been
// updated to disable furter Commands (I.e. it is made sure that the SI-side
// Command has been forwarded to both Cmd FIFO and MI-side).
//
// It is allowed to continue pushing new commands as long as
// * There is room in the queue(s)
// * The ID is the same as previously queued. Since data is not reordered
// for the same ID it is always OK to let them proceed.
// Or, if no split transaction is ongoing any ID can be allowed.
//
/////////////////////////////////////////////////////////////////////////////
// Keep track of current ID in queue.
always @ (posedge ACLK) begin
if (ARESET) begin
queue_id <= {C_AXI_ID_WIDTH{1'b0}};
multiple_id_non_split <= 1'b0;
split_in_progress <= 1'b0;
end else begin
if ( cmd_push ) begin
// Store ID (it will be matching ID or a "new beginning").
queue_id <= S_AXI_AID_Q;
end
if ( no_cmd & no_b_cmd ) begin
multiple_id_non_split <= 1'b0;
end else if ( cmd_push & allow_non_split_cmd & ~id_match ) begin
multiple_id_non_split <= 1'b1;
end
if ( no_cmd & no_b_cmd ) begin
split_in_progress <= 1'b0;
end else if ( cmd_push & allow_split_cmd ) begin
split_in_progress <= 1'b1;
end
end
end
// Determine if the command FIFOs are empty.
assign no_cmd = almost_empty & cmd_ready | cmd_empty;
assign no_b_cmd = almost_b_empty & cmd_b_ready | cmd_b_empty;
// Check ID to make sure this command is allowed.
assign id_match = ( C_SINGLE_THREAD == 0 ) | ( queue_id == S_AXI_AID_Q);
assign cmd_id_check = (cmd_empty & cmd_b_empty) | ( id_match & (~cmd_empty | ~cmd_b_empty) );
// Command type affects possibility to push immediately or wait.
assign allow_split_cmd = need_to_split_q & cmd_id_check & ~multiple_id_non_split;
assign allow_non_split_cmd = ~need_to_split_q & (cmd_id_check | ~split_in_progress);
assign allow_this_cmd = allow_split_cmd | allow_non_split_cmd | ( C_SINGLE_THREAD == 0 );
// Check if it is allowed to push more commands.
assign allow_new_cmd = (~cmd_full & ~cmd_b_full & allow_this_cmd) |
cmd_push_block;
// Push new command when allowed and MI-side is able to receive the command.
assign cmd_push = M_AXI_AVALID_I & ~cmd_push_block;
assign cmd_b_push = M_AXI_AVALID_I & ~cmd_b_push_block & (C_AXI_CHANNEL == 0);
// Block furter push until command has been forwarded to MI-side.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_push_block <= 1'b0;
end else begin
if ( pushed_new_cmd ) begin
cmd_push_block <= 1'b0;
end else if ( cmd_push & mi_stalling ) begin
cmd_push_block <= 1'b1;
end
end
end
// Block furter push until command has been forwarded to MI-side.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_block <= 1'b0;
end else begin
if ( S_AXI_AREADY_I ) begin
cmd_b_push_block <= 1'b0;
end else if ( cmd_b_push ) begin
cmd_b_push_block <= 1'b1;
end
end
end
// Acknowledge command when we can push it into queue (and forward it).
assign pushed_new_cmd = M_AXI_AVALID_I & M_AXI_AREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue (W/R):
//
// Instantiate a FIFO as the queue and adjust the control signals.
//
// The features from Command FIFO can be reduced depending on configuration:
// Read Channel only need the split information.
// Write Channel always require ID information. When bursts are supported
// Split and Length information is also used.
//
/////////////////////////////////////////////////////////////////////////////
// Instantiated queue.
generate
if ( C_AXI_CHANNEL == 1 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_R_CHANNEL
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(1),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_split_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_split}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_id = {C_AXI_ID_WIDTH{1'b0}};
assign cmd_length = 4'b0;
end else if (C_SUPPORT_BURSTS == 1) begin : USE_BURSTS
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_AXI_ID_WIDTH+4),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_id_i, cmd_length_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_id, cmd_length}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_split = 1'b0;
end else begin : NO_BURSTS
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(C_AXI_ID_WIDTH),
.C_FIFO_TYPE("lut")
)
cmd_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_id_i}),
.S_VALID(cmd_push),
.S_READY(s_ready),
.M_MESG({cmd_id}),
.M_VALID(cmd_valid),
.M_READY(cmd_ready)
);
assign cmd_split = 1'b0;
assign cmd_length = 4'b0;
end
endgenerate
// Queue is concidered full when not ready.
assign cmd_full = ~s_ready;
// Queue is empty when no data at output port.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_empty <= 1'b1;
cmd_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end else begin
if ( cmd_push & ~cmd_ready ) begin
// Push only => Increase depth.
cmd_depth <= cmd_depth + 1'b1;
cmd_empty <= 1'b0;
end else if ( ~cmd_push & cmd_ready ) begin
// Pop only => Decrease depth.
cmd_depth <= cmd_depth - 1'b1;
cmd_empty <= almost_empty;
end
end
end
assign almost_empty = ( cmd_depth == 1 );
/////////////////////////////////////////////////////////////////////////////
// Command Queue (B):
//
// Add command queue for B channel only when it is AW channel and both burst
// and splitting is supported.
//
// When turned off the command appears always empty.
//
/////////////////////////////////////////////////////////////////////////////
// Instantiated queue.
generate
if ( C_AXI_CHANNEL == 0 && C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_B_CHANNEL
wire cmd_b_valid_i;
wire s_b_ready;
axi_data_fifo_v2_1_axic_fifo #
(
.C_FAMILY(C_FAMILY),
.C_FIFO_DEPTH_LOG(C_FIFO_DEPTH_LOG),
.C_FIFO_WIDTH(1+4),
.C_FIFO_TYPE("lut")
)
cmd_b_queue
(
.ACLK(ACLK),
.ARESET(ARESET),
.S_MESG({cmd_b_split_i, cmd_b_repeat_i}),
.S_VALID(cmd_b_push),
.S_READY(s_b_ready),
.M_MESG({cmd_b_split, cmd_b_repeat}),
.M_VALID(cmd_b_valid_i),
.M_READY(cmd_b_ready)
);
// Queue is concidered full when not ready.
assign cmd_b_full = ~s_b_ready;
// Queue is empty when no data at output port.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_empty <= 1'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end else begin
if ( cmd_b_push & ~cmd_b_ready ) begin
// Push only => Increase depth.
cmd_b_depth <= cmd_b_depth + 1'b1;
cmd_b_empty <= 1'b0;
end else if ( ~cmd_b_push & cmd_b_ready ) begin
// Pop only => Decrease depth.
cmd_b_depth <= cmd_b_depth - 1'b1;
cmd_b_empty <= ( cmd_b_depth == 1 );
end
end
end
assign almost_b_empty = ( cmd_b_depth == 1 );
// Assign external signal.
assign cmd_b_valid = cmd_b_valid_i;
end else begin : NO_B_CHANNEL
// Assign external command signals.
assign cmd_b_valid = 1'b0;
assign cmd_b_split = 1'b0;
assign cmd_b_repeat = 4'b0;
// Assign internal command FIFO signals.
assign cmd_b_full = 1'b0;
assign almost_b_empty = 1'b0;
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_empty <= 1'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end else begin
// Constant FF due to ModelSim behavior.
cmd_b_empty <= 1'b1;
cmd_b_depth <= {C_FIFO_DEPTH_LOG+1{1'b0}};
end
end
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
assign M_AXI_AID = M_AXI_AID_I;
assign M_AXI_AADDR = M_AXI_AADDR_I;
assign M_AXI_ALEN = M_AXI_ALEN_I;
assign M_AXI_ASIZE = M_AXI_ASIZE_I;
assign M_AXI_ABURST = M_AXI_ABURST_I;
assign M_AXI_ALOCK = M_AXI_ALOCK_I;
assign M_AXI_ACACHE = M_AXI_ACACHE_I;
assign M_AXI_APROT = M_AXI_APROT_I;
assign M_AXI_AQOS = M_AXI_AQOS_I;
assign M_AXI_AUSER = M_AXI_AUSER_I;
assign M_AXI_AVALID = M_AXI_AVALID_I;
assign M_AXI_AREADY_I = M_AXI_AREADY;
endmodule
|
module all;
reg pass;
task automatic check;
input sig;
input val;
input [32*8:1] name;
begin
if (sig !== val) begin
$display("FAILED \"%0s\", expected %b, got %b", name, val, sig);
pass = 1'b0;
end
end
endtask
initial begin
pass = 1'b1;
#100;
if (pass) $display("PASSED");
end
endmodule
/* Check the wire net type. */
`default_nettype wire
module top_wire;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1'b0; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "wire(0,0)");
in0 = 1'b0; in1 = 1'b1;
#1 all.check(tmp, 1'bx, "wire(0,1)");
in0 = 1'b0; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "wire(0,x)");
in0 = 1'b0; in1 = 1'bz;
#1 all.check(tmp, 1'b0, "wire(0,z)");
in0 = 1'b1; in1 = 1'b0;
#1 all.check(tmp, 1'bx, "wire(1,0)");
in0 = 1'b1; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "wire(1,1)");
in0 = 1'b1; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "wire(1,x)");
in0 = 1'b1; in1 = 1'bz;
#1 all.check(tmp, 1'b1, "wire(1,z)");
in0 = 1'bx; in1 = 1'b0;
#1 all.check(tmp, 1'bx, "wire(x,0)");
in0 = 1'bx; in1 = 1'b1;
#1 all.check(tmp, 1'bx, "wire(x,1)");
in0 = 1'bx; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "wire(x,x)");
in0 = 1'bx; in1 = 1'bz;
#1 all.check(tmp, 1'bx, "wire(x,z)");
in0 = 1'bz; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "wire(z,0)");
in0 = 1'bz; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "wire(z,1)");
in0 = 1'bz; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "wire(z,x)");
in0 = 1'bz; in1 = 1'bz;
#1 all.check(tmp, 1'bz, "wire(z,z)");
end
endmodule
/* Check the tri net type (should be identical to wire). */
`default_nettype tri
module top_tri;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1'b0; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "tri(0,0)");
in0 = 1'b0; in1 = 1'b1;
#1 all.check(tmp, 1'bx, "tri(0,1)");
in0 = 1'b0; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "tri(0,x)");
in0 = 1'b0; in1 = 1'bz;
#1 all.check(tmp, 1'b0, "tri(0,z)");
in0 = 1'b1; in1 = 1'b0;
#1 all.check(tmp, 1'bx, "tri(1,0)");
in0 = 1'b1; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "tri(1,1)");
in0 = 1'b1; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "tri(1,x)");
in0 = 1'b1; in1 = 1'bz;
#1 all.check(tmp, 1'b1, "tri(1,z)");
in0 = 1'bx; in1 = 1'b0;
#1 all.check(tmp, 1'bx, "tri(x,0)");
in0 = 1'bx; in1 = 1'b1;
#1 all.check(tmp, 1'bx, "tri(x,1)");
in0 = 1'bx; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "tri(x,x)");
in0 = 1'bx; in1 = 1'bz;
#1 all.check(tmp, 1'bx, "tri(x,z)");
in0 = 1'bz; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "tri(z,0)");
in0 = 1'bz; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "tri(z,1)");
in0 = 1'bz; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "tri(z,x)");
in0 = 1'bz; in1 = 1'bz;
#1 all.check(tmp, 1'bz, "tri(z,z)");
end
endmodule
/* Check the tri0 net type (should be the same as tri except z,z is 0). */
`default_nettype tri0
module top_tri0;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1'b0; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "tri0(0,0)");
in0 = 1'b0; in1 = 1'b1;
#1 all.check(tmp, 1'bx, "tri0(0,1)");
in0 = 1'b0; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "tri0(0,x)");
in0 = 1'b0; in1 = 1'bz;
#1 all.check(tmp, 1'b0, "tri0(0,z)");
in0 = 1'b1; in1 = 1'b0;
#1 all.check(tmp, 1'bx, "tri0(1,0)");
in0 = 1'b1; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "tri0(1,1)");
in0 = 1'b1; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "tri0(1,x)");
in0 = 1'b1; in1 = 1'bz;
#1 all.check(tmp, 1'b1, "tri0(1,z)");
in0 = 1'bx; in1 = 1'b0;
#1 all.check(tmp, 1'bx, "tri0(x,0)");
in0 = 1'bx; in1 = 1'b1;
#1 all.check(tmp, 1'bx, "tri0(x,1)");
in0 = 1'bx; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "tri0(x,x)");
in0 = 1'bx; in1 = 1'bz;
#1 all.check(tmp, 1'bx, "tri0(x,z)");
in0 = 1'bz; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "tri0(z,0)");
in0 = 1'bz; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "tri0(z,1)");
in0 = 1'bz; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "tri0(z,x)");
in0 = 1'bz; in1 = 1'bz;
#1 all.check(tmp, 1'b0, "tri0(z,z)");
end
endmodule
/* Check the tri1 net type (should be the same as tri except z,z is 1). */
`default_nettype tri1
module top_tri1;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1'b0; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "tri1(0,0)");
in0 = 1'b0; in1 = 1'b1;
#1 all.check(tmp, 1'bx, "tri1(0,1)");
in0 = 1'b0; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "tri1(0,x)");
in0 = 1'b0; in1 = 1'bz;
#1 all.check(tmp, 1'b0, "tri1(0,z)");
in0 = 1'b1; in1 = 1'b0;
#1 all.check(tmp, 1'bx, "tri1(1,0)");
in0 = 1'b1; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "tri1(1,1)");
in0 = 1'b1; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "tri1(1,x)");
in0 = 1'b1; in1 = 1'bz;
#1 all.check(tmp, 1'b1, "tri1(1,z)");
in0 = 1'bx; in1 = 1'b0;
#1 all.check(tmp, 1'bx, "tri1(x,0)");
in0 = 1'bx; in1 = 1'b1;
#1 all.check(tmp, 1'bx, "tri1(x,1)");
in0 = 1'bx; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "tri1(x,x)");
in0 = 1'bx; in1 = 1'bz;
#1 all.check(tmp, 1'bx, "tri1(x,z)");
in0 = 1'bz; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "tri1(z,0)");
in0 = 1'bz; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "tri1(z,1)");
in0 = 1'bz; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "tri1(z,x)");
in0 = 1'bz; in1 = 1'bz;
#1 all.check(tmp, 1'b1, "tri1(z,z)");
end
endmodule
/* Check the wand net type. */
`default_nettype wand
module top_wand;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1'b0; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "wand(0,0)");
in0 = 1'b0; in1 = 1'b1;
#1 all.check(tmp, 1'b0, "wand(0,1)");
in0 = 1'b0; in1 = 1'bx;
#1 all.check(tmp, 1'b0, "wand(0,x)");
in0 = 1'b0; in1 = 1'bz;
#1 all.check(tmp, 1'b0, "wand(0,z)");
in0 = 1'b1; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "wand(1,0)");
in0 = 1'b1; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "wand(1,1)");
in0 = 1'b1; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "wand(1,x)");
in0 = 1'b1; in1 = 1'bz;
#1 all.check(tmp, 1'b1, "wand(1,z)");
in0 = 1'bx; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "wand(x,0)");
in0 = 1'bx; in1 = 1'b1;
#1 all.check(tmp, 1'bx, "wand(x,1)");
in0 = 1'bx; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "wand(x,x)");
in0 = 1'bx; in1 = 1'bz;
#1 all.check(tmp, 1'bx, "wand(x,z)");
in0 = 1'bz; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "wand(z,0)");
in0 = 1'bz; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "wand(z,1)");
in0 = 1'bz; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "wand(z,x)");
in0 = 1'bz; in1 = 1'bz;
#1 all.check(tmp, 1'bz, "wand(z,z)");
end
endmodule
/* Check the triand net type (should be the same as wand). */
`default_nettype triand
module top_triand;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1'b0; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "triand(0,0)");
in0 = 1'b0; in1 = 1'b1;
#1 all.check(tmp, 1'b0, "triand(0,1)");
in0 = 1'b0; in1 = 1'bx;
#1 all.check(tmp, 1'b0, "triand(0,x)");
in0 = 1'b0; in1 = 1'bz;
#1 all.check(tmp, 1'b0, "triand(0,z)");
in0 = 1'b1; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "triand(1,0)");
in0 = 1'b1; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "triand(1,1)");
in0 = 1'b1; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "triand(1,x)");
in0 = 1'b1; in1 = 1'bz;
#1 all.check(tmp, 1'b1, "triand(1,z)");
in0 = 1'bx; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "triand(x,0)");
in0 = 1'bx; in1 = 1'b1;
#1 all.check(tmp, 1'bx, "triand(x,1)");
in0 = 1'bx; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "triand(x,x)");
in0 = 1'bx; in1 = 1'bz;
#1 all.check(tmp, 1'bx, "triand(x,z)");
in0 = 1'bz; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "triand(z,0)");
in0 = 1'bz; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "triand(z,1)");
in0 = 1'bz; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "triand(z,x)");
in0 = 1'bz; in1 = 1'bz;
#1 all.check(tmp, 1'bz, "triand(z,z)");
end
endmodule
/* Check the wor net type. */
`default_nettype wor
module top_wor;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1'b0; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "wor(0,0)");
in0 = 1'b0; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "wor(0,1)");
in0 = 1'b0; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "wor(0,x)");
in0 = 1'b0; in1 = 1'bz;
#1 all.check(tmp, 1'b0, "wor(0,z)");
in0 = 1'b1; in1 = 1'b0;
#1 all.check(tmp, 1'b1, "wor(1,0)");
in0 = 1'b1; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "wor(1,1)");
in0 = 1'b1; in1 = 1'bx;
#1 all.check(tmp, 1'b1, "wor(1,x)");
in0 = 1'b1; in1 = 1'bz;
#1 all.check(tmp, 1'b1, "wor(1,z)");
in0 = 1'bx; in1 = 1'b0;
#1 all.check(tmp, 1'bx, "wor(x,0)");
in0 = 1'bx; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "wor(x,1)");
in0 = 1'bx; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "wor(x,x)");
in0 = 1'bx; in1 = 1'bz;
#1 all.check(tmp, 1'bx, "wor(x,z)");
in0 = 1'bz; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "wor(z,0)");
in0 = 1'bz; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "wor(z,1)");
in0 = 1'bz; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "wor(z,x)");
in0 = 1'bz; in1 = 1'bz;
#1 all.check(tmp, 1'bz, "wor(z,z)");
end
endmodule
/* Check the trior net type (should be the same as wor). */
`default_nettype trior
module top_trior;
reg in0, in1;
assign tmp = in0;
assign tmp = in1;
initial begin
in0 = 1'b0; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "trior(0,0)");
in0 = 1'b0; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "trior(0,1)");
in0 = 1'b0; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "trior(0,x)");
in0 = 1'b0; in1 = 1'bz;
#1 all.check(tmp, 1'b0, "trior(0,z)");
in0 = 1'b1; in1 = 1'b0;
#1 all.check(tmp, 1'b1, "trior(1,0)");
in0 = 1'b1; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "trior(1,1)");
in0 = 1'b1; in1 = 1'bx;
#1 all.check(tmp, 1'b1, "trior(1,x)");
in0 = 1'b1; in1 = 1'bz;
#1 all.check(tmp, 1'b1, "trior(1,z)");
in0 = 1'bx; in1 = 1'b0;
#1 all.check(tmp, 1'bx, "trior(x,0)");
in0 = 1'bx; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "trior(x,1)");
in0 = 1'bx; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "trior(x,x)");
in0 = 1'bx; in1 = 1'bz;
#1 all.check(tmp, 1'bx, "trior(x,z)");
in0 = 1'bz; in1 = 1'b0;
#1 all.check(tmp, 1'b0, "trior(z,0)");
in0 = 1'bz; in1 = 1'b1;
#1 all.check(tmp, 1'b1, "trior(z,1)");
in0 = 1'bz; in1 = 1'bx;
#1 all.check(tmp, 1'bx, "trior(z,x)");
in0 = 1'bz; in1 = 1'bz;
#1 all.check(tmp, 1'bz, "trior(z,z)");
end
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2012 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import Bool NAxioms NSub NPow NDiv NParity NLog.
(** Derived properties of bitwise operations *)
Module Type NBitsProp
(Import A : NAxiomsSig')
(Import B : NSubProp A)
(Import C : NParityProp A B)
(Import D : NPowProp A B C)
(Import E : NDivProp A B)
(Import F : NLog2Prop A B C D).
Include BoolEqualityFacts A.
Ltac order_nz := try apply pow_nonzero; order'.
Hint Rewrite div_0_l mod_0_l div_1_r mod_1_r : nz.
(** Some properties of power and division *)
Lemma pow_sub_r : forall a b c, a~=0 -> c<=b -> a^(b-c) == a^b / a^c.
Proof.
intros a b c Ha H.
apply div_unique with 0.
generalize (pow_nonzero a c Ha) (le_0_l (a^c)); order'.
nzsimpl. now rewrite <- pow_add_r, add_comm, sub_add.
Qed.
Lemma pow_div_l : forall a b c, b~=0 -> a mod b == 0 ->
(a/b)^c == a^c / b^c.
Proof.
intros a b c Hb H.
apply div_unique with 0.
generalize (pow_nonzero b c Hb) (le_0_l (b^c)); order'.
nzsimpl. rewrite <- pow_mul_l. f_equiv. now apply div_exact.
Qed.
(** An injection from bits [true] and [false] to numbers 1 and 0.
We declare it as a (local) coercion for shorter statements. *)
Definition b2n (b:bool) := if b then 1 else 0.
Local Coercion b2n : bool >-> t.
Instance b2n_proper : Proper (Logic.eq ==> eq) b2n.
Proof. solve_proper. Qed.
Lemma exists_div2 a : exists a' (b:bool), a == 2*a' + b.
Proof.
elim (Even_or_Odd a); [intros (a',H)| intros (a',H)].
exists a'. exists false. now nzsimpl.
exists a'. exists true. now simpl.
Qed.
(** We can compact [testbit_odd_0] [testbit_even_0]
[testbit_even_succ] [testbit_odd_succ] in only two lemmas. *)
Lemma testbit_0_r a (b:bool) : testbit (2*a+b) 0 = b.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_0.
apply testbit_even_0.
Qed.
Lemma testbit_succ_r a (b:bool) n :
testbit (2*a+b) (succ n) = testbit a n.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_succ, le_0_l.
apply testbit_even_succ, le_0_l.
Qed.
(** Alternative caracterisations of [testbit] *)
(** This concise equation could have been taken as specification
for testbit in the interface, but it would have been hard to
implement with little initial knowledge about div and mod *)
Lemma testbit_spec' a n : a.[n] == (a / 2^n) mod 2.
Proof.
revert a. induct n.
intros a. nzsimpl.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_0_r. apply mod_unique with a'; trivial.
destruct b; order'.
intros n IH a.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_succ_r, IH. f_equiv.
rewrite pow_succ_r', <- div_div by order_nz. f_equiv.
apply div_unique with b; trivial.
destruct b; order'.
Qed.
(** This caracterisation that uses only basic operations and
power was initially taken as specification for testbit.
We describe [a] as having a low part and a high part, with
the corresponding bit in the middle. This caracterisation
is moderatly complex to implement, but also moderately
usable... *)
Lemma testbit_spec a n :
exists l h, 0<=l<2^n /\ a == l + (a.[n] + 2*h)*2^n.
Proof.
exists (a mod 2^n). exists (a / 2^n / 2). split.
split; [apply le_0_l | apply mod_upper_bound; order_nz].
rewrite add_comm, mul_comm, (add_comm a.[n]).
rewrite (div_mod a (2^n)) at 1 by order_nz. do 2 f_equiv.
rewrite testbit_spec'. apply div_mod. order'.
Qed.
Lemma testbit_true : forall a n,
a.[n] = true <-> (a / 2^n) mod 2 == 1.
Proof.
intros a n.
rewrite <- testbit_spec'; destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_false : forall a n,
a.[n] = false <-> (a / 2^n) mod 2 == 0.
Proof.
intros a n.
rewrite <- testbit_spec'; destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_eqb : forall a n,
a.[n] = eqb ((a / 2^n) mod 2) 1.
Proof.
intros a n.
apply eq_true_iff_eq. now rewrite testbit_true, eqb_eq.
Qed.
(** Results about the injection [b2n] *)
Lemma b2n_inj : forall (a0 b0:bool), a0 == b0 -> a0 = b0.
Proof.
intros [|] [|]; simpl; trivial; order'.
Qed.
Lemma add_b2n_double_div2 : forall (a0:bool) a, (a0+2*a)/2 == a.
Proof.
intros a0 a. rewrite mul_comm, div_add by order'.
now rewrite div_small, add_0_l by (destruct a0; order').
Qed.
Lemma add_b2n_double_bit0 : forall (a0:bool) a, (a0+2*a).[0] = a0.
Proof.
intros a0 a. apply b2n_inj.
rewrite testbit_spec'. nzsimpl. rewrite mul_comm, mod_add by order'.
now rewrite mod_small by (destruct a0; order').
Qed.
Lemma b2n_div2 : forall (a0:bool), a0/2 == 0.
Proof.
intros a0. rewrite <- (add_b2n_double_div2 a0 0). now nzsimpl.
Qed.
Lemma b2n_bit0 : forall (a0:bool), a0.[0] = a0.
Proof.
intros a0. rewrite <- (add_b2n_double_bit0 a0 0) at 2. now nzsimpl.
Qed.
(** The specification of testbit by low and high parts is complete *)
Lemma testbit_unique : forall a n (a0:bool) l h,
l<2^n -> a == l + (a0 + 2*h)*2^n -> a.[n] = a0.
Proof.
intros a n a0 l h Hl EQ.
apply b2n_inj. rewrite testbit_spec' by trivial.
symmetry. apply mod_unique with h. destruct a0; simpl; order'.
symmetry. apply div_unique with l; trivial.
now rewrite add_comm, (add_comm _ a0), mul_comm.
Qed.
(** All bits of number 0 are 0 *)
Lemma bits_0 : forall n, 0.[n] = false.
Proof.
intros n. apply testbit_false. nzsimpl; order_nz.
Qed.
(** Various ways to refer to the lowest bit of a number *)
Lemma bit0_odd : forall a, a.[0] = odd a.
Proof.
intros. symmetry.
destruct (exists_div2 a) as (a' & b & EQ).
rewrite EQ, testbit_0_r, add_comm, odd_add_mul_2.
destruct b; simpl; apply odd_1 || apply odd_0.
Qed.
Lemma bit0_eqb : forall a, a.[0] = eqb (a mod 2) 1.
Proof.
intros a. rewrite testbit_eqb. now nzsimpl.
Qed.
Lemma bit0_mod : forall a, a.[0] == a mod 2.
Proof.
intros a. rewrite testbit_spec'. now nzsimpl.
Qed.
(** Hence testing a bit is equivalent to shifting and testing parity *)
Lemma testbit_odd : forall a n, a.[n] = odd (a>>n).
Proof.
intros. now rewrite <- bit0_odd, shiftr_spec, add_0_l.
Qed.
(** [log2] gives the highest nonzero bit *)
Lemma bit_log2 : forall a, a~=0 -> a.[log2 a] = true.
Proof.
intros a Ha.
assert (Ha' : 0 < a) by (generalize (le_0_l a); order).
destruct (log2_spec_alt a Ha') as (r & EQ & (_,Hr)).
rewrite EQ at 1.
rewrite testbit_true, add_comm.
rewrite <- (mul_1_l (2^log2 a)) at 1.
rewrite div_add by order_nz.
rewrite div_small by trivial.
rewrite add_0_l. apply mod_small. order'.
Qed.
Lemma bits_above_log2 : forall a n, log2 a < n ->
a.[n] = false.
Proof.
intros a n H.
rewrite testbit_false.
rewrite div_small. nzsimpl; order'.
apply log2_lt_cancel. rewrite log2_pow2; trivial using le_0_l.
Qed.
(** Hence the number of bits of [a] is [1+log2 a]
(see [Pos.size_nat] and [Pos.size]).
*)
(** Testing bits after division or multiplication by a power of two *)
Lemma div2_bits : forall a n, (a/2).[n] = a.[S n].
Proof.
intros. apply eq_true_iff_eq.
rewrite 2 testbit_true.
rewrite pow_succ_r by apply le_0_l.
now rewrite div_div by order_nz.
Qed.
Lemma div_pow2_bits : forall a n m, (a/2^n).[m] = a.[m+n].
Proof.
intros a n. revert a. induct n.
intros a m. now nzsimpl.
intros n IH a m. nzsimpl; try apply le_0_l.
rewrite <- div_div by order_nz.
now rewrite IH, div2_bits.
Qed.
Lemma double_bits_succ : forall a n, (2*a).[S n] = a.[n].
Proof.
intros. rewrite <- div2_bits. now rewrite mul_comm, div_mul by order'.
Qed.
Lemma mul_pow2_bits_add : forall a n m, (a*2^n).[m+n] = a.[m].
Proof.
intros. rewrite <- div_pow2_bits. now rewrite div_mul by order_nz.
Qed.
Lemma mul_pow2_bits_high : forall a n m, n<=m -> (a*2^n).[m] = a.[m-n].
Proof.
intros.
rewrite <- (sub_add n m) at 1 by order'.
now rewrite mul_pow2_bits_add.
Qed.
Lemma mul_pow2_bits_low : forall a n m, m<n -> (a*2^n).[m] = false.
Proof.
intros. apply testbit_false.
rewrite <- (sub_add m n) by order'. rewrite pow_add_r, mul_assoc.
rewrite div_mul by order_nz.
rewrite <- (succ_pred (n-m)). rewrite pow_succ_r.
now rewrite (mul_comm 2), mul_assoc, mod_mul by order'.
apply lt_le_pred.
apply sub_gt in H. generalize (le_0_l (n-m)); order.
now apply sub_gt.
Qed.
(** Selecting the low part of a number can be done by a modulo *)
Lemma mod_pow2_bits_high : forall a n m, n<=m ->
(a mod 2^n).[m] = false.
Proof.
intros a n m H.
destruct (eq_0_gt_0_cases (a mod 2^n)) as [EQ|LT].
now rewrite EQ, bits_0.
apply bits_above_log2.
apply lt_le_trans with n; trivial.
apply log2_lt_pow2; trivial.
apply mod_upper_bound; order_nz.
Qed.
Lemma mod_pow2_bits_low : forall a n m, m<n ->
(a mod 2^n).[m] = a.[m].
Proof.
intros a n m H.
rewrite testbit_eqb.
rewrite <- (mod_add _ (2^(P (n-m))*(a/2^n))) by order'.
rewrite <- div_add by order_nz.
rewrite (mul_comm _ 2), mul_assoc, <- pow_succ_r', succ_pred
by now apply sub_gt.
rewrite mul_comm, mul_assoc, <- pow_add_r, (add_comm m), sub_add
by order.
rewrite add_comm, <- div_mod by order_nz.
symmetry. apply testbit_eqb.
Qed.
(** We now prove that having the same bits implies equality.
For that we use a notion of equality over functional
streams of bits. *)
Definition eqf (f g:t -> bool) := forall n:t, f n = g n.
Instance eqf_equiv : Equivalence eqf.
Proof.
split; congruence.
Qed.
Local Infix "===" := eqf (at level 70, no associativity).
Instance testbit_eqf : Proper (eq==>eqf) testbit.
Proof.
intros a a' Ha n. now rewrite Ha.
Qed.
(** Only zero corresponds to the always-false stream. *)
Lemma bits_inj_0 :
forall a, (forall n, a.[n] = false) -> a == 0.
Proof.
intros a H. destruct (eq_decidable a 0) as [EQ|NEQ]; trivial.
apply bit_log2 in NEQ. now rewrite H in NEQ.
Qed.
(** If two numbers produce the same stream of bits, they are equal. *)
Lemma bits_inj : forall a b, testbit a === testbit b -> a == b.
Proof.
intros a. pattern a.
apply strong_right_induction with 0;[solve_proper|clear a|apply le_0_l].
intros a _ IH b H.
destruct (eq_0_gt_0_cases a) as [EQ|LT].
rewrite EQ in H |- *. symmetry. apply bits_inj_0.
intros n. now rewrite <- H, bits_0.
rewrite (div_mod a 2), (div_mod b 2) by order'.
f_equiv; [ | now rewrite <- 2 bit0_mod, H].
f_equiv.
apply IH; trivial using le_0_l.
apply div_lt; order'.
intro n. rewrite 2 div2_bits. apply H.
Qed.
Lemma bits_inj_iff : forall a b, testbit a === testbit b <-> a == b.
Proof.
split. apply bits_inj. intros EQ; now rewrite EQ.
Qed.
Hint Rewrite lxor_spec lor_spec land_spec ldiff_spec bits_0 : bitwise.
Ltac bitwise := apply bits_inj; intros ?m; autorewrite with bitwise.
(** The streams of bits that correspond to a natural numbers are
exactly the ones that are always 0 after some point *)
Lemma are_bits : forall (f:t->bool), Proper (eq==>Logic.eq) f ->
((exists n, f === testbit n) <->
(exists k, forall m, k<=m -> f m = false)).
Proof.
intros f Hf. split.
intros (a,H).
exists (S (log2 a)). intros m Hm. apply le_succ_l in Hm.
rewrite H, bits_above_log2; trivial using lt_succ_diag_r.
intros (k,Hk).
revert f Hf Hk. induct k.
intros f Hf H0.
exists 0. intros m. rewrite bits_0, H0; trivial. apply le_0_l.
intros k IH f Hf Hk.
destruct (IH (fun m => f (S m))) as (n, Hn).
solve_proper.
intros m Hm. apply Hk. now rewrite <- succ_le_mono.
exists (f 0 + 2*n). intros m.
destruct (zero_or_succ m) as [Hm|(m', Hm)]; rewrite Hm.
symmetry. apply add_b2n_double_bit0.
rewrite Hn, <- div2_bits.
rewrite mul_comm, div_add, b2n_div2, add_0_l; trivial. order'.
Qed.
(** Properties of shifts *)
Lemma shiftr_spec' : forall a n m, (a >> n).[m] = a.[m+n].
Proof.
intros. apply shiftr_spec. apply le_0_l.
Qed.
Lemma shiftl_spec_high' : forall a n m, n<=m -> (a << n).[m] = a.[m-n].
Proof.
intros. apply shiftl_spec_high; trivial. apply le_0_l.
Qed.
Lemma shiftr_div_pow2 : forall a n, a >> n == a / 2^n.
Proof.
intros. bitwise. rewrite shiftr_spec'.
symmetry. apply div_pow2_bits.
Qed.
Lemma shiftl_mul_pow2 : forall a n, a << n == a * 2^n.
Proof.
intros. bitwise.
destruct (le_gt_cases n m) as [H|H].
now rewrite shiftl_spec_high', mul_pow2_bits_high.
now rewrite shiftl_spec_low, mul_pow2_bits_low.
Qed.
Lemma shiftl_spec_alt : forall a n m, (a << n).[m+n] = a.[m].
Proof.
intros. now rewrite shiftl_mul_pow2, mul_pow2_bits_add.
Qed.
Instance shiftr_wd : Proper (eq==>eq==>eq) shiftr.
Proof.
intros a a' Ha b b' Hb. now rewrite 2 shiftr_div_pow2, Ha, Hb.
Qed.
Instance shiftl_wd : Proper (eq==>eq==>eq) shiftl.
Proof.
intros a a' Ha b b' Hb. now rewrite 2 shiftl_mul_pow2, Ha, Hb.
Qed.
Lemma shiftl_shiftl : forall a n m,
(a << n) << m == a << (n+m).
Proof.
intros. now rewrite !shiftl_mul_pow2, pow_add_r, mul_assoc.
Qed.
Lemma shiftr_shiftr : forall a n m,
(a >> n) >> m == a >> (n+m).
Proof.
intros.
now rewrite !shiftr_div_pow2, pow_add_r, div_div by order_nz.
Qed.
Lemma shiftr_shiftl_l : forall a n m, m<=n ->
(a << n) >> m == a << (n-m).
Proof.
intros.
rewrite shiftr_div_pow2, !shiftl_mul_pow2.
rewrite <- (sub_add m n) at 1 by trivial.
now rewrite pow_add_r, mul_assoc, div_mul by order_nz.
Qed.
Lemma shiftr_shiftl_r : forall a n m, n<=m ->
(a << n) >> m == a >> (m-n).
Proof.
intros.
rewrite !shiftr_div_pow2, shiftl_mul_pow2.
rewrite <- (sub_add n m) at 1 by trivial.
rewrite pow_add_r, (mul_comm (2^(m-n))).
now rewrite <- div_div, div_mul by order_nz.
Qed.
(** shifts and constants *)
Lemma shiftl_1_l : forall n, 1 << n == 2^n.
Proof.
intros. now rewrite shiftl_mul_pow2, mul_1_l.
Qed.
Lemma shiftl_0_r : forall a, a << 0 == a.
Proof.
intros. rewrite shiftl_mul_pow2. now nzsimpl.
Qed.
Lemma shiftr_0_r : forall a, a >> 0 == a.
Proof.
intros. rewrite shiftr_div_pow2. now nzsimpl.
Qed.
Lemma shiftl_0_l : forall n, 0 << n == 0.
Proof.
intros. rewrite shiftl_mul_pow2. now nzsimpl.
Qed.
Lemma shiftr_0_l : forall n, 0 >> n == 0.
Proof.
intros. rewrite shiftr_div_pow2. nzsimpl; order_nz.
Qed.
Lemma shiftl_eq_0_iff : forall a n, a << n == 0 <-> a == 0.
Proof.
intros a n. rewrite shiftl_mul_pow2. rewrite eq_mul_0. split.
intros [H | H]; trivial. contradict H; order_nz.
intros H. now left.
Qed.
Lemma shiftr_eq_0_iff : forall a n,
a >> n == 0 <-> a==0 \/ (0<a /\ log2 a < n).
Proof.
intros a n.
rewrite shiftr_div_pow2, div_small_iff by order_nz.
destruct (eq_0_gt_0_cases a) as [EQ|LT].
rewrite EQ. split. now left. intros _.
assert (H : 2~=0) by order'.
generalize (pow_nonzero 2 n H) (le_0_l (2^n)); order.
rewrite log2_lt_pow2; trivial.
split. right; split; trivial. intros [H|[_ H]]; now order.
Qed.
Lemma shiftr_eq_0 : forall a n, log2 a < n -> a >> n == 0.
Proof.
intros a n H. rewrite shiftr_eq_0_iff.
destruct (eq_0_gt_0_cases a) as [EQ|LT]. now left. right; now split.
Qed.
(** Properties of [div2]. *)
Lemma div2_div : forall a, div2 a == a/2.
Proof.
intros. rewrite div2_spec, shiftr_div_pow2. now nzsimpl.
Qed.
Instance div2_wd : Proper (eq==>eq) div2.
Proof.
intros a a' Ha. now rewrite 2 div2_div, Ha.
Qed.
Lemma div2_odd : forall a, a == 2*(div2 a) + odd a.
Proof.
intros a. rewrite div2_div, <- bit0_odd, bit0_mod.
apply div_mod. order'.
Qed.
(** Properties of [lxor] and others, directly deduced
from properties of [xorb] and others. *)
Instance lxor_wd : Proper (eq ==> eq ==> eq) lxor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance land_wd : Proper (eq ==> eq ==> eq) land.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance lor_wd : Proper (eq ==> eq ==> eq) lor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance ldiff_wd : Proper (eq ==> eq ==> eq) ldiff.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Lemma lxor_eq : forall a a', lxor a a' == 0 -> a == a'.
Proof.
intros a a' H. bitwise. apply xorb_eq.
now rewrite <- lxor_spec, H, bits_0.
Qed.
Lemma lxor_nilpotent : forall a, lxor a a == 0.
Proof.
intros. bitwise. apply xorb_nilpotent.
Qed.
Lemma lxor_eq_0_iff : forall a a', lxor a a' == 0 <-> a == a'.
Proof.
split. apply lxor_eq. intros EQ; rewrite EQ; apply lxor_nilpotent.
Qed.
Lemma lxor_0_l : forall a, lxor 0 a == a.
Proof.
intros. bitwise. apply xorb_false_l.
Qed.
Lemma lxor_0_r : forall a, lxor a 0 == a.
Proof.
intros. bitwise. apply xorb_false_r.
Qed.
Lemma lxor_comm : forall a b, lxor a b == lxor b a.
Proof.
intros. bitwise. apply xorb_comm.
Qed.
Lemma lxor_assoc :
forall a b c, lxor (lxor a b) c == lxor a (lxor b c).
Proof.
intros. bitwise. apply xorb_assoc.
Qed.
Lemma lor_0_l : forall a, lor 0 a == a.
Proof.
intros. bitwise. trivial.
Qed.
Lemma lor_0_r : forall a, lor a 0 == a.
Proof.
intros. bitwise. apply orb_false_r.
Qed.
Lemma lor_comm : forall a b, lor a b == lor b a.
Proof.
intros. bitwise. apply orb_comm.
Qed.
Lemma lor_assoc :
forall a b c, lor a (lor b c) == lor (lor a b) c.
Proof.
intros. bitwise. apply orb_assoc.
Qed.
Lemma lor_diag : forall a, lor a a == a.
Proof.
intros. bitwise. apply orb_diag.
Qed.
Lemma lor_eq_0_l : forall a b, lor a b == 0 -> a == 0.
Proof.
intros a b H. bitwise.
apply (orb_false_iff a.[m] b.[m]).
now rewrite <- lor_spec, H, bits_0.
Qed.
Lemma lor_eq_0_iff : forall a b, lor a b == 0 <-> a == 0 /\ b == 0.
Proof.
intros a b. split.
split. now apply lor_eq_0_l in H.
rewrite lor_comm in H. now apply lor_eq_0_l in H.
intros (EQ,EQ'). now rewrite EQ, lor_0_l.
Qed.
Lemma land_0_l : forall a, land 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma land_0_r : forall a, land a 0 == 0.
Proof.
intros. bitwise. apply andb_false_r.
Qed.
Lemma land_comm : forall a b, land a b == land b a.
Proof.
intros. bitwise. apply andb_comm.
Qed.
Lemma land_assoc :
forall a b c, land a (land b c) == land (land a b) c.
Proof.
intros. bitwise. apply andb_assoc.
Qed.
Lemma land_diag : forall a, land a a == a.
Proof.
intros. bitwise. apply andb_diag.
Qed.
Lemma ldiff_0_l : forall a, ldiff 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma ldiff_0_r : forall a, ldiff a 0 == a.
Proof.
intros. bitwise. now rewrite andb_true_r.
Qed.
Lemma ldiff_diag : forall a, ldiff a a == 0.
Proof.
intros. bitwise. apply andb_negb_r.
Qed.
Lemma lor_land_distr_l : forall a b c,
lor (land a b) c == land (lor a c) (lor b c).
Proof.
intros. bitwise. apply orb_andb_distrib_l.
Qed.
Lemma lor_land_distr_r : forall a b c,
lor a (land b c) == land (lor a b) (lor a c).
Proof.
intros. bitwise. apply orb_andb_distrib_r.
Qed.
Lemma land_lor_distr_l : forall a b c,
land (lor a b) c == lor (land a c) (land b c).
Proof.
intros. bitwise. apply andb_orb_distrib_l.
Qed.
Lemma land_lor_distr_r : forall a b c,
land a (lor b c) == lor (land a b) (land a c).
Proof.
intros. bitwise. apply andb_orb_distrib_r.
Qed.
Lemma ldiff_ldiff_l : forall a b c,
ldiff (ldiff a b) c == ldiff a (lor b c).
Proof.
intros. bitwise. now rewrite negb_orb, andb_assoc.
Qed.
Lemma lor_ldiff_and : forall a b,
lor (ldiff a b) (land a b) == a.
Proof.
intros. bitwise.
now rewrite <- andb_orb_distrib_r, orb_comm, orb_negb_r, andb_true_r.
Qed.
Lemma land_ldiff : forall a b,
land (ldiff a b) b == 0.
Proof.
intros. bitwise.
now rewrite <-andb_assoc, (andb_comm (negb _)), andb_negb_r, andb_false_r.
Qed.
(** Properties of [setbit] and [clearbit] *)
Definition setbit a n := lor a (1<<n).
Definition clearbit a n := ldiff a (1<<n).
Lemma setbit_spec' : forall a n, setbit a n == lor a (2^n).
Proof.
intros. unfold setbit. now rewrite shiftl_1_l.
Qed.
Lemma clearbit_spec' : forall a n, clearbit a n == ldiff a (2^n).
Proof.
intros. unfold clearbit. now rewrite shiftl_1_l.
Qed.
Instance setbit_wd : Proper (eq==>eq==>eq) setbit.
Proof. unfold setbit. solve_proper. Qed.
Instance clearbit_wd : Proper (eq==>eq==>eq) clearbit.
Proof. unfold clearbit. solve_proper. Qed.
Lemma pow2_bits_true : forall n, (2^n).[n] = true.
Proof.
intros. rewrite <- (mul_1_l (2^n)). rewrite <- (add_0_l n) at 2.
now rewrite mul_pow2_bits_add, bit0_odd, odd_1.
Qed.
Lemma pow2_bits_false : forall n m, n~=m -> (2^n).[m] = false.
Proof.
intros.
rewrite <- (mul_1_l (2^n)).
destruct (le_gt_cases n m).
rewrite mul_pow2_bits_high; trivial.
rewrite <- (succ_pred (m-n)) by (apply sub_gt; order).
now rewrite <- div2_bits, div_small, bits_0 by order'.
rewrite mul_pow2_bits_low; trivial.
Qed.
Lemma pow2_bits_eqb : forall n m, (2^n).[m] = eqb n m.
Proof.
intros. apply eq_true_iff_eq. rewrite eqb_eq. split.
destruct (eq_decidable n m) as [H|H]. trivial.
now rewrite (pow2_bits_false _ _ H).
intros EQ. rewrite EQ. apply pow2_bits_true.
Qed.
Lemma setbit_eqb : forall a n m,
(setbit a n).[m] = eqb n m || a.[m].
Proof.
intros. now rewrite setbit_spec', lor_spec, pow2_bits_eqb, orb_comm.
Qed.
Lemma setbit_iff : forall a n m,
(setbit a n).[m] = true <-> n==m \/ a.[m] = true.
Proof.
intros. now rewrite setbit_eqb, orb_true_iff, eqb_eq.
Qed.
Lemma setbit_eq : forall a n, (setbit a n).[n] = true.
Proof.
intros. apply setbit_iff. now left.
Qed.
Lemma setbit_neq : forall a n m, n~=m ->
(setbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite setbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. now rewrite H.
Qed.
Lemma clearbit_eqb : forall a n m,
(clearbit a n).[m] = a.[m] && negb (eqb n m).
Proof.
intros. now rewrite clearbit_spec', ldiff_spec, pow2_bits_eqb.
Qed.
Lemma clearbit_iff : forall a n m,
(clearbit a n).[m] = true <-> a.[m] = true /\ n~=m.
Proof.
intros. rewrite clearbit_eqb, andb_true_iff, <- eqb_eq.
now rewrite negb_true_iff, not_true_iff_false.
Qed.
Lemma clearbit_eq : forall a n, (clearbit a n).[n] = false.
Proof.
intros. rewrite clearbit_eqb, (proj2 (eqb_eq _ _) (eq_refl n)).
apply andb_false_r.
Qed.
Lemma clearbit_neq : forall a n m, n~=m ->
(clearbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite clearbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. rewrite H.
apply andb_true_r.
Qed.
(** Shifts of bitwise operations *)
Lemma shiftl_lxor : forall a b n,
(lxor a b) << n == lxor (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', lxor_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_lxor : forall a b n,
(lxor a b) >> n == lxor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', lxor_spec.
Qed.
Lemma shiftl_land : forall a b n,
(land a b) << n == land (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', land_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_land : forall a b n,
(land a b) >> n == land (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', land_spec.
Qed.
Lemma shiftl_lor : forall a b n,
(lor a b) << n == lor (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', lor_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_lor : forall a b n,
(lor a b) >> n == lor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', lor_spec.
Qed.
Lemma shiftl_ldiff : forall a b n,
(ldiff a b) << n == ldiff (a << n) (b << n).
Proof.
intros. bitwise.
destruct (le_gt_cases n m).
now rewrite !shiftl_spec_high', ldiff_spec.
now rewrite !shiftl_spec_low.
Qed.
Lemma shiftr_ldiff : forall a b n,
(ldiff a b) >> n == ldiff (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec', ldiff_spec.
Qed.
(** We cannot have a function complementing all bits of a number,
otherwise it would have an infinity of bit 1. Nonetheless,
we can design a bounded complement *)
Definition ones n := P (1 << n).
Definition lnot a n := lxor a (ones n).
Instance ones_wd : Proper (eq==>eq) ones.
Proof. unfold ones. solve_proper. Qed.
Instance lnot_wd : Proper (eq==>eq==>eq) lnot.
Proof. unfold lnot. solve_proper. Qed.
Lemma ones_equiv : forall n, ones n == P (2^n).
Proof.
intros; unfold ones; now rewrite shiftl_1_l.
Qed.
Lemma ones_add : forall n m, ones (m+n) == 2^m * ones n + ones m.
Proof.
intros n m. rewrite !ones_equiv.
rewrite <- !sub_1_r, mul_sub_distr_l, mul_1_r, <- pow_add_r.
rewrite add_sub_assoc, sub_add. reflexivity.
apply pow_le_mono_r. order'.
rewrite <- (add_0_r m) at 1. apply add_le_mono_l, le_0_l.
rewrite <- (pow_0_r 2). apply pow_le_mono_r. order'. apply le_0_l.
Qed.
Lemma ones_div_pow2 : forall n m, m<=n -> ones n / 2^m == ones (n-m).
Proof.
intros n m H. symmetry. apply div_unique with (ones m).
rewrite ones_equiv.
apply le_succ_l. rewrite succ_pred; order_nz.
rewrite <- (sub_add m n H) at 1. rewrite (add_comm _ m).
apply ones_add.
Qed.
Lemma ones_mod_pow2 : forall n m, m<=n -> (ones n) mod (2^m) == ones m.
Proof.
intros n m H. symmetry. apply mod_unique with (ones (n-m)).
rewrite ones_equiv.
apply le_succ_l. rewrite succ_pred; order_nz.
rewrite <- (sub_add m n H) at 1. rewrite (add_comm _ m).
apply ones_add.
Qed.
Lemma ones_spec_low : forall n m, m<n -> (ones n).[m] = true.
Proof.
intros. apply testbit_true. rewrite ones_div_pow2 by order.
rewrite <- (pow_1_r 2). rewrite ones_mod_pow2.
rewrite ones_equiv. now nzsimpl'.
apply le_add_le_sub_r. nzsimpl. now apply le_succ_l.
Qed.
Lemma ones_spec_high : forall n m, n<=m -> (ones n).[m] = false.
Proof.
intros.
destruct (eq_0_gt_0_cases n) as [EQ|LT]; rewrite ones_equiv.
now rewrite EQ, pow_0_r, one_succ, pred_succ, bits_0.
apply bits_above_log2.
rewrite log2_pred_pow2; trivial. rewrite <-le_succ_l, succ_pred; order.
Qed.
Lemma ones_spec_iff : forall n m, (ones n).[m] = true <-> m<n.
Proof.
intros. split. intros H.
apply lt_nge. intro H'. apply ones_spec_high in H'.
rewrite H in H'; discriminate.
apply ones_spec_low.
Qed.
Lemma lnot_spec_low : forall a n m, m<n ->
(lnot a n).[m] = negb a.[m].
Proof.
intros. unfold lnot. now rewrite lxor_spec, ones_spec_low.
Qed.
Lemma lnot_spec_high : forall a n m, n<=m ->
(lnot a n).[m] = a.[m].
Proof.
intros. unfold lnot. now rewrite lxor_spec, ones_spec_high, xorb_false_r.
Qed.
Lemma lnot_involutive : forall a n, lnot (lnot a n) n == a.
Proof.
intros a n. bitwise.
destruct (le_gt_cases n m).
now rewrite 2 lnot_spec_high.
now rewrite 2 lnot_spec_low, negb_involutive.
Qed.
Lemma lnot_0_l : forall n, lnot 0 n == ones n.
Proof.
intros. unfold lnot. apply lxor_0_l.
Qed.
Lemma lnot_ones : forall n, lnot (ones n) n == 0.
Proof.
intros. unfold lnot. apply lxor_nilpotent.
Qed.
(** Bounded complement and other operations *)
Lemma lor_ones_low : forall a n, log2 a < n ->
lor a (ones n) == ones n.
Proof.
intros a n H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, orb_true_r.
Qed.
Lemma land_ones : forall a n, land a (ones n) == a mod 2^n.
Proof.
intros a n. bitwise. destruct (le_gt_cases n m).
now rewrite ones_spec_high, mod_pow2_bits_high, andb_false_r.
now rewrite ones_spec_low, mod_pow2_bits_low, andb_true_r.
Qed.
Lemma land_ones_low : forall a n, log2 a < n ->
land a (ones n) == a.
Proof.
intros; rewrite land_ones. apply mod_small.
apply log2_lt_cancel. rewrite log2_pow2; trivial using le_0_l.
Qed.
Lemma ldiff_ones_r : forall a n,
ldiff a (ones n) == (a >> n) << n.
Proof.
intros a n. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, shiftl_spec_high', shiftr_spec'; trivial.
rewrite sub_add; trivial. apply andb_true_r.
now rewrite ones_spec_low, shiftl_spec_low, andb_false_r.
Qed.
Lemma ldiff_ones_r_low : forall a n, log2 a < n ->
ldiff a (ones n) == 0.
Proof.
intros a n H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, andb_false_r.
Qed.
Lemma ldiff_ones_l_low : forall a n, log2 a < n ->
ldiff (ones n) a == lnot a n.
Proof.
intros a n H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, lnot_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
now rewrite ones_spec_low, lnot_spec_low.
Qed.
Lemma lor_lnot_diag : forall a n,
lor a (lnot a n) == lor a (ones n).
Proof.
intros a n. bitwise.
destruct (le_gt_cases n m).
rewrite lnot_spec_high, ones_spec_high; trivial. now destruct a.[m].
rewrite lnot_spec_low, ones_spec_low; trivial. now destruct a.[m].
Qed.
Lemma lor_lnot_diag_low : forall a n, log2 a < n ->
lor a (lnot a n) == ones n.
Proof.
intros a n H. now rewrite lor_lnot_diag, lor_ones_low.
Qed.
Lemma land_lnot_diag : forall a n,
land a (lnot a n) == ldiff a (ones n).
Proof.
intros a n. bitwise.
destruct (le_gt_cases n m).
rewrite lnot_spec_high, ones_spec_high; trivial. now destruct a.[m].
rewrite lnot_spec_low, ones_spec_low; trivial. now destruct a.[m].
Qed.
Lemma land_lnot_diag_low : forall a n, log2 a < n ->
land a (lnot a n) == 0.
Proof.
intros. now rewrite land_lnot_diag, ldiff_ones_r_low.
Qed.
Lemma lnot_lor_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (lor a b) n == land (lnot a n) (lnot b n).
Proof.
intros a b n Ha Hb. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lor_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, lor_spec, negb_orb.
Qed.
Lemma lnot_land_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (land a b) n == lor (lnot a n) (lnot b n).
Proof.
intros a b n Ha Hb. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, land_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, land_spec, negb_andb.
Qed.
Lemma ldiff_land_low : forall a b n, log2 a < n ->
ldiff a b == land a (lnot b n).
Proof.
intros a b n Ha. bitwise. destruct (le_gt_cases n m).
rewrite (bits_above_log2 a m). trivial.
now apply lt_le_trans with n.
rewrite !lnot_spec_low; trivial.
Qed.
Lemma lnot_ldiff_low : forall a b n, log2 a < n -> log2 b < n ->
lnot (ldiff a b) n == lor (lnot a n) b.
Proof.
intros a b n Ha Hb. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, ldiff_spec, !bits_above_log2; trivial.
now apply lt_le_trans with n.
now apply lt_le_trans with n.
now rewrite !lnot_spec_low, ldiff_spec, negb_andb, negb_involutive.
Qed.
Lemma lxor_lnot_lnot : forall a b n,
lxor (lnot a n) (lnot b n) == lxor a b.
Proof.
intros a b n. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high; trivial.
rewrite !lnot_spec_low, xorb_negb_negb; trivial.
Qed.
Lemma lnot_lxor_l : forall a b n,
lnot (lxor a b) n == lxor (lnot a n) b.
Proof.
intros a b n. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lxor_spec; trivial.
rewrite !lnot_spec_low, lxor_spec, negb_xorb_l; trivial.
Qed.
Lemma lnot_lxor_r : forall a b n,
lnot (lxor a b) n == lxor a (lnot b n).
Proof.
intros a b n. bitwise. destruct (le_gt_cases n m).
rewrite !lnot_spec_high, lxor_spec; trivial.
rewrite !lnot_spec_low, lxor_spec, negb_xorb_r; trivial.
Qed.
Lemma lxor_lor : forall a b, land a b == 0 ->
lxor a b == lor a b.
Proof.
intros a b H. bitwise.
assert (a.[m] && b.[m] = false)
by now rewrite <- land_spec, H, bits_0.
now destruct a.[m], b.[m].
Qed.
(** Bitwise operations and log2 *)
Lemma log2_bits_unique : forall a n,
a.[n] = true ->
(forall m, n<m -> a.[m] = false) ->
log2 a == n.
Proof.
intros a n H H'.
destruct (eq_0_gt_0_cases a) as [Ha|Ha].
now rewrite Ha, bits_0 in H.
apply le_antisymm; apply le_ngt; intros LT.
specialize (H' _ LT). now rewrite bit_log2 in H' by order.
now rewrite bits_above_log2 in H by order.
Qed.
Lemma log2_shiftr : forall a n, log2 (a >> n) == log2 a - n.
Proof.
intros a n.
destruct (eq_0_gt_0_cases a) as [Ha|Ha].
now rewrite Ha, shiftr_0_l, log2_nonpos, sub_0_l by order.
destruct (lt_ge_cases (log2 a) n).
rewrite shiftr_eq_0, log2_nonpos by order.
symmetry. rewrite sub_0_le; order.
apply log2_bits_unique.
now rewrite shiftr_spec', sub_add, bit_log2 by order.
intros m Hm.
rewrite shiftr_spec'; trivial. apply bits_above_log2; try order.
now apply lt_sub_lt_add_r.
Qed.
Lemma log2_shiftl : forall a n, a~=0 -> log2 (a << n) == log2 a + n.
Proof.
intros a n Ha.
rewrite shiftl_mul_pow2, add_comm by trivial.
apply log2_mul_pow2. generalize (le_0_l a); order. apply le_0_l.
Qed.
Lemma log2_lor : forall a b,
log2 (lor a b) == max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (lor a b) == log2 b).
intros a b H.
destruct (eq_0_gt_0_cases a) as [Ha|Ha]. now rewrite Ha, lor_0_l.
apply log2_bits_unique.
now rewrite lor_spec, bit_log2, orb_true_r by order.
intros m Hm. assert (H' := log2_le_mono _ _ H).
now rewrite lor_spec, 2 bits_above_log2 by order.
(* main *)
intros a b. destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono.
now apply AUX.
rewrite max_l by now apply log2_le_mono.
rewrite lor_comm. now apply AUX.
Qed.
Lemma log2_land : forall a b,
log2 (land a b) <= min (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (land a b) <= log2 a).
intros a b H.
apply le_ngt. intros H'.
destruct (eq_decidable (land a b) 0) as [EQ|NEQ].
rewrite EQ in H'. apply log2_lt_cancel in H'. generalize (le_0_l a); order.
generalize (bit_log2 (land a b) NEQ).
now rewrite land_spec, bits_above_log2.
(* main *)
intros a b.
destruct (le_ge_cases a b) as [H|H].
rewrite min_l by now apply log2_le_mono. now apply AUX.
rewrite min_r by now apply log2_le_mono. rewrite land_comm. now apply AUX.
Qed.
Lemma log2_lxor : forall a b,
log2 (lxor a b) <= max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, a<=b -> log2 (lxor a b) <= log2 b).
intros a b H.
apply le_ngt. intros H'.
destruct (eq_decidable (lxor a b) 0) as [EQ|NEQ].
rewrite EQ in H'. apply log2_lt_cancel in H'. generalize (le_0_l a); order.
generalize (bit_log2 (lxor a b) NEQ).
rewrite lxor_spec, 2 bits_above_log2; try order. discriminate.
apply le_lt_trans with (log2 b); trivial. now apply log2_le_mono.
(* main *)
intros a b.
destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono. now apply AUX.
rewrite max_l by now apply log2_le_mono. rewrite lxor_comm. now apply AUX.
Qed.
(** Bitwise operations and arithmetical operations *)
Local Notation xor3 a b c := (xorb (xorb a b) c).
Local Notation lxor3 a b c := (lxor (lxor a b) c).
Local Notation nextcarry a b c := ((a&&b) || (c && (a||b))).
Local Notation lnextcarry a b c := (lor (land a b) (land c (lor a b))).
Lemma add_bit0 : forall a b, (a+b).[0] = xorb a.[0] b.[0].
Proof.
intros. now rewrite !bit0_odd, odd_add.
Qed.
Lemma add3_bit0 : forall a b c,
(a+b+c).[0] = xor3 a.[0] b.[0] c.[0].
Proof.
intros. now rewrite !add_bit0.
Qed.
Lemma add3_bits_div2 : forall (a0 b0 c0 : bool),
(a0 + b0 + c0)/2 == nextcarry a0 b0 c0.
Proof.
assert (H : 1+1 == 2) by now nzsimpl'.
intros [|] [|] [|]; simpl; rewrite ?add_0_l, ?add_0_r, ?H;
(apply div_same; order') || (apply div_small; order') || idtac.
symmetry. apply div_unique with 1. order'. now nzsimpl'.
Qed.
Lemma add_carry_div2 : forall a b (c0:bool),
(a + b + c0)/2 == a/2 + b/2 + nextcarry a.[0] b.[0] c0.
Proof.
intros.
rewrite <- add3_bits_div2.
rewrite (add_comm ((a/2)+_)).
rewrite <- div_add by order'.
f_equiv.
rewrite <- !div2_div, mul_comm, mul_add_distr_l.
rewrite (div2_odd a), <- bit0_odd at 1. fold (b2n a.[0]).
rewrite (div2_odd b), <- bit0_odd at 1. fold (b2n b.[0]).
rewrite add_shuffle1.
rewrite <-(add_assoc _ _ c0). apply add_comm.
Qed.
(** The main result concerning addition: we express the bits of the sum
in term of bits of [a] and [b] and of some carry stream which is also
recursively determined by another equation.
*)
Lemma add_carry_bits : forall a b (c0:bool), exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros a b c0.
(* induction over some n such that [a<2^n] and [b<2^n] *)
set (n:=max a b).
assert (Ha : a<2^n).
apply lt_le_trans with (2^a). apply pow_gt_lin_r, lt_1_2.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases a b); [rewrite max_r|rewrite max_l]; order'.
assert (Hb : b<2^n).
apply lt_le_trans with (2^b). apply pow_gt_lin_r, lt_1_2.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases a b); [rewrite max_r|rewrite max_l]; order'.
clearbody n.
revert a b c0 Ha Hb. induct n.
(*base*)
intros a b c0. rewrite !pow_0_r, !one_succ, !lt_succ_r. intros Ha Hb.
exists c0.
setoid_replace a with 0 by (generalize (le_0_l a); order').
setoid_replace b with 0 by (generalize (le_0_l b); order').
rewrite !add_0_l, !lxor_0_l, !lor_0_r, !land_0_r, !lor_0_r.
rewrite b2n_div2, b2n_bit0; now repeat split.
(*step*)
intros n IH a b c0 Ha Hb.
set (c1:=nextcarry a.[0] b.[0] c0).
destruct (IH (a/2) (b/2) c1) as (c & IH1 & IH2 & Hc); clear IH.
apply div_lt_upper_bound; trivial. order'. now rewrite <- pow_succ_r'.
apply div_lt_upper_bound; trivial. order'. now rewrite <- pow_succ_r'.
exists (c0 + 2*c). repeat split.
(* - add *)
bitwise.
destruct (zero_or_succ m) as [EQ|[m' EQ]]; rewrite EQ; clear EQ.
now rewrite add_b2n_double_bit0, add3_bit0, b2n_bit0.
rewrite <- !div2_bits, <- 2 lxor_spec.
f_equiv.
rewrite add_b2n_double_div2, <- IH1. apply add_carry_div2.
(* - carry *)
rewrite add_b2n_double_div2.
bitwise.
destruct (zero_or_succ m) as [EQ|[m' EQ]]; rewrite EQ; clear EQ.
now rewrite add_b2n_double_bit0.
rewrite <- !div2_bits, IH2. autorewrite with bitwise.
now rewrite add_b2n_double_div2.
(* - carry0 *)
apply add_b2n_double_bit0.
Qed.
(** Particular case : the second bit of an addition *)
Lemma add_bit1 : forall a b,
(a+b).[1] = xor3 a.[1] b.[1] (a.[0] && b.[0]).
Proof.
intros a b.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
autorewrite with bitwise. f_equal.
rewrite one_succ, <- div2_bits, EQ2.
autorewrite with bitwise.
rewrite Hc. simpl. apply orb_false_r.
Qed.
(** In an addition, there will be no carries iff there is
no common bits in the numbers to add *)
Lemma nocarry_equiv : forall a b c,
c/2 == lnextcarry a b c -> c.[0] = false ->
(c == 0 <-> land a b == 0).
Proof.
intros a b c H H'.
split. intros EQ; rewrite EQ in *.
rewrite div_0_l in H by order'.
symmetry in H. now apply lor_eq_0_l in H.
intros EQ. rewrite EQ, lor_0_l in H.
apply bits_inj_0.
induct n. trivial.
intros n IH.
rewrite <- div2_bits, H.
autorewrite with bitwise.
now rewrite IH.
Qed.
(** When there is no common bits, the addition is just a xor *)
Lemma add_nocarry_lxor : forall a b, land a b == 0 ->
a+b == lxor a b.
Proof.
intros a b H.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
apply (nocarry_equiv a b c) in H; trivial.
rewrite H. now rewrite lxor_0_r.
Qed.
(** A null [ldiff] implies being smaller *)
Lemma ldiff_le : forall a b, ldiff a b == 0 -> a <= b.
Proof.
cut (forall n a b, a < 2^n -> ldiff a b == 0 -> a <= b).
intros H a b. apply (H a), pow_gt_lin_r; order'.
induct n.
intros a b Ha _. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
assert (Ha' : a == 0) by (generalize (le_0_l a); order').
rewrite Ha'. apply le_0_l.
intros n IH a b Ha H.
assert (NEQ : 2 ~= 0) by order'.
rewrite (div_mod a 2 NEQ), (div_mod b 2 NEQ).
apply add_le_mono.
apply mul_le_mono_l.
apply IH.
apply div_lt_upper_bound; trivial. now rewrite <- pow_succ_r'.
rewrite <- (pow_1_r 2), <- 2 shiftr_div_pow2.
now rewrite <- shiftr_ldiff, H, shiftr_div_pow2, pow_1_r, div_0_l.
rewrite <- 2 bit0_mod.
apply bits_inj_iff in H. specialize (H 0).
rewrite ldiff_spec, bits_0 in H.
destruct a.[0], b.[0]; try discriminate; simpl; order'.
Qed.
(** Subtraction can be a ldiff when the opposite ldiff is null. *)
Lemma sub_nocarry_ldiff : forall a b, ldiff b a == 0 ->
a-b == ldiff a b.
Proof.
intros a b H.
apply add_cancel_r with b.
rewrite sub_add.
symmetry.
rewrite add_nocarry_lxor.
bitwise.
apply bits_inj_iff in H. specialize (H m).
rewrite ldiff_spec, bits_0 in H.
now destruct a.[m], b.[m].
apply land_ldiff.
now apply ldiff_le.
Qed.
(** We can express lnot in term of subtraction *)
Lemma add_lnot_diag_low : forall a n, log2 a < n ->
a + lnot a n == ones n.
Proof.
intros a n H.
assert (H' := land_lnot_diag_low a n H).
rewrite add_nocarry_lxor, lxor_lor by trivial.
now apply lor_lnot_diag_low.
Qed.
Lemma lnot_sub_low : forall a n, log2 a < n ->
lnot a n == ones n - a.
Proof.
intros a n H.
now rewrite <- (add_lnot_diag_low a n H), add_comm, add_sub.
Qed.
(** Adding numbers with no common bits cannot lead to a much bigger number *)
Lemma add_nocarry_lt_pow2 : forall a b n, land a b == 0 ->
a < 2^n -> b < 2^n -> a+b < 2^n.
Proof.
intros a b n H Ha Hb.
rewrite add_nocarry_lxor by trivial.
apply div_small_iff. order_nz.
rewrite <- shiftr_div_pow2, shiftr_lxor, !shiftr_div_pow2.
rewrite 2 div_small by trivial.
apply lxor_0_l.
Qed.
Lemma add_nocarry_mod_lt_pow2 : forall a b n, land a b == 0 ->
a mod 2^n + b mod 2^n < 2^n.
Proof.
intros a b n H.
apply add_nocarry_lt_pow2.
bitwise.
destruct (le_gt_cases n m).
now rewrite mod_pow2_bits_high.
now rewrite !mod_pow2_bits_low, <- land_spec, H, bits_0.
apply mod_upper_bound; order_nz.
apply mod_upper_bound; order_nz.
Qed.
End NBitsProp.
|
(****************************************************************************)
(* Copyright 2021 The Project Oak Authors *)
(* *)
(* Licensed under the Apache License, Version 2.0 (the "License") *)
(* you may not use this file except in compliance with the License. *)
(* You may obtain a copy of the License at *)
(* *)
(* http://www.apache.org/licenses/LICENSE-2.0 *)
(* *)
(* Unless required by applicable law or agreed to in writing, software *)
(* distributed under the License is distributed on an "AS IS" BASIS, *)
(* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *)
(* See the License for the specific language governing permissions and *)
(* limitations under the License. *)
(****************************************************************************)
Require Import Coq.Arith.PeanoNat.
Require Import Coq.Lists.List.
Require Import Coq.NArith.NArith.
Require Import coqutil.Datatypes.List.
Require Import Cava.Util.BitArithmetic.
Require Import Cava.Util.Byte.
Require Import Cava.Expr.
Require Import Cava.Semantics.
Require Import Cava.Types.
Require Import HmacSpec.SHA256.
Require Import HmacSpec.Tests.SHA256TestVectors.
Require Import HmacHardware.Sha256.
Import ListNotations.
(**** Convert to/from circuit signals ****)
(* extra cycles to allow for padder synchronization after each block of true
input; can be an overestimate *)
Definition extra_cycles : nat := 80.
(* convert test vector data into circuit input signals *)
Definition to_sha256_input (t : sha256_test_vector)
: list (denote_type (input_of sha256)) :=
(* input must be divided into into 32-bit words *)
let l := N.to_nat t.(l) in
let nwords := l / 32 + (if l mod 32 =? 0 then 0 else 1) in
(* separate bytes for the final word and bytes for non-final words *)
let non_final_bytes := firstn ((nwords - 1) * 4) t.(msg_bytes) in
let final_bytes := skipn ((nwords - 1) * 4) t.(msg_bytes) in
(* convert bytes to words *)
let non_final_words := BigEndianBytes.bytes_to_Ns 4 non_final_bytes in
let final_bytes_padded := final_bytes ++ repeat Byte.x00 (4 - length final_bytes) in
let final_word := BigEndianBytes.concat_bytes final_bytes_padded in
let final_length := N.of_nat (length final_bytes) in
(* create actual input signals *)
let non_final_input : list (denote_type (input_of sha256)) :=
(* fifo_data_valid=1, fifo_data, is_final=0, final_length=0, clear=0 *)
List.map (fun data => (true, (data, (false, (0, (false, tt)))))%N) non_final_words in
let final_input : denote_type (input_of sha256) :=
(* fifo_data_valid=1, fifo_data, is_final=1, final_length=final_length,
clear=0 *)
(true, (final_word, (true, (final_length, (false, tt)))))%N in
(* if input is multiple blocks long *before* padding, we need to add dummy
inputs after each block to wait for the padder to be ready to accept input
again *)
let words_per_block := (512 / N.to_nat w) in
let nblocks_non_final :=
length (non_final_input) / words_per_block
+ if (length (non_final_input) mod words_per_block =? 0) then 0 else 1 in
let nblocks_padded := length (SHA256.padded_msg t.(msg_bytes)) / words_per_block in
let dummy_input : denote_type (input_of sha256) :=
(false, (0, (false, (0, (false, tt)))))%N in
(* introduce dummy inputs between each block of 16 words in the input,
including between non-final and final blocks if there is at least one
non-final block *)
let non_final_input_spaced :=
flat_map
(fun i => firstn words_per_block (skipn (words_per_block*i) non_final_input)
++ repeat dummy_input extra_cycles)
(seq 0 nblocks_non_final) in
(* cycles to wait after input
= cycles for padding (16 per post-padding block)
+ cycles for compression (64 per post-padding block)
+ extra_cycles *)
let ndummy := ((64+16)*nblocks_padded + extra_cycles) in
non_final_input_spaced ++ [final_input] ++ repeat dummy_input ndummy.
(* extract test result from circuit output signals *)
Definition from_sha256_output
(out : list (denote_type (output_of sha256)))
: N :=
let '(done, (digest, accept_input)) := last out default in
BigEndianBytes.concat_bytes (concat_digest digest).
(* convert test vector data into input signals for padder *)
Definition to_sha256_padder_input (t : sha256_test_vector)
: list (denote_type (input_of sha256_padder)) :=
(* For padder tests, we assume the consumer is always ready *)
List.map
(fun '(fifo_data_valid,(fifo_data,(is_final,(final_length,(clear,_))))) =>
(* data_valid, data, is_final, final_length, consumer_ready, clear *)
(fifo_data_valid,(fifo_data, (is_final, (final_length, (true, (clear, tt)))))))
(to_sha256_input t).
Definition concat_words (n : nat) (ws : list N) : N :=
fold_left (fun acc w => N.lor (N.shiftl acc (N.of_nat n)) (w mod 2 ^ N.of_nat n)) ws 0%N.
(* extract test result from padder output signals *)
Definition from_sha256_padder_output
(out : list (denote_type (output_of sha256_padder)))
: N :=
(* remove invalid output signals entirely, and extract data from signals *)
let valid_out :=
flat_map
(fun '(out_valid, (data, done)) =>
if (out_valid : bool) then [data] else []) out in
concat_words (N.to_nat w) valid_out.
(* extract all intermediate digests from circuit output signals *)
Definition intermediate_digests_from_sha256_output
(out : list (denote_type (output_of sha256)))
: list (list N) :=
let digests := List.map (fun '(done, (digest, accept_input)) => digest) out in
(* remove repetitions of the same digest *)
dedup (list_eqb N.eqb) digests.
(**** Run test vectors ****)
(* test the padder in isolation *)
Goal (let t := test1 in
from_sha256_padder_output
(simulate sha256_padder (to_sha256_padder_input t)) = t.(expected_padded_msg)).
Proof. vm_compute. reflexivity. Qed.
Goal (let t := test2 in
from_sha256_padder_output
(simulate sha256_padder (to_sha256_padder_input t)) = t.(expected_padded_msg)).
Proof. vm_compute. reflexivity. Qed.
(* test intermediate digests *)
Goal (let t := test1 in
intermediate_digests_from_sha256_output
(simulate sha256 (to_sha256_input t)) = H0 :: t.(expected_intermediate_digests)).
Proof. vm_compute. reflexivity. Qed.
Goal (let t := test2 in
intermediate_digests_from_sha256_output
(simulate sha256 (to_sha256_input t)) = H0 :: t.(expected_intermediate_digests)).
Proof. vm_compute. reflexivity. Qed.
(* Test the full circuit *)
Goal (let t := test1 in
from_sha256_output (simulate sha256 (to_sha256_input t)) = t.(expected_digest)).
Proof. vm_compute. reflexivity. Qed.
Goal (let t := test2 in
from_sha256_output (simulate sha256 (to_sha256_input t)) = t.(expected_digest)).
Proof. vm_compute. reflexivity. Qed.
Goal (let t := test3 in
from_sha256_output (simulate sha256 (to_sha256_input t)) = t.(expected_digest)).
Proof. vm_compute. reflexivity. Qed.
Goal (let t := test4 in
from_sha256_output (simulate sha256 (to_sha256_input t)) = t.(expected_digest)).
Proof. vm_compute. reflexivity. Qed.
|
//----------------------------------------------------------------------------
//-- Asynchronous serial transmitter Unit
//------------------------------------------
//-- (C) BQ. December 2015. Written by Juan Gonzalez (Obijuan)
//-- GPL license
//----------------------------------------------------------------------------
//-- Tested at all the standard baudrates:
//-- 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200
//----------------------------------------------------------------------------
//-- Although this transmitter has been written from the scratch, it has been
//-- inspired by the one developed in the swapforth proyect by James Bowman
//--
//-- https://github.com/jamesbowman/swapforth
//--
//----------------------------------------------------------------------------
`default_nettype none
`include "baudgen.vh"
//--- Serial transmitter unit module
//--- TX output is not registered
module uart_tx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire clk, //-- System clcok (12MHz in the ICEstick)
input wire rstn, //-- Reset (Active low)
input wire start, //-- Set to 1 for starting the transmission
input wire [7:0] data, //-- Byte to transmit
output reg tx, //-- Serial data output
output reg ready //-- Transmitter ready (1) / busy (0)
);
//-- Transmission clock
wire clk_baud;
//-- Bitcounter
reg [3:0] bitc;
//-- Registered data
reg [7:0] data_r;
//--------- control signals
reg load; //-- Load the shifter register / reset
reg baud_en; //-- Enable the baud generator
//-------------------------------------
//-- DATAPATH
//-------------------------------------
//-- Register the input data
always @(posedge clk)
if (start == 1 && state == IDLE)
data_r <= data;
//-- 1 bit start + 8 bits datos + 1 bit stop
//-- Shifter register. It stored the frame to transmit:
//-- 1 start bit + 8 data bits + 1 stop bit
reg [9:0] shifter;
//-- When the control signal load is 1, the frame is loaded
//-- when load = 0, the frame is shifted right to send 1 bit,
//-- at the baudrate determined by clk_baud
//-- 1s are introduced by the left
always @(posedge clk)
//-- Reset
if (rstn == 0)
shifter <= 10'b11_1111_1111;
//-- Load mode
else if (load == 1)
shifter <= {data_r,2'b01};
//-- Shift mode
else if (load == 0 && clk_baud == 1)
shifter <= {1'b1, shifter[9:1]};
//-- Sent bit counter
//-- When load (=1) the counter is reset
//-- When load = 0, the sent bits are counted (with the raising edge of clk_baud)
always @(posedge clk)
if (!rstn)
bitc <= 0;
else if (load == 1)
bitc <= 0;
else if (load == 0 && clk_baud == 1)
bitc <= bitc + 1;
//-- The less significant bit is transmited through tx
//-- It is a registed output, because tx is connected to an Asynchronous bus
//-- and the glitches should be avoided
always @(posedge clk)
tx <= shifter[0];
//-- Baud generator
baudgen_tx #( .BAUDRATE(BAUDRATE))
BAUD0 (
.rstn(rstn),
.clk(clk),
.clk_ena(baud_en),
.clk_out(clk_baud)
);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam IDLE = 0; //-- Idle state
localparam START = 1; //-- Start transmission
localparam TRANS = 2; //-- Transmitting data
//-- Registers for storing the states
reg [1:0] state;
reg [1:0] next_state;
//-- Transition between states
always @(posedge clk)
if (!rstn)
state <= IDLE;
else
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
load = 0;
baud_en = 0;
case (state)
//-- Idle state
//-- Remain in this state until start is 1
IDLE: begin
ready = 1;
if (start == 1)
next_state = START;
end
//-- 1 cycle long
//-- turn on the baudrate generator and the load the shift register
START: begin
load = 1;
baud_en = 1;
ready = 0;
next_state = TRANS;
end
//-- Stay here until all the bits have been sent
TRANS: begin
baud_en = 1;
ready = 0;
if (bitc == 11)
next_state = IDLE;
end
default:
ready = 0;
endcase
end
endmodule
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