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//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module add32 (
dataa,
datab,
result)/* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
endmodule
|
module parallella_base(/*AUTOARG*/
// Outputs
s_axi_wready, s_axi_rvalid, s_axi_rresp, s_axi_rlast, s_axi_rid,
s_axi_rdata, s_axi_bvalid, s_axi_bresp, s_axi_bid, s_axi_awready,
s_axi_arready, m_axi_wvalid, m_axi_wstrb, m_axi_wlast, m_axi_wid,
m_axi_wdata, m_axi_rready, m_axi_bready, m_axi_awvalid,
m_axi_awsize, m_axi_awqos, m_axi_awprot, m_axi_awlock, m_axi_awlen,
m_axi_awid, m_axi_awcache, m_axi_awburst, m_axi_awaddr,
m_axi_arvalid, m_axi_arsize, m_axi_arqos, m_axi_arprot,
m_axi_arlock, m_axi_arlen, m_axi_arid, m_axi_arcache,
m_axi_arburst, m_axi_araddr, cclk_n, cclk_p, chip_nreset, chipid,
elink_active, mailbox_irq, i2c_scl_i, i2c_sda_i, ps_gpio_i,
txo_data_n, txo_data_p, txo_frame_n, txo_frame_p, txo_lclk_n,
txo_lclk_p, rxo_rd_wait_n, rxo_rd_wait_p, rxo_wr_wait_n,
rxo_wr_wait_p, constant_zero, constant_one,
// Inouts
i2c_scl, i2c_sda, gpio_n, gpio_p,
// Inputs
s_axi_wvalid, s_axi_wstrb, s_axi_wlast, s_axi_wid, s_axi_wdata,
s_axi_rready, s_axi_bready, s_axi_awvalid, s_axi_awsize,
s_axi_awqos, s_axi_awprot, s_axi_awlock, s_axi_awlen, s_axi_awid,
s_axi_awcache, s_axi_awburst, s_axi_awaddr, s_axi_arvalid,
s_axi_arsize, s_axi_arqos, s_axi_arprot, s_axi_arlock, s_axi_arlen,
s_axi_arid, s_axi_aresetn, s_axi_arcache, s_axi_arburst,
s_axi_araddr, m_axi_wready, m_axi_rvalid, m_axi_rresp, m_axi_rlast,
m_axi_rid, m_axi_rdata, m_axi_bvalid, m_axi_bresp, m_axi_bid,
m_axi_awready, m_axi_arready, m_axi_aresetn, sys_clk, sys_nreset,
i2c_scl_o, i2c_scl_t, i2c_sda_o, i2c_sda_t, ps_gpio_o, ps_gpio_t,
txi_rd_wait_n, txi_rd_wait_p, txi_wr_wait_n, txi_wr_wait_p,
rxi_data_n, rxi_data_p, rxi_frame_n, rxi_frame_p, rxi_lclk_n,
rxi_lclk_p
);
parameter AW = 32;
parameter DW = 32;
parameter PW = 104; //packet width
parameter ID = 12'h810;
parameter S_IDW = 12; //ID width for S_AXI
parameter M_IDW = 6; //ID width for M_AXI
parameter IOSTD_ELINK = "LVDS_25";
parameter NGPIO = 24;
parameter NPS = 64; //Number of PS signals
//RESET+CLK
input sys_clk;
input sys_nreset;
//MISC
output cclk_n;
output cclk_p;
output chip_nreset;
output [11:0] chipid;
output elink_active;
output mailbox_irq;
//I2C
output i2c_scl_i;
output i2c_sda_i;
input i2c_scl_o;
input i2c_scl_t;
input i2c_sda_o;
input i2c_sda_t;
inout i2c_scl;
inout i2c_sda;
//GPIO
input [NPS-1:0] ps_gpio_o;
input [NPS-1:0] ps_gpio_t;
output [NPS-1:0] ps_gpio_i;
inout [NGPIO-1:0] gpio_n;
inout [NGPIO-1:0] gpio_p;
//TX
output [7:0] txo_data_n;
output [7:0] txo_data_p;
output txo_frame_n;
output txo_frame_p;
output txo_lclk_n;
output txo_lclk_p;
input txi_rd_wait_n;
input txi_rd_wait_p;
input txi_wr_wait_n;
input txi_wr_wait_p;
//RX
input [7:0] rxi_data_n;
input [7:0] rxi_data_p;
input rxi_frame_n;
input rxi_frame_p;
input rxi_lclk_n;
input rxi_lclk_p;
output rxo_rd_wait_n;
output rxo_rd_wait_p;
output rxo_wr_wait_n;
output rxo_wr_wait_p;
output constant_zero;
output constant_one;
/*AUTOINOUT*/
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [31:0] m_axi_araddr; // From axi_elink of axi_elink.v
output [1:0] m_axi_arburst; // From axi_elink of axi_elink.v
output [3:0] m_axi_arcache; // From axi_elink of axi_elink.v
output [M_IDW-1:0] m_axi_arid; // From axi_elink of axi_elink.v
output [7:0] m_axi_arlen; // From axi_elink of axi_elink.v
output m_axi_arlock; // From axi_elink of axi_elink.v
output [2:0] m_axi_arprot; // From axi_elink of axi_elink.v
output [3:0] m_axi_arqos; // From axi_elink of axi_elink.v
output [2:0] m_axi_arsize; // From axi_elink of axi_elink.v
output m_axi_arvalid; // From axi_elink of axi_elink.v
output [31:0] m_axi_awaddr; // From axi_elink of axi_elink.v
output [1:0] m_axi_awburst; // From axi_elink of axi_elink.v
output [3:0] m_axi_awcache; // From axi_elink of axi_elink.v
output [M_IDW-1:0] m_axi_awid; // From axi_elink of axi_elink.v
output [7:0] m_axi_awlen; // From axi_elink of axi_elink.v
output m_axi_awlock; // From axi_elink of axi_elink.v
output [2:0] m_axi_awprot; // From axi_elink of axi_elink.v
output [3:0] m_axi_awqos; // From axi_elink of axi_elink.v
output [2:0] m_axi_awsize; // From axi_elink of axi_elink.v
output m_axi_awvalid; // From axi_elink of axi_elink.v
output m_axi_bready; // From axi_elink of axi_elink.v
output m_axi_rready; // From axi_elink of axi_elink.v
output [63:0] m_axi_wdata; // From axi_elink of axi_elink.v
output [M_IDW-1:0] m_axi_wid; // From axi_elink of axi_elink.v
output m_axi_wlast; // From axi_elink of axi_elink.v
output [7:0] m_axi_wstrb; // From axi_elink of axi_elink.v
output m_axi_wvalid; // From axi_elink of axi_elink.v
output s_axi_arready; // From axi_elink of axi_elink.v
output s_axi_awready; // From axi_elink of axi_elink.v
output [S_IDW-1:0] s_axi_bid; // From axi_elink of axi_elink.v
output [1:0] s_axi_bresp; // From axi_elink of axi_elink.v
output s_axi_bvalid; // From axi_elink of axi_elink.v
output [31:0] s_axi_rdata; // From axi_elink of axi_elink.v
output [S_IDW-1:0] s_axi_rid; // From axi_elink of axi_elink.v
output s_axi_rlast; // From axi_elink of axi_elink.v
output [1:0] s_axi_rresp; // From axi_elink of axi_elink.v
output s_axi_rvalid; // From axi_elink of axi_elink.v
output s_axi_wready; // From axi_elink of axi_elink.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input m_axi_aresetn; // To axi_elink of axi_elink.v
input m_axi_arready; // To axi_elink of axi_elink.v
input m_axi_awready; // To axi_elink of axi_elink.v
input [M_IDW-1:0] m_axi_bid; // To axi_elink of axi_elink.v
input [1:0] m_axi_bresp; // To axi_elink of axi_elink.v
input m_axi_bvalid; // To axi_elink of axi_elink.v
input [63:0] m_axi_rdata; // To axi_elink of axi_elink.v
input [M_IDW-1:0] m_axi_rid; // To axi_elink of axi_elink.v
input m_axi_rlast; // To axi_elink of axi_elink.v
input [1:0] m_axi_rresp; // To axi_elink of axi_elink.v
input m_axi_rvalid; // To axi_elink of axi_elink.v
input m_axi_wready; // To axi_elink of axi_elink.v
input [31:0] s_axi_araddr; // To axi_elink of axi_elink.v
input [1:0] s_axi_arburst; // To axi_elink of axi_elink.v
input [3:0] s_axi_arcache; // To axi_elink of axi_elink.v
input s_axi_aresetn; // To axi_elink of axi_elink.v
input [S_IDW-1:0] s_axi_arid; // To axi_elink of axi_elink.v
input [7:0] s_axi_arlen; // To axi_elink of axi_elink.v
input s_axi_arlock; // To axi_elink of axi_elink.v
input [2:0] s_axi_arprot; // To axi_elink of axi_elink.v
input [3:0] s_axi_arqos; // To axi_elink of axi_elink.v
input [2:0] s_axi_arsize; // To axi_elink of axi_elink.v
input s_axi_arvalid; // To axi_elink of axi_elink.v
input [31:0] s_axi_awaddr; // To axi_elink of axi_elink.v
input [1:0] s_axi_awburst; // To axi_elink of axi_elink.v
input [3:0] s_axi_awcache; // To axi_elink of axi_elink.v
input [S_IDW-1:0] s_axi_awid; // To axi_elink of axi_elink.v
input [7:0] s_axi_awlen; // To axi_elink of axi_elink.v
input s_axi_awlock; // To axi_elink of axi_elink.v
input [2:0] s_axi_awprot; // To axi_elink of axi_elink.v
input [3:0] s_axi_awqos; // To axi_elink of axi_elink.v
input [2:0] s_axi_awsize; // To axi_elink of axi_elink.v
input s_axi_awvalid; // To axi_elink of axi_elink.v
input s_axi_bready; // To axi_elink of axi_elink.v
input s_axi_rready; // To axi_elink of axi_elink.v
input [31:0] s_axi_wdata; // To axi_elink of axi_elink.v
input [S_IDW-1:0] s_axi_wid; // To axi_elink of axi_elink.v
input s_axi_wlast; // To axi_elink of axi_elink.v
input [3:0] s_axi_wstrb; // To axi_elink of axi_elink.v
input s_axi_wvalid; // To axi_elink of axi_elink.v
// End of automatics
/*AUTOWIRE*/
assign constant_zero = 1'b0;
assign constant_one = 1'b1;
/*axi_elink AUTO_TEMPLATE (
.m_axi_\(.*\) (m_axi_\1[]),
.s_axi_\(.*\) (s_axi_\1[]),
);
*/
defparam axi_elink.ID=ID;
axi_elink axi_elink (
/*AUTOINST*/
// Outputs
.elink_active (elink_active),
.rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p),
.rxo_rd_wait_n (rxo_rd_wait_n),
.txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]),
.chipid (chipid[11:0]),
.chip_nreset (chip_nreset),
.cclk_p (cclk_p),
.cclk_n (cclk_n),
.mailbox_irq (mailbox_irq),
.m_axi_awid (m_axi_awid[M_IDW-1:0]), // Templated
.m_axi_awaddr (m_axi_awaddr[31:0]), // Templated
.m_axi_awlen (m_axi_awlen[7:0]), // Templated
.m_axi_awsize (m_axi_awsize[2:0]), // Templated
.m_axi_awburst (m_axi_awburst[1:0]), // Templated
.m_axi_awlock (m_axi_awlock), // Templated
.m_axi_awcache (m_axi_awcache[3:0]), // Templated
.m_axi_awprot (m_axi_awprot[2:0]), // Templated
.m_axi_awqos (m_axi_awqos[3:0]), // Templated
.m_axi_awvalid (m_axi_awvalid), // Templated
.m_axi_wid (m_axi_wid[M_IDW-1:0]), // Templated
.m_axi_wdata (m_axi_wdata[63:0]), // Templated
.m_axi_wstrb (m_axi_wstrb[7:0]), // Templated
.m_axi_wlast (m_axi_wlast), // Templated
.m_axi_wvalid (m_axi_wvalid), // Templated
.m_axi_bready (m_axi_bready), // Templated
.m_axi_arid (m_axi_arid[M_IDW-1:0]), // Templated
.m_axi_araddr (m_axi_araddr[31:0]), // Templated
.m_axi_arlen (m_axi_arlen[7:0]), // Templated
.m_axi_arsize (m_axi_arsize[2:0]), // Templated
.m_axi_arburst (m_axi_arburst[1:0]), // Templated
.m_axi_arlock (m_axi_arlock), // Templated
.m_axi_arcache (m_axi_arcache[3:0]), // Templated
.m_axi_arprot (m_axi_arprot[2:0]), // Templated
.m_axi_arqos (m_axi_arqos[3:0]), // Templated
.m_axi_arvalid (m_axi_arvalid), // Templated
.m_axi_rready (m_axi_rready), // Templated
.s_axi_arready (s_axi_arready), // Templated
.s_axi_awready (s_axi_awready), // Templated
.s_axi_bid (s_axi_bid[S_IDW-1:0]), // Templated
.s_axi_bresp (s_axi_bresp[1:0]), // Templated
.s_axi_bvalid (s_axi_bvalid), // Templated
.s_axi_rid (s_axi_rid[S_IDW-1:0]), // Templated
.s_axi_rdata (s_axi_rdata[31:0]), // Templated
.s_axi_rlast (s_axi_rlast), // Templated
.s_axi_rresp (s_axi_rresp[1:0]), // Templated
.s_axi_rvalid (s_axi_rvalid), // Templated
.s_axi_wready (s_axi_wready), // Templated
// Inputs
.sys_nreset (sys_nreset),
.sys_clk (sys_clk),
.rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p),
.rxi_frame_n (rxi_frame_n),
.rxi_data_p (rxi_data_p[7:0]),
.rxi_data_n (rxi_data_n[7:0]),
.txi_wr_wait_p (txi_wr_wait_p),
.txi_wr_wait_n (txi_wr_wait_n),
.txi_rd_wait_p (txi_rd_wait_p),
.txi_rd_wait_n (txi_rd_wait_n),
.m_axi_aresetn (m_axi_aresetn), // Templated
.m_axi_awready (m_axi_awready), // Templated
.m_axi_wready (m_axi_wready), // Templated
.m_axi_bid (m_axi_bid[M_IDW-1:0]), // Templated
.m_axi_bresp (m_axi_bresp[1:0]), // Templated
.m_axi_bvalid (m_axi_bvalid), // Templated
.m_axi_arready (m_axi_arready), // Templated
.m_axi_rid (m_axi_rid[M_IDW-1:0]), // Templated
.m_axi_rdata (m_axi_rdata[63:0]), // Templated
.m_axi_rresp (m_axi_rresp[1:0]), // Templated
.m_axi_rlast (m_axi_rlast), // Templated
.m_axi_rvalid (m_axi_rvalid), // Templated
.s_axi_aresetn (s_axi_aresetn), // Templated
.s_axi_arid (s_axi_arid[S_IDW-1:0]), // Templated
.s_axi_araddr (s_axi_araddr[31:0]), // Templated
.s_axi_arburst (s_axi_arburst[1:0]), // Templated
.s_axi_arcache (s_axi_arcache[3:0]), // Templated
.s_axi_arlock (s_axi_arlock), // Templated
.s_axi_arlen (s_axi_arlen[7:0]), // Templated
.s_axi_arprot (s_axi_arprot[2:0]), // Templated
.s_axi_arqos (s_axi_arqos[3:0]), // Templated
.s_axi_arsize (s_axi_arsize[2:0]), // Templated
.s_axi_arvalid (s_axi_arvalid), // Templated
.s_axi_awid (s_axi_awid[S_IDW-1:0]), // Templated
.s_axi_awaddr (s_axi_awaddr[31:0]), // Templated
.s_axi_awburst (s_axi_awburst[1:0]), // Templated
.s_axi_awcache (s_axi_awcache[3:0]), // Templated
.s_axi_awlock (s_axi_awlock), // Templated
.s_axi_awlen (s_axi_awlen[7:0]), // Templated
.s_axi_awprot (s_axi_awprot[2:0]), // Templated
.s_axi_awqos (s_axi_awqos[3:0]), // Templated
.s_axi_awsize (s_axi_awsize[2:0]), // Templated
.s_axi_awvalid (s_axi_awvalid), // Templated
.s_axi_bready (s_axi_bready), // Templated
.s_axi_rready (s_axi_rready), // Templated
.s_axi_wid (s_axi_wid[S_IDW-1:0]), // Templated
.s_axi_wdata (s_axi_wdata[31:0]), // Templated
.s_axi_wlast (s_axi_wlast), // Templated
.s_axi_wstrb (s_axi_wstrb[3:0]), // Templated
.s_axi_wvalid (s_axi_wvalid)); // Templated
pgpio #(.NGPIO(NGPIO)) pgpio (/*AUTOINST*/
// Outputs
.ps_gpio_i (ps_gpio_i[NPS-1:0]),
// Inouts
.gpio_p (gpio_p[NGPIO-1:0]),
.gpio_n (gpio_n[NGPIO-1:0]),
// Inputs
.ps_gpio_o (ps_gpio_o[NPS-1:0]),
.ps_gpio_t (ps_gpio_t[NPS-1:0]));
pi2c pi2c (/*AUTOINST*/
// Outputs
.i2c_sda_i (i2c_sda_i),
.i2c_scl_i (i2c_scl_i),
// Inouts
.i2c_sda (i2c_sda),
.i2c_scl (i2c_scl),
// Inputs
.i2c_sda_o (i2c_sda_o),
.i2c_sda_t (i2c_sda_t),
.i2c_scl_o (i2c_scl_o),
.i2c_scl_t (i2c_scl_t));
endmodule // parallella_generic
// Local Variables:
// verilog-library-directories:("." "../../elink/hdl")
// End:
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Nov 10 01:13:52 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, n167, n168, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196,
n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251,
n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284,
n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306,
n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317,
n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328,
n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350,
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DP_OP_153J132_122_5442_n296, DP_OP_153J132_122_5442_n293,
DP_OP_153J132_122_5442_n292, DP_OP_153J132_122_5442_n290,
DP_OP_153J132_122_5442_n289, DP_OP_153J132_122_5442_n288,
DP_OP_153J132_122_5442_n287, DP_OP_153J132_122_5442_n282,
DP_OP_153J132_122_5442_n274, DP_OP_153J132_122_5442_n273,
DP_OP_153J132_122_5442_n271, DP_OP_153J132_122_5442_n270,
DP_OP_153J132_122_5442_n269, DP_OP_153J132_122_5442_n268,
DP_OP_153J132_122_5442_n266, DP_OP_153J132_122_5442_n265,
DP_OP_153J132_122_5442_n264, DP_OP_153J132_122_5442_n263,
DP_OP_153J132_122_5442_n262, DP_OP_153J132_122_5442_n261,
DP_OP_153J132_122_5442_n259, DP_OP_153J132_122_5442_n258,
DP_OP_153J132_122_5442_n257, DP_OP_153J132_122_5442_n256,
DP_OP_153J132_122_5442_n255, DP_OP_153J132_122_5442_n254,
DP_OP_153J132_122_5442_n253, DP_OP_153J132_122_5442_n252,
DP_OP_153J132_122_5442_n251, DP_OP_153J132_122_5442_n250,
DP_OP_153J132_122_5442_n249, DP_OP_153J132_122_5442_n248,
DP_OP_153J132_122_5442_n247, DP_OP_153J132_122_5442_n234,
DP_OP_153J132_122_5442_n229, DP_OP_153J132_122_5442_n228,
DP_OP_153J132_122_5442_n227, DP_OP_153J132_122_5442_n224,
DP_OP_153J132_122_5442_n205, DP_OP_153J132_122_5442_n204,
DP_OP_153J132_122_5442_n203, DP_OP_153J132_122_5442_n202,
DP_OP_153J132_122_5442_n201, DP_OP_153J132_122_5442_n200,
DP_OP_153J132_122_5442_n196, DP_OP_153J132_122_5442_n195,
DP_OP_153J132_122_5442_n194, DP_OP_153J132_122_5442_n193,
DP_OP_153J132_122_5442_n192, DP_OP_153J132_122_5442_n191,
DP_OP_153J132_122_5442_n187, DP_OP_153J132_122_5442_n186,
DP_OP_153J132_122_5442_n185, DP_OP_153J132_122_5442_n184,
DP_OP_153J132_122_5442_n183, DP_OP_153J132_122_5442_n182,
DP_OP_153J132_122_5442_n177, DP_OP_153J132_122_5442_n176,
DP_OP_153J132_122_5442_n175, DP_OP_153J132_122_5442_n174,
DP_OP_153J132_122_5442_n173, DP_OP_153J132_122_5442_n169,
DP_OP_153J132_122_5442_n167, DP_OP_153J132_122_5442_n166,
DP_OP_153J132_122_5442_n165, DP_OP_153J132_122_5442_n162,
DP_OP_153J132_122_5442_n161, DP_OP_153J132_122_5442_n159,
DP_OP_153J132_122_5442_n158, DP_OP_153J132_122_5442_n157,
DP_OP_153J132_122_5442_n156, DP_OP_153J132_122_5442_n155,
DP_OP_153J132_122_5442_n154, DP_OP_153J132_122_5442_n151,
DP_OP_153J132_122_5442_n150, DP_OP_153J132_122_5442_n149,
DP_OP_153J132_122_5442_n148, DP_OP_153J132_122_5442_n145,
DP_OP_153J132_122_5442_n133, DP_OP_153J132_122_5442_n128,
DP_OP_153J132_122_5442_n127, DP_OP_153J132_122_5442_n125,
DP_OP_153J132_122_5442_n124, DP_OP_153J132_122_5442_n123,
DP_OP_153J132_122_5442_n122, DP_OP_153J132_122_5442_n121,
DP_OP_153J132_122_5442_n120, DP_OP_153J132_122_5442_n119,
DP_OP_153J132_122_5442_n118, DP_OP_153J132_122_5442_n117,
DP_OP_153J132_122_5442_n116, DP_OP_153J132_122_5442_n115,
DP_OP_153J132_122_5442_n113, DP_OP_153J132_122_5442_n112,
DP_OP_153J132_122_5442_n111, DP_OP_153J132_122_5442_n110,
DP_OP_153J132_122_5442_n109, DP_OP_153J132_122_5442_n108,
DP_OP_153J132_122_5442_n107, DP_OP_153J132_122_5442_n106,
DP_OP_153J132_122_5442_n105, DP_OP_153J132_122_5442_n104,
DP_OP_153J132_122_5442_n103, DP_OP_153J132_122_5442_n102,
DP_OP_153J132_122_5442_n101, DP_OP_153J132_122_5442_n100,
DP_OP_153J132_122_5442_n99, DP_OP_153J132_122_5442_n98,
DP_OP_153J132_122_5442_n97, DP_OP_153J132_122_5442_n95,
DP_OP_153J132_122_5442_n94, DP_OP_153J132_122_5442_n93,
DP_OP_153J132_122_5442_n92, DP_OP_153J132_122_5442_n91,
DP_OP_153J132_122_5442_n90, DP_OP_153J132_122_5442_n89,
DP_OP_153J132_122_5442_n88, DP_OP_153J132_122_5442_n87,
DP_OP_153J132_122_5442_n84, DP_OP_153J132_122_5442_n83,
DP_OP_153J132_122_5442_n82, DP_OP_153J132_122_5442_n81,
DP_OP_153J132_122_5442_n80, DP_OP_153J132_122_5442_n79,
DP_OP_153J132_122_5442_n78, DP_OP_153J132_122_5442_n77,
DP_OP_153J132_122_5442_n76, DP_OP_153J132_122_5442_n75,
DP_OP_153J132_122_5442_n74, DP_OP_153J132_122_5442_n73,
DP_OP_153J132_122_5442_n72, DP_OP_153J132_122_5442_n71,
DP_OP_153J132_122_5442_n70, DP_OP_153J132_122_5442_n69,
DP_OP_153J132_122_5442_n68, DP_OP_153J132_122_5442_n67,
DP_OP_153J132_122_5442_n66, DP_OP_153J132_122_5442_n65,
DP_OP_153J132_122_5442_n64, DP_OP_153J132_122_5442_n63,
DP_OP_153J132_122_5442_n62, DP_OP_153J132_122_5442_n61,
DP_OP_153J132_122_5442_n60, DP_OP_153J132_122_5442_n59,
DP_OP_153J132_122_5442_n58, DP_OP_153J132_122_5442_n57,
DP_OP_153J132_122_5442_n56, DP_OP_153J132_122_5442_n55,
DP_OP_153J132_122_5442_n54, DP_OP_153J132_122_5442_n53,
DP_OP_153J132_122_5442_n52, DP_OP_153J132_122_5442_n51,
DP_OP_153J132_122_5442_n50, DP_OP_153J132_122_5442_n49,
DP_OP_153J132_122_5442_n48, DP_OP_153J132_122_5442_n47,
DP_OP_153J132_122_5442_n46, DP_OP_153J132_122_5442_n45,
DP_OP_153J132_122_5442_n44, DP_OP_153J132_122_5442_n43,
DP_OP_153J132_122_5442_n42, DP_OP_153J132_122_5442_n41,
DP_OP_153J132_122_5442_n40, DP_OP_153J132_122_5442_n38,
DP_OP_153J132_122_5442_n37, DP_OP_153J132_122_5442_n36,
DP_OP_153J132_122_5442_n35, DP_OP_153J132_122_5442_n34,
DP_OP_153J132_122_5442_n33, DP_OP_153J132_122_5442_n32,
DP_OP_153J132_122_5442_n31, DP_OP_153J132_122_5442_n30,
DP_OP_153J132_122_5442_n29, DP_OP_153J132_122_5442_n28,
DP_OP_153J132_122_5442_n27, DP_OP_153J132_122_5442_n26,
DP_OP_153J132_122_5442_n25, DP_OP_153J132_122_5442_n23,
DP_OP_153J132_122_5442_n22, DP_OP_153J132_122_5442_n21,
DP_OP_36J132_126_4699_n33, DP_OP_36J132_126_4699_n22,
DP_OP_36J132_126_4699_n21, DP_OP_36J132_126_4699_n20,
DP_OP_36J132_126_4699_n19, DP_OP_36J132_126_4699_n18,
DP_OP_36J132_126_4699_n17, DP_OP_36J132_126_4699_n16,
DP_OP_36J132_126_4699_n15, DP_OP_36J132_126_4699_n9,
DP_OP_36J132_126_4699_n8, DP_OP_36J132_126_4699_n7,
DP_OP_36J132_126_4699_n6, DP_OP_36J132_126_4699_n5,
DP_OP_36J132_126_4699_n4, DP_OP_36J132_126_4699_n3,
DP_OP_36J132_126_4699_n2, DP_OP_36J132_126_4699_n1, n391, n393, n394,
n395, n396, n397, n398, n399, n400, n401, n402, n403, n404, n405,
n406, n407, n408, n409, n410, n411, n412, n413, n414, n415, n416,
n417, n418, n419, n420, n421, n422, n423, n424, n425, n426, n427,
n428, n429, n430, n431, n432, n433, n434, n435, n436, n437, n438,
n439, n440, n441, n442, n443, n444, n445, n446, n447, n448, n449,
n450, n451, n452, n453, n454, n455, n456, n457, n458, n459, n460,
n461, n462, n463, n464, n465, n466, n467, n468, n469, n470, n471,
n472, n473, n474, n475, n476, n477, n478, n479, n480, n481, n482,
n483, n484, n485, n486, n487, n488, n489, n490, n491, n492, n493,
n494, n495, n496, n497, n498, n499, n500, n501, n502, n503, n504,
n505, n506, n507, n508, n509, n510, n511, n512, n513, n514, n515,
n516, n517, n518, n519, n520, n521, n522, n523, n524, n525, n526,
n527, n528, n529, n530, n531, n532, n533, n534, n535, n536, n537,
n538, n539, n540, n541, n542, n543, n544, n545, n546, n547, n548,
n549, n550, n551, n552, n553, n554, n555, n556, n557, n558, n559,
n560, n561, n562, n563, n564, n565, n566, n567, n568, n569, n570,
n571, n572, n573, n574, n575, n576, n577, n578, n579, n580, n581,
n582, n583, n584, n585, n586, n587, n588, n589, n590, n591, n592,
n593, n594, n595, n596, n597, n598, n599, n600, n601, n602, n603,
n604, n605, n606, n607, n608, n609, n610, n611, n612, n613, n614,
n615, n616, n617, n618, n619, n620, n621, n622, n623, n624, n625,
n626, n627, n628, n629, n630, n631, n632, n633, n634, n635, n636,
n637, n638, n639, n640, n641, n642, n643, n644, n645, n646, n647,
n648, n649, n650, n651, n652, n653, n654, n655, n656, n657, n658,
n659, n660, n661, n662, n663, n664, n665, n666, n667, n668, n669,
n670, n671, n672, n673, n674, n675, n676, n677, n678, n679, n680,
n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691,
n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702,
n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713,
n714, n715, n716, n717, n718, n719, n720, n721, n722, n723, n724,
n725, n726, n727, n728, n729, n730, n731, n732, n733, n734, n735,
n736, n737, n738, n739, n740, n741, n742, n743, n744, n745, n746,
n747, n748, n749, n750, n751, n752, n753, n754, n755, n756, n757,
n758, n759, n760, n761, n762, n763, n764, n765, n766, n767, n768,
n769, n770, n771, n772, n773, n774, n775, n776, n777, n778, n779,
n780, n781, n782, n783, n784, n785, n786, n787, n788, n789, n790,
n791, n792, n793, n794, n795, n796, n797, n798, n799, n800, n801,
n802, n803, n804, n805, n806, n807, n808, n809, n810, n811, n812,
n813, n814, n815, n816, n817, n818, n819, n820, n821, n822, n823,
n824, n825, n826, n827, n828, n829, n830, n831, n832, n833, n834,
n835, n836, n837, n838, n839, n840, n841, n842, n843, n844, n845,
n846, n847, n848, n849, n850, n851, n852, n853, n854, n855, n856,
n857, n858, n859, n860, n861, n862, n863, n864, n865, n866, n867,
n868, n869, n870, n871, n872, n873, n874, n875, n876, n877, n878,
n879, n880, n881, n882, n883, n884, n885, n886, n887, n888, n889,
n890, n891, n892, n893, n894, n895, n896, n897, n898, n899, n900,
n901, n902, n903, n904, n905, n906, n907, n908, n909, n910, n911,
n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922,
n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933,
n934, n935, n936, n937, n938, n939, n940, n941, n942, n943, n944,
n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955,
n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966,
n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999,
n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009,
n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019,
n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029,
n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039,
n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049,
n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059,
n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069,
n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079,
n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089,
n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099,
n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109,
n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119,
n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129,
n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139,
n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149,
n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159,
n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169,
n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239,
n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249,
n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259,
n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269,
n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279,
n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289,
n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299,
n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309,
n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319,
n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329,
n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339,
n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349,
n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359,
n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369,
n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379,
n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389,
n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399,
n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409,
n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419,
n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429,
n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439,
n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449,
n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459,
n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469,
n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479,
n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489,
n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499,
n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509,
n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519,
n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529,
n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539,
n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549,
n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559,
n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569,
n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579,
n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589,
n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599,
n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609,
n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619,
n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629,
n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639,
n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649,
n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659,
n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669,
n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679,
n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689,
n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699,
n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709,
n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719,
n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769,
n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779,
n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789,
n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
wire [11:8] Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [16:1] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [13:8] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [9:0] Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [11:8] Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left;
CMPR42X1TS DP_OP_156J132_125_3370_U46 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .C(
DP_OP_156J132_125_3370_n110), .D(DP_OP_156J132_125_3370_n133), .ICI(
DP_OP_156J132_125_3370_n81), .S(DP_OP_156J132_125_3370_n78), .ICO(
DP_OP_156J132_125_3370_n76), .CO(DP_OP_156J132_125_3370_n77) );
CMPR42X1TS DP_OP_156J132_125_3370_U45 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]), .C(
DP_OP_156J132_125_3370_n109), .D(DP_OP_156J132_125_3370_n132), .ICI(
DP_OP_156J132_125_3370_n76), .S(DP_OP_156J132_125_3370_n75), .ICO(
DP_OP_156J132_125_3370_n73), .CO(DP_OP_156J132_125_3370_n74) );
CMPR42X1TS DP_OP_156J132_125_3370_U44 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]), .C(
DP_OP_156J132_125_3370_n108), .D(DP_OP_156J132_125_3370_n131), .ICI(
DP_OP_156J132_125_3370_n73), .S(DP_OP_156J132_125_3370_n72), .ICO(
DP_OP_156J132_125_3370_n70), .CO(DP_OP_156J132_125_3370_n71) );
CMPR42X1TS DP_OP_156J132_125_3370_U43 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]), .C(
DP_OP_156J132_125_3370_n107), .D(DP_OP_156J132_125_3370_n130), .ICI(
DP_OP_156J132_125_3370_n70), .S(DP_OP_156J132_125_3370_n69), .ICO(
DP_OP_156J132_125_3370_n67), .CO(DP_OP_156J132_125_3370_n68) );
CMPR42X1TS DP_OP_156J132_125_3370_U42 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]), .C(
DP_OP_156J132_125_3370_n106), .D(DP_OP_156J132_125_3370_n129), .ICI(
DP_OP_156J132_125_3370_n67), .S(DP_OP_156J132_125_3370_n66), .ICO(
DP_OP_156J132_125_3370_n64), .CO(DP_OP_156J132_125_3370_n65) );
CMPR42X1TS DP_OP_156J132_125_3370_U41 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .C(
DP_OP_156J132_125_3370_n105), .D(DP_OP_156J132_125_3370_n128), .ICI(
DP_OP_156J132_125_3370_n64), .S(DP_OP_156J132_125_3370_n63), .ICO(
DP_OP_156J132_125_3370_n61), .CO(DP_OP_156J132_125_3370_n62) );
CMPR42X1TS DP_OP_156J132_125_3370_U40 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .C(
DP_OP_156J132_125_3370_n104), .D(DP_OP_156J132_125_3370_n127), .ICI(
DP_OP_156J132_125_3370_n61), .S(DP_OP_156J132_125_3370_n60), .ICO(
DP_OP_156J132_125_3370_n58), .CO(DP_OP_156J132_125_3370_n59) );
CMPR42X1TS DP_OP_156J132_125_3370_U39 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .C(
DP_OP_156J132_125_3370_n103), .D(DP_OP_156J132_125_3370_n126), .ICI(
DP_OP_156J132_125_3370_n58), .S(DP_OP_156J132_125_3370_n57), .ICO(
DP_OP_156J132_125_3370_n55), .CO(DP_OP_156J132_125_3370_n56) );
CMPR42X1TS DP_OP_156J132_125_3370_U38 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .C(
DP_OP_156J132_125_3370_n102), .D(DP_OP_156J132_125_3370_n125), .ICI(
DP_OP_156J132_125_3370_n55), .S(DP_OP_156J132_125_3370_n54), .ICO(
DP_OP_156J132_125_3370_n52), .CO(DP_OP_156J132_125_3370_n53) );
CMPR42X1TS DP_OP_156J132_125_3370_U37 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .C(
DP_OP_156J132_125_3370_n101), .D(DP_OP_156J132_125_3370_n124), .ICI(
DP_OP_156J132_125_3370_n52), .S(DP_OP_156J132_125_3370_n51), .ICO(
DP_OP_156J132_125_3370_n49), .CO(DP_OP_156J132_125_3370_n50) );
CMPR42X1TS DP_OP_156J132_125_3370_U36 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .C(
DP_OP_156J132_125_3370_n100), .D(DP_OP_156J132_125_3370_n123), .ICI(
DP_OP_156J132_125_3370_n49), .S(DP_OP_156J132_125_3370_n48), .ICO(
DP_OP_156J132_125_3370_n46), .CO(DP_OP_156J132_125_3370_n47) );
CMPR42X1TS DP_OP_156J132_125_3370_U35 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .C(
DP_OP_156J132_125_3370_n99), .D(DP_OP_156J132_125_3370_n122), .ICI(
DP_OP_156J132_125_3370_n46), .S(DP_OP_156J132_125_3370_n45), .ICO(
DP_OP_156J132_125_3370_n43), .CO(DP_OP_156J132_125_3370_n44) );
CMPR42X1TS DP_OP_156J132_125_3370_U34 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .C(
DP_OP_156J132_125_3370_n98), .D(DP_OP_156J132_125_3370_n121), .ICI(
DP_OP_156J132_125_3370_n43), .S(DP_OP_156J132_125_3370_n42), .ICO(
DP_OP_156J132_125_3370_n40), .CO(DP_OP_156J132_125_3370_n41) );
CMPR42X1TS DP_OP_156J132_125_3370_U33 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .C(
DP_OP_156J132_125_3370_n97), .D(DP_OP_156J132_125_3370_n120), .ICI(
DP_OP_156J132_125_3370_n40), .S(DP_OP_156J132_125_3370_n39), .ICO(
DP_OP_156J132_125_3370_n37), .CO(DP_OP_156J132_125_3370_n38) );
CMPR42X1TS DP_OP_156J132_125_3370_U32 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .C(
DP_OP_156J132_125_3370_n96), .D(DP_OP_156J132_125_3370_n119), .ICI(
DP_OP_156J132_125_3370_n37), .S(DP_OP_156J132_125_3370_n36), .ICO(
DP_OP_156J132_125_3370_n34), .CO(DP_OP_156J132_125_3370_n35) );
CMPR42X1TS DP_OP_156J132_125_3370_U31 ( .A(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .C(
DP_OP_156J132_125_3370_n95), .D(DP_OP_156J132_125_3370_n118), .ICI(
DP_OP_156J132_125_3370_n34), .S(DP_OP_156J132_125_3370_n33), .ICO(
DP_OP_156J132_125_3370_n31), .CO(DP_OP_156J132_125_3370_n32) );
CMPR42X1TS DP_OP_155J132_124_2038_U253 ( .A(DP_OP_155J132_124_2038_n370),
.B(DP_OP_155J132_124_2038_n360), .C(DP_OP_155J132_124_2038_n365), .D(
DP_OP_155J132_124_2038_n335), .ICI(DP_OP_155J132_124_2038_n332), .S(
DP_OP_155J132_124_2038_n330), .ICO(DP_OP_155J132_124_2038_n328), .CO(
DP_OP_155J132_124_2038_n329) );
CMPR42X1TS DP_OP_155J132_124_2038_U250 ( .A(DP_OP_155J132_124_2038_n364),
.B(DP_OP_155J132_124_2038_n331), .C(DP_OP_155J132_124_2038_n328), .D(
DP_OP_155J132_124_2038_n327), .ICI(DP_OP_155J132_124_2038_n325), .S(
DP_OP_155J132_124_2038_n323), .ICO(DP_OP_155J132_124_2038_n321), .CO(
DP_OP_155J132_124_2038_n322) );
CMPR42X1TS DP_OP_155J132_124_2038_U247 ( .A(DP_OP_155J132_124_2038_n326),
.B(DP_OP_155J132_124_2038_n324), .C(DP_OP_155J132_124_2038_n320), .D(
DP_OP_155J132_124_2038_n318), .ICI(DP_OP_155J132_124_2038_n321), .S(
DP_OP_155J132_124_2038_n316), .ICO(DP_OP_155J132_124_2038_n314), .CO(
DP_OP_155J132_124_2038_n315) );
CMPR42X1TS DP_OP_155J132_124_2038_U245 ( .A(DP_OP_155J132_124_2038_n352),
.B(DP_OP_155J132_124_2038_n319), .C(DP_OP_155J132_124_2038_n317), .D(
DP_OP_155J132_124_2038_n313), .ICI(DP_OP_155J132_124_2038_n314), .S(
DP_OP_155J132_124_2038_n311), .ICO(DP_OP_155J132_124_2038_n309), .CO(
DP_OP_155J132_124_2038_n310) );
CMPR42X1TS DP_OP_155J132_124_2038_U244 ( .A(DP_OP_155J132_124_2038_n351),
.B(DP_OP_155J132_124_2038_n341), .C(DP_OP_155J132_124_2038_n346), .D(
DP_OP_155J132_124_2038_n312), .ICI(DP_OP_155J132_124_2038_n309), .S(
DP_OP_155J132_124_2038_n308), .ICO(DP_OP_155J132_124_2038_n306), .CO(
DP_OP_155J132_124_2038_n307) );
CMPR42X1TS DP_OP_155J132_124_2038_U180 ( .A(DP_OP_155J132_124_2038_n279),
.B(DP_OP_155J132_124_2038_n269), .C(DP_OP_155J132_124_2038_n274), .D(
n402), .ICI(DP_OP_155J132_124_2038_n241), .S(
DP_OP_155J132_124_2038_n239), .ICO(DP_OP_155J132_124_2038_n237), .CO(
DP_OP_155J132_124_2038_n238) );
CMPR42X1TS DP_OP_155J132_124_2038_U177 ( .A(DP_OP_155J132_124_2038_n273),
.B(DP_OP_155J132_124_2038_n240), .C(DP_OP_155J132_124_2038_n237), .D(
DP_OP_155J132_124_2038_n236), .ICI(DP_OP_155J132_124_2038_n234), .S(
DP_OP_155J132_124_2038_n232), .ICO(DP_OP_155J132_124_2038_n230), .CO(
DP_OP_155J132_124_2038_n231) );
CMPR42X1TS DP_OP_155J132_124_2038_U174 ( .A(DP_OP_155J132_124_2038_n235),
.B(DP_OP_155J132_124_2038_n233), .C(DP_OP_155J132_124_2038_n229), .D(
DP_OP_155J132_124_2038_n227), .ICI(DP_OP_155J132_124_2038_n230), .S(
DP_OP_155J132_124_2038_n225), .ICO(DP_OP_155J132_124_2038_n223), .CO(
DP_OP_155J132_124_2038_n224) );
CMPR42X1TS DP_OP_155J132_124_2038_U172 ( .A(DP_OP_155J132_124_2038_n261),
.B(DP_OP_155J132_124_2038_n228), .C(DP_OP_155J132_124_2038_n226), .D(
DP_OP_155J132_124_2038_n222), .ICI(DP_OP_155J132_124_2038_n223), .S(
DP_OP_155J132_124_2038_n220), .ICO(DP_OP_155J132_124_2038_n218), .CO(
DP_OP_155J132_124_2038_n219) );
CMPR42X1TS DP_OP_155J132_124_2038_U171 ( .A(DP_OP_155J132_124_2038_n260),
.B(DP_OP_155J132_124_2038_n250), .C(DP_OP_155J132_124_2038_n255), .D(
DP_OP_155J132_124_2038_n221), .ICI(DP_OP_155J132_124_2038_n218), .S(
DP_OP_155J132_124_2038_n217), .ICO(DP_OP_155J132_124_2038_n215), .CO(
DP_OP_155J132_124_2038_n216) );
CMPR42X1TS DP_OP_155J132_124_2038_U39 ( .A(DP_OP_155J132_124_2038_n202), .B(
DP_OP_155J132_124_2038_n87), .C(DP_OP_155J132_124_2038_n201), .D(
DP_OP_155J132_124_2038_n118), .ICI(DP_OP_155J132_124_2038_n125), .S(
DP_OP_155J132_124_2038_n75), .ICO(DP_OP_155J132_124_2038_n73), .CO(
DP_OP_155J132_124_2038_n74) );
CMPR42X1TS DP_OP_155J132_124_2038_U37 ( .A(DP_OP_155J132_124_2038_n86), .B(
DP_OP_155J132_124_2038_n124), .C(DP_OP_155J132_124_2038_n72), .D(
DP_OP_155J132_124_2038_n117), .ICI(DP_OP_155J132_124_2038_n91), .S(
DP_OP_155J132_124_2038_n70), .ICO(DP_OP_155J132_124_2038_n68), .CO(
DP_OP_155J132_124_2038_n69) );
CMPR42X1TS DP_OP_155J132_124_2038_U35 ( .A(DP_OP_155J132_124_2038_n116), .B(
DP_OP_155J132_124_2038_n109), .C(DP_OP_155J132_124_2038_n123), .D(
DP_OP_155J132_124_2038_n68), .ICI(DP_OP_155J132_124_2038_n67), .S(
DP_OP_155J132_124_2038_n65), .ICO(DP_OP_155J132_124_2038_n63), .CO(
DP_OP_155J132_124_2038_n64) );
CMPR42X1TS DP_OP_155J132_124_2038_U32 ( .A(DP_OP_155J132_124_2038_n122), .B(
DP_OP_155J132_124_2038_n62), .C(DP_OP_155J132_124_2038_n108), .D(
DP_OP_155J132_124_2038_n90), .ICI(DP_OP_155J132_124_2038_n60), .S(
DP_OP_155J132_124_2038_n58), .ICO(DP_OP_155J132_124_2038_n56), .CO(
DP_OP_155J132_124_2038_n57) );
CMPR42X1TS DP_OP_155J132_124_2038_U31 ( .A(DP_OP_155J132_124_2038_n114), .B(
DP_OP_155J132_124_2038_n61), .C(DP_OP_155J132_124_2038_n83), .D(
DP_OP_155J132_124_2038_n197), .ICI(DP_OP_155J132_124_2038_n100), .S(
DP_OP_155J132_124_2038_n55), .ICO(DP_OP_155J132_124_2038_n53), .CO(
DP_OP_155J132_124_2038_n54) );
CMPR42X1TS DP_OP_155J132_124_2038_U30 ( .A(DP_OP_155J132_124_2038_n121), .B(
DP_OP_155J132_124_2038_n107), .C(DP_OP_155J132_124_2038_n59), .D(
DP_OP_155J132_124_2038_n56), .ICI(DP_OP_155J132_124_2038_n55), .S(
DP_OP_155J132_124_2038_n52), .ICO(DP_OP_155J132_124_2038_n50), .CO(
DP_OP_155J132_124_2038_n51) );
CMPR42X1TS DP_OP_155J132_124_2038_U29 ( .A(DP_OP_155J132_124_2038_n120), .B(
DP_OP_155J132_124_2038_n113), .C(DP_OP_155J132_124_2038_n106), .D(
DP_OP_155J132_124_2038_n99), .ICI(DP_OP_155J132_124_2038_n82), .S(
DP_OP_155J132_124_2038_n49), .ICO(DP_OP_155J132_124_2038_n47), .CO(
DP_OP_155J132_124_2038_n48) );
CMPR42X1TS DP_OP_155J132_124_2038_U28 ( .A(DP_OP_155J132_124_2038_n53), .B(
DP_OP_155J132_124_2038_n196), .C(DP_OP_155J132_124_2038_n50), .D(
DP_OP_155J132_124_2038_n54), .ICI(DP_OP_155J132_124_2038_n49), .S(
DP_OP_155J132_124_2038_n46), .ICO(DP_OP_155J132_124_2038_n44), .CO(
DP_OP_155J132_124_2038_n45) );
CMPR42X1TS DP_OP_155J132_124_2038_U27 ( .A(DP_OP_155J132_124_2038_n119), .B(
DP_OP_155J132_124_2038_n112), .C(DP_OP_155J132_124_2038_n105), .D(
DP_OP_155J132_124_2038_n98), .ICI(DP_OP_155J132_124_2038_n47), .S(
DP_OP_155J132_124_2038_n43), .ICO(DP_OP_155J132_124_2038_n41), .CO(
DP_OP_155J132_124_2038_n42) );
CMPR42X1TS DP_OP_155J132_124_2038_U26 ( .A(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .B(
DP_OP_155J132_124_2038_n81), .C(DP_OP_155J132_124_2038_n48), .D(
DP_OP_155J132_124_2038_n44), .ICI(DP_OP_155J132_124_2038_n43), .S(
DP_OP_155J132_124_2038_n40), .ICO(DP_OP_155J132_124_2038_n38), .CO(
DP_OP_155J132_124_2038_n39) );
CMPR42X1TS DP_OP_155J132_124_2038_U25 ( .A(DP_OP_155J132_124_2038_n111), .B(
DP_OP_155J132_124_2038_n104), .C(DP_OP_155J132_124_2038_n97), .D(
DP_OP_155J132_124_2038_n41), .ICI(DP_OP_155J132_124_2038_n195), .S(
DP_OP_155J132_124_2038_n37), .ICO(DP_OP_155J132_124_2038_n35), .CO(
DP_OP_155J132_124_2038_n36) );
CMPR42X1TS DP_OP_155J132_124_2038_U24 ( .A(DP_OP_155J132_124_2038_n42), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .C(
DP_OP_155J132_124_2038_n80), .D(DP_OP_155J132_124_2038_n38), .ICI(
DP_OP_155J132_124_2038_n37), .S(DP_OP_155J132_124_2038_n34), .ICO(
DP_OP_155J132_124_2038_n32), .CO(DP_OP_155J132_124_2038_n33) );
CMPR42X1TS DP_OP_155J132_124_2038_U23 ( .A(DP_OP_155J132_124_2038_n110), .B(
DP_OP_155J132_124_2038_n103), .C(DP_OP_155J132_124_2038_n96), .D(
DP_OP_155J132_124_2038_n35), .ICI(DP_OP_155J132_124_2038_n194), .S(
DP_OP_155J132_124_2038_n31), .ICO(DP_OP_155J132_124_2038_n29), .CO(
DP_OP_155J132_124_2038_n30) );
CMPR42X1TS DP_OP_155J132_124_2038_U22 ( .A(DP_OP_155J132_124_2038_n36), .B(
DP_OP_155J132_124_2038_n32), .C(DP_OP_155J132_124_2038_n193), .D(
DP_OP_155J132_124_2038_n79), .ICI(DP_OP_155J132_124_2038_n31), .S(
DP_OP_155J132_124_2038_n28), .ICO(DP_OP_155J132_124_2038_n26), .CO(
DP_OP_155J132_124_2038_n27) );
CMPR42X1TS DP_OP_155J132_124_2038_U20 ( .A(DP_OP_155J132_124_2038_n25), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .C(
DP_OP_155J132_124_2038_n30), .D(DP_OP_155J132_124_2038_n78), .ICI(
DP_OP_155J132_124_2038_n26), .S(DP_OP_155J132_124_2038_n23), .ICO(
DP_OP_155J132_124_2038_n21), .CO(DP_OP_155J132_124_2038_n22) );
CMPR42X1TS DP_OP_155J132_124_2038_U19 ( .A(DP_OP_155J132_124_2038_n94), .B(
DP_OP_155J132_124_2038_n101), .C(DP_OP_155J132_124_2038_n24), .D(
DP_OP_155J132_124_2038_n192), .ICI(DP_OP_155J132_124_2038_n21), .S(
DP_OP_155J132_124_2038_n20), .ICO(DP_OP_155J132_124_2038_n18), .CO(
DP_OP_155J132_124_2038_n19) );
CMPR42X1TS DP_OP_154J132_123_2038_U254 ( .A(DP_OP_154J132_123_2038_n369),
.B(DP_OP_154J132_123_2038_n359), .C(DP_OP_154J132_123_2038_n364), .D(
DP_OP_154J132_123_2038_n335), .ICI(DP_OP_154J132_123_2038_n332), .S(
DP_OP_154J132_123_2038_n330), .ICO(DP_OP_154J132_123_2038_n328), .CO(
DP_OP_154J132_123_2038_n329) );
CMPR42X1TS DP_OP_154J132_123_2038_U251 ( .A(DP_OP_154J132_123_2038_n358),
.B(DP_OP_154J132_123_2038_n331), .C(DP_OP_154J132_123_2038_n328), .D(
DP_OP_154J132_123_2038_n327), .ICI(DP_OP_154J132_123_2038_n325), .S(
DP_OP_154J132_123_2038_n323), .ICO(DP_OP_154J132_123_2038_n321), .CO(
DP_OP_154J132_123_2038_n322) );
CMPR42X1TS DP_OP_154J132_123_2038_U248 ( .A(DP_OP_154J132_123_2038_n326),
.B(DP_OP_154J132_123_2038_n320), .C(DP_OP_154J132_123_2038_n324), .D(
DP_OP_154J132_123_2038_n318), .ICI(DP_OP_154J132_123_2038_n321), .S(
DP_OP_154J132_123_2038_n316), .ICO(DP_OP_154J132_123_2038_n314), .CO(
DP_OP_154J132_123_2038_n315) );
CMPR42X1TS DP_OP_154J132_123_2038_U246 ( .A(DP_OP_154J132_123_2038_n351),
.B(DP_OP_154J132_123_2038_n319), .C(DP_OP_154J132_123_2038_n313), .D(
DP_OP_154J132_123_2038_n317), .ICI(DP_OP_154J132_123_2038_n314), .S(
DP_OP_154J132_123_2038_n311), .ICO(DP_OP_154J132_123_2038_n309), .CO(
DP_OP_154J132_123_2038_n310) );
CMPR42X1TS DP_OP_154J132_123_2038_U245 ( .A(Op_MX[21]), .B(Op_MY[21]), .C(
DP_OP_154J132_123_2038_n345), .D(DP_OP_154J132_123_2038_n312), .ICI(
DP_OP_154J132_123_2038_n309), .S(DP_OP_154J132_123_2038_n308), .ICO(
DP_OP_154J132_123_2038_n306), .CO(DP_OP_154J132_123_2038_n307) );
CMPR42X1TS DP_OP_154J132_123_2038_U180 ( .A(DP_OP_154J132_123_2038_n279),
.B(DP_OP_154J132_123_2038_n269), .C(DP_OP_154J132_123_2038_n274), .D(
DP_OP_154J132_123_2038_n244), .ICI(DP_OP_154J132_123_2038_n241), .S(
DP_OP_154J132_123_2038_n239), .ICO(DP_OP_154J132_123_2038_n237), .CO(
DP_OP_154J132_123_2038_n238) );
CMPR42X1TS DP_OP_154J132_123_2038_U177 ( .A(DP_OP_154J132_123_2038_n273),
.B(DP_OP_154J132_123_2038_n240), .C(DP_OP_154J132_123_2038_n237), .D(
DP_OP_154J132_123_2038_n236), .ICI(DP_OP_154J132_123_2038_n234), .S(
DP_OP_154J132_123_2038_n232), .ICO(DP_OP_154J132_123_2038_n230), .CO(
DP_OP_154J132_123_2038_n231) );
CMPR42X1TS DP_OP_154J132_123_2038_U174 ( .A(DP_OP_154J132_123_2038_n235),
.B(DP_OP_154J132_123_2038_n233), .C(DP_OP_154J132_123_2038_n229), .D(
DP_OP_154J132_123_2038_n227), .ICI(DP_OP_154J132_123_2038_n230), .S(
DP_OP_154J132_123_2038_n225), .ICO(DP_OP_154J132_123_2038_n223), .CO(
DP_OP_154J132_123_2038_n224) );
CMPR42X1TS DP_OP_154J132_123_2038_U172 ( .A(DP_OP_154J132_123_2038_n261),
.B(DP_OP_154J132_123_2038_n228), .C(DP_OP_154J132_123_2038_n226), .D(
DP_OP_154J132_123_2038_n222), .ICI(DP_OP_154J132_123_2038_n223), .S(
DP_OP_154J132_123_2038_n220), .ICO(DP_OP_154J132_123_2038_n218), .CO(
DP_OP_154J132_123_2038_n219) );
CMPR42X1TS DP_OP_154J132_123_2038_U171 ( .A(DP_OP_154J132_123_2038_n260),
.B(DP_OP_154J132_123_2038_n250), .C(DP_OP_154J132_123_2038_n255), .D(
DP_OP_154J132_123_2038_n221), .ICI(DP_OP_154J132_123_2038_n218), .S(
DP_OP_154J132_123_2038_n217), .ICO(DP_OP_154J132_123_2038_n215), .CO(
DP_OP_154J132_123_2038_n216) );
CMPR42X1TS DP_OP_154J132_123_2038_U39 ( .A(DP_OP_154J132_123_2038_n202), .B(
DP_OP_154J132_123_2038_n87), .C(DP_OP_154J132_123_2038_n201), .D(
DP_OP_154J132_123_2038_n118), .ICI(DP_OP_154J132_123_2038_n125), .S(
DP_OP_154J132_123_2038_n75), .ICO(DP_OP_154J132_123_2038_n73), .CO(
DP_OP_154J132_123_2038_n74) );
CMPR42X1TS DP_OP_154J132_123_2038_U37 ( .A(DP_OP_154J132_123_2038_n86), .B(
DP_OP_154J132_123_2038_n124), .C(DP_OP_154J132_123_2038_n72), .D(
DP_OP_154J132_123_2038_n117), .ICI(DP_OP_154J132_123_2038_n91), .S(
DP_OP_154J132_123_2038_n70), .ICO(DP_OP_154J132_123_2038_n68), .CO(
DP_OP_154J132_123_2038_n69) );
CMPR42X1TS DP_OP_154J132_123_2038_U35 ( .A(DP_OP_154J132_123_2038_n116), .B(
DP_OP_154J132_123_2038_n109), .C(DP_OP_154J132_123_2038_n123), .D(
DP_OP_154J132_123_2038_n68), .ICI(DP_OP_154J132_123_2038_n67), .S(
DP_OP_154J132_123_2038_n65), .ICO(DP_OP_154J132_123_2038_n63), .CO(
DP_OP_154J132_123_2038_n64) );
CMPR42X1TS DP_OP_154J132_123_2038_U32 ( .A(DP_OP_154J132_123_2038_n62), .B(
DP_OP_154J132_123_2038_n122), .C(DP_OP_154J132_123_2038_n60), .D(
DP_OP_154J132_123_2038_n64), .ICI(DP_OP_154J132_123_2038_n108), .S(
DP_OP_154J132_123_2038_n58), .ICO(DP_OP_154J132_123_2038_n56), .CO(
DP_OP_154J132_123_2038_n57) );
CMPR42X1TS DP_OP_154J132_123_2038_U31 ( .A(DP_OP_154J132_123_2038_n114), .B(
DP_OP_154J132_123_2038_n61), .C(DP_OP_154J132_123_2038_n83), .D(
DP_OP_154J132_123_2038_n197), .ICI(DP_OP_154J132_123_2038_n100), .S(
DP_OP_154J132_123_2038_n55), .ICO(DP_OP_154J132_123_2038_n53), .CO(
DP_OP_154J132_123_2038_n54) );
CMPR42X1TS DP_OP_154J132_123_2038_U30 ( .A(DP_OP_154J132_123_2038_n121), .B(
DP_OP_154J132_123_2038_n59), .C(DP_OP_154J132_123_2038_n107), .D(
DP_OP_154J132_123_2038_n56), .ICI(DP_OP_154J132_123_2038_n55), .S(
DP_OP_154J132_123_2038_n52), .ICO(DP_OP_154J132_123_2038_n50), .CO(
DP_OP_154J132_123_2038_n51) );
CMPR42X1TS DP_OP_154J132_123_2038_U29 ( .A(DP_OP_154J132_123_2038_n120), .B(
DP_OP_154J132_123_2038_n113), .C(DP_OP_154J132_123_2038_n53), .D(
DP_OP_154J132_123_2038_n196), .ICI(DP_OP_154J132_123_2038_n82), .S(
DP_OP_154J132_123_2038_n49), .ICO(DP_OP_154J132_123_2038_n47), .CO(
DP_OP_154J132_123_2038_n48) );
CMPR42X1TS DP_OP_154J132_123_2038_U28 ( .A(DP_OP_154J132_123_2038_n99), .B(
DP_OP_154J132_123_2038_n106), .C(DP_OP_154J132_123_2038_n54), .D(
DP_OP_154J132_123_2038_n50), .ICI(DP_OP_154J132_123_2038_n49), .S(
DP_OP_154J132_123_2038_n46), .ICO(DP_OP_154J132_123_2038_n44), .CO(
DP_OP_154J132_123_2038_n45) );
CMPR42X1TS DP_OP_154J132_123_2038_U27 ( .A(DP_OP_154J132_123_2038_n119), .B(
DP_OP_154J132_123_2038_n112), .C(DP_OP_154J132_123_2038_n98), .D(
DP_OP_154J132_123_2038_n105), .ICI(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .S(
DP_OP_154J132_123_2038_n43), .ICO(DP_OP_154J132_123_2038_n41), .CO(
DP_OP_154J132_123_2038_n42) );
CMPR42X1TS DP_OP_154J132_123_2038_U26 ( .A(DP_OP_154J132_123_2038_n47), .B(
DP_OP_154J132_123_2038_n81), .C(DP_OP_154J132_123_2038_n44), .D(
DP_OP_154J132_123_2038_n48), .ICI(DP_OP_154J132_123_2038_n43), .S(
DP_OP_154J132_123_2038_n40), .ICO(DP_OP_154J132_123_2038_n38), .CO(
DP_OP_154J132_123_2038_n39) );
CMPR42X1TS DP_OP_154J132_123_2038_U25 ( .A(DP_OP_154J132_123_2038_n111), .B(
DP_OP_154J132_123_2038_n97), .C(DP_OP_154J132_123_2038_n104), .D(
DP_OP_154J132_123_2038_n195), .ICI(DP_OP_154J132_123_2038_n41), .S(
DP_OP_154J132_123_2038_n37), .ICO(DP_OP_154J132_123_2038_n35), .CO(
DP_OP_154J132_123_2038_n36) );
CMPR42X1TS DP_OP_154J132_123_2038_U24 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(
DP_OP_154J132_123_2038_n80), .C(DP_OP_154J132_123_2038_n42), .D(
DP_OP_154J132_123_2038_n38), .ICI(DP_OP_154J132_123_2038_n37), .S(
DP_OP_154J132_123_2038_n34), .ICO(DP_OP_154J132_123_2038_n32), .CO(
DP_OP_154J132_123_2038_n33) );
CMPR42X1TS DP_OP_154J132_123_2038_U23 ( .A(DP_OP_154J132_123_2038_n110), .B(
DP_OP_154J132_123_2038_n96), .C(DP_OP_154J132_123_2038_n103), .D(
DP_OP_154J132_123_2038_n35), .ICI(DP_OP_154J132_123_2038_n194), .S(
DP_OP_154J132_123_2038_n31), .ICO(DP_OP_154J132_123_2038_n29), .CO(
DP_OP_154J132_123_2038_n30) );
CMPR42X1TS DP_OP_154J132_123_2038_U22 ( .A(DP_OP_154J132_123_2038_n36), .B(
DP_OP_154J132_123_2038_n79), .C(DP_OP_154J132_123_2038_n32), .D(
DP_OP_154J132_123_2038_n31), .ICI(DP_OP_154J132_123_2038_n193), .S(
DP_OP_154J132_123_2038_n28), .ICO(DP_OP_154J132_123_2038_n26), .CO(
DP_OP_154J132_123_2038_n27) );
CMPR42X1TS DP_OP_154J132_123_2038_U20 ( .A(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .B(
DP_OP_154J132_123_2038_n25), .C(DP_OP_154J132_123_2038_n78), .D(
DP_OP_154J132_123_2038_n30), .ICI(DP_OP_154J132_123_2038_n26), .S(
DP_OP_154J132_123_2038_n23), .ICO(DP_OP_154J132_123_2038_n21), .CO(
DP_OP_154J132_123_2038_n22) );
CMPR42X1TS DP_OP_154J132_123_2038_U19 ( .A(DP_OP_154J132_123_2038_n94), .B(
DP_OP_154J132_123_2038_n101), .C(DP_OP_154J132_123_2038_n24), .D(
DP_OP_154J132_123_2038_n192), .ICI(DP_OP_154J132_123_2038_n21), .S(
DP_OP_154J132_123_2038_n20), .ICO(DP_OP_154J132_123_2038_n18), .CO(
DP_OP_154J132_123_2038_n19) );
CMPR42X1TS DP_OP_153J132_122_5442_U283 ( .A(DP_OP_153J132_122_5442_n394),
.B(DP_OP_153J132_122_5442_n414), .C(DP_OP_153J132_122_5442_n407), .D(
DP_OP_153J132_122_5442_n400), .ICI(DP_OP_153J132_122_5442_n380), .S(
DP_OP_153J132_122_5442_n377), .ICO(DP_OP_153J132_122_5442_n375), .CO(
DP_OP_153J132_122_5442_n376) );
CMPR42X1TS DP_OP_153J132_122_5442_U282 ( .A(DP_OP_153J132_122_5442_n413),
.B(DP_OP_153J132_122_5442_n393), .C(DP_OP_153J132_122_5442_n399), .D(
DP_OP_153J132_122_5442_n406), .ICI(DP_OP_153J132_122_5442_n375), .S(
DP_OP_153J132_122_5442_n374), .ICO(DP_OP_153J132_122_5442_n372), .CO(
DP_OP_153J132_122_5442_n373) );
CMPR42X1TS DP_OP_153J132_122_5442_U280 ( .A(DP_OP_153J132_122_5442_n405),
.B(DP_OP_153J132_122_5442_n398), .C(DP_OP_153J132_122_5442_n412), .D(
DP_OP_153J132_122_5442_n371), .ICI(DP_OP_153J132_122_5442_n372), .S(
DP_OP_153J132_122_5442_n369), .ICO(DP_OP_153J132_122_5442_n367), .CO(
DP_OP_153J132_122_5442_n368) );
CMPR42X1TS DP_OP_153J132_122_5442_U278 ( .A(DP_OP_153J132_122_5442_n404),
.B(DP_OP_153J132_122_5442_n370), .C(DP_OP_153J132_122_5442_n397), .D(
DP_OP_153J132_122_5442_n366), .ICI(DP_OP_153J132_122_5442_n367), .S(
DP_OP_153J132_122_5442_n364), .ICO(DP_OP_153J132_122_5442_n362), .CO(
DP_OP_153J132_122_5442_n363) );
CMPR42X1TS DP_OP_153J132_122_5442_U277 ( .A(DP_OP_153J132_122_5442_n365),
.B(DP_OP_153J132_122_5442_n396), .C(DP_OP_153J132_122_5442_n392), .D(
DP_OP_153J132_122_5442_n403), .ICI(DP_OP_153J132_122_5442_n362), .S(
DP_OP_153J132_122_5442_n361), .ICO(DP_OP_153J132_122_5442_n359), .CO(
DP_OP_153J132_122_5442_n360) );
CMPR42X1TS DP_OP_153J132_122_5442_U192 ( .A(DP_OP_153J132_122_5442_n306),
.B(DP_OP_153J132_122_5442_n296), .C(DP_OP_153J132_122_5442_n274), .D(
DP_OP_153J132_122_5442_n273), .ICI(DP_OP_153J132_122_5442_n311), .S(
DP_OP_153J132_122_5442_n271), .ICO(DP_OP_153J132_122_5442_n269), .CO(
DP_OP_153J132_122_5442_n270) );
CMPR42X1TS DP_OP_153J132_122_5442_U189 ( .A(DP_OP_153J132_122_5442_n268),
.B(DP_OP_153J132_122_5442_n305), .C(DP_OP_153J132_122_5442_n290), .D(
DP_OP_153J132_122_5442_n266), .ICI(DP_OP_153J132_122_5442_n269), .S(
DP_OP_153J132_122_5442_n264), .ICO(DP_OP_153J132_122_5442_n262), .CO(
DP_OP_153J132_122_5442_n263) );
CMPR42X1TS DP_OP_153J132_122_5442_U186 ( .A(DP_OP_153J132_122_5442_n289),
.B(DP_OP_153J132_122_5442_n265), .C(DP_OP_153J132_122_5442_n261), .D(
DP_OP_153J132_122_5442_n262), .ICI(DP_OP_153J132_122_5442_n259), .S(
DP_OP_153J132_122_5442_n257), .ICO(DP_OP_153J132_122_5442_n255), .CO(
DP_OP_153J132_122_5442_n256) );
CMPR42X1TS DP_OP_153J132_122_5442_U184 ( .A(DP_OP_153J132_122_5442_n293),
.B(DP_OP_153J132_122_5442_n288), .C(DP_OP_153J132_122_5442_n254), .D(
DP_OP_153J132_122_5442_n258), .ICI(DP_OP_153J132_122_5442_n255), .S(
DP_OP_153J132_122_5442_n252), .ICO(DP_OP_153J132_122_5442_n250), .CO(
DP_OP_153J132_122_5442_n251) );
CMPR42X1TS DP_OP_153J132_122_5442_U183 ( .A(DP_OP_153J132_122_5442_n292),
.B(DP_OP_153J132_122_5442_n282), .C(DP_OP_153J132_122_5442_n287), .D(
DP_OP_153J132_122_5442_n253), .ICI(DP_OP_153J132_122_5442_n250), .S(
DP_OP_153J132_122_5442_n249), .ICO(DP_OP_153J132_122_5442_n247), .CO(
DP_OP_153J132_122_5442_n248) );
CMPR42X1TS DP_OP_153J132_122_5442_U63 ( .A(DP_OP_153J132_122_5442_n234), .B(
DP_OP_153J132_122_5442_n205), .C(DP_OP_153J132_122_5442_n191), .D(
DP_OP_153J132_122_5442_n128), .ICI(DP_OP_153J132_122_5442_n127), .S(
DP_OP_153J132_122_5442_n125), .ICO(DP_OP_153J132_122_5442_n123), .CO(
DP_OP_153J132_122_5442_n124) );
CMPR42X1TS DP_OP_153J132_122_5442_U60 ( .A(DP_OP_153J132_122_5442_n204), .B(
DP_OP_153J132_122_5442_n183), .C(DP_OP_153J132_122_5442_n122), .D(
DP_OP_153J132_122_5442_n120), .ICI(DP_OP_153J132_122_5442_n124), .S(
DP_OP_153J132_122_5442_n118), .ICO(DP_OP_153J132_122_5442_n116), .CO(
DP_OP_153J132_122_5442_n117) );
CMPR42X1TS DP_OP_153J132_122_5442_U58 ( .A(DP_OP_153J132_122_5442_n121), .B(
DP_OP_153J132_122_5442_n182), .C(DP_OP_153J132_122_5442_n196), .D(
DP_OP_153J132_122_5442_n115), .ICI(DP_OP_153J132_122_5442_n116), .S(
DP_OP_153J132_122_5442_n113), .ICO(DP_OP_153J132_122_5442_n111), .CO(
DP_OP_153J132_122_5442_n112) );
CMPR42X1TS DP_OP_153J132_122_5442_U57 ( .A(DP_OP_153J132_122_5442_n119), .B(
DP_OP_153J132_122_5442_n175), .C(DP_OP_153J132_122_5442_n203), .D(
DP_OP_153J132_122_5442_n113), .ICI(DP_OP_153J132_122_5442_n117), .S(
DP_OP_153J132_122_5442_n110), .ICO(DP_OP_153J132_122_5442_n108), .CO(
DP_OP_153J132_122_5442_n109) );
CMPR42X1TS DP_OP_153J132_122_5442_U54 ( .A(DP_OP_153J132_122_5442_n107), .B(
DP_OP_153J132_122_5442_n195), .C(DP_OP_153J132_122_5442_n174), .D(
DP_OP_153J132_122_5442_n105), .ICI(DP_OP_153J132_122_5442_n202), .S(
DP_OP_153J132_122_5442_n103), .ICO(DP_OP_153J132_122_5442_n101), .CO(
DP_OP_153J132_122_5442_n102) );
CMPR42X1TS DP_OP_153J132_122_5442_U53 ( .A(DP_OP_153J132_122_5442_n112), .B(
DP_OP_153J132_122_5442_n108), .C(DP_OP_153J132_122_5442_n167), .D(
DP_OP_153J132_122_5442_n103), .ICI(DP_OP_153J132_122_5442_n109), .S(
DP_OP_153J132_122_5442_n100), .ICO(DP_OP_153J132_122_5442_n98), .CO(
DP_OP_153J132_122_5442_n99) );
CMPR42X1TS DP_OP_153J132_122_5442_U51 ( .A(DP_OP_153J132_122_5442_n106), .B(
DP_OP_153J132_122_5442_n97), .C(DP_OP_153J132_122_5442_n173), .D(
DP_OP_153J132_122_5442_n187), .ICI(DP_OP_153J132_122_5442_n104), .S(
DP_OP_153J132_122_5442_n95), .ICO(DP_OP_153J132_122_5442_n93), .CO(
DP_OP_153J132_122_5442_n94) );
CMPR42X1TS DP_OP_153J132_122_5442_U50 ( .A(DP_OP_153J132_122_5442_n101), .B(
DP_OP_153J132_122_5442_n166), .C(DP_OP_153J132_122_5442_n194), .D(
DP_OP_153J132_122_5442_n98), .ICI(DP_OP_153J132_122_5442_n95), .S(
DP_OP_153J132_122_5442_n92), .ICO(DP_OP_153J132_122_5442_n90), .CO(
DP_OP_153J132_122_5442_n91) );
CMPR42X1TS DP_OP_153J132_122_5442_U49 ( .A(DP_OP_153J132_122_5442_n201), .B(
DP_OP_153J132_122_5442_n159), .C(DP_OP_153J132_122_5442_n102), .D(
DP_OP_153J132_122_5442_n229), .ICI(DP_OP_153J132_122_5442_n92), .S(
DP_OP_153J132_122_5442_n89), .ICO(DP_OP_153J132_122_5442_n87), .CO(
DP_OP_153J132_122_5442_n88) );
CMPR42X1TS DP_OP_153J132_122_5442_U46 ( .A(DP_OP_153J132_122_5442_n93), .B(
DP_OP_153J132_122_5442_n165), .C(DP_OP_153J132_122_5442_n186), .D(
DP_OP_153J132_122_5442_n151), .ICI(DP_OP_153J132_122_5442_n158), .S(
DP_OP_153J132_122_5442_n82), .ICO(DP_OP_153J132_122_5442_n80), .CO(
DP_OP_153J132_122_5442_n81) );
CMPR42X1TS DP_OP_153J132_122_5442_U45 ( .A(DP_OP_153J132_122_5442_n200), .B(
DP_OP_153J132_122_5442_n90), .C(DP_OP_153J132_122_5442_n94), .D(
DP_OP_153J132_122_5442_n193), .ICI(DP_OP_153J132_122_5442_n87), .S(
DP_OP_153J132_122_5442_n79), .ICO(DP_OP_153J132_122_5442_n77), .CO(
DP_OP_153J132_122_5442_n78) );
CMPR42X1TS DP_OP_153J132_122_5442_U44 ( .A(DP_OP_153J132_122_5442_n84), .B(
DP_OP_153J132_122_5442_n91), .C(DP_OP_153J132_122_5442_n82), .D(
DP_OP_153J132_122_5442_n79), .ICI(DP_OP_153J132_122_5442_n228), .S(
DP_OP_153J132_122_5442_n76), .ICO(DP_OP_153J132_122_5442_n74), .CO(
DP_OP_153J132_122_5442_n75) );
CMPR42X1TS DP_OP_153J132_122_5442_U41 ( .A(DP_OP_153J132_122_5442_n73), .B(
DP_OP_153J132_122_5442_n83), .C(DP_OP_153J132_122_5442_n192), .D(
DP_OP_153J132_122_5442_n150), .ICI(DP_OP_153J132_122_5442_n71), .S(
DP_OP_153J132_122_5442_n69), .ICO(DP_OP_153J132_122_5442_n67), .CO(
DP_OP_153J132_122_5442_n68) );
CMPR42X1TS DP_OP_153J132_122_5442_U40 ( .A(DP_OP_153J132_122_5442_n80), .B(
DP_OP_153J132_122_5442_n185), .C(DP_OP_153J132_122_5442_n157), .D(
DP_OP_153J132_122_5442_n77), .ICI(DP_OP_153J132_122_5442_n81), .S(
DP_OP_153J132_122_5442_n66), .ICO(DP_OP_153J132_122_5442_n64), .CO(
DP_OP_153J132_122_5442_n65) );
CMPR42X1TS DP_OP_153J132_122_5442_U39 ( .A(DP_OP_153J132_122_5442_n78), .B(
DP_OP_153J132_122_5442_n69), .C(DP_OP_153J132_122_5442_n74), .D(
DP_OP_153J132_122_5442_n66), .ICI(DP_OP_153J132_122_5442_n227), .S(
DP_OP_153J132_122_5442_n63), .ICO(DP_OP_153J132_122_5442_n61), .CO(
DP_OP_153J132_122_5442_n62) );
CMPR42X1TS DP_OP_153J132_122_5442_U37 ( .A(DP_OP_153J132_122_5442_n72), .B(
DP_OP_153J132_122_5442_n149), .C(DP_OP_153J132_122_5442_n184), .D(
DP_OP_153J132_122_5442_n156), .ICI(DP_OP_153J132_122_5442_n60), .S(
DP_OP_153J132_122_5442_n58), .ICO(DP_OP_153J132_122_5442_n56), .CO(
DP_OP_153J132_122_5442_n57) );
CMPR42X1TS DP_OP_153J132_122_5442_U36 ( .A(DP_OP_153J132_122_5442_n177), .B(
DP_OP_153J132_122_5442_n70), .C(DP_OP_153J132_122_5442_n67), .D(
DP_OP_153J132_122_5442_n64), .ICI(DP_OP_153J132_122_5442_n68), .S(
DP_OP_153J132_122_5442_n55), .ICO(DP_OP_153J132_122_5442_n53), .CO(
DP_OP_153J132_122_5442_n54) );
CMPR42X1TS DP_OP_153J132_122_5442_U35 ( .A(DP_OP_153J132_122_5442_n58), .B(
DP_OP_153J132_122_5442_n65), .C(DP_OP_153J132_122_5442_n55), .D(
DP_OP_153J132_122_5442_n61), .ICI(DP_OP_153J132_122_5442_n62), .S(
DP_OP_153J132_122_5442_n52), .ICO(DP_OP_153J132_122_5442_n50), .CO(
DP_OP_153J132_122_5442_n51) );
CMPR42X1TS DP_OP_153J132_122_5442_U34 ( .A(DP_OP_153J132_122_5442_n133), .B(
DP_OP_153J132_122_5442_n162), .C(DP_OP_153J132_122_5442_n148), .D(
DP_OP_153J132_122_5442_n176), .ICI(DP_OP_153J132_122_5442_n155), .S(
DP_OP_153J132_122_5442_n49), .ICO(DP_OP_153J132_122_5442_n47), .CO(
DP_OP_153J132_122_5442_n48) );
CMPR42X1TS DP_OP_153J132_122_5442_U33 ( .A(DP_OP_153J132_122_5442_n169), .B(
DP_OP_153J132_122_5442_n59), .C(DP_OP_153J132_122_5442_n56), .D(
DP_OP_153J132_122_5442_n53), .ICI(DP_OP_153J132_122_5442_n57), .S(
DP_OP_153J132_122_5442_n46), .ICO(DP_OP_153J132_122_5442_n44), .CO(
DP_OP_153J132_122_5442_n45) );
CMPR42X1TS DP_OP_153J132_122_5442_U32 ( .A(DP_OP_153J132_122_5442_n49), .B(
DP_OP_153J132_122_5442_n54), .C(DP_OP_153J132_122_5442_n46), .D(
DP_OP_153J132_122_5442_n50), .ICI(DP_OP_153J132_122_5442_n51), .S(
DP_OP_153J132_122_5442_n43), .ICO(DP_OP_153J132_122_5442_n41), .CO(
DP_OP_153J132_122_5442_n42) );
CMPR42X1TS DP_OP_153J132_122_5442_U30 ( .A(DP_OP_153J132_122_5442_n161), .B(
DP_OP_153J132_122_5442_n154), .C(DP_OP_153J132_122_5442_n47), .D(
DP_OP_153J132_122_5442_n40), .ICI(DP_OP_153J132_122_5442_n44), .S(
DP_OP_153J132_122_5442_n38), .ICO(DP_OP_153J132_122_5442_n36), .CO(
DP_OP_153J132_122_5442_n37) );
CMPR42X1TS DP_OP_153J132_122_5442_U29 ( .A(DP_OP_153J132_122_5442_n48), .B(
DP_OP_153J132_122_5442_n38), .C(DP_OP_153J132_122_5442_n45), .D(
DP_OP_153J132_122_5442_n41), .ICI(DP_OP_153J132_122_5442_n224), .S(
DP_OP_153J132_122_5442_n35), .ICO(DP_OP_153J132_122_5442_n33), .CO(
DP_OP_153J132_122_5442_n34) );
CMPR42X1TS DP_OP_153J132_122_5442_U25 ( .A(DP_OP_153J132_122_5442_n36), .B(
DP_OP_153J132_122_5442_n32), .C(DP_OP_153J132_122_5442_n30), .D(
DP_OP_153J132_122_5442_n37), .ICI(DP_OP_153J132_122_5442_n33), .S(
DP_OP_153J132_122_5442_n28), .ICO(DP_OP_153J132_122_5442_n26), .CO(
DP_OP_153J132_122_5442_n27) );
CMPR42X1TS DP_OP_153J132_122_5442_U22 ( .A(DP_OP_153J132_122_5442_n145), .B(
DP_OP_153J132_122_5442_n31), .C(DP_OP_153J132_122_5442_n29), .D(
DP_OP_153J132_122_5442_n25), .ICI(DP_OP_153J132_122_5442_n26), .S(
DP_OP_153J132_122_5442_n23), .ICO(DP_OP_153J132_122_5442_n21), .CO(
DP_OP_153J132_122_5442_n22) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n379), .CK(n1796), .RN(n167), .Q(
FS_Module_state_reg[0]), .QN(n1760) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n236), .CK(n1794), .RN(n1767), .Q(
FSM_selector_B[0]), .QN(n1759) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n168),
.CK(n415), .RN(n1761), .Q(final_result_ieee[31]), .QN(n1758) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n262), .CK(n1790), .RN(
n1779), .Q(P_Sgf[24]), .QN(n1757) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n283), .CK(n1787), .RN(
n1782), .Q(P_Sgf[45]), .QN(n1756) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(n1794), .RN(n1782), .Q(
FS_Module_state_reg[3]), .QN(n1755) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n307), .CK(n1785), .RN(n1771),
.Q(Add_result[2]), .QN(n1754) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n310), .CK(n1797),
.RN(n1766), .Q(Sgf_normalized_result[23]), .QN(n1753) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n267), .CK(n1791), .RN(
n1779), .Q(P_Sgf[29]), .QN(n1752) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n275), .CK(n1785), .RN(
n1778), .Q(P_Sgf[37]), .QN(n1751) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n206), .CK(n1784),
.RN(n1764), .Q(Sgf_normalized_result[4]), .QN(n1750) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n269), .CK(n1785), .RN(
n1778), .Q(P_Sgf[31]), .QN(n1749) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n273), .CK(n1786), .RN(
n1778), .Q(P_Sgf[35]), .QN(n1748) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n224), .CK(n1797),
.RN(n1766), .Q(Sgf_normalized_result[22]), .QN(n1747) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n222), .CK(n1795),
.RN(n1766), .Q(Sgf_normalized_result[20]), .QN(n1746) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n220), .CK(n1794),
.RN(n1766), .Q(Sgf_normalized_result[18]), .QN(n1745) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n218), .CK(n1796),
.RN(n1766), .Q(Sgf_normalized_result[16]), .QN(n1744) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n216), .CK(n1783),
.RN(n1765), .Q(Sgf_normalized_result[14]), .QN(n1743) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n214), .CK(n1794),
.RN(n1765), .Q(Sgf_normalized_result[12]), .QN(n1742) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n212), .CK(n1796),
.RN(n1765), .Q(Sgf_normalized_result[10]), .QN(n1741) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n210), .CK(n1797),
.RN(n1765), .Q(Sgf_normalized_result[8]), .QN(n1740) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n208), .CK(n1795),
.RN(n1765), .Q(Sgf_normalized_result[6]), .QN(n1739) );
DFFRX1TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(n1796),
.RN(n1761), .Q(zero_flag), .QN(n1738) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n263), .CK(n1785), .RN(
n1779), .QN(n1737) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n265), .CK(n435), .RN(
n1779), .QN(n1736) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n271), .CK(n1791), .RN(
n1778), .QN(n1735) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n277), .CK(n1788), .RN(
n1778), .QN(n1734) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n279), .CK(n1786), .RN(
n1782), .QN(n1733) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n281), .CK(n1792), .RN(
n167), .QN(n1732) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(n1785), .RN(
n1770), .Q(Op_MY[20]), .QN(n1731) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(n1792), .RN(
n1770), .Q(Op_MY[22]), .QN(n1730) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(n1798), .RN(
n1769), .Q(Op_MY[15]), .QN(n1729) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(n435), .RN(
n1769), .Q(Op_MY[9]), .QN(n1728) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(n1785), .RN(
n1768), .Q(Op_MY[3]), .QN(n1727) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(n1786), .RN(
n1769), .Q(Op_MY[17]), .QN(n1726) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(n1798), .RN(
n1769), .Q(Op_MY[16]), .QN(n1725) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(n1789), .RN(
n1768), .Q(Op_MY[5]), .QN(n1724) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(n1792), .RN(
n1768), .Q(Op_MY[4]), .QN(n1723) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(n1790), .RN(
n1769), .Q(Op_MY[10]), .QN(n1722) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(n1788), .RN(
n1769), .Q(Op_MY[11]), .QN(n1721) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(n1787), .RN(
n1770), .Q(Op_MY[21]), .QN(n1720) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(n435), .RN(
n1768), .Q(Op_MY[2]), .QN(n1719) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(n1789), .RN(
n1769), .Q(Op_MY[14]), .QN(n1718) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n331), .CK(n1786), .RN(
n1770), .Q(Op_MY[19]), .QN(n1716) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n235), .CK(n1783), .RN(n1767), .Q(
FSM_selector_B[1]), .QN(n1715) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(n1796), .RN(n1782), .Q(
FS_Module_state_reg[1]), .QN(n1714) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(n1795), .RN(
n1775), .Q(Op_MX[20]), .QN(n1713) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n357), .CK(n1783), .RN(
n1775), .Q(Op_MX[13]), .QN(n1712) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(n1798), .RN(
n1774), .Q(Op_MX[7]), .QN(n1711) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n345), .CK(n435), .RN(
n1774), .Q(Op_MX[1]), .QN(n1710) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(n434), .RN(
n1775), .Q(Op_MX[19]), .QN(n1709) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(n1794), .RN(
n1774), .Q(Op_MX[8]), .QN(n1708) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n346), .CK(n1785), .RN(
n1774), .Q(Op_MX[2]), .QN(n1707) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n358), .CK(n1796), .RN(
n1775), .Q(Op_MX[14]), .QN(n1706) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(n1784), .RN(
n1776), .Q(Op_MX[22]), .QN(n1705) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(n1787), .RN(
n1774), .Q(Op_MX[4]), .QN(n1704) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(n1783), .RN(
n1775), .Q(Op_MX[11]), .QN(n1703) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(n1784), .RN(
n1775), .Q(Op_MX[16]), .QN(n1702) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n377), .CK(n1783), .RN(n167), .Q(
FS_Module_state_reg[2]), .QN(n1701) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(n1797), .RN(
n1776), .Q(Op_MX[21]), .QN(n1700) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(n1791), .RN(
n1774), .Q(Op_MX[6]), .QN(n1699) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(n1797), .RN(
n1775), .Q(Op_MX[15]), .QN(n1698) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(n1789), .RN(
n1774), .Q(Op_MX[3]), .QN(n1697) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(clk), .RN(
n1774), .Q(Op_MX[9]), .QN(n1696) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(n1792), .RN(
n1774), .Q(Op_MX[5]), .QN(n1695) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(n1787), .RN(
n1775), .Q(Op_MX[17]), .QN(n1694) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(n1791), .RN(
n1768), .Q(Op_MY[8]), .QN(n1692) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(n1788), .RN(
n1769), .Q(Op_MY[13]), .QN(n1691) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n200),
.CK(n438), .RN(n1764), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n199),
.CK(n924), .RN(n1764), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n198),
.CK(n1799), .RN(n1764), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n197),
.CK(n415), .RN(n1763), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n196),
.CK(n414), .RN(n1763), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n195),
.CK(n415), .RN(n1763), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n194),
.CK(n1799), .RN(n1763), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n193),
.CK(n415), .RN(n1763), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n192),
.CK(n414), .RN(n1763), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n191),
.CK(n1799), .RN(n1763), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n190),
.CK(n1798), .RN(n1763), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n189),
.CK(n438), .RN(n1763), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n188),
.CK(n415), .RN(n1763), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n187),
.CK(n438), .RN(n1762), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n186),
.CK(n1798), .RN(n1762), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n185),
.CK(n1798), .RN(n1762), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n184),
.CK(n414), .RN(n1762), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n183),
.CK(n415), .RN(n1762), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n182),
.CK(n1799), .RN(n1762), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n181),
.CK(n1799), .RN(n1762), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n180),
.CK(n415), .RN(n1762), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n179),
.CK(n1798), .RN(n1762), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n178),
.CK(n414), .RN(n1762), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n171),
.CK(n415), .RN(n1761), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n170),
.CK(n415), .RN(n1761), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n177),
.CK(n1798), .RN(n1761), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n176),
.CK(n924), .RN(n1761), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n175),
.CK(n438), .RN(n1761), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n174),
.CK(n438), .RN(n1761), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n173),
.CK(n924), .RN(n1761), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n172),
.CK(n414), .RN(n1761), .Q(final_result_ieee[28]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n225), .CK(clk), .RN(n1768), .Q(
Exp_module_Overflow_flag_A) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n250), .CK(n1795), .RN(
n1780), .Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n238), .CK(clk), .RN(
n1781), .Q(P_Sgf[0]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n381), .CK(clk), .RN(
n1769), .Q(Op_MY[31]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n257), .CK(n434), .RN(
n1780), .Q(P_Sgf[19]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n252), .CK(clk), .RN(
n1780), .Q(P_Sgf[14]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n246), .CK(n1793), .RN(
n1781), .Q(P_Sgf[8]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n260), .CK(n1792), .RN(
n1779), .Q(P_Sgf[22]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n239), .CK(clk), .RN(
n1781), .Q(P_Sgf[1]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n256), .CK(n1795), .RN(
n1780), .Q(P_Sgf[18]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n249), .CK(n1793), .RN(
n1780), .Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n241), .CK(n1793), .RN(
n1781), .Q(P_Sgf[3]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n255), .CK(n1799), .RN(
n1780), .Q(P_Sgf[17]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n258), .CK(clk), .RN(
n1779), .Q(P_Sgf[20]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n251), .CK(n434), .RN(
n1780), .Q(P_Sgf[13]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n253), .CK(n1787), .RN(
n1780), .Q(P_Sgf[15]) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(n1788), .RN(
n1773), .Q(Op_MX[31]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n259), .CK(n1795), .RN(
n1779), .Q(P_Sgf[21]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n254), .CK(n1799), .RN(
n1780), .Q(P_Sgf[16]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n286), .CK(n1789), .RN(n1771), .Q(Add_result[23]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n309), .CK(n1789), .RN(n1771),
.Q(Add_result[0]) );
DFFRXLTS Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n284), .CK(n1792), .RN(
n1782), .Q(P_Sgf[46]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(n1788), .RN(
n1770), .Q(Op_MY[26]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(n1786), .RN(
n1770), .Q(Op_MY[27]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(n1792), .RN(
n1771), .Q(Op_MY[29]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(n1790), .RN(
n1770), .Q(Op_MY[25]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(n1791), .RN(
n1770), .Q(Op_MY[24]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(n1790), .RN(
n1771), .Q(Op_MY[28]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n237), .CK(n1783), .RN(
n1782), .Q(P_Sgf[47]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(n1787), .RN(
n1771), .Q(Op_MY[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(n434), .RN(
n1776), .Q(Op_MX[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(n1784), .RN(
n1776), .Q(Op_MX[23]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(n1796), .RN(
n1776), .Q(Op_MX[28]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(n1797), .RN(
n1776), .Q(Op_MX[24]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(n1783), .RN(
n1776), .Q(Op_MX[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(n1795), .RN(
n1776), .Q(Op_MX[26]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n226), .CK(n434), .RN(n1766),
.Q(exp_oper_result[8]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(n1794), .RN(
n1776), .Q(Op_MX[29]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(n434), .RN(
n1776), .Q(Op_MX[25]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(n1788), .RN(
n1770), .Q(Op_MY[23]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n234), .CK(n1796), .RN(n1767),
.Q(exp_oper_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n233), .CK(n1794), .RN(n1767),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n232), .CK(n1783), .RN(n1767),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n231), .CK(n1796), .RN(n1767),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n230), .CK(n1784), .RN(n1767),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n229), .CK(n1797), .RN(n1767),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n228), .CK(n1795), .RN(n1767),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n227), .CK(n434), .RN(n1767),
.Q(exp_oper_result[7]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n285), .CK(n1789), .RN(
n1771), .Q(FSM_add_overflow_flag) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n304), .CK(n1786), .RN(n1772),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n306), .CK(n1792), .RN(n1771),
.Q(Add_result[3]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n270), .CK(n1790), .RN(
n1778), .Q(P_Sgf[32]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n302), .CK(n435), .RN(n1772),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n305), .CK(n1789), .RN(n1771),
.Q(Add_result[4]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n280), .CK(n435), .RN(
n1782), .Q(P_Sgf[42]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n278), .CK(n1786), .RN(
n1782), .Q(P_Sgf[40]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n274), .CK(n435), .RN(
n1778), .Q(P_Sgf[36]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n272), .CK(n1787), .RN(
n1778), .Q(P_Sgf[34]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n288), .CK(n1789), .RN(n1773), .Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n290), .CK(n1788), .RN(n1773), .Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n292), .CK(n435), .RN(n1773),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n294), .CK(n1786), .RN(n1773), .Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n296), .CK(n1789), .RN(n1772), .Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n298), .CK(n1792), .RN(n1772), .Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n300), .CK(n1788), .RN(n1772),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n308), .CK(n1786), .RN(n1771),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n287), .CK(n1785), .RN(n1773), .Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n303), .CK(n1785), .RN(n1772),
.Q(Add_result[6]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n264), .CK(n1785), .RN(
n1779), .Q(P_Sgf[26]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n282), .CK(n1790), .RN(
n167), .Q(P_Sgf[44]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n276), .CK(n1791), .RN(
n1778), .Q(P_Sgf[38]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n289), .CK(n1791), .RN(n1773), .Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n291), .CK(n1798), .RN(n1773), .Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n293), .CK(n1792), .RN(n1773), .Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n295), .CK(n1790), .RN(n1772), .Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n297), .CK(n1787), .RN(n1772), .Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n299), .CK(n1789), .RN(n1772), .Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n301), .CK(n1791), .RN(n1772),
.Q(Add_result[8]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n268), .CK(n1798), .RN(
n1778), .Q(P_Sgf[30]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n266), .CK(n1790), .RN(
n1779), .Q(P_Sgf[28]) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n201), .CK(n438), .RN(n1764),
.Q(underflow_flag) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n204), .CK(n1784),
.RN(n1764), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n223), .CK(n1797),
.RN(n1766), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n221), .CK(n1783),
.RN(n1766), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n219), .CK(n1794),
.RN(n1766), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n217), .CK(n1796),
.RN(n1765), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n215), .CK(n1783),
.RN(n1765), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n213), .CK(n1794),
.RN(n1765), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n211), .CK(n1797),
.RN(n1765), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n209), .CK(n1795),
.RN(n1765), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n207), .CK(n434),
.RN(n1764), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n205), .CK(n1784),
.RN(n1764), .Q(Sgf_normalized_result[3]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n203), .CK(n1795),
.RN(n1764), .Q(Sgf_normalized_result[1]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(clk), .RN(
n1774), .Q(Op_MX[10]), .QN(n443) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n202), .CK(n1784),
.RN(n1764), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n376), .CK(n1794), .RN(n1777), .Q(
FSM_selector_A), .QN(n444) );
CMPR32X2TS DP_OP_36J132_126_4699_U10 ( .A(S_Oper_A_exp[0]), .B(
DP_OP_36J132_126_4699_n33), .C(DP_OP_36J132_126_4699_n22), .CO(
DP_OP_36J132_126_4699_n9), .S(Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_36J132_126_4699_U9 ( .A(DP_OP_36J132_126_4699_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J132_126_4699_n9), .CO(
DP_OP_36J132_126_4699_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J132_126_4699_U8 ( .A(DP_OP_36J132_126_4699_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J132_126_4699_n8), .CO(
DP_OP_36J132_126_4699_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J132_126_4699_U7 ( .A(DP_OP_36J132_126_4699_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J132_126_4699_n7), .CO(
DP_OP_36J132_126_4699_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J132_126_4699_U6 ( .A(DP_OP_36J132_126_4699_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J132_126_4699_n6), .CO(
DP_OP_36J132_126_4699_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J132_126_4699_U5 ( .A(DP_OP_36J132_126_4699_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J132_126_4699_n5), .CO(
DP_OP_36J132_126_4699_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J132_126_4699_U4 ( .A(DP_OP_36J132_126_4699_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J132_126_4699_n4), .CO(
DP_OP_36J132_126_4699_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J132_126_4699_U3 ( .A(DP_OP_36J132_126_4699_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J132_126_4699_n3), .CO(
DP_OP_36J132_126_4699_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J132_126_4699_U2 ( .A(DP_OP_36J132_126_4699_n33), .B(
S_Oper_A_exp[8]), .C(DP_OP_36J132_126_4699_n2), .CO(
DP_OP_36J132_126_4699_n1), .S(Exp_module_Data_S[8]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n247), .CK(n1793), .RN(
n1781), .Q(P_Sgf[9]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(n1788), .RN(
n1768), .Q(Op_MY[7]), .QN(n1717) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n242), .CK(n1793), .RN(
n1781), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n245), .CK(n1793), .RN(
n1781), .Q(P_Sgf[7]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n243), .CK(n1793), .RN(
n1781), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n248), .CK(n1793), .RN(
n1780), .Q(P_Sgf[10]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n240), .CK(n1793), .RN(
n1781), .Q(P_Sgf[2]) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n244), .CK(n1793), .RN(
n1781), .Q(P_Sgf[6]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(n434), .RN(
n1775), .Q(Op_MX[18]), .QN(n1693) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(n1790), .RN(
n1768), .Q(Op_MY[1]), .QN(n1690) );
DFFRX1TS Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n261), .CK(n1787), .RN(
n1779), .Q(P_Sgf[23]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(n435), .RN(
n1769), .Q(Op_MY[12]), .QN(n403) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n330), .CK(n1790), .RN(
n1770), .Q(Op_MY[18]), .QN(n397) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n344), .CK(n435), .RN(
n1773), .Q(Op_MX[0]), .QN(n394) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n356), .CK(clk), .RN(
n1775), .Q(Op_MX[12]), .QN(n395) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(n1786), .RN(
n1768), .Q(Op_MY[6]), .QN(n396) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n312), .CK(n1791), .RN(
n1768), .Q(Op_MY[0]), .QN(n393) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n375), .CK(n1784), .RN(n1766), .Q(
FSM_selector_C), .QN(n398) );
INVX6TS U406 ( .A(n413), .Y(n415) );
CLKINVX6TS U407 ( .A(n413), .Y(n414) );
CMPR32X2TS U408 ( .A(n1527), .B(n936), .C(n935), .CO(n679), .S(n937) );
CMPR32X2TS U409 ( .A(n1426), .B(n1508), .C(n960), .CO(n505), .S(n961) );
CMPR32X2TS U410 ( .A(Op_MY[22]), .B(Op_MY[10]), .C(n510), .CO(n508), .S(
n1516) );
CMPR32X2TS U411 ( .A(Op_MX[16]), .B(Op_MX[22]), .C(n604), .CO(n605), .S(n606) );
CMPR32X2TS U412 ( .A(Op_MY[19]), .B(Op_MY[7]), .C(n493), .CO(n507), .S(n953)
);
CMPR32X2TS U413 ( .A(Op_MX[15]), .B(Op_MX[21]), .C(n603), .CO(n604), .S(
n1563) );
CMPR32X2TS U414 ( .A(Op_MX[17]), .B(Op_MX[5]), .C(n494), .CO(n495), .S(n1426) );
CMPR32X2TS U415 ( .A(Op_MX[15]), .B(Op_MX[3]), .C(n498), .CO(n496), .S(n1530) );
CMPR32X2TS U416 ( .A(Op_MX[11]), .B(Op_MX[5]), .C(n514), .CO(n515), .S(n1583) );
OAI32X4TS U417 ( .A0(n722), .A1(n1690), .A2(n394), .B0(n468), .B1(n722), .Y(
n1335) );
CMPR32X2TS U418 ( .A(Op_MX[3]), .B(Op_MX[9]), .C(n929), .CO(n933), .S(n1596)
);
CMPR32X2TS U419 ( .A(Op_MX[1]), .B(Op_MX[7]), .C(n513), .CO(n927), .S(n931)
);
BUFX6TS U420 ( .A(n414), .Y(n1798) );
BUFX3TS U421 ( .A(n414), .Y(n439) );
ADDFX1TS U422 ( .A(n1299), .B(n1517), .CI(n1298), .CO(
DP_OP_153J132_122_5442_n258), .S(DP_OP_153J132_122_5442_n259) );
ADDFX1TS U423 ( .A(n1032), .B(n1031), .CI(n1030), .CO(
DP_OP_153J132_122_5442_n274), .S(n946) );
ADDFX1TS U424 ( .A(n1451), .B(n1450), .CI(n1449), .CO(
DP_OP_153J132_122_5442_n265), .S(DP_OP_153J132_122_5442_n266) );
ADDFX1TS U425 ( .A(n1052), .B(n1051), .CI(n1050), .CO(n989), .S(n1135) );
ADDFX1TS U426 ( .A(DP_OP_154J132_123_2038_n87), .B(
DP_OP_155J132_124_2038_n87), .CI(n1507), .CO(n865), .S(n846) );
CLKBUFX3TS U427 ( .A(n1583), .Y(n419) );
OR3X2TS U428 ( .A(underflow_flag), .B(overflow_flag), .C(n1400), .Y(n1687)
);
CLKINVX3TS U429 ( .A(n1426), .Y(n391) );
OA21X2TS U430 ( .A0(n982), .A1(n1613), .B0(FS_Module_state_reg[1]), .Y(n516)
);
ADDFX1TS U431 ( .A(n460), .B(n459), .CI(n458), .CO(n727), .S(n1006) );
ADDFX1TS U432 ( .A(n724), .B(n723), .CI(n722), .CO(n828), .S(n1302) );
NAND2X4TS U433 ( .A(n1492), .B(n1189), .Y(n1268) );
NAND3X2TS U434 ( .A(FS_Module_state_reg[3]), .B(n1492), .C(n1701), .Y(n1003)
);
INVX2TS U435 ( .A(n950), .Y(DP_OP_154J132_123_2038_n119) );
OAI32X1TS U436 ( .A0(n442), .A1(n1597), .A2(n1601), .B0(n1599), .B1(n442),
.Y(DP_OP_155J132_124_2038_n91) );
CLKBUFX3TS U437 ( .A(n1301), .Y(n1300) );
AO22XLTS U438 ( .A0(n1686), .A1(P_Sgf[1]), .B0(n1369), .B1(n1335), .Y(n239)
);
AO22XLTS U439 ( .A0(n1394), .A1(P_Sgf[0]), .B0(n1369), .B1(n1368), .Y(n238)
);
INVX2TS U440 ( .A(n412), .Y(n566) );
INVX2TS U441 ( .A(n557), .Y(n411) );
NOR2X2TS U442 ( .A(FSM_selector_C), .B(n1178), .Y(n557) );
INVX2TS U443 ( .A(n411), .Y(n412) );
AOI21X2TS U444 ( .A0(n405), .A1(n394), .B0(n503), .Y(n399) );
OR2X1TS U445 ( .A(n1178), .B(n398), .Y(n400) );
OR2X1TS U446 ( .A(n398), .B(n517), .Y(n401) );
NOR4X2TS U447 ( .A(n393), .B(n1690), .C(n1697), .D(n1707), .Y(n402) );
BUFX4TS U448 ( .A(n439), .Y(n1797) );
BUFX4TS U449 ( .A(n439), .Y(n1784) );
OR4X2TS U450 ( .A(n1447), .B(n1445), .C(n1054), .D(n1297), .Y(n404) );
INVX2TS U451 ( .A(Op_MX[12]), .Y(n405) );
INVX2TS U452 ( .A(n1563), .Y(n406) );
INVX2TS U453 ( .A(n406), .Y(n407) );
INVX2TS U454 ( .A(Op_MY[18]), .Y(n408) );
INVX2TS U455 ( .A(n1596), .Y(n409) );
INVX2TS U456 ( .A(n409), .Y(n410) );
INVX2TS U457 ( .A(clk), .Y(n413) );
INVX2TS U458 ( .A(Op_MX[0]), .Y(n416) );
INVX2TS U459 ( .A(Op_MY[6]), .Y(n417) );
INVX2TS U460 ( .A(Op_MY[0]), .Y(n418) );
INVX2TS U461 ( .A(n1530), .Y(n420) );
INVX2TS U462 ( .A(n1530), .Y(n421) );
INVX2TS U463 ( .A(n421), .Y(n422) );
INVX2TS U464 ( .A(n403), .Y(n423) );
INVX2TS U465 ( .A(n423), .Y(n424) );
INVX2TS U466 ( .A(n423), .Y(n425) );
INVX2TS U467 ( .A(n391), .Y(n426) );
INVX2TS U468 ( .A(n400), .Y(n427) );
INVX2TS U469 ( .A(n400), .Y(n428) );
INVX2TS U470 ( .A(n400), .Y(n429) );
INVX2TS U471 ( .A(n401), .Y(n430) );
INVX2TS U472 ( .A(n401), .Y(n431) );
INVX2TS U473 ( .A(n401), .Y(n432) );
NOR2X1TS U474 ( .A(n1475), .B(n1460), .Y(DP_OP_153J132_122_5442_n184) );
OAI2BB2X1TS U475 ( .B0(n1537), .B1(n1536), .A0N(n1535), .A1N(n1534), .Y(
DP_OP_153J132_122_5442_n407) );
BUFX4TS U476 ( .A(n1799), .Y(n1787) );
AOI211X2TS U477 ( .A0(n399), .A1(n839), .B0(n840), .C0(
DP_OP_153J132_122_5442_n412), .Y(n842) );
NOR2X1TS U478 ( .A(n1722), .B(n1699), .Y(DP_OP_155J132_124_2038_n370) );
NOR2X1TS U479 ( .A(n1721), .B(n1696), .Y(DP_OP_155J132_124_2038_n351) );
NOR2X1TS U480 ( .A(n1148), .B(n1293), .Y(DP_OP_153J132_122_5442_n289) );
NOR2X1TS U481 ( .A(n1693), .B(n1730), .Y(DP_OP_154J132_123_2038_n369) );
OAI2BB2X1TS U482 ( .B0(n1569), .B1(n1562), .A0N(n1561), .A1N(n1560), .Y(
DP_OP_154J132_123_2038_n114) );
OAI2BB2X1TS U483 ( .B0(n1601), .B1(n1595), .A0N(n1594), .A1N(n1593), .Y(
DP_OP_155J132_124_2038_n114) );
NOR2X2TS U484 ( .A(n1747), .B(n1643), .Y(n1649) );
NOR4X4TS U485 ( .A(n1692), .B(n1717), .C(n1699), .D(n1711), .Y(n456) );
OAI211XLTS U486 ( .A0(Sgf_normalized_result[11]), .A1(n1629), .B0(n1644),
.C0(n1628), .Y(n1630) );
NOR2X2TS U487 ( .A(n1741), .B(n1625), .Y(n1629) );
OAI211XLTS U488 ( .A0(Sgf_normalized_result[15]), .A1(n1635), .B0(n1644),
.C0(n1634), .Y(n1636) );
NOR2X2TS U489 ( .A(n1743), .B(n1631), .Y(n1635) );
OAI211XLTS U490 ( .A0(Sgf_normalized_result[19]), .A1(n1641), .B0(n1644),
.C0(n1640), .Y(n1642) );
NOR2X2TS U491 ( .A(n1745), .B(n1637), .Y(n1641) );
OAI211XLTS U492 ( .A0(Sgf_normalized_result[7]), .A1(n1623), .B0(n1644),
.C0(n1622), .Y(n1624) );
NOR2X2TS U493 ( .A(n1739), .B(n1619), .Y(n1623) );
CLKINVX3TS U494 ( .A(n953), .Y(n1445) );
NOR2X2TS U495 ( .A(DP_OP_156J132_125_3370_n123), .B(n1656), .Y(n1653) );
INVX2TS U496 ( .A(n404), .Y(n433) );
NOR4X2TS U497 ( .A(n417), .B(n1717), .C(n1699), .D(n1711), .Y(n459) );
NOR4X4TS U498 ( .A(n416), .B(n1690), .C(n1719), .D(n1710), .Y(n449) );
NOR4X2TS U499 ( .A(n1296), .B(n1295), .C(n1294), .D(n1293), .Y(n1517) );
NOR4X2TS U500 ( .A(n1447), .B(n1054), .C(n1297), .D(n1293), .Y(n1031) );
NAND2X4TS U501 ( .A(n567), .B(n505), .Y(n1498) );
OAI21X4TS U502 ( .A0(n1254), .A1(n513), .B0(n931), .Y(n1153) );
NOR4X2TS U503 ( .A(n397), .B(n1693), .C(n1716), .D(n1709), .Y(n665) );
NOR2X4TS U504 ( .A(n841), .B(n1538), .Y(n1106) );
NOR2X4TS U505 ( .A(n1602), .B(DP_OP_155J132_124_2038_n119), .Y(n1150) );
CLKINVX3TS U506 ( .A(n516), .Y(n1176) );
NOR2X4TS U507 ( .A(n1571), .B(DP_OP_154J132_123_2038_n119), .Y(n1161) );
AOI21X2TS U508 ( .A0(n1538), .A1(n1447), .B0(n944), .Y(n1048) );
NOR3X1TS U509 ( .A(n1474), .B(n1476), .C(n1507), .Y(n1505) );
AOI21X2TS U510 ( .A0(n837), .A1(n836), .B0(n835), .Y(n1507) );
OAI32X1TS U511 ( .A0(n1554), .A1(n436), .A2(n1565), .B0(n1553), .B1(n436),
.Y(n607) );
AOI21X4TS U512 ( .A0(n424), .A1(n397), .B0(n609), .Y(n1565) );
NOR3X6TS U513 ( .A(n994), .B(n1714), .C(n1760), .Y(n1689) );
NOR3X2TS U514 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]), .C(
n1701), .Y(n779) );
NAND2X4TS U515 ( .A(Op_MX[17]), .B(n605), .Y(n1577) );
CLKBUFX3TS U516 ( .A(n1268), .Y(n1303) );
CLKBUFX3TS U517 ( .A(n1268), .Y(n1363) );
CLKBUFX3TS U518 ( .A(n1268), .Y(n1236) );
NOR4X2TS U519 ( .A(n424), .B(n1691), .C(n1698), .D(n1706), .Y(
DP_OP_154J132_123_2038_n244) );
NOR4X2TS U520 ( .A(n416), .B(n418), .C(n1690), .D(n1710), .Y(n722) );
NOR2X4TS U521 ( .A(n1245), .B(n741), .Y(n1597) );
NOR4X2TS U522 ( .A(n417), .B(n1717), .C(n443), .D(n1703), .Y(
DP_OP_155J132_124_2038_n326) );
NOR4X4TS U523 ( .A(n395), .B(n1712), .C(n1691), .D(n1718), .Y(n583) );
NOR4X2TS U524 ( .A(n424), .B(n395), .C(n1712), .D(n1691), .Y(n719) );
BUFX4TS U525 ( .A(n414), .Y(n1788) );
BUFX4TS U526 ( .A(n438), .Y(n1791) );
BUFX6TS U527 ( .A(n439), .Y(n1794) );
BUFX6TS U528 ( .A(n439), .Y(n1796) );
BUFX6TS U529 ( .A(n439), .Y(n1783) );
BUFX4TS U530 ( .A(n438), .Y(n434) );
BUFX6TS U531 ( .A(n439), .Y(n1795) );
BUFX6TS U532 ( .A(n414), .Y(n438) );
BUFX6TS U533 ( .A(n1799), .Y(n1793) );
CLKINVX6TS U534 ( .A(n413), .Y(n435) );
BUFX6TS U535 ( .A(n439), .Y(n1790) );
BUFX6TS U536 ( .A(n438), .Y(n1789) );
BUFX6TS U537 ( .A(n438), .Y(n1792) );
BUFX6TS U538 ( .A(n439), .Y(n1785) );
BUFX6TS U539 ( .A(n439), .Y(n1786) );
NOR2X4TS U540 ( .A(Op_MY[11]), .B(n508), .Y(n1448) );
CLKINVX3TS U541 ( .A(n1583), .Y(n1584) );
NOR2X1TS U542 ( .A(n1292), .B(n1148), .Y(DP_OP_153J132_122_5442_n287) );
AOI21X4TS U543 ( .A0(n508), .A1(Op_MY[11]), .B0(n1448), .Y(n1292) );
NOR2X2TS U544 ( .A(n416), .B(n418), .Y(n1368) );
INVX2TS U545 ( .A(n407), .Y(n1564) );
OAI2BB2X1TS U546 ( .B0(n1586), .B1(n1587), .A0N(n1456), .A1N(n1417), .Y(
DP_OP_155J132_124_2038_n107) );
NOR4X1TS U547 ( .A(P_Sgf[6]), .B(P_Sgf[7]), .C(P_Sgf[8]), .D(P_Sgf[9]), .Y(
n1481) );
OAI211XLTS U548 ( .A0(Sgf_normalized_result[21]), .A1(n1645), .B0(n1644),
.C0(n1643), .Y(n1646) );
NOR2X2TS U549 ( .A(n1746), .B(n1640), .Y(n1645) );
OAI211XLTS U550 ( .A0(Sgf_normalized_result[17]), .A1(n1638), .B0(n1644),
.C0(n1637), .Y(n1639) );
NOR2X2TS U551 ( .A(n1744), .B(n1634), .Y(n1638) );
OAI211XLTS U552 ( .A0(Sgf_normalized_result[13]), .A1(n1632), .B0(n1644),
.C0(n1631), .Y(n1633) );
NOR2X2TS U553 ( .A(n1742), .B(n1628), .Y(n1632) );
OAI211XLTS U554 ( .A0(Sgf_normalized_result[9]), .A1(n1626), .B0(n1644),
.C0(n1625), .Y(n1627) );
NOR2X2TS U555 ( .A(n1740), .B(n1622), .Y(n1626) );
NOR2X2TS U556 ( .A(DP_OP_156J132_125_3370_n125), .B(n1660), .Y(n1657) );
AOI2BB2X2TS U557 ( .B0(n1671), .B1(DP_OP_154J132_123_2038_n86), .A0N(n1670),
.A1N(n1673), .Y(n1208) );
AOI2BB2X2TS U558 ( .B0(n1352), .B1(DP_OP_156J132_125_3370_n131), .A0N(n1351),
.A1N(n1354), .Y(n1213) );
OAI2BB2X1TS U559 ( .B0(n1599), .B1(n1600), .A0N(n972), .A1N(n959), .Y(
DP_OP_155J132_124_2038_n116) );
AOI22X2TS U560 ( .A0(n931), .A1(n930), .B0(n1154), .B1(
DP_OP_155J132_124_2038_n119), .Y(n972) );
OAI2BB2X1TS U561 ( .B0(n1567), .B1(n1568), .A0N(n1165), .A1N(n1164), .Y(
DP_OP_154J132_123_2038_n116) );
AOI22X2TS U562 ( .A0(n950), .A1(n949), .B0(n1159), .B1(
DP_OP_154J132_123_2038_n119), .Y(n1165) );
AOI21X2TS U563 ( .A0(n1522), .A1(n1445), .B0(n943), .Y(n1049) );
AOI21X2TS U564 ( .A0(n844), .A1(n843), .B0(n842), .Y(n1052) );
CLKINVX3TS U565 ( .A(n516), .Y(n563) );
NOR2X2TS U566 ( .A(DP_OP_156J132_125_3370_n121), .B(n1652), .Y(n1181) );
OAI21X2TS U567 ( .A0(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]),
.A1(n682), .B0(n681), .Y(DP_OP_156J132_125_3370_n121) );
OAI22X2TS U568 ( .A0(beg_FSM), .A1(n1777), .B0(ack_FSM), .B1(n1000), .Y(
n1228) );
CLKINVX3TS U569 ( .A(n1300), .Y(n1678) );
AOI22X4TS U570 ( .A0(n841), .A1(n991), .B0(n985), .B1(
DP_OP_153J132_122_5442_n412), .Y(n710) );
NOR3X2TS U571 ( .A(n1311), .B(n1473), .C(n1475), .Y(n1313) );
CLKINVX3TS U572 ( .A(n992), .Y(n1475) );
AOI222X4TS U573 ( .A0(DP_OP_156J132_125_3370_n102), .A1(n1281), .B0(
DP_OP_156J132_125_3370_n102), .B1(n870), .C0(n1281), .C1(n870), .Y(
n1326) );
NAND2X4TS U574 ( .A(n1539), .B(n679), .Y(n1460) );
CLKBUFX2TS U575 ( .A(n1551), .Y(n436) );
NOR2X2TS U576 ( .A(FS_Module_state_reg[1]), .B(n1760), .Y(n1492) );
OAI21X4TS U577 ( .A0(n1583), .A1(n515), .B0(n1611), .Y(n1609) );
NAND2X4TS U578 ( .A(n1583), .B(n515), .Y(n1611) );
NOR4X2TS U579 ( .A(n1054), .B(n1294), .C(n1297), .D(n1293), .Y(n1451) );
OAI21X4TS U580 ( .A0(n1426), .A1(n567), .B0(n1521), .Y(n1523) );
NAND2X4TS U581 ( .A(n1426), .B(n567), .Y(n1521) );
OAI32X4TS U582 ( .A0(DP_OP_154J132_123_2038_n192), .A1(
DP_OP_154J132_123_2038_n193), .A2(n1170), .B0(n1169), .B1(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(
DP_OP_156J132_125_3370_n118) );
AOI2BB2X2TS U583 ( .B0(DP_OP_154J132_123_2038_n193), .B1(n1169), .A0N(n1169),
.A1N(DP_OP_154J132_123_2038_n193), .Y(DP_OP_156J132_125_3370_n119) );
AOI21X2TS U584 ( .A0(n575), .A1(n574), .B0(DP_OP_154J132_123_2038_n192), .Y(
DP_OP_154J132_123_2038_n193) );
NOR4X2TS U585 ( .A(n417), .B(n1717), .C(n1708), .D(n1696), .Y(
DP_OP_155J132_124_2038_n335) );
NOR4X2TS U586 ( .A(n397), .B(n1716), .C(n1700), .D(n1713), .Y(
DP_OP_154J132_123_2038_n335) );
INVX2TS U587 ( .A(n1370), .Y(n437) );
NAND2X2TS U588 ( .A(n779), .B(n1714), .Y(n1370) );
NOR4X2TS U589 ( .A(n418), .B(n1690), .C(n1704), .D(n1695), .Y(
DP_OP_155J132_124_2038_n235) );
NOR4X2TS U590 ( .A(n424), .B(n1691), .C(n1702), .D(n1694), .Y(
DP_OP_154J132_123_2038_n235) );
BUFX4TS U591 ( .A(n414), .Y(n1799) );
NOR2X4TS U592 ( .A(n600), .B(DP_OP_154J132_123_2038_n119), .Y(n1160) );
AOI21X2TS U593 ( .A0(n395), .A1(n1693), .B0(n602), .Y(n600) );
OAI2BB2X2TS U594 ( .B0(n1273), .B1(DP_OP_156J132_125_3370_n95), .A0N(n1275),
.A1N(n1272), .Y(n1388) );
XNOR2X2TS U595 ( .A(n773), .B(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(
DP_OP_156J132_125_3370_n95) );
NOR3X4TS U596 ( .A(n1254), .B(n513), .C(n931), .Y(n1151) );
OR2X1TS U597 ( .A(FSM_selector_C), .B(n517), .Y(n979) );
INVX2TS U598 ( .A(n979), .Y(n440) );
INVX2TS U599 ( .A(n979), .Y(n441) );
INVX2TS U600 ( .A(n440), .Y(n560) );
AOI21X4TS U601 ( .A0(n497), .A1(Op_MX[11]), .B0(n1446), .Y(n1148) );
NOR4X2TS U602 ( .A(n1295), .B(n1296), .C(n1054), .D(n1446), .Y(n1510) );
NOR2X4TS U603 ( .A(Op_MX[11]), .B(n497), .Y(n1446) );
CLKBUFX2TS U604 ( .A(n409), .Y(n442) );
NOR2XLTS U605 ( .A(n1469), .B(n1468), .Y(n942) );
NOR2XLTS U606 ( .A(n1476), .B(n1498), .Y(DP_OP_153J132_122_5442_n150) );
NOR2XLTS U607 ( .A(n1496), .B(n1480), .Y(DP_OP_153J132_122_5442_n155) );
INVX2TS U608 ( .A(DP_OP_155J132_124_2038_n29), .Y(n1157) );
NOR2XLTS U609 ( .A(n1580), .B(n1579), .Y(DP_OP_154J132_123_2038_n100) );
NOR2XLTS U610 ( .A(n1292), .B(n1294), .Y(n1299) );
NOR2XLTS U611 ( .A(n1720), .B(n1700), .Y(n1361) );
NOR2XLTS U612 ( .A(n1730), .B(n1709), .Y(n1412) );
NOR2XLTS U613 ( .A(n1725), .B(n1694), .Y(n592) );
NOR2XLTS U614 ( .A(n1446), .B(n1292), .Y(n910) );
NOR2XLTS U615 ( .A(n1724), .B(n1710), .Y(n1409) );
NOR2XLTS U616 ( .A(n405), .B(n1726), .Y(n1461) );
NOR3XLTS U617 ( .A(P_Sgf[22]), .B(P_Sgf[0]), .C(P_Sgf[1]), .Y(n1483) );
OAI21XLTS U618 ( .A0(n396), .A1(n394), .B0(n473), .Y(n472) );
OAI21XLTS U619 ( .A0(n1211), .A1(n1208), .B0(n1209), .Y(n894) );
OAI21XLTS U620 ( .A0(n1664), .A1(n1663), .B0(n1678), .Y(n1665) );
OAI21XLTS U621 ( .A0(n1649), .A1(Sgf_normalized_result[23]), .B0(n1648), .Y(
n1650) );
OAI31X1TS U622 ( .A0(FS_Module_state_reg[1]), .A1(n1615), .A2(n1614), .B0(
n398), .Y(n375) );
NAND2X1TS U623 ( .A(Op_MY[6]), .B(Op_MX[7]), .Y(n446) );
NAND2X1TS U624 ( .A(Op_MY[7]), .B(Op_MX[6]), .Y(n445) );
AOI21X1TS U625 ( .A0(n446), .A1(n445), .B0(n459), .Y(n756) );
INVX2TS U626 ( .A(n756), .Y(DP_OP_155J132_124_2038_n202) );
NOR2X2TS U627 ( .A(n416), .B(n1699), .Y(n513) );
INVX2TS U628 ( .A(n931), .Y(DP_OP_155J132_124_2038_n119) );
NAND2X1TS U629 ( .A(Op_MY[1]), .B(Op_MX[1]), .Y(n447) );
OAI32X1TS U630 ( .A0(n449), .A1(n1719), .A2(n394), .B0(n447), .B1(n449), .Y(
n724) );
NOR2XLTS U631 ( .A(n393), .B(n1707), .Y(n723) );
NAND2X1TS U632 ( .A(Op_MY[1]), .B(Op_MX[2]), .Y(n448) );
OAI32X1TS U633 ( .A0(n402), .A1(n1697), .A2(n393), .B0(n448), .B1(n402), .Y(
n827) );
AOI21X1TS U634 ( .A0(Op_MY[3]), .A1(Op_MX[0]), .B0(n449), .Y(n452) );
AOI21X1TS U635 ( .A0(n449), .A1(Op_MY[3]), .B0(n452), .Y(n450) );
NAND2X1TS U636 ( .A(Op_MY[2]), .B(Op_MX[1]), .Y(n451) );
XNOR2X1TS U637 ( .A(n450), .B(n451), .Y(n826) );
NOR2XLTS U638 ( .A(n452), .B(n451), .Y(n818) );
INVX2TS U639 ( .A(n453), .Y(DP_OP_155J132_124_2038_n83) );
NAND2X1TS U640 ( .A(Op_MY[7]), .B(Op_MX[7]), .Y(n454) );
OAI32X1TS U641 ( .A0(n456), .A1(n1699), .A2(n1692), .B0(n454), .B1(n456),
.Y(n460) );
NOR2XLTS U642 ( .A(n396), .B(n1708), .Y(n458) );
NAND2X1TS U643 ( .A(Op_MY[7]), .B(Op_MX[8]), .Y(n455) );
OAI32X1TS U644 ( .A0(DP_OP_155J132_124_2038_n335), .A1(n1696), .A2(n396),
.B0(n455), .B1(DP_OP_155J132_124_2038_n335), .Y(n726) );
AOI21X1TS U645 ( .A0(Op_MX[6]), .A1(Op_MY[9]), .B0(n456), .Y(n729) );
AOI31XLTS U646 ( .A0(Op_MX[6]), .A1(Op_MY[9]), .A2(n456), .B0(n729), .Y(n457) );
NAND2X1TS U647 ( .A(Op_MY[8]), .B(Op_MX[7]), .Y(n728) );
XNOR2X1TS U648 ( .A(n457), .B(n728), .Y(n725) );
NOR2X1TS U649 ( .A(n396), .B(n1699), .Y(n860) );
NOR2XLTS U650 ( .A(n1724), .B(n1704), .Y(n463) );
NOR2XLTS U651 ( .A(n1723), .B(n1695), .Y(n462) );
CMPR32X2TS U652 ( .A(DP_OP_155J132_124_2038_n231), .B(
DP_OP_155J132_124_2038_n225), .C(n461), .CO(n467), .S(n453) );
CMPR32X2TS U653 ( .A(DP_OP_155J132_124_2038_n215), .B(n463), .C(n462), .CO(
n484), .S(n464) );
NOR2XLTS U654 ( .A(n1724), .B(n1695), .Y(n482) );
CMPR32X2TS U655 ( .A(DP_OP_155J132_124_2038_n216), .B(n465), .C(n464), .CO(
n483), .S(n1022) );
CMPR32X2TS U656 ( .A(DP_OP_155J132_124_2038_n219), .B(
DP_OP_155J132_124_2038_n217), .C(n466), .CO(n465), .S(n1113) );
CMPR32X2TS U657 ( .A(DP_OP_155J132_124_2038_n224), .B(
DP_OP_155J132_124_2038_n220), .C(n467), .CO(n466), .S(n973) );
NAND2X1TS U658 ( .A(Op_MY[0]), .B(Op_MX[1]), .Y(n468) );
NOR2X1TS U659 ( .A(n393), .B(n396), .Y(n741) );
NOR2X2TS U660 ( .A(Op_MX[0]), .B(Op_MX[6]), .Y(n1254) );
NOR2X1TS U661 ( .A(Op_MY[0]), .B(Op_MY[6]), .Y(n1245) );
INVX2TS U662 ( .A(n978), .Y(n1610) );
NOR2X1TS U663 ( .A(n1254), .B(n513), .Y(n471) );
INVX2TS U664 ( .A(n471), .Y(n1602) );
OAI2BB2XLTS U665 ( .B0(n1597), .B1(n1153), .A0N(n1610), .A1N(n1150), .Y(n469) );
AOI21X1TS U666 ( .A0(n978), .A1(n1151), .B0(n469), .Y(n477) );
INVX2TS U667 ( .A(n470), .Y(n476) );
AOI21X1TS U668 ( .A0(n1597), .A1(n471), .B0(DP_OP_155J132_124_2038_n119),
.Y(n475) );
INVX2TS U669 ( .A(n1597), .Y(n1612) );
OAI22X1TS U670 ( .A0(n1368), .A1(n860), .B0(n1602), .B1(n1612), .Y(n474) );
NAND2X1TS U671 ( .A(Op_MX[6]), .B(Op_MY[0]), .Y(n473) );
OAI31X1TS U672 ( .A0(n417), .A1(n473), .A2(n416), .B0(n472), .Y(n802) );
NOR2X1TS U673 ( .A(DP_OP_155J132_124_2038_n83), .B(n802), .Y(n801) );
CMPR32X2TS U674 ( .A(n476), .B(n475), .C(n474), .CO(n480), .S(n795) );
CMPR32X2TS U675 ( .A(DP_OP_155J132_124_2038_n202), .B(n1335), .C(n477), .CO(
n478), .S(n470) );
INVX2TS U676 ( .A(n478), .Y(n479) );
CMPR32X2TS U677 ( .A(DP_OP_155J132_124_2038_n75), .B(n480), .C(n479), .CO(
n481), .S(n1025) );
CMPR32X2TS U678 ( .A(DP_OP_155J132_124_2038_n70), .B(
DP_OP_155J132_124_2038_n74), .C(n481), .CO(n485), .S(n1020) );
CMPR32X2TS U679 ( .A(n484), .B(n483), .C(n482), .CO(n1015), .S(n1016) );
CMPR32X2TS U680 ( .A(DP_OP_155J132_124_2038_n69), .B(
DP_OP_155J132_124_2038_n65), .C(n485), .CO(n486), .S(n1017) );
CMPR32X2TS U681 ( .A(DP_OP_155J132_124_2038_n58), .B(
DP_OP_155J132_124_2038_n64), .C(n486), .CO(n487), .S(n1013) );
CMPR32X2TS U682 ( .A(DP_OP_155J132_124_2038_n57), .B(
DP_OP_155J132_124_2038_n52), .C(n487), .CO(n488), .S(n858) );
CMPR32X2TS U683 ( .A(DP_OP_155J132_124_2038_n51), .B(
DP_OP_155J132_124_2038_n46), .C(n488), .CO(n489), .S(n754) );
CMPR32X2TS U684 ( .A(DP_OP_155J132_124_2038_n45), .B(
DP_OP_155J132_124_2038_n40), .C(n489), .CO(n734), .S(n751) );
INVX2TS U685 ( .A(n490), .Y(DP_OP_156J132_125_3370_n103) );
NOR2X1TS U686 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n1189) );
NAND3X2TS U687 ( .A(n1760), .B(n1189), .C(n1714), .Y(n491) );
BUFX3TS U688 ( .A(n491), .Y(n1762) );
INVX2TS U689 ( .A(rst), .Y(n167) );
BUFX3TS U690 ( .A(n167), .Y(n1780) );
BUFX3TS U691 ( .A(n167), .Y(n1781) );
BUFX3TS U692 ( .A(n491), .Y(n1761) );
CLKBUFX2TS U693 ( .A(n491), .Y(n923) );
BUFX3TS U694 ( .A(n923), .Y(n1767) );
BUFX3TS U695 ( .A(n491), .Y(n1776) );
BUFX3TS U696 ( .A(n923), .Y(n1768) );
BUFX3TS U697 ( .A(n491), .Y(n1774) );
BUFX3TS U698 ( .A(n923), .Y(n1769) );
BUFX3TS U699 ( .A(n491), .Y(n1775) );
BUFX3TS U700 ( .A(n923), .Y(n1772) );
BUFX3TS U701 ( .A(n167), .Y(n1778) );
BUFX3TS U702 ( .A(n491), .Y(n1764) );
BUFX3TS U703 ( .A(n923), .Y(n1773) );
BUFX3TS U704 ( .A(n923), .Y(n1771) );
BUFX3TS U705 ( .A(n167), .Y(n1779) );
NOR2X1TS U706 ( .A(n425), .B(n393), .Y(n492) );
CMPR32X2TS U707 ( .A(Op_MY[13]), .B(Op_MY[1]), .C(n492), .CO(n511), .S(n839)
);
AOI21X4TS U708 ( .A0(n424), .A1(n418), .B0(n492), .Y(n840) );
INVX2TS U709 ( .A(n840), .Y(n1522) );
NOR2X1TS U710 ( .A(n1522), .B(n1445), .Y(n943) );
INVX2TS U711 ( .A(n1503), .Y(n1476) );
NOR2X1TS U712 ( .A(n405), .B(n394), .Y(n503) );
CMPR32X2TS U713 ( .A(Op_MX[18]), .B(Op_MX[6]), .C(n495), .CO(n504), .S(n567)
);
INVX2TS U714 ( .A(n1446), .Y(n1508) );
CMPR32X2TS U715 ( .A(Op_MX[16]), .B(Op_MX[4]), .C(n496), .CO(n494), .S(n1055) );
INVX2TS U716 ( .A(n1148), .Y(n958) );
CMPR32X2TS U717 ( .A(Op_MX[22]), .B(Op_MX[10]), .C(n499), .CO(n497), .S(
n1514) );
CMPR32X2TS U718 ( .A(Op_MX[14]), .B(Op_MX[2]), .C(n500), .CO(n498), .S(n991)
);
CMPR32X2TS U719 ( .A(Op_MX[21]), .B(Op_MX[9]), .C(n501), .CO(n499), .S(n1515) );
CMPR32X2TS U720 ( .A(Op_MX[13]), .B(Op_MX[1]), .C(n503), .CO(n500), .S(n841)
);
CMPR32X2TS U721 ( .A(Op_MX[20]), .B(Op_MX[8]), .C(n502), .CO(n501), .S(n952)
);
INVX2TS U722 ( .A(n399), .Y(n1538) );
CMPR32X2TS U723 ( .A(Op_MX[19]), .B(Op_MX[7]), .C(n504), .CO(n502), .S(n954)
);
INVX2TS U724 ( .A(n954), .Y(n1447) );
NOR2X1TS U725 ( .A(n1538), .B(n1447), .Y(n944) );
OAI21X4TS U726 ( .A0(n567), .A1(n505), .B0(n1498), .Y(n1496) );
NOR2XLTS U727 ( .A(n1476), .B(n1496), .Y(DP_OP_153J132_122_5442_n158) );
CMPR32X2TS U728 ( .A(Op_MY[16]), .B(Op_MY[4]), .C(n506), .CO(n676), .S(n1531) );
CMPR32X2TS U729 ( .A(Op_MY[20]), .B(Op_MY[8]), .C(n507), .CO(n512), .S(n1509) );
INVX2TS U730 ( .A(n1292), .Y(n678) );
CMPR32X2TS U731 ( .A(Op_MY[15]), .B(Op_MY[3]), .C(n509), .CO(n506), .S(n1425) );
CMPR32X2TS U732 ( .A(Op_MY[14]), .B(Op_MY[2]), .C(n511), .CO(n509), .S(n1270) );
CMPR32X2TS U733 ( .A(Op_MY[21]), .B(Op_MY[9]), .C(n512), .CO(n510), .S(n1513) );
CMPR32X2TS U734 ( .A(n839), .B(n1509), .C(n943), .CO(n925), .S(n1503) );
INVX2TS U735 ( .A(n997), .Y(n1480) );
NOR2XLTS U736 ( .A(n1612), .B(n1609), .Y(DP_OP_155J132_124_2038_n100) );
NOR2X1TS U737 ( .A(FS_Module_state_reg[3]), .B(n1701), .Y(n982) );
NAND2X1TS U738 ( .A(FS_Module_state_reg[3]), .B(n1701), .Y(n994) );
NOR2X2TS U739 ( .A(FS_Module_state_reg[0]), .B(n994), .Y(n1613) );
AOI32X4TS U740 ( .A0(FSM_add_overflow_flag), .A1(FS_Module_state_reg[1]),
.A2(n1613), .B0(n779), .B1(FS_Module_state_reg[1]), .Y(n1178) );
NAND2X1TS U741 ( .A(n516), .B(n1178), .Y(n517) );
AOI22X1TS U742 ( .A0(Sgf_normalized_result[4]), .A1(n1176), .B0(n427), .B1(
Add_result[5]), .Y(n519) );
AOI22X1TS U743 ( .A0(P_Sgf[28]), .A1(n557), .B0(n432), .B1(Add_result[4]),
.Y(n518) );
OAI211XLTS U744 ( .A0(n560), .A1(n1736), .B0(n519), .C0(n518), .Y(n206) );
AOI22X1TS U745 ( .A0(Sgf_normalized_result[2]), .A1(n1176), .B0(n427), .B1(
Add_result[3]), .Y(n521) );
AOI22X1TS U746 ( .A0(n430), .A1(Add_result[2]), .B0(n412), .B1(P_Sgf[26]),
.Y(n520) );
OAI211XLTS U747 ( .A0(n560), .A1(n1737), .B0(n521), .C0(n520), .Y(n204) );
INVX2TS U748 ( .A(n516), .Y(n530) );
AOI22X1TS U749 ( .A0(Sgf_normalized_result[21]), .A1(n530), .B0(
Add_result[22]), .B1(n427), .Y(n523) );
AOI22X1TS U750 ( .A0(Add_result[21]), .A1(n430), .B0(P_Sgf[44]), .B1(n440),
.Y(n522) );
OAI211XLTS U751 ( .A0(n1756), .A1(n566), .B0(n523), .C0(n522), .Y(n223) );
AOI22X1TS U752 ( .A0(Sgf_normalized_result[20]), .A1(n530), .B0(
Add_result[21]), .B1(n427), .Y(n525) );
AOI22X1TS U753 ( .A0(Add_result[20]), .A1(n430), .B0(P_Sgf[44]), .B1(n412),
.Y(n524) );
OAI211XLTS U754 ( .A0(n1732), .A1(n560), .B0(n525), .C0(n524), .Y(n222) );
AOI22X1TS U755 ( .A0(Sgf_normalized_result[19]), .A1(n530), .B0(
Add_result[20]), .B1(n428), .Y(n527) );
AOI22X1TS U756 ( .A0(Add_result[19]), .A1(n430), .B0(n440), .B1(P_Sgf[42]),
.Y(n526) );
OAI211XLTS U757 ( .A0(n1732), .A1(n411), .B0(n527), .C0(n526), .Y(n221) );
AOI22X1TS U758 ( .A0(Sgf_normalized_result[17]), .A1(n530), .B0(
Add_result[18]), .B1(n429), .Y(n529) );
AOI22X1TS U759 ( .A0(Add_result[17]), .A1(n430), .B0(n441), .B1(P_Sgf[40]),
.Y(n528) );
OAI211XLTS U760 ( .A0(n566), .A1(n1733), .B0(n529), .C0(n528), .Y(n219) );
AOI22X1TS U761 ( .A0(Sgf_normalized_result[18]), .A1(n530), .B0(
Add_result[19]), .B1(n428), .Y(n532) );
AOI22X1TS U762 ( .A0(Add_result[18]), .A1(n430), .B0(n412), .B1(P_Sgf[42]),
.Y(n531) );
OAI211XLTS U763 ( .A0(n560), .A1(n1733), .B0(n532), .C0(n531), .Y(n220) );
AOI22X1TS U764 ( .A0(Sgf_normalized_result[15]), .A1(n563), .B0(
Add_result[16]), .B1(n429), .Y(n534) );
AOI22X1TS U765 ( .A0(Add_result[15]), .A1(n430), .B0(n440), .B1(P_Sgf[38]),
.Y(n533) );
OAI211XLTS U766 ( .A0(n566), .A1(n1734), .B0(n534), .C0(n533), .Y(n217) );
AOI22X1TS U767 ( .A0(Sgf_normalized_result[13]), .A1(n563), .B0(
Add_result[14]), .B1(n428), .Y(n536) );
AOI22X1TS U768 ( .A0(Add_result[13]), .A1(n432), .B0(n441), .B1(P_Sgf[36]),
.Y(n535) );
OAI211XLTS U769 ( .A0(n411), .A1(n1751), .B0(n536), .C0(n535), .Y(n215) );
AOI22X1TS U770 ( .A0(Sgf_normalized_result[16]), .A1(n563), .B0(
Add_result[17]), .B1(n428), .Y(n538) );
AOI22X1TS U771 ( .A0(Add_result[16]), .A1(n431), .B0(n412), .B1(P_Sgf[40]),
.Y(n537) );
OAI211XLTS U772 ( .A0(n560), .A1(n1734), .B0(n538), .C0(n537), .Y(n218) );
AOI22X1TS U773 ( .A0(Sgf_normalized_result[11]), .A1(n563), .B0(
Add_result[12]), .B1(n429), .Y(n540) );
AOI22X1TS U774 ( .A0(Add_result[11]), .A1(n432), .B0(n440), .B1(P_Sgf[34]),
.Y(n539) );
OAI211XLTS U775 ( .A0(n1748), .A1(n566), .B0(n540), .C0(n539), .Y(n213) );
AOI22X1TS U776 ( .A0(Sgf_normalized_result[9]), .A1(n563), .B0(
Add_result[10]), .B1(n429), .Y(n542) );
AOI22X1TS U777 ( .A0(Add_result[9]), .A1(n431), .B0(n441), .B1(P_Sgf[32]),
.Y(n541) );
OAI211XLTS U778 ( .A0(n566), .A1(n1735), .B0(n542), .C0(n541), .Y(n211) );
AOI22X1TS U779 ( .A0(Sgf_normalized_result[14]), .A1(n563), .B0(
Add_result[15]), .B1(n428), .Y(n544) );
AOI22X1TS U780 ( .A0(Add_result[14]), .A1(n432), .B0(n412), .B1(P_Sgf[38]),
.Y(n543) );
OAI211XLTS U781 ( .A0(n560), .A1(n1751), .B0(n544), .C0(n543), .Y(n216) );
AOI22X1TS U782 ( .A0(Sgf_normalized_result[7]), .A1(n1176), .B0(
Add_result[8]), .B1(n429), .Y(n546) );
AOI22X1TS U783 ( .A0(P_Sgf[30]), .A1(n440), .B0(Add_result[7]), .B1(n431),
.Y(n545) );
OAI211XLTS U784 ( .A0(n1749), .A1(n411), .B0(n546), .C0(n545), .Y(n209) );
AOI22X1TS U785 ( .A0(Sgf_normalized_result[5]), .A1(n1176), .B0(
Add_result[6]), .B1(n428), .Y(n548) );
AOI22X1TS U786 ( .A0(P_Sgf[28]), .A1(n441), .B0(n431), .B1(Add_result[5]),
.Y(n547) );
OAI211XLTS U787 ( .A0(n411), .A1(n1752), .B0(n548), .C0(n547), .Y(n207) );
AOI22X1TS U788 ( .A0(Sgf_normalized_result[12]), .A1(n563), .B0(
Add_result[13]), .B1(n429), .Y(n550) );
AOI22X1TS U789 ( .A0(Add_result[12]), .A1(n431), .B0(n557), .B1(P_Sgf[36]),
.Y(n549) );
OAI211XLTS U790 ( .A0(n1748), .A1(n560), .B0(n550), .C0(n549), .Y(n214) );
AOI22X1TS U791 ( .A0(Sgf_normalized_result[3]), .A1(n1176), .B0(n427), .B1(
Add_result[4]), .Y(n552) );
AOI22X1TS U792 ( .A0(n441), .A1(P_Sgf[26]), .B0(n432), .B1(Add_result[3]),
.Y(n551) );
OAI211XLTS U793 ( .A0(n566), .A1(n1736), .B0(n552), .C0(n551), .Y(n205) );
AOI22X1TS U794 ( .A0(Sgf_normalized_result[10]), .A1(n563), .B0(
Add_result[11]), .B1(n428), .Y(n554) );
AOI22X1TS U795 ( .A0(Add_result[10]), .A1(n432), .B0(n412), .B1(P_Sgf[34]),
.Y(n553) );
OAI211XLTS U796 ( .A0(n560), .A1(n1735), .B0(n554), .C0(n553), .Y(n212) );
AOI22X1TS U797 ( .A0(Sgf_normalized_result[8]), .A1(n563), .B0(Add_result[9]), .B1(n428), .Y(n556) );
AOI22X1TS U798 ( .A0(Add_result[8]), .A1(n431), .B0(n557), .B1(P_Sgf[32]),
.Y(n555) );
OAI211XLTS U799 ( .A0(n1749), .A1(n560), .B0(n556), .C0(n555), .Y(n210) );
AOI22X1TS U800 ( .A0(Sgf_normalized_result[6]), .A1(n1176), .B0(
Add_result[7]), .B1(n429), .Y(n559) );
AOI22X1TS U801 ( .A0(P_Sgf[30]), .A1(n412), .B0(Add_result[6]), .B1(n432),
.Y(n558) );
OAI211XLTS U802 ( .A0(n560), .A1(n1752), .B0(n559), .C0(n558), .Y(n208) );
AOI22X1TS U803 ( .A0(Sgf_normalized_result[1]), .A1(n1176), .B0(n427), .B1(
Add_result[2]), .Y(n562) );
AOI22X1TS U804 ( .A0(P_Sgf[24]), .A1(n440), .B0(n431), .B1(Add_result[1]),
.Y(n561) );
OAI211XLTS U805 ( .A0(n411), .A1(n1737), .B0(n562), .C0(n561), .Y(n203) );
AOI22X1TS U806 ( .A0(Sgf_normalized_result[0]), .A1(n563), .B0(n427), .B1(
Add_result[1]), .Y(n565) );
AOI22X1TS U807 ( .A0(P_Sgf[23]), .A1(n441), .B0(n432), .B1(Add_result[0]),
.Y(n564) );
OAI211XLTS U808 ( .A0(n1757), .A1(n566), .B0(n565), .C0(n564), .Y(n202) );
INVX2TS U809 ( .A(n1270), .Y(n1269) );
INVX2TS U810 ( .A(n839), .Y(n1524) );
OAI22X1TS U811 ( .A0(n1269), .A1(n1523), .B0(n1524), .B1(n1521), .Y(
DP_OP_153J132_122_5442_n370) );
INVX2TS U812 ( .A(DP_OP_153J132_122_5442_n370), .Y(
DP_OP_153J132_122_5442_n371) );
NOR2X2TS U813 ( .A(n1716), .B(n1709), .Y(DP_OP_154J132_123_2038_n319) );
CMPR32X2TS U814 ( .A(DP_OP_154J132_123_2038_n306), .B(Op_MX[22]), .C(
Op_MY[22]), .CO(n574), .S(n577) );
NAND2X1TS U815 ( .A(Op_MY[19]), .B(Op_MX[20]), .Y(n568) );
OAI32X1TS U816 ( .A0(DP_OP_154J132_123_2038_n335), .A1(n1700), .A2(n408),
.B0(n568), .B1(DP_OP_154J132_123_2038_n335), .Y(n669) );
NOR2XLTS U817 ( .A(n1693), .B(n1731), .Y(n569) );
NAND3X1TS U818 ( .A(Op_MX[18]), .B(Op_MY[20]), .C(
DP_OP_154J132_123_2038_n319), .Y(n570) );
OA21XLTS U819 ( .A0(DP_OP_154J132_123_2038_n319), .A1(n569), .B0(n570), .Y(
n666) );
NOR2XLTS U820 ( .A(n408), .B(n1713), .Y(n664) );
NAND2X1TS U821 ( .A(Op_MY[20]), .B(Op_MX[19]), .Y(n572) );
OAI21X1TS U822 ( .A0(n1720), .A1(n1693), .B0(n570), .Y(n573) );
OAI31X1TS U823 ( .A0(n1720), .A1(n1693), .A2(n570), .B0(n573), .Y(n571) );
XOR2X1TS U824 ( .A(n572), .B(n571), .Y(n667) );
NOR2BX1TS U825 ( .AN(n573), .B(n572), .Y(n670) );
NOR2X2TS U826 ( .A(n574), .B(n575), .Y(DP_OP_154J132_123_2038_n192) );
CMPR32X2TS U827 ( .A(DP_OP_154J132_123_2038_n307), .B(n577), .C(n576), .CO(
n575), .S(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]) );
CMPR32X2TS U828 ( .A(DP_OP_154J132_123_2038_n310), .B(
DP_OP_154J132_123_2038_n308), .C(n578), .CO(n576), .S(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]) );
NAND2X1TS U829 ( .A(Op_MY[18]), .B(Op_MX[19]), .Y(n580) );
NAND2X1TS U830 ( .A(Op_MX[18]), .B(Op_MY[19]), .Y(n579) );
AOI21X1TS U831 ( .A0(n580), .A1(n579), .B0(n665), .Y(n790) );
INVX2TS U832 ( .A(n790), .Y(DP_OP_154J132_123_2038_n202) );
NOR2X1TS U833 ( .A(n405), .B(n1693), .Y(n602) );
NOR2X2TS U834 ( .A(n397), .B(n1693), .Y(DP_OP_154J132_123_2038_n326) );
NAND2X1TS U835 ( .A(Op_MX[13]), .B(Op_MY[13]), .Y(n581) );
OAI32X1TS U836 ( .A0(n583), .A1(n1718), .A2(n395), .B0(n581), .B1(n583), .Y(
n720) );
NOR2XLTS U837 ( .A(n425), .B(n1706), .Y(n718) );
NAND2X1TS U838 ( .A(Op_MY[13]), .B(Op_MX[14]), .Y(n582) );
OAI32X1TS U839 ( .A0(DP_OP_154J132_123_2038_n244), .A1(n1698), .A2(n425),
.B0(n582), .B1(DP_OP_154J132_123_2038_n244), .Y(n775) );
AOI21X1TS U840 ( .A0(Op_MY[15]), .A1(Op_MX[12]), .B0(n583), .Y(n586) );
AOI21X1TS U841 ( .A0(n583), .A1(Op_MY[15]), .B0(n586), .Y(n584) );
NAND2X1TS U842 ( .A(Op_MX[13]), .B(Op_MY[14]), .Y(n585) );
XNOR2X1TS U843 ( .A(n584), .B(n585), .Y(n774) );
NOR2XLTS U844 ( .A(n586), .B(n585), .Y(n816) );
NOR2XLTS U845 ( .A(n1726), .B(n1702), .Y(n593) );
INVX2TS U846 ( .A(n587), .Y(DP_OP_154J132_123_2038_n80) );
CMPR32X2TS U847 ( .A(DP_OP_154J132_123_2038_n219), .B(
DP_OP_154J132_123_2038_n217), .C(n588), .CO(n595), .S(n589) );
INVX2TS U848 ( .A(n589), .Y(DP_OP_154J132_123_2038_n81) );
CMPR32X2TS U849 ( .A(DP_OP_154J132_123_2038_n224), .B(
DP_OP_154J132_123_2038_n220), .C(n590), .CO(n588), .S(n591) );
INVX2TS U850 ( .A(n591), .Y(DP_OP_154J132_123_2038_n82) );
CMPR32X2TS U851 ( .A(DP_OP_154J132_123_2038_n215), .B(n593), .C(n592), .CO(
n635), .S(n594) );
CMPR32X2TS U852 ( .A(DP_OP_154J132_123_2038_n216), .B(n595), .C(n594), .CO(
n634), .S(n587) );
NOR2XLTS U853 ( .A(n1726), .B(n1694), .Y(n633) );
INVX2TS U854 ( .A(n596), .Y(DP_OP_154J132_123_2038_n79) );
INVX2TS U855 ( .A(DP_OP_154J132_123_2038_n20), .Y(n615) );
INVX2TS U856 ( .A(DP_OP_154J132_123_2038_n22), .Y(n614) );
INVX2TS U857 ( .A(DP_OP_154J132_123_2038_n27), .Y(n619) );
INVX2TS U858 ( .A(DP_OP_154J132_123_2038_n23), .Y(n618) );
INVX2TS U859 ( .A(DP_OP_154J132_123_2038_n33), .Y(n623) );
INVX2TS U860 ( .A(DP_OP_154J132_123_2038_n28), .Y(n622) );
INVX2TS U861 ( .A(DP_OP_154J132_123_2038_n39), .Y(n627) );
INVX2TS U862 ( .A(DP_OP_154J132_123_2038_n34), .Y(n626) );
INVX2TS U863 ( .A(DP_OP_154J132_123_2038_n45), .Y(n631) );
INVX2TS U864 ( .A(DP_OP_154J132_123_2038_n40), .Y(n630) );
INVX2TS U865 ( .A(DP_OP_154J132_123_2038_n51), .Y(n662) );
INVX2TS U866 ( .A(DP_OP_154J132_123_2038_n46), .Y(n661) );
INVX2TS U867 ( .A(DP_OP_154J132_123_2038_n57), .Y(n658) );
INVX2TS U868 ( .A(DP_OP_154J132_123_2038_n52), .Y(n657) );
INVX2TS U869 ( .A(DP_OP_154J132_123_2038_n58), .Y(n654) );
INVX2TS U870 ( .A(DP_OP_154J132_123_2038_n69), .Y(n650) );
INVX2TS U871 ( .A(DP_OP_154J132_123_2038_n65), .Y(n649) );
INVX2TS U872 ( .A(DP_OP_154J132_123_2038_n70), .Y(n647) );
INVX2TS U873 ( .A(DP_OP_154J132_123_2038_n74), .Y(n646) );
INVX2TS U874 ( .A(DP_OP_154J132_123_2038_n75), .Y(n644) );
NOR2X1TS U875 ( .A(n425), .B(n408), .Y(n609) );
INVX2TS U876 ( .A(n1565), .Y(n1579) );
NAND2X2TS U877 ( .A(n600), .B(DP_OP_154J132_123_2038_n119), .Y(n1163) );
INVX2TS U878 ( .A(n600), .Y(n1571) );
AOI2BB2XLTS U879 ( .B0(n1548), .B1(n1163), .A0N(n1161), .A1N(n1548), .Y(n597) );
AOI21X1TS U880 ( .A0(n1160), .A1(n1579), .B0(n597), .Y(n601) );
NAND2X1TS U881 ( .A(Op_MY[12]), .B(Op_MX[13]), .Y(n599) );
NAND2X1TS U882 ( .A(Op_MX[12]), .B(Op_MY[13]), .Y(n598) );
AOI21X1TS U883 ( .A0(n599), .A1(n598), .B0(n719), .Y(n845) );
OAI21XLTS U884 ( .A0(n1579), .A1(n1571), .B0(n950), .Y(n638) );
NOR2X2TS U885 ( .A(n425), .B(n395), .Y(n1389) );
AOI2BB2XLTS U886 ( .B0(n1565), .B1(n600), .A0N(n1389), .A1N(
DP_OP_154J132_123_2038_n326), .Y(n637) );
CMPR32X2TS U887 ( .A(DP_OP_154J132_123_2038_n202), .B(n601), .C(n845), .CO(
n643), .S(n636) );
CMPR32X2TS U888 ( .A(Op_MX[13]), .B(Op_MX[19]), .C(n602), .CO(n948), .S(n950) );
INVX2TS U889 ( .A(n606), .Y(n1118) );
AOI22X4TS U890 ( .A0(n407), .A1(n1118), .B0(n606), .B1(n1564), .Y(n1554) );
OAI21X4TS U891 ( .A0(Op_MX[17]), .A1(n605), .B0(n1577), .Y(n1550) );
INVX2TS U892 ( .A(n1550), .Y(n1551) );
OAI221X4TS U893 ( .A0(n606), .A1(n1550), .B0(n1118), .B1(n436), .C0(n1554),
.Y(n1553) );
INVX2TS U894 ( .A(n607), .Y(n652) );
XOR2X1TS U895 ( .A(DP_OP_154J132_123_2038_n19), .B(n608), .Y(n611) );
CMPR32X2TS U896 ( .A(Op_MY[13]), .B(Op_MY[19]), .C(n609), .CO(n951), .S(
n1548) );
NOR2X4TS U897 ( .A(Op_MY[17]), .B(n1133), .Y(n1572) );
OAI21XLTS U898 ( .A0(n1572), .A1(n1577), .B0(n611), .Y(n610) );
OAI31X1TS U899 ( .A0(n611), .A1(n1572), .A2(n1577), .B0(n610), .Y(n612) );
XNOR2X1TS U900 ( .A(DP_OP_154J132_123_2038_n18), .B(n612), .Y(n781) );
CMPR32X2TS U901 ( .A(n615), .B(n614), .C(n613), .CO(n608), .S(n616) );
INVX2TS U902 ( .A(n616), .Y(n684) );
CMPR32X2TS U903 ( .A(n619), .B(n618), .C(n617), .CO(n613), .S(n620) );
INVX2TS U904 ( .A(n620), .Y(n783) );
CMPR32X2TS U905 ( .A(n623), .B(n622), .C(n621), .CO(n617), .S(n624) );
INVX2TS U906 ( .A(n624), .Y(n687) );
CMPR32X2TS U907 ( .A(n627), .B(n626), .C(n625), .CO(n621), .S(n628) );
INVX2TS U908 ( .A(n628), .Y(n785) );
CMPR32X2TS U909 ( .A(n631), .B(n630), .C(n629), .CO(n625), .S(n632) );
INVX2TS U910 ( .A(n632), .Y(n787) );
CMPR32X2TS U911 ( .A(n635), .B(n634), .C(n633), .CO(n1036), .S(n596) );
CMPR32X2TS U912 ( .A(n638), .B(n637), .C(n636), .CO(n642), .S(n793) );
CMPR32X2TS U913 ( .A(DP_OP_154J132_123_2038_n231), .B(
DP_OP_154J132_123_2038_n225), .C(n639), .CO(n590), .S(n1035) );
NAND2X1TS U914 ( .A(Op_MX[12]), .B(Op_MY[18]), .Y(n641) );
NAND2X1TS U915 ( .A(Op_MX[18]), .B(Op_MY[12]), .Y(n640) );
XOR2X1TS U916 ( .A(n641), .B(n640), .Y(n800) );
NAND2X1TS U917 ( .A(n1035), .B(n800), .Y(n799) );
CMPR32X2TS U918 ( .A(n644), .B(n643), .C(n642), .CO(n645), .S(n691) );
CMPR32X2TS U919 ( .A(n647), .B(n646), .C(n645), .CO(n648), .S(n689) );
CMPR32X2TS U920 ( .A(n650), .B(n649), .C(n648), .CO(n653), .S(n777) );
INVX2TS U921 ( .A(n651), .Y(n904) );
CMPR32X2TS U922 ( .A(n654), .B(n653), .C(n652), .CO(n656), .S(n655) );
INVX2TS U923 ( .A(n655), .Y(n903) );
CMPR32X2TS U924 ( .A(n658), .B(n657), .C(n656), .CO(n660), .S(n659) );
INVX2TS U925 ( .A(n659), .Y(n791) );
CMPR32X2TS U926 ( .A(n662), .B(n661), .C(n660), .CO(n629), .S(n663) );
INVX2TS U927 ( .A(n663), .Y(n788) );
CMPR32X2TS U928 ( .A(n666), .B(n665), .C(n664), .CO(n668), .S(n1019) );
CMPR32X2TS U929 ( .A(n669), .B(n668), .C(n667), .CO(n671), .S(n975) );
CMPR32X2TS U930 ( .A(DP_OP_154J132_123_2038_n330), .B(n671), .C(n670), .CO(
n672), .S(n1033) );
CMPR32X2TS U931 ( .A(DP_OP_154J132_123_2038_n329), .B(
DP_OP_154J132_123_2038_n323), .C(n672), .CO(n673), .S(n1541) );
CMPR32X2TS U932 ( .A(DP_OP_154J132_123_2038_n322), .B(
DP_OP_154J132_123_2038_n316), .C(n673), .CO(n674), .S(n986) );
CMPR32X2TS U933 ( .A(DP_OP_154J132_123_2038_n315), .B(
DP_OP_154J132_123_2038_n311), .C(n674), .CO(n578), .S(n984) );
NAND3XLTS U934 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .C(n682), .Y(
n1170) );
INVX2TS U935 ( .A(n1170), .Y(n1169) );
CMPR32X2TS U936 ( .A(n841), .B(n952), .C(n944), .CO(n990), .S(n1504) );
INVX2TS U937 ( .A(n1504), .Y(n1474) );
CMPR32X2TS U938 ( .A(Op_MY[18]), .B(Op_MY[6]), .C(n675), .CO(n493), .S(n1539) );
CMPR32X2TS U939 ( .A(Op_MY[17]), .B(Op_MY[5]), .C(n676), .CO(n675), .S(n1527) );
INVX2TS U940 ( .A(n1448), .Y(n936) );
CMPR32X2TS U941 ( .A(n1531), .B(n678), .C(n677), .CO(n935), .S(n997) );
OAI21X4TS U942 ( .A0(n1539), .A1(n679), .B0(n1460), .Y(n1495) );
NOR2XLTS U943 ( .A(n1474), .B(n1495), .Y(DP_OP_153J132_122_5442_n193) );
CMPR32X2TS U944 ( .A(n1425), .B(n1516), .C(n680), .CO(n677), .S(n940) );
INVX2TS U945 ( .A(n940), .Y(n1468) );
NOR2XLTS U946 ( .A(n1496), .B(n1468), .Y(DP_OP_153J132_122_5442_n156) );
INVX2TS U947 ( .A(n1370), .Y(DP_OP_36J132_126_4699_n33) );
INVX2TS U948 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(
DP_OP_154J132_123_2038_n194) );
NAND2X1TS U949 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .B(
n682), .Y(n681) );
AO21X1TS U950 ( .A0(DP_OP_154J132_123_2038_n194), .A1(n681), .B0(n1169), .Y(
DP_OP_156J132_125_3370_n120) );
CMPR32X2TS U951 ( .A(n684), .B(n683), .C(n986), .CO(n780), .S(n685) );
INVX2TS U952 ( .A(n685), .Y(DP_OP_156J132_125_3370_n123) );
CMPR32X2TS U953 ( .A(n687), .B(n686), .C(n1033), .CO(n782), .S(n688) );
INVX2TS U954 ( .A(n688), .Y(DP_OP_156J132_125_3370_n125) );
CMPR32X2TS U955 ( .A(DP_OP_154J132_123_2038_n80), .B(n690), .C(n689), .CO(
n778), .S(DP_OP_156J132_125_3370_n132) );
CMPR32X2TS U956 ( .A(DP_OP_154J132_123_2038_n81), .B(n692), .C(n691), .CO(
n690), .S(DP_OP_156J132_125_3370_n133) );
NAND2X2TS U957 ( .A(n399), .B(n841), .Y(n1105) );
NAND2X2TS U958 ( .A(n841), .B(n1538), .Y(n1108) );
OAI22X1TS U959 ( .A0(n1527), .A1(n1105), .B0(n1531), .B1(n1108), .Y(n693) );
AOI21X1TS U960 ( .A0(n1106), .A1(n1527), .B0(n693), .Y(n696) );
INVX2TS U961 ( .A(n1055), .Y(n694) );
AOI22X4TS U962 ( .A0(n422), .A1(n1055), .B0(n694), .B1(n421), .Y(n1444) );
OAI33X4TS U963 ( .A0(n426), .A1(n420), .A2(n694), .B0(n391), .B1(n1530),
.B2(n1055), .Y(n1442) );
AOI32X1TS U964 ( .A0(n1444), .A1(n426), .A2(n1522), .B0(n1442), .B1(n1426),
.Y(n695) );
NOR2X1TS U965 ( .A(n696), .B(n695), .Y(DP_OP_153J132_122_5442_n380) );
INVX2TS U966 ( .A(n841), .Y(DP_OP_153J132_122_5442_n412) );
AOI21X1TS U967 ( .A0(n696), .A1(n695), .B0(DP_OP_153J132_122_5442_n380), .Y(
n812) );
INVX2TS U968 ( .A(n991), .Y(n985) );
AOI22X1TS U969 ( .A0(n1270), .A1(n422), .B0(n420), .B1(n1269), .Y(n709) );
AOI221X4TS U970 ( .A0(n991), .A1(n422), .B0(n985), .B1(n420), .C0(n710), .Y(
n1535) );
AOI22X1TS U971 ( .A0(n839), .A1(n1530), .B0(n420), .B1(n1524), .Y(n701) );
AOI22X1TS U972 ( .A0(n710), .A1(n709), .B0(n1535), .B1(n701), .Y(n707) );
NAND2X1TS U973 ( .A(n840), .B(n1444), .Y(n706) );
OAI22X1TS U974 ( .A0(n1531), .A1(n1105), .B0(n1425), .B1(n1108), .Y(n697) );
AOI21X1TS U975 ( .A0(n1106), .A1(n1531), .B0(n697), .Y(n705) );
INVX2TS U976 ( .A(n698), .Y(n822) );
OAI22X1TS U977 ( .A0(n1270), .A1(n1108), .B0(n1425), .B1(n1105), .Y(n699) );
AOI21X1TS U978 ( .A0(n1106), .A1(n1425), .B0(n699), .Y(n702) );
AOI22X1TS U979 ( .A0(n840), .A1(n1530), .B0(n420), .B1(n1522), .Y(n700) );
AOI22X1TS U980 ( .A0(n710), .A1(n701), .B0(n1535), .B1(n700), .Y(n703) );
NOR2X1TS U981 ( .A(n702), .B(n703), .Y(n821) );
AOI21X1TS U982 ( .A0(n703), .A1(n702), .B0(n821), .Y(n830) );
INVX2TS U983 ( .A(n710), .Y(n1537) );
INVX2TS U984 ( .A(n1535), .Y(n1532) );
OAI32X1TS U985 ( .A0(n421), .A1(n840), .A2(n1537), .B0(n1532), .B1(n420),
.Y(n829) );
OAI22X1TS U986 ( .A0(n1270), .A1(n1105), .B0(n839), .B1(n1108), .Y(n704) );
AOI21X1TS U987 ( .A0(n1106), .A1(n1270), .B0(n704), .Y(n836) );
AOI21X1TS U988 ( .A0(n840), .A1(n710), .B0(n842), .Y(n837) );
NOR2X1TS U989 ( .A(n836), .B(n837), .Y(n835) );
CMPR32X2TS U990 ( .A(n707), .B(n706), .C(n705), .CO(n714), .S(n698) );
AOI22X1TS U991 ( .A0(n839), .A1(n426), .B0(n391), .B1(n1524), .Y(n1271) );
AOI22X1TS U992 ( .A0(n840), .A1(n426), .B0(n391), .B1(n1522), .Y(n708) );
AOI22X1TS U993 ( .A0(n1444), .A1(n1271), .B0(n1442), .B1(n708), .Y(n713) );
INVX2TS U994 ( .A(n1425), .Y(n1520) );
AOI22X1TS U995 ( .A0(n422), .A1(n1425), .B0(n1520), .B1(n420), .Y(n1534) );
AOI22X1TS U996 ( .A0(n710), .A1(n1534), .B0(n1535), .B1(n709), .Y(n712) );
INVX2TS U997 ( .A(n711), .Y(n810) );
CMPR32X2TS U998 ( .A(n714), .B(n713), .C(n712), .CO(n715), .S(n711) );
INVX2TS U999 ( .A(n715), .Y(n803) );
INVX2TS U1000 ( .A(n1467), .Y(n797) );
NAND2X1TS U1001 ( .A(n954), .B(n840), .Y(n717) );
OAI21XLTS U1002 ( .A0(n1445), .A1(n1538), .B0(n717), .Y(n716) );
OAI31X1TS U1003 ( .A0(n1445), .A1(n717), .A2(n1538), .B0(n716), .Y(n796) );
NOR2X1TS U1004 ( .A(n797), .B(n796), .Y(DP_OP_156J132_125_3370_n81) );
CMPR32X2TS U1005 ( .A(n720), .B(n719), .C(n718), .CO(n776), .S(n721) );
INVX2TS U1006 ( .A(n721), .Y(DP_OP_154J132_123_2038_n87) );
INVX2TS U1007 ( .A(n1302), .Y(DP_OP_155J132_124_2038_n87) );
CMPR32X2TS U1008 ( .A(n727), .B(n726), .C(n725), .CO(n736), .S(n966) );
NOR2XLTS U1009 ( .A(n729), .B(n728), .Y(n735) );
CMPR32X2TS U1010 ( .A(DP_OP_155J132_124_2038_n322), .B(
DP_OP_155J132_124_2038_n316), .C(n730), .CO(n758), .S(n1002) );
CMPR32X2TS U1011 ( .A(DP_OP_155J132_124_2038_n329), .B(
DP_OP_155J132_124_2038_n323), .C(n731), .CO(n730), .S(n1582) );
CMPR32X2TS U1012 ( .A(n966), .B(n733), .C(n732), .CO(n750), .S(n490) );
CMPR32X2TS U1013 ( .A(DP_OP_155J132_124_2038_n39), .B(
DP_OP_155J132_124_2038_n34), .C(n734), .CO(n737), .S(n732) );
CMPR32X2TS U1014 ( .A(DP_OP_155J132_124_2038_n330), .B(n736), .C(n735), .CO(
n731), .S(n970) );
CMPR32X2TS U1015 ( .A(DP_OP_155J132_124_2038_n33), .B(
DP_OP_155J132_124_2038_n28), .C(n737), .CO(n738), .S(n749) );
CMPR32X2TS U1016 ( .A(DP_OP_155J132_124_2038_n27), .B(
DP_OP_155J132_124_2038_n23), .C(n738), .CO(n739), .S(n852) );
CMPR32X2TS U1017 ( .A(DP_OP_155J132_124_2038_n22), .B(
DP_OP_155J132_124_2038_n20), .C(n739), .CO(n740), .S(n746) );
XOR2X1TS U1018 ( .A(DP_OP_155J132_124_2038_n19), .B(n740), .Y(n743) );
CMPR32X2TS U1019 ( .A(Op_MY[1]), .B(Op_MY[7]), .C(n741), .CO(n932), .S(n978)
);
INVX2TS U1020 ( .A(n1603), .Y(n1605) );
OAI21XLTS U1021 ( .A0(n1611), .A1(n1605), .B0(n743), .Y(n742) );
OAI31X1TS U1022 ( .A0(n743), .A1(n1611), .A2(n1605), .B0(n742), .Y(n744) );
XOR2X1TS U1023 ( .A(DP_OP_155J132_124_2038_n18), .B(n744), .Y(n759) );
INVX2TS U1024 ( .A(n745), .Y(DP_OP_156J132_125_3370_n99) );
CMPR32X2TS U1025 ( .A(n1002), .B(n747), .C(n746), .CO(n760), .S(n748) );
INVX2TS U1026 ( .A(n748), .Y(DP_OP_156J132_125_3370_n100) );
CMPR32X2TS U1027 ( .A(n750), .B(n749), .C(n970), .CO(n853), .S(n1282) );
INVX2TS U1028 ( .A(n1282), .Y(DP_OP_156J132_125_3370_n102) );
CMPR32X2TS U1029 ( .A(n1006), .B(n752), .C(n751), .CO(n733), .S(n753) );
INVX2TS U1030 ( .A(n753), .Y(DP_OP_156J132_125_3370_n104) );
CMPR32X2TS U1031 ( .A(n756), .B(n755), .C(n754), .CO(n752), .S(n757) );
INVX2TS U1032 ( .A(n757), .Y(DP_OP_156J132_125_3370_n105) );
CMPR32X2TS U1033 ( .A(DP_OP_155J132_124_2038_n315), .B(
DP_OP_155J132_124_2038_n311), .C(n758), .CO(n761), .S(n1109) );
CMPR32X2TS U1034 ( .A(n1109), .B(n760), .C(n759), .CO(n762), .S(n745) );
NAND2X1TS U1035 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]),
.B(n762), .Y(n763) );
OAI21X1TS U1036 ( .A0(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]),
.A1(n762), .B0(n763), .Y(DP_OP_156J132_125_3370_n98) );
CMPR32X2TS U1037 ( .A(DP_OP_155J132_124_2038_n310), .B(
DP_OP_155J132_124_2038_n308), .C(n761), .CO(n767), .S(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]) );
NOR2XLTS U1038 ( .A(n1721), .B(n443), .Y(n765) );
NOR2XLTS U1039 ( .A(n1722), .B(n1703), .Y(n764) );
INVX2TS U1040 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(
DP_OP_155J132_124_2038_n194) );
NAND3X1TS U1041 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]),
.B(n762), .C(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(
n769) );
OAI2BB1X1TS U1042 ( .A0N(n763), .A1N(DP_OP_155J132_124_2038_n194), .B0(n769),
.Y(DP_OP_156J132_125_3370_n97) );
CMPR32X2TS U1043 ( .A(DP_OP_155J132_124_2038_n306), .B(n765), .C(n764), .CO(
n772), .S(n766) );
CMPR32X2TS U1044 ( .A(DP_OP_155J132_124_2038_n307), .B(n767), .C(n766), .CO(
n771), .S(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]) );
NOR2XLTS U1045 ( .A(n1721), .B(n1703), .Y(n770) );
INVX2TS U1046 ( .A(n768), .Y(DP_OP_155J132_124_2038_n193) );
NOR2X1TS U1047 ( .A(n769), .B(DP_OP_155J132_124_2038_n193), .Y(n773) );
AO21XLTS U1048 ( .A0(n769), .A1(DP_OP_155J132_124_2038_n193), .B0(n773), .Y(
DP_OP_156J132_125_3370_n96) );
CMPR32X2TS U1049 ( .A(n772), .B(n771), .C(n770), .CO(
Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .S(n768) );
CMPR32X2TS U1050 ( .A(n776), .B(n775), .C(n774), .CO(n817), .S(n833) );
INVX2TS U1051 ( .A(n833), .Y(DP_OP_154J132_123_2038_n86) );
CMPR32X2TS U1052 ( .A(n778), .B(n777), .C(DP_OP_154J132_123_2038_n79), .CO(
n651), .S(DP_OP_156J132_125_3370_n131) );
AOI31X4TS U1053 ( .A0(n1613), .A1(FS_Module_state_reg[1]), .A2(
FSM_add_overflow_flag), .B0(n779), .Y(n1301) );
CMPR32X2TS U1054 ( .A(n781), .B(n780), .C(n984), .CO(n682), .S(n1654) );
CMPR32X2TS U1055 ( .A(n783), .B(n782), .C(n1541), .CO(n683), .S(n1658) );
CMPR32X2TS U1056 ( .A(n785), .B(n784), .C(n975), .CO(n686), .S(n1661) );
CMPR32X2TS U1057 ( .A(n787), .B(n786), .C(n1019), .CO(n784), .S(n1664) );
CMPR32X2TS U1058 ( .A(n790), .B(n789), .C(n788), .CO(n786), .S(n1185) );
CMPR32X2TS U1059 ( .A(DP_OP_154J132_123_2038_n326), .B(n792), .C(n791), .CO(
n789), .S(n1343) );
CMPR32X2TS U1060 ( .A(DP_OP_154J132_123_2038_n82), .B(n793), .C(n799), .CO(
n692), .S(n794) );
INVX2TS U1061 ( .A(n794), .Y(n1196) );
CMPR32X2TS U1062 ( .A(n973), .B(n795), .C(n801), .CO(n1026), .S(n1320) );
AO21XLTS U1063 ( .A0(n797), .A1(n796), .B0(DP_OP_156J132_125_3370_n81), .Y(
n848) );
INVX2TS U1064 ( .A(n798), .Y(n880) );
OA21X1TS U1065 ( .A0(n1035), .A1(n800), .B0(n799), .Y(n1203) );
AOI21X1TS U1066 ( .A0(DP_OP_155J132_124_2038_n83), .A1(n802), .B0(n801), .Y(
n1280) );
CMPR32X2TS U1067 ( .A(DP_OP_153J132_122_5442_n377), .B(n804), .C(n803), .CO(
n996), .S(n805) );
INVX2TS U1068 ( .A(n805), .Y(n941) );
INVX2TS U1069 ( .A(n806), .Y(n879) );
CMPR32X2TS U1070 ( .A(n1203), .B(n1280), .C(n941), .CO(n806), .S(n807) );
INVX2TS U1071 ( .A(n807), .Y(n876) );
CMPR32X2TS U1072 ( .A(DP_OP_154J132_123_2038_n238), .B(
DP_OP_154J132_123_2038_n232), .C(n808), .CO(n639), .S(n1174) );
CMPR32X2TS U1073 ( .A(DP_OP_155J132_124_2038_n238), .B(
DP_OP_155J132_124_2038_n232), .C(n809), .CO(n461), .S(n1305) );
CMPR32X2TS U1074 ( .A(n812), .B(n811), .C(n810), .CO(n804), .S(n1464) );
INVX2TS U1075 ( .A(n1464), .Y(n814) );
INVX2TS U1076 ( .A(n813), .Y(n875) );
CMPR32X2TS U1077 ( .A(n1174), .B(n1305), .C(n814), .CO(n813), .S(n815) );
INVX2TS U1078 ( .A(n815), .Y(n873) );
CMPR32X2TS U1079 ( .A(DP_OP_154J132_123_2038_n239), .B(n817), .C(n816), .CO(
n808), .S(n1209) );
CMPR32X2TS U1080 ( .A(DP_OP_155J132_124_2038_n239), .B(n819), .C(n818), .CO(
n809), .S(n1328) );
CMPR32X2TS U1081 ( .A(n822), .B(n821), .C(n820), .CO(n811), .S(n1311) );
INVX2TS U1082 ( .A(n1311), .Y(n824) );
INVX2TS U1083 ( .A(n823), .Y(n872) );
CMPR32X2TS U1084 ( .A(n1209), .B(n1328), .C(n824), .CO(n823), .S(n825) );
INVX2TS U1085 ( .A(n825), .Y(n869) );
CMPR32X2TS U1086 ( .A(n828), .B(n827), .C(n826), .CO(n819), .S(n1329) );
CMPR32X2TS U1087 ( .A(n830), .B(n829), .C(n835), .CO(n820), .S(n1502) );
INVX2TS U1088 ( .A(n1502), .Y(n832) );
INVX2TS U1089 ( .A(n831), .Y(n868) );
CMPR32X2TS U1090 ( .A(n833), .B(n1329), .C(n832), .CO(n831), .S(n834) );
INVX2TS U1091 ( .A(n834), .Y(n866) );
NOR2XLTS U1092 ( .A(n839), .B(n1105), .Y(n838) );
AOI21X1TS U1093 ( .A0(n1106), .A1(n839), .B0(n838), .Y(n844) );
NAND2X1TS U1094 ( .A(n399), .B(n840), .Y(n1047) );
NAND2X1TS U1095 ( .A(n841), .B(n1047), .Y(n843) );
INVX2TS U1096 ( .A(n845), .Y(n1677) );
NOR2X1TS U1097 ( .A(n1052), .B(n1677), .Y(n863) );
INVX2TS U1098 ( .A(n846), .Y(n862) );
OA21XLTS U1099 ( .A0(n1389), .A1(n1368), .B0(n1047), .Y(n855) );
AOI21X1TS U1100 ( .A0(n1052), .A1(n1677), .B0(n863), .Y(n854) );
INVX2TS U1101 ( .A(n847), .Y(n864) );
CMPR32X2TS U1102 ( .A(n1196), .B(n1320), .C(n848), .CO(n849), .S(n798) );
INVX2TS U1103 ( .A(n849), .Y(n882) );
CMPR32X2TS U1104 ( .A(DP_OP_156J132_125_3370_n68), .B(
DP_OP_156J132_125_3370_n66), .C(n850), .CO(n888), .S(n1391) );
CMPR32X2TS U1105 ( .A(DP_OP_156J132_125_3370_n77), .B(
DP_OP_156J132_125_3370_n75), .C(n851), .CO(n885), .S(n1290) );
CMPR32X2TS U1106 ( .A(n1582), .B(n853), .C(n852), .CO(n747), .S(n1012) );
CMPR32X2TS U1107 ( .A(n1335), .B(n855), .C(n854), .CO(n861), .S(n1315) );
NAND2X1TS U1108 ( .A(Op_MY[0]), .B(Op_MX[12]), .Y(n857) );
NAND2X1TS U1109 ( .A(Op_MX[0]), .B(Op_MY[12]), .Y(n856) );
XOR2X1TS U1110 ( .A(n857), .B(n856), .Y(n1684) );
CMPR32X2TS U1111 ( .A(n860), .B(n859), .C(n858), .CO(n755), .S(n1683) );
NAND2X1TS U1112 ( .A(n1684), .B(n1683), .Y(n1681) );
CMPR32X2TS U1113 ( .A(n863), .B(n862), .C(n861), .CO(n847), .S(n1348) );
NOR2X1TS U1114 ( .A(n1307), .B(DP_OP_156J132_125_3370_n103), .Y(n1306) );
CMPR32X2TS U1115 ( .A(n866), .B(n865), .C(n864), .CO(n867), .S(n1309) );
OAI2BB2X2TS U1116 ( .B0(n1306), .B1(n1309), .A0N(n1307), .A1N(
DP_OP_156J132_125_3370_n103), .Y(n1281) );
CMPR32X2TS U1117 ( .A(n869), .B(n868), .C(n867), .CO(n871), .S(n1284) );
INVX2TS U1118 ( .A(n1284), .Y(n870) );
CMPR32X2TS U1119 ( .A(n873), .B(n872), .C(n871), .CO(n874), .S(n1324) );
AOI222X1TS U1120 ( .A0(n1012), .A1(n1326), .B0(n1012), .B1(n1324), .C0(n1326), .C1(n1324), .Y(n1333) );
CMPR32X2TS U1121 ( .A(n876), .B(n875), .C(n874), .CO(n878), .S(n877) );
INVX2TS U1122 ( .A(n877), .Y(n1332) );
CMPR32X2TS U1123 ( .A(n880), .B(n879), .C(n878), .CO(n883), .S(n881) );
INVX2TS U1124 ( .A(n881), .Y(n1356) );
CMPR32X2TS U1125 ( .A(DP_OP_156J132_125_3370_n78), .B(n883), .C(n882), .CO(
n851), .S(n884) );
INVX2TS U1126 ( .A(n884), .Y(n1317) );
NAND2X1TS U1127 ( .A(n1288), .B(DP_OP_156J132_125_3370_n97), .Y(n1287) );
AOI2BB2XLTS U1128 ( .B0(n1290), .B1(n1287), .A0N(n1288), .A1N(
DP_OP_156J132_125_3370_n97), .Y(n1338) );
CMPR32X2TS U1129 ( .A(DP_OP_156J132_125_3370_n74), .B(
DP_OP_156J132_125_3370_n72), .C(n885), .CO(n887), .S(n886) );
INVX2TS U1130 ( .A(n886), .Y(n1337) );
CMPR32X2TS U1131 ( .A(DP_OP_156J132_125_3370_n71), .B(
DP_OP_156J132_125_3370_n69), .C(n887), .CO(n850), .S(n1275) );
NAND2X1TS U1132 ( .A(n1273), .B(DP_OP_156J132_125_3370_n95), .Y(n1272) );
AOI222X1TS U1133 ( .A0(n1389), .A1(n1391), .B0(n1389), .B1(n1388), .C0(n1391), .C1(n1388), .Y(n1676) );
CMPR32X2TS U1134 ( .A(DP_OP_156J132_125_3370_n65), .B(
DP_OP_156J132_125_3370_n63), .C(n888), .CO(n890), .S(n889) );
INVX2TS U1135 ( .A(n889), .Y(n1675) );
CMPR32X2TS U1136 ( .A(DP_OP_156J132_125_3370_n62), .B(
DP_OP_156J132_125_3370_n60), .C(n890), .CO(n892), .S(n891) );
INVX2TS U1137 ( .A(n891), .Y(n1190) );
NOR2X1TS U1138 ( .A(n1671), .B(DP_OP_154J132_123_2038_n86), .Y(n1670) );
CMPR32X2TS U1139 ( .A(DP_OP_156J132_125_3370_n59), .B(
DP_OP_156J132_125_3370_n57), .C(n892), .CO(n893), .S(n1673) );
CMPR32X2TS U1140 ( .A(DP_OP_156J132_125_3370_n56), .B(
DP_OP_156J132_125_3370_n54), .C(n893), .CO(n895), .S(n1211) );
OAI2BB1X1TS U1141 ( .A0N(n1208), .A1N(n1211), .B0(n894), .Y(n1173) );
CMPR32X2TS U1142 ( .A(DP_OP_156J132_125_3370_n53), .B(
DP_OP_156J132_125_3370_n51), .C(n895), .CO(n896), .S(n1172) );
CMPR32X2TS U1143 ( .A(DP_OP_156J132_125_3370_n50), .B(
DP_OP_156J132_125_3370_n48), .C(n896), .CO(n897), .S(n1205) );
OR2X1TS U1144 ( .A(n1202), .B(n1203), .Y(n1201) );
AO22X1TS U1145 ( .A0(n1202), .A1(n1203), .B0(n1205), .B1(n1201), .Y(n1197)
);
AOI222X1TS U1146 ( .A0(n1199), .A1(n1197), .B0(n1199), .B1(n1196), .C0(n1197), .C1(n1196), .Y(n1366) );
CMPR32X2TS U1147 ( .A(DP_OP_156J132_125_3370_n47), .B(
DP_OP_156J132_125_3370_n45), .C(n897), .CO(n899), .S(n1199) );
INVX2TS U1148 ( .A(n898), .Y(n1365) );
CMPR32X2TS U1149 ( .A(DP_OP_156J132_125_3370_n44), .B(
DP_OP_156J132_125_3370_n42), .C(n899), .CO(n901), .S(n898) );
INVX2TS U1150 ( .A(n900), .Y(n1667) );
NOR2X1TS U1151 ( .A(n1352), .B(DP_OP_156J132_125_3370_n131), .Y(n1351) );
CMPR32X2TS U1152 ( .A(DP_OP_156J132_125_3370_n41), .B(
DP_OP_156J132_125_3370_n39), .C(n901), .CO(n902), .S(n900) );
CMPR32X2TS U1153 ( .A(DP_OP_156J132_125_3370_n38), .B(
DP_OP_156J132_125_3370_n36), .C(n902), .CO(n912), .S(n1354) );
CMPR32X2TS U1154 ( .A(n1036), .B(n904), .C(n903), .CO(n792), .S(n1214) );
OAI21XLTS U1155 ( .A0(n1216), .A1(n1213), .B0(n1214), .Y(n905) );
OAI2BB1X1TS U1156 ( .A0N(n1213), .A1N(n1216), .B0(n905), .Y(n1342) );
INVX2TS U1157 ( .A(n1515), .Y(n1294) );
NOR2XLTS U1158 ( .A(n1445), .B(n1294), .Y(n1040) );
NAND2X1TS U1159 ( .A(n1509), .B(n952), .Y(n907) );
NAND2X1TS U1160 ( .A(n954), .B(n1513), .Y(n906) );
INVX2TS U1161 ( .A(n1509), .Y(n1054) );
INVX2TS U1162 ( .A(n952), .Y(n1297) );
INVX2TS U1163 ( .A(n1513), .Y(n1293) );
AOI21X1TS U1164 ( .A0(n907), .A1(n906), .B0(n1031), .Y(n1039) );
INVX2TS U1165 ( .A(n1516), .Y(n1296) );
NOR2XLTS U1166 ( .A(n1447), .B(n1296), .Y(n1032) );
INVX2TS U1167 ( .A(n1514), .Y(n1295) );
NOR2XLTS U1168 ( .A(n1445), .B(n1295), .Y(n1030) );
NAND2X1TS U1169 ( .A(n1509), .B(n1515), .Y(n909) );
NAND2X1TS U1170 ( .A(n952), .B(n1513), .Y(n908) );
AOI21X1TS U1171 ( .A0(n909), .A1(n908), .B0(n1451), .Y(n945) );
NOR2XLTS U1172 ( .A(n1148), .B(n1445), .Y(n1041) );
NOR2XLTS U1173 ( .A(n1448), .B(n1148), .Y(n911) );
NOR2XLTS U1174 ( .A(n1446), .B(n1448), .Y(n914) );
CMPR32X2TS U1175 ( .A(DP_OP_153J132_122_5442_n247), .B(n911), .C(n910), .CO(
n913), .S(n1044) );
XOR2X1TS U1176 ( .A(n1087), .B(DP_OP_156J132_125_3370_n31), .Y(n917) );
CMPR32X2TS U1177 ( .A(DP_OP_156J132_125_3370_n35), .B(
DP_OP_156J132_125_3370_n33), .C(n912), .CO(n916), .S(n1216) );
NAND2X1TS U1178 ( .A(n1087), .B(DP_OP_156J132_125_3370_n31), .Y(n920) );
CMPR32X2TS U1179 ( .A(n915), .B(n914), .C(n913), .CO(n964), .S(n1087) );
CMPR32X2TS U1180 ( .A(DP_OP_156J132_125_3370_n32), .B(n917), .C(n916), .CO(
n918), .S(n1341) );
XOR2XLTS U1181 ( .A(n964), .B(n918), .Y(n919) );
XOR2X1TS U1182 ( .A(n920), .B(n919), .Y(n1183) );
NAND3X1TS U1183 ( .A(n1661), .B(n1664), .C(n1663), .Y(n1660) );
NAND2X1TS U1184 ( .A(n1658), .B(n1657), .Y(n1656) );
NAND2X1TS U1185 ( .A(n1654), .B(n1653), .Y(n1652) );
INVX2TS U1186 ( .A(n1181), .Y(n921) );
CLKBUFX3TS U1187 ( .A(n1301), .Y(n1680) );
AOI21X1TS U1188 ( .A0(DP_OP_156J132_125_3370_n120), .A1(n921), .B0(n1680),
.Y(n922) );
NAND2BX1TS U1189 ( .AN(DP_OP_156J132_125_3370_n120), .B(n1181), .Y(n1278) );
AO22XLTS U1190 ( .A0(n1301), .A1(P_Sgf[45]), .B0(n922), .B1(n1278), .Y(n283)
);
CLKBUFX2TS U1191 ( .A(n923), .Y(n1777) );
OR2X1TS U1192 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
CLKBUFX2TS U1193 ( .A(n415), .Y(n924) );
CMPR32X2TS U1194 ( .A(n1270), .B(n1513), .C(n925), .CO(n680), .S(n926) );
INVX2TS U1195 ( .A(n926), .Y(n1473) );
NOR2X1TS U1196 ( .A(n1496), .B(n1473), .Y(DP_OP_153J132_122_5442_n157) );
CMPR32X2TS U1197 ( .A(Op_MX[2]), .B(Op_MX[8]), .C(n927), .CO(n929), .S(n930)
);
INVX2TS U1198 ( .A(n930), .Y(n1154) );
CMPR32X2TS U1199 ( .A(Op_MY[3]), .B(Op_MY[9]), .C(n928), .CO(n1010), .S(
n1416) );
INVX2TS U1200 ( .A(n1416), .Y(n1607) );
AOI22X1TS U1201 ( .A0(n1416), .A1(n1596), .B0(n409), .B1(n1607), .Y(n1594)
);
OAI33X4TS U1202 ( .A0(n931), .A1(n930), .A2(n442), .B0(
DP_OP_155J132_124_2038_n119), .B1(n1154), .B2(n410), .Y(n1593) );
CMPR32X2TS U1203 ( .A(Op_MY[2]), .B(Op_MY[8]), .C(n932), .CO(n928), .S(n1092) );
INVX2TS U1204 ( .A(n1092), .Y(n1608) );
AOI22X1TS U1205 ( .A0(n410), .A1(n1092), .B0(n1608), .B1(n409), .Y(n959) );
AOI22X1TS U1206 ( .A0(n972), .A1(n1594), .B0(n1593), .B1(n959), .Y(n1581) );
NOR2X1TS U1207 ( .A(n1581), .B(n1582), .Y(DP_OP_155J132_124_2038_n61) );
CMPR32X2TS U1208 ( .A(Op_MX[4]), .B(Op_MX[10]), .C(n933), .CO(n514), .S(n934) );
INVX2TS U1209 ( .A(n934), .Y(n1129) );
AOI22X2TS U1210 ( .A0(n410), .A1(n1129), .B0(n934), .B1(n409), .Y(n1588) );
OAI221X2TS U1211 ( .A0(n934), .A1(n419), .B0(n1129), .B1(n1584), .C0(n1588),
.Y(n1586) );
AOI22X1TS U1212 ( .A0(n978), .A1(n1584), .B0(n419), .B1(n1610), .Y(n1587) );
INVX2TS U1213 ( .A(n1588), .Y(n1456) );
AOI22X1TS U1214 ( .A0(n1092), .A1(n419), .B0(n1584), .B1(n1608), .Y(n1417)
);
INVX2TS U1215 ( .A(n937), .Y(n1497) );
NOR2X1TS U1216 ( .A(n1496), .B(n1497), .Y(DP_OP_153J132_122_5442_n154) );
CMPR32X2TS U1217 ( .A(n422), .B(n1514), .C(n938), .CO(n957), .S(n939) );
INVX2TS U1218 ( .A(n939), .Y(n1469) );
NAND3X1TS U1219 ( .A(n940), .B(n939), .C(n941), .Y(n1466) );
OA21XLTS U1220 ( .A0(n942), .A1(n941), .B0(n1466), .Y(
DP_OP_153J132_122_5442_n97) );
INVX2TS U1221 ( .A(n1049), .Y(n1073) );
NOR2X1TS U1222 ( .A(n1073), .B(n1496), .Y(DP_OP_153J132_122_5442_n159) );
INVX2TS U1223 ( .A(n1505), .Y(n1501) );
NOR2X1TS U1224 ( .A(n1502), .B(n1501), .Y(DP_OP_153J132_122_5442_n121) );
INVX2TS U1225 ( .A(n1048), .Y(n1145) );
NOR2X1TS U1226 ( .A(n1145), .B(n1495), .Y(DP_OP_153J132_122_5442_n201) );
CMPR32X2TS U1227 ( .A(n947), .B(n946), .C(n945), .CO(n1042), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
CMPR32X2TS U1228 ( .A(Op_MX[14]), .B(Op_MX[20]), .C(n948), .CO(n603), .S(
n949) );
INVX2TS U1229 ( .A(n949), .Y(n1159) );
OAI33X4TS U1230 ( .A0(n407), .A1(DP_OP_154J132_123_2038_n119), .A2(n1159),
.B0(n406), .B1(n950), .B2(n949), .Y(n1560) );
INVX2TS U1231 ( .A(n1560), .Y(n1567) );
INVX2TS U1232 ( .A(n1548), .Y(n1578) );
AOI22X1TS U1233 ( .A0(n407), .A1(n1578), .B0(n1548), .B1(n1564), .Y(n1568)
);
CMPR32X2TS U1234 ( .A(Op_MY[14]), .B(Op_MY[20]), .C(n951), .CO(n1028), .S(
n1546) );
INVX2TS U1235 ( .A(n1546), .Y(n1576) );
AOI22X1TS U1236 ( .A0(n407), .A1(n1546), .B0(n1576), .B1(n1564), .Y(n1164)
);
NAND2X1TS U1237 ( .A(n953), .B(n952), .Y(n956) );
NAND2X1TS U1238 ( .A(n954), .B(n1509), .Y(n955) );
AOI21X1TS U1239 ( .A0(n956), .A1(n955), .B0(n433), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]) );
NOR2X1TS U1240 ( .A(n1469), .B(n1495), .Y(DP_OP_153J132_122_5442_n177) );
OAI22X1TS U1241 ( .A0(n1269), .A1(n1521), .B0(n1520), .B1(n1523), .Y(
DP_OP_153J132_122_5442_n365) );
CMPR32X2TS U1242 ( .A(n1055), .B(n958), .C(n957), .CO(n960), .S(n998) );
INVX2TS U1243 ( .A(n998), .Y(n1479) );
NOR2X1TS U1244 ( .A(n1479), .B(n1495), .Y(DP_OP_153J132_122_5442_n169) );
INVX2TS U1245 ( .A(n1593), .Y(n1599) );
AOI22X1TS U1246 ( .A0(n410), .A1(n1610), .B0(n978), .B1(n409), .Y(n1600) );
INVX2TS U1247 ( .A(n961), .Y(n1459) );
NOR2X1TS U1248 ( .A(n1459), .B(n1495), .Y(DP_OP_153J132_122_5442_n161) );
NOR2X1TS U1249 ( .A(n1522), .B(n1523), .Y(DP_OP_153J132_122_5442_n394) );
NOR2X1TS U1250 ( .A(n1498), .B(n1495), .Y(DP_OP_153J132_122_5442_n145) );
BUFX3TS U1251 ( .A(n1777), .Y(n1770) );
CLKBUFX3TS U1252 ( .A(n167), .Y(n1782) );
BUFX3TS U1253 ( .A(n1777), .Y(n1765) );
BUFX3TS U1254 ( .A(n1777), .Y(n1763) );
BUFX3TS U1255 ( .A(n1777), .Y(n1766) );
CMPR32X2TS U1256 ( .A(DP_OP_153J132_122_5442_n256), .B(
DP_OP_153J132_122_5442_n252), .C(n962), .CO(n963), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
INVX2TS U1257 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(
DP_OP_153J132_122_5442_n228) );
CMPR32X2TS U1258 ( .A(DP_OP_153J132_122_5442_n251), .B(
DP_OP_153J132_122_5442_n249), .C(n963), .CO(n1045), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
INVX2TS U1259 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(
DP_OP_153J132_122_5442_n227) );
NOR2XLTS U1260 ( .A(n1145), .B(n1497), .Y(DP_OP_153J132_122_5442_n202) );
NOR2XLTS U1261 ( .A(n1292), .B(n1447), .Y(DP_OP_153J132_122_5442_n311) );
INVX2TS U1262 ( .A(n964), .Y(DP_OP_153J132_122_5442_n224) );
INVX2TS U1263 ( .A(n1577), .Y(n1580) );
NOR4X2TS U1264 ( .A(n397), .B(n1716), .C(n1700), .D(n1705), .Y(
DP_OP_154J132_123_2038_n331) );
NAND2X1TS U1265 ( .A(Op_MY[19]), .B(Op_MX[21]), .Y(n965) );
OAI32X1TS U1266 ( .A0(DP_OP_154J132_123_2038_n331), .A1(n1705), .A2(n408),
.B0(n965), .B1(DP_OP_154J132_123_2038_n331), .Y(
DP_OP_154J132_123_2038_n332) );
INVX2TS U1267 ( .A(DP_OP_155J132_124_2038_n63), .Y(n1008) );
INVX2TS U1268 ( .A(n966), .Y(n1408) );
NAND2X1TS U1269 ( .A(n1408), .B(DP_OP_155J132_124_2038_n73), .Y(n1407) );
INVX2TS U1270 ( .A(n967), .Y(DP_OP_155J132_124_2038_n60) );
AOI22X1TS U1271 ( .A0(n1160), .A1(n1578), .B0(n1161), .B1(n1576), .Y(n968)
);
OAI21XLTS U1272 ( .A0(n1576), .A1(n1163), .B0(n968), .Y(
DP_OP_154J132_123_2038_n125) );
NOR4X2TS U1273 ( .A(n417), .B(n1717), .C(n443), .D(n1696), .Y(
DP_OP_155J132_124_2038_n331) );
NAND2X1TS U1274 ( .A(Op_MY[7]), .B(Op_MX[9]), .Y(n969) );
OAI32X1TS U1275 ( .A0(DP_OP_155J132_124_2038_n331), .A1(n443), .A2(n396),
.B0(n969), .B1(DP_OP_155J132_124_2038_n331), .Y(
DP_OP_155J132_124_2038_n332) );
CMPR32X2TS U1276 ( .A(n970), .B(n1328), .C(n1407), .CO(n1007), .S(n971) );
INVX2TS U1277 ( .A(n971), .Y(DP_OP_155J132_124_2038_n67) );
INVX2TS U1278 ( .A(n1165), .Y(n1569) );
OAI32X1TS U1279 ( .A0(n1564), .A1(n1565), .A2(n1569), .B0(n1567), .B1(n1564),
.Y(DP_OP_154J132_123_2038_n91) );
INVX2TS U1280 ( .A(n972), .Y(n1601) );
INVX2TS U1281 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(
DP_OP_155J132_124_2038_n195) );
INVX2TS U1282 ( .A(n973), .Y(DP_OP_155J132_124_2038_n82) );
NOR4X2TS U1283 ( .A(n418), .B(n1690), .C(n1704), .D(n1697), .Y(
DP_OP_155J132_124_2038_n240) );
NAND2X1TS U1284 ( .A(Op_MY[1]), .B(Op_MX[3]), .Y(n974) );
OAI32X1TS U1285 ( .A0(DP_OP_155J132_124_2038_n240), .A1(n1704), .A2(n393),
.B0(n974), .B1(DP_OP_155J132_124_2038_n240), .Y(
DP_OP_155J132_124_2038_n241) );
INVX2TS U1286 ( .A(n975), .Y(n1424) );
NAND2X1TS U1287 ( .A(n1424), .B(DP_OP_154J132_123_2038_n73), .Y(n1423) );
INVX2TS U1288 ( .A(n976), .Y(DP_OP_154J132_123_2038_n67) );
AOI22X1TS U1289 ( .A0(n1092), .A1(n1151), .B0(n1150), .B1(n1608), .Y(n977)
);
OAI21XLTS U1290 ( .A0(n978), .A1(n1153), .B0(n977), .Y(
DP_OP_155J132_124_2038_n125) );
NOR2XLTS U1291 ( .A(n1612), .B(n1601), .Y(DP_OP_155J132_124_2038_n118) );
AOI22X1TS U1292 ( .A0(FSM_selector_C), .A1(Add_result[23]), .B0(P_Sgf[46]),
.B1(n398), .Y(n1177) );
AOI22X1TS U1293 ( .A0(Sgf_normalized_result[22]), .A1(n1176), .B0(
Add_result[22]), .B1(n431), .Y(n981) );
NAND2X1TS U1294 ( .A(P_Sgf[45]), .B(n441), .Y(n980) );
OAI211XLTS U1295 ( .A0(n1178), .A1(n1177), .B0(n981), .C0(n980), .Y(n224) );
INVX2TS U1296 ( .A(n1654), .Y(DP_OP_156J132_125_3370_n122) );
NOR2X1TS U1297 ( .A(FS_Module_state_reg[2]), .B(n1714), .Y(n1494) );
NAND3X2TS U1298 ( .A(n1494), .B(n1755), .C(FS_Module_state_reg[0]), .Y(n1265) );
INVX2TS U1299 ( .A(n1265), .Y(n1286) );
INVX2TS U1300 ( .A(n1003), .Y(n1398) );
NAND2X1TS U1301 ( .A(n1492), .B(n982), .Y(n1229) );
NOR2BX1TS U1302 ( .AN(P_Sgf[47]), .B(n1229), .Y(n1004) );
INVX2TS U1303 ( .A(n1004), .Y(n983) );
OAI31X1TS U1304 ( .A0(n1286), .A1(n1398), .A2(n1715), .B0(n983), .Y(n235) );
INVX2TS U1305 ( .A(n1658), .Y(DP_OP_156J132_125_3370_n124) );
INVX2TS U1306 ( .A(n1661), .Y(DP_OP_156J132_125_3370_n126) );
INVX2TS U1307 ( .A(n1664), .Y(DP_OP_156J132_125_3370_n127) );
INVX2TS U1308 ( .A(n1185), .Y(DP_OP_156J132_125_3370_n128) );
INVX2TS U1309 ( .A(n1343), .Y(DP_OP_156J132_125_3370_n129) );
INVX2TS U1310 ( .A(n1214), .Y(DP_OP_156J132_125_3370_n130) );
INVX2TS U1311 ( .A(Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(
DP_OP_154J132_123_2038_n195) );
INVX2TS U1312 ( .A(n984), .Y(DP_OP_154J132_123_2038_n196) );
INVX2TS U1313 ( .A(DP_OP_153J132_122_5442_n365), .Y(
DP_OP_153J132_122_5442_n366) );
OAI21XLTS U1314 ( .A0(DP_OP_153J132_122_5442_n412), .A1(n985), .B0(n1530),
.Y(DP_OP_153J132_122_5442_n403) );
NOR3X1TS U1315 ( .A(n1451), .B(n1293), .C(n1294), .Y(
DP_OP_153J132_122_5442_n273) );
INVX2TS U1316 ( .A(n986), .Y(DP_OP_154J132_123_2038_n197) );
NOR2XLTS U1317 ( .A(n1448), .B(n1294), .Y(n988) );
NOR2XLTS U1318 ( .A(n1446), .B(n1293), .Y(n987) );
CMPR32X2TS U1319 ( .A(n1510), .B(n988), .C(n987), .CO(
DP_OP_153J132_122_5442_n253), .S(DP_OP_153J132_122_5442_n254) );
NAND2X1TS U1320 ( .A(n1503), .B(n1048), .Y(n1051) );
NAND2X1TS U1321 ( .A(n1504), .B(n1049), .Y(n1050) );
INVX2TS U1322 ( .A(n989), .Y(DP_OP_153J132_122_5442_n128) );
NOR2XLTS U1323 ( .A(n1579), .B(n1569), .Y(DP_OP_154J132_123_2038_n118) );
CMPR32X2TS U1324 ( .A(n991), .B(n1515), .C(n990), .CO(n938), .S(n992) );
NOR2XLTS U1325 ( .A(n1475), .B(n1480), .Y(DP_OP_153J132_122_5442_n187) );
CMPR32X2TS U1326 ( .A(DP_OP_153J132_122_5442_n263), .B(
DP_OP_153J132_122_5442_n257), .C(n993), .CO(n962), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
INVX2TS U1327 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .Y(
DP_OP_153J132_122_5442_n229) );
NOR2XLTS U1328 ( .A(n1073), .B(n1498), .Y(DP_OP_153J132_122_5442_n151) );
INVX2TS U1329 ( .A(n1016), .Y(DP_OP_155J132_124_2038_n79) );
NOR2XLTS U1330 ( .A(n1469), .B(n1460), .Y(DP_OP_153J132_122_5442_n176) );
INVX2TS U1331 ( .A(n1689), .Y(n1179) );
CLKBUFX3TS U1332 ( .A(n1179), .Y(n1400) );
XOR2X1TS U1333 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n1488) );
NOR2XLTS U1334 ( .A(n1488), .B(underflow_flag), .Y(n995) );
OAI32X1TS U1335 ( .A0(n1400), .A1(n995), .A2(overflow_flag), .B0(n1689),
.B1(n1758), .Y(n168) );
CMPR32X2TS U1336 ( .A(DP_OP_153J132_122_5442_n376), .B(
DP_OP_153J132_122_5442_n374), .C(n996), .CO(n1146), .S(n1467) );
INVX2TS U1337 ( .A(n1539), .Y(n1525) );
AOI22X1TS U1338 ( .A0(n1426), .A1(n1539), .B0(n1525), .B1(n391), .Y(n1437)
);
AOI22X1TS U1339 ( .A0(n426), .A1(n1444), .B0(n1442), .B1(n1437), .Y(n1061)
);
INVX2TS U1340 ( .A(n1527), .Y(n1526) );
INVX2TS U1341 ( .A(n1531), .Y(n1529) );
OAI22X1TS U1342 ( .A0(n1526), .A1(n1523), .B0(n1529), .B1(n1521), .Y(n1057)
);
INVX2TS U1343 ( .A(n1498), .Y(n1071) );
NAND2X1TS U1344 ( .A(n1071), .B(n997), .Y(n1038) );
INVX2TS U1345 ( .A(n1460), .Y(n1070) );
NAND2X1TS U1346 ( .A(n998), .B(n1070), .Y(n1037) );
INVX2TS U1347 ( .A(n999), .Y(DP_OP_153J132_122_5442_n40) );
NAND2X1TS U1348 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n1491) );
NOR3X1TS U1349 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n1491), .Y(ready) );
AOI22X1TS U1350 ( .A0(DP_OP_36J132_126_4699_n33), .A1(n1738), .B0(n1701),
.B1(n1760), .Y(n1001) );
INVX2TS U1351 ( .A(ready), .Y(n1000) );
OAI22X1TS U1352 ( .A0(n1001), .A1(n1228), .B0(P_Sgf[47]), .B1(n1229), .Y(
n379) );
INVX2TS U1353 ( .A(Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]),
.Y(DP_OP_155J132_124_2038_n192) );
INVX2TS U1354 ( .A(n1002), .Y(DP_OP_155J132_124_2038_n197) );
INVX2TS U1355 ( .A(n1015), .Y(DP_OP_155J132_124_2038_n78) );
CLKBUFX3TS U1356 ( .A(n1003), .Y(n1340) );
OAI211XLTS U1357 ( .A0(n1004), .A1(n1759), .B0(n1340), .C0(n1265), .Y(n236)
);
OAI21XLTS U1358 ( .A0(n1701), .A1(n1228), .B0(FS_Module_state_reg[3]), .Y(
n1005) );
OAI211XLTS U1359 ( .A0(n1738), .A1(n1370), .B0(n1176), .C0(n1005), .Y(n380)
);
NOR2X1TS U1360 ( .A(n1728), .B(n1711), .Y(DP_OP_155J132_124_2038_n365) );
INVX2TS U1361 ( .A(n1006), .Y(DP_OP_155J132_124_2038_n201) );
NOR2X1TS U1362 ( .A(n1727), .B(n1710), .Y(DP_OP_155J132_124_2038_n274) );
NOR2X1TS U1363 ( .A(n1722), .B(n443), .Y(DP_OP_155J132_124_2038_n346) );
INVX2TS U1364 ( .A(n1022), .Y(DP_OP_155J132_124_2038_n80) );
NOR2X1TS U1365 ( .A(n1723), .B(n1704), .Y(DP_OP_155J132_124_2038_n255) );
CMPR32X2TS U1366 ( .A(n1008), .B(n1305), .C(n1007), .CO(n1009), .S(n967) );
INVX2TS U1367 ( .A(n1009), .Y(DP_OP_155J132_124_2038_n59) );
CMPR32X2TS U1368 ( .A(Op_MY[4]), .B(Op_MY[10]), .C(n1010), .CO(n1023), .S(
n1591) );
INVX2TS U1369 ( .A(n1591), .Y(n1606) );
AOI22X1TS U1370 ( .A0(n1591), .A1(n1151), .B0(n1150), .B1(n1606), .Y(n1011)
);
OAI21X1TS U1371 ( .A0(n1416), .A1(n1153), .B0(n1011), .Y(
DP_OP_155J132_124_2038_n123) );
INVX2TS U1372 ( .A(n1012), .Y(DP_OP_156J132_125_3370_n101) );
NOR2X1TS U1373 ( .A(n1730), .B(n1705), .Y(DP_OP_154J132_123_2038_n345) );
NOR2X1TS U1374 ( .A(n1712), .B(n1729), .Y(DP_OP_154J132_123_2038_n274) );
NOR2X1TS U1375 ( .A(n1720), .B(n1709), .Y(DP_OP_154J132_123_2038_n364) );
INVX2TS U1376 ( .A(n1683), .Y(DP_OP_156J132_125_3370_n106) );
CMPR32X2TS U1377 ( .A(n1015), .B(n1014), .C(n1013), .CO(n859), .S(n1330) );
INVX2TS U1378 ( .A(n1330), .Y(DP_OP_156J132_125_3370_n107) );
NOR2X1TS U1379 ( .A(n1725), .B(n1702), .Y(DP_OP_154J132_123_2038_n255) );
CMPR32X2TS U1380 ( .A(n1018), .B(n1017), .C(n1016), .CO(n1014), .S(n1304) );
INVX2TS U1381 ( .A(n1304), .Y(DP_OP_156J132_125_3370_n108) );
INVX2TS U1382 ( .A(n1019), .Y(DP_OP_154J132_123_2038_n201) );
CMPR32X2TS U1383 ( .A(n1022), .B(n1021), .C(n1020), .CO(n1018), .S(n1312) );
INVX2TS U1384 ( .A(n1312), .Y(DP_OP_156J132_125_3370_n109) );
INVX2TS U1385 ( .A(n1586), .Y(n1454) );
AOI22X1TS U1386 ( .A0(n1583), .A1(n1603), .B0(n1605), .B1(n1584), .Y(n1455)
);
AOI22X1TS U1387 ( .A0(n1456), .A1(n419), .B0(n1454), .B1(n1455), .Y(n1156)
);
CMPR32X2TS U1388 ( .A(Op_MY[11]), .B(Op_MY[5]), .C(n1023), .CO(n1603), .S(
n1589) );
INVX2TS U1389 ( .A(n1589), .Y(n1604) );
OA22X1TS U1390 ( .A0(n1604), .A1(n1609), .B0(n1606), .B1(n1611), .Y(n1155)
);
INVX2TS U1391 ( .A(n1024), .Y(DP_OP_155J132_124_2038_n24) );
CMPR32X2TS U1392 ( .A(n1113), .B(n1026), .C(n1025), .CO(n1021), .S(n1347) );
INVX2TS U1393 ( .A(n1347), .Y(DP_OP_156J132_125_3370_n110) );
NOR2X1TS U1394 ( .A(n1073), .B(n1475), .Y(DP_OP_153J132_122_5442_n191) );
NOR2X1TS U1395 ( .A(n1148), .B(n1054), .Y(DP_OP_153J132_122_5442_n290) );
CMPR32X2TS U1396 ( .A(Op_MY[16]), .B(Op_MY[22]), .C(n1027), .CO(n1133), .S(
n1558) );
INVX2TS U1397 ( .A(n1558), .Y(n1574) );
CMPR32X2TS U1398 ( .A(Op_MY[15]), .B(Op_MY[21]), .C(n1028), .CO(n1027), .S(
n1544) );
INVX2TS U1399 ( .A(n1544), .Y(n1575) );
AOI22X1TS U1400 ( .A0(n1161), .A1(n1574), .B0(n1160), .B1(n1575), .Y(n1029)
);
OAI21X1TS U1401 ( .A0(n1574), .A1(n1163), .B0(n1029), .Y(
DP_OP_154J132_123_2038_n123) );
NOR2X1TS U1402 ( .A(n1073), .B(n1459), .Y(DP_OP_153J132_122_5442_n167) );
NOR2X1TS U1403 ( .A(n1498), .B(n1468), .Y(DP_OP_153J132_122_5442_n148) );
NOR2X1TS U1404 ( .A(n1476), .B(n1479), .Y(DP_OP_153J132_122_5442_n174) );
INVX2TS U1405 ( .A(DP_OP_154J132_123_2038_n63), .Y(n1140) );
CMPR32X2TS U1406 ( .A(n1209), .B(n1033), .C(n1423), .CO(n1139), .S(n976) );
INVX2TS U1407 ( .A(n1034), .Y(DP_OP_154J132_123_2038_n60) );
NOR2X1TS U1408 ( .A(n1145), .B(n1480), .Y(DP_OP_153J132_122_5442_n203) );
INVX2TS U1409 ( .A(n1035), .Y(DP_OP_154J132_123_2038_n83) );
INVX2TS U1410 ( .A(n1036), .Y(DP_OP_154J132_123_2038_n78) );
NOR2X1TS U1411 ( .A(n1475), .B(n1497), .Y(DP_OP_153J132_122_5442_n186) );
NOR2X1TS U1412 ( .A(n1474), .B(n1460), .Y(DP_OP_153J132_122_5442_n192) );
CMPR32X2TS U1413 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]),
.B(n1038), .C(n1037), .CO(n1500), .S(n999) );
NOR3X1TS U1414 ( .A(n1500), .B(n1497), .C(n1498), .Y(
DP_OP_153J132_122_5442_n29) );
NOR2X1TS U1415 ( .A(n1474), .B(n1468), .Y(DP_OP_153J132_122_5442_n196) );
NOR2X1TS U1416 ( .A(n1479), .B(n1473), .Y(DP_OP_153J132_122_5442_n173) );
NOR2X1TS U1417 ( .A(n1474), .B(n1497), .Y(DP_OP_153J132_122_5442_n194) );
NOR2X1TS U1418 ( .A(n1476), .B(n1469), .Y(DP_OP_153J132_122_5442_n182) );
INVX2TS U1419 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .Y(
DP_OP_153J132_122_5442_n234) );
NOR2X1TS U1420 ( .A(n1447), .B(n1445), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]) );
CMPR32X2TS U1421 ( .A(n1040), .B(n1039), .C(n433), .CO(n947), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
CMPR32X2TS U1422 ( .A(DP_OP_153J132_122_5442_n271), .B(n1042), .C(n1041),
.CO(n1043), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
CMPR32X2TS U1423 ( .A(DP_OP_153J132_122_5442_n270), .B(
DP_OP_153J132_122_5442_n264), .C(n1043), .CO(n993), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
CMPR32X2TS U1424 ( .A(DP_OP_153J132_122_5442_n248), .B(n1045), .C(n1044),
.CO(n915), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
INVX2TS U1425 ( .A(DP_OP_153J132_122_5442_n23), .Y(n1069) );
INVX2TS U1426 ( .A(DP_OP_153J132_122_5442_n27), .Y(n1068) );
INVX2TS U1427 ( .A(DP_OP_153J132_122_5442_n28), .Y(n1098) );
INVX2TS U1428 ( .A(DP_OP_153J132_122_5442_n34), .Y(n1097) );
INVX2TS U1429 ( .A(DP_OP_153J132_122_5442_n42), .Y(n1076) );
INVX2TS U1430 ( .A(DP_OP_153J132_122_5442_n35), .Y(n1075) );
INVX2TS U1431 ( .A(DP_OP_153J132_122_5442_n43), .Y(n1088) );
INVX2TS U1432 ( .A(DP_OP_153J132_122_5442_n52), .Y(n1094) );
INVX2TS U1433 ( .A(DP_OP_153J132_122_5442_n75), .Y(n1102) );
INVX2TS U1434 ( .A(DP_OP_153J132_122_5442_n63), .Y(n1101) );
INVX2TS U1435 ( .A(DP_OP_153J132_122_5442_n88), .Y(n1116) );
INVX2TS U1436 ( .A(DP_OP_153J132_122_5442_n76), .Y(n1115) );
INVX2TS U1437 ( .A(DP_OP_153J132_122_5442_n89), .Y(n1124) );
INVX2TS U1438 ( .A(DP_OP_153J132_122_5442_n99), .Y(n1123) );
INVX2TS U1439 ( .A(DP_OP_153J132_122_5442_n100), .Y(n1131) );
INVX2TS U1440 ( .A(DP_OP_153J132_122_5442_n110), .Y(n1111) );
INVX2TS U1441 ( .A(DP_OP_153J132_122_5442_n118), .Y(n1143) );
INVX2TS U1442 ( .A(DP_OP_153J132_122_5442_n125), .Y(n1127) );
INVX2TS U1443 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(
n1046) );
AOI22X1TS U1444 ( .A0(n1049), .A1(n1048), .B0(n1047), .B1(n1046), .Y(n1136)
);
INVX2TS U1445 ( .A(n1053), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
NOR2X1TS U1446 ( .A(n1692), .B(n1708), .Y(DP_OP_155J132_124_2038_n360) );
NOR2X1TS U1447 ( .A(n1459), .B(n1497), .Y(DP_OP_153J132_122_5442_n162) );
NOR4X2TS U1448 ( .A(n1692), .B(n1717), .C(n443), .D(n1703), .Y(
DP_OP_155J132_124_2038_n319) );
NOR2X1TS U1449 ( .A(n1295), .B(n1054), .Y(DP_OP_153J132_122_5442_n296) );
NOR2X1TS U1450 ( .A(n1073), .B(n1469), .Y(DP_OP_153J132_122_5442_n183) );
NOR2X1TS U1451 ( .A(n1145), .B(n1473), .Y(DP_OP_153J132_122_5442_n205) );
NOR2X1TS U1452 ( .A(n1727), .B(n1695), .Y(DP_OP_155J132_124_2038_n250) );
NOR2X1TS U1453 ( .A(n1728), .B(n1703), .Y(DP_OP_155J132_124_2038_n341) );
OA22X1TS U1454 ( .A0(n1526), .A1(n1521), .B0(n1525), .B1(n1523), .Y(n1062)
);
AOI21X1TS U1455 ( .A0(n422), .A1(n1055), .B0(n391), .Y(n1060) );
INVX2TS U1456 ( .A(n1056), .Y(n1121) );
CMPR32X2TS U1457 ( .A(DP_OP_153J132_122_5442_n359), .B(n1061), .C(n1057),
.CO(n1120), .S(n1058) );
CMPR32X2TS U1458 ( .A(DP_OP_153J132_122_5442_n360), .B(n1059), .C(n1058),
.CO(n1119), .S(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11])
);
CMPR32X2TS U1459 ( .A(n1062), .B(n1061), .C(n1060), .CO(n1064), .S(n1056) );
OAI21XLTS U1460 ( .A0(n1525), .A1(n1521), .B0(n1064), .Y(n1063) );
OAI31X1TS U1461 ( .A0(n1525), .A1(n1064), .A2(n1521), .B0(n1063), .Y(n1065)
);
CLKXOR2X2TS U1462 ( .A(n1066), .B(n1065), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]) );
INVX2TS U1463 ( .A(DP_OP_153J132_122_5442_n22), .Y(n1080) );
CMPR32X2TS U1464 ( .A(n1069), .B(n1068), .C(n1067), .CO(n1079), .S(n1053) );
INVX2TS U1465 ( .A(DP_OP_153J132_122_5442_n21), .Y(n1083) );
OAI21X1TS U1466 ( .A0(n1496), .A1(n1460), .B0(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .Y(n1384) );
INVX2TS U1467 ( .A(n1384), .Y(n1082) );
NAND2X1TS U1468 ( .A(n1071), .B(n1070), .Y(n1081) );
INVX2TS U1469 ( .A(n1072), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]) );
NOR2X1TS U1470 ( .A(n1073), .B(n1479), .Y(DP_OP_153J132_122_5442_n175) );
CMPR32X2TS U1471 ( .A(n1076), .B(n1075), .C(n1074), .CO(n1096), .S(n1077) );
INVX2TS U1472 ( .A(n1077), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
NOR2X1TS U1473 ( .A(n1148), .B(n1296), .Y(DP_OP_153J132_122_5442_n288) );
CMPR32X2TS U1474 ( .A(n1080), .B(n1079), .C(n1078), .CO(n1085), .S(n1072) );
CMPR32X2TS U1475 ( .A(n1083), .B(n1082), .C(n1081), .CO(n1084), .S(n1078) );
NAND2X1TS U1476 ( .A(n1085), .B(n1084), .Y(n1104) );
OAI21X1TS U1477 ( .A0(n1085), .A1(n1084), .B0(n1104), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]) );
CMPR32X2TS U1478 ( .A(n1088), .B(n1087), .C(n1086), .CO(n1074), .S(n1089) );
INVX2TS U1479 ( .A(n1089), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
NOR2X1TS U1480 ( .A(n1292), .B(n1297), .Y(DP_OP_153J132_122_5442_n305) );
CMPR32X2TS U1481 ( .A(DP_OP_153J132_122_5442_n368), .B(
DP_OP_153J132_122_5442_n364), .C(n1090), .CO(n1147), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]) );
NOR2X1TS U1482 ( .A(n1474), .B(n1480), .Y(DP_OP_153J132_122_5442_n195) );
NOR2X1TS U1483 ( .A(n1719), .B(n1707), .Y(DP_OP_155J132_124_2038_n269) );
NOR2X1TS U1484 ( .A(n1612), .B(n1588), .Y(DP_OP_155J132_124_2038_n109) );
AOI22X1TS U1485 ( .A0(n1416), .A1(n1151), .B0(n1150), .B1(n1607), .Y(n1091)
);
OAI21X1TS U1486 ( .A0(n1092), .A1(n1153), .B0(n1091), .Y(
DP_OP_155J132_124_2038_n124) );
CMPR32X2TS U1487 ( .A(n1094), .B(n1093), .C(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .CO(n1086), .S(
n1095) );
INVX2TS U1488 ( .A(n1095), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
NOR2X1TS U1489 ( .A(n1498), .B(n1473), .Y(DP_OP_153J132_122_5442_n149) );
CMPR32X2TS U1490 ( .A(n1098), .B(n1097), .C(n1096), .CO(n1067), .S(n1099) );
INVX2TS U1491 ( .A(n1099), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
NOR4X2TS U1492 ( .A(n1690), .B(n1719), .C(n1704), .D(n1695), .Y(
DP_OP_155J132_124_2038_n228) );
CMPR32X2TS U1493 ( .A(n1102), .B(n1101), .C(n1100), .CO(n1093), .S(n1103) );
INVX2TS U1494 ( .A(n1103), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
INVX2TS U1495 ( .A(n1104), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]) );
AOI2BB2XLTS U1496 ( .B0(n1539), .B1(n1106), .A0N(n1105), .A1N(n1539), .Y(
n1107) );
OAI21X1TS U1497 ( .A0(n1527), .A1(n1108), .B0(n1107), .Y(
DP_OP_153J132_122_5442_n414) );
INVX2TS U1498 ( .A(n1109), .Y(DP_OP_155J132_124_2038_n196) );
CMPR32X2TS U1499 ( .A(n1111), .B(n1110), .C(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .CO(n1130), .S(
n1112) );
INVX2TS U1500 ( .A(n1112), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]) );
NOR2X1TS U1501 ( .A(n1579), .B(n1554), .Y(DP_OP_154J132_123_2038_n109) );
INVX2TS U1502 ( .A(n1113), .Y(DP_OP_155J132_124_2038_n81) );
CMPR32X2TS U1503 ( .A(n1116), .B(n1115), .C(n1114), .CO(n1100), .S(n1117) );
INVX2TS U1504 ( .A(n1117), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
OAI21X1TS U1505 ( .A0(n1118), .A1(n406), .B0(n1550), .Y(
DP_OP_154J132_123_2038_n101) );
NOR2X1TS U1506 ( .A(n1731), .B(n1713), .Y(DP_OP_154J132_123_2038_n359) );
CMPR32X2TS U1507 ( .A(n1121), .B(n1120), .C(n1119), .CO(n1066), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]) );
OAI21X1TS U1508 ( .A0(n1459), .A1(n1460), .B0(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(
DP_OP_153J132_122_5442_n31) );
CMPR32X2TS U1509 ( .A(n1124), .B(n1123), .C(n1122), .CO(n1114), .S(n1125) );
INVX2TS U1510 ( .A(n1125), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
CMPR32X2TS U1511 ( .A(n1127), .B(n1126), .C(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .CO(n1142), .S(
n1128) );
INVX2TS U1512 ( .A(n1128), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]) );
OAI21X1TS U1513 ( .A0(n409), .A1(n1129), .B0(n419), .Y(
DP_OP_155J132_124_2038_n101) );
NOR2X1TS U1514 ( .A(n1475), .B(n1495), .Y(DP_OP_153J132_122_5442_n185) );
NOR4X2TS U1515 ( .A(n1691), .B(n1718), .C(n1702), .D(n1694), .Y(
DP_OP_154J132_123_2038_n228) );
NOR2X1TS U1516 ( .A(n1476), .B(n1459), .Y(DP_OP_153J132_122_5442_n166) );
CMPR32X2TS U1517 ( .A(n1131), .B(n1130), .C(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .CO(n1122), .S(
n1132) );
INVX2TS U1518 ( .A(n1132), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]) );
NOR2X1TS U1519 ( .A(n1729), .B(n1694), .Y(DP_OP_154J132_123_2038_n250) );
NOR2X1TS U1520 ( .A(n1459), .B(n1473), .Y(DP_OP_153J132_122_5442_n165) );
AOI21X4TS U1521 ( .A0(n1133), .A1(Op_MY[17]), .B0(n1572), .Y(n1573) );
AOI22X1TS U1522 ( .A0(n1573), .A1(n1161), .B0(n1160), .B1(n1574), .Y(n1134)
);
OAI21X1TS U1523 ( .A0(n1573), .A1(n1163), .B0(n1134), .Y(
DP_OP_154J132_123_2038_n122) );
CMPR32X2TS U1524 ( .A(DP_OP_153J132_122_5442_n234), .B(n1136), .C(n1135),
.CO(n1126), .S(n1137) );
INVX2TS U1525 ( .A(n1137), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]) );
AOI22X1TS U1526 ( .A0(n1160), .A1(n1576), .B0(n1161), .B1(n1575), .Y(n1138)
);
OAI21X1TS U1527 ( .A0(n1575), .A1(n1163), .B0(n1138), .Y(
DP_OP_154J132_123_2038_n124) );
CMPR32X2TS U1528 ( .A(n1140), .B(n1174), .C(n1139), .CO(n1141), .S(n1034) );
INVX2TS U1529 ( .A(n1141), .Y(DP_OP_154J132_123_2038_n59) );
CMPR32X2TS U1530 ( .A(n1143), .B(n1142), .C(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .CO(n1110), .S(
n1144) );
INVX2TS U1531 ( .A(n1144), .Y(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]) );
NOR2X1TS U1532 ( .A(n1718), .B(n1706), .Y(DP_OP_154J132_123_2038_n269) );
NOR4X2TS U1533 ( .A(n424), .B(n1691), .C(n1698), .D(n1702), .Y(
DP_OP_154J132_123_2038_n240) );
NOR3X2TS U1534 ( .A(n1464), .B(n1468), .C(n1475), .Y(
DP_OP_153J132_122_5442_n106) );
NOR2X1TS U1535 ( .A(n1145), .B(n1460), .Y(DP_OP_153J132_122_5442_n200) );
NOR2X1TS U1536 ( .A(n1145), .B(n1468), .Y(DP_OP_153J132_122_5442_n204) );
CMPR32X2TS U1537 ( .A(DP_OP_153J132_122_5442_n373), .B(
DP_OP_153J132_122_5442_n369), .C(n1146), .CO(n1090), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
NOR3X2TS U1538 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]),
.B(n1480), .C(n1479), .Y(DP_OP_153J132_122_5442_n72) );
NOR2X1TS U1539 ( .A(n1722), .B(n1711), .Y(DP_OP_155J132_124_2038_n364) );
NOR2X1TS U1540 ( .A(n1448), .B(n1295), .Y(DP_OP_153J132_122_5442_n292) );
NOR2X1TS U1541 ( .A(n1722), .B(n1696), .Y(DP_OP_155J132_124_2038_n352) );
NOR2X1TS U1542 ( .A(n1292), .B(n1295), .Y(DP_OP_153J132_122_5442_n293) );
CMPR32X2TS U1543 ( .A(DP_OP_153J132_122_5442_n363), .B(
DP_OP_153J132_122_5442_n361), .C(n1147), .CO(n1059), .S(
Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]) );
INVX2TS U1544 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]),
.Y(DP_OP_153J132_122_5442_n133) );
NOR2X1TS U1545 ( .A(n394), .B(n1723), .Y(DP_OP_155J132_124_2038_n279) );
NOR2X1TS U1546 ( .A(n1723), .B(n1710), .Y(DP_OP_155J132_124_2038_n273) );
NOR2X1TS U1547 ( .A(n1723), .B(n1697), .Y(DP_OP_155J132_124_2038_n261) );
NOR2X1TS U1548 ( .A(n1724), .B(n1697), .Y(DP_OP_155J132_124_2038_n260) );
NOR2X1TS U1549 ( .A(n1296), .B(n1297), .Y(DP_OP_153J132_122_5442_n306) );
INVX2TS U1550 ( .A(n1329), .Y(DP_OP_155J132_124_2038_n86) );
AOI22X1TS U1551 ( .A0(n1589), .A1(n1151), .B0(n1150), .B1(n1604), .Y(n1149)
);
OAI21X1TS U1552 ( .A0(n1591), .A1(n1153), .B0(n1149), .Y(
DP_OP_155J132_124_2038_n122) );
AOI22X1TS U1553 ( .A0(n1603), .A1(n1151), .B0(n1150), .B1(n1605), .Y(n1152)
);
OAI21X1TS U1554 ( .A0(n1589), .A1(n1153), .B0(n1152), .Y(
DP_OP_155J132_124_2038_n121) );
OAI21X1TS U1555 ( .A0(DP_OP_155J132_124_2038_n119), .A1(n1154), .B0(n1596),
.Y(DP_OP_155J132_124_2038_n110) );
INVX2TS U1556 ( .A(DP_OP_154J132_123_2038_n192), .Y(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]) );
CMPR32X2TS U1557 ( .A(n1157), .B(n1156), .C(n1155), .CO(n1024), .S(n1158) );
INVX2TS U1558 ( .A(n1158), .Y(DP_OP_155J132_124_2038_n25) );
OAI21X1TS U1559 ( .A0(DP_OP_154J132_123_2038_n119), .A1(n1159), .B0(n1563),
.Y(DP_OP_154J132_123_2038_n110) );
NOR2X1TS U1560 ( .A(n1720), .B(n1713), .Y(DP_OP_154J132_123_2038_n358) );
NOR2X1TS U1561 ( .A(n1730), .B(n1700), .Y(DP_OP_154J132_123_2038_n351) );
NOR2X1TS U1562 ( .A(n405), .B(n1725), .Y(DP_OP_154J132_123_2038_n279) );
NOR2X1TS U1563 ( .A(n1712), .B(n1725), .Y(DP_OP_154J132_123_2038_n273) );
NOR2X1TS U1564 ( .A(n1725), .B(n1698), .Y(DP_OP_154J132_123_2038_n261) );
AOI22X1TS U1565 ( .A0(n1572), .A1(n1161), .B0(n1573), .B1(n1160), .Y(n1162)
);
OAI21X1TS U1566 ( .A0(n1572), .A1(n1163), .B0(n1162), .Y(
DP_OP_154J132_123_2038_n121) );
NOR2X1TS U1567 ( .A(n1726), .B(n1698), .Y(DP_OP_154J132_123_2038_n260) );
AOI22X1TS U1568 ( .A0(n407), .A1(n1544), .B0(n1575), .B1(n406), .Y(n1561) );
AOI22X1TS U1569 ( .A0(n1165), .A1(n1561), .B0(n1560), .B1(n1164), .Y(n1540)
);
NOR2X1TS U1570 ( .A(n1540), .B(n1541), .Y(DP_OP_154J132_123_2038_n61) );
NOR2X1TS U1571 ( .A(n1446), .B(n1296), .Y(DP_OP_153J132_122_5442_n282) );
NAND2X1TS U1572 ( .A(Op_MY[13]), .B(Op_MX[15]), .Y(n1166) );
OAI32X1TS U1573 ( .A0(DP_OP_154J132_123_2038_n240), .A1(n1702), .A2(n425),
.B0(n1166), .B1(DP_OP_154J132_123_2038_n240), .Y(
DP_OP_154J132_123_2038_n241) );
OR3X1TS U1574 ( .A(Sgf_normalized_result[2]), .B(Sgf_normalized_result[1]),
.C(Sgf_normalized_result[0]), .Y(n1617) );
NAND2X1TS U1575 ( .A(Sgf_normalized_result[3]), .B(n1617), .Y(n1616) );
NAND2X1TS U1576 ( .A(n1750), .B(n1616), .Y(n1620) );
NAND2X1TS U1577 ( .A(Sgf_normalized_result[5]), .B(n1620), .Y(n1619) );
AOI21X1TS U1578 ( .A0(n1739), .A1(n1619), .B0(n1623), .Y(n1167) );
CLKBUFX3TS U1579 ( .A(n1003), .Y(n1651) );
AO22XLTS U1580 ( .A0(n1398), .A1(n1167), .B0(n1651), .B1(Add_result[6]), .Y(
n303) );
OAI32X1TS U1581 ( .A0(n1584), .A1(n1597), .A2(n1588), .B0(n1586), .B1(n1584),
.Y(DP_OP_155J132_124_2038_n90) );
INVX2TS U1582 ( .A(n1003), .Y(n1396) );
NAND2X1TS U1583 ( .A(Sgf_normalized_result[7]), .B(n1623), .Y(n1622) );
NAND2X1TS U1584 ( .A(Sgf_normalized_result[9]), .B(n1626), .Y(n1625) );
NAND2X1TS U1585 ( .A(Sgf_normalized_result[11]), .B(n1629), .Y(n1628) );
NAND2X1TS U1586 ( .A(Sgf_normalized_result[13]), .B(n1632), .Y(n1631) );
NAND2X1TS U1587 ( .A(Sgf_normalized_result[15]), .B(n1635), .Y(n1634) );
NAND2X1TS U1588 ( .A(Sgf_normalized_result[17]), .B(n1638), .Y(n1637) );
NAND2X1TS U1589 ( .A(Sgf_normalized_result[19]), .B(n1641), .Y(n1640) );
AOI21X1TS U1590 ( .A0(n1746), .A1(n1640), .B0(n1645), .Y(n1168) );
AO22XLTS U1591 ( .A0(n1396), .A1(n1168), .B0(n1003), .B1(Add_result[20]),
.Y(n289) );
INVX2TS U1592 ( .A(n1300), .Y(n1369) );
NOR2X1TS U1593 ( .A(DP_OP_156J132_125_3370_n119), .B(n1278), .Y(n1277) );
OAI22X1TS U1594 ( .A0(n1277), .A1(DP_OP_156J132_125_3370_n118), .B0(
Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .B1(n1278), .Y(
n1171) );
AO22XLTS U1595 ( .A0(n1300), .A1(P_Sgf[47]), .B0(n1369), .B1(n1171), .Y(n237) );
CLKBUFX3TS U1596 ( .A(n1301), .Y(n1387) );
INVX2TS U1597 ( .A(n1300), .Y(n1393) );
CMPR32X2TS U1598 ( .A(n1174), .B(n1173), .C(n1172), .CO(n1202), .S(n1175) );
AO22XLTS U1599 ( .A0(n1387), .A1(P_Sgf[29]), .B0(n1393), .B1(n1175), .Y(n267) );
INVX2TS U1600 ( .A(n1687), .Y(n1232) );
CLKBUFX2TS U1601 ( .A(n1179), .Y(n1231) );
AO22XLTS U1602 ( .A0(Sgf_normalized_result[3]), .A1(n1232), .B0(
final_result_ieee[3]), .B1(n1231), .Y(n197) );
AOI32X1TS U1603 ( .A0(n1178), .A1(n516), .A2(n1177), .B0(n1753), .B1(n1176),
.Y(n310) );
AO22XLTS U1604 ( .A0(Sgf_normalized_result[7]), .A1(n1232), .B0(
final_result_ieee[7]), .B1(n1179), .Y(n193) );
AOI21X1TS U1605 ( .A0(n1745), .A1(n1637), .B0(n1641), .Y(n1180) );
AO22XLTS U1606 ( .A0(n1396), .A1(n1180), .B0(n1340), .B1(Add_result[18]),
.Y(n291) );
AO22XLTS U1607 ( .A0(Sgf_normalized_result[1]), .A1(n1232), .B0(
final_result_ieee[1]), .B1(n1231), .Y(n199) );
AO22XLTS U1608 ( .A0(Sgf_normalized_result[6]), .A1(n1232), .B0(
final_result_ieee[6]), .B1(n1179), .Y(n194) );
INVX2TS U1609 ( .A(n1300), .Y(n1386) );
AOI21X1TS U1610 ( .A0(DP_OP_156J132_125_3370_n121), .A1(n1652), .B0(n1181),
.Y(n1182) );
AO22XLTS U1611 ( .A0(n1680), .A1(P_Sgf[44]), .B0(n1386), .B1(n1182), .Y(n282) );
AO22XLTS U1612 ( .A0(Sgf_normalized_result[5]), .A1(n1232), .B0(
final_result_ieee[5]), .B1(n1231), .Y(n195) );
CMPR32X2TS U1613 ( .A(n1185), .B(n1184), .C(n1183), .CO(n1663), .S(n1186) );
AO22XLTS U1614 ( .A0(n1387), .A1(P_Sgf[37]), .B0(n1369), .B1(n1186), .Y(n275) );
AO22XLTS U1615 ( .A0(Sgf_normalized_result[0]), .A1(n1232), .B0(
final_result_ieee[0]), .B1(n1400), .Y(n200) );
AO22XLTS U1616 ( .A0(Sgf_normalized_result[9]), .A1(n1232), .B0(
final_result_ieee[9]), .B1(n1179), .Y(n191) );
INVX2TS U1617 ( .A(n1687), .Y(n1401) );
AO22XLTS U1618 ( .A0(Sgf_normalized_result[10]), .A1(n1401), .B0(
final_result_ieee[10]), .B1(n1231), .Y(n190) );
AOI21X1TS U1619 ( .A0(n1743), .A1(n1631), .B0(n1635), .Y(n1187) );
AO22XLTS U1620 ( .A0(n1398), .A1(n1187), .B0(n1340), .B1(Add_result[14]),
.Y(n295) );
OAI21XLTS U1621 ( .A0(Sgf_normalized_result[1]), .A1(
Sgf_normalized_result[0]), .B0(Sgf_normalized_result[2]), .Y(n1188) );
AOI32X1TS U1622 ( .A0(n1617), .A1(n1398), .A2(n1188), .B0(n1754), .B1(n1340),
.Y(n307) );
AO22XLTS U1623 ( .A0(Sgf_normalized_result[2]), .A1(n1232), .B0(
final_result_ieee[2]), .B1(n1231), .Y(n198) );
INVX2TS U1624 ( .A(n1303), .Y(n1264) );
AO22XLTS U1625 ( .A0(n1268), .A1(Op_MY[8]), .B0(n1264), .B1(Data_MY[8]), .Y(
n320) );
AO22XLTS U1626 ( .A0(Sgf_normalized_result[8]), .A1(n1232), .B0(
final_result_ieee[8]), .B1(n1179), .Y(n192) );
CMPR32X2TS U1627 ( .A(DP_OP_154J132_123_2038_n87), .B(n1191), .C(n1190),
.CO(n1671), .S(n1192) );
INVX2TS U1628 ( .A(n1300), .Y(n1682) );
AOI2BB2XLTS U1629 ( .B0(n1192), .B1(n1682), .A0N(n1678), .A1N(P_Sgf[26]),
.Y(n264) );
CLKBUFX3TS U1630 ( .A(n1268), .Y(n1261) );
INVX2TS U1631 ( .A(n1303), .Y(n1235) );
AO22XLTS U1632 ( .A0(n1363), .A1(Op_MX[18]), .B0(n1235), .B1(Data_MX[18]),
.Y(n362) );
AOI21X1TS U1633 ( .A0(n1741), .A1(n1625), .B0(n1629), .Y(n1193) );
AO22XLTS U1634 ( .A0(n1398), .A1(n1193), .B0(n1340), .B1(Add_result[10]),
.Y(n299) );
NAND2X1TS U1635 ( .A(Op_MY[1]), .B(Op_MX[4]), .Y(n1194) );
OAI32X1TS U1636 ( .A0(DP_OP_155J132_124_2038_n235), .A1(n1695), .A2(n393),
.B0(n1194), .B1(DP_OP_155J132_124_2038_n235), .Y(
DP_OP_155J132_124_2038_n236) );
INVX2TS U1637 ( .A(n1303), .Y(n1260) );
AO22XLTS U1638 ( .A0(n1263), .A1(Op_MX[17]), .B0(n1260), .B1(Data_MX[17]),
.Y(n361) );
AOI21X1TS U1639 ( .A0(n1740), .A1(n1622), .B0(n1626), .Y(n1195) );
AO22XLTS U1640 ( .A0(n1398), .A1(n1195), .B0(n1340), .B1(Add_result[8]), .Y(
n301) );
XNOR2X1TS U1641 ( .A(n1197), .B(n1196), .Y(n1198) );
XNOR2X1TS U1642 ( .A(n1199), .B(n1198), .Y(n1200) );
AO22XLTS U1643 ( .A0(n1387), .A1(P_Sgf[31]), .B0(n1393), .B1(n1200), .Y(n269) );
CLKBUFX3TS U1644 ( .A(n1268), .Y(n1267) );
INVX2TS U1645 ( .A(n1303), .Y(n1266) );
AO22XLTS U1646 ( .A0(n1261), .A1(Op_MX[5]), .B0(n1266), .B1(Data_MX[5]), .Y(
n349) );
AO22XLTS U1647 ( .A0(n1267), .A1(Op_MX[9]), .B0(n1260), .B1(Data_MX[9]), .Y(
n353) );
OAI2BB1X1TS U1648 ( .A0N(n1203), .A1N(n1202), .B0(n1201), .Y(n1204) );
XNOR2X1TS U1649 ( .A(n1205), .B(n1204), .Y(n1206) );
AO22XLTS U1650 ( .A0(n1387), .A1(P_Sgf[30]), .B0(n1369), .B1(n1206), .Y(n268) );
AO22XLTS U1651 ( .A0(n1263), .A1(Op_MX[3]), .B0(n1266), .B1(Data_MX[3]), .Y(
n347) );
AOI21X1TS U1652 ( .A0(n1742), .A1(n1628), .B0(n1632), .Y(n1207) );
AO22XLTS U1653 ( .A0(n1398), .A1(n1207), .B0(n1340), .B1(Add_result[12]),
.Y(n297) );
XNOR2X1TS U1654 ( .A(n1209), .B(n1208), .Y(n1210) );
XNOR2X1TS U1655 ( .A(n1211), .B(n1210), .Y(n1212) );
AO22XLTS U1656 ( .A0(n1387), .A1(P_Sgf[28]), .B0(n1393), .B1(n1212), .Y(n266) );
XNOR2X1TS U1657 ( .A(n1214), .B(n1213), .Y(n1215) );
XNOR2X1TS U1658 ( .A(n1216), .B(n1215), .Y(n1217) );
AO22XLTS U1659 ( .A0(n1387), .A1(P_Sgf[35]), .B0(n1393), .B1(n1217), .Y(n273) );
AO22XLTS U1660 ( .A0(n1261), .A1(Op_MX[15]), .B0(n1260), .B1(Data_MX[15]),
.Y(n359) );
AO22XLTS U1661 ( .A0(n1267), .A1(Op_MX[6]), .B0(n1266), .B1(Data_MX[6]), .Y(
n350) );
NOR3XLTS U1662 ( .A(Exp_module_Data_S[7]), .B(Exp_module_Data_S[8]), .C(
n1265), .Y(n1220) );
AND4X1TS U1663 ( .A(Exp_module_Data_S[6]), .B(Exp_module_Data_S[3]), .C(
Exp_module_Data_S[2]), .D(Exp_module_Data_S[1]), .Y(n1218) );
NAND4XLTS U1664 ( .A(Exp_module_Data_S[0]), .B(Exp_module_Data_S[5]), .C(
Exp_module_Data_S[4]), .D(n1218), .Y(n1219) );
AO22XLTS U1665 ( .A0(n1220), .A1(n1219), .B0(underflow_flag), .B1(n1265),
.Y(n201) );
NOR2XLTS U1666 ( .A(n1727), .B(n1704), .Y(n1223) );
NOR2XLTS U1667 ( .A(n1719), .B(n1695), .Y(n1222) );
NOR2XLTS U1668 ( .A(n1724), .B(n1707), .Y(n1221) );
CMPR32X2TS U1669 ( .A(n1223), .B(n1222), .C(n1221), .CO(
DP_OP_155J132_124_2038_n221), .S(DP_OP_155J132_124_2038_n222) );
NOR2XLTS U1670 ( .A(n1728), .B(n443), .Y(n1226) );
NOR2XLTS U1671 ( .A(n1692), .B(n1703), .Y(n1225) );
NOR2XLTS U1672 ( .A(n1721), .B(n1708), .Y(n1224) );
CMPR32X2TS U1673 ( .A(n1226), .B(n1225), .C(n1224), .CO(
DP_OP_155J132_124_2038_n312), .S(DP_OP_155J132_124_2038_n313) );
AO22XLTS U1674 ( .A0(n1363), .A1(Op_MX[21]), .B0(n1235), .B1(Data_MX[21]),
.Y(n365) );
AOI21X1TS U1675 ( .A0(n1744), .A1(n1634), .B0(n1638), .Y(n1227) );
AO22XLTS U1676 ( .A0(n1396), .A1(n1227), .B0(n1340), .B1(Add_result[16]),
.Y(n293) );
AOI32X1TS U1677 ( .A0(FS_Module_state_reg[1]), .A1(n1701), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n1228), .Y(
n1230) );
NAND3XLTS U1678 ( .A(n1230), .B(n1370), .C(n1229), .Y(n377) );
AO22XLTS U1679 ( .A0(n1236), .A1(Op_MX[16]), .B0(n1260), .B1(Data_MX[16]),
.Y(n360) );
AO22XLTS U1680 ( .A0(Sgf_normalized_result[4]), .A1(n1232), .B0(
final_result_ieee[4]), .B1(n1231), .Y(n196) );
INVX2TS U1681 ( .A(n1303), .Y(n1364) );
AO22XLTS U1682 ( .A0(n1236), .A1(Op_MY[1]), .B0(n1364), .B1(Data_MY[1]), .Y(
n313) );
AO22XLTS U1683 ( .A0(n1363), .A1(Op_MX[11]), .B0(n1260), .B1(Data_MX[11]),
.Y(n355) );
CLKBUFX3TS U1684 ( .A(n1268), .Y(n1263) );
INVX2TS U1685 ( .A(n1303), .Y(n1262) );
AO22XLTS U1686 ( .A0(n1236), .A1(Op_MY[13]), .B0(n1262), .B1(Data_MY[13]),
.Y(n325) );
AO22XLTS U1687 ( .A0(n1261), .A1(Op_MX[4]), .B0(n1266), .B1(Data_MX[4]), .Y(
n348) );
NAND2X1TS U1688 ( .A(Op_MY[7]), .B(Op_MX[10]), .Y(n1233) );
OAI32X1TS U1689 ( .A0(DP_OP_155J132_124_2038_n326), .A1(n1703), .A2(n396),
.B0(n1233), .B1(DP_OP_155J132_124_2038_n326), .Y(
DP_OP_155J132_124_2038_n327) );
NAND2X1TS U1690 ( .A(Sgf_normalized_result[21]), .B(n1645), .Y(n1643) );
AOI211XLTS U1691 ( .A0(n1747), .A1(n1643), .B0(n1649), .C0(n1340), .Y(n1234)
);
AO21XLTS U1692 ( .A0(Add_result[22]), .A1(n1651), .B0(n1234), .Y(n287) );
AO22XLTS U1693 ( .A0(n1263), .A1(Op_MX[22]), .B0(n1364), .B1(Data_MX[22]),
.Y(n366) );
AO22XLTS U1694 ( .A0(n1263), .A1(Op_MX[14]), .B0(n1260), .B1(Data_MX[14]),
.Y(n358) );
AO22XLTS U1695 ( .A0(n1236), .A1(Op_MX[8]), .B0(n1260), .B1(Data_MX[8]), .Y(
n352) );
AO22XLTS U1696 ( .A0(n1267), .A1(Op_MX[19]), .B0(n1235), .B1(Data_MX[19]),
.Y(n363) );
AO22XLTS U1697 ( .A0(n1363), .A1(Op_MX[1]), .B0(n1266), .B1(Data_MX[1]), .Y(
n345) );
AO22XLTS U1698 ( .A0(n1263), .A1(Op_MX[7]), .B0(n1266), .B1(Data_MX[7]), .Y(
n351) );
AO22XLTS U1699 ( .A0(n1267), .A1(Op_MX[13]), .B0(n1260), .B1(Data_MX[13]),
.Y(n357) );
AO22XLTS U1700 ( .A0(n1363), .A1(Op_MX[20]), .B0(n1235), .B1(Data_MX[20]),
.Y(n364) );
AO22XLTS U1701 ( .A0(n1363), .A1(Op_MY[19]), .B0(n1262), .B1(Data_MY[19]),
.Y(n331) );
AO22XLTS U1702 ( .A0(n1263), .A1(Op_MY[14]), .B0(n1262), .B1(Data_MY[14]),
.Y(n326) );
AO22XLTS U1703 ( .A0(n1261), .A1(Op_MY[2]), .B0(n1264), .B1(Data_MY[2]), .Y(
n314) );
AO22XLTS U1704 ( .A0(n1268), .A1(Op_MY[6]), .B0(n1264), .B1(Data_MY[6]), .Y(
n318) );
AO22XLTS U1705 ( .A0(n1267), .A1(Op_MY[21]), .B0(n1262), .B1(Data_MY[21]),
.Y(n333) );
AO22XLTS U1706 ( .A0(n1303), .A1(Op_MY[11]), .B0(n1264), .B1(Data_MY[11]),
.Y(n323) );
AO22XLTS U1707 ( .A0(n1261), .A1(Op_MY[18]), .B0(n1262), .B1(Data_MY[18]),
.Y(n330) );
AO22XLTS U1708 ( .A0(n1236), .A1(Op_MY[10]), .B0(n1264), .B1(Data_MY[10]),
.Y(n322) );
AO22XLTS U1709 ( .A0(n1267), .A1(Op_MY[0]), .B0(n1266), .B1(Data_MY[0]), .Y(
n312) );
AO22XLTS U1710 ( .A0(n1363), .A1(Op_MY[4]), .B0(n1264), .B1(Data_MY[4]), .Y(
n316) );
AO22XLTS U1711 ( .A0(n1303), .A1(Op_MY[5]), .B0(n1266), .B1(Data_MY[5]), .Y(
n317) );
AO22XLTS U1712 ( .A0(n1236), .A1(Op_MY[12]), .B0(n1264), .B1(Data_MY[12]),
.Y(n324) );
AO22XLTS U1713 ( .A0(n1263), .A1(Op_MY[16]), .B0(n1262), .B1(Data_MY[16]),
.Y(n328) );
AO22XLTS U1714 ( .A0(n1261), .A1(Op_MX[0]), .B0(n1266), .B1(Data_MX[0]), .Y(
n344) );
AO22XLTS U1715 ( .A0(n1267), .A1(Op_MY[17]), .B0(n1262), .B1(Data_MY[17]),
.Y(n329) );
AO22XLTS U1716 ( .A0(n1363), .A1(Op_MY[3]), .B0(n1264), .B1(Data_MY[3]), .Y(
n315) );
AO22XLTS U1717 ( .A0(n1303), .A1(Op_MY[9]), .B0(n1264), .B1(Data_MY[9]), .Y(
n321) );
AO22XLTS U1718 ( .A0(n1261), .A1(Op_MX[10]), .B0(n1260), .B1(Data_MX[10]),
.Y(n354) );
NOR4X1TS U1719 ( .A(Op_MY[28]), .B(Op_MY[27]), .C(Op_MY[26]), .D(Op_MY[25]),
.Y(n1240) );
NOR4X1TS U1720 ( .A(Op_MY[20]), .B(Op_MY[19]), .C(Op_MY[7]), .D(Op_MY[29]),
.Y(n1239) );
NOR4X1TS U1721 ( .A(Op_MY[13]), .B(Op_MY[14]), .C(Op_MY[3]), .D(Op_MY[2]),
.Y(n1238) );
NOR4X1TS U1722 ( .A(Op_MY[24]), .B(Op_MY[23]), .C(Op_MY[30]), .D(Op_MY[11]),
.Y(n1237) );
NAND4XLTS U1723 ( .A(n1240), .B(n1239), .C(n1238), .D(n1237), .Y(n1258) );
NAND2X1TS U1724 ( .A(n425), .B(n408), .Y(n1241) );
NOR4X1TS U1725 ( .A(Op_MY[1]), .B(Op_MY[15]), .C(Op_MY[10]), .D(n1241), .Y(
n1244) );
NOR4X1TS U1726 ( .A(Op_MY[16]), .B(Op_MY[4]), .C(Op_MY[17]), .D(Op_MY[5]),
.Y(n1243) );
NOR4X1TS U1727 ( .A(Op_MY[8]), .B(Op_MY[21]), .C(Op_MY[9]), .D(Op_MY[22]),
.Y(n1242) );
NAND4XLTS U1728 ( .A(n1245), .B(n1244), .C(n1243), .D(n1242), .Y(n1257) );
NOR4X1TS U1729 ( .A(Op_MX[29]), .B(Op_MX[28]), .C(Op_MX[27]), .D(Op_MX[26]),
.Y(n1249) );
NOR4X1TS U1730 ( .A(Op_MX[20]), .B(Op_MX[19]), .C(Op_MX[7]), .D(Op_MX[30]),
.Y(n1248) );
NOR4X1TS U1731 ( .A(Op_MX[13]), .B(Op_MX[14]), .C(Op_MX[3]), .D(Op_MX[2]),
.Y(n1247) );
NOR4X1TS U1732 ( .A(Op_MX[25]), .B(Op_MX[24]), .C(Op_MX[23]), .D(Op_MX[11]),
.Y(n1246) );
NAND4XLTS U1733 ( .A(n1249), .B(n1248), .C(n1247), .D(n1246), .Y(n1256) );
NAND2X1TS U1734 ( .A(n405), .B(n1693), .Y(n1250) );
NOR4X1TS U1735 ( .A(Op_MX[1]), .B(Op_MX[15]), .C(Op_MX[10]), .D(n1250), .Y(
n1253) );
NOR4X1TS U1736 ( .A(Op_MX[16]), .B(Op_MX[4]), .C(Op_MX[17]), .D(Op_MX[5]),
.Y(n1252) );
NOR4X1TS U1737 ( .A(Op_MX[8]), .B(Op_MX[21]), .C(Op_MX[9]), .D(Op_MX[22]),
.Y(n1251) );
NAND4XLTS U1738 ( .A(n1254), .B(n1253), .C(n1252), .D(n1251), .Y(n1255) );
OAI22X1TS U1739 ( .A0(n1258), .A1(n1257), .B0(n1256), .B1(n1255), .Y(n1259)
);
AO22XLTS U1740 ( .A0(n1265), .A1(zero_flag), .B0(n1286), .B1(n1259), .Y(n311) );
AO22XLTS U1741 ( .A0(n1261), .A1(Op_MY[15]), .B0(n1262), .B1(Data_MY[15]),
.Y(n327) );
AO22XLTS U1742 ( .A0(n1263), .A1(Op_MY[22]), .B0(n1262), .B1(Data_MY[22]),
.Y(n334) );
AO22XLTS U1743 ( .A0(n1236), .A1(Op_MX[12]), .B0(n1260), .B1(Data_MX[12]),
.Y(n356) );
AO22XLTS U1744 ( .A0(n1267), .A1(Op_MY[20]), .B0(n1262), .B1(Data_MY[20]),
.Y(n332) );
AO22XLTS U1745 ( .A0(n1303), .A1(Op_MY[7]), .B0(n1264), .B1(Data_MY[7]), .Y(
n319) );
NAND2X1TS U1746 ( .A(n1265), .B(n444), .Y(n376) );
AO22XLTS U1747 ( .A0(n1236), .A1(Op_MX[2]), .B0(n1266), .B1(Data_MX[2]), .Y(
n346) );
CLKBUFX2TS U1748 ( .A(n1268), .Y(n1345) );
INVX2TS U1749 ( .A(n1345), .Y(n1346) );
AO22XLTS U1750 ( .A0(n1346), .A1(Data_MY[30]), .B0(n1263), .B1(Op_MY[30]),
.Y(n342) );
AO22XLTS U1751 ( .A0(n1346), .A1(Data_MY[24]), .B0(n1345), .B1(Op_MY[24]),
.Y(n336) );
AO22XLTS U1752 ( .A0(n1346), .A1(Data_MY[25]), .B0(n1345), .B1(Op_MY[25]),
.Y(n337) );
AO22XLTS U1753 ( .A0(n1364), .A1(Data_MX[27]), .B0(n1267), .B1(Op_MX[27]),
.Y(n371) );
AOI22X1TS U1754 ( .A0(n1270), .A1(n426), .B0(n391), .B1(n1269), .Y(n1427) );
AO22XLTS U1755 ( .A0(n1444), .A1(n1427), .B0(n1442), .B1(n1271), .Y(
DP_OP_153J132_122_5442_n400) );
AO22XLTS U1756 ( .A0(n1346), .A1(Data_MY[29]), .B0(n1345), .B1(Op_MY[29]),
.Y(n341) );
AO22XLTS U1757 ( .A0(n1364), .A1(Data_MX[23]), .B0(n1261), .B1(Op_MX[23]),
.Y(n367) );
AO22XLTS U1758 ( .A0(n1346), .A1(Data_MY[27]), .B0(n1345), .B1(Op_MY[27]),
.Y(n339) );
AO22XLTS U1759 ( .A0(n1346), .A1(Data_MY[26]), .B0(n1345), .B1(Op_MY[26]),
.Y(n338) );
AO22XLTS U1760 ( .A0(n1346), .A1(Data_MX[28]), .B0(n1236), .B1(Op_MX[28]),
.Y(n372) );
CLKBUFX3TS U1761 ( .A(n1301), .Y(n1394) );
OAI21XLTS U1762 ( .A0(n1273), .A1(DP_OP_156J132_125_3370_n95), .B0(n1272),
.Y(n1274) );
XNOR2X1TS U1763 ( .A(n1275), .B(n1274), .Y(n1276) );
AO22XLTS U1764 ( .A0(n1394), .A1(P_Sgf[23]), .B0(n1393), .B1(n1276), .Y(n261) );
AOI21X1TS U1765 ( .A0(DP_OP_156J132_125_3370_n119), .A1(n1278), .B0(n1277),
.Y(n1279) );
AO22XLTS U1766 ( .A0(n1387), .A1(P_Sgf[46]), .B0(n1369), .B1(n1279), .Y(n284) );
AO22XLTS U1767 ( .A0(n1364), .A1(Data_MX[24]), .B0(n1363), .B1(Op_MX[24]),
.Y(n368) );
AOI2BB2XLTS U1768 ( .B0(n1398), .B1(Sgf_normalized_result[0]), .A0N(
Add_result[0]), .A1N(n1396), .Y(n309) );
AO22XLTS U1769 ( .A0(n1364), .A1(Data_MX[30]), .B0(n1263), .B1(Op_MX[30]),
.Y(n374) );
AO22XLTS U1770 ( .A0(n1364), .A1(Data_MX[26]), .B0(n1267), .B1(Op_MX[26]),
.Y(n370) );
AO22XLTS U1771 ( .A0(n1394), .A1(P_Sgf[6]), .B0(n1369), .B1(n1280), .Y(n244)
);
AOI2BB2XLTS U1772 ( .B0(n1282), .B1(n1281), .A0N(n1281), .A1N(n1282), .Y(
n1283) );
XNOR2X1TS U1773 ( .A(n1284), .B(n1283), .Y(n1285) );
AO22XLTS U1774 ( .A0(n1394), .A1(P_Sgf[16]), .B0(n1369), .B1(n1285), .Y(n254) );
NOR2X4TS U1775 ( .A(n1286), .B(n1678), .Y(n1336) );
MX2X1TS U1776 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n1336),
.Y(n226) );
OAI21XLTS U1777 ( .A0(n1288), .A1(DP_OP_156J132_125_3370_n97), .B0(n1287),
.Y(n1289) );
XNOR2X1TS U1778 ( .A(n1290), .B(n1289), .Y(n1291) );
AO22XLTS U1779 ( .A0(n1394), .A1(P_Sgf[21]), .B0(n1393), .B1(n1291), .Y(n259) );
AO22XLTS U1780 ( .A0(n1346), .A1(Data_MX[29]), .B0(n1261), .B1(Op_MX[29]),
.Y(n373) );
NOR2XLTS U1781 ( .A(n1448), .B(n1297), .Y(n1298) );
AO22XLTS U1782 ( .A0(n1364), .A1(Data_MX[31]), .B0(n1268), .B1(Op_MX[31]),
.Y(n343) );
INVX2TS U1783 ( .A(n1300), .Y(n1358) );
CLKBUFX3TS U1784 ( .A(n1301), .Y(n1686) );
AO22XLTS U1785 ( .A0(n1358), .A1(n1302), .B0(n1686), .B1(P_Sgf[2]), .Y(n240)
);
AO22XLTS U1786 ( .A0(n1364), .A1(Data_MX[25]), .B0(n1236), .B1(Op_MX[25]),
.Y(n369) );
AO22XLTS U1787 ( .A0(n1358), .A1(n1304), .B0(n1686), .B1(P_Sgf[10]), .Y(n248) );
MX2X1TS U1788 ( .A(Op_MY[23]), .B(Data_MY[23]), .S0(n1346), .Y(n335) );
AO22XLTS U1789 ( .A0(n1686), .A1(P_Sgf[5]), .B0(n1369), .B1(n1305), .Y(n243)
);
AOI21X1TS U1790 ( .A0(n1307), .A1(DP_OP_156J132_125_3370_n103), .B0(n1306),
.Y(n1308) );
XOR2XLTS U1791 ( .A(n1309), .B(n1308), .Y(n1310) );
AO22XLTS U1792 ( .A0(n1394), .A1(P_Sgf[15]), .B0(n1386), .B1(n1310), .Y(n253) );
MX2X1TS U1793 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n1336),
.Y(n234) );
OAI32X1TS U1794 ( .A0(n1313), .A1(n1473), .A2(n1475), .B0(n1311), .B1(n1313),
.Y(DP_OP_153J132_122_5442_n115) );
AO22XLTS U1795 ( .A0(n1358), .A1(n1312), .B0(n1686), .B1(P_Sgf[9]), .Y(n247)
);
NOR2XLTS U1796 ( .A(n1469), .B(n1473), .Y(n1314) );
CMPR32X2TS U1797 ( .A(DP_OP_153J132_122_5442_n111), .B(n1314), .C(n1313),
.CO(DP_OP_153J132_122_5442_n104), .S(DP_OP_153J132_122_5442_n105) );
CMPR32X2TS U1798 ( .A(DP_OP_156J132_125_3370_n105), .B(n1315), .C(n1681),
.CO(n1349), .S(n1316) );
AOI2BB2XLTS U1799 ( .B0(n1316), .B1(n1682), .A0N(n1358), .A1N(P_Sgf[13]),
.Y(n251) );
MX2X1TS U1800 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n1336),
.Y(n233) );
CMPR32X2TS U1801 ( .A(n1318), .B(n1317), .C(DP_OP_156J132_125_3370_n98),
.CO(n1288), .S(n1319) );
AOI2BB2XLTS U1802 ( .B0(n1319), .B1(n1682), .A0N(n1358), .A1N(P_Sgf[20]),
.Y(n258) );
MX2X1TS U1803 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n1336),
.Y(n232) );
AO22XLTS U1804 ( .A0(n1394), .A1(P_Sgf[7]), .B0(n1386), .B1(n1320), .Y(n245)
);
NOR2XLTS U1805 ( .A(n1729), .B(n1702), .Y(n1323) );
NOR2XLTS U1806 ( .A(n1718), .B(n1694), .Y(n1322) );
NOR2XLTS U1807 ( .A(n1726), .B(n1706), .Y(n1321) );
CMPR32X2TS U1808 ( .A(n1323), .B(n1322), .C(n1321), .CO(
DP_OP_154J132_123_2038_n221), .S(DP_OP_154J132_123_2038_n222) );
MX2X1TS U1809 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n1336),
.Y(n231) );
AOI2BB2XLTS U1810 ( .B0(n1324), .B1(DP_OP_156J132_125_3370_n101), .A0N(
DP_OP_156J132_125_3370_n101), .A1N(n1324), .Y(n1325) );
XNOR2X1TS U1811 ( .A(n1326), .B(n1325), .Y(n1327) );
AO22XLTS U1812 ( .A0(n1394), .A1(P_Sgf[17]), .B0(n1386), .B1(n1327), .Y(n255) );
AO22XLTS U1813 ( .A0(n1394), .A1(P_Sgf[4]), .B0(n1369), .B1(n1328), .Y(n242)
);
MX2X1TS U1814 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n1336),
.Y(n230) );
AO22XLTS U1815 ( .A0(n1358), .A1(n1329), .B0(n1686), .B1(P_Sgf[3]), .Y(n241)
);
MX2X1TS U1816 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n1336),
.Y(n229) );
AO22XLTS U1817 ( .A0(n1393), .A1(n1330), .B0(n1686), .B1(P_Sgf[11]), .Y(n249) );
NAND2X1TS U1818 ( .A(Op_MY[13]), .B(Op_MX[16]), .Y(n1331) );
OAI32X1TS U1819 ( .A0(DP_OP_154J132_123_2038_n235), .A1(n1694), .A2(n425),
.B0(n1331), .B1(DP_OP_154J132_123_2038_n235), .Y(
DP_OP_154J132_123_2038_n236) );
CMPR32X2TS U1820 ( .A(DP_OP_156J132_125_3370_n100), .B(n1333), .C(n1332),
.CO(n1357), .S(n1334) );
AOI2BB2XLTS U1821 ( .B0(n1334), .B1(n1682), .A0N(n1358), .A1N(P_Sgf[18]),
.Y(n256) );
MX2X1TS U1822 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(n1336),
.Y(n228) );
MX2X1TS U1823 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n1336),
.Y(n227) );
CMPR32X2TS U1824 ( .A(n1338), .B(n1337), .C(DP_OP_156J132_125_3370_n96),
.CO(n1273), .S(n1339) );
AOI2BB2XLTS U1825 ( .B0(n1339), .B1(n1682), .A0N(n1358), .A1N(P_Sgf[22]),
.Y(n260) );
AOI21X1TS U1826 ( .A0(n1649), .A1(Sgf_normalized_result[23]), .B0(n1340),
.Y(n1648) );
AOI2BB1XLTS U1827 ( .A0N(n1398), .A1N(FSM_add_overflow_flag), .B0(n1648),
.Y(n285) );
CMPR32X2TS U1828 ( .A(n1343), .B(n1342), .C(n1341), .CO(n1184), .S(n1344) );
AO22XLTS U1829 ( .A0(n1387), .A1(P_Sgf[36]), .B0(n1386), .B1(n1344), .Y(n274) );
AO22XLTS U1830 ( .A0(n1346), .A1(Data_MY[28]), .B0(Op_MY[28]), .B1(n1345),
.Y(n340) );
AO22XLTS U1831 ( .A0(n1393), .A1(n1347), .B0(n1686), .B1(P_Sgf[8]), .Y(n246)
);
CMPR32X2TS U1832 ( .A(DP_OP_156J132_125_3370_n104), .B(n1349), .C(n1348),
.CO(n1307), .S(n1350) );
AOI2BB2XLTS U1833 ( .B0(n1350), .B1(n1682), .A0N(n1358), .A1N(P_Sgf[14]),
.Y(n252) );
AOI21X1TS U1834 ( .A0(DP_OP_156J132_125_3370_n131), .A1(n1352), .B0(n1351),
.Y(n1353) );
XOR2XLTS U1835 ( .A(n1354), .B(n1353), .Y(n1355) );
AO22XLTS U1836 ( .A0(n1387), .A1(P_Sgf[34]), .B0(n1393), .B1(n1355), .Y(n272) );
CMPR32X2TS U1837 ( .A(DP_OP_156J132_125_3370_n99), .B(n1357), .C(n1356),
.CO(n1318), .S(n1359) );
AOI2BB2XLTS U1838 ( .B0(n1359), .B1(n1682), .A0N(n1358), .A1N(P_Sgf[19]),
.Y(n257) );
NOR2XLTS U1839 ( .A(n1730), .B(n1713), .Y(n1362) );
NOR2XLTS U1840 ( .A(n1731), .B(n1705), .Y(n1360) );
CMPR32X2TS U1841 ( .A(n1362), .B(n1361), .C(n1360), .CO(
DP_OP_154J132_123_2038_n317), .S(DP_OP_154J132_123_2038_n318) );
AO22XLTS U1842 ( .A0(n1364), .A1(Data_MY[31]), .B0(n1363), .B1(Op_MY[31]),
.Y(n381) );
CMPR32X2TS U1843 ( .A(DP_OP_156J132_125_3370_n133), .B(n1366), .C(n1365),
.CO(n1668), .S(n1367) );
AOI2BB2XLTS U1844 ( .B0(n1367), .B1(n1682), .A0N(n1678), .A1N(P_Sgf[32]),
.Y(n270) );
XNOR2X1TS U1845 ( .A(DP_OP_36J132_126_4699_n1), .B(n1370), .Y(n1371) );
AO22XLTS U1846 ( .A0(n1371), .A1(n1682), .B0(n1680), .B1(
Exp_module_Overflow_flag_A), .Y(n225) );
NOR2XLTS U1847 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n1372) );
NAND2X2TS U1848 ( .A(FSM_selector_B[0]), .B(n1715), .Y(n1379) );
OAI21XLTS U1849 ( .A0(FSM_selector_B[0]), .A1(n1372), .B0(n1379), .Y(n1373)
);
XOR2X1TS U1850 ( .A(DP_OP_36J132_126_4699_n33), .B(n1373), .Y(
DP_OP_36J132_126_4699_n22) );
MX2X1TS U1851 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
MX2X1TS U1852 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
OAI2BB1X1TS U1853 ( .A0N(Op_MY[24]), .A1N(n1715), .B0(n1379), .Y(n1374) );
XOR2X1TS U1854 ( .A(DP_OP_36J132_126_4699_n33), .B(n1374), .Y(
DP_OP_36J132_126_4699_n21) );
MX2X1TS U1855 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
OAI2BB1X1TS U1856 ( .A0N(Op_MY[25]), .A1N(n1715), .B0(n1379), .Y(n1375) );
XOR2X1TS U1857 ( .A(DP_OP_36J132_126_4699_n33), .B(n1375), .Y(
DP_OP_36J132_126_4699_n20) );
MX2X1TS U1858 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
OAI2BB1X1TS U1859 ( .A0N(Op_MY[26]), .A1N(n1715), .B0(n1379), .Y(n1376) );
XOR2X1TS U1860 ( .A(DP_OP_36J132_126_4699_n33), .B(n1376), .Y(
DP_OP_36J132_126_4699_n19) );
MX2X1TS U1861 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
OAI2BB1X1TS U1862 ( .A0N(Op_MY[27]), .A1N(n1715), .B0(n1379), .Y(n1377) );
XOR2X1TS U1863 ( .A(DP_OP_36J132_126_4699_n33), .B(n1377), .Y(
DP_OP_36J132_126_4699_n18) );
MX2X1TS U1864 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
OAI2BB1X1TS U1865 ( .A0N(Op_MY[28]), .A1N(n1715), .B0(n1379), .Y(n1378) );
XOR2X1TS U1866 ( .A(n437), .B(n1378), .Y(DP_OP_36J132_126_4699_n17) );
MX2X1TS U1867 ( .A(Op_MX[29]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
OAI2BB1X1TS U1868 ( .A0N(Op_MY[29]), .A1N(n1715), .B0(n1379), .Y(n1380) );
XOR2X1TS U1869 ( .A(n437), .B(n1380), .Y(DP_OP_36J132_126_4699_n16) );
MX2X1TS U1870 ( .A(Op_MX[30]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
NOR3BX1TS U1871 ( .AN(Op_MY[30]), .B(FSM_selector_B[0]), .C(
FSM_selector_B[1]), .Y(n1381) );
XOR2X1TS U1872 ( .A(n437), .B(n1381), .Y(DP_OP_36J132_126_4699_n15) );
CLKAND2X2TS U1873 ( .A(FSM_selector_A), .B(exp_oper_result[8]), .Y(
S_Oper_A_exp[8]) );
OAI21XLTS U1874 ( .A0(n1616), .A1(n1750), .B0(n1620), .Y(n1382) );
AO22XLTS U1875 ( .A0(n1396), .A1(n1382), .B0(n1651), .B1(Add_result[4]), .Y(
n305) );
AO22XLTS U1876 ( .A0(Sgf_normalized_result[18]), .A1(n1401), .B0(
final_result_ieee[18]), .B1(n1400), .Y(n182) );
AOI21X1TS U1877 ( .A0(DP_OP_156J132_125_3370_n123), .A1(n1656), .B0(n1653),
.Y(n1383) );
AO22XLTS U1878 ( .A0(n1680), .A1(P_Sgf[42]), .B0(n1386), .B1(n1383), .Y(n280) );
OAI31X1TS U1879 ( .A0(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]),
.A1(n1460), .A2(n1496), .B0(n1384), .Y(DP_OP_153J132_122_5442_n25) );
AOI21X1TS U1880 ( .A0(DP_OP_156J132_125_3370_n125), .A1(n1660), .B0(n1657),
.Y(n1385) );
AO22XLTS U1881 ( .A0(n1387), .A1(P_Sgf[40]), .B0(n1386), .B1(n1385), .Y(n278) );
AO22XLTS U1882 ( .A0(Sgf_normalized_result[15]), .A1(n1401), .B0(
final_result_ieee[15]), .B1(n1400), .Y(n185) );
XNOR2X1TS U1883 ( .A(n1389), .B(n1388), .Y(n1390) );
XNOR2X1TS U1884 ( .A(n1391), .B(n1390), .Y(n1392) );
AO22XLTS U1885 ( .A0(n1394), .A1(P_Sgf[24]), .B0(n1393), .B1(n1392), .Y(n262) );
NOR2XLTS U1886 ( .A(Sgf_normalized_result[1]), .B(Sgf_normalized_result[0]),
.Y(n1395) );
AOI21X1TS U1887 ( .A0(Sgf_normalized_result[0]), .A1(
Sgf_normalized_result[1]), .B0(n1395), .Y(n1397) );
AOI2BB2XLTS U1888 ( .B0(n1398), .B1(n1397), .A0N(Add_result[1]), .A1N(n1396),
.Y(n308) );
AO22XLTS U1889 ( .A0(Sgf_normalized_result[12]), .A1(n1401), .B0(
final_result_ieee[12]), .B1(n1231), .Y(n188) );
AO22XLTS U1890 ( .A0(Sgf_normalized_result[11]), .A1(n1401), .B0(
final_result_ieee[11]), .B1(n1179), .Y(n189) );
INVX2TS U1891 ( .A(n1687), .Y(n1399) );
AO22XLTS U1892 ( .A0(Sgf_normalized_result[21]), .A1(n1399), .B0(
final_result_ieee[21]), .B1(n1400), .Y(n179) );
AO22XLTS U1893 ( .A0(Sgf_normalized_result[22]), .A1(n1399), .B0(
final_result_ieee[22]), .B1(n1400), .Y(n178) );
AO22XLTS U1894 ( .A0(Sgf_normalized_result[19]), .A1(n1401), .B0(
final_result_ieee[19]), .B1(n1400), .Y(n181) );
AO22XLTS U1895 ( .A0(Sgf_normalized_result[13]), .A1(n1401), .B0(
final_result_ieee[13]), .B1(n1179), .Y(n187) );
AO22XLTS U1896 ( .A0(Sgf_normalized_result[20]), .A1(n1399), .B0(
final_result_ieee[20]), .B1(n1400), .Y(n180) );
AO22XLTS U1897 ( .A0(Sgf_normalized_result[14]), .A1(n1401), .B0(
final_result_ieee[14]), .B1(n1179), .Y(n186) );
AO22XLTS U1898 ( .A0(Sgf_normalized_result[16]), .A1(n1401), .B0(
final_result_ieee[16]), .B1(n1400), .Y(n184) );
AO22XLTS U1899 ( .A0(Sgf_normalized_result[17]), .A1(n1401), .B0(
final_result_ieee[17]), .B1(n1179), .Y(n183) );
NAND2X1TS U1900 ( .A(Op_MY[7]), .B(Op_MX[11]), .Y(n1402) );
OAI32X1TS U1901 ( .A0(DP_OP_155J132_124_2038_n319), .A1(n443), .A2(n1692),
.B0(n1402), .B1(DP_OP_155J132_124_2038_n319), .Y(
DP_OP_155J132_124_2038_n320) );
NAND2X1TS U1902 ( .A(Op_MY[2]), .B(Op_MX[4]), .Y(n1403) );
OAI32X1TS U1903 ( .A0(DP_OP_155J132_124_2038_n228), .A1(n1695), .A2(n1690),
.B0(n1403), .B1(DP_OP_155J132_124_2038_n228), .Y(
DP_OP_155J132_124_2038_n229) );
NOR2XLTS U1904 ( .A(n1722), .B(n1708), .Y(n1406) );
NOR2XLTS U1905 ( .A(n1728), .B(n1696), .Y(n1405) );
NOR2XLTS U1906 ( .A(n1721), .B(n1711), .Y(n1404) );
CMPR32X2TS U1907 ( .A(n1406), .B(n1405), .C(n1404), .CO(
DP_OP_155J132_124_2038_n317), .S(DP_OP_155J132_124_2038_n318) );
OA21XLTS U1908 ( .A0(DP_OP_155J132_124_2038_n73), .A1(n1408), .B0(n1407),
.Y(DP_OP_155J132_124_2038_n72) );
NOR2XLTS U1909 ( .A(n1723), .B(n1707), .Y(n1411) );
NOR2XLTS U1910 ( .A(n1727), .B(n1697), .Y(n1410) );
CMPR32X2TS U1911 ( .A(n1411), .B(n1410), .C(n1409), .CO(
DP_OP_155J132_124_2038_n226), .S(DP_OP_155J132_124_2038_n227) );
NOR2XLTS U1912 ( .A(n1731), .B(n1700), .Y(n1414) );
NOR2XLTS U1913 ( .A(n1716), .B(n1705), .Y(n1413) );
CMPR32X2TS U1914 ( .A(n1414), .B(n1413), .C(n1412), .CO(
DP_OP_154J132_123_2038_n324), .S(DP_OP_154J132_123_2038_n325) );
NOR2XLTS U1915 ( .A(n1720), .B(n1705), .Y(n1415) );
CMPR32X2TS U1916 ( .A(Op_MX[20]), .B(Op_MY[20]), .C(n1415), .CO(
DP_OP_154J132_123_2038_n312), .S(DP_OP_154J132_123_2038_n313) );
AOI22X1TS U1917 ( .A0(n1416), .A1(n419), .B0(n1584), .B1(n1607), .Y(n1422)
);
AO22XLTS U1918 ( .A0(n1456), .A1(n1422), .B0(n1454), .B1(n1417), .Y(
DP_OP_155J132_124_2038_n106) );
NAND2X1TS U1919 ( .A(Op_MY[14]), .B(Op_MX[16]), .Y(n1418) );
OAI32X1TS U1920 ( .A0(DP_OP_154J132_123_2038_n228), .A1(n1694), .A2(n1691),
.B0(n1418), .B1(DP_OP_154J132_123_2038_n228), .Y(
DP_OP_154J132_123_2038_n229) );
NOR2XLTS U1921 ( .A(n1725), .B(n1706), .Y(n1421) );
NOR2XLTS U1922 ( .A(n1729), .B(n1698), .Y(n1420) );
NOR2XLTS U1923 ( .A(n1712), .B(n1726), .Y(n1419) );
CMPR32X2TS U1924 ( .A(n1421), .B(n1420), .C(n1419), .CO(
DP_OP_154J132_123_2038_n226), .S(DP_OP_154J132_123_2038_n227) );
AOI22X1TS U1925 ( .A0(n1583), .A1(n1591), .B0(n1606), .B1(n1584), .Y(n1452)
);
AO22XLTS U1926 ( .A0(n1456), .A1(n1452), .B0(n1454), .B1(n1422), .Y(
DP_OP_155J132_124_2038_n105) );
OA21XLTS U1927 ( .A0(DP_OP_154J132_123_2038_n73), .A1(n1424), .B0(n1423),
.Y(DP_OP_154J132_123_2038_n72) );
AOI22X1TS U1928 ( .A0(n1527), .A1(n426), .B0(n391), .B1(n1526), .Y(n1436) );
AOI22X1TS U1929 ( .A0(n1531), .A1(n426), .B0(n391), .B1(n1529), .Y(n1443) );
AO22XLTS U1930 ( .A0(n1444), .A1(n1436), .B0(n1442), .B1(n1443), .Y(
DP_OP_153J132_122_5442_n397) );
AOI22X1TS U1931 ( .A0(n426), .A1(n1425), .B0(n1520), .B1(n391), .Y(n1441) );
AO22XLTS U1932 ( .A0(n1444), .A1(n1441), .B0(n1442), .B1(n1427), .Y(
DP_OP_153J132_122_5442_n399) );
NOR2XLTS U1933 ( .A(n1728), .B(n1708), .Y(n1430) );
NOR2XLTS U1934 ( .A(n1692), .B(n1696), .Y(n1429) );
NOR2XLTS U1935 ( .A(n1721), .B(n1699), .Y(n1428) );
CMPR32X2TS U1936 ( .A(n1430), .B(n1429), .C(n1428), .CO(
DP_OP_155J132_124_2038_n324), .S(DP_OP_155J132_124_2038_n325) );
NOR2XLTS U1937 ( .A(n1459), .B(n1468), .Y(n1432) );
NOR2XLTS U1938 ( .A(n1469), .B(n1497), .Y(n1431) );
NOR2X1TS U1939 ( .A(n1467), .B(n1466), .Y(n1465) );
CMPR32X2TS U1940 ( .A(n1432), .B(n1431), .C(n1465), .CO(
DP_OP_153J132_122_5442_n70), .S(DP_OP_153J132_122_5442_n71) );
NOR2XLTS U1941 ( .A(n1727), .B(n1707), .Y(n1435) );
NOR2XLTS U1942 ( .A(n1719), .B(n1697), .Y(n1434) );
NOR2XLTS U1943 ( .A(n394), .B(n1724), .Y(n1433) );
CMPR32X2TS U1944 ( .A(n1435), .B(n1434), .C(n1433), .CO(
DP_OP_155J132_124_2038_n233), .S(DP_OP_155J132_124_2038_n234) );
AO22XLTS U1945 ( .A0(n1444), .A1(n1437), .B0(n1442), .B1(n1436), .Y(
DP_OP_153J132_122_5442_n396) );
INVX2TS U1946 ( .A(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]),
.Y(n1440) );
NOR2XLTS U1947 ( .A(n1459), .B(n1480), .Y(n1439) );
NOR2XLTS U1948 ( .A(n1479), .B(n1497), .Y(n1438) );
CMPR32X2TS U1949 ( .A(n1440), .B(n1439), .C(n1438), .CO(
DP_OP_153J132_122_5442_n59), .S(DP_OP_153J132_122_5442_n60) );
AO22XLTS U1950 ( .A0(n1444), .A1(n1443), .B0(n1442), .B1(n1441), .Y(
DP_OP_153J132_122_5442_n398) );
NOR2XLTS U1951 ( .A(n1446), .B(n1445), .Y(n1450) );
NOR2XLTS U1952 ( .A(n1448), .B(n1447), .Y(n1449) );
AOI22X1TS U1953 ( .A0(n419), .A1(n1589), .B0(n1604), .B1(n1584), .Y(n1453)
);
AO22XLTS U1954 ( .A0(n1456), .A1(n1453), .B0(n1454), .B1(n1452), .Y(
DP_OP_155J132_124_2038_n104) );
AO22XLTS U1955 ( .A0(n1456), .A1(n1455), .B0(n1454), .B1(n1453), .Y(
DP_OP_155J132_124_2038_n103) );
AOI22X1TS U1956 ( .A0(n1580), .A1(n1574), .B0(n1573), .B1(n1577), .Y(n1458)
);
INVX2TS U1957 ( .A(n1572), .Y(n1570) );
AOI22X1TS U1958 ( .A0(n1551), .A1(n1570), .B0(n1572), .B1(n1550), .Y(n1542)
);
OAI22X1TS U1959 ( .A0(n436), .A1(n1554), .B0(n1553), .B1(n1542), .Y(n1457)
);
CMPR32X2TS U1960 ( .A(DP_OP_154J132_123_2038_n29), .B(n1458), .C(n1457),
.CO(DP_OP_154J132_123_2038_n24), .S(DP_OP_154J132_123_2038_n25) );
OAI31X1TS U1961 ( .A0(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]),
.A1(n1460), .A2(n1459), .B0(DP_OP_153J132_122_5442_n31), .Y(
DP_OP_153J132_122_5442_n32) );
NOR2XLTS U1962 ( .A(n1729), .B(n1706), .Y(n1463) );
NOR2XLTS U1963 ( .A(n1718), .B(n1698), .Y(n1462) );
CMPR32X2TS U1964 ( .A(n1463), .B(n1462), .C(n1461), .CO(
DP_OP_154J132_123_2038_n233), .S(DP_OP_154J132_123_2038_n234) );
OAI32X1TS U1965 ( .A0(DP_OP_153J132_122_5442_n106), .A1(n1468), .A2(n1475),
.B0(n1464), .B1(DP_OP_153J132_122_5442_n106), .Y(
DP_OP_153J132_122_5442_n107) );
AOI21X1TS U1966 ( .A0(n1467), .A1(n1466), .B0(n1465), .Y(n1472) );
NOR2XLTS U1967 ( .A(n1479), .B(n1468), .Y(n1471) );
NOR2XLTS U1968 ( .A(n1469), .B(n1480), .Y(n1470) );
CMPR32X2TS U1969 ( .A(n1472), .B(n1471), .C(n1470), .CO(
DP_OP_153J132_122_5442_n83), .S(DP_OP_153J132_122_5442_n84) );
NOR2XLTS U1970 ( .A(n1474), .B(n1473), .Y(n1478) );
NOR2XLTS U1971 ( .A(n1476), .B(n1475), .Y(n1477) );
CMPR32X2TS U1972 ( .A(DP_OP_153J132_122_5442_n123), .B(n1478), .C(n1477),
.CO(DP_OP_153J132_122_5442_n119), .S(DP_OP_153J132_122_5442_n120) );
OAI32X1TS U1973 ( .A0(DP_OP_153J132_122_5442_n72), .A1(n1480), .A2(n1479),
.B0(Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B1(
DP_OP_153J132_122_5442_n72), .Y(DP_OP_153J132_122_5442_n73) );
NOR4X1TS U1974 ( .A(P_Sgf[16]), .B(P_Sgf[17]), .C(P_Sgf[14]), .D(P_Sgf[15]),
.Y(n1487) );
NOR4X1TS U1975 ( .A(P_Sgf[21]), .B(P_Sgf[18]), .C(P_Sgf[19]), .D(P_Sgf[20]),
.Y(n1486) );
NOR4X1TS U1976 ( .A(P_Sgf[2]), .B(P_Sgf[3]), .C(P_Sgf[4]), .D(P_Sgf[5]), .Y(
n1484) );
NOR4X1TS U1977 ( .A(P_Sgf[10]), .B(P_Sgf[11]), .C(P_Sgf[12]), .D(P_Sgf[13]),
.Y(n1482) );
AND4X1TS U1978 ( .A(n1484), .B(n1483), .C(n1482), .D(n1481), .Y(n1485) );
NAND3XLTS U1979 ( .A(n1487), .B(n1486), .C(n1485), .Y(n1490) );
MXI2X1TS U1980 ( .A(round_mode[0]), .B(round_mode[1]), .S0(n1488), .Y(n1489)
);
OAI211X1TS U1981 ( .A0(round_mode[0]), .A1(round_mode[1]), .B0(n1490), .C0(
n1489), .Y(n1614) );
AOI22X1TS U1982 ( .A0(n1492), .A1(n1491), .B0(n1613), .B1(n1614), .Y(n1493)
);
OAI2BB1X1TS U1983 ( .A0N(n1494), .A1N(n1760), .B0(n1493), .Y(n378) );
OAI22X1TS U1984 ( .A0(n1498), .A1(n1497), .B0(n1496), .B1(n1495), .Y(n1499)
);
XNOR2X1TS U1985 ( .A(n1500), .B(n1499), .Y(DP_OP_153J132_122_5442_n30) );
AOI21X1TS U1986 ( .A0(n1502), .A1(n1501), .B0(DP_OP_153J132_122_5442_n121),
.Y(DP_OP_153J132_122_5442_n122) );
NAND2X1TS U1987 ( .A(n1504), .B(n1503), .Y(n1506) );
AOI21X1TS U1988 ( .A0(n1507), .A1(n1506), .B0(n1505), .Y(
DP_OP_153J132_122_5442_n127) );
NAND2X1TS U1989 ( .A(n1516), .B(n1514), .Y(n1512) );
NAND2X1TS U1990 ( .A(n1509), .B(n1508), .Y(n1511) );
AOI21X1TS U1991 ( .A0(n1512), .A1(n1511), .B0(n1510), .Y(
DP_OP_153J132_122_5442_n261) );
NAND2X1TS U1992 ( .A(n1514), .B(n1513), .Y(n1519) );
NAND2X1TS U1993 ( .A(n1516), .B(n1515), .Y(n1518) );
AOI21X1TS U1994 ( .A0(n1519), .A1(n1518), .B0(n1517), .Y(
DP_OP_153J132_122_5442_n268) );
OAI22X1TS U1995 ( .A0(n1529), .A1(n1523), .B0(n1520), .B1(n1521), .Y(
DP_OP_153J132_122_5442_n392) );
OAI22X1TS U1996 ( .A0(n1524), .A1(n1523), .B0(n1522), .B1(n1521), .Y(
DP_OP_153J132_122_5442_n393) );
AOI22X1TS U1997 ( .A0(n422), .A1(n1525), .B0(n1539), .B1(n420), .Y(n1528) );
OAI22X1TS U1998 ( .A0(n1537), .A1(n421), .B0(n1532), .B1(n1528), .Y(
DP_OP_153J132_122_5442_n404) );
AOI22X1TS U1999 ( .A0(n1527), .A1(n421), .B0(n1530), .B1(n1526), .Y(n1533)
);
OAI22X1TS U2000 ( .A0(n1537), .A1(n1528), .B0(n1532), .B1(n1533), .Y(
DP_OP_153J132_122_5442_n405) );
AOI22X1TS U2001 ( .A0(n1531), .A1(n421), .B0(n1530), .B1(n1529), .Y(n1536)
);
OAI22X1TS U2002 ( .A0(n1537), .A1(n1533), .B0(n1532), .B1(n1536), .Y(
DP_OP_153J132_122_5442_n406) );
AOI21X1TS U2003 ( .A0(n1539), .A1(n1538), .B0(DP_OP_153J132_122_5442_n412),
.Y(DP_OP_153J132_122_5442_n413) );
AOI21X1TS U2004 ( .A0(n1541), .A1(n1540), .B0(DP_OP_154J132_123_2038_n61),
.Y(DP_OP_154J132_123_2038_n62) );
AOI21X1TS U2005 ( .A0(n1716), .A1(n1709), .B0(DP_OP_154J132_123_2038_n319),
.Y(DP_OP_154J132_123_2038_n320) );
AOI21X1TS U2006 ( .A0(n408), .A1(n1693), .B0(DP_OP_154J132_123_2038_n326),
.Y(DP_OP_154J132_123_2038_n327) );
INVX2TS U2007 ( .A(n1573), .Y(n1556) );
AOI22X1TS U2008 ( .A0(n1551), .A1(n1556), .B0(n1573), .B1(n1550), .Y(n1543)
);
OAI22X1TS U2009 ( .A0(n1554), .A1(n1542), .B0(n1553), .B1(n1543), .Y(
DP_OP_154J132_123_2038_n103) );
AOI22X1TS U2010 ( .A0(n1551), .A1(n1558), .B0(n1574), .B1(n1550), .Y(n1545)
);
OAI22X1TS U2011 ( .A0(n1545), .A1(n1553), .B0(n1554), .B1(n1543), .Y(
DP_OP_154J132_123_2038_n104) );
AOI22X1TS U2012 ( .A0(n1551), .A1(n1544), .B0(n1575), .B1(n1550), .Y(n1547)
);
OAI22X1TS U2013 ( .A0(n1545), .A1(n1554), .B0(n1547), .B1(n1553), .Y(
DP_OP_154J132_123_2038_n105) );
AOI22X1TS U2014 ( .A0(n1551), .A1(n1546), .B0(n1576), .B1(n1550), .Y(n1549)
);
OAI22X1TS U2015 ( .A0(n1547), .A1(n1554), .B0(n1549), .B1(n1553), .Y(
DP_OP_154J132_123_2038_n106) );
AOI22X1TS U2016 ( .A0(n1551), .A1(n1548), .B0(n1578), .B1(n1550), .Y(n1555)
);
OAI22X1TS U2017 ( .A0(n1549), .A1(n1554), .B0(n1555), .B1(n1553), .Y(
DP_OP_154J132_123_2038_n107) );
AOI22X1TS U2018 ( .A0(n1565), .A1(n1551), .B0(n1550), .B1(n1579), .Y(n1552)
);
OAI22X1TS U2019 ( .A0(n1555), .A1(n1554), .B0(n1553), .B1(n1552), .Y(
DP_OP_154J132_123_2038_n108) );
AOI22X1TS U2020 ( .A0(n1563), .A1(n1572), .B0(n1570), .B1(n406), .Y(n1557)
);
OAI22X1TS U2021 ( .A0(n1557), .A1(n1567), .B0(n1564), .B1(n1569), .Y(
DP_OP_154J132_123_2038_n111) );
AOI22X1TS U2022 ( .A0(n1563), .A1(n1573), .B0(n1556), .B1(n406), .Y(n1559)
);
OAI22X1TS U2023 ( .A0(n1557), .A1(n1569), .B0(n1559), .B1(n1567), .Y(
DP_OP_154J132_123_2038_n112) );
AOI22X1TS U2024 ( .A0(n1563), .A1(n1574), .B0(n1558), .B1(n406), .Y(n1562)
);
OAI22X1TS U2025 ( .A0(n1559), .A1(n1569), .B0(n1567), .B1(n1562), .Y(
DP_OP_154J132_123_2038_n113) );
AOI22X1TS U2026 ( .A0(n1565), .A1(n1564), .B0(n1563), .B1(n1579), .Y(n1566)
);
OAI22X1TS U2027 ( .A0(n1569), .A1(n1568), .B0(n1567), .B1(n1566), .Y(
DP_OP_154J132_123_2038_n117) );
AOI21X1TS U2028 ( .A0(n1571), .A1(n1570), .B0(DP_OP_154J132_123_2038_n119),
.Y(DP_OP_154J132_123_2038_n120) );
AOI22X1TS U2029 ( .A0(n1580), .A1(n1573), .B0(n1572), .B1(n1577), .Y(
DP_OP_154J132_123_2038_n94) );
AOI22X1TS U2030 ( .A0(n1580), .A1(n1575), .B0(n1574), .B1(n1577), .Y(
DP_OP_154J132_123_2038_n96) );
AOI22X1TS U2031 ( .A0(n1580), .A1(n1576), .B0(n1575), .B1(n1577), .Y(
DP_OP_154J132_123_2038_n97) );
AOI22X1TS U2032 ( .A0(n1580), .A1(n1578), .B0(n1576), .B1(n1577), .Y(
DP_OP_154J132_123_2038_n98) );
AOI22X1TS U2033 ( .A0(n1580), .A1(n1579), .B0(n1578), .B1(n1577), .Y(
DP_OP_154J132_123_2038_n99) );
AOI21X1TS U2034 ( .A0(n1582), .A1(n1581), .B0(DP_OP_155J132_124_2038_n61),
.Y(DP_OP_155J132_124_2038_n62) );
AOI22X1TS U2035 ( .A0(n1597), .A1(n1584), .B0(n419), .B1(n1612), .Y(n1585)
);
OAI22X1TS U2036 ( .A0(n1588), .A1(n1587), .B0(n1586), .B1(n1585), .Y(
DP_OP_155J132_124_2038_n108) );
AOI22X1TS U2037 ( .A0(n410), .A1(n1605), .B0(n1603), .B1(n442), .Y(n1590) );
OAI22X1TS U2038 ( .A0(n1601), .A1(n409), .B0(n1599), .B1(n1590), .Y(
DP_OP_155J132_124_2038_n111) );
AOI22X1TS U2039 ( .A0(n1596), .A1(n1604), .B0(n1589), .B1(n442), .Y(n1592)
);
OAI22X1TS U2040 ( .A0(n1601), .A1(n1590), .B0(n1599), .B1(n1592), .Y(
DP_OP_155J132_124_2038_n112) );
AOI22X1TS U2041 ( .A0(n1596), .A1(n1606), .B0(n1591), .B1(n442), .Y(n1595)
);
OAI22X1TS U2042 ( .A0(n1601), .A1(n1592), .B0(n1599), .B1(n1595), .Y(
DP_OP_155J132_124_2038_n113) );
AOI22X1TS U2043 ( .A0(n1597), .A1(n409), .B0(n1596), .B1(n1612), .Y(n1598)
);
OAI22X1TS U2044 ( .A0(n1601), .A1(n1600), .B0(n1599), .B1(n1598), .Y(
DP_OP_155J132_124_2038_n117) );
AOI21X1TS U2045 ( .A0(n1603), .A1(n1602), .B0(DP_OP_155J132_124_2038_n119),
.Y(DP_OP_155J132_124_2038_n120) );
OAI22X1TS U2046 ( .A0(n1605), .A1(n1609), .B0(n1604), .B1(n1611), .Y(
DP_OP_155J132_124_2038_n94) );
OAI22X1TS U2047 ( .A0(n1607), .A1(n1611), .B0(n1606), .B1(n1609), .Y(
DP_OP_155J132_124_2038_n96) );
OAI22X1TS U2048 ( .A0(n1607), .A1(n1609), .B0(n1608), .B1(n1611), .Y(
DP_OP_155J132_124_2038_n97) );
OAI22X1TS U2049 ( .A0(n1608), .A1(n1609), .B0(n1610), .B1(n1611), .Y(
DP_OP_155J132_124_2038_n98) );
OAI22X1TS U2050 ( .A0(n1612), .A1(n1611), .B0(n1610), .B1(n1609), .Y(
DP_OP_155J132_124_2038_n99) );
INVX2TS U2051 ( .A(n1613), .Y(n1615) );
CLKBUFX2TS U2052 ( .A(n1003), .Y(n1647) );
INVX2TS U2053 ( .A(n1003), .Y(n1644) );
OAI211XLTS U2054 ( .A0(Sgf_normalized_result[3]), .A1(n1617), .B0(n1644),
.C0(n1616), .Y(n1618) );
OAI2BB1X1TS U2055 ( .A0N(Add_result[3]), .A1N(n1647), .B0(n1618), .Y(n306)
);
OAI211XLTS U2056 ( .A0(Sgf_normalized_result[5]), .A1(n1620), .B0(n1644),
.C0(n1619), .Y(n1621) );
OAI2BB1X1TS U2057 ( .A0N(Add_result[5]), .A1N(n1647), .B0(n1621), .Y(n304)
);
OAI2BB1X1TS U2058 ( .A0N(Add_result[7]), .A1N(n1651), .B0(n1624), .Y(n302)
);
OAI2BB1X1TS U2059 ( .A0N(Add_result[9]), .A1N(n1651), .B0(n1627), .Y(n300)
);
OAI2BB1X1TS U2060 ( .A0N(Add_result[11]), .A1N(n1651), .B0(n1630), .Y(n298)
);
OAI2BB1X1TS U2061 ( .A0N(Add_result[13]), .A1N(n1651), .B0(n1633), .Y(n296)
);
OAI2BB1X1TS U2062 ( .A0N(Add_result[15]), .A1N(n1651), .B0(n1636), .Y(n294)
);
OAI2BB1X1TS U2063 ( .A0N(Add_result[17]), .A1N(n1651), .B0(n1639), .Y(n292)
);
OAI2BB1X1TS U2064 ( .A0N(Add_result[19]), .A1N(n1647), .B0(n1642), .Y(n290)
);
OAI2BB1X1TS U2065 ( .A0N(Add_result[21]), .A1N(n1647), .B0(n1646), .Y(n288)
);
OAI2BB1X1TS U2066 ( .A0N(Add_result[23]), .A1N(n1651), .B0(n1650), .Y(n286)
);
OAI21XLTS U2067 ( .A0(n1654), .A1(n1653), .B0(n1652), .Y(n1655) );
AOI22X1TS U2068 ( .A0(n1680), .A1(n1732), .B0(n1655), .B1(n1678), .Y(n281)
);
OAI21XLTS U2069 ( .A0(n1658), .A1(n1657), .B0(n1656), .Y(n1659) );
AOI22X1TS U2070 ( .A0(n1680), .A1(n1733), .B0(n1659), .B1(n1678), .Y(n279)
);
CLKAND2X2TS U2071 ( .A(n1663), .B(n1664), .Y(n1666) );
OAI21XLTS U2072 ( .A0(n1661), .A1(n1666), .B0(n1660), .Y(n1662) );
AOI22X1TS U2073 ( .A0(n1680), .A1(n1734), .B0(n1662), .B1(n1678), .Y(n277)
);
OAI2BB2XLTS U2074 ( .B0(n1666), .B1(n1665), .A0N(n1686), .A1N(P_Sgf[38]),
.Y(n276) );
CMPR32X2TS U2075 ( .A(DP_OP_156J132_125_3370_n132), .B(n1668), .C(n1667),
.CO(n1352), .S(n1669) );
AOI22X1TS U2076 ( .A0(n1680), .A1(n1735), .B0(n1669), .B1(n1678), .Y(n271)
);
AOI21X1TS U2077 ( .A0(n1671), .A1(DP_OP_154J132_123_2038_n86), .B0(n1670),
.Y(n1672) );
XNOR2X1TS U2078 ( .A(n1673), .B(n1672), .Y(n1674) );
AOI22X1TS U2079 ( .A0(n1680), .A1(n1736), .B0(n1674), .B1(n1678), .Y(n265)
);
CMPR32X2TS U2080 ( .A(n1677), .B(n1676), .C(n1675), .CO(n1191), .S(n1679) );
AOI22X1TS U2081 ( .A0(n1680), .A1(n1737), .B0(n1679), .B1(n1678), .Y(n263)
);
OAI211XLTS U2082 ( .A0(n1684), .A1(n1683), .B0(n1682), .C0(n1681), .Y(n1685)
);
OAI2BB1X1TS U2083 ( .A0N(P_Sgf[12]), .A1N(n1686), .B0(n1685), .Y(n250) );
OA22X1TS U2084 ( .A0(n1689), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n1687), .Y(n177) );
CLKBUFX2TS U2085 ( .A(n1687), .Y(n1688) );
OA22X1TS U2086 ( .A0(n1689), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n1688), .Y(n176) );
OA22X1TS U2087 ( .A0(n1689), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n1688), .Y(n175) );
OA22X1TS U2088 ( .A0(n1689), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n1688), .Y(n174) );
OA22X1TS U2089 ( .A0(n1689), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n1688), .Y(n173) );
OA22X1TS U2090 ( .A0(n1689), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n1688), .Y(n172) );
OA22X1TS U2091 ( .A0(n1689), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n1688), .Y(n171) );
OA22X1TS U2092 ( .A0(n1689), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n1688), .Y(n170) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_noclk.tcl_RKOA_1STAGE_syn.sdf");
endmodule
|
`timescale 1ns/1ps
module SPIFSM #(
parameter SPPRWidth = 4,
parameter SPRWidth = 4,
parameter DataWidth = 8
) (
input Reset_n_i,
input Clk_i,
// FSM control
input Start_i,
output reg Done_o,
output reg [DataWidth-1:0] Byte0_o,
output reg [DataWidth-1:0] Byte1_o,
// to/from SPI_Master
input SPI_Transmission_i,
output reg SPI_Write_o,
output reg SPI_ReadNext_o,
output reg [DataWidth-1:0] SPI_Data_o,
input [DataWidth-1:0] SPI_Data_i,
input SPI_FIFOFull_i,
input SPI_FIFOEmpty_i,
// to ADT7310
output reg ADT7310CS_n_o,
// parameters
input [31:0] ParamCounterPreset_i
);
// SPI FSM
localparam stIdle = 4'b0000;
localparam stWriteValue = 4'b0001;
localparam stWaitSent = 4'b0010;
localparam stConsume1 = 4'b0011;
localparam stWait = 4'b0100;
localparam stWriteDummy1= 4'b0101;
localparam stWriteDummy2= 4'b0110;
localparam stRead1 = 4'b0111;
localparam stRead2 = 4'b1000;
localparam stRead3 = 4'b1001;
localparam stPause = 4'b1010;
reg [3:0] SPI_FSM_State;
reg [3:0] SPI_FSM_NextState;
wire SPI_FSM_TimerOvfl;
reg SPI_FSM_TimerPreset;
reg SPI_FSM_TimerEnable;
reg SPI_FSM_Wr1;
reg SPI_FSM_Wr0;
/////////////////////////////////////////////////////////////////////////////
// FSM //////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SPI_FSM_State <= stIdle;
end
else
begin
SPI_FSM_State <= SPI_FSM_NextState;
end
end
always @(SPI_FSM_State, Start_i, SPI_Transmission_i, SPI_FSM_TimerOvfl)
begin // process SPI_FSM_CombProc
SPI_FSM_NextState = SPI_FSM_State;
// control signal default values
ADT7310CS_n_o = 1'b1;
SPI_Data_o = 8'bxxxxxxxx; // most time we don't care which value is set
SPI_Write_o = 1'b0;
SPI_ReadNext_o = 1'b0;
SPI_FSM_TimerPreset = 1'b1;
SPI_FSM_TimerEnable = 1'b0;
SPI_FSM_Wr1 = 1'b0;
SPI_FSM_Wr0 = 1'b0;
Done_o = 1'b1;
// next state and output logic
case (SPI_FSM_State)
stIdle: begin
if (Start_i == 1'b1)
begin
// single-shot measurement mode: write to 8-bit configuration
// register (0x01): send 0x08 0x20 (one shot mode)
SPI_FSM_NextState = stWriteValue;
ADT7310CS_n_o = 1'b0;
SPI_Data_o = 8'h08;
SPI_Write_o = 1'b1;
Done_o = 1'b0;
end
end
stWriteValue: begin
SPI_FSM_NextState = stWaitSent;
ADT7310CS_n_o = 1'b0;
// send 0x20
SPI_Data_o = 8'h20;
SPI_Write_o = 1'b1;
Done_o = 1'b0;
end
stWaitSent: begin
// wait until SPI transmission has finished
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
if (SPI_Transmission_i == 1'b0)
begin
SPI_FSM_NextState = stConsume1;
SPI_ReadNext_o = 1'b1; // consume first received value
end
end
stConsume1: begin
SPI_FSM_NextState = stWait;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_ReadNext_o = 1'b1; // consume second received value
SPI_FSM_TimerPreset = 1'b0;
SPI_FSM_TimerEnable = 1'b1; // start timer
end
stWait: begin
// wait for 240ms
ADT7310CS_n_o = 1'b1;
Done_o = 1'b0;
if (SPI_FSM_TimerOvfl == 1'b0)
begin
SPI_FSM_TimerPreset = 1'b0;
SPI_FSM_TimerEnable = 1'b1; // timer running
end
else
begin
// timer overflow -> continue: send read command and two dummy bytes
ADT7310CS_n_o = 1'b0;
SPI_FSM_NextState = stWriteDummy1;
SPI_Data_o = 8'h50;
SPI_Write_o = 1'b1;
end
end
stWriteDummy1: begin
SPI_FSM_NextState = stWriteDummy2;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_Data_o = 8'hFF;
SPI_Write_o = 1'b1;
end
stWriteDummy2: begin
SPI_FSM_NextState = stRead1;
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
SPI_Data_o = 8'hFF;
SPI_Write_o = 1'b1;
end
stRead1: begin
ADT7310CS_n_o = 1'b0;
Done_o = 1'b0;
// wait until SPI transmission has finished
if (SPI_Transmission_i == 1'b0) begin
SPI_FSM_NextState = stRead2;
// consume and ignore first byte
SPI_ReadNext_o = 1'b1;
end
end
stRead2: begin
Done_o = 1'b0;
// consume and store second byte
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr1 = 1'b1;
SPI_FSM_NextState = stRead3;
end
stRead3: begin
Done_o = 1'b0;
// consume and store third byte
SPI_ReadNext_o = 1'b1;
SPI_FSM_Wr0 = 1'b1;
SPI_FSM_NextState = stPause;
end
stPause: begin
SPI_FSM_NextState = stIdle;
end
default: begin
end
endcase
end
/////////////////////////////////////////////////////////////////////////////
// Byte-wide Memory /////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
Byte0_o <= 8'd0;
Byte1_o <= 8'd0;
end
else
begin
if (SPI_FSM_Wr0)
begin
Byte0_o <= SPI_Data_i;
end
if (SPI_FSM_Wr1)
begin
Byte1_o <= SPI_Data_i;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Word Arithmetic //////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
reg [31:0] SPI_FSM_Timer;
always @(negedge Reset_n_i or posedge Clk_i)
begin
if (!Reset_n_i)
begin
SPI_FSM_Timer <= 32'd0;
end
else
begin
if (SPI_FSM_TimerPreset)
begin
SPI_FSM_Timer <= ParamCounterPreset_i;
end
else if (SPI_FSM_TimerEnable)
begin
SPI_FSM_Timer <= SPI_FSM_Timer - 1'b1;
end
end
end
assign SPI_FSM_TimerOvfl = (SPI_FSM_Timer == 0) ? 1'b1 : 1'b0;
endmodule // SPIFSM
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// sign_extender.v
// Created: 5.16.2012
// Modified: 5.16.2012
//
// Generic sign extension module
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module sign_extender
#(
parameter
INPUT_WIDTH = 8,
OUTPUT_WIDTH = 16
)
(
input [INPUT_WIDTH-1:0] original,
output reg [OUTPUT_WIDTH-1:0] sign_extended_original
);
wire [OUTPUT_WIDTH-INPUT_WIDTH-1:0] sign_extend;
generate
genvar i;
for (i = 0; i < OUTPUT_WIDTH-INPUT_WIDTH; i = i + 1) begin : gen_sign_extend
assign sign_extend[i] = (original[INPUT_WIDTH-1]) ? 1'b1 : 1'b0;
end
endgenerate
always @ * begin
sign_extended_original = {sign_extend,original};
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Packed Stipple Area BLT State Machine
// File : dex_smlablt.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Included by dex_sm.v
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module dex_smlablt
(
input de_clk,
input de_rstn,
input goblt,
input stpl_pk_1,
input apat_1,
input mcrdy,
input cache_rdy,
input signx,
input signy,
input yeqz,
input xeqz,
input [2:0] clp_status,
input apat32_2,
input rmw,
input read_2,
input mw_fip,
input local_eol,
output reg [21:0] lab_op,
output reg [4:0] lab_ksel,
output reg lab_set_busy,
output reg lab_clr_busy,
output reg lab_ld_wcnt,
output reg lab_mem_req,
output reg lab_mem_rd,
output reg lab_dchgy,
output reg lab_rstn_wad,
output reg lab_ld_rad,
output reg lab_set_sol,
output reg lab_set_eol,
output reg lab_ld_msk,
output reg lab_mul,
output reg lab_set_local_eol,
output reg lab_clr_local_eol,
output reg lab_rst_cr
);
// These parameters were formerly included by de_param.h
//`include "de_param.h"
parameter one = 5'h1,
LAB_WAIT = 5'h0,
LABS1 = 5'h1,
LABS2 = 5'h2,
LABS3 = 5'h3,
LABS4 = 5'h4,
LABS5 = 5'h5,
LABR1 = 5'h6,
LABR2 = 5'h7,
LABR3 = 5'h8,
LABW1 = 5'h9,
LABW2 = 5'ha,
LABW3 = 5'hb,
LABW4 = 5'hc,
LABNL1 = 5'hd,
LABNL2 = 5'he,
LABNL3 = 5'hf,
LABNL4 = 5'h10,
LABS2B = 5'h11,
LABS2C = 5'h12,
LABS2D = 5'h13,
LABS2E = 5'h14,
LABS2F = 5'h15,
LABS2G = 5'h16,
noop = 5'h0, // noop address.
pline = 5'h10, // pipeline address
sorgl = 5'he, // src org address low nibble.
dorgl = 5'hf, // src org address low nibble.
src = 5'h0, // source/start point register
dst = 5'h1, // destination/end point
mov = 5'hd, // bx--> fx, by--> fy
pix_dstx = 5'h5, // wrk3x
wrhi = 2'b01, // define write enables
wrlo = 2'b10, // define write enables
wrhl = 2'b00, // define write enables
wrno = 2'b11, // define write enables
addnib = 5'h2, // ax + bx(nibble)
dst_sav = 5'h9, // dst & wrk1y
add = 5'h1, // ax + bx, ay + by
size = 5'h2, // wrk0x and wrk0y
sav_dst = 5'h4,
xend_pc = 5'h09,
xmin_pc = 5'h0a,
xmax_pc = 5'h0b,
sub = 5'h12, // ax - bx, ay - by
amcn = 5'h4, // ax-k, ay-k
amcn_d = 5'h14, // {ax - const,ax - const}
zero = 5'h0,
four = 5'h4,
div16 = 5'ha, // bx/16 + wadj.
wr_wrds_sav = 5'hc, // wrk4x & wrk6x
mov_k = 5'he, // move constant.
eight = 5'h6,
wr_wrds = 5'h6, // wrk4x
sav_src_dst = 5'h3, // wrk1x & wrk1y
movx = 5'hf, // bx--> fy, by--> fx
apcn = 5'h6, // ax+k, ay+k
D64 = 5'h11,
D128 = 5'h15,
sav_wr_wrds = 5'h8; // wrk6x
/****************************************************************/
/* DEFINE PARAMETERS */
/****************************************************************/
/* define internal wires and make assignments */
reg [4:0] lab_cs;
reg [4:0] lab_ns;
/* create the state register */
always @(posedge de_clk or negedge de_rstn)
begin
if(!de_rstn)lab_cs <= 0;
else lab_cs <= lab_ns;
end
always @*
begin
lab_op = 22'b00000_00000_00000_00000_11;
lab_ksel = one;
lab_set_busy = 1'b0;
lab_clr_busy = 1'b0;
lab_ld_wcnt = 1'b0;
lab_mem_req = 1'b0;
lab_mem_rd = 1'b0;
lab_dchgy = 1'b0;
lab_rstn_wad = 1'b0;
lab_ld_rad = 1'b0;
lab_set_sol = 1'b0;
lab_set_eol = 1'b0;
lab_mem_req = 1'b0;
lab_mem_rd = 1'b0;
lab_ld_msk = 1'b0;
lab_mul = 1'b0;
lab_set_local_eol = 1'b0;
lab_clr_local_eol = 1'b0;
lab_rst_cr = 1'b0;
case(lab_cs) /* synopsys full_case parallel_case */
/* if goblt and stipple and area pattern begin. */
/* ELSE wait. */
LAB_WAIT:if(goblt && (stpl_pk_1 && apat_1))
begin
lab_ns=LABS1;
lab_op={noop,dst,mov,pix_dstx,wrhi};
lab_set_busy = 1'b1;
lab_mul = 1'b1;
end
else lab_ns= LAB_WAIT;
/* multiply the src, dst, and size by 2 for 16BPP, or 4 for 32BPP. */
/* add org low nibble to destination point */
/* save the original destination X, to use on the next scan line. */
LABS1: begin
lab_ns=LABS2;
lab_op={dorgl,dst,addnib,dst_sav,wrhl};
end
LABS2: begin
lab_ns=LABS2B;
lab_op={sorgl,src,add,src,wrhi};
end
LABS2B: begin
lab_ns=LABS2C;
lab_op={noop,size,mov,sav_dst,wrlo};
end
LABS2C: begin
if(clp_status[2]) // trivial reject.
begin
lab_clr_busy = 1'b1;
lab_rst_cr = 1'b1;
lab_ns=LAB_WAIT;
end
else if(clp_status==3'b000)lab_ns=LABS3; // No clipping.
else if(clp_status==3'b011)
begin
lab_op={xend_pc,xmax_pc,sub,noop,wrno};
lab_ns=LABS2F;
end
else begin
lab_op={xmin_pc,dst,sub,noop,wrno};
lab_ns=LABS2D;
end
end
LABS2D: begin
lab_op={size,pline,sub,size,wrhi};
if(clp_status==3'b001)lab_ns=LABS2G;
else lab_ns=LABS2E;
end
LABS2E: begin
lab_op={xend_pc,xmax_pc,sub,noop,wrno};
lab_ns=LABS2F;
end
LABS2F: begin
lab_op={size,pline,sub,size,wrhi};
if(clp_status==3'b011)lab_ns=LABS3;
else lab_ns=LABS2G;
end
LABS2G: begin
lab_op={xmin_pc,noop,amcn_d,dst_sav,wrhl};
lab_ksel=zero;
lab_ns=LABS3;
end
/* calculate the write words per line adjusted X size. */
LABS3: begin
lab_ns=LABS4;
lab_set_sol=1'b1;
if(clp_status==3'b000)lab_op={dst,size,div16,wr_wrds_sav,wrhi};
else if(clp_status==3'b011) lab_op={dst,pline,div16,wr_wrds_sav,wrhi};
else lab_op={pline,size,div16,wr_wrds_sav,wrhi};
end
/* generate the start and end mask to be loaded in LABS5. */
LABS4: begin
lab_ns=LABS5;
lab_op={dst,size,add,noop,wrno};
lab_rstn_wad = 1'b1;
end
/* source minus destination nibble mode. for FIFO ADDRESS read = write, read = write-1. */
/* this will set the first read 8 flag if source nibble is less than destination nibble.*/
LABS5: begin
lab_ns=LABR1;
lab_ld_msk=1'b1; /* load the mask generated in LABS4. */
lab_op={noop,pix_dstx,mov,noop,wrno};
lab_ld_rad = 1'b1;
end
/* load the one and only read page count. */
LABR1: begin
lab_ld_wcnt=1'b1; /* this signal is externally delayed one clock. */
lab_op={noop,noop,mov_k,noop,wrno};
if(apat32_2)lab_ksel=eight;
else lab_ksel=one;
lab_ns=LABR2;
end
LABR2: lab_ns=LABR3;
/* request the read cycles. */
LABR3: begin
lab_op={wr_wrds,noop,amcn,noop,wrno};
if(!rmw)lab_ksel=eight;
else lab_ksel=four;
/* if source fetch disable skip the read. */
if(!read_2)lab_ns=LABW1;
else if(mcrdy && !mw_fip)
begin
lab_mem_req=1'b1;
lab_mem_rd=1'b1;
lab_ns=LABW1;
end
else lab_ns=LABR3;
end
/* wait for the pipeline. */
LABW1: begin
lab_ns=LABW2;
if(!rmw)lab_ksel=eight;
else lab_ksel=four;
lab_op={wr_wrds,noop,amcn,wr_wrds,wrhi};
end
/* Begin the write portion of the stretch bit blt state machine. */
LABW2: begin
lab_ld_wcnt=1'b1;
lab_ns=LABW3;
if(!rmw)lab_ksel=eight;
else lab_ksel=four;
if(signx | xeqz)begin
lab_op={noop,wr_wrds,mov,noop,wrno};
lab_set_eol=1'b1;
lab_set_local_eol=1'b1;
end
else lab_op={noop,noop,mov_k,noop,wrno};
end
/* add 128 to the destination x pointer. */
LABW3: begin
if(local_eol && mcrdy && cache_rdy)
begin
lab_op={noop,sav_src_dst,movx,dst,wrhi};
lab_ns=LABW4;
end
else if(mcrdy && cache_rdy)
begin
lab_op={dst,noop,apcn,dst,wrhi};
lab_ns=LABW4;
end
else lab_ns=LABW3;
if(rmw)lab_ksel=D64;
else lab_ksel=D128;
end
LABW4: begin
if(local_eol)
begin
lab_op={noop,sav_src_dst,movx,dst,wrhi};
lab_mem_req=1'b1;
lab_clr_local_eol=1'b1;
lab_ns=LABNL1;
end
else
begin
lab_op={wr_wrds,noop,amcn,noop,wrno};
if(!rmw)lab_ksel=eight;
else lab_ksel=four;
lab_mem_req=1'b1;
lab_ns=LABW1;
end
end
/* decrement the Y size register. */
LABNL1: begin
lab_op={size,noop,amcn,size,wrlo};
lab_set_sol=1'b1;
lab_dchgy = 1'b1;
lab_ns=LABNL2;
end
/* restore the write words per line. */
LABNL2: begin
lab_op={noop,sav_wr_wrds,mov,wr_wrds,wrhi};
lab_ns=LABNL3;
end
/* If Y size register goes to zero the bit blt is all done. */
/* Restore the original X destination registers. */
LABNL3: begin
if(!rmw)lab_ksel=eight;
else lab_ksel=four;
if(yeqz)
begin
lab_clr_busy = 1'b1;
lab_rst_cr = 1'b1;
lab_ns=LAB_WAIT;
end
else begin
lab_ns=LABW1;
lab_op={pline,noop,amcn,noop,wrno};
end
end
LABNL4:
begin
lab_op={dst,pline,sub,dst,wrlo};
lab_ns=LABS3;
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/27/2016 08:26:13 AM
// Design Name:
// Module Name: Mux_8x1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux_8x1
(
//Input Signals
input wire [2:0] select,
input wire [7:0] ch_0,
input wire [7:0] ch_1,
input wire [7:0] ch_2,
input wire [7:0] ch_3,
input wire [7:0] ch_4,
input wire [7:0] ch_5,
input wire [7:0] ch_6,
input wire [7:0] ch_7,
//Output Signals
output reg [7:0] data_out
);
always @*
begin
case(select)
3'b111: data_out = ch_0;
3'b110: data_out = ch_1;
3'b101: data_out = ch_2;
3'b100: data_out = ch_3;
3'b011: data_out = ch_4;
3'b010: data_out = ch_5;
3'b001: data_out = ch_6;
3'b000: data_out = ch_7;
default : data_out = ch_0;
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:09 07/10/2009
// Design Name:
// Module Name: spi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1]) begin
byte_data_received <= {byte_data_received[6:0], MOSI};
end
if(~SSELSCKr[1] && bitcnt==3'b111) byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive) begin
byte_cnt_r <= 16'h0000;
end else if(byte_received_sync) begin
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v1_x_ddr_if_post_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Extends the depth of a PHASER IN_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_if_post_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input [3:0] empty_in,
input rd_en_in,
input [WIDTH-1:0] d_in, // write data from controller
output empty_out,
output byte_rd_en,
output [WIDTH-1:0] d_out // write data to OUT_FIFO
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
(((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx);
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1];
(* max_fanout = 40 *) reg [4:0] my_empty /* synthesis syn_maxfan = 3 */;
(* max_fanout = 40 *) reg [1:0] my_full /* synthesis syn_maxfan = 3 */;
reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
// Register duplication to reduce the fan out
(* KEEP = "TRUE" *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
wire [WIDTH-1:0] mem_out;
(* max_fanout = 40 *) wire wr_en /* synthesis syn_maxfan = 10 */;
task updt_ptrs;
input rd;
input wr;
reg [1:0] next_rd_ptr;
reg [1:0] next_wr_ptr;
begin
next_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
next_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
casez ({rd, wr, my_empty[1], my_full[1]})
4'b00zz: ; // No access, do nothing
4'b0100: begin
// Write when neither empty, nor full; check for full
wr_ptr <= #TCQ next_wr_ptr;
my_full[0] <= #TCQ (next_wr_ptr == rd_ptr);
my_full[1] <= #TCQ (next_wr_ptr == rd_ptr);
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0110: begin
// Write when empty; no need to check for full
wr_ptr <= #TCQ next_wr_ptr;
my_empty <= #TCQ 5'b00000;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b1000: begin
// Read when neither empty, nor full; check for empty
rd_ptr <= #TCQ next_rd_ptr;
rd_ptr_timing <= #TCQ next_rd_ptr;
my_empty[0] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[1] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[2] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[3] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[4] <= #TCQ (next_rd_ptr == wr_ptr);
end
4'b1001: begin
// Read when full; no need to check for empty
rd_ptr <= #TCQ next_rd_ptr;
rd_ptr_timing <= #TCQ next_rd_ptr;
my_full[0] <= #TCQ 1'b0;
my_full[1] <= #TCQ 1'b0;
end
4'b1100, 4'b1101, 4'b1110: begin
// Read and write when empty, full, or neither empty/full; no need
// to check for empty or full conditions
rd_ptr <= #TCQ next_rd_ptr;
rd_ptr_timing <= #TCQ next_rd_ptr;
wr_ptr <= #TCQ next_wr_ptr;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0101, 4'b1010: ;
// Read when empty, Write when full; Keep all pointers the same
// and don't change any of the flags (i.e. ignore the read/write).
// This might happen because a faulty DQS_FOUND calibration could
// result in excessive skew between when the various IN_FIFO's
// first become not empty. In this case, the data going to each
// post-FIFO/IN_FIFO should be read out and discarded
// synthesis translate_off
default: begin
// Covers any other cases, in particular for simulation if
// any signals are X's
$display("ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b",
$time, rd, wr, my_empty[1], my_full[1]);
rd_ptr <= #TCQ 2'bxx;
rd_ptr_timing <= #TCQ 2'bxx;
wr_ptr <= #TCQ 2'bxx;
end
// synthesis translate_on
endcase
end
endtask
assign d_out = my_empty[4] ? d_in : mem_out;//mem[rd_ptr];
// The combined IN_FIFO + post FIFO is only "empty" when both are empty
assign empty_out = empty_in[0] & my_empty[0];
assign byte_rd_en = !empty_in[3] || !my_empty[3];
always @(posedge clk)
if (rst) begin
my_empty <= #TCQ 5'b11111;
my_full <= #TCQ 2'b00;
rd_ptr <= #TCQ 'b0;
rd_ptr_timing <= #TCQ 'b0;
wr_ptr <= #TCQ 'b0;
end else begin
// Special mode: If IN_FIFO has data, and controller is reading at
// the same time, then operate post-FIFO in "passthrough" mode (i.e.
// don't update any of the read/write pointers, and route IN_FIFO
// data to post-FIFO data)
if (my_empty[1] && !my_full[1] && rd_en_in && !empty_in[1]) ;
else
// Otherwise, we're writing to FIFO when IN_FIFO is not empty,
// and reading from the FIFO based on the rd_en_in signal (read
// enable from controller). The functino updt_ptrs should catch
// an illegal conditions.
updt_ptrs(rd_en_in, !empty_in[1]);
end
assign wr_en = (!empty_in[2] & ((!rd_en_in & !my_full[0]) |
(rd_en_in & !my_empty[2])));
always @ (posedge clk)
begin
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
end
assign mem_out = mem[rd_ptr_timing];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DLRTP_BLACKBOX_V
`define SKY130_FD_SC_MS__DLRTP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DLRTP_BLACKBOX_V
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND3B_2_V
`define SKY130_FD_SC_HDLL__AND3B_2_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3b_2 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and3b_2 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND3B_2_V
|
`default_nettype none
`timescale 1ns / 1ps
`include "asserts.vh"
module sia_txq_tb();
reg story_to, fault_to;
reg clk_i, reset_i;
reg [11:0] dat_i;
reg we_i;
wire txd_o, txc_o, not_full_o, empty_o, idle_o;
sia_txq #(
.SHIFT_REG_WIDTH(12),
.BAUD_RATE_WIDTH(32),
.DEPTH_BITS(2)
) x(
.clk_i(clk_i),
.reset_i(reset_i),
.dat_i(dat_i),
.we_i(we_i),
.bits_i(5'd10), // 8N1
.baud_i(32'd49), // 1Mbps when clocked at 50MHz.
.txcmod_i(3'b100),
.txd_o(txd_o),
.txc_o(txc_o),
.not_full_o(not_full_o),
.empty_o(empty_o),
.idle_o(idle_o)
);
always begin
#10 clk_i <= ~clk_i;
end
`STANDARD_FAULT
`DEFASSERT0(txd, o)
`DEFASSERT0(idle, o)
`DEFASSERT0(empty, o)
`DEFASSERT0(not_full, o)
initial begin
$dumpfile("sia_txq.vcd");
$dumpvars;
{clk_i, reset_i, dat_i, we_i} <= 0;
wait(~clk_i); wait(clk_i); #1;
reset_i <= 1;
wait(~clk_i); wait(clk_i); #1;
reset_i <= 0;
wait(~clk_i); wait(clk_i); #1;
wait(~clk_i); wait(clk_i); #1;
// Write a single value to the queue.
// Transmission should start soon thereafter.
dat_i <= 12'b111_11101101_0;
we_i <= 1;
wait(~clk_i); wait(clk_i); #1;
we_i <= 0;
wait(~clk_i); wait(clk_i); #1;
wait(txc_o); wait(~txc_o);
assert_txd(0);
assert_idle(0);
assert_empty(1); // EMPTY reports FIFO status, not engine status.
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(0);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(0);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
wait(txc_o); wait(~txc_o);
assert_txd(1);
assert_idle(0);
assert_empty(1);
assert_not_full(1);
#1000; // No TXC to wait on, so fake it 'til you make it.
assert_txd(1);
assert_idle(1);
assert_empty(1);
assert_not_full(1);
wait(~clk_i); wait(clk_i); #1;
// Keep writing until we fill the queue. For this test's
// configuration, that should amount to FIVE values.
// The first four are provided by the FIFO, and the third
// is whatever the engine has consumed and is currently
// sending.
dat_i <= 12'b111_11101101_0;
we_i <= 1;
fault_to <= 0;
wait(~clk_i); wait(clk_i); #1; // Fills FIFO(0)
assert_empty(0);
assert_not_full(1);
fault_to <= 1;
wait(~clk_i); wait(clk_i); #1; // TXE activated; refills FIFO(0)
assert_empty(0);
assert_not_full(1);
fault_to <= 0;
wait(~clk_i); wait(clk_i); #1; // Fills FIFO(1)
assert_empty(0);
assert_not_full(1);
fault_to <= 1;
wait(~clk_i); wait(clk_i); #1; // Fills FIFO(2)
assert_empty(0);
assert_not_full(1);
fault_to <= 0;
wait(~clk_i); wait(clk_i); #1; // Fills FIFO(3); now full.
assert_empty(0);
assert_not_full(0);
fault_to <= 1'bX;
we_i <= 0;
#10000; // Wait for all five characters to be sent.
assert_empty(0);
assert_not_full(1);
#10000;
assert_empty(0);
assert_not_full(1);
#10000;
assert_empty(0);
assert_not_full(1);
#10000;
assert_empty(0);
assert_not_full(1);
#10000;
assert_empty(1);
assert_not_full(1);
#100;
$display("@I Done.");
$stop;
end
endmodule
|
//----------------------------------------------------------------------
// Title : Demo Testbench
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : demo_tb.v
// Version : 1.5
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------
// Description: This testbench will exercise the PHY ports of the EMAC
// to demonstrate the functionality.
//----------------------------------------------------------------------
`timescale 1ps / 1ps
module testbench;
//--------------------------------------------------------------------
// Testbench signals
//--------------------------------------------------------------------
wire reset;
wire tx_client_clk;
wire [7:0] tx_ifg_delay;
wire rx_client_clk;
wire [15:0] pause_val;
wire pause_req;
// GMII wires
wire gmii_tx_clk;
wire gmii_tx_en;
wire gmii_tx_er;
wire [7:0] gmii_txd;
wire gmii_rx_clk;
wire gmii_rx_dv;
wire gmii_rx_er;
wire [7:0] gmii_rxd;
// Not asserted: full duplex only testbench
wire mii_tx_clk;
wire gmii_crs;
wire gmii_col;
// Clock wires
wire host_clk;
reg gtx_clk;
reg refclk;
//----------------------------------------------------------------
// Testbench Semaphores
//----------------------------------------------------------------
wire configuration_busy;
wire monitor_finished_1g;
wire monitor_finished_100m;
wire monitor_finished_10m;
//----------------------------------------------------------------
// Wire up device under test
//----------------------------------------------------------------
v6_emac_v1_5_example_design dut
(
// Client receiver interface
.EMACCLIENTRXDVLD (),
.EMACCLIENTRXFRAMEDROP (),
.EMACCLIENTRXSTATS (),
.EMACCLIENTRXSTATSVLD (),
.EMACCLIENTRXSTATSBYTEVLD (),
// Client transmitter interface
.CLIENTEMACTXIFGDELAY (tx_ifg_delay),
.EMACCLIENTTXSTATS (),
.EMACCLIENTTXSTATSVLD (),
.EMACCLIENTTXSTATSBYTEVLD (),
// MAC Control interface
.CLIENTEMACPAUSEREQ (pause_req),
.CLIENTEMACPAUSEVAL (pause_val),
// Clock signal
.GTX_CLK (gtx_clk),
// GMII interface
.GMII_TXD (gmii_txd),
.GMII_TX_EN (gmii_tx_en),
.GMII_TX_ER (gmii_tx_er),
.GMII_TX_CLK (gmii_tx_clk),
.GMII_RXD (gmii_rxd),
.GMII_RX_DV (gmii_rx_dv),
.GMII_RX_ER (gmii_rx_er),
.GMII_RX_CLK (gmii_rx_clk),
.REFCLK (refclk),
// Asynchronous reset
.RESET (reset)
);
//--------------------------------------------------------------------------
// Flow control is unused in this demonstration
//--------------------------------------------------------------------------
assign pause_req = 1'b0;
assign pause_val = 16'b0;
// IFG stretching not used in demo.
assign tx_ifg_delay = 8'b0;
//--------------------------------------------------------------------------
// Clock drivers
//--------------------------------------------------------------------------
// Drive GTX_CLK at 125 MHz
initial
begin
gtx_clk <= 1'b0;
#10000;
forever
begin
gtx_clk <= 1'b0;
#4000;
gtx_clk <= 1'b1;
#4000;
end
end
// Drive refclk at 200MHz
initial
begin
refclk <= 1'b0;
#10000;
forever
begin
refclk <= 1'b1;
#2500;
refclk <= 1'b0;
#2500;
end
end
//--------------------------------------------------------------------
// Instantiate the PHY stimulus and monitor
//--------------------------------------------------------------------
phy_tb phy_test
(
//----------------------------------------------------------------
// GMII interface
//----------------------------------------------------------------
.gmii_txd (gmii_txd),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_er (gmii_tx_er),
.gmii_tx_clk (gmii_tx_clk),
.gmii_rxd (gmii_rxd),
.gmii_rx_dv (gmii_rx_dv),
.gmii_rx_er (gmii_rx_er),
.gmii_rx_clk (gmii_rx_clk),
.gmii_col (gmii_col),
.gmii_crs (gmii_crs),
.mii_tx_clk (mii_tx_clk),
//----------------------------------------------------------------
// Testbench semaphores
//----------------------------------------------------------------
.configuration_busy (configuration_busy),
.monitor_finished_1g (monitor_finished_1g),
.monitor_finished_100m (monitor_finished_100m),
.monitor_finished_10m (monitor_finished_10m),
.monitor_error (monitor_error)
);
//--------------------------------------------------------------------
// Instantiate the no-host configuration stimulus
//--------------------------------------------------------------------
configuration_tb config_test
(
.reset (reset),
//----------------------------------------------------------------
// Host interface: host_clk is always required
//----------------------------------------------------------------
.host_clk (host_clk),
//----------------------------------------------------------------
// Testbench semaphores
//----------------------------------------------------------------
.configuration_busy (configuration_busy),
.monitor_finished_1g (monitor_finished_1g),
.monitor_finished_100m (monitor_finished_100m),
.monitor_finished_10m (monitor_finished_10m),
.monitor_error (monitor_error)
);
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_cobs_decode
*/
module test_axis_cobs_decode;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] s_axis_tdata = 0;
reg s_axis_tvalid = 0;
reg s_axis_tlast = 0;
reg s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire s_axis_tready;
wire [7:0] m_axis_tdata;
wire m_axis_tvalid;
wire m_axis_tlast;
wire m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tvalid,
s_axis_tlast,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tvalid,
m_axis_tlast,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_cobs_decode.lxt");
$dumpvars(0, test_axis_cobs_decode);
end
axis_cobs_decode
UUT (
.clk(clk),
.rst(rst),
.s_axis_tdata(s_axis_tdata),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tuser(s_axis_tuser),
.m_axis_tdata(m_axis_tdata),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
`timescale 1ns / 1ps
//The papilio logic start wing has 4096 color depth.
//Each color R,G and B is 4 bits.
//The VGA section of the LogicStart Shield uses 12 resistors to implement
// 4096 color depth. VGA video is analog in nature so there needs to be
// some way to vary the RGB (Red, Green, and Blue) signals between 0V and
//.7V. For each RGB signal the shade, or intensity, of the color is
// controlled by varying the voltage of the pin between 0 and .7V.
//The finer control you have over the voltage the more colors you
//can create. For the LogicStart Shield we are able to control 4
// Red, 4 Green, and 4 Blue bits which allows us to generate 16
//different voltage levels between 0 and .7V for Red and Green and Blue.
//If we add all three colors together we have 12 bit video which gives
//us (2^12=4096) the possibility of 4096 colors.
module VgaController
(
input wire Clock,
input wire Reset,
output wire [3:0] oVgaRed,oVgaGreen,oVgaBlue,
output wire oVgaVsync, //Polarity of horizontal sync pulse is negative.
output wire oVgaHsync, //Polarity of vertical sync pulse is negative.
output wire [15:0] oRow,oCol
);
wire wHSync,wVSync,wPolarity_V,wPolarity_H;
//The Papilio Duo clock is 32Mhz. We will create a 64Mhz to trick
//the VGA into thinking that we are XGA 1024x768@60 Hz (pixel clock 65.0 MHz)
//`define XGA_1280x1024_60Hz
//`define XGA_1024x768_60Hz
`ifdef XGA_1024x768_60Hz
//http://tinyvga.com/vga-timing/1024x768@60Hz
parameter HSYNC_VISIBLE_AREA = 1024;
parameter HSYNC_FRONT_PORCH = 24;
parameter HSYNC_PULSE = 136;
parameter HSYN_BACK_PORCH = 48;
parameter HORIZONTAL_LINE = 1344;
parameter VSYNC_VISIBLE_AREA = 768;
parameter VSYNC_FRONT_PORCH = 3;
parameter VSYNC_PULSE = 6;
parameter VSYN_BACK_PORCH = 38;
parameter VERTICAL_LINE = 806;
//65.0Mhz = 32Mhz*27/8 = 66Mhz
parameter CLK_M = 31;
parameter CLK_D = 15;
assign wPolarity_V = 1'b0;
assign wPolarity_H = 1'b0;
`elsif XGA_1280x1024_60Hz
//http://tinyvga.com/vga-timing/1280x1024@60Hz
//Tested in a Dell LCD Monitor from LICIT and also in my home LCD Monitor
parameter HSYNC_VISIBLE_AREA = 1280;
parameter HSYNC_FRONT_PORCH = 48;
parameter HSYNC_PULSE = 112;
parameter HSYNC_BACK_PORCH = 248;
parameter HORIZONTAL_LINE = 1688;
parameter VSYNC_VISIBLE_AREA = 1024;
parameter VSYNC_FRONT_PORCH = 1;
parameter VSYNC_PULSE = 3;
parameter VSYNC_BACK_PORCH = 38;
parameter VERTICAL_LINE = 1066;
//108.0Mhz = 32Mhz*27/8
parameter CLK_M = 27;
parameter CLK_D = 8;
assign wPolarity_V = 1'b0;
assign wPolarity_H = 1'b0;
`else
//http://tinyvga.com/vga-timing/640x480@60Hz
//Works fine on LICIT LCD Dell monitor
parameter HSYNC_VISIBLE_AREA = 640;
parameter HSYNC_FRONT_PORCH = 16;
parameter HSYNC_PULSE = 96;
parameter HSYNC_BACK_PORCH = 48;
parameter HORIZONTAL_LINE = 800;
parameter VSYNC_VISIBLE_AREA = 480;
parameter VSYNC_FRONT_PORCH = 10;
parameter VSYNC_PULSE = 2;
parameter VSYN_BACK_PORCH = 33;
parameter VERTICAL_LINE = 525;
//25.175Mhz = 32Mhz*27/28 = 25.14Mhz
parameter CLK_M = 25;
parameter CLK_D = 32;
assign wPolarity_V = 1'b0;
assign wPolarity_H = 1'b0;
`endif
wire wClockVga,wHCountEnd,wVCountEnd;
wire [15:0] wHCount,wVCount;
wire wPllLocked,wPsDone;
`ifdef XILINX_IP
DCM_SP
#
(
.CLKFX_MULTIPLY(CLK_M), //Values range from 2..32
.CLKFX_DIVIDE(CLK_D) //Values range from 1..32
)
ClockVga
(
.CLKIN(Clock), //32Mhz
.CLKFB(wClockVga), //Feed back
.RST( Reset ), //Global reset
.PSEN(1'b0), //Disable variable phase shift. Ignore inputs to phase shifter
.LOCKED(wPllLocked), //Use this signal to make sure PLL is locked
.PSDONE(wPsDone), //I am not really using this one
.CLKFX(wClockVga) //FCLKFX = FCLKIN * CLKFX_MULTIPLY / CLKFX_DIVIDE
);
`else
assign wClockVga = Clock;
assign wPllLocked = 1'b1;
`endif
assign wHCountEnd = (wHCount == HORIZONTAL_LINE-1)? 1'b1 : 1'b0;
assign wVCountEnd = (wVCount == VERTICAL_LINE-1) ? 1'b1 : 1'b0;
UPCOUNTER_POSEDGE # (.SIZE(16)) HCOUNT
(
.Clock(wClockVga),
.Reset(Reset | ~wPllLocked | wHCountEnd),
.Initial(16'b0),
.Enable(wPllLocked),
.Q(wHCount)
);
UPCOUNTER_POSEDGE # (.SIZE(16)) VCOUNT
(
.Clock(wClockVga),
.Reset(Reset | ~wPllLocked | wVCountEnd ),
.Initial( 16'b0 ),
.Enable(wHCountEnd),
.Q(wVCount)
);
assign wVSync =
(
wVCount >= (VSYNC_VISIBLE_AREA + VSYNC_FRONT_PORCH ) &&
wVCount <= (VSYNC_VISIBLE_AREA + VSYNC_FRONT_PORCH + VSYNC_PULSE )
) ? 1'b1 : 1'b0;
assign wHSync =
(
wHCount >= (HSYNC_VISIBLE_AREA + HSYNC_FRONT_PORCH ) &&
wHCount <= (HSYNC_VISIBLE_AREA + HSYNC_FRONT_PORCH + HSYNC_PULSE )
) ? 1'b1 : 1'b0;
assign oVgaVsync = (wPolarity_V == 1'b1) ? wVSync : ~wVSync ;
assign oVgaHsync = (wPolarity_H == 1'b1) ? wHSync : ~wHSync ;
wire[3:0] wColorR, wColorG, wColorB;
assign wColorR = (wHCount < (HSYNC_VISIBLE_AREA/2)) ? 4'b1111 : 4'b0000;
assign wColorG = (wVCount < (VSYNC_VISIBLE_AREA/2)) ? 4'b1111 : 4'b0000;
assign wColorB = (wHCount >= (HSYNC_VISIBLE_AREA/2) && wVCount < (VSYNC_VISIBLE_AREA/2)) ? 4'b1111: 4'b0000;
assign {oVgaRed,oVgaGreen,oVgaBlue} = (wHCount < HSYNC_VISIBLE_AREA && wVCount < VSYNC_VISIBLE_AREA) ?
{wColorR,wColorG,wColorB} : //display color
{4'b1111,4'b0,4'b0}; //black
assign oCol = wHCount;
assign oRow = wVCount;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:01:20 11/17/2015
// Design Name:
// Module Name: MPU_controller
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MPU_controller(
input clk,
input clk_frame,
input rst,
input en,
output reg busy,
output reg [15:0] AcX,
output reg [15:0] AcY,
output reg [15:0] AcZ,
output reg [15:0] GyX,
output reg [15:0] GyY,
output reg [15:0] GyZ,
output reg error_i2c,
output SCL,
input SDA_in,
output SDA_out,
output SDA_oen
);
////////////////////// MPU-6050 Registers ////////////////////////////////////////
localparam MPU_SPRT = 8'h19, // Sample Rate //
MPU_CONF = 8'h1A, // General Configuration //
MPU_CONF_GYRO = 8'h1B, // Gyroscope Configuration //
MPU_CONF_ACC = 8'h1C, // Accelerometer Configuration //
MPU_ACC_X_H = 8'h3B, // Accelerometer Reading //
MPU_ACC_X_L = 8'h3C, // Accelerometer Reading //
MPU_ACC_Y_H = 8'h3D, // Accelerometer Reading //
MPU_ACC_Y_L = 8'h3E, // Accelerometer Reading //
MPU_ACC_Z_H = 8'h3F, // Accelerometer Reading //
MPU_ACC_Z_L = 8'h40, // Accelerometer Reading //
MPU_TMP_h = 8'h41, // Temperature Reading //
MPU_TMP_L = 8'h42, // Temperature Reading //
MPU_GYR_X_H = 8'h43, // Gyroscope Reading //
MPU_GYR_X_L = 8'h44, // Gyroscope Reading //
MPU_GYR_Y_H = 8'h45, // Gyroscope Reading //
MPU_GYR_Y_L = 8'h46, // Gyroscope Reading //
MPU_GYR_Z_H = 8'h47, // Gyroscope Reading //
MPU_GYR_Z_L = 8'h48, // Gyroscope Reading //
MPU_PWR_MGM = 8'h6B, // Powr Management Register //
MPU_WAI = 8'h75; // Who Am I? //
//////////////////////////////////////////////////////////////////////////////////
///////////////// MPU-6050 Registers Configuration ///////////////////////////////
localparam MPU_SPRT_VAL = 8'h00, // SR = GOR/(1+MPU_SPRT_VAL) //
MPU_FSYNC_DIS = 8'h00, // Disable Frame Synchronization //
MPU_LPF_CONF_260 = 8'h00, // Low Pass Filter: 260Hz -> GOR = 8000 //
MPU_LPF_CONF_184 = 8'h01, // Low Pass Filter: 184Hz -> GOR = 1000 //
MPU_LPF_CONF_94 = 8'h02, // Low Pass Filter: 094Hz -> GOR = 1000 //
MPU_LPF_CONF_44 = 8'h03, // Low Pass Filter: 044Hz -> GOR = 1000 //
MPU_LPF_CONF_21 = 8'h04, // Low Pass Filter: 021Hz -> GOR = 1000 //
MPU_LPF_CONF_10 = 8'h05, // Low Pass Filter: 010Hz -> GOR = 1000 //
MPU_LPF_CONF_5 = 8'h06, // Low Pass Filter: 005Hz -> GOR = 1000 //
MPU_GYRO_250 = 8'h00, // 250°/S //
MPU_GYRO_500 = 8'h08, // 500°/S //
MPU_GYRO_1000 = 8'h10, // 1000°/S //
MPU_GYRO_2000 = 8'h18, // 2000°/S //
MPU_ACCL_2 = 8'h00, // 2g //
MPU_ACCL_4 = 8'h08, // 4g //
MPU_ACCL_8 = 8'h10, // 8g //
MPU_ACCL_16 = 8'h18, // 16g //
MPU_RST = 8'h80, // Resets device //
MPU_WUP = 8'h00, // Wakes up Device //
ADDR_W = 8'b01101000, // Slave Addres, Write mode //
ADDR_R = 8'b01101001; // Generate START condition //
//////////////////////////////////////////////////////////////////////////////////
//////////////////////// Internal Registers ///////////////////////
reg [7:0] regDir,data,regDir_d,data_d; //
reg [3:0] i; //
reg stop_d,ack_o_d;
///////////////////////////////////////////////////////////////////
///////////////////// I2C Instantiation /////////////////////////////////
reg en_i2c,start,stop,ack_o,rw; //
reg[7:0] out_byte; //
wire err,busy_i2c; //
wire[7:0] in_byte; //
I2C_Top I2C ( //
.clk(clk), //
.clk_frame(clk_frame), //
.rst(rst), //
.en(en_i2c), //
.start(start), //
.stop(stop), //
.ack_o(ack_o), //
.rw(rw), //
.out_byte(out_byte), //
.busy(busy_i2c), //
.err(err_i2c), //
.in_byte(in_byte), //
.SCL(SCL), //
.SDA_in(SDA_in), //
.SDA_out(SDA_out), //
.SDA_oen(SDA_oen) //
); //
/////////////////////////////////////////////////////////////////////////
///////////////////////// Math Instances ////////////////////////////////
reg [15:0] mul1_A; //
reg [15:0] mul1_B; //
reg mul1_en; //
reg mul1_rst; //
reg mul1_busy; //
wire [31:0] mul1_R; //
booth_mult multi_1 ( //
.clk(clk), //
.rst(mul1_rst), //
.en(mul1_en), //
.A(mul1_A), //
.B(mul1_B), //
.busy(mul1_busy), //
.R(mul1_R) //
); //
reg [15:0] mul2_A; //
reg [15:0] mul2_B; //
reg mul2_en; //
reg mul2_rst; //
reg mul2_busy; //
wire [31:0] mul2_R; //
booth_mult multi_2 ( //
.clk(clk), //
.rst(mul2_rst), //
.en(mul2_en), //
.A(mul2_A), //
.B(mul2_B), //
.busy(mul2_busy), //
.R(mul2_R) //
); //
/////////////////////////////////////////////////////////////////////////
///////////////////////////// States ////////////////////////////////////
reg [4:0] state, pointer, pointer2, pointer3,temp; //
initial begin
state = 5'h00;
pointer = 5'h00;
pointer2 = 5'h00;
pointer3 = 5'h00;
end
localparam reset = 00, //
set_FSNC = 01, //
set_LPF = 02, //
set_res_gyr = 03, //
set_res_acc = 04, //
wake_up = 05, //
idle = 06, //
write_accX = 07, //
read = 08, //
read_w = 09, //
check1 = 10, //
check2 = 11, //
check3 = 12, //
error = 13, //
start_cond = 14, //
send_addresR = 15, //
send_addresW = 16, //
send_regAddr = 17, //
send_byte = 18, //
read_8_ACK = 19, //
read_8_NACK = 20, //
stop_cond = 21, //
wait_i2c = 22, //
wait_i2c_A = 23, //
wait_i2c_B = 24; //
/////////////////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(rst) begin
i <= 4'h0;
AcX <= 16'h0000;
AcY <= 16'h0000;
AcZ <= 16'h0000;
GyX <= 16'h0000;
GyY <= 16'h0000;
GyZ <= 16'h0000;
state <= set_FSNC;
pointer <= reset;
pointer2 <= reset;
pointer3 <= reset;
state <= reset;
end
else begin
case(state)
reset: begin
i <= 4'h0;
AcX <= 16'h0000;
AcY <= 16'h0000;
AcZ <= 16'h0000;
GyX <= 16'h0000;
GyY <= 16'h0000;
GyZ <= 16'h0000;
state <= set_FSNC;
pointer <= reset;
pointer2 <= reset;
pointer3 <= reset;
end
set_FSNC: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
state <= send_addresW;
pointer <= send_regAddr;
pointer2 <= send_byte;
pointer3 <= set_LPF;
end
set_LPF: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
state <= send_addresW;
pointer <= send_regAddr;
pointer2 <= send_byte;
pointer3 <= set_res_gyr;
end
set_res_gyr: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
state <= send_addresW;
pointer <= send_regAddr;
pointer2 <= send_byte;
pointer3 <= set_res_acc;
end
set_res_acc: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
state <= send_addresW;
pointer <= send_regAddr;
pointer2 <= send_byte;
pointer3 <= wake_up;
end
wake_up: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
state <= send_addresW;
pointer <= send_regAddr;
pointer2 <= send_byte;
pointer3 <= idle;
end
idle: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= idle;
pointer2 <= idle;
pointer3 <= idle;
if(en) state <= write_accX;
else state <= idle;
end
write_accX: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= send_regAddr;
pointer2 <= send_addresR;
pointer3 <= read;
state <= send_addresW;
end
read: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= read_w;
else state <= read;
end
read_w: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= read_w;
else state <= check1;
end
check1: begin
i <= i;
case(i)
4'h0: begin
AcX[15:8] <= in_byte;
AcX[7:0] <= 8'h00;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h1: begin
AcX[15:8] <= AcX[15:8];
AcX[7:0] <= in_byte;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h2: begin
AcX <= AcX;
AcY[15:8] <= in_byte;
AcY[7:0] <= 8'h00;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h3: begin
AcX <= AcX;
AcY[15:8] <= AcY[15:8];
AcY[7:0] <= in_byte;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h4: begin
AcX <= AcX;
AcY <= AcY;
AcZ[15:8] <= in_byte;
AcZ[7:0] <= 8'h00;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h5: begin
AcX <= AcX;
AcY <= AcY;
AcZ[15:8] <= AcZ[15:8];
AcZ[7:0] <= in_byte;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h6: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h7: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h8: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX[15:8] <= in_byte;
GyX[7:0] <= 8'h00;
GyY <= GyY;
GyZ <= GyZ;
end
4'h9: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX[15:8] <= GyX[15:8];
GyX[7:0] <= in_byte;
GyY <= GyY;
GyZ <= GyZ;
end
4'hA: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY[15:8] <= in_byte;
GyY[7:0] <= 8'h00;
GyZ <= GyZ;
end
4'hB: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY[15:8] <= GyY[15:8];
GyY[7:0] <= in_byte;
GyZ <= GyZ;
end
4'hC: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ[15:8] <= in_byte;
GyZ[7:0] <= 8'h00;
end
4'hD: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ[15:8] <= GyZ[15:8];
GyZ[7:0] <= in_byte;
end
default: begin
AcX <= 16'h0000;
AcY <= 16'h0000;
AcZ <= 16'h0000;
GyX <= 16'h0000;
GyY <= 16'h0000;
GyZ[15:8] <= 16'h0000;
GyZ[7:0] <= 16'h0000;
end
endcase
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
state <= check2;
end
check2: begin
i <= i+1;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
state <= check3;
end
check3: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(i == 4'hE) state <= idle;
else state <= read;
end
error: begin
i <= 4'h00;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= error;
pointer2 <= error;
pointer3 <= error;
state <= error;
end
send_addresR: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= wait_i2c_A;
else state <= send_addresR;
end
send_addresW: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= wait_i2c_A;
else state <= send_addresW;
end
send_regAddr: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= wait_i2c_A;
else state <= send_regAddr;
end
send_byte: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= wait_i2c_A;
else state <= send_byte;
end
wait_i2c_A: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer2;
pointer2 <= pointer3;
pointer3 <= pointer;
state <= wait_i2c_B;
end
wait_i2c_B: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= wait_i2c_B;
else state <= pointer3;
end
default: begin
i <= 4'h0;
AcX <= 16'h0000;
AcY <= 16'h0000;
AcZ <= 16'h0000;
GyX <= 16'h0000;
GyY <= 16'h0000;
GyZ <= 16'h0000;
state <= error;
pointer <= reset;
pointer2 <= reset;
pointer3 <= reset;
end
endcase
end
end
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always@(*) begin
case(state)
reset: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
set_FSNC: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= MPU_CONF;
data <= MPU_FSYNC_DIS;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
set_LPF: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= MPU_CONF;
data <= MPU_LPF_CONF_184;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
set_res_gyr: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= MPU_CONF_GYRO;
data <= MPU_GYRO_250;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
set_res_acc: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= MPU_CONF_ACC;
data <= MPU_ACCL_2;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
wake_up: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= MPU_PWR_MGM;
data <= MPU_WUP;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
idle: begin
busy <= 1'b0;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
write_accX: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= MPU_ACC_X_H;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
read: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b1;
start <= 1'b0;
if(i == 4'hD) begin
stop <= 1'b1;
ack_o <= 1'b1;
end
else begin
stop <= 1'b0;
ack_o <= 1'b0;
end
rw <= 1'b0;
out_byte <= 8'h00;
end
read_w: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
check1: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
check2: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
check3: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
error: begin
busy <= 1'b0;
error_i2c<= 1'b1;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= 1'b0;
ack_o <= 1'b0;
rw <= 1'b0;
out_byte <= 8'h00;
end
send_addresR: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b1;
start <= 1'b1;
stop <= 1'b0;
ack_o <= 1'b0;
rw <= 1'b1;
out_byte <= ADDR_R;
end
send_addresW: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b1;
start <= 1'b1;
stop <= 1'b0;
ack_o <= 1'b0;
rw <= 1'b1;
out_byte <= ADDR_W;
end
send_regAddr: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b1;
start <= 1'b0;
stop <= 1'b0;
ack_o <= 1'b0;
rw <= 1'b1;
out_byte <= regDir;
end
send_byte: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b1;
start <= 1'b0;
stop <= 1'b1;
ack_o <= 1'b0;
rw <= 1'b1;
out_byte <= data;
end
wait_i2c_A: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
wait_i2c_B: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
default: begin
busy <= 1'b0;
error_i2c<= 1'b1;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
endcase
end
always@(negedge clk) begin
regDir_d <= regDir;
data_d <= data;
stop_d <= stop;
ack_o_d <= ack_o;
end
endmodule
|
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_sqrt CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=30 ROUNDING="TO_NEAREST" WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock data result
//VERSION_BEGIN 12.0 cbx_altfp_sqrt 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//alt_sqrt_block CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix V" PIPELINE=30 WIDTH_SQRT=54 aclr clken clock rad root_result
//VERSION_BEGIN 12.0 cbx_altfp_sqrt 2012:05:31:20:08:02:SJ cbx_cycloneii 2012:05:31:20:08:02:SJ cbx_lpm_add_sub 2012:05:31:20:08:02:SJ cbx_mgl 2012:05:31:20:10:16:SJ cbx_stratix 2012:05:31:20:08:02:SJ cbx_stratixii 2012:05:31:20:08:02:SJ VERSION_END
//synthesis_resources = lpm_add_sub 54 reg 2383
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sqrt_s5_double_alt_sqrt_block_odb
(
aclr,
clken,
clock,
rad,
root_result) ;
input aclr;
input clken;
input clock;
input [54:0] rad;
output [53:0] root_result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] q_ff0c;
reg [51:0] q_ff10c;
reg [51:0] q_ff12c;
reg [51:0] q_ff14c;
reg [51:0] q_ff16c;
reg [51:0] q_ff18c;
reg [51:0] q_ff20c;
reg [51:0] q_ff22c;
reg [51:0] q_ff24c;
reg [51:0] q_ff26c;
reg [51:0] q_ff28c;
reg [51:0] q_ff2c;
reg [51:0] q_ff30c;
reg [51:0] q_ff32c;
reg [51:0] q_ff34c;
reg [51:0] q_ff36c;
reg [51:0] q_ff38c;
reg [51:0] q_ff40c;
reg [51:0] q_ff42c;
reg [51:0] q_ff44c;
reg [51:0] q_ff46c;
reg [51:0] q_ff48c;
reg [51:0] q_ff4c;
reg [51:0] q_ff50c;
reg [26:0] q_ff52c;
reg [51:0] q_ff6c;
reg [51:0] q_ff8c;
reg [43:0] rad_ff11c;
reg [41:0] rad_ff13c;
reg [39:0] rad_ff15c;
reg [37:0] rad_ff17c;
reg [35:0] rad_ff19c;
reg [53:0] rad_ff1c;
reg [33:0] rad_ff21c;
reg [31:0] rad_ff23c;
reg [29:0] rad_ff25c;
reg [27:0] rad_ff27c;
reg [28:0] rad_ff29c;
reg [30:0] rad_ff31c;
reg [32:0] rad_ff33c;
reg [34:0] rad_ff35c;
reg [36:0] rad_ff37c;
reg [38:0] rad_ff39c;
reg [51:0] rad_ff3c;
reg [40:0] rad_ff41c;
reg [42:0] rad_ff43c;
reg [44:0] rad_ff45c;
reg [46:0] rad_ff47c;
reg [48:0] rad_ff49c;
reg [50:0] rad_ff51c;
reg [49:0] rad_ff5c;
reg [47:0] rad_ff7c;
reg [45:0] rad_ff9c;
wire [8:0] wire_add_sub10_result;
wire [9:0] wire_add_sub11_result;
wire [10:0] wire_add_sub12_result;
wire [11:0] wire_add_sub13_result;
wire [12:0] wire_add_sub14_result;
wire [13:0] wire_add_sub15_result;
wire [14:0] wire_add_sub16_result;
wire [15:0] wire_add_sub17_result;
wire [16:0] wire_add_sub18_result;
wire [17:0] wire_add_sub19_result;
wire [18:0] wire_add_sub20_result;
wire [19:0] wire_add_sub21_result;
wire [20:0] wire_add_sub22_result;
wire [21:0] wire_add_sub23_result;
wire [22:0] wire_add_sub24_result;
wire [23:0] wire_add_sub25_result;
wire [24:0] wire_add_sub26_result;
wire [25:0] wire_add_sub27_result;
wire [26:0] wire_add_sub28_result;
wire [27:0] wire_add_sub29_result;
wire [28:0] wire_add_sub30_result;
wire [27:0] wire_add_sub31_result;
wire [27:0] wire_add_sub32_result;
wire [28:0] wire_add_sub33_result;
wire [29:0] wire_add_sub34_result;
wire [30:0] wire_add_sub35_result;
wire [31:0] wire_add_sub36_result;
wire [32:0] wire_add_sub37_result;
wire [33:0] wire_add_sub38_result;
wire [34:0] wire_add_sub39_result;
wire [2:0] wire_add_sub4_result;
wire [35:0] wire_add_sub40_result;
wire [36:0] wire_add_sub41_result;
wire [37:0] wire_add_sub42_result;
wire [38:0] wire_add_sub43_result;
wire [39:0] wire_add_sub44_result;
wire [40:0] wire_add_sub45_result;
wire [41:0] wire_add_sub46_result;
wire [42:0] wire_add_sub47_result;
wire [43:0] wire_add_sub48_result;
wire [44:0] wire_add_sub49_result;
wire [3:0] wire_add_sub5_result;
wire [45:0] wire_add_sub50_result;
wire [46:0] wire_add_sub51_result;
wire [47:0] wire_add_sub52_result;
wire [48:0] wire_add_sub53_result;
wire [49:0] wire_add_sub54_result;
wire [50:0] wire_add_sub55_result;
wire [51:0] wire_add_sub56_result;
wire [52:0] wire_add_sub57_result;
wire [4:0] wire_add_sub6_result;
wire [5:0] wire_add_sub7_result;
wire [6:0] wire_add_sub8_result;
wire [7:0] wire_add_sub9_result;
wire [55:0] addnode_w0c;
wire [55:0] addnode_w10c;
wire [55:0] addnode_w11c;
wire [55:0] addnode_w12c;
wire [55:0] addnode_w13c;
wire [55:0] addnode_w14c;
wire [55:0] addnode_w15c;
wire [55:0] addnode_w16c;
wire [55:0] addnode_w17c;
wire [55:0] addnode_w18c;
wire [55:0] addnode_w19c;
wire [55:0] addnode_w1c;
wire [55:0] addnode_w20c;
wire [55:0] addnode_w21c;
wire [55:0] addnode_w22c;
wire [55:0] addnode_w23c;
wire [55:0] addnode_w24c;
wire [55:0] addnode_w25c;
wire [55:0] addnode_w26c;
wire [55:0] addnode_w27c;
wire [55:0] addnode_w28c;
wire [55:0] addnode_w29c;
wire [55:0] addnode_w2c;
wire [55:0] addnode_w30c;
wire [55:0] addnode_w31c;
wire [55:0] addnode_w32c;
wire [55:0] addnode_w33c;
wire [55:0] addnode_w34c;
wire [55:0] addnode_w35c;
wire [55:0] addnode_w36c;
wire [55:0] addnode_w37c;
wire [55:0] addnode_w38c;
wire [55:0] addnode_w39c;
wire [55:0] addnode_w3c;
wire [55:0] addnode_w40c;
wire [55:0] addnode_w41c;
wire [55:0] addnode_w42c;
wire [55:0] addnode_w43c;
wire [55:0] addnode_w44c;
wire [55:0] addnode_w45c;
wire [55:0] addnode_w46c;
wire [55:0] addnode_w47c;
wire [55:0] addnode_w48c;
wire [55:0] addnode_w49c;
wire [55:0] addnode_w4c;
wire [55:0] addnode_w50c;
wire [55:0] addnode_w51c;
wire [55:0] addnode_w52c;
wire [55:0] addnode_w53c;
wire [55:0] addnode_w5c;
wire [55:0] addnode_w6c;
wire [55:0] addnode_w7c;
wire [55:0] addnode_w8c;
wire [55:0] addnode_w9c;
wire [2:0] qlevel_w0c;
wire [12:0] qlevel_w10c;
wire [13:0] qlevel_w11c;
wire [14:0] qlevel_w12c;
wire [15:0] qlevel_w13c;
wire [16:0] qlevel_w14c;
wire [17:0] qlevel_w15c;
wire [18:0] qlevel_w16c;
wire [19:0] qlevel_w17c;
wire [20:0] qlevel_w18c;
wire [21:0] qlevel_w19c;
wire [3:0] qlevel_w1c;
wire [22:0] qlevel_w20c;
wire [23:0] qlevel_w21c;
wire [24:0] qlevel_w22c;
wire [25:0] qlevel_w23c;
wire [26:0] qlevel_w24c;
wire [27:0] qlevel_w25c;
wire [28:0] qlevel_w26c;
wire [29:0] qlevel_w27c;
wire [30:0] qlevel_w28c;
wire [31:0] qlevel_w29c;
wire [4:0] qlevel_w2c;
wire [32:0] qlevel_w30c;
wire [33:0] qlevel_w31c;
wire [34:0] qlevel_w32c;
wire [35:0] qlevel_w33c;
wire [36:0] qlevel_w34c;
wire [37:0] qlevel_w35c;
wire [38:0] qlevel_w36c;
wire [39:0] qlevel_w37c;
wire [40:0] qlevel_w38c;
wire [41:0] qlevel_w39c;
wire [5:0] qlevel_w3c;
wire [42:0] qlevel_w40c;
wire [43:0] qlevel_w41c;
wire [44:0] qlevel_w42c;
wire [45:0] qlevel_w43c;
wire [46:0] qlevel_w44c;
wire [47:0] qlevel_w45c;
wire [48:0] qlevel_w46c;
wire [49:0] qlevel_w47c;
wire [50:0] qlevel_w48c;
wire [51:0] qlevel_w49c;
wire [6:0] qlevel_w4c;
wire [52:0] qlevel_w50c;
wire [53:0] qlevel_w51c;
wire [54:0] qlevel_w52c;
wire [55:0] qlevel_w53c;
wire [7:0] qlevel_w5c;
wire [8:0] qlevel_w6c;
wire [9:0] qlevel_w7c;
wire [10:0] qlevel_w8c;
wire [11:0] qlevel_w9c;
wire [55:0] slevel_w0c;
wire [55:0] slevel_w10c;
wire [55:0] slevel_w11c;
wire [55:0] slevel_w12c;
wire [55:0] slevel_w13c;
wire [55:0] slevel_w14c;
wire [55:0] slevel_w15c;
wire [55:0] slevel_w16c;
wire [55:0] slevel_w17c;
wire [55:0] slevel_w18c;
wire [55:0] slevel_w19c;
wire [55:0] slevel_w1c;
wire [55:0] slevel_w20c;
wire [55:0] slevel_w21c;
wire [55:0] slevel_w22c;
wire [55:0] slevel_w23c;
wire [55:0] slevel_w24c;
wire [55:0] slevel_w25c;
wire [55:0] slevel_w26c;
wire [55:0] slevel_w27c;
wire [55:0] slevel_w28c;
wire [55:0] slevel_w29c;
wire [55:0] slevel_w2c;
wire [55:0] slevel_w30c;
wire [55:0] slevel_w31c;
wire [55:0] slevel_w32c;
wire [55:0] slevel_w33c;
wire [55:0] slevel_w34c;
wire [55:0] slevel_w35c;
wire [55:0] slevel_w36c;
wire [55:0] slevel_w37c;
wire [55:0] slevel_w38c;
wire [55:0] slevel_w39c;
wire [55:0] slevel_w3c;
wire [55:0] slevel_w40c;
wire [55:0] slevel_w41c;
wire [55:0] slevel_w42c;
wire [55:0] slevel_w43c;
wire [55:0] slevel_w44c;
wire [55:0] slevel_w45c;
wire [55:0] slevel_w46c;
wire [55:0] slevel_w47c;
wire [55:0] slevel_w48c;
wire [55:0] slevel_w49c;
wire [55:0] slevel_w4c;
wire [55:0] slevel_w50c;
wire [55:0] slevel_w51c;
wire [55:0] slevel_w52c;
wire [55:0] slevel_w53c;
wire [55:0] slevel_w5c;
wire [55:0] slevel_w6c;
wire [55:0] slevel_w7c;
wire [55:0] slevel_w8c;
wire [55:0] slevel_w9c;
// synopsys translate_off
initial
q_ff0c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff0c <= 2'b0;
else if (clken == 1'b1) q_ff0c <= {(~ addnode_w52c[55]), (~ addnode_w53c[55])};
// synopsys translate_off
initial
q_ff10c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff10c <= 52'b0;
else if (clken == 1'b1) q_ff10c <= {q_ff10c[49:0], (~ addnode_w42c[55]), (~ addnode_w43c[55])};
// synopsys translate_off
initial
q_ff12c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff12c <= 52'b0;
else if (clken == 1'b1) q_ff12c <= {q_ff12c[49:0], (~ addnode_w40c[55]), (~ addnode_w41c[55])};
// synopsys translate_off
initial
q_ff14c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff14c <= 52'b0;
else if (clken == 1'b1) q_ff14c <= {q_ff14c[49:0], (~ addnode_w38c[55]), (~ addnode_w39c[55])};
// synopsys translate_off
initial
q_ff16c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff16c <= 52'b0;
else if (clken == 1'b1) q_ff16c <= {q_ff16c[49:0], (~ addnode_w36c[55]), (~ addnode_w37c[55])};
// synopsys translate_off
initial
q_ff18c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff18c <= 52'b0;
else if (clken == 1'b1) q_ff18c <= {q_ff18c[49:0], (~ addnode_w34c[55]), (~ addnode_w35c[55])};
// synopsys translate_off
initial
q_ff20c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff20c <= 52'b0;
else if (clken == 1'b1) q_ff20c <= {q_ff20c[49:0], (~ addnode_w32c[55]), (~ addnode_w33c[55])};
// synopsys translate_off
initial
q_ff22c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff22c <= 52'b0;
else if (clken == 1'b1) q_ff22c <= {q_ff22c[49:0], (~ addnode_w30c[55]), (~ addnode_w31c[55])};
// synopsys translate_off
initial
q_ff24c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff24c <= 52'b0;
else if (clken == 1'b1) q_ff24c <= {q_ff24c[49:0], (~ addnode_w28c[55]), (~ addnode_w29c[55])};
// synopsys translate_off
initial
q_ff26c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff26c <= 52'b0;
else if (clken == 1'b1) q_ff26c <= {q_ff26c[49:0], (~ addnode_w26c[55]), (~ addnode_w27c[55])};
// synopsys translate_off
initial
q_ff28c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff28c <= 52'b0;
else if (clken == 1'b1) q_ff28c <= {q_ff28c[49:0], (~ addnode_w24c[55]), (~ addnode_w25c[55])};
// synopsys translate_off
initial
q_ff2c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff2c <= 52'b0;
else if (clken == 1'b1) q_ff2c <= {q_ff2c[49:0], (~ addnode_w50c[55]), (~ addnode_w51c[55])};
// synopsys translate_off
initial
q_ff30c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff30c <= 52'b0;
else if (clken == 1'b1) q_ff30c <= {q_ff30c[49:0], (~ addnode_w22c[55]), (~ addnode_w23c[55])};
// synopsys translate_off
initial
q_ff32c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff32c <= 52'b0;
else if (clken == 1'b1) q_ff32c <= {q_ff32c[49:0], (~ addnode_w20c[55]), (~ addnode_w21c[55])};
// synopsys translate_off
initial
q_ff34c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff34c <= 52'b0;
else if (clken == 1'b1) q_ff34c <= {q_ff34c[49:0], (~ addnode_w18c[55]), (~ addnode_w19c[55])};
// synopsys translate_off
initial
q_ff36c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff36c <= 52'b0;
else if (clken == 1'b1) q_ff36c <= {q_ff36c[49:0], (~ addnode_w16c[55]), (~ addnode_w17c[55])};
// synopsys translate_off
initial
q_ff38c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff38c <= 52'b0;
else if (clken == 1'b1) q_ff38c <= {q_ff38c[49:0], (~ addnode_w14c[55]), (~ addnode_w15c[55])};
// synopsys translate_off
initial
q_ff40c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff40c <= 52'b0;
else if (clken == 1'b1) q_ff40c <= {q_ff40c[49:0], (~ addnode_w12c[55]), (~ addnode_w13c[55])};
// synopsys translate_off
initial
q_ff42c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff42c <= 52'b0;
else if (clken == 1'b1) q_ff42c <= {q_ff42c[49:0], (~ addnode_w10c[55]), (~ addnode_w11c[55])};
// synopsys translate_off
initial
q_ff44c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff44c <= 52'b0;
else if (clken == 1'b1) q_ff44c <= {q_ff44c[49:0], (~ addnode_w8c[55]), (~ addnode_w9c[55])};
// synopsys translate_off
initial
q_ff46c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff46c <= 52'b0;
else if (clken == 1'b1) q_ff46c <= {q_ff46c[49:0], (~ addnode_w6c[55]), (~ addnode_w7c[55])};
// synopsys translate_off
initial
q_ff48c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff48c <= 52'b0;
else if (clken == 1'b1) q_ff48c <= {q_ff48c[49:0], (~ addnode_w4c[55]), (~ addnode_w5c[55])};
// synopsys translate_off
initial
q_ff4c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff4c <= 52'b0;
else if (clken == 1'b1) q_ff4c <= {q_ff4c[49:0], (~ addnode_w48c[55]), (~ addnode_w49c[55])};
// synopsys translate_off
initial
q_ff50c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff50c <= 52'b0;
else if (clken == 1'b1) q_ff50c <= {q_ff50c[49:0], (~ addnode_w2c[55]), (~ addnode_w3c[55])};
// synopsys translate_off
initial
q_ff52c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff52c <= 27'b0;
else if (clken == 1'b1) q_ff52c <= {q_ff52c[25:0], (~ addnode_w1c[55])};
// synopsys translate_off
initial
q_ff6c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff6c <= 52'b0;
else if (clken == 1'b1) q_ff6c <= {q_ff6c[49:0], (~ addnode_w46c[55]), (~ addnode_w47c[55])};
// synopsys translate_off
initial
q_ff8c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) q_ff8c <= 52'b0;
else if (clken == 1'b1) q_ff8c <= {q_ff8c[49:0], (~ addnode_w44c[55]), (~ addnode_w45c[55])};
// synopsys translate_off
initial
rad_ff11c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff11c <= 44'b0;
else if (clken == 1'b1) rad_ff11c <= addnode_w11c[55:12];
// synopsys translate_off
initial
rad_ff13c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff13c <= 42'b0;
else if (clken == 1'b1) rad_ff13c <= addnode_w13c[55:14];
// synopsys translate_off
initial
rad_ff15c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff15c <= 40'b0;
else if (clken == 1'b1) rad_ff15c <= addnode_w15c[55:16];
// synopsys translate_off
initial
rad_ff17c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff17c <= 38'b0;
else if (clken == 1'b1) rad_ff17c <= addnode_w17c[55:18];
// synopsys translate_off
initial
rad_ff19c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff19c <= 36'b0;
else if (clken == 1'b1) rad_ff19c <= addnode_w19c[55:20];
// synopsys translate_off
initial
rad_ff1c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff1c <= 54'b0;
else if (clken == 1'b1) rad_ff1c <= addnode_w1c[55:2];
// synopsys translate_off
initial
rad_ff21c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff21c <= 34'b0;
else if (clken == 1'b1) rad_ff21c <= addnode_w21c[55:22];
// synopsys translate_off
initial
rad_ff23c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff23c <= 32'b0;
else if (clken == 1'b1) rad_ff23c <= addnode_w23c[55:24];
// synopsys translate_off
initial
rad_ff25c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff25c <= 30'b0;
else if (clken == 1'b1) rad_ff25c <= addnode_w25c[55:26];
// synopsys translate_off
initial
rad_ff27c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff27c <= 28'b0;
else if (clken == 1'b1) rad_ff27c <= addnode_w27c[55:28];
// synopsys translate_off
initial
rad_ff29c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff29c <= 29'b0;
else if (clken == 1'b1) rad_ff29c <= addnode_w29c[55:27];
// synopsys translate_off
initial
rad_ff31c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff31c <= 31'b0;
else if (clken == 1'b1) rad_ff31c <= addnode_w31c[55:25];
// synopsys translate_off
initial
rad_ff33c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff33c <= 33'b0;
else if (clken == 1'b1) rad_ff33c <= addnode_w33c[55:23];
// synopsys translate_off
initial
rad_ff35c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff35c <= 35'b0;
else if (clken == 1'b1) rad_ff35c <= addnode_w35c[55:21];
// synopsys translate_off
initial
rad_ff37c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff37c <= 37'b0;
else if (clken == 1'b1) rad_ff37c <= addnode_w37c[55:19];
// synopsys translate_off
initial
rad_ff39c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff39c <= 39'b0;
else if (clken == 1'b1) rad_ff39c <= addnode_w39c[55:17];
// synopsys translate_off
initial
rad_ff3c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff3c <= 52'b0;
else if (clken == 1'b1) rad_ff3c <= addnode_w3c[55:4];
// synopsys translate_off
initial
rad_ff41c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff41c <= 41'b0;
else if (clken == 1'b1) rad_ff41c <= addnode_w41c[55:15];
// synopsys translate_off
initial
rad_ff43c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff43c <= 43'b0;
else if (clken == 1'b1) rad_ff43c <= addnode_w43c[55:13];
// synopsys translate_off
initial
rad_ff45c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff45c <= 45'b0;
else if (clken == 1'b1) rad_ff45c <= addnode_w45c[55:11];
// synopsys translate_off
initial
rad_ff47c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff47c <= 47'b0;
else if (clken == 1'b1) rad_ff47c <= addnode_w47c[55:9];
// synopsys translate_off
initial
rad_ff49c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff49c <= 49'b0;
else if (clken == 1'b1) rad_ff49c <= addnode_w49c[55:7];
// synopsys translate_off
initial
rad_ff51c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff51c <= 51'b0;
else if (clken == 1'b1) rad_ff51c <= addnode_w51c[55:5];
// synopsys translate_off
initial
rad_ff5c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff5c <= 50'b0;
else if (clken == 1'b1) rad_ff5c <= addnode_w5c[55:6];
// synopsys translate_off
initial
rad_ff7c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff7c <= 48'b0;
else if (clken == 1'b1) rad_ff7c <= addnode_w7c[55:8];
// synopsys translate_off
initial
rad_ff9c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) rad_ff9c <= 46'b0;
else if (clken == 1'b1) rad_ff9c <= addnode_w9c[55:10];
lpm_add_sub add_sub10
(
.cout(),
.dataa({slevel_w6c[55:47]}),
.datab({(({7{(~ rad_ff5c[49])}} & (~ qlevel_w6c[8:2])) | ({7{rad_ff5c[49]}} & qlevel_w6c[8:2])), qlevel_w6c[1:0]}),
.overflow(),
.result(wire_add_sub10_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub10.lpm_direction = "ADD",
add_sub10.lpm_pipeline = 0,
add_sub10.lpm_width = 9,
add_sub10.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub11
(
.cout(),
.dataa({slevel_w7c[55:46]}),
.datab({(({8{(~ addnode_w6c[55])}} & (~ qlevel_w7c[9:2])) | ({8{addnode_w6c[55]}} & qlevel_w7c[9:2])), qlevel_w7c[1:0]}),
.overflow(),
.result(wire_add_sub11_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub11.lpm_direction = "ADD",
add_sub11.lpm_pipeline = 0,
add_sub11.lpm_width = 10,
add_sub11.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub12
(
.cout(),
.dataa({slevel_w8c[55:45]}),
.datab({(({9{(~ rad_ff7c[47])}} & (~ qlevel_w8c[10:2])) | ({9{rad_ff7c[47]}} & qlevel_w8c[10:2])), qlevel_w8c[1:0]}),
.overflow(),
.result(wire_add_sub12_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub12.lpm_direction = "ADD",
add_sub12.lpm_pipeline = 0,
add_sub12.lpm_width = 11,
add_sub12.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub13
(
.cout(),
.dataa({slevel_w9c[55:44]}),
.datab({(({10{(~ addnode_w8c[55])}} & (~ qlevel_w9c[11:2])) | ({10{addnode_w8c[55]}} & qlevel_w9c[11:2])), qlevel_w9c[1:0]}),
.overflow(),
.result(wire_add_sub13_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub13.lpm_direction = "ADD",
add_sub13.lpm_pipeline = 0,
add_sub13.lpm_width = 12,
add_sub13.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub14
(
.cout(),
.dataa({slevel_w10c[55:43]}),
.datab({(({11{(~ rad_ff9c[45])}} & (~ qlevel_w10c[12:2])) | ({11{rad_ff9c[45]}} & qlevel_w10c[12:2])), qlevel_w10c[1:0]}),
.overflow(),
.result(wire_add_sub14_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub14.lpm_direction = "ADD",
add_sub14.lpm_pipeline = 0,
add_sub14.lpm_width = 13,
add_sub14.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub15
(
.cout(),
.dataa({slevel_w11c[55:42]}),
.datab({(({12{(~ addnode_w10c[55])}} & (~ qlevel_w11c[13:2])) | ({12{addnode_w10c[55]}} & qlevel_w11c[13:2])), qlevel_w11c[1:0]}),
.overflow(),
.result(wire_add_sub15_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub15.lpm_direction = "ADD",
add_sub15.lpm_pipeline = 0,
add_sub15.lpm_width = 14,
add_sub15.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub16
(
.cout(),
.dataa({slevel_w12c[55:41]}),
.datab({(({13{(~ rad_ff11c[43])}} & (~ qlevel_w12c[14:2])) | ({13{rad_ff11c[43]}} & qlevel_w12c[14:2])), qlevel_w12c[1:0]}),
.overflow(),
.result(wire_add_sub16_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub16.lpm_direction = "ADD",
add_sub16.lpm_pipeline = 0,
add_sub16.lpm_width = 15,
add_sub16.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub17
(
.cout(),
.dataa({slevel_w13c[55:40]}),
.datab({(({14{(~ addnode_w12c[55])}} & (~ qlevel_w13c[15:2])) | ({14{addnode_w12c[55]}} & qlevel_w13c[15:2])), qlevel_w13c[1:0]}),
.overflow(),
.result(wire_add_sub17_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub17.lpm_direction = "ADD",
add_sub17.lpm_pipeline = 0,
add_sub17.lpm_width = 16,
add_sub17.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub18
(
.cout(),
.dataa({slevel_w14c[55:39]}),
.datab({(({15{(~ rad_ff13c[41])}} & (~ qlevel_w14c[16:2])) | ({15{rad_ff13c[41]}} & qlevel_w14c[16:2])), qlevel_w14c[1:0]}),
.overflow(),
.result(wire_add_sub18_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub18.lpm_direction = "ADD",
add_sub18.lpm_pipeline = 0,
add_sub18.lpm_width = 17,
add_sub18.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub19
(
.cout(),
.dataa({slevel_w15c[55:38]}),
.datab({(({16{(~ addnode_w14c[55])}} & (~ qlevel_w15c[17:2])) | ({16{addnode_w14c[55]}} & qlevel_w15c[17:2])), qlevel_w15c[1:0]}),
.overflow(),
.result(wire_add_sub19_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub19.lpm_direction = "ADD",
add_sub19.lpm_pipeline = 0,
add_sub19.lpm_width = 18,
add_sub19.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub20
(
.cout(),
.dataa({slevel_w16c[55:37]}),
.datab({(({17{(~ rad_ff15c[39])}} & (~ qlevel_w16c[18:2])) | ({17{rad_ff15c[39]}} & qlevel_w16c[18:2])), qlevel_w16c[1:0]}),
.overflow(),
.result(wire_add_sub20_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub20.lpm_direction = "ADD",
add_sub20.lpm_pipeline = 0,
add_sub20.lpm_width = 19,
add_sub20.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub21
(
.cout(),
.dataa({slevel_w17c[55:36]}),
.datab({(({18{(~ addnode_w16c[55])}} & (~ qlevel_w17c[19:2])) | ({18{addnode_w16c[55]}} & qlevel_w17c[19:2])), qlevel_w17c[1:0]}),
.overflow(),
.result(wire_add_sub21_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub21.lpm_direction = "ADD",
add_sub21.lpm_pipeline = 0,
add_sub21.lpm_width = 20,
add_sub21.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub22
(
.cout(),
.dataa({slevel_w18c[55:35]}),
.datab({(({19{(~ rad_ff17c[37])}} & (~ qlevel_w18c[20:2])) | ({19{rad_ff17c[37]}} & qlevel_w18c[20:2])), qlevel_w18c[1:0]}),
.overflow(),
.result(wire_add_sub22_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub22.lpm_direction = "ADD",
add_sub22.lpm_pipeline = 0,
add_sub22.lpm_width = 21,
add_sub22.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub23
(
.cout(),
.dataa({slevel_w19c[55:34]}),
.datab({(({20{(~ addnode_w18c[55])}} & (~ qlevel_w19c[21:2])) | ({20{addnode_w18c[55]}} & qlevel_w19c[21:2])), qlevel_w19c[1:0]}),
.overflow(),
.result(wire_add_sub23_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub23.lpm_direction = "ADD",
add_sub23.lpm_pipeline = 0,
add_sub23.lpm_width = 22,
add_sub23.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub24
(
.cout(),
.dataa({slevel_w20c[55:33]}),
.datab({(({21{(~ rad_ff19c[35])}} & (~ qlevel_w20c[22:2])) | ({21{rad_ff19c[35]}} & qlevel_w20c[22:2])), qlevel_w20c[1:0]}),
.overflow(),
.result(wire_add_sub24_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub24.lpm_direction = "ADD",
add_sub24.lpm_pipeline = 0,
add_sub24.lpm_width = 23,
add_sub24.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub25
(
.cout(),
.dataa({slevel_w21c[55:32]}),
.datab({(({22{(~ addnode_w20c[55])}} & (~ qlevel_w21c[23:2])) | ({22{addnode_w20c[55]}} & qlevel_w21c[23:2])), qlevel_w21c[1:0]}),
.overflow(),
.result(wire_add_sub25_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub25.lpm_direction = "ADD",
add_sub25.lpm_pipeline = 0,
add_sub25.lpm_width = 24,
add_sub25.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub26
(
.cout(),
.dataa({slevel_w22c[55:31]}),
.datab({(({23{(~ rad_ff21c[33])}} & (~ qlevel_w22c[24:2])) | ({23{rad_ff21c[33]}} & qlevel_w22c[24:2])), qlevel_w22c[1:0]}),
.overflow(),
.result(wire_add_sub26_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub26.lpm_direction = "ADD",
add_sub26.lpm_pipeline = 0,
add_sub26.lpm_width = 25,
add_sub26.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub27
(
.cout(),
.dataa({slevel_w23c[55:30]}),
.datab({(({24{(~ addnode_w22c[55])}} & (~ qlevel_w23c[25:2])) | ({24{addnode_w22c[55]}} & qlevel_w23c[25:2])), qlevel_w23c[1:0]}),
.overflow(),
.result(wire_add_sub27_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub27.lpm_direction = "ADD",
add_sub27.lpm_pipeline = 0,
add_sub27.lpm_width = 26,
add_sub27.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub28
(
.cout(),
.dataa({slevel_w24c[55:29]}),
.datab({(({25{(~ rad_ff23c[31])}} & (~ qlevel_w24c[26:2])) | ({25{rad_ff23c[31]}} & qlevel_w24c[26:2])), qlevel_w24c[1:0]}),
.overflow(),
.result(wire_add_sub28_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub28.lpm_direction = "ADD",
add_sub28.lpm_pipeline = 0,
add_sub28.lpm_width = 27,
add_sub28.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub29
(
.cout(),
.dataa({slevel_w25c[55:28]}),
.datab({(({26{(~ addnode_w24c[55])}} & (~ qlevel_w25c[27:2])) | ({26{addnode_w24c[55]}} & qlevel_w25c[27:2])), qlevel_w25c[1:0]}),
.overflow(),
.result(wire_add_sub29_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub29.lpm_direction = "ADD",
add_sub29.lpm_pipeline = 0,
add_sub29.lpm_width = 28,
add_sub29.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub30
(
.cout(),
.dataa({slevel_w26c[55:27]}),
.datab({(({27{(~ rad_ff25c[29])}} & (~ qlevel_w26c[28:2])) | ({27{rad_ff25c[29]}} & qlevel_w26c[28:2])), qlevel_w26c[1:0]}),
.overflow(),
.result(wire_add_sub30_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub30.lpm_direction = "ADD",
add_sub30.lpm_pipeline = 0,
add_sub30.lpm_width = 29,
add_sub30.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub31
(
.cout(),
.dataa({slevel_w27c[55:28]}),
.datab({(({28{(~ addnode_w26c[55])}} & (~ qlevel_w27c[29:2])) | ({28{addnode_w26c[55]}} & qlevel_w27c[29:2]))}),
.overflow(),
.result(wire_add_sub31_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub31.lpm_direction = "ADD",
add_sub31.lpm_pipeline = 0,
add_sub31.lpm_width = 28,
add_sub31.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub32
(
.cout(),
.dataa({slevel_w28c[55:28]}),
.datab({(({28{(~ rad_ff27c[27])}} & (~ qlevel_w28c[30:3])) | ({28{rad_ff27c[27]}} & qlevel_w28c[30:3]))}),
.overflow(),
.result(wire_add_sub32_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub32.lpm_direction = "ADD",
add_sub32.lpm_pipeline = 0,
add_sub32.lpm_width = 28,
add_sub32.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub33
(
.cout(),
.dataa({slevel_w29c[55:27]}),
.datab({(({29{(~ addnode_w28c[55])}} & (~ qlevel_w29c[31:3])) | ({29{addnode_w28c[55]}} & qlevel_w29c[31:3]))}),
.overflow(),
.result(wire_add_sub33_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub33.lpm_direction = "ADD",
add_sub33.lpm_pipeline = 0,
add_sub33.lpm_width = 29,
add_sub33.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub34
(
.cout(),
.dataa({slevel_w30c[55:26]}),
.datab({(({30{(~ rad_ff29c[28])}} & (~ qlevel_w30c[32:3])) | ({30{rad_ff29c[28]}} & qlevel_w30c[32:3]))}),
.overflow(),
.result(wire_add_sub34_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub34.lpm_direction = "ADD",
add_sub34.lpm_pipeline = 0,
add_sub34.lpm_width = 30,
add_sub34.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub35
(
.cout(),
.dataa({slevel_w31c[55:25]}),
.datab({(({31{(~ addnode_w30c[55])}} & (~ qlevel_w31c[33:3])) | ({31{addnode_w30c[55]}} & qlevel_w31c[33:3]))}),
.overflow(),
.result(wire_add_sub35_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub35.lpm_direction = "ADD",
add_sub35.lpm_pipeline = 0,
add_sub35.lpm_width = 31,
add_sub35.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub36
(
.cout(),
.dataa({slevel_w32c[55:24]}),
.datab({(({32{(~ rad_ff31c[30])}} & (~ qlevel_w32c[34:3])) | ({32{rad_ff31c[30]}} & qlevel_w32c[34:3]))}),
.overflow(),
.result(wire_add_sub36_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub36.lpm_direction = "ADD",
add_sub36.lpm_pipeline = 0,
add_sub36.lpm_width = 32,
add_sub36.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub37
(
.cout(),
.dataa({slevel_w33c[55:23]}),
.datab({(({33{(~ addnode_w32c[55])}} & (~ qlevel_w33c[35:3])) | ({33{addnode_w32c[55]}} & qlevel_w33c[35:3]))}),
.overflow(),
.result(wire_add_sub37_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub37.lpm_direction = "ADD",
add_sub37.lpm_pipeline = 0,
add_sub37.lpm_width = 33,
add_sub37.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub38
(
.cout(),
.dataa({slevel_w34c[55:22]}),
.datab({(({34{(~ rad_ff33c[32])}} & (~ qlevel_w34c[36:3])) | ({34{rad_ff33c[32]}} & qlevel_w34c[36:3]))}),
.overflow(),
.result(wire_add_sub38_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub38.lpm_direction = "ADD",
add_sub38.lpm_pipeline = 0,
add_sub38.lpm_width = 34,
add_sub38.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub39
(
.cout(),
.dataa({slevel_w35c[55:21]}),
.datab({(({35{(~ addnode_w34c[55])}} & (~ qlevel_w35c[37:3])) | ({35{addnode_w34c[55]}} & qlevel_w35c[37:3]))}),
.overflow(),
.result(wire_add_sub39_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub39.lpm_direction = "ADD",
add_sub39.lpm_pipeline = 0,
add_sub39.lpm_width = 35,
add_sub39.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub4
(
.cout(),
.dataa({slevel_w0c[55:53]}),
.datab({qlevel_w0c[2:0]}),
.overflow(),
.result(wire_add_sub4_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub4.lpm_direction = "ADD",
add_sub4.lpm_pipeline = 0,
add_sub4.lpm_width = 3,
add_sub4.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub40
(
.cout(),
.dataa({slevel_w36c[55:20]}),
.datab({(({36{(~ rad_ff35c[34])}} & (~ qlevel_w36c[38:3])) | ({36{rad_ff35c[34]}} & qlevel_w36c[38:3]))}),
.overflow(),
.result(wire_add_sub40_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub40.lpm_direction = "ADD",
add_sub40.lpm_pipeline = 0,
add_sub40.lpm_width = 36,
add_sub40.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub41
(
.cout(),
.dataa({slevel_w37c[55:19]}),
.datab({(({37{(~ addnode_w36c[55])}} & (~ qlevel_w37c[39:3])) | ({37{addnode_w36c[55]}} & qlevel_w37c[39:3]))}),
.overflow(),
.result(wire_add_sub41_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub41.lpm_direction = "ADD",
add_sub41.lpm_pipeline = 0,
add_sub41.lpm_width = 37,
add_sub41.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub42
(
.cout(),
.dataa({slevel_w38c[55:18]}),
.datab({(({38{(~ rad_ff37c[36])}} & (~ qlevel_w38c[40:3])) | ({38{rad_ff37c[36]}} & qlevel_w38c[40:3]))}),
.overflow(),
.result(wire_add_sub42_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub42.lpm_direction = "ADD",
add_sub42.lpm_pipeline = 0,
add_sub42.lpm_width = 38,
add_sub42.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub43
(
.cout(),
.dataa({slevel_w39c[55:17]}),
.datab({(({39{(~ addnode_w38c[55])}} & (~ qlevel_w39c[41:3])) | ({39{addnode_w38c[55]}} & qlevel_w39c[41:3]))}),
.overflow(),
.result(wire_add_sub43_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub43.lpm_direction = "ADD",
add_sub43.lpm_pipeline = 0,
add_sub43.lpm_width = 39,
add_sub43.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub44
(
.cout(),
.dataa({slevel_w40c[55:16]}),
.datab({(({40{(~ rad_ff39c[38])}} & (~ qlevel_w40c[42:3])) | ({40{rad_ff39c[38]}} & qlevel_w40c[42:3]))}),
.overflow(),
.result(wire_add_sub44_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub44.lpm_direction = "ADD",
add_sub44.lpm_pipeline = 0,
add_sub44.lpm_width = 40,
add_sub44.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub45
(
.cout(),
.dataa({slevel_w41c[55:15]}),
.datab({(({41{(~ addnode_w40c[55])}} & (~ qlevel_w41c[43:3])) | ({41{addnode_w40c[55]}} & qlevel_w41c[43:3]))}),
.overflow(),
.result(wire_add_sub45_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub45.lpm_direction = "ADD",
add_sub45.lpm_pipeline = 0,
add_sub45.lpm_width = 41,
add_sub45.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub46
(
.cout(),
.dataa({slevel_w42c[55:14]}),
.datab({(({42{(~ rad_ff41c[40])}} & (~ qlevel_w42c[44:3])) | ({42{rad_ff41c[40]}} & qlevel_w42c[44:3]))}),
.overflow(),
.result(wire_add_sub46_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub46.lpm_direction = "ADD",
add_sub46.lpm_pipeline = 0,
add_sub46.lpm_width = 42,
add_sub46.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub47
(
.cout(),
.dataa({slevel_w43c[55:13]}),
.datab({(({43{(~ addnode_w42c[55])}} & (~ qlevel_w43c[45:3])) | ({43{addnode_w42c[55]}} & qlevel_w43c[45:3]))}),
.overflow(),
.result(wire_add_sub47_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub47.lpm_direction = "ADD",
add_sub47.lpm_pipeline = 0,
add_sub47.lpm_width = 43,
add_sub47.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub48
(
.cout(),
.dataa({slevel_w44c[55:12]}),
.datab({(({44{(~ rad_ff43c[42])}} & (~ qlevel_w44c[46:3])) | ({44{rad_ff43c[42]}} & qlevel_w44c[46:3]))}),
.overflow(),
.result(wire_add_sub48_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub48.lpm_direction = "ADD",
add_sub48.lpm_pipeline = 0,
add_sub48.lpm_width = 44,
add_sub48.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub49
(
.cout(),
.dataa({slevel_w45c[55:11]}),
.datab({(({45{(~ addnode_w44c[55])}} & (~ qlevel_w45c[47:3])) | ({45{addnode_w44c[55]}} & qlevel_w45c[47:3]))}),
.overflow(),
.result(wire_add_sub49_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub49.lpm_direction = "ADD",
add_sub49.lpm_pipeline = 0,
add_sub49.lpm_width = 45,
add_sub49.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub5
(
.cout(),
.dataa({slevel_w1c[55:52]}),
.datab({qlevel_w1c[3:0]}),
.overflow(),
.result(wire_add_sub5_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub5.lpm_direction = "ADD",
add_sub5.lpm_pipeline = 0,
add_sub5.lpm_width = 4,
add_sub5.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub50
(
.cout(),
.dataa({slevel_w46c[55:10]}),
.datab({(({46{(~ rad_ff45c[44])}} & (~ qlevel_w46c[48:3])) | ({46{rad_ff45c[44]}} & qlevel_w46c[48:3]))}),
.overflow(),
.result(wire_add_sub50_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub50.lpm_direction = "ADD",
add_sub50.lpm_pipeline = 0,
add_sub50.lpm_width = 46,
add_sub50.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub51
(
.cout(),
.dataa({slevel_w47c[55:9]}),
.datab({(({47{(~ addnode_w46c[55])}} & (~ qlevel_w47c[49:3])) | ({47{addnode_w46c[55]}} & qlevel_w47c[49:3]))}),
.overflow(),
.result(wire_add_sub51_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub51.lpm_direction = "ADD",
add_sub51.lpm_pipeline = 0,
add_sub51.lpm_width = 47,
add_sub51.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub52
(
.cout(),
.dataa({slevel_w48c[55:8]}),
.datab({(({48{(~ rad_ff47c[46])}} & (~ qlevel_w48c[50:3])) | ({48{rad_ff47c[46]}} & qlevel_w48c[50:3]))}),
.overflow(),
.result(wire_add_sub52_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub52.lpm_direction = "ADD",
add_sub52.lpm_pipeline = 0,
add_sub52.lpm_width = 48,
add_sub52.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub53
(
.cout(),
.dataa({slevel_w49c[55:7]}),
.datab({(({49{(~ addnode_w48c[55])}} & (~ qlevel_w49c[51:3])) | ({49{addnode_w48c[55]}} & qlevel_w49c[51:3]))}),
.overflow(),
.result(wire_add_sub53_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub53.lpm_direction = "ADD",
add_sub53.lpm_pipeline = 0,
add_sub53.lpm_width = 49,
add_sub53.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub54
(
.cout(),
.dataa({slevel_w50c[55:6]}),
.datab({(({50{(~ rad_ff49c[48])}} & (~ qlevel_w50c[52:3])) | ({50{rad_ff49c[48]}} & qlevel_w50c[52:3]))}),
.overflow(),
.result(wire_add_sub54_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub54.lpm_direction = "ADD",
add_sub54.lpm_pipeline = 0,
add_sub54.lpm_width = 50,
add_sub54.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub55
(
.cout(),
.dataa({slevel_w51c[55:5]}),
.datab({(({51{(~ addnode_w50c[55])}} & (~ qlevel_w51c[53:3])) | ({51{addnode_w50c[55]}} & qlevel_w51c[53:3]))}),
.overflow(),
.result(wire_add_sub55_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub55.lpm_direction = "ADD",
add_sub55.lpm_pipeline = 0,
add_sub55.lpm_width = 51,
add_sub55.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub56
(
.cout(),
.dataa({slevel_w52c[55:4]}),
.datab({(({52{(~ rad_ff51c[50])}} & (~ qlevel_w52c[54:3])) | ({52{rad_ff51c[50]}} & qlevel_w52c[54:3]))}),
.overflow(),
.result(wire_add_sub56_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub56.lpm_direction = "ADD",
add_sub56.lpm_pipeline = 0,
add_sub56.lpm_width = 52,
add_sub56.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub57
(
.cout(),
.dataa({slevel_w53c[55:3]}),
.datab({qlevel_w53c[55:54], (({51{(~ addnode_w52c[55])}} & (~ qlevel_w53c[53:3])) | ({51{addnode_w52c[55]}} & qlevel_w53c[53:3]))}),
.overflow(),
.result(wire_add_sub57_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub57.lpm_direction = "ADD",
add_sub57.lpm_pipeline = 0,
add_sub57.lpm_width = 53,
add_sub57.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub6
(
.cout(),
.dataa({slevel_w2c[55:51]}),
.datab({(({3{(~ rad_ff1c[53])}} & (~ qlevel_w2c[4:2])) | ({3{rad_ff1c[53]}} & qlevel_w2c[4:2])), qlevel_w2c[1:0]}),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_direction = "ADD",
add_sub6.lpm_pipeline = 0,
add_sub6.lpm_width = 5,
add_sub6.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub7
(
.cout(),
.dataa({slevel_w3c[55:50]}),
.datab({(({4{(~ addnode_w2c[55])}} & (~ qlevel_w3c[5:2])) | ({4{addnode_w2c[55]}} & qlevel_w3c[5:2])), qlevel_w3c[1:0]}),
.overflow(),
.result(wire_add_sub7_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub7.lpm_direction = "ADD",
add_sub7.lpm_pipeline = 0,
add_sub7.lpm_width = 6,
add_sub7.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub8
(
.cout(),
.dataa({slevel_w4c[55:49]}),
.datab({(({5{(~ rad_ff3c[51])}} & (~ qlevel_w4c[6:2])) | ({5{rad_ff3c[51]}} & qlevel_w4c[6:2])), qlevel_w4c[1:0]}),
.overflow(),
.result(wire_add_sub8_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub8.lpm_direction = "ADD",
add_sub8.lpm_pipeline = 0,
add_sub8.lpm_width = 7,
add_sub8.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub9
(
.cout(),
.dataa({slevel_w5c[55:48]}),
.datab({(({6{(~ addnode_w4c[55])}} & (~ qlevel_w5c[7:2])) | ({6{addnode_w4c[55]}} & qlevel_w5c[7:2])), qlevel_w5c[1:0]}),
.overflow(),
.result(wire_add_sub9_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub9.lpm_direction = "ADD",
add_sub9.lpm_pipeline = 0,
add_sub9.lpm_width = 8,
add_sub9.lpm_type = "lpm_add_sub";
assign
addnode_w0c = {wire_add_sub4_result[2:0], slevel_w0c[52:0]},
addnode_w10c = {wire_add_sub14_result[12:0], slevel_w10c[42:0]},
addnode_w11c = {wire_add_sub15_result[13:0], slevel_w11c[41:0]},
addnode_w12c = {wire_add_sub16_result[14:0], slevel_w12c[40:0]},
addnode_w13c = {wire_add_sub17_result[15:0], slevel_w13c[39:0]},
addnode_w14c = {wire_add_sub18_result[16:0], slevel_w14c[38:0]},
addnode_w15c = {wire_add_sub19_result[17:0], slevel_w15c[37:0]},
addnode_w16c = {wire_add_sub20_result[18:0], slevel_w16c[36:0]},
addnode_w17c = {wire_add_sub21_result[19:0], slevel_w17c[35:0]},
addnode_w18c = {wire_add_sub22_result[20:0], slevel_w18c[34:0]},
addnode_w19c = {wire_add_sub23_result[21:0], slevel_w19c[33:0]},
addnode_w1c = {wire_add_sub5_result[3:0], slevel_w1c[51:0]},
addnode_w20c = {wire_add_sub24_result[22:0], slevel_w20c[32:0]},
addnode_w21c = {wire_add_sub25_result[23:0], slevel_w21c[31:0]},
addnode_w22c = {wire_add_sub26_result[24:0], slevel_w22c[30:0]},
addnode_w23c = {wire_add_sub27_result[25:0], slevel_w23c[29:0]},
addnode_w24c = {wire_add_sub28_result[26:0], slevel_w24c[28:0]},
addnode_w25c = {wire_add_sub29_result[27:0], slevel_w25c[27:0]},
addnode_w26c = {wire_add_sub30_result[28:0], slevel_w26c[26:0]},
addnode_w27c = {wire_add_sub31_result[27:0], qlevel_w27c[1:0], slevel_w27c[25:0]},
addnode_w28c = {wire_add_sub32_result[27:0], 1'b1, qlevel_w28c[1:0], slevel_w28c[24:0]},
addnode_w29c = {wire_add_sub33_result[28:0], 1'b1, qlevel_w29c[1:0], slevel_w29c[23:0]},
addnode_w2c = {wire_add_sub6_result[4:0], slevel_w2c[50:0]},
addnode_w30c = {wire_add_sub34_result[29:0], 1'b1, qlevel_w30c[1:0], slevel_w30c[22:0]},
addnode_w31c = {wire_add_sub35_result[30:0], 1'b1, qlevel_w31c[1:0], slevel_w31c[21:0]},
addnode_w32c = {wire_add_sub36_result[31:0], 1'b1, qlevel_w32c[1:0], slevel_w32c[20:0]},
addnode_w33c = {wire_add_sub37_result[32:0], 1'b1, qlevel_w33c[1:0], slevel_w33c[19:0]},
addnode_w34c = {wire_add_sub38_result[33:0], 1'b1, qlevel_w34c[1:0], slevel_w34c[18:0]},
addnode_w35c = {wire_add_sub39_result[34:0], 1'b1, qlevel_w35c[1:0], slevel_w35c[17:0]},
addnode_w36c = {wire_add_sub40_result[35:0], 1'b1, qlevel_w36c[1:0], slevel_w36c[16:0]},
addnode_w37c = {wire_add_sub41_result[36:0], 1'b1, qlevel_w37c[1:0], slevel_w37c[15:0]},
addnode_w38c = {wire_add_sub42_result[37:0], 1'b1, qlevel_w38c[1:0], slevel_w38c[14:0]},
addnode_w39c = {wire_add_sub43_result[38:0], 1'b1, qlevel_w39c[1:0], slevel_w39c[13:0]},
addnode_w3c = {wire_add_sub7_result[5:0], slevel_w3c[49:0]},
addnode_w40c = {wire_add_sub44_result[39:0], 1'b1, qlevel_w40c[1:0], slevel_w40c[12:0]},
addnode_w41c = {wire_add_sub45_result[40:0], 1'b1, qlevel_w41c[1:0], slevel_w41c[11:0]},
addnode_w42c = {wire_add_sub46_result[41:0], 1'b1, qlevel_w42c[1:0], slevel_w42c[10:0]},
addnode_w43c = {wire_add_sub47_result[42:0], 1'b1, qlevel_w43c[1:0], slevel_w43c[9:0]},
addnode_w44c = {wire_add_sub48_result[43:0], 1'b1, qlevel_w44c[1:0], slevel_w44c[8:0]},
addnode_w45c = {wire_add_sub49_result[44:0], 1'b1, qlevel_w45c[1:0], slevel_w45c[7:0]},
addnode_w46c = {wire_add_sub50_result[45:0], 1'b1, qlevel_w46c[1:0], slevel_w46c[6:0]},
addnode_w47c = {wire_add_sub51_result[46:0], 1'b1, qlevel_w47c[1:0], slevel_w47c[5:0]},
addnode_w48c = {wire_add_sub52_result[47:0], 1'b1, qlevel_w48c[1:0], slevel_w48c[4:0]},
addnode_w49c = {wire_add_sub53_result[48:0], 1'b1, qlevel_w49c[1:0], slevel_w49c[3:0]},
addnode_w4c = {wire_add_sub8_result[6:0], slevel_w4c[48:0]},
addnode_w50c = {wire_add_sub54_result[49:0], 1'b1, qlevel_w50c[1:0], slevel_w50c[2:0]},
addnode_w51c = {wire_add_sub55_result[50:0], 1'b1, qlevel_w51c[1:0], slevel_w51c[1:0]},
addnode_w52c = {wire_add_sub56_result[51:0], 1'b1, qlevel_w52c[1:0], slevel_w52c[0]},
addnode_w53c = {wire_add_sub57_result[52:0], 1'b1, qlevel_w53c[1:0]},
addnode_w5c = {wire_add_sub9_result[7:0], slevel_w5c[47:0]},
addnode_w6c = {wire_add_sub10_result[8:0], slevel_w6c[46:0]},
addnode_w7c = {wire_add_sub11_result[9:0], slevel_w7c[45:0]},
addnode_w8c = {wire_add_sub12_result[10:0], slevel_w8c[44:0]},
addnode_w9c = {wire_add_sub13_result[11:0], slevel_w9c[43:0]},
qlevel_w0c = {3{1'b1}},
qlevel_w10c = {1'b0, 1'b1, q_ff52c[4], q_ff50c[7:6], q_ff48c[5:4], q_ff46c[3:2], q_ff44c[1:0], {2{1'b1}}},
qlevel_w11c = {1'b0, 1'b1, q_ff52c[4], q_ff50c[7:6], q_ff48c[5:4], q_ff46c[3:2], q_ff44c[1:0], (~ addnode_w10c[55]), {2{1'b1}}},
qlevel_w12c = {1'b0, 1'b1, q_ff52c[5], q_ff50c[9:8], q_ff48c[7:6], q_ff46c[5:4], q_ff44c[3:2], q_ff42c[1:0], {2{1'b1}}},
qlevel_w13c = {1'b0, 1'b1, q_ff52c[5], q_ff50c[9:8], q_ff48c[7:6], q_ff46c[5:4], q_ff44c[3:2], q_ff42c[1:0], (~ addnode_w12c[55]), {2{1'b1}}},
qlevel_w14c = {1'b0, 1'b1, q_ff52c[6], q_ff50c[11:10], q_ff48c[9:8], q_ff46c[7:6], q_ff44c[5:4], q_ff42c[3:2], q_ff40c[1:0], {2{1'b1}}},
qlevel_w15c = {1'b0, 1'b1, q_ff52c[6], q_ff50c[11:10], q_ff48c[9:8], q_ff46c[7:6], q_ff44c[5:4], q_ff42c[3:2], q_ff40c[1:0], (~ addnode_w14c[55]), {2{1'b1}}},
qlevel_w16c = {1'b0, 1'b1, q_ff52c[7], q_ff50c[13:12], q_ff48c[11:10], q_ff46c[9:8], q_ff44c[7:6], q_ff42c[5:4], q_ff40c[3:2], q_ff38c[1:0], {2{1'b1}}},
qlevel_w17c = {1'b0, 1'b1, q_ff52c[7], q_ff50c[13:12], q_ff48c[11:10], q_ff46c[9:8], q_ff44c[7:6], q_ff42c[5:4], q_ff40c[3:2], q_ff38c[1:0], (~ addnode_w16c[55]), {2{1'b1}}},
qlevel_w18c = {1'b0, 1'b1, q_ff52c[8], q_ff50c[15:14], q_ff48c[13:12], q_ff46c[11:10], q_ff44c[9:8], q_ff42c[7:6], q_ff40c[5:4], q_ff38c[3:2], q_ff36c[1:0], {2{1'b1}}},
qlevel_w19c = {1'b0, 1'b1, q_ff52c[8], q_ff50c[15:14], q_ff48c[13:12], q_ff46c[11:10], q_ff44c[9:8], q_ff42c[7:6], q_ff40c[5:4], q_ff38c[3:2], q_ff36c[1:0], (~ addnode_w18c[55]), {2{1'b1}}},
qlevel_w1c = {1'b1, 1'b0, {2{1'b1}}},
qlevel_w20c = {1'b0, 1'b1, q_ff52c[9], q_ff50c[17:16], q_ff48c[15:14], q_ff46c[13:12], q_ff44c[11:10], q_ff42c[9:8], q_ff40c[7:6], q_ff38c[5:4], q_ff36c[3:2], q_ff34c[1:0], {2{1'b1}}},
qlevel_w21c = {1'b0, 1'b1, q_ff52c[9], q_ff50c[17:16], q_ff48c[15:14], q_ff46c[13:12], q_ff44c[11:10], q_ff42c[9:8], q_ff40c[7:6], q_ff38c[5:4], q_ff36c[3:2], q_ff34c[1:0], (~ addnode_w20c[55]), {2{1'b1}}},
qlevel_w22c = {1'b0, 1'b1, q_ff52c[10], q_ff50c[19:18], q_ff48c[17:16], q_ff46c[15:14], q_ff44c[13:12], q_ff42c[11:10], q_ff40c[9:8], q_ff38c[7:6], q_ff36c[5:4], q_ff34c[3:2], q_ff32c[1:0], {2{1'b1}}},
qlevel_w23c = {1'b0, 1'b1, q_ff52c[10], q_ff50c[19:18], q_ff48c[17:16], q_ff46c[15:14], q_ff44c[13:12], q_ff42c[11:10], q_ff40c[9:8], q_ff38c[7:6], q_ff36c[5:4], q_ff34c[3:2], q_ff32c[1:0], (~ addnode_w22c[55]), {2{1'b1}}},
qlevel_w24c = {1'b0, 1'b1, q_ff52c[11], q_ff50c[21:20], q_ff48c[19:18], q_ff46c[17:16], q_ff44c[15:14], q_ff42c[13:12], q_ff40c[11:10], q_ff38c[9:8], q_ff36c[7:6], q_ff34c[5:4], q_ff32c[3:2], q_ff30c[1:0], {2{1'b1}}},
qlevel_w25c = {1'b0, 1'b1, q_ff52c[11], q_ff50c[21:20], q_ff48c[19:18], q_ff46c[17:16], q_ff44c[15:14], q_ff42c[13:12], q_ff40c[11:10], q_ff38c[9:8], q_ff36c[7:6], q_ff34c[5:4], q_ff32c[3:2], q_ff30c[1:0], (~ addnode_w24c[55]), {2{1'b1}}},
qlevel_w26c = {1'b0, 1'b1, q_ff52c[12], q_ff50c[23:22], q_ff48c[21:20], q_ff46c[19:18], q_ff44c[17:16], q_ff42c[15:14], q_ff40c[13:12], q_ff38c[11:10], q_ff36c[9:8], q_ff34c[7:6], q_ff32c[5:4], q_ff30c[3:2], q_ff28c[1:0], {2{1'b1}}},
qlevel_w27c = {1'b0, 1'b1, q_ff52c[12], q_ff50c[23:22], q_ff48c[21:20], q_ff46c[19:18], q_ff44c[17:16], q_ff42c[15:14], q_ff40c[13:12], q_ff38c[11:10], q_ff36c[9:8], q_ff34c[7:6], q_ff32c[5:4], q_ff30c[3:2], q_ff28c[1:0], (~ addnode_w26c[55]), {2{1'b1}}},
qlevel_w28c = {1'b0, 1'b1, q_ff52c[13], q_ff50c[25:24], q_ff48c[23:22], q_ff46c[21:20], q_ff44c[19:18], q_ff42c[17:16], q_ff40c[15:14], q_ff38c[13:12], q_ff36c[11:10], q_ff34c[9:8], q_ff32c[7:6], q_ff30c[5:4], q_ff28c[3:2], q_ff26c[1:0], {2{1'b1}}},
qlevel_w29c = {1'b0, 1'b1, q_ff52c[13], q_ff50c[25:24], q_ff48c[23:22], q_ff46c[21:20], q_ff44c[19:18], q_ff42c[17:16], q_ff40c[15:14], q_ff38c[13:12], q_ff36c[11:10], q_ff34c[9:8], q_ff32c[7:6], q_ff30c[5:4], q_ff28c[3:2], q_ff26c[1:0], (~ addnode_w28c[55]), {2{1'b1}}},
qlevel_w2c = {1'b0, 1'b1, q_ff52c[0], {2{1'b1}}},
qlevel_w30c = {1'b0, 1'b1, q_ff52c[14], q_ff50c[27:26], q_ff48c[25:24], q_ff46c[23:22], q_ff44c[21:20], q_ff42c[19:18], q_ff40c[17:16], q_ff38c[15:14], q_ff36c[13:12], q_ff34c[11:10], q_ff32c[9:8], q_ff30c[7:6], q_ff28c[5:4], q_ff26c[3:2], q_ff24c[1:0], {2{1'b1}}},
qlevel_w31c = {1'b0, 1'b1, q_ff52c[14], q_ff50c[27:26], q_ff48c[25:24], q_ff46c[23:22], q_ff44c[21:20], q_ff42c[19:18], q_ff40c[17:16], q_ff38c[15:14], q_ff36c[13:12], q_ff34c[11:10], q_ff32c[9:8], q_ff30c[7:6], q_ff28c[5:4], q_ff26c[3:2], q_ff24c[1:0], (~ addnode_w30c[55]), {2{1'b1}}},
qlevel_w32c = {1'b0, 1'b1, q_ff52c[15], q_ff50c[29:28], q_ff48c[27:26], q_ff46c[25:24], q_ff44c[23:22], q_ff42c[21:20], q_ff40c[19:18], q_ff38c[17:16], q_ff36c[15:14], q_ff34c[13:12], q_ff32c[11:10], q_ff30c[9:8], q_ff28c[7:6], q_ff26c[5:4], q_ff24c[3:2], q_ff22c[1:0], {2{1'b1}}},
qlevel_w33c = {1'b0, 1'b1, q_ff52c[15], q_ff50c[29:28], q_ff48c[27:26], q_ff46c[25:24], q_ff44c[23:22], q_ff42c[21:20], q_ff40c[19:18], q_ff38c[17:16], q_ff36c[15:14], q_ff34c[13:12], q_ff32c[11:10], q_ff30c[9:8], q_ff28c[7:6], q_ff26c[5:4], q_ff24c[3:2], q_ff22c[1:0], (~ addnode_w32c[55]), {2{1'b1}}},
qlevel_w34c = {1'b0, 1'b1, q_ff52c[16], q_ff50c[31:30], q_ff48c[29:28], q_ff46c[27:26], q_ff44c[25:24], q_ff42c[23:22], q_ff40c[21:20], q_ff38c[19:18], q_ff36c[17:16], q_ff34c[15:14], q_ff32c[13:12], q_ff30c[11:10], q_ff28c[9:8], q_ff26c[7:6], q_ff24c[5:4], q_ff22c[3:2], q_ff20c[1:0], {2{1'b1}}},
qlevel_w35c = {1'b0, 1'b1, q_ff52c[16], q_ff50c[31:30], q_ff48c[29:28], q_ff46c[27:26], q_ff44c[25:24], q_ff42c[23:22], q_ff40c[21:20], q_ff38c[19:18], q_ff36c[17:16], q_ff34c[15:14], q_ff32c[13:12], q_ff30c[11:10], q_ff28c[9:8], q_ff26c[7:6], q_ff24c[5:4], q_ff22c[3:2], q_ff20c[1:0], (~ addnode_w34c[55]), {2{1'b1}}},
qlevel_w36c = {1'b0, 1'b1, q_ff52c[17], q_ff50c[33:32], q_ff48c[31:30], q_ff46c[29:28], q_ff44c[27:26], q_ff42c[25:24], q_ff40c[23:22], q_ff38c[21:20], q_ff36c[19:18], q_ff34c[17:16], q_ff32c[15:14], q_ff30c[13:12], q_ff28c[11:10], q_ff26c[9:8], q_ff24c[7:6], q_ff22c[5:4], q_ff20c[3:2], q_ff18c[1:0], {2{1'b1}}},
qlevel_w37c = {1'b0, 1'b1, q_ff52c[17], q_ff50c[33:32], q_ff48c[31:30], q_ff46c[29:28], q_ff44c[27:26], q_ff42c[25:24], q_ff40c[23:22], q_ff38c[21:20], q_ff36c[19:18], q_ff34c[17:16], q_ff32c[15:14], q_ff30c[13:12], q_ff28c[11:10], q_ff26c[9:8], q_ff24c[7:6], q_ff22c[5:4], q_ff20c[3:2], q_ff18c[1:0], (~ addnode_w36c[55]), {2{1'b1}}},
qlevel_w38c = {1'b0, 1'b1, q_ff52c[18], q_ff50c[35:34], q_ff48c[33:32], q_ff46c[31:30], q_ff44c[29:28], q_ff42c[27:26], q_ff40c[25:24], q_ff38c[23:22], q_ff36c[21:20], q_ff34c[19:18], q_ff32c[17:16], q_ff30c[15:14], q_ff28c[13:12], q_ff26c[11:10], q_ff24c[9:8], q_ff22c[7:6], q_ff20c[5:4], q_ff18c[3:2], q_ff16c[1:0], {2{1'b1}}},
qlevel_w39c = {1'b0, 1'b1, q_ff52c[18], q_ff50c[35:34], q_ff48c[33:32], q_ff46c[31:30], q_ff44c[29:28], q_ff42c[27:26], q_ff40c[25:24], q_ff38c[23:22], q_ff36c[21:20], q_ff34c[19:18], q_ff32c[17:16], q_ff30c[15:14], q_ff28c[13:12], q_ff26c[11:10], q_ff24c[9:8], q_ff22c[7:6], q_ff20c[5:4], q_ff18c[3:2], q_ff16c[1:0], (~ addnode_w38c[55]), {2{1'b1}}},
qlevel_w3c = {1'b0, 1'b1, q_ff52c[0], (~ addnode_w2c[55]), {2{1'b1}}},
qlevel_w40c = {1'b0, 1'b1, q_ff52c[19], q_ff50c[37:36], q_ff48c[35:34], q_ff46c[33:32], q_ff44c[31:30], q_ff42c[29:28], q_ff40c[27:26], q_ff38c[25:24], q_ff36c[23:22], q_ff34c[21:20], q_ff32c[19:18], q_ff30c[17:16], q_ff28c[15:14], q_ff26c[13:12], q_ff24c[11:10], q_ff22c[9:8], q_ff20c[7:6], q_ff18c[5:4], q_ff16c[3:2], q_ff14c[1:0], {2{1'b1}}},
qlevel_w41c = {1'b0, 1'b1, q_ff52c[19], q_ff50c[37:36], q_ff48c[35:34], q_ff46c[33:32], q_ff44c[31:30], q_ff42c[29:28], q_ff40c[27:26], q_ff38c[25:24], q_ff36c[23:22], q_ff34c[21:20], q_ff32c[19:18], q_ff30c[17:16], q_ff28c[15:14], q_ff26c[13:12], q_ff24c[11:10], q_ff22c[9:8], q_ff20c[7:6], q_ff18c[5:4], q_ff16c[3:2], q_ff14c[1:0], (~ addnode_w40c[55]), {2{1'b1}}},
qlevel_w42c = {1'b0, 1'b1, q_ff52c[20], q_ff50c[39:38], q_ff48c[37:36], q_ff46c[35:34], q_ff44c[33:32], q_ff42c[31:30], q_ff40c[29:28], q_ff38c[27:26], q_ff36c[25:24], q_ff34c[23:22], q_ff32c[21:20], q_ff30c[19:18], q_ff28c[17:16], q_ff26c[15:14], q_ff24c[13:12], q_ff22c[11:10], q_ff20c[9:8], q_ff18c[7:6], q_ff16c[5:4], q_ff14c[3:2], q_ff12c[1:0], {2{1'b1}}},
qlevel_w43c = {1'b0, 1'b1, q_ff52c[20], q_ff50c[39:38], q_ff48c[37:36], q_ff46c[35:34], q_ff44c[33:32], q_ff42c[31:30], q_ff40c[29:28], q_ff38c[27:26], q_ff36c[25:24], q_ff34c[23:22], q_ff32c[21:20], q_ff30c[19:18], q_ff28c[17:16], q_ff26c[15:14], q_ff24c[13:12], q_ff22c[11:10], q_ff20c[9:8], q_ff18c[7:6], q_ff16c[5:4], q_ff14c[3:2], q_ff12c[1:0], (~ addnode_w42c[55]), {2{1'b1}}},
qlevel_w44c = {1'b0, 1'b1, q_ff52c[21], q_ff50c[41:40], q_ff48c[39:38], q_ff46c[37:36], q_ff44c[35:34], q_ff42c[33:32], q_ff40c[31:30], q_ff38c[29:28], q_ff36c[27:26], q_ff34c[25:24], q_ff32c[23:22], q_ff30c[21:20], q_ff28c[19:18], q_ff26c[17:16], q_ff24c[15:14], q_ff22c[13:12], q_ff20c[11:10], q_ff18c[9:8], q_ff16c[7:6], q_ff14c[5:4], q_ff12c[3:2], q_ff10c[1:0], {2{1'b1}}},
qlevel_w45c = {1'b0, 1'b1, q_ff52c[21], q_ff50c[41:40], q_ff48c[39:38], q_ff46c[37:36], q_ff44c[35:34], q_ff42c[33:32], q_ff40c[31:30], q_ff38c[29:28], q_ff36c[27:26], q_ff34c[25:24], q_ff32c[23:22], q_ff30c[21:20], q_ff28c[19:18], q_ff26c[17:16], q_ff24c[15:14], q_ff22c[13:12], q_ff20c[11:10], q_ff18c[9:8], q_ff16c[7:6], q_ff14c[5:4], q_ff12c[3:2], q_ff10c[1:0], (~ addnode_w44c[55]), {2{1'b1}}},
qlevel_w46c = {1'b0, 1'b1, q_ff52c[22], q_ff50c[43:42], q_ff48c[41:40], q_ff46c[39:38], q_ff44c[37:36], q_ff42c[35:34], q_ff40c[33:32], q_ff38c[31:30], q_ff36c[29:28], q_ff34c[27:26], q_ff32c[25:24], q_ff30c[23:22], q_ff28c[21:20], q_ff26c[19:18], q_ff24c[17:16], q_ff22c[15:14], q_ff20c[13:12], q_ff18c[11:10], q_ff16c[9:8], q_ff14c[7:6], q_ff12c[5:4], q_ff10c[3:2], q_ff8c[1:0], {2{1'b1}}},
qlevel_w47c = {1'b0, 1'b1, q_ff52c[22], q_ff50c[43:42], q_ff48c[41:40], q_ff46c[39:38], q_ff44c[37:36], q_ff42c[35:34], q_ff40c[33:32], q_ff38c[31:30], q_ff36c[29:28], q_ff34c[27:26], q_ff32c[25:24], q_ff30c[23:22], q_ff28c[21:20], q_ff26c[19:18], q_ff24c[17:16], q_ff22c[15:14], q_ff20c[13:12], q_ff18c[11:10], q_ff16c[9:8], q_ff14c[7:6], q_ff12c[5:4], q_ff10c[3:2], q_ff8c[1:0], (~ addnode_w46c[55]), {2{1'b1}}},
qlevel_w48c = {1'b0, 1'b1, q_ff52c[23], q_ff50c[45:44], q_ff48c[43:42], q_ff46c[41:40], q_ff44c[39:38], q_ff42c[37:36], q_ff40c[35:34], q_ff38c[33:32], q_ff36c[31:30], q_ff34c[29:28], q_ff32c[27:26], q_ff30c[25:24], q_ff28c[23:22], q_ff26c[21:20], q_ff24c[19:18], q_ff22c[17:16], q_ff20c[15:14], q_ff18c[13:12], q_ff16c[11:10], q_ff14c[9:8], q_ff12c[7:6], q_ff10c[5:4], q_ff8c[3:2], q_ff6c[1:0], {2{1'b1}}},
qlevel_w49c = {1'b0, 1'b1, q_ff52c[23], q_ff50c[45:44], q_ff48c[43:42], q_ff46c[41:40], q_ff44c[39:38], q_ff42c[37:36], q_ff40c[35:34], q_ff38c[33:32], q_ff36c[31:30], q_ff34c[29:28], q_ff32c[27:26], q_ff30c[25:24], q_ff28c[23:22], q_ff26c[21:20], q_ff24c[19:18], q_ff22c[17:16], q_ff20c[15:14], q_ff18c[13:12], q_ff16c[11:10], q_ff14c[9:8], q_ff12c[7:6], q_ff10c[5:4], q_ff8c[3:2], q_ff6c[1:0], (~ addnode_w48c[55]), {2{1'b1}}},
qlevel_w4c = {1'b0, 1'b1, q_ff52c[1], q_ff50c[1:0], {2{1'b1}}},
qlevel_w50c = {1'b0, 1'b1, q_ff52c[24], q_ff50c[47:46], q_ff48c[45:44], q_ff46c[43:42], q_ff44c[41:40], q_ff42c[39:38], q_ff40c[37:36], q_ff38c[35:34], q_ff36c[33:32], q_ff34c[31:30], q_ff32c[29:28], q_ff30c[27:26], q_ff28c[25:24], q_ff26c[23:22], q_ff24c[21:20], q_ff22c[19:18], q_ff20c[17:16], q_ff18c[15:14], q_ff16c[13:12], q_ff14c[11:10], q_ff12c[9:8], q_ff10c[7:6], q_ff8c[5:4], q_ff6c[3:2], q_ff4c[1:0], {2{1'b1}}},
qlevel_w51c = {1'b0, 1'b1, q_ff52c[24], q_ff50c[47:46], q_ff48c[45:44], q_ff46c[43:42], q_ff44c[41:40], q_ff42c[39:38], q_ff40c[37:36], q_ff38c[35:34], q_ff36c[33:32], q_ff34c[31:30], q_ff32c[29:28], q_ff30c[27:26], q_ff28c[25:24], q_ff26c[23:22], q_ff24c[21:20], q_ff22c[19:18], q_ff20c[17:16], q_ff18c[15:14], q_ff16c[13:12], q_ff14c[11:10], q_ff12c[9:8], q_ff10c[7:6], q_ff8c[5:4], q_ff6c[3:2], q_ff4c[1:0], (~ addnode_w50c[55]), {2{1'b1}}},
qlevel_w52c = {1'b0, 1'b1, q_ff52c[25], q_ff50c[49:48], q_ff48c[47:46], q_ff46c[45:44], q_ff44c[43:42], q_ff42c[41:40], q_ff40c[39:38], q_ff38c[37:36], q_ff36c[35:34], q_ff34c[33:32], q_ff32c[31:30], q_ff30c[29:28], q_ff28c[27:26], q_ff26c[25:24], q_ff24c[23:22], q_ff22c[21:20], q_ff20c[19:18], q_ff18c[17:16], q_ff16c[15:14], q_ff14c[13:12], q_ff12c[11:10], q_ff10c[9:8], q_ff8c[7:6], q_ff6c[5:4], q_ff4c[3:2], q_ff2c[1:0], {2{1'b1}}},
qlevel_w53c = {(~ addnode_w52c[55]), addnode_w52c[55], q_ff52c[25], q_ff50c[49:48], q_ff48c[47:46], q_ff46c[45:44], q_ff44c[43:42], q_ff42c[41:40], q_ff40c[39:38], q_ff38c[37:36], q_ff36c[35:34], q_ff34c[33:32], q_ff32c[31:30], q_ff30c[29:28], q_ff28c[27:26], q_ff26c[25:24], q_ff24c[23:22], q_ff22c[21:20], q_ff20c[19:18], q_ff18c[17:16], q_ff16c[15:14], q_ff14c[13:12], q_ff12c[11:10], q_ff10c[9:8], q_ff8c[7:6], q_ff6c[5:4], q_ff4c[3:2], q_ff2c[1:0], (~ addnode_w52c[55]), {2{1'b1}}},
qlevel_w5c = {1'b0, 1'b1, q_ff52c[1], q_ff50c[1:0], (~ addnode_w4c[55]), {2{1'b1}}},
qlevel_w6c = {1'b0, 1'b1, q_ff52c[2], q_ff50c[3:2], q_ff48c[1:0], {2{1'b1}}},
qlevel_w7c = {1'b0, 1'b1, q_ff52c[2], q_ff50c[3:2], q_ff48c[1:0], (~ addnode_w6c[55]), {2{1'b1}}},
qlevel_w8c = {1'b0, 1'b1, q_ff52c[3], q_ff50c[5:4], q_ff48c[3:2], q_ff46c[1:0], {2{1'b1}}},
qlevel_w9c = {1'b0, 1'b1, q_ff52c[3], q_ff50c[5:4], q_ff48c[3:2], q_ff46c[1:0], (~ addnode_w8c[55]), {2{1'b1}}},
root_result = {1'b1, q_ff52c[26], q_ff50c[51:50], q_ff48c[49:48], q_ff46c[47:46], q_ff44c[45:44], q_ff42c[43:42], q_ff40c[41:40], q_ff38c[39:38], q_ff36c[37:36], q_ff34c[35:34], q_ff32c[33:32], q_ff30c[31:30], q_ff28c[29:28], q_ff26c[27:26], q_ff24c[25:24], q_ff22c[23:22], q_ff20c[21:20], q_ff18c[19:18], q_ff16c[17:16], q_ff14c[15:14], q_ff12c[13:12], q_ff10c[11:10], q_ff8c[9:8], q_ff6c[7:6], q_ff4c[5:4], q_ff2c[3:2], q_ff0c[1:0]},
slevel_w0c = {1'b0, rad},
slevel_w10c = {rad_ff9c[44:0], {11{1'b0}}},
slevel_w11c = {addnode_w10c[54:11], {12{1'b0}}},
slevel_w12c = {rad_ff11c[42:0], {13{1'b0}}},
slevel_w13c = {addnode_w12c[54:13], {14{1'b0}}},
slevel_w14c = {rad_ff13c[40:0], {15{1'b0}}},
slevel_w15c = {addnode_w14c[54:15], {16{1'b0}}},
slevel_w16c = {rad_ff15c[38:0], {17{1'b0}}},
slevel_w17c = {addnode_w16c[54:17], {18{1'b0}}},
slevel_w18c = {rad_ff17c[36:0], {19{1'b0}}},
slevel_w19c = {addnode_w18c[54:19], {20{1'b0}}},
slevel_w1c = {addnode_w0c[54:1], {2{1'b0}}},
slevel_w20c = {rad_ff19c[34:0], {21{1'b0}}},
slevel_w21c = {addnode_w20c[54:21], {22{1'b0}}},
slevel_w22c = {rad_ff21c[32:0], {23{1'b0}}},
slevel_w23c = {addnode_w22c[54:23], {24{1'b0}}},
slevel_w24c = {rad_ff23c[30:0], {25{1'b0}}},
slevel_w25c = {addnode_w24c[54:25], {26{1'b0}}},
slevel_w26c = {rad_ff25c[28:0], {27{1'b0}}},
slevel_w27c = {addnode_w26c[54:27], {28{1'b0}}},
slevel_w28c = {rad_ff27c[26:0], {2{1'b1}}, {27{1'b0}}},
slevel_w29c = {addnode_w28c[54:28], {3{1'b1}}, {26{1'b0}}},
slevel_w2c = {rad_ff1c[52:0], {3{1'b0}}},
slevel_w30c = {rad_ff29c[27:0], {3{1'b1}}, {25{1'b0}}},
slevel_w31c = {addnode_w30c[54:26], {3{1'b1}}, {24{1'b0}}},
slevel_w32c = {rad_ff31c[29:0], {3{1'b1}}, {23{1'b0}}},
slevel_w33c = {addnode_w32c[54:24], {3{1'b1}}, {22{1'b0}}},
slevel_w34c = {rad_ff33c[31:0], {3{1'b1}}, {21{1'b0}}},
slevel_w35c = {addnode_w34c[54:22], {3{1'b1}}, {20{1'b0}}},
slevel_w36c = {rad_ff35c[33:0], {3{1'b1}}, {19{1'b0}}},
slevel_w37c = {addnode_w36c[54:20], {3{1'b1}}, {18{1'b0}}},
slevel_w38c = {rad_ff37c[35:0], {3{1'b1}}, {17{1'b0}}},
slevel_w39c = {addnode_w38c[54:18], {3{1'b1}}, {16{1'b0}}},
slevel_w3c = {addnode_w2c[54:3], {4{1'b0}}},
slevel_w40c = {rad_ff39c[37:0], {3{1'b1}}, {15{1'b0}}},
slevel_w41c = {addnode_w40c[54:16], {3{1'b1}}, {14{1'b0}}},
slevel_w42c = {rad_ff41c[39:0], {3{1'b1}}, {13{1'b0}}},
slevel_w43c = {addnode_w42c[54:14], {3{1'b1}}, {12{1'b0}}},
slevel_w44c = {rad_ff43c[41:0], {3{1'b1}}, {11{1'b0}}},
slevel_w45c = {addnode_w44c[54:12], {3{1'b1}}, {10{1'b0}}},
slevel_w46c = {rad_ff45c[43:0], {3{1'b1}}, {9{1'b0}}},
slevel_w47c = {addnode_w46c[54:10], {3{1'b1}}, {8{1'b0}}},
slevel_w48c = {rad_ff47c[45:0], {3{1'b1}}, {7{1'b0}}},
slevel_w49c = {addnode_w48c[54:8], {3{1'b1}}, {6{1'b0}}},
slevel_w4c = {rad_ff3c[50:0], {5{1'b0}}},
slevel_w50c = {rad_ff49c[47:0], {3{1'b1}}, {5{1'b0}}},
slevel_w51c = {addnode_w50c[54:6], {3{1'b1}}, {4{1'b0}}},
slevel_w52c = {rad_ff51c[49:0], {3{1'b1}}, {3{1'b0}}},
slevel_w53c = {addnode_w52c[54:4], {3{1'b1}}, {2{1'b0}}},
slevel_w5c = {addnode_w4c[54:5], {6{1'b0}}},
slevel_w6c = {rad_ff5c[48:0], {7{1'b0}}},
slevel_w7c = {addnode_w6c[54:7], {8{1'b0}}},
slevel_w8c = {rad_ff7c[46:0], {9{1'b0}}},
slevel_w9c = {addnode_w8c[54:9], {10{1'b0}}};
endmodule //acl_fp_sqrt_s5_double_alt_sqrt_block_odb
//synthesis_resources = lpm_add_sub 56 reg 2983
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_sqrt_s5_double_altfp_sqrt_n9d
(
clk_en,
clock,
data,
result) ;
input clk_en;
input clock;
input [63:0] data;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [53:0] wire_alt_sqrt_block2_root_result;
reg exp_all_one_ff;
reg [10:0] exp_ff1;
reg [10:0] exp_ff20c;
reg [10:0] exp_ff210c;
reg [10:0] exp_ff211c;
reg [10:0] exp_ff212c;
reg [10:0] exp_ff213c;
reg [10:0] exp_ff214c;
reg [10:0] exp_ff215c;
reg [10:0] exp_ff216c;
reg [10:0] exp_ff217c;
reg [10:0] exp_ff218c;
reg [10:0] exp_ff219c;
reg [10:0] exp_ff21c;
reg [10:0] exp_ff220c;
reg [10:0] exp_ff221c;
reg [10:0] exp_ff222c;
reg [10:0] exp_ff223c;
reg [10:0] exp_ff224c;
reg [10:0] exp_ff225c;
reg [10:0] exp_ff226c;
reg [10:0] exp_ff22c;
reg [10:0] exp_ff23c;
reg [10:0] exp_ff24c;
reg [10:0] exp_ff25c;
reg [10:0] exp_ff26c;
reg [10:0] exp_ff27c;
reg [10:0] exp_ff28c;
reg [10:0] exp_ff29c;
reg [10:0] exp_in_ff;
reg exp_not_zero_ff;
reg [10:0] exp_result_ff;
reg [0:0] infinity_ff0;
reg [0:0] infinity_ff1;
reg [0:0] infinity_ff2;
reg [0:0] infinity_ff3;
reg [0:0] infinity_ff4;
reg [0:0] infinity_ff5;
reg [0:0] infinity_ff6;
reg [0:0] infinity_ff7;
reg [0:0] infinity_ff8;
reg [0:0] infinity_ff9;
reg [0:0] infinity_ff10;
reg [0:0] infinity_ff11;
reg [0:0] infinity_ff12;
reg [0:0] infinity_ff13;
reg [0:0] infinity_ff14;
reg [0:0] infinity_ff15;
reg [0:0] infinity_ff16;
reg [0:0] infinity_ff17;
reg [0:0] infinity_ff18;
reg [0:0] infinity_ff19;
reg [0:0] infinity_ff20;
reg [0:0] infinity_ff21;
reg [0:0] infinity_ff22;
reg [0:0] infinity_ff23;
reg [0:0] infinity_ff24;
reg [0:0] infinity_ff25;
reg [0:0] infinity_ff26;
reg [51:0] man_in_ff;
reg man_not_zero_ff;
reg [51:0] man_result_ff;
reg [51:0] man_rounding_ff;
reg [0:0] nan_man_ff0;
reg [0:0] nan_man_ff1;
reg [0:0] nan_man_ff2;
reg [0:0] nan_man_ff3;
reg [0:0] nan_man_ff4;
reg [0:0] nan_man_ff5;
reg [0:0] nan_man_ff6;
reg [0:0] nan_man_ff7;
reg [0:0] nan_man_ff8;
reg [0:0] nan_man_ff9;
reg [0:0] nan_man_ff10;
reg [0:0] nan_man_ff11;
reg [0:0] nan_man_ff12;
reg [0:0] nan_man_ff13;
reg [0:0] nan_man_ff14;
reg [0:0] nan_man_ff15;
reg [0:0] nan_man_ff16;
reg [0:0] nan_man_ff17;
reg [0:0] nan_man_ff18;
reg [0:0] nan_man_ff19;
reg [0:0] nan_man_ff20;
reg [0:0] nan_man_ff21;
reg [0:0] nan_man_ff22;
reg [0:0] nan_man_ff23;
reg [0:0] nan_man_ff24;
reg [0:0] nan_man_ff25;
reg [0:0] nan_man_ff26;
reg [0:0] sign_node_ff0;
reg [0:0] sign_node_ff1;
reg [0:0] sign_node_ff2;
reg [0:0] sign_node_ff3;
reg [0:0] sign_node_ff4;
reg [0:0] sign_node_ff5;
reg [0:0] sign_node_ff6;
reg [0:0] sign_node_ff7;
reg [0:0] sign_node_ff8;
reg [0:0] sign_node_ff9;
reg [0:0] sign_node_ff10;
reg [0:0] sign_node_ff11;
reg [0:0] sign_node_ff12;
reg [0:0] sign_node_ff13;
reg [0:0] sign_node_ff14;
reg [0:0] sign_node_ff15;
reg [0:0] sign_node_ff16;
reg [0:0] sign_node_ff17;
reg [0:0] sign_node_ff18;
reg [0:0] sign_node_ff19;
reg [0:0] sign_node_ff20;
reg [0:0] sign_node_ff21;
reg [0:0] sign_node_ff22;
reg [0:0] sign_node_ff23;
reg [0:0] sign_node_ff24;
reg [0:0] sign_node_ff25;
reg [0:0] sign_node_ff26;
reg [0:0] sign_node_ff27;
reg [0:0] sign_node_ff28;
reg [0:0] sign_node_ff29;
reg [0:0] zero_exp_ff0;
reg [0:0] zero_exp_ff1;
reg [0:0] zero_exp_ff2;
reg [0:0] zero_exp_ff3;
reg [0:0] zero_exp_ff4;
reg [0:0] zero_exp_ff5;
reg [0:0] zero_exp_ff6;
reg [0:0] zero_exp_ff7;
reg [0:0] zero_exp_ff8;
reg [0:0] zero_exp_ff9;
reg [0:0] zero_exp_ff10;
reg [0:0] zero_exp_ff11;
reg [0:0] zero_exp_ff12;
reg [0:0] zero_exp_ff13;
reg [0:0] zero_exp_ff14;
reg [0:0] zero_exp_ff15;
reg [0:0] zero_exp_ff16;
reg [0:0] zero_exp_ff17;
reg [0:0] zero_exp_ff18;
reg [0:0] zero_exp_ff19;
reg [0:0] zero_exp_ff20;
reg [0:0] zero_exp_ff21;
reg [0:0] zero_exp_ff22;
reg [0:0] zero_exp_ff23;
reg [0:0] zero_exp_ff24;
reg [0:0] zero_exp_ff25;
reg [0:0] zero_exp_ff26;
wire [11:0] wire_add_sub1_result;
wire [51:0] wire_add_sub3_result;
wire aclr;
wire [10:0] bias;
wire [10:0] exp_all_one_w;
wire [10:0] exp_div_w;
wire [10:0] exp_ff2_w;
wire [10:0] exp_not_zero_w;
wire infinitycondition_w;
wire [51:0] man_not_zero_w;
wire [53:0] man_root_result_w;
wire nancondition_w;
wire preadjust_w;
wire [54:0] radicand_w;
wire roundbit_w;
acl_fp_sqrt_s5_double_alt_sqrt_block_odb alt_sqrt_block2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.rad(radicand_w),
.root_result(wire_alt_sqrt_block2_root_result));
// synopsys translate_off
initial
exp_all_one_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_all_one_ff <= 1'b0;
else if (clk_en == 1'b1) exp_all_one_ff <= exp_all_one_w[10];
// synopsys translate_off
initial
exp_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff1 <= 11'b0;
else if (clk_en == 1'b1) exp_ff1 <= exp_div_w;
// synopsys translate_off
initial
exp_ff20c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff20c <= 11'b0;
else if (clk_en == 1'b1) exp_ff20c <= exp_ff1;
// synopsys translate_off
initial
exp_ff210c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff210c <= 11'b0;
else if (clk_en == 1'b1) exp_ff210c <= exp_ff29c;
// synopsys translate_off
initial
exp_ff211c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff211c <= 11'b0;
else if (clk_en == 1'b1) exp_ff211c <= exp_ff210c;
// synopsys translate_off
initial
exp_ff212c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff212c <= 11'b0;
else if (clk_en == 1'b1) exp_ff212c <= exp_ff211c;
// synopsys translate_off
initial
exp_ff213c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff213c <= 11'b0;
else if (clk_en == 1'b1) exp_ff213c <= exp_ff212c;
// synopsys translate_off
initial
exp_ff214c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff214c <= 11'b0;
else if (clk_en == 1'b1) exp_ff214c <= exp_ff213c;
// synopsys translate_off
initial
exp_ff215c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff215c <= 11'b0;
else if (clk_en == 1'b1) exp_ff215c <= exp_ff214c;
// synopsys translate_off
initial
exp_ff216c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff216c <= 11'b0;
else if (clk_en == 1'b1) exp_ff216c <= exp_ff215c;
// synopsys translate_off
initial
exp_ff217c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff217c <= 11'b0;
else if (clk_en == 1'b1) exp_ff217c <= exp_ff216c;
// synopsys translate_off
initial
exp_ff218c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff218c <= 11'b0;
else if (clk_en == 1'b1) exp_ff218c <= exp_ff217c;
// synopsys translate_off
initial
exp_ff219c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff219c <= 11'b0;
else if (clk_en == 1'b1) exp_ff219c <= exp_ff218c;
// synopsys translate_off
initial
exp_ff21c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff21c <= 11'b0;
else if (clk_en == 1'b1) exp_ff21c <= exp_ff20c;
// synopsys translate_off
initial
exp_ff220c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff220c <= 11'b0;
else if (clk_en == 1'b1) exp_ff220c <= exp_ff219c;
// synopsys translate_off
initial
exp_ff221c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff221c <= 11'b0;
else if (clk_en == 1'b1) exp_ff221c <= exp_ff220c;
// synopsys translate_off
initial
exp_ff222c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff222c <= 11'b0;
else if (clk_en == 1'b1) exp_ff222c <= exp_ff221c;
// synopsys translate_off
initial
exp_ff223c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff223c <= 11'b0;
else if (clk_en == 1'b1) exp_ff223c <= exp_ff222c;
// synopsys translate_off
initial
exp_ff224c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff224c <= 11'b0;
else if (clk_en == 1'b1) exp_ff224c <= exp_ff223c;
// synopsys translate_off
initial
exp_ff225c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff225c <= 11'b0;
else if (clk_en == 1'b1) exp_ff225c <= exp_ff224c;
// synopsys translate_off
initial
exp_ff226c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff226c <= 11'b0;
else if (clk_en == 1'b1) exp_ff226c <= exp_ff225c;
// synopsys translate_off
initial
exp_ff22c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff22c <= 11'b0;
else if (clk_en == 1'b1) exp_ff22c <= exp_ff21c;
// synopsys translate_off
initial
exp_ff23c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff23c <= 11'b0;
else if (clk_en == 1'b1) exp_ff23c <= exp_ff22c;
// synopsys translate_off
initial
exp_ff24c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff24c <= 11'b0;
else if (clk_en == 1'b1) exp_ff24c <= exp_ff23c;
// synopsys translate_off
initial
exp_ff25c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff25c <= 11'b0;
else if (clk_en == 1'b1) exp_ff25c <= exp_ff24c;
// synopsys translate_off
initial
exp_ff26c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff26c <= 11'b0;
else if (clk_en == 1'b1) exp_ff26c <= exp_ff25c;
// synopsys translate_off
initial
exp_ff27c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff27c <= 11'b0;
else if (clk_en == 1'b1) exp_ff27c <= exp_ff26c;
// synopsys translate_off
initial
exp_ff28c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff28c <= 11'b0;
else if (clk_en == 1'b1) exp_ff28c <= exp_ff27c;
// synopsys translate_off
initial
exp_ff29c = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_ff29c <= 11'b0;
else if (clk_en == 1'b1) exp_ff29c <= exp_ff28c;
// synopsys translate_off
initial
exp_in_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_in_ff <= 11'b0;
else if (clk_en == 1'b1) exp_in_ff <= data[62:52];
// synopsys translate_off
initial
exp_not_zero_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_not_zero_ff <= 1'b0;
else if (clk_en == 1'b1) exp_not_zero_ff <= exp_not_zero_w[10];
// synopsys translate_off
initial
exp_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_result_ff <= 11'b0;
else if (clk_en == 1'b1) exp_result_ff <= (((exp_ff2_w & {11{zero_exp_ff26[0:0]}}) | {11{nan_man_ff26[0:0]}}) | {11{infinity_ff26[0:0]}});
// synopsys translate_off
initial
infinity_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff0 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff0 <= (infinitycondition_w & (~ sign_node_ff1[0:0]));
// synopsys translate_off
initial
infinity_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff1 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff1 <= infinity_ff0[0:0];
// synopsys translate_off
initial
infinity_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff2 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff2 <= infinity_ff1[0:0];
// synopsys translate_off
initial
infinity_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff3 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff3 <= infinity_ff2[0:0];
// synopsys translate_off
initial
infinity_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff4 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff4 <= infinity_ff3[0:0];
// synopsys translate_off
initial
infinity_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff5 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff5 <= infinity_ff4[0:0];
// synopsys translate_off
initial
infinity_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff6 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff6 <= infinity_ff5[0:0];
// synopsys translate_off
initial
infinity_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff7 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff7 <= infinity_ff6[0:0];
// synopsys translate_off
initial
infinity_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff8 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff8 <= infinity_ff7[0:0];
// synopsys translate_off
initial
infinity_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff9 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff9 <= infinity_ff8[0:0];
// synopsys translate_off
initial
infinity_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff10 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff10 <= infinity_ff9[0:0];
// synopsys translate_off
initial
infinity_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff11 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff11 <= infinity_ff10[0:0];
// synopsys translate_off
initial
infinity_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff12 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff12 <= infinity_ff11[0:0];
// synopsys translate_off
initial
infinity_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff13 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff13 <= infinity_ff12[0:0];
// synopsys translate_off
initial
infinity_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff14 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff14 <= infinity_ff13[0:0];
// synopsys translate_off
initial
infinity_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff15 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff15 <= infinity_ff14[0:0];
// synopsys translate_off
initial
infinity_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff16 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff16 <= infinity_ff15[0:0];
// synopsys translate_off
initial
infinity_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff17 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff17 <= infinity_ff16[0:0];
// synopsys translate_off
initial
infinity_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff18 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff18 <= infinity_ff17[0:0];
// synopsys translate_off
initial
infinity_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff19 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff19 <= infinity_ff18[0:0];
// synopsys translate_off
initial
infinity_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff20 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff20 <= infinity_ff19[0:0];
// synopsys translate_off
initial
infinity_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff21 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff21 <= infinity_ff20[0:0];
// synopsys translate_off
initial
infinity_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff22 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff22 <= infinity_ff21[0:0];
// synopsys translate_off
initial
infinity_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff23 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff23 <= infinity_ff22[0:0];
// synopsys translate_off
initial
infinity_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff24 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff24 <= infinity_ff23[0:0];
// synopsys translate_off
initial
infinity_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff25 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff25 <= infinity_ff24[0:0];
// synopsys translate_off
initial
infinity_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) infinity_ff26 <= 1'b0;
else if (clk_en == 1'b1) infinity_ff26 <= infinity_ff25[0:0];
// synopsys translate_off
initial
man_in_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_in_ff <= 52'b0;
else if (clk_en == 1'b1) man_in_ff <= data[51:0];
// synopsys translate_off
initial
man_not_zero_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_not_zero_ff <= 1'b0;
else if (clk_en == 1'b1) man_not_zero_ff <= man_not_zero_w[51];
// synopsys translate_off
initial
man_result_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_result_ff <= 52'b0;
else if (clk_en == 1'b1) man_result_ff <= ((man_rounding_ff & {52{zero_exp_ff26[0:0]}}) | {52{nan_man_ff26[0:0]}});
// synopsys translate_off
initial
man_rounding_ff = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_rounding_ff <= 52'b0;
else if (clk_en == 1'b1) man_rounding_ff <= wire_add_sub3_result;
// synopsys translate_off
initial
nan_man_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff0 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff0 <= nancondition_w;
// synopsys translate_off
initial
nan_man_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff1 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff1 <= nan_man_ff0[0:0];
// synopsys translate_off
initial
nan_man_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff2 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff2 <= nan_man_ff1[0:0];
// synopsys translate_off
initial
nan_man_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff3 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff3 <= nan_man_ff2[0:0];
// synopsys translate_off
initial
nan_man_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff4 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff4 <= nan_man_ff3[0:0];
// synopsys translate_off
initial
nan_man_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff5 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff5 <= nan_man_ff4[0:0];
// synopsys translate_off
initial
nan_man_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff6 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff6 <= nan_man_ff5[0:0];
// synopsys translate_off
initial
nan_man_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff7 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff7 <= nan_man_ff6[0:0];
// synopsys translate_off
initial
nan_man_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff8 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff8 <= nan_man_ff7[0:0];
// synopsys translate_off
initial
nan_man_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff9 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff9 <= nan_man_ff8[0:0];
// synopsys translate_off
initial
nan_man_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff10 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff10 <= nan_man_ff9[0:0];
// synopsys translate_off
initial
nan_man_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff11 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff11 <= nan_man_ff10[0:0];
// synopsys translate_off
initial
nan_man_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff12 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff12 <= nan_man_ff11[0:0];
// synopsys translate_off
initial
nan_man_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff13 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff13 <= nan_man_ff12[0:0];
// synopsys translate_off
initial
nan_man_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff14 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff14 <= nan_man_ff13[0:0];
// synopsys translate_off
initial
nan_man_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff15 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff15 <= nan_man_ff14[0:0];
// synopsys translate_off
initial
nan_man_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff16 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff16 <= nan_man_ff15[0:0];
// synopsys translate_off
initial
nan_man_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff17 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff17 <= nan_man_ff16[0:0];
// synopsys translate_off
initial
nan_man_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff18 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff18 <= nan_man_ff17[0:0];
// synopsys translate_off
initial
nan_man_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff19 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff19 <= nan_man_ff18[0:0];
// synopsys translate_off
initial
nan_man_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff20 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff20 <= nan_man_ff19[0:0];
// synopsys translate_off
initial
nan_man_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff21 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff21 <= nan_man_ff20[0:0];
// synopsys translate_off
initial
nan_man_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff22 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff22 <= nan_man_ff21[0:0];
// synopsys translate_off
initial
nan_man_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff23 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff23 <= nan_man_ff22[0:0];
// synopsys translate_off
initial
nan_man_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff24 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff24 <= nan_man_ff23[0:0];
// synopsys translate_off
initial
nan_man_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff25 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff25 <= nan_man_ff24[0:0];
// synopsys translate_off
initial
nan_man_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) nan_man_ff26 <= 1'b0;
else if (clk_en == 1'b1) nan_man_ff26 <= nan_man_ff25[0:0];
// synopsys translate_off
initial
sign_node_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff0 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff0 <= data[63];
// synopsys translate_off
initial
sign_node_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff1 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff1 <= sign_node_ff0[0:0];
// synopsys translate_off
initial
sign_node_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff2 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff2 <= sign_node_ff1[0:0];
// synopsys translate_off
initial
sign_node_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff3 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff3 <= sign_node_ff2[0:0];
// synopsys translate_off
initial
sign_node_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff4 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff4 <= sign_node_ff3[0:0];
// synopsys translate_off
initial
sign_node_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff5 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff5 <= sign_node_ff4[0:0];
// synopsys translate_off
initial
sign_node_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff6 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff6 <= sign_node_ff5[0:0];
// synopsys translate_off
initial
sign_node_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff7 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff7 <= sign_node_ff6[0:0];
// synopsys translate_off
initial
sign_node_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff8 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff8 <= sign_node_ff7[0:0];
// synopsys translate_off
initial
sign_node_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff9 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff9 <= sign_node_ff8[0:0];
// synopsys translate_off
initial
sign_node_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff10 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff10 <= sign_node_ff9[0:0];
// synopsys translate_off
initial
sign_node_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff11 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff11 <= sign_node_ff10[0:0];
// synopsys translate_off
initial
sign_node_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff12 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff12 <= sign_node_ff11[0:0];
// synopsys translate_off
initial
sign_node_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff13 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff13 <= sign_node_ff12[0:0];
// synopsys translate_off
initial
sign_node_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff14 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff14 <= sign_node_ff13[0:0];
// synopsys translate_off
initial
sign_node_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff15 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff15 <= sign_node_ff14[0:0];
// synopsys translate_off
initial
sign_node_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff16 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff16 <= sign_node_ff15[0:0];
// synopsys translate_off
initial
sign_node_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff17 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff17 <= sign_node_ff16[0:0];
// synopsys translate_off
initial
sign_node_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff18 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff18 <= sign_node_ff17[0:0];
// synopsys translate_off
initial
sign_node_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff19 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff19 <= sign_node_ff18[0:0];
// synopsys translate_off
initial
sign_node_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff20 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff20 <= sign_node_ff19[0:0];
// synopsys translate_off
initial
sign_node_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff21 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff21 <= sign_node_ff20[0:0];
// synopsys translate_off
initial
sign_node_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff22 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff22 <= sign_node_ff21[0:0];
// synopsys translate_off
initial
sign_node_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff23 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff23 <= sign_node_ff22[0:0];
// synopsys translate_off
initial
sign_node_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff24 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff24 <= sign_node_ff23[0:0];
// synopsys translate_off
initial
sign_node_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff25 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff25 <= sign_node_ff24[0:0];
// synopsys translate_off
initial
sign_node_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff26 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff26 <= sign_node_ff25[0:0];
// synopsys translate_off
initial
sign_node_ff27 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff27 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff27 <= sign_node_ff26[0:0];
// synopsys translate_off
initial
sign_node_ff28 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff28 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff28 <= sign_node_ff27[0:0];
// synopsys translate_off
initial
sign_node_ff29 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_node_ff29 <= 1'b0;
else if (clk_en == 1'b1) sign_node_ff29 <= sign_node_ff28[0:0];
// synopsys translate_off
initial
zero_exp_ff0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff0 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff0 <= exp_not_zero_ff;
// synopsys translate_off
initial
zero_exp_ff1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff1 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff1 <= zero_exp_ff0[0:0];
// synopsys translate_off
initial
zero_exp_ff2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff2 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff2 <= zero_exp_ff1[0:0];
// synopsys translate_off
initial
zero_exp_ff3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff3 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff3 <= zero_exp_ff2[0:0];
// synopsys translate_off
initial
zero_exp_ff4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff4 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff4 <= zero_exp_ff3[0:0];
// synopsys translate_off
initial
zero_exp_ff5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff5 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff5 <= zero_exp_ff4[0:0];
// synopsys translate_off
initial
zero_exp_ff6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff6 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff6 <= zero_exp_ff5[0:0];
// synopsys translate_off
initial
zero_exp_ff7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff7 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff7 <= zero_exp_ff6[0:0];
// synopsys translate_off
initial
zero_exp_ff8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff8 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff8 <= zero_exp_ff7[0:0];
// synopsys translate_off
initial
zero_exp_ff9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff9 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff9 <= zero_exp_ff8[0:0];
// synopsys translate_off
initial
zero_exp_ff10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff10 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff10 <= zero_exp_ff9[0:0];
// synopsys translate_off
initial
zero_exp_ff11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff11 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff11 <= zero_exp_ff10[0:0];
// synopsys translate_off
initial
zero_exp_ff12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff12 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff12 <= zero_exp_ff11[0:0];
// synopsys translate_off
initial
zero_exp_ff13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff13 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff13 <= zero_exp_ff12[0:0];
// synopsys translate_off
initial
zero_exp_ff14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff14 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff14 <= zero_exp_ff13[0:0];
// synopsys translate_off
initial
zero_exp_ff15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff15 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff15 <= zero_exp_ff14[0:0];
// synopsys translate_off
initial
zero_exp_ff16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff16 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff16 <= zero_exp_ff15[0:0];
// synopsys translate_off
initial
zero_exp_ff17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff17 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff17 <= zero_exp_ff16[0:0];
// synopsys translate_off
initial
zero_exp_ff18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff18 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff18 <= zero_exp_ff17[0:0];
// synopsys translate_off
initial
zero_exp_ff19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff19 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff19 <= zero_exp_ff18[0:0];
// synopsys translate_off
initial
zero_exp_ff20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff20 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff20 <= zero_exp_ff19[0:0];
// synopsys translate_off
initial
zero_exp_ff21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff21 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff21 <= zero_exp_ff20[0:0];
// synopsys translate_off
initial
zero_exp_ff22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff22 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff22 <= zero_exp_ff21[0:0];
// synopsys translate_off
initial
zero_exp_ff23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff23 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff23 <= zero_exp_ff22[0:0];
// synopsys translate_off
initial
zero_exp_ff24 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff24 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff24 <= zero_exp_ff23[0:0];
// synopsys translate_off
initial
zero_exp_ff25 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff25 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff25 <= zero_exp_ff24[0:0];
// synopsys translate_off
initial
zero_exp_ff26 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) zero_exp_ff26 <= 1'b0;
else if (clk_en == 1'b1) zero_exp_ff26 <= zero_exp_ff25[0:0];
lpm_add_sub add_sub1
(
.cout(),
.dataa({1'b0, exp_in_ff}),
.datab({1'b0, bias}),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_pipeline = 0,
add_sub1.lpm_width = 12,
add_sub1.lpm_type = "lpm_add_sub";
lpm_add_sub add_sub3
(
.cout(),
.dataa(man_root_result_w[52:1]),
.datab({{51{1'b0}}, roundbit_w}),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "ADD",
add_sub3.lpm_pipeline = 0,
add_sub3.lpm_width = 52,
add_sub3.lpm_type = "lpm_add_sub";
assign
aclr = 1'b0,
bias = {1'b0, {10{1'b1}}},
exp_all_one_w = {(exp_in_ff[10] & exp_all_one_w[9]), (exp_in_ff[9] & exp_all_one_w[8]), (exp_in_ff[8] & exp_all_one_w[7]), (exp_in_ff[7] & exp_all_one_w[6]), (exp_in_ff[6] & exp_all_one_w[5]), (exp_in_ff[5] & exp_all_one_w[4]), (exp_in_ff[4] & exp_all_one_w[3]), (exp_in_ff[3] & exp_all_one_w[2]), (exp_in_ff[2] & exp_all_one_w[1]), (exp_in_ff[1] & exp_all_one_w[0]), exp_in_ff[0]},
exp_div_w = {wire_add_sub1_result[11:1]},
exp_ff2_w = exp_ff226c,
exp_not_zero_w = {(exp_in_ff[10] | exp_not_zero_w[9]), (exp_in_ff[9] | exp_not_zero_w[8]), (exp_in_ff[8] | exp_not_zero_w[7]), (exp_in_ff[7] | exp_not_zero_w[6]), (exp_in_ff[6] | exp_not_zero_w[5]), (exp_in_ff[5] | exp_not_zero_w[4]), (exp_in_ff[4] | exp_not_zero_w[3]), (exp_in_ff[3] | exp_not_zero_w[2]), (exp_in_ff[2] | exp_not_zero_w[1]), (exp_in_ff[1] | exp_not_zero_w[0]), exp_in_ff[0]},
infinitycondition_w = ((~ man_not_zero_ff) & exp_all_one_ff),
man_not_zero_w = {(man_in_ff[51] | man_not_zero_w[50]), (man_in_ff[50] | man_not_zero_w[49]), (man_in_ff[49] | man_not_zero_w[48]), (man_in_ff[48] | man_not_zero_w[47]), (man_in_ff[47] | man_not_zero_w[46]), (man_in_ff[46] | man_not_zero_w[45]), (man_in_ff[45] | man_not_zero_w[44]), (man_in_ff[44] | man_not_zero_w[43]), (man_in_ff[43] | man_not_zero_w[42]), (man_in_ff[42] | man_not_zero_w[41]), (man_in_ff[41] | man_not_zero_w[40]), (man_in_ff[40] | man_not_zero_w[39]), (man_in_ff[39] | man_not_zero_w[38]), (man_in_ff[38] | man_not_zero_w[37]), (man_in_ff[37] | man_not_zero_w[36]), (man_in_ff[36] | man_not_zero_w[35]), (man_in_ff[35] | man_not_zero_w[34]), (man_in_ff[34] | man_not_zero_w[33]), (man_in_ff[33] | man_not_zero_w[32]), (man_in_ff[32] | man_not_zero_w[31]), (man_in_ff[31] | man_not_zero_w[30]), (man_in_ff[30] | man_not_zero_w[29]), (man_in_ff[29] | man_not_zero_w[28]), (man_in_ff[28] | man_not_zero_w[27]), (man_in_ff[27] | man_not_zero_w[26]), (man_in_ff[26] | man_not_zero_w[25]), (man_in_ff[25] | man_not_zero_w[24]), (man_in_ff[24] | man_not_zero_w[23]), (man_in_ff[23] | man_not_zero_w[22]), (man_in_ff[22] | man_not_zero_w[21]), (man_in_ff[21] | man_not_zero_w[20]), (man_in_ff[20] | man_not_zero_w[19]), (man_in_ff[19] | man_not_zero_w[18]), (man_in_ff[18] | man_not_zero_w[17]), (man_in_ff[17] | man_not_zero_w[16]), (man_in_ff[16] | man_not_zero_w[15]), (man_in_ff[15] | man_not_zero_w[14]), (man_in_ff[14] | man_not_zero_w[13]), (man_in_ff[13] | man_not_zero_w[12]), (man_in_ff[12] | man_not_zero_w[11]), (man_in_ff[11] | man_not_zero_w[10]), (man_in_ff[10] | man_not_zero_w[9]), (man_in_ff[9] | man_not_zero_w[8]), (man_in_ff[8] | man_not_zero_w[7]), (man_in_ff[7] | man_not_zero_w[6]), (man_in_ff[6] | man_not_zero_w[5]), (man_in_ff[5] | man_not_zero_w[4]), (man_in_ff[4] | man_not_zero_w[3]), (man_in_ff[3] | man_not_zero_w[2]), (man_in_ff[2] | man_not_zero_w[1]), (man_in_ff[1] | man_not_zero_w[0]), man_in_ff[0]},
man_root_result_w = wire_alt_sqrt_block2_root_result,
nancondition_w = ((sign_node_ff1[0:0] & exp_not_zero_ff) | (exp_all_one_ff & man_not_zero_ff)),
preadjust_w = exp_in_ff[0],
radicand_w = {(~ preadjust_w), (preadjust_w | (man_in_ff[51] & (~ preadjust_w))), ((man_in_ff[51:1] & {51{preadjust_w}}) | (man_in_ff[50:0] & {51{(~ preadjust_w)}})), (man_in_ff[0] & preadjust_w), 1'b0},
result = {sign_node_ff29[0:0], exp_result_ff, man_result_ff},
roundbit_w = wire_alt_sqrt_block2_root_result[0];
endmodule //acl_fp_sqrt_s5_double_altfp_sqrt_n9d
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_sqrt_s5_double (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [63:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_sqrt_s5_double_altfp_sqrt_n9d acl_fp_sqrt_s5_double_altfp_sqrt_n9d_component (
.clk_en (enable),
.clock (clock),
.data (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "30"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_s5_double.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_s5_double.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_s5_double.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_s5_double.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_s5_double_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_sqrt_s5_double_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(**************************************************************)
(* MSetDecide.v *)
(* *)
(* Author: Aaron Bohannon *)
(**************************************************************)
(** This file implements a decision procedure for a certain
class of propositions involving finite sets. *)
Require Import Decidable DecidableTypeEx MSetFacts.
(** First, a version for Weak Sets in functorial presentation *)
Module WDecideOn (E : DecidableType)(Import M : WSetsOn E).
Module F := MSetFacts.WFactsOn E M.
(** * Overview
This functor defines the tactic [fsetdec], which will
solve any valid goal of the form
<<
forall s1 ... sn,
forall x1 ... xm,
P1 -> ... -> Pk -> P
>>
where [P]'s are defined by the grammar:
<<
P ::=
| Q
| Empty F
| Subset F F'
| Equal F F'
Q ::=
| E.eq X X'
| In X F
| Q /\ Q'
| Q \/ Q'
| Q -> Q'
| Q <-> Q'
| ~ Q
| True
| False
F ::=
| S
| empty
| singleton X
| add X F
| remove X F
| union F F'
| inter F F'
| diff F F'
X ::= x1 | ... | xm
S ::= s1 | ... | sn
>>
The tactic will also work on some goals that vary slightly from
the above form:
- The variables and hypotheses may be mixed in any order and may
have already been introduced into the context. Moreover,
there may be additional, unrelated hypotheses mixed in (these
will be ignored).
- A conjunction of hypotheses will be handled as easily as
separate hypotheses, i.e., [P1 /\ P2 -> P] can be solved iff
[P1 -> P2 -> P] can be solved.
- [fsetdec] should solve any goal if the MSet-related hypotheses
are contradictory.
- [fsetdec] will first perform any necessary zeta and beta
reductions and will invoke [subst] to eliminate any Coq
equalities between finite sets or their elements.
- If [E.eq] is convertible with Coq's equality, it will not
matter which one is used in the hypotheses or conclusion.
- The tactic can solve goals where the finite sets or set
elements are expressed by Coq terms that are more complicated
than variables. However, non-local definitions are not
expanded, and Coq equalities between non-variable terms are
not used. For example, this goal will be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2)
>>
This one will not be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2)
>>
*)
(** * Facts and Tactics for Propositional Logic
These lemmas and tactics are in a module so that they do
not affect the namespace if you import the enclosing
module [Decide]. *)
Module MSetLogicalFacts.
Require Export Decidable.
Require Export Setoid.
(** ** Lemmas and Tactics About Decidable Propositions *)
(** ** Propositional Equivalences Involving Negation
These are all written with the unfolded form of
negation, since I am not sure if setoid rewriting will
always perform conversion. *)
(** ** Tactics for Negations *)
Tactic Notation "fold" "any" "not" :=
repeat (
match goal with
| H: context [?P -> False] |- _ =>
fold (~ P) in H
| |- context [?P -> False] =>
fold (~ P)
end).
(** [push not using db] will pushes all negations to the
leaves of propositions in the goal, using the lemmas in
[db] to assist in checking the decidability of the
propositions involved. If [using db] is omitted, then
[core] will be used. Additional versions are provided
to manipulate the hypotheses or the hypotheses and goal
together.
XXX: This tactic and the similar subsequent ones should
have been defined using [autorewrite]. However, dealing
with multiples rewrite sites and side-conditions is
done more cleverly with the following explicit
analysis of goals. *)
Ltac or_not_l_iff P Q tac :=
(rewrite (or_not_l_iff_1 P Q) by tac) ||
(rewrite (or_not_l_iff_2 P Q) by tac).
Ltac or_not_r_iff P Q tac :=
(rewrite (or_not_r_iff_1 P Q) by tac) ||
(rewrite (or_not_r_iff_2 P Q) by tac).
Ltac or_not_l_iff_in P Q H tac :=
(rewrite (or_not_l_iff_1 P Q) in H by tac) ||
(rewrite (or_not_l_iff_2 P Q) in H by tac).
Ltac or_not_r_iff_in P Q H tac :=
(rewrite (or_not_r_iff_1 P Q) in H by tac) ||
(rewrite (or_not_r_iff_2 P Q) in H by tac).
Tactic Notation "push" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [?P \/ ?Q -> False] => rewrite (not_or_iff P Q)
| |- context [?P /\ ?Q -> False] => rewrite (not_and_iff P Q)
| |- context [(?P -> ?Q) -> False] => rewrite (not_imp_iff P Q) by dec
end);
fold any not.
Tactic Notation "push" "not" :=
push not using core.
Tactic Notation
"push" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [?P \/ ?Q -> False] |- _ => rewrite (not_or_iff P Q) in H
| H: context [?P /\ ?Q -> False] |- _ => rewrite (not_and_iff P Q) in H
| H: context [(?P -> ?Q) -> False] |- _ =>
rewrite (not_imp_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "push" "not" "in" "*" "|-" :=
push not in * |- using core.
Tactic Notation "push" "not" "in" "*" "using" ident(db) :=
push not using db; push not in * |- using db.
Tactic Notation "push" "not" "in" "*" :=
push not in * using core.
(** A simple test case to see how this works. *)
Lemma test_push : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ ((R -> P) \/ (Q -> R))) ->
(~ (P /\ R)) ->
(~ (P -> R)) ->
True.
Proof.
intros. push not in *.
(* note that ~(R->P) remains (since R isnt decidable) *)
tauto.
Qed.
(** [pull not using db] will pull as many negations as
possible toward the top of the propositions in the goal,
using the lemmas in [db] to assist in checking the
decidability of the propositions involved. If [using
db] is omitted, then [core] will be used. Additional
versions are provided to manipulate the hypotheses or
the hypotheses and goal together. *)
Tactic Notation "pull" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [(?P -> False) /\ (?Q -> False)] =>
rewrite <- (not_or_iff P Q)
| |- context [?P -> ?Q -> False] => rewrite <- (not_and_iff P Q)
| |- context [?P /\ (?Q -> False)] => rewrite <- (not_imp_iff P Q) by dec
| |- context [(?Q -> False) /\ ?P] =>
rewrite <- (not_imp_rev_iff P Q) by dec
end);
fold any not.
Tactic Notation "pull" "not" :=
pull not using core.
Tactic Notation
"pull" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [(?P -> False) /\ (?Q -> False)] |- _ =>
rewrite <- (not_or_iff P Q) in H
| H: context [?P -> ?Q -> False] |- _ =>
rewrite <- (not_and_iff P Q) in H
| H: context [?P /\ (?Q -> False)] |- _ =>
rewrite <- (not_imp_iff P Q) in H by dec
| H: context [(?Q -> False) /\ ?P] |- _ =>
rewrite <- (not_imp_rev_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "pull" "not" "in" "*" "|-" :=
pull not in * |- using core.
Tactic Notation "pull" "not" "in" "*" "using" ident(db) :=
pull not using db; pull not in * |- using db.
Tactic Notation "pull" "not" "in" "*" :=
pull not in * using core.
(** A simple test case to see how this works. *)
Lemma test_pull : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ (R -> P) /\ ~ (Q -> R)) ->
(~ P \/ ~ R) ->
(P /\ ~ R) ->
(~ R /\ P) ->
True.
Proof.
intros. pull not in *. tauto.
Qed.
End MSetLogicalFacts.
Import MSetLogicalFacts.
(** * Auxiliary Tactics
Again, these lemmas and tactics are in a module so that
they do not affect the namespace if you import the
enclosing module [Decide]. *)
Module MSetDecideAuxiliary.
(** ** Generic Tactics
We begin by defining a few generic, useful tactics. *)
(** remove logical hypothesis inter-dependencies (fix #2136). *)
Ltac no_logical_interdep :=
match goal with
| H : ?P |- _ =>
match type of P with
| Prop =>
match goal with H' : context [ H ] |- _ => clear dependent H' end
| _ => fail
end; no_logical_interdep
| _ => idtac
end.
(** [if t then t1 else t2] executes [t] and, if it does not
fail, then [t1] will be applied to all subgoals
produced. If [t] fails, then [t2] is executed. *)
Tactic Notation
"if" tactic(t)
"then" tactic(t1)
"else" tactic(t2) :=
first [ t; first [ t1 | fail 2 ] | t2 ].
Ltac abstract_term t :=
if (is_var t) then fail "no need to abstract a variable"
else (let x := fresh "x" in set (x := t) in *; try clearbody x).
Ltac abstract_elements :=
repeat
(match goal with
| |- context [ singleton ?t ] => abstract_term t
| _ : context [ singleton ?t ] |- _ => abstract_term t
| |- context [ add ?t _ ] => abstract_term t
| _ : context [ add ?t _ ] |- _ => abstract_term t
| |- context [ remove ?t _ ] => abstract_term t
| _ : context [ remove ?t _ ] |- _ => abstract_term t
| |- context [ In ?t _ ] => abstract_term t
| _ : context [ In ?t _ ] |- _ => abstract_term t
end).
(** [prop P holds by t] succeeds (but does not modify the
goal or context) if the proposition [P] can be proved by
[t] in the current context. Otherwise, the tactic
fails. *)
Tactic Notation "prop" constr(P) "holds" "by" tactic(t) :=
let H := fresh in
assert P as H by t;
clear H.
(** This tactic acts just like [assert ... by ...] but will
fail if the context already contains the proposition. *)
Tactic Notation "assert" "new" constr(e) "by" tactic(t) :=
match goal with
| H: e |- _ => fail 1
| _ => assert e by t
end.
(** [subst++] is similar to [subst] except that
- it never fails (as [subst] does on recursive
equations),
- it substitutes locally defined variable for their
definitions,
- it performs beta reductions everywhere, which may
arise after substituting a locally defined function
for its definition.
*)
Tactic Notation "subst" "++" :=
repeat (
match goal with
| x : _ |- _ => subst x
end);
cbv zeta beta in *.
(** [decompose records] calls [decompose record H] on every
relevant hypothesis [H]. *)
Tactic Notation "decompose" "records" :=
repeat (
match goal with
| H: _ |- _ => progress (decompose record H); clear H
end).
(** ** Discarding Irrelevant Hypotheses
We will want to clear the context of any
non-MSet-related hypotheses in order to increase the
speed of the tactic. To do this, we will need to be
able to decide which are relevant. We do this by making
a simple inductive definition classifying the
propositions of interest. *)
Inductive MSet_elt_Prop : Prop -> Prop :=
| eq_Prop : forall (S : Type) (x y : S),
MSet_elt_Prop (x = y)
| eq_elt_prop : forall x y,
MSet_elt_Prop (E.eq x y)
| In_elt_prop : forall x s,
MSet_elt_Prop (In x s)
| True_elt_prop :
MSet_elt_Prop True
| False_elt_prop :
MSet_elt_Prop False
| conj_elt_prop : forall P Q,
MSet_elt_Prop P ->
MSet_elt_Prop Q ->
MSet_elt_Prop (P /\ Q)
| disj_elt_prop : forall P Q,
MSet_elt_Prop P ->
MSet_elt_Prop Q ->
MSet_elt_Prop (P \/ Q)
| impl_elt_prop : forall P Q,
MSet_elt_Prop P ->
MSet_elt_Prop Q ->
MSet_elt_Prop (P -> Q)
| not_elt_prop : forall P,
MSet_elt_Prop P ->
MSet_elt_Prop (~ P).
Inductive MSet_Prop : Prop -> Prop :=
| elt_MSet_Prop : forall P,
MSet_elt_Prop P ->
MSet_Prop P
| Empty_MSet_Prop : forall s,
MSet_Prop (Empty s)
| Subset_MSet_Prop : forall s1 s2,
MSet_Prop (Subset s1 s2)
| Equal_MSet_Prop : forall s1 s2,
MSet_Prop (Equal s1 s2).
(** Here is the tactic that will throw away hypotheses that
are not useful (for the intended scope of the [fsetdec]
tactic). *)
Hint Constructors MSet_elt_Prop MSet_Prop : MSet_Prop.
Ltac discard_nonMSet :=
repeat (
match goal with
| H : context [ @Logic.eq ?T ?x ?y ] |- _ =>
if (change T with E.t in H) then fail
else if (change T with t in H) then fail
else clear H
| H : ?P |- _ =>
if prop (MSet_Prop P) holds by
(auto 100 with MSet_Prop)
then fail
else clear H
end).
(** ** Turning Set Operators into Propositional Connectives
The lemmas from [MSetFacts] will be used to break down
set operations into propositional formulas built over
the predicates [In] and [E.eq] applied only to
variables. We are going to use them with [autorewrite].
*)
Hint Rewrite
F.empty_iff F.singleton_iff F.add_iff F.remove_iff
F.union_iff F.inter_iff F.diff_iff
: set_simpl.
Lemma eq_refl_iff (x : E.t) : E.eq x x <-> True.
Proof.
now split.
Qed.
Hint Rewrite eq_refl_iff : set_eq_simpl.
(** ** Decidability of MSet Propositions *)
(** [In] is decidable. *)
Lemma dec_In : forall x s,
decidable (In x s).
Proof.
red; intros; generalize (F.mem_iff s x); case (mem x s); intuition.
Qed.
(** [E.eq] is decidable. *)
Lemma dec_eq : forall (x y : E.t),
decidable (E.eq x y).
Proof.
red; intros x y; destruct (E.eq_dec x y); auto.
Qed.
(** The hint database [MSet_decidability] will be given to
the [push_neg] tactic from the module [Negation]. *)
Hint Resolve dec_In dec_eq : MSet_decidability.
(** ** Normalizing Propositions About Equality
We have to deal with the fact that [E.eq] may be
convertible with Coq's equality. Thus, we will find the
following tactics useful to replace one form with the
other everywhere. *)
(** The next tactic, [Logic_eq_to_E_eq], mentions the term
[E.t]; thus, we must ensure that [E.t] is used in favor
of any other convertible but syntactically distinct
term. *)
Ltac change_to_E_t :=
repeat (
match goal with
| H : ?T |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
| H : forall x : ?T, _ |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
end).
(** These two tactics take us from Coq's built-in equality
to [E.eq] (and vice versa) when possible. *)
Ltac Logic_eq_to_E_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change (@Logic.eq E.t) with E.eq in H)
| |- _ =>
progress (change (@Logic.eq E.t) with E.eq)
end).
Ltac E_eq_to_Logic_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change E.eq with (@Logic.eq E.t) in H)
| |- _ =>
progress (change E.eq with (@Logic.eq E.t))
end).
(** This tactic works like the built-in tactic [subst], but
at the level of set element equality (which may not be
the convertible with Coq's equality). *)
Ltac substMSet :=
repeat (
match goal with
| H: E.eq ?x ?x |- _ => clear H
| H: E.eq ?x ?y |- _ => rewrite H in *; clear H
end);
autorewrite with set_eq_simpl in *.
(** ** Considering Decidability of Base Propositions
This tactic adds assertions about the decidability of
[E.eq] and [In] to the context. This is necessary for
the completeness of the [fsetdec] tactic. However, in
order to minimize the cost of proof search, we should be
careful to not add more than we need. Once negations
have been pushed to the leaves of the propositions, we
only need to worry about decidability for those base
propositions that appear in a negated form. *)
Ltac assert_decidability :=
(** We actually don't want these rules to fire if the
syntactic context in the patterns below is trivially
empty, but we'll just do some clean-up at the
afterward. *)
repeat (
match goal with
| H: context [~ E.eq ?x ?y] |- _ =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| H: context [~ In ?x ?s] |- _ =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
| |- context [~ E.eq ?x ?y] =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| |- context [~ In ?x ?s] =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
end);
(** Now we eliminate the useless facts we added (because
they would likely be very harmful to performance). *)
repeat (
match goal with
| _: ~ ?P, H : ?P \/ ~ ?P |- _ => clear H
end).
(** ** Handling [Empty], [Subset], and [Equal]
This tactic instantiates universally quantified
hypotheses (which arise from the unfolding of [Empty],
[Subset], and [Equal]) for each of the set element
expressions that is involved in some membership or
equality fact. Then it throws away those hypotheses,
which should no longer be needed. *)
Ltac inst_MSet_hypotheses :=
repeat (
match goal with
| H : forall a : E.t, _,
_ : context [ In ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ In ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq _ ?x ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq _ ?x ] =>
let P := type of (H x) in
assert new P by (exact (H x))
end);
repeat (
match goal with
| H : forall a : E.t, _ |- _ =>
clear H
end).
(** ** The Core [fsetdec] Auxiliary Tactics *)
(** Here is the crux of the proof search. Recursion through
[intuition]! (This will terminate if I correctly
understand the behavior of [intuition].) *)
Ltac fsetdec_rec := progress substMSet; intuition fsetdec_rec.
(** If we add [unfold Empty, Subset, Equal in *; intros;] to
the beginning of this tactic, it will satisfy the same
specification as the [fsetdec] tactic; however, it will
be much slower than necessary without the pre-processing
done by the wrapper tactic [fsetdec]. *)
Ltac fsetdec_body :=
autorewrite with set_eq_simpl in *;
inst_MSet_hypotheses;
autorewrite with set_simpl set_eq_simpl in *;
push not in * using MSet_decidability;
substMSet;
assert_decidability;
auto;
(intuition fsetdec_rec) ||
fail 1
"because the goal is beyond the scope of this tactic".
End MSetDecideAuxiliary.
Import MSetDecideAuxiliary.
(** * The [fsetdec] Tactic
Here is the top-level tactic (the only one intended for
clients of this library). It's specification is given at
the top of the file. *)
Ltac fsetdec :=
(** We first unfold any occurrences of [iff]. *)
unfold iff in *;
(** We fold occurrences of [not] because it is better for
[intros] to leave us with a goal of [~ P] than a goal of
[False]. *)
fold any not; intros;
(** We don't care about the value of elements : complex ones are
abstracted as new variables (avoiding potential dependencies,
see bug #2464) *)
abstract_elements;
(** We remove dependencies to logical hypothesis. This way,
later "clear" will work nicely (see bug #2136) *)
no_logical_interdep;
(** Now we decompose conjunctions, which will allow the
[discard_nonMSet] and [assert_decidability] tactics to
do a much better job. *)
decompose records;
discard_nonMSet;
(** We unfold these defined propositions on finite sets. If
our goal was one of them, then have one more item to
introduce now. *)
unfold Empty, Subset, Equal in *; intros;
(** We now want to get rid of all uses of [=] in favor of
[E.eq]. However, the best way to eliminate a [=] is in
the context is with [subst], so we will try that first.
In fact, we may as well convert uses of [E.eq] into [=]
when possible before we do [subst] so that we can even
more mileage out of it. Then we will convert all
remaining uses of [=] back to [E.eq] when possible. We
use [change_to_E_t] to ensure that we have a canonical
name for set elements, so that [Logic_eq_to_E_eq] will
work properly. *)
change_to_E_t; E_eq_to_Logic_eq; subst++; Logic_eq_to_E_eq;
(** The next optimization is to swap a negated goal with a
negated hypothesis when possible. Any swap will improve
performance by eliminating the total number of
negations, but we will get the maximum benefit if we
swap the goal with a hypotheses mentioning the same set
element, so we try that first. If we reach the fourth
branch below, we attempt any swap. However, to maintain
completeness of this tactic, we can only perform such a
swap with a decidable proposition; hence, we first test
whether the hypothesis is an [MSet_elt_Prop], noting
that any [MSet_elt_Prop] is decidable. *)
pull not using MSet_decidability;
unfold not in *;
match goal with
| H: (In ?x ?r) -> False |- (In ?x ?s) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?x ?y) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?y ?x) -> False =>
contradict H; fsetdec_body
| H: ?P -> False |- ?Q -> False =>
if prop (MSet_elt_Prop P) holds by
(auto 100 with MSet_Prop)
then (contradict H; fsetdec_body)
else fsetdec_body
| |- _ =>
fsetdec_body
end.
(** * Examples *)
Module MSetDecideTestCases.
Lemma test_eq_trans_1 : forall x y z s,
E.eq x y ->
~ ~ E.eq z y ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_trans_2 : forall x y z r s,
In x (singleton y) ->
~ In z r ->
~ ~ In z (add y r) ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_1 : forall w x y z s,
E.eq x w ->
~ ~ E.eq x y ->
~ E.eq y z ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_2 : forall w x y z r1 r2 s,
In x (singleton w) ->
~ In x r1 ->
In x (add y r1) ->
In y r2 ->
In y (remove z r2) ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_In_singleton : forall x,
In x (singleton x).
Proof. fsetdec. Qed.
Lemma test_add_In : forall x y s,
In x (add y s) ->
~ E.eq x y ->
In x s.
Proof. fsetdec. Qed.
Lemma test_Subset_add_remove : forall x s,
s [<=] (add x (remove x s)).
Proof. fsetdec. Qed.
Lemma test_eq_disjunction : forall w x y z,
In w (add x (add y (singleton z))) ->
E.eq w x \/ E.eq w y \/ E.eq w z.
Proof. fsetdec. Qed.
Lemma test_not_In_disj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ (In x s1 \/ In x s4 \/ E.eq y x).
Proof. fsetdec. Qed.
Lemma test_not_In_conj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ In x s1 /\ ~ In x s4 /\ ~ E.eq y x.
Proof. fsetdec. Qed.
Lemma test_iff_conj : forall a x s s',
(In a s' <-> E.eq x a \/ In a s) ->
(In a s' <-> In a (add x s)).
Proof. fsetdec. Qed.
Lemma test_set_ops_1 : forall x q r s,
(singleton x) [<=] s ->
Empty (union q r) ->
Empty (inter (diff s q) (diff s r)) ->
~ In x s.
Proof. fsetdec. Qed.
Lemma eq_chain_test : forall x1 x2 x3 x4 s1 s2 s3 s4,
Empty s1 ->
In x2 (add x1 s1) ->
In x3 s2 ->
~ In x3 (remove x2 s2) ->
~ In x4 s3 ->
In x4 (add x3 s3) ->
In x1 s4 ->
Subset (add x4 s4) s4.
Proof. fsetdec. Qed.
Lemma test_too_complex : forall x y z r s,
E.eq x y ->
(In x (singleton y) -> r [<=] s) ->
In z r ->
In z s.
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until s; intros Heq H Hr; lapply H; fsetdec.
Qed.
Lemma function_test_1 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2).
Proof. fsetdec. Qed.
Lemma function_test_2 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2).
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until 3. intros g_eq. rewrite <- g_eq. fsetdec.
Qed.
Lemma test_baydemir :
forall (f : t -> t),
forall (s : t),
forall (x y : elt),
In x (add y (f s)) ->
~ E.eq x y ->
In x (f s).
Proof.
fsetdec.
Qed.
End MSetDecideTestCases.
End WDecideOn.
Require Import MSetInterface.
(** Now comes variants for self-contained weak sets and for full sets.
For these variants, only one argument is necessary. Thanks to
the subtyping [WS<=S], the [Decide] functor which is meant to be
used on modules [(M:S)] can simply be an alias of [WDecide]. *)
Module WDecide (M:WSets) := !WDecideOn M.E M.
Module Decide := WDecide.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_PP_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ls__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__sedfxtp (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ls__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXTP_BEHAVIORAL_PP_V |
`include "orpsoc-defines.v"
// One master, 2 slaves.
module arbiter_ibus
(
// instruction bus in
// Wishbone Master interface
wbm_adr_o,
wbm_dat_o,
wbm_sel_o,
wbm_we_o,
wbm_cyc_o,
wbm_stb_o,
wbm_cti_o,
wbm_bte_o,
wbm_dat_i,
wbm_ack_i,
wbm_err_i,
wbm_rty_i,
// Slave one
// Wishbone Slave interface
wbs0_adr_i,
wbs0_dat_i,
wbs0_sel_i,
wbs0_we_i,
wbs0_cyc_i,
wbs0_stb_i,
wbs0_cti_i,
wbs0_bte_i,
wbs0_dat_o,
wbs0_ack_o,
wbs0_err_o,
wbs0_rty_o,
// Slave two
// Wishbone Slave interface
wbs1_adr_i,
wbs1_dat_i,
wbs1_sel_i,
wbs1_we_i,
wbs1_cyc_i,
wbs1_stb_i,
wbs1_cti_i,
wbs1_bte_i,
wbs1_dat_o,
wbs1_ack_o,
wbs1_err_o,
wbs1_rty_o,
wb_clk,
wb_rst
);
parameter wb_dat_width = 32;
parameter wb_adr_width = 32;
parameter slave0_addr_width = 12;
parameter slave1_addr_width = 28;
input wb_clk;
input wb_rst;
// WB Master
input [wb_adr_width-1:0] wbm_adr_o;
input [wb_dat_width-1:0] wbm_dat_o;
input [3:0] wbm_sel_o;
input wbm_we_o;
input wbm_cyc_o;
input wbm_stb_o;
input [2:0] wbm_cti_o;
input [1:0] wbm_bte_o;
output [wb_dat_width-1:0] wbm_dat_i;
output wbm_ack_i;
output wbm_err_i;
output wbm_rty_i;
// WB Slave 0
output [wb_adr_width-1:0] wbs0_adr_i;
output [wb_dat_width-1:0] wbs0_dat_i;
output [3:0] wbs0_sel_i;
output wbs0_we_i;
output wbs0_cyc_i;
output wbs0_stb_i;
output [2:0] wbs0_cti_i;
output [1:0] wbs0_bte_i;
input [wb_dat_width-1:0] wbs0_dat_o;
input wbs0_ack_o;
input wbs0_err_o;
input wbs0_rty_o;
// WB Slave 1
output [wb_adr_width-1:0] wbs1_adr_i;
output [wb_dat_width-1:0] wbs1_dat_i;
output [3:0] wbs1_sel_i;
output wbs1_we_i;
output wbs1_cyc_i;
output wbs1_stb_i;
output [2:0] wbs1_cti_i;
output [1:0] wbs1_bte_i;
input [wb_dat_width-1:0] wbs1_dat_o;
input wbs1_ack_o;
input wbs1_err_o;
input wbs1_rty_o;
wire [1:0] slave_sel; // One bit per slave
reg watchdog_err;
`ifdef ARBITER_IBUS_WATCHDOG
reg [`ARBITER_IBUS_WATCHDOG_TIMER_WIDTH:0] watchdog_timer;
reg wbm_stb_r; // Register strobe
wire wbm_stb_edge; // Detect its edge
reg wbm_stb_edge_r, wbm_ack_i_r; // Reg these, better timing
always @(posedge wb_clk)
wbm_stb_r <= wbm_stb_o;
assign wbm_stb_edge = (wbm_stb_o & !wbm_stb_r);
always @(posedge wb_clk)
wbm_stb_edge_r <= wbm_stb_edge;
always @(posedge wb_clk)
wbm_ack_i_r <= wbm_ack_i;
// Counter logic
always @(posedge wb_clk)
if (wb_rst) watchdog_timer <= 0;
else if (wbm_ack_i_r) // When we see an ack, turn off timer
watchdog_timer <= 0;
else if (wbm_stb_edge_r) // New access means start timer again
watchdog_timer <= 1;
else if (|watchdog_timer) // Continue counting if counter > 0
watchdog_timer <= watchdog_timer + 1;
always @(posedge wb_clk)
watchdog_err <= (&watchdog_timer);
`else // !`ifdef ARBITER_IBUS_WATCHDOG
always @(posedge wb_clk)
watchdog_err <= 0;
`endif // !`ifdef ARBITER_IBUS_WATCHDOG
// Slave select
// ROM/RAM
assign slave_sel[0] = ~|wbm_adr_o[wb_adr_width - 1:slave0_addr_width];
// DDR
assign slave_sel[1] = ~slave_sel[0] & ~|wbm_adr_o[wb_adr_width - 1:slave1_addr_width];
// Slave out assigns
assign wbs0_adr_i = wbm_adr_o;
assign wbs0_dat_i = wbm_dat_o;
assign wbs0_we_i = wbm_we_o;
assign wbs0_sel_i = wbm_sel_o;
assign wbs0_cti_i = wbm_cti_o;
assign wbs0_bte_i = wbm_bte_o;
assign wbs0_cyc_i = wbm_cyc_o & slave_sel[0];
assign wbs0_stb_i = wbm_stb_o & slave_sel[0];
assign wbs1_adr_i = wbm_adr_o;
assign wbs1_dat_i = wbm_dat_o;
assign wbs1_we_i = wbm_we_o;
assign wbs1_sel_i = wbm_sel_o;
assign wbs1_cti_i = wbm_cti_o;
assign wbs1_bte_i = wbm_bte_o;
assign wbs1_cyc_i = wbm_cyc_o & slave_sel[1];
assign wbs1_stb_i = wbm_stb_o & slave_sel[1];
// Master out assigns
// Don't care about none selected...
assign wbm_dat_i = slave_sel[1] ? wbs1_dat_o :
wbs0_dat_o ;
assign wbm_ack_i = (slave_sel[0] & wbs0_ack_o) |
(slave_sel[1] & wbs1_ack_o);
assign wbm_err_i = (slave_sel[0] & wbs0_err_o) |
(slave_sel[1] & wbs1_err_o) |
watchdog_err;
assign wbm_rty_i = (slave_sel[0] & wbs0_rty_o) |
(slave_sel[1] & wbs1_rty_o);
endmodule // arbiter_ibus
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ad
//
// Generated
// by: wig
// on: Mon Oct 24 15:17:36 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ad.v,v 1.2 2005/10/24 15:50:24 wig Exp $
// $Date: 2005/10/24 15:50:24 $
// $Log: ent_ad.v,v $
// Revision 1.2 2005/10/24 15:50:24 wig
// added 'reg detection to ::out column
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.64 2005/10/20 17:28:26 lutscher Exp
//
// Generator: mix_0.pl Revision: 1.38 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ad
//
// No `defines in this module
module ent_ad
//
// Generated module inst_ad
//
(
port_ad_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ad_2;
// Generated Wires:
reg port_ad_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ad
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the on board periphal devices *
* on the DE2-70 board. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_de2_70 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [26: 0] audio_rom_data;
wire [26: 0] video_rom_data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = audio_rom_data | video_rom_data;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_av_config_auto_init_ob_audio Auto_Init_Audio_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (audio_rom_data)
);
defparam
Auto_Init_Audio_ROM.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Init_Audio_ROM.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Init_Audio_ROM.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Init_Audio_ROM.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Init_Audio_ROM.AUD_POWER = AUD_POWER,
Auto_Init_Audio_ROM.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Init_Audio_ROM.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Init_Audio_ROM.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
altera_up_av_config_auto_init_ob_adv7180 Auto_Init_Video_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (video_rom_data)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__OR4B_FUNCTIONAL_PP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4B_FUNCTIONAL_PP_V |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 6;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
// DESCRIPTION:tor:ilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [31:0] o;
wire [31:0] oe;
Test test (/*AUTOINST*/
// Outputs
.o (o[31:0]),
.oe (oe[31:0]));
// Test loop
always @ (posedge clk) begin
if (o !== 32'h00000001) $stop;
if (oe !== 32'h00000001) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module subimp(o,oe);
output [31:0] o;
assign o = 32'h12345679;
output [31:0] oe;
assign oe = 32'hab345679;
endmodule
module Test(o,oe);
output [31:0] o;
output [31:0] oe;
wire [31:0] xe;
assign xe[31:1] = 0;
// verilator lint_off IMPLICIT
// verilator lint_off WIDTH
subimp subimp(x, // x is implicit and one bit
xe[0]); // xe explicit one bit
assign o = x;
assign oe = xe;
// verilator lint_on WIDTH
// verilator lint_on IMPLICIT
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: IIT Kharagpur
// Engineer: Krishna Bagadia
//
// Create Date: 14:08:09 08/14/2016
// Design Name: LCMQ
// Module Name: tag
// Project Name: LCMQ
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module XOR(O,A,B);
input wire A,B;
output wire O;
assign O = (~A)*B + A*(~B);
endmodule
module AND(O,A,B);
input wire A,B;
output wire O;
assign O = A*B;
endmodule
module XOR_SINGLE_ARRAY(O,A);
parameter m=163;
input wire[0:m-1] A;
output wire O;
assign O = ^A;
endmodule
module AND_ARRAY(O,A,B);
parameter m=163;//default
input wire[0:m-1] A,B;
output wire[0:m-1] O;
AND a[0:m-1] (O,A,B);
endmodule
module XOR_ARRAY(O, A, B);
parameter m=163; //default
input wire[0:m-1] A, B;
output wire[0:m-1] O;
XOR x[0:m-1] (O,A,B);
endmodule
module INNER_PRODUCT(O,A,B);
parameter m=163;
input wire[0:m-1] A,B;
output wire O;
wire[0:m-1] temp;
AND_ARRAY a(temp,A,B);
XOR_SINGLE_ARRAY x(O,temp);
endmodule
module MUX(O,A,B,sel);
input wire A,B;
output wire O;
input wire sel;
assign O = (~sel)*A + (sel&B);
endmodule
module D_FLIP_FLOP(Q,A,clk,reset);
parameter m=163;
input wire[0:m-1] A;
output wire[0:m-1] Q;
reg[0:m-1] Q1;
input wire clk,reset;
assign Q=Q1;
initial
begin
Q1=163'd0;
end
always@(posedge clk or negedge reset)
if(~reset)begin
Q1<=163'd0;
end
else begin
Q1 <= A;
end
endmodule
module MUX_ARRAY(O,B_R,A,B,sel,clk);
parameter m=163;
input wire[0:m-1] A,B;
output wire[0:m-1] O,B_R;
input wire sel,clk;
wire[0:m-1] temp;
MUX mu[0:m-1](O,A,B,sel);
assign B_R = O;
//D_FLIP_FLOP d(O,temp,clk,1); // why do u need this ???
//D_FLIP_FLOP dd(B_R,B,clk,1);
endmodule
module TRI_BUF(O,A,E);
input wire A,E;
output wire O;
assign O = (E)?A:1'bz;
endmodule
//module DEMUX(O,A,sel);
// parameter m=163;
// parameter log_m = 7;
// input wire A;
// input wire[0:log_m] sel;
// output wire[0:m-1] O;
// integer i;
// always@(sel)
// i = sel;
// assign O[i-:1] = A;
//endmodule
module RIGHT_SHIFT(O,A, clk);
parameter m=163;
input wire[0:m-1] A;
input wire clk;
output wire[0:m-1] O;
wire[0:m-1] temp;
assign temp={A[m-1],A[0:m-2]};
D_FLIP_FLOP #m d(O,temp,clk,1'b1);
endmodule
module test_bench_right_shift();
parameter m=163;
wire[0:m-1] A,O;
wire clk;
RIGHT_SHIFT rs(O,A,clk);
reg[0:m-1] A1;
reg clk1;
assign clk=clk1;
assign A=A1;
initial begin
clk1=0;
A1=163'd1;
end
always #100 clk1=~clk1;
always #100 $display("A=%b O=%b ",A,O);
endmodule
module MULTIPLY_B_CK(O,B,C_k,clk1);
parameter m=163; // mxn 1xm
parameter n=162; //size of the output
parameter START_STATE=2'b00;
parameter INTER_STATE=2'b01;
parameter FINAL_STATE=2'b10;
reg[0:1] current_state, next_state;
input wire[0:m-1] B;
input wire[0:m-1] C_k;
input wire clk1;
output wire[0:n-1] O;
wire sel,O1,select, clk,mux_result;
wire[0:m-1] Ckr, mux_inner_poduct, shift_mux;
wire[0:n-1] shift_result,result,result_shift;
integer i;
reg sel1,select1, stop, start;
assign sel = sel1;
assign select = select1;
assign clk = (clk1&(~stop))&start;
MUX_ARRAY ma(mux_inner_poduct,Ckr,C_k,shift_mux,sel,clk);
RIGHT_SHIFT rs(shift_mux,Ckr,clk);
INNER_PRODUCT ip(O1,B,mux_inner_poduct);
//MUX m1(mux_result,O1,shift_result[0],select);
D_FLIP_FLOP #162 df(result,{O1,result[2:n-1],result[0]},clk,1'b1);
//RIGHT_SHIFT #162 rs2(shift_result,result,clk);
assign O = {result[1:n-1],result[0]};
initial begin
current_state = START_STATE;
sel1=1'b0;
i=0;
stop = 1'b0;
start = 1'b0;
end
always @(posedge clk)
begin
current_state <= next_state;
i=i+1;
if(i==n+1)
current_state<=FINAL_STATE;
end
always@(*)
begin
case(current_state)
START_STATE: begin
if(i>0)
next_state = INTER_STATE;
start = 1'b1;
//i = i+1;
end
INTER_STATE: begin
if(i==m)begin
next_state = FINAL_STATE;
end
$display("Incrementing the value of i");
//i=i+1;
sel1<=1'b1;
end
FINAL_STATE: begin
stop = 1'b1;
end
endcase
end
endmodule
module test_bench_multiply_b_ck();
wire[0:162] B,C_k;
wire[0:161] O;
wire clk;
MULTIPLY_B_CK mk(O,B,C_k,clk);
reg[0:162] B1,C_k1;
reg clk1;
assign clk=clk1;
assign B=B1;
assign C_k = C_k1;
initial
begin
clk1=1;
B1=163'd2;
C_k1=163'd2;
end
always #1 clk1=~clk1;
always #1 $display("B=%b C_k=%b O=%b mux_inner_poduct=%b Ckr=%b sel=%b O1=%b mux_result=%b shift_mux=%b i=%d",B,C_k,O,mk.mux_inner_poduct, mk.Ckr, mk.sel,mk.O1,mk.mux_result,mk.shift_mux ,mk.i);
endmodule
module tag(
);
endmodule
//module test_bench_demux();
// parameter m=163;
// parameter log_m = 7;
// wire A,clk;
// wire[0:log_m] sel;
// wire[0:m-1] O;
// DEMUX dm(O,A,sel,clk);
// reg[0:log_m] sel1;
// reg A1;
// assign A= A1;
// assign clk=1;
// initial
// begin
// #10
// sel1 = 7'd0;
// A1=1;
// $display("A=%b O=%b sel=%b",A,O,sel);
// #10
// sel1=7'd2;
// A1=0;
// $display("A=%b O=%b sel=%b",A,O,sel);
// #10
// sel1=7'd0;
// A1=0;
// $display("A=%b O=%b sel=%b",A,O,sel);
// end
//endmodule
module test_bench_d_flip_flop();
parameter m=163;
wire[0:m-1] A,Q;
reg[0:m-1] A1;
wire clk,reset;
reg clk1;
assign A=A1;
assign clk=clk1;
assign reset=1;
D_FLIP_FLOP d(Q,A,clk,reset);
initial
begin
clk1=0;
A1=163'd1;
end
always#100 clk1=~clk1;
initial
begin
#200
A1=163'd2;
$display("Q=%b A1=%b",Q,A);
#300
A1=163'd3;
$display("Q=%b A1=%b",Q,A);
#600
$display("Q=%b A1=%b",Q,A);
end
endmodule
module test_bench_mux();
wire A,B,O,sel;
MUX m(O,A,B,sel);
reg A1,B1,sel1;
assign A=A1,B=B1,sel=sel1;
initial
begin
#1
A1=1'b1;
B1=1'b0;
sel1=1'b1;
#2
$display("A=%b B=%b O=%b sel=%b ",A,B,O,sel);
#3
A1=1'b1;
B1=1'b0;
sel1=1'b0;
#4
$display("A=%b B=%b O=%b sel=%b ",A,B,O,sel);
end
endmodule
module test_bench_mux_array();
parameter m=163;
wire[0:m-1] A,B,O,B_R;
reg[0:m-1] A1,B1;
wire sel,clk;
reg sel1,clk1;
MUX_ARRAY mu(O,B_R,A,B,sel,clk);
assign A = A1;
assign B = B1;
assign sel = sel1;
assign clk = clk1;
initial
begin
#1
A1 = 163'd1;
B1 = 163'd3;
sel1 = 0;
#2
clk1 = 1;
#3
$display("A=%b B=%b B_R=%b sel=%b O=%b clk=%b",A,B,B_R,sel,O,clk);
#4
clk1=0;
#5
sel1=1;
#6
$display("A=%b B=%b B_R=%b sel=%b O=%b clk=%b",A,B,B_R,sel,O,clk);
#7
clk1=1;
#8
$display("A=%b B=%b B_R=%b sel=%b O=%b clk=%b",A,B,B_R,sel,O,clk);
end
endmodule
module test_bench_inner_product();
parameter m=163;
wire[0:m-1] A,B;
wire O;
INNER_PRODUCT in(O,A,B);
reg[0:162] A1,B1;
assign A=A1;
assign B=B1;
initial
begin
#10
A1 = 163'd3;
B1 = 163'd3;
#20
$display("A=%b B=%b O=%b",A,B,O);
#10
A1 = 163'd1;
B1 = 163'd0;
#20
$display("A=%b B=%b O=%b",A,B,O);
#10
A1 = 163'd1;
B1 = 163'd1;
#20
$display("A=%b B=%b O=%b",A,B,O);
end
endmodule
module test_bench_xor_gate();
wire A,B,O;
reg A1, B1;
XOR x(O,A,B);
assign A = A1;
assign B = B1;
initial
begin
#10
A1 = 1'b1;
B1 = 1'b1;
#20
$display("A=%b B=%b O=%b",A,B,O);
#30
A1 = 1'b0;
B1 = 1'b1;
#40
$display("A=%b B=%b O=%b",A,B,O);
#50
A1 = 1'b1;
B1 = 1'b0;
#60
$display("A=%b B=%b O=%b",A,B,O);
#70
A1 = 1'b0;
B1 = 1'b0;
#80
$display("A=%b B=%b O=%b",A,B,O);
end
endmodule
module test_bench_xor_array();
parameter m=163;
wire[0:m-1] A,B,O;
reg[0:m-1] A1,B1;
XOR_ARRAY x(O,A,B);
assign A = A1;
assign B = B1;
initial
begin
A1 = 10'd163;
B1 = 10'd163;
#10
$display("A=%b , B=%b, O=%b",A,B,O);
end
endmodule
module test_bench_and_array();
parameter m=163;
wire[0:m-1] A,B,O;
reg[0:m-1] A1,B1;
AND_ARRAY x(O,A,B);
assign A = A1;
assign B = B1;
initial
begin
A1 = 10'd163;
B1 = 10'd163;
#10
$display("A=%b , B=%b, O=%b",A,B,O);
end
endmodule
module testbench_xor_single_array();
parameter m=163;
wire[0:m-1] A;
wire O;
reg[0:m-1] A1;
XOR_SINGLE_ARRAY x(O,A);
assign A = A1;
initial
begin
A1 = 10'd3;
#10
$display("A=%b , O=%b",A,O);
end
endmodule |
/*
* Data memory test bench for five stage MIPS CPU.
*
* Currently only runs for several cycles and
* dumps a .vcd for Gtkwave.
*/
`include "dm.v"
module dm_tb;
reg clk;
reg [6:0] addr;
reg rd, wr;
reg [31:0] wdata;
wire [31:0] rdata;
dm dm1(.clk(clk), .addr(addr), .rd(rd), .wr(wr),
.rdata(rdata), .wdata(wdata));
always begin
clk <= ~clk;
#5;
end
initial begin
$dumpfile("dm_tb.vcd");
$dumpvars(0, dm_tb);
$display("addr, rd, wr, rdata, wdata");
$monitor("%x, %x, %x, %x, %x", addr, rd, wr, rdata, wdata);
clk <= 1'b0;
rd <= 1'b0;
wr <= 1'b0;
addr <= 7'd0;
@(posedge clk);
wdata <= 32'hABCDEF01;
addr <= 7'd0;
rd <= 1'b0;
wr <= 1'b1;
@(posedge clk);
wdata <= 32'hFFFFAAAA;
addr <= 7'd1;
rd <= 1'b0;
wr <= 1'b1;
@(posedge clk);
rd <= 1'b1;
wr <= 1'b0;
addr <= 7'd0;
@(posedge clk);
rd <= 1'b1;
wr <= 1'b0;
addr <= 7'd1;
@(posedge clk);
rd <= 1'b1;
wr <= 1'b1;
wdata <= 32'hFEFEFEFE;
addr <= 7'd0;
$finish;
end
endmodule
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31; // Data width
parameter DATA_DEPTH = 128;
parameter AW = 6; // Address width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data),
// Unused
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer j;
integer hit_count;
reg [63:0] cam_lookup_hit_vector;
strings strings ();
task show;
input [8*8-1:0] str;
reg [7:0] char;
integer loc;
begin
$write("[%0t] ",$time);
strings.stringStart(8*8-1);
for (char = strings.stringByte(str); !strings.isNull(char); char = strings.stringByte(str)) begin
$write("%c",char);
end
$write("\n");
end
endtask
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
show("hello\000xx");
end
if (cyc==2) begin
show("world\000xx");
end
if (cyc==4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module strings;
// **NOT** reentrant, just a test!
integer index;
task stringStart;
input [31:0] bits;
begin
index = (bits-1)/8;
end
endtask
function isNull;
input [7:0] chr;
isNull = (chr == 8'h0);
endfunction
function [7:0] stringByte;
input [8*8-1:0] str;
begin
if (index<=0) stringByte=8'h0;
else stringByte = str[index*8 +: 8];
index = index - 1;
end
endfunction
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module sub32 (
dataa,
datab,
clock,
aclr,
clken,
result)/* synthesis synthesis_clearbox = 1 */;
input [31:0] dataa;
input [31:0] datab;
input clock;
input aclr;
input clken;
output [31:0] result;
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module implements exponent extraction and returns the adjusted exponent as integer.
// Adjusted means that we remove the bias implicit in the FP numbers. That is exp=127 that represents exponent of 0
// is returned as 0.
module acl_fp_extract_exp( clock, resetn, enable, valid_in, valid_out, stall_in, stall_out, dataa, result);
parameter WIDTH = 32;
parameter HIGH_CAPACITY = 1;
input clock, resetn;
input enable, valid_in, stall_in;
output valid_out, stall_out;
input [WIDTH-1:0] dataa;
output [31:0] result;
// Simply extract the mantissa and at the most shift it to the right by one position.
reg c1_valid;
wire c1_stall;
wire c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
reg [31:0] c1_exponent;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_valid <= 1'b0;
c1_exponent <= 32'dx;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
if (WIDTH==32)
begin
if ((~(|dataa[WIDTH-2:WIDTH-9])) || (&dataa[WIDTH-2:WIDTH-9]))
begin
c1_exponent <= 32'h7fffffff;
end
else
begin
c1_exponent <= {1'b0, dataa[WIDTH-2:WIDTH-9]} - 9'd127;
end
end
else
begin
if ((~(|dataa[WIDTH-2:WIDTH-12])) || (&dataa[WIDTH-2:WIDTH-12]))
begin
c1_exponent <= 32'h7fffffff;
end
else
begin
c1_exponent <= {1'b0, dataa[WIDTH-2:WIDTH-12]} - 12'd1023;
end
end
end
end
assign c1_stall = stall_in;
assign valid_out = c1_valid;
assign result = c1_exponent;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYGATE4S15_PP_SYMBOL_V
`define SKY130_FD_SC_LP__DLYGATE4S15_PP_SYMBOL_V
/**
* dlygate4s15: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlygate4s15 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYGATE4S15_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221AI_4_V
`define SKY130_FD_SC_MS__O221AI_4_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog wrapper for o221ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o221ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o221ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o221ai_4 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o221ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221AI_4_V
|
module mojo_top(
// 50MHz clock input
input clk,
// Input from rst button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard leds
output[7:0]led,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
input en,
input [3:0] F,
output [3:0] D,
output [3:0] Q,
output A,
output B,
output A_latch,
output B_latch
);
wire rst = ~rst_n; // make rst active high
// these signals should be high-z when not used
assign spi_miso = 1'bz;
assign avr_rx = 1'bz;
assign spi_channel = 4'bzzzz;
reg [24:0] slow_clk_d, slow_clk_q;
always @(slow_clk_q) begin
slow_clk_d = slow_clk_q + 1'b1;
end
always @(posedge clk, posedge rst) begin
if (rst == 1) begin
slow_clk_q <= 25'b0;
end
else begin
slow_clk_q <= slow_clk_d;
end
end
assign led[7:4] = {4{slow_clk_q[24]}};
elevator real_deal (
.clk(slow_clk_q[24]),
.reset(rst),
.en(en),
.F(F),
.D(D),
.Q(Q),
.A(A),
.B(B),
.A_latch(A_latch),
.B_latch(B_latch),
.LED(led[3:0])
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
// bug749
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
genvar g;
for (g=1; g<3; ++g) begin : gblk
sub2 #(.IN(g)) u ();
//sub #(.IN(g)) u2 ();
end
sub1 #(.IN(0)) u ();
always @ (posedge clk) begin
if (t.u.IN != 0) $stop;
if (t.u.FLAVOR != 1) $stop;
//if (t.u2.IN != 0) $stop; // This should be not found
if (t.gblk[1].u.IN != 1) $stop;
if (t.gblk[2].u.IN != 2) $stop;
if (t.gblk[1].u.FLAVOR != 2) $stop;
if (t.gblk[2].u.FLAVOR != 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
module sub1 (/*AUTOARG*/);
parameter [31:0] IN = 99;
parameter FLAVOR = 1;
`ifdef TEST_VERBOSE
initial $display("%m");
`endif
endmodule
module sub2 (/*AUTOARG*/);
parameter [31:0] IN = 99;
parameter FLAVOR = 2;
`ifdef TEST_VERBOSE
initial $display("%m");
`endif
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* This tests the printing of a string stored in a reg, with leading blanks. */
module main;
reg [8*7:1] foo;
reg [7:0] tmp;
initial
begin
foo = "PASSED";
tmp = foo[8*7:8*6+1];
if (tmp !== 8'h00) begin
$display("FAILED -- high bits are %b", tmp);
$finish;
end
$display("%s", foo);
end
endmodule // main
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: AXI3 Slave Converter
// This module instantiates Address, Write Data and Read Data AXI3 Converter
// modules, each one taking care of the channel specific tasks.
// The Address AXI3 converter can handle both AR and AW channels.
// The Write Respons Channel is reused from the Down-Sizer.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi3_conv
// a_axi3_conv
// axic_fifo
// w_axi3_conv
// b_downsizer
// r_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1,
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
parameter integer C_SINGLE_THREAD = 1
// 0 = Ignore ID when propagating transactions (assume all responses are in order).
// 1 = Enforce single-threading (one ID at a time) when any outstanding or
// requested transaction requires splitting.
// While no split is ongoing any new non-split transaction will pass immediately regardless
// off ID.
// A split transaction will stall if there are multiple ID (non-split) transactions
// ongoing, once it has been forwarded only transactions with the same ID is allowed
// (split or not) until all ongoing split transactios has been completed.
)
(
// System Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [8-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [1-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [4-1:0] S_AXI_AWQOS,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [8-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [1-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [4-1:0] S_AXI_ARQOS,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [4-1:0] M_AXI_AWQOS,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [4-1:0] M_AXI_ARQOS,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
// Write Channel Signals for Commands Queue Interface.
wire wr_cmd_valid;
wire [C_AXI_ID_WIDTH-1:0] wr_cmd_id;
wire [4-1:0] wr_cmd_length;
wire wr_cmd_ready;
wire wr_cmd_b_valid;
wire wr_cmd_b_split;
wire [4-1:0] wr_cmd_b_repeat;
wire wr_cmd_b_ready;
// Write Address Channel.
axi_protocol_converter_v2_1_8_a_axi3_conv #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_AXI_CHANNEL (0),
.C_SUPPORT_SPLITTING (C_SUPPORT_SPLITTING),
.C_SUPPORT_BURSTS (C_SUPPORT_BURSTS),
.C_SINGLE_THREAD (C_SINGLE_THREAD)
) write_addr_inst
(
// Global Signals
.ARESET (~ARESETN),
.ACLK (ACLK),
// Command Interface (W)
.cmd_valid (wr_cmd_valid),
.cmd_split (),
.cmd_id (wr_cmd_id),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Command Interface (B)
.cmd_b_valid (wr_cmd_b_valid),
.cmd_b_split (wr_cmd_b_split),
.cmd_b_repeat (wr_cmd_b_repeat),
.cmd_b_ready (wr_cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AID (S_AXI_AWID),
.S_AXI_AADDR (S_AXI_AWADDR),
.S_AXI_ALEN (S_AXI_AWLEN),
.S_AXI_ASIZE (S_AXI_AWSIZE),
.S_AXI_ABURST (S_AXI_AWBURST),
.S_AXI_ALOCK (S_AXI_AWLOCK),
.S_AXI_ACACHE (S_AXI_AWCACHE),
.S_AXI_APROT (S_AXI_AWPROT),
.S_AXI_AQOS (S_AXI_AWQOS),
.S_AXI_AUSER (S_AXI_AWUSER),
.S_AXI_AVALID (S_AXI_AWVALID),
.S_AXI_AREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AID (M_AXI_AWID),
.M_AXI_AADDR (M_AXI_AWADDR),
.M_AXI_ALEN (M_AXI_AWLEN),
.M_AXI_ASIZE (M_AXI_AWSIZE),
.M_AXI_ABURST (M_AXI_AWBURST),
.M_AXI_ALOCK (M_AXI_AWLOCK),
.M_AXI_ACACHE (M_AXI_AWCACHE),
.M_AXI_APROT (M_AXI_AWPROT),
.M_AXI_AQOS (M_AXI_AWQOS),
.M_AXI_AUSER (M_AXI_AWUSER),
.M_AXI_AVALID (M_AXI_AWVALID),
.M_AXI_AREADY (M_AXI_AWREADY)
);
// Write Data Channel.
axi_protocol_converter_v2_1_8_w_axi3_conv #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH),
.C_SUPPORT_SPLITTING (C_SUPPORT_SPLITTING),
.C_SUPPORT_BURSTS (C_SUPPORT_BURSTS)
) write_data_inst
(
// Global Signals
.ARESET (~ARESETN),
.ACLK (ACLK),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_id (wr_cmd_id),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
if ( C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_SPLIT_W
// Write Data Response Channel.
axi_protocol_converter_v2_1_8_b_downsizer #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH)
) write_resp_inst
(
// Global Signals
.ARESET (~ARESETN),
.ACLK (ACLK),
// Command Interface
.cmd_valid (wr_cmd_b_valid),
.cmd_split (wr_cmd_b_split),
.cmd_repeat (wr_cmd_b_repeat),
.cmd_ready (wr_cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY)
);
end else begin : NO_SPLIT_W
// MI -> SI Interface Write Response Ports
assign S_AXI_BID = M_AXI_BID;
assign S_AXI_BRESP = M_AXI_BRESP;
assign S_AXI_BUSER = M_AXI_BUSER;
assign S_AXI_BVALID = M_AXI_BVALID;
assign M_AXI_BREADY = S_AXI_BREADY;
end
end else begin : NO_WRITE
// Slave Interface Write Address Ports
assign S_AXI_AWREADY = 1'b0;
// Slave Interface Write Data Ports
assign S_AXI_WREADY = 1'b0;
// Slave Interface Write Response Ports
assign S_AXI_BID = {C_AXI_ID_WIDTH{1'b0}};
assign S_AXI_BRESP = 2'b0;
assign S_AXI_BUSER = {C_AXI_BUSER_WIDTH{1'b0}};
assign S_AXI_BVALID = 1'b0;
// Master Interface Write Address Port
assign M_AXI_AWID = {C_AXI_ID_WIDTH{1'b0}};
assign M_AXI_AWADDR = {C_AXI_ADDR_WIDTH{1'b0}};
assign M_AXI_AWLEN = 4'b0;
assign M_AXI_AWSIZE = 3'b0;
assign M_AXI_AWBURST = 2'b0;
assign M_AXI_AWLOCK = 2'b0;
assign M_AXI_AWCACHE = 4'b0;
assign M_AXI_AWPROT = 3'b0;
assign M_AXI_AWQOS = 4'b0;
assign M_AXI_AWUSER = {C_AXI_AWUSER_WIDTH{1'b0}};
assign M_AXI_AWVALID = 1'b0;
// Master Interface Write Data Ports
assign M_AXI_WDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign M_AXI_WSTRB = {C_AXI_DATA_WIDTH/8{1'b0}};
assign M_AXI_WLAST = 1'b0;
assign M_AXI_WUSER = {C_AXI_WUSER_WIDTH{1'b0}};
assign M_AXI_WVALID = 1'b0;
// Master Interface Write Response Ports
assign M_AXI_BREADY = 1'b0;
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
// Write Response channel.
if ( C_SUPPORT_SPLITTING == 1 && C_SUPPORT_BURSTS == 1 ) begin : USE_SPLIT_R
// Read Channel Signals for Commands Queue Interface.
wire rd_cmd_valid;
wire rd_cmd_split;
wire rd_cmd_ready;
// Write Address Channel.
axi_protocol_converter_v2_1_8_a_axi3_conv #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_AUSER_WIDTH (C_AXI_ARUSER_WIDTH),
.C_AXI_CHANNEL (1),
.C_SUPPORT_SPLITTING (C_SUPPORT_SPLITTING),
.C_SUPPORT_BURSTS (C_SUPPORT_BURSTS),
.C_SINGLE_THREAD (C_SINGLE_THREAD)
) read_addr_inst
(
// Global Signals
.ARESET (~ARESETN),
.ACLK (ACLK),
// Command Interface (R)
.cmd_valid (rd_cmd_valid),
.cmd_split (rd_cmd_split),
.cmd_id (),
.cmd_length (),
.cmd_ready (rd_cmd_ready),
// Command Interface (B)
.cmd_b_valid (),
.cmd_b_split (),
.cmd_b_repeat (),
.cmd_b_ready (1'b0),
// Slave Interface Write Address Ports
.S_AXI_AID (S_AXI_ARID),
.S_AXI_AADDR (S_AXI_ARADDR),
.S_AXI_ALEN (S_AXI_ARLEN),
.S_AXI_ASIZE (S_AXI_ARSIZE),
.S_AXI_ABURST (S_AXI_ARBURST),
.S_AXI_ALOCK (S_AXI_ARLOCK),
.S_AXI_ACACHE (S_AXI_ARCACHE),
.S_AXI_APROT (S_AXI_ARPROT),
.S_AXI_AQOS (S_AXI_ARQOS),
.S_AXI_AUSER (S_AXI_ARUSER),
.S_AXI_AVALID (S_AXI_ARVALID),
.S_AXI_AREADY (S_AXI_ARREADY),
// Master Interface Write Address Port
.M_AXI_AID (M_AXI_ARID),
.M_AXI_AADDR (M_AXI_ARADDR),
.M_AXI_ALEN (M_AXI_ARLEN),
.M_AXI_ASIZE (M_AXI_ARSIZE),
.M_AXI_ABURST (M_AXI_ARBURST),
.M_AXI_ALOCK (M_AXI_ARLOCK),
.M_AXI_ACACHE (M_AXI_ARCACHE),
.M_AXI_APROT (M_AXI_ARPROT),
.M_AXI_AQOS (M_AXI_ARQOS),
.M_AXI_AUSER (M_AXI_ARUSER),
.M_AXI_AVALID (M_AXI_ARVALID),
.M_AXI_AREADY (M_AXI_ARREADY)
);
// Read Data Channel.
axi_protocol_converter_v2_1_8_r_axi3_conv #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (C_AXI_SUPPORTS_USER_SIGNALS),
.C_AXI_RUSER_WIDTH (C_AXI_RUSER_WIDTH),
.C_SUPPORT_SPLITTING (C_SUPPORT_SPLITTING),
.C_SUPPORT_BURSTS (C_SUPPORT_BURSTS)
) read_data_inst
(
// Global Signals
.ARESET (~ARESETN),
.ACLK (ACLK),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_split (rd_cmd_split),
.cmd_ready (rd_cmd_ready),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_RID),
.S_AXI_RDATA (S_AXI_RDATA),
.S_AXI_RRESP (S_AXI_RRESP),
.S_AXI_RLAST (S_AXI_RLAST),
.S_AXI_RUSER (S_AXI_RUSER),
.S_AXI_RVALID (S_AXI_RVALID),
.S_AXI_RREADY (S_AXI_RREADY),
// Master Interface Read Data Ports
.M_AXI_RID (M_AXI_RID),
.M_AXI_RDATA (M_AXI_RDATA),
.M_AXI_RRESP (M_AXI_RRESP),
.M_AXI_RLAST (M_AXI_RLAST),
.M_AXI_RUSER (M_AXI_RUSER),
.M_AXI_RVALID (M_AXI_RVALID),
.M_AXI_RREADY (M_AXI_RREADY)
);
end else begin : NO_SPLIT_R
// SI -> MI Interface Write Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARQOS = S_AXI_ARQOS;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// MI -> SI Interface Read Data Ports
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
end
end else begin : NO_READ
// Slave Interface Read Address Ports
assign S_AXI_ARREADY = 1'b0;
// Slave Interface Read Data Ports
assign S_AXI_RID = {C_AXI_ID_WIDTH{1'b0}};
assign S_AXI_RDATA = {C_AXI_DATA_WIDTH{1'b0}};
assign S_AXI_RRESP = 2'b0;
assign S_AXI_RLAST = 1'b0;
assign S_AXI_RUSER = {C_AXI_RUSER_WIDTH{1'b0}};
assign S_AXI_RVALID = 1'b0;
// Master Interface Read Address Port
assign M_AXI_ARID = {C_AXI_ID_WIDTH{1'b0}};
assign M_AXI_ARADDR = {C_AXI_ADDR_WIDTH{1'b0}};
assign M_AXI_ARLEN = 4'b0;
assign M_AXI_ARSIZE = 3'b0;
assign M_AXI_ARBURST = 2'b0;
assign M_AXI_ARLOCK = 2'b0;
assign M_AXI_ARCACHE = 4'b0;
assign M_AXI_ARPROT = 3'b0;
assign M_AXI_ARQOS = 4'b0;
assign M_AXI_ARUSER = {C_AXI_ARUSER_WIDTH{1'b0}};
assign M_AXI_ARVALID = 1'b0;
// Master Interface Read Data Ports
assign M_AXI_RREADY = 1'b0;
end
endgenerate
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
wire [31:0] inp = crc[31:0];
wire reset = (cyc < 5);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [31:0] outp; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.outp (outp[31:0]),
// Inputs
.reset (reset),
.clk (clk),
.inp (inp[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {32'h0, outp};
// What checksum will we end up with
`define EXPECTED_SUM 64'ha7f0a34f9cf56ccb
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
outp,
// Inputs
reset, clk, inp
);
input reset;
input clk;
input [31:0] inp;
output [31:0] outp;
function [31:0] no_inline_function;
input [31:0] var1;
input [31:0] var2;
/*verilator no_inline_task*/
reg [31*2:0] product1 ;
reg [31*2:0] product2 ;
integer i;
reg [31:0] tmp;
begin
product2 = {(31*2+1){1'b0}};
for (i = 0; i < 32; i = i + 1)
if (var2[i]) begin
product1 = { {31*2+1-32{1'b0}}, var1} << i;
product2 = product2 ^ product1;
end
no_inline_function = 0;
for (i= 0; i < 31; i = i + 1 )
no_inline_function[i+1] = no_inline_function[i] ^ product2[i] ^ var1[i];
end
endfunction
reg [31:0] outp;
reg [31:0] inp_d;
always @( posedge clk ) begin
if( reset ) begin
outp <= 0;
end
else begin
inp_d <= inp;
outp <= no_inline_function(inp, inp_d);
end
end
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_switch
*/
module test_axis_switch_4x4;
// Parameters
parameter S_COUNT = 4;
parameter M_COUNT = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_WIDTH = $clog2(M_COUNT+1);
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter M_BASE = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_TOP = {3'd3, 3'd2, 3'd1, 3'd0};
parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}};
parameter S_REG_TYPE = 0;
parameter M_REG_TYPE = 2;
parameter ARB_TYPE_ROUND_ROBIN = 1;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg [M_COUNT-1:0] m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata;
wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep;
wire [M_COUNT-1:0] m_axis_tvalid;
wire [M_COUNT-1:0] m_axis_tlast;
wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid;
wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest;
wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_switch_4x4.lxt");
$dumpvars(0, test_axis_switch_4x4);
end
axis_switch #(
.M_COUNT(M_COUNT),
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.M_BASE(M_BASE),
.M_TOP(M_TOP),
.M_CONNECT(M_CONNECT),
.S_REG_TYPE(S_REG_TYPE),
.M_REG_TYPE(M_REG_TYPE),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Title : LPDDR2 controller address and command decoder
//
// File : alt_mem_ddrx_lpddr2_addr_cmd.v
//
// Abstract : LPDDR2 Address and command decoder
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module alt_mem_ddrx_lpddr2_addr_cmd
# (parameter
// Global parameters
CFG_PORT_WIDTH_OUTPUT_REGD = 1,
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CKE_WIDTH = 1, // same width as CS_WIDTH
CFG_MEM_IF_ADDR_WIDTH = 20,
CFG_MEM_IF_ROW_WIDTH = 15, // max supported row bits
CFG_MEM_IF_COL_WIDTH = 12, // max supported column bits
CFG_MEM_IF_BA_WIDTH = 3, // max supported bank bits
CFG_DWIDTH_RATIO = 2
)
(
ctl_clk,
ctl_reset_n,
ctl_cal_success,
//run-time configuration interface
cfg_output_regd,
// AFI interface (Signals from Arbiter block)
do_write,
do_read,
do_auto_precharge,
do_activate,
do_precharge,
do_precharge_all,
do_refresh,
do_self_refresh,
do_power_down,
do_lmr,
do_lmr_read, //Currently does not exist in arbiter
do_refresh_1bank, //Currently does not exist in arbiter
do_burst_terminate, //Currently does not exist in arbiter
do_deep_pwrdwn, //Currently does not exist in arbiter
// address information
to_chip, // active high input (one hot)
to_bank,
to_row,
to_col,
to_lmr,
lmr_opcode,
//output
afi_cke,
afi_cs_n,
afi_addr,
afi_rst_n
);
input ctl_clk;
input ctl_reset_n;
input ctl_cal_success;
//run-time configuration input
input [CFG_PORT_WIDTH_OUTPUT_REGD -1:0] cfg_output_regd;
// Arbiter command inputs
input do_write;
input do_read;
input do_auto_precharge;
input do_activate;
input do_precharge;
input [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
input [CFG_MEM_IF_CHIP-1:0] do_refresh;
input [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
input [CFG_MEM_IF_CHIP-1:0] do_power_down;
input [CFG_MEM_IF_CHIP-1:0] do_deep_pwrdwn;
input do_lmr;
input do_lmr_read;
input do_refresh_1bank;
input do_burst_terminate;
input [CFG_MEM_IF_CHIP-1:0] to_chip;
input [CFG_MEM_IF_BA_WIDTH-1:0] to_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] to_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] to_col;
input [7:0] to_lmr;
input [7:0] lmr_opcode;
//output
output [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
wire do_write;
wire do_read;
wire do_auto_precharge;
wire do_activate;
wire do_precharge;
wire [CFG_MEM_IF_CHIP-1:0] do_precharge_all;
wire [CFG_MEM_IF_CHIP-1:0] do_refresh;
wire [CFG_MEM_IF_CHIP-1:0] do_self_refresh;
wire [CFG_MEM_IF_CHIP-1:0] do_power_down;
wire [CFG_MEM_IF_CHIP-1:0] do_deep_pwrdwn;
wire do_lmr;
wire do_lmr_read;
wire do_refresh_1bank;
wire do_burst_terminate;
reg [2:0] temp_bank_addr;
reg [14:0] temp_row_addr;
reg [11:0] temp_col_addr;
wire [(CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cke;
wire [(CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
wire [(CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO/2)) - 1:0] afi_addr;
wire [(CFG_DWIDTH_RATIO/2) - 1:0] afi_rst_n;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] int_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] int_cs_n;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] int_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr;
reg [(CFG_MEM_IF_CKE_WIDTH) - 1:0] combi_cke_r;
reg [(CFG_MEM_IF_CHIP) - 1:0] combi_cs_n_r;
reg [(CFG_MEM_IF_ADDR_WIDTH) - 1:0] combi_addr_r;
reg [CFG_MEM_IF_CHIP-1:0] chip_in_self_refresh;
assign afi_rst_n = {(CFG_DWIDTH_RATIO/2){1'b1}};
generate
if (CFG_DWIDTH_RATIO == 2) begin
assign afi_cke = int_cke;
assign afi_cs_n = int_cs_n;
assign afi_addr = int_addr;
end
else begin
assign afi_cke = {int_cke,int_cke};
assign afi_cs_n = (do_burst_terminate)? {int_cs_n,int_cs_n} :{int_cs_n,{CFG_MEM_IF_CHIP{1'b1}}};
assign afi_addr = {int_addr,int_addr};
end
endgenerate
// need half rate code to adjust for half rate cke or cs
always @(posedge ctl_clk, negedge ctl_reset_n) // toogles cs_n for only one cyle when state machine continues to stay in slf rfsh mode or DPD
begin
if (!ctl_reset_n)
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
else
if ((do_self_refresh) || (do_deep_pwrdwn))
chip_in_self_refresh <= do_self_refresh | do_deep_pwrdwn;
else
chip_in_self_refresh <= {(CFG_MEM_IF_CHIP){1'b0}};
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
combi_cke_r <= {CFG_MEM_IF_CKE_WIDTH{1'b1}} ;
combi_cs_n_r <= {CFG_MEM_IF_CHIP{1'b1}} ;
combi_addr_r <= {CFG_MEM_IF_ADDR_WIDTH{1'b0}};
end
else
begin
combi_cke_r <= combi_cke ;
combi_cs_n_r <= combi_cs_n ;
combi_addr_r <= combi_addr ;
end
end
always @(*)
begin
if (cfg_output_regd)
begin
int_cke = combi_cke_r;
int_cs_n = combi_cs_n_r;
int_addr = combi_addr_r;
end
else
begin
int_cke = combi_cke;
int_cs_n = combi_cs_n;
int_addr = combi_addr;
end
end
always @ (*)
begin
temp_row_addr = {CFG_MEM_IF_ROW_WIDTH{1'b0}} ;
temp_col_addr = {CFG_MEM_IF_COL_WIDTH{1'b0}} ;
temp_bank_addr = {CFG_MEM_IF_BA_WIDTH {1'b0}} ;
temp_row_addr = to_row ;
temp_col_addr = to_col ;
temp_bank_addr = to_bank;
end
//CKE generation block
always @(*)
begin
if (ctl_cal_success)
begin
combi_cke = ~(do_self_refresh | do_power_down | do_deep_pwrdwn);
end
else
begin
combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
end
end
always @(*)
begin
if (ctl_cal_success)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
if (|do_refresh)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~do_refresh;
combi_addr[3:0] = 4'b1100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_refresh_1bank)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if ((|do_precharge_all) || do_precharge)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~ (do_precharge_all|do_precharge);
combi_addr[3:0] = 4'b1011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,2'b00,(|do_precharge_all)};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_activate)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = {temp_row_addr[9:8],2'b10};
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_row_addr[12:10]};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_row_addr[14:13],temp_row_addr[7:0]};
end
if (do_write)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0001;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_col_addr[2:1],1'b0};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_col_addr[11:3],do_auto_precharge};
end
if (do_read)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0101;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {temp_bank_addr,temp_col_addr[2:1],1'b0};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {temp_col_addr[11:3],do_auto_precharge};
end
if (|do_power_down)
begin
//combi_cke = ~do_power_down;
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr[3:0] = 4'b0000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (|do_deep_pwrdwn)
begin
//combi_cke = ~do_deep_pwrdwn;
combi_cs_n = ~do_deep_pwrdwn; // toogles cs_n for only one cyle when state machine continues to stay in DPD;
combi_addr[3:0] = 4'b0011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (|do_self_refresh)
begin
//combi_cke = ~do_self_refresh;
combi_cs_n = ~do_self_refresh; // toogles cs_n for only one cyle when state machine continues to stay in DPD;
combi_addr[3:0] = 4'b0100;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
if (do_lmr)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = to_lmr[5:0];
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {to_lmr[7:6],lmr_opcode};
end
if (do_lmr_read)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b1000;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = to_lmr[5:0];
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {to_lmr[7:6],{8{1'b0}}};
end
if (do_burst_terminate)
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = ~to_chip;
combi_addr[3:0] = 4'b0011;
combi_addr[(CFG_MEM_IF_ADDR_WIDTH/2) - 1 : 4] = {(CFG_MEM_IF_ADDR_WIDTH/2 - 4){1'b0}};
combi_addr[CFG_MEM_IF_ADDR_WIDTH - 1 : 10] = {(CFG_MEM_IF_ADDR_WIDTH/2){1'b0}};
end
end
else
begin
//combi_cke = {(CFG_MEM_IF_CKE_WIDTH){1'b1}};
combi_cs_n = {(CFG_MEM_IF_CHIP){1'b1}};
combi_addr = {(CFG_MEM_IF_ADDR_WIDTH){1'b0}};
end
end
endmodule
|
module testbench();
`include "bsg_noc_links.vh"
parameter x_cord_width_p = 2;
parameter y_cord_width_p = 2;
parameter max_payload_width_p = 17;
parameter max_num_flit_p = 3;
localparam len_width_lp = `BSG_SAFE_CLOG2(max_num_flit_p);
localparam max_packet_width_lp = (max_payload_width_p+len_width_lp+y_cord_width_p+x_cord_width_p);
localparam flit_width_lp =
(max_packet_width_lp/max_num_flit_p)+((max_packet_width_lp%max_num_flit_p) == 0 ? 0 : 1);
logic clk;
bsg_nonsynth_clock_gen #(
.cycle_time_p(1000)
) clock_gen (
.o(clk)
);
logic reset;
bsg_nonsynth_reset_gen #(
.num_clocks_p(1)
,.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
logic [max_packet_width_lp-1:0] data_li;
logic v_li, ready_lo;
logic [flit_width_lp-1:0] data_lo;
logic v_lo, ready_li;
`declare_bsg_ready_and_link_sif_s(flit_width_lp, bsg_ready_and_link_sif_s);
bsg_ready_and_link_sif_s link_lo, link_li;
assign data_lo = link_lo.data;
assign v_lo = link_lo.v;
assign link_li.v = '0;
assign link_li.data = '0;
assign link_li.ready_and_rev = ready_li;
bsg_wormhole_router_adapter_in #(
.max_num_flit_p(max_num_flit_p)
,.max_payload_width_p(max_payload_width_p)
,.x_cord_width_p(x_cord_width_p)
,.y_cord_width_p(y_cord_width_p)
) adapter (
.clk_i(clk)
,.reset_i(reset)
,.data_i(data_li)
,.v_i(v_li)
,.ready_o(ready_lo)
,.link_o(link_lo)
,.link_i(link_li)
);
logic [flit_width_lp-1:0] fifo_data_lo;
logic fifo_yumi_li;
logic fifo_v_lo;
logic fifo_ready_lo;
bsg_fifo_1r1w_small #(
.width_p(flit_width_lp)
,.els_p(16)
) fifo_out (
.clk_i(clk)
,.reset_i(reset)
,.v_i(v_lo)
,.data_i(data_lo)
,.ready_o(fifo_ready_lo)
,.data_o(fifo_data_lo)
,.v_o(fifo_v_lo)
,.yumi_i(fifo_yumi_li)
);
assign ready_li = fifo_ready_lo;
logic [flit_width_lp-1:0] fifo_data_lo;
logic fifo_yumi_li;
logic fifo_v_lo;
logic fifo_ready_lo;
bsg_fifo_1r1w_small #(
.width_p(flit_width_lp)
,.els_p(16)
) fifo_out (
.clk_i(clk)
,.reset_i(reset)
,.v_i(v_lo)
,.data_i(data_lo)
,.ready_o(fifo_ready_lo)
,.data_o(fifo_data_lo)
,.v_o(fifo_v_lo)
,.yumi_i(fifo_yumi_li)
);
assign ready_li = fifo_ready_lo;
parameter rom_addr_width_p = 10;
logic [rom_addr_width_p-1:0] rom_addr;
logic [max_packet_width_lp+4-1:0] rom_data;
logic done;
logic tr_ready_lo;
bsg_fsb_node_trace_replay #(
.ring_width_p(max_packet_width_lp)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(fifo_v_lo)
,.data_i({{(max_packet_width_lp-flit_width_lp){1'b0}}, fifo_data_lo})
,.ready_o(tr_ready_lo)
,.v_o(v_li)
,.data_o(data_li)
,.yumi_i(v_li & ready_lo)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(done)
,.error_o()
);
assign fifo_yumi_li = fifo_v_lo & tr_ready_lo;
bsg_trace_rom #(
.width_p(max_packet_width_lp+4)
,.addr_width_p(rom_addr_width_p)
) rom (
.addr_i(rom_addr)
,.data_o(rom_data)
);
initial begin
wait(done);
//for (integer i =0; i < 1000; i++) begin
// @(posedge clk);
//end
$finish;
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module control(clk,en,dsp_sel,an);
input clk, en;
output [1:0]dsp_sel;
output [3:0]an;
wire a,b,c,d,e,f,g,h,i,j,k,l;
assign an[3] = a;
assign an[2] = b;
assign an[1] = c;
assign an[0] = d;
assign dsp_sel[1] = e;
assign dsp_sel[0] = i;
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF3(
.Q(a), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(d), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF2(
.Q(b), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(a), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF1(
.Q(c), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(b), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF0(
.Q(d), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(c), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF7(
.Q(e), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(h), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF6(
.Q(f), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(e), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF5(
.Q(g), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(f), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF4(
.Q(h), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(g), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF11(
.Q(i), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(l), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF10(
.Q(j), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(i), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) DFF9(
.Q(k), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(j), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
FDRSE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) DFF8(
.Q(l), // Data output
.C(clk), // Clock input
.CE(en), // Clock enable input
.D(k), // Data input
.R(1'b0), // Synchronous reset input
.S(1'b0) // Synchronous set input
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: length_gen_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module length_gen_fifo (
aclr,
clock,
data,
rdreq,
wrreq,
empty,
q,
usedw);
input aclr;
input clock;
input [32:0] data;
input rdreq;
input wrreq;
output empty;
output [32:0] q;
output [8:0] usedw;
wire [8:0] sub_wire0;
wire sub_wire1;
wire [32:0] sub_wire2;
wire [8:0] usedw = sub_wire0[8:0];
wire empty = sub_wire1;
wire [32:0] q = sub_wire2[32:0];
scfifo scfifo_component (
.rdreq (rdreq),
.aclr (aclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.almost_empty (),
.almost_full (),
.full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Arria II GX",
scfifo_component.lpm_numwords = 512,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 33,
scfifo_component.lpm_widthu = 9,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "33"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "33"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "33"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 33 0 INPUT NODEFVAL data[32..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: q 0 0 33 0 OUTPUT NODEFVAL q[32..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 9 0 OUTPUT NODEFVAL usedw[8..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 33 0 data 0 0 33 0
// Retrieval info: CONNECT: q 0 0 33 0 @q 0 0 33 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 9 0 @usedw 0 0 9 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL length_gen_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL length_gen_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL length_gen_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL length_gen_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL length_gen_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL length_gen_fifo_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL length_gen_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL length_gen_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SEDFXTP_2_V
`define SKY130_FD_SC_LS__SEDFXTP_2_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog wrapper for sedfxtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sedfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sedfxtp_2 (
Q ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sedfxtp_2 (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sedfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SEDFXTP_2_V
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/counter.v
*/
// Behavioral model for the 32-bit program counter
module program_counter2 (next_pc,rst,clk);
// Output signals...
// Incremented value of the program counter
output [0:31] next_pc;
// ===============================================================
// Input signals
// Clock signal for the program counter
input clk;
// Reset signal for the program counter
input rst;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*/
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:31] next_pc; // Output signals
reg [0:31] temp_pc; // Output signals
// ===============================================================
always @(posedge clk)
begin
// If the reset signal sis set to HIGH
if(rst)
begin
// Set its value to ZERO
next_pc<=32'd0;
temp_pc<=32'd0;
end
else
begin
temp_pc<=temp_pc+32'd4;
next_pc<=temp_pc>>2;
end
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// --------------------------------------------------------------------------------
//| Avalon ST Bytes to Packet
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_bytes_to_packets
//if ENCODING ==0, CHANNEL_WIDTH must be 8
//else CHANNEL_WIDTH can be from 0 to 127
#( parameter CHANNEL_WIDTH = 8,
parameter ENCODING = 0 )
(
// Interface: clk
input clk,
input reset_n,
// Interface: ST out with packets
input out_ready,
output reg out_valid,
output reg [7: 0] out_data,
output reg [CHANNEL_WIDTH-1: 0] out_channel,
output reg out_startofpacket,
output reg out_endofpacket,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc, received_channel, received_varchannel;
wire escape_char, sop_char, eop_char, channel_char, varchannelesc_char;
// data out mux.
// we need it twice (data & channel out), so use a wire here
wire [7:0] data_out;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign sop_char = (in_data == 8'h7a);
assign eop_char = (in_data == 8'h7b);
assign channel_char = (in_data == 8'h7c);
assign escape_char = (in_data == 8'h7d);
assign data_out = received_esc ? (in_data ^ 8'h20) : in_data;
generate
if (CHANNEL_WIDTH == 0) begin
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
//we choose not to pipeline here. We can process special characters when
//in_ready, but in a chain of microcores, backpressure path is usually
//time critical, so we keep it simple here.
in_ready = out_ready;
//out_valid when in_valid, except when we are processing the special
//characters. However, if we are in escape received mode, then we are
//valid
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (sop_char | eop_char | escape_char | channel_char) out_valid = 0;
end
out_data = data_out;
end
end else begin
assign varchannelesc_char = in_data[7];
// Synchorous block -- reset and registers
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
received_channel <= 0;
received_varchannel <= 0;
out_startofpacket <= 0;
out_endofpacket <= 0;
end else begin
// we take data when in_valid and in_ready
if (in_valid & in_ready) begin
if (received_esc) begin
//if we got esc char, after next byte is consumed, quit esc mode
if (out_ready | received_channel | received_varchannel) received_esc <= 0;
end else begin
if (escape_char) received_esc <= 1;
if (sop_char) out_startofpacket <= 1;
if (eop_char) out_endofpacket <= 1;
if (channel_char & ENCODING ) received_varchannel <= 1;
if (channel_char & ~ENCODING) received_channel <= 1;
end
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char ))) begin
received_channel <= 0;
end
if (received_varchannel & ~varchannelesc_char & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
received_varchannel <= 0;
end
if (out_ready & out_valid) begin
out_startofpacket <= 0;
out_endofpacket <= 0;
end
end
end
end
// Combinational block for in_ready and out_valid
always @* begin
in_ready = out_ready;
out_valid = 0;
if ((out_ready | ~out_valid) && in_valid) begin
out_valid = 1;
if (received_esc) begin
if (received_channel | received_varchannel) out_valid = 0;
end else begin
if (sop_char | eop_char | escape_char | channel_char | received_channel | received_varchannel) out_valid = 0;
end
end
out_data = data_out;
end
end
endgenerate
// Channel block
generate
if (CHANNEL_WIDTH == 0) begin
always @(posedge clk) begin
out_channel <= 'h0;
end
end else if (CHANNEL_WIDTH < 8) begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out only the required bits
out_channel[CHANNEL_WIDTH-1:0] <= data_out[CHANNEL_WIDTH-1:0];
end
end
end
end
end else begin
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
out_channel <= 'h0;
end else begin
if (in_ready & in_valid) begin
if (received_channel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char))) begin
out_channel <= data_out;
end else if ((channel_char & ENCODING) & (~received_esc & ~sop_char & ~eop_char & ~escape_char )) begin
// Variable Channel Encoding always setting to 0 before begin to shift the channel in
out_channel <= 'h0;
end else if (received_varchannel & (received_esc | (~sop_char & ~eop_char & ~escape_char & ~channel_char & ~received_channel))) begin
// Shifting out the lower 7 bits
out_channel <= out_channel <<7;
out_channel[6:0] <= data_out[6:0];
end
end
end
end
end
endgenerate
endmodule
|
`timescale 1ns/10ps
module video720_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("true"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(1),
.output_clock_frequency0("74.250000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O221AI_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o221ai (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221AI_BLACKBOX_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: icd2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module sgb_icd2(
input RST,
output CPU_RST,
input CLK,
input CLK_SYSCLK,
output CLK_CPU_EDGE,
// MMIO interface
input SNES_RD_start,
input SNES_WR_end,
input [23:0] SNES_ADDR,
input [7:0] DATA_IN,
output [7:0] DATA_OUT,
input BOOTROM_ACTIVE,
// Pixel interface
input PPU_DOT_EDGE,
input PPU_PIXEL_VALID,
input [1:0] PPU_PIXEL,
input PPU_VSYNC_EDGE,
input PPU_HSYNC_EDGE,
// Button/Serial interface
input [1:0] P1I,
output [3:0] P1O,
// Halt interface
output IDL,
// Features
input [15:0] FEAT,
// Debug state
input [11:0] DBG_ADDR,
output [7:0] DBG_DATA_OUT
);
integer i;
//-------------------------------------------------------------------
// DESCRIPTION
//-------------------------------------------------------------------
// The ICD2 interfaces the SNES with the SGB via two points:
// SNES - cartridge bus
// SGB - pixel output, button/serial
//
// The pixel interface takes the 2b PPU output and renders it back into a SNES
// 2bpp planar format before writing into 1 of 4 row (scanline) buffers.
// The 2b button interface serves as a way for the SGB to get the controller
// state from the SNES via ICD2 registers written over the SNES cart bus.
// The serial interface overloads the 2b button interface to transfer
// 16B packets to the SNES. The SGB boot ROMs use this to transfer a
// portion of the GB header. GB games may also be customized to generate these
// packets for SGB-enhanced content.
//-------------------------------------------------------------------
// Clocks
//-------------------------------------------------------------------
// GB Crystal - 20.97152 MHz
// GB CPU Frequency - 4.194304 MHz
// GB Bus Frequency - 1.048576 MHz
// To approximate the SGB2 frequency the SD2SNES implements a 84 MHz
// base clock which may be further divided down. With a skip
// clock every 737 base clocks the effective base frequency is:
// 84 MHz * 736 / 737 = 83.886024 MHz
// With /20 the frequency is roughly .000024% slower than the original SGB2.
//
// The CPU implementation is pipelined into a fetch and execute stage.
// Each stage is multiple base clocks some of which may be idle to
// pad out to the equivalent SGB2 clock.
//
// The clock logic generates clock edge signals in the base clock
// domain.
//
// The SGB supports a /4, /5 (default), /7, and /9 clock. This is
// accounted for by adjusting the number of base clocks per CPU clock
// assertion.
reg [9:0] clk_skp_ctr_r; // in base domain
reg [5:0] clk_cpu_ctr_r; // in base domain
reg [2:0] clk_sys_r;
reg [3:0] clk_cpu_snes_ctr_r;
reg [1:0] clk_mult_r;
reg clk_cpu_edge_r;
wire [1:0] clk_mult;
// assert on 736
assign clk_skp_ast = clk_skp_ctr_r[9] & &clk_skp_ctr_r[7:5];
// check for 15, 19, 27, and 35 based on divisor
assign clk_cpu_ast = ( ~clk_skp_ast
& ( (~clk_mult_r[1] & ~clk_mult_r[0] & &clk_cpu_ctr_r[3:0] ) // 16-1
| (~clk_mult_r[1] & clk_mult_r[0] & &clk_cpu_ctr_r[4:4] & &clk_cpu_ctr_r[1:0]) // 20-1
| ( clk_mult_r[1] & ~clk_mult_r[0] & &clk_cpu_ctr_r[4:3] & &clk_cpu_ctr_r[1:0]) // 28-1
| ( clk_mult_r[1] & clk_mult_r[0] & &clk_cpu_ctr_r[5:5] & &clk_cpu_ctr_r[1:0]) // 36-1
)
);
wire clk_sysclk_edge = (clk_sys_r[2:1] == 2'b01);
assign clk_cpu_snes_ast = ( clk_sysclk_edge
& ( (~clk_mult_r[1] & ~clk_mult_r[0] & &clk_cpu_snes_ctr_r[1:0]) // 4-1
| (~clk_mult_r[1] & clk_mult_r[0] & &clk_cpu_snes_ctr_r[2:2]) // 5-1
| ( clk_mult_r[1] & ~clk_mult_r[0] & &clk_cpu_snes_ctr_r[2:1]) // 7-1
| ( clk_mult_r[1] & clk_mult_r[0] & &clk_cpu_snes_ctr_r[3:3]) // 9-1
)
);
assign CLK_CPU_EDGE = clk_cpu_edge_r;
always @(posedge CLK) begin
if (RST) begin
clk_skp_ctr_r <= 0;
clk_cpu_ctr_r <= 0;
clk_sys_r <= 0;
clk_cpu_snes_ctr_r <= 0;
end
else begin
clk_skp_ctr_r <= clk_skp_ast ? 0 : clk_skp_ctr_r + 1;
// The CPU clock absorbs the skip clock since it's the primary that feeds all GB logic
clk_cpu_ctr_r <= clk_skp_ast ? clk_cpu_ctr_r : (clk_cpu_ast ? 0 : (clk_cpu_ctr_r + 1));
clk_sys_r <= {clk_sys_r[1:0], CLK_SYSCLK};
clk_cpu_snes_ctr_r <= ~clk_sysclk_edge ? clk_cpu_snes_ctr_r : (clk_cpu_snes_ast ? 0 : clk_cpu_snes_ctr_r + 1);
// arbitrary point assigned to define edge for cpu clock
clk_cpu_edge_r <= FEAT[`SGB_FEAT_SGB1_TIMING] ? clk_cpu_snes_ast : clk_cpu_ast;
end
end
// Generate a BUS clock edge from the incoming CPU clock edge. The
// BUS clock is always /4.
reg [1:0] clk_bus_ctr_r; always @(posedge CLK) clk_bus_ctr_r <= RST ? 0 : clk_bus_ctr_r + (CLK_CPU_EDGE ? 1 : 0);
wire CLK_BUS_EDGE = CLK_CPU_EDGE & &clk_bus_ctr_r;
// synchronize on bus edge
always @(posedge CLK) if (RST | CLK_BUS_EDGE) clk_mult_r <= clk_mult;
// Add a delay on cold reset since the SNES has to win the race to capture the buffer. Do we need this for CPU reset, too?
reg [15:0] rst_cnt_r;
always @(posedge CLK) if (RST) rst_cnt_r <= -1; else if (CLK_BUS_EDGE & |rst_cnt_r) rst_cnt_r <= rst_cnt_r - 1;
// Synchronize reset to bus edge. Want a full bus clock prior to first edge assertion
reg cpu_ireset_r; always @(posedge CLK) cpu_ireset_r <= RST | CPU_RST | (cpu_ireset_r & ~CLK_BUS_EDGE) | |rst_cnt_r;
//-------------------------------------------------------------------
// Row Buffers
//-------------------------------------------------------------------
`define ROW_CNT 4
wire row_wren[`ROW_CNT-1:0];
wire [8:0] row_address[`ROW_CNT-1:0];
//wire [7:0] row_rddata[`ROW_CNT-1:0];
wire [7:0] row_wrdata[`ROW_CNT-1:0];
//wire icd_row_wren[`ROW_CNT-1:0];
wire [8:0] icd_row_address[`ROW_CNT-1:0];
wire [7:0] icd_row_rddata[`ROW_CNT-1:0];
//wire [7:0] icd_row_wrdata[`ROW_CNT-1:0];
`ifdef MK2
row_buf row0 (
.clka(CLK), // input clka
.wea(row_wren[0]), // input [0 : 0] wea
.addra(row_address[0]), // input [8 : 0] addra
.dina(row_wrdata[0]), // input [7 : 0] dina
//.douta(row_rddata[0]), // output [7 : 0] douta
.clkb(CLK), // input clkb
//.web(icd_row_wren[0]), // input [0 : 0] web
.addrb(icd_row_address[0]), // input [12 : 0] addrb
//.dinb(icd_row_wrdata[0]), // input [7 : 0] dinb
.doutb(icd_row_rddata[0]) // output [7 : 0] doutb
);
row_buf row1 (
.clka(CLK), // input clka
.wea(row_wren[1]), // input [0 : 0] wea
.addra(row_address[1]), // input [8 : 0] addra
.dina(row_wrdata[1]), // input [7 : 0] dina
//.douta(row_rddata[1]), // output [7 : 0] douta
.clkb(CLK), // input clkb
//.web(icd_row_wren[1]), // input [0 : 0] web
.addrb(icd_row_address[1]), // input [12 : 0] addrb
//.dinb(icd_row_wrdata[1]), // input [7 : 0] dinb
.doutb(icd_row_rddata[1]) // output [7 : 0] doutb
);
row_buf row2 (
.clka(CLK), // input clka
.wea(row_wren[2]), // input [0 : 0] wea
.addra(row_address[2]), // input [8 : 0] addra
.dina(row_wrdata[2]), // input [7 : 0] dina
//.douta(row_rddata[2]), // output [7 : 0] douta
.clkb(CLK), // input clkb
//.web(icd_row_wren[2]), // input [0 : 0] web
.addrb(icd_row_address[2]), // input [12 : 0] addrb
//.dinb(icd_row_wrdata[2]), // input [7 : 0] dinb
.doutb(icd_row_rddata[2]) // output [7 : 0] doutb
);
row_buf row3 (
.clka(CLK), // input clka
.wea(row_wren[3]), // input [0 : 0] wea
.addra(row_address[3]), // input [8 : 0] addra
.dina(row_wrdata[3]), // input [7 : 0] dina
//.douta(row_rddata[3]), // output [7 : 0] douta
.clkb(CLK), // input clkb
//.web(icd_row_wren[3]), // input [0 : 0] web
.addrb(icd_row_address[3]), // input [12 : 0] addrb
//.dinb(icd_row_wrdata[3]), // input [7 : 0] dinb
.doutb(icd_row_rddata[3]) // output [7 : 0] doutb
);
`endif
`ifdef MK3
row_buf row0 (
.clock(CLK), // input clka
.wren(row_wren[0]), // input [0 : 0] wea
.wraddress(row_address[0]), // input [8 : 0] addra
.data(row_wrdata[0]), // input [7 : 0] dina
//.q_a(row_rddata[0]), // output [7 : 0] douta
//.wren_b(icd_row_wren[0]), // input [0 : 0] web
.rdaddress(icd_row_address[0]), // input [12 : 0] addrb
//.data_b(icd_row_wrdata[0]), // input [7 : 0] dinb
.q(icd_row_rddata[0]) // output [7 : 0] doutb
);
row_buf row1 (
.clock(CLK), // input clka
.wren(row_wren[1]), // input [0 : 0] wea
.wraddress(row_address[1]), // input [8 : 0] addra
.data(row_wrdata[1]), // input [7 : 0] dina
//.q_a(row_rddata[1]), // output [7 : 0] douta
//.wren_b(icd_row_wren[1]), // input [0 : 0] web
.rdaddress(icd_row_address[1]), // input [12 : 0] addrb
//.data_b(icd_row_wrdata[1]), // input [7 : 0] dinb
.q(icd_row_rddata[1]) // output [7 : 0] doutb
);
row_buf row2 (
.clock(CLK), // input clka
.wren(row_wren[2]), // input [0 : 0] wea
.wraddress(row_address[2]), // input [8 : 0] addra
.data(row_wrdata[2]), // input [7 : 0] dina
//.q_a(row_rddata[2]), // output [7 : 0] douta
//.wren_b(icd_row_wren[2]), // input [0 : 0] web
.rdaddress(icd_row_address[2]), // input [12 : 0] addrb
//.data_b(icd_row_wrdata[2]), // input [7 : 0] dinb
.q(icd_row_rddata[2]) // output [7 : 0] doutb
);
row_buf row3 (
.clock(CLK), // input clka
.wren(row_wren[3]), // input [0 : 0] wea
.wraddress(row_address[3]), // input [8 : 0] addra
.data(row_wrdata[3]), // input [7 : 0] dina
//.q_a(row_rddata[3]), // output [7 : 0] douta
//.wren_b(icd_row_wren[3]), // input [0 : 0] web
.rdaddress(icd_row_address[3]), // input [12 : 0] addrb
//.data_b(icd_row_wrdata[3]), // input [7 : 0] dinb
.q(icd_row_rddata[3]) // output [7 : 0] doutb
);
`endif
//-------------------------------------------------------------------
// REG
//-------------------------------------------------------------------
`define PKT_CNT 16
`define LCDC_ROW_INDEX 1:0
`define LCDC_CHAR_ROW 7:3
reg [7:0] REG_LCDCHW_r; // 6000 R
reg [7:0] REG_LCDCHR_r; // 6001 W
reg [7:0] REG_PKTRDY_r; // 6002 R
reg [7:0] REG_CTL_r; // 6003 W
reg [7:0] REG_PAD_r[3:0]; // 6004-6007 W
reg [7:0] REG_VER_r; // 600F R
reg [7:0] REG_PKT_r[`PKT_CNT-1:0];// 7000-700F R
reg [7:0] REG_CHDAT_r; // 7800 R
reg [7:0] reg_mdr_r;
reg [8:0] reg_row_index_read_r;
reg reg_pktrdy_clear_r;
assign DATA_OUT = reg_mdr_r;
assign CPU_RST = ~REG_CTL_r[7];
assign clk_mult = REG_CTL_r[1:0];
always @(posedge CLK) begin
if (cpu_ireset_r) begin
REG_LCDCHR_r <= 0; // 6001 W
//REG_CTL_R <= 8'h01;
for (i = 0; i < 4; i = i + 1) REG_PAD_r[i] <= 8'hFF; // 6004-6007 W
REG_VER_r <= 8'h61; // 600F R
REG_CHDAT_r <= 0; // 7800-780F R
reg_row_index_read_r <= 0;
reg_pktrdy_clear_r <= 0;
end
else begin
// It's important to flop the data early in the SNES read cycle so that concurrent
// writes don't cause late changes on the bus which will lead to errors in the SNES.
case (REG_CTL_r[5:4]) // 1(0),2(1),4(3) players enabled. 0 out if not enabled to avoid spurious presses
0: begin REG_PAD_r[1] <= 8'hFF; REG_PAD_r[2] <= 8'hFF; REG_PAD_r[3] <= 8'hFF; end
1: begin REG_PAD_r[2] <= 8'hFF; REG_PAD_r[3] <= 8'hFF; end
endcase
reg_pktrdy_clear_r <= 0;
casez ({SNES_ADDR[22],SNES_ADDR[15:11],7'h00,SNES_ADDR[3:0]})
{1'b0,16'h6000}: if (SNES_RD_start) reg_mdr_r <= REG_LCDCHW_r; // R
{1'b0,16'h6001}: begin
if (SNES_WR_end) begin
REG_LCDCHR_r[`LCDC_ROW_INDEX] <= DATA_IN[`LCDC_ROW_INDEX]; // W
reg_row_index_read_r <= 0;
end
end
{1'b0,16'h6002}: if (SNES_RD_start) reg_mdr_r <= REG_PKTRDY_r; // R
//{1'b0,16'h6003}: if (SNES_WR_end) {REG_CTL_r[7],REG_CTL_r[5:4],REG_CTL_r[1:0]} <= {DATA_IN[7],DATA_IN[5:4],DATA_IN[1:0]}; // W
{1'b0,16'h6004}: if (SNES_WR_end) REG_PAD_r[0] <= DATA_IN; // W
{1'b0,16'h6005}: if (SNES_WR_end) REG_PAD_r[1] <= DATA_IN; // W
{1'b0,16'h6006}: if (SNES_WR_end) REG_PAD_r[2] <= DATA_IN; // W
{1'b0,16'h6007}: if (SNES_WR_end) REG_PAD_r[3] <= DATA_IN; // W
{1'b0,16'h600F}: if (SNES_RD_start) reg_mdr_r <= REG_VER_r; // R
{1'b0,16'h700?}: begin
if (SNES_RD_start) begin
reg_mdr_r <= REG_PKT_r[SNES_ADDR[3:0]];
// pulse PKTRDY clear
if (SNES_ADDR[3:0] == 0) reg_pktrdy_clear_r <= 1;
end
end
{1'b0,16'h7800}: begin
if (SNES_RD_start) begin
reg_mdr_r <= REG_CHDAT_r; // R
reg_row_index_read_r <= reg_row_index_read_r + 1;
end
end
endcase
REG_CHDAT_r <= icd_row_rddata[REG_LCDCHR_r[`LCDC_ROW_INDEX]];
end
// COLD reset forces a complete reinit. Otherwise this register is not affected by a WARM (CPU) reset.
REG_CTL_r <= ( RST ? 8'h01
: ({SNES_ADDR[22],SNES_ADDR[15:11],7'h00,SNES_ADDR[3:0]} == {1'b0,16'h6003} && SNES_WR_end) ? {DATA_IN[7],1'b0,DATA_IN[5:4],2'h0,DATA_IN[1:0]}
: REG_CTL_r
);
end
//-------------------------------------------------------------------
// PIXELS
//-------------------------------------------------------------------
reg [8:0] pix_row_index_r;
reg [2:0] pix_index_r;
reg [7:0] pix_data_r[1:0];
reg [1:0] pix_row_write_r;
reg [8:0] pix_row_index_write_r;
assign row_address[0] = {pix_row_index_write_r[8:1],pix_row_write_r[1]};
assign row_address[1] = {pix_row_index_write_r[8:1],pix_row_write_r[1]};
assign row_address[2] = {pix_row_index_write_r[8:1],pix_row_write_r[1]};
assign row_address[3] = {pix_row_index_write_r[8:1],pix_row_write_r[1]};
assign row_wrdata[0] = pix_data_r[pix_row_write_r[1]];
assign row_wrdata[1] = pix_data_r[pix_row_write_r[1]];
assign row_wrdata[2] = pix_data_r[pix_row_write_r[1]];
assign row_wrdata[3] = pix_data_r[pix_row_write_r[1]];
assign row_wren[0] = (REG_LCDCHW_r[`LCDC_ROW_INDEX] == 0) ? |pix_row_write_r : 0;
assign row_wren[1] = (REG_LCDCHW_r[`LCDC_ROW_INDEX] == 1) ? |pix_row_write_r : 0;
assign row_wren[2] = (REG_LCDCHW_r[`LCDC_ROW_INDEX] == 2) ? |pix_row_write_r : 0;
assign row_wren[3] = (REG_LCDCHW_r[`LCDC_ROW_INDEX] == 3) ? |pix_row_write_r : 0;
assign icd_row_address[0] = reg_row_index_read_r;
assign icd_row_address[1] = reg_row_index_read_r;
assign icd_row_address[2] = reg_row_index_read_r;
assign icd_row_address[3] = reg_row_index_read_r;
always @(posedge CLK) begin
if (cpu_ireset_r) begin
REG_LCDCHW_r <= 0;
pix_row_index_r <= 0;
pix_index_r <= 0;
pix_row_write_r <= 0;
end
else begin
pix_row_write_r <= {pix_row_write_r[0],1'b0};
if (PPU_DOT_EDGE) begin
if (PPU_PIXEL_VALID) begin
pix_index_r <= pix_index_r + 1;
// pack pixels into 2bpp planar format
{pix_data_r[1][~pix_index_r[2:0]],pix_data_r[0][~pix_index_r[2:0]]} <= PPU_PIXEL;
if (&pix_index_r) begin
pix_row_index_r[8:4] <= pix_row_index_r[8:4] + 1;
pix_row_write_r[0] <= 1;
pix_row_index_write_r <= pix_row_index_r;
end
end
else if (PPU_VSYNC_EDGE) begin
pix_row_index_r[8:4] <= 0;
pix_index_r <= 0;
REG_LCDCHW_r[`LCDC_CHAR_ROW] <= 0;
end
// early advance of line and row buffer write pointer on dot after 2b pixel 159
// fixes occasional flashing line 120 on BMGB (SGB + 4 controllers)
else if (pix_row_index_r[8] & pix_row_index_r[6]/*PPU_HSYNC_EDGE*/) begin
if (~REG_LCDCHW_r[7] | ~REG_LCDCHW_r[4]) begin
pix_row_index_r[3:1] <= pix_row_index_r[3:1] + 1;
pix_row_index_r[8:4] <= 0;
if (pix_row_index_r[3:1] == 3'h7) begin
REG_LCDCHW_r[`LCDC_ROW_INDEX] <= REG_LCDCHW_r[`LCDC_ROW_INDEX] + 1;
REG_LCDCHW_r[`LCDC_CHAR_ROW] <= REG_LCDCHW_r[`LCDC_CHAR_ROW] + 1;
end
end
end
end
end
end
//-------------------------------------------------------------------
// BUTTON/SERIAL
//-------------------------------------------------------------------
parameter
ST_BTN_IDLE = 4'b0001,
ST_BTN_RECV = 4'b0010,
ST_BTN_WAIT = 4'b0100,
ST_BTN_END = 4'b1000;
reg [3:0] btn_state_r;
reg [3:0] btn_state_next_r;
reg [1:0] btn_prev_r;
reg [1:0] btn_curr_id_r;
reg [6:0] btn_bit_pos_r;
reg btn_pktrdy_set_r;
// Output assignment is:
// IDLE P1I = 11 -> ~CurId (0=F,1=E,2=D,3=C)
// IDLE P1I = 01 -> ~Btn[7:4][CurID] // buttons
// IDLE P1I = 10 -> ~Btn[3:0][CurID] // d-pad
//
// IDLE P1I = 01 -> 10 or 11 -> Increment ID mod NumPad
assign P1O = &P1I ? ~{2'h0,btn_curr_id_r} : (({4{P1I[1]}} | REG_PAD_r[btn_curr_id_r][7:4]) & ({4{P1I[0]}} | REG_PAD_r[btn_curr_id_r][3:0]));
assign IDL = |(btn_state_r & ST_BTN_IDLE) | (|(btn_state_r & ST_BTN_WAIT) & ~|btn_bit_pos_r);
always @(posedge CLK) begin
if (cpu_ireset_r) begin
REG_PKTRDY_r <= 0;
for (i = 0; i < `PKT_CNT; i = i + 1) REG_PKT_r[i] <= 0;
btn_state_r <= ST_BTN_IDLE;
btn_prev_r <= 2'b00;
btn_curr_id_r <= 0;
btn_pktrdy_set_r <= 0;
end
else begin
btn_pktrdy_set_r <= 0;
if (CLK_CPU_EDGE) begin
btn_prev_r <= P1I;
if (P1I != btn_prev_r) begin
if (~|P1I & (BOOTROM_ACTIVE | ~FEAT[`SGB_FEAT_ENH_OVERRIDE])) begin
// *->00 from any state causes us to go to serial transfer mode
// Is this true if we are already in serial transfer mode? Convenient to assume so.
btn_bit_pos_r <= 0;
btn_state_next_r <= ST_BTN_RECV;
btn_state_r <= ST_BTN_WAIT;
end
else begin
case (btn_state_r)
ST_BTN_IDLE: begin
if (~btn_prev_r[1] & P1I[1]) begin
// 01->(10|11) transition increments id
btn_curr_id_r <= (btn_curr_id_r + 1) & REG_CTL_r[5:4];
end
end
ST_BTN_RECV: begin
// 11 is considered a NOP
if (^P1I) begin
// Xilinx compiler silently fails to create logic if we use the following code:
// REG_PKT_r[btn_bit_pos_r[6:3]][btn_bit_pos_r[2:0]] <= P1I[0];
case (btn_bit_pos_r[6:3])
0: REG_PKT_r[0 ][btn_bit_pos_r[2:0]] <= P1I[0];
1: REG_PKT_r[1 ][btn_bit_pos_r[2:0]] <= P1I[0];
2: REG_PKT_r[2 ][btn_bit_pos_r[2:0]] <= P1I[0];
3: REG_PKT_r[3 ][btn_bit_pos_r[2:0]] <= P1I[0];
4: REG_PKT_r[4 ][btn_bit_pos_r[2:0]] <= P1I[0];
5: REG_PKT_r[5 ][btn_bit_pos_r[2:0]] <= P1I[0];
6: REG_PKT_r[6 ][btn_bit_pos_r[2:0]] <= P1I[0];
7: REG_PKT_r[7 ][btn_bit_pos_r[2:0]] <= P1I[0];
8: REG_PKT_r[8 ][btn_bit_pos_r[2:0]] <= P1I[0];
9: REG_PKT_r[9 ][btn_bit_pos_r[2:0]] <= P1I[0];
10: REG_PKT_r[10][btn_bit_pos_r[2:0]] <= P1I[0];
11: REG_PKT_r[11][btn_bit_pos_r[2:0]] <= P1I[0];
12: REG_PKT_r[12][btn_bit_pos_r[2:0]] <= P1I[0];
13: REG_PKT_r[13][btn_bit_pos_r[2:0]] <= P1I[0];
14: REG_PKT_r[14][btn_bit_pos_r[2:0]] <= P1I[0];
15: REG_PKT_r[15][btn_bit_pos_r[2:0]] <= P1I[0];
endcase
btn_bit_pos_r <= btn_bit_pos_r + 1;
btn_state_next_r <= &btn_bit_pos_r ? ST_BTN_WAIT : ST_BTN_RECV;
btn_state_r <= ST_BTN_WAIT;
end
end
ST_BTN_WAIT: begin
// 11 transition unless we are looping WAIT->WAIT->IDLE on 10 (TERM).
if (P1I == {1'b1,~|(btn_state_next_r & ST_BTN_IDLE)}) begin
// set packet ready if we are successfully transitioning to idle
btn_pktrdy_set_r <= |(btn_state_next_r & ST_BTN_IDLE);
btn_state_next_r <= ST_BTN_IDLE;
btn_state_r <= btn_state_next_r;
end
else if (^P1I) begin
// 10|01 are bad transitions when not waiting for terminating 10. 11 is NOP when we are waiting for 10.
// exiting rather than ignoring these states seems to fix a few games like Bonk's Adventure (hang at start) and Pokemon Gold (no background)
btn_state_r <= ST_BTN_IDLE;
end
end
endcase
end
end
end
REG_PKTRDY_r[0] <= (REG_PKTRDY_r[0] & ~reg_pktrdy_clear_r) | btn_pktrdy_set_r;
end
end
//-------------------------------------------------------------------
// DBG
//-------------------------------------------------------------------
`ifdef SGB_DEBUG
reg [7:0] dbg_data_r = 0;
assign DBG_DATA_OUT = dbg_data_r;
always @(posedge CLK) begin
if (~DBG_ADDR[11]) begin
casez(DBG_ADDR[7:0])
8'h00: dbg_data_r <= REG_LCDCHW_r;
8'h01: dbg_data_r <= REG_LCDCHR_r;
8'h02: dbg_data_r <= REG_PKTRDY_r;
8'h03: dbg_data_r <= REG_CTL_r;
8'h04: dbg_data_r <= REG_PAD_r[0];
8'h05: dbg_data_r <= REG_PAD_r[1];
8'h06: dbg_data_r <= REG_PAD_r[2];
8'h07: dbg_data_r <= REG_PAD_r[3];
8'h08: dbg_data_r <= REG_CHDAT_r;
8'h1?: dbg_data_r <= REG_PKT_r[DBG_ADDR[3:0]];
8'h20: dbg_data_r <= P1I;
8'h21: dbg_data_r <= P1O;
8'h22: dbg_data_r <= btn_state_r;
8'h23: dbg_data_r <= btn_prev_r;
8'h24: dbg_data_r <= btn_curr_id_r;
8'h25: dbg_data_r <= btn_bit_pos_r;
8'h30: dbg_data_r <= REG_LCDCHW_r[`LCDC_CHAR_ROW];
8'h31: dbg_data_r <= REG_LCDCHW_r[`LCDC_ROW_INDEX];
8'h32: dbg_data_r <= pix_row_index_write_r[7:0];
8'h33: dbg_data_r <= pix_row_index_write_r[8];
8'h34: dbg_data_r <= reg_row_index_read_r[7:0];
8'h35: dbg_data_r <= reg_row_index_read_r[8];
default: dbg_data_r <= 0;
endcase
end
end
`endif
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: rx_trn_data_fsm
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Receive TRN Data FSM. This module interfaces to the Block Plus RX
// TRN. It presents the 64-bit data from completer and and forwards that
// data with a data_valid signal. This block also decodes packet header info
// and forwards it to the rx_trn_monitor block.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module rx_trn_data_fsm(
input wire clk,
input wire rst,
// Rx Local-Link
input wire [63:0] trn_rd,
input wire [7:0] trn_rrem_n,
input wire trn_rsof_n,
input wire trn_reof_n,
input wire trn_rsrc_rdy_n,
input wire trn_rsrc_dsc_n,
output reg trn_rdst_rdy_n,
input wire trn_rerrfwd_n,
output wire trn_rnp_ok_n,
input wire [6:0] trn_rbar_hit_n,
input wire [11:0] trn_rfc_npd_av,
input wire [7:0] trn_rfc_nph_av,
input wire [11:0] trn_rfc_pd_av,
input wire [7:0] trn_rfc_ph_av,
input wire [11:0] trn_rfc_cpld_av,
input wire [7:0] trn_rfc_cplh_av,
output wire trn_rcpl_streaming_n,
//DATA FIFO SIGNALS
output reg [63:0] data_out,
output wire [7:0] data_out_be,
output reg data_valid,
input wire data_fifo_status,
//END DATA FIFO SIGNALS
//HEADER FIELD SIGNALS
//The following are registered from the header fields of the current packet
//See the PCIe Base Specification for definitions of these headers
output reg fourdw_n_threedw, //fourdw = 1'b1; 3dw = 1'b0;
output reg payload,
output reg [2:0] tc, //traffic class
output reg td, //digest
output reg ep, //poisoned bit
output reg [1:0] attr, //attribute field
output reg [9:0] dw_length, //DWORD Length
//the following fields are dependent on the type of TLP being received
//regs with MEM prefix are valid for memory TLPS and regs with CMP prefix
//are valid for completion TLPS
output reg [15:0] MEM_req_id, //requester ID for memory TLPs
output reg [7:0] MEM_tag, //tag for non-posted memory read request
output reg [15:0] CMP_comp_id, //completer id for completion TLPs
output reg [2:0]CMP_compl_stat, //status for completion TLPs
output reg CMP_bcm, //byte count modified field for completions TLPs
output reg [11:0] CMP_byte_count, //remaining byte count for completion TLPs
output reg [63:0] MEM_addr, //address field for memory TLPs
output reg [15:0] CMP_req_id, //requester if for completions TLPs
output reg [7:0] CMP_tag, //tag field for completion TLPs
output reg [6:0] CMP_lower_addr, //lower address field for completion TLPs
//decode of the format field
output wire MRd, //Mem read
output wire MWr, //Mem write
output wire CplD, //Completion w/ data
output wire Msg, //Message TLP
output wire UR, //Unsupported request TLP i.e. IO, CPL,etc..
output reg [6:0] bar_hit, //valid when a BAR is hit
output reg header_fields_valid//valid signal to qualify the above header fields
//END HEADER FIELD SIGNALS
);
//state machine states
localparam IDLE = 3'b000;
localparam NOT_READY = 3'b001;
localparam SOF = 3'b010;
localparam HEAD2 = 3'b011;
localparam BODY = 3'b100;
localparam EOF = 3'b101;
//additional pipelines regs for RX TRN interface
reg [63:0] trn_rd_d1;
reg [7:0] trn_rrem_d1_n;
reg trn_rsof_d1_n;
reg trn_reof_d1_n;
reg trn_rsrc_rdy_d1_n;
reg trn_rsrc_dsc_d1_n;
reg trn_rerrfwd_d1_n;
reg [6:0] trn_rbar_hit_d1_n;
reg [11:0] trn_rfc_npd_av_d1;
reg [7:0] trn_rfc_nph_av_d1;
reg [11:0] trn_rfc_pd_av_d1;
reg [7:0] trn_rfc_ph_av_d1;
reg [11:0] trn_rfc_cpld_av_d1;
reg [7:0] trn_rfc_cplh_av_d1;
//second pipeline
reg [63:0] trn_rd_d2;
reg [7:0] trn_rrem_d2_n;
reg trn_rsof_d2_n;
reg trn_reof_d2_n;
reg trn_rsrc_rdy_d2_n;
reg trn_rsrc_dsc_d2_n;
reg trn_rerrfwd_d2_n;
reg [6:0] trn_rbar_hit_d2_n;
reg [11:0] trn_rfc_npd_av_d2;
reg [7:0] trn_rfc_nph_av_d2;
reg [11:0] trn_rfc_pd_av_d2;
reg [7:0] trn_rfc_ph_av_d2;
reg [11:0] trn_rfc_cpld_av_d2;
reg [7:0] trn_rfc_cplh_av_d2;
reg [4:0] rx_packet_type;
reg [2:0] trn_state;
wire [63:0] data_out_mux;
wire [7:0] data_out_be_mux;
reg data_valid_early;
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
// TIE constant signals here
assign trn_rnp_ok_n = 1'b0;
assign trn_rcpl_streaming_n = 1'b0; //use completion streaming mode
//all the outputs of the endpoint should be pipelined
//to help meet required timing of an 8 lane design
always @ (posedge clk)
begin
trn_rd_d1[63:0] <= trn_rd[63:0] ;
trn_rrem_d1_n[7:0] <= trn_rrem_n[7:0] ;
trn_rsof_d1_n <= trn_rsof_n ;
trn_reof_d1_n <= trn_reof_n ;
trn_rsrc_rdy_d1_n <= trn_rsrc_rdy_n ;
trn_rsrc_dsc_d1_n <= trn_rsrc_dsc_n ;
trn_rerrfwd_d1_n <= trn_rerrfwd_n ;
trn_rbar_hit_d1_n[6:0] <= trn_rbar_hit_n[6:0] ;
trn_rfc_npd_av_d1[11:0] <= trn_rfc_npd_av[11:0] ;
trn_rfc_nph_av_d1[7:0] <= trn_rfc_nph_av[7:0] ;
trn_rfc_pd_av_d1[11:0] <= trn_rfc_pd_av[11:0] ;
trn_rfc_ph_av_d1[7:0] <= trn_rfc_ph_av[7:0] ;
trn_rfc_cpld_av_d1[11:0] <= trn_rfc_cpld_av[11:0];
trn_rfc_cplh_av_d1[7:0] <= trn_rfc_cplh_av[7:0] ;
trn_rd_d2[63:0] <= trn_rd_d1[63:0] ;
trn_rrem_d2_n[7:0] <= trn_rrem_d1_n[7:0] ;
trn_rsof_d2_n <= trn_rsof_d1_n ;
trn_reof_d2_n <= trn_reof_d1_n ;
trn_rsrc_rdy_d2_n <= trn_rsrc_rdy_d1_n ;
trn_rsrc_dsc_d2_n <= trn_rsrc_dsc_d1_n ;
trn_rerrfwd_d2_n <= trn_rerrfwd_d1_n ;
trn_rbar_hit_d2_n[6:0] <= trn_rbar_hit_d1_n[6:0] ;
trn_rfc_npd_av_d2[11:0] <= trn_rfc_npd_av_d1[11:0] ;
trn_rfc_nph_av_d2[7:0] <= trn_rfc_nph_av_d1[7:0] ;
trn_rfc_pd_av_d2[11:0] <= trn_rfc_pd_av_d1[11:0] ;
trn_rfc_ph_av_d2[7:0] <= trn_rfc_ph_av_d1[7:0] ;
trn_rfc_cpld_av_d2[11:0] <= trn_rfc_cpld_av_d1[11:0];
trn_rfc_cplh_av_d2[7:0] <= trn_rfc_cplh_av_d1[7:0] ;
end
assign rx_sof_d1 = ~trn_rsof_d1_n & ~trn_rsrc_rdy_d1_n;
// Assign packet type information about the current RX Packet
// rx_packet_type is decoded in always block directly below these assigns
assign MRd = rx_packet_type[4];
assign MWr = rx_packet_type[3];
assign CplD = rx_packet_type[2];
assign Msg = rx_packet_type[1];
assign UR = rx_packet_type[0];
//register the packet header fields and decode the packet type
//both memory and completion TLP header fields are registered for each
//received packet, however, only the fields for the incoming type will be
//valid
always@(posedge clk )
begin
if(rst_reg)begin
rx_packet_type[4:0] <= 5'b00000;
fourdw_n_threedw <= 0;
payload <= 0;
tc[2:0] <= 0; //traffic class
td <= 0; //digest
ep <= 0; //poisoned bit
attr[1:0] <= 0;
dw_length[9:0] <= 0;
MEM_req_id[15:0] <= 0;
MEM_tag[7:0] <= 0;
CMP_comp_id[15:0] <= 0;
CMP_compl_stat[2:0] <= 0;
CMP_bcm <= 0;
CMP_byte_count[11:0] <= 0;
end else begin
if(rx_sof_d1)begin
//these fields same for all TLPs
fourdw_n_threedw <= trn_rd_d1[61];
payload <= trn_rd_d1[62];
tc[2:0] <= trn_rd_d1[54:52]; //traffic class
td <= trn_rd_d1[47]; //digest
ep <= trn_rd_d1[46]; //poisoned bit
attr[1:0] <= trn_rd_d1[45:44];
dw_length[9:0] <= trn_rd_d1[41:32];
//also latch bar_hit
bar_hit[6:0] <= ~trn_rbar_hit_d1_n[6:0];
//these following fields dependent on packet type
//i.e. memory packet fields are only valid for mem packet types
//and completer packet fields are only valid for completer packet type;
//memory packet fields
MEM_req_id[15:0] <= trn_rd_d1[31:16];
MEM_tag[7:0] <= trn_rd_d1[15:8];
//first and last byte enables not needed because plus core delivers
//completer packet fields
CMP_comp_id[15:0] <= trn_rd_d1[31:16];
CMP_compl_stat[2:0] <= trn_rd_d1[15:13];
CMP_bcm <= trn_rd_d1[12];
CMP_byte_count[11:0] <= trn_rd_d1[11:0];
//add message fields here if needed
//decode the packet type and register in rx_packet_type
casex({trn_rd_d1[62],trn_rd_d1[60:56]})
6'b000000: begin //mem read
rx_packet_type[4:0] <= 5'b10000;
end
6'b100000: begin //mem write
rx_packet_type[4:0] <= 5'b01000;
end
6'b101010: begin //completer with data
rx_packet_type[4:0] <= 5'b00100;
end
6'bx10xxx: begin //message
rx_packet_type[4:0] <= 5'b00010;
end
default: begin //all other packet types are unsupported for this design
rx_packet_type[4:0] <= 5'b00001;
end
endcase
end
end
end
// Now do the same for the second header of the current packet
always@(posedge clk )begin
if(rst_reg)begin
MEM_addr[63:0] <= 0;
CMP_req_id[15:0] <= 0;
CMP_tag[7:0] <= 0;
CMP_lower_addr[6:0] <= 0;
end else begin
if(trn_state == SOF & ~trn_rsrc_rdy_d1_n)begin //packet is in process of
//reading out second header
if(fourdw_n_threedw)
MEM_addr[63:0] <= trn_rd_d1[63:0];
else
MEM_addr[63:0] <= {32'h00000000,trn_rd_d1[63:32]};
CMP_req_id[15:0] <= trn_rd_d1[63:48];
CMP_tag[7:0] <= trn_rd_d1[47:40];
CMP_lower_addr[6:0] <= trn_rd_d1[48:32];
end
end
end
// generate a valid signal for the headers field
always@(posedge clk)begin
if(rst_reg)
header_fields_valid <= 0;
else
header_fields_valid <= ~trn_rsrc_rdy_d2_n & trn_rsof_d1_n;
end
//This state machine keeps track of what state the RX TRN interface
//is currently in
always @ (posedge clk )
begin
if(rst_reg)
begin
trn_state <= IDLE;
trn_rdst_rdy_n <= 1'b0;
end
else
begin
case(trn_state)
IDLE: begin
trn_rdst_rdy_n <= 1'b0;
if(rx_sof_d1)
trn_state <= SOF;
else
trn_state <= IDLE;
end
/// Jiansong: notice, completion streaming here
NOT_READY: begin // This state is a placeholder only - it is currently not
// entered from any other state
// This state could be used for throttling the PCIe
// Endpoint Block Plus RX TRN interface, however, this
// should not be done when using completion streaming
// mode as this reference design does
trn_rdst_rdy_n <= 1'b1;
trn_state <= IDLE;
end
SOF: begin
if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= EOF;
else if(trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= HEAD2;
else
trn_state <= SOF;
end
HEAD2: begin
if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= EOF;
else if(trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= BODY;
else
trn_state <= HEAD2;
end
BODY: begin
if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= EOF;
else
trn_state <= BODY;
end
EOF: begin
if(~trn_rsof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= SOF;
else if(trn_rsof_d1_n & trn_rsrc_rdy_d1_n)
trn_state <= IDLE;
else if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= EOF;
else
trn_state <= IDLE;
end
default: begin
trn_state <= IDLE;
end
endcase
end
end
//data shifter logic
//need to shift the data depending if we receive a four DWORD or three DWORD
//TLP type - Note that completion packets will always be 3DW TLPs
assign data_out_mux[63:0] = (fourdw_n_threedw)
? trn_rd_d2[63:0]
: {trn_rd_d2[31:0],trn_rd_d1[63:32]};
/// Jiansong: notice, why? 64bit data? likely should be modified
//swap the byte ordering to little endian
//e.g. data_out = B7,B6,B5,B4,B3,B2,B1,B0
always@(posedge clk)
data_out[63:0] <= {data_out_mux[7:0],data_out_mux[15:8],
data_out_mux[23:16],data_out_mux[31:24],
data_out_mux[39:32],data_out_mux[47:40],
data_out_mux[55:48],data_out_mux[63:56]};
//Data byte enable logic:
//Need to add byte enable logic for incoming memory transactions if desired
//to allow memory transaction granularity smaller than DWORD.
//
//This design always requests data on 128 byte boundaries so for
//completion TLPs the byte enables would always be asserted
//
//Note that the endpoint block plus uses negative logic, however,
//I decided to use positive logic for the user application.
assign data_out_be = 8'hff;
//data_valid generation logic
//Generally, data_valid should be asserted the same amount of cycles
//that trn_rsrc_rdy_n is asserted (minus the cycles that sof and
//eof are asserted).
//There are two exceptions to this:
// - 3DW TLPs with odd number of DW without Digest
// In this case an extra cycle is required
// - eof is used to generate this extra cycle
// - 4DW TLPs with even number of DW with Digest
// In this case an extra cycle needs to be removed
// - the last cycle is removed
// Jiansong: fix Mrd data to fifo bug
always@(*)begin
case({fourdw_n_threedw, dw_length[0], td})
3'b010: data_valid_early = ~trn_rsrc_rdy_d2_n
& trn_rsof_d2_n
& ~trn_reof_d2_n
& payload;
3'b101: data_valid_early = ~trn_rsrc_rdy_d2_n
& trn_reof_d1_n
& payload;
default: data_valid_early = ~trn_rsrc_rdy_d2_n
& trn_rsof_d2_n
& trn_reof_d2_n
& payload;
endcase
end
//delay by one clock to match data_out (and presumably data_out_be)
always@(posedge clk)
if(rst_reg)
data_valid <= 1'b0;
else
data_valid <= data_valid_early;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`include "verilated.v"
module t;
`verilator_file_descriptor file;
integer chars;
reg [1*8:1] letterl;
reg [8*8:1] letterq;
reg [16*8:1] letterw;
reg [16*8:1] letterz;
real r;
string s;
reg [7:0] v_a,v_b,v_c,v_d;
reg [31:0] v_worda;
reg [31:0] v_wordb;
`ifdef TEST_VERBOSE
`define verbose 1'b1
`else
`define verbose 1'b0
`endif
initial begin
// Display formatting
`ifdef verilator
if (file != 0) $stop;
$fwrite(file, "Never printed, file closed\n");
if (!$feof(file)) $stop;
`endif
`ifdef AUTOFLUSH
// The "w" is required so we get a FD not a MFD
file = $fopen("obj_dir/t_sys_file_autoflush/t_sys_file_autoflush.log","w");
`else
// The "w" is required so we get a FD not a MFD
file = $fopen("obj_dir/t_sys_file_basic/t_sys_file_basic_test.log","w");
`endif
if ($feof(file)) $stop;
$fdisplay(file, "[%0t] hello v=%x", $time, 32'h12345667);
$fwrite(file, "[%0t] %s\n", $time, "Hello2");
$fflush(file);
$fclose(file);
`ifdef verilator
if (file != 0) $stop(1); // Also test arguments to stop
$fwrite(file, "Never printed, file closed\n");
`endif
begin
// Check for opening errors
// The "r" is required so we get a FD not a MFD
file = $fopen("obj_dir/t_sys_file_basic/DOES_NOT_EXIST","r");
if (|file) $stop; // Should not exist, IE must return 0
end
begin
// Check quadword access; a little strange, but it's legal to open "."
file = $fopen(".","r");
$fclose(file);
end
begin
// Check read functions w/string
s = "t/t_sys_file_basic_input.dat";
file = $fopen(s,"r");
if ($feof(file)) $stop;
$fclose(file);
end
begin
// Check read functions
file = $fopen("t/t_sys_file_basic_input.dat","r");
if ($feof(file)) $stop;
// $fgetc
if ($fgetc(file) != "h") $stop;
if ($fgetc(file) != "i") $stop;
if ($fgetc(file) != "\n") $stop;
// $fgets
chars = $fgets(letterl, file);
if (`verbose) $write("c=%0d l=%s\n", chars, letterl);
if (chars != 1) $stop;
if (letterl != "l") $stop;
chars = $fgets(letterq, file);
if (`verbose) $write("c=%0d q=%x=%s", chars, letterq, letterq); // Output includes newline
if (chars != 5) $stop;
if (letterq != "\0\0\0quad\n") $stop;
letterw = "5432109876543210";
chars = $fgets(letterw, file);
if (`verbose) $write("c=%0d w=%s", chars, letterw); // Output includes newline
if (chars != 10) $stop;
if (letterw != "\0\0\0\0\0\0widestuff\n") $stop;
// $sscanf
if ($sscanf("x","")!=0) $stop;
if ($sscanf("z","z")!=0) $stop;
chars = $sscanf("blabcdefghijklmnop",
"%s", letterq);
if (`verbose) $write("c=%0d sa=%s\n", chars, letterq);
if (chars != 1) $stop;
if (letterq != "ijklmnop") $stop;
chars = $sscanf("xa=1f xb=12898971238912389712783490823_237904689_02348923",
"xa=%x xb=%x", letterq, letterw);
if (`verbose) $write("c=%0d xa=%x xb=%x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h1f) $stop;
if (letterw != 128'h38971278349082323790468902348923) $stop;
chars = $sscanf("ba=10 bb=110100101010010101012 note_the_two ",
"ba=%b bb=%b%s", letterq, letterw, letterz);
if (`verbose) $write("c=%0d xa=%x xb=%x z=%0s\n", chars, letterq, letterw, letterz);
if (chars != 3) $stop;
if (letterq != 64'h2) $stop;
if (letterw != 128'hd2a55) $stop;
if (letterz != {"\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0","2"}) $stop;
chars = $sscanf("oa=23 ob=125634123615234123681236",
"oa=%o ob=%o", letterq, letterw);
if (`verbose) $write("c=%0d oa=%x ob=%x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h13) $stop;
if (letterw != 128'h55ce14f1a9c29e) $stop;
chars = $sscanf("r=0.1 d=-236123",
"r=%g d=%d", r, letterq);
if (`verbose) $write("c=%0d d=%d\n", chars, letterq);
if (chars != 2) $stop;
if (r != 0.1) $stop;
if (letterq != 64'hfffffffffffc65a5) $stop;
s = "r=0.2 d=-236124";
chars = $sscanf(s, "r=%g d=%d", r, letterq);
if (`verbose) $write("c=%0d d=%d\n", chars, letterq);
if (chars != 2) $stop;
if (r != 0.2) $stop;
if (letterq != 64'hfffffffffffc65a4) $stop;
// $fscanf
if ($fscanf(file,"")!=0) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "xa=%x xb=%x", letterq, letterw);
if (`verbose) $write("c=%0d xa=%0x xb=%0x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h1f) $stop;
if (letterw != 128'h23790468902348923) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "ba=%b bb=%b %s", letterq, letterw, letterz);
if (`verbose) $write("c=%0d ba=%0x bb=%0x z=%0s\n", chars, letterq, letterw, letterz);
if (chars != 3) $stop;
if (letterq != 64'h2) $stop;
if (letterw != 128'hd2a55) $stop;
if (letterz != "\0\0\0\0note_the_two") $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "oa=%o ob=%o", letterq, letterw);
if (`verbose) $write("c=%0d oa=%0x ob=%0x\n", chars, letterq, letterw);
if (chars != 2) $stop;
if (letterq != 64'h13) $stop;
if (letterw != 128'h1573) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "d=%d", letterq);
if (`verbose) $write("c=%0d d=%0x\n", chars, letterq);
if (chars != 1) $stop;
if (letterq != 64'hfffffffffffc65a5) $stop;
if (!sync("\n")) $stop;
if (!sync("*")) $stop;
chars = $fscanf(file, "%c%s", letterl, letterw);
if (`verbose) $write("c=%0d q=%c s=%s\n", chars, letterl, letterw);
if (chars != 2) $stop;
if (letterl != "f") $stop;
if (letterw != "\0\0\0\0\0redfishblah") $stop;
chars = $fscanf(file, "%c", letterl);
if (`verbose) $write("c=%0d l=%x\n", chars, letterl);
if (chars != 1) $stop;
if (letterl != "\n") $stop;
// msg1229
v_a = $fgetc(file);
v_b = $fgetc(file);
v_c = $fgetc(file);
v_d = $fgetc(file);
v_worda = { v_d, v_c, v_b, v_a };
if (v_worda != "4321") $stop;
v_wordb[7:0] = $fgetc(file);
v_wordb[15:8] = $fgetc(file);
v_wordb[23:16] = $fgetc(file);
v_wordb[31:24] = $fgetc(file);
if (v_wordb != "9876") $stop;
if ($fgetc(file) != "\n") $stop;
$fclose(file);
end
$write("*-* All Finished *-*\n");
$finish(0); // Test arguments to finish
end
function sync;
input [7:0] cexp;
reg [7:0] cgot;
begin
cgot = $fgetc(file);
if (`verbose) $write("sync=%x='%c'\n", cgot,cgot);
sync = (cgot == cexp);
end
endfunction
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module tx_chain_hb
(input clock,
input reset,
input enable,
input wire [7:0] interp_rate,
input sample_strobe,
input interpolator_strobe,
input hb_strobe,
input wire [31:0] freq,
input wire [15:0] i_in,
input wire [15:0] q_in,
output wire [15:0] i_out,
output wire [15:0] q_out,
output wire [15:0] debug, output [15:0] hb_i_out
);
assign debug[15:13] = {sample_strobe,hb_strobe,interpolator_strobe};
wire [15:0] bb_i, bb_q;
wire [15:0] hb_i_out, hb_q_out;
halfband_interp hb
(.clock(clock),.reset(reset),.enable(enable),
.strobe_in(interpolator_strobe),.strobe_out(hb_strobe),
.signal_in_i(i_in),.signal_in_q(q_in),
.signal_out_i(hb_i_out),.signal_out_q(hb_q_out),
.debug(debug[12:0]));
cic_interp cic_interp_i
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_i_out),.signal_out(bb_i) );
cic_interp cic_interp_q
( .clock(clock),.reset(reset),.enable(enable),
.rate(interp_rate),.strobe_in(hb_strobe),.strobe_out(sample_strobe),
.signal_in(hb_q_out),.signal_out(bb_q) );
`define NOCORDIC_TX
`ifdef NOCORDIC_TX
assign i_out = bb_i;
assign q_out = bb_q;
`else
wire [31:0] phase;
phase_acc phase_acc_tx
(.clk(clock),.reset(reset),.enable(enable),
.strobe(sample_strobe),.freq(freq),.phase(phase) );
cordic tx_cordic_0
( .clock(clock),.reset(reset),.enable(sample_strobe),
.xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
.xo(i_out),.yo(q_out),.zo() );
`endif
endmodule // tx_chain
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO1P_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__INPUTISO1P_BEHAVIORAL_PP_V
/**
* inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__inputiso1p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO1P_BEHAVIORAL_PP_V |
// --------------------------------------------------------------------------------
//| Avalon ST Idle Inserter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module altera_avalon_st_idle_inserter (
// Interface: clk
input clk,
input reset_n,
// Interface: ST in
output reg in_ready,
input in_valid,
input [7: 0] in_data,
// Interface: ST out
input out_ready,
output reg out_valid,
output reg [7: 0] out_data
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg received_esc;
wire escape_char, idle_char;
// ---------------------------------------------------------------------
//| Thingofamagick
// ---------------------------------------------------------------------
assign idle_char = (in_data == 8'h4a);
assign escape_char = (in_data == 8'h4d);
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
received_esc <= 0;
end else begin
if (in_valid & out_ready) begin
if ((idle_char | escape_char) & ~received_esc & out_ready) begin
received_esc <= 1;
end else begin
received_esc <= 0;
end
end
end
end
always @* begin
//we are always valid
out_valid = 1'b1;
in_ready = out_ready & (~in_valid | ((~idle_char & ~escape_char) | received_esc));
out_data = (~in_valid) ? 8'h4a : //if input is not valid, insert idle
(received_esc) ? in_data ^ 8'h20 : //escaped once, send data XOR'd
(idle_char | escape_char) ? 8'h4d : //input needs escaping, send escape_char
in_data; //send data
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/28/2016 11:50:35 AM
// Design Name:
// Module Name: box
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`define TOP 0
`define RIGHT 1
`define BOTTOM 2
`define LEFT 3
`define WIDTH 640
`define HEIGHT 480
`define BOX_WIDTH WIDTH/4
`define BOX_HEIGHT HEIGHT/4
`define START_X WIDTH/2
`define START_Y HEIGHT/2
module box(
input logic move_up, move_down, move_left, move_right, mode, rst_n,
input logic [9:0] x, y,
output logic draw_box
);
logic [9:0] width, height, c_x, c_y;
logic [9:0] left, right, top, bottom;
assign draw_box = (x == left || x == right ||
y == top || y == bottom)
assign top = c_y - height;
assign bottom = c_y + height;
assign left = c_x - width;
assign right = c_x + width;
assign x_y_mode = mode;
assign width_height_mode = !mode;
up_down_counter #(BOX_WIDTH) width_counter(clk, rst_n,
width_height_mode, move_right, move_left, width);
up_down_counter #(BOX_HEIGHT) height_counter(clk, rst_n,
width_height_mode, move_up, move_down, height);
up_down_counter #(START_X) c_x_counter(clk, rst_n,
x_y_mode, move_right, move_left, c_x);
up_down_counter #(START_Y) c_y_counter(clk, rst_n,
x_y_mode, move_up, move_down, c_y);
endmodule
module up_down_counter
#(parameter DEFAULT=8'd100) (
input logic clk, rst_n, clr, en,
input logic count_up, count_down,
output logic [9:0] count
);
always_ff @(posedge clk) begin
if (~rst_n)
count <= DEFAULT;
else if (clr)
count <= DEFAULT;
else if (en) begin
if (count_up) count <= count + 1'b1;
else if (count_down) count <= count - 1'b1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_2_V
`define SKY130_FD_SC_LP__A221O_2_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CONB_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__CONB_PP_BLACKBOX_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CONB_PP_BLACKBOX_V
|
// file: io_clock_gen_600mhz.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___600.000______0.000______50.0_______83.768_____87.180
// CLK_OUT2___300.000______0.000______50.0_______94.862_____87.180
// CLK_OUT3____75.000______0.000______50.0______122.158_____87.180
// CLK_OUT4___300.000_____90.000______50.0_______94.862_____87.180
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "io_clock_gen_600mhz,clk_wiz_v3_6,{component_name=io_clock_gen_600mhz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module io_clock_gen_600mhz
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
BUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (12.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (2.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (4),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (16),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (4),
.CLKOUT3_PHASE (90.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
BUFG clkout3_buf
(.O (CLK_OUT3),
.I (clkout2));
BUFG clkout4_buf
(.O (CLK_OUT4),
.I (clkout3));
endmodule
|
module toggle2pulse(/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in, reset
);
//clocks
input clk;
input in;
output out;
//reset
input reset;
reg out_reg;
always @ (posedge clk)
if(reset)
out_reg <= 1'b0;
else
out_reg <= in;
assign out = in ^ out_reg;
endmodule
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
/*
* integer1 - a verilog test for integer conditionals
*
* Copyright (C) 1999 Stephen G. Tell
* Portions inspired by qmark.v by Steven Wilson ([email protected])
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this software; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, MA 02111-1307 USA
*/
module integer1lt;
integer a;
integer b;
reg error;
initial begin
error = 0;
a = 2;
if(a < 2) begin
$display("FAILED 2 < 2");
error = 1;
end
a = 3;
if(a < 2) begin
$display("FAILED 3 < 2");
error = 1;
end
a = 1;
if(a < 2) begin
b = 1;
end else begin
$display("FAILED 1 < 2");
error = 1;
end
b = 0;
for(a = 0; a < 5; a = a + 1) begin
b = b + a;
end // for (a = 0; a < 5; a = a + 1)
if(b != 10) begin
$display("FAILED forloop b=%d expected 10", b);
error = 1;
end
if(error == 0)
$display("PASSED");
$finish;
end // initial begin
endmodule
|
// soc_system.v
// Generated using ACDS version 16.1 196
`timescale 1 ps / 1 ps
module soc_system (
input wire alt_vip_itc_0_clocked_video_vid_clk, // alt_vip_itc_0_clocked_video.vid_clk
output wire [31:0] alt_vip_itc_0_clocked_video_vid_data, // .vid_data
output wire alt_vip_itc_0_clocked_video_underflow, // .underflow
output wire alt_vip_itc_0_clocked_video_vid_datavalid, // .vid_datavalid
output wire alt_vip_itc_0_clocked_video_vid_v_sync, // .vid_v_sync
output wire alt_vip_itc_0_clocked_video_vid_h_sync, // .vid_h_sync
output wire alt_vip_itc_0_clocked_video_vid_f, // .vid_f
output wire alt_vip_itc_0_clocked_video_vid_h, // .vid_h
output wire alt_vip_itc_0_clocked_video_vid_v, // .vid_v
input wire [1:0] button_pio_external_connection_export, // button_pio_external_connection.export
input wire clk_clk, // clk.clk
input wire [9:0] dipsw_pio_external_connection_export, // dipsw_pio_external_connection.export
output wire hps_0_h2f_reset_reset_n, // hps_0_h2f_reset.reset_n
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CLK, // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_0_hps_io_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_0_hps_io_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_0_hps_io_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_0_hps_io_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_0_hps_io_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_0_hps_io_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_0_hps_io_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_0_hps_io_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_0_hps_io_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_0_hps_io_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_0_hps_io_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_0_hps_io_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_0_hps_io_hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_0_hps_io_hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_0_hps_io_hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_0_hps_io_hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_0_hps_io_hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_0_hps_io_hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_0_hps_io_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_0_hps_io_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_0_hps_io_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_0_hps_io_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_0_hps_io_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_0_hps_io_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_0_hps_io_hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_0_hps_io_hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_0_hps_io_hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_0_hps_io_hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_0_hps_io_hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_0_hps_io_hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_0_hps_io_hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_0_hps_io_hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_0_hps_io_hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_0_hps_io_hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_0_hps_io_hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_0_hps_io_hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_0_hps_io_hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_0_hps_io_hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_0_hps_io_hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_0_hps_io_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_0_hps_io_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_0_hps_io_hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_0_hps_io_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_0_hps_io_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_0_hps_io_hps_io_gpio_inst_GPIO61, // .hps_io_gpio_inst_GPIO61
output wire [9:0] led_pio_external_connection_export, // led_pio_external_connection.export
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
input wire reset_reset_n // reset.reset_n
);
wire alt_vip_vfr_vga_avalon_streaming_source_valid; // alt_vip_vfr_vga:dout_valid -> alt_vip_itc_0:is_valid
wire [31:0] alt_vip_vfr_vga_avalon_streaming_source_data; // alt_vip_vfr_vga:dout_data -> alt_vip_itc_0:is_data
wire alt_vip_vfr_vga_avalon_streaming_source_ready; // alt_vip_itc_0:is_ready -> alt_vip_vfr_vga:dout_ready
wire alt_vip_vfr_vga_avalon_streaming_source_startofpacket; // alt_vip_vfr_vga:dout_startofpacket -> alt_vip_itc_0:is_sop
wire alt_vip_vfr_vga_avalon_streaming_source_endofpacket; // alt_vip_vfr_vga:dout_endofpacket -> alt_vip_itc_0:is_eop
wire pll_stream_outclk0_clk; // pll_stream:outclk_0 -> [alt_vip_itc_0:is_clk, alt_vip_vfr_vga:clock, mm_interconnect_1:pll_stream_outclk0_clk, rst_controller:clk]
wire [127:0] alt_vip_vfr_vga_avalon_master_readdata; // mm_interconnect_0:alt_vip_vfr_vga_avalon_master_readdata -> alt_vip_vfr_vga:master_readdata
wire alt_vip_vfr_vga_avalon_master_waitrequest; // mm_interconnect_0:alt_vip_vfr_vga_avalon_master_waitrequest -> alt_vip_vfr_vga:master_waitrequest
wire [31:0] alt_vip_vfr_vga_avalon_master_address; // alt_vip_vfr_vga:master_address -> mm_interconnect_0:alt_vip_vfr_vga_avalon_master_address
wire alt_vip_vfr_vga_avalon_master_read; // alt_vip_vfr_vga:master_read -> mm_interconnect_0:alt_vip_vfr_vga_avalon_master_read
wire alt_vip_vfr_vga_avalon_master_readdatavalid; // mm_interconnect_0:alt_vip_vfr_vga_avalon_master_readdatavalid -> alt_vip_vfr_vga:master_readdatavalid
wire [5:0] alt_vip_vfr_vga_avalon_master_burstcount; // alt_vip_vfr_vga:master_burstcount -> mm_interconnect_0:alt_vip_vfr_vga_avalon_master_burstcount
wire [31:0] master_secure_master_readdata; // mm_interconnect_0:master_secure_master_readdata -> master_secure:master_readdata
wire master_secure_master_waitrequest; // mm_interconnect_0:master_secure_master_waitrequest -> master_secure:master_waitrequest
wire [31:0] master_secure_master_address; // master_secure:master_address -> mm_interconnect_0:master_secure_master_address
wire master_secure_master_read; // master_secure:master_read -> mm_interconnect_0:master_secure_master_read
wire [3:0] master_secure_master_byteenable; // master_secure:master_byteenable -> mm_interconnect_0:master_secure_master_byteenable
wire master_secure_master_readdatavalid; // mm_interconnect_0:master_secure_master_readdatavalid -> master_secure:master_readdatavalid
wire master_secure_master_write; // master_secure:master_write -> mm_interconnect_0:master_secure_master_write
wire [31:0] master_secure_master_writedata; // master_secure:master_writedata -> mm_interconnect_0:master_secure_master_writedata
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_awburst; // mm_interconnect_0:hps_0_f2h_axi_slave_awburst -> hps_0:f2h_AWBURST
wire [4:0] mm_interconnect_0_hps_0_f2h_axi_slave_awuser; // mm_interconnect_0:hps_0_f2h_axi_slave_awuser -> hps_0:f2h_AWUSER
wire [3:0] mm_interconnect_0_hps_0_f2h_axi_slave_arlen; // mm_interconnect_0:hps_0_f2h_axi_slave_arlen -> hps_0:f2h_ARLEN
wire [15:0] mm_interconnect_0_hps_0_f2h_axi_slave_wstrb; // mm_interconnect_0:hps_0_f2h_axi_slave_wstrb -> hps_0:f2h_WSTRB
wire mm_interconnect_0_hps_0_f2h_axi_slave_wready; // hps_0:f2h_WREADY -> mm_interconnect_0:hps_0_f2h_axi_slave_wready
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_rid; // hps_0:f2h_RID -> mm_interconnect_0:hps_0_f2h_axi_slave_rid
wire mm_interconnect_0_hps_0_f2h_axi_slave_rready; // mm_interconnect_0:hps_0_f2h_axi_slave_rready -> hps_0:f2h_RREADY
wire [3:0] mm_interconnect_0_hps_0_f2h_axi_slave_awlen; // mm_interconnect_0:hps_0_f2h_axi_slave_awlen -> hps_0:f2h_AWLEN
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_wid; // mm_interconnect_0:hps_0_f2h_axi_slave_wid -> hps_0:f2h_WID
wire [3:0] mm_interconnect_0_hps_0_f2h_axi_slave_arcache; // mm_interconnect_0:hps_0_f2h_axi_slave_arcache -> hps_0:f2h_ARCACHE
wire mm_interconnect_0_hps_0_f2h_axi_slave_wvalid; // mm_interconnect_0:hps_0_f2h_axi_slave_wvalid -> hps_0:f2h_WVALID
wire [31:0] mm_interconnect_0_hps_0_f2h_axi_slave_araddr; // mm_interconnect_0:hps_0_f2h_axi_slave_araddr -> hps_0:f2h_ARADDR
wire [2:0] mm_interconnect_0_hps_0_f2h_axi_slave_arprot; // mm_interconnect_0:hps_0_f2h_axi_slave_arprot -> hps_0:f2h_ARPROT
wire [2:0] mm_interconnect_0_hps_0_f2h_axi_slave_awprot; // mm_interconnect_0:hps_0_f2h_axi_slave_awprot -> hps_0:f2h_AWPROT
wire [127:0] mm_interconnect_0_hps_0_f2h_axi_slave_wdata; // mm_interconnect_0:hps_0_f2h_axi_slave_wdata -> hps_0:f2h_WDATA
wire mm_interconnect_0_hps_0_f2h_axi_slave_arvalid; // mm_interconnect_0:hps_0_f2h_axi_slave_arvalid -> hps_0:f2h_ARVALID
wire [3:0] mm_interconnect_0_hps_0_f2h_axi_slave_awcache; // mm_interconnect_0:hps_0_f2h_axi_slave_awcache -> hps_0:f2h_AWCACHE
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_arid; // mm_interconnect_0:hps_0_f2h_axi_slave_arid -> hps_0:f2h_ARID
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_arlock; // mm_interconnect_0:hps_0_f2h_axi_slave_arlock -> hps_0:f2h_ARLOCK
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_awlock; // mm_interconnect_0:hps_0_f2h_axi_slave_awlock -> hps_0:f2h_AWLOCK
wire [31:0] mm_interconnect_0_hps_0_f2h_axi_slave_awaddr; // mm_interconnect_0:hps_0_f2h_axi_slave_awaddr -> hps_0:f2h_AWADDR
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_bresp; // hps_0:f2h_BRESP -> mm_interconnect_0:hps_0_f2h_axi_slave_bresp
wire mm_interconnect_0_hps_0_f2h_axi_slave_arready; // hps_0:f2h_ARREADY -> mm_interconnect_0:hps_0_f2h_axi_slave_arready
wire [127:0] mm_interconnect_0_hps_0_f2h_axi_slave_rdata; // hps_0:f2h_RDATA -> mm_interconnect_0:hps_0_f2h_axi_slave_rdata
wire mm_interconnect_0_hps_0_f2h_axi_slave_awready; // hps_0:f2h_AWREADY -> mm_interconnect_0:hps_0_f2h_axi_slave_awready
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_arburst; // mm_interconnect_0:hps_0_f2h_axi_slave_arburst -> hps_0:f2h_ARBURST
wire [2:0] mm_interconnect_0_hps_0_f2h_axi_slave_arsize; // mm_interconnect_0:hps_0_f2h_axi_slave_arsize -> hps_0:f2h_ARSIZE
wire mm_interconnect_0_hps_0_f2h_axi_slave_bready; // mm_interconnect_0:hps_0_f2h_axi_slave_bready -> hps_0:f2h_BREADY
wire mm_interconnect_0_hps_0_f2h_axi_slave_rlast; // hps_0:f2h_RLAST -> mm_interconnect_0:hps_0_f2h_axi_slave_rlast
wire mm_interconnect_0_hps_0_f2h_axi_slave_wlast; // mm_interconnect_0:hps_0_f2h_axi_slave_wlast -> hps_0:f2h_WLAST
wire [1:0] mm_interconnect_0_hps_0_f2h_axi_slave_rresp; // hps_0:f2h_RRESP -> mm_interconnect_0:hps_0_f2h_axi_slave_rresp
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_awid; // mm_interconnect_0:hps_0_f2h_axi_slave_awid -> hps_0:f2h_AWID
wire [7:0] mm_interconnect_0_hps_0_f2h_axi_slave_bid; // hps_0:f2h_BID -> mm_interconnect_0:hps_0_f2h_axi_slave_bid
wire mm_interconnect_0_hps_0_f2h_axi_slave_bvalid; // hps_0:f2h_BVALID -> mm_interconnect_0:hps_0_f2h_axi_slave_bvalid
wire [2:0] mm_interconnect_0_hps_0_f2h_axi_slave_awsize; // mm_interconnect_0:hps_0_f2h_axi_slave_awsize -> hps_0:f2h_AWSIZE
wire mm_interconnect_0_hps_0_f2h_axi_slave_awvalid; // mm_interconnect_0:hps_0_f2h_axi_slave_awvalid -> hps_0:f2h_AWVALID
wire [4:0] mm_interconnect_0_hps_0_f2h_axi_slave_aruser; // mm_interconnect_0:hps_0_f2h_axi_slave_aruser -> hps_0:f2h_ARUSER
wire mm_interconnect_0_hps_0_f2h_axi_slave_rvalid; // hps_0:f2h_RVALID -> mm_interconnect_0:hps_0_f2h_axi_slave_rvalid
wire [1:0] hps_0_h2f_lw_axi_master_awburst; // hps_0:h2f_lw_AWBURST -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awburst
wire [3:0] hps_0_h2f_lw_axi_master_arlen; // hps_0:h2f_lw_ARLEN -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arlen
wire [3:0] hps_0_h2f_lw_axi_master_wstrb; // hps_0:h2f_lw_WSTRB -> mm_interconnect_1:hps_0_h2f_lw_axi_master_wstrb
wire hps_0_h2f_lw_axi_master_wready; // mm_interconnect_1:hps_0_h2f_lw_axi_master_wready -> hps_0:h2f_lw_WREADY
wire [11:0] hps_0_h2f_lw_axi_master_rid; // mm_interconnect_1:hps_0_h2f_lw_axi_master_rid -> hps_0:h2f_lw_RID
wire hps_0_h2f_lw_axi_master_rready; // hps_0:h2f_lw_RREADY -> mm_interconnect_1:hps_0_h2f_lw_axi_master_rready
wire [3:0] hps_0_h2f_lw_axi_master_awlen; // hps_0:h2f_lw_AWLEN -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awlen
wire [11:0] hps_0_h2f_lw_axi_master_wid; // hps_0:h2f_lw_WID -> mm_interconnect_1:hps_0_h2f_lw_axi_master_wid
wire [3:0] hps_0_h2f_lw_axi_master_arcache; // hps_0:h2f_lw_ARCACHE -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arcache
wire hps_0_h2f_lw_axi_master_wvalid; // hps_0:h2f_lw_WVALID -> mm_interconnect_1:hps_0_h2f_lw_axi_master_wvalid
wire [20:0] hps_0_h2f_lw_axi_master_araddr; // hps_0:h2f_lw_ARADDR -> mm_interconnect_1:hps_0_h2f_lw_axi_master_araddr
wire [2:0] hps_0_h2f_lw_axi_master_arprot; // hps_0:h2f_lw_ARPROT -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arprot
wire [2:0] hps_0_h2f_lw_axi_master_awprot; // hps_0:h2f_lw_AWPROT -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awprot
wire [31:0] hps_0_h2f_lw_axi_master_wdata; // hps_0:h2f_lw_WDATA -> mm_interconnect_1:hps_0_h2f_lw_axi_master_wdata
wire hps_0_h2f_lw_axi_master_arvalid; // hps_0:h2f_lw_ARVALID -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arvalid
wire [3:0] hps_0_h2f_lw_axi_master_awcache; // hps_0:h2f_lw_AWCACHE -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awcache
wire [11:0] hps_0_h2f_lw_axi_master_arid; // hps_0:h2f_lw_ARID -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arid
wire [1:0] hps_0_h2f_lw_axi_master_arlock; // hps_0:h2f_lw_ARLOCK -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arlock
wire [1:0] hps_0_h2f_lw_axi_master_awlock; // hps_0:h2f_lw_AWLOCK -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awlock
wire [20:0] hps_0_h2f_lw_axi_master_awaddr; // hps_0:h2f_lw_AWADDR -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awaddr
wire [1:0] hps_0_h2f_lw_axi_master_bresp; // mm_interconnect_1:hps_0_h2f_lw_axi_master_bresp -> hps_0:h2f_lw_BRESP
wire hps_0_h2f_lw_axi_master_arready; // mm_interconnect_1:hps_0_h2f_lw_axi_master_arready -> hps_0:h2f_lw_ARREADY
wire [31:0] hps_0_h2f_lw_axi_master_rdata; // mm_interconnect_1:hps_0_h2f_lw_axi_master_rdata -> hps_0:h2f_lw_RDATA
wire hps_0_h2f_lw_axi_master_awready; // mm_interconnect_1:hps_0_h2f_lw_axi_master_awready -> hps_0:h2f_lw_AWREADY
wire [1:0] hps_0_h2f_lw_axi_master_arburst; // hps_0:h2f_lw_ARBURST -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arburst
wire [2:0] hps_0_h2f_lw_axi_master_arsize; // hps_0:h2f_lw_ARSIZE -> mm_interconnect_1:hps_0_h2f_lw_axi_master_arsize
wire hps_0_h2f_lw_axi_master_bready; // hps_0:h2f_lw_BREADY -> mm_interconnect_1:hps_0_h2f_lw_axi_master_bready
wire hps_0_h2f_lw_axi_master_rlast; // mm_interconnect_1:hps_0_h2f_lw_axi_master_rlast -> hps_0:h2f_lw_RLAST
wire hps_0_h2f_lw_axi_master_wlast; // hps_0:h2f_lw_WLAST -> mm_interconnect_1:hps_0_h2f_lw_axi_master_wlast
wire [1:0] hps_0_h2f_lw_axi_master_rresp; // mm_interconnect_1:hps_0_h2f_lw_axi_master_rresp -> hps_0:h2f_lw_RRESP
wire [11:0] hps_0_h2f_lw_axi_master_awid; // hps_0:h2f_lw_AWID -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awid
wire [11:0] hps_0_h2f_lw_axi_master_bid; // mm_interconnect_1:hps_0_h2f_lw_axi_master_bid -> hps_0:h2f_lw_BID
wire hps_0_h2f_lw_axi_master_bvalid; // mm_interconnect_1:hps_0_h2f_lw_axi_master_bvalid -> hps_0:h2f_lw_BVALID
wire [2:0] hps_0_h2f_lw_axi_master_awsize; // hps_0:h2f_lw_AWSIZE -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awsize
wire hps_0_h2f_lw_axi_master_awvalid; // hps_0:h2f_lw_AWVALID -> mm_interconnect_1:hps_0_h2f_lw_axi_master_awvalid
wire hps_0_h2f_lw_axi_master_rvalid; // mm_interconnect_1:hps_0_h2f_lw_axi_master_rvalid -> hps_0:h2f_lw_RVALID
wire [31:0] master_non_sec_master_readdata; // mm_interconnect_1:master_non_sec_master_readdata -> master_non_sec:master_readdata
wire master_non_sec_master_waitrequest; // mm_interconnect_1:master_non_sec_master_waitrequest -> master_non_sec:master_waitrequest
wire [31:0] master_non_sec_master_address; // master_non_sec:master_address -> mm_interconnect_1:master_non_sec_master_address
wire master_non_sec_master_read; // master_non_sec:master_read -> mm_interconnect_1:master_non_sec_master_read
wire [3:0] master_non_sec_master_byteenable; // master_non_sec:master_byteenable -> mm_interconnect_1:master_non_sec_master_byteenable
wire master_non_sec_master_readdatavalid; // mm_interconnect_1:master_non_sec_master_readdatavalid -> master_non_sec:master_readdatavalid
wire master_non_sec_master_write; // master_non_sec:master_write -> mm_interconnect_1:master_non_sec_master_write
wire [31:0] master_non_sec_master_writedata; // master_non_sec:master_writedata -> mm_interconnect_1:master_non_sec_master_writedata
wire mm_interconnect_1_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_1:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_1_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_1:jtag_uart_avalon_jtag_slave_readdata
wire mm_interconnect_1_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_1:jtag_uart_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_1_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_1:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_1_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_1:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire mm_interconnect_1_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_1:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire [31:0] mm_interconnect_1_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_1:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [31:0] mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_readdata; // alt_vip_vfr_vga:slave_readdata -> mm_interconnect_1:alt_vip_vfr_vga_avalon_slave_readdata
wire [4:0] mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_address; // mm_interconnect_1:alt_vip_vfr_vga_avalon_slave_address -> alt_vip_vfr_vga:slave_address
wire mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_read; // mm_interconnect_1:alt_vip_vfr_vga_avalon_slave_read -> alt_vip_vfr_vga:slave_read
wire mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_write; // mm_interconnect_1:alt_vip_vfr_vga_avalon_slave_write -> alt_vip_vfr_vga:slave_write
wire [31:0] mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_writedata; // mm_interconnect_1:alt_vip_vfr_vga_avalon_slave_writedata -> alt_vip_vfr_vga:slave_writedata
wire [31:0] mm_interconnect_1_sysid_qsys_control_slave_readdata; // sysid_qsys:readdata -> mm_interconnect_1:sysid_qsys_control_slave_readdata
wire [0:0] mm_interconnect_1_sysid_qsys_control_slave_address; // mm_interconnect_1:sysid_qsys_control_slave_address -> sysid_qsys:address
wire mm_interconnect_1_led_pio_s1_chipselect; // mm_interconnect_1:led_pio_s1_chipselect -> led_pio:chipselect
wire [31:0] mm_interconnect_1_led_pio_s1_readdata; // led_pio:readdata -> mm_interconnect_1:led_pio_s1_readdata
wire [1:0] mm_interconnect_1_led_pio_s1_address; // mm_interconnect_1:led_pio_s1_address -> led_pio:address
wire mm_interconnect_1_led_pio_s1_write; // mm_interconnect_1:led_pio_s1_write -> led_pio:write_n
wire [31:0] mm_interconnect_1_led_pio_s1_writedata; // mm_interconnect_1:led_pio_s1_writedata -> led_pio:writedata
wire mm_interconnect_1_dipsw_pio_s1_chipselect; // mm_interconnect_1:dipsw_pio_s1_chipselect -> dipsw_pio:chipselect
wire [31:0] mm_interconnect_1_dipsw_pio_s1_readdata; // dipsw_pio:readdata -> mm_interconnect_1:dipsw_pio_s1_readdata
wire [1:0] mm_interconnect_1_dipsw_pio_s1_address; // mm_interconnect_1:dipsw_pio_s1_address -> dipsw_pio:address
wire mm_interconnect_1_dipsw_pio_s1_write; // mm_interconnect_1:dipsw_pio_s1_write -> dipsw_pio:write_n
wire [31:0] mm_interconnect_1_dipsw_pio_s1_writedata; // mm_interconnect_1:dipsw_pio_s1_writedata -> dipsw_pio:writedata
wire mm_interconnect_1_button_pio_s1_chipselect; // mm_interconnect_1:button_pio_s1_chipselect -> button_pio:chipselect
wire [31:0] mm_interconnect_1_button_pio_s1_readdata; // button_pio:readdata -> mm_interconnect_1:button_pio_s1_readdata
wire [1:0] mm_interconnect_1_button_pio_s1_address; // mm_interconnect_1:button_pio_s1_address -> button_pio:address
wire mm_interconnect_1_button_pio_s1_write; // mm_interconnect_1:button_pio_s1_write -> button_pio:write_n
wire [31:0] mm_interconnect_1_button_pio_s1_writedata; // mm_interconnect_1:button_pio_s1_writedata -> button_pio:writedata
wire [31:0] mm_interconnect_1_intr_capturer_0_avalon_slave_0_readdata; // intr_capturer_0:rddata -> mm_interconnect_1:intr_capturer_0_avalon_slave_0_readdata
wire [0:0] mm_interconnect_1_intr_capturer_0_avalon_slave_0_address; // mm_interconnect_1:intr_capturer_0_avalon_slave_0_address -> intr_capturer_0:addr
wire mm_interconnect_1_intr_capturer_0_avalon_slave_0_read; // mm_interconnect_1:intr_capturer_0_avalon_slave_0_read -> intr_capturer_0:read
wire [31:0] hps_0_f2h_irq0_irq; // irq_mapper:sender_irq -> hps_0:f2h_irq_p0
wire [31:0] hps_0_f2h_irq1_irq; // irq_mapper_001:sender_irq -> hps_0:f2h_irq_p1
wire [31:0] intr_capturer_0_interrupt_receiver_irq; // irq_mapper_002:sender_irq -> intr_capturer_0:interrupt_in
wire irq_mapper_receiver1_irq; // button_pio:irq -> [irq_mapper:receiver1_irq, irq_mapper_002:receiver1_irq]
wire irq_mapper_receiver2_irq; // dipsw_pio:irq -> [irq_mapper:receiver2_irq, irq_mapper_002:receiver2_irq]
wire irq_mapper_receiver0_irq; // jtag_uart:av_irq -> [irq_mapper:receiver0_irq, irq_mapper_002:receiver0_irq]
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [alt_vip_itc_0:rst, alt_vip_vfr_vga:reset, mm_interconnect_1:alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [alt_vip_vfr_vga:master_reset, button_pio:reset_n, dipsw_pio:reset_n, intr_capturer_0:rst_n, irq_mapper_002:reset, jtag_uart:rst_n, led_pio:reset_n, mm_interconnect_0:alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset, mm_interconnect_0:master_secure_clk_reset_reset_bridge_in_reset_reset, mm_interconnect_1:jtag_uart_reset_reset_bridge_in_reset_reset, mm_interconnect_1:master_non_sec_clk_reset_reset_bridge_in_reset_reset, sysid_qsys:reset_n]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [mm_interconnect_0:hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset, mm_interconnect_1:hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset]
alt_vipitc131_IS2Vid #(
.NUMBER_OF_COLOUR_PLANES (4),
.COLOUR_PLANES_ARE_IN_PARALLEL (1),
.BPS (8),
.INTERLACED (0),
.H_ACTIVE_PIXELS (1024),
.V_ACTIVE_LINES (768),
.ACCEPT_COLOURS_IN_SEQ (0),
.FIFO_DEPTH (1920),
.CLOCKS_ARE_SAME (0),
.USE_CONTROL (0),
.NO_OF_MODES (1),
.THRESHOLD (1919),
.STD_WIDTH (1),
.GENERATE_SYNC (0),
.USE_EMBEDDED_SYNCS (0),
.AP_LINE (0),
.V_BLANK (0),
.H_BLANK (0),
.H_SYNC_LENGTH (136),
.H_FRONT_PORCH (24),
.H_BACK_PORCH (160),
.V_SYNC_LENGTH (6),
.V_FRONT_PORCH (3),
.V_BACK_PORCH (29),
.F_RISING_EDGE (0),
.F_FALLING_EDGE (0),
.FIELD0_V_RISING_EDGE (0),
.FIELD0_V_BLANK (0),
.FIELD0_V_SYNC_LENGTH (0),
.FIELD0_V_FRONT_PORCH (0),
.FIELD0_V_BACK_PORCH (0),
.ANC_LINE (0),
.FIELD0_ANC_LINE (0)
) alt_vip_itc_0 (
.is_clk (pll_stream_outclk0_clk), // is_clk_rst.clk
.rst (rst_controller_reset_out_reset), // is_clk_rst_reset.reset
.is_data (alt_vip_vfr_vga_avalon_streaming_source_data), // din.data
.is_valid (alt_vip_vfr_vga_avalon_streaming_source_valid), // .valid
.is_ready (alt_vip_vfr_vga_avalon_streaming_source_ready), // .ready
.is_sop (alt_vip_vfr_vga_avalon_streaming_source_startofpacket), // .startofpacket
.is_eop (alt_vip_vfr_vga_avalon_streaming_source_endofpacket), // .endofpacket
.vid_clk (alt_vip_itc_0_clocked_video_vid_clk), // clocked_video.export
.vid_data (alt_vip_itc_0_clocked_video_vid_data), // .export
.underflow (alt_vip_itc_0_clocked_video_underflow), // .export
.vid_datavalid (alt_vip_itc_0_clocked_video_vid_datavalid), // .export
.vid_v_sync (alt_vip_itc_0_clocked_video_vid_v_sync), // .export
.vid_h_sync (alt_vip_itc_0_clocked_video_vid_h_sync), // .export
.vid_f (alt_vip_itc_0_clocked_video_vid_f), // .export
.vid_h (alt_vip_itc_0_clocked_video_vid_h), // .export
.vid_v (alt_vip_itc_0_clocked_video_vid_v) // .export
);
alt_vipvfr131_vfr #(
.BITS_PER_PIXEL_PER_COLOR_PLANE (8),
.NUMBER_OF_CHANNELS_IN_PARALLEL (4),
.NUMBER_OF_CHANNELS_IN_SEQUENCE (1),
.MAX_IMAGE_WIDTH (1024),
.MAX_IMAGE_HEIGHT (768),
.MEM_PORT_WIDTH (128),
.RMASTER_FIFO_DEPTH (64),
.RMASTER_BURST_TARGET (32),
.CLOCKS_ARE_SEPARATE (1)
) alt_vip_vfr_vga (
.clock (pll_stream_outclk0_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.master_clock (clk_clk), // clock_master.clk
.master_reset (rst_controller_001_reset_out_reset), // clock_master_reset.reset
.slave_address (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_address), // avalon_slave.address
.slave_write (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_write), // .write
.slave_writedata (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_writedata), // .writedata
.slave_read (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_read), // .read
.slave_readdata (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_readdata), // .readdata
.slave_irq (), // interrupt_sender.irq
.dout_data (alt_vip_vfr_vga_avalon_streaming_source_data), // avalon_streaming_source.data
.dout_valid (alt_vip_vfr_vga_avalon_streaming_source_valid), // .valid
.dout_ready (alt_vip_vfr_vga_avalon_streaming_source_ready), // .ready
.dout_startofpacket (alt_vip_vfr_vga_avalon_streaming_source_startofpacket), // .startofpacket
.dout_endofpacket (alt_vip_vfr_vga_avalon_streaming_source_endofpacket), // .endofpacket
.master_address (alt_vip_vfr_vga_avalon_master_address), // avalon_master.address
.master_burstcount (alt_vip_vfr_vga_avalon_master_burstcount), // .burstcount
.master_readdata (alt_vip_vfr_vga_avalon_master_readdata), // .readdata
.master_read (alt_vip_vfr_vga_avalon_master_read), // .read
.master_readdatavalid (alt_vip_vfr_vga_avalon_master_readdatavalid), // .readdatavalid
.master_waitrequest (alt_vip_vfr_vga_avalon_master_waitrequest) // .waitrequest
);
soc_system_button_pio button_pio (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_button_pio_s1_address), // s1.address
.write_n (~mm_interconnect_1_button_pio_s1_write), // .write_n
.writedata (mm_interconnect_1_button_pio_s1_writedata), // .writedata
.chipselect (mm_interconnect_1_button_pio_s1_chipselect), // .chipselect
.readdata (mm_interconnect_1_button_pio_s1_readdata), // .readdata
.in_port (button_pio_external_connection_export), // external_connection.export
.irq (irq_mapper_receiver1_irq) // irq.irq
);
soc_system_dipsw_pio dipsw_pio (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_dipsw_pio_s1_address), // s1.address
.write_n (~mm_interconnect_1_dipsw_pio_s1_write), // .write_n
.writedata (mm_interconnect_1_dipsw_pio_s1_writedata), // .writedata
.chipselect (mm_interconnect_1_dipsw_pio_s1_chipselect), // .chipselect
.readdata (mm_interconnect_1_dipsw_pio_s1_readdata), // .readdata
.in_port (dipsw_pio_external_connection_export), // external_connection.export
.irq (irq_mapper_receiver2_irq) // irq.irq
);
soc_system_hps_0 #(
.F2S_Width (3),
.S2F_Width (2)
) hps_0 (
.f2h_boot_from_fpga_ready (), // f2h_boot_from_fpga.boot_from_fpga_ready
.f2h_boot_from_fpga_on_failure (), // .boot_from_fpga_on_failure
.mem_a (memory_mem_a), // memory.mem_a
.mem_ba (memory_mem_ba), // .mem_ba
.mem_ck (memory_mem_ck), // .mem_ck
.mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.mem_cke (memory_mem_cke), // .mem_cke
.mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.mem_we_n (memory_mem_we_n), // .mem_we_n
.mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.mem_dq (memory_mem_dq), // .mem_dq
.mem_dqs (memory_mem_dqs), // .mem_dqs
.mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.mem_odt (memory_mem_odt), // .mem_odt
.mem_dm (memory_mem_dm), // .mem_dm
.oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_0_hps_io_hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_0_hps_io_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_0_hps_io_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_0_hps_io_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_0_hps_io_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_0_hps_io_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_0_hps_io_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_0_hps_io_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_0_hps_io_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_0_hps_io_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_0_hps_io_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_0_hps_io_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_0_hps_io_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_0_hps_io_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_0_hps_io_hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_0_hps_io_hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_0_hps_io_hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_0_hps_io_hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_0_hps_io_hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_0_hps_io_hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_0_hps_io_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_0_hps_io_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_0_hps_io_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_0_hps_io_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_0_hps_io_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_0_hps_io_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_0_hps_io_hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_0_hps_io_hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_0_hps_io_hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_0_hps_io_hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_0_hps_io_hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_0_hps_io_hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_0_hps_io_hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_0_hps_io_hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_0_hps_io_hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_0_hps_io_hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_0_hps_io_hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_0_hps_io_hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_0_hps_io_hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_0_hps_io_hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_0_hps_io_hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_0_hps_io_hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_0_hps_io_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_0_hps_io_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_0_hps_io_hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_0_hps_io_hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_0_hps_io_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_0_hps_io_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_0_hps_io_hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_0_hps_io_hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_0_hps_io_hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_0_hps_io_hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_0_hps_io_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_0_hps_io_hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_0_hps_io_hps_io_gpio_inst_GPIO61), // .hps_io_gpio_inst_GPIO61
.h2f_rst_n (hps_0_h2f_reset_reset_n), // h2f_reset.reset_n
.h2f_axi_clk (clk_clk), // h2f_axi_clock.clk
.h2f_AWID (), // h2f_axi_master.awid
.h2f_AWADDR (), // .awaddr
.h2f_AWLEN (), // .awlen
.h2f_AWSIZE (), // .awsize
.h2f_AWBURST (), // .awburst
.h2f_AWLOCK (), // .awlock
.h2f_AWCACHE (), // .awcache
.h2f_AWPROT (), // .awprot
.h2f_AWVALID (), // .awvalid
.h2f_AWREADY (), // .awready
.h2f_WID (), // .wid
.h2f_WDATA (), // .wdata
.h2f_WSTRB (), // .wstrb
.h2f_WLAST (), // .wlast
.h2f_WVALID (), // .wvalid
.h2f_WREADY (), // .wready
.h2f_BID (), // .bid
.h2f_BRESP (), // .bresp
.h2f_BVALID (), // .bvalid
.h2f_BREADY (), // .bready
.h2f_ARID (), // .arid
.h2f_ARADDR (), // .araddr
.h2f_ARLEN (), // .arlen
.h2f_ARSIZE (), // .arsize
.h2f_ARBURST (), // .arburst
.h2f_ARLOCK (), // .arlock
.h2f_ARCACHE (), // .arcache
.h2f_ARPROT (), // .arprot
.h2f_ARVALID (), // .arvalid
.h2f_ARREADY (), // .arready
.h2f_RID (), // .rid
.h2f_RDATA (), // .rdata
.h2f_RRESP (), // .rresp
.h2f_RLAST (), // .rlast
.h2f_RVALID (), // .rvalid
.h2f_RREADY (), // .rready
.f2h_axi_clk (clk_clk), // f2h_axi_clock.clk
.f2h_AWID (mm_interconnect_0_hps_0_f2h_axi_slave_awid), // f2h_axi_slave.awid
.f2h_AWADDR (mm_interconnect_0_hps_0_f2h_axi_slave_awaddr), // .awaddr
.f2h_AWLEN (mm_interconnect_0_hps_0_f2h_axi_slave_awlen), // .awlen
.f2h_AWSIZE (mm_interconnect_0_hps_0_f2h_axi_slave_awsize), // .awsize
.f2h_AWBURST (mm_interconnect_0_hps_0_f2h_axi_slave_awburst), // .awburst
.f2h_AWLOCK (mm_interconnect_0_hps_0_f2h_axi_slave_awlock), // .awlock
.f2h_AWCACHE (mm_interconnect_0_hps_0_f2h_axi_slave_awcache), // .awcache
.f2h_AWPROT (mm_interconnect_0_hps_0_f2h_axi_slave_awprot), // .awprot
.f2h_AWVALID (mm_interconnect_0_hps_0_f2h_axi_slave_awvalid), // .awvalid
.f2h_AWREADY (mm_interconnect_0_hps_0_f2h_axi_slave_awready), // .awready
.f2h_AWUSER (mm_interconnect_0_hps_0_f2h_axi_slave_awuser), // .awuser
.f2h_WID (mm_interconnect_0_hps_0_f2h_axi_slave_wid), // .wid
.f2h_WDATA (mm_interconnect_0_hps_0_f2h_axi_slave_wdata), // .wdata
.f2h_WSTRB (mm_interconnect_0_hps_0_f2h_axi_slave_wstrb), // .wstrb
.f2h_WLAST (mm_interconnect_0_hps_0_f2h_axi_slave_wlast), // .wlast
.f2h_WVALID (mm_interconnect_0_hps_0_f2h_axi_slave_wvalid), // .wvalid
.f2h_WREADY (mm_interconnect_0_hps_0_f2h_axi_slave_wready), // .wready
.f2h_BID (mm_interconnect_0_hps_0_f2h_axi_slave_bid), // .bid
.f2h_BRESP (mm_interconnect_0_hps_0_f2h_axi_slave_bresp), // .bresp
.f2h_BVALID (mm_interconnect_0_hps_0_f2h_axi_slave_bvalid), // .bvalid
.f2h_BREADY (mm_interconnect_0_hps_0_f2h_axi_slave_bready), // .bready
.f2h_ARID (mm_interconnect_0_hps_0_f2h_axi_slave_arid), // .arid
.f2h_ARADDR (mm_interconnect_0_hps_0_f2h_axi_slave_araddr), // .araddr
.f2h_ARLEN (mm_interconnect_0_hps_0_f2h_axi_slave_arlen), // .arlen
.f2h_ARSIZE (mm_interconnect_0_hps_0_f2h_axi_slave_arsize), // .arsize
.f2h_ARBURST (mm_interconnect_0_hps_0_f2h_axi_slave_arburst), // .arburst
.f2h_ARLOCK (mm_interconnect_0_hps_0_f2h_axi_slave_arlock), // .arlock
.f2h_ARCACHE (mm_interconnect_0_hps_0_f2h_axi_slave_arcache), // .arcache
.f2h_ARPROT (mm_interconnect_0_hps_0_f2h_axi_slave_arprot), // .arprot
.f2h_ARVALID (mm_interconnect_0_hps_0_f2h_axi_slave_arvalid), // .arvalid
.f2h_ARREADY (mm_interconnect_0_hps_0_f2h_axi_slave_arready), // .arready
.f2h_ARUSER (mm_interconnect_0_hps_0_f2h_axi_slave_aruser), // .aruser
.f2h_RID (mm_interconnect_0_hps_0_f2h_axi_slave_rid), // .rid
.f2h_RDATA (mm_interconnect_0_hps_0_f2h_axi_slave_rdata), // .rdata
.f2h_RRESP (mm_interconnect_0_hps_0_f2h_axi_slave_rresp), // .rresp
.f2h_RLAST (mm_interconnect_0_hps_0_f2h_axi_slave_rlast), // .rlast
.f2h_RVALID (mm_interconnect_0_hps_0_f2h_axi_slave_rvalid), // .rvalid
.f2h_RREADY (mm_interconnect_0_hps_0_f2h_axi_slave_rready), // .rready
.h2f_lw_axi_clk (clk_clk), // h2f_lw_axi_clock.clk
.h2f_lw_AWID (hps_0_h2f_lw_axi_master_awid), // h2f_lw_axi_master.awid
.h2f_lw_AWADDR (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.h2f_lw_AWLEN (hps_0_h2f_lw_axi_master_awlen), // .awlen
.h2f_lw_AWSIZE (hps_0_h2f_lw_axi_master_awsize), // .awsize
.h2f_lw_AWBURST (hps_0_h2f_lw_axi_master_awburst), // .awburst
.h2f_lw_AWLOCK (hps_0_h2f_lw_axi_master_awlock), // .awlock
.h2f_lw_AWCACHE (hps_0_h2f_lw_axi_master_awcache), // .awcache
.h2f_lw_AWPROT (hps_0_h2f_lw_axi_master_awprot), // .awprot
.h2f_lw_AWVALID (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.h2f_lw_AWREADY (hps_0_h2f_lw_axi_master_awready), // .awready
.h2f_lw_WID (hps_0_h2f_lw_axi_master_wid), // .wid
.h2f_lw_WDATA (hps_0_h2f_lw_axi_master_wdata), // .wdata
.h2f_lw_WSTRB (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.h2f_lw_WLAST (hps_0_h2f_lw_axi_master_wlast), // .wlast
.h2f_lw_WVALID (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.h2f_lw_WREADY (hps_0_h2f_lw_axi_master_wready), // .wready
.h2f_lw_BID (hps_0_h2f_lw_axi_master_bid), // .bid
.h2f_lw_BRESP (hps_0_h2f_lw_axi_master_bresp), // .bresp
.h2f_lw_BVALID (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.h2f_lw_BREADY (hps_0_h2f_lw_axi_master_bready), // .bready
.h2f_lw_ARID (hps_0_h2f_lw_axi_master_arid), // .arid
.h2f_lw_ARADDR (hps_0_h2f_lw_axi_master_araddr), // .araddr
.h2f_lw_ARLEN (hps_0_h2f_lw_axi_master_arlen), // .arlen
.h2f_lw_ARSIZE (hps_0_h2f_lw_axi_master_arsize), // .arsize
.h2f_lw_ARBURST (hps_0_h2f_lw_axi_master_arburst), // .arburst
.h2f_lw_ARLOCK (hps_0_h2f_lw_axi_master_arlock), // .arlock
.h2f_lw_ARCACHE (hps_0_h2f_lw_axi_master_arcache), // .arcache
.h2f_lw_ARPROT (hps_0_h2f_lw_axi_master_arprot), // .arprot
.h2f_lw_ARVALID (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.h2f_lw_ARREADY (hps_0_h2f_lw_axi_master_arready), // .arready
.h2f_lw_RID (hps_0_h2f_lw_axi_master_rid), // .rid
.h2f_lw_RDATA (hps_0_h2f_lw_axi_master_rdata), // .rdata
.h2f_lw_RRESP (hps_0_h2f_lw_axi_master_rresp), // .rresp
.h2f_lw_RLAST (hps_0_h2f_lw_axi_master_rlast), // .rlast
.h2f_lw_RVALID (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.h2f_lw_RREADY (hps_0_h2f_lw_axi_master_rready), // .rready
.f2h_irq_p0 (hps_0_f2h_irq0_irq), // f2h_irq0.irq
.f2h_irq_p1 (hps_0_f2h_irq1_irq) // f2h_irq1.irq
);
intr_capturer #(
.NUM_INTR (32)
) intr_capturer_0 (
.clk (clk_clk), // clock.clk
.rst_n (~rst_controller_001_reset_out_reset), // reset_sink.reset_n
.addr (mm_interconnect_1_intr_capturer_0_avalon_slave_0_address), // avalon_slave_0.address
.read (mm_interconnect_1_intr_capturer_0_avalon_slave_0_read), // .read
.rddata (mm_interconnect_1_intr_capturer_0_avalon_slave_0_readdata), // .readdata
.interrupt_in (intr_capturer_0_interrupt_receiver_irq) // interrupt_receiver.irq
);
soc_system_jtag_uart jtag_uart (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_1_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_1_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_1_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_1_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_1_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_1_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_1_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
soc_system_led_pio led_pio (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_1_led_pio_s1_address), // s1.address
.write_n (~mm_interconnect_1_led_pio_s1_write), // .write_n
.writedata (mm_interconnect_1_led_pio_s1_writedata), // .writedata
.chipselect (mm_interconnect_1_led_pio_s1_chipselect), // .chipselect
.readdata (mm_interconnect_1_led_pio_s1_readdata), // .readdata
.out_port (led_pio_external_connection_export) // external_connection.export
);
soc_system_master_non_sec #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) master_non_sec (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (master_non_sec_master_address), // master.address
.master_readdata (master_non_sec_master_readdata), // .readdata
.master_read (master_non_sec_master_read), // .read
.master_write (master_non_sec_master_write), // .write
.master_writedata (master_non_sec_master_writedata), // .writedata
.master_waitrequest (master_non_sec_master_waitrequest), // .waitrequest
.master_readdatavalid (master_non_sec_master_readdatavalid), // .readdatavalid
.master_byteenable (master_non_sec_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
soc_system_master_non_sec #(
.USE_PLI (0),
.PLI_PORT (50000),
.FIFO_DEPTHS (2)
) master_secure (
.clk_clk (clk_clk), // clk.clk
.clk_reset_reset (~reset_reset_n), // clk_reset.reset
.master_address (master_secure_master_address), // master.address
.master_readdata (master_secure_master_readdata), // .readdata
.master_read (master_secure_master_read), // .read
.master_write (master_secure_master_write), // .write
.master_writedata (master_secure_master_writedata), // .writedata
.master_waitrequest (master_secure_master_waitrequest), // .waitrequest
.master_readdatavalid (master_secure_master_readdatavalid), // .readdatavalid
.master_byteenable (master_secure_master_byteenable), // .byteenable
.master_reset_reset () // master_reset.reset
);
soc_system_pll_stream pll_stream (
.refclk (clk_clk), // refclk.clk
.rst (~reset_reset_n), // reset.reset
.outclk_0 (pll_stream_outclk0_clk), // outclk0.clk
.locked () // locked.export
);
soc_system_sysid_qsys sysid_qsys (
.clock (clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.readdata (mm_interconnect_1_sysid_qsys_control_slave_readdata), // control_slave.readdata
.address (mm_interconnect_1_sysid_qsys_control_slave_address) // .address
);
soc_system_mm_interconnect_0 mm_interconnect_0 (
.hps_0_f2h_axi_slave_awid (mm_interconnect_0_hps_0_f2h_axi_slave_awid), // hps_0_f2h_axi_slave.awid
.hps_0_f2h_axi_slave_awaddr (mm_interconnect_0_hps_0_f2h_axi_slave_awaddr), // .awaddr
.hps_0_f2h_axi_slave_awlen (mm_interconnect_0_hps_0_f2h_axi_slave_awlen), // .awlen
.hps_0_f2h_axi_slave_awsize (mm_interconnect_0_hps_0_f2h_axi_slave_awsize), // .awsize
.hps_0_f2h_axi_slave_awburst (mm_interconnect_0_hps_0_f2h_axi_slave_awburst), // .awburst
.hps_0_f2h_axi_slave_awlock (mm_interconnect_0_hps_0_f2h_axi_slave_awlock), // .awlock
.hps_0_f2h_axi_slave_awcache (mm_interconnect_0_hps_0_f2h_axi_slave_awcache), // .awcache
.hps_0_f2h_axi_slave_awprot (mm_interconnect_0_hps_0_f2h_axi_slave_awprot), // .awprot
.hps_0_f2h_axi_slave_awuser (mm_interconnect_0_hps_0_f2h_axi_slave_awuser), // .awuser
.hps_0_f2h_axi_slave_awvalid (mm_interconnect_0_hps_0_f2h_axi_slave_awvalid), // .awvalid
.hps_0_f2h_axi_slave_awready (mm_interconnect_0_hps_0_f2h_axi_slave_awready), // .awready
.hps_0_f2h_axi_slave_wid (mm_interconnect_0_hps_0_f2h_axi_slave_wid), // .wid
.hps_0_f2h_axi_slave_wdata (mm_interconnect_0_hps_0_f2h_axi_slave_wdata), // .wdata
.hps_0_f2h_axi_slave_wstrb (mm_interconnect_0_hps_0_f2h_axi_slave_wstrb), // .wstrb
.hps_0_f2h_axi_slave_wlast (mm_interconnect_0_hps_0_f2h_axi_slave_wlast), // .wlast
.hps_0_f2h_axi_slave_wvalid (mm_interconnect_0_hps_0_f2h_axi_slave_wvalid), // .wvalid
.hps_0_f2h_axi_slave_wready (mm_interconnect_0_hps_0_f2h_axi_slave_wready), // .wready
.hps_0_f2h_axi_slave_bid (mm_interconnect_0_hps_0_f2h_axi_slave_bid), // .bid
.hps_0_f2h_axi_slave_bresp (mm_interconnect_0_hps_0_f2h_axi_slave_bresp), // .bresp
.hps_0_f2h_axi_slave_bvalid (mm_interconnect_0_hps_0_f2h_axi_slave_bvalid), // .bvalid
.hps_0_f2h_axi_slave_bready (mm_interconnect_0_hps_0_f2h_axi_slave_bready), // .bready
.hps_0_f2h_axi_slave_arid (mm_interconnect_0_hps_0_f2h_axi_slave_arid), // .arid
.hps_0_f2h_axi_slave_araddr (mm_interconnect_0_hps_0_f2h_axi_slave_araddr), // .araddr
.hps_0_f2h_axi_slave_arlen (mm_interconnect_0_hps_0_f2h_axi_slave_arlen), // .arlen
.hps_0_f2h_axi_slave_arsize (mm_interconnect_0_hps_0_f2h_axi_slave_arsize), // .arsize
.hps_0_f2h_axi_slave_arburst (mm_interconnect_0_hps_0_f2h_axi_slave_arburst), // .arburst
.hps_0_f2h_axi_slave_arlock (mm_interconnect_0_hps_0_f2h_axi_slave_arlock), // .arlock
.hps_0_f2h_axi_slave_arcache (mm_interconnect_0_hps_0_f2h_axi_slave_arcache), // .arcache
.hps_0_f2h_axi_slave_arprot (mm_interconnect_0_hps_0_f2h_axi_slave_arprot), // .arprot
.hps_0_f2h_axi_slave_aruser (mm_interconnect_0_hps_0_f2h_axi_slave_aruser), // .aruser
.hps_0_f2h_axi_slave_arvalid (mm_interconnect_0_hps_0_f2h_axi_slave_arvalid), // .arvalid
.hps_0_f2h_axi_slave_arready (mm_interconnect_0_hps_0_f2h_axi_slave_arready), // .arready
.hps_0_f2h_axi_slave_rid (mm_interconnect_0_hps_0_f2h_axi_slave_rid), // .rid
.hps_0_f2h_axi_slave_rdata (mm_interconnect_0_hps_0_f2h_axi_slave_rdata), // .rdata
.hps_0_f2h_axi_slave_rresp (mm_interconnect_0_hps_0_f2h_axi_slave_rresp), // .rresp
.hps_0_f2h_axi_slave_rlast (mm_interconnect_0_hps_0_f2h_axi_slave_rlast), // .rlast
.hps_0_f2h_axi_slave_rvalid (mm_interconnect_0_hps_0_f2h_axi_slave_rvalid), // .rvalid
.hps_0_f2h_axi_slave_rready (mm_interconnect_0_hps_0_f2h_axi_slave_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // alt_vip_vfr_vga_clock_master_reset_reset_bridge_in_reset.reset
.hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // hps_0_f2h_axi_slave_agent_reset_sink_reset_bridge_in_reset.reset
.master_secure_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // master_secure_clk_reset_reset_bridge_in_reset.reset
.alt_vip_vfr_vga_avalon_master_address (alt_vip_vfr_vga_avalon_master_address), // alt_vip_vfr_vga_avalon_master.address
.alt_vip_vfr_vga_avalon_master_waitrequest (alt_vip_vfr_vga_avalon_master_waitrequest), // .waitrequest
.alt_vip_vfr_vga_avalon_master_burstcount (alt_vip_vfr_vga_avalon_master_burstcount), // .burstcount
.alt_vip_vfr_vga_avalon_master_read (alt_vip_vfr_vga_avalon_master_read), // .read
.alt_vip_vfr_vga_avalon_master_readdata (alt_vip_vfr_vga_avalon_master_readdata), // .readdata
.alt_vip_vfr_vga_avalon_master_readdatavalid (alt_vip_vfr_vga_avalon_master_readdatavalid), // .readdatavalid
.master_secure_master_address (master_secure_master_address), // master_secure_master.address
.master_secure_master_waitrequest (master_secure_master_waitrequest), // .waitrequest
.master_secure_master_byteenable (master_secure_master_byteenable), // .byteenable
.master_secure_master_read (master_secure_master_read), // .read
.master_secure_master_readdata (master_secure_master_readdata), // .readdata
.master_secure_master_readdatavalid (master_secure_master_readdatavalid), // .readdatavalid
.master_secure_master_write (master_secure_master_write), // .write
.master_secure_master_writedata (master_secure_master_writedata) // .writedata
);
soc_system_mm_interconnect_1 mm_interconnect_1 (
.hps_0_h2f_lw_axi_master_awid (hps_0_h2f_lw_axi_master_awid), // hps_0_h2f_lw_axi_master.awid
.hps_0_h2f_lw_axi_master_awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.hps_0_h2f_lw_axi_master_awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.hps_0_h2f_lw_axi_master_awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.hps_0_h2f_lw_axi_master_awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.hps_0_h2f_lw_axi_master_awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.hps_0_h2f_lw_axi_master_awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.hps_0_h2f_lw_axi_master_awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.hps_0_h2f_lw_axi_master_awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.hps_0_h2f_lw_axi_master_awready (hps_0_h2f_lw_axi_master_awready), // .awready
.hps_0_h2f_lw_axi_master_wid (hps_0_h2f_lw_axi_master_wid), // .wid
.hps_0_h2f_lw_axi_master_wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.hps_0_h2f_lw_axi_master_wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.hps_0_h2f_lw_axi_master_wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.hps_0_h2f_lw_axi_master_wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.hps_0_h2f_lw_axi_master_wready (hps_0_h2f_lw_axi_master_wready), // .wready
.hps_0_h2f_lw_axi_master_bid (hps_0_h2f_lw_axi_master_bid), // .bid
.hps_0_h2f_lw_axi_master_bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.hps_0_h2f_lw_axi_master_bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.hps_0_h2f_lw_axi_master_bready (hps_0_h2f_lw_axi_master_bready), // .bready
.hps_0_h2f_lw_axi_master_arid (hps_0_h2f_lw_axi_master_arid), // .arid
.hps_0_h2f_lw_axi_master_araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.hps_0_h2f_lw_axi_master_arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.hps_0_h2f_lw_axi_master_arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.hps_0_h2f_lw_axi_master_arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.hps_0_h2f_lw_axi_master_arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.hps_0_h2f_lw_axi_master_arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.hps_0_h2f_lw_axi_master_arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.hps_0_h2f_lw_axi_master_arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.hps_0_h2f_lw_axi_master_arready (hps_0_h2f_lw_axi_master_arready), // .arready
.hps_0_h2f_lw_axi_master_rid (hps_0_h2f_lw_axi_master_rid), // .rid
.hps_0_h2f_lw_axi_master_rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.hps_0_h2f_lw_axi_master_rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.hps_0_h2f_lw_axi_master_rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.hps_0_h2f_lw_axi_master_rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.hps_0_h2f_lw_axi_master_rready (hps_0_h2f_lw_axi_master_rready), // .rready
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.pll_stream_outclk0_clk (pll_stream_outclk0_clk), // pll_stream_outclk0.clk
.alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // alt_vip_vfr_vga_clock_reset_reset_reset_bridge_in_reset.reset
.hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
.jtag_uart_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // jtag_uart_reset_reset_bridge_in_reset.reset
.master_non_sec_clk_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // master_non_sec_clk_reset_reset_bridge_in_reset.reset
.master_non_sec_master_address (master_non_sec_master_address), // master_non_sec_master.address
.master_non_sec_master_waitrequest (master_non_sec_master_waitrequest), // .waitrequest
.master_non_sec_master_byteenable (master_non_sec_master_byteenable), // .byteenable
.master_non_sec_master_read (master_non_sec_master_read), // .read
.master_non_sec_master_readdata (master_non_sec_master_readdata), // .readdata
.master_non_sec_master_readdatavalid (master_non_sec_master_readdatavalid), // .readdatavalid
.master_non_sec_master_write (master_non_sec_master_write), // .write
.master_non_sec_master_writedata (master_non_sec_master_writedata), // .writedata
.alt_vip_vfr_vga_avalon_slave_address (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_address), // alt_vip_vfr_vga_avalon_slave.address
.alt_vip_vfr_vga_avalon_slave_write (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_write), // .write
.alt_vip_vfr_vga_avalon_slave_read (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_read), // .read
.alt_vip_vfr_vga_avalon_slave_readdata (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_readdata), // .readdata
.alt_vip_vfr_vga_avalon_slave_writedata (mm_interconnect_1_alt_vip_vfr_vga_avalon_slave_writedata), // .writedata
.button_pio_s1_address (mm_interconnect_1_button_pio_s1_address), // button_pio_s1.address
.button_pio_s1_write (mm_interconnect_1_button_pio_s1_write), // .write
.button_pio_s1_readdata (mm_interconnect_1_button_pio_s1_readdata), // .readdata
.button_pio_s1_writedata (mm_interconnect_1_button_pio_s1_writedata), // .writedata
.button_pio_s1_chipselect (mm_interconnect_1_button_pio_s1_chipselect), // .chipselect
.dipsw_pio_s1_address (mm_interconnect_1_dipsw_pio_s1_address), // dipsw_pio_s1.address
.dipsw_pio_s1_write (mm_interconnect_1_dipsw_pio_s1_write), // .write
.dipsw_pio_s1_readdata (mm_interconnect_1_dipsw_pio_s1_readdata), // .readdata
.dipsw_pio_s1_writedata (mm_interconnect_1_dipsw_pio_s1_writedata), // .writedata
.dipsw_pio_s1_chipselect (mm_interconnect_1_dipsw_pio_s1_chipselect), // .chipselect
.intr_capturer_0_avalon_slave_0_address (mm_interconnect_1_intr_capturer_0_avalon_slave_0_address), // intr_capturer_0_avalon_slave_0.address
.intr_capturer_0_avalon_slave_0_read (mm_interconnect_1_intr_capturer_0_avalon_slave_0_read), // .read
.intr_capturer_0_avalon_slave_0_readdata (mm_interconnect_1_intr_capturer_0_avalon_slave_0_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_1_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_1_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_1_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_1_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_1_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_1_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_1_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.led_pio_s1_address (mm_interconnect_1_led_pio_s1_address), // led_pio_s1.address
.led_pio_s1_write (mm_interconnect_1_led_pio_s1_write), // .write
.led_pio_s1_readdata (mm_interconnect_1_led_pio_s1_readdata), // .readdata
.led_pio_s1_writedata (mm_interconnect_1_led_pio_s1_writedata), // .writedata
.led_pio_s1_chipselect (mm_interconnect_1_led_pio_s1_chipselect), // .chipselect
.sysid_qsys_control_slave_address (mm_interconnect_1_sysid_qsys_control_slave_address), // sysid_qsys_control_slave.address
.sysid_qsys_control_slave_readdata (mm_interconnect_1_sysid_qsys_control_slave_readdata) // .readdata
);
soc_system_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.sender_irq (hps_0_f2h_irq0_irq) // sender.irq
);
soc_system_irq_mapper_001 irq_mapper_001 (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.sender_irq (hps_0_f2h_irq1_irq) // sender.irq
);
soc_system_irq_mapper irq_mapper_002 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.sender_irq (intr_capturer_0_interrupt_receiver_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (pll_stream_outclk0_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~hps_0_h2f_reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8
// Date : 16/06/2019, 23:18:37
// Component : VexRiscv
`define AluCtrlEnum_defaultEncoding_type [1:0]
`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00
`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01
`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10
`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0]
`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00
`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01
`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10
`define Src2CtrlEnum_defaultEncoding_type [1:0]
`define Src2CtrlEnum_defaultEncoding_RS 2'b00
`define Src2CtrlEnum_defaultEncoding_IMI 2'b01
`define Src2CtrlEnum_defaultEncoding_IMS 2'b10
`define Src2CtrlEnum_defaultEncoding_PC 2'b11
`define BranchCtrlEnum_defaultEncoding_type [1:0]
`define BranchCtrlEnum_defaultEncoding_INC 2'b00
`define BranchCtrlEnum_defaultEncoding_B 2'b01
`define BranchCtrlEnum_defaultEncoding_JAL 2'b10
`define BranchCtrlEnum_defaultEncoding_JALR 2'b11
`define Src1CtrlEnum_defaultEncoding_type [1:0]
`define Src1CtrlEnum_defaultEncoding_RS 2'b00
`define Src1CtrlEnum_defaultEncoding_IMU 2'b01
`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10
`define Src1CtrlEnum_defaultEncoding_URS1 2'b11
`define EnvCtrlEnum_defaultEncoding_type [0:0]
`define EnvCtrlEnum_defaultEncoding_NONE 1'b0
`define EnvCtrlEnum_defaultEncoding_XRET 1'b1
`define ShiftCtrlEnum_defaultEncoding_type [1:0]
`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00
`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01
`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10
`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
input io_cpu_fetch_dataBypassValid,
input [31:0] io_cpu_fetch_dataBypass,
output io_cpu_fetch_mmuBus_cmd_isValid,
output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress,
output io_cpu_fetch_mmuBus_cmd_bypassTranslation,
input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress,
input io_cpu_fetch_mmuBus_rsp_isIoAccess,
input io_cpu_fetch_mmuBus_rsp_allowRead,
input io_cpu_fetch_mmuBus_rsp_allowWrite,
input io_cpu_fetch_mmuBus_rsp_allowExecute,
input io_cpu_fetch_mmuBus_rsp_exception,
input io_cpu_fetch_mmuBus_rsp_refilling,
output io_cpu_fetch_mmuBus_end,
input io_cpu_fetch_mmuBus_busy,
output [31:0] io_cpu_fetch_physicalAddress,
output io_cpu_fetch_haltIt,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset);
reg [22:0] _zz_10_;
reg [31:0] _zz_11_;
wire _zz_12_;
wire _zz_13_;
wire [0:0] _zz_14_;
wire [0:0] _zz_15_;
wire [22:0] _zz_16_;
reg _zz_1_;
reg _zz_2_;
reg lineLoader_fire;
reg lineLoader_valid;
reg [31:0] lineLoader_address;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [6:0] lineLoader_flushCounter;
reg _zz_3_;
reg lineLoader_cmdSent;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
reg [2:0] lineLoader_wordIndex;
wire lineLoader_write_tag_0_valid;
wire [5:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [20:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [8:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire _zz_4_;
wire [5:0] _zz_5_;
wire _zz_6_;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [20:0] fetchStage_read_waysValues_0_tag_address;
wire [22:0] _zz_7_;
wire [8:0] _zz_8_;
wire _zz_9_;
wire [31:0] fetchStage_read_waysValues_0_data;
wire fetchStage_hit_hits_0;
wire fetchStage_hit_valid;
wire fetchStage_hit_error;
wire [31:0] fetchStage_hit_data;
wire [31:0] fetchStage_hit_word;
reg [31:0] io_cpu_fetch_data_regNextWhen;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_hit_valid;
reg decodeStage_hit_error;
(* ram_style = "block" *) reg [22:0] ways_0_tags [0:63];
(* ram_style = "block" *) reg [31:0] ways_0_datas [0:511];
assign _zz_12_ = (! lineLoader_flushCounter[6]);
assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign _zz_14_ = _zz_7_[0 : 0];
assign _zz_15_ = _zz_7_[1 : 1];
assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @ (posedge clk) begin
if(_zz_2_) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_;
end
end
always @ (posedge clk) begin
if(_zz_6_) begin
_zz_10_ <= ways_0_tags[_zz_5_];
end
end
always @ (posedge clk) begin
if(_zz_1_) begin
ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @ (posedge clk) begin
if(_zz_9_) begin
_zz_11_ <= ways_0_datas[_zz_8_];
end
end
always @ (*) begin
_zz_1_ = 1'b0;
if(lineLoader_write_data_0_valid)begin
_zz_1_ = 1'b1;
end
end
always @ (*) begin
_zz_2_ = 1'b0;
if(lineLoader_write_tag_0_valid)begin
_zz_2_ = 1'b1;
end
end
assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy;
always @ (*) begin
lineLoader_fire = 1'b0;
if(io_mem_rsp_valid)begin
if((lineLoader_wordIndex == (3'b111)))begin
lineLoader_fire = 1'b1;
end
end
end
always @ (*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(_zz_12_)begin
io_cpu_prefetch_haltIt = 1'b1;
end
if((! _zz_3_))begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(io_flush)begin
io_cpu_prefetch_haltIt = 1'b1;
end
end
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)};
assign io_mem_cmd_payload_size = (3'b101);
always @ (*) begin
lineLoader_wayToAllocate_willIncrement = 1'b0;
if((! lineLoader_valid))begin
lineLoader_wayToAllocate_willIncrement = 1'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign _zz_4_ = 1'b1;
assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[6]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign _zz_5_ = io_cpu_prefetch_pc[10 : 5];
assign _zz_6_ = (! io_cpu_fetch_isStuck);
assign _zz_7_ = _zz_10_;
assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0];
assign fetchStage_read_waysValues_0_tag_address = _zz_7_[22 : 2];
assign _zz_8_ = io_cpu_prefetch_pc[10 : 2];
assign _zz_9_ = (! io_cpu_fetch_isStuck);
assign fetchStage_read_waysValues_0_data = _zz_11_;
assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 11]));
assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0));
assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
assign fetchStage_hit_data = fetchStage_read_waysValues_0_data;
assign fetchStage_hit_word = fetchStage_hit_data[31 : 0];
assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word);
assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid;
assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc;
assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0;
assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved);
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress;
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = decodeStage_hit_error;
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
always @ (posedge clk) begin
if(reset) begin
lineLoader_valid <= 1'b0;
lineLoader_hadError <= 1'b0;
lineLoader_flushPending <= 1'b1;
lineLoader_cmdSent <= 1'b0;
lineLoader_wordIndex <= (3'b000);
end else begin
if(lineLoader_fire)begin
lineLoader_valid <= 1'b0;
end
if(lineLoader_fire)begin
lineLoader_hadError <= 1'b0;
end
if(io_cpu_fill_valid)begin
lineLoader_valid <= 1'b1;
end
if(io_flush)begin
lineLoader_flushPending <= 1'b1;
end
if(_zz_13_)begin
lineLoader_flushPending <= 1'b0;
end
if((io_mem_cmd_valid && io_mem_cmd_ready))begin
lineLoader_cmdSent <= 1'b1;
end
if(lineLoader_fire)begin
lineLoader_cmdSent <= 1'b0;
end
if(io_mem_rsp_valid)begin
lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001));
if(io_mem_rsp_payload_error)begin
lineLoader_hadError <= 1'b1;
end
end
end
end
always @ (posedge clk) begin
if(io_cpu_fill_valid)begin
lineLoader_address <= io_cpu_fill_payload;
end
if(_zz_12_)begin
lineLoader_flushCounter <= (lineLoader_flushCounter + (7'b0000001));
end
_zz_3_ <= lineLoader_flushCounter[6];
if(_zz_13_)begin
lineLoader_flushCounter <= (7'b0000000);
end
if((! io_cpu_decode_isStuck))begin
io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
end
if((! io_cpu_decode_isStuck))begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling;
end
if((! io_cpu_decode_isStuck))begin
decodeStage_hit_valid <= fetchStage_hit_valid;
end
if((! io_cpu_decode_isStuck))begin
decodeStage_hit_error <= fetchStage_hit_error;
end
end
endmodule
module VexRiscv (
input [31:0] externalResetVector,
input timerInterrupt,
input softwareInterrupt,
input [31:0] externalInterruptArray,
output reg iBusWishbone_CYC,
output reg iBusWishbone_STB,
input iBusWishbone_ACK,
output iBusWishbone_WE,
output [29:0] iBusWishbone_ADR,
input [31:0] iBusWishbone_DAT_MISO,
output [31:0] iBusWishbone_DAT_MOSI,
output [3:0] iBusWishbone_SEL,
input iBusWishbone_ERR,
output [1:0] iBusWishbone_BTE,
output [2:0] iBusWishbone_CTI,
output dBusWishbone_CYC,
output dBusWishbone_STB,
input dBusWishbone_ACK,
output dBusWishbone_WE,
output [29:0] dBusWishbone_ADR,
input [31:0] dBusWishbone_DAT_MISO,
output [31:0] dBusWishbone_DAT_MOSI,
output reg [3:0] dBusWishbone_SEL,
input dBusWishbone_ERR,
output [1:0] dBusWishbone_BTE,
output [2:0] dBusWishbone_CTI,
input clk,
input reset);
wire _zz_205_;
wire _zz_206_;
wire _zz_207_;
wire _zz_208_;
wire [31:0] _zz_209_;
wire _zz_210_;
wire _zz_211_;
wire _zz_212_;
reg _zz_213_;
reg [31:0] _zz_214_;
reg [31:0] _zz_215_;
reg [31:0] _zz_216_;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt;
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress;
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation;
wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire _zz_217_;
wire _zz_218_;
wire _zz_219_;
wire _zz_220_;
wire _zz_221_;
wire _zz_222_;
wire _zz_223_;
wire _zz_224_;
wire _zz_225_;
wire _zz_226_;
wire _zz_227_;
wire _zz_228_;
wire _zz_229_;
wire _zz_230_;
wire _zz_231_;
wire _zz_232_;
wire _zz_233_;
wire _zz_234_;
wire _zz_235_;
wire [1:0] _zz_236_;
wire _zz_237_;
wire _zz_238_;
wire _zz_239_;
wire _zz_240_;
wire _zz_241_;
wire _zz_242_;
wire _zz_243_;
wire _zz_244_;
wire _zz_245_;
wire _zz_246_;
wire _zz_247_;
wire _zz_248_;
wire _zz_249_;
wire _zz_250_;
wire _zz_251_;
wire _zz_252_;
wire [1:0] _zz_253_;
wire _zz_254_;
wire [4:0] _zz_255_;
wire [2:0] _zz_256_;
wire [31:0] _zz_257_;
wire [11:0] _zz_258_;
wire [31:0] _zz_259_;
wire [19:0] _zz_260_;
wire [11:0] _zz_261_;
wire [31:0] _zz_262_;
wire [31:0] _zz_263_;
wire [19:0] _zz_264_;
wire [11:0] _zz_265_;
wire [2:0] _zz_266_;
wire [0:0] _zz_267_;
wire [0:0] _zz_268_;
wire [0:0] _zz_269_;
wire [0:0] _zz_270_;
wire [0:0] _zz_271_;
wire [0:0] _zz_272_;
wire [0:0] _zz_273_;
wire [0:0] _zz_274_;
wire [0:0] _zz_275_;
wire [0:0] _zz_276_;
wire [0:0] _zz_277_;
wire [0:0] _zz_278_;
wire [0:0] _zz_279_;
wire [0:0] _zz_280_;
wire [0:0] _zz_281_;
wire [0:0] _zz_282_;
wire [0:0] _zz_283_;
wire [2:0] _zz_284_;
wire [4:0] _zz_285_;
wire [11:0] _zz_286_;
wire [11:0] _zz_287_;
wire [31:0] _zz_288_;
wire [31:0] _zz_289_;
wire [31:0] _zz_290_;
wire [31:0] _zz_291_;
wire [31:0] _zz_292_;
wire [31:0] _zz_293_;
wire [31:0] _zz_294_;
wire [31:0] _zz_295_;
wire [32:0] _zz_296_;
wire [11:0] _zz_297_;
wire [19:0] _zz_298_;
wire [11:0] _zz_299_;
wire [31:0] _zz_300_;
wire [31:0] _zz_301_;
wire [31:0] _zz_302_;
wire [11:0] _zz_303_;
wire [19:0] _zz_304_;
wire [11:0] _zz_305_;
wire [2:0] _zz_306_;
wire [1:0] _zz_307_;
wire [1:0] _zz_308_;
wire [1:0] _zz_309_;
wire [1:0] _zz_310_;
wire [0:0] _zz_311_;
wire [5:0] _zz_312_;
wire [33:0] _zz_313_;
wire [32:0] _zz_314_;
wire [33:0] _zz_315_;
wire [32:0] _zz_316_;
wire [33:0] _zz_317_;
wire [32:0] _zz_318_;
wire [0:0] _zz_319_;
wire [5:0] _zz_320_;
wire [32:0] _zz_321_;
wire [32:0] _zz_322_;
wire [31:0] _zz_323_;
wire [31:0] _zz_324_;
wire [32:0] _zz_325_;
wire [32:0] _zz_326_;
wire [32:0] _zz_327_;
wire [0:0] _zz_328_;
wire [32:0] _zz_329_;
wire [0:0] _zz_330_;
wire [32:0] _zz_331_;
wire [0:0] _zz_332_;
wire [31:0] _zz_333_;
wire [0:0] _zz_334_;
wire [0:0] _zz_335_;
wire [0:0] _zz_336_;
wire [0:0] _zz_337_;
wire [0:0] _zz_338_;
wire [0:0] _zz_339_;
wire [26:0] _zz_340_;
wire [6:0] _zz_341_;
wire _zz_342_;
wire _zz_343_;
wire [2:0] _zz_344_;
wire _zz_345_;
wire _zz_346_;
wire _zz_347_;
wire _zz_348_;
wire [0:0] _zz_349_;
wire [0:0] _zz_350_;
wire [0:0] _zz_351_;
wire [0:0] _zz_352_;
wire _zz_353_;
wire [0:0] _zz_354_;
wire [23:0] _zz_355_;
wire [31:0] _zz_356_;
wire [31:0] _zz_357_;
wire _zz_358_;
wire [0:0] _zz_359_;
wire [0:0] _zz_360_;
wire [0:0] _zz_361_;
wire [0:0] _zz_362_;
wire [1:0] _zz_363_;
wire [1:0] _zz_364_;
wire _zz_365_;
wire [0:0] _zz_366_;
wire [20:0] _zz_367_;
wire [31:0] _zz_368_;
wire [31:0] _zz_369_;
wire [31:0] _zz_370_;
wire [31:0] _zz_371_;
wire _zz_372_;
wire [0:0] _zz_373_;
wire [1:0] _zz_374_;
wire [0:0] _zz_375_;
wire [0:0] _zz_376_;
wire _zz_377_;
wire [0:0] _zz_378_;
wire [17:0] _zz_379_;
wire [31:0] _zz_380_;
wire [31:0] _zz_381_;
wire [31:0] _zz_382_;
wire [31:0] _zz_383_;
wire [31:0] _zz_384_;
wire [31:0] _zz_385_;
wire [31:0] _zz_386_;
wire [31:0] _zz_387_;
wire [0:0] _zz_388_;
wire [0:0] _zz_389_;
wire [5:0] _zz_390_;
wire [5:0] _zz_391_;
wire _zz_392_;
wire [0:0] _zz_393_;
wire [14:0] _zz_394_;
wire [31:0] _zz_395_;
wire [31:0] _zz_396_;
wire _zz_397_;
wire [0:0] _zz_398_;
wire [2:0] _zz_399_;
wire _zz_400_;
wire _zz_401_;
wire [0:0] _zz_402_;
wire [2:0] _zz_403_;
wire [0:0] _zz_404_;
wire [0:0] _zz_405_;
wire _zz_406_;
wire [0:0] _zz_407_;
wire [11:0] _zz_408_;
wire [31:0] _zz_409_;
wire [31:0] _zz_410_;
wire [31:0] _zz_411_;
wire _zz_412_;
wire [0:0] _zz_413_;
wire [0:0] _zz_414_;
wire [31:0] _zz_415_;
wire [31:0] _zz_416_;
wire [31:0] _zz_417_;
wire [31:0] _zz_418_;
wire _zz_419_;
wire [0:0] _zz_420_;
wire [0:0] _zz_421_;
wire [31:0] _zz_422_;
wire [31:0] _zz_423_;
wire [0:0] _zz_424_;
wire [0:0] _zz_425_;
wire [0:0] _zz_426_;
wire [0:0] _zz_427_;
wire _zz_428_;
wire [0:0] _zz_429_;
wire [9:0] _zz_430_;
wire [31:0] _zz_431_;
wire [31:0] _zz_432_;
wire [31:0] _zz_433_;
wire [31:0] _zz_434_;
wire [31:0] _zz_435_;
wire [31:0] _zz_436_;
wire [31:0] _zz_437_;
wire [31:0] _zz_438_;
wire [31:0] _zz_439_;
wire [31:0] _zz_440_;
wire [31:0] _zz_441_;
wire [31:0] _zz_442_;
wire [31:0] _zz_443_;
wire [31:0] _zz_444_;
wire _zz_445_;
wire [0:0] _zz_446_;
wire [0:0] _zz_447_;
wire _zz_448_;
wire [0:0] _zz_449_;
wire [7:0] _zz_450_;
wire _zz_451_;
wire [0:0] _zz_452_;
wire [0:0] _zz_453_;
wire [0:0] _zz_454_;
wire [0:0] _zz_455_;
wire [0:0] _zz_456_;
wire [0:0] _zz_457_;
wire _zz_458_;
wire [0:0] _zz_459_;
wire [3:0] _zz_460_;
wire [31:0] _zz_461_;
wire [31:0] _zz_462_;
wire [31:0] _zz_463_;
wire [31:0] _zz_464_;
wire [31:0] _zz_465_;
wire _zz_466_;
wire _zz_467_;
wire [0:0] _zz_468_;
wire [1:0] _zz_469_;
wire [2:0] _zz_470_;
wire [2:0] _zz_471_;
wire _zz_472_;
wire [0:0] _zz_473_;
wire [0:0] _zz_474_;
wire [31:0] _zz_475_;
wire [31:0] _zz_476_;
wire [31:0] _zz_477_;
wire [31:0] _zz_478_;
wire [31:0] _zz_479_;
wire _zz_480_;
wire _zz_481_;
wire [31:0] _zz_482_;
wire [31:0] _zz_483_;
wire [0:0] _zz_484_;
wire [0:0] _zz_485_;
wire _zz_486_;
wire [31:0] _zz_487_;
wire [31:0] _zz_488_;
wire [31:0] _zz_489_;
wire _zz_490_;
wire [0:0] _zz_491_;
wire [10:0] _zz_492_;
wire [31:0] _zz_493_;
wire [31:0] _zz_494_;
wire [31:0] _zz_495_;
wire _zz_496_;
wire [0:0] _zz_497_;
wire [4:0] _zz_498_;
wire [31:0] _zz_499_;
wire [31:0] _zz_500_;
wire [31:0] _zz_501_;
wire [31:0] _zz_502_;
wire [31:0] _zz_503_;
wire _zz_504_;
wire _zz_505_;
wire _zz_506_;
wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL;
wire `AluCtrlEnum_defaultEncoding_type _zz_1_;
wire `AluCtrlEnum_defaultEncoding_type _zz_2_;
wire `AluCtrlEnum_defaultEncoding_type _zz_3_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_4_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_5_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_6_;
wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_defaultEncoding_type _zz_7_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_8_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_9_;
wire decode_IS_RS2_SIGNED;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire decode_IS_RS1_SIGNED;
wire decode_CSR_READ_OPCODE;
wire decode_IS_DIV;
wire [1:0] memory_MEMORY_ADDRESS_LOW;
wire [1:0] execute_MEMORY_ADDRESS_LOW;
wire decode_IS_MUL;
wire [31:0] execute_BRANCH_CALC;
wire `BranchCtrlEnum_defaultEncoding_type _zz_10_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_11_;
wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_defaultEncoding_type _zz_12_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_13_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_14_;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_SRC2_FORCE_ZERO;
wire decode_CSR_WRITE_OPCODE;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire execute_BRANCH_DO;
wire decode_SRC_LESS_UNSIGNED;
wire `EnvCtrlEnum_defaultEncoding_type _zz_15_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_16_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_17_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_18_;
wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_19_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_20_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_21_;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire decode_MEMORY_STORE;
wire decode_PREDICTION_HAD_BRANCHED2;
wire decode_IS_CSR;
wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_24_;
wire [31:0] memory_MEMORY_READ_DATA;
wire execute_IS_RS1_SIGNED;
wire execute_IS_DIV;
wire execute_IS_MUL;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire memory_IS_MUL;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_25_;
wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_26_;
wire _zz_27_;
wire _zz_28_;
wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_defaultEncoding_type _zz_29_;
wire [31:0] memory_BRANCH_CALC;
wire memory_BRANCH_DO;
wire [31:0] _zz_30_;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
wire _zz_31_;
wire [31:0] execute_RS1;
wire execute_BRANCH_COND_RESULT;
wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_defaultEncoding_type _zz_32_;
wire _zz_33_;
wire _zz_34_;
wire decode_RS2_USE;
wire decode_RS1_USE;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
reg [31:0] _zz_35_;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
reg [31:0] _zz_36_;
wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_37_;
wire _zz_38_;
wire [31:0] _zz_39_;
wire [31:0] _zz_40_;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_41_;
wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_defaultEncoding_type _zz_42_;
wire [31:0] _zz_43_;
wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_defaultEncoding_type _zz_44_;
wire [31:0] _zz_45_;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire _zz_46_;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL;
wire `AluCtrlEnum_defaultEncoding_type _zz_47_;
wire [31:0] _zz_48_;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_49_;
wire [31:0] _zz_50_;
wire _zz_51_;
reg _zz_52_;
wire [31:0] _zz_53_;
wire [31:0] _zz_54_;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire decode_LEGAL_INSTRUCTION;
wire decode_INSTRUCTION_READY;
wire _zz_55_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_56_;
wire _zz_57_;
wire _zz_58_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_59_;
wire _zz_60_;
wire _zz_61_;
wire _zz_62_;
wire _zz_63_;
wire _zz_64_;
wire _zz_65_;
wire _zz_66_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_67_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_68_;
wire _zz_69_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_70_;
wire _zz_71_;
wire `AluCtrlEnum_defaultEncoding_type _zz_72_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_73_;
wire _zz_74_;
wire _zz_75_;
wire _zz_76_;
wire _zz_77_;
wire _zz_78_;
wire writeBack_MEMORY_STORE;
reg [31:0] _zz_79_;
wire writeBack_MEMORY_ENABLE;
wire [1:0] writeBack_MEMORY_ADDRESS_LOW;
wire [31:0] writeBack_MEMORY_READ_DATA;
wire memory_MMU_FAULT;
wire [31:0] memory_MMU_RSP_physicalAddress;
wire memory_MMU_RSP_isIoAccess;
wire memory_MMU_RSP_allowRead;
wire memory_MMU_RSP_allowWrite;
wire memory_MMU_RSP_allowExecute;
wire memory_MMU_RSP_exception;
wire memory_MMU_RSP_refilling;
wire [31:0] memory_PC;
wire memory_ALIGNEMENT_FAULT;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_MEMORY_STORE;
wire memory_MEMORY_ENABLE;
wire [31:0] _zz_80_;
wire [31:0] _zz_81_;
wire _zz_82_;
wire _zz_83_;
wire _zz_84_;
wire _zz_85_;
wire _zz_86_;
wire _zz_87_;
wire execute_MMU_FAULT;
wire [31:0] execute_MMU_RSP_physicalAddress;
wire execute_MMU_RSP_isIoAccess;
wire execute_MMU_RSP_allowRead;
wire execute_MMU_RSP_allowWrite;
wire execute_MMU_RSP_allowExecute;
wire execute_MMU_RSP_exception;
wire execute_MMU_RSP_refilling;
wire _zz_88_;
wire [31:0] execute_SRC_ADD;
wire [1:0] _zz_89_;
wire [31:0] execute_RS2;
wire [31:0] execute_INSTRUCTION;
wire execute_MEMORY_STORE;
wire execute_MEMORY_ENABLE;
wire execute_ALIGNEMENT_FAULT;
wire _zz_90_;
wire decode_MEMORY_ENABLE;
wire decode_FLUSH_ALL;
reg IBusCachedPlugin_rsp_issueDetected;
reg _zz_91_;
reg _zz_92_;
reg _zz_93_;
wire [31:0] _zz_94_;
wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_defaultEncoding_type _zz_95_;
wire [31:0] decode_INSTRUCTION;
reg [31:0] _zz_96_;
reg [31:0] _zz_97_;
wire [31:0] decode_PC;
wire [31:0] _zz_98_;
wire [31:0] _zz_99_;
wire [31:0] _zz_100_;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
reg decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
wire decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
wire execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
wire execute_arbitration_flushIt;
wire execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
reg memory_arbitration_flushIt;
reg memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
wire writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
wire writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusCachedPlugin_fetcherHalt;
reg IBusCachedPlugin_fetcherflushIt;
reg IBusCachedPlugin_incomingInstruction;
wire IBusCachedPlugin_predictionJumpInterface_valid;
(* syn_keep , keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire IBusCachedPlugin_decodePrediction_rsp_wasWrong;
wire IBusCachedPlugin_pcValids_0;
wire IBusCachedPlugin_pcValids_1;
wire IBusCachedPlugin_pcValids_2;
wire IBusCachedPlugin_pcValids_3;
wire IBusCachedPlugin_redoBranch_valid;
wire [31:0] IBusCachedPlugin_redoBranch_payload;
reg IBusCachedPlugin_decodeExceptionPort_valid;
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
wire IBusCachedPlugin_mmuBus_cmd_isValid;
wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress;
wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation;
wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire IBusCachedPlugin_mmuBus_rsp_allowRead;
wire IBusCachedPlugin_mmuBus_rsp_allowWrite;
wire IBusCachedPlugin_mmuBus_rsp_allowExecute;
wire IBusCachedPlugin_mmuBus_rsp_exception;
wire IBusCachedPlugin_mmuBus_rsp_refilling;
wire IBusCachedPlugin_mmuBus_end;
wire IBusCachedPlugin_mmuBus_busy;
reg DBusSimplePlugin_memoryExceptionPort_valid;
reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code;
wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr;
wire DBusSimplePlugin_mmuBus_cmd_isValid;
wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress;
wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation;
wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress;
wire DBusSimplePlugin_mmuBus_rsp_isIoAccess;
wire DBusSimplePlugin_mmuBus_rsp_allowRead;
wire DBusSimplePlugin_mmuBus_rsp_allowWrite;
wire DBusSimplePlugin_mmuBus_rsp_allowExecute;
wire DBusSimplePlugin_mmuBus_rsp_exception;
wire DBusSimplePlugin_mmuBus_rsp_refilling;
wire DBusSimplePlugin_mmuBus_end;
wire DBusSimplePlugin_mmuBus_busy;
reg DBusSimplePlugin_redoBranch_valid;
wire [31:0] DBusSimplePlugin_redoBranch_payload;
wire decodeExceptionPort_valid;
wire [3:0] decodeExceptionPort_payload_code;
wire [31:0] decodeExceptionPort_payload_badAddr;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
wire BranchPlugin_branchExceptionPort_valid;
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire externalInterrupt;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
wire CsrPlugin_forceMachineWire;
wire CsrPlugin_allowInterrupts;
wire CsrPlugin_allowException;
wire IBusCachedPlugin_jump_pcLoad_valid;
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
wire [4:0] _zz_101_;
wire [4:0] _zz_102_;
wire _zz_103_;
wire _zz_104_;
wire _zz_105_;
wire _zz_106_;
wire IBusCachedPlugin_fetchPc_output_valid;
wire IBusCachedPlugin_fetchPc_output_ready;
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusCachedPlugin_fetchPc_corrected;
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
reg IBusCachedPlugin_fetchPc_booted;
reg IBusCachedPlugin_fetchPc_inc;
reg [31:0] IBusCachedPlugin_fetchPc_pc;
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
wire IBusCachedPlugin_iBusRsp_stages_0_inputSample;
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
wire IBusCachedPlugin_iBusRsp_stages_1_inputSample;
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid;
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid;
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload;
reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt;
wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample;
wire _zz_107_;
wire _zz_108_;
wire _zz_109_;
wire _zz_110_;
wire _zz_111_;
reg _zz_112_;
wire _zz_113_;
reg _zz_114_;
reg [31:0] _zz_115_;
reg IBusCachedPlugin_iBusRsp_readyForError;
wire IBusCachedPlugin_iBusRsp_decodeInput_valid;
wire IBusCachedPlugin_iBusRsp_decodeInput_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc;
wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error;
wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst;
wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc;
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
reg IBusCachedPlugin_injector_nextPcCalc_valids_3;
reg IBusCachedPlugin_injector_nextPcCalc_valids_4;
reg IBusCachedPlugin_injector_decodeRemoved;
wire _zz_116_;
reg [18:0] _zz_117_;
wire _zz_118_;
reg [10:0] _zz_119_;
wire _zz_120_;
reg [18:0] _zz_121_;
reg _zz_122_;
wire _zz_123_;
reg [10:0] _zz_124_;
wire _zz_125_;
reg [18:0] _zz_126_;
wire iBus_cmd_valid;
wire iBus_cmd_ready;
reg [31:0] iBus_cmd_payload_address;
wire [2:0] iBus_cmd_payload_size;
wire iBus_rsp_valid;
wire [31:0] iBus_rsp_payload_data;
wire iBus_rsp_payload_error;
wire [31:0] _zz_127_;
reg [31:0] IBusCachedPlugin_rspCounter;
wire IBusCachedPlugin_s0_tightlyCoupledHit;
reg IBusCachedPlugin_s1_tightlyCoupledHit;
reg IBusCachedPlugin_s2_tightlyCoupledHit;
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
reg IBusCachedPlugin_rsp_redoFetch;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [1:0] dBus_cmd_payload_size;
wire dBus_rsp_ready;
wire dBus_rsp_error;
wire [31:0] dBus_rsp_data;
wire _zz_128_;
reg execute_DBusSimplePlugin_skipCmd;
reg [31:0] _zz_129_;
reg [3:0] _zz_130_;
wire [3:0] execute_DBusSimplePlugin_formalMask;
reg [31:0] writeBack_DBusSimplePlugin_rspShifted;
wire _zz_131_;
reg [31:0] _zz_132_;
wire _zz_133_;
reg [31:0] _zz_134_;
reg [31:0] writeBack_DBusSimplePlugin_rspFormated;
wire [29:0] _zz_135_;
wire _zz_136_;
wire _zz_137_;
wire _zz_138_;
wire _zz_139_;
wire _zz_140_;
wire _zz_141_;
wire `ShiftCtrlEnum_defaultEncoding_type _zz_142_;
wire `AluCtrlEnum_defaultEncoding_type _zz_143_;
wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_144_;
wire `BranchCtrlEnum_defaultEncoding_type _zz_145_;
wire `EnvCtrlEnum_defaultEncoding_type _zz_146_;
wire `Src2CtrlEnum_defaultEncoding_type _zz_147_;
wire `Src1CtrlEnum_defaultEncoding_type _zz_148_;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_149_;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_150_;
reg [31:0] _zz_151_;
wire _zz_152_;
reg [19:0] _zz_153_;
wire _zz_154_;
reg [19:0] _zz_155_;
reg [31:0] _zz_156_;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
reg execute_LightShifterPlugin_isActive;
wire execute_LightShifterPlugin_isShift;
reg [4:0] execute_LightShifterPlugin_amplitudeReg;
wire [4:0] execute_LightShifterPlugin_amplitude;
wire [31:0] execute_LightShifterPlugin_shiftInput;
wire execute_LightShifterPlugin_done;
reg [31:0] _zz_157_;
reg _zz_158_;
reg _zz_159_;
wire _zz_160_;
reg _zz_161_;
reg [4:0] _zz_162_;
reg [31:0] _zz_163_;
wire _zz_164_;
wire _zz_165_;
wire _zz_166_;
wire _zz_167_;
wire _zz_168_;
wire _zz_169_;
wire execute_BranchPlugin_eq;
wire [2:0] _zz_170_;
reg _zz_171_;
reg _zz_172_;
wire _zz_173_;
reg [19:0] _zz_174_;
wire _zz_175_;
reg [10:0] _zz_176_;
wire _zz_177_;
reg [18:0] _zz_178_;
reg _zz_179_;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_180_;
reg [19:0] _zz_181_;
wire _zz_182_;
reg [10:0] _zz_183_;
wire _zz_184_;
reg [18:0] _zz_185_;
wire [31:0] execute_BranchPlugin_branchAdder;
wire [1:0] CsrPlugin_misa_base;
wire [25:0] CsrPlugin_misa_extensions;
reg [1:0] CsrPlugin_mtvec_mode;
reg [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_186_;
wire _zz_187_;
wire _zz_188_;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
wire [1:0] _zz_189_;
wire _zz_190_;
wire [1:0] _zz_191_;
wire _zz_192_;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire CsrPlugin_exception;
wire CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_done;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException;
reg [1:0] CsrPlugin_targetPrivilege;
reg [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
wire execute_CsrPlugin_inWfi /* verilator public */ ;
reg execute_CsrPlugin_wfiWake;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
reg [31:0] execute_CsrPlugin_readData;
wire execute_CsrPlugin_writeInstruction;
wire execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
reg [31:0] execute_CsrPlugin_writeData;
wire [11:0] execute_CsrPlugin_csrAddress;
reg [32:0] memory_MulDivIterativePlugin_rs1;
reg [31:0] memory_MulDivIterativePlugin_rs2;
reg [64:0] memory_MulDivIterativePlugin_accumulator;
reg memory_MulDivIterativePlugin_mul_counter_willIncrement;
reg memory_MulDivIterativePlugin_mul_counter_willClear;
reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext;
reg [5:0] memory_MulDivIterativePlugin_mul_counter_value;
wire memory_MulDivIterativePlugin_mul_willOverflowIfInc;
wire memory_MulDivIterativePlugin_mul_counter_willOverflow;
reg memory_MulDivIterativePlugin_div_needRevert;
reg memory_MulDivIterativePlugin_div_counter_willIncrement;
reg memory_MulDivIterativePlugin_div_counter_willClear;
reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext;
reg [5:0] memory_MulDivIterativePlugin_div_counter_value;
wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc;
wire memory_MulDivIterativePlugin_div_counter_willOverflow;
reg memory_MulDivIterativePlugin_div_done;
reg [31:0] memory_MulDivIterativePlugin_div_result;
wire [31:0] _zz_193_;
wire [32:0] _zz_194_;
wire [32:0] _zz_195_;
wire [31:0] _zz_196_;
wire _zz_197_;
wire _zz_198_;
reg [32:0] _zz_199_;
reg [31:0] externalInterruptArray_regNext;
reg [31:0] _zz_200_;
wire [31:0] _zz_201_;
reg [31:0] decode_to_execute_INSTRUCTION;
reg [31:0] execute_to_memory_INSTRUCTION;
reg [31:0] memory_to_writeBack_INSTRUCTION;
reg execute_to_memory_ALIGNEMENT_FAULT;
reg [31:0] memory_to_writeBack_MEMORY_READ_DATA;
reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL;
reg decode_to_execute_IS_CSR;
reg [31:0] decode_to_execute_PC;
reg [31:0] execute_to_memory_PC;
reg [31:0] memory_to_writeBack_PC;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
reg decode_to_execute_MEMORY_STORE;
reg execute_to_memory_MEMORY_STORE;
reg memory_to_writeBack_MEMORY_STORE;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL;
reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL;
reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL;
reg decode_to_execute_REGFILE_WRITE_VALID;
reg execute_to_memory_REGFILE_WRITE_VALID;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
reg decode_to_execute_SRC_LESS_UNSIGNED;
reg execute_to_memory_BRANCH_DO;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
reg decode_to_execute_CSR_WRITE_OPCODE;
reg [31:0] decode_to_execute_RS1;
reg decode_to_execute_SRC2_FORCE_ZERO;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL;
reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL;
reg decode_to_execute_MEMORY_ENABLE;
reg execute_to_memory_MEMORY_ENABLE;
reg memory_to_writeBack_MEMORY_ENABLE;
reg decode_to_execute_SRC_USE_SUB_LESS;
reg execute_to_memory_MMU_FAULT;
reg [31:0] execute_to_memory_BRANCH_CALC;
reg [31:0] decode_to_execute_RS2;
reg decode_to_execute_IS_MUL;
reg execute_to_memory_IS_MUL;
reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW;
reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW;
reg decode_to_execute_IS_DIV;
reg execute_to_memory_IS_DIV;
reg decode_to_execute_CSR_READ_OPCODE;
reg decode_to_execute_IS_RS1_SIGNED;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
reg [31:0] execute_to_memory_MMU_RSP_physicalAddress;
reg execute_to_memory_MMU_RSP_isIoAccess;
reg execute_to_memory_MMU_RSP_allowRead;
reg execute_to_memory_MMU_RSP_allowWrite;
reg execute_to_memory_MMU_RSP_allowExecute;
reg execute_to_memory_MMU_RSP_exception;
reg execute_to_memory_MMU_RSP_refilling;
reg decode_to_execute_IS_RS2_SIGNED;
reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL;
reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL;
reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL;
reg [2:0] _zz_202_;
reg _zz_203_;
reg [31:0] iBusWishbone_DAT_MISO_regNext;
wire dBus_cmd_halfPipe_valid;
wire dBus_cmd_halfPipe_ready;
wire dBus_cmd_halfPipe_payload_wr;
wire [31:0] dBus_cmd_halfPipe_payload_address;
wire [31:0] dBus_cmd_halfPipe_payload_data;
wire [1:0] dBus_cmd_halfPipe_payload_size;
reg dBus_cmd_halfPipe_regs_valid;
reg dBus_cmd_halfPipe_regs_ready;
reg dBus_cmd_halfPipe_regs_payload_wr;
reg [31:0] dBus_cmd_halfPipe_regs_payload_address;
reg [31:0] dBus_cmd_halfPipe_regs_payload_data;
reg [1:0] dBus_cmd_halfPipe_regs_payload_size;
reg [3:0] _zz_204_;
`ifndef SYNTHESIS
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_1__string;
reg [63:0] _zz_2__string;
reg [63:0] _zz_3__string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_4__string;
reg [39:0] _zz_5__string;
reg [39:0] _zz_6__string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_7__string;
reg [23:0] _zz_8__string;
reg [23:0] _zz_9__string;
reg [31:0] _zz_10__string;
reg [31:0] _zz_11__string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_12__string;
reg [95:0] _zz_13__string;
reg [95:0] _zz_14__string;
reg [31:0] _zz_15__string;
reg [31:0] _zz_16__string;
reg [31:0] _zz_17__string;
reg [31:0] _zz_18__string;
reg [31:0] decode_ENV_CTRL_string;
reg [31:0] _zz_19__string;
reg [31:0] _zz_20__string;
reg [31:0] _zz_21__string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_22__string;
reg [71:0] _zz_23__string;
reg [71:0] _zz_24__string;
reg [31:0] memory_ENV_CTRL_string;
reg [31:0] _zz_25__string;
reg [31:0] execute_ENV_CTRL_string;
reg [31:0] _zz_26__string;
reg [31:0] writeBack_ENV_CTRL_string;
reg [31:0] _zz_29__string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_32__string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_37__string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_42__string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_44__string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_47__string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_49__string;
reg [95:0] _zz_56__string;
reg [23:0] _zz_59__string;
reg [31:0] _zz_67__string;
reg [31:0] _zz_68__string;
reg [39:0] _zz_70__string;
reg [63:0] _zz_72__string;
reg [71:0] _zz_73__string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_95__string;
reg [71:0] _zz_142__string;
reg [63:0] _zz_143__string;
reg [39:0] _zz_144__string;
reg [31:0] _zz_145__string;
reg [31:0] _zz_146__string;
reg [23:0] _zz_147__string;
reg [95:0] _zz_148__string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_ENV_CTRL_string;
reg [31:0] execute_to_memory_ENV_CTRL_string;
reg [31:0] memory_to_writeBack_ENV_CTRL_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
`endif
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_217_ = (memory_arbitration_isValid && memory_IS_MUL);
assign _zz_218_ = (memory_arbitration_isValid && memory_IS_DIV);
assign _zz_219_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign _zz_220_ = 1'b1;
assign _zz_221_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign _zz_222_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign _zz_223_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000)));
assign _zz_224_ = (execute_arbitration_isValid && execute_IS_CSR);
assign _zz_225_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_91_));
assign _zz_226_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_92_));
assign _zz_227_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_93_));
assign _zz_228_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0));
assign _zz_229_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00));
assign _zz_230_ = (! execute_arbitration_isStuckByOthers);
assign _zz_231_ = (! memory_MulDivIterativePlugin_mul_willOverflowIfInc);
assign _zz_232_ = (! memory_MulDivIterativePlugin_div_done);
assign _zz_233_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2'b00));
assign _zz_234_ = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign _zz_235_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET));
assign _zz_236_ = writeBack_INSTRUCTION[29 : 28];
assign _zz_237_ = (! IBusCachedPlugin_iBusRsp_readyForError);
assign _zz_238_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE));
assign _zz_239_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers))));
assign _zz_240_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign _zz_241_ = (1'b0 || (! 1'b1));
assign _zz_242_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign _zz_243_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign _zz_244_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign _zz_245_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign _zz_246_ = (! memory_arbitration_isStuck);
assign _zz_247_ = (iBus_cmd_valid || (_zz_202_ != (3'b000)));
assign _zz_248_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11)));
assign _zz_249_ = ((_zz_186_ && 1'b1) && (! 1'b0));
assign _zz_250_ = ((_zz_187_ && 1'b1) && (! 1'b0));
assign _zz_251_ = ((_zz_188_ && 1'b1) && (! 1'b0));
assign _zz_252_ = (! dBus_cmd_halfPipe_regs_valid);
assign _zz_253_ = writeBack_INSTRUCTION[13 : 12];
assign _zz_254_ = execute_INSTRUCTION[13];
assign _zz_255_ = (_zz_101_ - (5'b00001));
assign _zz_256_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)};
assign _zz_257_ = {29'd0, _zz_256_};
assign _zz_258_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_259_ = {{_zz_117_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz_260_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz_261_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_262_ = {{_zz_119_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0};
assign _zz_263_ = {{_zz_121_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz_264_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz_265_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_266_ = (memory_MEMORY_STORE ? (3'b110) : (3'b100));
assign _zz_267_ = _zz_135_[0 : 0];
assign _zz_268_ = _zz_135_[1 : 1];
assign _zz_269_ = _zz_135_[2 : 2];
assign _zz_270_ = _zz_135_[3 : 3];
assign _zz_271_ = _zz_135_[8 : 8];
assign _zz_272_ = _zz_135_[11 : 11];
assign _zz_273_ = _zz_135_[15 : 15];
assign _zz_274_ = _zz_135_[16 : 16];
assign _zz_275_ = _zz_135_[17 : 17];
assign _zz_276_ = _zz_135_[18 : 18];
assign _zz_277_ = _zz_135_[19 : 19];
assign _zz_278_ = _zz_135_[20 : 20];
assign _zz_279_ = _zz_135_[21 : 21];
assign _zz_280_ = _zz_135_[24 : 24];
assign _zz_281_ = _zz_135_[26 : 26];
assign _zz_282_ = _zz_135_[29 : 29];
assign _zz_283_ = execute_SRC_LESS;
assign _zz_284_ = (3'b100);
assign _zz_285_ = execute_INSTRUCTION[19 : 15];
assign _zz_286_ = execute_INSTRUCTION[31 : 20];
assign _zz_287_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_288_ = ($signed(_zz_289_) + $signed(_zz_292_));
assign _zz_289_ = ($signed(_zz_290_) + $signed(_zz_291_));
assign _zz_290_ = execute_SRC1;
assign _zz_291_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_292_ = (execute_SRC_USE_SUB_LESS ? _zz_293_ : _zz_294_);
assign _zz_293_ = (32'b00000000000000000000000000000001);
assign _zz_294_ = (32'b00000000000000000000000000000000);
assign _zz_295_ = (_zz_296_ >>> 1);
assign _zz_296_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput};
assign _zz_297_ = execute_INSTRUCTION[31 : 20];
assign _zz_298_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz_299_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_300_ = {_zz_174_,execute_INSTRUCTION[31 : 20]};
assign _zz_301_ = {{_zz_176_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
assign _zz_302_ = {{_zz_178_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
assign _zz_303_ = execute_INSTRUCTION[31 : 20];
assign _zz_304_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz_305_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_306_ = (3'b100);
assign _zz_307_ = (_zz_189_ & (~ _zz_308_));
assign _zz_308_ = (_zz_189_ - (2'b01));
assign _zz_309_ = (_zz_191_ & (~ _zz_310_));
assign _zz_310_ = (_zz_191_ - (2'b01));
assign _zz_311_ = memory_MulDivIterativePlugin_mul_counter_willIncrement;
assign _zz_312_ = {5'd0, _zz_311_};
assign _zz_313_ = (_zz_315_ + _zz_317_);
assign _zz_314_ = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : (33'b000000000000000000000000000000000));
assign _zz_315_ = {{1{_zz_314_[32]}}, _zz_314_};
assign _zz_316_ = _zz_318_;
assign _zz_317_ = {{1{_zz_316_[32]}}, _zz_316_};
assign _zz_318_ = (memory_MulDivIterativePlugin_accumulator >>> 32);
assign _zz_319_ = memory_MulDivIterativePlugin_div_counter_willIncrement;
assign _zz_320_ = {5'd0, _zz_319_};
assign _zz_321_ = {1'd0, memory_MulDivIterativePlugin_rs2};
assign _zz_322_ = {_zz_193_,(! _zz_195_[32])};
assign _zz_323_ = _zz_195_[31:0];
assign _zz_324_ = _zz_194_[31:0];
assign _zz_325_ = _zz_326_;
assign _zz_326_ = _zz_327_;
assign _zz_327_ = ({1'b0,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_196_) : _zz_196_)} + _zz_329_);
assign _zz_328_ = memory_MulDivIterativePlugin_div_needRevert;
assign _zz_329_ = {32'd0, _zz_328_};
assign _zz_330_ = _zz_198_;
assign _zz_331_ = {32'd0, _zz_330_};
assign _zz_332_ = _zz_197_;
assign _zz_333_ = {31'd0, _zz_332_};
assign _zz_334_ = execute_CsrPlugin_writeData[7 : 7];
assign _zz_335_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_336_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_337_ = execute_CsrPlugin_writeData[11 : 11];
assign _zz_338_ = execute_CsrPlugin_writeData[7 : 7];
assign _zz_339_ = execute_CsrPlugin_writeData[3 : 3];
assign _zz_340_ = (iBus_cmd_payload_address >>> 5);
assign _zz_341_ = ({3'd0,_zz_204_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]);
assign _zz_342_ = 1'b1;
assign _zz_343_ = 1'b1;
assign _zz_344_ = {_zz_104_,{_zz_106_,_zz_105_}};
assign _zz_345_ = decode_INSTRUCTION[31];
assign _zz_346_ = decode_INSTRUCTION[31];
assign _zz_347_ = decode_INSTRUCTION[7];
assign _zz_348_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100));
assign _zz_349_ = ((decode_INSTRUCTION & _zz_356_) == (32'b00000000000000000000000000000100));
assign _zz_350_ = _zz_141_;
assign _zz_351_ = ((decode_INSTRUCTION & _zz_357_) == (32'b00000010000000000100000000100000));
assign _zz_352_ = (1'b0);
assign _zz_353_ = ({_zz_358_,{_zz_359_,_zz_360_}} != (3'b000));
assign _zz_354_ = ({_zz_361_,_zz_362_} != (2'b00));
assign _zz_355_ = {(_zz_363_ != _zz_364_),{_zz_365_,{_zz_366_,_zz_367_}}};
assign _zz_356_ = (32'b00000000000000000000000001000100);
assign _zz_357_ = (32'b00000010000000000100000001100100);
assign _zz_358_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000001000000));
assign _zz_359_ = ((decode_INSTRUCTION & _zz_368_) == (32'b00000000000000000000000001000000));
assign _zz_360_ = ((decode_INSTRUCTION & _zz_369_) == (32'b00000000000000000000000000000000));
assign _zz_361_ = _zz_140_;
assign _zz_362_ = _zz_139_;
assign _zz_363_ = {_zz_136_,(_zz_370_ == _zz_371_)};
assign _zz_364_ = (2'b00);
assign _zz_365_ = ({_zz_136_,_zz_372_} != (2'b00));
assign _zz_366_ = ({_zz_373_,_zz_374_} != (3'b000));
assign _zz_367_ = {(_zz_375_ != _zz_376_),{_zz_377_,{_zz_378_,_zz_379_}}};
assign _zz_368_ = (32'b00000000000000000011000001000000);
assign _zz_369_ = (32'b00000000000000000000000000111000);
assign _zz_370_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000));
assign _zz_371_ = (32'b00000000000000000000000000100000);
assign _zz_372_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000));
assign _zz_373_ = ((decode_INSTRUCTION & _zz_380_) == (32'b00000000000000000000000001000000));
assign _zz_374_ = {(_zz_381_ == _zz_382_),(_zz_383_ == _zz_384_)};
assign _zz_375_ = ((decode_INSTRUCTION & _zz_385_) == (32'b00000000000000000000000000100000));
assign _zz_376_ = (1'b0);
assign _zz_377_ = ((_zz_386_ == _zz_387_) != (1'b0));
assign _zz_378_ = ({_zz_388_,_zz_389_} != (2'b00));
assign _zz_379_ = {(_zz_390_ != _zz_391_),{_zz_392_,{_zz_393_,_zz_394_}}};
assign _zz_380_ = (32'b00000000000000000000000001000100);
assign _zz_381_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100));
assign _zz_382_ = (32'b00000000000000000010000000010000);
assign _zz_383_ = (decode_INSTRUCTION & (32'b01000000000000000100000000110100));
assign _zz_384_ = (32'b01000000000000000000000000110000);
assign _zz_385_ = (32'b00000000000000000000000000100000);
assign _zz_386_ = (decode_INSTRUCTION & (32'b00000000000000000001000001001000));
assign _zz_387_ = (32'b00000000000000000001000000001000);
assign _zz_388_ = ((decode_INSTRUCTION & _zz_395_) == (32'b00000000000000000000000000100000));
assign _zz_389_ = ((decode_INSTRUCTION & _zz_396_) == (32'b00000000000000000000000000100000));
assign _zz_390_ = {_zz_138_,{_zz_397_,{_zz_398_,_zz_399_}}};
assign _zz_391_ = (6'b000000);
assign _zz_392_ = ({_zz_400_,_zz_401_} != (2'b00));
assign _zz_393_ = ({_zz_402_,_zz_403_} != (4'b0000));
assign _zz_394_ = {(_zz_404_ != _zz_405_),{_zz_406_,{_zz_407_,_zz_408_}}};
assign _zz_395_ = (32'b00000000000000000000000000110100);
assign _zz_396_ = (32'b00000000000000000000000001100100);
assign _zz_397_ = ((decode_INSTRUCTION & _zz_409_) == (32'b00000000000000000001000000010000));
assign _zz_398_ = (_zz_410_ == _zz_411_);
assign _zz_399_ = {_zz_412_,{_zz_413_,_zz_414_}};
assign _zz_400_ = ((decode_INSTRUCTION & _zz_415_) == (32'b00000000000000000010000000000000));
assign _zz_401_ = ((decode_INSTRUCTION & _zz_416_) == (32'b00000000000000000001000000000000));
assign _zz_402_ = (_zz_417_ == _zz_418_);
assign _zz_403_ = {_zz_419_,{_zz_420_,_zz_421_}};
assign _zz_404_ = (_zz_422_ == _zz_423_);
assign _zz_405_ = (1'b0);
assign _zz_406_ = ({_zz_424_,_zz_425_} != (2'b00));
assign _zz_407_ = (_zz_426_ != _zz_427_);
assign _zz_408_ = {_zz_428_,{_zz_429_,_zz_430_}};
assign _zz_409_ = (32'b00000000000000000001000000010000);
assign _zz_410_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000));
assign _zz_411_ = (32'b00000000000000000010000000010000);
assign _zz_412_ = ((decode_INSTRUCTION & _zz_431_) == (32'b00000000000000000000000000010000));
assign _zz_413_ = (_zz_432_ == _zz_433_);
assign _zz_414_ = (_zz_434_ == _zz_435_);
assign _zz_415_ = (32'b00000000000000000010000000010000);
assign _zz_416_ = (32'b00000000000000000101000000000000);
assign _zz_417_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100));
assign _zz_418_ = (32'b00000000000000000000000000000000);
assign _zz_419_ = ((decode_INSTRUCTION & _zz_436_) == (32'b00000000000000000000000000000000));
assign _zz_420_ = (_zz_437_ == _zz_438_);
assign _zz_421_ = (_zz_439_ == _zz_440_);
assign _zz_422_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010000));
assign _zz_423_ = (32'b00000000000000000000000001010000);
assign _zz_424_ = _zz_138_;
assign _zz_425_ = (_zz_441_ == _zz_442_);
assign _zz_426_ = (_zz_443_ == _zz_444_);
assign _zz_427_ = (1'b0);
assign _zz_428_ = (_zz_445_ != (1'b0));
assign _zz_429_ = (_zz_446_ != _zz_447_);
assign _zz_430_ = {_zz_448_,{_zz_449_,_zz_450_}};
assign _zz_431_ = (32'b00000000000000000000000001010000);
assign _zz_432_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100));
assign _zz_433_ = (32'b00000000000000000000000000000100);
assign _zz_434_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000));
assign _zz_435_ = (32'b00000000000000000000000000000000);
assign _zz_436_ = (32'b00000000000000000000000000011000);
assign _zz_437_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100));
assign _zz_438_ = (32'b00000000000000000010000000000000);
assign _zz_439_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100));
assign _zz_440_ = (32'b00000000000000000001000000000000);
assign _zz_441_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011100));
assign _zz_442_ = (32'b00000000000000000000000000000100);
assign _zz_443_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000));
assign _zz_444_ = (32'b00000000000000000000000001000000);
assign _zz_445_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001110100)) == (32'b00000010000000000000000000110000));
assign _zz_446_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000));
assign _zz_447_ = (1'b0);
assign _zz_448_ = (_zz_137_ != (1'b0));
assign _zz_449_ = ({_zz_451_,{_zz_452_,_zz_453_}} != (3'b000));
assign _zz_450_ = {({_zz_454_,_zz_455_} != (2'b00)),{(_zz_456_ != _zz_457_),{_zz_458_,{_zz_459_,_zz_460_}}}};
assign _zz_451_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100));
assign _zz_452_ = ((decode_INSTRUCTION & _zz_461_) == (32'b00000000000000000001000000010000));
assign _zz_453_ = ((decode_INSTRUCTION & _zz_462_) == (32'b00000000000000000001000000010000));
assign _zz_454_ = ((decode_INSTRUCTION & _zz_463_) == (32'b00000000000000000110000000010000));
assign _zz_455_ = ((decode_INSTRUCTION & _zz_464_) == (32'b00000000000000000100000000010000));
assign _zz_456_ = ((decode_INSTRUCTION & _zz_465_) == (32'b00000000000000000010000000010000));
assign _zz_457_ = (1'b0);
assign _zz_458_ = ({_zz_466_,_zz_467_} != (2'b00));
assign _zz_459_ = ({_zz_468_,_zz_469_} != (3'b000));
assign _zz_460_ = {(_zz_470_ != _zz_471_),{_zz_472_,{_zz_473_,_zz_474_}}};
assign _zz_461_ = (32'b00000000000000000011000000110100);
assign _zz_462_ = (32'b00000010000000000011000001010100);
assign _zz_463_ = (32'b00000000000000000110000000010100);
assign _zz_464_ = (32'b00000000000000000101000000010100);
assign _zz_465_ = (32'b00000000000000000110000000010100);
assign _zz_466_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000110100)) == (32'b00000000000000000101000000010000));
assign _zz_467_ = ((decode_INSTRUCTION & (32'b00000010000000000111000001100100)) == (32'b00000000000000000101000000100000));
assign _zz_468_ = ((decode_INSTRUCTION & _zz_475_) == (32'b01000000000000000001000000010000));
assign _zz_469_ = {(_zz_476_ == _zz_477_),(_zz_478_ == _zz_479_)};
assign _zz_470_ = {_zz_136_,{_zz_480_,_zz_481_}};
assign _zz_471_ = (3'b000);
assign _zz_472_ = ((_zz_482_ == _zz_483_) != (1'b0));
assign _zz_473_ = ({_zz_484_,_zz_485_} != (2'b00));
assign _zz_474_ = (_zz_486_ != (1'b0));
assign _zz_475_ = (32'b01000000000000000011000001010100);
assign _zz_476_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100));
assign _zz_477_ = (32'b00000000000000000001000000010000);
assign _zz_478_ = (decode_INSTRUCTION & (32'b00000010000000000111000001010100));
assign _zz_479_ = (32'b00000000000000000001000000010000);
assign _zz_480_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000110000)) == (32'b00000000000000000000000000010000));
assign _zz_481_ = ((decode_INSTRUCTION & (32'b00000010000000000000000001100000)) == (32'b00000000000000000000000000100000));
assign _zz_482_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000));
assign _zz_483_ = (32'b00000000000000000000000000000000);
assign _zz_484_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001010000)) == (32'b00000000000000000001000001010000));
assign _zz_485_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000001010000));
assign _zz_486_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000));
assign _zz_487_ = (32'b00000000000000000001000001111111);
assign _zz_488_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111));
assign _zz_489_ = (32'b00000000000000000010000001110011);
assign _zz_490_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011));
assign _zz_491_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011));
assign _zz_492_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_493_) == (32'b00000000000000000000000000000011)),{(_zz_494_ == _zz_495_),{_zz_496_,{_zz_497_,_zz_498_}}}}}};
assign _zz_493_ = (32'b00000000000000000101000001011111);
assign _zz_494_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011));
assign _zz_495_ = (32'b00000000000000000000000001100011);
assign _zz_496_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111));
assign _zz_497_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011));
assign _zz_498_ = {((decode_INSTRUCTION & (32'b11111100000000000011000001011111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_499_) == (32'b00000000000000000101000000110011)),{(_zz_500_ == _zz_501_),(_zz_502_ == _zz_503_)}}}};
assign _zz_499_ = (32'b10111110000000000111000001111111);
assign _zz_500_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111));
assign _zz_501_ = (32'b00000000000000000000000000110011);
assign _zz_502_ = (decode_INSTRUCTION & (32'b11011111111111111111111111111111));
assign _zz_503_ = (32'b00010000001000000000000001110011);
assign _zz_504_ = execute_INSTRUCTION[31];
assign _zz_505_ = execute_INSTRUCTION[31];
assign _zz_506_ = execute_INSTRUCTION[7];
always @ (posedge clk) begin
if(_zz_52_) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
always @ (posedge clk) begin
if(_zz_342_) begin
_zz_214_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @ (posedge clk) begin
if(_zz_343_) begin
_zz_215_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
InstructionCache IBusCachedPlugin_cache (
.io_flush(_zz_205_),
.io_cpu_prefetch_isValid(_zz_206_),
.io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt),
.io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload),
.io_cpu_fetch_isValid(_zz_207_),
.io_cpu_fetch_isStuck(_zz_208_),
.io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt),
.io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload),
.io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data),
.io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit),
.io_cpu_fetch_dataBypass(_zz_209_),
.io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid),
.io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress),
.io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation),
.io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress),
.io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess),
.io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead),
.io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite),
.io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute),
.io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception),
.io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling),
.io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end),
.io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy),
.io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress),
.io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt),
.io_cpu_decode_isValid(_zz_210_),
.io_cpu_decode_isStuck(_zz_211_),
.io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload),
.io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress),
.io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data),
.io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss),
.io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error),
.io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling),
.io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException),
.io_cpu_decode_isUser(_zz_212_),
.io_cpu_fill_valid(_zz_213_),
.io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress),
.io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid),
.io_mem_cmd_ready(iBus_cmd_ready),
.io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address),
.io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size),
.io_mem_rsp_valid(iBus_rsp_valid),
.io_mem_rsp_payload_data(iBus_rsp_payload_data),
.io_mem_rsp_payload_error(iBus_rsp_payload_error),
.clk(clk),
.reset(reset)
);
always @(*) begin
case(_zz_344_)
3'b000 : begin
_zz_216_ = CsrPlugin_jumpInterface_payload;
end
3'b001 : begin
_zz_216_ = DBusSimplePlugin_redoBranch_payload;
end
3'b010 : begin
_zz_216_ = BranchPlugin_jumpInterface_payload;
end
3'b011 : begin
_zz_216_ = IBusCachedPlugin_redoBranch_payload;
end
default : begin
_zz_216_ = IBusCachedPlugin_predictionJumpInterface_payload;
end
endcase
end
`ifndef SYNTHESIS
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_1_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_1__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_1__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_1__string = "BITWISE ";
default : _zz_1__string = "????????";
endcase
end
always @(*) begin
case(_zz_2_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_2__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_2__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_2__string = "BITWISE ";
default : _zz_2__string = "????????";
endcase
end
always @(*) begin
case(_zz_3_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_3__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_3__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_3__string = "BITWISE ";
default : _zz_3__string = "????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_4_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_4__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_4__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_4__string = "AND_1";
default : _zz_4__string = "?????";
endcase
end
always @(*) begin
case(_zz_5_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_5__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_5__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_5__string = "AND_1";
default : _zz_5__string = "?????";
endcase
end
always @(*) begin
case(_zz_6_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1";
default : _zz_6__string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_7_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_7__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_7__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_7__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_7__string = "PC ";
default : _zz_7__string = "???";
endcase
end
always @(*) begin
case(_zz_8_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_8__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_8__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_8__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_8__string = "PC ";
default : _zz_8__string = "???";
endcase
end
always @(*) begin
case(_zz_9_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_9__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_9__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_9__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_9__string = "PC ";
default : _zz_9__string = "???";
endcase
end
always @(*) begin
case(_zz_10_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_10__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_10__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_10__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_10__string = "JALR";
default : _zz_10__string = "????";
endcase
end
always @(*) begin
case(_zz_11_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_11__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_11__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_11__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_11__string = "JALR";
default : _zz_11__string = "????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_12_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_12__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_12__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_12__string = "URS1 ";
default : _zz_12__string = "????????????";
endcase
end
always @(*) begin
case(_zz_13_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_13__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_13__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_13__string = "URS1 ";
default : _zz_13__string = "????????????";
endcase
end
always @(*) begin
case(_zz_14_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_14__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_14__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_14__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_14__string = "URS1 ";
default : _zz_14__string = "????????????";
endcase
end
always @(*) begin
case(_zz_15_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_15__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_15__string = "XRET";
default : _zz_15__string = "????";
endcase
end
always @(*) begin
case(_zz_16_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_16__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_16__string = "XRET";
default : _zz_16__string = "????";
endcase
end
always @(*) begin
case(_zz_17_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_17__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_17__string = "XRET";
default : _zz_17__string = "????";
endcase
end
always @(*) begin
case(_zz_18_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_18__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_18__string = "XRET";
default : _zz_18__string = "????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET";
default : decode_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_19_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_19__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_19__string = "XRET";
default : _zz_19__string = "????";
endcase
end
always @(*) begin
case(_zz_20_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_20__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_20__string = "XRET";
default : _zz_20__string = "????";
endcase
end
always @(*) begin
case(_zz_21_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_21__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_21__string = "XRET";
default : _zz_21__string = "????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_22_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 ";
default : _zz_22__string = "?????????";
endcase
end
always @(*) begin
case(_zz_23_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_23__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_23__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_23__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_23__string = "SRA_1 ";
default : _zz_23__string = "?????????";
endcase
end
always @(*) begin
case(_zz_24_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_24__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_24__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_24__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_24__string = "SRA_1 ";
default : _zz_24__string = "?????????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET";
default : memory_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_25_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_25__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_25__string = "XRET";
default : _zz_25__string = "????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET";
default : execute_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_26_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET";
default : _zz_26__string = "????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET";
default : writeBack_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_29_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_29__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_29__string = "XRET";
default : _zz_29__string = "????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_32_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_32__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_32__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_32__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_32__string = "JALR";
default : _zz_32__string = "????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_37_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_37__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_37__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_37__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_37__string = "SRA_1 ";
default : _zz_37__string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_42_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_42__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_42__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_42__string = "PC ";
default : _zz_42__string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_44_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_44__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_44__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_44__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_44__string = "URS1 ";
default : _zz_44__string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_47_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_47__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_47__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_47__string = "BITWISE ";
default : _zz_47__string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_49_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_49__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_49__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_49__string = "AND_1";
default : _zz_49__string = "?????";
endcase
end
always @(*) begin
case(_zz_56_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_56__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_56__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_56__string = "URS1 ";
default : _zz_56__string = "????????????";
endcase
end
always @(*) begin
case(_zz_59_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_59__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_59__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_59__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_59__string = "PC ";
default : _zz_59__string = "???";
endcase
end
always @(*) begin
case(_zz_67_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_67__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_67__string = "XRET";
default : _zz_67__string = "????";
endcase
end
always @(*) begin
case(_zz_68_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_68__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_68__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_68__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_68__string = "JALR";
default : _zz_68__string = "????";
endcase
end
always @(*) begin
case(_zz_70_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_70__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_70__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_70__string = "AND_1";
default : _zz_70__string = "?????";
endcase
end
always @(*) begin
case(_zz_72_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_72__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_72__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_72__string = "BITWISE ";
default : _zz_72__string = "????????";
endcase
end
always @(*) begin
case(_zz_73_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_73__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_73__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_73__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_73__string = "SRA_1 ";
default : _zz_73__string = "?????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_95_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_95__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_95__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_95__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_95__string = "JALR";
default : _zz_95__string = "????";
endcase
end
always @(*) begin
case(_zz_142_)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_142__string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_142__string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_142__string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_142__string = "SRA_1 ";
default : _zz_142__string = "?????????";
endcase
end
always @(*) begin
case(_zz_143_)
`AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_143__string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_143__string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : _zz_143__string = "BITWISE ";
default : _zz_143__string = "????????";
endcase
end
always @(*) begin
case(_zz_144_)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_144__string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_144__string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_144__string = "AND_1";
default : _zz_144__string = "?????";
endcase
end
always @(*) begin
case(_zz_145_)
`BranchCtrlEnum_defaultEncoding_INC : _zz_145__string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : _zz_145__string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : _zz_145__string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : _zz_145__string = "JALR";
default : _zz_145__string = "????";
endcase
end
always @(*) begin
case(_zz_146_)
`EnvCtrlEnum_defaultEncoding_NONE : _zz_146__string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : _zz_146__string = "XRET";
default : _zz_146__string = "????";
endcase
end
always @(*) begin
case(_zz_147_)
`Src2CtrlEnum_defaultEncoding_RS : _zz_147__string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : _zz_147__string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : _zz_147__string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : _zz_147__string = "PC ";
default : _zz_147__string = "???";
endcase
end
always @(*) begin
case(_zz_148_)
`Src1CtrlEnum_defaultEncoding_RS : _zz_148__string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : _zz_148__string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_148__string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : _zz_148__string = "URS1 ";
default : _zz_148__string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET";
default : decode_to_execute_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET";
default : execute_to_memory_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE";
`EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET";
default : memory_to_writeBack_ENV_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
`endif
assign decode_ALU_CTRL = _zz_1_;
assign _zz_2_ = _zz_3_;
assign decode_ALU_BITWISE_CTRL = _zz_4_;
assign _zz_5_ = _zz_6_;
assign decode_SRC2_CTRL = _zz_7_;
assign _zz_8_ = _zz_9_;
assign decode_IS_RS2_SIGNED = _zz_58_;
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_74_;
assign decode_IS_RS1_SIGNED = _zz_55_;
assign decode_CSR_READ_OPCODE = _zz_27_;
assign decode_IS_DIV = _zz_57_;
assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW;
assign execute_MEMORY_ADDRESS_LOW = _zz_89_;
assign decode_IS_MUL = _zz_69_;
assign execute_BRANCH_CALC = _zz_30_;
assign _zz_10_ = _zz_11_;
assign decode_SRC1_CTRL = _zz_12_;
assign _zz_13_ = _zz_14_;
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_77_;
assign decode_SRC2_FORCE_ZERO = _zz_46_;
assign decode_CSR_WRITE_OPCODE = _zz_28_;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign execute_REGFILE_WRITE_DATA = _zz_48_;
assign execute_BRANCH_DO = _zz_31_;
assign decode_SRC_LESS_UNSIGNED = _zz_65_;
assign _zz_15_ = _zz_16_;
assign _zz_17_ = _zz_18_;
assign decode_ENV_CTRL = _zz_19_;
assign _zz_20_ = _zz_21_;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = _zz_98_;
assign decode_MEMORY_STORE = _zz_61_;
assign decode_PREDICTION_HAD_BRANCHED2 = _zz_34_;
assign decode_IS_CSR = _zz_76_;
assign decode_SHIFT_CTRL = _zz_22_;
assign _zz_23_ = _zz_24_;
assign memory_MEMORY_READ_DATA = _zz_80_;
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_25_;
assign execute_ENV_CTRL = _zz_26_;
assign writeBack_ENV_CTRL = _zz_29_;
assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC;
assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO;
assign execute_PC = decode_to_execute_PC;
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_COND_RESULT = _zz_33_;
assign execute_BRANCH_CTRL = _zz_32_;
assign decode_RS2_USE = _zz_63_;
assign decode_RS1_USE = _zz_66_;
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
always @ (*) begin
_zz_35_ = memory_REGFILE_WRITE_DATA;
if(_zz_217_)begin
_zz_35_ = ((memory_INSTRUCTION[13 : 12] == (2'b00)) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]);
end
if(_zz_218_)begin
_zz_35_ = memory_MulDivIterativePlugin_div_result;
end
end
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @ (*) begin
decode_RS2 = _zz_53_;
if(_zz_161_)begin
if((_zz_162_ == decode_INSTRUCTION[24 : 20]))begin
decode_RS2 = _zz_163_;
end
end
if(_zz_219_)begin
if(_zz_220_)begin
if(_zz_165_)begin
decode_RS2 = _zz_79_;
end
end
end
if(_zz_221_)begin
if(memory_BYPASSABLE_MEMORY_STAGE)begin
if(_zz_167_)begin
decode_RS2 = _zz_35_;
end
end
end
if(_zz_222_)begin
if(execute_BYPASSABLE_EXECUTE_STAGE)begin
if(_zz_169_)begin
decode_RS2 = _zz_36_;
end
end
end
end
always @ (*) begin
decode_RS1 = _zz_54_;
if(_zz_161_)begin
if((_zz_162_ == decode_INSTRUCTION[19 : 15]))begin
decode_RS1 = _zz_163_;
end
end
if(_zz_219_)begin
if(_zz_220_)begin
if(_zz_164_)begin
decode_RS1 = _zz_79_;
end
end
end
if(_zz_221_)begin
if(memory_BYPASSABLE_MEMORY_STAGE)begin
if(_zz_166_)begin
decode_RS1 = _zz_35_;
end
end
end
if(_zz_222_)begin
if(execute_BYPASSABLE_EXECUTE_STAGE)begin
if(_zz_168_)begin
decode_RS1 = _zz_36_;
end
end
end
end
always @ (*) begin
_zz_36_ = execute_REGFILE_WRITE_DATA;
if(_zz_223_)begin
_zz_36_ = _zz_157_;
end
if(_zz_224_)begin
_zz_36_ = execute_CsrPlugin_readData;
end
end
assign execute_SHIFT_CTRL = _zz_37_;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_41_ = execute_PC;
assign execute_SRC2_CTRL = _zz_42_;
assign execute_SRC1_CTRL = _zz_44_;
assign decode_SRC_USE_SUB_LESS = _zz_60_;
assign decode_SRC_ADD_ZERO = _zz_71_;
assign execute_SRC_ADD_SUB = _zz_40_;
assign execute_SRC_LESS = _zz_38_;
assign execute_ALU_CTRL = _zz_47_;
assign execute_SRC2 = _zz_43_;
assign execute_SRC1 = _zz_45_;
assign execute_ALU_BITWISE_CTRL = _zz_49_;
assign _zz_50_ = writeBack_INSTRUCTION;
assign _zz_51_ = writeBack_REGFILE_WRITE_VALID;
always @ (*) begin
_zz_52_ = 1'b0;
if(lastStageRegFileWrite_valid)begin
_zz_52_ = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = _zz_94_;
always @ (*) begin
decode_REGFILE_WRITE_VALID = _zz_64_;
if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
assign decode_LEGAL_INSTRUCTION = _zz_78_;
assign decode_INSTRUCTION_READY = 1'b1;
assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE;
always @ (*) begin
_zz_79_ = writeBack_REGFILE_WRITE_DATA;
if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin
_zz_79_ = writeBack_DBusSimplePlugin_rspFormated;
end
end
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW;
assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA;
assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT;
assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress;
assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess;
assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead;
assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite;
assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute;
assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception;
assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling;
assign memory_PC = execute_to_memory_PC;
assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_MMU_FAULT = _zz_88_;
assign execute_MMU_RSP_physicalAddress = _zz_81_;
assign execute_MMU_RSP_isIoAccess = _zz_82_;
assign execute_MMU_RSP_allowRead = _zz_83_;
assign execute_MMU_RSP_allowWrite = _zz_84_;
assign execute_MMU_RSP_allowExecute = _zz_85_;
assign execute_MMU_RSP_exception = _zz_86_;
assign execute_MMU_RSP_refilling = _zz_87_;
assign execute_SRC_ADD = _zz_39_;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_ALIGNEMENT_FAULT = _zz_90_;
assign decode_MEMORY_ENABLE = _zz_75_;
assign decode_FLUSH_ALL = _zz_62_;
always @ (*) begin
IBusCachedPlugin_rsp_issueDetected = _zz_91_;
if(_zz_225_)begin
IBusCachedPlugin_rsp_issueDetected = 1'b1;
end
end
always @ (*) begin
_zz_91_ = _zz_92_;
if(_zz_226_)begin
_zz_91_ = 1'b1;
end
end
always @ (*) begin
_zz_92_ = _zz_93_;
if(_zz_227_)begin
_zz_92_ = 1'b1;
end
end
always @ (*) begin
_zz_93_ = 1'b0;
if(_zz_228_)begin
_zz_93_ = 1'b1;
end
end
assign decode_BRANCH_CTRL = _zz_95_;
assign decode_INSTRUCTION = _zz_99_;
always @ (*) begin
_zz_96_ = memory_FORMAL_PC_NEXT;
if(DBusSimplePlugin_redoBranch_valid)begin
_zz_96_ = DBusSimplePlugin_redoBranch_payload;
end
if(BranchPlugin_jumpInterface_valid)begin
_zz_96_ = BranchPlugin_jumpInterface_payload;
end
end
always @ (*) begin
_zz_97_ = decode_FORMAL_PC_NEXT;
if(IBusCachedPlugin_predictionJumpInterface_valid)begin
_zz_97_ = IBusCachedPlugin_predictionJumpInterface_payload;
end
if(IBusCachedPlugin_redoBranch_valid)begin
_zz_97_ = IBusCachedPlugin_redoBranch_payload;
end
end
assign decode_PC = _zz_100_;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
always @ (*) begin
decode_arbitration_haltItself = 1'b0;
if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin
decode_arbitration_haltItself = 1'b1;
end
end
always @ (*) begin
decode_arbitration_haltByOther = 1'b0;
if((decode_arbitration_isValid && (_zz_158_ || _zz_159_)))begin
decode_arbitration_haltByOther = 1'b1;
end
if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin
decode_arbitration_haltByOther = decode_arbitration_isValid;
end
if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @ (*) begin
decode_arbitration_removeIt = 1'b0;
if(_zz_229_)begin
decode_arbitration_removeIt = 1'b1;
end
if(decode_arbitration_isFlushed)begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_flushIt = 1'b0;
always @ (*) begin
decode_arbitration_flushNext = 1'b0;
if(IBusCachedPlugin_redoBranch_valid)begin
decode_arbitration_flushNext = 1'b1;
end
if(_zz_229_)begin
decode_arbitration_flushNext = 1'b1;
end
end
always @ (*) begin
execute_arbitration_haltItself = 1'b0;
if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_128_)))begin
execute_arbitration_haltItself = 1'b1;
end
if(_zz_223_)begin
if(_zz_230_)begin
if(! execute_LightShifterPlugin_done) begin
execute_arbitration_haltItself = 1'b1;
end
end
end
if(_zz_224_)begin
if(execute_CsrPlugin_blockedBySideEffects)begin
execute_arbitration_haltItself = 1'b1;
end
end
end
assign execute_arbitration_haltByOther = 1'b0;
always @ (*) begin
execute_arbitration_removeIt = 1'b0;
if(execute_arbitration_isFlushed)begin
execute_arbitration_removeIt = 1'b1;
end
end
assign execute_arbitration_flushIt = 1'b0;
assign execute_arbitration_flushNext = 1'b0;
always @ (*) begin
memory_arbitration_haltItself = 1'b0;
if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin
memory_arbitration_haltItself = 1'b1;
end
if(_zz_217_)begin
if(_zz_231_)begin
memory_arbitration_haltItself = 1'b1;
end
end
if(_zz_218_)begin
if(_zz_232_)begin
memory_arbitration_haltItself = 1'b1;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @ (*) begin
memory_arbitration_removeIt = 1'b0;
if(_zz_233_)begin
memory_arbitration_removeIt = 1'b1;
end
if(memory_arbitration_isFlushed)begin
memory_arbitration_removeIt = 1'b1;
end
end
always @ (*) begin
memory_arbitration_flushIt = 1'b0;
if(DBusSimplePlugin_redoBranch_valid)begin
memory_arbitration_flushIt = 1'b1;
end
end
always @ (*) begin
memory_arbitration_flushNext = 1'b0;
if(DBusSimplePlugin_redoBranch_valid)begin
memory_arbitration_flushNext = 1'b1;
end
if(BranchPlugin_jumpInterface_valid)begin
memory_arbitration_flushNext = 1'b1;
end
if(_zz_233_)begin
memory_arbitration_flushNext = 1'b1;
end
end
assign writeBack_arbitration_haltItself = 1'b0;
assign writeBack_arbitration_haltByOther = 1'b0;
always @ (*) begin
writeBack_arbitration_removeIt = 1'b0;
if(writeBack_arbitration_isFlushed)begin
writeBack_arbitration_removeIt = 1'b1;
end
end
assign writeBack_arbitration_flushIt = 1'b0;
always @ (*) begin
writeBack_arbitration_flushNext = 1'b0;
if(_zz_234_)begin
writeBack_arbitration_flushNext = 1'b1;
end
if(_zz_235_)begin
writeBack_arbitration_flushNext = 1'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @ (*) begin
IBusCachedPlugin_fetcherHalt = 1'b0;
if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(_zz_234_)begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(_zz_235_)begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
always @ (*) begin
IBusCachedPlugin_fetcherflushIt = 1'b0;
if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin
IBusCachedPlugin_fetcherflushIt = 1'b1;
end
if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin
IBusCachedPlugin_fetcherflushIt = 1'b1;
end
end
always @ (*) begin
IBusCachedPlugin_incomingInstruction = 1'b0;
if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin
IBusCachedPlugin_incomingInstruction = 1'b1;
end
end
always @ (*) begin
CsrPlugin_jumpInterface_valid = 1'b0;
if(_zz_234_)begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
if(_zz_235_)begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
end
always @ (*) begin
CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
if(_zz_234_)begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)};
end
if(_zz_235_)begin
case(_zz_236_)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
assign CsrPlugin_forceMachineWire = 1'b0;
assign CsrPlugin_allowInterrupts = 1'b1;
assign CsrPlugin_allowException = 1'b1;
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000));
assign _zz_101_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}};
assign _zz_102_ = (_zz_101_ & (~ _zz_255_));
assign _zz_103_ = _zz_102_[3];
assign _zz_104_ = _zz_102_[4];
assign _zz_105_ = (_zz_102_[1] || _zz_103_);
assign _zz_106_ = (_zz_102_[2] || _zz_103_);
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_216_;
always @ (*) begin
IBusCachedPlugin_fetchPc_corrected = 1'b0;
if(IBusCachedPlugin_jump_pcLoad_valid)begin
IBusCachedPlugin_fetchPc_corrected = 1'b1;
end
end
always @ (*) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
always @ (*) begin
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_257_);
if(IBusCachedPlugin_jump_pcLoad_valid)begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
end
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
end
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1;
always @ (*) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
end
end
assign _zz_107_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_107_);
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_107_);
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
always @ (*) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_108_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_108_);
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_108_);
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
always @ (*) begin
IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0;
if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin
IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1;
end
end
assign _zz_109_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt);
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_109_);
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_109_);
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_110_;
assign _zz_110_ = ((1'b0 && (! _zz_111_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_111_ = _zz_112_;
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_111_;
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_113_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready);
assign _zz_113_ = _zz_114_;
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_113_;
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_115_;
always @ (*) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
if((! IBusCachedPlugin_pcValids_0))begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
end
end
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck);
assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved));
assign _zz_100_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc;
assign _zz_99_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst;
assign _zz_98_ = (decode_PC + (32'b00000000000000000000000000000100));
assign _zz_116_ = _zz_258_[11];
always @ (*) begin
_zz_117_[18] = _zz_116_;
_zz_117_[17] = _zz_116_;
_zz_117_[16] = _zz_116_;
_zz_117_[15] = _zz_116_;
_zz_117_[14] = _zz_116_;
_zz_117_[13] = _zz_116_;
_zz_117_[12] = _zz_116_;
_zz_117_[11] = _zz_116_;
_zz_117_[10] = _zz_116_;
_zz_117_[9] = _zz_116_;
_zz_117_[8] = _zz_116_;
_zz_117_[7] = _zz_116_;
_zz_117_[6] = _zz_116_;
_zz_117_[5] = _zz_116_;
_zz_117_[4] = _zz_116_;
_zz_117_[3] = _zz_116_;
_zz_117_[2] = _zz_116_;
_zz_117_[1] = _zz_116_;
_zz_117_[0] = _zz_116_;
end
always @ (*) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_259_[31]));
if(_zz_122_)begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0;
end
end
assign _zz_118_ = _zz_260_[19];
always @ (*) begin
_zz_119_[10] = _zz_118_;
_zz_119_[9] = _zz_118_;
_zz_119_[8] = _zz_118_;
_zz_119_[7] = _zz_118_;
_zz_119_[6] = _zz_118_;
_zz_119_[5] = _zz_118_;
_zz_119_[4] = _zz_118_;
_zz_119_[3] = _zz_118_;
_zz_119_[2] = _zz_118_;
_zz_119_[1] = _zz_118_;
_zz_119_[0] = _zz_118_;
end
assign _zz_120_ = _zz_261_[11];
always @ (*) begin
_zz_121_[18] = _zz_120_;
_zz_121_[17] = _zz_120_;
_zz_121_[16] = _zz_120_;
_zz_121_[15] = _zz_120_;
_zz_121_[14] = _zz_120_;
_zz_121_[13] = _zz_120_;
_zz_121_[12] = _zz_120_;
_zz_121_[11] = _zz_120_;
_zz_121_[10] = _zz_120_;
_zz_121_[9] = _zz_120_;
_zz_121_[8] = _zz_120_;
_zz_121_[7] = _zz_120_;
_zz_121_[6] = _zz_120_;
_zz_121_[5] = _zz_120_;
_zz_121_[4] = _zz_120_;
_zz_121_[3] = _zz_120_;
_zz_121_[2] = _zz_120_;
_zz_121_[1] = _zz_120_;
_zz_121_[0] = _zz_120_;
end
always @ (*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_JAL : begin
_zz_122_ = _zz_262_[1];
end
default : begin
_zz_122_ = _zz_263_[1];
end
endcase
end
assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch);
assign _zz_123_ = _zz_264_[19];
always @ (*) begin
_zz_124_[10] = _zz_123_;
_zz_124_[9] = _zz_123_;
_zz_124_[8] = _zz_123_;
_zz_124_[7] = _zz_123_;
_zz_124_[6] = _zz_123_;
_zz_124_[5] = _zz_123_;
_zz_124_[4] = _zz_123_;
_zz_124_[3] = _zz_123_;
_zz_124_[2] = _zz_123_;
_zz_124_[1] = _zz_123_;
_zz_124_[0] = _zz_123_;
end
assign _zz_125_ = _zz_265_[11];
always @ (*) begin
_zz_126_[18] = _zz_125_;
_zz_126_[17] = _zz_125_;
_zz_126_[16] = _zz_125_;
_zz_126_[15] = _zz_125_;
_zz_126_[14] = _zz_125_;
_zz_126_[13] = _zz_125_;
_zz_126_[12] = _zz_125_;
_zz_126_[11] = _zz_125_;
_zz_126_[10] = _zz_125_;
_zz_126_[9] = _zz_125_;
_zz_126_[8] = _zz_125_;
_zz_126_[7] = _zz_125_;
_zz_126_[6] = _zz_125_;
_zz_126_[5] = _zz_125_;
_zz_126_[4] = _zz_125_;
_zz_126_[3] = _zz_125_;
_zz_126_[2] = _zz_125_;
_zz_126_[1] = _zz_125_;
_zz_126_[0] = _zz_125_;
end
assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_124_,{{{_zz_345_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_126_,{{{_zz_346_,_zz_347_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
always @ (*) begin
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
end
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
assign _zz_206_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
assign _zz_209_ = (32'b00000000000000000000000000000000);
assign _zz_207_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
assign _zz_208_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_210_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
assign _zz_211_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready);
assign _zz_212_ = (CsrPlugin_privilege == (2'b00));
assign _zz_94_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
always @ (*) begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
if(_zz_228_)begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(_zz_226_)begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(_zz_237_)begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
end
end
always @ (*) begin
_zz_213_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
if(_zz_226_)begin
_zz_213_ = 1'b1;
end
if(_zz_237_)begin
_zz_213_ = 1'b0;
end
end
always @ (*) begin
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
if(_zz_227_)begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
if(_zz_225_)begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
end
always @ (*) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx);
if(_zz_227_)begin
IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100);
end
if(_zz_225_)begin
IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001);
end
end
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)};
assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch;
assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload;
assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid;
assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready;
assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload;
assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid;
assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress;
assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation;
assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end;
assign _zz_205_ = (decode_arbitration_isValid && decode_FLUSH_ALL);
assign _zz_128_ = 1'b0;
assign _zz_90_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0))));
always @ (*) begin
execute_DBusSimplePlugin_skipCmd = 1'b0;
if(execute_ALIGNEMENT_FAULT)begin
execute_DBusSimplePlugin_skipCmd = 1'b1;
end
if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin
execute_DBusSimplePlugin_skipCmd = 1'b1;
end
end
assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_128_));
assign dBus_cmd_payload_wr = execute_MEMORY_STORE;
assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12];
always @ (*) begin
case(dBus_cmd_payload_size)
2'b00 : begin
_zz_129_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_129_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_129_ = execute_RS2[31 : 0];
end
endcase
end
assign dBus_cmd_payload_data = _zz_129_;
assign _zz_89_ = dBus_cmd_payload_address[1 : 0];
always @ (*) begin
case(dBus_cmd_payload_size)
2'b00 : begin
_zz_130_ = (4'b0001);
end
2'b01 : begin
_zz_130_ = (4'b0011);
end
default : begin
_zz_130_ = (4'b1111);
end
endcase
end
assign execute_DBusSimplePlugin_formalMask = (_zz_130_ <<< dBus_cmd_payload_address[1 : 0]);
assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD;
assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0;
assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress;
assign _zz_88_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE)));
assign _zz_81_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress;
assign _zz_82_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess;
assign _zz_83_ = DBusSimplePlugin_mmuBus_rsp_allowRead;
assign _zz_84_ = DBusSimplePlugin_mmuBus_rsp_allowWrite;
assign _zz_85_ = DBusSimplePlugin_mmuBus_rsp_allowExecute;
assign _zz_86_ = DBusSimplePlugin_mmuBus_rsp_exception;
assign _zz_87_ = DBusSimplePlugin_mmuBus_rsp_refilling;
assign _zz_80_ = dBus_rsp_data;
always @ (*) begin
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
if(_zz_238_)begin
DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
end
if(memory_ALIGNEMENT_FAULT)begin
DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
end
if(memory_MMU_RSP_refilling)begin
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
end else begin
if(memory_MMU_FAULT)begin
DBusSimplePlugin_memoryExceptionPort_valid = 1'b1;
end
end
if(_zz_239_)begin
DBusSimplePlugin_memoryExceptionPort_valid = 1'b0;
end
end
always @ (*) begin
DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx);
if(_zz_238_)begin
DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101);
end
if(memory_ALIGNEMENT_FAULT)begin
DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_266_};
end
if(! memory_MMU_RSP_refilling) begin
if(memory_MMU_FAULT)begin
DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101));
end
end
end
assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA;
always @ (*) begin
DBusSimplePlugin_redoBranch_valid = 1'b0;
if(memory_MMU_RSP_refilling)begin
DBusSimplePlugin_redoBranch_valid = 1'b1;
end
if(_zz_239_)begin
DBusSimplePlugin_redoBranch_valid = 1'b0;
end
end
assign DBusSimplePlugin_redoBranch_payload = memory_PC;
always @ (*) begin
writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA;
case(writeBack_MEMORY_ADDRESS_LOW)
2'b01 : begin
writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8];
end
2'b10 : begin
writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16];
end
2'b11 : begin
writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24];
end
default : begin
end
endcase
end
assign _zz_131_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14]));
always @ (*) begin
_zz_132_[31] = _zz_131_;
_zz_132_[30] = _zz_131_;
_zz_132_[29] = _zz_131_;
_zz_132_[28] = _zz_131_;
_zz_132_[27] = _zz_131_;
_zz_132_[26] = _zz_131_;
_zz_132_[25] = _zz_131_;
_zz_132_[24] = _zz_131_;
_zz_132_[23] = _zz_131_;
_zz_132_[22] = _zz_131_;
_zz_132_[21] = _zz_131_;
_zz_132_[20] = _zz_131_;
_zz_132_[19] = _zz_131_;
_zz_132_[18] = _zz_131_;
_zz_132_[17] = _zz_131_;
_zz_132_[16] = _zz_131_;
_zz_132_[15] = _zz_131_;
_zz_132_[14] = _zz_131_;
_zz_132_[13] = _zz_131_;
_zz_132_[12] = _zz_131_;
_zz_132_[11] = _zz_131_;
_zz_132_[10] = _zz_131_;
_zz_132_[9] = _zz_131_;
_zz_132_[8] = _zz_131_;
_zz_132_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0];
end
assign _zz_133_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14]));
always @ (*) begin
_zz_134_[31] = _zz_133_;
_zz_134_[30] = _zz_133_;
_zz_134_[29] = _zz_133_;
_zz_134_[28] = _zz_133_;
_zz_134_[27] = _zz_133_;
_zz_134_[26] = _zz_133_;
_zz_134_[25] = _zz_133_;
_zz_134_[24] = _zz_133_;
_zz_134_[23] = _zz_133_;
_zz_134_[22] = _zz_133_;
_zz_134_[21] = _zz_133_;
_zz_134_[20] = _zz_133_;
_zz_134_[19] = _zz_133_;
_zz_134_[18] = _zz_133_;
_zz_134_[17] = _zz_133_;
_zz_134_[16] = _zz_133_;
_zz_134_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0];
end
always @ (*) begin
case(_zz_253_)
2'b00 : begin
writeBack_DBusSimplePlugin_rspFormated = _zz_132_;
end
2'b01 : begin
writeBack_DBusSimplePlugin_rspFormated = _zz_134_;
end
default : begin
writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted;
end
endcase
end
assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress;
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign IBusCachedPlugin_mmuBus_busy = 1'b0;
assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress;
assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1;
assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31];
assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0;
assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0;
assign DBusSimplePlugin_mmuBus_busy = 1'b0;
assign _zz_136_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100));
assign _zz_137_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000));
assign _zz_138_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000));
assign _zz_139_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000000000)) == (32'b00000000000000000001000000000000));
assign _zz_140_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000100000000000000));
assign _zz_141_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000));
assign _zz_135_ = {({_zz_140_,{_zz_137_,_zz_139_}} != (3'b000)),{({_zz_348_,_zz_141_} != (2'b00)),{({_zz_349_,_zz_350_} != (2'b00)),{(_zz_351_ != _zz_352_),{_zz_353_,{_zz_354_,_zz_355_}}}}}};
assign _zz_78_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_487_) == (32'b00000000000000000001000001110011)),{(_zz_488_ == _zz_489_),{_zz_490_,{_zz_491_,_zz_492_}}}}}}} != (18'b000000000000000000));
assign _zz_77_ = _zz_267_[0];
assign _zz_76_ = _zz_268_[0];
assign _zz_75_ = _zz_269_[0];
assign _zz_74_ = _zz_270_[0];
assign _zz_142_ = _zz_135_[5 : 4];
assign _zz_73_ = _zz_142_;
assign _zz_143_ = _zz_135_[7 : 6];
assign _zz_72_ = _zz_143_;
assign _zz_71_ = _zz_271_[0];
assign _zz_144_ = _zz_135_[10 : 9];
assign _zz_70_ = _zz_144_;
assign _zz_69_ = _zz_272_[0];
assign _zz_145_ = _zz_135_[13 : 12];
assign _zz_68_ = _zz_145_;
assign _zz_146_ = _zz_135_[14 : 14];
assign _zz_67_ = _zz_146_;
assign _zz_66_ = _zz_273_[0];
assign _zz_65_ = _zz_274_[0];
assign _zz_64_ = _zz_275_[0];
assign _zz_63_ = _zz_276_[0];
assign _zz_62_ = _zz_277_[0];
assign _zz_61_ = _zz_278_[0];
assign _zz_60_ = _zz_279_[0];
assign _zz_147_ = _zz_135_[23 : 22];
assign _zz_59_ = _zz_147_;
assign _zz_58_ = _zz_280_[0];
assign _zz_57_ = _zz_281_[0];
assign _zz_148_ = _zz_135_[28 : 27];
assign _zz_56_ = _zz_148_;
assign _zz_55_ = _zz_282_[0];
assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION));
assign decodeExceptionPort_payload_code = (4'b0010);
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_214_;
assign decode_RegFilePlugin_rs2Data = _zz_215_;
assign _zz_54_ = decode_RegFilePlugin_rs1Data;
assign _zz_53_ = decode_RegFilePlugin_rs2Data;
always @ (*) begin
lastStageRegFileWrite_valid = (_zz_51_ && writeBack_arbitration_isFiring);
if(_zz_149_)begin
lastStageRegFileWrite_valid = 1'b1;
end
end
assign lastStageRegFileWrite_payload_address = _zz_50_[11 : 7];
assign lastStageRegFileWrite_payload_data = _zz_79_;
always @ (*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @ (*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_defaultEncoding_BITWISE : begin
_zz_150_ = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_defaultEncoding_SLT_SLTU : begin
_zz_150_ = {31'd0, _zz_283_};
end
default : begin
_zz_150_ = execute_SRC_ADD_SUB;
end
endcase
end
assign _zz_48_ = _zz_150_;
assign _zz_46_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
always @ (*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_defaultEncoding_RS : begin
_zz_151_ = execute_RS1;
end
`Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin
_zz_151_ = {29'd0, _zz_284_};
end
`Src1CtrlEnum_defaultEncoding_IMU : begin
_zz_151_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)};
end
default : begin
_zz_151_ = {27'd0, _zz_285_};
end
endcase
end
assign _zz_45_ = _zz_151_;
assign _zz_152_ = _zz_286_[11];
always @ (*) begin
_zz_153_[19] = _zz_152_;
_zz_153_[18] = _zz_152_;
_zz_153_[17] = _zz_152_;
_zz_153_[16] = _zz_152_;
_zz_153_[15] = _zz_152_;
_zz_153_[14] = _zz_152_;
_zz_153_[13] = _zz_152_;
_zz_153_[12] = _zz_152_;
_zz_153_[11] = _zz_152_;
_zz_153_[10] = _zz_152_;
_zz_153_[9] = _zz_152_;
_zz_153_[8] = _zz_152_;
_zz_153_[7] = _zz_152_;
_zz_153_[6] = _zz_152_;
_zz_153_[5] = _zz_152_;
_zz_153_[4] = _zz_152_;
_zz_153_[3] = _zz_152_;
_zz_153_[2] = _zz_152_;
_zz_153_[1] = _zz_152_;
_zz_153_[0] = _zz_152_;
end
assign _zz_154_ = _zz_287_[11];
always @ (*) begin
_zz_155_[19] = _zz_154_;
_zz_155_[18] = _zz_154_;
_zz_155_[17] = _zz_154_;
_zz_155_[16] = _zz_154_;
_zz_155_[15] = _zz_154_;
_zz_155_[14] = _zz_154_;
_zz_155_[13] = _zz_154_;
_zz_155_[12] = _zz_154_;
_zz_155_[11] = _zz_154_;
_zz_155_[10] = _zz_154_;
_zz_155_[9] = _zz_154_;
_zz_155_[8] = _zz_154_;
_zz_155_[7] = _zz_154_;
_zz_155_[6] = _zz_154_;
_zz_155_[5] = _zz_154_;
_zz_155_[4] = _zz_154_;
_zz_155_[3] = _zz_154_;
_zz_155_[2] = _zz_154_;
_zz_155_[1] = _zz_154_;
_zz_155_[0] = _zz_154_;
end
always @ (*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_defaultEncoding_RS : begin
_zz_156_ = execute_RS2;
end
`Src2CtrlEnum_defaultEncoding_IMI : begin
_zz_156_ = {_zz_153_,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_defaultEncoding_IMS : begin
_zz_156_ = {_zz_155_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_156_ = _zz_41_;
end
endcase
end
assign _zz_43_ = _zz_156_;
always @ (*) begin
execute_SrcPlugin_addSub = _zz_288_;
if(execute_SRC2_FORCE_ZERO)begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign _zz_40_ = execute_SrcPlugin_addSub;
assign _zz_39_ = execute_SrcPlugin_addSub;
assign _zz_38_ = execute_SrcPlugin_less;
assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1);
assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]);
assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1);
assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000));
always @ (*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_defaultEncoding_SLL_1 : begin
_zz_157_ = (execute_LightShifterPlugin_shiftInput <<< 1);
end
default : begin
_zz_157_ = _zz_295_;
end
endcase
end
always @ (*) begin
_zz_158_ = 1'b0;
if(_zz_240_)begin
if(_zz_241_)begin
if(_zz_164_)begin
_zz_158_ = 1'b1;
end
end
end
if(_zz_242_)begin
if(_zz_243_)begin
if(_zz_166_)begin
_zz_158_ = 1'b1;
end
end
end
if(_zz_244_)begin
if(_zz_245_)begin
if(_zz_168_)begin
_zz_158_ = 1'b1;
end
end
end
if((! decode_RS1_USE))begin
_zz_158_ = 1'b0;
end
end
always @ (*) begin
_zz_159_ = 1'b0;
if(_zz_240_)begin
if(_zz_241_)begin
if(_zz_165_)begin
_zz_159_ = 1'b1;
end
end
end
if(_zz_242_)begin
if(_zz_243_)begin
if(_zz_167_)begin
_zz_159_ = 1'b1;
end
end
end
if(_zz_244_)begin
if(_zz_245_)begin
if(_zz_169_)begin
_zz_159_ = 1'b1;
end
end
end
if((! decode_RS2_USE))begin
_zz_159_ = 1'b0;
end
end
assign _zz_160_ = (_zz_51_ && writeBack_arbitration_isFiring);
assign _zz_164_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign _zz_165_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign _zz_166_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign _zz_167_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign _zz_168_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign _zz_169_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign _zz_34_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch;
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign _zz_170_ = execute_INSTRUCTION[14 : 12];
always @ (*) begin
if((_zz_170_ == (3'b000))) begin
_zz_171_ = execute_BranchPlugin_eq;
end else if((_zz_170_ == (3'b001))) begin
_zz_171_ = (! execute_BranchPlugin_eq);
end else if((((_zz_170_ & (3'b101)) == (3'b101)))) begin
_zz_171_ = (! execute_SRC_LESS);
end else begin
_zz_171_ = execute_SRC_LESS;
end
end
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_INC : begin
_zz_172_ = 1'b0;
end
`BranchCtrlEnum_defaultEncoding_JAL : begin
_zz_172_ = 1'b1;
end
`BranchCtrlEnum_defaultEncoding_JALR : begin
_zz_172_ = 1'b1;
end
default : begin
_zz_172_ = _zz_171_;
end
endcase
end
assign _zz_33_ = _zz_172_;
assign _zz_173_ = _zz_297_[11];
always @ (*) begin
_zz_174_[19] = _zz_173_;
_zz_174_[18] = _zz_173_;
_zz_174_[17] = _zz_173_;
_zz_174_[16] = _zz_173_;
_zz_174_[15] = _zz_173_;
_zz_174_[14] = _zz_173_;
_zz_174_[13] = _zz_173_;
_zz_174_[12] = _zz_173_;
_zz_174_[11] = _zz_173_;
_zz_174_[10] = _zz_173_;
_zz_174_[9] = _zz_173_;
_zz_174_[8] = _zz_173_;
_zz_174_[7] = _zz_173_;
_zz_174_[6] = _zz_173_;
_zz_174_[5] = _zz_173_;
_zz_174_[4] = _zz_173_;
_zz_174_[3] = _zz_173_;
_zz_174_[2] = _zz_173_;
_zz_174_[1] = _zz_173_;
_zz_174_[0] = _zz_173_;
end
assign _zz_175_ = _zz_298_[19];
always @ (*) begin
_zz_176_[10] = _zz_175_;
_zz_176_[9] = _zz_175_;
_zz_176_[8] = _zz_175_;
_zz_176_[7] = _zz_175_;
_zz_176_[6] = _zz_175_;
_zz_176_[5] = _zz_175_;
_zz_176_[4] = _zz_175_;
_zz_176_[3] = _zz_175_;
_zz_176_[2] = _zz_175_;
_zz_176_[1] = _zz_175_;
_zz_176_[0] = _zz_175_;
end
assign _zz_177_ = _zz_299_[11];
always @ (*) begin
_zz_178_[18] = _zz_177_;
_zz_178_[17] = _zz_177_;
_zz_178_[16] = _zz_177_;
_zz_178_[15] = _zz_177_;
_zz_178_[14] = _zz_177_;
_zz_178_[13] = _zz_177_;
_zz_178_[12] = _zz_177_;
_zz_178_[11] = _zz_177_;
_zz_178_[10] = _zz_177_;
_zz_178_[9] = _zz_177_;
_zz_178_[8] = _zz_177_;
_zz_178_[7] = _zz_177_;
_zz_178_[6] = _zz_177_;
_zz_178_[5] = _zz_177_;
_zz_178_[4] = _zz_177_;
_zz_178_[3] = _zz_177_;
_zz_178_[2] = _zz_177_;
_zz_178_[1] = _zz_177_;
_zz_178_[0] = _zz_177_;
end
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_JALR : begin
_zz_179_ = (_zz_300_[1] ^ execute_RS1[1]);
end
`BranchCtrlEnum_defaultEncoding_JAL : begin
_zz_179_ = _zz_301_[1];
end
default : begin
_zz_179_ = _zz_302_[1];
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_179_);
assign _zz_31_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1;
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC;
end
endcase
end
assign _zz_180_ = _zz_303_[11];
always @ (*) begin
_zz_181_[19] = _zz_180_;
_zz_181_[18] = _zz_180_;
_zz_181_[17] = _zz_180_;
_zz_181_[16] = _zz_180_;
_zz_181_[15] = _zz_180_;
_zz_181_[14] = _zz_180_;
_zz_181_[13] = _zz_180_;
_zz_181_[12] = _zz_180_;
_zz_181_[11] = _zz_180_;
_zz_181_[10] = _zz_180_;
_zz_181_[9] = _zz_180_;
_zz_181_[8] = _zz_180_;
_zz_181_[7] = _zz_180_;
_zz_181_[6] = _zz_180_;
_zz_181_[5] = _zz_180_;
_zz_181_[4] = _zz_180_;
_zz_181_[3] = _zz_180_;
_zz_181_[2] = _zz_180_;
_zz_181_[1] = _zz_180_;
_zz_181_[0] = _zz_180_;
end
always @ (*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_defaultEncoding_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_181_,execute_INSTRUCTION[31 : 20]};
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_183_,{{{_zz_504_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_185_,{{{_zz_505_,_zz_506_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
if(execute_PREDICTION_HAD_BRANCHED2)begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_306_};
end
end
endcase
end
assign _zz_182_ = _zz_304_[19];
always @ (*) begin
_zz_183_[10] = _zz_182_;
_zz_183_[9] = _zz_182_;
_zz_183_[8] = _zz_182_;
_zz_183_[7] = _zz_182_;
_zz_183_[6] = _zz_182_;
_zz_183_[5] = _zz_182_;
_zz_183_[4] = _zz_182_;
_zz_183_[3] = _zz_182_;
_zz_183_[2] = _zz_182_;
_zz_183_[1] = _zz_182_;
_zz_183_[0] = _zz_182_;
end
assign _zz_184_ = _zz_305_[11];
always @ (*) begin
_zz_185_[18] = _zz_184_;
_zz_185_[17] = _zz_184_;
_zz_185_[16] = _zz_184_;
_zz_185_[15] = _zz_184_;
_zz_185_[14] = _zz_184_;
_zz_185_[13] = _zz_184_;
_zz_185_[12] = _zz_184_;
_zz_185_[11] = _zz_184_;
_zz_185_[10] = _zz_184_;
_zz_185_[9] = _zz_184_;
_zz_185_[8] = _zz_184_;
_zz_185_[7] = _zz_184_;
_zz_185_[6] = _zz_184_;
_zz_185_[5] = _zz_184_;
_zz_185_[4] = _zz_184_;
_zz_185_[3] = _zz_184_;
_zz_185_[2] = _zz_184_;
_zz_185_[1] = _zz_184_;
_zz_185_[0] = _zz_184_;
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign _zz_30_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)};
assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC;
assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1]));
assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000);
assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC;
assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid;
always @ (*) begin
CsrPlugin_privilege = (2'b11);
if(CsrPlugin_forceMachineWire)begin
CsrPlugin_privilege = (2'b11);
end
end
assign CsrPlugin_misa_base = (2'b01);
assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010);
assign _zz_186_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_187_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_188_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
assign _zz_189_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
assign _zz_190_ = _zz_307_[0];
assign _zz_191_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid};
assign _zz_192_ = _zz_309_[0];
always @ (*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
if(_zz_229_)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
end
if(decode_arbitration_isFlushed)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
end
end
always @ (*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(execute_arbitration_isFlushed)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
end
always @ (*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(_zz_233_)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1;
end
if(memory_arbitration_isFlushed)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @ (*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(writeBack_arbitration_isFlushed)begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
assign CsrPlugin_lastStageWasWfi = 1'b0;
always @ (*) begin
CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3);
if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
if(CsrPlugin_hadException)begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
always @ (*) begin
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
if(CsrPlugin_hadException)begin
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
end
end
always @ (*) begin
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
if(CsrPlugin_hadException)begin
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
end
always @ (*) begin
CsrPlugin_xtvec_mode = (2'bxx);
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @ (*) begin
CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign _zz_28_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000)))));
assign _zz_27_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000));
assign execute_CsrPlugin_inWfi = 1'b0;
assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00));
always @ (*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
case(execute_CsrPlugin_csrAddress)
12'b101111000000 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
12'b001100000000 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
12'b001101000001 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
12'b001100000101 : begin
if(execute_CSR_WRITE_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
12'b001101000100 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
12'b001101000011 : begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
12'b111111000000 : begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
12'b001100000100 : begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
12'b001101000010 : begin
if(execute_CSR_READ_OPCODE)begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
default : begin
end
endcase
if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @ (*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin
if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
always @ (*) begin
execute_CsrPlugin_readData = (32'b00000000000000000000000000000000);
case(execute_CsrPlugin_csrAddress)
12'b101111000000 : begin
execute_CsrPlugin_readData[31 : 0] = _zz_200_;
end
12'b001100000000 : begin
execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP;
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE;
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE;
end
12'b001101000001 : begin
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc;
end
12'b001100000101 : begin
end
12'b001101000100 : begin
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP;
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP;
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP;
end
12'b001101000011 : begin
execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval;
end
12'b111111000000 : begin
execute_CsrPlugin_readData[31 : 0] = _zz_201_;
end
12'b001100000100 : begin
execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE;
execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE;
execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE;
end
12'b001101000010 : begin
execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt;
execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
default : begin
end
endcase
end
assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers));
assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData;
always @ (*) begin
case(_zz_254_)
1'b0 : begin
execute_CsrPlugin_writeData = execute_SRC1;
end
default : begin
execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
always @ (*) begin
memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0;
if(_zz_217_)begin
if(_zz_231_)begin
memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1;
end
end
end
always @ (*) begin
memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0;
if((! memory_arbitration_isStuck))begin
memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1;
end
end
assign memory_MulDivIterativePlugin_mul_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == (6'b100000));
assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement);
always @ (*) begin
if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin
memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000);
end else begin
memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_312_);
end
if(memory_MulDivIterativePlugin_mul_counter_willClear)begin
memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000);
end
end
always @ (*) begin
memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0;
if(_zz_218_)begin
if(_zz_232_)begin
memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @ (*) begin
memory_MulDivIterativePlugin_div_counter_willClear = 1'b0;
if(_zz_246_)begin
memory_MulDivIterativePlugin_div_counter_willClear = 1'b1;
end
end
assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == (6'b100001));
assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement);
always @ (*) begin
if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin
memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000);
end else begin
memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_320_);
end
if(memory_MulDivIterativePlugin_div_counter_willClear)begin
memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000);
end
end
assign _zz_193_ = memory_MulDivIterativePlugin_rs1[31 : 0];
assign _zz_194_ = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_193_[31]};
assign _zz_195_ = (_zz_194_ - _zz_321_);
assign _zz_196_ = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]);
assign _zz_197_ = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_198_ = ((execute_IS_MUL && _zz_197_) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @ (*) begin
_zz_199_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_199_[31 : 0] = execute_RS1;
end
assign _zz_201_ = (_zz_200_ & externalInterruptArray_regNext);
assign externalInterrupt = (_zz_201_ != (32'b00000000000000000000000000000000));
assign _zz_24_ = decode_SHIFT_CTRL;
assign _zz_22_ = _zz_73_;
assign _zz_37_ = decode_to_execute_SHIFT_CTRL;
assign _zz_21_ = decode_ENV_CTRL;
assign _zz_18_ = execute_ENV_CTRL;
assign _zz_16_ = memory_ENV_CTRL;
assign _zz_19_ = _zz_67_;
assign _zz_26_ = decode_to_execute_ENV_CTRL;
assign _zz_25_ = execute_to_memory_ENV_CTRL;
assign _zz_29_ = memory_to_writeBack_ENV_CTRL;
assign _zz_14_ = decode_SRC1_CTRL;
assign _zz_12_ = _zz_56_;
assign _zz_44_ = decode_to_execute_SRC1_CTRL;
assign _zz_11_ = decode_BRANCH_CTRL;
assign _zz_95_ = _zz_68_;
assign _zz_32_ = decode_to_execute_BRANCH_CTRL;
assign _zz_9_ = decode_SRC2_CTRL;
assign _zz_7_ = _zz_59_;
assign _zz_42_ = decode_to_execute_SRC2_CTRL;
assign _zz_6_ = decode_ALU_BITWISE_CTRL;
assign _zz_4_ = _zz_70_;
assign _zz_49_ = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_3_ = decode_ALU_CTRL;
assign _zz_1_ = _zz_72_;
assign _zz_47_ = decode_to_execute_ALU_CTRL;
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000)));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000)));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00)));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0)));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
assign iBusWishbone_ADR = {_zz_340_,_zz_202_};
assign iBusWishbone_CTI = ((_zz_202_ == (3'b111)) ? (3'b111) : (3'b010));
assign iBusWishbone_BTE = (2'b00);
assign iBusWishbone_SEL = (4'b1111);
assign iBusWishbone_WE = 1'b0;
assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx);
always @ (*) begin
iBusWishbone_CYC = 1'b0;
if(_zz_247_)begin
iBusWishbone_CYC = 1'b1;
end
end
always @ (*) begin
iBusWishbone_STB = 1'b0;
if(_zz_247_)begin
iBusWishbone_STB = 1'b1;
end
end
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
assign iBus_rsp_valid = _zz_203_;
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
assign iBus_rsp_payload_error = 1'b0;
assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid;
assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr;
assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address;
assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data;
assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size;
assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready;
assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2);
assign dBusWishbone_CTI = (3'b000);
assign dBusWishbone_BTE = (2'b00);
always @ (*) begin
case(dBus_cmd_halfPipe_payload_size)
2'b00 : begin
_zz_204_ = (4'b0001);
end
2'b01 : begin
_zz_204_ = (4'b0011);
end
default : begin
_zz_204_ = (4'b1111);
end
endcase
end
always @ (*) begin
dBusWishbone_SEL = _zz_341_[3:0];
if((! dBus_cmd_halfPipe_payload_wr))begin
dBusWishbone_SEL = (4'b1111);
end
end
assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr;
assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data;
assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK);
assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid;
assign dBusWishbone_STB = dBus_cmd_halfPipe_valid;
assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
assign dBus_rsp_data = dBusWishbone_DAT_MISO;
assign dBus_rsp_error = 1'b0;
always @ (posedge clk) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
_zz_112_ <= 1'b0;
_zz_114_ <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
IBusCachedPlugin_injector_decodeRemoved <= 1'b0;
IBusCachedPlugin_rspCounter <= _zz_127_;
IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000);
_zz_149_ <= 1'b1;
execute_LightShifterPlugin_isActive <= 1'b0;
_zz_161_ <= 1'b0;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= (2'b11);
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
memory_MulDivIterativePlugin_mul_counter_value <= (6'b000000);
memory_MulDivIterativePlugin_div_counter_value <= (6'b000000);
_zz_200_ <= (32'b00000000000000000000000000000000);
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000);
memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000);
_zz_202_ <= (3'b000);
_zz_203_ <= 1'b0;
dBus_cmd_halfPipe_regs_valid <= 1'b0;
dBus_cmd_halfPipe_regs_ready <= 1'b1;
end else begin
IBusCachedPlugin_fetchPc_booted <= 1'b1;
if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin
IBusCachedPlugin_fetchPc_inc <= 1'b1;
end
if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
end
if(IBusCachedPlugin_fetcherflushIt)begin
_zz_112_ <= 1'b0;
end
if(_zz_110_)begin
_zz_112_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid;
end
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin
_zz_114_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid;
end
if(IBusCachedPlugin_fetcherflushIt)begin
_zz_114_ <= 1'b0;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if((! execute_arbitration_isStuck))begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if((! memory_arbitration_isStuck))begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if((! writeBack_arbitration_isStuck))begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(decode_arbitration_removeIt)begin
IBusCachedPlugin_injector_decodeRemoved <= 1'b1;
end
if(IBusCachedPlugin_fetcherflushIt)begin
IBusCachedPlugin_injector_decodeRemoved <= 1'b0;
end
if(iBus_rsp_valid)begin
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001));
end
_zz_149_ <= 1'b0;
if(_zz_223_)begin
if(_zz_230_)begin
execute_LightShifterPlugin_isActive <= 1'b1;
if(execute_LightShifterPlugin_done)begin
execute_LightShifterPlugin_isActive <= 1'b0;
end
end
end
if(execute_arbitration_removeIt)begin
execute_LightShifterPlugin_isActive <= 1'b0;
end
_zz_161_ <= _zz_160_;
if((! decode_arbitration_isStuck))begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
end
if((! execute_arbitration_isStuck))begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if((! memory_arbitration_isStuck))begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if((! writeBack_arbitration_isStuck))begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(_zz_248_)begin
if(_zz_249_)begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(_zz_250_)begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(_zz_251_)begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(_zz_234_)begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(_zz_235_)begin
case(_zz_236_)
2'b11 : begin
CsrPlugin_mstatus_MPP <= (2'b00);
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= ({_zz_188_,{_zz_187_,_zz_186_}} != (3'b000));
memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext;
memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext;
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_35_;
end
if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin
execute_arbitration_isValid <= 1'b0;
end
if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin
memory_arbitration_isValid <= 1'b0;
end
if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin
writeBack_arbitration_isValid <= 1'b0;
end
if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
case(execute_CsrPlugin_csrAddress)
12'b101111000000 : begin
if(execute_CsrPlugin_writeEnable)begin
_zz_200_ <= execute_CsrPlugin_writeData[31 : 0];
end
end
12'b001100000000 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11];
CsrPlugin_mstatus_MPIE <= _zz_334_[0];
CsrPlugin_mstatus_MIE <= _zz_335_[0];
end
end
12'b001101000001 : begin
end
12'b001100000101 : begin
end
12'b001101000100 : begin
end
12'b001101000011 : begin
end
12'b111111000000 : begin
end
12'b001100000100 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mie_MEIE <= _zz_337_[0];
CsrPlugin_mie_MTIE <= _zz_338_[0];
CsrPlugin_mie_MSIE <= _zz_339_[0];
end
end
12'b001101000010 : begin
end
default : begin
end
endcase
if(_zz_247_)begin
if(iBusWishbone_ACK)begin
_zz_202_ <= (_zz_202_ + (3'b001));
end
end
_zz_203_ <= (iBusWishbone_CYC && iBusWishbone_ACK);
if(_zz_252_)begin
dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid;
dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid);
end else begin
dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready);
dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready;
end
end
end
always @ (posedge clk) begin
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin
_zz_115_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
end
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
end
if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
end
if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin
$display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend");
end
if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin
$display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend");
end
if(_zz_223_)begin
if(_zz_230_)begin
execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001));
end
end
if(_zz_160_)begin
_zz_162_ <= _zz_50_[11 : 7];
_zz_163_ <= _zz_79_;
end
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001));
if(writeBack_arbitration_isFiring)begin
CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001));
end
if(_zz_229_)begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_190_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_190_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
end
if(_zz_233_)begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_192_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_192_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr);
end
if(_zz_248_)begin
if(_zz_249_)begin
CsrPlugin_interrupt_code <= (4'b0111);
CsrPlugin_interrupt_targetPrivilege <= (2'b11);
end
if(_zz_250_)begin
CsrPlugin_interrupt_code <= (4'b0011);
CsrPlugin_interrupt_targetPrivilege <= (2'b11);
end
if(_zz_251_)begin
CsrPlugin_interrupt_code <= (4'b1011);
CsrPlugin_interrupt_targetPrivilege <= (2'b11);
end
end
if(_zz_234_)begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= writeBack_PC;
if(CsrPlugin_hadException)begin
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
end
end
default : begin
end
endcase
end
if(_zz_217_)begin
if(_zz_231_)begin
memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1);
memory_MulDivIterativePlugin_accumulator <= ({_zz_313_,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1);
end
end
if((memory_MulDivIterativePlugin_div_counter_value == (6'b100000)))begin
memory_MulDivIterativePlugin_div_done <= 1'b1;
end
if((! memory_arbitration_isStuck))begin
memory_MulDivIterativePlugin_div_done <= 1'b0;
end
if(_zz_218_)begin
if(_zz_232_)begin
memory_MulDivIterativePlugin_rs1[31 : 0] <= _zz_322_[31:0];
memory_MulDivIterativePlugin_accumulator[31 : 0] <= ((! _zz_195_[32]) ? _zz_323_ : _zz_324_);
if((memory_MulDivIterativePlugin_div_counter_value == (6'b100000)))begin
memory_MulDivIterativePlugin_div_result <= _zz_325_[31:0];
end
end
end
if(_zz_246_)begin
memory_MulDivIterativePlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000);
memory_MulDivIterativePlugin_rs1 <= ((_zz_198_ ? (~ _zz_199_) : _zz_199_) + _zz_331_);
memory_MulDivIterativePlugin_rs2 <= ((_zz_197_ ? (~ execute_RS2) : execute_RS2) + _zz_333_);
memory_MulDivIterativePlugin_div_needRevert <= ((_zz_198_ ^ (_zz_197_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
externalInterruptArray_regNext <= externalInterruptArray;
if((! execute_arbitration_isStuck))begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SHIFT_CTRL <= _zz_23_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_PC <= decode_PC;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_PC <= _zz_41_;
end
if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin
memory_to_writeBack_PC <= memory_PC;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_97_;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_FORMAL_PC_NEXT <= _zz_96_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ENV_CTRL <= _zz_20_;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_ENV_CTRL <= _zz_17_;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_ENV_CTRL <= _zz_15_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BRANCH_DO <= execute_BRANCH_DO;
end
if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_36_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_RS1 <= decode_RS1;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC1_CTRL <= _zz_13_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BRANCH_CTRL <= _zz_10_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MMU_FAULT <= execute_MMU_FAULT;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_RS2 <= decode_RS2;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW;
end
if((! writeBack_arbitration_isStuck))begin
memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if((! memory_arbitration_isStuck))begin
execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress;
execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess;
execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead;
execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite;
execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute;
execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception;
execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_SRC2_CTRL <= _zz_8_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_5_;
end
if((! execute_arbitration_isStuck))begin
decode_to_execute_ALU_CTRL <= _zz_2_;
end
case(execute_CsrPlugin_csrAddress)
12'b101111000000 : begin
end
12'b001100000000 : begin
end
12'b001101000001 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0];
end
end
12'b001100000101 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2];
CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0];
end
end
12'b001101000100 : begin
if(execute_CsrPlugin_writeEnable)begin
CsrPlugin_mip_MSIP <= _zz_336_[0];
end
end
12'b001101000011 : begin
end
12'b111111000000 : begin
end
12'b001100000100 : begin
end
12'b001101000010 : begin
end
default : begin
end
endcase
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
if(_zz_252_)begin
dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr;
dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address;
dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data;
dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size;
end
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// (c) Copyright 2011-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axisc_downsizer
// Convert from SI data width < MI datawidth.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_vdma_v6_2_8_axis_dwidth_converter_v1_0_axisc_upsizer #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_S_AXIS_TDATA_WIDTH = 32,
parameter integer C_M_AXIS_TDATA_WIDTH = 96,
parameter integer C_AXIS_TID_WIDTH = 1,
parameter integer C_AXIS_TDEST_WIDTH = 1,
parameter integer C_S_AXIS_TUSER_WIDTH = 1,
parameter integer C_M_AXIS_TUSER_WIDTH = 3,
parameter [31:0] C_AXIS_SIGNAL_SET = 32'hFF ,
// C_AXIS_SIGNAL_SET: each bit if enabled specifies which axis optional signals are present
// [0] => TREADY present
// [1] => TDATA present
// [2] => TSTRB present, TDATA must be present
// [3] => TKEEP present, TDATA must be present
// [4] => TLAST present
// [5] => TID present
// [6] => TDEST present
// [7] => TUSER present
parameter integer C_RATIO = 3 // Should always be 1:C_RATIO (upsizer)
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// System Signals
input wire ACLK,
input wire ARESET,
input wire ACLKEN,
// Slave side
input wire S_AXIS_TVALID,
output wire S_AXIS_TREADY,
input wire [C_S_AXIS_TDATA_WIDTH-1:0] S_AXIS_TDATA,
input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TSTRB,
input wire [C_S_AXIS_TDATA_WIDTH/8-1:0] S_AXIS_TKEEP,
input wire S_AXIS_TLAST,
input wire [C_AXIS_TID_WIDTH-1:0] S_AXIS_TID,
input wire [C_AXIS_TDEST_WIDTH-1:0] S_AXIS_TDEST,
input wire [C_S_AXIS_TUSER_WIDTH-1:0] S_AXIS_TUSER,
// Master side
output wire M_AXIS_TVALID,
input wire M_AXIS_TREADY,
output wire [C_M_AXIS_TDATA_WIDTH-1:0] M_AXIS_TDATA,
output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TSTRB,
output wire [C_M_AXIS_TDATA_WIDTH/8-1:0] M_AXIS_TKEEP,
output wire M_AXIS_TLAST,
output wire [C_AXIS_TID_WIDTH-1:0] M_AXIS_TID,
output wire [C_AXIS_TDEST_WIDTH-1:0] M_AXIS_TDEST,
output wire [C_M_AXIS_TUSER_WIDTH-1:0] M_AXIS_TUSER
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_vdma_v6_2_8_axis_infrastructure_v1_0_axis_infrastructure.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_READY_EXIST = C_AXIS_SIGNAL_SET[0];
localparam P_DATA_EXIST = C_AXIS_SIGNAL_SET[1];
localparam P_STRB_EXIST = C_AXIS_SIGNAL_SET[2];
localparam P_KEEP_EXIST = C_AXIS_SIGNAL_SET[3];
localparam P_LAST_EXIST = C_AXIS_SIGNAL_SET[4];
localparam P_ID_EXIST = C_AXIS_SIGNAL_SET[5];
localparam P_DEST_EXIST = C_AXIS_SIGNAL_SET[6];
localparam P_USER_EXIST = C_AXIS_SIGNAL_SET[7];
localparam P_S_AXIS_TSTRB_WIDTH = C_S_AXIS_TDATA_WIDTH/8;
localparam P_M_AXIS_TSTRB_WIDTH = C_M_AXIS_TDATA_WIDTH/8;
// State Machine possible states. Bits 1:0 used to encode output signals.
// /--- M_AXIS_TVALID state
// |/-- S_AXIS_TREADY state
localparam SM_RESET = 3'b000; // De-assert Ready during reset
localparam SM_IDLE = 3'b001; // R0 reg is empty
localparam SM_ACTIVE = 3'b101; // R0 reg is active
localparam SM_END = 3'b011; // R0 reg is empty and ACC reg is active
localparam SM_END_TO_ACTIVE = 3'b010; // R0/ACC reg are both active.
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [2:0] state;
reg [C_M_AXIS_TDATA_WIDTH-1:0] acc_data;
reg [P_M_AXIS_TSTRB_WIDTH-1:0] acc_strb;
reg [P_M_AXIS_TSTRB_WIDTH-1:0] acc_keep;
reg acc_last;
reg [C_AXIS_TID_WIDTH-1:0] acc_id;
reg [C_AXIS_TDEST_WIDTH-1:0] acc_dest;
reg [C_M_AXIS_TUSER_WIDTH-1:0] acc_user;
wire [C_RATIO-1:0] acc_reg_en;
reg [C_RATIO-1:0] r0_reg_sel;
wire next_xfer_is_end;
reg [C_S_AXIS_TDATA_WIDTH-1:0] r0_data;
reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_strb;
reg [P_S_AXIS_TSTRB_WIDTH-1:0] r0_keep;
reg r0_last;
reg [C_AXIS_TID_WIDTH-1:0] r0_id;
reg [C_AXIS_TDEST_WIDTH-1:0] r0_dest;
reg [C_S_AXIS_TUSER_WIDTH-1:0] r0_user;
wire id_match;
wire dest_match;
wire id_dest_mismatch;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// S Ready/M Valid outputs are encoded in the current state.
assign S_AXIS_TREADY = state[0];
assign M_AXIS_TVALID = state[1];
// State machine controls M_AXIS_TVALID and S_AXIS_TREADY, and loading
always @(posedge ACLK) begin
if (ARESET) begin
state <= SM_RESET;
end else if (ACLKEN) begin
case (state)
SM_RESET: begin
state <= SM_IDLE;
end
SM_IDLE: begin
if (S_AXIS_TVALID & id_dest_mismatch & ~r0_reg_sel[0]) begin
state <= SM_END_TO_ACTIVE;
end
else if (S_AXIS_TVALID & next_xfer_is_end) begin
state <= SM_END;
end
else if (S_AXIS_TVALID) begin
state <= SM_ACTIVE;
end
else begin
state <= SM_IDLE;
end
end
SM_ACTIVE: begin
if (S_AXIS_TVALID & (id_dest_mismatch | r0_last)) begin
state <= SM_END_TO_ACTIVE;
end
else if ((~S_AXIS_TVALID & r0_last) | (S_AXIS_TVALID & next_xfer_is_end)) begin
state <= SM_END;
end
else if (S_AXIS_TVALID & ~next_xfer_is_end) begin
state <= SM_ACTIVE;
end
else begin
state <= SM_IDLE;
end
end
SM_END: begin
if (M_AXIS_TREADY & S_AXIS_TVALID) begin
state <= SM_ACTIVE;
end
else if ( ~M_AXIS_TREADY & S_AXIS_TVALID) begin
state <= SM_END_TO_ACTIVE;
end
else if ( M_AXIS_TREADY & ~S_AXIS_TVALID) begin
state <= SM_IDLE;
end
else begin
state <= SM_END;
end
end
SM_END_TO_ACTIVE: begin
if (M_AXIS_TREADY) begin
state <= SM_ACTIVE;
end
else begin
state <= SM_END_TO_ACTIVE;
end
end
default: begin
state <= SM_IDLE;
end
endcase // case (state)
end
end
assign M_AXIS_TDATA = acc_data;
assign M_AXIS_TSTRB = acc_strb;
assign M_AXIS_TKEEP = acc_keep;
assign M_AXIS_TUSER = acc_user;
generate
genvar i;
// DATA/USER/STRB/KEEP accumulators
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_data[0*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= acc_reg_en[0] ? r0_data
: acc_data[0*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
acc_user[0*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= acc_reg_en[0] ? r0_user
: acc_user[0*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
acc_strb[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? r0_strb
: acc_strb[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
acc_keep[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? r0_keep
: acc_keep[0*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
end
end
for (i = 1; i < C_RATIO-1; i = i + 1) begin : gen_data_accumulator
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_data[i*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= acc_reg_en[i] ? r0_data
: acc_data[i*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
acc_user[i*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= acc_reg_en[i] ? r0_user
: acc_user[i*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
acc_strb[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? {P_S_AXIS_TSTRB_WIDTH{1'b0}}
: acc_reg_en[i] ? r0_strb : acc_strb[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
acc_keep[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= acc_reg_en[0] ? {P_S_AXIS_TSTRB_WIDTH{1'b0}}
: acc_reg_en[i] ? r0_keep : acc_keep[i*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
end
end
end
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_data[(C_RATIO-1)*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH] <= (state == SM_IDLE) | (state == SM_ACTIVE)
? S_AXIS_TDATA : acc_data[(C_RATIO-1)*C_S_AXIS_TDATA_WIDTH+:C_S_AXIS_TDATA_WIDTH];
acc_user[(C_RATIO-1)*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH] <= (state == SM_IDLE) | (state == SM_ACTIVE)
? S_AXIS_TUSER : acc_user[(C_RATIO-1)*C_S_AXIS_TUSER_WIDTH+:C_S_AXIS_TUSER_WIDTH];
acc_strb[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= (acc_reg_en[0] && C_RATIO > 2) | (state == SM_ACTIVE & r0_last) | (id_dest_mismatch & (state == SM_ACTIVE | state == SM_IDLE))
? {P_S_AXIS_TSTRB_WIDTH{1'b0}} : (state == SM_IDLE) | (state == SM_ACTIVE)
? S_AXIS_TSTRB : acc_strb[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
acc_keep[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH] <= (acc_reg_en[0] && C_RATIO > 2) | (state == SM_ACTIVE & r0_last) | (id_dest_mismatch & (state == SM_ACTIVE| state == SM_IDLE))
? {P_S_AXIS_TSTRB_WIDTH{1'b0}} : (state == SM_IDLE) | (state == SM_ACTIVE)
? S_AXIS_TKEEP : acc_keep[(C_RATIO-1)*P_S_AXIS_TSTRB_WIDTH+:P_S_AXIS_TSTRB_WIDTH];
end
end
endgenerate
assign acc_reg_en = (state == SM_ACTIVE) ? r0_reg_sel : {C_RATIO{1'b0}};
// Accumulator selector (1 hot left barrel shifter)
always @(posedge ACLK) begin
if (ARESET) begin
r0_reg_sel[0] <= 1'b1;
r0_reg_sel[1+:C_RATIO-1] <= {C_RATIO{1'b0}};
end else if (ACLKEN) begin
r0_reg_sel[0] <= M_AXIS_TVALID & M_AXIS_TREADY ? 1'b1
: (state == SM_ACTIVE) ? 1'b0 : r0_reg_sel[0];
r0_reg_sel[1+:C_RATIO-1] <= M_AXIS_TVALID & M_AXIS_TREADY ? {C_RATIO-1{1'b0}}
: (state == SM_ACTIVE) ? r0_reg_sel[0+:C_RATIO-1] : r0_reg_sel[1+:C_RATIO-1];
end
end
assign next_xfer_is_end = (r0_reg_sel[C_RATIO-2] && (state == SM_ACTIVE)) | r0_reg_sel[C_RATIO-1];
always @(posedge ACLK) begin
if (ACLKEN) begin
r0_data <= S_AXIS_TREADY ? S_AXIS_TDATA : r0_data;
r0_strb <= S_AXIS_TREADY ? S_AXIS_TSTRB : r0_strb;
r0_keep <= S_AXIS_TREADY ? S_AXIS_TKEEP : r0_keep;
r0_last <= (!P_LAST_EXIST) ? 1'b0 : S_AXIS_TREADY ? S_AXIS_TLAST : r0_last;
r0_id <= (S_AXIS_TREADY & S_AXIS_TVALID) ? S_AXIS_TID : r0_id;
r0_dest <= (S_AXIS_TREADY & S_AXIS_TVALID) ? S_AXIS_TDEST : r0_dest;
r0_user <= S_AXIS_TREADY ? S_AXIS_TUSER : r0_user;
end
end
assign M_AXIS_TLAST = acc_last;
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_last <= (state == SM_END | state == SM_END_TO_ACTIVE) ? acc_last :
(state == SM_ACTIVE & r0_last ) ? 1'b1 :
(id_dest_mismatch & (state == SM_IDLE)) ? 1'b0 :
(id_dest_mismatch & (state == SM_ACTIVE)) ? r0_last :
S_AXIS_TLAST;
end
end
assign M_AXIS_TID = acc_id;
assign M_AXIS_TDEST = acc_dest;
always @(posedge ACLK) begin
if (ACLKEN) begin
acc_id <= acc_reg_en[0] ? r0_id : acc_id;
acc_dest <= acc_reg_en[0] ? r0_dest : acc_dest;
end
end
assign id_match = P_ID_EXIST ? (S_AXIS_TID == r0_id) : 1'b1;
assign dest_match = P_DEST_EXIST ? (S_AXIS_TDEST == r0_dest) : 1'b1;
assign id_dest_mismatch = (~id_match | ~dest_match) ? 1'b1 : 1'b0;
endmodule // axisc_upsizer
`default_nettype wire
|
// add check for wg out of inflight wg buffer
module host_test (/*AUTOARG*/
// Outputs
host_wg_valid, host_wg_id, host_num_wf, host_vgpr_size_per_wf,
host_vgpr_size_total, host_sgpr_size_per_wf, host_sgpr_size_total,
host_lds_size_total, host_gds_size_total, host_wf_size,
host_start_pc, all_wf_dispatched,
// Inputs
rst, clk, inflight_wg_buffer_host_rcvd_ack
) ;
input rst, clk;
input inflight_wg_buffer_host_rcvd_ack;
parameter WG_ID_WIDTH = 6;
parameter WG_SLOT_ID_WIDTH = 6;
parameter CU_ID_WIDTH = 2;
parameter WAVE_ITEM_WIDTH = 6;
parameter WF_COUNT_WIDTH = 4;
localparam MAX_WF_PER_WG = 2**WF_COUNT_WIDTH;
parameter MEM_ADDR_WIDTH = 32;
parameter VGPR_ID_WIDTH = 8;
parameter NUMBER_VGPR_SLOTS = 256;
parameter SGPR_ID_WIDTH = 4;
parameter NUMBER_SGPR_SLOTS = 13;
parameter LDS_ID_WIDTH = 8;
parameter NUMBER_LDS_SLOTS = 256;
parameter GDS_ID_WIDTH = 14;
parameter GDS_SIZE = 16384;
output reg host_wg_valid;
output reg [WG_ID_WIDTH-1:0] host_wg_id;
output reg [WF_COUNT_WIDTH-1:0] host_num_wf;
output reg [VGPR_ID_WIDTH:0] host_vgpr_size_per_wf;
output reg [VGPR_ID_WIDTH:0] host_vgpr_size_total;
output reg [SGPR_ID_WIDTH:0] host_sgpr_size_per_wf;
output reg [SGPR_ID_WIDTH:0] host_sgpr_size_total;
output reg [LDS_ID_WIDTH:0] host_lds_size_total;
output reg [GDS_ID_WIDTH:0] host_gds_size_total;
output reg [WAVE_ITEM_WIDTH-1:0] host_wf_size;
output reg [MEM_ADDR_WIDTH-1:0] host_start_pc;
output reg all_wf_dispatched;
localparam NUM_ADDED_WG = 10;
reg [WG_ID_WIDTH-1:0] sim_host_wg_id[NUM_ADDED_WG-1:0];
reg [WAVE_ITEM_WIDTH-1:0] sim_host_wf_size[NUM_ADDED_WG-1:0];
reg [WF_COUNT_WIDTH-1:0] sim_host_num_wf[NUM_ADDED_WG-1:0];
reg [VGPR_ID_WIDTH:0] sim_host_vgpr_size_per_wf[NUM_ADDED_WG-1:0];
reg [VGPR_ID_WIDTH:0] sim_host_vgpr_size_total[NUM_ADDED_WG-1:0];
reg [SGPR_ID_WIDTH:0] sim_host_sgpr_size_per_wf[NUM_ADDED_WG-1:0];
reg [SGPR_ID_WIDTH:0] sim_host_sgpr_size_total[NUM_ADDED_WG-1:0];
reg [LDS_ID_WIDTH:0] sim_host_lds_size_total[NUM_ADDED_WG-1:0];
reg [GDS_ID_WIDTH:0] sim_host_gds_size_total[NUM_ADDED_WG-1:0];
reg [MEM_ADDR_WIDTH-1:0] sim_host_start_pc[NUM_ADDED_WG-1:0];
reg [NUM_ADDED_WG-1:0] sim_wg_accepted
= '{ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
reg [NUM_ADDED_WG-1:0] sim_wg_issued
= '{ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
reg [NUM_ADDED_WG-1:0] sim_wg_ended
= '{ 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
integer host_curr_wg;
initial begin : INITIALIZE_VALUES
integer currInit;
for (currInit = 0; currInit < NUM_ADDED_WG; currInit=currInit+1) begin
sim_host_wg_id[currInit] = currInit;
sim_host_wf_size[currInit] = ({$random}%(2**WAVE_ITEM_WIDTH)) + 1;
sim_host_num_wf[currInit] = ({$random}%(MAX_WF_PER_WG-1))+1;
sim_host_vgpr_size_per_wf[currInit]
= {$random}%(NUMBER_VGPR_SLOTS/sim_host_num_wf[currInit]);
sim_host_vgpr_size_total[currInit]
= sim_host_vgpr_size_per_wf[currInit]*sim_host_num_wf[currInit];
sim_host_sgpr_size_per_wf[currInit]
= {$random}%(NUMBER_SGPR_SLOTS/sim_host_num_wf[currInit]);
sim_host_sgpr_size_total[currInit]
= sim_host_sgpr_size_per_wf[currInit]*sim_host_num_wf[currInit];
sim_host_lds_size_total[currInit]
= {$random}%NUMBER_LDS_SLOTS;
sim_host_gds_size_total[currInit]
= {$random}%(GDS_SIZE/50);
sim_host_start_pc[currInit] = {$random};
end
end
task host_new_wf;
input [WG_ID_WIDTH-1:0] wg_id;
input [WF_COUNT_WIDTH-1:0] num_wf;
input [WAVE_ITEM_WIDTH-1:0] wf_size;
input [VGPR_ID_WIDTH:0] vgpr_size_total;
input [VGPR_ID_WIDTH:0] vgpr_size_per_wf;
input [SGPR_ID_WIDTH:0] sgpr_size_total;
input [SGPR_ID_WIDTH:0] sgpr_size_per_wf;
input [LDS_ID_WIDTH:0] lds_size_total;
input [GDS_ID_WIDTH:0] gds_size_total;
input [MEM_ADDR_WIDTH-1:0] start_pc;
begin
host_wg_valid = 1'b1;
host_wg_id = wg_id;
host_num_wf = num_wf;
host_wf_size = wf_size;
host_gds_size_total = gds_size_total;
host_lds_size_total= lds_size_total;
host_sgpr_size_per_wf = sgpr_size_per_wf;
host_sgpr_size_total = sgpr_size_total;
host_vgpr_size_per_wf = vgpr_size_per_wf;
host_vgpr_size_total = vgpr_size_total;
host_start_pc = start_pc;
@(posedge clk);
while(!inflight_wg_buffer_host_rcvd_ack) @(posedge clk);
@(posedge clk);
host_wg_valid = 1'b0;
end
endtask //
// Host block
initial begin
host_curr_wg = 0;
host_wg_valid = 1'b0;
all_wf_dispatched = 1'b0;
@(posedge clk);
@(negedge rst);
@(posedge clk);
for (host_curr_wg = 0; host_curr_wg<NUM_ADDED_WG;
host_curr_wg = host_curr_wg + 1) begin
host_new_wf(sim_host_wg_id[host_curr_wg], sim_host_num_wf[host_curr_wg],
sim_host_wf_size[host_curr_wg],
sim_host_vgpr_size_total[host_curr_wg],
sim_host_vgpr_size_per_wf[host_curr_wg],
sim_host_sgpr_size_total[host_curr_wg],
sim_host_sgpr_size_per_wf[host_curr_wg],
sim_host_lds_size_total[host_curr_wg],
sim_host_gds_size_total[host_curr_wg],
sim_host_start_pc[host_curr_wg]);
@(posedge clk);
end
@(posedge clk);
@(posedge clk);
all_wf_dispatched = 1'b1;
end
endmodule // host_test
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////////////
// Company: Digilent Inc.
// Engineer: Andrew Skreen
//
// Create Date: 07/11/2012
// Module Name: decimal_select
// Project Name: PmodGYRO_Demo
// Target Devices: Nexys3
// Tool versions: ISE 14.1
// Description: Select decimal display data.
//
// Revision History:
// Revision 0.01 - File Created (Andrew Skreen)
// Revision 1.00 - Added Comments and Converted to Verilog (Josh Sackos)
//////////////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module decimal_select(
control,
dp
);
// ==============================================================================
// Port Declarations
// ==============================================================================
input [1:0] control;
output dp;
// ==============================================================================
// Implementation
// ==============================================================================
assign dp = (control == 2'b11) ? 1'b1 :
(control == 2'b10) ? 1'b1 :
(control == 2'b01) ? 1'b1 :
1'b1;
endmodule
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
// Date : Tue Jun 21 04:37:54 2016
// Host : jalapeno running 64-bit unknown
// Command : write_verilog -force -mode synth_stub {/home/hhassan/git/GateKeeper/FPGA
// Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/clk_gen/clk_gen_stub.v}
// Design : clk_gen
// Purpose : Stub declaration of top-level module interface
// Device : xc7vx690tffg1761-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module clk_gen(clk_in1, clk_out1, reset)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,reset" */;
input clk_in1;
output clk_out1;
input reset;
endmodule
|
// generates activity on avr SPI aimed to send bytes over SDcard SPI.
//
`ifdef SPITEST
`include "../include/tune.v"
`define AVR_HALF_PERIOD (45.2)
module spitest_avr(
output wire spick,
output reg spics_n,
output wire spido,
input wire spidi
);
reg aclk;
reg spistart;
wire spirdy;
reg [7:0] spidin;
wire [7:0] spidout;
// clock gen
initial
begin
aclk = 1'b0;
forever #`AVR_HALF_PERIOD aclk = ~aclk;
end
// signals init
initial
begin
spics_n = 1'b1;
spistart = 1'b0;
end
// use standard spi2 module to send and receive over SPI.
// reverse bytes since spi2 sends and receives MSB first,
// while slavespi LSB first
spi2 spi2(
.clock(aclk),
.sck(spick),
.sdo(spido),
.sdi(spidi),
.bsync(),
.start(spistart),
.rdy (spirdy ),
.speed(2'b00),
.din ({spidin[0], spidin[1], spidin[2], spidin[3],
spidin[4], spidin[5], spidin[6], spidin[7]}),
.dout({spidout[0], spidout[1], spidout[2], spidout[3],
spidout[4], spidout[5], spidout[6], spidout[7]})
);
// test loop
initial
begin
repeat(2211) @(posedge aclk);
forever
begin
get_access();
send_msg();
release_access();
repeat(1234) @(posedge aclk);
end
end
task get_access(
);
reg [7:0] tmp;
reg_io( 8'h61, 8'h81, tmp );
while( !tmp[7] )
reg_io( 8'h61, 8'h81, tmp );
endtask
task send_msg(
);
reg [7:0] tmp;
reg [71:0] msg = "AVR SEND\n";
integer i;
reg_io( 8'h61, 8'h80, tmp );
for(i=8;i>=0;i=i-1)
begin
reg_io( 8'h60, msg[i*8 +: 8], tmp );
end
reg_io( 8'h61, 8'h81, tmp );
endtask
task release_access(
);
reg [7:0] tmp;
reg_io( 8'h61, 8'h81, tmp );
reg_io( 8'h61, 8'h01, tmp );
endtask
task reg_io(
input [7:0] addr,
input [7:0] wrdata,
output [7:0] rddata
);
reg [7:0] trash;
spics_n <= 1'b1;
@(posedge aclk);
spi_io( addr, trash );
spics_n <= 1'b0;
@(posedge aclk);
spi_io( wrdata, rddata );
spics_n <= 1'b1;
@(posedge aclk);
endtask
task spi_io(
input [7:0] wrdata,
output [7:0] rddata
);
spidin <= wrdata;
spistart <= 1'b1;
@(posedge aclk);
spistart <= 1'b0;
@(posedge aclk);
wait(spirdy==1'b1);
@(posedge aclk);
rddata = spidout;
endtask
endmodule
`endif
|
//-----------------------------------------------
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_simple_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH-1:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = (0);
localparam [C_AWIDTH-1:0] C_FULL = C_EMPTY-1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = (C_DEPTH < 8) ? C_FULL-1 : C_FULL-(C_DEPTH/8);
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH-1:0] cnt_read;
// synthesis attribute MAX_FANOUT of cnt_read is 10;
///////////////////////////////////////
// Main simple FIFO Array
///////////////////////////////////////
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else if ( wr_en & !rd_en) cnt_read <= cnt_read + 1'b1;
else if (!wr_en & rd_en) cnt_read <= cnt_read - 1'b1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = ((cnt_read >= C_FULL_PRE) && (cnt_read != C_EMPTY));
assign a_empty = (cnt_read == C_EMPTY_PRE);
assign dout = (C_DEPTH == 1) ? memory[0] : memory[cnt_read];
endmodule // axi_protocol_converter_v2_1_b2s_simple_fifo
`default_nettype wire
|
// ******************************************************************************* //
// ** General Information ** //
// ******************************************************************************* //
// ** Module : firdecim_m5_n15.v ** //
// ** Project : ISAAC Newton ** //
// ** Author : Kayla Nguyen ** //
// ** First Release Date : August 13, 2008 ** //
// ** Description : Polyphase Decimation Filter ** //
// ** M = 5, L = 15 ** //
// ******************************************************************************* //
// ** Revision History ** //
// ******************************************************************************* //
// ** ** //
// ** File : firdecim_m5_n15.v ** //
// ** Revision : 1 ** //
// ** Author : kaylangu ** //
// ** Date : August 13, 2008 ** //
// ** FileName : ** //
// ** Notes : Initial Release for ISAAC demo ** //
// ** ** //
// ** File : firdecim_m5_n15.v ** //
// ** Revision : 2 ** //
// ** Author : kaylangu ** //
// ** Date : October 23, 2008 ** //
// ** FileName : ** //
// ** Notes : Add Sync signal to synchronize filter with LkupTbl ** //
// ** ** //
// ** File : firdecim_m5_n15.v ** //
// ** Revision : 3 ** //
// ** Author : kaylangu ** //
// ** Date : January 28, 2009 ** //
// ** FileName : ** //
// ** Notes : Remove Sync signal ** //
// ** ** //
// ** File : firdecim_m5_n15.v ** //
// ** Revision : 4 ** //
// ** Author : kaylangu ** //
// ** Date : February 9, 2009 ** //
// ** FileName : ** //
// ** Notes : Remove shift registers for coefficients and replace with ** //
// ** distrubited ROMs ** //
// ** ** //
// ******************************************************************************* //
`timescale 1 ns / 100 ps
module firdecim_m5_n15
(/*AUTOARG*/
// Outputs
SigOut, DataValid,
// Inputs
CLK, ARST, InputValid, SigIn
);
//**************************************************************************//
//* Declarations *//
//**************************************************************************//
// DATA TYPE - PARAMETERS
parameter IWIDTH = 16;
parameter OWIDTH = 32;
parameter ACCUMWIDTH = 32;
// DATA TYPE - INPUTS AND OUTPUTS
output reg signed [(OWIDTH-1):0] SigOut;
output reg DataValid;
input CLK; // 60MHz Clock
input ARST;
input InputValid;
input signed [(IWIDTH-1):0] SigIn;
// DATA TYPE - REGISTERS
reg signed [15:0] coe10;
reg signed [15:0] coe5;
reg signed [15:0] coe0;
reg [3:0] count;
// DATA TYPE - WIRES
wire signed [(ACCUMWIDTH-1):0] SigOut1;
wire signed [(ACCUMWIDTH-1):0] SigOut2;
wire signed [(ACCUMWIDTH-1):0] SigOut3;
wire initialize1;
wire initialize2;
wire initialize3;
wire DataValid1;
wire DataValid2;
wire DataValid3;
wire [3:0] coe0_cnt;
wire [3:0] coe5_cnt;
wire [3:0] coe10_cnt;
//**************************************************************************//
//* Coefficient Rotation *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
coe0[15:0] <= 16'd0;
end
else
begin
case (coe0_cnt[3:0])
4'b0000: coe0[15:0] <= 16'sb1111111111001010;//0000_0000_0001_1111
4'b0001: coe0[15:0] <= 16'sb1111111111011001;//0000_0000_1000_1101
4'b0010: coe0[15:0] <= 16'sb0000000001111110;//0000_0001_1000_0010
4'b0011: coe0[15:0] <= 16'sb0000001000101101;//0000_0011_0001_1110
4'b0100: coe0[15:0] <= 16'sb0000010011101110;//0000_0101_0011_1111
4'b0101: coe0[15:0] <= 16'sb0000100000100111;//0000_0111_0111_1000
4'b0110: coe0[15:0] <= 16'sb0000101011001010;//0000_1001_0010_1011
4'b0111: coe0[15:0] <= 16'sb0000101111001111;//0000_1001_1100_1111
4'b1000: coe0[15:0] <= 16'sb0000101011001010;//0000_1001_0010_1011
4'b1001: coe0[15:0] <= 16'sb0000100000100111;//0000_0111_0111_1000
4'b1010: coe0[15:0] <= 16'sb0000010011101110;//0000_0101_0011_1111
4'b1011: coe0[15:0] <= 16'sb0000001000101101;//0000_0011_0001_1110
4'b1100: coe0[15:0] <= 16'sb0000000001111110;//0000_0001_1000_0010
4'b1101: coe0[15:0] <= 16'sb1111111111011001;//0000_0000_1000_1101
4'b1110: coe0[15:0] <= 16'sb1111111111001010;//0000_0000_0001_1111
default: coe0[15:0] <= 16'sb1111111111001010;//0000_0000_0001_1111;
endcase
end
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
coe5[15:0] <= 16'd0;
end
else
begin
case (coe5_cnt[3:0])
4'b0000: coe5[15:0] <= 16'sb1111111111001010;//0000_0000_0001_1111;
4'b0001: coe5[15:0] <= 16'sb1111111111011001;//0000_0000_1000_1101;
4'b0010: coe5[15:0] <= 16'sb0000000001111110;//0000_0001_1000_0010;
4'b0011: coe5[15:0] <= 16'sb0000001000101101;//0000_0011_0001_1110;
4'b0100: coe5[15:0] <= 16'sb0000010011101110;//0000_0101_0011_1111;
4'b0101: coe5[15:0] <= 16'sb0000100000100111;//0000_0111_0111_1000;
4'b0110: coe5[15:0] <= 16'sb0000101011001010;//0000_1001_0010_1011;
4'b0111: coe5[15:0] <= 16'sb0000101111001111;//0000_1001_1100_1111;
4'b1000: coe5[15:0] <= 16'sb0000101011001010;//0000_1001_0010_1011;
4'b1001: coe5[15:0] <= 16'sb0000100000100111;//0000_0111_0111_1000;
4'b1010: coe5[15:0] <= 16'sb0000010011101110;//0000_0101_0011_1111;
4'b1011: coe5[15:0] <= 16'sb0000001000101101;//0000_0011_0001_1110;
4'b1100: coe5[15:0] <= 16'sb0000000001111110;//0000_0001_1000_0010;
4'b1101: coe5[15:0] <= 16'sb1111111111011001;//0000_0000_1000_1101;
4'b1110: coe5[15:0] <= 16'sb1111111111001010;//0000_0000_0001_1111;
default: coe5[15:0] <= 16'sb1111111111001010;//0000_0000_0001_1111;
endcase
end
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
coe10[15:0] <= 16'd0;
end
else
begin
case (coe10_cnt[3:0])
4'b0000: coe10[15:0] <= 16'sb1111111111001010;//0000_0000_0001_1111;
4'b0001: coe10[15:0] <= 16'sb1111111111011001;//0000_0000_1000_1101;
4'b0010: coe10[15:0] <= 16'sb0000000001111110;//0000_0001_1000_0010;
4'b0011: coe10[15:0] <= 16'sb0000001000101101;//0000_0011_0001_1110;
4'b0100: coe10[15:0] <= 16'sb0000010011101110;//0000_0101_0011_1111;
4'b0101: coe10[15:0] <= 16'sb0000100000100111;//0000_0111_0111_1000;
4'b0110: coe10[15:0] <= 16'sb0000101011001010;//0000_1001_0010_1011;
4'b0111: coe10[15:0] <= 16'sb0000101111001111;//0000_1001_1100_1111;
4'b1000: coe10[15:0] <= 16'sb0000101011001010;//0000_1001_0010_1011;
4'b1001: coe10[15:0] <= 16'sb0000100000100111;//0000_0111_0111_1000;
4'b1010: coe10[15:0] <= 16'sb0000010011101110;//0000_0101_0011_1111;
4'b1011: coe10[15:0] <= 16'sb0000001000101101;//0000_0011_0001_1110;
4'b1100: coe10[15:0] <= 16'sb0000000001111110;//0000_0001_1000_0010;
4'b1101: coe10[15:0] <= 16'sb1111111111011001;//0000_0000_1000_1101;
4'b1110: coe10[15:0] <= 16'sb1111111111001010;//0000_0000_0001_1111;
default: coe10[15:0] <= 16'sb1111111111001010;//0000_0000_0001_1111;
endcase
end
//**************************************************************************//
//* Counter *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
count[3:0] <= {(4){1'b0}} ;
end
else if (InputValid)
begin
count[3:0] <= (count[3:0] == (14)) ? 0 : count[3:0] + 1 ;
end
assign coe0_cnt[3:0] = count[3:0] == 14 ? 0 :
count[3:0] + 1;
assign coe5_cnt[3:0] = (count[3:0] + 6 ) > 14 ? count[3:0] - 9 :
count[3:0] + 6 ;
assign coe10_cnt[3:0] = (count[3:0] + 11 ) > 14 ? count[3:0] - 4 :
count[3:0] + 11 ;
//**************************************************************************//
//* Reset each MAC *//
//**************************************************************************//
assign initialize1 = (count == 0) ;
assign initialize2 = (count == 5) ;
assign initialize3 = (count == 10) ;
//**************************************************************************//
//* Output Buffers *//
//**************************************************************************//
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
SigOut[(OWIDTH-1):0] <= {(OWIDTH){1'b0}};
end
else if (DataValid1 | DataValid2 | DataValid3)
begin
SigOut[(OWIDTH-1):0] <= {(OWIDTH){DataValid1}} & SigOut1 |
{(OWIDTH){DataValid2}} & SigOut2 |
{(OWIDTH){DataValid3}} & SigOut3 ;
end
always @ (posedge CLK or posedge ARST)
if (ARST)
begin
DataValid <= 1'b0 ;
end
else
begin
DataValid <= (DataValid1 | DataValid2 | DataValid3) ;
end
//**************************************************************************//
//* Submodules *//
//**************************************************************************//
//First MAC
MAC1 MAC1_a
(// Inputs
.CLK (CLK), // CLK
.ARST (ARST), // ARST
.filterCoef (coe0), // Filter Coeficients
.InData (SigIn), // Input Data
.input_Valid (InputValid), // Input Valid
.initialize (initialize1), // Initialize
//Outputs
.OutData (SigOut1), // Output Data
.output_Valid (DataValid1) // Output Valid
);
// Second MAC
MAC1 MAC1_b
(// Inputs
.CLK (CLK), // CLK
.ARST (ARST), // ARST
.filterCoef (coe10), // Filter Coeficients
.InData (SigIn), // Input Data
.input_Valid (InputValid), // Input Valid
.initialize (initialize2), // Initialize
//Outputs
.OutData (SigOut2), // Output Data
.output_Valid (DataValid2) // Output Valid
);
// Third MAC
MAC1 MAC1_c
(// Inputs
.CLK (CLK), // CLK
.ARST (ARST), // ARST
.filterCoef (coe5), // Filter Coeficients
.InData (SigIn), // Input Data
.input_Valid (InputValid), // Input Valid
.initialize (initialize3), // Initialize
//Outputs
.OutData (SigOut3), // Output Data
.output_Valid (DataValid3) // Output Valid
);
endmodule // firdecim_m5_n15 |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:36:46 09/06/2015
// Design Name:
// Module Name: FPU_Multiplication_Function
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module FPU_Multiplication_Function
//SINGLE PRECISION PARAMETERS
/*# (parameter W = 32, parameter EW = 8, parameter SW = 23) // */
//DOUBLE PRECISION PARAMETERS
# (parameter W = 64, parameter EW = 11, parameter SW = 52) // */
(
input wire clk,
input wire rst,
input wire beg_FSM,
input wire ack_FSM,
input wire [W-1:0] Data_MX,
input wire [W-1:0] Data_MY,
input wire [1:0] round_mode,
output wire overflow_flag,
output wire underflow_flag,
output wire ready,
output wire [W-1:0] final_result_ieee
);
//GENERAL
wire rst_int; //**
//FSM_load_signals
wire FSM_first_phase_load; //**
wire FSM_load_first_step; /*Zero flag, Exp operation underflow, Sgf operation first reg,
sign result reg*/
wire FSM_exp_operation_load_result; //Exp operation result,
wire FSM_load_second_step; //Exp operation Overflow, Sgf operation second reg
wire FSM_barrel_shifter_load;
wire FSM_adder_round_norm_load;
wire FSM_final_result_load;
//ZERO FLAG
//Op_MX;
//Op_MY
wire zero_flag;
//FIRST PHASE
wire [W-1:0] Op_MX;
wire [W-1:0] Op_MY;
//Mux S-> exp_operation OPER_A_i//////////
wire FSM_selector_A;
//D0=Op_MX[W-2:W-EW-1]
//D1=exp_oper_result
wire [EW:0] S_Oper_A_exp;
//Mux S-> exp_operation OPER_B_i//////////
wire [1:0] FSM_selector_B;
//D0=Op_MY[W-2:W-EW-1]
//D1=LZA_output
//D2=1
wire [EW-1:0] S_Oper_B_exp;
///////////exp_operation///////////////////////////
wire FSM_exp_operation_A_S;
//oper_A= S_Oper_A_exp
//oper_B= S_Oper_B_exp
wire [EW:0] exp_oper_result;
//Sgf operation//////////////////
//Op_A={1'b1, Op_MX[SW-1:0]}
//Op_B={1'b1, Op_MY[SW-1:0]}
wire [2*SW+1:0] P_Sgf;
wire[SW:0] significand;
wire[SW:0] non_significand;
//Sign Operation
wire sign_final_result;
//barrel shifter multiplexers
wire [SW:0] S_Data_Shift;
//barrel shifter
wire [SW:0] Sgf_normalized_result;
//adder rounding
wire FSM_add_overflow_flag;
//Oper_A_i=norm result
//Oper_B_i=1
wire [SW:0] Add_result;
//round decoder
wire FSM_round_flag;
//Selecto moltiplexers
wire selector_A;
wire [1:0] selector_B;
wire load_b;
wire selector_C;
//Barrel shifter multiplexer
/////////////////////////////////////////FSM////////////////////////////////////////////
FSM_Mult_Function FS_Module (
.clk(clk), //**
.rst(rst), //**
.beg_FSM(beg_FSM), //**
.ack_FSM(ack_FSM), //**
.zero_flag_i(zero_flag),
.Mult_shift_i(P_Sgf[2*SW+1]),
.round_flag_i(FSM_round_flag),
.Add_Overflow_i(FSM_add_overflow_flag),
.load_0_o(FSM_first_phase_load),
.load_1_o(FSM_load_first_step),
.load_2_o(FSM_exp_operation_load_result),
.load_3_o(FSM_load_second_step),
.load_4_o(FSM_adder_round_norm_load),
.load_5_o(FSM_final_result_load),
.load_6_o(FSM_barrel_shifter_load),
.ctrl_select_a_o(selector_A),
.ctrl_select_b_o(load_b),
.selector_b_o(selector_B),
.ctrl_select_c_o(selector_C),
.exp_op_o(FSM_exp_operation_A_S),
.shift_value_o(FSM_Shift_Value),
.rst_int(rst_int), //
.ready(ready)
);
///////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////Selector's registers//////////////////////////////
RegisterAdd #(.W(1)) Sel_A ( //Selector_A register
.clk(clk),
.rst(rst_int),
.load(selector_A),
.D(1'b1),
.Q(FSM_selector_A)
);
RegisterAdd #(.W(1)) Sel_C ( //Selector_C register
.clk(clk),
.rst(rst_int),
.load(selector_C),
.D(1'b1),
.Q(FSM_selector_C)
);
RegisterAdd #(.W(2)) Sel_B ( //Selector_B register
.clk(clk),
.rst(rst_int),
.load(load_b),
.D(selector_B),
.Q(FSM_selector_B)
);
///////////////////////////////////////////////////////////////////////////////////////////
First_Phase_M #(.W(W)) Operands_load_reg ( //
.clk(clk), //**
.rst(rst_int), //**
.load(FSM_first_phase_load), //**
.Data_MX(Data_MX), //**
.Data_MY(Data_MY), //**
.Op_MX(Op_MX),
.Op_MY(Op_MY)
);
Zero_InfMult_Unit #(.W(W)) Zero_Result_Detect (
.clk(clk),
.rst(rst_int),
.load(FSM_load_first_step),
.Data_A(Op_MX [W-2:0]),
.Data_B(Op_MY [W-2:0]),
.zero_m_flag(zero_flag)
);
///////////Mux exp_operation OPER_A_i//////////
Multiplexer_AC #(.W(EW+1)) Exp_Oper_A_mux(
.ctrl(FSM_selector_A),
.D0 ({1'b0,Op_MX[W-2:W-EW-1]}),
.D1 (exp_oper_result),
.S (S_Oper_A_exp)
);
///////////Mux exp_operation OPER_B_i//////////
wire [EW-1:0] Exp_oper_B_D1, Exp_oper_B_D2;
Mux_3x1 #(.W(EW)) Exp_Oper_B_mux(
.ctrl(FSM_selector_B),
.D0 (Op_MY[W-2:W-EW-1]),
.D1 (Exp_oper_B_D1),
.D2 (Exp_oper_B_D2),
.S(S_Oper_B_exp)
);
generate
case(EW)
8:begin
assign Exp_oper_B_D1 = 8'd127;
assign Exp_oper_B_D2 = 8'd1;
end
default:begin
assign Exp_oper_B_D1 = 11'd1023;
assign Exp_oper_B_D2 = 11'd1;
end
endcase
endgenerate
///////////exp_operation///////////////////////////
Exp_Operation_m #(.EW(EW)) Exp_module (
.clk(clk),
.rst(rst_int),
.load_a_i(FSM_load_first_step),
.load_b_i(FSM_load_second_step),
.load_c_i(FSM_exp_operation_load_result),
.Data_A_i(S_Oper_A_exp),
.Data_B_i({1'b0,S_Oper_B_exp}),
.Add_Subt_i(FSM_exp_operation_A_S),
.Data_Result_o(exp_oper_result),
.Overflow_flag_o(overflow_flag),
.Underflow_flag_o(underflow_flag)
);
////////Sign_operation//////////////////////////////
XOR_M Sign_operation (
.Sgn_X(Op_MX[W-1]),
.Sgn_Y(Op_MY[W-1]),
.Sgn_Info(sign_final_result)
);
/////Significant_Operation//////////////////////////
Sgf_Multiplication #(.SW(SW+1)) Sgf_operation (
.clk(clk),
.rst(rst),
.load_b_i(FSM_load_second_step),
.Data_A_i({1'b1,Op_MX[SW-1:0]}),
.Data_B_i({1'b1,Op_MY[SW-1:0]}),
.sgf_result_o(P_Sgf)
);
//////////Mux Barrel shifter shift_Value/////////////////
assign significand = P_Sgf [2*SW:SW];
assign non_significand = P_Sgf [SW-1:0];
///////////Mux Barrel shifter Data_in//////
Multiplexer_AC #(.W(SW+1)) Barrel_Shifter_D_I_mux(
.ctrl(FSM_selector_C),
.D0 (significand),
.D1 (Add_result),
.S (S_Data_Shift)
);
///////////Barrel_Shifter//////////////////////////
Barrel_Shifter_M #(.SW(SW+1)) Barrel_Shifter_module (
.clk(clk),
.rst(rst_int),
.load_i(FSM_barrel_shifter_load),
.Shift_Value_i(FSM_Shift_Value),
.Shift_Data_i(S_Data_Shift),
.N_mant_o(Sgf_normalized_result)
);
////Round decoder/////////////////////////////////
Round_decoder_M #(.SW(SW)) Round_Decoder (
.Round_Bits_i(non_significand),
.Round_Mode_i(round_mode),
.Sign_Result_i(sign_final_result),
.Round_Flag_o(FSM_round_flag)
);
//rounding_adder
wire [SW:0] Add_Sgf_Oper_B;
assign Add_Sgf_Oper_B = (SW)*1'b1;
Adder_Round #(.SW(SW+1)) Adder_M (
.clk(clk),
.rst(rst_int),
.load_i(FSM_adder_round_norm_load),
.Data_A_i(Sgf_normalized_result),
.Data_B_i(Add_Sgf_Oper_B),
.Data_Result_o(Add_result),
.FSM_C_o(FSM_add_overflow_flag)
);
////Final Result///////////////////////////////
Tenth_Phase #(.W(W),.EW(EW),.SW(SW)) final_result_ieee_Module(
.clk(clk),
.rst(rst_int),
.load_i(FSM_final_result_load),
.sel_a_i(overflow_flag),
.sel_b_i(underflow_flag),
.sign_i(sign_final_result),
.exp_ieee_i(exp_oper_result[EW-1:0]),
.sgf_ieee_i(Sgf_normalized_result[SW-1:0]),
.final_result_ieee_o(final_result_ieee)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / _description_
// /___/ /\ Filename : GTYE3_CHANNEL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTYE3_CHANNEL #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0,
parameter [0:0] ACJTAG_MODE = 1'b0,
parameter [0:0] ACJTAG_RESET = 1'b0,
parameter [15:0] ADAPT_CFG0 = 16'h9200,
parameter [15:0] ADAPT_CFG1 = 16'h801C,
parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000,
parameter ALIGN_COMMA_DOUBLE = "FALSE",
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111,
parameter integer ALIGN_COMMA_WORD = 1,
parameter ALIGN_MCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011,
parameter ALIGN_PCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100,
parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0,
parameter [0:0] A_RXOSCALRESET = 1'b0,
parameter [0:0] A_RXPROGDIVRESET = 1'b0,
parameter [4:0] A_TXDIFFCTRL = 5'b01100,
parameter [0:0] A_TXPROGDIVRESET = 1'b0,
parameter [0:0] CAPBYPASS_FORCE = 1'b0,
parameter CBCC_DATA_SOURCE_SEL = "DECODED",
parameter [0:0] CDR_SWAP_MODE_EN = 1'b0,
parameter CHAN_BOND_KEEP_ALIGN = "FALSE",
parameter integer CHAN_BOND_MAX_SKEW = 7,
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100,
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111,
parameter CHAN_BOND_SEQ_2_USE = "FALSE",
parameter integer CHAN_BOND_SEQ_LEN = 2,
parameter [15:0] CH_HSPMUX = 16'h0000,
parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000,
parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000,
parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000,
parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000,
parameter [15:0] CKCAL_RSVD0 = 16'h0000,
parameter [15:0] CKCAL_RSVD1 = 16'h0000,
parameter CLK_CORRECT_USE = "TRUE",
parameter CLK_COR_KEEP_IDLE = "FALSE",
parameter integer CLK_COR_MAX_LAT = 20,
parameter integer CLK_COR_MIN_LAT = 18,
parameter CLK_COR_PRECEDENCE = "TRUE",
parameter integer CLK_COR_REPEAT_WAIT = 0,
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100,
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111,
parameter CLK_COR_SEQ_2_USE = "FALSE",
parameter integer CLK_COR_SEQ_LEN = 2,
parameter [15:0] CPLL_CFG0 = 16'h20F8,
parameter [15:0] CPLL_CFG1 = 16'hA494,
parameter [15:0] CPLL_CFG2 = 16'hF001,
parameter [5:0] CPLL_CFG3 = 6'h00,
parameter integer CPLL_FBDIV = 4,
parameter integer CPLL_FBDIV_45 = 4,
parameter [15:0] CPLL_INIT_CFG0 = 16'h001E,
parameter [7:0] CPLL_INIT_CFG1 = 8'h00,
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8,
parameter integer CPLL_REFCLK_DIV = 1,
parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000,
parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0,
parameter [1:0] DDI_CTRL = 2'b00,
parameter integer DDI_REALIGN_WAIT = 15,
parameter DEC_MCOMMA_DETECT = "TRUE",
parameter DEC_PCOMMA_DETECT = "TRUE",
parameter DEC_VALID_COMMA_ONLY = "TRUE",
parameter [0:0] DFE_D_X_REL_POS = 1'b0,
parameter [0:0] DFE_VCM_COMP_EN = 1'b0,
parameter [9:0] DMONITOR_CFG0 = 10'h000,
parameter [7:0] DMONITOR_CFG1 = 8'h00,
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0,
parameter [5:0] ES_CONTROL = 6'b000000,
parameter ES_ERRDET_EN = "FALSE",
parameter ES_EYE_SCAN_EN = "FALSE",
parameter [11:0] ES_HORZ_OFFSET = 12'h000,
parameter [9:0] ES_PMA_CFG = 10'b0000000000,
parameter [4:0] ES_PRESCALE = 5'b00000,
parameter [15:0] ES_QUALIFIER0 = 16'h0000,
parameter [15:0] ES_QUALIFIER1 = 16'h0000,
parameter [15:0] ES_QUALIFIER2 = 16'h0000,
parameter [15:0] ES_QUALIFIER3 = 16'h0000,
parameter [15:0] ES_QUALIFIER4 = 16'h0000,
parameter [15:0] ES_QUALIFIER5 = 16'h0000,
parameter [15:0] ES_QUALIFIER6 = 16'h0000,
parameter [15:0] ES_QUALIFIER7 = 16'h0000,
parameter [15:0] ES_QUALIFIER8 = 16'h0000,
parameter [15:0] ES_QUALIFIER9 = 16'h0000,
parameter [15:0] ES_QUAL_MASK0 = 16'h0000,
parameter [15:0] ES_QUAL_MASK1 = 16'h0000,
parameter [15:0] ES_QUAL_MASK2 = 16'h0000,
parameter [15:0] ES_QUAL_MASK3 = 16'h0000,
parameter [15:0] ES_QUAL_MASK4 = 16'h0000,
parameter [15:0] ES_QUAL_MASK5 = 16'h0000,
parameter [15:0] ES_QUAL_MASK6 = 16'h0000,
parameter [15:0] ES_QUAL_MASK7 = 16'h0000,
parameter [15:0] ES_QUAL_MASK8 = 16'h0000,
parameter [15:0] ES_QUAL_MASK9 = 16'h0000,
parameter [15:0] ES_SDATA_MASK0 = 16'h0000,
parameter [15:0] ES_SDATA_MASK1 = 16'h0000,
parameter [15:0] ES_SDATA_MASK2 = 16'h0000,
parameter [15:0] ES_SDATA_MASK3 = 16'h0000,
parameter [15:0] ES_SDATA_MASK4 = 16'h0000,
parameter [15:0] ES_SDATA_MASK5 = 16'h0000,
parameter [15:0] ES_SDATA_MASK6 = 16'h0000,
parameter [15:0] ES_SDATA_MASK7 = 16'h0000,
parameter [15:0] ES_SDATA_MASK8 = 16'h0000,
parameter [15:0] ES_SDATA_MASK9 = 16'h0000,
parameter [10:0] EVODD_PHI_CFG = 11'b00000000000,
parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0,
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111,
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111,
parameter FTS_LANE_DESKEW_EN = "FALSE",
parameter [4:0] GEARBOX_MODE = 5'b00000,
parameter [0:0] GM_BIAS_SELECT = 1'b0,
parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0,
parameter [0:0] LOCAL_MASTER = 1'b0,
parameter [15:0] LOOP0_CFG = 16'h0000,
parameter [15:0] LOOP10_CFG = 16'h0000,
parameter [15:0] LOOP11_CFG = 16'h0000,
parameter [15:0] LOOP12_CFG = 16'h0000,
parameter [15:0] LOOP13_CFG = 16'h0000,
parameter [15:0] LOOP1_CFG = 16'h0000,
parameter [15:0] LOOP2_CFG = 16'h0000,
parameter [15:0] LOOP3_CFG = 16'h0000,
parameter [15:0] LOOP4_CFG = 16'h0000,
parameter [15:0] LOOP5_CFG = 16'h0000,
parameter [15:0] LOOP6_CFG = 16'h0000,
parameter [15:0] LOOP7_CFG = 16'h0000,
parameter [15:0] LOOP8_CFG = 16'h0000,
parameter [15:0] LOOP9_CFG = 16'h0000,
parameter [2:0] LPBK_BIAS_CTRL = 3'b000,
parameter [0:0] LPBK_EN_RCAL_B = 1'b0,
parameter [3:0] LPBK_EXT_RCAL = 4'b0000,
parameter [3:0] LPBK_RG_CTRL = 4'b0000,
parameter [1:0] OOBDIVCTL = 2'b00,
parameter [0:0] OOB_PWRUP = 1'b0,
parameter PCI3_AUTO_REALIGN = "FRST_SMPL",
parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1,
parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00,
parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0,
parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000,
parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000,
parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000,
parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0,
parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0,
parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000,
parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_RXPMA_CFG = 16'h0000,
parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_TXPMA_CFG = 16'h0000,
parameter PCS_PCIE_EN = "FALSE",
parameter [15:0] PCS_RSVD0 = 16'b0000000000000000,
parameter [2:0] PCS_RSVD1 = 3'b000,
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C,
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19,
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64,
parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0,
parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0,
parameter [15:0] PMA_RSV0 = 16'h0000,
parameter [15:0] PMA_RSV1 = 16'h0000,
parameter integer PREIQ_FREQ_BST = 0,
parameter [2:0] PROCESS_PAR = 3'b010,
parameter [0:0] RATE_SW_USE_DRP = 1'b0,
parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0,
parameter [4:0] RXBUFRESET_TIME = 5'b00001,
parameter RXBUF_ADDR_MODE = "FULL",
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000,
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000,
parameter RXBUF_EN = "TRUE",
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE",
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE",
parameter RXBUF_RESET_ON_EIDLE = "FALSE",
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE",
parameter integer RXBUF_THRESH_OVFLW = 0,
parameter RXBUF_THRESH_OVRD = "FALSE",
parameter integer RXBUF_THRESH_UNDFLW = 4,
parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001,
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001,
parameter [15:0] RXCDR_CFG0 = 16'h0000,
parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG1 = 16'h0300,
parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0300,
parameter [15:0] RXCDR_CFG2 = 16'h0060,
parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0060,
parameter [15:0] RXCDR_CFG3 = 16'h0000,
parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG4 = 16'h0002,
parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0002,
parameter [15:0] RXCDR_CFG5 = 16'h0000,
parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000,
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0,
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0,
parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0001,
parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000,
parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000,
parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000,
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0,
parameter [1:0] RXCFOKDONE_SRC = 2'b00,
parameter [15:0] RXCFOK_CFG0 = 16'h3E00,
parameter [15:0] RXCFOK_CFG1 = 16'h0042,
parameter [15:0] RXCFOK_CFG2 = 16'h002D,
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111,
parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000,
parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022,
parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100,
parameter [15:0] RXDFE_CFG0 = 16'h4C00,
parameter [15:0] RXDFE_CFG1 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG0 = 16'h1E00,
parameter [15:0] RXDFE_GC_CFG1 = 16'h1900,
parameter [15:0] RXDFE_GC_CFG2 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H3_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H3_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H4_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H4_CFG1 = 16'h0003,
parameter [15:0] RXDFE_H5_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H5_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H6_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H6_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H7_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H7_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H8_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H8_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H9_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H9_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HA_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HA_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HB_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HB_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HC_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HD_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HD_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HE_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HE_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HF_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HF_CFG1 = 16'h0002,
parameter [15:0] RXDFE_OS_CFG0 = 16'h0000,
parameter [15:0] RXDFE_OS_CFG1 = 16'h0200,
parameter [0:0] RXDFE_PWR_SAVING = 1'b0,
parameter [15:0] RXDFE_UT_CFG0 = 16'h0000,
parameter [15:0] RXDFE_UT_CFG1 = 16'h0002,
parameter [15:0] RXDFE_VP_CFG0 = 16'h0000,
parameter [15:0] RXDFE_VP_CFG1 = 16'h0022,
parameter [15:0] RXDLY_CFG = 16'h001F,
parameter [15:0] RXDLY_LCFG = 16'h0030,
parameter RXELECIDLE_CFG = "SIGCFG_4",
parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter RXGEARBOX_EN = "FALSE",
parameter [4:0] RXISCANRESET_TIME = 5'b00001,
parameter [15:0] RXLPM_CFG = 16'h0000,
parameter [15:0] RXLPM_GC_CFG = 16'h0200,
parameter [15:0] RXLPM_KH_CFG0 = 16'h0000,
parameter [15:0] RXLPM_KH_CFG1 = 16'h0002,
parameter [15:0] RXLPM_OS_CFG0 = 16'h0400,
parameter [15:0] RXLPM_OS_CFG1 = 16'h0000,
parameter [8:0] RXOOB_CFG = 9'b000000110,
parameter RXOOB_CLK_CFG = "PMA",
parameter [4:0] RXOSCALRESET_TIME = 5'b00011,
parameter integer RXOUT_DIV = 4,
parameter [4:0] RXPCSRESET_TIME = 5'b00001,
parameter [15:0] RXPHBEACON_CFG = 16'h0000,
parameter [15:0] RXPHDLY_CFG = 16'h2020,
parameter [15:0] RXPHSAMP_CFG = 16'h2100,
parameter [15:0] RXPHSLIP_CFG = 16'h9933,
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000,
parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0,
parameter [15:0] RXPI_CFG = 16'h0100,
parameter [0:0] RXPI_LPM = 1'b0,
parameter [15:0] RXPI_RSV0 = 16'h0000,
parameter [1:0] RXPI_SEL_LC = 2'b00,
parameter [1:0] RXPI_STARTCODE = 2'b00,
parameter [0:0] RXPI_VREFSEL = 1'b0,
parameter RXPMACLK_SEL = "DATA",
parameter [4:0] RXPMARESET_TIME = 5'b00001,
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0,
parameter integer RXPRBS_LINKACQ_CNT = 15,
parameter integer RXSLIDE_AUTO_WAIT = 7,
parameter RXSLIDE_MODE = "OFF",
parameter [0:0] RXSYNC_MULTILANE = 1'b0,
parameter [0:0] RXSYNC_OVRD = 1'b0,
parameter [0:0] RXSYNC_SKIP_DA = 1'b0,
parameter [0:0] RX_AFE_CM_EN = 1'b0,
parameter [15:0] RX_BIAS_CFG0 = 16'h1534,
parameter [5:0] RX_BUFFER_CFG = 6'b000000,
parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0,
parameter integer RX_CLK25_DIV = 8,
parameter [0:0] RX_CLKMUX_EN = 1'b1,
parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000,
parameter [3:0] RX_CM_BUF_CFG = 4'b1010,
parameter [0:0] RX_CM_BUF_PD = 1'b0,
parameter integer RX_CM_SEL = 3,
parameter integer RX_CM_TRIM = 10,
parameter [0:0] RX_CTLE1_KHKL = 1'b0,
parameter [0:0] RX_CTLE2_KHKL = 1'b0,
parameter [0:0] RX_CTLE3_AGC = 1'b0,
parameter integer RX_DATA_WIDTH = 20,
parameter [5:0] RX_DDI_SEL = 6'b000000,
parameter RX_DEFER_RESET_BUF_EN = "TRUE",
parameter [2:0] RX_DEGEN_CTRL = 3'b010,
parameter integer RX_DFELPM_CFG0 = 6,
parameter [0:0] RX_DFELPM_CFG1 = 1'b0,
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1,
parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00,
parameter integer RX_DFE_AGC_CFG1 = 4,
parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1,
parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2,
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01,
parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010,
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0,
parameter RX_DISPERR_SEQ_MATCH = "TRUE",
parameter [0:0] RX_DIV2_MODE_B = 1'b0,
parameter [4:0] RX_DIVRESET_TIME = 5'b00001,
parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0,
parameter [0:0] RX_EN_HI_LR = 1'b0,
parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000,
parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000,
parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0,
parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00,
parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0,
parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0,
parameter integer RX_INT_DATAWIDTH = 1,
parameter [0:0] RX_PMA_POWER_SAVE = 1'b0,
parameter real RX_PROGDIV_CFG = 0.0,
parameter [15:0] RX_PROGDIV_RATE = 16'h0001,
parameter [3:0] RX_RESLOAD_CTRL = 4'b0000,
parameter [0:0] RX_RESLOAD_OVRD = 1'b0,
parameter [2:0] RX_SAMPLE_PERIOD = 3'b101,
parameter integer RX_SIG_VALID_DLY = 11,
parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0,
parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000,
parameter [3:0] RX_SUM_VCMTUNE = 4'b1000,
parameter [0:0] RX_SUM_VCM_OVWR = 1'b0,
parameter [2:0] RX_SUM_VREF_TUNE = 3'b100,
parameter [1:0] RX_TUNE_AFE_OS = 2'b00,
parameter [2:0] RX_VREG_CTRL = 3'b101,
parameter [0:0] RX_VREG_PDB = 1'b1,
parameter [1:0] RX_WIDEMODE_CDR = 2'b01,
parameter RX_XCLK_SEL = "RXDES",
parameter [0:0] RX_XMODE_SEL = 1'b0,
parameter integer SAS_MAX_COM = 64,
parameter integer SAS_MIN_COM = 36,
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111,
parameter [2:0] SATA_BURST_VAL = 3'b100,
parameter SATA_CPLL_CFG = "VCO_3000MHZ",
parameter [2:0] SATA_EIDLE_VAL = 3'b100,
parameter integer SATA_MAX_BURST = 8,
parameter integer SATA_MAX_INIT = 21,
parameter integer SATA_MAX_WAKE = 7,
parameter integer SATA_MIN_BURST = 4,
parameter integer SATA_MIN_INIT = 12,
parameter integer SATA_MIN_WAKE = 4,
parameter SHOW_REALIGN_COMMA = "TRUE",
parameter SIM_RECEIVER_DETECT_PASS = "TRUE",
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0,
parameter real SIM_VERSION = 1.0,
parameter [1:0] TAPDLY_SET_TX = 2'h0,
parameter [3:0] TEMPERATURE_PAR = 4'b0010,
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000,
parameter [2:0] TERM_RCAL_OVRD = 3'b000,
parameter [7:0] TRANS_TIME_RATE = 8'h0E,
parameter [7:0] TST_RSV0 = 8'h00,
parameter [7:0] TST_RSV1 = 8'h00,
parameter TXBUF_EN = "TRUE",
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE",
parameter [15:0] TXDLY_CFG = 16'h001F,
parameter [15:0] TXDLY_LCFG = 16'h0030,
parameter TXFIFO_ADDR_CFG = "LOW",
parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter TXGEARBOX_EN = "FALSE",
parameter integer TXOUT_DIV = 4,
parameter [4:0] TXPCSRESET_TIME = 5'b00001,
parameter [15:0] TXPHDLY_CFG0 = 16'h2020,
parameter [15:0] TXPHDLY_CFG1 = 16'h0001,
parameter [15:0] TXPH_CFG = 16'h0123,
parameter [15:0] TXPH_CFG2 = 16'h0000,
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000,
parameter [1:0] TXPI_CFG0 = 2'b00,
parameter [1:0] TXPI_CFG1 = 2'b00,
parameter [1:0] TXPI_CFG2 = 2'b00,
parameter [0:0] TXPI_CFG3 = 1'b0,
parameter [0:0] TXPI_CFG4 = 1'b1,
parameter [2:0] TXPI_CFG5 = 3'b000,
parameter [0:0] TXPI_GRAY_SEL = 1'b0,
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0,
parameter [0:0] TXPI_LPM = 1'b0,
parameter TXPI_PPMCLK_SEL = "TXUSRCLK2",
parameter [7:0] TXPI_PPM_CFG = 8'b00000000,
parameter [15:0] TXPI_RSV0 = 16'h0000,
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000,
parameter [0:0] TXPI_VREFSEL = 1'b0,
parameter [4:0] TXPMARESET_TIME = 5'b00001,
parameter [0:0] TXSYNC_MULTILANE = 1'b0,
parameter [0:0] TXSYNC_OVRD = 1'b0,
parameter [0:0] TXSYNC_SKIP_DA = 1'b0,
parameter integer TX_CLK25_DIV = 8,
parameter [0:0] TX_CLKMUX_EN = 1'b1,
parameter [0:0] TX_CLKREG_PDB = 1'b0,
parameter [2:0] TX_CLKREG_SET = 3'b000,
parameter integer TX_DATA_WIDTH = 20,
parameter [5:0] TX_DCD_CFG = 6'b000010,
parameter [0:0] TX_DCD_EN = 1'b0,
parameter [5:0] TX_DEEMPH0 = 6'b000000,
parameter [5:0] TX_DEEMPH1 = 6'b000000,
parameter [4:0] TX_DIVRESET_TIME = 5'b00001,
parameter TX_DRIVE_MODE = "DIRECT",
parameter integer TX_DRVMUX_CTRL = 2,
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110,
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100,
parameter [0:0] TX_EML_PHI_TUNE = 1'b0,
parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0,
parameter [0:0] TX_FIFO_BYP_EN = 1'b0,
parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0,
parameter integer TX_INT_DATAWIDTH = 1,
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE",
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0,
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110,
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001,
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101,
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010,
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110,
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100,
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010,
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000,
parameter [2:0] TX_MODE_SEL = 3'b000,
parameter [15:0] TX_PHICAL_CFG0 = 16'h0000,
parameter [15:0] TX_PHICAL_CFG1 = 16'h7E00,
parameter [15:0] TX_PHICAL_CFG2 = 16'h0000,
parameter integer TX_PI_BIASSET = 0,
parameter [15:0] TX_PI_CFG0 = 16'h0000,
parameter [15:0] TX_PI_CFG1 = 16'h0000,
parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0,
parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0,
parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0,
parameter [0:0] TX_PMADATA_OPT = 1'b0,
parameter [0:0] TX_PMA_POWER_SAVE = 1'b0,
parameter integer TX_PREDRV_CTRL = 2,
parameter TX_PROGCLK_SEL = "POSTPI",
parameter real TX_PROGDIV_CFG = 0.0,
parameter [15:0] TX_PROGDIV_RATE = 16'h0001,
parameter [13:0] TX_RXDETECT_CFG = 14'h0032,
parameter integer TX_RXDETECT_REF = 4,
parameter [2:0] TX_SAMPLE_PERIOD = 3'b101,
parameter [0:0] TX_SARC_LPBK_ENB = 1'b0,
parameter TX_XCLK_SEL = "TXOUT",
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0
)(
output [2:0] BUFGTCE,
output [2:0] BUFGTCEMASK,
output [8:0] BUFGTDIV,
output [2:0] BUFGTRESET,
output [2:0] BUFGTRSTMASK,
output CPLLFBCLKLOST,
output CPLLLOCK,
output CPLLREFCLKLOST,
output [16:0] DMONITOROUT,
output [15:0] DRPDO,
output DRPRDY,
output EYESCANDATAERROR,
output GTPOWERGOOD,
output GTREFCLKMONITOR,
output GTYTXN,
output GTYTXP,
output PCIERATEGEN3,
output PCIERATEIDLE,
output [1:0] PCIERATEQPLLPD,
output [1:0] PCIERATEQPLLRESET,
output PCIESYNCTXSYNCDONE,
output PCIEUSERGEN3RDY,
output PCIEUSERPHYSTATUSRST,
output PCIEUSERRATESTART,
output [15:0] PCSRSVDOUT,
output PHYSTATUS,
output [7:0] PINRSRVDAS,
output RESETEXCEPTION,
output [2:0] RXBUFSTATUS,
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCDRLOCK,
output RXCDRPHDONE,
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
output [4:0] RXCHBONDO,
output RXCKCALDONE,
output [1:0] RXCLKCORCNT,
output RXCOMINITDET,
output RXCOMMADET,
output RXCOMSASDET,
output RXCOMWAKEDET,
output [15:0] RXCTRL0,
output [15:0] RXCTRL1,
output [7:0] RXCTRL2,
output [7:0] RXCTRL3,
output [127:0] RXDATA,
output [7:0] RXDATAEXTENDRSVD,
output [1:0] RXDATAVALID,
output RXDLYSRESETDONE,
output RXELECIDLE,
output [5:0] RXHEADER,
output [1:0] RXHEADERVALID,
output [6:0] RXMONITOROUT,
output RXOSINTDONE,
output RXOSINTSTARTED,
output RXOSINTSTROBEDONE,
output RXOSINTSTROBESTARTED,
output RXOUTCLK,
output RXOUTCLKFABRIC,
output RXOUTCLKPCS,
output RXPHALIGNDONE,
output RXPHALIGNERR,
output RXPMARESETDONE,
output RXPRBSERR,
output RXPRBSLOCKED,
output RXPRGDIVRESETDONE,
output RXRATEDONE,
output RXRECCLKOUT,
output RXRESETDONE,
output RXSLIDERDY,
output RXSLIPDONE,
output RXSLIPOUTCLKRDY,
output RXSLIPPMARDY,
output [1:0] RXSTARTOFSEQ,
output [2:0] RXSTATUS,
output RXSYNCDONE,
output RXSYNCOUT,
output RXVALID,
output [1:0] TXBUFSTATUS,
output TXCOMFINISH,
output TXDCCDONE,
output TXDLYSRESETDONE,
output TXOUTCLK,
output TXOUTCLKFABRIC,
output TXOUTCLKPCS,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXPMARESETDONE,
output TXPRGDIVRESETDONE,
output TXRATEDONE,
output TXRESETDONE,
output TXSYNCDONE,
output TXSYNCOUT,
input CDRSTEPDIR,
input CDRSTEPSQ,
input CDRSTEPSX,
input CFGRESET,
input CLKRSVD0,
input CLKRSVD1,
input CPLLLOCKDETCLK,
input CPLLLOCKEN,
input CPLLPD,
input [2:0] CPLLREFCLKSEL,
input CPLLRESET,
input DMONFIFORESET,
input DMONITORCLK,
input [9:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input DRPEN,
input DRPWE,
input ELPCALDVORWREN,
input ELPCALPAORWREN,
input EVODDPHICALDONE,
input EVODDPHICALSTART,
input EVODDPHIDRDEN,
input EVODDPHIDWREN,
input EVODDPHIXRDEN,
input EVODDPHIXWREN,
input EYESCANMODE,
input EYESCANRESET,
input EYESCANTRIGGER,
input GTGREFCLK,
input GTNORTHREFCLK0,
input GTNORTHREFCLK1,
input GTREFCLK0,
input GTREFCLK1,
input GTRESETSEL,
input [15:0] GTRSVD,
input GTRXRESET,
input GTSOUTHREFCLK0,
input GTSOUTHREFCLK1,
input GTTXRESET,
input GTYRXN,
input GTYRXP,
input [2:0] LOOPBACK,
input [15:0] LOOPRSVD,
input LPBKRXTXSEREN,
input LPBKTXRXSEREN,
input PCIEEQRXEQADAPTDONE,
input PCIERSTIDLE,
input PCIERSTTXSYNCSTART,
input PCIEUSERRATEDONE,
input [15:0] PCSRSVDIN,
input [4:0] PCSRSVDIN2,
input [4:0] PMARSVDIN,
input QPLL0CLK,
input QPLL0REFCLK,
input QPLL1CLK,
input QPLL1REFCLK,
input RESETOVRD,
input RSTCLKENTX,
input RX8B10BEN,
input RXBUFRESET,
input RXCDRFREQRESET,
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESET,
input RXCDRRESETRSV,
input RXCHBONDEN,
input [4:0] RXCHBONDI,
input [2:0] RXCHBONDLEVEL,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCKCALRESET,
input RXCOMMADETEN,
input RXDCCFORCESTART,
input RXDFEAGCHOLD,
input RXDFEAGCOVRDEN,
input RXDFELFHOLD,
input RXDFELFOVRDEN,
input RXDFELPMRESET,
input RXDFETAP10HOLD,
input RXDFETAP10OVRDEN,
input RXDFETAP11HOLD,
input RXDFETAP11OVRDEN,
input RXDFETAP12HOLD,
input RXDFETAP12OVRDEN,
input RXDFETAP13HOLD,
input RXDFETAP13OVRDEN,
input RXDFETAP14HOLD,
input RXDFETAP14OVRDEN,
input RXDFETAP15HOLD,
input RXDFETAP15OVRDEN,
input RXDFETAP2HOLD,
input RXDFETAP2OVRDEN,
input RXDFETAP3HOLD,
input RXDFETAP3OVRDEN,
input RXDFETAP4HOLD,
input RXDFETAP4OVRDEN,
input RXDFETAP5HOLD,
input RXDFETAP5OVRDEN,
input RXDFETAP6HOLD,
input RXDFETAP6OVRDEN,
input RXDFETAP7HOLD,
input RXDFETAP7OVRDEN,
input RXDFETAP8HOLD,
input RXDFETAP8OVRDEN,
input RXDFETAP9HOLD,
input RXDFETAP9OVRDEN,
input RXDFEUTHOLD,
input RXDFEUTOVRDEN,
input RXDFEVPHOLD,
input RXDFEVPOVRDEN,
input RXDFEVSEN,
input RXDFEXYDEN,
input RXDLYBYPASS,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDLYSRESET,
input [1:0] RXELECIDLEMODE,
input RXGEARBOXSLIP,
input RXLATCLK,
input RXLPMEN,
input RXLPMGCHOLD,
input RXLPMGCOVRDEN,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFKLOVRDEN,
input RXLPMOSHOLD,
input RXLPMOSOVRDEN,
input RXMCOMMAALIGNEN,
input [1:0] RXMONITORSEL,
input RXOOBRESET,
input RXOSCALRESET,
input RXOSHOLD,
input [3:0] RXOSINTCFG,
input RXOSINTEN,
input RXOSINTHOLD,
input RXOSINTOVRDEN,
input RXOSINTSTROBE,
input RXOSINTTESTOVRDEN,
input RXOSOVRDEN,
input [2:0] RXOUTCLKSEL,
input RXPCOMMAALIGNEN,
input RXPCSRESET,
input [1:0] RXPD,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHDLYPD,
input RXPHDLYRESET,
input RXPHOVRDEN,
input [1:0] RXPLLCLKSEL,
input RXPMARESET,
input RXPOLARITY,
input RXPRBSCNTRESET,
input [3:0] RXPRBSSEL,
input RXPROGDIVRESET,
input [2:0] RXRATE,
input RXRATEMODE,
input RXSLIDE,
input RXSLIPOUTCLK,
input RXSLIPPMA,
input RXSYNCALLIN,
input RXSYNCIN,
input RXSYNCMODE,
input [1:0] RXSYSCLKSEL,
input RXUSERRDY,
input RXUSRCLK,
input RXUSRCLK2,
input SIGVALIDCLK,
input [19:0] TSTIN,
input [7:0] TX8B10BBYPASS,
input TX8B10BEN,
input [2:0] TXBUFDIFFCTRL,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
input [15:0] TXCTRL0,
input [15:0] TXCTRL1,
input [7:0] TXCTRL2,
input [127:0] TXDATA,
input [7:0] TXDATAEXTENDRSVD,
input TXDCCFORCESTART,
input TXDCCRESET,
input TXDEEMPH,
input TXDETECTRX,
input [4:0] TXDIFFCTRL,
input TXDIFFPD,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYHOLD,
input TXDLYOVRDEN,
input TXDLYSRESET,
input TXDLYUPDOWN,
input TXELECIDLE,
input TXELFORCESTART,
input [5:0] TXHEADER,
input TXINHIBIT,
input TXLATCLK,
input [6:0] TXMAINCURSOR,
input [2:0] TXMARGIN,
input [2:0] TXOUTCLKSEL,
input TXPCSRESET,
input [1:0] TXPD,
input TXPDELECIDLEMODE,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHDLYPD,
input TXPHDLYRESET,
input TXPHDLYTSTCLK,
input TXPHINIT,
input TXPHOVRDEN,
input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMPD,
input TXPIPPMSEL,
input [4:0] TXPIPPMSTEPSIZE,
input TXPISOPD,
input [1:0] TXPLLCLKSEL,
input TXPMARESET,
input TXPOLARITY,
input [4:0] TXPOSTCURSOR,
input TXPRBSFORCEERR,
input [3:0] TXPRBSSEL,
input [4:0] TXPRECURSOR,
input TXPROGDIVRESET,
input [2:0] TXRATE,
input TXRATEMODE,
input [6:0] TXSEQUENCE,
input TXSWING,
input TXSYNCALLIN,
input TXSYNCIN,
input TXSYNCMODE,
input [1:0] TXSYSCLKSEL,
input TXUSERRDY,
input TXUSRCLK,
input TXUSRCLK2
);
// define constants
localparam MODULE_NAME = "GTYE3_CHANNEL";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
`ifndef XIL_DR
localparam [0:0] ACJTAG_DEBUG_MODE_REG = ACJTAG_DEBUG_MODE;
localparam [0:0] ACJTAG_MODE_REG = ACJTAG_MODE;
localparam [0:0] ACJTAG_RESET_REG = ACJTAG_RESET;
localparam [15:0] ADAPT_CFG0_REG = ADAPT_CFG0;
localparam [15:0] ADAPT_CFG1_REG = ADAPT_CFG1;
localparam [15:0] ADAPT_CFG2_REG = ADAPT_CFG2;
localparam [40:1] ALIGN_COMMA_DOUBLE_REG = ALIGN_COMMA_DOUBLE;
localparam [9:0] ALIGN_COMMA_ENABLE_REG = ALIGN_COMMA_ENABLE;
localparam [2:0] ALIGN_COMMA_WORD_REG = ALIGN_COMMA_WORD;
localparam [40:1] ALIGN_MCOMMA_DET_REG = ALIGN_MCOMMA_DET;
localparam [9:0] ALIGN_MCOMMA_VALUE_REG = ALIGN_MCOMMA_VALUE;
localparam [40:1] ALIGN_PCOMMA_DET_REG = ALIGN_PCOMMA_DET;
localparam [9:0] ALIGN_PCOMMA_VALUE_REG = ALIGN_PCOMMA_VALUE;
localparam [0:0] AUTO_BW_SEL_BYPASS_REG = AUTO_BW_SEL_BYPASS;
localparam [0:0] A_RXOSCALRESET_REG = A_RXOSCALRESET;
localparam [0:0] A_RXPROGDIVRESET_REG = A_RXPROGDIVRESET;
localparam [4:0] A_TXDIFFCTRL_REG = A_TXDIFFCTRL;
localparam [0:0] A_TXPROGDIVRESET_REG = A_TXPROGDIVRESET;
localparam [0:0] CAPBYPASS_FORCE_REG = CAPBYPASS_FORCE;
localparam [56:1] CBCC_DATA_SOURCE_SEL_REG = CBCC_DATA_SOURCE_SEL;
localparam [0:0] CDR_SWAP_MODE_EN_REG = CDR_SWAP_MODE_EN;
localparam [40:1] CHAN_BOND_KEEP_ALIGN_REG = CHAN_BOND_KEEP_ALIGN;
localparam [3:0] CHAN_BOND_MAX_SKEW_REG = CHAN_BOND_MAX_SKEW;
localparam [9:0] CHAN_BOND_SEQ_1_1_REG = CHAN_BOND_SEQ_1_1;
localparam [9:0] CHAN_BOND_SEQ_1_2_REG = CHAN_BOND_SEQ_1_2;
localparam [9:0] CHAN_BOND_SEQ_1_3_REG = CHAN_BOND_SEQ_1_3;
localparam [9:0] CHAN_BOND_SEQ_1_4_REG = CHAN_BOND_SEQ_1_4;
localparam [3:0] CHAN_BOND_SEQ_1_ENABLE_REG = CHAN_BOND_SEQ_1_ENABLE;
localparam [9:0] CHAN_BOND_SEQ_2_1_REG = CHAN_BOND_SEQ_2_1;
localparam [9:0] CHAN_BOND_SEQ_2_2_REG = CHAN_BOND_SEQ_2_2;
localparam [9:0] CHAN_BOND_SEQ_2_3_REG = CHAN_BOND_SEQ_2_3;
localparam [9:0] CHAN_BOND_SEQ_2_4_REG = CHAN_BOND_SEQ_2_4;
localparam [3:0] CHAN_BOND_SEQ_2_ENABLE_REG = CHAN_BOND_SEQ_2_ENABLE;
localparam [40:1] CHAN_BOND_SEQ_2_USE_REG = CHAN_BOND_SEQ_2_USE;
localparam [2:0] CHAN_BOND_SEQ_LEN_REG = CHAN_BOND_SEQ_LEN;
localparam [15:0] CH_HSPMUX_REG = CH_HSPMUX;
localparam [15:0] CKCAL1_CFG_0_REG = CKCAL1_CFG_0;
localparam [15:0] CKCAL1_CFG_1_REG = CKCAL1_CFG_1;
localparam [15:0] CKCAL1_CFG_2_REG = CKCAL1_CFG_2;
localparam [15:0] CKCAL1_CFG_3_REG = CKCAL1_CFG_3;
localparam [15:0] CKCAL2_CFG_0_REG = CKCAL2_CFG_0;
localparam [15:0] CKCAL2_CFG_1_REG = CKCAL2_CFG_1;
localparam [15:0] CKCAL2_CFG_2_REG = CKCAL2_CFG_2;
localparam [15:0] CKCAL2_CFG_3_REG = CKCAL2_CFG_3;
localparam [15:0] CKCAL2_CFG_4_REG = CKCAL2_CFG_4;
localparam [15:0] CKCAL_RSVD0_REG = CKCAL_RSVD0;
localparam [15:0] CKCAL_RSVD1_REG = CKCAL_RSVD1;
localparam [40:1] CLK_CORRECT_USE_REG = CLK_CORRECT_USE;
localparam [40:1] CLK_COR_KEEP_IDLE_REG = CLK_COR_KEEP_IDLE;
localparam [5:0] CLK_COR_MAX_LAT_REG = CLK_COR_MAX_LAT;
localparam [5:0] CLK_COR_MIN_LAT_REG = CLK_COR_MIN_LAT;
localparam [40:1] CLK_COR_PRECEDENCE_REG = CLK_COR_PRECEDENCE;
localparam [4:0] CLK_COR_REPEAT_WAIT_REG = CLK_COR_REPEAT_WAIT;
localparam [9:0] CLK_COR_SEQ_1_1_REG = CLK_COR_SEQ_1_1;
localparam [9:0] CLK_COR_SEQ_1_2_REG = CLK_COR_SEQ_1_2;
localparam [9:0] CLK_COR_SEQ_1_3_REG = CLK_COR_SEQ_1_3;
localparam [9:0] CLK_COR_SEQ_1_4_REG = CLK_COR_SEQ_1_4;
localparam [3:0] CLK_COR_SEQ_1_ENABLE_REG = CLK_COR_SEQ_1_ENABLE;
localparam [9:0] CLK_COR_SEQ_2_1_REG = CLK_COR_SEQ_2_1;
localparam [9:0] CLK_COR_SEQ_2_2_REG = CLK_COR_SEQ_2_2;
localparam [9:0] CLK_COR_SEQ_2_3_REG = CLK_COR_SEQ_2_3;
localparam [9:0] CLK_COR_SEQ_2_4_REG = CLK_COR_SEQ_2_4;
localparam [3:0] CLK_COR_SEQ_2_ENABLE_REG = CLK_COR_SEQ_2_ENABLE;
localparam [40:1] CLK_COR_SEQ_2_USE_REG = CLK_COR_SEQ_2_USE;
localparam [2:0] CLK_COR_SEQ_LEN_REG = CLK_COR_SEQ_LEN;
localparam [15:0] CPLL_CFG0_REG = CPLL_CFG0;
localparam [15:0] CPLL_CFG1_REG = CPLL_CFG1;
localparam [15:0] CPLL_CFG2_REG = CPLL_CFG2;
localparam [5:0] CPLL_CFG3_REG = CPLL_CFG3;
localparam [4:0] CPLL_FBDIV_REG = CPLL_FBDIV;
localparam [2:0] CPLL_FBDIV_45_REG = CPLL_FBDIV_45;
localparam [15:0] CPLL_INIT_CFG0_REG = CPLL_INIT_CFG0;
localparam [7:0] CPLL_INIT_CFG1_REG = CPLL_INIT_CFG1;
localparam [15:0] CPLL_LOCK_CFG_REG = CPLL_LOCK_CFG;
localparam [4:0] CPLL_REFCLK_DIV_REG = CPLL_REFCLK_DIV;
localparam [2:0] CTLE3_OCAP_EXT_CTRL_REG = CTLE3_OCAP_EXT_CTRL;
localparam [0:0] CTLE3_OCAP_EXT_EN_REG = CTLE3_OCAP_EXT_EN;
localparam [1:0] DDI_CTRL_REG = DDI_CTRL;
localparam [4:0] DDI_REALIGN_WAIT_REG = DDI_REALIGN_WAIT;
localparam [40:1] DEC_MCOMMA_DETECT_REG = DEC_MCOMMA_DETECT;
localparam [40:1] DEC_PCOMMA_DETECT_REG = DEC_PCOMMA_DETECT;
localparam [40:1] DEC_VALID_COMMA_ONLY_REG = DEC_VALID_COMMA_ONLY;
localparam [0:0] DFE_D_X_REL_POS_REG = DFE_D_X_REL_POS;
localparam [0:0] DFE_VCM_COMP_EN_REG = DFE_VCM_COMP_EN;
localparam [9:0] DMONITOR_CFG0_REG = DMONITOR_CFG0;
localparam [7:0] DMONITOR_CFG1_REG = DMONITOR_CFG1;
localparam [0:0] ES_CLK_PHASE_SEL_REG = ES_CLK_PHASE_SEL;
localparam [5:0] ES_CONTROL_REG = ES_CONTROL;
localparam [40:1] ES_ERRDET_EN_REG = ES_ERRDET_EN;
localparam [40:1] ES_EYE_SCAN_EN_REG = ES_EYE_SCAN_EN;
localparam [11:0] ES_HORZ_OFFSET_REG = ES_HORZ_OFFSET;
localparam [9:0] ES_PMA_CFG_REG = ES_PMA_CFG;
localparam [4:0] ES_PRESCALE_REG = ES_PRESCALE;
localparam [15:0] ES_QUALIFIER0_REG = ES_QUALIFIER0;
localparam [15:0] ES_QUALIFIER1_REG = ES_QUALIFIER1;
localparam [15:0] ES_QUALIFIER2_REG = ES_QUALIFIER2;
localparam [15:0] ES_QUALIFIER3_REG = ES_QUALIFIER3;
localparam [15:0] ES_QUALIFIER4_REG = ES_QUALIFIER4;
localparam [15:0] ES_QUALIFIER5_REG = ES_QUALIFIER5;
localparam [15:0] ES_QUALIFIER6_REG = ES_QUALIFIER6;
localparam [15:0] ES_QUALIFIER7_REG = ES_QUALIFIER7;
localparam [15:0] ES_QUALIFIER8_REG = ES_QUALIFIER8;
localparam [15:0] ES_QUALIFIER9_REG = ES_QUALIFIER9;
localparam [15:0] ES_QUAL_MASK0_REG = ES_QUAL_MASK0;
localparam [15:0] ES_QUAL_MASK1_REG = ES_QUAL_MASK1;
localparam [15:0] ES_QUAL_MASK2_REG = ES_QUAL_MASK2;
localparam [15:0] ES_QUAL_MASK3_REG = ES_QUAL_MASK3;
localparam [15:0] ES_QUAL_MASK4_REG = ES_QUAL_MASK4;
localparam [15:0] ES_QUAL_MASK5_REG = ES_QUAL_MASK5;
localparam [15:0] ES_QUAL_MASK6_REG = ES_QUAL_MASK6;
localparam [15:0] ES_QUAL_MASK7_REG = ES_QUAL_MASK7;
localparam [15:0] ES_QUAL_MASK8_REG = ES_QUAL_MASK8;
localparam [15:0] ES_QUAL_MASK9_REG = ES_QUAL_MASK9;
localparam [15:0] ES_SDATA_MASK0_REG = ES_SDATA_MASK0;
localparam [15:0] ES_SDATA_MASK1_REG = ES_SDATA_MASK1;
localparam [15:0] ES_SDATA_MASK2_REG = ES_SDATA_MASK2;
localparam [15:0] ES_SDATA_MASK3_REG = ES_SDATA_MASK3;
localparam [15:0] ES_SDATA_MASK4_REG = ES_SDATA_MASK4;
localparam [15:0] ES_SDATA_MASK5_REG = ES_SDATA_MASK5;
localparam [15:0] ES_SDATA_MASK6_REG = ES_SDATA_MASK6;
localparam [15:0] ES_SDATA_MASK7_REG = ES_SDATA_MASK7;
localparam [15:0] ES_SDATA_MASK8_REG = ES_SDATA_MASK8;
localparam [15:0] ES_SDATA_MASK9_REG = ES_SDATA_MASK9;
localparam [10:0] EVODD_PHI_CFG_REG = EVODD_PHI_CFG;
localparam [0:0] EYE_SCAN_SWAP_EN_REG = EYE_SCAN_SWAP_EN;
localparam [3:0] FTS_DESKEW_SEQ_ENABLE_REG = FTS_DESKEW_SEQ_ENABLE;
localparam [3:0] FTS_LANE_DESKEW_CFG_REG = FTS_LANE_DESKEW_CFG;
localparam [40:1] FTS_LANE_DESKEW_EN_REG = FTS_LANE_DESKEW_EN;
localparam [4:0] GEARBOX_MODE_REG = GEARBOX_MODE;
localparam [0:0] GM_BIAS_SELECT_REG = GM_BIAS_SELECT;
localparam [0:0] ISCAN_CK_PH_SEL2_REG = ISCAN_CK_PH_SEL2;
localparam [0:0] LOCAL_MASTER_REG = LOCAL_MASTER;
localparam [15:0] LOOP0_CFG_REG = LOOP0_CFG;
localparam [15:0] LOOP10_CFG_REG = LOOP10_CFG;
localparam [15:0] LOOP11_CFG_REG = LOOP11_CFG;
localparam [15:0] LOOP12_CFG_REG = LOOP12_CFG;
localparam [15:0] LOOP13_CFG_REG = LOOP13_CFG;
localparam [15:0] LOOP1_CFG_REG = LOOP1_CFG;
localparam [15:0] LOOP2_CFG_REG = LOOP2_CFG;
localparam [15:0] LOOP3_CFG_REG = LOOP3_CFG;
localparam [15:0] LOOP4_CFG_REG = LOOP4_CFG;
localparam [15:0] LOOP5_CFG_REG = LOOP5_CFG;
localparam [15:0] LOOP6_CFG_REG = LOOP6_CFG;
localparam [15:0] LOOP7_CFG_REG = LOOP7_CFG;
localparam [15:0] LOOP8_CFG_REG = LOOP8_CFG;
localparam [15:0] LOOP9_CFG_REG = LOOP9_CFG;
localparam [2:0] LPBK_BIAS_CTRL_REG = LPBK_BIAS_CTRL;
localparam [0:0] LPBK_EN_RCAL_B_REG = LPBK_EN_RCAL_B;
localparam [3:0] LPBK_EXT_RCAL_REG = LPBK_EXT_RCAL;
localparam [3:0] LPBK_RG_CTRL_REG = LPBK_RG_CTRL;
localparam [1:0] OOBDIVCTL_REG = OOBDIVCTL;
localparam [0:0] OOB_PWRUP_REG = OOB_PWRUP;
localparam [80:1] PCI3_AUTO_REALIGN_REG = PCI3_AUTO_REALIGN;
localparam [0:0] PCI3_PIPE_RX_ELECIDLE_REG = PCI3_PIPE_RX_ELECIDLE;
localparam [1:0] PCI3_RX_ASYNC_EBUF_BYPASS_REG = PCI3_RX_ASYNC_EBUF_BYPASS;
localparam [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE_REG = PCI3_RX_ELECIDLE_EI2_ENABLE;
localparam [5:0] PCI3_RX_ELECIDLE_H2L_COUNT_REG = PCI3_RX_ELECIDLE_H2L_COUNT;
localparam [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE_REG = PCI3_RX_ELECIDLE_H2L_DISABLE;
localparam [5:0] PCI3_RX_ELECIDLE_HI_COUNT_REG = PCI3_RX_ELECIDLE_HI_COUNT;
localparam [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE_REG = PCI3_RX_ELECIDLE_LP4_DISABLE;
localparam [0:0] PCI3_RX_FIFO_DISABLE_REG = PCI3_RX_FIFO_DISABLE;
localparam [15:0] PCIE_BUFG_DIV_CTRL_REG = PCIE_BUFG_DIV_CTRL;
localparam [15:0] PCIE_RXPCS_CFG_GEN3_REG = PCIE_RXPCS_CFG_GEN3;
localparam [15:0] PCIE_RXPMA_CFG_REG = PCIE_RXPMA_CFG;
localparam [15:0] PCIE_TXPCS_CFG_GEN3_REG = PCIE_TXPCS_CFG_GEN3;
localparam [15:0] PCIE_TXPMA_CFG_REG = PCIE_TXPMA_CFG;
localparam [40:1] PCS_PCIE_EN_REG = PCS_PCIE_EN;
localparam [15:0] PCS_RSVD0_REG = PCS_RSVD0;
localparam [2:0] PCS_RSVD1_REG = PCS_RSVD1;
localparam [11:0] PD_TRANS_TIME_FROM_P2_REG = PD_TRANS_TIME_FROM_P2;
localparam [7:0] PD_TRANS_TIME_NONE_P2_REG = PD_TRANS_TIME_NONE_P2;
localparam [7:0] PD_TRANS_TIME_TO_P2_REG = PD_TRANS_TIME_TO_P2;
localparam [1:0] PLL_SEL_MODE_GEN12_REG = PLL_SEL_MODE_GEN12;
localparam [1:0] PLL_SEL_MODE_GEN3_REG = PLL_SEL_MODE_GEN3;
localparam [15:0] PMA_RSV0_REG = PMA_RSV0;
localparam [15:0] PMA_RSV1_REG = PMA_RSV1;
localparam [1:0] PREIQ_FREQ_BST_REG = PREIQ_FREQ_BST;
localparam [2:0] PROCESS_PAR_REG = PROCESS_PAR;
localparam [0:0] RATE_SW_USE_DRP_REG = RATE_SW_USE_DRP;
localparam [0:0] RESET_POWERSAVE_DISABLE_REG = RESET_POWERSAVE_DISABLE;
localparam [4:0] RXBUFRESET_TIME_REG = RXBUFRESET_TIME;
localparam [32:1] RXBUF_ADDR_MODE_REG = RXBUF_ADDR_MODE;
localparam [3:0] RXBUF_EIDLE_HI_CNT_REG = RXBUF_EIDLE_HI_CNT;
localparam [3:0] RXBUF_EIDLE_LO_CNT_REG = RXBUF_EIDLE_LO_CNT;
localparam [40:1] RXBUF_EN_REG = RXBUF_EN;
localparam [40:1] RXBUF_RESET_ON_CB_CHANGE_REG = RXBUF_RESET_ON_CB_CHANGE;
localparam [40:1] RXBUF_RESET_ON_COMMAALIGN_REG = RXBUF_RESET_ON_COMMAALIGN;
localparam [40:1] RXBUF_RESET_ON_EIDLE_REG = RXBUF_RESET_ON_EIDLE;
localparam [40:1] RXBUF_RESET_ON_RATE_CHANGE_REG = RXBUF_RESET_ON_RATE_CHANGE;
localparam [5:0] RXBUF_THRESH_OVFLW_REG = RXBUF_THRESH_OVFLW;
localparam [40:1] RXBUF_THRESH_OVRD_REG = RXBUF_THRESH_OVRD;
localparam [5:0] RXBUF_THRESH_UNDFLW_REG = RXBUF_THRESH_UNDFLW;
localparam [4:0] RXCDRFREQRESET_TIME_REG = RXCDRFREQRESET_TIME;
localparam [4:0] RXCDRPHRESET_TIME_REG = RXCDRPHRESET_TIME;
localparam [15:0] RXCDR_CFG0_REG = RXCDR_CFG0;
localparam [15:0] RXCDR_CFG0_GEN3_REG = RXCDR_CFG0_GEN3;
localparam [15:0] RXCDR_CFG1_REG = RXCDR_CFG1;
localparam [15:0] RXCDR_CFG1_GEN3_REG = RXCDR_CFG1_GEN3;
localparam [15:0] RXCDR_CFG2_REG = RXCDR_CFG2;
localparam [15:0] RXCDR_CFG2_GEN3_REG = RXCDR_CFG2_GEN3;
localparam [15:0] RXCDR_CFG3_REG = RXCDR_CFG3;
localparam [15:0] RXCDR_CFG3_GEN3_REG = RXCDR_CFG3_GEN3;
localparam [15:0] RXCDR_CFG4_REG = RXCDR_CFG4;
localparam [15:0] RXCDR_CFG4_GEN3_REG = RXCDR_CFG4_GEN3;
localparam [15:0] RXCDR_CFG5_REG = RXCDR_CFG5;
localparam [15:0] RXCDR_CFG5_GEN3_REG = RXCDR_CFG5_GEN3;
localparam [0:0] RXCDR_FR_RESET_ON_EIDLE_REG = RXCDR_FR_RESET_ON_EIDLE;
localparam [0:0] RXCDR_HOLD_DURING_EIDLE_REG = RXCDR_HOLD_DURING_EIDLE;
localparam [15:0] RXCDR_LOCK_CFG0_REG = RXCDR_LOCK_CFG0;
localparam [15:0] RXCDR_LOCK_CFG1_REG = RXCDR_LOCK_CFG1;
localparam [15:0] RXCDR_LOCK_CFG2_REG = RXCDR_LOCK_CFG2;
localparam [15:0] RXCDR_LOCK_CFG3_REG = RXCDR_LOCK_CFG3;
localparam [0:0] RXCDR_PH_RESET_ON_EIDLE_REG = RXCDR_PH_RESET_ON_EIDLE;
localparam [1:0] RXCFOKDONE_SRC_REG = RXCFOKDONE_SRC;
localparam [15:0] RXCFOK_CFG0_REG = RXCFOK_CFG0;
localparam [15:0] RXCFOK_CFG1_REG = RXCFOK_CFG1;
localparam [15:0] RXCFOK_CFG2_REG = RXCFOK_CFG2;
localparam [6:0] RXDFELPMRESET_TIME_REG = RXDFELPMRESET_TIME;
localparam [15:0] RXDFELPM_KL_CFG0_REG = RXDFELPM_KL_CFG0;
localparam [15:0] RXDFELPM_KL_CFG1_REG = RXDFELPM_KL_CFG1;
localparam [15:0] RXDFELPM_KL_CFG2_REG = RXDFELPM_KL_CFG2;
localparam [15:0] RXDFE_CFG0_REG = RXDFE_CFG0;
localparam [15:0] RXDFE_CFG1_REG = RXDFE_CFG1;
localparam [15:0] RXDFE_GC_CFG0_REG = RXDFE_GC_CFG0;
localparam [15:0] RXDFE_GC_CFG1_REG = RXDFE_GC_CFG1;
localparam [15:0] RXDFE_GC_CFG2_REG = RXDFE_GC_CFG2;
localparam [15:0] RXDFE_H2_CFG0_REG = RXDFE_H2_CFG0;
localparam [15:0] RXDFE_H2_CFG1_REG = RXDFE_H2_CFG1;
localparam [15:0] RXDFE_H3_CFG0_REG = RXDFE_H3_CFG0;
localparam [15:0] RXDFE_H3_CFG1_REG = RXDFE_H3_CFG1;
localparam [15:0] RXDFE_H4_CFG0_REG = RXDFE_H4_CFG0;
localparam [15:0] RXDFE_H4_CFG1_REG = RXDFE_H4_CFG1;
localparam [15:0] RXDFE_H5_CFG0_REG = RXDFE_H5_CFG0;
localparam [15:0] RXDFE_H5_CFG1_REG = RXDFE_H5_CFG1;
localparam [15:0] RXDFE_H6_CFG0_REG = RXDFE_H6_CFG0;
localparam [15:0] RXDFE_H6_CFG1_REG = RXDFE_H6_CFG1;
localparam [15:0] RXDFE_H7_CFG0_REG = RXDFE_H7_CFG0;
localparam [15:0] RXDFE_H7_CFG1_REG = RXDFE_H7_CFG1;
localparam [15:0] RXDFE_H8_CFG0_REG = RXDFE_H8_CFG0;
localparam [15:0] RXDFE_H8_CFG1_REG = RXDFE_H8_CFG1;
localparam [15:0] RXDFE_H9_CFG0_REG = RXDFE_H9_CFG0;
localparam [15:0] RXDFE_H9_CFG1_REG = RXDFE_H9_CFG1;
localparam [15:0] RXDFE_HA_CFG0_REG = RXDFE_HA_CFG0;
localparam [15:0] RXDFE_HA_CFG1_REG = RXDFE_HA_CFG1;
localparam [15:0] RXDFE_HB_CFG0_REG = RXDFE_HB_CFG0;
localparam [15:0] RXDFE_HB_CFG1_REG = RXDFE_HB_CFG1;
localparam [15:0] RXDFE_HC_CFG0_REG = RXDFE_HC_CFG0;
localparam [15:0] RXDFE_HC_CFG1_REG = RXDFE_HC_CFG1;
localparam [15:0] RXDFE_HD_CFG0_REG = RXDFE_HD_CFG0;
localparam [15:0] RXDFE_HD_CFG1_REG = RXDFE_HD_CFG1;
localparam [15:0] RXDFE_HE_CFG0_REG = RXDFE_HE_CFG0;
localparam [15:0] RXDFE_HE_CFG1_REG = RXDFE_HE_CFG1;
localparam [15:0] RXDFE_HF_CFG0_REG = RXDFE_HF_CFG0;
localparam [15:0] RXDFE_HF_CFG1_REG = RXDFE_HF_CFG1;
localparam [15:0] RXDFE_OS_CFG0_REG = RXDFE_OS_CFG0;
localparam [15:0] RXDFE_OS_CFG1_REG = RXDFE_OS_CFG1;
localparam [0:0] RXDFE_PWR_SAVING_REG = RXDFE_PWR_SAVING;
localparam [15:0] RXDFE_UT_CFG0_REG = RXDFE_UT_CFG0;
localparam [15:0] RXDFE_UT_CFG1_REG = RXDFE_UT_CFG1;
localparam [15:0] RXDFE_VP_CFG0_REG = RXDFE_VP_CFG0;
localparam [15:0] RXDFE_VP_CFG1_REG = RXDFE_VP_CFG1;
localparam [15:0] RXDLY_CFG_REG = RXDLY_CFG;
localparam [15:0] RXDLY_LCFG_REG = RXDLY_LCFG;
localparam [72:1] RXELECIDLE_CFG_REG = RXELECIDLE_CFG;
localparam [2:0] RXGBOX_FIFO_INIT_RD_ADDR_REG = RXGBOX_FIFO_INIT_RD_ADDR;
localparam [40:1] RXGEARBOX_EN_REG = RXGEARBOX_EN;
localparam [4:0] RXISCANRESET_TIME_REG = RXISCANRESET_TIME;
localparam [15:0] RXLPM_CFG_REG = RXLPM_CFG;
localparam [15:0] RXLPM_GC_CFG_REG = RXLPM_GC_CFG;
localparam [15:0] RXLPM_KH_CFG0_REG = RXLPM_KH_CFG0;
localparam [15:0] RXLPM_KH_CFG1_REG = RXLPM_KH_CFG1;
localparam [15:0] RXLPM_OS_CFG0_REG = RXLPM_OS_CFG0;
localparam [15:0] RXLPM_OS_CFG1_REG = RXLPM_OS_CFG1;
localparam [8:0] RXOOB_CFG_REG = RXOOB_CFG;
localparam [48:1] RXOOB_CLK_CFG_REG = RXOOB_CLK_CFG;
localparam [4:0] RXOSCALRESET_TIME_REG = RXOSCALRESET_TIME;
localparam [5:0] RXOUT_DIV_REG = RXOUT_DIV;
localparam [4:0] RXPCSRESET_TIME_REG = RXPCSRESET_TIME;
localparam [15:0] RXPHBEACON_CFG_REG = RXPHBEACON_CFG;
localparam [15:0] RXPHDLY_CFG_REG = RXPHDLY_CFG;
localparam [15:0] RXPHSAMP_CFG_REG = RXPHSAMP_CFG;
localparam [15:0] RXPHSLIP_CFG_REG = RXPHSLIP_CFG;
localparam [4:0] RXPH_MONITOR_SEL_REG = RXPH_MONITOR_SEL;
localparam [0:0] RXPI_AUTO_BW_SEL_BYPASS_REG = RXPI_AUTO_BW_SEL_BYPASS;
localparam [15:0] RXPI_CFG_REG = RXPI_CFG;
localparam [0:0] RXPI_LPM_REG = RXPI_LPM;
localparam [15:0] RXPI_RSV0_REG = RXPI_RSV0;
localparam [1:0] RXPI_SEL_LC_REG = RXPI_SEL_LC;
localparam [1:0] RXPI_STARTCODE_REG = RXPI_STARTCODE;
localparam [0:0] RXPI_VREFSEL_REG = RXPI_VREFSEL;
localparam [64:1] RXPMACLK_SEL_REG = RXPMACLK_SEL;
localparam [4:0] RXPMARESET_TIME_REG = RXPMARESET_TIME;
localparam [0:0] RXPRBS_ERR_LOOPBACK_REG = RXPRBS_ERR_LOOPBACK;
localparam [7:0] RXPRBS_LINKACQ_CNT_REG = RXPRBS_LINKACQ_CNT;
localparam [3:0] RXSLIDE_AUTO_WAIT_REG = RXSLIDE_AUTO_WAIT;
localparam [32:1] RXSLIDE_MODE_REG = RXSLIDE_MODE;
localparam [0:0] RXSYNC_MULTILANE_REG = RXSYNC_MULTILANE;
localparam [0:0] RXSYNC_OVRD_REG = RXSYNC_OVRD;
localparam [0:0] RXSYNC_SKIP_DA_REG = RXSYNC_SKIP_DA;
localparam [0:0] RX_AFE_CM_EN_REG = RX_AFE_CM_EN;
localparam [15:0] RX_BIAS_CFG0_REG = RX_BIAS_CFG0;
localparam [5:0] RX_BUFFER_CFG_REG = RX_BUFFER_CFG;
localparam [0:0] RX_CAPFF_SARC_ENB_REG = RX_CAPFF_SARC_ENB;
localparam [5:0] RX_CLK25_DIV_REG = RX_CLK25_DIV;
localparam [0:0] RX_CLKMUX_EN_REG = RX_CLKMUX_EN;
localparam [4:0] RX_CLK_SLIP_OVRD_REG = RX_CLK_SLIP_OVRD;
localparam [3:0] RX_CM_BUF_CFG_REG = RX_CM_BUF_CFG;
localparam [0:0] RX_CM_BUF_PD_REG = RX_CM_BUF_PD;
localparam [1:0] RX_CM_SEL_REG = RX_CM_SEL;
localparam [3:0] RX_CM_TRIM_REG = RX_CM_TRIM;
localparam [0:0] RX_CTLE1_KHKL_REG = RX_CTLE1_KHKL;
localparam [0:0] RX_CTLE2_KHKL_REG = RX_CTLE2_KHKL;
localparam [0:0] RX_CTLE3_AGC_REG = RX_CTLE3_AGC;
localparam [7:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH;
localparam [5:0] RX_DDI_SEL_REG = RX_DDI_SEL;
localparam [40:1] RX_DEFER_RESET_BUF_EN_REG = RX_DEFER_RESET_BUF_EN;
localparam [2:0] RX_DEGEN_CTRL_REG = RX_DEGEN_CTRL;
localparam [2:0] RX_DFELPM_CFG0_REG = RX_DFELPM_CFG0;
localparam [0:0] RX_DFELPM_CFG1_REG = RX_DFELPM_CFG1;
localparam [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_REG = RX_DFELPM_KLKH_AGC_STUP_EN;
localparam [1:0] RX_DFE_AGC_CFG0_REG = RX_DFE_AGC_CFG0;
localparam [2:0] RX_DFE_AGC_CFG1_REG = RX_DFE_AGC_CFG1;
localparam [1:0] RX_DFE_KL_LPM_KH_CFG0_REG = RX_DFE_KL_LPM_KH_CFG0;
localparam [2:0] RX_DFE_KL_LPM_KH_CFG1_REG = RX_DFE_KL_LPM_KH_CFG1;
localparam [1:0] RX_DFE_KL_LPM_KL_CFG0_REG = RX_DFE_KL_LPM_KL_CFG0;
localparam [2:0] RX_DFE_KL_LPM_KL_CFG1_REG = RX_DFE_KL_LPM_KL_CFG1;
localparam [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_REG = RX_DFE_LPM_HOLD_DURING_EIDLE;
localparam [40:1] RX_DISPERR_SEQ_MATCH_REG = RX_DISPERR_SEQ_MATCH;
localparam [0:0] RX_DIV2_MODE_B_REG = RX_DIV2_MODE_B;
localparam [4:0] RX_DIVRESET_TIME_REG = RX_DIVRESET_TIME;
localparam [0:0] RX_EN_CTLE_RCAL_B_REG = RX_EN_CTLE_RCAL_B;
localparam [0:0] RX_EN_HI_LR_REG = RX_EN_HI_LR;
localparam [8:0] RX_EXT_RL_CTRL_REG = RX_EXT_RL_CTRL;
localparam [6:0] RX_EYESCAN_VS_CODE_REG = RX_EYESCAN_VS_CODE;
localparam [0:0] RX_EYESCAN_VS_NEG_DIR_REG = RX_EYESCAN_VS_NEG_DIR;
localparam [1:0] RX_EYESCAN_VS_RANGE_REG = RX_EYESCAN_VS_RANGE;
localparam [0:0] RX_EYESCAN_VS_UT_SIGN_REG = RX_EYESCAN_VS_UT_SIGN;
localparam [0:0] RX_FABINT_USRCLK_FLOP_REG = RX_FABINT_USRCLK_FLOP;
localparam [1:0] RX_INT_DATAWIDTH_REG = RX_INT_DATAWIDTH;
localparam [0:0] RX_PMA_POWER_SAVE_REG = RX_PMA_POWER_SAVE;
localparam real RX_PROGDIV_CFG_REG = RX_PROGDIV_CFG;
localparam [15:0] RX_PROGDIV_RATE_REG = RX_PROGDIV_RATE;
localparam [3:0] RX_RESLOAD_CTRL_REG = RX_RESLOAD_CTRL;
localparam [0:0] RX_RESLOAD_OVRD_REG = RX_RESLOAD_OVRD;
localparam [2:0] RX_SAMPLE_PERIOD_REG = RX_SAMPLE_PERIOD;
localparam [5:0] RX_SIG_VALID_DLY_REG = RX_SIG_VALID_DLY;
localparam [0:0] RX_SUM_DFETAPREP_EN_REG = RX_SUM_DFETAPREP_EN;
localparam [3:0] RX_SUM_IREF_TUNE_REG = RX_SUM_IREF_TUNE;
localparam [3:0] RX_SUM_VCMTUNE_REG = RX_SUM_VCMTUNE;
localparam [0:0] RX_SUM_VCM_OVWR_REG = RX_SUM_VCM_OVWR;
localparam [2:0] RX_SUM_VREF_TUNE_REG = RX_SUM_VREF_TUNE;
localparam [1:0] RX_TUNE_AFE_OS_REG = RX_TUNE_AFE_OS;
localparam [2:0] RX_VREG_CTRL_REG = RX_VREG_CTRL;
localparam [0:0] RX_VREG_PDB_REG = RX_VREG_PDB;
localparam [1:0] RX_WIDEMODE_CDR_REG = RX_WIDEMODE_CDR;
localparam [40:1] RX_XCLK_SEL_REG = RX_XCLK_SEL;
localparam [0:0] RX_XMODE_SEL_REG = RX_XMODE_SEL;
localparam [6:0] SAS_MAX_COM_REG = SAS_MAX_COM;
localparam [5:0] SAS_MIN_COM_REG = SAS_MIN_COM;
localparam [3:0] SATA_BURST_SEQ_LEN_REG = SATA_BURST_SEQ_LEN;
localparam [2:0] SATA_BURST_VAL_REG = SATA_BURST_VAL;
localparam [88:1] SATA_CPLL_CFG_REG = SATA_CPLL_CFG;
localparam [2:0] SATA_EIDLE_VAL_REG = SATA_EIDLE_VAL;
localparam [5:0] SATA_MAX_BURST_REG = SATA_MAX_BURST;
localparam [5:0] SATA_MAX_INIT_REG = SATA_MAX_INIT;
localparam [5:0] SATA_MAX_WAKE_REG = SATA_MAX_WAKE;
localparam [5:0] SATA_MIN_BURST_REG = SATA_MIN_BURST;
localparam [5:0] SATA_MIN_INIT_REG = SATA_MIN_INIT;
localparam [5:0] SATA_MIN_WAKE_REG = SATA_MIN_WAKE;
localparam [40:1] SHOW_REALIGN_COMMA_REG = SHOW_REALIGN_COMMA;
localparam [40:1] SIM_RECEIVER_DETECT_PASS_REG = SIM_RECEIVER_DETECT_PASS;
localparam [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
localparam [0:0] SIM_TX_EIDLE_DRIVE_LEVEL_REG = SIM_TX_EIDLE_DRIVE_LEVEL;
localparam real SIM_VERSION_REG = SIM_VERSION;
localparam [1:0] TAPDLY_SET_TX_REG = TAPDLY_SET_TX;
localparam [3:0] TEMPERATURE_PAR_REG = TEMPERATURE_PAR;
localparam [14:0] TERM_RCAL_CFG_REG = TERM_RCAL_CFG;
localparam [2:0] TERM_RCAL_OVRD_REG = TERM_RCAL_OVRD;
localparam [7:0] TRANS_TIME_RATE_REG = TRANS_TIME_RATE;
localparam [7:0] TST_RSV0_REG = TST_RSV0;
localparam [7:0] TST_RSV1_REG = TST_RSV1;
localparam [40:1] TXBUF_EN_REG = TXBUF_EN;
localparam [40:1] TXBUF_RESET_ON_RATE_CHANGE_REG = TXBUF_RESET_ON_RATE_CHANGE;
localparam [15:0] TXDLY_CFG_REG = TXDLY_CFG;
localparam [15:0] TXDLY_LCFG_REG = TXDLY_LCFG;
localparam [32:1] TXFIFO_ADDR_CFG_REG = TXFIFO_ADDR_CFG;
localparam [2:0] TXGBOX_FIFO_INIT_RD_ADDR_REG = TXGBOX_FIFO_INIT_RD_ADDR;
localparam [40:1] TXGEARBOX_EN_REG = TXGEARBOX_EN;
localparam [5:0] TXOUT_DIV_REG = TXOUT_DIV;
localparam [4:0] TXPCSRESET_TIME_REG = TXPCSRESET_TIME;
localparam [15:0] TXPHDLY_CFG0_REG = TXPHDLY_CFG0;
localparam [15:0] TXPHDLY_CFG1_REG = TXPHDLY_CFG1;
localparam [15:0] TXPH_CFG_REG = TXPH_CFG;
localparam [15:0] TXPH_CFG2_REG = TXPH_CFG2;
localparam [4:0] TXPH_MONITOR_SEL_REG = TXPH_MONITOR_SEL;
localparam [1:0] TXPI_CFG0_REG = TXPI_CFG0;
localparam [1:0] TXPI_CFG1_REG = TXPI_CFG1;
localparam [1:0] TXPI_CFG2_REG = TXPI_CFG2;
localparam [0:0] TXPI_CFG3_REG = TXPI_CFG3;
localparam [0:0] TXPI_CFG4_REG = TXPI_CFG4;
localparam [2:0] TXPI_CFG5_REG = TXPI_CFG5;
localparam [0:0] TXPI_GRAY_SEL_REG = TXPI_GRAY_SEL;
localparam [0:0] TXPI_INVSTROBE_SEL_REG = TXPI_INVSTROBE_SEL;
localparam [0:0] TXPI_LPM_REG = TXPI_LPM;
localparam [72:1] TXPI_PPMCLK_SEL_REG = TXPI_PPMCLK_SEL;
localparam [7:0] TXPI_PPM_CFG_REG = TXPI_PPM_CFG;
localparam [15:0] TXPI_RSV0_REG = TXPI_RSV0;
localparam [2:0] TXPI_SYNFREQ_PPM_REG = TXPI_SYNFREQ_PPM;
localparam [0:0] TXPI_VREFSEL_REG = TXPI_VREFSEL;
localparam [4:0] TXPMARESET_TIME_REG = TXPMARESET_TIME;
localparam [0:0] TXSYNC_MULTILANE_REG = TXSYNC_MULTILANE;
localparam [0:0] TXSYNC_OVRD_REG = TXSYNC_OVRD;
localparam [0:0] TXSYNC_SKIP_DA_REG = TXSYNC_SKIP_DA;
localparam [5:0] TX_CLK25_DIV_REG = TX_CLK25_DIV;
localparam [0:0] TX_CLKMUX_EN_REG = TX_CLKMUX_EN;
localparam [0:0] TX_CLKREG_PDB_REG = TX_CLKREG_PDB;
localparam [2:0] TX_CLKREG_SET_REG = TX_CLKREG_SET;
localparam [7:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH;
localparam [5:0] TX_DCD_CFG_REG = TX_DCD_CFG;
localparam [0:0] TX_DCD_EN_REG = TX_DCD_EN;
localparam [5:0] TX_DEEMPH0_REG = TX_DEEMPH0;
localparam [5:0] TX_DEEMPH1_REG = TX_DEEMPH1;
localparam [4:0] TX_DIVRESET_TIME_REG = TX_DIVRESET_TIME;
localparam [64:1] TX_DRIVE_MODE_REG = TX_DRIVE_MODE;
localparam [1:0] TX_DRVMUX_CTRL_REG = TX_DRVMUX_CTRL;
localparam [2:0] TX_EIDLE_ASSERT_DELAY_REG = TX_EIDLE_ASSERT_DELAY;
localparam [2:0] TX_EIDLE_DEASSERT_DELAY_REG = TX_EIDLE_DEASSERT_DELAY;
localparam [0:0] TX_EML_PHI_TUNE_REG = TX_EML_PHI_TUNE;
localparam [0:0] TX_FABINT_USRCLK_FLOP_REG = TX_FABINT_USRCLK_FLOP;
localparam [0:0] TX_FIFO_BYP_EN_REG = TX_FIFO_BYP_EN;
localparam [0:0] TX_IDLE_DATA_ZERO_REG = TX_IDLE_DATA_ZERO;
localparam [1:0] TX_INT_DATAWIDTH_REG = TX_INT_DATAWIDTH;
localparam [40:1] TX_LOOPBACK_DRIVE_HIZ_REG = TX_LOOPBACK_DRIVE_HIZ;
localparam [0:0] TX_MAINCURSOR_SEL_REG = TX_MAINCURSOR_SEL;
localparam [6:0] TX_MARGIN_FULL_0_REG = TX_MARGIN_FULL_0;
localparam [6:0] TX_MARGIN_FULL_1_REG = TX_MARGIN_FULL_1;
localparam [6:0] TX_MARGIN_FULL_2_REG = TX_MARGIN_FULL_2;
localparam [6:0] TX_MARGIN_FULL_3_REG = TX_MARGIN_FULL_3;
localparam [6:0] TX_MARGIN_FULL_4_REG = TX_MARGIN_FULL_4;
localparam [6:0] TX_MARGIN_LOW_0_REG = TX_MARGIN_LOW_0;
localparam [6:0] TX_MARGIN_LOW_1_REG = TX_MARGIN_LOW_1;
localparam [6:0] TX_MARGIN_LOW_2_REG = TX_MARGIN_LOW_2;
localparam [6:0] TX_MARGIN_LOW_3_REG = TX_MARGIN_LOW_3;
localparam [6:0] TX_MARGIN_LOW_4_REG = TX_MARGIN_LOW_4;
localparam [2:0] TX_MODE_SEL_REG = TX_MODE_SEL;
localparam [15:0] TX_PHICAL_CFG0_REG = TX_PHICAL_CFG0;
localparam [15:0] TX_PHICAL_CFG1_REG = TX_PHICAL_CFG1;
localparam [15:0] TX_PHICAL_CFG2_REG = TX_PHICAL_CFG2;
localparam [1:0] TX_PI_BIASSET_REG = TX_PI_BIASSET;
localparam [15:0] TX_PI_CFG0_REG = TX_PI_CFG0;
localparam [15:0] TX_PI_CFG1_REG = TX_PI_CFG1;
localparam [0:0] TX_PI_DIV2_MODE_B_REG = TX_PI_DIV2_MODE_B;
localparam [0:0] TX_PI_SEL_QPLL0_REG = TX_PI_SEL_QPLL0;
localparam [0:0] TX_PI_SEL_QPLL1_REG = TX_PI_SEL_QPLL1;
localparam [0:0] TX_PMADATA_OPT_REG = TX_PMADATA_OPT;
localparam [0:0] TX_PMA_POWER_SAVE_REG = TX_PMA_POWER_SAVE;
localparam [1:0] TX_PREDRV_CTRL_REG = TX_PREDRV_CTRL;
localparam [48:1] TX_PROGCLK_SEL_REG = TX_PROGCLK_SEL;
localparam real TX_PROGDIV_CFG_REG = TX_PROGDIV_CFG;
localparam [15:0] TX_PROGDIV_RATE_REG = TX_PROGDIV_RATE;
localparam [13:0] TX_RXDETECT_CFG_REG = TX_RXDETECT_CFG;
localparam [2:0] TX_RXDETECT_REF_REG = TX_RXDETECT_REF;
localparam [2:0] TX_SAMPLE_PERIOD_REG = TX_SAMPLE_PERIOD;
localparam [0:0] TX_SARC_LPBK_ENB_REG = TX_SARC_LPBK_ENB;
localparam [40:1] TX_XCLK_SEL_REG = TX_XCLK_SEL;
localparam [0:0] USE_PCS_CLK_PHASE_SEL_REG = USE_PCS_CLK_PHASE_SEL;
`endif
localparam [0:0] AEN_CDRSTEPSEL_REG = 1'b0;
localparam [0:0] AEN_CPLL_REG = 1'b0;
localparam [0:0] AEN_ELPCAL_REG = 1'b0;
localparam [0:0] AEN_EYESCAN_REG = 1'b1;
localparam [0:0] AEN_LOOPBACK_REG = 1'b0;
localparam [0:0] AEN_MASTER_REG = 1'b0;
localparam [0:0] AEN_MUXDCD_REG = 1'b0;
localparam [0:0] AEN_PD_AND_EIDLE_REG = 1'b0;
localparam [0:0] AEN_POLARITY_REG = 1'b0;
localparam [0:0] AEN_PRBS_REG = 1'b0;
localparam [0:0] AEN_RESET_REG = 1'b0;
localparam [0:0] AEN_RXCDR_REG = 1'b0;
localparam [0:0] AEN_RXDFE_REG = 1'b0;
localparam [0:0] AEN_RXDFELPM_REG = 1'b0;
localparam [0:0] AEN_RXOUTCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_RXPHDLY_REG = 1'b0;
localparam [0:0] AEN_RXPLLCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_RXSYSCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXOUTCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXPHDLY_REG = 1'b0;
localparam [0:0] AEN_TXPI_PPM_REG = 1'b0;
localparam [0:0] AEN_TXPLLCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TXSYSCLK_SEL_REG = 1'b0;
localparam [0:0] AEN_TX_DRIVE_MODE_REG = 1'b0;
localparam [9:0] AMONITOR_CFG_REG = 1;
localparam [0:0] A_AFECFOKEN_REG = 1'b0;
localparam [0:0] A_CPLLLOCKEN_REG = 1'b0;
localparam [0:0] A_CPLLPD_REG = 1'b0;
localparam [0:0] A_CPLLRESET_REG = 1'b0;
localparam [5:0] A_DFECFOKFCDAC_REG = 6'b000000;
localparam [3:0] A_DFECFOKFCNUM_REG = 4'b0000;
localparam [0:0] A_DFECFOKFPULSE_REG = 1'b0;
localparam [0:0] A_DFECFOKHOLD_REG = 1'b0;
localparam [0:0] A_DFECFOKOVREN_REG = 1'b0;
localparam [0:0] A_ELPCALDVORWREN_REG = 1'b0;
localparam [0:0] A_ELPCALPAORWREN_REG = 1'b0;
localparam [0:0] A_EYESCANMODE_REG = 1'b0;
localparam [0:0] A_EYESCANRESET_REG = 1'b0;
localparam [0:0] A_GTRESETSEL_REG = 1'b0;
localparam [0:0] A_GTRXRESET_REG = 1'b0;
localparam [0:0] A_GTTXRESET_REG = 1'b0;
localparam [80:1] A_LOOPBACK_REG = "NoLoopBack";
localparam [0:0] A_LPMGCHOLD_REG = 1'b0;
localparam [0:0] A_LPMGCOVREN_REG = 1'b0;
localparam [0:0] A_LPMOSHOLD_REG = 1'b0;
localparam [0:0] A_LPMOSOVREN_REG = 1'b0;
localparam [0:0] A_MUXDCDEXHOLD_REG = 1'b0;
localparam [0:0] A_MUXDCDORWREN_REG = 1'b0;
localparam [0:0] A_RXBUFRESET_REG = 1'b0;
localparam [0:0] A_RXCDRFREQRESET_REG = 1'b0;
localparam [0:0] A_RXCDRHOLD_REG = 1'b0;
localparam [0:0] A_RXCDROVRDEN_REG = 1'b0;
localparam [0:0] A_RXCDRRESET_REG = 1'b0;
localparam [0:0] A_RXDFEAGCHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEAGCOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFECFOKFEN_REG = 1'b0;
localparam [0:0] A_RXDFELFHOLD_REG = 1'b0;
localparam [0:0] A_RXDFELFOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFELPMRESET_REG = 1'b0;
localparam [0:0] A_RXDFETAP10HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP10OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP11HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP11OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP12HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP12OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP13HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP13OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP14HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP14OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP15HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP15OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP2HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP2OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP3HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP3OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP4HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP4OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP5HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP5OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP6HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP6OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP7HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP7OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP8HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP8OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFETAP9HOLD_REG = 1'b0;
localparam [0:0] A_RXDFETAP9OVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEUTHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEUTOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEVPHOLD_REG = 1'b0;
localparam [0:0] A_RXDFEVPOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDFEVSEN_REG = 1'b0;
localparam [0:0] A_RXDFEXYDEN_REG = 1'b0;
localparam [0:0] A_RXDLYBYPASS_REG = 1'b0;
localparam [0:0] A_RXDLYEN_REG = 1'b0;
localparam [0:0] A_RXDLYOVRDEN_REG = 1'b0;
localparam [0:0] A_RXDLYSRESET_REG = 1'b0;
localparam [0:0] A_RXLPMEN_REG = 1'b0;
localparam [0:0] A_RXLPMHFHOLD_REG = 1'b0;
localparam [0:0] A_RXLPMHFOVRDEN_REG = 1'b0;
localparam [0:0] A_RXLPMLFHOLD_REG = 1'b0;
localparam [0:0] A_RXLPMLFKLOVRDEN_REG = 1'b0;
localparam [1:0] A_RXMONITORSEL_REG = 2'b00;
localparam [0:0] A_RXOOBRESET_REG = 1'b0;
localparam [0:0] A_RXOSHOLD_REG = 1'b0;
localparam [0:0] A_RXOSOVRDEN_REG = 1'b0;
localparam [128:1] A_RXOUTCLKSEL_REG = "Disabled";
localparam [0:0] A_RXPCSRESET_REG = 1'b0;
localparam [24:1] A_RXPD_REG = "P0";
localparam [0:0] A_RXPHALIGN_REG = 1'b0;
localparam [0:0] A_RXPHALIGNEN_REG = 1'b0;
localparam [0:0] A_RXPHDLYPD_REG = 1'b0;
localparam [0:0] A_RXPHDLYRESET_REG = 1'b0;
localparam [0:0] A_RXPHOVRDEN_REG = 1'b0;
localparam [64:1] A_RXPLLCLKSEL_REG = "CPLLCLK";
localparam [0:0] A_RXPMARESET_REG = 1'b0;
localparam [0:0] A_RXPOLARITY_REG = 1'b0;
localparam [0:0] A_RXPRBSCNTRESET_REG = 1'b0;
localparam [48:1] A_RXPRBSSEL_REG = "PRBS7";
localparam [88:1] A_RXSYSCLKSEL_REG = "CPLLREFCLK";
localparam [2:0] A_TXBUFDIFFCTRL_REG = 3'b100;
localparam [0:0] A_TXDEEMPH_REG = 1'b0;
localparam [0:0] A_TXDLYBYPASS_REG = 1'b0;
localparam [0:0] A_TXDLYEN_REG = 1'b0;
localparam [0:0] A_TXDLYOVRDEN_REG = 1'b0;
localparam [0:0] A_TXDLYSRESET_REG = 1'b0;
localparam [0:0] A_TXELECIDLE_REG = 1'b0;
localparam [0:0] A_TXINHIBIT_REG = 1'b0;
localparam [6:0] A_TXMAINCURSOR_REG = 7'b0000000;
localparam [2:0] A_TXMARGIN_REG = 3'b000;
localparam [128:1] A_TXOUTCLKSEL_REG = "Disabled";
localparam [0:0] A_TXPCSRESET_REG = 1'b0;
localparam [24:1] A_TXPD_REG = "P0";
localparam [0:0] A_TXPHALIGN_REG = 1'b0;
localparam [0:0] A_TXPHALIGNEN_REG = 1'b0;
localparam [0:0] A_TXPHDLYPD_REG = 1'b0;
localparam [0:0] A_TXPHDLYRESET_REG = 1'b0;
localparam [0:0] A_TXPHINIT_REG = 1'b0;
localparam [0:0] A_TXPHOVRDEN_REG = 1'b0;
localparam [0:0] A_TXPIPPMOVRDEN_REG = 1'b0;
localparam [0:0] A_TXPIPPMPD_REG = 1'b0;
localparam [0:0] A_TXPIPPMSEL_REG = 1'b0;
localparam [64:1] A_TXPLLCLKSEL_REG = "CPLLCLK";
localparam [0:0] A_TXPMARESET_REG = 1'b0;
localparam [0:0] A_TXPOLARITY_REG = 1'b0;
localparam [4:0] A_TXPOSTCURSOR_REG = 5'b00000;
localparam [0:0] A_TXPRBSFORCEERR_REG = 1'b0;
localparam [96:1] A_TXPRBSSEL_REG = "PRBS7";
localparam [4:0] A_TXPRECURSOR_REG = 5'b00000;
localparam [0:0] A_TXSWING_REG = 1'b0;
localparam [88:1] A_TXSYSCLKSEL_REG = "CPLLREFCLK";
localparam [40:1] GEN_RXUSRCLK_REG = "TRUE";
localparam [40:1] GEN_TXUSRCLK_REG = "TRUE";
localparam [0:0] GT_INSTANTIATED_REG = 1'b1;
localparam [40:1] RXPLL_SEL_REG = "CPLL";
localparam [0:0] TXOUTCLKPCS_SEL_REG = 1'b0;
localparam [9:0] TX_USERPATTERN_DATA0_REG = 10'b0101111100;
localparam [9:0] TX_USERPATTERN_DATA1_REG = 10'b0101010101;
localparam [9:0] TX_USERPATTERN_DATA2_REG = 10'b1010000011;
localparam [9:0] TX_USERPATTERN_DATA3_REG = 10'b1010101010;
localparam [9:0] TX_USERPATTERN_DATA4_REG = 10'b0101111100;
localparam [9:0] TX_USERPATTERN_DATA5_REG = 10'b0101010101;
localparam [9:0] TX_USERPATTERN_DATA6_REG = 10'b1010000011;
localparam [9:0] TX_USERPATTERN_DATA7_REG = 10'b1010101010;
wire [63:0] RX_PROGDIV_CFG_BIN;
wire [63:0] SIM_VERSION_BIN;
wire [63:0] TX_PROGDIV_CFG_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
tri0 glblGSR = glbl.GSR;
`ifdef XIL_TIMING
reg notifier;
`endif
reg trig_attr = 1'b0;
reg attr_err = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "GTYE3_CHANNEL_dr.v"
`endif
wire CPLLFBCLKLOST_out;
wire CPLLLOCK_out;
wire CPLLREFCLKLOST_out;
wire DRPRDY_out;
wire EYESCANDATAERROR_out;
wire GTPOWERGOOD_out;
wire GTREFCLKMONITOR_out;
wire GTYTXN_out;
wire GTYTXP_out;
wire PCIERATEGEN3_out;
wire PCIERATEIDLE_out;
wire PCIESYNCTXSYNCDONE_out;
wire PCIEUSERGEN3RDY_out;
wire PCIEUSERPHYSTATUSRST_out;
wire PCIEUSERRATESTART_out;
wire PHYSTATUS_out;
wire RESETEXCEPTION_out;
wire RXBYTEISALIGNED_out;
wire RXBYTEREALIGN_out;
wire RXCDRLOCK_out;
wire RXCDRPHDONE_out;
wire RXCHANBONDSEQ_out;
wire RXCHANISALIGNED_out;
wire RXCHANREALIGN_out;
wire RXCKCALDONE_out;
wire RXCOMINITDET_out;
wire RXCOMMADET_out;
wire RXCOMSASDET_out;
wire RXCOMWAKEDET_out;
wire RXDLYSRESETDONE_out;
wire RXELECIDLE_out;
wire RXOSINTDONE_out;
wire RXOSINTSTARTED_out;
wire RXOSINTSTROBEDONE_out;
wire RXOSINTSTROBESTARTED_out;
wire RXOUTCLKFABRIC_out;
wire RXOUTCLKPCS_out;
wire RXOUTCLK_out;
wire RXPHALIGNDONE_out;
wire RXPHALIGNERR_out;
wire RXPMARESETDONE_out;
wire RXPRBSERR_out;
wire RXPRBSLOCKED_out;
wire RXPRGDIVRESETDONE_out;
wire RXRATEDONE_out;
wire RXRECCLKOUT_out;
wire RXRESETDONE_out;
wire RXSLIDERDY_out;
wire RXSLIPDONE_out;
wire RXSLIPOUTCLKRDY_out;
wire RXSLIPPMARDY_out;
wire RXSYNCDONE_out;
wire RXSYNCOUT_out;
wire RXVALID_out;
wire TXCOMFINISH_out;
wire TXDCCDONE_out;
wire TXDLYSRESETDONE_out;
wire TXOUTCLKFABRIC_out;
wire TXOUTCLKPCS_out;
wire TXOUTCLK_out;
wire TXPHALIGNDONE_out;
wire TXPHINITDONE_out;
wire TXPMARESETDONE_out;
wire TXPRGDIVRESETDONE_out;
wire TXRATEDONE_out;
wire TXRESETDONE_out;
wire TXSYNCDONE_out;
wire TXSYNCOUT_out;
wire [11:0] PMASCANOUT_out;
wire [127:0] RXDATA_out;
wire [15:0] DRPDO_out;
wire [15:0] PCSRSVDOUT_out;
wire [15:0] RXCTRL0_out;
wire [15:0] RXCTRL1_out;
wire [16:0] DMONITOROUT_out;
wire [18:0] SCANOUT_out;
wire [1:0] PCIERATEQPLLPD_out;
wire [1:0] PCIERATEQPLLRESET_out;
wire [1:0] RXCLKCORCNT_out;
wire [1:0] RXDATAVALID_out;
wire [1:0] RXHEADERVALID_out;
wire [1:0] RXSTARTOFSEQ_out;
wire [1:0] TXBUFSTATUS_out;
wire [2:0] BUFGTCEMASK_out;
wire [2:0] BUFGTCE_out;
wire [2:0] BUFGTRESET_out;
wire [2:0] BUFGTRSTMASK_out;
wire [2:0] RXBUFSTATUS_out;
wire [2:0] RXSTATUS_out;
wire [4:0] RXCHBONDO_out;
wire [5:0] RXHEADER_out;
wire [6:0] RXMONITOROUT_out;
wire [7:0] PINRSRVDAS_out;
wire [7:0] RXCTRL2_out;
wire [7:0] RXCTRL3_out;
wire [7:0] RXDATAEXTENDRSVD_out;
wire [8:0] BUFGTDIV_out;
wire CPLLFBCLKLOST_delay;
wire CPLLLOCK_delay;
wire CPLLREFCLKLOST_delay;
wire DRPRDY_delay;
wire EYESCANDATAERROR_delay;
wire GTPOWERGOOD_delay;
wire GTREFCLKMONITOR_delay;
wire GTYTXN_delay;
wire GTYTXP_delay;
wire PCIERATEGEN3_delay;
wire PCIERATEIDLE_delay;
wire PCIESYNCTXSYNCDONE_delay;
wire PCIEUSERGEN3RDY_delay;
wire PCIEUSERPHYSTATUSRST_delay;
wire PCIEUSERRATESTART_delay;
wire PHYSTATUS_delay;
wire RESETEXCEPTION_delay;
wire RXBYTEISALIGNED_delay;
wire RXBYTEREALIGN_delay;
wire RXCDRLOCK_delay;
wire RXCDRPHDONE_delay;
wire RXCHANBONDSEQ_delay;
wire RXCHANISALIGNED_delay;
wire RXCHANREALIGN_delay;
wire RXCKCALDONE_delay;
wire RXCOMINITDET_delay;
wire RXCOMMADET_delay;
wire RXCOMSASDET_delay;
wire RXCOMWAKEDET_delay;
wire RXDLYSRESETDONE_delay;
wire RXELECIDLE_delay;
wire RXOSINTDONE_delay;
wire RXOSINTSTARTED_delay;
wire RXOSINTSTROBEDONE_delay;
wire RXOSINTSTROBESTARTED_delay;
wire RXOUTCLKFABRIC_delay;
wire RXOUTCLKPCS_delay;
wire RXOUTCLK_delay;
wire RXPHALIGNDONE_delay;
wire RXPHALIGNERR_delay;
wire RXPMARESETDONE_delay;
wire RXPRBSERR_delay;
wire RXPRBSLOCKED_delay;
wire RXPRGDIVRESETDONE_delay;
wire RXRATEDONE_delay;
wire RXRECCLKOUT_delay;
wire RXRESETDONE_delay;
wire RXSLIDERDY_delay;
wire RXSLIPDONE_delay;
wire RXSLIPOUTCLKRDY_delay;
wire RXSLIPPMARDY_delay;
wire RXSYNCDONE_delay;
wire RXSYNCOUT_delay;
wire RXVALID_delay;
wire TXCOMFINISH_delay;
wire TXDCCDONE_delay;
wire TXDLYSRESETDONE_delay;
wire TXOUTCLKFABRIC_delay;
wire TXOUTCLKPCS_delay;
wire TXOUTCLK_delay;
wire TXPHALIGNDONE_delay;
wire TXPHINITDONE_delay;
wire TXPMARESETDONE_delay;
wire TXPRGDIVRESETDONE_delay;
wire TXRATEDONE_delay;
wire TXRESETDONE_delay;
wire TXSYNCDONE_delay;
wire TXSYNCOUT_delay;
wire [127:0] RXDATA_delay;
wire [15:0] DRPDO_delay;
wire [15:0] PCSRSVDOUT_delay;
wire [15:0] RXCTRL0_delay;
wire [15:0] RXCTRL1_delay;
wire [16:0] DMONITOROUT_delay;
wire [1:0] PCIERATEQPLLPD_delay;
wire [1:0] PCIERATEQPLLRESET_delay;
wire [1:0] RXCLKCORCNT_delay;
wire [1:0] RXDATAVALID_delay;
wire [1:0] RXHEADERVALID_delay;
wire [1:0] RXSTARTOFSEQ_delay;
wire [1:0] TXBUFSTATUS_delay;
wire [2:0] BUFGTCEMASK_delay;
wire [2:0] BUFGTCE_delay;
wire [2:0] BUFGTRESET_delay;
wire [2:0] BUFGTRSTMASK_delay;
wire [2:0] RXBUFSTATUS_delay;
wire [2:0] RXSTATUS_delay;
wire [4:0] RXCHBONDO_delay;
wire [5:0] RXHEADER_delay;
wire [6:0] RXMONITOROUT_delay;
wire [7:0] PINRSRVDAS_delay;
wire [7:0] RXCTRL2_delay;
wire [7:0] RXCTRL3_delay;
wire [7:0] RXDATAEXTENDRSVD_delay;
wire [8:0] BUFGTDIV_delay;
wire CDRSTEPDIR_in;
wire CDRSTEPSQ_in;
wire CDRSTEPSX_in;
wire CFGRESET_in;
wire CLKRSVD0_in;
wire CLKRSVD1_in;
wire CPLLLOCKDETCLK_in;
wire CPLLLOCKEN_in;
wire CPLLPD_in;
wire CPLLRESET_in;
wire DMONFIFORESET_in;
wire DMONITORCLK_in;
wire DRPCLK_in;
wire DRPEN_in;
wire DRPWE_in;
wire ELPCALDVORWREN_in;
wire ELPCALPAORWREN_in;
wire EVODDPHICALDONE_in;
wire EVODDPHICALSTART_in;
wire EVODDPHIDRDEN_in;
wire EVODDPHIDWREN_in;
wire EVODDPHIXRDEN_in;
wire EVODDPHIXWREN_in;
wire EYESCANMODE_in;
wire EYESCANRESET_in;
wire EYESCANTRIGGER_in;
wire GTGREFCLK_in;
wire GTNORTHREFCLK0_in;
wire GTNORTHREFCLK1_in;
wire GTREFCLK0_in;
wire GTREFCLK1_in;
wire GTRESETSEL_in;
wire GTRXRESET_in;
wire GTSOUTHREFCLK0_in;
wire GTSOUTHREFCLK1_in;
wire GTTXRESET_in;
wire GTYRXN_in;
wire GTYRXP_in;
wire LPBKRXTXSEREN_in;
wire LPBKTXRXSEREN_in;
wire PCIEEQRXEQADAPTDONE_in;
wire PCIERSTIDLE_in;
wire PCIERSTTXSYNCSTART_in;
wire PCIEUSERRATEDONE_in;
wire PMASCANCLK0_in;
wire PMASCANCLK1_in;
wire PMASCANCLK2_in;
wire PMASCANCLK3_in;
wire PMASCANCLK4_in;
wire PMASCANCLK5_in;
wire PMASCANENB_in;
wire PMASCANMODEB_in;
wire PMASCANRSTEN_in;
wire QPLL0CLK_in;
wire QPLL0REFCLK_in;
wire QPLL1CLK_in;
wire QPLL1REFCLK_in;
wire RESETOVRD_in;
wire RSTCLKENTX_in;
wire RX8B10BEN_in;
wire RXBUFRESET_in;
wire RXCDRFREQRESET_in;
wire RXCDRHOLD_in;
wire RXCDROVRDEN_in;
wire RXCDRRESETRSV_in;
wire RXCDRRESET_in;
wire RXCHBONDEN_in;
wire RXCHBONDMASTER_in;
wire RXCHBONDSLAVE_in;
wire RXCKCALRESET_in;
wire RXCOMMADETEN_in;
wire RXDCCFORCESTART_in;
wire RXDFEAGCHOLD_in;
wire RXDFEAGCOVRDEN_in;
wire RXDFELFHOLD_in;
wire RXDFELFOVRDEN_in;
wire RXDFELPMRESET_in;
wire RXDFETAP10HOLD_in;
wire RXDFETAP10OVRDEN_in;
wire RXDFETAP11HOLD_in;
wire RXDFETAP11OVRDEN_in;
wire RXDFETAP12HOLD_in;
wire RXDFETAP12OVRDEN_in;
wire RXDFETAP13HOLD_in;
wire RXDFETAP13OVRDEN_in;
wire RXDFETAP14HOLD_in;
wire RXDFETAP14OVRDEN_in;
wire RXDFETAP15HOLD_in;
wire RXDFETAP15OVRDEN_in;
wire RXDFETAP2HOLD_in;
wire RXDFETAP2OVRDEN_in;
wire RXDFETAP3HOLD_in;
wire RXDFETAP3OVRDEN_in;
wire RXDFETAP4HOLD_in;
wire RXDFETAP4OVRDEN_in;
wire RXDFETAP5HOLD_in;
wire RXDFETAP5OVRDEN_in;
wire RXDFETAP6HOLD_in;
wire RXDFETAP6OVRDEN_in;
wire RXDFETAP7HOLD_in;
wire RXDFETAP7OVRDEN_in;
wire RXDFETAP8HOLD_in;
wire RXDFETAP8OVRDEN_in;
wire RXDFETAP9HOLD_in;
wire RXDFETAP9OVRDEN_in;
wire RXDFEUTHOLD_in;
wire RXDFEUTOVRDEN_in;
wire RXDFEVPHOLD_in;
wire RXDFEVPOVRDEN_in;
wire RXDFEVSEN_in;
wire RXDFEXYDEN_in;
wire RXDLYBYPASS_in;
wire RXDLYEN_in;
wire RXDLYOVRDEN_in;
wire RXDLYSRESET_in;
wire RXGEARBOXSLIP_in;
wire RXLATCLK_in;
wire RXLPMEN_in;
wire RXLPMGCHOLD_in;
wire RXLPMGCOVRDEN_in;
wire RXLPMHFHOLD_in;
wire RXLPMHFOVRDEN_in;
wire RXLPMLFHOLD_in;
wire RXLPMLFKLOVRDEN_in;
wire RXLPMOSHOLD_in;
wire RXLPMOSOVRDEN_in;
wire RXMCOMMAALIGNEN_in;
wire RXOOBRESET_in;
wire RXOSCALRESET_in;
wire RXOSHOLD_in;
wire RXOSINTEN_in;
wire RXOSINTHOLD_in;
wire RXOSINTOVRDEN_in;
wire RXOSINTSTROBE_in;
wire RXOSINTTESTOVRDEN_in;
wire RXOSOVRDEN_in;
wire RXPCOMMAALIGNEN_in;
wire RXPCSRESET_in;
wire RXPHALIGNEN_in;
wire RXPHALIGN_in;
wire RXPHDLYPD_in;
wire RXPHDLYRESET_in;
wire RXPHOVRDEN_in;
wire RXPMARESET_in;
wire RXPOLARITY_in;
wire RXPRBSCNTRESET_in;
wire RXPROGDIVRESET_in;
wire RXRATEMODE_in;
wire RXSLIDE_in;
wire RXSLIPOUTCLK_in;
wire RXSLIPPMA_in;
wire RXSYNCALLIN_in;
wire RXSYNCIN_in;
wire RXSYNCMODE_in;
wire RXUSERRDY_in;
wire RXUSRCLK2_in;
wire RXUSRCLK_in;
wire SARCCLK_in;
wire SCANCLK_in;
wire SCANENB_in;
wire SCANMODEB_in;
wire SIGVALIDCLK_in;
wire TSTCLK0_in;
wire TSTCLK1_in;
wire TSTPDOVRDB_in;
wire TX8B10BEN_in;
wire TXCOMINIT_in;
wire TXCOMSAS_in;
wire TXCOMWAKE_in;
wire TXDCCFORCESTART_in;
wire TXDCCRESET_in;
wire TXDEEMPH_in;
wire TXDETECTRX_in;
wire TXDIFFPD_in;
wire TXDLYBYPASS_in;
wire TXDLYEN_in;
wire TXDLYHOLD_in;
wire TXDLYOVRDEN_in;
wire TXDLYSRESET_in;
wire TXDLYUPDOWN_in;
wire TXELECIDLE_in;
wire TXELFORCESTART_in;
wire TXINHIBIT_in;
wire TXLATCLK_in;
wire TXPCSRESET_in;
wire TXPDELECIDLEMODE_in;
wire TXPHALIGNEN_in;
wire TXPHALIGN_in;
wire TXPHDLYPD_in;
wire TXPHDLYRESET_in;
wire TXPHDLYTSTCLK_in;
wire TXPHINIT_in;
wire TXPHOVRDEN_in;
wire TXPIPPMEN_in;
wire TXPIPPMOVRDEN_in;
wire TXPIPPMPD_in;
wire TXPIPPMSEL_in;
wire TXPISOPD_in;
wire TXPMARESET_in;
wire TXPOLARITY_in;
wire TXPRBSFORCEERR_in;
wire TXPROGDIVRESET_in;
wire TXRATEMODE_in;
wire TXSWING_in;
wire TXSYNCALLIN_in;
wire TXSYNCIN_in;
wire TXSYNCMODE_in;
wire TXUSERRDY_in;
wire TXUSRCLK2_in;
wire TXUSRCLK_in;
wire [11:0] PMASCANIN_in;
wire [127:0] TXDATA_in;
wire [15:0] DRPDI_in;
wire [15:0] GTRSVD_in;
wire [15:0] LOOPRSVD_in;
wire [15:0] PCSRSVDIN_in;
wire [15:0] TXCTRL0_in;
wire [15:0] TXCTRL1_in;
wire [18:0] SCANIN_in;
wire [19:0] TSTIN_in;
wire [1:0] RXELECIDLEMODE_in;
wire [1:0] RXMONITORSEL_in;
wire [1:0] RXPD_in;
wire [1:0] RXPLLCLKSEL_in;
wire [1:0] RXSYSCLKSEL_in;
wire [1:0] TXPD_in;
wire [1:0] TXPLLCLKSEL_in;
wire [1:0] TXSYSCLKSEL_in;
wire [2:0] CPLLREFCLKSEL_in;
wire [2:0] LOOPBACK_in;
wire [2:0] RXCHBONDLEVEL_in;
wire [2:0] RXOUTCLKSEL_in;
wire [2:0] RXRATE_in;
wire [2:0] TXBUFDIFFCTRL_in;
wire [2:0] TXMARGIN_in;
wire [2:0] TXOUTCLKSEL_in;
wire [2:0] TXRATE_in;
wire [3:0] RXOSINTCFG_in;
wire [3:0] RXPRBSSEL_in;
wire [3:0] TXPRBSSEL_in;
wire [4:0] PCSRSVDIN2_in;
wire [4:0] PMARSVDIN_in;
wire [4:0] RXCHBONDI_in;
wire [4:0] TSTPD_in;
wire [4:0] TXDIFFCTRL_in;
wire [4:0] TXPIPPMSTEPSIZE_in;
wire [4:0] TXPOSTCURSOR_in;
wire [4:0] TXPRECURSOR_in;
wire [5:0] TXHEADER_in;
wire [6:0] TXMAINCURSOR_in;
wire [6:0] TXSEQUENCE_in;
wire [7:0] TX8B10BBYPASS_in;
wire [7:0] TXCTRL2_in;
wire [7:0] TXDATAEXTENDRSVD_in;
wire [9:0] DRPADDR_in;
wire CDRSTEPDIR_delay;
wire CDRSTEPSQ_delay;
wire CDRSTEPSX_delay;
wire CFGRESET_delay;
wire CLKRSVD0_delay;
wire CLKRSVD1_delay;
wire CPLLLOCKDETCLK_delay;
wire CPLLLOCKEN_delay;
wire CPLLPD_delay;
wire CPLLRESET_delay;
wire DMONFIFORESET_delay;
wire DMONITORCLK_delay;
wire DRPCLK_delay;
wire DRPEN_delay;
wire DRPWE_delay;
wire ELPCALDVORWREN_delay;
wire ELPCALPAORWREN_delay;
wire EVODDPHICALDONE_delay;
wire EVODDPHICALSTART_delay;
wire EVODDPHIDRDEN_delay;
wire EVODDPHIDWREN_delay;
wire EVODDPHIXRDEN_delay;
wire EVODDPHIXWREN_delay;
wire EYESCANMODE_delay;
wire EYESCANRESET_delay;
wire EYESCANTRIGGER_delay;
wire GTGREFCLK_delay;
wire GTNORTHREFCLK0_delay;
wire GTNORTHREFCLK1_delay;
wire GTREFCLK0_delay;
wire GTREFCLK1_delay;
wire GTRESETSEL_delay;
wire GTRXRESET_delay;
wire GTSOUTHREFCLK0_delay;
wire GTSOUTHREFCLK1_delay;
wire GTTXRESET_delay;
wire GTYRXN_delay;
wire GTYRXP_delay;
wire LPBKRXTXSEREN_delay;
wire LPBKTXRXSEREN_delay;
wire PCIEEQRXEQADAPTDONE_delay;
wire PCIERSTIDLE_delay;
wire PCIERSTTXSYNCSTART_delay;
wire PCIEUSERRATEDONE_delay;
wire QPLL0CLK_delay;
wire QPLL0REFCLK_delay;
wire QPLL1CLK_delay;
wire QPLL1REFCLK_delay;
wire RESETOVRD_delay;
wire RSTCLKENTX_delay;
wire RX8B10BEN_delay;
wire RXBUFRESET_delay;
wire RXCDRFREQRESET_delay;
wire RXCDRHOLD_delay;
wire RXCDROVRDEN_delay;
wire RXCDRRESETRSV_delay;
wire RXCDRRESET_delay;
wire RXCHBONDEN_delay;
wire RXCHBONDMASTER_delay;
wire RXCHBONDSLAVE_delay;
wire RXCKCALRESET_delay;
wire RXCOMMADETEN_delay;
wire RXDCCFORCESTART_delay;
wire RXDFEAGCHOLD_delay;
wire RXDFEAGCOVRDEN_delay;
wire RXDFELFHOLD_delay;
wire RXDFELFOVRDEN_delay;
wire RXDFELPMRESET_delay;
wire RXDFETAP10HOLD_delay;
wire RXDFETAP10OVRDEN_delay;
wire RXDFETAP11HOLD_delay;
wire RXDFETAP11OVRDEN_delay;
wire RXDFETAP12HOLD_delay;
wire RXDFETAP12OVRDEN_delay;
wire RXDFETAP13HOLD_delay;
wire RXDFETAP13OVRDEN_delay;
wire RXDFETAP14HOLD_delay;
wire RXDFETAP14OVRDEN_delay;
wire RXDFETAP15HOLD_delay;
wire RXDFETAP15OVRDEN_delay;
wire RXDFETAP2HOLD_delay;
wire RXDFETAP2OVRDEN_delay;
wire RXDFETAP3HOLD_delay;
wire RXDFETAP3OVRDEN_delay;
wire RXDFETAP4HOLD_delay;
wire RXDFETAP4OVRDEN_delay;
wire RXDFETAP5HOLD_delay;
wire RXDFETAP5OVRDEN_delay;
wire RXDFETAP6HOLD_delay;
wire RXDFETAP6OVRDEN_delay;
wire RXDFETAP7HOLD_delay;
wire RXDFETAP7OVRDEN_delay;
wire RXDFETAP8HOLD_delay;
wire RXDFETAP8OVRDEN_delay;
wire RXDFETAP9HOLD_delay;
wire RXDFETAP9OVRDEN_delay;
wire RXDFEUTHOLD_delay;
wire RXDFEUTOVRDEN_delay;
wire RXDFEVPHOLD_delay;
wire RXDFEVPOVRDEN_delay;
wire RXDFEVSEN_delay;
wire RXDFEXYDEN_delay;
wire RXDLYBYPASS_delay;
wire RXDLYEN_delay;
wire RXDLYOVRDEN_delay;
wire RXDLYSRESET_delay;
wire RXGEARBOXSLIP_delay;
wire RXLATCLK_delay;
wire RXLPMEN_delay;
wire RXLPMGCHOLD_delay;
wire RXLPMGCOVRDEN_delay;
wire RXLPMHFHOLD_delay;
wire RXLPMHFOVRDEN_delay;
wire RXLPMLFHOLD_delay;
wire RXLPMLFKLOVRDEN_delay;
wire RXLPMOSHOLD_delay;
wire RXLPMOSOVRDEN_delay;
wire RXMCOMMAALIGNEN_delay;
wire RXOOBRESET_delay;
wire RXOSCALRESET_delay;
wire RXOSHOLD_delay;
wire RXOSINTEN_delay;
wire RXOSINTHOLD_delay;
wire RXOSINTOVRDEN_delay;
wire RXOSINTSTROBE_delay;
wire RXOSINTTESTOVRDEN_delay;
wire RXOSOVRDEN_delay;
wire RXPCOMMAALIGNEN_delay;
wire RXPCSRESET_delay;
wire RXPHALIGNEN_delay;
wire RXPHALIGN_delay;
wire RXPHDLYPD_delay;
wire RXPHDLYRESET_delay;
wire RXPHOVRDEN_delay;
wire RXPMARESET_delay;
wire RXPOLARITY_delay;
wire RXPRBSCNTRESET_delay;
wire RXPROGDIVRESET_delay;
wire RXRATEMODE_delay;
wire RXSLIDE_delay;
wire RXSLIPOUTCLK_delay;
wire RXSLIPPMA_delay;
wire RXSYNCALLIN_delay;
wire RXSYNCIN_delay;
wire RXSYNCMODE_delay;
wire RXUSERRDY_delay;
wire RXUSRCLK2_delay;
wire RXUSRCLK_delay;
wire SIGVALIDCLK_delay;
wire TX8B10BEN_delay;
wire TXCOMINIT_delay;
wire TXCOMSAS_delay;
wire TXCOMWAKE_delay;
wire TXDCCFORCESTART_delay;
wire TXDCCRESET_delay;
wire TXDEEMPH_delay;
wire TXDETECTRX_delay;
wire TXDIFFPD_delay;
wire TXDLYBYPASS_delay;
wire TXDLYEN_delay;
wire TXDLYHOLD_delay;
wire TXDLYOVRDEN_delay;
wire TXDLYSRESET_delay;
wire TXDLYUPDOWN_delay;
wire TXELECIDLE_delay;
wire TXELFORCESTART_delay;
wire TXINHIBIT_delay;
wire TXLATCLK_delay;
wire TXPCSRESET_delay;
wire TXPDELECIDLEMODE_delay;
wire TXPHALIGNEN_delay;
wire TXPHALIGN_delay;
wire TXPHDLYPD_delay;
wire TXPHDLYRESET_delay;
wire TXPHDLYTSTCLK_delay;
wire TXPHINIT_delay;
wire TXPHOVRDEN_delay;
wire TXPIPPMEN_delay;
wire TXPIPPMOVRDEN_delay;
wire TXPIPPMPD_delay;
wire TXPIPPMSEL_delay;
wire TXPISOPD_delay;
wire TXPMARESET_delay;
wire TXPOLARITY_delay;
wire TXPRBSFORCEERR_delay;
wire TXPROGDIVRESET_delay;
wire TXRATEMODE_delay;
wire TXSWING_delay;
wire TXSYNCALLIN_delay;
wire TXSYNCIN_delay;
wire TXSYNCMODE_delay;
wire TXUSERRDY_delay;
wire TXUSRCLK2_delay;
wire TXUSRCLK_delay;
wire [127:0] TXDATA_delay;
wire [15:0] DRPDI_delay;
wire [15:0] GTRSVD_delay;
wire [15:0] LOOPRSVD_delay;
wire [15:0] PCSRSVDIN_delay;
wire [15:0] TXCTRL0_delay;
wire [15:0] TXCTRL1_delay;
wire [19:0] TSTIN_delay;
wire [1:0] RXELECIDLEMODE_delay;
wire [1:0] RXMONITORSEL_delay;
wire [1:0] RXPD_delay;
wire [1:0] RXPLLCLKSEL_delay;
wire [1:0] RXSYSCLKSEL_delay;
wire [1:0] TXPD_delay;
wire [1:0] TXPLLCLKSEL_delay;
wire [1:0] TXSYSCLKSEL_delay;
wire [2:0] CPLLREFCLKSEL_delay;
wire [2:0] LOOPBACK_delay;
wire [2:0] RXCHBONDLEVEL_delay;
wire [2:0] RXOUTCLKSEL_delay;
wire [2:0] RXRATE_delay;
wire [2:0] TXBUFDIFFCTRL_delay;
wire [2:0] TXMARGIN_delay;
wire [2:0] TXOUTCLKSEL_delay;
wire [2:0] TXRATE_delay;
wire [3:0] RXOSINTCFG_delay;
wire [3:0] RXPRBSSEL_delay;
wire [3:0] TXPRBSSEL_delay;
wire [4:0] PCSRSVDIN2_delay;
wire [4:0] PMARSVDIN_delay;
wire [4:0] RXCHBONDI_delay;
wire [4:0] TXDIFFCTRL_delay;
wire [4:0] TXPIPPMSTEPSIZE_delay;
wire [4:0] TXPOSTCURSOR_delay;
wire [4:0] TXPRECURSOR_delay;
wire [5:0] TXHEADER_delay;
wire [6:0] TXMAINCURSOR_delay;
wire [6:0] TXSEQUENCE_delay;
wire [7:0] TX8B10BBYPASS_delay;
wire [7:0] TXCTRL2_delay;
wire [7:0] TXDATAEXTENDRSVD_delay;
wire [9:0] DRPADDR_delay;
assign #(out_delay) BUFGTCE = BUFGTCE_delay;
assign #(out_delay) BUFGTCEMASK = BUFGTCEMASK_delay;
assign #(out_delay) BUFGTDIV = BUFGTDIV_delay;
assign #(out_delay) BUFGTRESET = BUFGTRESET_delay;
assign #(out_delay) BUFGTRSTMASK = BUFGTRSTMASK_delay;
assign #(out_delay) CPLLFBCLKLOST = CPLLFBCLKLOST_delay;
assign #(out_delay) CPLLLOCK = CPLLLOCK_delay;
assign #(out_delay) CPLLREFCLKLOST = CPLLREFCLKLOST_delay;
assign #(out_delay) DMONITOROUT = DMONITOROUT_delay;
assign #(out_delay) DRPDO = DRPDO_delay;
assign #(out_delay) DRPRDY = DRPRDY_delay;
assign #(out_delay) EYESCANDATAERROR = EYESCANDATAERROR_delay;
assign #(out_delay) GTPOWERGOOD = GTPOWERGOOD_delay;
assign #(out_delay) GTREFCLKMONITOR = GTREFCLKMONITOR_delay;
assign #(out_delay) GTYTXN = GTYTXN_delay;
assign #(out_delay) GTYTXP = GTYTXP_delay;
assign #(out_delay) PCIERATEGEN3 = PCIERATEGEN3_delay;
assign #(out_delay) PCIERATEIDLE = PCIERATEIDLE_delay;
assign #(out_delay) PCIERATEQPLLPD = PCIERATEQPLLPD_delay;
assign #(out_delay) PCIERATEQPLLRESET = PCIERATEQPLLRESET_delay;
assign #(out_delay) PCIESYNCTXSYNCDONE = PCIESYNCTXSYNCDONE_delay;
assign #(out_delay) PCIEUSERGEN3RDY = PCIEUSERGEN3RDY_delay;
assign #(out_delay) PCIEUSERPHYSTATUSRST = PCIEUSERPHYSTATUSRST_delay;
assign #(out_delay) PCIEUSERRATESTART = PCIEUSERRATESTART_delay;
assign #(out_delay) PCSRSVDOUT = PCSRSVDOUT_delay;
assign #(out_delay) PHYSTATUS = PHYSTATUS_delay;
assign #(out_delay) PINRSRVDAS = PINRSRVDAS_delay;
assign #(out_delay) RESETEXCEPTION = RESETEXCEPTION_delay;
assign #(out_delay) RXBUFSTATUS = RXBUFSTATUS_delay;
assign #(out_delay) RXBYTEISALIGNED = RXBYTEISALIGNED_delay;
assign #(out_delay) RXBYTEREALIGN = RXBYTEREALIGN_delay;
assign #(out_delay) RXCDRLOCK = RXCDRLOCK_delay;
assign #(out_delay) RXCDRPHDONE = RXCDRPHDONE_delay;
assign #(out_delay) RXCHANBONDSEQ = RXCHANBONDSEQ_delay;
assign #(out_delay) RXCHANISALIGNED = RXCHANISALIGNED_delay;
assign #(out_delay) RXCHANREALIGN = RXCHANREALIGN_delay;
assign #(out_delay) RXCHBONDO = RXCHBONDO_delay;
assign #(out_delay) RXCKCALDONE = RXCKCALDONE_delay;
assign #(out_delay) RXCLKCORCNT = RXCLKCORCNT_delay;
assign #(out_delay) RXCOMINITDET = RXCOMINITDET_delay;
assign #(out_delay) RXCOMMADET = RXCOMMADET_delay;
assign #(out_delay) RXCOMSASDET = RXCOMSASDET_delay;
assign #(out_delay) RXCOMWAKEDET = RXCOMWAKEDET_delay;
assign #(out_delay) RXCTRL0 = RXCTRL0_delay;
assign #(out_delay) RXCTRL1 = RXCTRL1_delay;
assign #(out_delay) RXCTRL2 = RXCTRL2_delay;
assign #(out_delay) RXCTRL3 = RXCTRL3_delay;
assign #(out_delay) RXDATA = RXDATA_delay;
assign #(out_delay) RXDATAEXTENDRSVD = RXDATAEXTENDRSVD_delay;
assign #(out_delay) RXDATAVALID = RXDATAVALID_delay;
assign #(out_delay) RXDLYSRESETDONE = RXDLYSRESETDONE_delay;
assign #(out_delay) RXELECIDLE = RXELECIDLE_delay;
assign #(out_delay) RXHEADER = RXHEADER_delay;
assign #(out_delay) RXHEADERVALID = RXHEADERVALID_delay;
assign #(out_delay) RXMONITOROUT = RXMONITOROUT_delay;
assign #(out_delay) RXOSINTDONE = RXOSINTDONE_delay;
assign #(out_delay) RXOSINTSTARTED = RXOSINTSTARTED_delay;
assign #(out_delay) RXOSINTSTROBEDONE = RXOSINTSTROBEDONE_delay;
assign #(out_delay) RXOSINTSTROBESTARTED = RXOSINTSTROBESTARTED_delay;
assign #(out_delay) RXOUTCLK = RXOUTCLK_delay;
assign #(out_delay) RXOUTCLKFABRIC = RXOUTCLKFABRIC_delay;
assign #(out_delay) RXOUTCLKPCS = RXOUTCLKPCS_delay;
assign #(out_delay) RXPHALIGNDONE = RXPHALIGNDONE_delay;
assign #(out_delay) RXPHALIGNERR = RXPHALIGNERR_delay;
assign #(out_delay) RXPMARESETDONE = RXPMARESETDONE_delay;
assign #(out_delay) RXPRBSERR = RXPRBSERR_delay;
assign #(out_delay) RXPRBSLOCKED = RXPRBSLOCKED_delay;
assign #(out_delay) RXPRGDIVRESETDONE = RXPRGDIVRESETDONE_delay;
assign #(out_delay) RXRATEDONE = RXRATEDONE_delay;
assign #(out_delay) RXRECCLKOUT = RXRECCLKOUT_delay;
assign #(out_delay) RXRESETDONE = RXRESETDONE_delay;
assign #(out_delay) RXSLIDERDY = RXSLIDERDY_delay;
assign #(out_delay) RXSLIPDONE = RXSLIPDONE_delay;
assign #(out_delay) RXSLIPOUTCLKRDY = RXSLIPOUTCLKRDY_delay;
assign #(out_delay) RXSLIPPMARDY = RXSLIPPMARDY_delay;
assign #(out_delay) RXSTARTOFSEQ = RXSTARTOFSEQ_delay;
assign #(out_delay) RXSTATUS = RXSTATUS_delay;
assign #(out_delay) RXSYNCDONE = RXSYNCDONE_delay;
assign #(out_delay) RXSYNCOUT = RXSYNCOUT_delay;
assign #(out_delay) RXVALID = RXVALID_delay;
assign #(out_delay) TXBUFSTATUS = TXBUFSTATUS_delay;
assign #(out_delay) TXCOMFINISH = TXCOMFINISH_delay;
assign #(out_delay) TXDCCDONE = TXDCCDONE_delay;
assign #(out_delay) TXDLYSRESETDONE = TXDLYSRESETDONE_delay;
assign #(out_delay) TXOUTCLK = TXOUTCLK_delay;
assign #(out_delay) TXOUTCLKFABRIC = TXOUTCLKFABRIC_delay;
assign #(out_delay) TXOUTCLKPCS = TXOUTCLKPCS_delay;
assign #(out_delay) TXPHALIGNDONE = TXPHALIGNDONE_delay;
assign #(out_delay) TXPHINITDONE = TXPHINITDONE_delay;
assign #(out_delay) TXPMARESETDONE = TXPMARESETDONE_delay;
assign #(out_delay) TXPRGDIVRESETDONE = TXPRGDIVRESETDONE_delay;
assign #(out_delay) TXRATEDONE = TXRATEDONE_delay;
assign #(out_delay) TXRESETDONE = TXRESETDONE_delay;
assign #(out_delay) TXSYNCDONE = TXSYNCDONE_delay;
assign #(out_delay) TXSYNCOUT = TXSYNCOUT_delay;
`ifndef XIL_TIMING // inputs with timing checks
assign #(inclk_delay) DRPCLK_delay = DRPCLK;
assign #(inclk_delay) RXUSRCLK2_delay = RXUSRCLK2;
assign #(inclk_delay) RXUSRCLK_delay = RXUSRCLK;
assign #(inclk_delay) TXUSRCLK2_delay = TXUSRCLK2;
assign #(in_delay) DRPEN_delay = DRPEN;
assign #(in_delay) DRPWE_delay = DRPWE;
assign #(in_delay) RX8B10BEN_delay = RX8B10BEN;
assign #(in_delay) RXCHBONDEN_delay = RXCHBONDEN;
assign #(in_delay) RXCHBONDMASTER_delay = RXCHBONDMASTER;
assign #(in_delay) RXCHBONDSLAVE_delay = RXCHBONDSLAVE;
assign #(in_delay) RXCOMMADETEN_delay = RXCOMMADETEN;
assign #(in_delay) RXGEARBOXSLIP_delay = RXGEARBOXSLIP;
assign #(in_delay) RXMCOMMAALIGNEN_delay = RXMCOMMAALIGNEN;
assign #(in_delay) RXPCOMMAALIGNEN_delay = RXPCOMMAALIGNEN;
assign #(in_delay) RXPOLARITY_delay = RXPOLARITY;
assign #(in_delay) RXSLIDE_delay = RXSLIDE;
assign #(in_delay) RXSLIPOUTCLK_delay = RXSLIPOUTCLK;
assign #(in_delay) RXSLIPPMA_delay = RXSLIPPMA;
assign #(in_delay) TX8B10BEN_delay = TX8B10BEN;
assign #(in_delay) TXCOMINIT_delay = TXCOMINIT;
assign #(in_delay) TXCOMSAS_delay = TXCOMSAS;
assign #(in_delay) TXCOMWAKE_delay = TXCOMWAKE;
assign #(in_delay) TXDETECTRX_delay = TXDETECTRX;
assign #(in_delay) TXELECIDLE_delay = TXELECIDLE;
assign #(in_delay) TXINHIBIT_delay = TXINHIBIT;
assign #(in_delay) TXPOLARITY_delay = TXPOLARITY;
assign #(in_delay) TXPRBSFORCEERR_delay = TXPRBSFORCEERR;
`endif // `ifndef XIL_TIMING
// inputs with no timing checks
assign #(inclk_delay) CLKRSVD0_delay = CLKRSVD0;
assign #(inclk_delay) CLKRSVD1_delay = CLKRSVD1;
assign #(inclk_delay) CPLLLOCKDETCLK_delay = CPLLLOCKDETCLK;
assign #(inclk_delay) DMONITORCLK_delay = DMONITORCLK;
assign #(inclk_delay) GTGREFCLK_delay = GTGREFCLK;
assign #(inclk_delay) RXLATCLK_delay = RXLATCLK;
assign #(inclk_delay) SIGVALIDCLK_delay = SIGVALIDCLK;
assign #(inclk_delay) TXLATCLK_delay = TXLATCLK;
assign #(inclk_delay) TXPHDLYTSTCLK_delay = TXPHDLYTSTCLK;
assign #(inclk_delay) TXUSRCLK_delay = TXUSRCLK;
assign #(in_delay) CDRSTEPDIR_delay = CDRSTEPDIR;
assign #(in_delay) CDRSTEPSQ_delay = CDRSTEPSQ;
assign #(in_delay) CDRSTEPSX_delay = CDRSTEPSX;
assign #(in_delay) CFGRESET_delay = CFGRESET;
assign #(in_delay) CPLLLOCKEN_delay = CPLLLOCKEN;
assign #(in_delay) CPLLPD_delay = CPLLPD;
assign #(in_delay) CPLLREFCLKSEL_delay = CPLLREFCLKSEL;
assign #(in_delay) CPLLRESET_delay = CPLLRESET;
assign #(in_delay) DMONFIFORESET_delay = DMONFIFORESET;
assign #(in_delay) DRPADDR_delay = DRPADDR;
assign #(in_delay) DRPDI_delay = DRPDI;
assign #(in_delay) ELPCALDVORWREN_delay = ELPCALDVORWREN;
assign #(in_delay) ELPCALPAORWREN_delay = ELPCALPAORWREN;
assign #(in_delay) EVODDPHICALDONE_delay = EVODDPHICALDONE;
assign #(in_delay) EVODDPHICALSTART_delay = EVODDPHICALSTART;
assign #(in_delay) EVODDPHIDRDEN_delay = EVODDPHIDRDEN;
assign #(in_delay) EVODDPHIDWREN_delay = EVODDPHIDWREN;
assign #(in_delay) EVODDPHIXRDEN_delay = EVODDPHIXRDEN;
assign #(in_delay) EVODDPHIXWREN_delay = EVODDPHIXWREN;
assign #(in_delay) EYESCANMODE_delay = EYESCANMODE;
assign #(in_delay) EYESCANRESET_delay = EYESCANRESET;
assign #(in_delay) EYESCANTRIGGER_delay = EYESCANTRIGGER;
assign #(in_delay) GTNORTHREFCLK0_delay = GTNORTHREFCLK0;
assign #(in_delay) GTNORTHREFCLK1_delay = GTNORTHREFCLK1;
assign #(in_delay) GTREFCLK0_delay = GTREFCLK0;
assign #(in_delay) GTREFCLK1_delay = GTREFCLK1;
assign #(in_delay) GTRESETSEL_delay = GTRESETSEL;
assign #(in_delay) GTRSVD_delay = GTRSVD;
assign #(in_delay) GTRXRESET_delay = GTRXRESET;
assign #(in_delay) GTSOUTHREFCLK0_delay = GTSOUTHREFCLK0;
assign #(in_delay) GTSOUTHREFCLK1_delay = GTSOUTHREFCLK1;
assign #(in_delay) GTTXRESET_delay = GTTXRESET;
assign #(in_delay) GTYRXN_delay = GTYRXN;
assign #(in_delay) GTYRXP_delay = GTYRXP;
assign #(in_delay) LOOPBACK_delay = LOOPBACK;
assign #(in_delay) LOOPRSVD_delay = LOOPRSVD;
assign #(in_delay) LPBKRXTXSEREN_delay = LPBKRXTXSEREN;
assign #(in_delay) LPBKTXRXSEREN_delay = LPBKTXRXSEREN;
assign #(in_delay) PCIEEQRXEQADAPTDONE_delay = PCIEEQRXEQADAPTDONE;
assign #(in_delay) PCIERSTIDLE_delay = PCIERSTIDLE;
assign #(in_delay) PCIERSTTXSYNCSTART_delay = PCIERSTTXSYNCSTART;
assign #(in_delay) PCIEUSERRATEDONE_delay = PCIEUSERRATEDONE;
assign #(in_delay) PCSRSVDIN2_delay = PCSRSVDIN2;
assign #(in_delay) PCSRSVDIN_delay = PCSRSVDIN;
assign #(in_delay) PMARSVDIN_delay = PMARSVDIN;
assign #(in_delay) QPLL0CLK_delay = QPLL0CLK;
assign #(in_delay) QPLL0REFCLK_delay = QPLL0REFCLK;
assign #(in_delay) QPLL1CLK_delay = QPLL1CLK;
assign #(in_delay) QPLL1REFCLK_delay = QPLL1REFCLK;
assign #(in_delay) RESETOVRD_delay = RESETOVRD;
assign #(in_delay) RSTCLKENTX_delay = RSTCLKENTX;
assign #(in_delay) RXBUFRESET_delay = RXBUFRESET;
assign #(in_delay) RXCDRFREQRESET_delay = RXCDRFREQRESET;
assign #(in_delay) RXCDRHOLD_delay = RXCDRHOLD;
assign #(in_delay) RXCDROVRDEN_delay = RXCDROVRDEN;
assign #(in_delay) RXCDRRESETRSV_delay = RXCDRRESETRSV;
assign #(in_delay) RXCDRRESET_delay = RXCDRRESET;
assign #(in_delay) RXCHBONDI_delay = RXCHBONDI;
assign #(in_delay) RXCHBONDLEVEL_delay = RXCHBONDLEVEL;
assign #(in_delay) RXCKCALRESET_delay = RXCKCALRESET;
assign #(in_delay) RXDCCFORCESTART_delay = RXDCCFORCESTART;
assign #(in_delay) RXDFEAGCHOLD_delay = RXDFEAGCHOLD;
assign #(in_delay) RXDFEAGCOVRDEN_delay = RXDFEAGCOVRDEN;
assign #(in_delay) RXDFELFHOLD_delay = RXDFELFHOLD;
assign #(in_delay) RXDFELFOVRDEN_delay = RXDFELFOVRDEN;
assign #(in_delay) RXDFELPMRESET_delay = RXDFELPMRESET;
assign #(in_delay) RXDFETAP10HOLD_delay = RXDFETAP10HOLD;
assign #(in_delay) RXDFETAP10OVRDEN_delay = RXDFETAP10OVRDEN;
assign #(in_delay) RXDFETAP11HOLD_delay = RXDFETAP11HOLD;
assign #(in_delay) RXDFETAP11OVRDEN_delay = RXDFETAP11OVRDEN;
assign #(in_delay) RXDFETAP12HOLD_delay = RXDFETAP12HOLD;
assign #(in_delay) RXDFETAP12OVRDEN_delay = RXDFETAP12OVRDEN;
assign #(in_delay) RXDFETAP13HOLD_delay = RXDFETAP13HOLD;
assign #(in_delay) RXDFETAP13OVRDEN_delay = RXDFETAP13OVRDEN;
assign #(in_delay) RXDFETAP14HOLD_delay = RXDFETAP14HOLD;
assign #(in_delay) RXDFETAP14OVRDEN_delay = RXDFETAP14OVRDEN;
assign #(in_delay) RXDFETAP15HOLD_delay = RXDFETAP15HOLD;
assign #(in_delay) RXDFETAP15OVRDEN_delay = RXDFETAP15OVRDEN;
assign #(in_delay) RXDFETAP2HOLD_delay = RXDFETAP2HOLD;
assign #(in_delay) RXDFETAP2OVRDEN_delay = RXDFETAP2OVRDEN;
assign #(in_delay) RXDFETAP3HOLD_delay = RXDFETAP3HOLD;
assign #(in_delay) RXDFETAP3OVRDEN_delay = RXDFETAP3OVRDEN;
assign #(in_delay) RXDFETAP4HOLD_delay = RXDFETAP4HOLD;
assign #(in_delay) RXDFETAP4OVRDEN_delay = RXDFETAP4OVRDEN;
assign #(in_delay) RXDFETAP5HOLD_delay = RXDFETAP5HOLD;
assign #(in_delay) RXDFETAP5OVRDEN_delay = RXDFETAP5OVRDEN;
assign #(in_delay) RXDFETAP6HOLD_delay = RXDFETAP6HOLD;
assign #(in_delay) RXDFETAP6OVRDEN_delay = RXDFETAP6OVRDEN;
assign #(in_delay) RXDFETAP7HOLD_delay = RXDFETAP7HOLD;
assign #(in_delay) RXDFETAP7OVRDEN_delay = RXDFETAP7OVRDEN;
assign #(in_delay) RXDFETAP8HOLD_delay = RXDFETAP8HOLD;
assign #(in_delay) RXDFETAP8OVRDEN_delay = RXDFETAP8OVRDEN;
assign #(in_delay) RXDFETAP9HOLD_delay = RXDFETAP9HOLD;
assign #(in_delay) RXDFETAP9OVRDEN_delay = RXDFETAP9OVRDEN;
assign #(in_delay) RXDFEUTHOLD_delay = RXDFEUTHOLD;
assign #(in_delay) RXDFEUTOVRDEN_delay = RXDFEUTOVRDEN;
assign #(in_delay) RXDFEVPHOLD_delay = RXDFEVPHOLD;
assign #(in_delay) RXDFEVPOVRDEN_delay = RXDFEVPOVRDEN;
assign #(in_delay) RXDFEVSEN_delay = RXDFEVSEN;
assign #(in_delay) RXDFEXYDEN_delay = RXDFEXYDEN;
assign #(in_delay) RXDLYBYPASS_delay = RXDLYBYPASS;
assign #(in_delay) RXDLYEN_delay = RXDLYEN;
assign #(in_delay) RXDLYOVRDEN_delay = RXDLYOVRDEN;
assign #(in_delay) RXDLYSRESET_delay = RXDLYSRESET;
assign #(in_delay) RXELECIDLEMODE_delay = RXELECIDLEMODE;
assign #(in_delay) RXLPMEN_delay = RXLPMEN;
assign #(in_delay) RXLPMGCHOLD_delay = RXLPMGCHOLD;
assign #(in_delay) RXLPMGCOVRDEN_delay = RXLPMGCOVRDEN;
assign #(in_delay) RXLPMHFHOLD_delay = RXLPMHFHOLD;
assign #(in_delay) RXLPMHFOVRDEN_delay = RXLPMHFOVRDEN;
assign #(in_delay) RXLPMLFHOLD_delay = RXLPMLFHOLD;
assign #(in_delay) RXLPMLFKLOVRDEN_delay = RXLPMLFKLOVRDEN;
assign #(in_delay) RXLPMOSHOLD_delay = RXLPMOSHOLD;
assign #(in_delay) RXLPMOSOVRDEN_delay = RXLPMOSOVRDEN;
assign #(in_delay) RXMONITORSEL_delay = RXMONITORSEL;
assign #(in_delay) RXOOBRESET_delay = RXOOBRESET;
assign #(in_delay) RXOSCALRESET_delay = RXOSCALRESET;
assign #(in_delay) RXOSHOLD_delay = RXOSHOLD;
assign #(in_delay) RXOSINTCFG_delay = RXOSINTCFG;
assign #(in_delay) RXOSINTEN_delay = RXOSINTEN;
assign #(in_delay) RXOSINTHOLD_delay = RXOSINTHOLD;
assign #(in_delay) RXOSINTOVRDEN_delay = RXOSINTOVRDEN;
assign #(in_delay) RXOSINTSTROBE_delay = RXOSINTSTROBE;
assign #(in_delay) RXOSINTTESTOVRDEN_delay = RXOSINTTESTOVRDEN;
assign #(in_delay) RXOSOVRDEN_delay = RXOSOVRDEN;
assign #(in_delay) RXOUTCLKSEL_delay = RXOUTCLKSEL;
assign #(in_delay) RXPCSRESET_delay = RXPCSRESET;
assign #(in_delay) RXPD_delay = RXPD;
assign #(in_delay) RXPHALIGNEN_delay = RXPHALIGNEN;
assign #(in_delay) RXPHALIGN_delay = RXPHALIGN;
assign #(in_delay) RXPHDLYPD_delay = RXPHDLYPD;
assign #(in_delay) RXPHDLYRESET_delay = RXPHDLYRESET;
assign #(in_delay) RXPHOVRDEN_delay = RXPHOVRDEN;
assign #(in_delay) RXPLLCLKSEL_delay = RXPLLCLKSEL;
assign #(in_delay) RXPMARESET_delay = RXPMARESET;
assign #(in_delay) RXPRBSCNTRESET_delay = RXPRBSCNTRESET;
assign #(in_delay) RXPRBSSEL_delay = RXPRBSSEL;
assign #(in_delay) RXPROGDIVRESET_delay = RXPROGDIVRESET;
assign #(in_delay) RXRATEMODE_delay = RXRATEMODE;
assign #(in_delay) RXRATE_delay = RXRATE;
assign #(in_delay) RXSYNCALLIN_delay = RXSYNCALLIN;
assign #(in_delay) RXSYNCIN_delay = RXSYNCIN;
assign #(in_delay) RXSYNCMODE_delay = RXSYNCMODE;
assign #(in_delay) RXSYSCLKSEL_delay = RXSYSCLKSEL;
assign #(in_delay) RXUSERRDY_delay = RXUSERRDY;
assign #(in_delay) TSTIN_delay = TSTIN;
assign #(in_delay) TX8B10BBYPASS_delay = TX8B10BBYPASS;
assign #(in_delay) TXBUFDIFFCTRL_delay = TXBUFDIFFCTRL;
assign #(in_delay) TXCTRL0_delay = TXCTRL0;
assign #(in_delay) TXCTRL1_delay = TXCTRL1;
assign #(in_delay) TXCTRL2_delay = TXCTRL2;
assign #(in_delay) TXDATAEXTENDRSVD_delay = TXDATAEXTENDRSVD;
assign #(in_delay) TXDATA_delay = TXDATA;
assign #(in_delay) TXDCCFORCESTART_delay = TXDCCFORCESTART;
assign #(in_delay) TXDCCRESET_delay = TXDCCRESET;
assign #(in_delay) TXDEEMPH_delay = TXDEEMPH;
assign #(in_delay) TXDIFFCTRL_delay = TXDIFFCTRL;
assign #(in_delay) TXDIFFPD_delay = TXDIFFPD;
assign #(in_delay) TXDLYBYPASS_delay = TXDLYBYPASS;
assign #(in_delay) TXDLYEN_delay = TXDLYEN;
assign #(in_delay) TXDLYHOLD_delay = TXDLYHOLD;
assign #(in_delay) TXDLYOVRDEN_delay = TXDLYOVRDEN;
assign #(in_delay) TXDLYSRESET_delay = TXDLYSRESET;
assign #(in_delay) TXDLYUPDOWN_delay = TXDLYUPDOWN;
assign #(in_delay) TXELFORCESTART_delay = TXELFORCESTART;
assign #(in_delay) TXHEADER_delay = TXHEADER;
assign #(in_delay) TXMAINCURSOR_delay = TXMAINCURSOR;
assign #(in_delay) TXMARGIN_delay = TXMARGIN;
assign #(in_delay) TXOUTCLKSEL_delay = TXOUTCLKSEL;
assign #(in_delay) TXPCSRESET_delay = TXPCSRESET;
assign #(in_delay) TXPDELECIDLEMODE_delay = TXPDELECIDLEMODE;
assign #(in_delay) TXPD_delay = TXPD;
assign #(in_delay) TXPHALIGNEN_delay = TXPHALIGNEN;
assign #(in_delay) TXPHALIGN_delay = TXPHALIGN;
assign #(in_delay) TXPHDLYPD_delay = TXPHDLYPD;
assign #(in_delay) TXPHDLYRESET_delay = TXPHDLYRESET;
assign #(in_delay) TXPHINIT_delay = TXPHINIT;
assign #(in_delay) TXPHOVRDEN_delay = TXPHOVRDEN;
assign #(in_delay) TXPIPPMEN_delay = TXPIPPMEN;
assign #(in_delay) TXPIPPMOVRDEN_delay = TXPIPPMOVRDEN;
assign #(in_delay) TXPIPPMPD_delay = TXPIPPMPD;
assign #(in_delay) TXPIPPMSEL_delay = TXPIPPMSEL;
assign #(in_delay) TXPIPPMSTEPSIZE_delay = TXPIPPMSTEPSIZE;
assign #(in_delay) TXPISOPD_delay = TXPISOPD;
assign #(in_delay) TXPLLCLKSEL_delay = TXPLLCLKSEL;
assign #(in_delay) TXPMARESET_delay = TXPMARESET;
assign #(in_delay) TXPOSTCURSOR_delay = TXPOSTCURSOR;
assign #(in_delay) TXPRBSSEL_delay = TXPRBSSEL;
assign #(in_delay) TXPRECURSOR_delay = TXPRECURSOR;
assign #(in_delay) TXPROGDIVRESET_delay = TXPROGDIVRESET;
assign #(in_delay) TXRATEMODE_delay = TXRATEMODE;
assign #(in_delay) TXRATE_delay = TXRATE;
assign #(in_delay) TXSEQUENCE_delay = TXSEQUENCE;
assign #(in_delay) TXSWING_delay = TXSWING;
assign #(in_delay) TXSYNCALLIN_delay = TXSYNCALLIN;
assign #(in_delay) TXSYNCIN_delay = TXSYNCIN;
assign #(in_delay) TXSYNCMODE_delay = TXSYNCMODE;
assign #(in_delay) TXSYSCLKSEL_delay = TXSYSCLKSEL;
assign #(in_delay) TXUSERRDY_delay = TXUSERRDY;
assign BUFGTCEMASK_delay = BUFGTCEMASK_out;
assign BUFGTCE_delay = BUFGTCE_out;
assign BUFGTDIV_delay = BUFGTDIV_out;
assign BUFGTRESET_delay = BUFGTRESET_out;
assign BUFGTRSTMASK_delay = BUFGTRSTMASK_out;
assign CPLLFBCLKLOST_delay = CPLLFBCLKLOST_out;
assign CPLLLOCK_delay = CPLLLOCK_out;
assign CPLLREFCLKLOST_delay = CPLLREFCLKLOST_out;
assign DMONITOROUT_delay = DMONITOROUT_out;
assign DRPDO_delay = DRPDO_out;
assign DRPRDY_delay = DRPRDY_out;
assign EYESCANDATAERROR_delay = EYESCANDATAERROR_out;
assign GTPOWERGOOD_delay = GTPOWERGOOD_out;
assign GTREFCLKMONITOR_delay = GTREFCLKMONITOR_out;
assign GTYTXN_delay = GTYTXN_out;
assign GTYTXP_delay = GTYTXP_out;
assign PCIERATEGEN3_delay = PCIERATEGEN3_out;
assign PCIERATEIDLE_delay = PCIERATEIDLE_out;
assign PCIERATEQPLLPD_delay = PCIERATEQPLLPD_out;
assign PCIERATEQPLLRESET_delay = PCIERATEQPLLRESET_out;
assign PCIESYNCTXSYNCDONE_delay = PCIESYNCTXSYNCDONE_out;
assign PCIEUSERGEN3RDY_delay = PCIEUSERGEN3RDY_out;
assign PCIEUSERPHYSTATUSRST_delay = PCIEUSERPHYSTATUSRST_out;
assign PCIEUSERRATESTART_delay = PCIEUSERRATESTART_out;
assign PCSRSVDOUT_delay = PCSRSVDOUT_out;
assign PHYSTATUS_delay = PHYSTATUS_out;
assign PINRSRVDAS_delay = PINRSRVDAS_out;
assign RESETEXCEPTION_delay = RESETEXCEPTION_out;
assign RXBUFSTATUS_delay = RXBUFSTATUS_out;
assign RXBYTEISALIGNED_delay = RXBYTEISALIGNED_out;
assign RXBYTEREALIGN_delay = RXBYTEREALIGN_out;
assign RXCDRLOCK_delay = RXCDRLOCK_out;
assign RXCDRPHDONE_delay = RXCDRPHDONE_out;
assign RXCHANBONDSEQ_delay = RXCHANBONDSEQ_out;
assign RXCHANISALIGNED_delay = RXCHANISALIGNED_out;
assign RXCHANREALIGN_delay = RXCHANREALIGN_out;
assign RXCHBONDO_delay = RXCHBONDO_out;
assign RXCKCALDONE_delay = RXCKCALDONE_out;
assign RXCLKCORCNT_delay = RXCLKCORCNT_out;
assign RXCOMINITDET_delay = RXCOMINITDET_out;
assign RXCOMMADET_delay = RXCOMMADET_out;
assign RXCOMSASDET_delay = RXCOMSASDET_out;
assign RXCOMWAKEDET_delay = RXCOMWAKEDET_out;
assign RXCTRL0_delay = RXCTRL0_out;
assign RXCTRL1_delay = RXCTRL1_out;
assign RXCTRL2_delay = RXCTRL2_out;
assign RXCTRL3_delay = RXCTRL3_out;
assign RXDATAEXTENDRSVD_delay = RXDATAEXTENDRSVD_out;
assign RXDATAVALID_delay = RXDATAVALID_out;
assign RXDATA_delay = RXDATA_out;
assign RXDLYSRESETDONE_delay = RXDLYSRESETDONE_out;
assign RXELECIDLE_delay = RXELECIDLE_out;
assign RXHEADERVALID_delay = RXHEADERVALID_out;
assign RXHEADER_delay = RXHEADER_out;
assign RXMONITOROUT_delay = RXMONITOROUT_out;
assign RXOSINTDONE_delay = RXOSINTDONE_out;
assign RXOSINTSTARTED_delay = RXOSINTSTARTED_out;
assign RXOSINTSTROBEDONE_delay = RXOSINTSTROBEDONE_out;
assign RXOSINTSTROBESTARTED_delay = RXOSINTSTROBESTARTED_out;
assign RXOUTCLKFABRIC_delay = RXOUTCLKFABRIC_out;
assign RXOUTCLKPCS_delay = RXOUTCLKPCS_out;
assign RXOUTCLK_delay = RXOUTCLK_out;
assign RXPHALIGNDONE_delay = RXPHALIGNDONE_out;
assign RXPHALIGNERR_delay = RXPHALIGNERR_out;
assign RXPMARESETDONE_delay = RXPMARESETDONE_out;
assign RXPRBSERR_delay = RXPRBSERR_out;
assign RXPRBSLOCKED_delay = RXPRBSLOCKED_out;
assign RXPRGDIVRESETDONE_delay = RXPRGDIVRESETDONE_out;
assign RXRATEDONE_delay = RXRATEDONE_out;
assign RXRECCLKOUT_delay = RXRECCLKOUT_out;
assign RXRESETDONE_delay = RXRESETDONE_out;
assign RXSLIDERDY_delay = RXSLIDERDY_out;
assign RXSLIPDONE_delay = RXSLIPDONE_out;
assign RXSLIPOUTCLKRDY_delay = RXSLIPOUTCLKRDY_out;
assign RXSLIPPMARDY_delay = RXSLIPPMARDY_out;
assign RXSTARTOFSEQ_delay = RXSTARTOFSEQ_out;
assign RXSTATUS_delay = RXSTATUS_out;
assign RXSYNCDONE_delay = RXSYNCDONE_out;
assign RXSYNCOUT_delay = RXSYNCOUT_out;
assign RXVALID_delay = RXVALID_out;
assign TXBUFSTATUS_delay = TXBUFSTATUS_out;
assign TXCOMFINISH_delay = TXCOMFINISH_out;
assign TXDCCDONE_delay = TXDCCDONE_out;
assign TXDLYSRESETDONE_delay = TXDLYSRESETDONE_out;
assign TXOUTCLKFABRIC_delay = TXOUTCLKFABRIC_out;
assign TXOUTCLKPCS_delay = TXOUTCLKPCS_out;
assign TXOUTCLK_delay = TXOUTCLK_out;
assign TXPHALIGNDONE_delay = TXPHALIGNDONE_out;
assign TXPHINITDONE_delay = TXPHINITDONE_out;
assign TXPMARESETDONE_delay = TXPMARESETDONE_out;
assign TXPRGDIVRESETDONE_delay = TXPRGDIVRESETDONE_out;
assign TXRATEDONE_delay = TXRATEDONE_out;
assign TXRESETDONE_delay = TXRESETDONE_out;
assign TXSYNCDONE_delay = TXSYNCDONE_out;
assign TXSYNCOUT_delay = TXSYNCOUT_out;
assign CDRSTEPDIR_in = (CDRSTEPDIR !== 1'bz) && CDRSTEPDIR_delay; // rv 0
assign CDRSTEPSQ_in = (CDRSTEPSQ !== 1'bz) && CDRSTEPSQ_delay; // rv 0
assign CDRSTEPSX_in = (CDRSTEPSX !== 1'bz) && CDRSTEPSX_delay; // rv 0
assign CFGRESET_in = (CFGRESET !== 1'bz) && CFGRESET_delay; // rv 0
assign CLKRSVD0_in = (CLKRSVD0 !== 1'bz) && CLKRSVD0_delay; // rv 0
assign CLKRSVD1_in = (CLKRSVD1 !== 1'bz) && CLKRSVD1_delay; // rv 0
assign CPLLLOCKDETCLK_in = (CPLLLOCKDETCLK !== 1'bz) && CPLLLOCKDETCLK_delay; // rv 0
assign CPLLLOCKEN_in = (CPLLLOCKEN !== 1'bz) && CPLLLOCKEN_delay; // rv 0
assign CPLLPD_in = (CPLLPD !== 1'bz) && CPLLPD_delay; // rv 0
assign CPLLREFCLKSEL_in[0] = (CPLLREFCLKSEL[0] === 1'bz) || CPLLREFCLKSEL_delay[0]; // rv 1
assign CPLLREFCLKSEL_in[1] = (CPLLREFCLKSEL[1] !== 1'bz) && CPLLREFCLKSEL_delay[1]; // rv 0
assign CPLLREFCLKSEL_in[2] = (CPLLREFCLKSEL[2] !== 1'bz) && CPLLREFCLKSEL_delay[2]; // rv 0
assign CPLLRESET_in = (CPLLRESET !== 1'bz) && CPLLRESET_delay; // rv 0
assign DMONFIFORESET_in = (DMONFIFORESET !== 1'bz) && DMONFIFORESET_delay; // rv 0
assign DMONITORCLK_in = (DMONITORCLK !== 1'bz) && DMONITORCLK_delay; // rv 0
assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0
assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0
assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0
assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0
assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0
assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0
assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0
assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0
assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0
assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0
assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0
assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0
assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0
assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0
assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0
assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0
assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0
assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0
assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0
assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0
assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0
assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0
assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0
assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0
assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0
assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0
assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0
assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0
assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0
assign ELPCALDVORWREN_in = (ELPCALDVORWREN !== 1'bz) && ELPCALDVORWREN_delay; // rv 0
assign ELPCALPAORWREN_in = (ELPCALPAORWREN !== 1'bz) && ELPCALPAORWREN_delay; // rv 0
assign EVODDPHICALDONE_in = (EVODDPHICALDONE !== 1'bz) && EVODDPHICALDONE_delay; // rv 0
assign EVODDPHICALSTART_in = (EVODDPHICALSTART !== 1'bz) && EVODDPHICALSTART_delay; // rv 0
assign EVODDPHIDRDEN_in = (EVODDPHIDRDEN !== 1'bz) && EVODDPHIDRDEN_delay; // rv 0
assign EVODDPHIDWREN_in = (EVODDPHIDWREN !== 1'bz) && EVODDPHIDWREN_delay; // rv 0
assign EVODDPHIXRDEN_in = (EVODDPHIXRDEN !== 1'bz) && EVODDPHIXRDEN_delay; // rv 0
assign EVODDPHIXWREN_in = (EVODDPHIXWREN !== 1'bz) && EVODDPHIXWREN_delay; // rv 0
assign EYESCANMODE_in = (EYESCANMODE !== 1'bz) && EYESCANMODE_delay; // rv 0
assign EYESCANRESET_in = (EYESCANRESET !== 1'bz) && EYESCANRESET_delay; // rv 0
assign EYESCANTRIGGER_in = (EYESCANTRIGGER !== 1'bz) && EYESCANTRIGGER_delay; // rv 0
assign GTGREFCLK_in = GTGREFCLK_delay;
assign GTNORTHREFCLK0_in = GTNORTHREFCLK0_delay;
assign GTNORTHREFCLK1_in = GTNORTHREFCLK1_delay;
assign GTREFCLK0_in = GTREFCLK0_delay;
assign GTREFCLK1_in = GTREFCLK1_delay;
assign GTRESETSEL_in = (GTRESETSEL !== 1'bz) && GTRESETSEL_delay; // rv 0
assign GTRSVD_in[0] = (GTRSVD[0] !== 1'bz) && GTRSVD_delay[0]; // rv 0
assign GTRSVD_in[10] = (GTRSVD[10] !== 1'bz) && GTRSVD_delay[10]; // rv 0
assign GTRSVD_in[11] = (GTRSVD[11] !== 1'bz) && GTRSVD_delay[11]; // rv 0
assign GTRSVD_in[12] = (GTRSVD[12] !== 1'bz) && GTRSVD_delay[12]; // rv 0
assign GTRSVD_in[13] = (GTRSVD[13] !== 1'bz) && GTRSVD_delay[13]; // rv 0
assign GTRSVD_in[14] = (GTRSVD[14] !== 1'bz) && GTRSVD_delay[14]; // rv 0
assign GTRSVD_in[15] = (GTRSVD[15] !== 1'bz) && GTRSVD_delay[15]; // rv 0
assign GTRSVD_in[1] = (GTRSVD[1] !== 1'bz) && GTRSVD_delay[1]; // rv 0
assign GTRSVD_in[2] = (GTRSVD[2] !== 1'bz) && GTRSVD_delay[2]; // rv 0
assign GTRSVD_in[3] = (GTRSVD[3] !== 1'bz) && GTRSVD_delay[3]; // rv 0
assign GTRSVD_in[4] = (GTRSVD[4] !== 1'bz) && GTRSVD_delay[4]; // rv 0
assign GTRSVD_in[5] = (GTRSVD[5] !== 1'bz) && GTRSVD_delay[5]; // rv 0
assign GTRSVD_in[6] = (GTRSVD[6] !== 1'bz) && GTRSVD_delay[6]; // rv 0
assign GTRSVD_in[7] = (GTRSVD[7] !== 1'bz) && GTRSVD_delay[7]; // rv 0
assign GTRSVD_in[8] = (GTRSVD[8] !== 1'bz) && GTRSVD_delay[8]; // rv 0
assign GTRSVD_in[9] = (GTRSVD[9] !== 1'bz) && GTRSVD_delay[9]; // rv 0
assign GTRXRESET_in = (GTRXRESET !== 1'bz) && GTRXRESET_delay; // rv 0
assign GTSOUTHREFCLK0_in = GTSOUTHREFCLK0_delay;
assign GTSOUTHREFCLK1_in = GTSOUTHREFCLK1_delay;
assign GTTXRESET_in = (GTTXRESET !== 1'bz) && GTTXRESET_delay; // rv 0
assign GTYRXN_in = GTYRXN_delay;
assign GTYRXP_in = GTYRXP_delay;
assign LOOPBACK_in[0] = (LOOPBACK[0] !== 1'bz) && LOOPBACK_delay[0]; // rv 0
assign LOOPBACK_in[1] = (LOOPBACK[1] !== 1'bz) && LOOPBACK_delay[1]; // rv 0
assign LOOPBACK_in[2] = (LOOPBACK[2] !== 1'bz) && LOOPBACK_delay[2]; // rv 0
assign LOOPRSVD_in[0] = (LOOPRSVD[0] !== 1'bz) && LOOPRSVD_delay[0]; // rv 0
assign LOOPRSVD_in[10] = (LOOPRSVD[10] !== 1'bz) && LOOPRSVD_delay[10]; // rv 0
assign LOOPRSVD_in[11] = (LOOPRSVD[11] !== 1'bz) && LOOPRSVD_delay[11]; // rv 0
assign LOOPRSVD_in[12] = (LOOPRSVD[12] !== 1'bz) && LOOPRSVD_delay[12]; // rv 0
assign LOOPRSVD_in[13] = (LOOPRSVD[13] !== 1'bz) && LOOPRSVD_delay[13]; // rv 0
assign LOOPRSVD_in[14] = (LOOPRSVD[14] !== 1'bz) && LOOPRSVD_delay[14]; // rv 0
assign LOOPRSVD_in[15] = (LOOPRSVD[15] !== 1'bz) && LOOPRSVD_delay[15]; // rv 0
assign LOOPRSVD_in[1] = (LOOPRSVD[1] !== 1'bz) && LOOPRSVD_delay[1]; // rv 0
assign LOOPRSVD_in[2] = (LOOPRSVD[2] !== 1'bz) && LOOPRSVD_delay[2]; // rv 0
assign LOOPRSVD_in[3] = (LOOPRSVD[3] !== 1'bz) && LOOPRSVD_delay[3]; // rv 0
assign LOOPRSVD_in[4] = (LOOPRSVD[4] !== 1'bz) && LOOPRSVD_delay[4]; // rv 0
assign LOOPRSVD_in[5] = (LOOPRSVD[5] !== 1'bz) && LOOPRSVD_delay[5]; // rv 0
assign LOOPRSVD_in[6] = (LOOPRSVD[6] !== 1'bz) && LOOPRSVD_delay[6]; // rv 0
assign LOOPRSVD_in[7] = (LOOPRSVD[7] !== 1'bz) && LOOPRSVD_delay[7]; // rv 0
assign LOOPRSVD_in[8] = (LOOPRSVD[8] !== 1'bz) && LOOPRSVD_delay[8]; // rv 0
assign LOOPRSVD_in[9] = (LOOPRSVD[9] !== 1'bz) && LOOPRSVD_delay[9]; // rv 0
assign LPBKRXTXSEREN_in = (LPBKRXTXSEREN !== 1'bz) && LPBKRXTXSEREN_delay; // rv 0
assign LPBKTXRXSEREN_in = (LPBKTXRXSEREN !== 1'bz) && LPBKTXRXSEREN_delay; // rv 0
assign PCIEEQRXEQADAPTDONE_in = (PCIEEQRXEQADAPTDONE !== 1'bz) && PCIEEQRXEQADAPTDONE_delay; // rv 0
assign PCIERSTIDLE_in = (PCIERSTIDLE !== 1'bz) && PCIERSTIDLE_delay; // rv 0
assign PCIERSTTXSYNCSTART_in = (PCIERSTTXSYNCSTART !== 1'bz) && PCIERSTTXSYNCSTART_delay; // rv 0
assign PCIEUSERRATEDONE_in = (PCIEUSERRATEDONE !== 1'bz) && PCIEUSERRATEDONE_delay; // rv 0
assign PCSRSVDIN2_in[0] = (PCSRSVDIN2[0] !== 1'bz) && PCSRSVDIN2_delay[0]; // rv 0
assign PCSRSVDIN2_in[1] = (PCSRSVDIN2[1] !== 1'bz) && PCSRSVDIN2_delay[1]; // rv 0
assign PCSRSVDIN2_in[2] = (PCSRSVDIN2[2] !== 1'bz) && PCSRSVDIN2_delay[2]; // rv 0
assign PCSRSVDIN2_in[3] = (PCSRSVDIN2[3] !== 1'bz) && PCSRSVDIN2_delay[3]; // rv 0
assign PCSRSVDIN2_in[4] = (PCSRSVDIN2[4] !== 1'bz) && PCSRSVDIN2_delay[4]; // rv 0
assign PCSRSVDIN_in[0] = (PCSRSVDIN[0] !== 1'bz) && PCSRSVDIN_delay[0]; // rv 0
assign PCSRSVDIN_in[10] = (PCSRSVDIN[10] !== 1'bz) && PCSRSVDIN_delay[10]; // rv 0
assign PCSRSVDIN_in[11] = (PCSRSVDIN[11] !== 1'bz) && PCSRSVDIN_delay[11]; // rv 0
assign PCSRSVDIN_in[12] = (PCSRSVDIN[12] !== 1'bz) && PCSRSVDIN_delay[12]; // rv 0
assign PCSRSVDIN_in[13] = (PCSRSVDIN[13] !== 1'bz) && PCSRSVDIN_delay[13]; // rv 0
assign PCSRSVDIN_in[14] = (PCSRSVDIN[14] !== 1'bz) && PCSRSVDIN_delay[14]; // rv 0
assign PCSRSVDIN_in[15] = (PCSRSVDIN[15] !== 1'bz) && PCSRSVDIN_delay[15]; // rv 0
assign PCSRSVDIN_in[1] = (PCSRSVDIN[1] !== 1'bz) && PCSRSVDIN_delay[1]; // rv 0
assign PCSRSVDIN_in[2] = (PCSRSVDIN[2] !== 1'bz) && PCSRSVDIN_delay[2]; // rv 0
assign PCSRSVDIN_in[3] = (PCSRSVDIN[3] !== 1'bz) && PCSRSVDIN_delay[3]; // rv 0
assign PCSRSVDIN_in[4] = (PCSRSVDIN[4] !== 1'bz) && PCSRSVDIN_delay[4]; // rv 0
assign PCSRSVDIN_in[5] = (PCSRSVDIN[5] !== 1'bz) && PCSRSVDIN_delay[5]; // rv 0
assign PCSRSVDIN_in[6] = (PCSRSVDIN[6] !== 1'bz) && PCSRSVDIN_delay[6]; // rv 0
assign PCSRSVDIN_in[7] = (PCSRSVDIN[7] !== 1'bz) && PCSRSVDIN_delay[7]; // rv 0
assign PCSRSVDIN_in[8] = (PCSRSVDIN[8] !== 1'bz) && PCSRSVDIN_delay[8]; // rv 0
assign PCSRSVDIN_in[9] = (PCSRSVDIN[9] !== 1'bz) && PCSRSVDIN_delay[9]; // rv 0
assign PMARSVDIN_in[0] = (PMARSVDIN[0] !== 1'bz) && PMARSVDIN_delay[0]; // rv 0
assign PMARSVDIN_in[1] = (PMARSVDIN[1] !== 1'bz) && PMARSVDIN_delay[1]; // rv 0
assign PMARSVDIN_in[2] = (PMARSVDIN[2] !== 1'bz) && PMARSVDIN_delay[2]; // rv 0
assign PMARSVDIN_in[3] = (PMARSVDIN[3] !== 1'bz) && PMARSVDIN_delay[3]; // rv 0
assign PMARSVDIN_in[4] = (PMARSVDIN[4] !== 1'bz) && PMARSVDIN_delay[4]; // rv 0
assign QPLL0CLK_in = QPLL0CLK_delay;
assign QPLL0REFCLK_in = QPLL0REFCLK_delay;
assign QPLL1CLK_in = QPLL1CLK_delay;
assign QPLL1REFCLK_in = QPLL1REFCLK_delay;
assign RESETOVRD_in = (RESETOVRD !== 1'bz) && RESETOVRD_delay; // rv 0
assign RSTCLKENTX_in = (RSTCLKENTX !== 1'bz) && RSTCLKENTX_delay; // rv 0
assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN_delay; // rv 0
assign RXBUFRESET_in = (RXBUFRESET !== 1'bz) && RXBUFRESET_delay; // rv 0
assign RXCDRFREQRESET_in = (RXCDRFREQRESET !== 1'bz) && RXCDRFREQRESET_delay; // rv 0
assign RXCDRHOLD_in = (RXCDRHOLD !== 1'bz) && RXCDRHOLD_delay; // rv 0
assign RXCDROVRDEN_in = (RXCDROVRDEN !== 1'bz) && RXCDROVRDEN_delay; // rv 0
assign RXCDRRESETRSV_in = (RXCDRRESETRSV !== 1'bz) && RXCDRRESETRSV_delay; // rv 0
assign RXCDRRESET_in = (RXCDRRESET !== 1'bz) && RXCDRRESET_delay; // rv 0
assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN_delay; // rv 0
assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI_delay[0]; // rv 0
assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI_delay[1]; // rv 0
assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI_delay[2]; // rv 0
assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI_delay[3]; // rv 0
assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI_delay[4]; // rv 0
assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL_delay[0]; // rv 0
assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL_delay[1]; // rv 0
assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL_delay[2]; // rv 0
assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER_delay; // rv 0
assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE_delay; // rv 0
assign RXCKCALRESET_in = (RXCKCALRESET !== 1'bz) && RXCKCALRESET_delay; // rv 0
assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN_delay; // rv 0
assign RXDCCFORCESTART_in = (RXDCCFORCESTART !== 1'bz) && RXDCCFORCESTART_delay; // rv 0
assign RXDFEAGCHOLD_in = (RXDFEAGCHOLD !== 1'bz) && RXDFEAGCHOLD_delay; // rv 0
assign RXDFEAGCOVRDEN_in = (RXDFEAGCOVRDEN !== 1'bz) && RXDFEAGCOVRDEN_delay; // rv 0
assign RXDFELFHOLD_in = (RXDFELFHOLD !== 1'bz) && RXDFELFHOLD_delay; // rv 0
assign RXDFELFOVRDEN_in = (RXDFELFOVRDEN !== 1'bz) && RXDFELFOVRDEN_delay; // rv 0
assign RXDFELPMRESET_in = (RXDFELPMRESET !== 1'bz) && RXDFELPMRESET_delay; // rv 0
assign RXDFETAP10HOLD_in = (RXDFETAP10HOLD !== 1'bz) && RXDFETAP10HOLD_delay; // rv 0
assign RXDFETAP10OVRDEN_in = (RXDFETAP10OVRDEN !== 1'bz) && RXDFETAP10OVRDEN_delay; // rv 0
assign RXDFETAP11HOLD_in = (RXDFETAP11HOLD !== 1'bz) && RXDFETAP11HOLD_delay; // rv 0
assign RXDFETAP11OVRDEN_in = (RXDFETAP11OVRDEN !== 1'bz) && RXDFETAP11OVRDEN_delay; // rv 0
assign RXDFETAP12HOLD_in = (RXDFETAP12HOLD !== 1'bz) && RXDFETAP12HOLD_delay; // rv 0
assign RXDFETAP12OVRDEN_in = (RXDFETAP12OVRDEN !== 1'bz) && RXDFETAP12OVRDEN_delay; // rv 0
assign RXDFETAP13HOLD_in = (RXDFETAP13HOLD !== 1'bz) && RXDFETAP13HOLD_delay; // rv 0
assign RXDFETAP13OVRDEN_in = (RXDFETAP13OVRDEN !== 1'bz) && RXDFETAP13OVRDEN_delay; // rv 0
assign RXDFETAP14HOLD_in = (RXDFETAP14HOLD !== 1'bz) && RXDFETAP14HOLD_delay; // rv 0
assign RXDFETAP14OVRDEN_in = (RXDFETAP14OVRDEN !== 1'bz) && RXDFETAP14OVRDEN_delay; // rv 0
assign RXDFETAP15HOLD_in = (RXDFETAP15HOLD !== 1'bz) && RXDFETAP15HOLD_delay; // rv 0
assign RXDFETAP15OVRDEN_in = (RXDFETAP15OVRDEN !== 1'bz) && RXDFETAP15OVRDEN_delay; // rv 0
assign RXDFETAP2HOLD_in = (RXDFETAP2HOLD !== 1'bz) && RXDFETAP2HOLD_delay; // rv 0
assign RXDFETAP2OVRDEN_in = (RXDFETAP2OVRDEN !== 1'bz) && RXDFETAP2OVRDEN_delay; // rv 0
assign RXDFETAP3HOLD_in = (RXDFETAP3HOLD !== 1'bz) && RXDFETAP3HOLD_delay; // rv 0
assign RXDFETAP3OVRDEN_in = (RXDFETAP3OVRDEN !== 1'bz) && RXDFETAP3OVRDEN_delay; // rv 0
assign RXDFETAP4HOLD_in = (RXDFETAP4HOLD !== 1'bz) && RXDFETAP4HOLD_delay; // rv 0
assign RXDFETAP4OVRDEN_in = (RXDFETAP4OVRDEN !== 1'bz) && RXDFETAP4OVRDEN_delay; // rv 0
assign RXDFETAP5HOLD_in = (RXDFETAP5HOLD !== 1'bz) && RXDFETAP5HOLD_delay; // rv 0
assign RXDFETAP5OVRDEN_in = (RXDFETAP5OVRDEN !== 1'bz) && RXDFETAP5OVRDEN_delay; // rv 0
assign RXDFETAP6HOLD_in = (RXDFETAP6HOLD !== 1'bz) && RXDFETAP6HOLD_delay; // rv 0
assign RXDFETAP6OVRDEN_in = (RXDFETAP6OVRDEN !== 1'bz) && RXDFETAP6OVRDEN_delay; // rv 0
assign RXDFETAP7HOLD_in = (RXDFETAP7HOLD !== 1'bz) && RXDFETAP7HOLD_delay; // rv 0
assign RXDFETAP7OVRDEN_in = (RXDFETAP7OVRDEN !== 1'bz) && RXDFETAP7OVRDEN_delay; // rv 0
assign RXDFETAP8HOLD_in = (RXDFETAP8HOLD !== 1'bz) && RXDFETAP8HOLD_delay; // rv 0
assign RXDFETAP8OVRDEN_in = (RXDFETAP8OVRDEN !== 1'bz) && RXDFETAP8OVRDEN_delay; // rv 0
assign RXDFETAP9HOLD_in = (RXDFETAP9HOLD !== 1'bz) && RXDFETAP9HOLD_delay; // rv 0
assign RXDFETAP9OVRDEN_in = (RXDFETAP9OVRDEN !== 1'bz) && RXDFETAP9OVRDEN_delay; // rv 0
assign RXDFEUTHOLD_in = (RXDFEUTHOLD !== 1'bz) && RXDFEUTHOLD_delay; // rv 0
assign RXDFEUTOVRDEN_in = (RXDFEUTOVRDEN !== 1'bz) && RXDFEUTOVRDEN_delay; // rv 0
assign RXDFEVPHOLD_in = (RXDFEVPHOLD !== 1'bz) && RXDFEVPHOLD_delay; // rv 0
assign RXDFEVPOVRDEN_in = (RXDFEVPOVRDEN !== 1'bz) && RXDFEVPOVRDEN_delay; // rv 0
assign RXDFEVSEN_in = (RXDFEVSEN !== 1'bz) && RXDFEVSEN_delay; // rv 0
assign RXDFEXYDEN_in = (RXDFEXYDEN !== 1'bz) && RXDFEXYDEN_delay; // rv 0
assign RXDLYBYPASS_in = (RXDLYBYPASS !== 1'bz) && RXDLYBYPASS_delay; // rv 0
assign RXDLYEN_in = (RXDLYEN !== 1'bz) && RXDLYEN_delay; // rv 0
assign RXDLYOVRDEN_in = (RXDLYOVRDEN !== 1'bz) && RXDLYOVRDEN_delay; // rv 0
assign RXDLYSRESET_in = (RXDLYSRESET !== 1'bz) && RXDLYSRESET_delay; // rv 0
assign RXELECIDLEMODE_in[0] = (RXELECIDLEMODE[0] !== 1'bz) && RXELECIDLEMODE_delay[0]; // rv 0
assign RXELECIDLEMODE_in[1] = (RXELECIDLEMODE[1] !== 1'bz) && RXELECIDLEMODE_delay[1]; // rv 0
assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP_delay; // rv 0
assign RXLATCLK_in = (RXLATCLK !== 1'bz) && RXLATCLK_delay; // rv 0
assign RXLPMEN_in = (RXLPMEN !== 1'bz) && RXLPMEN_delay; // rv 0
assign RXLPMGCHOLD_in = (RXLPMGCHOLD !== 1'bz) && RXLPMGCHOLD_delay; // rv 0
assign RXLPMGCOVRDEN_in = (RXLPMGCOVRDEN !== 1'bz) && RXLPMGCOVRDEN_delay; // rv 0
assign RXLPMHFHOLD_in = (RXLPMHFHOLD !== 1'bz) && RXLPMHFHOLD_delay; // rv 0
assign RXLPMHFOVRDEN_in = (RXLPMHFOVRDEN !== 1'bz) && RXLPMHFOVRDEN_delay; // rv 0
assign RXLPMLFHOLD_in = (RXLPMLFHOLD !== 1'bz) && RXLPMLFHOLD_delay; // rv 0
assign RXLPMLFKLOVRDEN_in = (RXLPMLFKLOVRDEN !== 1'bz) && RXLPMLFKLOVRDEN_delay; // rv 0
assign RXLPMOSHOLD_in = (RXLPMOSHOLD !== 1'bz) && RXLPMOSHOLD_delay; // rv 0
assign RXLPMOSOVRDEN_in = (RXLPMOSOVRDEN !== 1'bz) && RXLPMOSOVRDEN_delay; // rv 0
assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN_delay; // rv 0
assign RXMONITORSEL_in[0] = (RXMONITORSEL[0] !== 1'bz) && RXMONITORSEL_delay[0]; // rv 0
assign RXMONITORSEL_in[1] = (RXMONITORSEL[1] !== 1'bz) && RXMONITORSEL_delay[1]; // rv 0
assign RXOOBRESET_in = (RXOOBRESET !== 1'bz) && RXOOBRESET_delay; // rv 0
assign RXOSCALRESET_in = (RXOSCALRESET !== 1'bz) && RXOSCALRESET_delay; // rv 0
assign RXOSHOLD_in = (RXOSHOLD !== 1'bz) && RXOSHOLD_delay; // rv 0
assign RXOSINTCFG_in[0] = (RXOSINTCFG[0] !== 1'bz) && RXOSINTCFG_delay[0]; // rv 0
assign RXOSINTCFG_in[1] = (RXOSINTCFG[1] === 1'bz) || RXOSINTCFG_delay[1]; // rv 1
assign RXOSINTCFG_in[2] = (RXOSINTCFG[2] === 1'bz) || RXOSINTCFG_delay[2]; // rv 1
assign RXOSINTCFG_in[3] = (RXOSINTCFG[3] !== 1'bz) && RXOSINTCFG_delay[3]; // rv 0
assign RXOSINTEN_in = (RXOSINTEN === 1'bz) || RXOSINTEN_delay; // rv 1
assign RXOSINTHOLD_in = (RXOSINTHOLD !== 1'bz) && RXOSINTHOLD_delay; // rv 0
assign RXOSINTOVRDEN_in = (RXOSINTOVRDEN !== 1'bz) && RXOSINTOVRDEN_delay; // rv 0
assign RXOSINTSTROBE_in = (RXOSINTSTROBE !== 1'bz) && RXOSINTSTROBE_delay; // rv 0
assign RXOSINTTESTOVRDEN_in = (RXOSINTTESTOVRDEN !== 1'bz) && RXOSINTTESTOVRDEN_delay; // rv 0
assign RXOSOVRDEN_in = (RXOSOVRDEN !== 1'bz) && RXOSOVRDEN_delay; // rv 0
assign RXOUTCLKSEL_in[0] = (RXOUTCLKSEL[0] !== 1'bz) && RXOUTCLKSEL_delay[0]; // rv 0
assign RXOUTCLKSEL_in[1] = (RXOUTCLKSEL[1] !== 1'bz) && RXOUTCLKSEL_delay[1]; // rv 0
assign RXOUTCLKSEL_in[2] = (RXOUTCLKSEL[2] !== 1'bz) && RXOUTCLKSEL_delay[2]; // rv 0
assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN_delay; // rv 0
assign RXPCSRESET_in = (RXPCSRESET !== 1'bz) && RXPCSRESET_delay; // rv 0
assign RXPD_in[0] = (RXPD[0] !== 1'bz) && RXPD_delay[0]; // rv 0
assign RXPD_in[1] = (RXPD[1] !== 1'bz) && RXPD_delay[1]; // rv 0
assign RXPHALIGNEN_in = (RXPHALIGNEN !== 1'bz) && RXPHALIGNEN_delay; // rv 0
assign RXPHALIGN_in = (RXPHALIGN !== 1'bz) && RXPHALIGN_delay; // rv 0
assign RXPHDLYPD_in = (RXPHDLYPD !== 1'bz) && RXPHDLYPD_delay; // rv 0
assign RXPHDLYRESET_in = (RXPHDLYRESET !== 1'bz) && RXPHDLYRESET_delay; // rv 0
assign RXPHOVRDEN_in = (RXPHOVRDEN !== 1'bz) && RXPHOVRDEN_delay; // rv 0
assign RXPLLCLKSEL_in[0] = (RXPLLCLKSEL[0] !== 1'bz) && RXPLLCLKSEL_delay[0]; // rv 0
assign RXPLLCLKSEL_in[1] = (RXPLLCLKSEL[1] !== 1'bz) && RXPLLCLKSEL_delay[1]; // rv 0
assign RXPMARESET_in = (RXPMARESET !== 1'bz) && RXPMARESET_delay; // rv 0
assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY_delay; // rv 0
assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET_delay; // rv 0
assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL_delay[0]; // rv 0
assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL_delay[1]; // rv 0
assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL_delay[2]; // rv 0
assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL_delay[3]; // rv 0
assign RXPROGDIVRESET_in = (RXPROGDIVRESET !== 1'bz) && RXPROGDIVRESET_delay; // rv 0
assign RXRATEMODE_in = (RXRATEMODE !== 1'bz) && RXRATEMODE_delay; // rv 0
assign RXRATE_in[0] = (RXRATE[0] !== 1'bz) && RXRATE_delay[0]; // rv 0
assign RXRATE_in[1] = (RXRATE[1] !== 1'bz) && RXRATE_delay[1]; // rv 0
assign RXRATE_in[2] = (RXRATE[2] !== 1'bz) && RXRATE_delay[2]; // rv 0
assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE_delay; // rv 0
assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK_delay; // rv 0
assign RXSLIPPMA_in = (RXSLIPPMA !== 1'bz) && RXSLIPPMA_delay; // rv 0
assign RXSYNCALLIN_in = (RXSYNCALLIN !== 1'bz) && RXSYNCALLIN_delay; // rv 0
assign RXSYNCIN_in = (RXSYNCIN !== 1'bz) && RXSYNCIN_delay; // rv 0
assign RXSYNCMODE_in = (RXSYNCMODE === 1'bz) || RXSYNCMODE_delay; // rv 1
assign RXSYSCLKSEL_in[0] = (RXSYSCLKSEL[0] !== 1'bz) && RXSYSCLKSEL_delay[0]; // rv 0
assign RXSYSCLKSEL_in[1] = (RXSYSCLKSEL[1] !== 1'bz) && RXSYSCLKSEL_delay[1]; // rv 0
assign RXUSERRDY_in = (RXUSERRDY !== 1'bz) && RXUSERRDY_delay; // rv 0
assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2_delay; // rv 0
assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK_delay; // rv 0
assign SIGVALIDCLK_in = (SIGVALIDCLK !== 1'bz) && SIGVALIDCLK_delay; // rv 0
assign TSTIN_in[0] = (TSTIN[0] !== 1'bz) && TSTIN_delay[0]; // rv 0
assign TSTIN_in[10] = (TSTIN[10] !== 1'bz) && TSTIN_delay[10]; // rv 0
assign TSTIN_in[11] = (TSTIN[11] !== 1'bz) && TSTIN_delay[11]; // rv 0
assign TSTIN_in[12] = (TSTIN[12] !== 1'bz) && TSTIN_delay[12]; // rv 0
assign TSTIN_in[13] = (TSTIN[13] !== 1'bz) && TSTIN_delay[13]; // rv 0
assign TSTIN_in[14] = (TSTIN[14] !== 1'bz) && TSTIN_delay[14]; // rv 0
assign TSTIN_in[15] = (TSTIN[15] !== 1'bz) && TSTIN_delay[15]; // rv 0
assign TSTIN_in[16] = (TSTIN[16] !== 1'bz) && TSTIN_delay[16]; // rv 0
assign TSTIN_in[17] = (TSTIN[17] !== 1'bz) && TSTIN_delay[17]; // rv 0
assign TSTIN_in[18] = (TSTIN[18] !== 1'bz) && TSTIN_delay[18]; // rv 0
assign TSTIN_in[19] = (TSTIN[19] !== 1'bz) && TSTIN_delay[19]; // rv 0
assign TSTIN_in[1] = (TSTIN[1] !== 1'bz) && TSTIN_delay[1]; // rv 0
assign TSTIN_in[2] = (TSTIN[2] !== 1'bz) && TSTIN_delay[2]; // rv 0
assign TSTIN_in[3] = (TSTIN[3] !== 1'bz) && TSTIN_delay[3]; // rv 0
assign TSTIN_in[4] = (TSTIN[4] !== 1'bz) && TSTIN_delay[4]; // rv 0
assign TSTIN_in[5] = (TSTIN[5] !== 1'bz) && TSTIN_delay[5]; // rv 0
assign TSTIN_in[6] = (TSTIN[6] !== 1'bz) && TSTIN_delay[6]; // rv 0
assign TSTIN_in[7] = (TSTIN[7] !== 1'bz) && TSTIN_delay[7]; // rv 0
assign TSTIN_in[8] = (TSTIN[8] !== 1'bz) && TSTIN_delay[8]; // rv 0
assign TSTIN_in[9] = (TSTIN[9] !== 1'bz) && TSTIN_delay[9]; // rv 0
assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS_delay[0]; // rv 0
assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS_delay[1]; // rv 0
assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS_delay[2]; // rv 0
assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS_delay[3]; // rv 0
assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS_delay[4]; // rv 0
assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS_delay[5]; // rv 0
assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS_delay[6]; // rv 0
assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS_delay[7]; // rv 0
assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN_delay; // rv 0
assign TXBUFDIFFCTRL_in[0] = (TXBUFDIFFCTRL[0] !== 1'bz) && TXBUFDIFFCTRL_delay[0]; // rv 0
assign TXBUFDIFFCTRL_in[1] = (TXBUFDIFFCTRL[1] !== 1'bz) && TXBUFDIFFCTRL_delay[1]; // rv 0
assign TXBUFDIFFCTRL_in[2] = (TXBUFDIFFCTRL[2] !== 1'bz) && TXBUFDIFFCTRL_delay[2]; // rv 0
assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT_delay; // rv 0
assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS_delay; // rv 0
assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE_delay; // rv 0
assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0_delay[0]; // rv 0
assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0_delay[10]; // rv 0
assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0_delay[11]; // rv 0
assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0_delay[12]; // rv 0
assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0_delay[13]; // rv 0
assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0_delay[14]; // rv 0
assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0_delay[15]; // rv 0
assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0_delay[1]; // rv 0
assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0_delay[2]; // rv 0
assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0_delay[3]; // rv 0
assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0_delay[4]; // rv 0
assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0_delay[5]; // rv 0
assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0_delay[6]; // rv 0
assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0_delay[7]; // rv 0
assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0_delay[8]; // rv 0
assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0_delay[9]; // rv 0
assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1_delay[0]; // rv 0
assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1_delay[10]; // rv 0
assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1_delay[11]; // rv 0
assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1_delay[12]; // rv 0
assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1_delay[13]; // rv 0
assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1_delay[14]; // rv 0
assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1_delay[15]; // rv 0
assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1_delay[1]; // rv 0
assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1_delay[2]; // rv 0
assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1_delay[3]; // rv 0
assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1_delay[4]; // rv 0
assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1_delay[5]; // rv 0
assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1_delay[6]; // rv 0
assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1_delay[7]; // rv 0
assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1_delay[8]; // rv 0
assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1_delay[9]; // rv 0
assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2_delay[0]; // rv 0
assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2_delay[1]; // rv 0
assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2_delay[2]; // rv 0
assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2_delay[3]; // rv 0
assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2_delay[4]; // rv 0
assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2_delay[5]; // rv 0
assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2_delay[6]; // rv 0
assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2_delay[7]; // rv 0
assign TXDATAEXTENDRSVD_in[0] = (TXDATAEXTENDRSVD[0] !== 1'bz) && TXDATAEXTENDRSVD_delay[0]; // rv 0
assign TXDATAEXTENDRSVD_in[1] = (TXDATAEXTENDRSVD[1] !== 1'bz) && TXDATAEXTENDRSVD_delay[1]; // rv 0
assign TXDATAEXTENDRSVD_in[2] = (TXDATAEXTENDRSVD[2] !== 1'bz) && TXDATAEXTENDRSVD_delay[2]; // rv 0
assign TXDATAEXTENDRSVD_in[3] = (TXDATAEXTENDRSVD[3] !== 1'bz) && TXDATAEXTENDRSVD_delay[3]; // rv 0
assign TXDATAEXTENDRSVD_in[4] = (TXDATAEXTENDRSVD[4] !== 1'bz) && TXDATAEXTENDRSVD_delay[4]; // rv 0
assign TXDATAEXTENDRSVD_in[5] = (TXDATAEXTENDRSVD[5] !== 1'bz) && TXDATAEXTENDRSVD_delay[5]; // rv 0
assign TXDATAEXTENDRSVD_in[6] = (TXDATAEXTENDRSVD[6] !== 1'bz) && TXDATAEXTENDRSVD_delay[6]; // rv 0
assign TXDATAEXTENDRSVD_in[7] = (TXDATAEXTENDRSVD[7] !== 1'bz) && TXDATAEXTENDRSVD_delay[7]; // rv 0
assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA_delay[0]; // rv 0
assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA_delay[100]; // rv 0
assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA_delay[101]; // rv 0
assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA_delay[102]; // rv 0
assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA_delay[103]; // rv 0
assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA_delay[104]; // rv 0
assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA_delay[105]; // rv 0
assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA_delay[106]; // rv 0
assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA_delay[107]; // rv 0
assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA_delay[108]; // rv 0
assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA_delay[109]; // rv 0
assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA_delay[10]; // rv 0
assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA_delay[110]; // rv 0
assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA_delay[111]; // rv 0
assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA_delay[112]; // rv 0
assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA_delay[113]; // rv 0
assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA_delay[114]; // rv 0
assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA_delay[115]; // rv 0
assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA_delay[116]; // rv 0
assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA_delay[117]; // rv 0
assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA_delay[118]; // rv 0
assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA_delay[119]; // rv 0
assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA_delay[11]; // rv 0
assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA_delay[120]; // rv 0
assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA_delay[121]; // rv 0
assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA_delay[122]; // rv 0
assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA_delay[123]; // rv 0
assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA_delay[124]; // rv 0
assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA_delay[125]; // rv 0
assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA_delay[126]; // rv 0
assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA_delay[127]; // rv 0
assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA_delay[12]; // rv 0
assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA_delay[13]; // rv 0
assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA_delay[14]; // rv 0
assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA_delay[15]; // rv 0
assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA_delay[16]; // rv 0
assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA_delay[17]; // rv 0
assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA_delay[18]; // rv 0
assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA_delay[19]; // rv 0
assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA_delay[1]; // rv 0
assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA_delay[20]; // rv 0
assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA_delay[21]; // rv 0
assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA_delay[22]; // rv 0
assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA_delay[23]; // rv 0
assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA_delay[24]; // rv 0
assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA_delay[25]; // rv 0
assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA_delay[26]; // rv 0
assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA_delay[27]; // rv 0
assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA_delay[28]; // rv 0
assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA_delay[29]; // rv 0
assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA_delay[2]; // rv 0
assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA_delay[30]; // rv 0
assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA_delay[31]; // rv 0
assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA_delay[32]; // rv 0
assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA_delay[33]; // rv 0
assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA_delay[34]; // rv 0
assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA_delay[35]; // rv 0
assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA_delay[36]; // rv 0
assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA_delay[37]; // rv 0
assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA_delay[38]; // rv 0
assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA_delay[39]; // rv 0
assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA_delay[3]; // rv 0
assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA_delay[40]; // rv 0
assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA_delay[41]; // rv 0
assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA_delay[42]; // rv 0
assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA_delay[43]; // rv 0
assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA_delay[44]; // rv 0
assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA_delay[45]; // rv 0
assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA_delay[46]; // rv 0
assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA_delay[47]; // rv 0
assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA_delay[48]; // rv 0
assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA_delay[49]; // rv 0
assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA_delay[4]; // rv 0
assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA_delay[50]; // rv 0
assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA_delay[51]; // rv 0
assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA_delay[52]; // rv 0
assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA_delay[53]; // rv 0
assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA_delay[54]; // rv 0
assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA_delay[55]; // rv 0
assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA_delay[56]; // rv 0
assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA_delay[57]; // rv 0
assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA_delay[58]; // rv 0
assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA_delay[59]; // rv 0
assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA_delay[5]; // rv 0
assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA_delay[60]; // rv 0
assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA_delay[61]; // rv 0
assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA_delay[62]; // rv 0
assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA_delay[63]; // rv 0
assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA_delay[64]; // rv 0
assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA_delay[65]; // rv 0
assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA_delay[66]; // rv 0
assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA_delay[67]; // rv 0
assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA_delay[68]; // rv 0
assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA_delay[69]; // rv 0
assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA_delay[6]; // rv 0
assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA_delay[70]; // rv 0
assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA_delay[71]; // rv 0
assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA_delay[72]; // rv 0
assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA_delay[73]; // rv 0
assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA_delay[74]; // rv 0
assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA_delay[75]; // rv 0
assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA_delay[76]; // rv 0
assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA_delay[77]; // rv 0
assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA_delay[78]; // rv 0
assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA_delay[79]; // rv 0
assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA_delay[7]; // rv 0
assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA_delay[80]; // rv 0
assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA_delay[81]; // rv 0
assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA_delay[82]; // rv 0
assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA_delay[83]; // rv 0
assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA_delay[84]; // rv 0
assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA_delay[85]; // rv 0
assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA_delay[86]; // rv 0
assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA_delay[87]; // rv 0
assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA_delay[88]; // rv 0
assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA_delay[89]; // rv 0
assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA_delay[8]; // rv 0
assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA_delay[90]; // rv 0
assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA_delay[91]; // rv 0
assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA_delay[92]; // rv 0
assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA_delay[93]; // rv 0
assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA_delay[94]; // rv 0
assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA_delay[95]; // rv 0
assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA_delay[96]; // rv 0
assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA_delay[97]; // rv 0
assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA_delay[98]; // rv 0
assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA_delay[99]; // rv 0
assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA_delay[9]; // rv 0
assign TXDCCFORCESTART_in = (TXDCCFORCESTART !== 1'bz) && TXDCCFORCESTART_delay; // rv 0
assign TXDCCRESET_in = (TXDCCRESET !== 1'bz) && TXDCCRESET_delay; // rv 0
assign TXDEEMPH_in = (TXDEEMPH !== 1'bz) && TXDEEMPH_delay; // rv 0
assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX_delay; // rv 0
assign TXDIFFCTRL_in[0] = (TXDIFFCTRL[0] !== 1'bz) && TXDIFFCTRL_delay[0]; // rv 0
assign TXDIFFCTRL_in[1] = (TXDIFFCTRL[1] !== 1'bz) && TXDIFFCTRL_delay[1]; // rv 0
assign TXDIFFCTRL_in[2] = (TXDIFFCTRL[2] !== 1'bz) && TXDIFFCTRL_delay[2]; // rv 0
assign TXDIFFCTRL_in[3] = (TXDIFFCTRL[3] !== 1'bz) && TXDIFFCTRL_delay[3]; // rv 0
assign TXDIFFCTRL_in[4] = (TXDIFFCTRL[4] !== 1'bz) && TXDIFFCTRL_delay[4]; // rv 0
assign TXDIFFPD_in = (TXDIFFPD !== 1'bz) && TXDIFFPD_delay; // rv 0
assign TXDLYBYPASS_in = (TXDLYBYPASS !== 1'bz) && TXDLYBYPASS_delay; // rv 0
assign TXDLYEN_in = (TXDLYEN !== 1'bz) && TXDLYEN_delay; // rv 0
assign TXDLYHOLD_in = (TXDLYHOLD !== 1'bz) && TXDLYHOLD_delay; // rv 0
assign TXDLYOVRDEN_in = (TXDLYOVRDEN !== 1'bz) && TXDLYOVRDEN_delay; // rv 0
assign TXDLYSRESET_in = (TXDLYSRESET !== 1'bz) && TXDLYSRESET_delay; // rv 0
assign TXDLYUPDOWN_in = (TXDLYUPDOWN !== 1'bz) && TXDLYUPDOWN_delay; // rv 0
assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE_delay; // rv 0
assign TXELFORCESTART_in = (TXELFORCESTART !== 1'bz) && TXELFORCESTART_delay; // rv 0
assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER_delay[0]; // rv 0
assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER_delay[1]; // rv 0
assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER_delay[2]; // rv 0
assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER_delay[3]; // rv 0
assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER_delay[4]; // rv 0
assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER_delay[5]; // rv 0
assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT_delay; // rv 0
assign TXLATCLK_in = (TXLATCLK !== 1'bz) && TXLATCLK_delay; // rv 0
assign TXMAINCURSOR_in[0] = (TXMAINCURSOR[0] !== 1'bz) && TXMAINCURSOR_delay[0]; // rv 0
assign TXMAINCURSOR_in[1] = (TXMAINCURSOR[1] !== 1'bz) && TXMAINCURSOR_delay[1]; // rv 0
assign TXMAINCURSOR_in[2] = (TXMAINCURSOR[2] !== 1'bz) && TXMAINCURSOR_delay[2]; // rv 0
assign TXMAINCURSOR_in[3] = (TXMAINCURSOR[3] !== 1'bz) && TXMAINCURSOR_delay[3]; // rv 0
assign TXMAINCURSOR_in[4] = (TXMAINCURSOR[4] !== 1'bz) && TXMAINCURSOR_delay[4]; // rv 0
assign TXMAINCURSOR_in[5] = (TXMAINCURSOR[5] !== 1'bz) && TXMAINCURSOR_delay[5]; // rv 0
assign TXMAINCURSOR_in[6] = (TXMAINCURSOR[6] !== 1'bz) && TXMAINCURSOR_delay[6]; // rv 0
assign TXMARGIN_in[0] = (TXMARGIN[0] !== 1'bz) && TXMARGIN_delay[0]; // rv 0
assign TXMARGIN_in[1] = (TXMARGIN[1] !== 1'bz) && TXMARGIN_delay[1]; // rv 0
assign TXMARGIN_in[2] = (TXMARGIN[2] !== 1'bz) && TXMARGIN_delay[2]; // rv 0
assign TXOUTCLKSEL_in[0] = (TXOUTCLKSEL[0] !== 1'bz) && TXOUTCLKSEL_delay[0]; // rv 0
assign TXOUTCLKSEL_in[1] = (TXOUTCLKSEL[1] !== 1'bz) && TXOUTCLKSEL_delay[1]; // rv 0
assign TXOUTCLKSEL_in[2] = (TXOUTCLKSEL[2] !== 1'bz) && TXOUTCLKSEL_delay[2]; // rv 0
assign TXPCSRESET_in = (TXPCSRESET !== 1'bz) && TXPCSRESET_delay; // rv 0
assign TXPDELECIDLEMODE_in = (TXPDELECIDLEMODE !== 1'bz) && TXPDELECIDLEMODE_delay; // rv 0
assign TXPD_in[0] = (TXPD[0] !== 1'bz) && TXPD_delay[0]; // rv 0
assign TXPD_in[1] = (TXPD[1] !== 1'bz) && TXPD_delay[1]; // rv 0
assign TXPHALIGNEN_in = (TXPHALIGNEN !== 1'bz) && TXPHALIGNEN_delay; // rv 0
assign TXPHALIGN_in = (TXPHALIGN !== 1'bz) && TXPHALIGN_delay; // rv 0
assign TXPHDLYPD_in = (TXPHDLYPD !== 1'bz) && TXPHDLYPD_delay; // rv 0
assign TXPHDLYRESET_in = (TXPHDLYRESET !== 1'bz) && TXPHDLYRESET_delay; // rv 0
assign TXPHDLYTSTCLK_in = (TXPHDLYTSTCLK !== 1'bz) && TXPHDLYTSTCLK_delay; // rv 0
assign TXPHINIT_in = (TXPHINIT !== 1'bz) && TXPHINIT_delay; // rv 0
assign TXPHOVRDEN_in = (TXPHOVRDEN !== 1'bz) && TXPHOVRDEN_delay; // rv 0
assign TXPIPPMEN_in = (TXPIPPMEN !== 1'bz) && TXPIPPMEN_delay; // rv 0
assign TXPIPPMOVRDEN_in = (TXPIPPMOVRDEN !== 1'bz) && TXPIPPMOVRDEN_delay; // rv 0
assign TXPIPPMPD_in = (TXPIPPMPD !== 1'bz) && TXPIPPMPD_delay; // rv 0
assign TXPIPPMSEL_in = (TXPIPPMSEL !== 1'bz) && TXPIPPMSEL_delay; // rv 0
assign TXPIPPMSTEPSIZE_in[0] = (TXPIPPMSTEPSIZE[0] !== 1'bz) && TXPIPPMSTEPSIZE_delay[0]; // rv 0
assign TXPIPPMSTEPSIZE_in[1] = (TXPIPPMSTEPSIZE[1] !== 1'bz) && TXPIPPMSTEPSIZE_delay[1]; // rv 0
assign TXPIPPMSTEPSIZE_in[2] = (TXPIPPMSTEPSIZE[2] !== 1'bz) && TXPIPPMSTEPSIZE_delay[2]; // rv 0
assign TXPIPPMSTEPSIZE_in[3] = (TXPIPPMSTEPSIZE[3] !== 1'bz) && TXPIPPMSTEPSIZE_delay[3]; // rv 0
assign TXPIPPMSTEPSIZE_in[4] = (TXPIPPMSTEPSIZE[4] !== 1'bz) && TXPIPPMSTEPSIZE_delay[4]; // rv 0
assign TXPISOPD_in = (TXPISOPD !== 1'bz) && TXPISOPD_delay; // rv 0
assign TXPLLCLKSEL_in[0] = (TXPLLCLKSEL[0] !== 1'bz) && TXPLLCLKSEL_delay[0]; // rv 0
assign TXPLLCLKSEL_in[1] = (TXPLLCLKSEL[1] !== 1'bz) && TXPLLCLKSEL_delay[1]; // rv 0
assign TXPMARESET_in = (TXPMARESET !== 1'bz) && TXPMARESET_delay; // rv 0
assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY_delay; // rv 0
assign TXPOSTCURSOR_in[0] = (TXPOSTCURSOR[0] !== 1'bz) && TXPOSTCURSOR_delay[0]; // rv 0
assign TXPOSTCURSOR_in[1] = (TXPOSTCURSOR[1] !== 1'bz) && TXPOSTCURSOR_delay[1]; // rv 0
assign TXPOSTCURSOR_in[2] = (TXPOSTCURSOR[2] !== 1'bz) && TXPOSTCURSOR_delay[2]; // rv 0
assign TXPOSTCURSOR_in[3] = (TXPOSTCURSOR[3] !== 1'bz) && TXPOSTCURSOR_delay[3]; // rv 0
assign TXPOSTCURSOR_in[4] = (TXPOSTCURSOR[4] !== 1'bz) && TXPOSTCURSOR_delay[4]; // rv 0
assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR_delay; // rv 0
assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL_delay[0]; // rv 0
assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL_delay[1]; // rv 0
assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL_delay[2]; // rv 0
assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL_delay[3]; // rv 0
assign TXPRECURSOR_in[0] = (TXPRECURSOR[0] !== 1'bz) && TXPRECURSOR_delay[0]; // rv 0
assign TXPRECURSOR_in[1] = (TXPRECURSOR[1] !== 1'bz) && TXPRECURSOR_delay[1]; // rv 0
assign TXPRECURSOR_in[2] = (TXPRECURSOR[2] !== 1'bz) && TXPRECURSOR_delay[2]; // rv 0
assign TXPRECURSOR_in[3] = (TXPRECURSOR[3] !== 1'bz) && TXPRECURSOR_delay[3]; // rv 0
assign TXPRECURSOR_in[4] = (TXPRECURSOR[4] !== 1'bz) && TXPRECURSOR_delay[4]; // rv 0
assign TXPROGDIVRESET_in = (TXPROGDIVRESET !== 1'bz) && TXPROGDIVRESET_delay; // rv 0
assign TXRATEMODE_in = (TXRATEMODE !== 1'bz) && TXRATEMODE_delay; // rv 0
assign TXRATE_in[0] = (TXRATE[0] !== 1'bz) && TXRATE_delay[0]; // rv 0
assign TXRATE_in[1] = (TXRATE[1] !== 1'bz) && TXRATE_delay[1]; // rv 0
assign TXRATE_in[2] = (TXRATE[2] !== 1'bz) && TXRATE_delay[2]; // rv 0
assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE_delay[0]; // rv 0
assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE_delay[1]; // rv 0
assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE_delay[2]; // rv 0
assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE_delay[3]; // rv 0
assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE_delay[4]; // rv 0
assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE_delay[5]; // rv 0
assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE_delay[6]; // rv 0
assign TXSWING_in = (TXSWING !== 1'bz) && TXSWING_delay; // rv 0
assign TXSYNCALLIN_in = (TXSYNCALLIN !== 1'bz) && TXSYNCALLIN_delay; // rv 0
assign TXSYNCIN_in = (TXSYNCIN !== 1'bz) && TXSYNCIN_delay; // rv 0
assign TXSYNCMODE_in = (TXSYNCMODE === 1'bz) || TXSYNCMODE_delay; // rv 1
assign TXSYSCLKSEL_in[0] = (TXSYSCLKSEL[0] !== 1'bz) && TXSYSCLKSEL_delay[0]; // rv 0
assign TXSYSCLKSEL_in[1] = (TXSYSCLKSEL[1] !== 1'bz) && TXSYSCLKSEL_delay[1]; // rv 0
assign TXUSERRDY_in = (TXUSERRDY !== 1'bz) && TXUSERRDY_delay; // rv 0
assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2_delay; // rv 0
assign TXUSRCLK_in = (TXUSRCLK !== 1'bz) && TXUSRCLK_delay; // rv 0
initial begin
#1;
trig_attr = ~trig_attr;
end
assign RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000;
assign SIM_VERSION_BIN = SIM_VERSION_REG * 1000;
assign TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000;
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CLK_COR_MAX_LAT_REG < 3) || (CLK_COR_MAX_LAT_REG > 60))) begin
$display("Error: [Unisim %s-301] CLK_COR_MAX_LAT attribute is set to %d. Legal values for this attribute are 3 to 60. Instance: %m", MODULE_NAME, CLK_COR_MAX_LAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_MIN_LAT_REG < 3) || (CLK_COR_MIN_LAT_REG > 63))) begin
$display("Error: [Unisim %s-302] CLK_COR_MIN_LAT attribute is set to %d. Legal values for this attribute are 3 to 63. Instance: %m", MODULE_NAME, CLK_COR_MIN_LAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_REPEAT_WAIT_REG < 0) || (CLK_COR_REPEAT_WAIT_REG > 31))) begin
$display("Error: [Unisim %s-304] CLK_COR_REPEAT_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, CLK_COR_REPEAT_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DDI_REALIGN_WAIT_REG < 0) || (DDI_REALIGN_WAIT_REG > 31))) begin
$display("Error: [Unisim %s-330] DDI_REALIGN_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, DDI_REALIGN_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_OVFLW_REG < 0) || (RXBUF_THRESH_OVFLW_REG > 63))) begin
$display("Error: [Unisim %s-444] RXBUF_THRESH_OVFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVFLW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_UNDFLW_REG < 0) || (RXBUF_THRESH_UNDFLW_REG > 63))) begin
$display("Error: [Unisim %s-446] RXBUF_THRESH_UNDFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_UNDFLW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPRBS_LINKACQ_CNT_REG < 15) || (RXPRBS_LINKACQ_CNT_REG > 255))) begin
$display("Error: [Unisim %s-549] RXPRBS_LINKACQ_CNT attribute is set to %d. Legal values for this attribute are 15 to 255. Instance: %m", MODULE_NAME, RXPRBS_LINKACQ_CNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CLK25_DIV_REG < 1) || (RX_CLK25_DIV_REG > 32))) begin
$display("Error: [Unisim %s-559] RX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SIG_VALID_DLY_REG < 1) || (RX_SIG_VALID_DLY_REG > 32))) begin
$display("Error: [Unisim %s-601] RX_SIG_VALID_DLY attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_SIG_VALID_DLY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SAS_MAX_COM_REG < 1) || (SAS_MAX_COM_REG > 127))) begin
$display("Error: [Unisim %s-613] SAS_MAX_COM attribute is set to %d. Legal values for this attribute are 1 to 127. Instance: %m", MODULE_NAME, SAS_MAX_COM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SAS_MIN_COM_REG < 1) || (SAS_MIN_COM_REG > 63))) begin
$display("Error: [Unisim %s-614] SAS_MIN_COM attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SAS_MIN_COM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MAX_BURST_REG < 1) || (SATA_MAX_BURST_REG > 63))) begin
$display("Error: [Unisim %s-619] SATA_MAX_BURST attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_BURST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MAX_INIT_REG < 1) || (SATA_MAX_INIT_REG > 63))) begin
$display("Error: [Unisim %s-620] SATA_MAX_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_INIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MAX_WAKE_REG < 1) || (SATA_MAX_WAKE_REG > 63))) begin
$display("Error: [Unisim %s-621] SATA_MAX_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MAX_WAKE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MIN_BURST_REG < 1) || (SATA_MIN_BURST_REG > 61))) begin
$display("Error: [Unisim %s-622] SATA_MIN_BURST attribute is set to %d. Legal values for this attribute are 1 to 61. Instance: %m", MODULE_NAME, SATA_MIN_BURST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MIN_INIT_REG < 1) || (SATA_MIN_INIT_REG > 63))) begin
$display("Error: [Unisim %s-623] SATA_MIN_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MIN_INIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_MIN_WAKE_REG < 1) || (SATA_MIN_WAKE_REG > 63))) begin
$display("Error: [Unisim %s-624] SATA_MIN_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, SATA_MIN_WAKE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_CLK25_DIV_REG < 1) || (TX_CLK25_DIV_REG > 32))) begin
$display("Error: [Unisim %s-670] TX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, TX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ACJTAG_DEBUG_MODE_REG !== 1'b0) && (ACJTAG_DEBUG_MODE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-101] ACJTAG_DEBUG_MODE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ACJTAG_DEBUG_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ACJTAG_MODE_REG !== 1'b0) && (ACJTAG_MODE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-102] ACJTAG_MODE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ACJTAG_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ACJTAG_RESET_REG !== 1'b0) && (ACJTAG_RESET_REG !== 1'b1))) begin
$display("Error: [Unisim %s-103] ACJTAG_RESET attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ACJTAG_RESET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ADAPT_CFG0_REG < 16'h0000) || (ADAPT_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-104] ADAPT_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ADAPT_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ADAPT_CFG1_REG < 16'h0000) || (ADAPT_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-105] ADAPT_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ADAPT_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ADAPT_CFG2_REG < 16'b0000000000000000) || (ADAPT_CFG2_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-106] ADAPT_CFG2 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, ADAPT_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_DOUBLE_REG != "FALSE") &&
(ALIGN_COMMA_DOUBLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-131] ALIGN_COMMA_DOUBLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ALIGN_COMMA_DOUBLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_ENABLE_REG < 10'b0000000000) || (ALIGN_COMMA_ENABLE_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-132] ALIGN_COMMA_ENABLE attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, ALIGN_COMMA_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_WORD_REG != 1) &&
(ALIGN_COMMA_WORD_REG != 2) &&
(ALIGN_COMMA_WORD_REG != 4))) begin
$display("Error: [Unisim %s-133] ALIGN_COMMA_WORD attribute is set to %d. Legal values for this attribute are 1, 2 or 4. Instance: %m", MODULE_NAME, ALIGN_COMMA_WORD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_MCOMMA_DET_REG != "TRUE") &&
(ALIGN_MCOMMA_DET_REG != "FALSE"))) begin
$display("Error: [Unisim %s-134] ALIGN_MCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_MCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_MCOMMA_VALUE_REG < 10'b0000000000) || (ALIGN_MCOMMA_VALUE_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-135] ALIGN_MCOMMA_VALUE attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, ALIGN_MCOMMA_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_PCOMMA_DET_REG != "TRUE") &&
(ALIGN_PCOMMA_DET_REG != "FALSE"))) begin
$display("Error: [Unisim %s-136] ALIGN_PCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_PCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_PCOMMA_VALUE_REG < 10'b0000000000) || (ALIGN_PCOMMA_VALUE_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-137] ALIGN_PCOMMA_VALUE attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, ALIGN_PCOMMA_VALUE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((AUTO_BW_SEL_BYPASS_REG !== 1'b0) && (AUTO_BW_SEL_BYPASS_REG !== 1'b1))) begin
$display("Error: [Unisim %s-139] AUTO_BW_SEL_BYPASS attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, AUTO_BW_SEL_BYPASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((A_RXOSCALRESET_REG !== 1'b0) && (A_RXOSCALRESET_REG !== 1'b1))) begin
$display("Error: [Unisim %s-219] A_RXOSCALRESET attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, A_RXOSCALRESET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((A_RXPROGDIVRESET_REG !== 1'b0) && (A_RXPROGDIVRESET_REG !== 1'b1))) begin
$display("Error: [Unisim %s-235] A_RXPROGDIVRESET attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, A_RXPROGDIVRESET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((A_TXDIFFCTRL_REG < 5'b00000) || (A_TXDIFFCTRL_REG > 5'b11111))) begin
$display("Error: [Unisim %s-239] A_TXDIFFCTRL attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, A_TXDIFFCTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((A_TXPROGDIVRESET_REG !== 1'b0) && (A_TXPROGDIVRESET_REG !== 1'b1))) begin
$display("Error: [Unisim %s-267] A_TXPROGDIVRESET attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, A_TXPROGDIVRESET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CAPBYPASS_FORCE_REG !== 1'b0) && (CAPBYPASS_FORCE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-270] CAPBYPASS_FORCE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, CAPBYPASS_FORCE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CBCC_DATA_SOURCE_SEL_REG != "DECODED") &&
(CBCC_DATA_SOURCE_SEL_REG != "ENCODED"))) begin
$display("Error: [Unisim %s-271] CBCC_DATA_SOURCE_SEL attribute is set to %s. Legal values for this attribute are DECODED or ENCODED. Instance: %m", MODULE_NAME, CBCC_DATA_SOURCE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CDR_SWAP_MODE_EN_REG !== 1'b0) && (CDR_SWAP_MODE_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-272] CDR_SWAP_MODE_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, CDR_SWAP_MODE_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_KEEP_ALIGN_REG != "FALSE") &&
(CHAN_BOND_KEEP_ALIGN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-273] CHAN_BOND_KEEP_ALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_MAX_SKEW_REG != 7) &&
(CHAN_BOND_MAX_SKEW_REG != 1) &&
(CHAN_BOND_MAX_SKEW_REG != 2) &&
(CHAN_BOND_MAX_SKEW_REG != 3) &&
(CHAN_BOND_MAX_SKEW_REG != 4) &&
(CHAN_BOND_MAX_SKEW_REG != 5) &&
(CHAN_BOND_MAX_SKEW_REG != 6) &&
(CHAN_BOND_MAX_SKEW_REG != 8) &&
(CHAN_BOND_MAX_SKEW_REG != 9) &&
(CHAN_BOND_MAX_SKEW_REG != 10) &&
(CHAN_BOND_MAX_SKEW_REG != 11) &&
(CHAN_BOND_MAX_SKEW_REG != 12) &&
(CHAN_BOND_MAX_SKEW_REG != 13) &&
(CHAN_BOND_MAX_SKEW_REG != 14))) begin
$display("Error: [Unisim %s-274] CHAN_BOND_MAX_SKEW attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13 or 14. Instance: %m", MODULE_NAME, CHAN_BOND_MAX_SKEW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_1_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_1_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-275] CHAN_BOND_SEQ_1_1 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_2_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_2_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-276] CHAN_BOND_SEQ_1_2 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_3_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_3_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-277] CHAN_BOND_SEQ_1_3 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_4_REG < 10'b0000000000) || (CHAN_BOND_SEQ_1_4_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-278] CHAN_BOND_SEQ_1_4 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_1_ENABLE_REG < 4'b0000) || (CHAN_BOND_SEQ_1_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-279] CHAN_BOND_SEQ_1_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_1_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_1_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_1_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-280] CHAN_BOND_SEQ_2_1 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_2_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_2_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-281] CHAN_BOND_SEQ_2_2 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_3_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_3_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-282] CHAN_BOND_SEQ_2_3 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_4_REG < 10'b0000000000) || (CHAN_BOND_SEQ_2_4_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-283] CHAN_BOND_SEQ_2_4 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_ENABLE_REG < 4'b0000) || (CHAN_BOND_SEQ_2_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-284] CHAN_BOND_SEQ_2_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_USE_REG != "FALSE") &&
(CHAN_BOND_SEQ_2_USE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-285] CHAN_BOND_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_LEN_REG != 2) &&
(CHAN_BOND_SEQ_LEN_REG != 1) &&
(CHAN_BOND_SEQ_LEN_REG != 3) &&
(CHAN_BOND_SEQ_LEN_REG != 4))) begin
$display("Error: [Unisim %s-286] CHAN_BOND_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CH_HSPMUX_REG < 16'h0000) || (CH_HSPMUX_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-287] CH_HSPMUX attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CH_HSPMUX_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CKCAL1_CFG_0_REG < 16'b0000000000000000) || (CKCAL1_CFG_0_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-288] CKCAL1_CFG_0 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, CKCAL1_CFG_0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CKCAL1_CFG_1_REG < 16'b0000000000000000) || (CKCAL1_CFG_1_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-289] CKCAL1_CFG_1 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, CKCAL1_CFG_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CKCAL1_CFG_2_REG < 16'b0000000000000000) || (CKCAL1_CFG_2_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-290] CKCAL1_CFG_2 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, CKCAL1_CFG_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CKCAL1_CFG_3_REG < 16'b0000000000000000) || (CKCAL1_CFG_3_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-291] CKCAL1_CFG_3 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, CKCAL1_CFG_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CKCAL2_CFG_0_REG < 16'b0000000000000000) || (CKCAL2_CFG_0_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-292] CKCAL2_CFG_0 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, CKCAL2_CFG_0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CKCAL2_CFG_1_REG < 16'b0000000000000000) || (CKCAL2_CFG_1_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-293] CKCAL2_CFG_1 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, CKCAL2_CFG_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CKCAL2_CFG_2_REG < 16'b0000000000000000) || (CKCAL2_CFG_2_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-294] CKCAL2_CFG_2 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, CKCAL2_CFG_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CKCAL2_CFG_3_REG < 16'b0000000000000000) || (CKCAL2_CFG_3_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-295] CKCAL2_CFG_3 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, CKCAL2_CFG_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CKCAL2_CFG_4_REG < 16'b0000000000000000) || (CKCAL2_CFG_4_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-296] CKCAL2_CFG_4 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, CKCAL2_CFG_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CKCAL_RSVD0_REG < 16'h0000) || (CKCAL_RSVD0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-297] CKCAL_RSVD0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CKCAL_RSVD0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CKCAL_RSVD1_REG < 16'h0000) || (CKCAL_RSVD1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-298] CKCAL_RSVD1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CKCAL_RSVD1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_CORRECT_USE_REG != "TRUE") &&
(CLK_CORRECT_USE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-299] CLK_CORRECT_USE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_CORRECT_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_KEEP_IDLE_REG != "FALSE") &&
(CLK_COR_KEEP_IDLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-300] CLK_COR_KEEP_IDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_KEEP_IDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_PRECEDENCE_REG != "TRUE") &&
(CLK_COR_PRECEDENCE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-303] CLK_COR_PRECEDENCE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_COR_PRECEDENCE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_1_REG < 10'b0000000000) || (CLK_COR_SEQ_1_1_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-305] CLK_COR_SEQ_1_1 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_2_REG < 10'b0000000000) || (CLK_COR_SEQ_1_2_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-306] CLK_COR_SEQ_1_2 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_3_REG < 10'b0000000000) || (CLK_COR_SEQ_1_3_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-307] CLK_COR_SEQ_1_3 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_4_REG < 10'b0000000000) || (CLK_COR_SEQ_1_4_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-308] CLK_COR_SEQ_1_4 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_1_ENABLE_REG < 4'b0000) || (CLK_COR_SEQ_1_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-309] CLK_COR_SEQ_1_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_1_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_1_REG < 10'b0000000000) || (CLK_COR_SEQ_2_1_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-310] CLK_COR_SEQ_2_1 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_2_REG < 10'b0000000000) || (CLK_COR_SEQ_2_2_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-311] CLK_COR_SEQ_2_2 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_3_REG < 10'b0000000000) || (CLK_COR_SEQ_2_3_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-312] CLK_COR_SEQ_2_3 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_4_REG < 10'b0000000000) || (CLK_COR_SEQ_2_4_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-313] CLK_COR_SEQ_2_4 attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_ENABLE_REG < 4'b0000) || (CLK_COR_SEQ_2_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-314] CLK_COR_SEQ_2_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_USE_REG != "FALSE") &&
(CLK_COR_SEQ_2_USE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-315] CLK_COR_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_LEN_REG != 2) &&
(CLK_COR_SEQ_LEN_REG != 1) &&
(CLK_COR_SEQ_LEN_REG != 3) &&
(CLK_COR_SEQ_LEN_REG != 4))) begin
$display("Error: [Unisim %s-316] CLK_COR_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CLK_COR_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_CFG0_REG < 16'h0000) || (CPLL_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-317] CPLL_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_CFG1_REG < 16'h0000) || (CPLL_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-318] CPLL_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_CFG2_REG < 16'h0000) || (CPLL_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-319] CPLL_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_CFG3_REG < 6'h00) || (CPLL_CFG3_REG > 6'h3F))) begin
$display("Error: [Unisim %s-320] CPLL_CFG3 attribute is set to %h. Legal values for this attribute are 6'h00 to 6'h3F. Instance: %m", MODULE_NAME, CPLL_CFG3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_FBDIV_45_REG != 4) &&
(CPLL_FBDIV_45_REG != 5))) begin
$display("Error: [Unisim %s-322] CPLL_FBDIV_45 attribute is set to %d. Legal values for this attribute are 4 or 5. Instance: %m", MODULE_NAME, CPLL_FBDIV_45_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_FBDIV_REG != 4) &&
(CPLL_FBDIV_REG != 1) &&
(CPLL_FBDIV_REG != 2) &&
(CPLL_FBDIV_REG != 3) &&
(CPLL_FBDIV_REG != 5) &&
(CPLL_FBDIV_REG != 6) &&
(CPLL_FBDIV_REG != 8) &&
(CPLL_FBDIV_REG != 10) &&
(CPLL_FBDIV_REG != 12) &&
(CPLL_FBDIV_REG != 16) &&
(CPLL_FBDIV_REG != 20))) begin
$display("Error: [Unisim %s-321] CPLL_FBDIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 3, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_FBDIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_INIT_CFG0_REG < 16'h0000) || (CPLL_INIT_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-323] CPLL_INIT_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_INIT_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_INIT_CFG1_REG < 8'h00) || (CPLL_INIT_CFG1_REG > 8'hFF))) begin
$display("Error: [Unisim %s-324] CPLL_INIT_CFG1 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, CPLL_INIT_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_LOCK_CFG_REG < 16'h0000) || (CPLL_LOCK_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-325] CPLL_LOCK_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, CPLL_LOCK_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_REFCLK_DIV_REG != 1) &&
(CPLL_REFCLK_DIV_REG != 2) &&
(CPLL_REFCLK_DIV_REG != 3) &&
(CPLL_REFCLK_DIV_REG != 4) &&
(CPLL_REFCLK_DIV_REG != 5) &&
(CPLL_REFCLK_DIV_REG != 6) &&
(CPLL_REFCLK_DIV_REG != 8) &&
(CPLL_REFCLK_DIV_REG != 10) &&
(CPLL_REFCLK_DIV_REG != 12) &&
(CPLL_REFCLK_DIV_REG != 16) &&
(CPLL_REFCLK_DIV_REG != 20))) begin
$display("Error: [Unisim %s-326] CPLL_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_REFCLK_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTLE3_OCAP_EXT_CTRL_REG < 3'b000) || (CTLE3_OCAP_EXT_CTRL_REG > 3'b111))) begin
$display("Error: [Unisim %s-327] CTLE3_OCAP_EXT_CTRL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, CTLE3_OCAP_EXT_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CTLE3_OCAP_EXT_EN_REG !== 1'b0) && (CTLE3_OCAP_EXT_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-328] CTLE3_OCAP_EXT_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, CTLE3_OCAP_EXT_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DDI_CTRL_REG < 2'b00) || (DDI_CTRL_REG > 2'b11))) begin
$display("Error: [Unisim %s-329] DDI_CTRL attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, DDI_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_MCOMMA_DETECT_REG != "TRUE") &&
(DEC_MCOMMA_DETECT_REG != "FALSE"))) begin
$display("Error: [Unisim %s-331] DEC_MCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_MCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_PCOMMA_DETECT_REG != "TRUE") &&
(DEC_PCOMMA_DETECT_REG != "FALSE"))) begin
$display("Error: [Unisim %s-332] DEC_PCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_PCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_VALID_COMMA_ONLY_REG != "TRUE") &&
(DEC_VALID_COMMA_ONLY_REG != "FALSE"))) begin
$display("Error: [Unisim %s-333] DEC_VALID_COMMA_ONLY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_VALID_COMMA_ONLY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DFE_D_X_REL_POS_REG !== 1'b0) && (DFE_D_X_REL_POS_REG !== 1'b1))) begin
$display("Error: [Unisim %s-334] DFE_D_X_REL_POS attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, DFE_D_X_REL_POS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DFE_VCM_COMP_EN_REG !== 1'b0) && (DFE_VCM_COMP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-335] DFE_VCM_COMP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, DFE_VCM_COMP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DMONITOR_CFG0_REG < 10'h000) || (DMONITOR_CFG0_REG > 10'h3FF))) begin
$display("Error: [Unisim %s-336] DMONITOR_CFG0 attribute is set to %h. Legal values for this attribute are 10'h000 to 10'h3FF. Instance: %m", MODULE_NAME, DMONITOR_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DMONITOR_CFG1_REG < 8'h00) || (DMONITOR_CFG1_REG > 8'hFF))) begin
$display("Error: [Unisim %s-337] DMONITOR_CFG1 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, DMONITOR_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_CLK_PHASE_SEL_REG !== 1'b0) && (ES_CLK_PHASE_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-338] ES_CLK_PHASE_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ES_CLK_PHASE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_CONTROL_REG < 6'b000000) || (ES_CONTROL_REG > 6'b111111))) begin
$display("Error: [Unisim %s-339] ES_CONTROL attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, ES_CONTROL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_ERRDET_EN_REG != "FALSE") &&
(ES_ERRDET_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-340] ES_ERRDET_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_ERRDET_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_EYE_SCAN_EN_REG != "FALSE") &&
(ES_EYE_SCAN_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-341] ES_EYE_SCAN_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_EYE_SCAN_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_HORZ_OFFSET_REG < 12'h000) || (ES_HORZ_OFFSET_REG > 12'hFFF))) begin
$display("Error: [Unisim %s-342] ES_HORZ_OFFSET attribute is set to %h. Legal values for this attribute are 12'h000 to 12'hFFF. Instance: %m", MODULE_NAME, ES_HORZ_OFFSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_PMA_CFG_REG < 10'b0000000000) || (ES_PMA_CFG_REG > 10'b1111111111))) begin
$display("Error: [Unisim %s-343] ES_PMA_CFG attribute is set to %b. Legal values for this attribute are 10'b0000000000 to 10'b1111111111. Instance: %m", MODULE_NAME, ES_PMA_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_PRESCALE_REG < 5'b00000) || (ES_PRESCALE_REG > 5'b11111))) begin
$display("Error: [Unisim %s-344] ES_PRESCALE attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, ES_PRESCALE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER0_REG < 16'h0000) || (ES_QUALIFIER0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-345] ES_QUALIFIER0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER1_REG < 16'h0000) || (ES_QUALIFIER1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-346] ES_QUALIFIER1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER2_REG < 16'h0000) || (ES_QUALIFIER2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-347] ES_QUALIFIER2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER3_REG < 16'h0000) || (ES_QUALIFIER3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-348] ES_QUALIFIER3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER4_REG < 16'h0000) || (ES_QUALIFIER4_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-349] ES_QUALIFIER4 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER5_REG < 16'h0000) || (ES_QUALIFIER5_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-350] ES_QUALIFIER5 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER6_REG < 16'h0000) || (ES_QUALIFIER6_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-351] ES_QUALIFIER6 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER6_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER7_REG < 16'h0000) || (ES_QUALIFIER7_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-352] ES_QUALIFIER7 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER7_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER8_REG < 16'h0000) || (ES_QUALIFIER8_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-353] ES_QUALIFIER8 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER8_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUALIFIER9_REG < 16'h0000) || (ES_QUALIFIER9_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-354] ES_QUALIFIER9 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUALIFIER9_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK0_REG < 16'h0000) || (ES_QUAL_MASK0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-355] ES_QUAL_MASK0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK1_REG < 16'h0000) || (ES_QUAL_MASK1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-356] ES_QUAL_MASK1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK2_REG < 16'h0000) || (ES_QUAL_MASK2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-357] ES_QUAL_MASK2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK3_REG < 16'h0000) || (ES_QUAL_MASK3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-358] ES_QUAL_MASK3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK4_REG < 16'h0000) || (ES_QUAL_MASK4_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-359] ES_QUAL_MASK4 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK5_REG < 16'h0000) || (ES_QUAL_MASK5_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-360] ES_QUAL_MASK5 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK6_REG < 16'h0000) || (ES_QUAL_MASK6_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-361] ES_QUAL_MASK6 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK6_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK7_REG < 16'h0000) || (ES_QUAL_MASK7_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-362] ES_QUAL_MASK7 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK7_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK8_REG < 16'h0000) || (ES_QUAL_MASK8_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-363] ES_QUAL_MASK8 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK8_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_QUAL_MASK9_REG < 16'h0000) || (ES_QUAL_MASK9_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-364] ES_QUAL_MASK9 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_QUAL_MASK9_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK0_REG < 16'h0000) || (ES_SDATA_MASK0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-365] ES_SDATA_MASK0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK1_REG < 16'h0000) || (ES_SDATA_MASK1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-366] ES_SDATA_MASK1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK2_REG < 16'h0000) || (ES_SDATA_MASK2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-367] ES_SDATA_MASK2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK3_REG < 16'h0000) || (ES_SDATA_MASK3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-368] ES_SDATA_MASK3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK4_REG < 16'h0000) || (ES_SDATA_MASK4_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-369] ES_SDATA_MASK4 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK5_REG < 16'h0000) || (ES_SDATA_MASK5_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-370] ES_SDATA_MASK5 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK6_REG < 16'h0000) || (ES_SDATA_MASK6_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-371] ES_SDATA_MASK6 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK6_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK7_REG < 16'h0000) || (ES_SDATA_MASK7_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-372] ES_SDATA_MASK7 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK7_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK8_REG < 16'h0000) || (ES_SDATA_MASK8_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-373] ES_SDATA_MASK8 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK8_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_SDATA_MASK9_REG < 16'h0000) || (ES_SDATA_MASK9_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-374] ES_SDATA_MASK9 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, ES_SDATA_MASK9_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EVODD_PHI_CFG_REG < 11'b00000000000) || (EVODD_PHI_CFG_REG > 11'b11111111111))) begin
$display("Error: [Unisim %s-375] EVODD_PHI_CFG attribute is set to %b. Legal values for this attribute are 11'b00000000000 to 11'b11111111111. Instance: %m", MODULE_NAME, EVODD_PHI_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EYE_SCAN_SWAP_EN_REG !== 1'b0) && (EYE_SCAN_SWAP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-376] EYE_SCAN_SWAP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, EYE_SCAN_SWAP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FTS_DESKEW_SEQ_ENABLE_REG < 4'b0000) || (FTS_DESKEW_SEQ_ENABLE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-377] FTS_DESKEW_SEQ_ENABLE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, FTS_DESKEW_SEQ_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FTS_LANE_DESKEW_CFG_REG < 4'b0000) || (FTS_LANE_DESKEW_CFG_REG > 4'b1111))) begin
$display("Error: [Unisim %s-378] FTS_LANE_DESKEW_CFG attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, FTS_LANE_DESKEW_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FTS_LANE_DESKEW_EN_REG != "FALSE") &&
(FTS_LANE_DESKEW_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-379] FTS_LANE_DESKEW_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FTS_LANE_DESKEW_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((GEARBOX_MODE_REG < 5'b00000) || (GEARBOX_MODE_REG > 5'b11111))) begin
$display("Error: [Unisim %s-380] GEARBOX_MODE attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, GEARBOX_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((GM_BIAS_SELECT_REG !== 1'b0) && (GM_BIAS_SELECT_REG !== 1'b1))) begin
$display("Error: [Unisim %s-383] GM_BIAS_SELECT attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, GM_BIAS_SELECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ISCAN_CK_PH_SEL2_REG !== 1'b0) && (ISCAN_CK_PH_SEL2_REG !== 1'b1))) begin
$display("Error: [Unisim %s-385] ISCAN_CK_PH_SEL2 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, ISCAN_CK_PH_SEL2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOCAL_MASTER_REG !== 1'b0) && (LOCAL_MASTER_REG !== 1'b1))) begin
$display("Error: [Unisim %s-386] LOCAL_MASTER attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, LOCAL_MASTER_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP0_CFG_REG < 16'h0000) || (LOOP0_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-387] LOOP0_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP0_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP10_CFG_REG < 16'h0000) || (LOOP10_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-388] LOOP10_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP10_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP11_CFG_REG < 16'h0000) || (LOOP11_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-389] LOOP11_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP11_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP12_CFG_REG < 16'h0000) || (LOOP12_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-390] LOOP12_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP12_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP13_CFG_REG < 16'h0000) || (LOOP13_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-391] LOOP13_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP13_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP1_CFG_REG < 16'h0000) || (LOOP1_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-392] LOOP1_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP1_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP2_CFG_REG < 16'h0000) || (LOOP2_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-393] LOOP2_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP2_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP3_CFG_REG < 16'h0000) || (LOOP3_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-394] LOOP3_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP3_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP4_CFG_REG < 16'h0000) || (LOOP4_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-395] LOOP4_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP4_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP5_CFG_REG < 16'h0000) || (LOOP5_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-396] LOOP5_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP5_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP6_CFG_REG < 16'h0000) || (LOOP6_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-397] LOOP6_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP6_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP7_CFG_REG < 16'h0000) || (LOOP7_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-398] LOOP7_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP7_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP8_CFG_REG < 16'h0000) || (LOOP8_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-399] LOOP8_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP8_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LOOP9_CFG_REG < 16'h0000) || (LOOP9_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-400] LOOP9_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, LOOP9_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LPBK_BIAS_CTRL_REG < 3'b000) || (LPBK_BIAS_CTRL_REG > 3'b111))) begin
$display("Error: [Unisim %s-401] LPBK_BIAS_CTRL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, LPBK_BIAS_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LPBK_EN_RCAL_B_REG !== 1'b0) && (LPBK_EN_RCAL_B_REG !== 1'b1))) begin
$display("Error: [Unisim %s-402] LPBK_EN_RCAL_B attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, LPBK_EN_RCAL_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LPBK_EXT_RCAL_REG < 4'b0000) || (LPBK_EXT_RCAL_REG > 4'b1111))) begin
$display("Error: [Unisim %s-403] LPBK_EXT_RCAL attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, LPBK_EXT_RCAL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LPBK_RG_CTRL_REG < 4'b0000) || (LPBK_RG_CTRL_REG > 4'b1111))) begin
$display("Error: [Unisim %s-404] LPBK_RG_CTRL attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, LPBK_RG_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OOBDIVCTL_REG < 2'b00) || (OOBDIVCTL_REG > 2'b11))) begin
$display("Error: [Unisim %s-405] OOBDIVCTL attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, OOBDIVCTL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OOB_PWRUP_REG !== 1'b0) && (OOB_PWRUP_REG !== 1'b1))) begin
$display("Error: [Unisim %s-406] OOB_PWRUP attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, OOB_PWRUP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_AUTO_REALIGN_REG != "FRST_SMPL") &&
(PCI3_AUTO_REALIGN_REG != "OVR_1K_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_8_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_64_BLK"))) begin
$display("Error: [Unisim %s-407] PCI3_AUTO_REALIGN attribute is set to %s. Legal values for this attribute are FRST_SMPL, OVR_1K_BLK, OVR_8_BLK or OVR_64_BLK. Instance: %m", MODULE_NAME, PCI3_AUTO_REALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_PIPE_RX_ELECIDLE_REG !== 1'b0) && (PCI3_PIPE_RX_ELECIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-408] PCI3_PIPE_RX_ELECIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, PCI3_PIPE_RX_ELECIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ASYNC_EBUF_BYPASS_REG < 2'b00) || (PCI3_RX_ASYNC_EBUF_BYPASS_REG > 2'b11))) begin
$display("Error: [Unisim %s-409] PCI3_RX_ASYNC_EBUF_BYPASS attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, PCI3_RX_ASYNC_EBUF_BYPASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_EI2_ENABLE_REG !== 1'b0) && (PCI3_RX_ELECIDLE_EI2_ENABLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-410] PCI3_RX_ELECIDLE_EI2_ENABLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_EI2_ENABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_H2L_COUNT_REG < 6'b000000) || (PCI3_RX_ELECIDLE_H2L_COUNT_REG > 6'b111111))) begin
$display("Error: [Unisim %s-411] PCI3_RX_ELECIDLE_H2L_COUNT attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_H2L_COUNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_H2L_DISABLE_REG < 3'b000) || (PCI3_RX_ELECIDLE_H2L_DISABLE_REG > 3'b111))) begin
$display("Error: [Unisim %s-412] PCI3_RX_ELECIDLE_H2L_DISABLE attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_H2L_DISABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_HI_COUNT_REG < 6'b000000) || (PCI3_RX_ELECIDLE_HI_COUNT_REG > 6'b111111))) begin
$display("Error: [Unisim %s-413] PCI3_RX_ELECIDLE_HI_COUNT attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_HI_COUNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_ELECIDLE_LP4_DISABLE_REG !== 1'b0) && (PCI3_RX_ELECIDLE_LP4_DISABLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-414] PCI3_RX_ELECIDLE_LP4_DISABLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, PCI3_RX_ELECIDLE_LP4_DISABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_RX_FIFO_DISABLE_REG !== 1'b0) && (PCI3_RX_FIFO_DISABLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-415] PCI3_RX_FIFO_DISABLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, PCI3_RX_FIFO_DISABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_BUFG_DIV_CTRL_REG < 16'h0000) || (PCIE_BUFG_DIV_CTRL_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-416] PCIE_BUFG_DIV_CTRL attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_BUFG_DIV_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_RXPCS_CFG_GEN3_REG < 16'h0000) || (PCIE_RXPCS_CFG_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-417] PCIE_RXPCS_CFG_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_RXPCS_CFG_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_RXPMA_CFG_REG < 16'h0000) || (PCIE_RXPMA_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-418] PCIE_RXPMA_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_RXPMA_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_TXPCS_CFG_GEN3_REG < 16'h0000) || (PCIE_TXPCS_CFG_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-419] PCIE_TXPCS_CFG_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_TXPCS_CFG_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_TXPMA_CFG_REG < 16'h0000) || (PCIE_TXPMA_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-420] PCIE_TXPMA_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PCIE_TXPMA_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCS_PCIE_EN_REG != "FALSE") &&
(PCS_PCIE_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-421] PCS_PCIE_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCS_PCIE_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCS_RSVD0_REG < 16'b0000000000000000) || (PCS_RSVD0_REG > 16'b1111111111111111))) begin
$display("Error: [Unisim %s-422] PCS_RSVD0 attribute is set to %b. Legal values for this attribute are 16'b0000000000000000 to 16'b1111111111111111. Instance: %m", MODULE_NAME, PCS_RSVD0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCS_RSVD1_REG < 3'b000) || (PCS_RSVD1_REG > 3'b111))) begin
$display("Error: [Unisim %s-423] PCS_RSVD1 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, PCS_RSVD1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PD_TRANS_TIME_FROM_P2_REG < 12'h000) || (PD_TRANS_TIME_FROM_P2_REG > 12'hFFF))) begin
$display("Error: [Unisim %s-424] PD_TRANS_TIME_FROM_P2 attribute is set to %h. Legal values for this attribute are 12'h000 to 12'hFFF. Instance: %m", MODULE_NAME, PD_TRANS_TIME_FROM_P2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PD_TRANS_TIME_NONE_P2_REG < 8'h00) || (PD_TRANS_TIME_NONE_P2_REG > 8'hFF))) begin
$display("Error: [Unisim %s-425] PD_TRANS_TIME_NONE_P2 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, PD_TRANS_TIME_NONE_P2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PD_TRANS_TIME_TO_P2_REG < 8'h00) || (PD_TRANS_TIME_TO_P2_REG > 8'hFF))) begin
$display("Error: [Unisim %s-426] PD_TRANS_TIME_TO_P2 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, PD_TRANS_TIME_TO_P2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PLL_SEL_MODE_GEN12_REG < 2'h0) || (PLL_SEL_MODE_GEN12_REG > 2'h3))) begin
$display("Error: [Unisim %s-427] PLL_SEL_MODE_GEN12 attribute is set to %h. Legal values for this attribute are 2'h0 to 2'h3. Instance: %m", MODULE_NAME, PLL_SEL_MODE_GEN12_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PLL_SEL_MODE_GEN3_REG < 2'h0) || (PLL_SEL_MODE_GEN3_REG > 2'h3))) begin
$display("Error: [Unisim %s-428] PLL_SEL_MODE_GEN3 attribute is set to %h. Legal values for this attribute are 2'h0 to 2'h3. Instance: %m", MODULE_NAME, PLL_SEL_MODE_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PMA_RSV0_REG < 16'h0000) || (PMA_RSV0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-429] PMA_RSV0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PMA_RSV0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PMA_RSV1_REG < 16'h0000) || (PMA_RSV1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-430] PMA_RSV1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, PMA_RSV1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PREIQ_FREQ_BST_REG != 0) &&
(PREIQ_FREQ_BST_REG != 1) &&
(PREIQ_FREQ_BST_REG != 2) &&
(PREIQ_FREQ_BST_REG != 3))) begin
$display("Error: [Unisim %s-431] PREIQ_FREQ_BST attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, PREIQ_FREQ_BST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PROCESS_PAR_REG < 3'b000) || (PROCESS_PAR_REG > 3'b111))) begin
$display("Error: [Unisim %s-432] PROCESS_PAR attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, PROCESS_PAR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RATE_SW_USE_DRP_REG !== 1'b0) && (RATE_SW_USE_DRP_REG !== 1'b1))) begin
$display("Error: [Unisim %s-433] RATE_SW_USE_DRP attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RATE_SW_USE_DRP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RESET_POWERSAVE_DISABLE_REG !== 1'b0) && (RESET_POWERSAVE_DISABLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-434] RESET_POWERSAVE_DISABLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RESET_POWERSAVE_DISABLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUFRESET_TIME_REG < 5'b00000) || (RXBUFRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-435] RXBUFRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXBUFRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_ADDR_MODE_REG != "FULL") &&
(RXBUF_ADDR_MODE_REG != "FAST"))) begin
$display("Error: [Unisim %s-436] RXBUF_ADDR_MODE attribute is set to %s. Legal values for this attribute are FULL or FAST. Instance: %m", MODULE_NAME, RXBUF_ADDR_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_EIDLE_HI_CNT_REG < 4'b0000) || (RXBUF_EIDLE_HI_CNT_REG > 4'b1111))) begin
$display("Error: [Unisim %s-437] RXBUF_EIDLE_HI_CNT attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RXBUF_EIDLE_HI_CNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_EIDLE_LO_CNT_REG < 4'b0000) || (RXBUF_EIDLE_LO_CNT_REG > 4'b1111))) begin
$display("Error: [Unisim %s-438] RXBUF_EIDLE_LO_CNT attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RXBUF_EIDLE_LO_CNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_EN_REG != "TRUE") &&
(RXBUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-439] RXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_CB_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_CB_CHANGE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-440] RXBUF_RESET_ON_CB_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_CB_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_COMMAALIGN_REG != "FALSE") &&
(RXBUF_RESET_ON_COMMAALIGN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-441] RXBUF_RESET_ON_COMMAALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_COMMAALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_EIDLE_REG != "FALSE") &&
(RXBUF_RESET_ON_EIDLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-442] RXBUF_RESET_ON_EIDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-443] RXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_OVRD_REG != "FALSE") &&
(RXBUF_THRESH_OVRD_REG != "TRUE"))) begin
$display("Error: [Unisim %s-445] RXBUF_THRESH_OVRD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDRFREQRESET_TIME_REG < 5'b00000) || (RXCDRFREQRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-447] RXCDRFREQRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXCDRFREQRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDRPHRESET_TIME_REG < 5'b00000) || (RXCDRPHRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-448] RXCDRPHRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXCDRPHRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG0_GEN3_REG < 16'h0000) || (RXCDR_CFG0_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-450] RXCDR_CFG0_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG0_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG0_REG < 16'h0000) || (RXCDR_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-449] RXCDR_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG1_GEN3_REG < 16'h0000) || (RXCDR_CFG1_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-452] RXCDR_CFG1_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG1_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG1_REG < 16'h0000) || (RXCDR_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-451] RXCDR_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG2_GEN3_REG < 16'h0000) || (RXCDR_CFG2_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-454] RXCDR_CFG2_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG2_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG2_REG < 16'h0000) || (RXCDR_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-453] RXCDR_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG3_GEN3_REG < 16'h0000) || (RXCDR_CFG3_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-456] RXCDR_CFG3_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG3_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG3_REG < 16'h0000) || (RXCDR_CFG3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-455] RXCDR_CFG3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG4_GEN3_REG < 16'h0000) || (RXCDR_CFG4_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-458] RXCDR_CFG4_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG4_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG4_REG < 16'h0000) || (RXCDR_CFG4_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-457] RXCDR_CFG4 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG5_GEN3_REG < 16'h0000) || (RXCDR_CFG5_GEN3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-460] RXCDR_CFG5_GEN3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG5_GEN3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_CFG5_REG < 16'h0000) || (RXCDR_CFG5_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-459] RXCDR_CFG5 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_CFG5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_FR_RESET_ON_EIDLE_REG !== 1'b0) && (RXCDR_FR_RESET_ON_EIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-461] RXCDR_FR_RESET_ON_EIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXCDR_FR_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_HOLD_DURING_EIDLE_REG !== 1'b0) && (RXCDR_HOLD_DURING_EIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-462] RXCDR_HOLD_DURING_EIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXCDR_HOLD_DURING_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_LOCK_CFG0_REG < 16'h0000) || (RXCDR_LOCK_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-463] RXCDR_LOCK_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_LOCK_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_LOCK_CFG1_REG < 16'h0000) || (RXCDR_LOCK_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-464] RXCDR_LOCK_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_LOCK_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_LOCK_CFG2_REG < 16'h0000) || (RXCDR_LOCK_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-465] RXCDR_LOCK_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_LOCK_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_LOCK_CFG3_REG < 16'h0000) || (RXCDR_LOCK_CFG3_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-466] RXCDR_LOCK_CFG3 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCDR_LOCK_CFG3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCDR_PH_RESET_ON_EIDLE_REG !== 1'b0) && (RXCDR_PH_RESET_ON_EIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-467] RXCDR_PH_RESET_ON_EIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXCDR_PH_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCFOKDONE_SRC_REG < 2'b00) || (RXCFOKDONE_SRC_REG > 2'b11))) begin
$display("Error: [Unisim %s-468] RXCFOKDONE_SRC attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RXCFOKDONE_SRC_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCFOK_CFG0_REG < 16'h0000) || (RXCFOK_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-469] RXCFOK_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCFOK_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCFOK_CFG1_REG < 16'h0000) || (RXCFOK_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-470] RXCFOK_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCFOK_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXCFOK_CFG2_REG < 16'h0000) || (RXCFOK_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-471] RXCFOK_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXCFOK_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFELPMRESET_TIME_REG < 7'b0000000) || (RXDFELPMRESET_TIME_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-472] RXDFELPMRESET_TIME attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, RXDFELPMRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFELPM_KL_CFG0_REG < 16'h0000) || (RXDFELPM_KL_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-473] RXDFELPM_KL_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFELPM_KL_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFELPM_KL_CFG1_REG < 16'h0000) || (RXDFELPM_KL_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-474] RXDFELPM_KL_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFELPM_KL_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFELPM_KL_CFG2_REG < 16'h0000) || (RXDFELPM_KL_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-475] RXDFELPM_KL_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFELPM_KL_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_CFG0_REG < 16'h0000) || (RXDFE_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-476] RXDFE_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_CFG1_REG < 16'h0000) || (RXDFE_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-477] RXDFE_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_GC_CFG0_REG < 16'h0000) || (RXDFE_GC_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-478] RXDFE_GC_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_GC_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_GC_CFG1_REG < 16'h0000) || (RXDFE_GC_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-479] RXDFE_GC_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_GC_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_GC_CFG2_REG < 16'h0000) || (RXDFE_GC_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-480] RXDFE_GC_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_GC_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H2_CFG0_REG < 16'h0000) || (RXDFE_H2_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-481] RXDFE_H2_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H2_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H2_CFG1_REG < 16'h0000) || (RXDFE_H2_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-482] RXDFE_H2_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H2_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H3_CFG0_REG < 16'h0000) || (RXDFE_H3_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-483] RXDFE_H3_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H3_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H3_CFG1_REG < 16'h0000) || (RXDFE_H3_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-484] RXDFE_H3_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H3_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H4_CFG0_REG < 16'h0000) || (RXDFE_H4_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-485] RXDFE_H4_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H4_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H4_CFG1_REG < 16'h0000) || (RXDFE_H4_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-486] RXDFE_H4_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H4_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H5_CFG0_REG < 16'h0000) || (RXDFE_H5_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-487] RXDFE_H5_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H5_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H5_CFG1_REG < 16'h0000) || (RXDFE_H5_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-488] RXDFE_H5_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H5_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H6_CFG0_REG < 16'h0000) || (RXDFE_H6_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-489] RXDFE_H6_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H6_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H6_CFG1_REG < 16'h0000) || (RXDFE_H6_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-490] RXDFE_H6_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H6_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H7_CFG0_REG < 16'h0000) || (RXDFE_H7_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-491] RXDFE_H7_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H7_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H7_CFG1_REG < 16'h0000) || (RXDFE_H7_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-492] RXDFE_H7_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H7_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H8_CFG0_REG < 16'h0000) || (RXDFE_H8_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-493] RXDFE_H8_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H8_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H8_CFG1_REG < 16'h0000) || (RXDFE_H8_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-494] RXDFE_H8_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H8_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H9_CFG0_REG < 16'h0000) || (RXDFE_H9_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-495] RXDFE_H9_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H9_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_H9_CFG1_REG < 16'h0000) || (RXDFE_H9_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-496] RXDFE_H9_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_H9_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HA_CFG0_REG < 16'h0000) || (RXDFE_HA_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-497] RXDFE_HA_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HA_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HA_CFG1_REG < 16'h0000) || (RXDFE_HA_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-498] RXDFE_HA_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HA_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HB_CFG0_REG < 16'h0000) || (RXDFE_HB_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-499] RXDFE_HB_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HB_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HB_CFG1_REG < 16'h0000) || (RXDFE_HB_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-500] RXDFE_HB_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HB_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HC_CFG0_REG < 16'h0000) || (RXDFE_HC_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-501] RXDFE_HC_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HC_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HC_CFG1_REG < 16'h0000) || (RXDFE_HC_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-502] RXDFE_HC_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HC_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HD_CFG0_REG < 16'h0000) || (RXDFE_HD_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-503] RXDFE_HD_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HD_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HD_CFG1_REG < 16'h0000) || (RXDFE_HD_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-504] RXDFE_HD_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HD_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HE_CFG0_REG < 16'h0000) || (RXDFE_HE_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-505] RXDFE_HE_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HE_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HE_CFG1_REG < 16'h0000) || (RXDFE_HE_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-506] RXDFE_HE_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HE_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HF_CFG0_REG < 16'h0000) || (RXDFE_HF_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-507] RXDFE_HF_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HF_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_HF_CFG1_REG < 16'h0000) || (RXDFE_HF_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-508] RXDFE_HF_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_HF_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_OS_CFG0_REG < 16'h0000) || (RXDFE_OS_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-509] RXDFE_OS_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_OS_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_OS_CFG1_REG < 16'h0000) || (RXDFE_OS_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-510] RXDFE_OS_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_OS_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_PWR_SAVING_REG !== 1'b0) && (RXDFE_PWR_SAVING_REG !== 1'b1))) begin
$display("Error: [Unisim %s-511] RXDFE_PWR_SAVING attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXDFE_PWR_SAVING_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_UT_CFG0_REG < 16'h0000) || (RXDFE_UT_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-512] RXDFE_UT_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_UT_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_UT_CFG1_REG < 16'h0000) || (RXDFE_UT_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-513] RXDFE_UT_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_UT_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_VP_CFG0_REG < 16'h0000) || (RXDFE_VP_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-514] RXDFE_VP_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_VP_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDFE_VP_CFG1_REG < 16'h0000) || (RXDFE_VP_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-515] RXDFE_VP_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDFE_VP_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDLY_CFG_REG < 16'h0000) || (RXDLY_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-516] RXDLY_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDLY_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXDLY_LCFG_REG < 16'h0000) || (RXDLY_LCFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-517] RXDLY_LCFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXDLY_LCFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXELECIDLE_CFG_REG != "SIGCFG_4") &&
(RXELECIDLE_CFG_REG != "SIGCFG_1") &&
(RXELECIDLE_CFG_REG != "SIGCFG_2") &&
(RXELECIDLE_CFG_REG != "SIGCFG_3") &&
(RXELECIDLE_CFG_REG != "SIGCFG_6") &&
(RXELECIDLE_CFG_REG != "SIGCFG_8") &&
(RXELECIDLE_CFG_REG != "SIGCFG_12") &&
(RXELECIDLE_CFG_REG != "SIGCFG_16"))) begin
$display("Error: [Unisim %s-518] RXELECIDLE_CFG attribute is set to %s. Legal values for this attribute are SIGCFG_4, SIGCFG_1, SIGCFG_2, SIGCFG_3, SIGCFG_6, SIGCFG_8, SIGCFG_12 or SIGCFG_16. Instance: %m", MODULE_NAME, RXELECIDLE_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 5))) begin
$display("Error: [Unisim %s-519] RXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3 or 5. Instance: %m", MODULE_NAME, RXGBOX_FIFO_INIT_RD_ADDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXGEARBOX_EN_REG != "FALSE") &&
(RXGEARBOX_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-520] RXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXISCANRESET_TIME_REG < 5'b00000) || (RXISCANRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-521] RXISCANRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXISCANRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_CFG_REG < 16'h0000) || (RXLPM_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-522] RXLPM_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_GC_CFG_REG < 16'h0000) || (RXLPM_GC_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-523] RXLPM_GC_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_GC_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_KH_CFG0_REG < 16'h0000) || (RXLPM_KH_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-524] RXLPM_KH_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_KH_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_KH_CFG1_REG < 16'h0000) || (RXLPM_KH_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-525] RXLPM_KH_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_KH_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_OS_CFG0_REG < 16'h0000) || (RXLPM_OS_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-526] RXLPM_OS_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_OS_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXLPM_OS_CFG1_REG < 16'h0000) || (RXLPM_OS_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-527] RXLPM_OS_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXLPM_OS_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOOB_CFG_REG < 9'b000000000) || (RXOOB_CFG_REG > 9'b111111111))) begin
$display("Error: [Unisim %s-528] RXOOB_CFG attribute is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111. Instance: %m", MODULE_NAME, RXOOB_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOOB_CLK_CFG_REG != "PMA") &&
(RXOOB_CLK_CFG_REG != "FABRIC"))) begin
$display("Error: [Unisim %s-529] RXOOB_CLK_CFG attribute is set to %s. Legal values for this attribute are PMA or FABRIC. Instance: %m", MODULE_NAME, RXOOB_CLK_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOSCALRESET_TIME_REG < 5'b00000) || (RXOSCALRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-530] RXOSCALRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXOSCALRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOUT_DIV_REG != 4) &&
(RXOUT_DIV_REG != 1) &&
(RXOUT_DIV_REG != 2) &&
(RXOUT_DIV_REG != 8) &&
(RXOUT_DIV_REG != 16) &&
(RXOUT_DIV_REG != 32))) begin
$display("Error: [Unisim %s-531] RXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8, 16 or 32. Instance: %m", MODULE_NAME, RXOUT_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPCSRESET_TIME_REG < 5'b00000) || (RXPCSRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-532] RXPCSRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXPCSRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPHBEACON_CFG_REG < 16'h0000) || (RXPHBEACON_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-533] RXPHBEACON_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPHBEACON_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPHDLY_CFG_REG < 16'h0000) || (RXPHDLY_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-534] RXPHDLY_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPHDLY_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPHSAMP_CFG_REG < 16'h0000) || (RXPHSAMP_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-535] RXPHSAMP_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPHSAMP_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPHSLIP_CFG_REG < 16'h0000) || (RXPHSLIP_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-536] RXPHSLIP_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPHSLIP_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPH_MONITOR_SEL_REG < 5'b00000) || (RXPH_MONITOR_SEL_REG > 5'b11111))) begin
$display("Error: [Unisim %s-537] RXPH_MONITOR_SEL attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXPH_MONITOR_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_AUTO_BW_SEL_BYPASS_REG !== 1'b0) && (RXPI_AUTO_BW_SEL_BYPASS_REG !== 1'b1))) begin
$display("Error: [Unisim %s-538] RXPI_AUTO_BW_SEL_BYPASS attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPI_AUTO_BW_SEL_BYPASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_CFG_REG < 16'h0000) || (RXPI_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-539] RXPI_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPI_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_LPM_REG !== 1'b0) && (RXPI_LPM_REG !== 1'b1))) begin
$display("Error: [Unisim %s-540] RXPI_LPM attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPI_LPM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_RSV0_REG < 16'h0000) || (RXPI_RSV0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-541] RXPI_RSV0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RXPI_RSV0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_SEL_LC_REG < 2'b00) || (RXPI_SEL_LC_REG > 2'b11))) begin
$display("Error: [Unisim %s-542] RXPI_SEL_LC attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RXPI_SEL_LC_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_STARTCODE_REG < 2'b00) || (RXPI_STARTCODE_REG > 2'b11))) begin
$display("Error: [Unisim %s-543] RXPI_STARTCODE attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RXPI_STARTCODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPI_VREFSEL_REG !== 1'b0) && (RXPI_VREFSEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-544] RXPI_VREFSEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPI_VREFSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPMACLK_SEL_REG != "DATA") &&
(RXPMACLK_SEL_REG != "CROSSING") &&
(RXPMACLK_SEL_REG != "EYESCAN"))) begin
$display("Error: [Unisim %s-546] RXPMACLK_SEL attribute is set to %s. Legal values for this attribute are DATA, CROSSING or EYESCAN. Instance: %m", MODULE_NAME, RXPMACLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPMARESET_TIME_REG < 5'b00000) || (RXPMARESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-547] RXPMARESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RXPMARESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPRBS_ERR_LOOPBACK_REG !== 1'b0) && (RXPRBS_ERR_LOOPBACK_REG !== 1'b1))) begin
$display("Error: [Unisim %s-548] RXPRBS_ERR_LOOPBACK attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXPRBS_ERR_LOOPBACK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSLIDE_AUTO_WAIT_REG != 7) &&
(RXSLIDE_AUTO_WAIT_REG != 1) &&
(RXSLIDE_AUTO_WAIT_REG != 2) &&
(RXSLIDE_AUTO_WAIT_REG != 3) &&
(RXSLIDE_AUTO_WAIT_REG != 4) &&
(RXSLIDE_AUTO_WAIT_REG != 5) &&
(RXSLIDE_AUTO_WAIT_REG != 6) &&
(RXSLIDE_AUTO_WAIT_REG != 8) &&
(RXSLIDE_AUTO_WAIT_REG != 9) &&
(RXSLIDE_AUTO_WAIT_REG != 10) &&
(RXSLIDE_AUTO_WAIT_REG != 11) &&
(RXSLIDE_AUTO_WAIT_REG != 12) &&
(RXSLIDE_AUTO_WAIT_REG != 13) &&
(RXSLIDE_AUTO_WAIT_REG != 14) &&
(RXSLIDE_AUTO_WAIT_REG != 15))) begin
$display("Error: [Unisim %s-550] RXSLIDE_AUTO_WAIT attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RXSLIDE_AUTO_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSLIDE_MODE_REG != "OFF") &&
(RXSLIDE_MODE_REG != "AUTO") &&
(RXSLIDE_MODE_REG != "PCS") &&
(RXSLIDE_MODE_REG != "PMA"))) begin
$display("Error: [Unisim %s-551] RXSLIDE_MODE attribute is set to %s. Legal values for this attribute are OFF, AUTO, PCS or PMA. Instance: %m", MODULE_NAME, RXSLIDE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSYNC_MULTILANE_REG !== 1'b0) && (RXSYNC_MULTILANE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-552] RXSYNC_MULTILANE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXSYNC_MULTILANE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSYNC_OVRD_REG !== 1'b0) && (RXSYNC_OVRD_REG !== 1'b1))) begin
$display("Error: [Unisim %s-553] RXSYNC_OVRD attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXSYNC_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSYNC_SKIP_DA_REG !== 1'b0) && (RXSYNC_SKIP_DA_REG !== 1'b1))) begin
$display("Error: [Unisim %s-554] RXSYNC_SKIP_DA attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RXSYNC_SKIP_DA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_AFE_CM_EN_REG !== 1'b0) && (RX_AFE_CM_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-555] RX_AFE_CM_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_AFE_CM_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_BIAS_CFG0_REG < 16'h0000) || (RX_BIAS_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-556] RX_BIAS_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RX_BIAS_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_BUFFER_CFG_REG < 6'b000000) || (RX_BUFFER_CFG_REG > 6'b111111))) begin
$display("Error: [Unisim %s-557] RX_BUFFER_CFG attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, RX_BUFFER_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CAPFF_SARC_ENB_REG !== 1'b0) && (RX_CAPFF_SARC_ENB_REG !== 1'b1))) begin
$display("Error: [Unisim %s-558] RX_CAPFF_SARC_ENB attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_CAPFF_SARC_ENB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CLKMUX_EN_REG !== 1'b0) && (RX_CLKMUX_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-560] RX_CLKMUX_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_CLKMUX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CLK_SLIP_OVRD_REG < 5'b00000) || (RX_CLK_SLIP_OVRD_REG > 5'b11111))) begin
$display("Error: [Unisim %s-561] RX_CLK_SLIP_OVRD attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RX_CLK_SLIP_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_BUF_CFG_REG < 4'b0000) || (RX_CM_BUF_CFG_REG > 4'b1111))) begin
$display("Error: [Unisim %s-562] RX_CM_BUF_CFG attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_CM_BUF_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_BUF_PD_REG !== 1'b0) && (RX_CM_BUF_PD_REG !== 1'b1))) begin
$display("Error: [Unisim %s-563] RX_CM_BUF_PD attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_CM_BUF_PD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_SEL_REG != 3) &&
(RX_CM_SEL_REG != 0) &&
(RX_CM_SEL_REG != 1) &&
(RX_CM_SEL_REG != 2))) begin
$display("Error: [Unisim %s-564] RX_CM_SEL attribute is set to %d. Legal values for this attribute are 3, 0, 1 or 2. Instance: %m", MODULE_NAME, RX_CM_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_TRIM_REG != 10) &&
(RX_CM_TRIM_REG != 0) &&
(RX_CM_TRIM_REG != 1) &&
(RX_CM_TRIM_REG != 2) &&
(RX_CM_TRIM_REG != 3) &&
(RX_CM_TRIM_REG != 4) &&
(RX_CM_TRIM_REG != 5) &&
(RX_CM_TRIM_REG != 6) &&
(RX_CM_TRIM_REG != 7) &&
(RX_CM_TRIM_REG != 8) &&
(RX_CM_TRIM_REG != 9) &&
(RX_CM_TRIM_REG != 11) &&
(RX_CM_TRIM_REG != 12) &&
(RX_CM_TRIM_REG != 13) &&
(RX_CM_TRIM_REG != 14) &&
(RX_CM_TRIM_REG != 15))) begin
$display("Error: [Unisim %s-565] RX_CM_TRIM attribute is set to %d. Legal values for this attribute are 10, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RX_CM_TRIM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CTLE1_KHKL_REG !== 1'b0) && (RX_CTLE1_KHKL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-566] RX_CTLE1_KHKL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_CTLE1_KHKL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CTLE2_KHKL_REG !== 1'b0) && (RX_CTLE2_KHKL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-567] RX_CTLE2_KHKL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_CTLE2_KHKL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CTLE3_AGC_REG !== 1'b0) && (RX_CTLE3_AGC_REG !== 1'b1))) begin
$display("Error: [Unisim %s-568] RX_CTLE3_AGC attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_CTLE3_AGC_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DATA_WIDTH_REG != 20) &&
(RX_DATA_WIDTH_REG != 16) &&
(RX_DATA_WIDTH_REG != 32) &&
(RX_DATA_WIDTH_REG != 40) &&
(RX_DATA_WIDTH_REG != 64) &&
(RX_DATA_WIDTH_REG != 80) &&
(RX_DATA_WIDTH_REG != 128) &&
(RX_DATA_WIDTH_REG != 160))) begin
$display("Error: [Unisim %s-569] RX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, RX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DDI_SEL_REG < 6'b000000) || (RX_DDI_SEL_REG > 6'b111111))) begin
$display("Error: [Unisim %s-570] RX_DDI_SEL attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, RX_DDI_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DEFER_RESET_BUF_EN_REG != "TRUE") &&
(RX_DEFER_RESET_BUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-571] RX_DEFER_RESET_BUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DEFER_RESET_BUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DEGEN_CTRL_REG < 3'b000) || (RX_DEGEN_CTRL_REG > 3'b111))) begin
$display("Error: [Unisim %s-572] RX_DEGEN_CTRL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_DEGEN_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFELPM_CFG0_REG != 6) &&
(RX_DFELPM_CFG0_REG != 0) &&
(RX_DFELPM_CFG0_REG != 1) &&
(RX_DFELPM_CFG0_REG != 2) &&
(RX_DFELPM_CFG0_REG != 3) &&
(RX_DFELPM_CFG0_REG != 4) &&
(RX_DFELPM_CFG0_REG != 5) &&
(RX_DFELPM_CFG0_REG != 7))) begin
$display("Error: [Unisim %s-573] RX_DFELPM_CFG0 attribute is set to %d. Legal values for this attribute are 6, 0, 1, 2, 3, 4, 5 or 7. Instance: %m", MODULE_NAME, RX_DFELPM_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFELPM_CFG1_REG !== 1'b0) && (RX_DFELPM_CFG1_REG !== 1'b1))) begin
$display("Error: [Unisim %s-574] RX_DFELPM_CFG1 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_DFELPM_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFELPM_KLKH_AGC_STUP_EN_REG !== 1'b0) && (RX_DFELPM_KLKH_AGC_STUP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-575] RX_DFELPM_KLKH_AGC_STUP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_DFELPM_KLKH_AGC_STUP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_AGC_CFG0_REG < 2'b00) || (RX_DFE_AGC_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-576] RX_DFE_AGC_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_DFE_AGC_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_AGC_CFG1_REG != 4) &&
(RX_DFE_AGC_CFG1_REG != 0) &&
(RX_DFE_AGC_CFG1_REG != 1) &&
(RX_DFE_AGC_CFG1_REG != 2) &&
(RX_DFE_AGC_CFG1_REG != 3) &&
(RX_DFE_AGC_CFG1_REG != 5) &&
(RX_DFE_AGC_CFG1_REG != 6) &&
(RX_DFE_AGC_CFG1_REG != 7))) begin
$display("Error: [Unisim %s-577] RX_DFE_AGC_CFG1 attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_AGC_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KH_CFG0_REG != 1) &&
(RX_DFE_KL_LPM_KH_CFG0_REG != 0) &&
(RX_DFE_KL_LPM_KH_CFG0_REG != 2) &&
(RX_DFE_KL_LPM_KH_CFG0_REG != 3))) begin
$display("Error: [Unisim %s-578] RX_DFE_KL_LPM_KH_CFG0 attribute is set to %d. Legal values for this attribute are 1, 0, 2 or 3. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KH_CFG1_REG != 2) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 1) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 3) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 4) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 5) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 6) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 7))) begin
$display("Error: [Unisim %s-579] RX_DFE_KL_LPM_KH_CFG1 attribute is set to %d. Legal values for this attribute are 2, 1, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KL_CFG0_REG < 2'b00) || (RX_DFE_KL_LPM_KL_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-580] RX_DFE_KL_LPM_KL_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KL_CFG1_REG < 3'b000) || (RX_DFE_KL_LPM_KL_CFG1_REG > 3'b111))) begin
$display("Error: [Unisim %s-581] RX_DFE_KL_LPM_KL_CFG1 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_LPM_HOLD_DURING_EIDLE_REG !== 1'b0) && (RX_DFE_LPM_HOLD_DURING_EIDLE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-582] RX_DFE_LPM_HOLD_DURING_EIDLE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_DFE_LPM_HOLD_DURING_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DISPERR_SEQ_MATCH_REG != "TRUE") &&
(RX_DISPERR_SEQ_MATCH_REG != "FALSE"))) begin
$display("Error: [Unisim %s-583] RX_DISPERR_SEQ_MATCH attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DISPERR_SEQ_MATCH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DIV2_MODE_B_REG !== 1'b0) && (RX_DIV2_MODE_B_REG !== 1'b1))) begin
$display("Error: [Unisim %s-584] RX_DIV2_MODE_B attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_DIV2_MODE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DIVRESET_TIME_REG < 5'b00000) || (RX_DIVRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-585] RX_DIVRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, RX_DIVRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EN_CTLE_RCAL_B_REG !== 1'b0) && (RX_EN_CTLE_RCAL_B_REG !== 1'b1))) begin
$display("Error: [Unisim %s-586] RX_EN_CTLE_RCAL_B attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_EN_CTLE_RCAL_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EN_HI_LR_REG !== 1'b0) && (RX_EN_HI_LR_REG !== 1'b1))) begin
$display("Error: [Unisim %s-587] RX_EN_HI_LR attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_EN_HI_LR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EXT_RL_CTRL_REG < 9'b000000000) || (RX_EXT_RL_CTRL_REG > 9'b111111111))) begin
$display("Error: [Unisim %s-588] RX_EXT_RL_CTRL attribute is set to %b. Legal values for this attribute are 9'b000000000 to 9'b111111111. Instance: %m", MODULE_NAME, RX_EXT_RL_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EYESCAN_VS_CODE_REG < 7'b0000000) || (RX_EYESCAN_VS_CODE_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-589] RX_EYESCAN_VS_CODE attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, RX_EYESCAN_VS_CODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EYESCAN_VS_NEG_DIR_REG !== 1'b0) && (RX_EYESCAN_VS_NEG_DIR_REG !== 1'b1))) begin
$display("Error: [Unisim %s-590] RX_EYESCAN_VS_NEG_DIR attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_EYESCAN_VS_NEG_DIR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EYESCAN_VS_RANGE_REG < 2'b00) || (RX_EYESCAN_VS_RANGE_REG > 2'b11))) begin
$display("Error: [Unisim %s-591] RX_EYESCAN_VS_RANGE attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_EYESCAN_VS_RANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EYESCAN_VS_UT_SIGN_REG !== 1'b0) && (RX_EYESCAN_VS_UT_SIGN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-592] RX_EYESCAN_VS_UT_SIGN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_EYESCAN_VS_UT_SIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_FABINT_USRCLK_FLOP_REG !== 1'b0) && (RX_FABINT_USRCLK_FLOP_REG !== 1'b1))) begin
$display("Error: [Unisim %s-593] RX_FABINT_USRCLK_FLOP attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_FABINT_USRCLK_FLOP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_INT_DATAWIDTH_REG != 1) &&
(RX_INT_DATAWIDTH_REG != 0) &&
(RX_INT_DATAWIDTH_REG != 2))) begin
$display("Error: [Unisim %s-594] RX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, RX_INT_DATAWIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_PMA_POWER_SAVE_REG !== 1'b0) && (RX_PMA_POWER_SAVE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-595] RX_PMA_POWER_SAVE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_PMA_POWER_SAVE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_PROGDIV_RATE_REG < 16'h0000) || (RX_PROGDIV_RATE_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-597] RX_PROGDIV_RATE attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, RX_PROGDIV_RATE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_RESLOAD_CTRL_REG < 4'b0000) || (RX_RESLOAD_CTRL_REG > 4'b1111))) begin
$display("Error: [Unisim %s-598] RX_RESLOAD_CTRL attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_RESLOAD_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_RESLOAD_OVRD_REG !== 1'b0) && (RX_RESLOAD_OVRD_REG !== 1'b1))) begin
$display("Error: [Unisim %s-599] RX_RESLOAD_OVRD attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_RESLOAD_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SAMPLE_PERIOD_REG < 3'b000) || (RX_SAMPLE_PERIOD_REG > 3'b111))) begin
$display("Error: [Unisim %s-600] RX_SAMPLE_PERIOD attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_SAMPLE_PERIOD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_DFETAPREP_EN_REG !== 1'b0) && (RX_SUM_DFETAPREP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-602] RX_SUM_DFETAPREP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_SUM_DFETAPREP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_IREF_TUNE_REG < 4'b0000) || (RX_SUM_IREF_TUNE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-603] RX_SUM_IREF_TUNE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_SUM_IREF_TUNE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_VCMTUNE_REG < 4'b0000) || (RX_SUM_VCMTUNE_REG > 4'b1111))) begin
$display("Error: [Unisim %s-604] RX_SUM_VCMTUNE attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, RX_SUM_VCMTUNE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_VCM_OVWR_REG !== 1'b0) && (RX_SUM_VCM_OVWR_REG !== 1'b1))) begin
$display("Error: [Unisim %s-605] RX_SUM_VCM_OVWR attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_SUM_VCM_OVWR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_VREF_TUNE_REG < 3'b000) || (RX_SUM_VREF_TUNE_REG > 3'b111))) begin
$display("Error: [Unisim %s-606] RX_SUM_VREF_TUNE attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_SUM_VREF_TUNE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_TUNE_AFE_OS_REG < 2'b00) || (RX_TUNE_AFE_OS_REG > 2'b11))) begin
$display("Error: [Unisim %s-607] RX_TUNE_AFE_OS attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_TUNE_AFE_OS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_VREG_CTRL_REG < 3'b000) || (RX_VREG_CTRL_REG > 3'b111))) begin
$display("Error: [Unisim %s-608] RX_VREG_CTRL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, RX_VREG_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_VREG_PDB_REG !== 1'b0) && (RX_VREG_PDB_REG !== 1'b1))) begin
$display("Error: [Unisim %s-609] RX_VREG_PDB attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_VREG_PDB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_WIDEMODE_CDR_REG < 2'b00) || (RX_WIDEMODE_CDR_REG > 2'b11))) begin
$display("Error: [Unisim %s-610] RX_WIDEMODE_CDR attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, RX_WIDEMODE_CDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_XCLK_SEL_REG != "RXDES") &&
(RX_XCLK_SEL_REG != "RXPMA") &&
(RX_XCLK_SEL_REG != "RXUSR"))) begin
$display("Error: [Unisim %s-611] RX_XCLK_SEL attribute is set to %s. Legal values for this attribute are RXDES, RXPMA or RXUSR. Instance: %m", MODULE_NAME, RX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_XMODE_SEL_REG !== 1'b0) && (RX_XMODE_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-612] RX_XMODE_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, RX_XMODE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_BURST_SEQ_LEN_REG < 4'b0000) || (SATA_BURST_SEQ_LEN_REG > 4'b1111))) begin
$display("Error: [Unisim %s-615] SATA_BURST_SEQ_LEN attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, SATA_BURST_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_BURST_VAL_REG < 3'b000) || (SATA_BURST_VAL_REG > 3'b111))) begin
$display("Error: [Unisim %s-616] SATA_BURST_VAL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, SATA_BURST_VAL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_CPLL_CFG_REG != "VCO_3000MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_750MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_1500MHZ"))) begin
$display("Error: [Unisim %s-617] SATA_CPLL_CFG attribute is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ or VCO_1500MHZ. Instance: %m", MODULE_NAME, SATA_CPLL_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_EIDLE_VAL_REG < 3'b000) || (SATA_EIDLE_VAL_REG > 3'b111))) begin
$display("Error: [Unisim %s-618] SATA_EIDLE_VAL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, SATA_EIDLE_VAL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SHOW_REALIGN_COMMA_REG != "TRUE") &&
(SHOW_REALIGN_COMMA_REG != "FALSE"))) begin
$display("Error: [Unisim %s-625] SHOW_REALIGN_COMMA attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SHOW_REALIGN_COMMA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_RECEIVER_DETECT_PASS_REG != "TRUE") &&
(SIM_RECEIVER_DETECT_PASS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-626] SIM_RECEIVER_DETECT_PASS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RECEIVER_DETECT_PASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_RESET_SPEEDUP_REG != "TRUE") &&
(SIM_RESET_SPEEDUP_REG != "FALSE"))) begin
$display("Error: [Unisim %s-627] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_TX_EIDLE_DRIVE_LEVEL_REG !== 1'b0) && (SIM_TX_EIDLE_DRIVE_LEVEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-628] SIM_TX_EIDLE_DRIVE_LEVEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, SIM_TX_EIDLE_DRIVE_LEVEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TAPDLY_SET_TX_REG < 2'h0) || (TAPDLY_SET_TX_REG > 2'h3))) begin
$display("Error: [Unisim %s-630] TAPDLY_SET_TX attribute is set to %h. Legal values for this attribute are 2'h0 to 2'h3. Instance: %m", MODULE_NAME, TAPDLY_SET_TX_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TEMPERATURE_PAR_REG < 4'b0000) || (TEMPERATURE_PAR_REG > 4'b1111))) begin
$display("Error: [Unisim %s-631] TEMPERATURE_PAR attribute is set to %b. Legal values for this attribute are 4'b0000 to 4'b1111. Instance: %m", MODULE_NAME, TEMPERATURE_PAR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TERM_RCAL_CFG_REG < 15'b000000000000000) || (TERM_RCAL_CFG_REG > 15'b111111111111111))) begin
$display("Error: [Unisim %s-632] TERM_RCAL_CFG attribute is set to %b. Legal values for this attribute are 15'b000000000000000 to 15'b111111111111111. Instance: %m", MODULE_NAME, TERM_RCAL_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TERM_RCAL_OVRD_REG < 3'b000) || (TERM_RCAL_OVRD_REG > 3'b111))) begin
$display("Error: [Unisim %s-633] TERM_RCAL_OVRD attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TERM_RCAL_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TRANS_TIME_RATE_REG < 8'h00) || (TRANS_TIME_RATE_REG > 8'hFF))) begin
$display("Error: [Unisim %s-634] TRANS_TIME_RATE attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, TRANS_TIME_RATE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TST_RSV0_REG < 8'h00) || (TST_RSV0_REG > 8'hFF))) begin
$display("Error: [Unisim %s-635] TST_RSV0 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, TST_RSV0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TST_RSV1_REG < 8'h00) || (TST_RSV1_REG > 8'hFF))) begin
$display("Error: [Unisim %s-636] TST_RSV1 attribute is set to %h. Legal values for this attribute are 8'h00 to 8'hFF. Instance: %m", MODULE_NAME, TST_RSV1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXBUF_EN_REG != "TRUE") &&
(TXBUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-637] TXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TXBUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE") &&
(TXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-638] TXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXDLY_CFG_REG < 16'h0000) || (TXDLY_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-639] TXDLY_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXDLY_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXDLY_LCFG_REG < 16'h0000) || (TXDLY_LCFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-640] TXDLY_LCFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXDLY_LCFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXFIFO_ADDR_CFG_REG != "LOW") &&
(TXFIFO_ADDR_CFG_REG != "HIGH"))) begin
$display("Error: [Unisim %s-641] TXFIFO_ADDR_CFG attribute is set to %s. Legal values for this attribute are LOW or HIGH. Instance: %m", MODULE_NAME, TXFIFO_ADDR_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 5) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 6))) begin
$display("Error: [Unisim %s-642] TXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3, 5 or 6. Instance: %m", MODULE_NAME, TXGBOX_FIFO_INIT_RD_ADDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXGEARBOX_EN_REG != "FALSE") &&
(TXGEARBOX_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-643] TXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXOUT_DIV_REG != 4) &&
(TXOUT_DIV_REG != 1) &&
(TXOUT_DIV_REG != 2) &&
(TXOUT_DIV_REG != 8) &&
(TXOUT_DIV_REG != 16) &&
(TXOUT_DIV_REG != 32))) begin
$display("Error: [Unisim %s-645] TXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8, 16 or 32. Instance: %m", MODULE_NAME, TXOUT_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPCSRESET_TIME_REG < 5'b00000) || (TXPCSRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-646] TXPCSRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, TXPCSRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPHDLY_CFG0_REG < 16'h0000) || (TXPHDLY_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-647] TXPHDLY_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXPHDLY_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPHDLY_CFG1_REG < 16'h0000) || (TXPHDLY_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-648] TXPHDLY_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXPHDLY_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPH_CFG2_REG < 16'h0000) || (TXPH_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-650] TXPH_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXPH_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPH_CFG_REG < 16'h0000) || (TXPH_CFG_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-649] TXPH_CFG attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXPH_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPH_MONITOR_SEL_REG < 5'b00000) || (TXPH_MONITOR_SEL_REG > 5'b11111))) begin
$display("Error: [Unisim %s-651] TXPH_MONITOR_SEL attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, TXPH_MONITOR_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG0_REG < 2'b00) || (TXPI_CFG0_REG > 2'b11))) begin
$display("Error: [Unisim %s-652] TXPI_CFG0 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, TXPI_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG1_REG < 2'b00) || (TXPI_CFG1_REG > 2'b11))) begin
$display("Error: [Unisim %s-653] TXPI_CFG1 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, TXPI_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG2_REG < 2'b00) || (TXPI_CFG2_REG > 2'b11))) begin
$display("Error: [Unisim %s-654] TXPI_CFG2 attribute is set to %b. Legal values for this attribute are 2'b00 to 2'b11. Instance: %m", MODULE_NAME, TXPI_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG3_REG !== 1'b0) && (TXPI_CFG3_REG !== 1'b1))) begin
$display("Error: [Unisim %s-655] TXPI_CFG3 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_CFG3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG4_REG !== 1'b0) && (TXPI_CFG4_REG !== 1'b1))) begin
$display("Error: [Unisim %s-656] TXPI_CFG4 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_CFG4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_CFG5_REG < 3'b000) || (TXPI_CFG5_REG > 3'b111))) begin
$display("Error: [Unisim %s-657] TXPI_CFG5 attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TXPI_CFG5_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_GRAY_SEL_REG !== 1'b0) && (TXPI_GRAY_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-658] TXPI_GRAY_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_GRAY_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_INVSTROBE_SEL_REG !== 1'b0) && (TXPI_INVSTROBE_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-659] TXPI_INVSTROBE_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_INVSTROBE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_LPM_REG !== 1'b0) && (TXPI_LPM_REG !== 1'b1))) begin
$display("Error: [Unisim %s-660] TXPI_LPM attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_LPM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_PPMCLK_SEL_REG != "TXUSRCLK2") &&
(TXPI_PPMCLK_SEL_REG != "TXUSRCLK"))) begin
$display("Error: [Unisim %s-661] TXPI_PPMCLK_SEL attribute is set to %s. Legal values for this attribute are TXUSRCLK2 or TXUSRCLK. Instance: %m", MODULE_NAME, TXPI_PPMCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_PPM_CFG_REG < 8'b00000000) || (TXPI_PPM_CFG_REG > 8'b11111111))) begin
$display("Error: [Unisim %s-662] TXPI_PPM_CFG attribute is set to %b. Legal values for this attribute are 8'b00000000 to 8'b11111111. Instance: %m", MODULE_NAME, TXPI_PPM_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_RSV0_REG < 16'h0000) || (TXPI_RSV0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-663] TXPI_RSV0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TXPI_RSV0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_SYNFREQ_PPM_REG < 3'b000) || (TXPI_SYNFREQ_PPM_REG > 3'b111))) begin
$display("Error: [Unisim %s-664] TXPI_SYNFREQ_PPM attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TXPI_SYNFREQ_PPM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPI_VREFSEL_REG !== 1'b0) && (TXPI_VREFSEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-665] TXPI_VREFSEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXPI_VREFSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXPMARESET_TIME_REG < 5'b00000) || (TXPMARESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-666] TXPMARESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, TXPMARESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXSYNC_MULTILANE_REG !== 1'b0) && (TXSYNC_MULTILANE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-667] TXSYNC_MULTILANE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXSYNC_MULTILANE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXSYNC_OVRD_REG !== 1'b0) && (TXSYNC_OVRD_REG !== 1'b1))) begin
$display("Error: [Unisim %s-668] TXSYNC_OVRD attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXSYNC_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXSYNC_SKIP_DA_REG !== 1'b0) && (TXSYNC_SKIP_DA_REG !== 1'b1))) begin
$display("Error: [Unisim %s-669] TXSYNC_SKIP_DA attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TXSYNC_SKIP_DA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_CLKMUX_EN_REG !== 1'b0) && (TX_CLKMUX_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-671] TX_CLKMUX_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_CLKMUX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_CLKREG_PDB_REG !== 1'b0) && (TX_CLKREG_PDB_REG !== 1'b1))) begin
$display("Error: [Unisim %s-672] TX_CLKREG_PDB attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_CLKREG_PDB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_CLKREG_SET_REG < 3'b000) || (TX_CLKREG_SET_REG > 3'b111))) begin
$display("Error: [Unisim %s-673] TX_CLKREG_SET attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_CLKREG_SET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DATA_WIDTH_REG != 20) &&
(TX_DATA_WIDTH_REG != 16) &&
(TX_DATA_WIDTH_REG != 32) &&
(TX_DATA_WIDTH_REG != 40) &&
(TX_DATA_WIDTH_REG != 64) &&
(TX_DATA_WIDTH_REG != 80) &&
(TX_DATA_WIDTH_REG != 128) &&
(TX_DATA_WIDTH_REG != 160))) begin
$display("Error: [Unisim %s-674] TX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DCD_CFG_REG < 6'b000000) || (TX_DCD_CFG_REG > 6'b111111))) begin
$display("Error: [Unisim %s-675] TX_DCD_CFG attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, TX_DCD_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DCD_EN_REG !== 1'b0) && (TX_DCD_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-676] TX_DCD_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_DCD_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DEEMPH0_REG < 6'b000000) || (TX_DEEMPH0_REG > 6'b111111))) begin
$display("Error: [Unisim %s-677] TX_DEEMPH0 attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, TX_DEEMPH0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DEEMPH1_REG < 6'b000000) || (TX_DEEMPH1_REG > 6'b111111))) begin
$display("Error: [Unisim %s-678] TX_DEEMPH1 attribute is set to %b. Legal values for this attribute are 6'b000000 to 6'b111111. Instance: %m", MODULE_NAME, TX_DEEMPH1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DIVRESET_TIME_REG < 5'b00000) || (TX_DIVRESET_TIME_REG > 5'b11111))) begin
$display("Error: [Unisim %s-679] TX_DIVRESET_TIME attribute is set to %b. Legal values for this attribute are 5'b00000 to 5'b11111. Instance: %m", MODULE_NAME, TX_DIVRESET_TIME_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DRIVE_MODE_REG != "DIRECT") &&
(TX_DRIVE_MODE_REG != "PIPE") &&
(TX_DRIVE_MODE_REG != "PIPEGEN3"))) begin
$display("Error: [Unisim %s-680] TX_DRIVE_MODE attribute is set to %s. Legal values for this attribute are DIRECT, PIPE or PIPEGEN3. Instance: %m", MODULE_NAME, TX_DRIVE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DRVMUX_CTRL_REG != 2) &&
(TX_DRVMUX_CTRL_REG != 0) &&
(TX_DRVMUX_CTRL_REG != 1) &&
(TX_DRVMUX_CTRL_REG != 3))) begin
$display("Error: [Unisim %s-681] TX_DRVMUX_CTRL attribute is set to %d. Legal values for this attribute are 2, 0, 1 or 3. Instance: %m", MODULE_NAME, TX_DRVMUX_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_EIDLE_ASSERT_DELAY_REG < 3'b000) || (TX_EIDLE_ASSERT_DELAY_REG > 3'b111))) begin
$display("Error: [Unisim %s-682] TX_EIDLE_ASSERT_DELAY attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_EIDLE_ASSERT_DELAY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_EIDLE_DEASSERT_DELAY_REG < 3'b000) || (TX_EIDLE_DEASSERT_DELAY_REG > 3'b111))) begin
$display("Error: [Unisim %s-683] TX_EIDLE_DEASSERT_DELAY attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_EIDLE_DEASSERT_DELAY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_EML_PHI_TUNE_REG !== 1'b0) && (TX_EML_PHI_TUNE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-684] TX_EML_PHI_TUNE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_EML_PHI_TUNE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_FABINT_USRCLK_FLOP_REG !== 1'b0) && (TX_FABINT_USRCLK_FLOP_REG !== 1'b1))) begin
$display("Error: [Unisim %s-685] TX_FABINT_USRCLK_FLOP attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_FABINT_USRCLK_FLOP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_FIFO_BYP_EN_REG !== 1'b0) && (TX_FIFO_BYP_EN_REG !== 1'b1))) begin
$display("Error: [Unisim %s-686] TX_FIFO_BYP_EN attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_FIFO_BYP_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_IDLE_DATA_ZERO_REG !== 1'b0) && (TX_IDLE_DATA_ZERO_REG !== 1'b1))) begin
$display("Error: [Unisim %s-687] TX_IDLE_DATA_ZERO attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_IDLE_DATA_ZERO_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_INT_DATAWIDTH_REG != 1) &&
(TX_INT_DATAWIDTH_REG != 0) &&
(TX_INT_DATAWIDTH_REG != 2))) begin
$display("Error: [Unisim %s-688] TX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, TX_INT_DATAWIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_LOOPBACK_DRIVE_HIZ_REG != "FALSE") &&
(TX_LOOPBACK_DRIVE_HIZ_REG != "TRUE"))) begin
$display("Error: [Unisim %s-689] TX_LOOPBACK_DRIVE_HIZ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TX_LOOPBACK_DRIVE_HIZ_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MAINCURSOR_SEL_REG !== 1'b0) && (TX_MAINCURSOR_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-690] TX_MAINCURSOR_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_MAINCURSOR_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_0_REG < 7'b0000000) || (TX_MARGIN_FULL_0_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-691] TX_MARGIN_FULL_0 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_1_REG < 7'b0000000) || (TX_MARGIN_FULL_1_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-692] TX_MARGIN_FULL_1 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_2_REG < 7'b0000000) || (TX_MARGIN_FULL_2_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-693] TX_MARGIN_FULL_2 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_3_REG < 7'b0000000) || (TX_MARGIN_FULL_3_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-694] TX_MARGIN_FULL_3 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_FULL_4_REG < 7'b0000000) || (TX_MARGIN_FULL_4_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-695] TX_MARGIN_FULL_4 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_FULL_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_0_REG < 7'b0000000) || (TX_MARGIN_LOW_0_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-696] TX_MARGIN_LOW_0 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_1_REG < 7'b0000000) || (TX_MARGIN_LOW_1_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-697] TX_MARGIN_LOW_1 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_2_REG < 7'b0000000) || (TX_MARGIN_LOW_2_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-698] TX_MARGIN_LOW_2 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_3_REG < 7'b0000000) || (TX_MARGIN_LOW_3_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-699] TX_MARGIN_LOW_3 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_3_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MARGIN_LOW_4_REG < 7'b0000000) || (TX_MARGIN_LOW_4_REG > 7'b1111111))) begin
$display("Error: [Unisim %s-700] TX_MARGIN_LOW_4 attribute is set to %b. Legal values for this attribute are 7'b0000000 to 7'b1111111. Instance: %m", MODULE_NAME, TX_MARGIN_LOW_4_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_MODE_SEL_REG < 3'b000) || (TX_MODE_SEL_REG > 3'b111))) begin
$display("Error: [Unisim %s-701] TX_MODE_SEL attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_MODE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PHICAL_CFG0_REG < 16'h0000) || (TX_PHICAL_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-702] TX_PHICAL_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TX_PHICAL_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PHICAL_CFG1_REG < 16'h0000) || (TX_PHICAL_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-703] TX_PHICAL_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TX_PHICAL_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PHICAL_CFG2_REG < 16'h0000) || (TX_PHICAL_CFG2_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-704] TX_PHICAL_CFG2 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TX_PHICAL_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PI_BIASSET_REG != 0) &&
(TX_PI_BIASSET_REG != 1) &&
(TX_PI_BIASSET_REG != 2) &&
(TX_PI_BIASSET_REG != 3))) begin
$display("Error: [Unisim %s-705] TX_PI_BIASSET attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, TX_PI_BIASSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PI_CFG0_REG < 16'h0000) || (TX_PI_CFG0_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-706] TX_PI_CFG0 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TX_PI_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PI_CFG1_REG < 16'h0000) || (TX_PI_CFG1_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-707] TX_PI_CFG1 attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TX_PI_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PI_DIV2_MODE_B_REG !== 1'b0) && (TX_PI_DIV2_MODE_B_REG !== 1'b1))) begin
$display("Error: [Unisim %s-708] TX_PI_DIV2_MODE_B attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_PI_DIV2_MODE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PI_SEL_QPLL0_REG !== 1'b0) && (TX_PI_SEL_QPLL0_REG !== 1'b1))) begin
$display("Error: [Unisim %s-709] TX_PI_SEL_QPLL0 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_PI_SEL_QPLL0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PI_SEL_QPLL1_REG !== 1'b0) && (TX_PI_SEL_QPLL1_REG !== 1'b1))) begin
$display("Error: [Unisim %s-710] TX_PI_SEL_QPLL1 attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_PI_SEL_QPLL1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PMADATA_OPT_REG !== 1'b0) && (TX_PMADATA_OPT_REG !== 1'b1))) begin
$display("Error: [Unisim %s-711] TX_PMADATA_OPT attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_PMADATA_OPT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PMA_POWER_SAVE_REG !== 1'b0) && (TX_PMA_POWER_SAVE_REG !== 1'b1))) begin
$display("Error: [Unisim %s-712] TX_PMA_POWER_SAVE attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_PMA_POWER_SAVE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PREDRV_CTRL_REG != 2) &&
(TX_PREDRV_CTRL_REG != 0) &&
(TX_PREDRV_CTRL_REG != 1) &&
(TX_PREDRV_CTRL_REG != 3))) begin
$display("Error: [Unisim %s-713] TX_PREDRV_CTRL attribute is set to %d. Legal values for this attribute are 2, 0, 1 or 3. Instance: %m", MODULE_NAME, TX_PREDRV_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PROGCLK_SEL_REG != "POSTPI") &&
(TX_PROGCLK_SEL_REG != "CPLL") &&
(TX_PROGCLK_SEL_REG != "PREPI"))) begin
$display("Error: [Unisim %s-714] TX_PROGCLK_SEL attribute is set to %s. Legal values for this attribute are POSTPI, CPLL or PREPI. Instance: %m", MODULE_NAME, TX_PROGCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PROGDIV_RATE_REG < 16'h0000) || (TX_PROGDIV_RATE_REG > 16'hFFFF))) begin
$display("Error: [Unisim %s-716] TX_PROGDIV_RATE attribute is set to %h. Legal values for this attribute are 16'h0000 to 16'hFFFF. Instance: %m", MODULE_NAME, TX_PROGDIV_RATE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_RXDETECT_CFG_REG < 14'h0000) || (TX_RXDETECT_CFG_REG > 14'h3FFF))) begin
$display("Error: [Unisim %s-717] TX_RXDETECT_CFG attribute is set to %h. Legal values for this attribute are 14'h0000 to 14'h3FFF. Instance: %m", MODULE_NAME, TX_RXDETECT_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_RXDETECT_REF_REG != 4) &&
(TX_RXDETECT_REF_REG != 0) &&
(TX_RXDETECT_REF_REG != 1) &&
(TX_RXDETECT_REF_REG != 2) &&
(TX_RXDETECT_REF_REG != 3) &&
(TX_RXDETECT_REF_REG != 5) &&
(TX_RXDETECT_REF_REG != 6) &&
(TX_RXDETECT_REF_REG != 7))) begin
$display("Error: [Unisim %s-718] TX_RXDETECT_REF attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, TX_RXDETECT_REF_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_SAMPLE_PERIOD_REG < 3'b000) || (TX_SAMPLE_PERIOD_REG > 3'b111))) begin
$display("Error: [Unisim %s-719] TX_SAMPLE_PERIOD attribute is set to %b. Legal values for this attribute are 3'b000 to 3'b111. Instance: %m", MODULE_NAME, TX_SAMPLE_PERIOD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_SARC_LPBK_ENB_REG !== 1'b0) && (TX_SARC_LPBK_ENB_REG !== 1'b1))) begin
$display("Error: [Unisim %s-720] TX_SARC_LPBK_ENB attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, TX_SARC_LPBK_ENB_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_XCLK_SEL_REG != "TXOUT") &&
(TX_XCLK_SEL_REG != "TXUSR"))) begin
$display("Error: [Unisim %s-729] TX_XCLK_SEL attribute is set to %s. Legal values for this attribute are TXOUT or TXUSR. Instance: %m", MODULE_NAME, TX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_PCS_CLK_PHASE_SEL_REG !== 1'b0) && (USE_PCS_CLK_PHASE_SEL_REG !== 1'b1))) begin
$display("Error: [Unisim %s-730] USE_PCS_CLK_PHASE_SEL attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, USE_PCS_CLK_PHASE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_PROGDIV_CFG_REG != 0.0) &&
(RX_PROGDIV_CFG_REG != 4.0) &&
(RX_PROGDIV_CFG_REG != 5.0) &&
(RX_PROGDIV_CFG_REG != 8.0) &&
(RX_PROGDIV_CFG_REG != 10.0) &&
(RX_PROGDIV_CFG_REG != 16.0) &&
(RX_PROGDIV_CFG_REG != 16.5) &&
(RX_PROGDIV_CFG_REG != 20.0) &&
(RX_PROGDIV_CFG_REG != 32.0) &&
(RX_PROGDIV_CFG_REG != 33.0) &&
(RX_PROGDIV_CFG_REG != 40.0) &&
(RX_PROGDIV_CFG_REG != 64.0) &&
(RX_PROGDIV_CFG_REG != 66.0) &&
(RX_PROGDIV_CFG_REG != 80.0) &&
(RX_PROGDIV_CFG_REG != 100.0))) begin
$display("Error: [Unisim %s-596] RX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0 or 100.0. Instance: %m", MODULE_NAME, RX_PROGDIV_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_VERSION_REG != 1.0) &&
(SIM_VERSION_REG != 2.0))) begin
$display("Error: [Unisim %s-629] SIM_VERSION attribute is set to %f. Legal values for this attribute are 1.0 or 2.0. Instance: %m", MODULE_NAME, SIM_VERSION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PROGDIV_CFG_REG != 0.0) &&
(TX_PROGDIV_CFG_REG != 4.0) &&
(TX_PROGDIV_CFG_REG != 5.0) &&
(TX_PROGDIV_CFG_REG != 8.0) &&
(TX_PROGDIV_CFG_REG != 10.0) &&
(TX_PROGDIV_CFG_REG != 16.0) &&
(TX_PROGDIV_CFG_REG != 16.5) &&
(TX_PROGDIV_CFG_REG != 20.0) &&
(TX_PROGDIV_CFG_REG != 32.0) &&
(TX_PROGDIV_CFG_REG != 33.0) &&
(TX_PROGDIV_CFG_REG != 40.0) &&
(TX_PROGDIV_CFG_REG != 64.0) &&
(TX_PROGDIV_CFG_REG != 66.0) &&
(TX_PROGDIV_CFG_REG != 80.0) &&
(TX_PROGDIV_CFG_REG != 100.0))) begin
$display("Error: [Unisim %s-715] TX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0 or 100.0. Instance: %m", MODULE_NAME, TX_PROGDIV_CFG_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
assign PMASCANCLK0_in = 1'b1; // tie off
assign PMASCANCLK1_in = 1'b1; // tie off
assign PMASCANCLK2_in = 1'b1; // tie off
assign PMASCANCLK3_in = 1'b1; // tie off
assign PMASCANCLK4_in = 1'b1; // tie off
assign PMASCANCLK5_in = 1'b1; // tie off
assign SCANCLK_in = 1'b1; // tie off
assign TSTCLK0_in = 1'b1; // tie off
assign TSTCLK1_in = 1'b1; // tie off
assign PMASCANENB_in = 1'b1; // tie off
assign PMASCANIN_in = 12'b111111111111; // tie off
assign PMASCANMODEB_in = 1'b1; // tie off
assign PMASCANRSTEN_in = 1'b1; // tie off
assign SARCCLK_in = 1'b1; // tie off
assign SCANENB_in = 1'b1; // tie off
assign SCANIN_in = 19'b1111111111111111111; // tie off
assign SCANMODEB_in = 1'b1; // tie off
assign TSTPDOVRDB_in = 1'b1; // tie off
assign TSTPD_in = 5'b11111; // tie off
SIP_GTYE3_CHANNEL #(
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL),
.SIM_VERSION (SIM_VERSION)
) SIP_GTYE3_CHANNEL_INST (
.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE_REG),
.ACJTAG_MODE (ACJTAG_MODE_REG),
.ACJTAG_RESET (ACJTAG_RESET_REG),
.ADAPT_CFG0 (ADAPT_CFG0_REG),
.ADAPT_CFG1 (ADAPT_CFG1_REG),
.ADAPT_CFG2 (ADAPT_CFG2_REG),
.AEN_CDRSTEPSEL (AEN_CDRSTEPSEL_REG),
.AEN_CPLL (AEN_CPLL_REG),
.AEN_ELPCAL (AEN_ELPCAL_REG),
.AEN_EYESCAN (AEN_EYESCAN_REG),
.AEN_LOOPBACK (AEN_LOOPBACK_REG),
.AEN_MASTER (AEN_MASTER_REG),
.AEN_MUXDCD (AEN_MUXDCD_REG),
.AEN_PD_AND_EIDLE (AEN_PD_AND_EIDLE_REG),
.AEN_POLARITY (AEN_POLARITY_REG),
.AEN_PRBS (AEN_PRBS_REG),
.AEN_RESET (AEN_RESET_REG),
.AEN_RXCDR (AEN_RXCDR_REG),
.AEN_RXDFE (AEN_RXDFE_REG),
.AEN_RXDFELPM (AEN_RXDFELPM_REG),
.AEN_RXOUTCLK_SEL (AEN_RXOUTCLK_SEL_REG),
.AEN_RXPHDLY (AEN_RXPHDLY_REG),
.AEN_RXPLLCLK_SEL (AEN_RXPLLCLK_SEL_REG),
.AEN_RXSYSCLK_SEL (AEN_RXSYSCLK_SEL_REG),
.AEN_TXOUTCLK_SEL (AEN_TXOUTCLK_SEL_REG),
.AEN_TXPHDLY (AEN_TXPHDLY_REG),
.AEN_TXPI_PPM (AEN_TXPI_PPM_REG),
.AEN_TXPLLCLK_SEL (AEN_TXPLLCLK_SEL_REG),
.AEN_TXSYSCLK_SEL (AEN_TXSYSCLK_SEL_REG),
.AEN_TX_DRIVE_MODE (AEN_TX_DRIVE_MODE_REG),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE_REG),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE_REG),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD_REG),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET_REG),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE_REG),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET_REG),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE_REG),
.AMONITOR_CFG (AMONITOR_CFG_REG),
.AUTO_BW_SEL_BYPASS (AUTO_BW_SEL_BYPASS_REG),
.A_AFECFOKEN (A_AFECFOKEN_REG),
.A_CPLLLOCKEN (A_CPLLLOCKEN_REG),
.A_CPLLPD (A_CPLLPD_REG),
.A_CPLLRESET (A_CPLLRESET_REG),
.A_DFECFOKFCDAC (A_DFECFOKFCDAC_REG),
.A_DFECFOKFCNUM (A_DFECFOKFCNUM_REG),
.A_DFECFOKFPULSE (A_DFECFOKFPULSE_REG),
.A_DFECFOKHOLD (A_DFECFOKHOLD_REG),
.A_DFECFOKOVREN (A_DFECFOKOVREN_REG),
.A_ELPCALDVORWREN (A_ELPCALDVORWREN_REG),
.A_ELPCALPAORWREN (A_ELPCALPAORWREN_REG),
.A_EYESCANMODE (A_EYESCANMODE_REG),
.A_EYESCANRESET (A_EYESCANRESET_REG),
.A_GTRESETSEL (A_GTRESETSEL_REG),
.A_GTRXRESET (A_GTRXRESET_REG),
.A_GTTXRESET (A_GTTXRESET_REG),
.A_LOOPBACK (A_LOOPBACK_REG),
.A_LPMGCHOLD (A_LPMGCHOLD_REG),
.A_LPMGCOVREN (A_LPMGCOVREN_REG),
.A_LPMOSHOLD (A_LPMOSHOLD_REG),
.A_LPMOSOVREN (A_LPMOSOVREN_REG),
.A_MUXDCDEXHOLD (A_MUXDCDEXHOLD_REG),
.A_MUXDCDORWREN (A_MUXDCDORWREN_REG),
.A_RXBUFRESET (A_RXBUFRESET_REG),
.A_RXCDRFREQRESET (A_RXCDRFREQRESET_REG),
.A_RXCDRHOLD (A_RXCDRHOLD_REG),
.A_RXCDROVRDEN (A_RXCDROVRDEN_REG),
.A_RXCDRRESET (A_RXCDRRESET_REG),
.A_RXDFEAGCHOLD (A_RXDFEAGCHOLD_REG),
.A_RXDFEAGCOVRDEN (A_RXDFEAGCOVRDEN_REG),
.A_RXDFECFOKFEN (A_RXDFECFOKFEN_REG),
.A_RXDFELFHOLD (A_RXDFELFHOLD_REG),
.A_RXDFELFOVRDEN (A_RXDFELFOVRDEN_REG),
.A_RXDFELPMRESET (A_RXDFELPMRESET_REG),
.A_RXDFETAP10HOLD (A_RXDFETAP10HOLD_REG),
.A_RXDFETAP10OVRDEN (A_RXDFETAP10OVRDEN_REG),
.A_RXDFETAP11HOLD (A_RXDFETAP11HOLD_REG),
.A_RXDFETAP11OVRDEN (A_RXDFETAP11OVRDEN_REG),
.A_RXDFETAP12HOLD (A_RXDFETAP12HOLD_REG),
.A_RXDFETAP12OVRDEN (A_RXDFETAP12OVRDEN_REG),
.A_RXDFETAP13HOLD (A_RXDFETAP13HOLD_REG),
.A_RXDFETAP13OVRDEN (A_RXDFETAP13OVRDEN_REG),
.A_RXDFETAP14HOLD (A_RXDFETAP14HOLD_REG),
.A_RXDFETAP14OVRDEN (A_RXDFETAP14OVRDEN_REG),
.A_RXDFETAP15HOLD (A_RXDFETAP15HOLD_REG),
.A_RXDFETAP15OVRDEN (A_RXDFETAP15OVRDEN_REG),
.A_RXDFETAP2HOLD (A_RXDFETAP2HOLD_REG),
.A_RXDFETAP2OVRDEN (A_RXDFETAP2OVRDEN_REG),
.A_RXDFETAP3HOLD (A_RXDFETAP3HOLD_REG),
.A_RXDFETAP3OVRDEN (A_RXDFETAP3OVRDEN_REG),
.A_RXDFETAP4HOLD (A_RXDFETAP4HOLD_REG),
.A_RXDFETAP4OVRDEN (A_RXDFETAP4OVRDEN_REG),
.A_RXDFETAP5HOLD (A_RXDFETAP5HOLD_REG),
.A_RXDFETAP5OVRDEN (A_RXDFETAP5OVRDEN_REG),
.A_RXDFETAP6HOLD (A_RXDFETAP6HOLD_REG),
.A_RXDFETAP6OVRDEN (A_RXDFETAP6OVRDEN_REG),
.A_RXDFETAP7HOLD (A_RXDFETAP7HOLD_REG),
.A_RXDFETAP7OVRDEN (A_RXDFETAP7OVRDEN_REG),
.A_RXDFETAP8HOLD (A_RXDFETAP8HOLD_REG),
.A_RXDFETAP8OVRDEN (A_RXDFETAP8OVRDEN_REG),
.A_RXDFETAP9HOLD (A_RXDFETAP9HOLD_REG),
.A_RXDFETAP9OVRDEN (A_RXDFETAP9OVRDEN_REG),
.A_RXDFEUTHOLD (A_RXDFEUTHOLD_REG),
.A_RXDFEUTOVRDEN (A_RXDFEUTOVRDEN_REG),
.A_RXDFEVPHOLD (A_RXDFEVPHOLD_REG),
.A_RXDFEVPOVRDEN (A_RXDFEVPOVRDEN_REG),
.A_RXDFEVSEN (A_RXDFEVSEN_REG),
.A_RXDFEXYDEN (A_RXDFEXYDEN_REG),
.A_RXDLYBYPASS (A_RXDLYBYPASS_REG),
.A_RXDLYEN (A_RXDLYEN_REG),
.A_RXDLYOVRDEN (A_RXDLYOVRDEN_REG),
.A_RXDLYSRESET (A_RXDLYSRESET_REG),
.A_RXLPMEN (A_RXLPMEN_REG),
.A_RXLPMHFHOLD (A_RXLPMHFHOLD_REG),
.A_RXLPMHFOVRDEN (A_RXLPMHFOVRDEN_REG),
.A_RXLPMLFHOLD (A_RXLPMLFHOLD_REG),
.A_RXLPMLFKLOVRDEN (A_RXLPMLFKLOVRDEN_REG),
.A_RXMONITORSEL (A_RXMONITORSEL_REG),
.A_RXOOBRESET (A_RXOOBRESET_REG),
.A_RXOSCALRESET (A_RXOSCALRESET_REG),
.A_RXOSHOLD (A_RXOSHOLD_REG),
.A_RXOSOVRDEN (A_RXOSOVRDEN_REG),
.A_RXOUTCLKSEL (A_RXOUTCLKSEL_REG),
.A_RXPCSRESET (A_RXPCSRESET_REG),
.A_RXPD (A_RXPD_REG),
.A_RXPHALIGN (A_RXPHALIGN_REG),
.A_RXPHALIGNEN (A_RXPHALIGNEN_REG),
.A_RXPHDLYPD (A_RXPHDLYPD_REG),
.A_RXPHDLYRESET (A_RXPHDLYRESET_REG),
.A_RXPHOVRDEN (A_RXPHOVRDEN_REG),
.A_RXPLLCLKSEL (A_RXPLLCLKSEL_REG),
.A_RXPMARESET (A_RXPMARESET_REG),
.A_RXPOLARITY (A_RXPOLARITY_REG),
.A_RXPRBSCNTRESET (A_RXPRBSCNTRESET_REG),
.A_RXPRBSSEL (A_RXPRBSSEL_REG),
.A_RXPROGDIVRESET (A_RXPROGDIVRESET_REG),
.A_RXSYSCLKSEL (A_RXSYSCLKSEL_REG),
.A_TXBUFDIFFCTRL (A_TXBUFDIFFCTRL_REG),
.A_TXDEEMPH (A_TXDEEMPH_REG),
.A_TXDIFFCTRL (A_TXDIFFCTRL_REG),
.A_TXDLYBYPASS (A_TXDLYBYPASS_REG),
.A_TXDLYEN (A_TXDLYEN_REG),
.A_TXDLYOVRDEN (A_TXDLYOVRDEN_REG),
.A_TXDLYSRESET (A_TXDLYSRESET_REG),
.A_TXELECIDLE (A_TXELECIDLE_REG),
.A_TXINHIBIT (A_TXINHIBIT_REG),
.A_TXMAINCURSOR (A_TXMAINCURSOR_REG),
.A_TXMARGIN (A_TXMARGIN_REG),
.A_TXOUTCLKSEL (A_TXOUTCLKSEL_REG),
.A_TXPCSRESET (A_TXPCSRESET_REG),
.A_TXPD (A_TXPD_REG),
.A_TXPHALIGN (A_TXPHALIGN_REG),
.A_TXPHALIGNEN (A_TXPHALIGNEN_REG),
.A_TXPHDLYPD (A_TXPHDLYPD_REG),
.A_TXPHDLYRESET (A_TXPHDLYRESET_REG),
.A_TXPHINIT (A_TXPHINIT_REG),
.A_TXPHOVRDEN (A_TXPHOVRDEN_REG),
.A_TXPIPPMOVRDEN (A_TXPIPPMOVRDEN_REG),
.A_TXPIPPMPD (A_TXPIPPMPD_REG),
.A_TXPIPPMSEL (A_TXPIPPMSEL_REG),
.A_TXPLLCLKSEL (A_TXPLLCLKSEL_REG),
.A_TXPMARESET (A_TXPMARESET_REG),
.A_TXPOLARITY (A_TXPOLARITY_REG),
.A_TXPOSTCURSOR (A_TXPOSTCURSOR_REG),
.A_TXPRBSFORCEERR (A_TXPRBSFORCEERR_REG),
.A_TXPRBSSEL (A_TXPRBSSEL_REG),
.A_TXPRECURSOR (A_TXPRECURSOR_REG),
.A_TXPROGDIVRESET (A_TXPROGDIVRESET_REG),
.A_TXSWING (A_TXSWING_REG),
.A_TXSYSCLKSEL (A_TXSYSCLKSEL_REG),
.CAPBYPASS_FORCE (CAPBYPASS_FORCE_REG),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL_REG),
.CDR_SWAP_MODE_EN (CDR_SWAP_MODE_EN_REG),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN_REG),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW_REG),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1_REG),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2_REG),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3_REG),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4_REG),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE_REG),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1_REG),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2_REG),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3_REG),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4_REG),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE_REG),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE_REG),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_REG),
.CH_HSPMUX (CH_HSPMUX_REG),
.CKCAL1_CFG_0 (CKCAL1_CFG_0_REG),
.CKCAL1_CFG_1 (CKCAL1_CFG_1_REG),
.CKCAL1_CFG_2 (CKCAL1_CFG_2_REG),
.CKCAL1_CFG_3 (CKCAL1_CFG_3_REG),
.CKCAL2_CFG_0 (CKCAL2_CFG_0_REG),
.CKCAL2_CFG_1 (CKCAL2_CFG_1_REG),
.CKCAL2_CFG_2 (CKCAL2_CFG_2_REG),
.CKCAL2_CFG_3 (CKCAL2_CFG_3_REG),
.CKCAL2_CFG_4 (CKCAL2_CFG_4_REG),
.CKCAL_RSVD0 (CKCAL_RSVD0_REG),
.CKCAL_RSVD1 (CKCAL_RSVD1_REG),
.CLK_CORRECT_USE (CLK_CORRECT_USE_REG),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE_REG),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT_REG),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT_REG),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE_REG),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT_REG),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1_REG),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2_REG),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3_REG),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4_REG),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE_REG),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1_REG),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2_REG),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3_REG),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4_REG),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE_REG),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE_REG),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_REG),
.CPLL_CFG0 (CPLL_CFG0_REG),
.CPLL_CFG1 (CPLL_CFG1_REG),
.CPLL_CFG2 (CPLL_CFG2_REG),
.CPLL_CFG3 (CPLL_CFG3_REG),
.CPLL_FBDIV (CPLL_FBDIV_REG),
.CPLL_FBDIV_45 (CPLL_FBDIV_45_REG),
.CPLL_INIT_CFG0 (CPLL_INIT_CFG0_REG),
.CPLL_INIT_CFG1 (CPLL_INIT_CFG1_REG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG_REG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV_REG),
.CTLE3_OCAP_EXT_CTRL (CTLE3_OCAP_EXT_CTRL_REG),
.CTLE3_OCAP_EXT_EN (CTLE3_OCAP_EXT_EN_REG),
.DDI_CTRL (DDI_CTRL_REG),
.DDI_REALIGN_WAIT (DDI_REALIGN_WAIT_REG),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT_REG),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT_REG),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY_REG),
.DFE_D_X_REL_POS (DFE_D_X_REL_POS_REG),
.DFE_VCM_COMP_EN (DFE_VCM_COMP_EN_REG),
.DMONITOR_CFG0 (DMONITOR_CFG0_REG),
.DMONITOR_CFG1 (DMONITOR_CFG1_REG),
.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL_REG),
.ES_CONTROL (ES_CONTROL_REG),
.ES_ERRDET_EN (ES_ERRDET_EN_REG),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN_REG),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET_REG),
.ES_PMA_CFG (ES_PMA_CFG_REG),
.ES_PRESCALE (ES_PRESCALE_REG),
.ES_QUALIFIER0 (ES_QUALIFIER0_REG),
.ES_QUALIFIER1 (ES_QUALIFIER1_REG),
.ES_QUALIFIER2 (ES_QUALIFIER2_REG),
.ES_QUALIFIER3 (ES_QUALIFIER3_REG),
.ES_QUALIFIER4 (ES_QUALIFIER4_REG),
.ES_QUALIFIER5 (ES_QUALIFIER5_REG),
.ES_QUALIFIER6 (ES_QUALIFIER6_REG),
.ES_QUALIFIER7 (ES_QUALIFIER7_REG),
.ES_QUALIFIER8 (ES_QUALIFIER8_REG),
.ES_QUALIFIER9 (ES_QUALIFIER9_REG),
.ES_QUAL_MASK0 (ES_QUAL_MASK0_REG),
.ES_QUAL_MASK1 (ES_QUAL_MASK1_REG),
.ES_QUAL_MASK2 (ES_QUAL_MASK2_REG),
.ES_QUAL_MASK3 (ES_QUAL_MASK3_REG),
.ES_QUAL_MASK4 (ES_QUAL_MASK4_REG),
.ES_QUAL_MASK5 (ES_QUAL_MASK5_REG),
.ES_QUAL_MASK6 (ES_QUAL_MASK6_REG),
.ES_QUAL_MASK7 (ES_QUAL_MASK7_REG),
.ES_QUAL_MASK8 (ES_QUAL_MASK8_REG),
.ES_QUAL_MASK9 (ES_QUAL_MASK9_REG),
.ES_SDATA_MASK0 (ES_SDATA_MASK0_REG),
.ES_SDATA_MASK1 (ES_SDATA_MASK1_REG),
.ES_SDATA_MASK2 (ES_SDATA_MASK2_REG),
.ES_SDATA_MASK3 (ES_SDATA_MASK3_REG),
.ES_SDATA_MASK4 (ES_SDATA_MASK4_REG),
.ES_SDATA_MASK5 (ES_SDATA_MASK5_REG),
.ES_SDATA_MASK6 (ES_SDATA_MASK6_REG),
.ES_SDATA_MASK7 (ES_SDATA_MASK7_REG),
.ES_SDATA_MASK8 (ES_SDATA_MASK8_REG),
.ES_SDATA_MASK9 (ES_SDATA_MASK9_REG),
.EVODD_PHI_CFG (EVODD_PHI_CFG_REG),
.EYE_SCAN_SWAP_EN (EYE_SCAN_SWAP_EN_REG),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE_REG),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG_REG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN_REG),
.GEARBOX_MODE (GEARBOX_MODE_REG),
.GEN_RXUSRCLK (GEN_RXUSRCLK_REG),
.GEN_TXUSRCLK (GEN_TXUSRCLK_REG),
.GM_BIAS_SELECT (GM_BIAS_SELECT_REG),
.GT_INSTANTIATED (GT_INSTANTIATED_REG),
.ISCAN_CK_PH_SEL2 (ISCAN_CK_PH_SEL2_REG),
.LOCAL_MASTER (LOCAL_MASTER_REG),
.LOOP0_CFG (LOOP0_CFG_REG),
.LOOP10_CFG (LOOP10_CFG_REG),
.LOOP11_CFG (LOOP11_CFG_REG),
.LOOP12_CFG (LOOP12_CFG_REG),
.LOOP13_CFG (LOOP13_CFG_REG),
.LOOP1_CFG (LOOP1_CFG_REG),
.LOOP2_CFG (LOOP2_CFG_REG),
.LOOP3_CFG (LOOP3_CFG_REG),
.LOOP4_CFG (LOOP4_CFG_REG),
.LOOP5_CFG (LOOP5_CFG_REG),
.LOOP6_CFG (LOOP6_CFG_REG),
.LOOP7_CFG (LOOP7_CFG_REG),
.LOOP8_CFG (LOOP8_CFG_REG),
.LOOP9_CFG (LOOP9_CFG_REG),
.LPBK_BIAS_CTRL (LPBK_BIAS_CTRL_REG),
.LPBK_EN_RCAL_B (LPBK_EN_RCAL_B_REG),
.LPBK_EXT_RCAL (LPBK_EXT_RCAL_REG),
.LPBK_RG_CTRL (LPBK_RG_CTRL_REG),
.OOBDIVCTL (OOBDIVCTL_REG),
.OOB_PWRUP (OOB_PWRUP_REG),
.PCI3_AUTO_REALIGN (PCI3_AUTO_REALIGN_REG),
.PCI3_PIPE_RX_ELECIDLE (PCI3_PIPE_RX_ELECIDLE_REG),
.PCI3_RX_ASYNC_EBUF_BYPASS (PCI3_RX_ASYNC_EBUF_BYPASS_REG),
.PCI3_RX_ELECIDLE_EI2_ENABLE (PCI3_RX_ELECIDLE_EI2_ENABLE_REG),
.PCI3_RX_ELECIDLE_H2L_COUNT (PCI3_RX_ELECIDLE_H2L_COUNT_REG),
.PCI3_RX_ELECIDLE_H2L_DISABLE (PCI3_RX_ELECIDLE_H2L_DISABLE_REG),
.PCI3_RX_ELECIDLE_HI_COUNT (PCI3_RX_ELECIDLE_HI_COUNT_REG),
.PCI3_RX_ELECIDLE_LP4_DISABLE (PCI3_RX_ELECIDLE_LP4_DISABLE_REG),
.PCI3_RX_FIFO_DISABLE (PCI3_RX_FIFO_DISABLE_REG),
.PCIE_BUFG_DIV_CTRL (PCIE_BUFG_DIV_CTRL_REG),
.PCIE_RXPCS_CFG_GEN3 (PCIE_RXPCS_CFG_GEN3_REG),
.PCIE_RXPMA_CFG (PCIE_RXPMA_CFG_REG),
.PCIE_TXPCS_CFG_GEN3 (PCIE_TXPCS_CFG_GEN3_REG),
.PCIE_TXPMA_CFG (PCIE_TXPMA_CFG_REG),
.PCS_PCIE_EN (PCS_PCIE_EN_REG),
.PCS_RSVD0 (PCS_RSVD0_REG),
.PCS_RSVD1 (PCS_RSVD1_REG),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2_REG),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2_REG),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2_REG),
.PLL_SEL_MODE_GEN12 (PLL_SEL_MODE_GEN12_REG),
.PLL_SEL_MODE_GEN3 (PLL_SEL_MODE_GEN3_REG),
.PMA_RSV0 (PMA_RSV0_REG),
.PMA_RSV1 (PMA_RSV1_REG),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST_REG),
.PROCESS_PAR (PROCESS_PAR_REG),
.RATE_SW_USE_DRP (RATE_SW_USE_DRP_REG),
.RESET_POWERSAVE_DISABLE (RESET_POWERSAVE_DISABLE_REG),
.RXBUFRESET_TIME (RXBUFRESET_TIME_REG),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE_REG),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT_REG),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT_REG),
.RXBUF_EN (RXBUF_EN_REG),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE_REG),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN_REG),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE_REG),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE_REG),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW_REG),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD_REG),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW_REG),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME_REG),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME_REG),
.RXCDR_CFG0 (RXCDR_CFG0_REG),
.RXCDR_CFG0_GEN3 (RXCDR_CFG0_GEN3_REG),
.RXCDR_CFG1 (RXCDR_CFG1_REG),
.RXCDR_CFG1_GEN3 (RXCDR_CFG1_GEN3_REG),
.RXCDR_CFG2 (RXCDR_CFG2_REG),
.RXCDR_CFG2_GEN3 (RXCDR_CFG2_GEN3_REG),
.RXCDR_CFG3 (RXCDR_CFG3_REG),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3_REG),
.RXCDR_CFG4 (RXCDR_CFG4_REG),
.RXCDR_CFG4_GEN3 (RXCDR_CFG4_GEN3_REG),
.RXCDR_CFG5 (RXCDR_CFG5_REG),
.RXCDR_CFG5_GEN3 (RXCDR_CFG5_GEN3_REG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE_REG),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE_REG),
.RXCDR_LOCK_CFG0 (RXCDR_LOCK_CFG0_REG),
.RXCDR_LOCK_CFG1 (RXCDR_LOCK_CFG1_REG),
.RXCDR_LOCK_CFG2 (RXCDR_LOCK_CFG2_REG),
.RXCDR_LOCK_CFG3 (RXCDR_LOCK_CFG3_REG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE_REG),
.RXCFOKDONE_SRC (RXCFOKDONE_SRC_REG),
.RXCFOK_CFG0 (RXCFOK_CFG0_REG),
.RXCFOK_CFG1 (RXCFOK_CFG1_REG),
.RXCFOK_CFG2 (RXCFOK_CFG2_REG),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME_REG),
.RXDFELPM_KL_CFG0 (RXDFELPM_KL_CFG0_REG),
.RXDFELPM_KL_CFG1 (RXDFELPM_KL_CFG1_REG),
.RXDFELPM_KL_CFG2 (RXDFELPM_KL_CFG2_REG),
.RXDFE_CFG0 (RXDFE_CFG0_REG),
.RXDFE_CFG1 (RXDFE_CFG1_REG),
.RXDFE_GC_CFG0 (RXDFE_GC_CFG0_REG),
.RXDFE_GC_CFG1 (RXDFE_GC_CFG1_REG),
.RXDFE_GC_CFG2 (RXDFE_GC_CFG2_REG),
.RXDFE_H2_CFG0 (RXDFE_H2_CFG0_REG),
.RXDFE_H2_CFG1 (RXDFE_H2_CFG1_REG),
.RXDFE_H3_CFG0 (RXDFE_H3_CFG0_REG),
.RXDFE_H3_CFG1 (RXDFE_H3_CFG1_REG),
.RXDFE_H4_CFG0 (RXDFE_H4_CFG0_REG),
.RXDFE_H4_CFG1 (RXDFE_H4_CFG1_REG),
.RXDFE_H5_CFG0 (RXDFE_H5_CFG0_REG),
.RXDFE_H5_CFG1 (RXDFE_H5_CFG1_REG),
.RXDFE_H6_CFG0 (RXDFE_H6_CFG0_REG),
.RXDFE_H6_CFG1 (RXDFE_H6_CFG1_REG),
.RXDFE_H7_CFG0 (RXDFE_H7_CFG0_REG),
.RXDFE_H7_CFG1 (RXDFE_H7_CFG1_REG),
.RXDFE_H8_CFG0 (RXDFE_H8_CFG0_REG),
.RXDFE_H8_CFG1 (RXDFE_H8_CFG1_REG),
.RXDFE_H9_CFG0 (RXDFE_H9_CFG0_REG),
.RXDFE_H9_CFG1 (RXDFE_H9_CFG1_REG),
.RXDFE_HA_CFG0 (RXDFE_HA_CFG0_REG),
.RXDFE_HA_CFG1 (RXDFE_HA_CFG1_REG),
.RXDFE_HB_CFG0 (RXDFE_HB_CFG0_REG),
.RXDFE_HB_CFG1 (RXDFE_HB_CFG1_REG),
.RXDFE_HC_CFG0 (RXDFE_HC_CFG0_REG),
.RXDFE_HC_CFG1 (RXDFE_HC_CFG1_REG),
.RXDFE_HD_CFG0 (RXDFE_HD_CFG0_REG),
.RXDFE_HD_CFG1 (RXDFE_HD_CFG1_REG),
.RXDFE_HE_CFG0 (RXDFE_HE_CFG0_REG),
.RXDFE_HE_CFG1 (RXDFE_HE_CFG1_REG),
.RXDFE_HF_CFG0 (RXDFE_HF_CFG0_REG),
.RXDFE_HF_CFG1 (RXDFE_HF_CFG1_REG),
.RXDFE_OS_CFG0 (RXDFE_OS_CFG0_REG),
.RXDFE_OS_CFG1 (RXDFE_OS_CFG1_REG),
.RXDFE_PWR_SAVING (RXDFE_PWR_SAVING_REG),
.RXDFE_UT_CFG0 (RXDFE_UT_CFG0_REG),
.RXDFE_UT_CFG1 (RXDFE_UT_CFG1_REG),
.RXDFE_VP_CFG0 (RXDFE_VP_CFG0_REG),
.RXDFE_VP_CFG1 (RXDFE_VP_CFG1_REG),
.RXDLY_CFG (RXDLY_CFG_REG),
.RXDLY_LCFG (RXDLY_LCFG_REG),
.RXELECIDLE_CFG (RXELECIDLE_CFG_REG),
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR_REG),
.RXGEARBOX_EN (RXGEARBOX_EN_REG),
.RXISCANRESET_TIME (RXISCANRESET_TIME_REG),
.RXLPM_CFG (RXLPM_CFG_REG),
.RXLPM_GC_CFG (RXLPM_GC_CFG_REG),
.RXLPM_KH_CFG0 (RXLPM_KH_CFG0_REG),
.RXLPM_KH_CFG1 (RXLPM_KH_CFG1_REG),
.RXLPM_OS_CFG0 (RXLPM_OS_CFG0_REG),
.RXLPM_OS_CFG1 (RXLPM_OS_CFG1_REG),
.RXOOB_CFG (RXOOB_CFG_REG),
.RXOOB_CLK_CFG (RXOOB_CLK_CFG_REG),
.RXOSCALRESET_TIME (RXOSCALRESET_TIME_REG),
.RXOUT_DIV (RXOUT_DIV_REG),
.RXPCSRESET_TIME (RXPCSRESET_TIME_REG),
.RXPHBEACON_CFG (RXPHBEACON_CFG_REG),
.RXPHDLY_CFG (RXPHDLY_CFG_REG),
.RXPHSAMP_CFG (RXPHSAMP_CFG_REG),
.RXPHSLIP_CFG (RXPHSLIP_CFG_REG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL_REG),
.RXPI_AUTO_BW_SEL_BYPASS (RXPI_AUTO_BW_SEL_BYPASS_REG),
.RXPI_CFG (RXPI_CFG_REG),
.RXPI_LPM (RXPI_LPM_REG),
.RXPI_RSV0 (RXPI_RSV0_REG),
.RXPI_SEL_LC (RXPI_SEL_LC_REG),
.RXPI_STARTCODE (RXPI_STARTCODE_REG),
.RXPI_VREFSEL (RXPI_VREFSEL_REG),
.RXPLL_SEL (RXPLL_SEL_REG),
.RXPMACLK_SEL (RXPMACLK_SEL_REG),
.RXPMARESET_TIME (RXPMARESET_TIME_REG),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK_REG),
.RXPRBS_LINKACQ_CNT (RXPRBS_LINKACQ_CNT_REG),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT_REG),
.RXSLIDE_MODE (RXSLIDE_MODE_REG),
.RXSYNC_MULTILANE (RXSYNC_MULTILANE_REG),
.RXSYNC_OVRD (RXSYNC_OVRD_REG),
.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA_REG),
.RX_AFE_CM_EN (RX_AFE_CM_EN_REG),
.RX_BIAS_CFG0 (RX_BIAS_CFG0_REG),
.RX_BUFFER_CFG (RX_BUFFER_CFG_REG),
.RX_CAPFF_SARC_ENB (RX_CAPFF_SARC_ENB_REG),
.RX_CLK25_DIV (RX_CLK25_DIV_REG),
.RX_CLKMUX_EN (RX_CLKMUX_EN_REG),
.RX_CLK_SLIP_OVRD (RX_CLK_SLIP_OVRD_REG),
.RX_CM_BUF_CFG (RX_CM_BUF_CFG_REG),
.RX_CM_BUF_PD (RX_CM_BUF_PD_REG),
.RX_CM_SEL (RX_CM_SEL_REG),
.RX_CM_TRIM (RX_CM_TRIM_REG),
.RX_CTLE1_KHKL (RX_CTLE1_KHKL_REG),
.RX_CTLE2_KHKL (RX_CTLE2_KHKL_REG),
.RX_CTLE3_AGC (RX_CTLE3_AGC_REG),
.RX_DATA_WIDTH (RX_DATA_WIDTH_REG),
.RX_DDI_SEL (RX_DDI_SEL_REG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN_REG),
.RX_DEGEN_CTRL (RX_DEGEN_CTRL_REG),
.RX_DFELPM_CFG0 (RX_DFELPM_CFG0_REG),
.RX_DFELPM_CFG1 (RX_DFELPM_CFG1_REG),
.RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN_REG),
.RX_DFE_AGC_CFG0 (RX_DFE_AGC_CFG0_REG),
.RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1_REG),
.RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0_REG),
.RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1_REG),
.RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0_REG),
.RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1_REG),
.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE_REG),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH_REG),
.RX_DIV2_MODE_B (RX_DIV2_MODE_B_REG),
.RX_DIVRESET_TIME (RX_DIVRESET_TIME_REG),
.RX_EN_CTLE_RCAL_B (RX_EN_CTLE_RCAL_B_REG),
.RX_EN_HI_LR (RX_EN_HI_LR_REG),
.RX_EXT_RL_CTRL (RX_EXT_RL_CTRL_REG),
.RX_EYESCAN_VS_CODE (RX_EYESCAN_VS_CODE_REG),
.RX_EYESCAN_VS_NEG_DIR (RX_EYESCAN_VS_NEG_DIR_REG),
.RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE_REG),
.RX_EYESCAN_VS_UT_SIGN (RX_EYESCAN_VS_UT_SIGN_REG),
.RX_FABINT_USRCLK_FLOP (RX_FABINT_USRCLK_FLOP_REG),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH_REG),
.RX_PMA_POWER_SAVE (RX_PMA_POWER_SAVE_REG),
.RX_PROGDIV_CFG (RX_PROGDIV_CFG_BIN),
.RX_PROGDIV_RATE (RX_PROGDIV_RATE_REG),
.RX_RESLOAD_CTRL (RX_RESLOAD_CTRL_REG),
.RX_RESLOAD_OVRD (RX_RESLOAD_OVRD_REG),
.RX_SAMPLE_PERIOD (RX_SAMPLE_PERIOD_REG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_REG),
.RX_SUM_DFETAPREP_EN (RX_SUM_DFETAPREP_EN_REG),
.RX_SUM_IREF_TUNE (RX_SUM_IREF_TUNE_REG),
.RX_SUM_VCMTUNE (RX_SUM_VCMTUNE_REG),
.RX_SUM_VCM_OVWR (RX_SUM_VCM_OVWR_REG),
.RX_SUM_VREF_TUNE (RX_SUM_VREF_TUNE_REG),
.RX_TUNE_AFE_OS (RX_TUNE_AFE_OS_REG),
.RX_VREG_CTRL (RX_VREG_CTRL_REG),
.RX_VREG_PDB (RX_VREG_PDB_REG),
.RX_WIDEMODE_CDR (RX_WIDEMODE_CDR_REG),
.RX_XCLK_SEL (RX_XCLK_SEL_REG),
.RX_XMODE_SEL (RX_XMODE_SEL_REG),
.SAS_MAX_COM (SAS_MAX_COM_REG),
.SAS_MIN_COM (SAS_MIN_COM_REG),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN_REG),
.SATA_BURST_VAL (SATA_BURST_VAL_REG),
.SATA_CPLL_CFG (SATA_CPLL_CFG_REG),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL_REG),
.SATA_MAX_BURST (SATA_MAX_BURST_REG),
.SATA_MAX_INIT (SATA_MAX_INIT_REG),
.SATA_MAX_WAKE (SATA_MAX_WAKE_REG),
.SATA_MIN_BURST (SATA_MIN_BURST_REG),
.SATA_MIN_INIT (SATA_MIN_INIT_REG),
.SATA_MIN_WAKE (SATA_MIN_WAKE_REG),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA_REG),
.TAPDLY_SET_TX (TAPDLY_SET_TX_REG),
.TEMPERATURE_PAR (TEMPERATURE_PAR_REG),
.TERM_RCAL_CFG (TERM_RCAL_CFG_REG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD_REG),
.TRANS_TIME_RATE (TRANS_TIME_RATE_REG),
.TST_RSV0 (TST_RSV0_REG),
.TST_RSV1 (TST_RSV1_REG),
.TXBUF_EN (TXBUF_EN_REG),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE_REG),
.TXDLY_CFG (TXDLY_CFG_REG),
.TXDLY_LCFG (TXDLY_LCFG_REG),
.TXFIFO_ADDR_CFG (TXFIFO_ADDR_CFG_REG),
.TXGBOX_FIFO_INIT_RD_ADDR (TXGBOX_FIFO_INIT_RD_ADDR_REG),
.TXGEARBOX_EN (TXGEARBOX_EN_REG),
.TXOUTCLKPCS_SEL (TXOUTCLKPCS_SEL_REG),
.TXOUT_DIV (TXOUT_DIV_REG),
.TXPCSRESET_TIME (TXPCSRESET_TIME_REG),
.TXPHDLY_CFG0 (TXPHDLY_CFG0_REG),
.TXPHDLY_CFG1 (TXPHDLY_CFG1_REG),
.TXPH_CFG (TXPH_CFG_REG),
.TXPH_CFG2 (TXPH_CFG2_REG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL_REG),
.TXPI_CFG0 (TXPI_CFG0_REG),
.TXPI_CFG1 (TXPI_CFG1_REG),
.TXPI_CFG2 (TXPI_CFG2_REG),
.TXPI_CFG3 (TXPI_CFG3_REG),
.TXPI_CFG4 (TXPI_CFG4_REG),
.TXPI_CFG5 (TXPI_CFG5_REG),
.TXPI_GRAY_SEL (TXPI_GRAY_SEL_REG),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL_REG),
.TXPI_LPM (TXPI_LPM_REG),
.TXPI_PPMCLK_SEL (TXPI_PPMCLK_SEL_REG),
.TXPI_PPM_CFG (TXPI_PPM_CFG_REG),
.TXPI_RSV0 (TXPI_RSV0_REG),
.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM_REG),
.TXPI_VREFSEL (TXPI_VREFSEL_REG),
.TXPMARESET_TIME (TXPMARESET_TIME_REG),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE_REG),
.TXSYNC_OVRD (TXSYNC_OVRD_REG),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA_REG),
.TX_CLK25_DIV (TX_CLK25_DIV_REG),
.TX_CLKMUX_EN (TX_CLKMUX_EN_REG),
.TX_CLKREG_PDB (TX_CLKREG_PDB_REG),
.TX_CLKREG_SET (TX_CLKREG_SET_REG),
.TX_DATA_WIDTH (TX_DATA_WIDTH_REG),
.TX_DCD_CFG (TX_DCD_CFG_REG),
.TX_DCD_EN (TX_DCD_EN_REG),
.TX_DEEMPH0 (TX_DEEMPH0_REG),
.TX_DEEMPH1 (TX_DEEMPH1_REG),
.TX_DIVRESET_TIME (TX_DIVRESET_TIME_REG),
.TX_DRIVE_MODE (TX_DRIVE_MODE_REG),
.TX_DRVMUX_CTRL (TX_DRVMUX_CTRL_REG),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY_REG),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY_REG),
.TX_EML_PHI_TUNE (TX_EML_PHI_TUNE_REG),
.TX_FABINT_USRCLK_FLOP (TX_FABINT_USRCLK_FLOP_REG),
.TX_FIFO_BYP_EN (TX_FIFO_BYP_EN_REG),
.TX_IDLE_DATA_ZERO (TX_IDLE_DATA_ZERO_REG),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH_REG),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ_REG),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL_REG),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0_REG),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1_REG),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2_REG),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3_REG),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4_REG),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0_REG),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1_REG),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2_REG),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3_REG),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4_REG),
.TX_MODE_SEL (TX_MODE_SEL_REG),
.TX_PHICAL_CFG0 (TX_PHICAL_CFG0_REG),
.TX_PHICAL_CFG1 (TX_PHICAL_CFG1_REG),
.TX_PHICAL_CFG2 (TX_PHICAL_CFG2_REG),
.TX_PI_BIASSET (TX_PI_BIASSET_REG),
.TX_PI_CFG0 (TX_PI_CFG0_REG),
.TX_PI_CFG1 (TX_PI_CFG1_REG),
.TX_PI_DIV2_MODE_B (TX_PI_DIV2_MODE_B_REG),
.TX_PI_SEL_QPLL0 (TX_PI_SEL_QPLL0_REG),
.TX_PI_SEL_QPLL1 (TX_PI_SEL_QPLL1_REG),
.TX_PMADATA_OPT (TX_PMADATA_OPT_REG),
.TX_PMA_POWER_SAVE (TX_PMA_POWER_SAVE_REG),
.TX_PREDRV_CTRL (TX_PREDRV_CTRL_REG),
.TX_PROGCLK_SEL (TX_PROGCLK_SEL_REG),
.TX_PROGDIV_CFG (TX_PROGDIV_CFG_BIN),
.TX_PROGDIV_RATE (TX_PROGDIV_RATE_REG),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG_REG),
.TX_RXDETECT_REF (TX_RXDETECT_REF_REG),
.TX_SAMPLE_PERIOD (TX_SAMPLE_PERIOD_REG),
.TX_SARC_LPBK_ENB (TX_SARC_LPBK_ENB_REG),
.TX_USERPATTERN_DATA0 (TX_USERPATTERN_DATA0_REG),
.TX_USERPATTERN_DATA1 (TX_USERPATTERN_DATA1_REG),
.TX_USERPATTERN_DATA2 (TX_USERPATTERN_DATA2_REG),
.TX_USERPATTERN_DATA3 (TX_USERPATTERN_DATA3_REG),
.TX_USERPATTERN_DATA4 (TX_USERPATTERN_DATA4_REG),
.TX_USERPATTERN_DATA5 (TX_USERPATTERN_DATA5_REG),
.TX_USERPATTERN_DATA6 (TX_USERPATTERN_DATA6_REG),
.TX_USERPATTERN_DATA7 (TX_USERPATTERN_DATA7_REG),
.TX_XCLK_SEL (TX_XCLK_SEL_REG),
.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL_REG),
.BUFGTCE (BUFGTCE_out),
.BUFGTCEMASK (BUFGTCEMASK_out),
.BUFGTDIV (BUFGTDIV_out),
.BUFGTRESET (BUFGTRESET_out),
.BUFGTRSTMASK (BUFGTRSTMASK_out),
.CPLLFBCLKLOST (CPLLFBCLKLOST_out),
.CPLLLOCK (CPLLLOCK_out),
.CPLLREFCLKLOST (CPLLREFCLKLOST_out),
.DMONITOROUT (DMONITOROUT_out),
.DRPDO (DRPDO_out),
.DRPRDY (DRPRDY_out),
.EYESCANDATAERROR (EYESCANDATAERROR_out),
.GTPOWERGOOD (GTPOWERGOOD_out),
.GTREFCLKMONITOR (GTREFCLKMONITOR_out),
.GTYTXN (GTYTXN_out),
.GTYTXP (GTYTXP_out),
.PCIERATEGEN3 (PCIERATEGEN3_out),
.PCIERATEIDLE (PCIERATEIDLE_out),
.PCIERATEQPLLPD (PCIERATEQPLLPD_out),
.PCIERATEQPLLRESET (PCIERATEQPLLRESET_out),
.PCIESYNCTXSYNCDONE (PCIESYNCTXSYNCDONE_out),
.PCIEUSERGEN3RDY (PCIEUSERGEN3RDY_out),
.PCIEUSERPHYSTATUSRST (PCIEUSERPHYSTATUSRST_out),
.PCIEUSERRATESTART (PCIEUSERRATESTART_out),
.PCSRSVDOUT (PCSRSVDOUT_out),
.PHYSTATUS (PHYSTATUS_out),
.PINRSRVDAS (PINRSRVDAS_out),
.PMASCANOUT (PMASCANOUT_out),
.RESETEXCEPTION (RESETEXCEPTION_out),
.RXBUFSTATUS (RXBUFSTATUS_out),
.RXBYTEISALIGNED (RXBYTEISALIGNED_out),
.RXBYTEREALIGN (RXBYTEREALIGN_out),
.RXCDRLOCK (RXCDRLOCK_out),
.RXCDRPHDONE (RXCDRPHDONE_out),
.RXCHANBONDSEQ (RXCHANBONDSEQ_out),
.RXCHANISALIGNED (RXCHANISALIGNED_out),
.RXCHANREALIGN (RXCHANREALIGN_out),
.RXCHBONDO (RXCHBONDO_out),
.RXCKCALDONE (RXCKCALDONE_out),
.RXCLKCORCNT (RXCLKCORCNT_out),
.RXCOMINITDET (RXCOMINITDET_out),
.RXCOMMADET (RXCOMMADET_out),
.RXCOMSASDET (RXCOMSASDET_out),
.RXCOMWAKEDET (RXCOMWAKEDET_out),
.RXCTRL0 (RXCTRL0_out),
.RXCTRL1 (RXCTRL1_out),
.RXCTRL2 (RXCTRL2_out),
.RXCTRL3 (RXCTRL3_out),
.RXDATA (RXDATA_out),
.RXDATAEXTENDRSVD (RXDATAEXTENDRSVD_out),
.RXDATAVALID (RXDATAVALID_out),
.RXDLYSRESETDONE (RXDLYSRESETDONE_out),
.RXELECIDLE (RXELECIDLE_out),
.RXHEADER (RXHEADER_out),
.RXHEADERVALID (RXHEADERVALID_out),
.RXMONITOROUT (RXMONITOROUT_out),
.RXOSINTDONE (RXOSINTDONE_out),
.RXOSINTSTARTED (RXOSINTSTARTED_out),
.RXOSINTSTROBEDONE (RXOSINTSTROBEDONE_out),
.RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED_out),
.RXOUTCLK (RXOUTCLK_out),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC_out),
.RXOUTCLKPCS (RXOUTCLKPCS_out),
.RXPHALIGNDONE (RXPHALIGNDONE_out),
.RXPHALIGNERR (RXPHALIGNERR_out),
.RXPMARESETDONE (RXPMARESETDONE_out),
.RXPRBSERR (RXPRBSERR_out),
.RXPRBSLOCKED (RXPRBSLOCKED_out),
.RXPRGDIVRESETDONE (RXPRGDIVRESETDONE_out),
.RXRATEDONE (RXRATEDONE_out),
.RXRECCLKOUT (RXRECCLKOUT_out),
.RXRESETDONE (RXRESETDONE_out),
.RXSLIDERDY (RXSLIDERDY_out),
.RXSLIPDONE (RXSLIPDONE_out),
.RXSLIPOUTCLKRDY (RXSLIPOUTCLKRDY_out),
.RXSLIPPMARDY (RXSLIPPMARDY_out),
.RXSTARTOFSEQ (RXSTARTOFSEQ_out),
.RXSTATUS (RXSTATUS_out),
.RXSYNCDONE (RXSYNCDONE_out),
.RXSYNCOUT (RXSYNCOUT_out),
.RXVALID (RXVALID_out),
.SCANOUT (SCANOUT_out),
.TXBUFSTATUS (TXBUFSTATUS_out),
.TXCOMFINISH (TXCOMFINISH_out),
.TXDCCDONE (TXDCCDONE_out),
.TXDLYSRESETDONE (TXDLYSRESETDONE_out),
.TXOUTCLK (TXOUTCLK_out),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC_out),
.TXOUTCLKPCS (TXOUTCLKPCS_out),
.TXPHALIGNDONE (TXPHALIGNDONE_out),
.TXPHINITDONE (TXPHINITDONE_out),
.TXPMARESETDONE (TXPMARESETDONE_out),
.TXPRGDIVRESETDONE (TXPRGDIVRESETDONE_out),
.TXRATEDONE (TXRATEDONE_out),
.TXRESETDONE (TXRESETDONE_out),
.TXSYNCDONE (TXSYNCDONE_out),
.TXSYNCOUT (TXSYNCOUT_out),
.CDRSTEPDIR (CDRSTEPDIR_in),
.CDRSTEPSQ (CDRSTEPSQ_in),
.CDRSTEPSX (CDRSTEPSX_in),
.CFGRESET (CFGRESET_in),
.CLKRSVD0 (CLKRSVD0_in),
.CLKRSVD1 (CLKRSVD1_in),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK_in),
.CPLLLOCKEN (CPLLLOCKEN_in),
.CPLLPD (CPLLPD_in),
.CPLLREFCLKSEL (CPLLREFCLKSEL_in),
.CPLLRESET (CPLLRESET_in),
.DMONFIFORESET (DMONFIFORESET_in),
.DMONITORCLK (DMONITORCLK_in),
.DRPADDR (DRPADDR_in),
.DRPCLK (DRPCLK_in),
.DRPDI (DRPDI_in),
.DRPEN (DRPEN_in),
.DRPWE (DRPWE_in),
.ELPCALDVORWREN (ELPCALDVORWREN_in),
.ELPCALPAORWREN (ELPCALPAORWREN_in),
.EVODDPHICALDONE (EVODDPHICALDONE_in),
.EVODDPHICALSTART (EVODDPHICALSTART_in),
.EVODDPHIDRDEN (EVODDPHIDRDEN_in),
.EVODDPHIDWREN (EVODDPHIDWREN_in),
.EVODDPHIXRDEN (EVODDPHIXRDEN_in),
.EVODDPHIXWREN (EVODDPHIXWREN_in),
.EYESCANMODE (EYESCANMODE_in),
.EYESCANRESET (EYESCANRESET_in),
.EYESCANTRIGGER (EYESCANTRIGGER_in),
.GTGREFCLK (GTGREFCLK_in),
.GTNORTHREFCLK0 (GTNORTHREFCLK0_in),
.GTNORTHREFCLK1 (GTNORTHREFCLK1_in),
.GTREFCLK0 (GTREFCLK0_in),
.GTREFCLK1 (GTREFCLK1_in),
.GTRESETSEL (GTRESETSEL_in),
.GTRSVD (GTRSVD_in),
.GTRXRESET (GTRXRESET_in),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0_in),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1_in),
.GTTXRESET (GTTXRESET_in),
.GTYRXN (GTYRXN_in),
.GTYRXP (GTYRXP_in),
.LOOPBACK (LOOPBACK_in),
.LOOPRSVD (LOOPRSVD_in),
.LPBKRXTXSEREN (LPBKRXTXSEREN_in),
.LPBKTXRXSEREN (LPBKTXRXSEREN_in),
.PCIEEQRXEQADAPTDONE (PCIEEQRXEQADAPTDONE_in),
.PCIERSTIDLE (PCIERSTIDLE_in),
.PCIERSTTXSYNCSTART (PCIERSTTXSYNCSTART_in),
.PCIEUSERRATEDONE (PCIEUSERRATEDONE_in),
.PCSRSVDIN (PCSRSVDIN_in),
.PCSRSVDIN2 (PCSRSVDIN2_in),
.PMARSVDIN (PMARSVDIN_in),
.PMASCANCLK0 (PMASCANCLK0_in),
.PMASCANCLK1 (PMASCANCLK1_in),
.PMASCANCLK2 (PMASCANCLK2_in),
.PMASCANCLK3 (PMASCANCLK3_in),
.PMASCANCLK4 (PMASCANCLK4_in),
.PMASCANCLK5 (PMASCANCLK5_in),
.PMASCANENB (PMASCANENB_in),
.PMASCANIN (PMASCANIN_in),
.PMASCANMODEB (PMASCANMODEB_in),
.PMASCANRSTEN (PMASCANRSTEN_in),
.QPLL0CLK (QPLL0CLK_in),
.QPLL0REFCLK (QPLL0REFCLK_in),
.QPLL1CLK (QPLL1CLK_in),
.QPLL1REFCLK (QPLL1REFCLK_in),
.RESETOVRD (RESETOVRD_in),
.RSTCLKENTX (RSTCLKENTX_in),
.RX8B10BEN (RX8B10BEN_in),
.RXBUFRESET (RXBUFRESET_in),
.RXCDRFREQRESET (RXCDRFREQRESET_in),
.RXCDRHOLD (RXCDRHOLD_in),
.RXCDROVRDEN (RXCDROVRDEN_in),
.RXCDRRESET (RXCDRRESET_in),
.RXCDRRESETRSV (RXCDRRESETRSV_in),
.RXCHBONDEN (RXCHBONDEN_in),
.RXCHBONDI (RXCHBONDI_in),
.RXCHBONDLEVEL (RXCHBONDLEVEL_in),
.RXCHBONDMASTER (RXCHBONDMASTER_in),
.RXCHBONDSLAVE (RXCHBONDSLAVE_in),
.RXCKCALRESET (RXCKCALRESET_in),
.RXCOMMADETEN (RXCOMMADETEN_in),
.RXDCCFORCESTART (RXDCCFORCESTART_in),
.RXDFEAGCHOLD (RXDFEAGCHOLD_in),
.RXDFEAGCOVRDEN (RXDFEAGCOVRDEN_in),
.RXDFELFHOLD (RXDFELFHOLD_in),
.RXDFELFOVRDEN (RXDFELFOVRDEN_in),
.RXDFELPMRESET (RXDFELPMRESET_in),
.RXDFETAP10HOLD (RXDFETAP10HOLD_in),
.RXDFETAP10OVRDEN (RXDFETAP10OVRDEN_in),
.RXDFETAP11HOLD (RXDFETAP11HOLD_in),
.RXDFETAP11OVRDEN (RXDFETAP11OVRDEN_in),
.RXDFETAP12HOLD (RXDFETAP12HOLD_in),
.RXDFETAP12OVRDEN (RXDFETAP12OVRDEN_in),
.RXDFETAP13HOLD (RXDFETAP13HOLD_in),
.RXDFETAP13OVRDEN (RXDFETAP13OVRDEN_in),
.RXDFETAP14HOLD (RXDFETAP14HOLD_in),
.RXDFETAP14OVRDEN (RXDFETAP14OVRDEN_in),
.RXDFETAP15HOLD (RXDFETAP15HOLD_in),
.RXDFETAP15OVRDEN (RXDFETAP15OVRDEN_in),
.RXDFETAP2HOLD (RXDFETAP2HOLD_in),
.RXDFETAP2OVRDEN (RXDFETAP2OVRDEN_in),
.RXDFETAP3HOLD (RXDFETAP3HOLD_in),
.RXDFETAP3OVRDEN (RXDFETAP3OVRDEN_in),
.RXDFETAP4HOLD (RXDFETAP4HOLD_in),
.RXDFETAP4OVRDEN (RXDFETAP4OVRDEN_in),
.RXDFETAP5HOLD (RXDFETAP5HOLD_in),
.RXDFETAP5OVRDEN (RXDFETAP5OVRDEN_in),
.RXDFETAP6HOLD (RXDFETAP6HOLD_in),
.RXDFETAP6OVRDEN (RXDFETAP6OVRDEN_in),
.RXDFETAP7HOLD (RXDFETAP7HOLD_in),
.RXDFETAP7OVRDEN (RXDFETAP7OVRDEN_in),
.RXDFETAP8HOLD (RXDFETAP8HOLD_in),
.RXDFETAP8OVRDEN (RXDFETAP8OVRDEN_in),
.RXDFETAP9HOLD (RXDFETAP9HOLD_in),
.RXDFETAP9OVRDEN (RXDFETAP9OVRDEN_in),
.RXDFEUTHOLD (RXDFEUTHOLD_in),
.RXDFEUTOVRDEN (RXDFEUTOVRDEN_in),
.RXDFEVPHOLD (RXDFEVPHOLD_in),
.RXDFEVPOVRDEN (RXDFEVPOVRDEN_in),
.RXDFEVSEN (RXDFEVSEN_in),
.RXDFEXYDEN (RXDFEXYDEN_in),
.RXDLYBYPASS (RXDLYBYPASS_in),
.RXDLYEN (RXDLYEN_in),
.RXDLYOVRDEN (RXDLYOVRDEN_in),
.RXDLYSRESET (RXDLYSRESET_in),
.RXELECIDLEMODE (RXELECIDLEMODE_in),
.RXGEARBOXSLIP (RXGEARBOXSLIP_in),
.RXLATCLK (RXLATCLK_in),
.RXLPMEN (RXLPMEN_in),
.RXLPMGCHOLD (RXLPMGCHOLD_in),
.RXLPMGCOVRDEN (RXLPMGCOVRDEN_in),
.RXLPMHFHOLD (RXLPMHFHOLD_in),
.RXLPMHFOVRDEN (RXLPMHFOVRDEN_in),
.RXLPMLFHOLD (RXLPMLFHOLD_in),
.RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN_in),
.RXLPMOSHOLD (RXLPMOSHOLD_in),
.RXLPMOSOVRDEN (RXLPMOSOVRDEN_in),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_in),
.RXMONITORSEL (RXMONITORSEL_in),
.RXOOBRESET (RXOOBRESET_in),
.RXOSCALRESET (RXOSCALRESET_in),
.RXOSHOLD (RXOSHOLD_in),
.RXOSINTCFG (RXOSINTCFG_in),
.RXOSINTEN (RXOSINTEN_in),
.RXOSINTHOLD (RXOSINTHOLD_in),
.RXOSINTOVRDEN (RXOSINTOVRDEN_in),
.RXOSINTSTROBE (RXOSINTSTROBE_in),
.RXOSINTTESTOVRDEN (RXOSINTTESTOVRDEN_in),
.RXOSOVRDEN (RXOSOVRDEN_in),
.RXOUTCLKSEL (RXOUTCLKSEL_in),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_in),
.RXPCSRESET (RXPCSRESET_in),
.RXPD (RXPD_in),
.RXPHALIGN (RXPHALIGN_in),
.RXPHALIGNEN (RXPHALIGNEN_in),
.RXPHDLYPD (RXPHDLYPD_in),
.RXPHDLYRESET (RXPHDLYRESET_in),
.RXPHOVRDEN (RXPHOVRDEN_in),
.RXPLLCLKSEL (RXPLLCLKSEL_in),
.RXPMARESET (RXPMARESET_in),
.RXPOLARITY (RXPOLARITY_in),
.RXPRBSCNTRESET (RXPRBSCNTRESET_in),
.RXPRBSSEL (RXPRBSSEL_in),
.RXPROGDIVRESET (RXPROGDIVRESET_in),
.RXRATE (RXRATE_in),
.RXRATEMODE (RXRATEMODE_in),
.RXSLIDE (RXSLIDE_in),
.RXSLIPOUTCLK (RXSLIPOUTCLK_in),
.RXSLIPPMA (RXSLIPPMA_in),
.RXSYNCALLIN (RXSYNCALLIN_in),
.RXSYNCIN (RXSYNCIN_in),
.RXSYNCMODE (RXSYNCMODE_in),
.RXSYSCLKSEL (RXSYSCLKSEL_in),
.RXUSERRDY (RXUSERRDY_in),
.RXUSRCLK (RXUSRCLK_in),
.RXUSRCLK2 (RXUSRCLK2_in),
.SARCCLK (SARCCLK_in),
.SCANCLK (SCANCLK_in),
.SCANENB (SCANENB_in),
.SCANIN (SCANIN_in),
.SCANMODEB (SCANMODEB_in),
.SIGVALIDCLK (SIGVALIDCLK_in),
.TSTCLK0 (TSTCLK0_in),
.TSTCLK1 (TSTCLK1_in),
.TSTIN (TSTIN_in),
.TSTPD (TSTPD_in),
.TSTPDOVRDB (TSTPDOVRDB_in),
.TX8B10BBYPASS (TX8B10BBYPASS_in),
.TX8B10BEN (TX8B10BEN_in),
.TXBUFDIFFCTRL (TXBUFDIFFCTRL_in),
.TXCOMINIT (TXCOMINIT_in),
.TXCOMSAS (TXCOMSAS_in),
.TXCOMWAKE (TXCOMWAKE_in),
.TXCTRL0 (TXCTRL0_in),
.TXCTRL1 (TXCTRL1_in),
.TXCTRL2 (TXCTRL2_in),
.TXDATA (TXDATA_in),
.TXDATAEXTENDRSVD (TXDATAEXTENDRSVD_in),
.TXDCCFORCESTART (TXDCCFORCESTART_in),
.TXDCCRESET (TXDCCRESET_in),
.TXDEEMPH (TXDEEMPH_in),
.TXDETECTRX (TXDETECTRX_in),
.TXDIFFCTRL (TXDIFFCTRL_in),
.TXDIFFPD (TXDIFFPD_in),
.TXDLYBYPASS (TXDLYBYPASS_in),
.TXDLYEN (TXDLYEN_in),
.TXDLYHOLD (TXDLYHOLD_in),
.TXDLYOVRDEN (TXDLYOVRDEN_in),
.TXDLYSRESET (TXDLYSRESET_in),
.TXDLYUPDOWN (TXDLYUPDOWN_in),
.TXELECIDLE (TXELECIDLE_in),
.TXELFORCESTART (TXELFORCESTART_in),
.TXHEADER (TXHEADER_in),
.TXINHIBIT (TXINHIBIT_in),
.TXLATCLK (TXLATCLK_in),
.TXMAINCURSOR (TXMAINCURSOR_in),
.TXMARGIN (TXMARGIN_in),
.TXOUTCLKSEL (TXOUTCLKSEL_in),
.TXPCSRESET (TXPCSRESET_in),
.TXPD (TXPD_in),
.TXPDELECIDLEMODE (TXPDELECIDLEMODE_in),
.TXPHALIGN (TXPHALIGN_in),
.TXPHALIGNEN (TXPHALIGNEN_in),
.TXPHDLYPD (TXPHDLYPD_in),
.TXPHDLYRESET (TXPHDLYRESET_in),
.TXPHDLYTSTCLK (TXPHDLYTSTCLK_in),
.TXPHINIT (TXPHINIT_in),
.TXPHOVRDEN (TXPHOVRDEN_in),
.TXPIPPMEN (TXPIPPMEN_in),
.TXPIPPMOVRDEN (TXPIPPMOVRDEN_in),
.TXPIPPMPD (TXPIPPMPD_in),
.TXPIPPMSEL (TXPIPPMSEL_in),
.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE_in),
.TXPISOPD (TXPISOPD_in),
.TXPLLCLKSEL (TXPLLCLKSEL_in),
.TXPMARESET (TXPMARESET_in),
.TXPOLARITY (TXPOLARITY_in),
.TXPOSTCURSOR (TXPOSTCURSOR_in),
.TXPRBSFORCEERR (TXPRBSFORCEERR_in),
.TXPRBSSEL (TXPRBSSEL_in),
.TXPRECURSOR (TXPRECURSOR_in),
.TXPROGDIVRESET (TXPROGDIVRESET_in),
.TXRATE (TXRATE_in),
.TXRATEMODE (TXRATEMODE_in),
.TXSEQUENCE (TXSEQUENCE_in),
.TXSWING (TXSWING_in),
.TXSYNCALLIN (TXSYNCALLIN_in),
.TXSYNCIN (TXSYNCIN_in),
.TXSYNCMODE (TXSYNCMODE_in),
.TXSYSCLKSEL (TXSYSCLKSEL_in),
.TXUSERRDY (TXUSERRDY_in),
.TXUSRCLK (TXUSRCLK_in),
.TXUSRCLK2 (TXUSRCLK2_in),
.GSR (glblGSR)
);
specify
(DMONITORCLK => DMONITOROUT[0]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[10]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[11]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[12]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[13]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[14]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[15]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[1]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[2]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[3]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[4]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[5]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[6]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[7]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[8]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[9]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[0]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[10]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[11]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[12]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[13]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[14]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[15]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[1]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[2]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[3]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[4]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[5]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[6]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[7]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[8]) = (0:0:0, 0:0:0);
(DRPCLK => DRPDO[9]) = (0:0:0, 0:0:0);
(DRPCLK => DRPRDY) = (0:0:0, 0:0:0);
(GTGREFCLK => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTGREFCLK => RXCDRPHDONE) = (0:0:0, 0:0:0);
(GTGREFCLK => RXOUTCLK) = (0:0:0, 0:0:0);
(GTGREFCLK => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTGREFCLK => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTGREFCLK => RXRESETDONE) = (0:0:0, 0:0:0);
(GTGREFCLK => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTGREFCLK => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTGREFCLK => TXRESETDONE) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => RXCDRPHDONE) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => RXOUTCLK) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => RXRESETDONE) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => TXRESETDONE) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => RXCDRPHDONE) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => RXOUTCLK) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => RXRESETDONE) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => TXRESETDONE) = (0:0:0, 0:0:0);
(GTREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => RXCDRPHDONE) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => RXOUTCLK) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => RXRESETDONE) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => TXRESETDONE) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => RXCDRPHDONE) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => RXOUTCLK) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => RXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => RXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => RXRESETDONE) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => TXOUTCLKFABRIC) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => TXOUTCLKPCS) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => TXRESETDONE) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCDRPHDONE) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[0]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[1]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[2]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[3]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[4]) = (0:0:0, 0:0:0);
(RXUSRCLK => RXRESETDONE) = (0:0:0, 0:0:0);
(RXUSRCLK => TXRESETDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => PHYSTATUS) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBUFSTATUS[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBUFSTATUS[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBUFSTATUS[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBYTEISALIGNED) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXBYTEREALIGN) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCDRPHDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCHANBONDSEQ) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCHANISALIGNED) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCHANREALIGN) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCLKCORCNT[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCLKCORCNT[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMINITDET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMMADET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMSASDET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCOMWAKEDET) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[10]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[11]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[12]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[13]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[14]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[15]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[8]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL0[9]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[10]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[11]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[12]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[13]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[14]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[15]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[8]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL1[9]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL2[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXCTRL3[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATAVALID[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATAVALID[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[100]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[101]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[102]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[103]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[104]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[105]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[106]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[107]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[108]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[109]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[10]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[110]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[111]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[112]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[113]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[114]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[115]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[116]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[117]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[118]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[119]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[11]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[120]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[121]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[122]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[123]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[124]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[125]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[126]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[127]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[12]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[13]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[14]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[15]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[16]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[17]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[18]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[19]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[20]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[21]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[22]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[23]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[24]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[25]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[26]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[27]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[28]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[29]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[30]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[31]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[32]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[33]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[34]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[35]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[36]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[37]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[38]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[39]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[40]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[41]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[42]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[43]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[44]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[45]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[46]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[47]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[48]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[49]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[50]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[51]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[52]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[53]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[54]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[55]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[56]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[57]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[58]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[59]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[60]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[61]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[62]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[63]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[64]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[65]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[66]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[67]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[68]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[69]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[6]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[70]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[71]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[72]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[73]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[74]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[75]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[76]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[77]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[78]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[79]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[7]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[80]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[81]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[82]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[83]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[84]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[85]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[86]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[87]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[88]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[89]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[8]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[90]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[91]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[92]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[93]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[94]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[95]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[96]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[97]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[98]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[99]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXDATA[9]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADERVALID[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADERVALID[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[3]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[4]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXHEADER[5]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXPRBSERR) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXPRBSLOCKED) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXRATEDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXRESETDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIDERDY) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIPDONE) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIPOUTCLKRDY) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSLIPPMARDY) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTARTOFSEQ[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTARTOFSEQ[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTATUS[0]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTATUS[1]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXSTATUS[2]) = (0:0:0, 0:0:0);
(RXUSRCLK2 => RXVALID) = (0:0:0, 0:0:0);
(RXUSRCLK2 => TXRESETDONE) = (0:0:0, 0:0:0);
(TXUSRCLK => RXRESETDONE) = (0:0:0, 0:0:0);
(TXUSRCLK => TXRESETDONE) = (0:0:0, 0:0:0);
(TXUSRCLK2 => RXRESETDONE) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXBUFSTATUS[0]) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXBUFSTATUS[1]) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXCOMFINISH) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXRATEDONE) = (0:0:0, 0:0:0);
(TXUSRCLK2 => TXRESETDONE) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[0] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[10] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[11] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[12] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[13] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[16] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[1] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[2] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[3] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[4] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[5] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[6] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[7] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[8] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (DMONITOROUT[9] +: 1)) = (0:0:0, 0:0:0);
(negedge RXCKCALRESET => (RXCKCALDONE +: 1)) = (0:0:0, 0:0:0);
(negedge TXDCCRESET => (DMONITOROUT[0] +: 1)) = (0:0:0, 0:0:0);
(negedge TXDCCRESET => (DMONITOROUT[16] +: 1)) = (0:0:0, 0:0:0);
(negedge TXDCCRESET => (DMONITOROUT[1] +: 1)) = (0:0:0, 0:0:0);
(negedge TXDCCRESET => (DMONITOROUT[2] +: 1)) = (0:0:0, 0:0:0);
(negedge TXDCCRESET => (DMONITOROUT[3] +: 1)) = (0:0:0, 0:0:0);
(negedge TXDCCRESET => (DMONITOROUT[4] +: 1)) = (0:0:0, 0:0:0);
(negedge TXDCCRESET => (DMONITOROUT[5] +: 1)) = (0:0:0, 0:0:0);
(negedge TXDCCRESET => (DMONITOROUT[6] +: 1)) = (0:0:0, 0:0:0);
(negedge TXDCCRESET => (TXDCCDONE +: 1)) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay);
$setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPADDR_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, DRPCLK_delay, DRPWE_delay);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier,,, RXUSRCLK_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RX8B10BEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDMASTER_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDSLAVE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCOMMADETEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXGEARBOXSLIP_delay);
$setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPOLARITY_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXRATE[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXRATE[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXRATE[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIDE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPOUTCLK_delay);
$setuphold (posedge RXUSRCLK2, negedge RXSLIPPMA, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPPMA_delay);
$setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RX8B10BEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDMASTER_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCHBONDSLAVE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXCOMMADETEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXGEARBOXSLIP_delay);
$setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPOLARITY_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXPRBSSEL_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXRATE[0], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXRATE[1], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXRATE[2], 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXRATE_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIDE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPOUTCLK_delay);
$setuphold (posedge RXUSRCLK2, posedge RXSLIPPMA, 0:0:0, 0:0:0, notifier,,, RXUSRCLK2_delay, RXSLIPPMA_delay);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BEN_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMINIT_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMSAS_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMWAKE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[10], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[10]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[11], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[11]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[12], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[12]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[13], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[13]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[14], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[14]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[15], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[15]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[8], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[8]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[9], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[9]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[10], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[10]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[11], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[11]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[12], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[12]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[13], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[13]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[14], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[14]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[15], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[15]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[8], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[8]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[9], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[9]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[100], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[100]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[101], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[101]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[102], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[102]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[103], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[103]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[104], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[104]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[105], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[105]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[106], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[106]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[107], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[107]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[108], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[108]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[109], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[109]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[10], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[10]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[110], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[110]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[111], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[111]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[112], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[112]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[113], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[113]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[114], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[114]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[115], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[115]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[116], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[116]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[117], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[117]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[118], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[118]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[119], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[119]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[11], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[11]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[120], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[120]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[121], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[121]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[122], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[122]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[123], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[123]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[124], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[124]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[125], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[125]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[126], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[126]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[127], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[127]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[12], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[12]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[13], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[13]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[14], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[14]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[15], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[15]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[16], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[16]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[17], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[17]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[18], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[18]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[19], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[19]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[20], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[20]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[21], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[21]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[22], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[22]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[23], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[23]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[24], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[24]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[25], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[25]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[26], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[26]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[27], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[27]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[28], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[28]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[29], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[29]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[30], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[30]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[31], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[31]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[32], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[32]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[33], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[33]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[34], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[34]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[35], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[35]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[36], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[36]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[37], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[37]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[38], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[38]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[39], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[39]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[40], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[40]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[41], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[41]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[42], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[42]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[43], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[43]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[44], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[44]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[45], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[45]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[46], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[46]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[47], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[47]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[48], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[48]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[49], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[49]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[50], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[50]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[51], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[51]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[52], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[52]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[53], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[53]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[54], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[54]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[55], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[55]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[56], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[56]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[57], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[57]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[58], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[58]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[59], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[59]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[60], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[60]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[61], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[61]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[62], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[62]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[63], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[63]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[64], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[64]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[65], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[65]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[66], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[66]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[67], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[67]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[68], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[68]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[69], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[69]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[70], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[70]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[71], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[71]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[72], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[72]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[73], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[73]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[74], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[74]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[75], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[75]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[76], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[76]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[77], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[77]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[78], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[78]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[79], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[79]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[80], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[80]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[81], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[81]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[82], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[82]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[83], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[83]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[84], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[84]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[85], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[85]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[86], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[86]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[87], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[87]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[88], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[88]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[89], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[89]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[8], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[8]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[90], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[90]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[91], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[91]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[92], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[92]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[93], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[93]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[94], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[94]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[95], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[95]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[96], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[96]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[97], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[97]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[98], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[98]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[99], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[99]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[9], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[9]);
$setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDETECTRX_delay);
$setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXELECIDLE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXINHIBIT_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPD[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXPD[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPOLARITY_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSFORCEERR_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXRATE[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXRATE[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXRATE[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TX8B10BEN_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMINIT_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMSAS_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCOMWAKE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[10], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[10]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[11], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[11]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[12], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[12]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[13], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[13]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[14], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[14]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[15], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[15]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[8], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[8]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[9], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL0_delay[9]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[10], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[10]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[11], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[11]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[12], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[12]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[13], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[13]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[14], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[14]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[15], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[15]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[8], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[8]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[9], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL1_delay[9]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXCTRL2_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[100], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[100]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[101], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[101]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[102], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[102]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[103], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[103]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[104], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[104]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[105], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[105]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[106], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[106]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[107], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[107]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[108], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[108]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[109], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[109]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[10], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[10]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[110], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[110]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[111], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[111]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[112], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[112]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[113], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[113]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[114], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[114]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[115], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[115]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[116], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[116]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[117], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[117]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[118], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[118]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[119], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[119]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[11], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[11]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[120], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[120]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[121], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[121]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[122], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[122]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[123], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[123]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[124], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[124]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[125], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[125]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[126], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[126]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[127], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[127]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[12], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[12]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[13], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[13]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[14], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[14]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[15], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[15]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[16], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[16]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[17], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[17]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[18], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[18]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[19], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[19]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[20], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[20]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[21], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[21]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[22], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[22]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[23], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[23]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[24], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[24]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[25], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[25]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[26], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[26]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[27], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[27]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[28], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[28]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[29], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[29]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[30], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[30]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[31], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[31]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[32], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[32]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[33], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[33]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[34], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[34]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[35], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[35]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[36], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[36]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[37], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[37]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[38], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[38]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[39], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[39]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[40], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[40]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[41], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[41]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[42], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[42]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[43], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[43]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[44], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[44]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[45], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[45]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[46], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[46]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[47], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[47]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[48], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[48]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[49], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[49]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[50], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[50]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[51], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[51]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[52], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[52]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[53], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[53]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[54], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[54]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[55], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[55]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[56], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[56]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[57], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[57]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[58], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[58]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[59], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[59]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[60], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[60]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[61], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[61]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[62], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[62]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[63], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[63]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[64], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[64]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[65], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[65]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[66], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[66]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[67], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[67]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[68], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[68]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[69], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[69]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[70], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[70]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[71], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[71]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[72], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[72]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[73], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[73]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[74], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[74]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[75], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[75]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[76], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[76]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[77], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[77]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[78], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[78]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[79], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[79]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[7], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[80], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[80]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[81], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[81]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[82], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[82]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[83], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[83]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[84], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[84]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[85], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[85]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[86], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[86]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[87], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[87]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[88], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[88]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[89], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[89]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[8], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[8]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[90], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[90]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[91], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[91]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[92], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[92]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[93], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[93]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[94], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[94]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[95], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[95]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[96], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[96]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[97], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[97]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[98], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[98]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[99], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[99]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[9], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDATA_delay[9]);
$setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXDETECTRX_delay);
$setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXELECIDLE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXHEADER_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXINHIBIT_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPD[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXPD[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPD_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPOLARITY_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSFORCEERR_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXPRBSSEL_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXRATE[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXRATE[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXRATE[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXRATE_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier,,, TXUSRCLK2_delay, TXSEQUENCE_delay[6]);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
module VgaSyncGenerator
(
input CLK ,
output reg VGA_HS ,
output reg VGA_VS ,
output wire [10:0] VGA_POS_X ,
output wire [9 :0] VGA_POS_Y ,
output wire VGA_ENABLE
);
// ------------------- Параметры синхрогенератора для выбранного разрешения ---------------------------
parameter HORIZONTAL_RESOLUTION = 10'd800;
parameter HORIZONTAL_FRONT_PORCH = 8'd40;
parameter HORIZONTAL_SYNC_PULSE = 8'd128;
parameter HORIZONTAL_BACK_PORCH = 8'd88;
parameter VERTICAL_RESOLUTION = 10'd600;
parameter VERTICAL_FRONT_PORCH = 1'd1;
parameter VERTICAL_SYNC_PULSE = 3'd4;
parameter VERTICAL_BACK_PORCH = 5'd23;
//-----------------------------------------------------------------------------------------------------
// -------------------- Границы видимого участка для выбранного разрешения ----------------------------
localparam SCREEN_LEFT_BORDER = HORIZONTAL_SYNC_PULSE + HORIZONTAL_BACK_PORCH;
localparam SCREEN_RIGHT_BORDER = HORIZONTAL_SYNC_PULSE + HORIZONTAL_BACK_PORCH + HORIZONTAL_RESOLUTION;
localparam SCREEN_UP_BORDER = VERTICAL_SYNC_PULSE + VERTICAL_BACK_PORCH;
localparam SCREEN_DOWN_BORDER = VERTICAL_SYNC_PULSE + VERTICAL_BACK_PORCH + VERTICAL_RESOLUTION;
//-----------------------------------------------------------------------------------------------------
reg [10:0]PosX = 0;
reg [9 :0]PosY = 0;
wire IsScreenX = ( PosX >= SCREEN_LEFT_BORDER ) && ( PosX < SCREEN_RIGHT_BORDER );
wire IsScreenY = ( PosY >= SCREEN_UP_BORDER ) && ( PosY < SCREEN_DOWN_BORDER );
assign VGA_POS_X = IsScreenX ? ( PosX - SCREEN_LEFT_BORDER ) : 10'd0;
assign VGA_POS_Y = IsScreenY ? ( PosY - SCREEN_UP_BORDER ) : 9'd0;
assign VGA_ENABLE = IsScreenX & IsScreenY;
reg Clk = 1'b0;
always @( posedge CLK )
begin
Clk <= ~ Clk;
end
always @( posedge Clk )
begin
VGA_HS <= (PosX > HORIZONTAL_SYNC_PULSE);
if( PosX > ( HORIZONTAL_SYNC_PULSE + HORIZONTAL_BACK_PORCH + HORIZONTAL_RESOLUTION + HORIZONTAL_FRONT_PORCH ) )
PosX <= 0;
else
PosX <= PosX + 1'b1;
end
always @( negedge VGA_HS )
begin
VGA_VS <= ( PosY > VERTICAL_SYNC_PULSE );
if( PosY > ( VERTICAL_SYNC_PULSE + VERTICAL_BACK_PORCH + VERTICAL_RESOLUTION + VERTICAL_FRONT_PORCH ) )
PosY <= 0;
else
PosY <= PosY + 1'b1;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_BLACKBOX_V
`define SKY130_FD_SC_LP__A221O_BLACKBOX_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_BLACKBOX_V
|
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 1
*/
// Behavioral model for Finite State Machine model of the sequence detector
module seq_detect(in,clk,rst,match,err);
// Output signals representing the end of the transaction
// Indicate if the sequence is detected when set to logic high
output match;
// Indicate if the sequence is not detected when set to logic high
output err;
// Input signals
// Input data bit of the sequence
input in;
/**
* Clock signal for the finite state machine to facilitate
* state transitions
*/
input clk;
/**
* Reset signal for the finite state machine to bring it to
* the initial state, Sone
*/
input rst;
// Declare "wire" signals:
//wire FSM_OUTPUT;
// Declare "reg" signals:
reg match; // Output signal
reg err;
/**
* state: current state of the FSM
* nextstate: next state of the FSM
*/
reg [1:0] state, nextstate;
/**
* num_bits for the number of bits in this sequence of 8-bits that
* have been processed
*/
reg [3:0] num_bits;
// Number of logic HIGH bits that have been processed
reg [2:0] num_high;
// Indicate if the previous sequence has been found
reg prev_find;
// Definitions for the states in the sequence detector
// State of the FSM where previous input = 1
parameter Szero = 2'b00;
// State of the FSM where previous input = 0
parameter Sone = 2'b01;
/**
* State of the FSM where the sequence is found to be a match
* or mismatch; this is also used as a initial state for the FSM
*/
parameter Sfound = 2'b10;
// State of the FSM where input is erroneous; input != (1 or 0)
parameter Serr = 2'b11; // Error state
// Number of bits that shall be processed
parameter total_bits = 4'd8;
// Number of logic HIGH bits that shall be processed
parameter total_high = 3'd5;
// State Memory
always @(posedge clk)
begin
// Synchronous reset
if (rst)
begin
num_high=1'd0;
num_bits=1'd0;
// Go to the initial/error state
state <= Serr;
end
else
begin
// Move/Proceed to the next state
state <= nextstate;
num_bits=num_bits+1;
if (in===1)
begin
num_high=num_high+1;
end
end
end
/**
* Next State Logic
*/
always @(*)
begin
case (state)
Sone:
begin
if((num_bits==4'd2)||(num_bits==4'd3)||(num_bits==4'd6))
begin
$display($time, ">>>>>>>>>>state",state,"num_bits",num_bits);
// num_bits=1'd0;
// num_high=1'd0;
end
if((in === 1'dz) || (in === 1'dx))
begin
/**
* Input signal is not a valid logic HIGH or LOW signal
* Input signal = Z or X
*/
$display($time, " << Err@1 >>");
nextstate <= Serr;
end
else
begin
// A match is found!
if ((in==1'd1) & (total_bits==num_bits)
& (total_high==num_high))
begin
num_bits=1'd0;
num_high=1'd0;
$display($time, "NUM_BITS and NUM_HIGH are RESET");
/*
if(prev_find==1'd1)
begin
num_bits=1'd2;
num_high=1'd1;
prev_find=1'd0;
end
else
begin
num_bits=1'd0;
num_high=1'd0;
end
*/
$display($time, " << Go to State Sfound >>");
nextstate <= Sfound;
end
else if(in === 1'd0)
begin
//if(num_bits==4'd5)
//if((num_bits+1)==4'd5)
/*
if((num_bits==4'd4)&(nextstate==Szero))
begin
$display($time, "*******state",state,"num_bits",num_bits);
num_bits=1'd2;
num_high=1'd1;
end
*/
//if(num_bits==4'd1)
if(num_bits==4'd0)
begin
$display($time, "##############state",state,"num_bits",num_bits);
num_bits=4'd2;
num_high=3'd1;
end
$display($time, " <<pre Szero >>");
$display(num_high,"=!=",num_bits);
// Increment the number of enumerated bits
//num_bits=num_bits+1;
$display($time, " << Szero >>");
$display(num_high,"=!=",num_bits);
// Move to state zero
nextstate <= Szero;
end
else
begin
if(~((num_bits==4'd5) || (num_bits==4'd7) || (num_bits==4'd8)))
begin
$display($time, "1----<<<state",state,"num_bits",num_bits);
num_bits=1'd1;
num_high=1'd1;
end
$display($time, " << pre Sone>>");
$display(num_high,"=!=",num_bits);
// in == 1
/**
* Increment the number of enumerated logic
* high bits
*/
//num_high=num_high+1;
// Increment the number of enumerated bits
//num_bits=num_bits+1;
$display($time, " << Sone>>");
$display(num_high,"=!=",num_bits);
// Remain at State one
nextstate <= Sone;
end
end
end
Szero:
begin
if((num_bits==4'd1)||(num_bits==4'd4)||(num_bits==4'd5)
&(num_bits==4'd7)||(num_bits==4'd8))
begin
$display($time, "<<<<<<<<<<state",state,"num_bits",num_bits);
// num_bits=1'd0;
// num_high=1'd0;
end
$display($time, " from state1::",state,"num_bits",num_bits,"in",in);
if((in === 1'dz) || (in === 1'dx))
begin
/**
* Input signal is not a valid logic HIGH or LOW signal
* Input signal = Z or X
*/
$display($time, " << Err@0 >>");
nextstate <= Serr;
end
else
begin
// Remain at state ZERO
if(in === 1'd0)
begin
if((num_bits!=4'd2)&&(num_bits!=4'd3))
begin
$display($time, "0---->>>state",state,"num_bits",num_bits);
num_bits=1'd1;
num_high=1'd0;
end
$display($time, " << pre Szero >>");
$display(num_high,"=!=",num_bits);
// Increment the number of enumerated bits
//num_bits=num_bits+1;
$display($time, " << Szero >>");
$display(num_high,"=!=",num_bits);
nextstate <= Szero;
end
else
begin
//*****************************************
if(num_bits==4'd2)
begin
$display($time, "______________state",state,"num_bits",num_bits);
num_bits=1'd1;
num_high=1'd1;
end
// Go to state ONE; in == 1
$display($time, " << pre Sone>>");
$display(num_high,"=!=",num_bits);
/**
* Increment the number of enumerated logic
* high bits
*/
//num_high=num_high+1;
// Increment the number of enumerated bits
//num_bits=num_bits+1;
$display($time, " << Sone>>");
$display(num_high,"=!=",num_bits);
nextstate <= Sone;
end
end
end
Sfound:
begin
$display($time, "NUM_BITS==0 and NUM_HIGH==0");
num_high=1'd0;
num_bits=1'd0;
prev_find=1'd1;
$display($time, " << Reached State Sfound >>", num_bits);
// Reset the FSM to the state its input takes it.
if(in === 1'd0)
begin
$display($time, " << Go to State Szero >>",num_bits);
nextstate <= Szero;
end
else if(in === 1'd1)
begin
// in == 1
num_high=1'd1;
num_bits=1'd1;
$display($time, "!!!!!!!!!!!!!!!!SGo to State Sone>>",num_bits);
nextstate <= Sone;
end
else
begin
// Logic value of "in" is invalid
$display($time, " << Go to State Serr>>",num_bits);
nextstate <= Serr;
end
end
Serr:
begin
$display($time, "NUM_BITS===NUM_HIGH===0");
num_bits=1'd0;
num_high=1'd0;
$display($time, " << Reached State Serr >>", num_bits);
// Reset the FSM to the state its input takes it.
if((in === 1'd0) & (rst===1'd0))
begin
//num_bits<=num_bits+1;
//num_bits=num_bits+1'd0;
num_bits=1'd1;
$display($time, " << Go to State Szero >>",num_bits);
nextstate <= Szero;
end
else if((in === 1'd1) & (rst===1'd0))
begin
//num_bits<=num_bits+1;
//num_bits=num_bits+1'd0;
num_bits=1'd1;
// in == 1
num_high=1'd1;
$display($time, " << Go to State Sone>>",num_bits);
nextstate <= Sone;
end
else
begin
// Logic value of "in" is invalid
$display($time, " << Go to State Sone>>",num_bits);
nextstate <= Serr;
end
end
// Default state is the error, Serr, state
default:
begin
$display($time, "NUM_BITS &&& NUM_HIGH R RESET");
num_high=1'd0;
num_bits=1'd0;
$display($time, " << Reached State Serr >>", num_bits);
// Reset the FSM to the state its input takes it.
if((in === 1'd0) & (rst===1'd0))
begin
//num_bits<=num_bits+1;
//num_bits=num_bits+1'd0;
num_bits=1'd1;
$display($time, " << Go to State Szero >>",num_bits);
nextstate <= Szero;
end
else if((in === 1'd1) & (rst===1'd0))
begin
//num_bits<=num_bits+1;
//num_bits=num_bits+1'd0;
num_bits=1'd1;
// in == 1
num_high=1'd1;
$display($time, " << Go to State Sone>>",num_bits);
nextstate <= Sone;
end
else
begin
// Logic value of "in" is invalid
$display($time, " << Go to State Sone>>",num_bits);
nextstate <= Serr;
end
end
endcase
end
/**
* Output Logic - Difference between the Mealy and the Moore machine
* is that the output logic is dependent only on the states in the latter
*/
always @(state)
begin
case(state)
Sone:
begin
match=1'd0;
err=1'd0;
end
Szero:
begin
match=1'd0;
err=1'd0;
end
Sfound:
begin
match=1'd1;
err=1'd0;
end
Serr:
begin
match=1'd0;
err=1'd1;
end
// Default state is the error, Serr, state
default:
begin
match=1'd0;
err=1'd1;
end
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
// psl cover {cyc==3 || cyc==4} @ (posedge clk);
// psl assert {cyc<100} @ (posedge clk) report "AssertionFalse1";
`ifdef FAILING_ASSERTIONS
// psl assert {toggle} @ (posedge clk) report "AssertionShouldFail";
`endif
// psl default clock = negedge clk;
//FIX // psl assert always {cyc<99};
// psl cover {cyc==9} report "DefaultClock,expect=1";
// psl assert {(cyc==5)->toggle};
// psl cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
`ifdef NOT_SUP
// psl assert {toggle<->cyc[0]};
// psl cover {toggle<->cyc[0]} report "CycsLogIff,expect=10";
`endif
// Test {{..}} == Sequence of sequence...
// psl assert {{true}};
always @ (negedge clk) begin
//if (!(cyc==5) || toggle) $write("%d: %s\n", cyc, "ToggleLogIf,expect=1");
//if (toggle&&cyc[0] || ~toggle&&~cyc[0]) $write("%d: %s\n", cyc, "CycsLogIff,expect=10");
end
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:53:07 07/01/2014
// Design Name:
// Module Name: cheat
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module cheat(
input clk,
input [7:0] SNES_PA,
input [23:0] SNES_ADDR,
input [7:0] SNES_DATA,
input SNES_wr_strobe,
input SNES_rd_strobe,
input SNES_reset_strobe,
input snescmd_enable,
input nmicmd_enable,
input return_vector_enable,
input reset_vector_enable,
input branch1_enable,
input branch2_enable,
input pad_latch,
input snes_ajr,
input SNES_cycle_start,
input [2:0] pgm_idx,
input pgm_we,
input [31:0] pgm_in,
output [7:0] data_out,
output cheat_hit,
output snescmd_unlock
);
wire snescmd_wr_strobe = snescmd_enable & SNES_wr_strobe;
reg cheat_enable = 0;
reg nmi_enable = 0;
reg irq_enable = 0;
reg holdoff_enable = 0; // temp disable hooks after reset
reg buttons_enable = 0;
reg wram_present = 0;
wire branch_wram = cheat_enable & wram_present;
reg auto_nmi_enable = 1;
reg auto_irq_enable = 0;
reg auto_nmi_enable_sync = 0;
reg auto_irq_enable_sync = 0;
reg hook_enable_sync = 0;
reg [1:0] sync_delay = 2'b10;
reg [4:0] nmi_usage = 5'h00;
reg [4:0] irq_usage = 5'h00;
reg [20:0] usage_count = 21'h1fffff;
reg [29:0] hook_enable_count = 0;
reg hook_disable = 0;
reg [1:0] vector_unlock_r = 0;
wire vector_unlock = |vector_unlock_r;
reg [1:0] reset_unlock_r = 2'b10;
wire reset_unlock = |reset_unlock_r;
reg [23:0] cheat_addr[5:0];
reg [7:0] cheat_data[5:0];
reg [5:0] cheat_enable_mask;
reg snescmd_unlock_r = 0;
assign snescmd_unlock = snescmd_unlock_r;
reg [7:0] nmicmd = 0;
reg [7:0] return_vector = 8'hea;
reg [7:0] branch1_offset = 8'h00;
reg [7:0] branch2_offset = 8'h00;
reg [15:0] pad_data = 0;
wire [5:0] cheat_match_bits ={(cheat_enable_mask[5] & (SNES_ADDR == cheat_addr[5])),
(cheat_enable_mask[4] & (SNES_ADDR == cheat_addr[4])),
(cheat_enable_mask[3] & (SNES_ADDR == cheat_addr[3])),
(cheat_enable_mask[2] & (SNES_ADDR == cheat_addr[2])),
(cheat_enable_mask[1] & (SNES_ADDR == cheat_addr[1])),
(cheat_enable_mask[0] & (SNES_ADDR == cheat_addr[0]))};
wire cheat_addr_match = |cheat_match_bits;
wire [1:0] nmi_match_bits = {SNES_ADDR == 24'h00FFEA, SNES_ADDR == 24'h00FFEB};
wire [1:0] irq_match_bits = {SNES_ADDR == 24'h00FFEE, SNES_ADDR == 24'h00FFEF};
wire [1:0] rst_match_bits = {SNES_ADDR == 24'h00FFFC, SNES_ADDR == 24'h00FFFD};
wire nmi_addr_match = |nmi_match_bits;
wire irq_addr_match = |irq_match_bits;
wire rst_addr_match = |rst_match_bits;
wire hook_enable = ~|hook_enable_count;
assign data_out = cheat_match_bits[0] ? cheat_data[0]
: cheat_match_bits[1] ? cheat_data[1]
: cheat_match_bits[2] ? cheat_data[2]
: cheat_match_bits[3] ? cheat_data[3]
: cheat_match_bits[4] ? cheat_data[4]
: cheat_match_bits[5] ? cheat_data[5]
: nmi_match_bits[1] ? 8'h04
: irq_match_bits[1] ? 8'h04
: rst_match_bits[1] ? 8'h6b
: nmicmd_enable ? nmicmd
: return_vector_enable ? return_vector
: branch1_enable ? branch1_offset
: branch2_enable ? branch2_offset
: 8'h2a;
assign cheat_hit = (snescmd_unlock & hook_enable_sync & (nmicmd_enable | return_vector_enable | branch1_enable | branch2_enable))
| (reset_unlock & rst_addr_match)
| (cheat_enable & cheat_addr_match)
| (hook_enable_sync & (((auto_nmi_enable_sync & nmi_enable) & nmi_addr_match & vector_unlock)
|((auto_irq_enable_sync & irq_enable) & irq_addr_match & vector_unlock)));
// irq/nmi detect based on CPU access pattern
// 4 writes (mirrored to B bus) signify that the CPU pushes PB, PC and
// SR to the stack and is going to read the vector address in the next
// two cycles.
// B bus mirror is used (combined with A BUS /WR!) so the write pattern
// cannot be confused with backwards DMA transfers.
reg [7:0] next_pa_addr = 0;
reg [2:0] cpu_push_cnt = 0;
always @(posedge clk) begin
if(SNES_reset_strobe) begin
cpu_push_cnt <= 0;
end else if(SNES_wr_strobe) begin
cpu_push_cnt <= cpu_push_cnt + 1;
if(cpu_push_cnt == 3'b0) begin
next_pa_addr <= SNES_PA - 1;
end else begin
if(SNES_PA == next_pa_addr) begin
next_pa_addr <= next_pa_addr - 1;
end else begin
cpu_push_cnt <= 3'b0;
end
end
end else if(SNES_rd_strobe) begin
cpu_push_cnt <= 3'b0;
end
end
// make patched vectors visible for last cycles of NMI/IRQ handling only
always @(posedge clk) begin
if(SNES_reset_strobe) begin
vector_unlock_r <= 2'b00;
end else if(SNES_rd_strobe) begin
if(hook_enable_sync
& ((auto_nmi_enable_sync & nmi_enable & nmi_match_bits[1])
|(auto_irq_enable_sync & irq_enable & irq_match_bits[1]))
& cpu_push_cnt == 4) begin
vector_unlock_r <= 2'b11;
end else if(|vector_unlock_r) begin
vector_unlock_r <= vector_unlock_r - 1;
end
end
end
// make patched reset vector visible for first fetch only
// (including masked read by Ultra16)
always @(posedge clk) begin
if(SNES_reset_strobe) begin
reset_unlock_r <= 2'b11;
end else if(SNES_cycle_start) begin
if(rst_addr_match & |reset_unlock_r) begin
reset_unlock_r <= reset_unlock_r - 1;
end
end
end
reg snescmd_unlock_disable_strobe = 1'b0;
reg [6:0] snescmd_unlock_disable_countdown = 0;
reg snescmd_unlock_disable = 0;
always @(posedge clk) begin
if(SNES_reset_strobe) begin
snescmd_unlock_r <= 0;
snescmd_unlock_disable <= 0;
end else begin
if(SNES_rd_strobe) begin
if(hook_enable_sync
& ((auto_nmi_enable_sync & nmi_enable & nmi_match_bits[1])
|(auto_irq_enable_sync & irq_enable & irq_match_bits[1]))
& cpu_push_cnt == 4) begin
// remember where we came from (IRQ/NMI) for hook exit
return_vector <= SNES_ADDR[7:0];
snescmd_unlock_r <= 1;
end
if(rst_match_bits[1] & |reset_unlock_r) begin
snescmd_unlock_r <= 1;
end
end
// give some time to exit snescmd memory and jump to original vector
if(SNES_cycle_start) begin
if(snescmd_unlock_disable) begin
if(|snescmd_unlock_disable_countdown) begin
snescmd_unlock_disable_countdown <= snescmd_unlock_disable_countdown - 1;
end else if(snescmd_unlock_disable_countdown == 0) begin
snescmd_unlock_r <= 0;
snescmd_unlock_disable <= 0;
end
end
end
if(snescmd_unlock_disable_strobe) begin
snescmd_unlock_disable_countdown <= 7'd72;
snescmd_unlock_disable <= 1;
end
end
end
always @(posedge clk) usage_count <= usage_count - 1;
// Try and autoselect NMI or IRQ hook
always @(posedge clk) begin
if(usage_count == 21'b0) begin
nmi_usage <= SNES_cycle_start & nmi_match_bits[1];
irq_usage <= SNES_cycle_start & irq_match_bits[1];
if(|nmi_usage & |irq_usage) begin
auto_nmi_enable <= 1'b1;
auto_irq_enable <= 1'b0;
end else if(irq_usage == 5'b0) begin
auto_nmi_enable <= 1'b1;
auto_irq_enable <= 1'b0;
end else if(nmi_usage == 5'b0) begin
auto_nmi_enable <= 1'b0;
auto_irq_enable <= 1'b1;
end
end else begin
if(SNES_cycle_start & nmi_match_bits[0]) nmi_usage <= nmi_usage + 1;
if(SNES_cycle_start & irq_match_bits[0]) irq_usage <= irq_usage + 1;
end
end
// Do not change vectors while they are being read
always @(posedge clk) begin
if(SNES_cycle_start) begin
if(nmi_addr_match | irq_addr_match) sync_delay <= 2'b10;
else begin
if (|sync_delay) sync_delay <= sync_delay - 1;
if (sync_delay == 2'b00) begin
auto_nmi_enable_sync <= auto_nmi_enable;
auto_irq_enable_sync <= auto_irq_enable;
hook_enable_sync <= hook_enable;
end
end
end
end
// CMD 0x85: disable hooks for 10 seconds
always @(posedge clk) begin
if((snescmd_unlock & snescmd_wr_strobe & ~|SNES_ADDR[8:0] & (SNES_DATA == 8'h85))
| (holdoff_enable & SNES_reset_strobe)) begin
hook_enable_count <= 30'd960000000;
end else if (|hook_enable_count) begin
hook_enable_count <= hook_enable_count - 1;
end
end
always @(posedge clk) begin
if(SNES_reset_strobe) begin
snescmd_unlock_disable_strobe <= 1'b0;
end else begin
snescmd_unlock_disable_strobe <= 1'b0;
if(snescmd_unlock & snescmd_wr_strobe) begin
if(~|SNES_ADDR[8:0]) begin
case(SNES_DATA)
8'h82: cheat_enable <= 1;
8'h83: cheat_enable <= 0;
8'h84: {nmi_enable, irq_enable} <= 2'b00;
endcase
end else if(SNES_ADDR[8:0] == 9'h1fd) begin
snescmd_unlock_disable_strobe <= 1'b1;
end
end else if(pgm_we) begin
if(pgm_idx < 6) begin
cheat_addr[pgm_idx] <= pgm_in[31:8];
cheat_data[pgm_idx] <= pgm_in[7:0];
end else if(pgm_idx == 6) begin // set rom patch enable
cheat_enable_mask <= pgm_in[5:0];
end else if(pgm_idx == 7) begin // set/reset global enable / hooks
// pgm_in[7:4] are reset bit flags
// pgm_in[3:0] are set bit flags
{wram_present, buttons_enable, holdoff_enable, irq_enable, nmi_enable, cheat_enable}
<= ({wram_present, buttons_enable, holdoff_enable, irq_enable, nmi_enable, cheat_enable}
& ~pgm_in[13:8])
| pgm_in[5:0];
end
end
end
end
// map controller input to cmd output
// check button combinations
// L+R+Start+Select : $3030
// L+R+Select+X : $2070
// L+R+Start+A : $10b0
// L+R+Start+B : $9030
// L+R+Start+Y : $5030
// L+R+Start+X : $1070
always @(posedge clk) begin
if(snescmd_wr_strobe) begin
if(SNES_ADDR[8:0] == 9'h1f0) begin
pad_data[7:0] <= SNES_DATA;
end else if(SNES_ADDR[8:0] == 9'h1f1) begin
pad_data[15:8] <= SNES_DATA;
end
end
end
always @* begin
case(pad_data)
16'h3030: nmicmd = 8'h80;
16'h2070: nmicmd = 8'h81;
16'h10b0: nmicmd = 8'h82;
16'h9030: nmicmd = 8'h83;
16'h5030: nmicmd = 8'h84;
16'h1070: nmicmd = 8'h85;
default: nmicmd = 8'h00;
endcase
end
always @* begin
if(buttons_enable) begin
if(snes_ajr) begin
if(nmicmd) begin
branch1_offset = 8'h30; // nmi_echocmd
end else begin
if(branch_wram) begin
branch1_offset = 8'h3a; // nmi_patches
end else begin
branch1_offset = 8'h3d; // nmi_exit
end
end
end else begin
if(pad_latch) begin
if(branch_wram) begin
branch1_offset = 8'h3a; // nmi_patches
end else begin
branch1_offset = 8'h3d; // nmi_exit
end
end else begin
branch1_offset = 8'h00; // continue with MJR
end
end
end else begin
if(branch_wram) begin
branch1_offset = 8'h3a; // nmi_patches
end else begin
branch1_offset = 8'h3d; // nmi_exit
end
end
end
always @* begin
if(nmicmd == 8'h81) begin
branch2_offset = 8'h0e; // nmi_stop
end else if(branch_wram) begin
branch2_offset = 8'h00; // nmi_patches
end else begin
branch2_offset = 8'h03; // nmi_exit
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O41AI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__O41AI_FUNCTIONAL_V
/**
* o41ai: 4-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o41ai (
Y ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O41AI_FUNCTIONAL_V |
// Build a test bench to test the design
module testBench;
wire [12:0] pc; // connect the pc
wire clock; // connect the clock
hal1 aComputer (clock, pc); // build an instance of the computer
test_it aTester(clock, pc); // build a tester
initial
begin
$dumpfile("hal1.vcd");
$dumpvars(1,aComputer);
end
endmodule
// The Computer - HAL1
module hal1 (clock, pc);
// declare the parameters
input clock;
output [12:0] pc;
reg [31:0] m [7:0]; // 8 x 32 bit memory
reg [12:0] pc; // 13 bit program counter
reg [31:0] acc; // 32 bit accumulator
reg [15:0] ir; // 16 bit instruction register
reg [31:0] r[7:0]; // 16 x 32 value
initial // initialize the pc and the accumulator
begin // define the instruction rom
pc = 0;
acc = 0;
$display("\nInitize acc with 0", acc);
m[0] = 'h0000; // these are for illustration
m[1] = 'h2001;
m[2] = 'h4002;
m[3] = 'h6003;
m[4] = 'ha004;
m[5] = 'hc005;
m[6] = 'h6206;
m[7] = 'h8007;
r[0] = 'h0; // these are for illustration
r[1] = 'h1;
r[2] = 'h2;
r[3] = 'h3;
r[4] = 'h4;
r[5] = 'h5;
r[6] = 'h6;
r[7] = 'h7;
end
always
begin
@(posedge clock)
ir = m [pc]; // fetch an instruction
if (ir[15:13] == 3'b000) // begin decoding
pc = m [ir [12:0]]; // and executing
else if (ir[15:13] == 3'b001)
pc = pc + m [ir [12:0]];
else if (ir[15:13] == 3'b010)
acc = m [ir [12:0]];
else if (ir[15:13] == 3'b011)
m [ir [12:0]] = acc;
else if ((ir[15:13] == 3'b101) || (ir[15:13] == 3'b100))
acc = acc - m [ir [12:0]];
else if (ir[15:13] == 3'b110)
begin
acc = -m [ir [12:0]];
pc = pc+1;
acc = r[(ir[12:10])]+r[(ir[3:0])];
end
pc = (pc + 1)%8; //increment program
// counter
end
endmodule
// Test module
module test_it(clock, pc);
// declare the parameters
input [12:0] pc;
output clock;
reg clock; // system clock
parameter period = 1;
initial
clock = 0;
// manage the clock
always
begin
#(period) clock = ~clock;
end
// manage the display
always @(posedge clock)
begin
$strobe ($time,, "pc = %d", pc); // record every time tick
// look for changes
$monitor ($time,, "pc = %d", pc); // record only changes
#(30*period); // let clock cycle a couple of times
#(period); // needed to see END of a simulation
$finish; // return to dos
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003-2007 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define STRINGIFY(x) `"x`"
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
wire out;
reg in;
Genit g (.clk(clk), .value(in), .result(out));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n", $time, cyc, in, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
in <= 1'b1;
end
else if (cyc==1) begin
in <= 1'b0;
end
else if (cyc==2) begin
if (out != 1'b1) $stop;
end
else if (cyc==3) begin
if (out != 1'b0) $stop;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
$dumpvars(12, t);
end
`endif
endmodule
module Generate (clk, value, result);
input clk;
input value;
output result;
reg Internal;
assign result = Internal ^ clk;
always @(posedge clk)
Internal <= #1 value;
endmodule
module Checker (clk, value);
input clk, value;
always @(posedge clk) begin
$write ("[%0t] value=%h\n", $time, value);
end
endmodule
module Test (clk, value, result);
input clk;
input value;
output result;
Generate gen (clk, value, result);
Checker chk (clk, gen.Internal);
endmodule
module Genit (clk, value, result);
input clk;
input value;
output result;
`ifndef ATSIM // else unsupported
`ifndef NC // else unsupported
`define WITH_FOR_GENVAR
`endif
`endif
`define WITH_GENERATE
`ifdef WITH_GENERATE
`ifndef WITH_FOR_GENVAR
genvar i;
`endif
generate
for (
`ifdef WITH_FOR_GENVAR
genvar
`endif
i = 0; i < 1; i = i + 1)
begin : foo
Test tt (clk, value, result);
end
endgenerate
`else
Test tt (clk, value, result);
`endif
wire Result2 = t.g.foo[0].tt.gen.Internal; // Works - Do not change!
always @ (posedge clk) begin
$write("[%0t] Result2 = %x\n", $time, Result2);
end
endmodule
|
// megafunction wizard: %ALTLVDS%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altlvds_rx
// ============================================================
// File Name: altera_tse_pma_lvds_rx.v
// Megafunction Name(s):
// altlvds_rx
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Internal Build 97 06/25/2007 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altera_tse_pma_lvds_rx (
rx_in,
rx_inclock,
rx_reset,
rx_divfwdclk,
rx_out,
rx_outclock);
input [0:0] rx_in;
input rx_inclock;
input [0:0] rx_reset;
output [0:0] rx_divfwdclk;
output [9:0] rx_out;
output rx_outclock;
wire [0:0] sub_wire0;
wire [9:0] sub_wire1;
wire sub_wire2;
wire [0:0] rx_divfwdclk = sub_wire0[0:0];
wire [9:0] rx_out = sub_wire1[9:0];
wire rx_outclock = sub_wire2;
altlvds_rx altlvds_rx_component (
.rx_inclock (rx_inclock),
.rx_reset (rx_reset),
.rx_in (rx_in),
.rx_divfwdclk (sub_wire0),
.rx_out (sub_wire1),
.rx_outclock (sub_wire2),
.pll_areset (1'b0),
.rx_cda_max (),
.rx_cda_reset (1'b0),
.rx_channel_data_align (1'b0),
.rx_coreclk (1'b1),
.rx_data_align (1'b0),
.rx_deskew (1'b0),
.rx_dpa_locked (),
.rx_dpll_enable (1'b1),
.rx_dpll_hold (1'b0),
.rx_dpll_reset (1'b0),
.rx_enable (1'b1),
.rx_fifo_reset (1'b0),
.rx_locked (),
.rx_pll_enable (1'b1),
.rx_readclock (1'b0),
.rx_syncclock (1'b0));
defparam
altlvds_rx_component.common_rx_tx_pll = "ON",
altlvds_rx_component.deserialization_factor = 10,
altlvds_rx_component.enable_dpa_mode = "ON",
altlvds_rx_component.enable_soft_cdr_mode = "ON",
altlvds_rx_component.implement_in_les = "OFF",
altlvds_rx_component.inclock_period = 8000,
altlvds_rx_component.input_data_rate = 1250,
altlvds_rx_component.intended_device_family = "Stratix III",
altlvds_rx_component.lpm_type = "altlvds_rx",
altlvds_rx_component.number_of_channels = 1,
altlvds_rx_component.outclock_resource = "AUTO",
altlvds_rx_component.registered_output = "ON",
altlvds_rx_component.use_external_pll = "OFF",
altlvds_rx_component.enable_dpa_align_to_rising_edge_only = "OFF",
altlvds_rx_component.enable_dpa_initial_phase_selection = "OFF";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Bitslip NUMERIC "4"
// Retrieval info: PRIVATE: Channel_Data_Align_Max NUMERIC "0"
// Retrieval info: PRIVATE: Channel_Data_Align_Reset NUMERIC "0"
// Retrieval info: PRIVATE: Clock_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Data_rate STRING "1250"
// Retrieval info: PRIVATE: Deser_Factor NUMERIC "10"
// Retrieval info: PRIVATE: Dpa_Locked NUMERIC "0"
// Retrieval info: PRIVATE: Dpll_Enable NUMERIC "0"
// Retrieval info: PRIVATE: Dpll_Hold NUMERIC "0"
// Retrieval info: PRIVATE: Dpll_Reset NUMERIC "1"
// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "ON"
// Retrieval info: PRIVATE: Ext_PLL STRING "OFF"
// Retrieval info: PRIVATE: Fifo_Reset NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: Int_Device STRING "Stratix III"
// Retrieval info: PRIVATE: LVDS_Mode NUMERIC "1"
// Retrieval info: PRIVATE: Le_Serdes STRING "OFF"
// Retrieval info: PRIVATE: Lose_Lock NUMERIC "0"
// Retrieval info: PRIVATE: Num_Channel NUMERIC "1"
// Retrieval info: PRIVATE: PLL_Enable NUMERIC "0"
// Retrieval info: PRIVATE: PLL_Freq STRING "125.00"
// Retrieval info: PRIVATE: PLL_Period STRING "8.000"
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
// Retrieval info: PRIVATE: Reset_Fifo NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "AUTO"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "1"
// Retrieval info: PRIVATE: Use_Data_Align NUMERIC "0"
// Retrieval info: PRIVATE: Use_Lock NUMERIC "0"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "10"
// Retrieval info: CONSTANT: ENABLE_DPA_MODE STRING "ON"
// Retrieval info: CONSTANT: ENABLE_SOFT_CDR_MODE STRING "ON"
// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "OFF"
// Retrieval info: CONSTANT: INCLOCK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: INPUT_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_rx"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OUTCLOCK_RESOURCE STRING "AUTO"
// Retrieval info: CONSTANT: REGISTERED_OUTPUT STRING "ON"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: CONSTANT: enable_dpa_align_to_rising_edge_only STRING "OFF"
// Retrieval info: CONSTANT: enable_dpa_initial_phase_selection STRING "OFF"
// Retrieval info: USED_PORT: rx_divfwdclk 0 0 1 0 OUTPUT NODEFVAL rx_divfwdclk[0..0]
// Retrieval info: USED_PORT: rx_in 0 0 1 0 INPUT NODEFVAL rx_in[0..0]
// Retrieval info: USED_PORT: rx_inclock 0 0 0 0 INPUT_CLK_EXT GND rx_inclock
// Retrieval info: USED_PORT: rx_out 0 0 10 0 OUTPUT NODEFVAL rx_out[9..0]
// Retrieval info: USED_PORT: rx_outclock 0 0 0 0 OUTPUT NODEFVAL rx_outclock
// Retrieval info: USED_PORT: rx_reset 0 0 1 0 INPUT GND rx_reset[0..0]
// Retrieval info: CONNECT: @rx_in 0 0 1 0 rx_in 0 0 1 0
// Retrieval info: CONNECT: rx_out 0 0 10 0 @rx_out 0 0 10 0
// Retrieval info: CONNECT: @rx_inclock 0 0 0 0 rx_inclock 0 0 0 0
// Retrieval info: CONNECT: rx_divfwdclk 0 0 1 0 @rx_divfwdclk 0 0 1 0
// Retrieval info: CONNECT: @rx_reset 0 0 1 0 rx_reset 0 0 1 0
// Retrieval info: CONNECT: rx_outclock 0 0 0 0 @rx_outclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_tse_pma_lvds_rx_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
Require Import Verdi.Verdi.
Require Import Verdi.HandlerMonad.
Require Import Verdi.NameOverlay.
Require Import Verdi.LabeledNet.
Require Import TreeAux.
Require Import ZTreeAggregationDynamicLabeled.
Require Import InfSeqExt.infseq.
Require Import Relation_Definitions.
Require Import Relation_Operators.
Require Import Sumbool.
Require String.
Require Import mathcomp.ssreflect.ssreflect.
Require Import mathcomp.ssreflect.ssrbool.
Local Arguments update {_} {_} _ _ _ _ _ : simpl never.
Set Implicit Arguments.
Module ZTreeAggregationCorrect (Import NT : NameType)
(NOT : NameOrderedType NT) (NSet : MSetInterface.S with Module E := NOT)
(NOTC : NameOrderedTypeCompat NT) (NMap : FMapInterface.S with Module E := NOTC)
(Import RNT : RootNameType NT)
(Import ANT : AdjacentNameType NT)
(Import TA : TAux NT NOT NSet NOTC NMap).
Module ZTA := ZTreeAggregation NT NOT NSet NOTC NMap RNT ANT TA.
Import ZTA.
Definition connected (ns : list name) :=
forall n n', In n ns -> In n' ns ->
n = n' \/ (clos_trans name adjacent_to) n n'.
Definition node_aggregate (state : name -> option data) (n : name) :=
match state n with
| None => 0
| Some d => d.(aggregate)
end.
Lemma churn_free_stabilization :
forall s, event_step_star step_ordered_dynamic step_ordered_dynamic_init (hd s) ->
connected (hd s).(evt_a).(odnwNodes) ->
lb_step_execution lb_step_ordered_dynamic s ->
weak_fairness lb_step_ordered_dynamic Tau s ->
forall n, root n -> In n (hd s).(evt_a).(odnwNodes) ->
eventually (always (now (fun e => length e.(evt_a).(odnwNodes) = node_aggregate e.(evt_a).(odnwState) n))) s.
Proof.
Admitted.
End ZTreeAggregationCorrect.
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:28:52 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xlconcat_0_0/zqynq_lab_1_design_xlconcat_0_0_sim_netlist.v
// Design : zqynq_lab_1_design_xlconcat_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_xlconcat_0_0,xlconcat_v2_1_1_xlconcat,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zqynq_lab_1_design_xlconcat_0_0
(In0,
In1,
dout);
input [0:0]In0;
input [0:0]In1;
output [1:0]dout;
wire [0:0]In0;
wire [0:0]In1;
assign dout[1] = In1;
assign dout[0] = In0;
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Generic source synchronous SDR input
*/
module ssio_sdr_in #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
// Use BUFR for Virtex-5, Virtex-6, 7-series
// Use BUFG for Ultrascale
// Use BUFIO2 for Spartan-6
parameter CLOCK_INPUT_STYLE = "BUFIO2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire input_clk,
input wire [WIDTH-1:0] input_d,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
wire clk_int;
wire clk_io;
generate
if (TARGET == "XILINX") begin
// use Xilinx clocking primitives
if (CLOCK_INPUT_STYLE == "BUFG") begin
// buffer RX clock
BUFG
clk_bufg (
.I(input_clk),
.O(clk_int)
);
// pass through RX clock to logic and input buffers
assign clk_io = clk_int;
assign output_clk = clk_int;
end else if (CLOCK_INPUT_STYLE == "BUFR") begin
assign clk_int = input_clk;
// pass through RX clock to input buffers
BUFIO
clk_bufio (
.I(clk_int),
.O(clk_io)
);
// pass through RX clock to logic
BUFR #(
.BUFR_DIVIDE("BYPASS")
)
clk_bufr (
.I(clk_int),
.O(output_clk),
.CE(1'b1),
.CLR(1'b0)
);
end else if (CLOCK_INPUT_STYLE == "BUFIO") begin
assign clk_int = input_clk;
// pass through RX clock to input buffers
BUFIO
clk_bufio (
.I(clk_int),
.O(clk_io)
);
// pass through RX clock to MAC
BUFG
clk_bufg (
.I(clk_int),
.O(output_clk)
);
end else if (CLOCK_INPUT_STYLE == "BUFIO2") begin
// pass through RX clock to input buffers
BUFIO2 #(
.DIVIDE(1),
.DIVIDE_BYPASS("TRUE"),
.I_INVERT("FALSE"),
.USE_DOUBLER("FALSE")
)
clk_bufio (
.I(input_clk),
.DIVCLK(clk_int),
.IOCLK(clk_io),
.SERDESSTROBE()
);
// pass through RX clock to MAC
BUFG
clk_bufg (
.I(clk_int),
.O(output_clk)
);
end
end else begin
// pass through RX clock to input buffers
assign clk_io = input_clk;
// pass through RX clock to logic
assign clk_int = input_clk;
assign output_clk = clk_int;
end
endgenerate
(* IOB = "TRUE" *)
reg [WIDTH-1:0] output_q_reg = {WIDTH{1'b0}};
assign output_q = output_q_reg;
always @(posedge clk_io) begin
output_q_reg <= input_d;
end
endmodule
`resetall
|
/***************************************************************************************************
** fpga_nes/hw/src/cmn/uart/uart_rx.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* UART receiver.
***************************************************************************************************/
module uart_rx
#(
parameter DATA_BITS = 8,
parameter STOP_BITS = 1,
parameter PARITY_MODE = 1, // 0 = NONE, 1 = ODD, 2 = EVEN
parameter BAUD_CLK_OVERSAMPLE_RATE = 16
)
(
input wire clk, // System clock
input wire reset, // Reset signal
input wire baud_clk_tick, // 1 tick per OVERSAMPLE_RATE baud clks
input wire rx, // RX transmission wire
output wire [DATA_BITS-1:0] rx_data, // Output data
output wire rx_done_tick, // Output rdy signal
output wire parity_err // Asserted for one clk on parity error
);
localparam [5:0] STOP_OVERSAMPLE_TICKS = STOP_BITS * BAUD_CLK_OVERSAMPLE_RATE;
// Symbolic state representations.
localparam [4:0] S_IDLE = 5'h01,
S_START = 5'h02,
S_DATA = 5'h04,
S_PARITY = 5'h08,
S_STOP = 5'h10;
// Registers
reg [4:0] q_state, d_state;
reg [3:0] q_oversample_tick_cnt, d_oversample_tick_cnt;
reg [DATA_BITS-1:0] q_data, d_data;
reg [2:0] q_data_bit_idx, d_data_bit_idx;
reg q_done_tick, d_done_tick;
reg q_parity_err, d_parity_err;
reg q_rx;
always @(posedge clk, posedge reset)
begin
if (reset)
begin
q_state <= S_IDLE;
q_oversample_tick_cnt <= 0;
q_data <= 0;
q_data_bit_idx <= 0;
q_done_tick <= 1'b0;
q_parity_err <= 1'b0;
q_rx <= 1'b1;
end
else
begin
q_state <= d_state;
q_oversample_tick_cnt <= d_oversample_tick_cnt;
q_data <= d_data;
q_data_bit_idx <= d_data_bit_idx;
q_done_tick <= d_done_tick;
q_parity_err <= d_parity_err;
q_rx <= rx;
end
end
always @*
begin
// Default most state to remain unchanged.
d_state = q_state;
d_data = q_data;
d_data_bit_idx = q_data_bit_idx;
// Increment the tick counter if the baud_clk counter ticked.
d_oversample_tick_cnt = (baud_clk_tick) ? q_oversample_tick_cnt + 4'h1 : q_oversample_tick_cnt;
// Default the done signal and parity err to 0.
d_done_tick = 1'b0;
d_parity_err = 1'b0;
case (q_state)
S_IDLE:
begin
// Detect incoming data when rx goes low (start bit).
if (~q_rx)
begin
d_state = S_START;
d_oversample_tick_cnt = 0;
end
end
S_START:
begin
// Wait for BAUD_CLK_OVERSAMPLE_RATE / 2 ticks to get "centered" in the start bit signal.
if (baud_clk_tick && (q_oversample_tick_cnt == ((BAUD_CLK_OVERSAMPLE_RATE - 1) / 2)))
begin
d_state = S_DATA;
d_oversample_tick_cnt = 0;
d_data_bit_idx = 0;
end
end
S_DATA:
begin
// Every BAUD_CLK_OVERSAMPLE_RATE clocks, sample rx and shift its value into the data reg.
if (baud_clk_tick && (q_oversample_tick_cnt == (BAUD_CLK_OVERSAMPLE_RATE - 1)))
begin
d_data = { q_rx, q_data[DATA_BITS-1:1] };
d_oversample_tick_cnt = 0;
if (q_data_bit_idx == (DATA_BITS - 1))
begin
if (PARITY_MODE == 0)
d_state = S_STOP;
else
d_state = S_PARITY;
end
else
d_data_bit_idx = q_data_bit_idx + 3'h1;
end
end
S_PARITY:
begin
if (baud_clk_tick && (q_oversample_tick_cnt == (BAUD_CLK_OVERSAMPLE_RATE - 1)))
begin
if (PARITY_MODE == 1)
d_parity_err = (q_rx != ~^q_data);
else
d_parity_err = (q_rx != ^q_data);
d_state = S_STOP;
d_oversample_tick_cnt = 0;
end
end
S_STOP:
begin
// Wait for stop bit before returning to idle. Signal done_tick.
if (baud_clk_tick && (q_oversample_tick_cnt == STOP_OVERSAMPLE_TICKS - 1))
begin
d_state = S_IDLE;
d_done_tick = 1'b1;
end
end
endcase
end
assign rx_data = q_data;
assign rx_done_tick = q_done_tick;
assign parity_err = q_parity_err;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/);
initial begin
int q[int];
int qe[int]; // Empty
int qv[$]; // Value returns
int qi[$]; // Index returns
int i;
string v;
q = '{10:1, 11:2, 12:2, 13:4, 14:3};
v = $sformatf("%p", q); `checks(v, "'{'ha:'h1, 'hb:'h2, 'hc:'h2, 'hd:'h4, 'he:'h3} ");
// NOT tested: with ... selectors
//q.sort; // Not legal on assoc - see t_assoc_meth_bad
//q.rsort; // Not legal on assoc - see t_assoc_meth_bad
//q.reverse; // Not legal on assoc - see t_assoc_meth_bad
//q.shuffle; // Not legal on assoc - see t_assoc_meth_bad
v = $sformatf("%p", qe); `checks(v, "'{}");
qv = q.unique;
v = $sformatf("%p", qv); `checks(v, "'{'h1, 'h2, 'h4, 'h3} ");
qv = qe.unique;
v = $sformatf("%p", qv); `checks(v, "'{}");
qi = q.unique_index; qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{'ha, 'hb, 'hd, 'he} ");
qi = qe.unique_index;
v = $sformatf("%p", qi); `checks(v, "'{}");
// These require an with clause or are illegal
// TODO add a lint check that with clause is provided
qv = q.find with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2, 'h2} ");
qv = q.find_first with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2} ");
qv = q.find_last with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2} ");
qv = q.find with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = q.find_first with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = q.find_last with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qi = q.find_index with (item == 2); qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{'hb, 'hc} ");
qi = q.find_first_index with (item == 2);
v = $sformatf("%p", qi); `checks(v, "'{'hb} ");
qi = q.find_last_index with (item == 2);
v = $sformatf("%p", qi); `checks(v, "'{'hc} ");
qi = q.find_index with (item == 20); qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_first_index with (item == 20);
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_last_index with (item == 20);
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_index with (item.index == 12);
v = $sformatf("%p", qi); `checks(v, "'{'hc} ");
qi = q.find with (item.index == 12);
v = $sformatf("%p", qi); `checks(v, "'{'h2} ");
qv = q.min;
v = $sformatf("%p", qv); `checks(v, "'{'h1} ");
qv = q.max;
v = $sformatf("%p", qv); `checks(v, "'{'h4} ");
qv = qe.min;
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = qe.max;
v = $sformatf("%p", qv); `checks(v, "'{}");
// Reduction methods
i = q.sum;
`checkh(i, 32'hc);
i = q.sum with (item + 1);
`checkh(i, 32'h11);
i = q.product;
`checkh(i, 32'h30);
i = q.product with (item + 1);
`checkh(i, 32'h168);
i = qe.sum;
`checkh(i, 32'h0);
i = qe.product;
`checkh(i, 32'h0);
q = '{10:32'b1100, 11:32'b1010};
i = q.and;
`checkh(i, 32'b1000);
i = q.and with (item + 1);
`checkh(i, 32'b1001);
i = q.or;
`checkh(i, 32'b1110);
i = q.or with (item + 1);
`checkh(i, 32'b1111);
i = q.xor;
`checkh(i, 32'b0110);
i = q.xor with (item + 1);
`checkh(i, 32'b0110);
i = qe.and;
`checkh(i, 32'b0);
i = qe.or;
`checkh(i, 32'b0);
i = qe.xor;
`checkh(i, 32'b0);
i = q.and();
`checkh(i, 32'b1000);
i = q.and() with (item + 1);
`checkh(i, 32'b1001);
i = q.or();
`checkh(i, 32'b1110);
i = q.or() with (item + 1);
`checkh(i, 32'b1111);
i = q.xor();
`checkh(i, 32'b0110);
i = q.xor() with (item + 1);
`checkh(i, 32'b0110);
i = qe.and();
`checkh(i, 32'b0);
i = qe.or();
`checkh(i, 32'b0);
i = qe.xor();
`checkh(i, 32'b0);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
module test_bench(clk, rst);
input clk;
input rst;
wire [63:0] wire_39069600;
wire wire_39069600_stb;
wire wire_39069600_ack;
wire [63:0] wire_39795024;
wire wire_39795024_stb;
wire wire_39795024_ack;
wire [63:0] wire_39795168;
wire wire_39795168_stb;
wire wire_39795168_ack;
file_reader_a file_reader_a_39796104(
.clk(clk),
.rst(rst),
.output_z(wire_39069600),
.output_z_stb(wire_39069600_stb),
.output_z_ack(wire_39069600_ack));
file_reader_b file_reader_b_39759816(
.clk(clk),
.rst(rst),
.output_z(wire_39795024),
.output_z_stb(wire_39795024_stb),
.output_z_ack(wire_39795024_ack));
file_writer file_writer_39028208(
.clk(clk),
.rst(rst),
.input_a(wire_39795168),
.input_a_stb(wire_39795168_stb),
.input_a_ack(wire_39795168_ack));
double_multiplier multiplier_39759952(
.clk(clk),
.rst(rst),
.input_a(wire_39069600),
.input_a_stb(wire_39069600_stb),
.input_a_ack(wire_39069600_ack),
.input_b(wire_39795024),
.input_b_stb(wire_39795024_stb),
.input_b_ack(wire_39795024_ack),
.output_z(wire_39795168),
.output_z_stb(wire_39795168_stb),
.output_z_ack(wire_39795168_ack));
endmodule
|
`include "oled_init.v"
`include "oled_cls.v"
module fpga (
input CLK,
input RST,
output CSN,
output SDIN,
output SCLK,
output DCN,
output RESN,
output VBATN,
output VDDN,
output [1:0] Led
);
reg [7:0] clock_counter='b0;
reg init_fin_latched='b1;
reg cls_fin_latched='b1;
assign Led[0]=init_fin_latched;
oled_init i_oled_init(
.clk(CLK),
.reset(RST),
.init_start(init_start),
.init_fin(init_fin),
.spi_csn(init_csn),
.spi_sdo(init_sdin),
.spi_sclk(init_sclk),
.spi_dcn(init_dcn),
.spi_resn(RESN),
.spi_vbatn(VBATN),
.spi_vddn(VDDN)
);
oled_cls i_oled_cls(
.clk(CLK),
.reset(RST),
.cls_start(cls_start),
.cls_fin(cls_fin),
.spi_csn(cls_csn),
.spi_sdo(cls_sdin),
.spi_sclk(cls_sclk),
.spi_dcn(cls_dcn)
);
assign init_start = (((&clock_counter)==1'b1) && (init_fin_latched==1'b0)) ? 1'b1 : 1'b0;
assign CSN = init_fin_latched ? cls_csn : init_csn;
assign SDIN = init_fin_latched ? cls_sdin : init_sdin;
assign SCLK = init_fin_latched ? cls_sclk : init_sclk;
assign DCN = init_fin_latched ? cls_dcn : init_dcn;
always @(posedge CLK) begin
if (RST) begin
clock_counter <= 'b0;
init_fin_latched <= 'b0;
cls_fin_latched <= 'b0;
end else begin
clock_counter <= clock_counter + 1;
if (init_fin)
init_fin_latched <= 'b1;
if (cls_fin)
cls_fin_latched <= 'b1;
end
end
assign cls_start = init_fin;
assign Led[1] = cls_fin_latched;
endmodule
|
//
// rom.v -- parallel flash ROM interface
//
module rom(clk, reset,
en, wr, size, addr,
data_out, wt,
ce_n, oe_n, we_n, rst_n, byte_n, a, d);
// internal interface signals
input clk;
input reset;
input en;
input wr;
input [1:0] size;
input [20:0] addr;
output reg [31:0] data_out;
output reg wt;
// flash ROM interface signals
output ce_n;
output oe_n;
output we_n;
output rst_n;
output byte_n;
output [19:0] a;
input [15:0] d;
reg [3:0] state;
reg a0;
// the following control signals are all
// either constantly asserted or deasserted
assign ce_n = 0;
assign oe_n = 0;
assign we_n = 1;
assign rst_n = 1;
assign byte_n = 1;
// the flash ROM is organized in 16-bit halfwords
// address line a0 is controlled by the state machine
// (this is necessary for word accesses)
assign a[19:1] = addr[20:2];
assign a[0] = a0;
// the state machine
always @(posedge clk) begin
if (reset == 1) begin
state <= 0;
wt <= 1;
end else begin
if (state == 0) begin
// wait for start of access
if (en == 1 && wr == 0) begin
state <= 1;
if (size[1] == 1) begin
// word access
a0 <= 0;
end else begin
// halfword or byte access
a0 <= addr[1];
end
end
end else
if (state == 6) begin
if (size[1] == 1) begin
// word access
// latch upper halfword
data_out[31:24] <= d[7:0];
data_out[23:16] <= d[15:8];
state <= 7;
a0 <= 1;
end else begin
// halfword or byte access
data_out[31:16] <= 16'h0000;
if (size[0] == 1) begin
// halfword access
data_out[15:8] <= d[7:0];
data_out[7:0] <= d[15:8];
end else begin
// byte access
data_out[15:8] <= 8'h00;
if (addr[0] == 0) begin
// even address
data_out[7:0] <= d[7:0];
end else begin
// odd address
data_out[7:0] <= d[15:8];
end
end
state <= 13;
wt <= 0;
end
end else
if (state == 12) begin
// word access (state is only reached in this case)
// latch lower halfword
data_out[15:8] <= d[7:0];
data_out[7:0] <= d[15:8];
state <= 13;
wt <= 0;
end else
if (state == 13) begin
// end of access
wt <= 1;
state <= 0;
end else begin
// wait for flash ROM access time to pass
state <= state + 1;
end
end
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This block takes the length and forms the appropriate burst count.
Whenever one of the short access enables are asserted this block
will post a burst of one. Posting a burst of one isn't necessary
but it will make it possible to add byte enable support to the
read master at a later date.
Revision History:
1.0 First version
1.1 Added generate logic around the internal burst count logic to prevent zero
replication simulation bug. In the case of a non-bursting master the
burst count is just hardcoded to 1.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_burst_control (
address,
length,
maximum_burst_count,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
burst_count
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE_LOG2 = 2; // log2(DATA WIDTH/8)
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when hte master supports programmable burst.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input [ADDRESS_WIDTH-1:0] address;
input [LENGTH_WIDTH-1:0] length;
input [BURST_COUNT_WIDTH-1:0] maximum_burst_count; // will be either a hardcoded input or programmable
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
wire [BURST_COUNT_WIDTH-1:0] posted_burst; // when the burst statemachine is used this will be the burst count posted to the fabric
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count; // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
wire burst_of_one_enable; // asserted when partial word accesses are occuring
wire short_burst_enable;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
// for unaligned or partial transfers we must use a burst length of 1 so that
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | // when performing partial accesses use a burst length of 1
((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0)); // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
generate
if ((BURST_ENABLE == 1) & (BURST_COUNT_WIDTH > 1))
begin
always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
begin
case ({short_burst_enable, burst_of_one_enable})
2'b00 : internal_burst_count = maximum_burst_count;
2'b01 : internal_burst_count = 1; // this is when the master starts unaligned
2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}}); // this could be followed by a burst of 1 if there are a few bytes leftover
2'b11 : internal_burst_count = 1; // burst of 1 needs to win, this is when the master starts with very little data to transfer
endcase
end
assign burst_count = internal_burst_count;
end
else
begin
assign burst_count = 1; // this will be stubbed at the top level but will be used for the address and pending reads incrementing
end
endgenerate
endmodule
|
`timescale 1ns/10ps
module RotaryLedSim;
reg clock0;
reg clock180;
reg reset;
reg [1:0] rotary;
wire [7:0] leds;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#5000 $finish;
end
initial begin
#0 clock0 = 1;
forever #2 clock0 = ~clock0;
end
initial begin
#0 clock180 = 0;
forever #2 clock180 = ~clock180;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#10 rotary = 2'b01;
#40 rotary = 2'b11;
#40 rotary = 2'b00;
#40 rotary = 2'b01;
#40 rotary = 2'b11;
#40 rotary = 2'b00;
#40 rotary = 2'b01;
#40 rotary = 2'b11;
#40 rotary = 2'b00;
#40 rotary = 2'b01;
#40 rotary = 2'b11;
#40 rotary = 2'b00;
#40 rotary = 2'b01;
#40 rotary = 2'b11;
#40 rotary = 2'b00;
#40 rotary = 2'b01;
#40 rotary = 2'b11;
#40 rotary = 2'b00;
#40 rotary = 2'b01;
#40 rotary = 2'b11;
#40 rotary = 2'b00;
#40 rotary = 2'b01;
#40 rotary = 2'b11;
#40 rotary = 2'b00;
#40 rotary = 2'b01;
#40 rotary = 2'b11;
#40 rotary = 2'b00;
#40 rotary = 2'b01;
#40 rotary = 2'b11;
#40 rotary = 2'b00;
#40 rotary = 2'b01;
#40 rotary = 2'b11;
#40 rotary = 2'b00;
end
RotaryLed
rotaryled (.clock0(clock0),
.clock180(clock180),
.reset(reset),
.rotary(rotary),
.leds(leds));
endmodule // ProtaryLedSim
|
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
// Digital model of a traffic light
// By Dan Hyde August 10, 1995
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red = off; amber = off; green = off;
$display(" Time green amber red");
$monitor("%3d %b %b %b", $time, green, amber, red);
end
// task to wait for 'tics' positive edge clocks
// before turning light off
task light;
output color;
input [31:0] tics;
begin
repeat(tics) // wait to detect tics positive edges on clock
@(posedge clock);
color = off;
end
endtask
// waveform for clock period of 2 time units
always begin: clock_wave
#1 clock = 0;
#1 clock = 1;
end
always begin: main_process
red = on;
light(red, red_tics); // call task to wait
green = on;
light(green, green_tics);
amber = on;
light(amber, amber_tics);
end
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: sfifo_65x128.v
// Megafunction Name(s):
// scfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 5.0 Build 168 06/22/2005 SP 1.30 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2005 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module sfifo_65x128 (
data,
wrreq,
rdreq,
clock,
aclr,
q,
full,
empty,
usedw,
almost_full);
input [64:0] data;
input wrreq;
input rdreq;
input clock;
input aclr;
output [64:0] q;
output full;
output empty;
output [6:0] usedw;
output almost_full;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Width NUMERIC "65"
// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "1"
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "3"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "65"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: ALMOST_FULL_VALUE NUMERIC "3"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: USED_PORT: data 0 0 65 0 INPUT NODEFVAL data[64..0]
// Retrieval info: USED_PORT: q 0 0 65 0 OUTPUT NODEFVAL q[64..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: usedw 0 0 7 0 OUTPUT NODEFVAL usedw[6..0]
// Retrieval info: USED_PORT: almost_full 0 0 0 0 OUTPUT NODEFVAL almost_full
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
// Retrieval info: CONNECT: @data 0 0 65 0 data 0 0 65 0
// Retrieval info: CONNECT: q 0 0 65 0 @q 0 0 65 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 7 0 @usedw 0 0 7 0
// Retrieval info: CONNECT: almost_full 0 0 0 0 @almost_full 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sfifo_65x128_wave*.jpg FALSE
|
/*
* Copyright 2012, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`timescale 1ns / 1ps
`define P 20 // clock period
`define M 593 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define WIDTH_D0 1187
module test_pairing;
// Inputs
reg clk;
reg reset;
reg sel;
reg [5:0] addr;
reg w;
reg update;
reg ready;
reg i;
// Outputs
wire done;
wire o;
// Buffers
reg [`WIDTH_D0:0] out;
// Instantiate the Unit Under Test (UUT)
pairing uut (
.clk(clk),
.reset(reset),
.sel(sel),
.addr(addr),
.w(w),
.update(update),
.ready(ready),
.i(i),
.o(o),
.done(done)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
sel = 0;
addr = 0;
w = 0;
update = 0;
ready = 0;
i = 0;
out = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
/* keep FSM silent */
reset = 1;
/* init xp, yp, xq, yq */
write(3, 1186'h088a6aa4a8aa80a9aa922965a92a56510856606aa6400649a6004866466928a20090908210195560a8162a52442029a44a68004a8168496a0a8a8564962a0948118a5599a29450214995828245914a099051991602550105228289686988621a1a9126648644619a66111a026452641169158a4686884aa212199582406600921229a5948802528289a62454a2566a4122586a496);
write(5, 1186'h05448582294062429a891a6509092496844141090214064988646241904502a0225046a54851a05454020044881088a2092411592909289861049124644a964a6188014aa25869a09890401a924048815a1008421459455411a4a65094410615a524458901026a9108a468650515a5aa50468005881a29055980995a145995146909841aa18890902264628884421894959956195);
write(6, 1186'h088a6aa4a8aa80a9aa922965a92a56510856606aa6400649a6004866466928a20090908210195560a8162a52442029a44a68004a8168496a0a8a8564962a0948118a5599a29450214995828245914a099051991602550105228289686988621a1a9126648644619a66111a026452641169158a4686884aa212199582406600921229a5948802528289a62454a2566a4122586a496);
write(7, 1186'h05448582294062429a891a6509092496844141090214064988646241904502a0225046a54851a05454020044881088a2092411592909289861049124644a964a6188014aa25869a09890401a924048815a1008421459455411a4a65094410615a524458901026a9108a468650515a5aa50468005881a29055980995a145995146909841aa18890902264628884421894959956195);
/* read back. uncomment me if error happens */
/* read(3);
$display("xp = %h", out);
read(5);
$display("yp = %h", out);
read(6);
$display("xq = %h", out);
read(7);
$display("yq = %h", out);*/
reset = 0;
sel = 0; w = 0;
@(posedge done);
@(negedge clk);
read(9);
check(1186'h20115a6958895a08585a412698a58250900a651a859448a4848125164545598a426119a09885802424154a08855a0042a168516099228606222540582026aa0a6029a88805a1888628856a2a64504120aa290491925284508921140a24a0a8641548a521512698985a610861a401208644612a4a52625119000006004518844899810191a056aaa680889958996508954685a0920);
read(10);
check(1186'h228a9556506501a0258028a8856851a5466a205a2544849a12a10a018a40aaa461959859a4408245094969a44565a160a98229805169491120568121008a04918050a9022854868440662591221116889a9668a82aa84182a59025424469164015a56698a95989555601618402286696055608a82508125aaa5882000aaa96114998660a684582889a5a5190058a0411426145250);
read(11);
check(1186'h001224a468a9154205488585aaa9a0a9882056194952001a88424522191052a96a21102915181a845a5509844985196696160900a0515956a2a10a100a12566408a14450049a586951896442400a8620148582958a8a51869990a161412406860012a61a66214a4461a86895640a48284528201852615921952aaaaa40802586168a929582128a985929990826a9110186891489a);
read(12);
check(1186'h019618a9624a522a280a06a0654418906998059625a892054996a0560a941a842589189984190884426125114000aa60a0a568285221026662226a626a8600605095054405486561a95059449282969a5a10819101a620902609052a1294182962a020512196945a2aa42598a41842096596551544969262a12a86685214a952494a956166a199682a649249a990088296422051a);
read(13);
check(1186'h1a6999a0105054aaa2145298116480601695482119a0619155a4414a8a82840918a512a5680a8000889a4905016868480211289860a8a5699a250245161a042846096a9866025094a189860a9829465281646040866a26959a61a18621848689101a9a95685016a9581224968461a0a108958a91205a0220a18865105928298299a642a906900289a95095845649aa41591069866);
read(14);
check(1186'h15a4208a19a0405005900212505098a881a49445242619a12a12491844110169529a422046a684668819599891a411954196961160591865590a699a04908a6196928965a1686a664210420908115a5816919169662656a855099464680902514586265602510840a566a94a506961a615420a908aa91959610a1a0899589600902a10962460a664104126056a82551462459169a);
$display("Good");
$finish;
end
initial #100 forever #(`P/2) clk = ~clk;
task write;
input [5:0] adr;
input [`WIDTH_D0:0] dat;
integer j;
begin
sel = 1;
w = 0;
addr = adr;
update = 1;
#`P;
update = 0;
ready = 1;
for(j=0;j<`WIDTH_D0+1;j=j+1)
begin
i = dat[j];
#`P;
end
ready = 0;
w = 1; #`P; w = 0;
end
endtask
task read;
input [5:0] adr;
integer j;
begin
sel = 1;
w = 0;
addr = adr;
#`P;
update = 1;
#`P;
update = 0;
out = 0;
ready = 1;
for(j=0;j<`WIDTH_D0+1;j=j+1)
begin
out = {o, out[`WIDTH_D0:1]};
#`P;
end
end
endtask
task check;
input [`WIDTH_D0:0] wish;
begin
if (out !== wish)
begin $display("Error!"); $finish; end
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EDFXTP_1_V
`define SKY130_FD_SC_HS__EDFXTP_1_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog wrapper for edfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__edfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__edfxtp_1 (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
sky130_fd_sc_hs__edfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__edfxtp_1 (
Q ,
CLK,
D ,
DE
);
output Q ;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__edfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.DE(DE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__EDFXTP_1_V
|
/*
Instruction Cache Tiles
Fetch 48 bits from the instruction cache.
Instructions are 16 or 32 bits, but is 48 bits for pipeline reasons.
I-Cache Tiles are 4 DWORDs, or 16 bytes.
This cache operates inside the virtual address space.
*/
module IcTile2(
/* verilator lint_off UNUSED */
clock, reset,
regInPc,
regOutPcVal, regOutPcOK,
memPcData,
memPcAddr, memPcOE, memPcOK
);
input clock;
input reset;
input[31:0] regInPc; //input PC address
output[47:0] regOutPcVal; //output PC value
output[1:0] regOutPcOK; //set if we have a valid value.
input[127:0] memPcData; //memory PC data
input[1:0] memPcOK; //memory PC OK
output[31:0] memPcAddr; //memory PC address
output memPcOE; //memory PC output-enable
// reg[31:0] icBlkLo[511:0]; //Block Low DWord
// reg[31:0] icBlkHi[511:0]; //Block High DWord
(* ram_style="block" *) reg[31:0] icBlkA[255:0]; //Block DWord A
(* ram_style="block" *) reg[31:0] icBlkB[255:0]; //Block DWord B
(* ram_style="block" *) reg[31:0] icBlkC[255:0]; //Block DWord C
(* ram_style="block" *) reg[31:0] icBlkD[255:0]; //Block DWord D
(* ram_style="block" *) reg[31:0] icBlkE[255:0]; //Block DWord E (So Single Port)
(* ram_style="block" *) reg[27:0] icBlkAd[255:0]; //Block Addresses
reg[31:0] tRegInPc1;
reg[31:0] tRegInPc2;
reg[27:0] tBlkNeedAd1;
reg[27:0] tBlkNeedAd2;
reg[31:0] tRegInPc3;
reg[31:0] tRegInPc4;
reg[63:0] tBlkData1;
reg[63:0] tBlkData2;
reg[47:0] tRegOutPcVal;
reg[1:0] tRegOutPcOK;
reg[31:0] tMemPcAddr; //memory PC address
reg tMemPcOE; //memory PC output-enable
reg[27:0] reqNeedAd;
reg[27:0] nReqNeedAd;
assign regOutPcVal = tRegOutPcVal;
assign regOutPcOK = tRegOutPcOK;
assign memPcAddr = tMemPcAddr;
assign memPcOE = tMemPcOE;
reg[2:0] isReqTileSt;
reg[27:0] isReqNeedAd;
reg[2:0] nxtReqTileSt;
reg[27:0] nxtReqNeedAd;
reg doReqNeedAd;
reg nxtDoReqNeedAd;
reg nxtReqCommit;
reg[27:0] nxtReqCommitAd1;
reg[27:0] nxtReqCommitAd2;
reg[159:0] reqTempBlk;
reg[159:0] nxtReqTempBlk;
reg[159:0] accTempBlk;
always @ (clock)
begin
tRegInPc1=regInPc;
tRegInPc2=regInPc+4;
tBlkNeedAd1=tRegInPc1[31:4];
tBlkNeedAd2=tRegInPc2[31:4];
tRegOutPcVal=48'h0F3B_0F3B_0F3B;
// tRegOutPcVal=0;
tRegOutPcOK=0;
nReqNeedAd=0;
nxtDoReqNeedAd=0;
if((tBlkNeedAd1==icBlkAd[tBlkNeedAd1[7:0]]) &&
(tBlkNeedAd2==icBlkAd[tBlkNeedAd2[7:0]]))
begin
accTempBlk[ 31: 0]=icBlkA[tBlkNeedAd1[7:0]];
accTempBlk[ 63: 32]=icBlkB[tBlkNeedAd1[7:0]];
accTempBlk[ 95: 64]=icBlkC[tBlkNeedAd1[7:0]];
accTempBlk[127: 96]=icBlkD[tBlkNeedAd1[7:0]];
accTempBlk[159:128]=icBlkE[tBlkNeedAd2[7:0]];
// accTempBlk[159:128]=icBlkA[tBlkNeedAd2[7:0]];
case(regInPc[3:1])
3'b000: tRegOutPcVal=accTempBlk[ 47: 0];
3'b001: tRegOutPcVal=accTempBlk[ 63: 16];
3'b010: tRegOutPcVal=accTempBlk[ 79: 32];
3'b011: tRegOutPcVal=accTempBlk[ 95: 48];
3'b100: tRegOutPcVal=accTempBlk[111: 64];
3'b101: tRegOutPcVal=accTempBlk[127: 80];
3'b110: tRegOutPcVal=accTempBlk[143: 96];
3'b111: tRegOutPcVal=accTempBlk[159:112];
endcase
tRegOutPcOK=1;
end
else if(isReqTileSt==3'h0)
begin
if(tBlkNeedAd1==icBlkAd[tBlkNeedAd1[7:0]])
begin
$display("IcMiss2 %X", tBlkNeedAd2);
nReqNeedAd=tBlkNeedAd2;
nxtDoReqNeedAd=1;
end
else
begin
$display("IcMiss1 %X", tBlkNeedAd1);
nReqNeedAd=tBlkNeedAd1;
nxtDoReqNeedAd=1;
end
end
tMemPcAddr=0;
tMemPcOE=0;
nxtReqTileSt=isReqTileSt;
nxtReqTempBlk = reqTempBlk;
nxtReqCommit = 0;
nxtReqCommitAd1 = 0;
nxtReqCommitAd2 = 0;
case(isReqTileSt)
3'h0: begin
// if(reqNeedAd!=0)
if(doReqNeedAd)
begin
nxtReqNeedAd=reqNeedAd;
// nxtReqTileSt=4;
nxtReqTileSt=2;
end
end
3'h1: begin
end
3'h2: begin
$display("IcTile2: Get2 %X", memPcData);
nxtReqTempBlk[127: 0]=memPcData[127:0];
nxtReqTempBlk[159:128]=memPcData[ 31:0];
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=0;
tMemPcOE=1;
nxtReqTileSt=0;
// nxtReqCommit=1;
nxtReqCommit=(memPcOK==UMEM_OK_OK);
nxtReqCommitAd1=isReqNeedAd;
nxtReqCommitAd2=isReqNeedAd;
end
3'h3: begin
end
3'h4: begin
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemPcOE=1;
nxtReqTileSt=5;
nxtReqTempBlk[ 31: 0]=memPcData[31:0];
nxtReqTempBlk[159:128]=memPcData[31:0];
end
3'h5: begin
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemPcOE=1;
nxtReqTileSt=6;
nxtReqTempBlk[63:32]=memPcData[31:0];
end
3'h6: begin
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemPcOE=1;
nxtReqTileSt=7;
nxtReqTempBlk[95:64]=memPcData[31:0];
end
3'h7: begin
tMemPcAddr[31:4]=isReqNeedAd;
tMemPcAddr[3:2]=isReqTileSt[1:0];
tMemPcOE=1;
nxtReqTileSt=0;
nxtReqTempBlk[127:96]=memPcData[31:0];
nxtReqCommit=1;
nxtReqCommitAd1=isReqNeedAd;
nxtReqCommitAd2=isReqNeedAd;
end
endcase
end
always @ (posedge clock)
begin
reqNeedAd <= nReqNeedAd;
isReqNeedAd <= nxtReqNeedAd;
reqTempBlk <= nxtReqTempBlk;
doReqNeedAd <= nxtDoReqNeedAd;
if(nxtReqCommit)
begin
$display("IcTile: Commit %X %X", nxtReqCommitAd1, nxtReqTempBlk);
icBlkA[nxtReqCommitAd1[7:0]] <= nxtReqTempBlk[ 31: 0];
icBlkB[nxtReqCommitAd1[7:0]] <= nxtReqTempBlk[ 63: 32];
icBlkC[nxtReqCommitAd1[7:0]] <= nxtReqTempBlk[ 95: 64];
icBlkD[nxtReqCommitAd1[7:0]] <= nxtReqTempBlk[127: 96];
icBlkE[nxtReqCommitAd2[7:0]] <= nxtReqTempBlk[159:128];
icBlkAd[nxtReqCommitAd1[7:0]] <= nxtReqCommitAd1;
end
if(memPcOK==UMEM_OK_OK)
begin
$display("IcTile: MemOK %X->%X",
isReqTileSt, nxtReqTileSt);
isReqTileSt <= nxtReqTileSt;
end
else if(memPcOK==UMEM_OK_READY)
begin
// $display("IcTile: MemReady");
case(isReqTileSt)
3'h0: begin
isReqTileSt <= nxtReqTileSt;
end
default: begin end
endcase
end
else if(memPcOK==UMEM_OK_HOLD)
begin
$display("IcTile: MemHold");
end
else if(memPcOK==UMEM_OK_FAULT)
begin
$display("IcTile: MemFault");
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1N_FUNCTIONAL_V
`define SKY130_FD_SC_LP__INPUTISO1N_FUNCTIONAL_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inputiso1n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1N_FUNCTIONAL_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:04:52 01/04/2013
// Design Name: ctrl_reg_readback
// Module Name: H:/Firmware/FONT5_base/ISE13/FONT5_base/ctrl_reg_rb_tb.v
// Project Name: FONT5_base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: ctrl_reg_readback
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ctrl_reg_rb_tb;
// Inputs
reg clk;
reg rst;
//reg [6:0] data;
reg tx_en;
reg tx_data_loaded;
// Outputs
wire tx_data_ready;
//wire [7:0] tx_data;
wire tx_complete;
wire [5:0] tx_cnt;
// Instantiate the Unit Under Test (UUT)
ctrl_reg_readback uut (
.clk(clk),
.rst(rst),
//.data(data),
.tx_en(tx_en),
.tx_data_loaded(tx_data_loaded),
.tx_data_ready(tx_data_ready),
//.tx_data(tx_data),
.tx_complete(tx_complete),
.tx_cnt(tx_cnt)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
//data = 0;
tx_en = 0;
tx_data_loaded = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rst = 1;
tx_en = 0;
#100;
rst=0;
tx_en = 1;
end
always #12.5 clk = !clk;
always @(*) begin
if (tx_data_ready) tx_data_loaded = 1;
else if (tx_data_loaded) #0 tx_data_loaded = 0;
else tx_data_loaded = tx_data_loaded;
if (tx_complete) tx_en=0;
else tx_en = tx_en;
end
endmodule
|