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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cmp_dram.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////
module cmp_dram( /*AUTOARG*/
// Inouts
DRAM0_CB, DRAM0_DQ, DRAM0_DQS, DRAM1_CB, DRAM1_DQ, DRAM1_DQS,
DRAM2_CB, DRAM2_DQ, DRAM2_DQS, DRAM3_CB, DRAM3_DQ, DRAM3_DQS,
DRAM02_SDA, DRAM13_SDA,
// Inputs
dram_gclk, cmp_grst, XXWP, XXSA, DRAM_FAIL_PART, DRAM_FAIL_OVER,
DRAM3_WE_L, DRAM3_RST_L, DRAM3_RAS_L, DRAM3_CS_L, DRAM3_CK_P,
DRAM3_CK_N, DRAM3_CKE, DRAM3_CAS_L, DRAM3_BA, DRAM3_ADDR,
DRAM2_WE_L, DRAM2_RST_L, DRAM2_RAS_L, DRAM2_CS_L, DRAM2_CK_P,
DRAM2_CK_N, DRAM2_CKE, DRAM2_CAS_L, DRAM2_BA, DRAM2_ADDR,
DRAM1_WE_L, DRAM1_RST_L, DRAM1_RAS_L, DRAM1_CS_L, DRAM1_CK_P,
DRAM1_CK_N, DRAM1_CKE, DRAM1_CAS_L, DRAM1_BA, DRAM1_ADDR,
DRAM0_WE_L, DRAM0_RST_L, DRAM0_RAS_L, DRAM0_CS_L, DRAM0_CK_P,
DRAM0_CK_N, DRAM0_CKE, DRAM0_CAS_L, DRAM0_BA, DRAM0_ADDR,
DRAM02_SCL, DRAM13_SCL
);
inout [15:0] DRAM0_CB; // To/From mem0 of ch_mem.v
inout [127:0] DRAM0_DQ; // To/From mem0 of ch_mem.v, ...
inout [35:0] DRAM0_DQS; // To/From mem0 of ch_mem.v
inout [15:0] DRAM1_CB; // To/From mem1 of ch_mem.v
inout [127:0] DRAM1_DQ; // To/From mem1 of ch_mem.v, ...
inout [35:0] DRAM1_DQS; // To/From mem1 of ch_mem.v
inout [15:0] DRAM2_CB; // To/From mem2 of ch_mem.v
inout [127:0] DRAM2_DQ; // To/From mem2 of ch_mem.v, ...
inout [35:0] DRAM2_DQS; // To/From mem2 of ch_mem.v
inout [15:0] DRAM3_CB; // To/From mem3 of ch_mem.v
inout [127:0] DRAM3_DQ; // To/From mem3 of ch_mem.v, ...
inout [35:0] DRAM3_DQS; // To/From mem3 of ch_mem.v
inout DRAM02_SDA;
inout DRAM13_SDA;
input DRAM02_SCL;
input DRAM13_SCL;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [14:0] DRAM0_ADDR; // To mem0 of ch_mem.v, ...
input [2:0] DRAM0_BA; // To mem0 of ch_mem.v, ...
input DRAM0_CAS_L; // To mem0 of ch_mem.v, ...
input DRAM0_CKE; // To mem0 of ch_mem.v, ...
input [3:0] DRAM0_CK_N; // To mem0 of ch_mem.v
input [3:0] DRAM0_CK_P; // To mem0 of ch_mem.v
input [3:0] DRAM0_CS_L; // To mem0 of ch_mem.v, ...
input DRAM0_RAS_L; // To mem0 of ch_mem.v, ...
input DRAM0_RST_L; // To mem0 of ch_mem.v, ...
input DRAM0_WE_L; // To mem0 of ch_mem.v, ...
input [14:0] DRAM1_ADDR; // To mem1 of ch_mem.v, ...
input [2:0] DRAM1_BA; // To mem1 of ch_mem.v, ...
input DRAM1_CAS_L; // To mem1 of ch_mem.v, ...
input DRAM1_CKE; // To mem1 of ch_mem.v, ...
input [3:0] DRAM1_CK_N; // To mem1 of ch_mem.v
input [3:0] DRAM1_CK_P; // To mem1 of ch_mem.v
input [3:0] DRAM1_CS_L; // To mem1 of ch_mem.v, ...
input DRAM1_RAS_L; // To mem1 of ch_mem.v, ...
input DRAM1_RST_L; // To mem1 of ch_mem.v, ...
input DRAM1_WE_L; // To mem1 of ch_mem.v, ...
input [14:0] DRAM2_ADDR; // To mem2 of ch_mem.v, ...
input [2:0] DRAM2_BA; // To mem2 of ch_mem.v, ...
input DRAM2_CAS_L; // To mem2 of ch_mem.v, ...
input DRAM2_CKE; // To mem2 of ch_mem.v, ...
input [3:0] DRAM2_CK_N; // To mem2 of ch_mem.v
input [3:0] DRAM2_CK_P; // To mem2 of ch_mem.v
input [3:0] DRAM2_CS_L; // To mem2 of ch_mem.v, ...
input DRAM2_RAS_L; // To mem2 of ch_mem.v, ...
input DRAM2_RST_L; // To mem2 of ch_mem.v, ...
input DRAM2_WE_L; // To mem2 of ch_mem.v, ...
input [14:0] DRAM3_ADDR; // To mem3 of ch_mem.v, ...
input [2:0] DRAM3_BA; // To mem3 of ch_mem.v, ...
input DRAM3_CAS_L; // To mem3 of ch_mem.v, ...
input DRAM3_CKE; // To mem3 of ch_mem.v, ...
input [3:0] DRAM3_CK_N; // To mem3 of ch_mem.v
input [3:0] DRAM3_CK_P; // To mem3 of ch_mem.v
input [3:0] DRAM3_CS_L; // To mem3 of ch_mem.v, ...
input DRAM3_RAS_L; // To mem3 of ch_mem.v, ...
input DRAM3_RST_L; // To mem3 of ch_mem.v, ...
input DRAM3_WE_L; // To mem3 of ch_mem.v, ...
input DRAM_FAIL_OVER; // To dimm_if_mon0 of dimm_if_mon.v, ...
input [5:0] DRAM_FAIL_PART; // To dimm_if_mon0 of dimm_if_mon.v, ...
input [2:0] XXSA; // To mem0 of ch_mem.v, ...
input XXWP; // To mem0 of ch_mem.v, ...
input cmp_grst; // To cmp_dram_mon of cmp_dram_mon.v
input dram_gclk; // To cmp_dram_mon of cmp_dram_mon.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire DRAM01; // To/From mem0 of ch_mem.v
wire DRAM23; // To/From mem1 of ch_mem.v
wire DRAM45; // To/From mem2 of ch_mem.v
wire DRAM67; // To/From mem3 of ch_mem.v
// End of automatics
// Local regs
wire DRAM0_ENB_ERROR;
wire DRAM1_ENB_ERROR;
wire DRAM2_ENB_ERROR;
wire DRAM3_ENB_ERROR;
wire DRAM0_FAIL_OVER;
wire DRAM1_FAIL_OVER;
wire DRAM2_FAIL_OVER;
wire DRAM3_FAIL_OVER;
wire [5:0] DRAM0_FAIL_PART;
wire [5:0] DRAM1_FAIL_PART;
wire [5:0] DRAM2_FAIL_PART;
wire [5:0] DRAM3_FAIL_PART;
integer am_id00, am_id01, am_id02, am_id03, am_id04, am_id05, am_id06;
integer am_id07, am_id08, am_id09, am_id10, am_id11, am_id12, am_id13;
integer am_id14, am_id15, am_id16, am_id17, am_id18, am_id19, am_id20;
integer am_id21, am_id22, am_id23, am_id24, am_id25, am_id26, am_id27;
integer am_id28, am_id29, am_id30, am_id31, am_id32, am_id33, am_id34;
integer am_id35;
integer bm_id00, bm_id01, bm_id02, bm_id03, bm_id04, bm_id05, bm_id06;
integer bm_id07, bm_id08, bm_id09, bm_id10, bm_id11, bm_id12, bm_id13;
integer bm_id14, bm_id15, bm_id16, bm_id17, bm_id18, bm_id19, bm_id20;
integer bm_id21, bm_id22, bm_id23, bm_id24, bm_id25, bm_id26, bm_id27;
integer bm_id28, bm_id29, bm_id30, bm_id31, bm_id32, bm_id33, bm_id34;
integer bm_id35;
integer cm_id00, cm_id01, cm_id02, cm_id03, cm_id04, cm_id05, cm_id06;
integer cm_id07, cm_id08, cm_id09, cm_id10, cm_id11, cm_id12, cm_id13;
integer cm_id14, cm_id15, cm_id16, cm_id17, cm_id18, cm_id19, cm_id20;
integer cm_id21, cm_id22, cm_id23, cm_id24, cm_id25, cm_id26, cm_id27;
integer cm_id28, cm_id29, cm_id30, cm_id31, cm_id32, cm_id33, cm_id34;
integer cm_id35;
integer dm_id00, dm_id01, dm_id02, dm_id03, dm_id04, dm_id05, dm_id06;
integer dm_id07, dm_id08, dm_id09, dm_id10, dm_id11, dm_id12, dm_id13;
integer dm_id14, dm_id15, dm_id16, dm_id17, dm_id18, dm_id19, dm_id20;
integer dm_id21, dm_id22, dm_id23, dm_id24, dm_id25, dm_id26, dm_id27;
integer dm_id28, dm_id29, dm_id30, dm_id31, dm_id32, dm_id33, dm_id34;
integer dm_id35;
integer sam_id00, sam_id01, sam_id02, sam_id03, sam_id04, sam_id05, sam_id06;
integer sam_id07, sam_id08, sam_id09, sam_id10, sam_id11, sam_id12, sam_id13;
integer sam_id14, sam_id15, sam_id16, sam_id17, sam_id18, sam_id19, sam_id20;
integer sam_id21, sam_id22, sam_id23, sam_id24, sam_id25, sam_id26, sam_id27;
integer sam_id28, sam_id29, sam_id30, sam_id31, sam_id32, sam_id33, sam_id34;
integer sam_id35;
integer sbm_id00, sbm_id01, sbm_id02, sbm_id03, sbm_id04, sbm_id05, sbm_id06;
integer sbm_id07, sbm_id08, sbm_id09, sbm_id10, sbm_id11, sbm_id12, sbm_id13;
integer sbm_id14, sbm_id15, sbm_id16, sbm_id17, sbm_id18, sbm_id19, sbm_id20;
integer sbm_id21, sbm_id22, sbm_id23, sbm_id24, sbm_id25, sbm_id26, sbm_id27;
integer sbm_id28, sbm_id29, sbm_id30, sbm_id31, sbm_id32, sbm_id33, sbm_id34;
integer sbm_id35;
integer scm_id00, scm_id01, scm_id02, scm_id03, scm_id04, scm_id05, scm_id06;
integer scm_id07, scm_id08, scm_id09, scm_id10, scm_id11, scm_id12, scm_id13;
integer scm_id14, scm_id15, scm_id16, scm_id17, scm_id18, scm_id19, scm_id20;
integer scm_id21, scm_id22, scm_id23, scm_id24, scm_id25, scm_id26, scm_id27;
integer scm_id28, scm_id29, scm_id30, scm_id31, scm_id32, scm_id33, scm_id34;
integer scm_id35;
integer sdm_id00, sdm_id01, sdm_id02, sdm_id03, sdm_id04, sdm_id05, sdm_id06;
integer sdm_id07, sdm_id08, sdm_id09, sdm_id10, sdm_id11, sdm_id12, sdm_id13;
integer sdm_id14, sdm_id15, sdm_id16, sdm_id17, sdm_id18, sdm_id19, sdm_id20;
integer sdm_id21, sdm_id22, sdm_id23, sdm_id24, sdm_id25, sdm_id26, sdm_id27;
integer sdm_id28, sdm_id29, sdm_id30, sdm_id31, sdm_id32, sdm_id33, sdm_id34;
integer sdm_id35;
integer ram_id00, ram_id01, ram_id02, ram_id03, ram_id04, ram_id05, ram_id06;
integer ram_id07, ram_id08, ram_id09, ram_id10, ram_id11, ram_id12, ram_id13;
integer ram_id14, ram_id15, ram_id16, ram_id17, ram_id18, ram_id19, ram_id20;
integer ram_id21, ram_id22, ram_id23, ram_id24, ram_id25, ram_id26, ram_id27;
integer ram_id28, ram_id29, ram_id30, ram_id31, ram_id32, ram_id33, ram_id34;
integer ram_id35;
integer rbm_id00, rbm_id01, rbm_id02, rbm_id03, rbm_id04, rbm_id05, rbm_id06;
integer rbm_id07, rbm_id08, rbm_id09, rbm_id10, rbm_id11, rbm_id12, rbm_id13;
integer rbm_id14, rbm_id15, rbm_id16, rbm_id17, rbm_id18, rbm_id19, rbm_id20;
integer rbm_id21, rbm_id22, rbm_id23, rbm_id24, rbm_id25, rbm_id26, rbm_id27;
integer rbm_id28, rbm_id29, rbm_id30, rbm_id31, rbm_id32, rbm_id33, rbm_id34;
integer rbm_id35;
integer rcm_id00, rcm_id01, rcm_id02, rcm_id03, rcm_id04, rcm_id05, rcm_id06;
integer rcm_id07, rcm_id08, rcm_id09, rcm_id10, rcm_id11, rcm_id12, rcm_id13;
integer rcm_id14, rcm_id15, rcm_id16, rcm_id17, rcm_id18, rcm_id19, rcm_id20;
integer rcm_id21, rcm_id22, rcm_id23, rcm_id24, rcm_id25, rcm_id26, rcm_id27;
integer rcm_id28, rcm_id29, rcm_id30, rcm_id31, rcm_id32, rcm_id33, rcm_id34;
integer rcm_id35;
integer rdm_id00, rdm_id01, rdm_id02, rdm_id03, rdm_id04, rdm_id05, rdm_id06;
integer rdm_id07, rdm_id08, rdm_id09, rdm_id10, rdm_id11, rdm_id12, rdm_id13;
integer rdm_id14, rdm_id15, rdm_id16, rdm_id17, rdm_id18, rdm_id19, rdm_id20;
integer rdm_id21, rdm_id22, rdm_id23, rdm_id24, rdm_id25, rdm_id26, rdm_id27;
integer rdm_id28, rdm_id29, rdm_id30, rdm_id31, rdm_id32, rdm_id33, rdm_id34;
integer rdm_id35;
integer rsam_id00, rsam_id01, rsam_id02, rsam_id03, rsam_id04, rsam_id05, rsam_id06;
integer rsam_id07, rsam_id08, rsam_id09, rsam_id10, rsam_id11, rsam_id12, rsam_id13;
integer rsam_id14, rsam_id15, rsam_id16, rsam_id17, rsam_id18, rsam_id19, rsam_id20;
integer rsam_id21, rsam_id22, rsam_id23, rsam_id24, rsam_id25, rsam_id26, rsam_id27;
integer rsam_id28, rsam_id29, rsam_id30, rsam_id31, rsam_id32, rsam_id33, rsam_id34;
integer rsam_id35;
integer rsbm_id00, rsbm_id01, rsbm_id02, rsbm_id03, rsbm_id04, rsbm_id05, rsbm_id06;
integer rsbm_id07, rsbm_id08, rsbm_id09, rsbm_id10, rsbm_id11, rsbm_id12, rsbm_id13;
integer rsbm_id14, rsbm_id15, rsbm_id16, rsbm_id17, rsbm_id18, rsbm_id19, rsbm_id20;
integer rsbm_id21, rsbm_id22, rsbm_id23, rsbm_id24, rsbm_id25, rsbm_id26, rsbm_id27;
integer rsbm_id28, rsbm_id29, rsbm_id30, rsbm_id31, rsbm_id32, rsbm_id33, rsbm_id34;
integer rsbm_id35;
integer rscm_id00, rscm_id01, rscm_id02, rscm_id03, rscm_id04, rscm_id05, rscm_id06;
integer rscm_id07, rscm_id08, rscm_id09, rscm_id10, rscm_id11, rscm_id12, rscm_id13;
integer rscm_id14, rscm_id15, rscm_id16, rscm_id17, rscm_id18, rscm_id19, rscm_id20;
integer rscm_id21, rscm_id22, rscm_id23, rscm_id24, rscm_id25, rscm_id26, rscm_id27;
integer rscm_id28, rscm_id29, rscm_id30, rscm_id31, rscm_id32, rscm_id33, rscm_id34;
integer rscm_id35;
integer rsdm_id00, rsdm_id01, rsdm_id02, rsdm_id03, rsdm_id04, rsdm_id05, rsdm_id06;
integer rsdm_id07, rsdm_id08, rsdm_id09, rsdm_id10, rsdm_id11, rsdm_id12, rsdm_id13;
integer rsdm_id14, rsdm_id15, rsdm_id16, rsdm_id17, rsdm_id18, rsdm_id19, rsdm_id20;
integer rsdm_id21, rsdm_id22, rsdm_id23, rsdm_id24, rsdm_id25, rsdm_id26, rsdm_id27;
integer rsdm_id28, rsdm_id29, rsdm_id30, rsdm_id31, rsdm_id32, rsdm_id33, rsdm_id34;
integer rsdm_id35;
integer avid0, avid1, avid2, avid3, avid4;
integer bvid0, bvid1, bvid2, bvid3, bvid4;
integer cvid0, cvid1, cvid2, cvid3, cvid4;
integer dvid0, dvid1, dvid2, dvid3, dvid4;
integer savid0, savid1, savid2, savid3, savid4;
integer sbvid0, sbvid1, sbvid2, sbvid3, sbvid4;
integer scvid0, scvid1, scvid2, scvid3, scvid4;
integer sdvid0, sdvid1, sdvid2, sdvid3, sdvid4;
integer ravid0, ravid1, ravid2, ravid3, ravid4;
integer rbvid0, rbvid1, rbvid2, rbvid3, rbvid4;
integer rcvid0, rcvid1, rcvid2, rcvid3, rcvid4;
integer rdvid0, rdvid1, rdvid2, rdvid3, rdvid4;
integer rsavid0, rsavid1, rsavid2, rsavid3, rsavid4;
integer rsbvid0, rsbvid1, rsbvid2, rsbvid3, rsbvid4;
integer rscvid0, rscvid1, rscvid2, rscvid3, rscvid4;
integer rsdvid0, rsdvid1, rsdvid2, rsdvid3, rsdvid4;
integer vid5, vid6;
integer svid5, svid6;
integer rvid5, rvid6;
integer rsvid5, rsvid6;
integer success;
reg [3:0] cas_latency;
`ifdef DENALI_ON
initial begin
/////////////////////////////////////////
// Create Denali System Memory
/////////////////////////
// RANK 0, Stack 0
// Channel 0
#10 // wait for mem.image.
am_id00 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U00");
am_id01 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U01");
am_id02 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U02");
am_id03 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U03");
am_id04 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U04");
am_id05 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U05");
am_id06 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U06");
am_id07 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U07");
am_id08 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U08");
am_id09 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U09");
am_id10 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U10");
am_id11 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U11");
am_id12 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U12");
am_id13 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U13");
am_id14 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U14");
am_id15 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U15");
am_id16 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U16");
am_id17 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U17");
am_id18 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U00");
am_id19 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U01");
am_id20 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U02");
am_id21 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U03");
am_id22 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U04");
am_id23 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U05");
am_id24 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U06");
am_id25 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U07");
am_id26 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U08");
am_id27 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U09");
am_id28 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U10");
am_id29 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U11");
am_id30 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U12");
am_id31 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U13");
am_id32 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U14");
am_id33 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U15");
am_id34 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U16");
am_id35 = $mminstanceid("cmp_top.cmp_dram.mem0.dimm1.U17");
// Channel 1
bm_id00 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U00");
bm_id01 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U01");
bm_id02 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U02");
bm_id03 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U03");
bm_id04 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U04");
bm_id05 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U05");
bm_id06 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U06");
bm_id07 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U07");
bm_id08 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U08");
bm_id09 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U09");
bm_id10 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U10");
bm_id11 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U11");
bm_id12 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U12");
bm_id13 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U13");
bm_id14 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U14");
bm_id15 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U15");
bm_id16 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U16");
bm_id17 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U17");
bm_id18 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U00");
bm_id19 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U01");
bm_id20 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U02");
bm_id21 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U03");
bm_id22 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U04");
bm_id23 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U05");
bm_id24 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U06");
bm_id25 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U07");
bm_id26 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U08");
bm_id27 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U09");
bm_id28 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U10");
bm_id29 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U11");
bm_id30 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U12");
bm_id31 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U13");
bm_id32 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U14");
bm_id33 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U15");
bm_id34 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U16");
bm_id35 = $mminstanceid("cmp_top.cmp_dram.mem1.dimm1.U17");
// Channe 2
cm_id00 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U00");
cm_id01 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U01");
cm_id02 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U02");
cm_id03 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U03");
cm_id04 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U04");
cm_id05 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U05");
cm_id06 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U06");
cm_id07 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U07");
cm_id08 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U08");
cm_id09 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U09");
cm_id10 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U10");
cm_id11 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U11");
cm_id12 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U12");
cm_id13 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U13");
cm_id14 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U14");
cm_id15 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U15");
cm_id16 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U16");
cm_id17 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U17");
cm_id18 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U00");
cm_id19 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U01");
cm_id20 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U02");
cm_id21 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U03");
cm_id22 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U04");
cm_id23 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U05");
cm_id24 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U06");
cm_id25 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U07");
cm_id26 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U08");
cm_id27 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U09");
cm_id28 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U10");
cm_id29 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U11");
cm_id30 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U12");
cm_id31 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U13");
cm_id32 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U14");
cm_id33 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U15");
cm_id34 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U16");
cm_id35 = $mminstanceid("cmp_top.cmp_dram.mem2.dimm1.U17");
// channel 3
dm_id00 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U00");
dm_id01 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U01");
dm_id02 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U02");
dm_id03 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U03");
dm_id04 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U04");
dm_id05 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U05");
dm_id06 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U06");
dm_id07 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U07");
dm_id08 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U08");
dm_id09 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U09");
dm_id10 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U10");
dm_id11 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U11");
dm_id12 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U12");
dm_id13 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U13");
dm_id14 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U14");
dm_id15 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U15");
dm_id16 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U16");
dm_id17 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U17");
dm_id18 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U00");
dm_id19 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U01");
dm_id20 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U02");
dm_id21 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U03");
dm_id22 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U04");
dm_id23 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U05");
dm_id24 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U06");
dm_id25 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U07");
dm_id26 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U08");
dm_id27 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U09");
dm_id28 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U10");
dm_id29 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U11");
dm_id30 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U12");
dm_id31 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U13");
dm_id32 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U14");
dm_id33 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U15");
dm_id34 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U16");
dm_id35 = $mminstanceid("cmp_top.cmp_dram.mem3.dimm1.U17");
//////////////////////////////////////
//workaround: for nested width problem
// Channel 0
avid4 = $mmcreatesysmem("sysmem","a_dimm144",36,1,1);
success=$mmaddtosysmem(avid4,am_id13,0,0,0);
success=$mmaddtosysmem(avid4,am_id04,1,0,0);
success=$mmaddtosysmem(avid4,am_id31,2,0,0);
success=$mmaddtosysmem(avid4,am_id22,3,0,0);
success=$mmaddtosysmem(avid4,am_id17,4,0,0);
success=$mmaddtosysmem(avid4,am_id16,5,0,0);
success=$mmaddtosysmem(avid4,am_id15,6,0,0);
success=$mmaddtosysmem(avid4,am_id14,7,0,0);
success=$mmaddtosysmem(avid4,am_id12,8,0,0);
success=$mmaddtosysmem(avid4,am_id11,9,0,0);
success=$mmaddtosysmem(avid4,am_id10,10,0,0);
success=$mmaddtosysmem(avid4,am_id09,11,0,0);
success=$mmaddtosysmem(avid4,am_id08,12,0,0);
success=$mmaddtosysmem(avid4,am_id07,13,0,0);
success=$mmaddtosysmem(avid4,am_id06,14,0,0);
success=$mmaddtosysmem(avid4,am_id05,15,0,0);
success=$mmaddtosysmem(avid4,am_id03,16,0,0);
success=$mmaddtosysmem(avid4,am_id02,17,0,0);
success=$mmaddtosysmem(avid4,am_id01,18,0,0);
success=$mmaddtosysmem(avid4,am_id00,19,0,0);
success=$mmaddtosysmem(avid4,am_id35,20,0,0);
success=$mmaddtosysmem(avid4,am_id34,21,0,0);
success=$mmaddtosysmem(avid4,am_id33,22,0,0);
success=$mmaddtosysmem(avid4,am_id32,23,0,0);
success=$mmaddtosysmem(avid4,am_id30,24,0,0);
success=$mmaddtosysmem(avid4,am_id29,25,0,0);
success=$mmaddtosysmem(avid4,am_id28,26,0,0);
success=$mmaddtosysmem(avid4,am_id27,27,0,0);
success=$mmaddtosysmem(avid4,am_id26,28,0,0);
success=$mmaddtosysmem(avid4,am_id25,29,0,0);
success=$mmaddtosysmem(avid4,am_id24,30,0,0);
success=$mmaddtosysmem(avid4,am_id23,31,0,0);
success=$mmaddtosysmem(avid4,am_id21,32,0,0);
success=$mmaddtosysmem(avid4,am_id20,33,0,0);
success=$mmaddtosysmem(avid4,am_id19,34,0,0);
success=$mmaddtosysmem(avid4,am_id18,35,0,0);
// Channel 1
bvid4 = $mmcreatesysmem("sysmem","b_dimm144",36,1,1);
success=$mmaddtosysmem(bvid4,bm_id13,0,0,0);
success=$mmaddtosysmem(bvid4,bm_id04,1,0,0);
success=$mmaddtosysmem(bvid4,bm_id31,2,0,0);
success=$mmaddtosysmem(bvid4,bm_id22,3,0,0);
success=$mmaddtosysmem(bvid4,bm_id17,4,0,0);
success=$mmaddtosysmem(bvid4,bm_id16,5,0,0);
success=$mmaddtosysmem(bvid4,bm_id15,6,0,0);
success=$mmaddtosysmem(bvid4,bm_id14,7,0,0);
success=$mmaddtosysmem(bvid4,bm_id12,8,0,0);
success=$mmaddtosysmem(bvid4,bm_id11,9,0,0);
success=$mmaddtosysmem(bvid4,bm_id10,10,0,0);
success=$mmaddtosysmem(bvid4,bm_id09,11,0,0);
success=$mmaddtosysmem(bvid4,bm_id08,12,0,0);
success=$mmaddtosysmem(bvid4,bm_id07,13,0,0);
success=$mmaddtosysmem(bvid4,bm_id06,14,0,0);
success=$mmaddtosysmem(bvid4,bm_id05,15,0,0);
success=$mmaddtosysmem(bvid4,bm_id03,16,0,0);
success=$mmaddtosysmem(bvid4,bm_id02,17,0,0);
success=$mmaddtosysmem(bvid4,bm_id01,18,0,0);
success=$mmaddtosysmem(bvid4,bm_id00,19,0,0);
success=$mmaddtosysmem(bvid4,bm_id35,20,0,0);
success=$mmaddtosysmem(bvid4,bm_id34,21,0,0);
success=$mmaddtosysmem(bvid4,bm_id33,22,0,0);
success=$mmaddtosysmem(bvid4,bm_id32,23,0,0);
success=$mmaddtosysmem(bvid4,bm_id30,24,0,0);
success=$mmaddtosysmem(bvid4,bm_id29,25,0,0);
success=$mmaddtosysmem(bvid4,bm_id28,26,0,0);
success=$mmaddtosysmem(bvid4,bm_id27,27,0,0);
success=$mmaddtosysmem(bvid4,bm_id26,28,0,0);
success=$mmaddtosysmem(bvid4,bm_id25,29,0,0);
success=$mmaddtosysmem(bvid4,bm_id24,30,0,0);
success=$mmaddtosysmem(bvid4,bm_id23,31,0,0);
success=$mmaddtosysmem(bvid4,bm_id21,32,0,0);
success=$mmaddtosysmem(bvid4,bm_id20,33,0,0);
success=$mmaddtosysmem(bvid4,bm_id19,34,0,0);
success=$mmaddtosysmem(bvid4,bm_id18,35,0,0);
// Channel 2
cvid4 = $mmcreatesysmem("sysmem","c_dimm144",36,1,1);
success=$mmaddtosysmem(cvid4,cm_id13,0,0,0);
success=$mmaddtosysmem(cvid4,cm_id04,1,0,0);
success=$mmaddtosysmem(cvid4,cm_id31,2,0,0);
success=$mmaddtosysmem(cvid4,cm_id22,3,0,0);
success=$mmaddtosysmem(cvid4,cm_id17,4,0,0);
success=$mmaddtosysmem(cvid4,cm_id16,5,0,0);
success=$mmaddtosysmem(cvid4,cm_id15,6,0,0);
success=$mmaddtosysmem(cvid4,cm_id14,7,0,0);
success=$mmaddtosysmem(cvid4,cm_id12,8,0,0);
success=$mmaddtosysmem(cvid4,cm_id11,9,0,0);
success=$mmaddtosysmem(cvid4,cm_id10,10,0,0);
success=$mmaddtosysmem(cvid4,cm_id09,11,0,0);
success=$mmaddtosysmem(cvid4,cm_id08,12,0,0);
success=$mmaddtosysmem(cvid4,cm_id07,13,0,0);
success=$mmaddtosysmem(cvid4,cm_id06,14,0,0);
success=$mmaddtosysmem(cvid4,cm_id05,15,0,0);
success=$mmaddtosysmem(cvid4,cm_id03,16,0,0);
success=$mmaddtosysmem(cvid4,cm_id02,17,0,0);
success=$mmaddtosysmem(cvid4,cm_id01,18,0,0);
success=$mmaddtosysmem(cvid4,cm_id00,19,0,0);
success=$mmaddtosysmem(cvid4,cm_id35,20,0,0);
success=$mmaddtosysmem(cvid4,cm_id34,21,0,0);
success=$mmaddtosysmem(cvid4,cm_id33,22,0,0);
success=$mmaddtosysmem(cvid4,cm_id32,23,0,0);
success=$mmaddtosysmem(cvid4,cm_id30,24,0,0);
success=$mmaddtosysmem(cvid4,cm_id29,25,0,0);
success=$mmaddtosysmem(cvid4,cm_id28,26,0,0);
success=$mmaddtosysmem(cvid4,cm_id27,27,0,0);
success=$mmaddtosysmem(cvid4,cm_id26,28,0,0);
success=$mmaddtosysmem(cvid4,cm_id25,29,0,0);
success=$mmaddtosysmem(cvid4,cm_id24,30,0,0);
success=$mmaddtosysmem(cvid4,cm_id23,31,0,0);
success=$mmaddtosysmem(cvid4,cm_id21,32,0,0);
success=$mmaddtosysmem(cvid4,cm_id20,33,0,0);
success=$mmaddtosysmem(cvid4,cm_id19,34,0,0);
success=$mmaddtosysmem(cvid4,cm_id18,35,0,0);
// Channel 3
dvid4 = $mmcreatesysmem("sysmem","d_dimm144",36,1,1);
success=$mmaddtosysmem(dvid4,dm_id13,0,0,0);
success=$mmaddtosysmem(dvid4,dm_id04,1,0,0);
success=$mmaddtosysmem(dvid4,dm_id31,2,0,0);
success=$mmaddtosysmem(dvid4,dm_id22,3,0,0);
success=$mmaddtosysmem(dvid4,dm_id17,4,0,0);
success=$mmaddtosysmem(dvid4,dm_id16,5,0,0);
success=$mmaddtosysmem(dvid4,dm_id15,6,0,0);
success=$mmaddtosysmem(dvid4,dm_id14,7,0,0);
success=$mmaddtosysmem(dvid4,dm_id12,8,0,0);
success=$mmaddtosysmem(dvid4,dm_id11,9,0,0);
success=$mmaddtosysmem(dvid4,dm_id10,10,0,0);
success=$mmaddtosysmem(dvid4,dm_id09,11,0,0);
success=$mmaddtosysmem(dvid4,dm_id08,12,0,0);
success=$mmaddtosysmem(dvid4,dm_id07,13,0,0);
success=$mmaddtosysmem(dvid4,dm_id06,14,0,0);
success=$mmaddtosysmem(dvid4,dm_id05,15,0,0);
success=$mmaddtosysmem(dvid4,dm_id03,16,0,0);
success=$mmaddtosysmem(dvid4,dm_id02,17,0,0);
success=$mmaddtosysmem(dvid4,dm_id01,18,0,0);
success=$mmaddtosysmem(dvid4,dm_id00,19,0,0);
success=$mmaddtosysmem(dvid4,dm_id35,20,0,0);
success=$mmaddtosysmem(dvid4,dm_id34,21,0,0);
success=$mmaddtosysmem(dvid4,dm_id33,22,0,0);
success=$mmaddtosysmem(dvid4,dm_id32,23,0,0);
success=$mmaddtosysmem(dvid4,dm_id30,24,0,0);
success=$mmaddtosysmem(dvid4,dm_id29,25,0,0);
success=$mmaddtosysmem(dvid4,dm_id28,26,0,0);
success=$mmaddtosysmem(dvid4,dm_id27,27,0,0);
success=$mmaddtosysmem(dvid4,dm_id26,28,0,0);
success=$mmaddtosysmem(dvid4,dm_id25,29,0,0);
success=$mmaddtosysmem(dvid4,dm_id24,30,0,0);
success=$mmaddtosysmem(dvid4,dm_id23,31,0,0);
success=$mmaddtosysmem(dvid4,dm_id21,32,0,0);
success=$mmaddtosysmem(dvid4,dm_id20,33,0,0);
success=$mmaddtosysmem(dvid4,dm_id19,34,0,0);
success=$mmaddtosysmem(dvid4,dm_id18,35,0,0);
`ifdef STACK_DIMM
//////////////////////
// RANK 0, STACK 1
// Channel 0
sam_id00 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U00");
sam_id01 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U01");
sam_id02 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U02");
sam_id03 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U03");
sam_id04 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U04");
sam_id05 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U05");
sam_id06 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U06");
sam_id07 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U07");
sam_id08 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U08");
sam_id09 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U09");
sam_id10 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U10");
sam_id11 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U11");
sam_id12 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U12");
sam_id13 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U13");
sam_id14 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U14");
sam_id15 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U15");
sam_id16 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U16");
sam_id17 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms0.U17");
sam_id18 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U00");
sam_id19 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U01");
sam_id20 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U02");
sam_id21 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U03");
sam_id22 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U04");
sam_id23 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U05");
sam_id24 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U06");
sam_id25 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U07");
sam_id26 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U08");
sam_id27 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U09");
sam_id28 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U10");
sam_id29 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U11");
sam_id30 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U12");
sam_id31 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U13");
sam_id32 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U14");
sam_id33 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U15");
sam_id34 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U16");
sam_id35 = $mminstanceid("cmp_top.cmp_dram.mem0.dimms1.U17");
// Channel 1
sbm_id00 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U00");
sbm_id01 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U01");
sbm_id02 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U02");
sbm_id03 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U03");
sbm_id04 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U04");
sbm_id05 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U05");
sbm_id06 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U06");
sbm_id07 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U07");
sbm_id08 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U08");
sbm_id09 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U09");
sbm_id10 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U10");
sbm_id11 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U11");
sbm_id12 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U12");
sbm_id13 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U13");
sbm_id14 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U14");
sbm_id15 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U15");
sbm_id16 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U16");
sbm_id17 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms0.U17");
sbm_id18 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U00");
sbm_id19 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U01");
sbm_id20 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U02");
sbm_id21 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U03");
sbm_id22 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U04");
sbm_id23 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U05");
sbm_id24 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U06");
sbm_id25 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U07");
sbm_id26 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U08");
sbm_id27 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U09");
sbm_id28 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U10");
sbm_id29 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U11");
sbm_id30 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U12");
sbm_id31 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U13");
sbm_id32 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U14");
sbm_id33 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U15");
sbm_id34 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U16");
sbm_id35 = $mminstanceid("cmp_top.cmp_dram.mem1.dimms1.U17");
// Channel 2
scm_id00 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U00");
scm_id01 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U01");
scm_id02 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U02");
scm_id03 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U03");
scm_id04 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U04");
scm_id05 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U05");
scm_id06 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U06");
scm_id07 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U07");
scm_id08 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U08");
scm_id09 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U09");
scm_id10 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U10");
scm_id11 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U11");
scm_id12 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U12");
scm_id13 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U13");
scm_id14 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U14");
scm_id15 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U15");
scm_id16 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U16");
scm_id17 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms0.U17");
scm_id18 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U00");
scm_id19 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U01");
scm_id20 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U02");
scm_id21 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U03");
scm_id22 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U04");
scm_id23 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U05");
scm_id24 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U06");
scm_id25 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U07");
scm_id26 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U08");
scm_id27 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U09");
scm_id28 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U10");
scm_id29 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U11");
scm_id30 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U12");
scm_id31 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U13");
scm_id32 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U14");
scm_id33 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U15");
scm_id34 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U16");
scm_id35 = $mminstanceid("cmp_top.cmp_dram.mem2.dimms1.U17");
// Channel 3
sdm_id00 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U00");
sdm_id01 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U01");
sdm_id02 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U02");
sdm_id03 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U03");
sdm_id04 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U04");
sdm_id05 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U05");
sdm_id06 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U06");
sdm_id07 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U07");
sdm_id08 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U08");
sdm_id09 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U09");
sdm_id10 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U10");
sdm_id11 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U11");
sdm_id12 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U12");
sdm_id13 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U13");
sdm_id14 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U14");
sdm_id15 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U15");
sdm_id16 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U16");
sdm_id17 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms0.U17");
sdm_id18 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U00");
sdm_id19 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U01");
sdm_id20 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U02");
sdm_id21 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U03");
sdm_id22 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U04");
sdm_id23 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U05");
sdm_id24 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U06");
sdm_id25 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U07");
sdm_id26 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U08");
sdm_id27 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U09");
sdm_id28 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U10");
sdm_id29 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U11");
sdm_id30 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U12");
sdm_id31 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U13");
sdm_id32 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U14");
sdm_id33 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U15");
sdm_id34 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U16");
sdm_id35 = $mminstanceid("cmp_top.cmp_dram.mem3.dimms1.U17");
//////////////////////////////////////
//workaround: for nested width problem
// Channel 0
savid4 = $mmcreatesysmem("sysmem","sa_dimm144",36,1,1);
success=$mmaddtosysmem(savid4,sam_id13,0,0,0);
success=$mmaddtosysmem(savid4,sam_id04,1,0,0);
success=$mmaddtosysmem(savid4,sam_id31,2,0,0);
success=$mmaddtosysmem(savid4,sam_id22,3,0,0);
success=$mmaddtosysmem(savid4,sam_id17,4,0,0);
success=$mmaddtosysmem(savid4,sam_id16,5,0,0);
success=$mmaddtosysmem(savid4,sam_id15,6,0,0);
success=$mmaddtosysmem(savid4,sam_id14,7,0,0);
success=$mmaddtosysmem(savid4,sam_id12,8,0,0);
success=$mmaddtosysmem(savid4,sam_id11,9,0,0);
success=$mmaddtosysmem(savid4,sam_id10,10,0,0);
success=$mmaddtosysmem(savid4,sam_id09,11,0,0);
success=$mmaddtosysmem(savid4,sam_id08,12,0,0);
success=$mmaddtosysmem(savid4,sam_id07,13,0,0);
success=$mmaddtosysmem(savid4,sam_id06,14,0,0);
success=$mmaddtosysmem(savid4,sam_id05,15,0,0);
success=$mmaddtosysmem(savid4,sam_id03,16,0,0);
success=$mmaddtosysmem(savid4,sam_id02,17,0,0);
success=$mmaddtosysmem(savid4,sam_id01,18,0,0);
success=$mmaddtosysmem(savid4,sam_id00,19,0,0);
success=$mmaddtosysmem(savid4,sam_id35,20,0,0);
success=$mmaddtosysmem(savid4,sam_id34,21,0,0);
success=$mmaddtosysmem(savid4,sam_id33,22,0,0);
success=$mmaddtosysmem(savid4,sam_id32,23,0,0);
success=$mmaddtosysmem(savid4,sam_id30,24,0,0);
success=$mmaddtosysmem(savid4,sam_id29,25,0,0);
success=$mmaddtosysmem(savid4,sam_id28,26,0,0);
success=$mmaddtosysmem(savid4,sam_id27,27,0,0);
success=$mmaddtosysmem(savid4,sam_id26,28,0,0);
success=$mmaddtosysmem(savid4,sam_id25,29,0,0);
success=$mmaddtosysmem(savid4,sam_id24,30,0,0);
success=$mmaddtosysmem(savid4,sam_id23,31,0,0);
success=$mmaddtosysmem(savid4,sam_id21,32,0,0);
success=$mmaddtosysmem(savid4,sam_id20,33,0,0);
success=$mmaddtosysmem(savid4,sam_id19,34,0,0);
success=$mmaddtosysmem(savid4,sam_id18,35,0,0);
// Channel 1
sbvid4 = $mmcreatesysmem("sysmem","sb_dimm144",36,1,1);
success=$mmaddtosysmem(sbvid4,sbm_id13,0,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id04,1,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id31,2,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id22,3,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id17,4,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id16,5,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id15,6,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id14,7,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id12,8,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id11,9,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id10,10,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id09,11,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id08,12,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id07,13,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id06,14,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id05,15,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id03,16,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id02,17,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id01,18,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id00,19,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id35,20,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id34,21,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id33,22,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id32,23,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id30,24,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id29,25,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id28,26,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id27,27,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id26,28,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id25,29,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id24,30,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id23,31,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id21,32,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id20,33,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id19,34,0,0);
success=$mmaddtosysmem(sbvid4,sbm_id18,35,0,0);
// Channel 2
scvid4 = $mmcreatesysmem("sysmem","sc_dimm144",36,1,1);
success=$mmaddtosysmem(scvid4,scm_id13,0,0,0);
success=$mmaddtosysmem(scvid4,scm_id04,1,0,0);
success=$mmaddtosysmem(scvid4,scm_id31,2,0,0);
success=$mmaddtosysmem(scvid4,scm_id22,3,0,0);
success=$mmaddtosysmem(scvid4,scm_id17,4,0,0);
success=$mmaddtosysmem(scvid4,scm_id16,5,0,0);
success=$mmaddtosysmem(scvid4,scm_id15,6,0,0);
success=$mmaddtosysmem(scvid4,scm_id14,7,0,0);
success=$mmaddtosysmem(scvid4,scm_id12,8,0,0);
success=$mmaddtosysmem(scvid4,scm_id11,9,0,0);
success=$mmaddtosysmem(scvid4,scm_id10,10,0,0);
success=$mmaddtosysmem(scvid4,scm_id09,11,0,0);
success=$mmaddtosysmem(scvid4,scm_id08,12,0,0);
success=$mmaddtosysmem(scvid4,scm_id07,13,0,0);
success=$mmaddtosysmem(scvid4,scm_id06,14,0,0);
success=$mmaddtosysmem(scvid4,scm_id05,15,0,0);
success=$mmaddtosysmem(scvid4,scm_id03,16,0,0);
success=$mmaddtosysmem(scvid4,scm_id02,17,0,0);
success=$mmaddtosysmem(scvid4,scm_id01,18,0,0);
success=$mmaddtosysmem(scvid4,scm_id00,19,0,0);
success=$mmaddtosysmem(scvid4,scm_id35,20,0,0);
success=$mmaddtosysmem(scvid4,scm_id34,21,0,0);
success=$mmaddtosysmem(scvid4,scm_id33,22,0,0);
success=$mmaddtosysmem(scvid4,scm_id32,23,0,0);
success=$mmaddtosysmem(scvid4,scm_id30,24,0,0);
success=$mmaddtosysmem(scvid4,scm_id29,25,0,0);
success=$mmaddtosysmem(scvid4,scm_id28,26,0,0);
success=$mmaddtosysmem(scvid4,scm_id27,27,0,0);
success=$mmaddtosysmem(scvid4,scm_id26,28,0,0);
success=$mmaddtosysmem(scvid4,scm_id25,29,0,0);
success=$mmaddtosysmem(scvid4,scm_id24,30,0,0);
success=$mmaddtosysmem(scvid4,scm_id23,31,0,0);
success=$mmaddtosysmem(scvid4,scm_id21,32,0,0);
success=$mmaddtosysmem(scvid4,scm_id20,33,0,0);
success=$mmaddtosysmem(scvid4,scm_id19,34,0,0);
success=$mmaddtosysmem(scvid4,scm_id18,35,0,0);
// Channel 3
sdvid4 = $mmcreatesysmem("sysmem","sd_dimm144",36,1,1);
success=$mmaddtosysmem(sdvid4,sdm_id13,0,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id04,1,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id31,2,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id22,3,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id17,4,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id16,5,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id15,6,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id14,7,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id12,8,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id11,9,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id10,10,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id09,11,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id08,12,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id07,13,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id06,14,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id05,15,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id03,16,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id02,17,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id01,18,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id00,19,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id35,20,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id34,21,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id33,22,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id32,23,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id30,24,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id29,25,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id28,26,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id27,27,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id26,28,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id25,29,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id24,30,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id23,31,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id21,32,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id20,33,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id19,34,0,0);
success=$mmaddtosysmem(sdvid4,sdm_id18,35,0,0);
`endif
`ifdef RANK_DIMM
/////////////////////////
// RANK 1, Stack 0
// Channel 0
ram_id00 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U00");
ram_id01 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U01");
ram_id02 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U02");
ram_id03 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U03");
ram_id04 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U04");
ram_id05 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U05");
ram_id06 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U06");
ram_id07 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U07");
ram_id08 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U08");
ram_id09 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U09");
ram_id10 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U10");
ram_id11 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U11");
ram_id12 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U12");
ram_id13 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U13");
ram_id14 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U14");
ram_id15 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U15");
ram_id16 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U16");
ram_id17 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr0.U17");
ram_id18 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U00");
ram_id19 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U01");
ram_id20 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U02");
ram_id21 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U03");
ram_id22 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U04");
ram_id23 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U05");
ram_id24 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U06");
ram_id25 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U07");
ram_id26 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U08");
ram_id27 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U09");
ram_id28 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U10");
ram_id29 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U11");
ram_id30 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U12");
ram_id31 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U13");
ram_id32 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U14");
ram_id33 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U15");
ram_id34 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U16");
ram_id35 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr1.U17");
// Channel 1
rbm_id00 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U00");
rbm_id01 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U01");
rbm_id02 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U02");
rbm_id03 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U03");
rbm_id04 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U04");
rbm_id05 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U05");
rbm_id06 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U06");
rbm_id07 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U07");
rbm_id08 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U08");
rbm_id09 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U09");
rbm_id10 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U10");
rbm_id11 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U11");
rbm_id12 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U12");
rbm_id13 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U13");
rbm_id14 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U14");
rbm_id15 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U15");
rbm_id16 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U16");
rbm_id17 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr0.U17");
rbm_id18 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U00");
rbm_id19 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U01");
rbm_id20 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U02");
rbm_id21 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U03");
rbm_id22 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U04");
rbm_id23 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U05");
rbm_id24 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U06");
rbm_id25 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U07");
rbm_id26 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U08");
rbm_id27 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U09");
rbm_id28 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U10");
rbm_id29 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U11");
rbm_id30 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U12");
rbm_id31 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U13");
rbm_id32 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U14");
rbm_id33 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U15");
rbm_id34 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U16");
rbm_id35 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr1.U17");
// Channe 2
rcm_id00 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U00");
rcm_id01 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U01");
rcm_id02 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U02");
rcm_id03 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U03");
rcm_id04 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U04");
rcm_id05 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U05");
rcm_id06 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U06");
rcm_id07 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U07");
rcm_id08 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U08");
rcm_id09 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U09");
rcm_id10 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U10");
rcm_id11 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U11");
rcm_id12 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U12");
rcm_id13 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U13");
rcm_id14 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U14");
rcm_id15 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U15");
rcm_id16 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U16");
rcm_id17 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr0.U17");
rcm_id18 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U00");
rcm_id19 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U01");
rcm_id20 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U02");
rcm_id21 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U03");
rcm_id22 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U04");
rcm_id23 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U05");
rcm_id24 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U06");
rcm_id25 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U07");
rcm_id26 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U08");
rcm_id27 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U09");
rcm_id28 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U10");
rcm_id29 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U11");
rcm_id30 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U12");
rcm_id31 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U13");
rcm_id32 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U14");
rcm_id33 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U15");
rcm_id34 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U16");
rcm_id35 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr1.U17");
// channel 3
rdm_id00 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U00");
rdm_id01 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U01");
rdm_id02 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U02");
rdm_id03 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U03");
rdm_id04 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U04");
rdm_id05 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U05");
rdm_id06 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U06");
rdm_id07 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U07");
rdm_id08 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U08");
rdm_id09 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U09");
rdm_id10 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U10");
rdm_id11 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U11");
rdm_id12 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U12");
rdm_id13 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U13");
rdm_id14 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U14");
rdm_id15 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U15");
rdm_id16 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U16");
rdm_id17 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr0.U17");
rdm_id18 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U00");
rdm_id19 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U01");
rdm_id20 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U02");
rdm_id21 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U03");
rdm_id22 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U04");
rdm_id23 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U05");
rdm_id24 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U06");
rdm_id25 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U07");
rdm_id26 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U08");
rdm_id27 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U09");
rdm_id28 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U10");
rdm_id29 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U11");
rdm_id30 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U12");
rdm_id31 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U13");
rdm_id32 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U14");
rdm_id33 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U15");
rdm_id34 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U16");
rdm_id35 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr1.U17");
//////////////////////////////////////
//workaround: for nested width problem
// Channel 0
ravid4 = $mmcreatesysmem("sysmem","ra_dimm144",36,1,1);
success=$mmaddtosysmem(ravid4,ram_id13,0,0,0);
success=$mmaddtosysmem(ravid4,ram_id04,1,0,0);
success=$mmaddtosysmem(ravid4,ram_id31,2,0,0);
success=$mmaddtosysmem(ravid4,ram_id22,3,0,0);
success=$mmaddtosysmem(ravid4,ram_id17,4,0,0);
success=$mmaddtosysmem(ravid4,ram_id16,5,0,0);
success=$mmaddtosysmem(ravid4,ram_id15,6,0,0);
success=$mmaddtosysmem(ravid4,ram_id14,7,0,0);
success=$mmaddtosysmem(ravid4,ram_id12,8,0,0);
success=$mmaddtosysmem(ravid4,ram_id11,9,0,0);
success=$mmaddtosysmem(ravid4,ram_id10,10,0,0);
success=$mmaddtosysmem(ravid4,ram_id09,11,0,0);
success=$mmaddtosysmem(ravid4,ram_id08,12,0,0);
success=$mmaddtosysmem(ravid4,ram_id07,13,0,0);
success=$mmaddtosysmem(ravid4,ram_id06,14,0,0);
success=$mmaddtosysmem(ravid4,ram_id05,15,0,0);
success=$mmaddtosysmem(ravid4,ram_id03,16,0,0);
success=$mmaddtosysmem(ravid4,ram_id02,17,0,0);
success=$mmaddtosysmem(ravid4,ram_id01,18,0,0);
success=$mmaddtosysmem(ravid4,ram_id00,19,0,0);
success=$mmaddtosysmem(ravid4,ram_id35,20,0,0);
success=$mmaddtosysmem(ravid4,ram_id34,21,0,0);
success=$mmaddtosysmem(ravid4,ram_id33,22,0,0);
success=$mmaddtosysmem(ravid4,ram_id32,23,0,0);
success=$mmaddtosysmem(ravid4,ram_id30,24,0,0);
success=$mmaddtosysmem(ravid4,ram_id29,25,0,0);
success=$mmaddtosysmem(ravid4,ram_id28,26,0,0);
success=$mmaddtosysmem(ravid4,ram_id27,27,0,0);
success=$mmaddtosysmem(ravid4,ram_id26,28,0,0);
success=$mmaddtosysmem(ravid4,ram_id25,29,0,0);
success=$mmaddtosysmem(ravid4,ram_id24,30,0,0);
success=$mmaddtosysmem(ravid4,ram_id23,31,0,0);
success=$mmaddtosysmem(ravid4,ram_id21,32,0,0);
success=$mmaddtosysmem(ravid4,ram_id20,33,0,0);
success=$mmaddtosysmem(ravid4,ram_id19,34,0,0);
success=$mmaddtosysmem(ravid4,ram_id18,35,0,0);
// Channel 1
rbvid4 = $mmcreatesysmem("sysmem","rb_dimm144",36,1,1);
success=$mmaddtosysmem(rbvid4,rbm_id13,0,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id04,1,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id31,2,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id22,3,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id17,4,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id16,5,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id15,6,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id14,7,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id12,8,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id11,9,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id10,10,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id09,11,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id08,12,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id07,13,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id06,14,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id05,15,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id03,16,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id02,17,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id01,18,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id00,19,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id35,20,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id34,21,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id33,22,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id32,23,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id30,24,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id29,25,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id28,26,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id27,27,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id26,28,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id25,29,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id24,30,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id23,31,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id21,32,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id20,33,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id19,34,0,0);
success=$mmaddtosysmem(rbvid4,rbm_id18,35,0,0);
// Channel 2
rcvid4 = $mmcreatesysmem("sysmem","rc_dimm144",36,1,1);
success=$mmaddtosysmem(rcvid4,rcm_id13,0,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id04,1,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id31,2,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id22,3,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id17,4,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id16,5,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id15,6,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id14,7,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id12,8,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id11,9,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id10,10,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id09,11,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id08,12,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id07,13,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id06,14,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id05,15,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id03,16,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id02,17,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id01,18,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id00,19,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id35,20,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id34,21,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id33,22,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id32,23,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id30,24,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id29,25,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id28,26,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id27,27,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id26,28,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id25,29,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id24,30,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id23,31,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id21,32,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id20,33,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id19,34,0,0);
success=$mmaddtosysmem(rcvid4,rcm_id18,35,0,0);
// Channel 3
rdvid4 = $mmcreatesysmem("sysmem","rd_dimm144",36,1,1);
success=$mmaddtosysmem(rdvid4,rdm_id13,0,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id04,1,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id31,2,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id22,3,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id17,4,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id16,5,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id15,6,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id14,7,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id12,8,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id11,9,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id10,10,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id09,11,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id08,12,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id07,13,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id06,14,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id05,15,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id03,16,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id02,17,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id01,18,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id00,19,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id35,20,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id34,21,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id33,22,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id32,23,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id30,24,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id29,25,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id28,26,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id27,27,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id26,28,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id25,29,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id24,30,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id23,31,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id21,32,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id20,33,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id19,34,0,0);
success=$mmaddtosysmem(rdvid4,rdm_id18,35,0,0);
`ifdef STACK_DIMM
//////////////////////
// RANK 1, STACK 1
// Channel 0
rsam_id00 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U00");
rsam_id01 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U01");
rsam_id02 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U02");
rsam_id03 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U03");
rsam_id04 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U04");
rsam_id05 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U05");
rsam_id06 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U06");
rsam_id07 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U07");
rsam_id08 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U08");
rsam_id09 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U09");
rsam_id10 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U10");
rsam_id11 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U11");
rsam_id12 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U12");
rsam_id13 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U13");
rsam_id14 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U14");
rsam_id15 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U15");
rsam_id16 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U16");
rsam_id17 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr2.U17");
rsam_id18 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U00");
rsam_id19 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U01");
rsam_id20 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U02");
rsam_id21 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U03");
rsam_id22 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U04");
rsam_id23 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U05");
rsam_id24 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U06");
rsam_id25 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U07");
rsam_id26 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U08");
rsam_id27 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U09");
rsam_id28 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U10");
rsam_id29 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U11");
rsam_id30 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U12");
rsam_id31 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U13");
rsam_id32 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U14");
rsam_id33 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U15");
rsam_id34 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U16");
rsam_id35 = $mminstanceid("cmp_top.cmp_dram.mem0.dimmr3.U17");
// Channel 1
rsbm_id00 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U00");
rsbm_id01 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U01");
rsbm_id02 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U02");
rsbm_id03 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U03");
rsbm_id04 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U04");
rsbm_id05 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U05");
rsbm_id06 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U06");
rsbm_id07 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U07");
rsbm_id08 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U08");
rsbm_id09 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U09");
rsbm_id10 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U10");
rsbm_id11 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U11");
rsbm_id12 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U12");
rsbm_id13 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U13");
rsbm_id14 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U14");
rsbm_id15 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U15");
rsbm_id16 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U16");
rsbm_id17 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr2.U17");
rsbm_id18 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U00");
rsbm_id19 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U01");
rsbm_id20 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U02");
rsbm_id21 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U03");
rsbm_id22 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U04");
rsbm_id23 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U05");
rsbm_id24 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U06");
rsbm_id25 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U07");
rsbm_id26 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U08");
rsbm_id27 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U09");
rsbm_id28 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U10");
rsbm_id29 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U11");
rsbm_id30 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U12");
rsbm_id31 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U13");
rsbm_id32 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U14");
rsbm_id33 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U15");
rsbm_id34 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U16");
rsbm_id35 = $mminstanceid("cmp_top.cmp_dram.mem1.dimmr3.U17");
// Channel 2
rscm_id00 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U00");
rscm_id01 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U01");
rscm_id02 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U02");
rscm_id03 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U03");
rscm_id04 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U04");
rscm_id05 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U05");
rscm_id06 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U06");
rscm_id07 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U07");
rscm_id08 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U08");
rscm_id09 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U09");
rscm_id10 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U10");
rscm_id11 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U11");
rscm_id12 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U12");
rscm_id13 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U13");
rscm_id14 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U14");
rscm_id15 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U15");
rscm_id16 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U16");
rscm_id17 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr2.U17");
rscm_id18 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U00");
rscm_id19 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U01");
rscm_id20 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U02");
rscm_id21 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U03");
rscm_id22 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U04");
rscm_id23 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U05");
rscm_id24 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U06");
rscm_id25 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U07");
rscm_id26 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U08");
rscm_id27 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U09");
rscm_id28 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U10");
rscm_id29 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U11");
rscm_id30 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U12");
rscm_id31 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U13");
rscm_id32 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U14");
rscm_id33 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U15");
rscm_id34 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U16");
rscm_id35 = $mminstanceid("cmp_top.cmp_dram.mem2.dimmr3.U17");
// Channel 3
rsdm_id00 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U00");
rsdm_id01 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U01");
rsdm_id02 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U02");
rsdm_id03 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U03");
rsdm_id04 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U04");
rsdm_id05 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U05");
rsdm_id06 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U06");
rsdm_id07 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U07");
rsdm_id08 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U08");
rsdm_id09 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U09");
rsdm_id10 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U10");
rsdm_id11 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U11");
rsdm_id12 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U12");
rsdm_id13 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U13");
rsdm_id14 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U14");
rsdm_id15 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U15");
rsdm_id16 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U16");
rsdm_id17 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr2.U17");
rsdm_id18 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U00");
rsdm_id19 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U01");
rsdm_id20 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U02");
rsdm_id21 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U03");
rsdm_id22 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U04");
rsdm_id23 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U05");
rsdm_id24 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U06");
rsdm_id25 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U07");
rsdm_id26 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U08");
rsdm_id27 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U09");
rsdm_id28 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U10");
rsdm_id29 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U11");
rsdm_id30 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U12");
rsdm_id31 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U13");
rsdm_id32 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U14");
rsdm_id33 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U15");
rsdm_id34 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U16");
rsdm_id35 = $mminstanceid("cmp_top.cmp_dram.mem3.dimmr3.U17");
//////////////////////////////////////
//workaround: for nested width problem
// Channel 0
rsavid4 = $mmcreatesysmem("sysmem","rsa_dimm144",36,1,1);
success=$mmaddtosysmem(rsavid4,rsam_id13,0,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id04,1,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id31,2,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id22,3,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id17,4,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id16,5,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id15,6,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id14,7,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id12,8,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id11,9,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id10,10,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id09,11,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id08,12,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id07,13,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id06,14,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id05,15,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id03,16,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id02,17,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id01,18,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id00,19,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id35,20,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id34,21,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id33,22,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id32,23,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id30,24,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id29,25,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id28,26,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id27,27,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id26,28,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id25,29,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id24,30,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id23,31,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id21,32,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id20,33,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id19,34,0,0);
success=$mmaddtosysmem(rsavid4,rsam_id18,35,0,0);
// Channel 1
rsbvid4 = $mmcreatesysmem("sysmem","rsb_dimm144",36,1,1);
success=$mmaddtosysmem(rsbvid4,rsbm_id13,0,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id04,1,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id31,2,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id22,3,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id17,4,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id16,5,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id15,6,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id14,7,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id12,8,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id11,9,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id10,10,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id09,11,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id08,12,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id07,13,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id06,14,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id05,15,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id03,16,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id02,17,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id01,18,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id00,19,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id35,20,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id34,21,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id33,22,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id32,23,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id30,24,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id29,25,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id28,26,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id27,27,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id26,28,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id25,29,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id24,30,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id23,31,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id21,32,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id20,33,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id19,34,0,0);
success=$mmaddtosysmem(rsbvid4,rsbm_id18,35,0,0);
// Channel 2
rscvid4 = $mmcreatesysmem("sysmem","rsc_dimm144",36,1,1);
success=$mmaddtosysmem(rscvid4,rscm_id13,0,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id04,1,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id31,2,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id22,3,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id17,4,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id16,5,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id15,6,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id14,7,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id12,8,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id11,9,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id10,10,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id09,11,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id08,12,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id07,13,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id06,14,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id05,15,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id03,16,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id02,17,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id01,18,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id00,19,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id35,20,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id34,21,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id33,22,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id32,23,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id30,24,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id29,25,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id28,26,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id27,27,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id26,28,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id25,29,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id24,30,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id23,31,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id21,32,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id20,33,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id19,34,0,0);
success=$mmaddtosysmem(rscvid4,rscm_id18,35,0,0);
// Channel 3
rsdvid4 = $mmcreatesysmem("sysmem","rsd_dimm144",36,1,1);
success=$mmaddtosysmem(rsdvid4,rsdm_id13,0,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id04,1,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id31,2,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id22,3,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id17,4,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id16,5,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id15,6,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id14,7,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id12,8,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id11,9,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id10,10,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id09,11,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id08,12,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id07,13,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id06,14,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id05,15,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id03,16,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id02,17,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id01,18,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id00,19,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id35,20,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id34,21,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id33,22,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id32,23,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id30,24,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id29,25,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id28,26,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id27,27,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id26,28,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id25,29,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id24,30,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id23,31,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id21,32,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id20,33,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id19,34,0,0);
success=$mmaddtosysmem(rsdvid4,rsdm_id18,35,0,0);
`endif // ifdef STACK_DIMM
`endif // ifdef RANK_DIMM
if($test$plusargs("RANK_DIMM")) begin
if($test$plusargs("STACK_DIMM")) begin
//////////////////////////////////////
//Ranked and Stacked Syatem Memory
rsvid5 = $mmcreatesysmem("sysmem","rank_stack_unsc",1,16,1);
success=$mmaddtosysmem(rsvid5,avid4,0,0,0);
success=$mmaddtosysmem(rsvid5,savid4,0,1,0);
success=$mmaddtosysmem(rsvid5,ravid4,0,2,0);
success=$mmaddtosysmem(rsvid5,rsavid4,0,3,0);
success=$mmaddtosysmem(rsvid5,bvid4,0,4,0);
success=$mmaddtosysmem(rsvid5,sbvid4,0,5,0);
success=$mmaddtosysmem(rsvid5,rbvid4,0,6,0);
success=$mmaddtosysmem(rsvid5,rsbvid4,0,7,0);
success=$mmaddtosysmem(rsvid5,cvid4,0,8,0);
success=$mmaddtosysmem(rsvid5,scvid4,0,9,0);
success=$mmaddtosysmem(rsvid5,rcvid4,0,10,0);
success=$mmaddtosysmem(rsvid5,rscvid4,0,11,0);
success=$mmaddtosysmem(rsvid5,dvid4,0,12,0);
success=$mmaddtosysmem(rsvid5,sdvid4,0,13,0);
success=$mmaddtosysmem(rsvid5,rdvid4,0,14,0);
success=$mmaddtosysmem(rsvid5,rsdvid4,0,15,0);
// adding a DRAM bank bit and changing RAS to 15
// debugging with rank
//svid6 = $mmaddressmap("rank_stack_sc",rsvid5,"29 28 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 27 26 25 31 30 1 0");
// added the Col width bit as 25, DRAM bank now 8 => 26,27,28, STACK,RANK 29,30, L2 Bank 31 32
// correct
svid6 = $mmaddressmap("rank_stack_sc",rsvid5,"30 29 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 28 27 26 32 31 1 0");
//svid6 = $mmaddressmap("rank_stack_sc",rsvid5,"28 27 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 26 25 30 29 1 0");
//svid6 = $mmaddressmap("rank_stack_sc",rsvid5,"26 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 25 24 23 28 27 2 1 0");
end
else begin
//////////////////////////////////////
//Unranked and Stacked Syatem Memory
rvid5 = $mmcreatesysmem("sysmem","rank_unsc",1,8,1);
success=$mmaddtosysmem(rvid5,avid4,0,0,0);
success=$mmaddtosysmem(rvid5,ravid4,0,1,0);
success=$mmaddtosysmem(rvid5,bvid4,0,2,0);
success=$mmaddtosysmem(rvid5,rbvid4,0,3,0);
success=$mmaddtosysmem(rvid5,cvid4,0,4,0);
success=$mmaddtosysmem(rvid5,rcvid4,0,5,0);
success=$mmaddtosysmem(rvid5,dvid4,0,6,0);
success=$mmaddtosysmem(rvid5,rdvid4,0,7,0);
// adding a DRAM bank bit and changing RAS to 15
svid6 = $mmaddressmap("rank_sc",rvid5,"29 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 28 27 26 31 30 1 0");
//svid6 = $mmaddressmap("rank_sc",rvid5,"27 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 26 25 29 28 1 0");
//svid6 = $mmaddressmap("rank_sc",rvid5,"25 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 24 23 27 26 2 1 0");
end
end
else if($test$plusargs("STACK_DIMM")) begin
//////////////////////////////////////
//Unranked and Stacked Syatem Memory
svid5 = $mmcreatesysmem("sysmem","stack_unsc",1,8,1);
success=$mmaddtosysmem(svid5,avid4,0,0,0);
success=$mmaddtosysmem(svid5,savid4,0,1,0);
success=$mmaddtosysmem(svid5,bvid4,0,2,0);
success=$mmaddtosysmem(svid5,sbvid4,0,3,0);
success=$mmaddtosysmem(svid5,cvid4,0,4,0);
success=$mmaddtosysmem(svid5,scvid4,0,5,0);
success=$mmaddtosysmem(svid5,dvid4,0,6,0);
success=$mmaddtosysmem(svid5,sdvid4,0,7,0);
// adding a DRAM bank bit and changing RAS to 15
svid6 = $mmaddressmap("stack_sc",svid5,"29 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 28 27 26 31 30 1 0");
//svid6 = $mmaddressmap("stack_sc",svid5,"27 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 26 25 29 28 1 0");
//svid6 = $mmaddressmap("stack_sc",svid5,"22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 25 24 23 27 26 2 1 0");
end
else begin
//////////////////////////////////////
//Unranked and Unstacked Syatem Memory
vid5 = $mmcreatesysmem("sysmem","single_unsc",1,4,1);
success=$mmaddtosysmem(vid5,avid4,0,0,0);
success=$mmaddtosysmem(vid5,bvid4,0,1,0);
success=$mmaddtosysmem(vid5,cvid4,0,2,0);
success=$mmaddtosysmem(vid5,dvid4,0,3,0);
// adding a DRAM bank bit and changing RAS to 15
// as discussed with sunil
// 28,27,26 => DRAM Bank , 30,29 => L2 Bank
vid6 = $mmaddressmap("single_sc",vid5,"25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 28 27 26 30 29 1 0");
//vid6 = $mmaddressmap("single_sc",vid5,"24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 26 25 28 27 1 0");
//vid6 = $mmaddressmap("single_sc",vid5,"22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 24 23 26 25 2 1 0");
end // NOT STACK_DIMM
end
//////////////////////////////
// Pre Load the denali memory
initial begin
if($test$plusargs("RANK_DIMM")) begin
if($test$plusargs("STACK_DIMM")) begin
`ifdef DRAM_SAT
#12 success = $mmload("rank_stack_sc", "./denali.data");
`else
#12 success = $mmload("rank_stack_sc", "./denali.image");
`endif
//$display("%0d: After loading denali.dat to memory variable success = %d\n", $time, success);
end
else begin
#12 success = $mmload("rank_sc", "./denali.data");
end
end
else if($test$plusargs("STACK_DIMM")) begin
#12 success = $mmload("stack_sc", "./denali.data");
end
else begin
#12 success = $mmload("single_sc", "./denali.data");
end
end
////////////////////////////////
// Enable denali error Injection
initial begin
#1
if($test$plusargs("DENALI_ERROR")) begin
if($test$plusargs("RANK_DIMM")) begin
if($test$plusargs("STACK_DIMM")) begin
success = $mmerrinject(rsavid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(rsbvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(rscvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(rsdvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
end
success = $mmerrinject(ravid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(rbvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(rcvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(rdvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
end
if($test$plusargs("STACK_DIMM")) begin
success = $mmerrinject(savid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(sbvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(scvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(sdvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
end
success = $mmerrinject(avid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(bvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(cvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
success = $mmerrinject(dvid4, "-seed 0 -reads 1 2 -bits 1 -percent 100");
end
end
`endif // DENALI_ON
/*
ch_mem AUTO_TEMPLATE (
// Outputs
.XXDQ (DRAM@_DQ[127:0]),
.XXCB (DRAM@_CB[15:0]),
.XXDQS (DRAM@_DQS[35:0]),
.XXSDA (DRAM@"(+ 0 (* 2 @))"@"(+ 1 (* 2 @))"),
// Inputs
.XXRAS_L (DRAM@_RAS_L),
.XXCAS_L (DRAM@_CAS_L),
.XXWE_L (DRAM@_WE_L),
.XXCS_L (DRAM@_CS_L[3:0]),
.XXRESET_L (DRAM@_RST_L),
.XXADDR (DRAM@_ADDR[14:0]),
.XXBA (DRAM@_BA[2:0]),
.XXCLK_L (DRAM@_CK_N[3:0]),
.XXCLK (DRAM@_CK_P[3:0]),
.XXCKE (DRAM@_CKE),
.XXSCL (DRAM@"(+ 0 (* 2 @))"@"(+ 1 (* 2 @))"));
*/
ch_mem mem0 (/*AUTOINST*/
// Inouts
.XXSDA (DRAM01), // Templated
.XXDQ (DRAM0_DQ[127:0]), // Templated
.XXCB (DRAM0_CB[15:0]), // Templated
.XXDQS (DRAM0_DQS[35:0]), // Templated
// Inputs
.XXRAS_L (DRAM0_RAS_L), // Templated
.XXCAS_L (DRAM0_CAS_L), // Templated
.XXWE_L (DRAM0_WE_L), // Templated
.XXCS_L (DRAM0_CS_L[3:0]), // Templated
.XXRESET_L (DRAM0_RST_L), // Templated
.XXADDR (DRAM0_ADDR[14:0]), // Templated
.XXBA (DRAM0_BA[2:0]), // Templated
.XXSA (XXSA[2:0]),
.XXSCL (DRAM01), // Templated
.XXWP (XXWP),
.XXCLK (DRAM0_CK_P[3:0]), // Templated
.XXCLK_L (DRAM0_CK_N[3:0]), // Templated
.XXCKE (DRAM0_CKE)); // Templated
ch_mem mem1 (/*AUTOINST*/
// Inouts
.XXSDA (DRAM23), // Templated
.XXDQ (DRAM1_DQ[127:0]), // Templated
.XXCB (DRAM1_CB[15:0]), // Templated
.XXDQS (DRAM1_DQS[35:0]), // Templated
// Inputs
.XXRAS_L (DRAM1_RAS_L), // Templated
.XXCAS_L (DRAM1_CAS_L), // Templated
.XXWE_L (DRAM1_WE_L), // Templated
.XXCS_L (DRAM1_CS_L[3:0]), // Templated
.XXRESET_L (DRAM1_RST_L), // Templated
.XXADDR (DRAM1_ADDR[14:0]), // Templated
.XXBA (DRAM1_BA[2:0]), // Templated
.XXSA (XXSA[2:0]),
.XXSCL (DRAM23), // Templated
.XXWP (XXWP),
.XXCLK (DRAM1_CK_P[3:0]), // Templated
.XXCLK_L (DRAM1_CK_N[3:0]), // Templated
.XXCKE (DRAM1_CKE)); // Templated
/*
ch_mem AUTO_TEMPLATE (
// Outputs
.XXDQ (DRAM@_DQ[127:0]),
.XXCB (DRAM@_CB[15:0]),
.XXDQS (DRAM@_DQS[35:0]),
.XXSDA (DRAM@"(+ 0 (* 2 @))"@"(+ 1 (* 2 @))"),
// Inputs
.XXRAS_L (DRAM@_RAS_L),
.XXCAS_L (DRAM@_CAS_L),
.XXWE_L (DRAM@_WE_L),
.XXCS_L (DRAM@_CS_L[3:0]),
.XXRESET_L (DRAM@_RST_L),
.XXADDR (DRAM@_ADDR[14:0]),
.XXBA (DRAM@_BA[2:0]),
.XXCLK_L (DRAM@_CK_N[3:0]),
.XXCLK (DRAM@_CK_P[3:0]),
.XXCKE (DRAM@_CKE),
.XXSCL (DRAM@"(+ 0 (* 2 @))"@"(+ 1 (* 2 @))"));
*/
ch_mem mem2 (/*AUTOINST*/
// Inouts
.XXSDA (DRAM45), // Templated
.XXDQ (DRAM2_DQ[127:0]), // Templated
.XXCB (DRAM2_CB[15:0]), // Templated
.XXDQS (DRAM2_DQS[35:0]), // Templated
// Inputs
.XXRAS_L (DRAM2_RAS_L), // Templated
.XXCAS_L (DRAM2_CAS_L), // Templated
.XXWE_L (DRAM2_WE_L), // Templated
.XXCS_L (DRAM2_CS_L[3:0]), // Templated
.XXRESET_L (DRAM2_RST_L), // Templated
.XXADDR (DRAM2_ADDR[14:0]), // Templated
.XXBA (DRAM2_BA[2:0]), // Templated
.XXSA (XXSA[2:0]),
.XXSCL (DRAM45), // Templated
.XXWP (XXWP),
.XXCLK (DRAM2_CK_P[3:0]), // Templated
.XXCLK_L (DRAM2_CK_N[3:0]), // Templated
.XXCKE (DRAM2_CKE)); // Templated
/*
ch_mem AUTO_TEMPLATE (
// Outputs
.XXDQ (DRAM@_DQ[127:0]),
.XXCB (DRAM@_CB[15:0]),
.XXDQS (DRAM@_DQS[35:0]),
.XXSDA (DRAM@"(+ 0 (* 2 @))"@"(+ 1 (* 2 @))"),
// Inputs
.XXRAS_L (DRAM@_RAS_L),
.XXCAS_L (DRAM@_CAS_L),
.XXWE_L (DRAM@_WE_L),
.XXCS_L (DRAM@_CS_L[3:0]),
.XXRESET_L (DRAM@_RST_L),
.XXADDR (DRAM@_ADDR[14:0]),
.XXBA (DRAM@_BA[2:0]),
.XXCLK_L (DRAM@_CK_N[3:0]),
.XXCLK (DRAM@_CK_P[3:0]),
.XXCKE (DRAM@_CKE),
.XXSCL (DRAM@"(+ 0 (* 2 @))"@"(+ 1 (* 2 @))"));
*/
ch_mem mem3 (/*AUTOINST*/
// Inouts
.XXSDA (DRAM67), // Templated
.XXDQ (DRAM3_DQ[127:0]), // Templated
.XXCB (DRAM3_CB[15:0]), // Templated
.XXDQS (DRAM3_DQS[35:0]), // Templated
// Inputs
.XXRAS_L (DRAM3_RAS_L), // Templated
.XXCAS_L (DRAM3_CAS_L), // Templated
.XXWE_L (DRAM3_WE_L), // Templated
.XXCS_L (DRAM3_CS_L[3:0]), // Templated
.XXRESET_L (DRAM3_RST_L), // Templated
.XXADDR (DRAM3_ADDR[14:0]), // Templated
.XXBA (DRAM3_BA[2:0]), // Templated
.XXSA (XXSA[2:0]),
.XXSCL (DRAM67), // Templated
.XXWP (XXWP),
.XXCLK (DRAM3_CK_P[3:0]), // Templated
.XXCLK_L (DRAM3_CK_N[3:0]), // Templated
.XXCKE (DRAM3_CKE)); // Templated
// don't include DRAM monitors when compiling for MSS SAT environment
`ifdef MSS_SAT
`else
/* cmp_dram_mon AUTO_TEMPLATE (
.clk (dram_gclk),
.dram_pad0_cs_l(DRAM0_CS_L[1:0]),
.dram_pad1_cs_l(DRAM1_CS_L[1:0]),
.dram_pad2_cs_l(DRAM2_CS_L[1:0]),
.dram_pad3_cs_l(DRAM3_CS_L[1:0]),
.rst_l(cmp_grst));
*/
cmp_dram_mon cmp_dram_mon (/*AUTOINST*/
// Inputs
.clk (dram_gclk), // Templated
.dram_pad0_cs_l(DRAM0_CS_L[1:0]), // Templated
.dram_pad1_cs_l(DRAM1_CS_L[1:0]), // Templated
.dram_pad2_cs_l(DRAM2_CS_L[1:0]), // Templated
.dram_pad3_cs_l(DRAM3_CS_L[1:0]), // Templated
.rst_l (cmp_grst)); // Templated
/* dimm_if_mon AUTO_TEMPLATE (
.clk (dram_gclk),
.DRAM_CK ({4{DRAM@_CK_P[3], DRAM@_CK_N[3]}}),
.DRAM_CKE (DRAM@_CKE),
.DRAM_RST_L (DRAM@_RST_L),
.DRAM_CS_L (DRAM@_CS_L[1:0]),
.DRAM_BA (DRAM@_BA[2:0]),
.DRAM_ADDR (DRAM@_ADDR[14:0]),
.DRAM_RAS_L (DRAM@_RAS_L),
.DRAM_CAS_L (DRAM@_CAS_L),
.DRAM_WE_L (DRAM@_WE_L),
.DRAM_DQ (DRAM@_DQ[127:0]),
.DRAM_CB (DRAM@_CB[15:0]),
.DRAM_DQS (DRAM@_DQS[35:0]),
.DRAM_ENB_ERROR (DRAM@_ENB_ERROR));
.DRAM_FAIL_OVER (DRAM@_FAIL_OVER));
.DRAM_FAIL_PART (DRAM@_FAIL_PART));
*/
dimm_if_mon dimm_if_mon0 (/*AUTOINST*/
// Inouts
.DRAM_DQ (DRAM0_DQ[127:0]), // Templated
// Inputs
.clk (dram_gclk), // Templated
.DRAM_CK ({4{DRAM0_CK_P[3], DRAM0_CK_N[3]}}), // Templated
.DRAM_CKE (DRAM0_CKE), // Templated
.DRAM_RST_L(DRAM0_RST_L), // Templated
.DRAM_CS_L (DRAM0_CS_L[1:0]), // Templated
.DRAM_BA (DRAM0_BA[2:0]), // Templated
.DRAM_ADDR (DRAM0_ADDR[14:0]), // Templated
.DRAM_RAS_L(DRAM0_RAS_L), // Templated
.DRAM_CAS_L(DRAM0_CAS_L), // Templated
.DRAM_WE_L (DRAM0_WE_L), // Templated
.DRAM_CB (DRAM0_CB[15:0]), // Templated
.DRAM_DQS (DRAM0_DQS[35:0]), // Templated
.DRAM_ENB_ERROR(DRAM0_ENB_ERROR), // Templated
.DRAM_FAIL_OVER(DRAM_FAIL_OVER),
.DRAM_FAIL_PART(DRAM_FAIL_PART[5:0]));
dimm_if_mon dimm_if_mon1 (/*AUTOINST*/
// Inouts
.DRAM_DQ (DRAM1_DQ[127:0]), // Templated
// Inputs
.clk (dram_gclk), // Templated
.DRAM_CK ({4{DRAM1_CK_P[3], DRAM1_CK_N[3]}}), // Templated
.DRAM_CKE (DRAM1_CKE), // Templated
.DRAM_RST_L(DRAM1_RST_L), // Templated
.DRAM_CS_L (DRAM1_CS_L[1:0]), // Templated
.DRAM_BA (DRAM1_BA[2:0]), // Templated
.DRAM_ADDR (DRAM1_ADDR[14:0]), // Templated
.DRAM_RAS_L(DRAM1_RAS_L), // Templated
.DRAM_CAS_L(DRAM1_CAS_L), // Templated
.DRAM_WE_L (DRAM1_WE_L), // Templated
.DRAM_CB (DRAM1_CB[15:0]), // Templated
.DRAM_DQS (DRAM1_DQS[35:0]), // Templated
.DRAM_ENB_ERROR(DRAM1_ENB_ERROR), // Templated
.DRAM_FAIL_OVER(DRAM_FAIL_OVER),
.DRAM_FAIL_PART(DRAM_FAIL_PART[5:0]));
dimm_if_mon dimm_if_mon2 (/*AUTOINST*/
// Inouts
.DRAM_DQ (DRAM2_DQ[127:0]), // Templated
// Inputs
.clk (dram_gclk), // Templated
.DRAM_CK ({4{DRAM2_CK_P[3], DRAM2_CK_N[3]}}), // Templated
.DRAM_CKE (DRAM2_CKE), // Templated
.DRAM_RST_L(DRAM2_RST_L), // Templated
.DRAM_CS_L (DRAM2_CS_L[1:0]), // Templated
.DRAM_BA (DRAM2_BA[2:0]), // Templated
.DRAM_ADDR (DRAM2_ADDR[14:0]), // Templated
.DRAM_RAS_L(DRAM2_RAS_L), // Templated
.DRAM_CAS_L(DRAM2_CAS_L), // Templated
.DRAM_WE_L (DRAM2_WE_L), // Templated
.DRAM_CB (DRAM2_CB[15:0]), // Templated
.DRAM_DQS (DRAM2_DQS[35:0]), // Templated
.DRAM_ENB_ERROR(DRAM2_ENB_ERROR), // Templated
.DRAM_FAIL_OVER(DRAM_FAIL_OVER),
.DRAM_FAIL_PART(DRAM_FAIL_PART[5:0]));
dimm_if_mon dimm_if_mon3 (/*AUTOINST*/
// Inouts
.DRAM_DQ (DRAM3_DQ[127:0]), // Templated
// Inputs
.clk (dram_gclk), // Templated
.DRAM_CK ({4{DRAM3_CK_P[3], DRAM3_CK_N[3]}}), // Templated
.DRAM_CKE (DRAM3_CKE), // Templated
.DRAM_RST_L(DRAM3_RST_L), // Templated
.DRAM_CS_L (DRAM3_CS_L[1:0]), // Templated
.DRAM_BA (DRAM3_BA[2:0]), // Templated
.DRAM_ADDR (DRAM3_ADDR[14:0]), // Templated
.DRAM_RAS_L(DRAM3_RAS_L), // Templated
.DRAM_CAS_L(DRAM3_CAS_L), // Templated
.DRAM_WE_L (DRAM3_WE_L), // Templated
.DRAM_CB (DRAM3_CB[15:0]), // Templated
.DRAM_DQS (DRAM3_DQS[35:0]), // Templated
.DRAM_ENB_ERROR(DRAM3_ENB_ERROR), // Templated
.DRAM_FAIL_OVER(DRAM_FAIL_OVER),
.DRAM_FAIL_PART(DRAM_FAIL_PART[5:0]));
`endif
initial begin
if ( $test$plusargs("CMP_DRAM_ENB_ERROR") ) begin
force `TOP_MOD.cmp_dram.DRAM0_ENB_ERROR = 1'b1;
force `TOP_MOD.cmp_dram.DRAM1_ENB_ERROR = 1'b1;
force `TOP_MOD.cmp_dram.DRAM2_ENB_ERROR = 1'b1;
force `TOP_MOD.cmp_dram.DRAM3_ENB_ERROR = 1'b1;
end
/*
DRAM0_FAIL_OVER = 1'b0;
DRAM1_FAIL_OVER = 1'b0;
DRAM2_FAIL_OVER = 1'b0;
DRAM3_FAIL_OVER = 1'b0;
DRAM0_FAIL_PART = 6'h0;
DRAM1_FAIL_PART = 6'h0;
DRAM2_FAIL_PART = 6'h0;
DRAM3_FAIL_PART = 6'h0;
*/
end
`ifdef DENALI_ON
//////////////////////////////////
// Task to enable error injection
//
task enb_errors;
input [3:0] ch;
input [17:0] comp;
input [31:0] seed;
input [3:0] bits;
integer m_id;
integer status;
begin
$display("%0d: Enabling error injection:- ch[%0d], component[%0d]\n", $time, ch, comp);
if (ch[0]) begin
if (comp[0]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U00");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[1]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U01");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[2]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U02");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[3]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U03");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[4]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U04");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[5]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U05");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[6]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U06");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[7]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U07");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[8]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U08");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[9]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U09");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[10]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U10");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[11]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U11");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[12]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U12");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[13]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U13");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[14]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U14");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[15]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U15");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[16]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U16");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[17]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem0.dimm0.U17");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
end
if (ch[1]) begin
if (comp[0]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U00");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[1]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U01");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[2]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U02");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[3]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U03");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[4]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U04");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[5]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U05");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[6]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U06");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[7]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U07");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[8]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U08");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[9]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U09");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[10]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U10");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[11]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U11");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[12]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U12");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[13]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U13");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[14]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U14");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[15]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U15");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[16]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U16");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[17]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem1.dimm0.U17");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
end
if (ch[2]) begin
if (comp[0]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U00");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[1]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U01");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[2]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U02");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[3]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U03");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[4]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U04");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[5]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U05");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[6]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U06");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[7]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U07");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[8]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U08");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[9]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U09");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[10]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U10");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[11]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U11");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[12]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U12");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[13]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U13");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[14]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U14");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[15]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U15");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[16]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U16");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[17]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem2.dimm0.U17");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
end
if (ch[3]) begin
if (comp[0]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U00");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[1]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U01");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[2]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U02");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[3]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U03");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[4]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U04");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[5]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U05");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[6]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U06");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[7]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U07");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[8]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U08");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[9]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U09");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[10]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U10");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[11]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U11");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[12]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U12");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[13]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U13");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[14]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U14");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[15]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U15");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[16]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U16");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
if (comp[17]) begin
m_id = $mminstanceid("cmp_top.cmp_dram.mem3.dimm0.U17");
status = $mmerrinject(m_id, "-seed 0 -reads 2 4 -bits 1 -percent 100");
end
end
end
endtask
`endif // DENALI_ON
`ifdef GATE_SIM_DRAM
reg dram_i2c_enabled;
initial
begin
if ($test$plusargs("LO_STACK_RANK_BIT")) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_bank_low_sel_u_dffrl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_bank_low_sel_u_dffrl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_bank_low_sel_u_dffrl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_bank_low_sel_u_dffrl_async_ns_0_.q = 1'b1 ;
end
end
initial
begin
if (!$test$plusargs("no_dram_slam_init")) begin
dram_i2c_enabled = 1'b0;
if ( ($test$plusargs("RANK_DIMM")) && ($test$plusargs("STACK_DIMM")) && ($test$plusargs("DRAM_I2C") == 0) ) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
end
else if ( ($test$plusargs("RANK_DIMM")) && ($test$plusargs("DRAM_I2C") == 0) ) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_rank1_present_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
end
else if ( ($test$plusargs("STACK_DIMM")) && ($test$plusargs("DRAM_I2C") == 0) ) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_stacked_dimm_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_2_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_1_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_tot_ranks_0_ = 1'b0;
end
if ($test$plusargs("DRAM_SCRUB")) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_data_scrub_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_data_scrub_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_data_scrub_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_data_scrub_u_dffrl_async_ns_0_.q = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_11_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_10_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_9_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_8_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_7_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_6_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_5_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_4_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_3_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_2_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_11_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_10_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_9_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_8_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_7_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_6_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_5_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_4_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_3_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_2_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_11_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_10_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_9_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_8_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_7_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_6_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_5_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_4_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_3_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_2_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_11_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_10_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_9_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_8_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_7_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_6_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_5_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_4_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_3_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_2_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_freq_scrb_u_dffsl_async_ns_0_.q = 1'b0 ;
end
if ($test$plusargs("DIMM_SIZE_1G")) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
end
else if ($test$plusargs("DIMM_SIZE_512")) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
end
else if ($test$plusargs("DIMM_SIZE_256")) begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_3_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_2_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_1_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ras_addr_bits_u_dffsl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_eight_bank_present_u_dffsl_async_ns_0_.q = 1'b0 ;
end
else begin
// use default = 2G b
end
if ($test$plusargs("2CHANNEL_01")) begin
#1300000 force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_ch_enabled_u_dffrl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_ch_enabled_u_dffrl_async_ns_0_.q = 1'b1 ;
end
else if ($test$plusargs("2CHANNEL_23")) begin
#1300000 force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_ch_enabled_u_dffrl_async_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_ch_enabled_u_dffrl_async_ns_0_.q = 1'b1 ;
end
end // of no_dram_slam_init
end
initial
begin
if (! $value$plusargs("force_cas_latency=%d", cas_latency)) begin
cas_latency = 3 ;
end
end
always @(posedge `DCTLPATH0.dram_rclk)
begin
if($test$plusargs("NO_BYPASS_POR_WAIT")) begin
if($test$plusargs("BYPASS_WMR_WAIT")) begin
// if warm reset and waiting for 200 us clocks
if({`DCTLPATH0.ch0_que_pos [4],
`DCTLPATH0.ch0_que_pos [3],
`DCTLPATH0.ch0_que_pos [2],
`DCTLPATH0.ch0_que_pos [1],
`DCTLPATH0.ch0_que_pos [0]} == 5'he)
begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
end else begin
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_;
end
end
end else begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_pad_clk_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_pad_clk_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_pad_clk_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_pad_clk_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_ff_cke_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_ff_cke_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_ff_cke_enable_u_dffrl_ns_0_.q = 1'b1 ;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_ff_cke_enable_u_dffrl_ns_0_.q = 1'b1 ;
if({`DCTLPATH0.ch0_que_pos [4],
`DCTLPATH0.ch0_que_pos [3],
`DCTLPATH0.ch0_que_pos [2],
`DCTLPATH0.ch0_que_pos [1],
`DCTLPATH0.ch0_que_pos [0]} == 5'h0)
begin
if(`DCTLPATH0.dramctl0_dram_dctl_dram_que_que_hw_selfrsh == 1'b0 )
begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_init = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_init = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_init = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_init = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
end
end
if({`DCTLPATH0.ch0_que_pos [4],
`DCTLPATH0.ch0_que_pos [3],
`DCTLPATH0.ch0_que_pos [2],
`DCTLPATH0.ch0_que_pos [1],
`DCTLPATH0.ch0_que_pos [0]} == 5'h1)
begin
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_init;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_init;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_init;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_init;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_;
end
// if warm reset and waiting for 200 us clocks
if({`DCTLPATH0.ch0_que_pos [4],
`DCTLPATH0.ch0_que_pos [3],
`DCTLPATH0.ch0_que_pos [2],
`DCTLPATH0.ch0_que_pos [1],
`DCTLPATH0.ch0_que_pos [0]} == 5'he)
begin
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_ = 1'b0;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_ = 1'b1;
force `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_ = 1'b1;
end else begin
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH0.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH0.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH1.dramctl0_dram_dctl_dram_que_que_bank_idle_cnt_4_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_0_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_1_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_2_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_3_;
release `DCTLPATH1.dramctl1_dram_dctl_dram_que_que_bank_idle_cnt_4_;
end
end
end // always
`else // ifdef GATE_SIM_DRAM
//////////////////////////////////////
// These are hacks, remove them later
reg [5:0] dv_cnt;
reg [5:0] rtw_dly_reg;
initial
begin
if (!$value$plusargs("SYSTEM_DV_MATCH=%d", dv_cnt)) begin
dv_cnt = 2 ;
end
case(dv_cnt)
3 : rtw_dly_reg = 1;
4 : rtw_dly_reg = 2;
default : rtw_dly_reg = 0;
endcase
if ($test$plusargs("SYSTEM_DV_MATCH")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_data_del_cnt = dv_cnt;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_data_del_cnt = dv_cnt;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_data_del_cnt = dv_cnt;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_data_del_cnt = dv_cnt;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.rtw_dly_reg = rtw_dly_reg;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.rtw_dly_reg = rtw_dly_reg;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.rtw_dly_reg = rtw_dly_reg;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.rtw_dly_reg = rtw_dly_reg;
end
end
reg dram_i2c_enabled;
// set the corresponding registers to achieve this
initial
begin
if ($test$plusargs("LO_STACK_RANK_BIT")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_addr_bank_low_sel = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_addr_bank_low_sel = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_addr_bank_low_sel = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_addr_bank_low_sel = 1'b1;
end
end
initial
begin
// This is included to keep the DRAM SAT tests transperent to the
// no_slam_init related changes. no_slam_init is now in dram.config,
// so by default there is no slamming, but we need slamming in rank,stack/etc
// regressions, so add this SLAM_INIT_CMP, so as to nothing changes for SAT
`ifdef DRAM_SAT
if ($test$plusargs("SLAM_INIT_CMP")) begin
`else
if (!$test$plusargs("no_dram_slam_init")) begin
`endif // ifdef DRAM_SAT
dram_i2c_enabled = 1'b0;
if ( ($test$plusargs("RANK_DIMM")) && ($test$plusargs("STACK_DIMM")) &&
($test$plusargs("DRAM_I2C") == 0) ) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h4;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h4;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h4;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h4;
end
else if ( ($test$plusargs("RANK_DIMM")) && ($test$plusargs("DRAM_I2C") == 0) ) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_rank1_present = 1'b1;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
end
else if ( ($test$plusargs("STACK_DIMM")) && ($test$plusargs("DRAM_I2C") == 0) ) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.chip_config_reg[0] = 1'b1;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_tot_ranks[2:0] = 3'h2;
end
if ($test$plusargs("DRAM_SCRUB")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_data_scrub_enabled = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_data_scrub_enabled = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_data_scrub_enabled = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_data_scrub_enabled = 1'b1;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.chip_config_reg[20:9] =12'h10;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.chip_config_reg[20:9] =12'h10;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.chip_config_reg[20:9] =12'h10;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.chip_config_reg[20:9] =12'h10;
end
if ($test$plusargs("DIMM_SIZE_1G")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
end
else if ($test$plusargs("DIMM_SIZE_512")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5] =12'he;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
end
else if ($test$plusargs("DIMM_SIZE_256")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5] =12'hd;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5] =12'hd;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.chip_config_reg[8:5] =12'hd;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.chip_config_reg[8:5] =12'hd;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_eight_bank_mode = 1'b0;
end
else begin
// use default = 2G b
end
`ifdef TWO_CH_DELAY_LONG_VERSION
`define TWO_CHANNEL_DELAY #1300000
`else
`define TWO_CHANNEL_DELAY #600000
`endif
if ($test$plusargs("2CHANNEL_01")) begin
`TWO_CHANNEL_DELAY
//force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_channel_disabled = 1'b1;
//force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_channel_disabled = 1'b1;
force `DRAM_PATH2.que_channel_disabled = 1'b1;
force `DRAM_PATH3.que_channel_disabled = 1'b1;
end
else if ($test$plusargs("2CHANNEL_23")) begin
`TWO_CHANNEL_DELAY
//force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_channel_disabled = 1'b1;
//force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_channel_disabled = 1'b1;
force `DRAM_PATH0.que_channel_disabled = 1'b1;
force `DRAM_PATH1.que_channel_disabled = 1'b1;
end
else if ($test$plusargs("2CHANNEL_03")) begin
`TWO_CHANNEL_DELAY
//force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_channel_disabled = 1'b1;
//force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_channel_disabled = 1'b1;
force `DRAM_PATH2.que_channel_disabled = 1'b1;
force `DRAM_PATH1.que_channel_disabled = 1'b1;
end
else if ($test$plusargs("2CHANNEL_21") || $test$plusargs("2CHANNEL_12") ) begin
`TWO_CHANNEL_DELAY
//force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_channel_disabled = 1'b1;
//force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_channel_disabled = 1'b1;
force `DRAM_PATH0.que_channel_disabled = 1'b1;
force `DRAM_PATH3.que_channel_disabled = 1'b1;
end
end // no_slam_init
end
initial
begin
if (! $value$plusargs("force_cas_latency=%d", cas_latency)) begin
cas_latency = 3 ;
end
end
// This is env fix so that logic does not have to wait 200us on POR
always @(posedge `DCTLPATH0.dramctl0.dram_dctl.dram_que.clk)
begin
if($test$plusargs("NO_BYPASS_POR_WAIT")) begin
if($test$plusargs("BYPASS_WMR_WAIT")) begin
// if warm reset and waiting for 200 us clocks
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_pos == 5'he)
begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
end else begin
release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt;
end
end
end else begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.dram_io_clk_enable = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.dram_io_clk_enable = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.dram_io_clk_enable = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.dram_io_clk_enable = 1'b1;
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_cke_reg = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_cke_reg = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_cke_reg = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_cke_reg = 1'b1;
// If I2C read disabled or enabled and rd_done then init
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_pos == 5'h0)
begin
// when warm reset then dont force
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_hw_selfrsh == 1'b0 )
begin
// If we need to change the default parameters and issue que_init from diag
if (!$test$plusargs("QUE_INIT_FROM_DIAG")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_init = 1'b1;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_init = 1'b1;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_init = 1'b1;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_init = 1'b1;
end
if($test$plusargs("force_cas_latency")) begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.mode_reg[6:4] = cas_latency;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.mode_reg[6:4] = cas_latency;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.mode_reg[6:4] = cas_latency;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.mode_reg[6:4] = cas_latency;
// In DRAM SAT register update is done, this is only for cmp
`ifdef DRAM_SAT
`else
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.rp_reg = cas_latency;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.rp_reg = cas_latency;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.rp_reg = cas_latency;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.rp_reg = cas_latency;
`endif
//force `DCTLPATH0.dramctl0.dram_dctl.dram_que.dal_reg = 4'hc;
//force `DCTLPATH0.dramctl1.dram_dctl.dram_que.dal_reg = 4'hc;
//force `DCTLPATH1.dramctl0.dram_dctl.dram_que.dal_reg = 4'hc;
//force `DCTLPATH1.dramctl1.dram_dctl.dram_que.dal_reg = 4'hc;
end
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
end
end
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_pos == 5'h1)
begin
release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_init;
release `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_init;
release `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_init;
release `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_init;
//release `DCTLPATH0.dramctl0.dram_dctl.dram_que.dram_io_clk_enable;
//release `DCTLPATH0.dramctl1.dram_dctl.dram_que.dram_io_clk_enable;
//release `DCTLPATH1.dramctl0.dram_dctl.dram_que.dram_io_clk_enable;
//release `DCTLPATH1.dramctl1.dram_dctl.dram_que.dram_io_clk_enable;
//release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_cke_reg;
//release `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_cke_reg;
//release `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_cke_reg;
//release `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_cke_reg;
release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt;
end
// if warm reset and waiting for 200 us clocks
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_pos == 5'he)
begin
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
force `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt = 5'h1c;
end else begin
release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH0.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH1.dramctl0.dram_dctl.dram_que.que_bank_idle_cnt;
release `DCTLPATH1.dramctl1.dram_dctl.dram_que.que_bank_idle_cnt;
end
end // NO_BYPASS_POR_WAIT
end // end always
// Added for bumping up the scrub counter
always @(posedge `DCTLPATH0.dramctl0.dram_dctl.dram_que.clk)
begin
if ($test$plusargs("SCRB_ADDR_BUMPUP")) begin
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_write_req == 1'b1)
begin
// If CAS is 2 ( que_scrb_cas_addr = 3) , bump it to 1fc
//if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_cas_addr == 9'h2)
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_cas_addr == 9'h1)
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_cas_addr = 9'h1fe;
// If RAS is 2 ( que_scrb_ras_addr = 3) , bump it to 7ffc
if(`DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_ras_addr == 15'h2)
force `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_ras_addr = 15'h7ffe;
end
else
begin
release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_cas_addr;
release `DCTLPATH0.dramctl0.dram_dctl.dram_que.que_scrb_ras_addr;
end
end // testplus arg
end // end always
//`ifdef WARM_RESET
initial
begin
if($test$plusargs("WARM_RESET")) begin
if($test$plusargs("POWER_THROTTLE")) begin
#6000000;
end
#300000;
#1905670;
//force `DCTLPATH0.dram_arst_l = 1'b1; This is not changed for warm reset.
force `DCTLPATH0.clspine_dram_selfrsh = 1'b1; // set refresh = 1 for warm refresh
#2000;
force `DCTLPATH0.jbus_grst_l = 1'b0;
force `DCTLPATH0.cmp_grst_l = 1'b0;
#2000;
//force `DCTLPATH0.clspine_dram_selfrsh = 1'b1; // set refresh = 1 for warm refresh
#1000000;
//#250000;
force `DCTLPATH0.dram_grst_l = 1'b0;
#700000;
force `DCTLPATH0.jbus_grst_l = 1'b1;
force `DCTLPATH0.cmp_grst_l = 1'b1;
force `DCTLPATH0.dram_grst_l = 1'b1;
#2000;
force `DCTLPATH0.clspine_dram_selfrsh = 1'b0; // set refresh = 1 for warm refresh
#700000;
release `DCTLPATH0.jbus_grst_l;
release `DCTLPATH0.cmp_grst_l;
release `DCTLPATH0.dram_grst_l;
end
end
//`endif
`endif // ifdef GATE_SIM_DRAM
endmodule //
// Local Variables:
// verilog-library-directories:("." "../../../design/sys/iop/rtl" "../../../design/sys/iop/dram/rtl""../../../design/sys/iop/pad_ddr02/rtl" "../../../design/sys/iop/pad_ddr13/rtl")
// verilog-library-extensions:(".v" ".h")
// End:
|
(* This program is free software; you can redistribute it and/or *)
(* modify it under the terms of the GNU Lesser General Public License *)
(* as published by the Free Software Foundation; either version 2.1 *)
(* of the License, or (at your option) any later version. *)
(* *)
(* This program is distributed in the hope that it will be useful, *)
(* but WITHOUT ANY WARRANTY; without even the implied warranty of *)
(* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *)
(* GNU General Public License for more details. *)
(* *)
(* You should have received a copy of the GNU Lesser General Public *)
(* License along with this program; if not, write to the Free *)
(* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA *)
(* 02110-1301 USA *)
(** This file includes random facts about Integers (and natural numbers) which are not found in the standard library. Some of the lemma here are not used in the QArith developement but are rather useful.
*)
Require Export ZArith.
Require Export ZArithRing.
Tactic Notation "ElimCompare" constr(c) constr(d) := elim_compare c d.
Ltac Flip :=
apply Zgt_lt || apply Zlt_gt || apply Zle_ge || apply Zge_le; assumption.
Ltac Falsum :=
try intro; apply False_ind;
repeat
match goal with
| id1:(~ ?X1) |- ?X2 =>
(apply id1; assumption || reflexivity) || clear id1
end.
Ltac Step_l a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X1 with a; [ idtac | try ring ]
end.
Ltac Step_r a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X2 with a; [ idtac | try ring ]
end.
Ltac CaseEq formula :=
generalize (refl_equal formula); pattern formula at -1 in |- *;
case formula.
Lemma pair_1 : forall (A B : Set) (H : A * B), H = pair (fst H) (snd H).
Proof.
intros.
case H.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma pair_2 :
forall (A B : Set) (H1 H2 : A * B),
fst H1 = fst H2 -> snd H1 = snd H2 -> H1 = H2.
Proof.
intros A B H1 H2.
case H1.
case H2.
simpl in |- *.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Section projection.
Variable A : Set.
Variable P : A -> Prop.
Definition projP1 (H : sig P) := let (x, h) := H in x.
Definition projP2 (H : sig P) :=
let (x, h) as H return (P (projP1 H)) := H in h.
End projection.
(*###########################################################################*)
(* Declaring some realtions on natural numbers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma le_stepl: forall x y z, le x y -> x=z -> le z y.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma le_stepr: forall x y z, le x y -> y=z -> le x z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma lt_stepl: forall x y z, lt x y -> x=z -> lt z y.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma lt_stepr: forall x y z, lt x y -> y=z -> lt x z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma neq_stepl:forall (x y z:nat), x<>y -> x=z -> z<>y.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma neq_stepr:forall (x y z:nat), x<>y -> y=z -> x<>z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step le_stepl.
Declare Right Step le_stepr.
Declare Left Step lt_stepl.
Declare Right Step lt_stepr.
Declare Left Step neq_stepl.
Declare Right Step neq_stepr.
(*###########################################################################*)
(** Some random facts about natural numbers, positive numbers and integers *)
(*###########################################################################*)
Lemma not_O_S : forall n : nat, n <> 0 -> {p : nat | n = S p}.
Proof.
intros [| np] Hn; [ exists 0; apply False_ind; apply Hn | exists np ];
reflexivity.
Qed.
Lemma lt_minus_neq : forall m n : nat, m < n -> n - m <> 0.
Proof.
intros.
omega.
Qed.
Lemma lt_minus_eq_0 : forall m n : nat, m < n -> m - n = 0.
Proof.
intros.
omega.
Qed.
Lemma le_plus_Sn_1_SSn : forall n : nat, S n + 1 <= S (S n).
Proof.
intros.
omega.
Qed.
Lemma le_plus_O_l : forall p q : nat, p + q <= 0 -> p = 0.
Proof.
intros; omega.
Qed.
Lemma le_plus_O_r : forall p q : nat, p + q <= 0 -> q = 0.
Proof.
intros; omega.
Qed.
Lemma minus_pred : forall m n : nat, 0 < n -> pred m - pred n = m - n.
Proof.
intros.
omega.
Qed.
(*###########################################################################*)
(* Declaring some realtions on integers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma Zle_stepl: forall x y z, (x<=y)%Z -> x=z -> (z<=y)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zle_stepr: forall x y z, (x<=y)%Z -> y=z -> (x<=z)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepl: forall x y z, (x<y)%Z -> x=z -> (z<y)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepr: forall x y z, (x<y)%Z -> y=z -> (x<z)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zneq_stepl:forall (x y z:Z), (x<>y)%Z -> x=z -> (z<>y)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma Zneq_stepr:forall (x y z:Z), (x<>y)%Z -> y=z -> (x<>z)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step Zle_stepl.
Declare Right Step Zle_stepr.
Declare Left Step Zlt_stepl.
Declare Right Step Zlt_stepr.
Declare Left Step Zneq_stepl.
Declare Right Step Zneq_stepr.
(*###########################################################################*)
(** Informative case analysis *)
(*###########################################################################*)
Lemma Zlt_cotrans :
forall x y : Z, (x < y)%Z -> forall z : Z, {(x < z)%Z} + {(z < y)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x z).
intro.
left.
assumption.
intro.
right.
apply Zle_lt_trans with (m := x).
apply Zge_le.
assumption.
assumption.
Qed.
Lemma Zlt_cotrans_pos :
forall x y : Z, (0 < x + y)%Z -> {(0 < x)%Z} + {(0 < y)%Z}.
Proof.
intros.
case (Zlt_cotrans 0 (x + y) H x).
intro.
left.
assumption.
intro.
right.
apply Zplus_lt_reg_l with (p := x).
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_cotrans_neg :
forall x y : Z, (x + y < 0)%Z -> {(x < 0)%Z} + {(y < 0)%Z}.
Proof.
intros x y H; case (Zlt_cotrans (x + y) 0 H x); intro Hxy;
[ right; apply Zplus_lt_reg_l with (p := x); rewrite Zplus_0_r | left ];
assumption.
Qed.
Lemma not_Zeq_inf : forall x y : Z, x <> y -> {(x < y)%Z} + {(y < x)%Z}.
Proof.
intros.
case Z_lt_ge_dec with x y.
intro.
left.
assumption.
intro H0.
generalize (Zge_le _ _ H0).
intro.
case (Z_le_lt_eq_dec _ _ H1).
intro.
right.
assumption.
intro.
apply False_rec.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec : forall x y : Z, {(x < y)%Z} + {(x > y)%Z} + {x = y}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro H.
left.
left.
assumption.
intro H.
generalize (Zge_le _ _ H).
intro H0.
case (Z_le_lt_eq_dec y x H0).
intro H1.
left.
right.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec' : forall x y : Z, {(x < y)%Z} + {(y < x)%Z} + {x = y}.
Proof.
intros x y.
case (Z_eq_dec x y); intro H;
[ right; assumption | left; apply (not_Zeq_inf _ _ H) ].
Qed.
Lemma Z_lt_le_dec : forall x y : Z, {(x < y)%Z} + {(y <= x)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro.
left.
assumption.
intro.
right.
apply Zge_le.
assumption.
Qed.
Lemma Z_le_lt_dec : forall x y : Z, {(x <= y)%Z} + {(y < x)%Z}.
Proof.
intros; case (Z_lt_le_dec y x); [ right | left ]; assumption.
Qed.
Lemma Z_lt_lt_S_eq_dec :
forall x y : Z, (x < y)%Z -> {(x + 1 < y)%Z} + {(x + 1)%Z = y}.
Proof.
intros.
generalize (Zlt_le_succ _ _ H).
unfold Zsucc in |- *.
apply Z_le_lt_eq_dec.
Qed.
Lemma quadro_leq_inf :
forall a b c d : Z,
{(c <= a)%Z /\ (d <= b)%Z} + {~ ((c <= a)%Z /\ (d <= b)%Z)}.
Proof.
intros.
case (Z_lt_le_dec a c).
intro z.
right.
intro.
elim H.
intros.
generalize z.
apply Zle_not_lt.
assumption.
intro.
case (Z_lt_le_dec b d).
intro z0.
right.
intro.
elim H.
intros.
generalize z0.
apply Zle_not_lt.
assumption.
intro.
left.
split.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** General auxiliary lemmata *)
(*###########################################################################*)
Lemma Zminus_eq : forall x y : Z, (x - y)%Z = 0%Z -> x = y.
Proof.
intros.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
unfold Zminus in H.
rewrite Zplus_comm.
assumption.
Qed.
Lemma Zlt_minus : forall a b : Z, (b < a)%Z -> (0 < a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_lt_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zle_minus : forall a b : Z, (b <= a)%Z -> (0 <= a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_le_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zlt_plus_plus :
forall m n p q : Z, (m < n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
apply Zlt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_lt_compat_l.
assumption.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zgt_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
intros.
apply Zgt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_gt_compat_l.
assumption.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zle_lt_plus_plus :
forall m n p q : Z, (m <= n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq m n).
assumption.
intro.
apply Zlt_plus_plus.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zge_gt_plus_plus :
forall m n p q : Z, (m >= n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq n m).
apply Zge_le.
assumption.
intro.
apply Zgt_plus_plus.
apply Zlt_gt.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zgt_ge_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p >= q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
rewrite Zplus_comm.
replace (n + q)%Z with (q + n)%Z.
apply Zge_gt_plus_plus.
assumption.
assumption.
apply Zplus_comm.
Qed.
Lemma Zlt_resp_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x + y)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zlt_plus_plus; assumption.
Qed.
Lemma Zle_resp_neg :
forall x y : Z, (x <= 0)%Z -> (y <= 0)%Z -> (x + y <= 0)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zplus_le_compat; assumption.
Qed.
Lemma Zlt_pos_opp : forall x : Z, (0 < x)%Z -> (- x < 0)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_neg_opp : forall x : Z, (x < 0)%Z -> (0 < - x)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_neg_opp : forall x : Z, (x <= 0)%Z -> (0 <= - x)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_pos_opp : forall x : Z, (0 <= x)%Z -> (- x <= 0)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zge_opp : forall x y : Z, (x <= y)%Z -> (- x >= - y)%Z.
Proof.
intros.
apply Zle_ge.
apply Zplus_le_reg_l with (p := (x + y)%Z).
ring_simplify (x + y + - y)%Z (x + y + - x)%Z.
assumption.
Qed.
(* Omega can't solve this *)
Lemma Zmult_pos_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_neg : forall x y : Z, (x < 0)%Z -> (y < 0)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_pos : forall x y : Z, (x < 0)%Z -> (0 < y)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_pos_neg : forall x y : Z, (0 < x)%Z -> (y < 0)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Hint Resolve Zmult_pos_pos Zmult_neg_neg Zmult_neg_pos Zmult_pos_neg: zarith.
Lemma Zle_reg_mult_l :
forall x y a : Z, (0 < a)%Z -> (x <= y)%Z -> (a * x <= a * y)%Z.
Proof.
intros.
apply Zplus_le_reg_l with (p := (- a * x)%Z).
ring_simplify (- a * x + a * x)%Z.
replace (- a * x + a * y)%Z with ((y - x) * a)%Z.
apply Zmult_gt_0_le_0_compat.
apply Zlt_gt.
assumption.
unfold Zminus in |- *.
apply Zle_left.
assumption.
ring.
Qed.
Lemma Zsimpl_plus_l_dep :
forall x y m n : Z, (x + m)%Z = (y + n)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zsimpl_plus_r_dep :
forall x y m n : Z, (m + x)%Z = (n + y)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite Zplus_comm.
rewrite Zplus_comm with x n.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zmult_simpl :
forall n m p q : Z, n = m -> p = q -> (n * p)%Z = (m * q)%Z.
Proof.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Lemma Zsimpl_mult_l :
forall n m p : Z, n <> 0%Z -> (n * m)%Z = (n * p)%Z -> m = p.
Proof.
intros.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + p)%Z with 0%Z.
apply Zmult_integral_l with (n := n).
assumption.
replace ((- p + m) * n)%Z with (n * m + - (n * p))%Z.
apply Zegal_left.
assumption.
ring.
ring.
Qed.
Lemma Zlt_reg_mult_l :
forall x y z : Z, (x > 0)%Z -> (y < z)%Z -> (x * y < x * z)%Z. (*QA*)
Proof.
intros.
case (Zcompare_Gt_spec x 0).
unfold Zgt in H.
assumption.
intros.
cut (x = Zpos x0).
intro.
rewrite H2.
unfold Zlt in H0.
unfold Zlt in |- *.
cut ((Zpos x0 * y ?= Zpos x0 * z)%Z = (y ?= z)%Z).
intro.
exact (trans_eq H3 H0).
apply Zcompare_mult_compat.
cut (x = (x + - (0))%Z).
intro.
exact (trans_eq H2 H1).
simpl in |- *.
apply (sym_eq (A:=Z)).
exact (Zplus_0_r x).
Qed.
Lemma Zlt_opp : forall x y : Z, (x < y)%Z -> (- x > - y)%Z. (*QA*)
Proof.
intros.
red in |- *.
apply sym_eq.
cut (Datatypes.Gt = (y ?= x)%Z).
intro.
cut ((y ?= x)%Z = (- x ?= - y)%Z).
intro.
exact (trans_eq H0 H1).
exact (Zcompare_opp y x).
apply sym_eq.
exact (Zlt_gt x y H).
Qed.
Lemma Zlt_conv_mult_l :
forall x y z : Z, (x < 0)%Z -> (y < z)%Z -> (x * y > x * z)%Z. (*QA*)
Proof.
intros.
cut (- x > 0)%Z.
intro.
cut (- x * y < - x * z)%Z.
intro.
cut (- (- x * y) > - (- x * z))%Z.
intro.
cut (- - (x * y) > - - (x * z))%Z.
intro.
cut ((- - (x * y))%Z = (x * y)%Z).
intro.
rewrite H5 in H4.
cut ((- - (x * z))%Z = (x * z)%Z).
intro.
rewrite H6 in H4.
assumption.
exact (Zopp_involutive (x * z)).
exact (Zopp_involutive (x * y)).
cut ((- (- x * y))%Z = (- - (x * y))%Z).
intro.
rewrite H4 in H3.
cut ((- (- x * z))%Z = (- - (x * z))%Z).
intro.
rewrite H5 in H3.
assumption.
cut ((- x * z)%Z = (- (x * z))%Z).
intro.
exact (f_equal Zopp H5).
exact (Zopp_mult_distr_l_reverse x z).
cut ((- x * y)%Z = (- (x * y))%Z).
intro.
exact (f_equal Zopp H4).
exact (Zopp_mult_distr_l_reverse x y).
exact (Zlt_opp (- x * y) (- x * z) H2).
exact (Zlt_reg_mult_l (- x) y z H1 H0).
exact (Zlt_opp x 0 H).
Qed.
Lemma Zgt_not_eq : forall x y : Z, (x > y)%Z -> x <> y. (*QA*)
Proof.
intros.
cut (y < x)%Z.
intro.
cut (y <> x).
intro.
red in |- *.
intros.
cut (y = x).
intros.
apply H1.
assumption.
exact (sym_eq H2).
exact (Zorder.Zlt_not_eq y x H0).
exact (Zgt_lt x y H).
Qed.
Lemma Zmult_resp_nonzero :
forall x y : Z, x <> 0%Z -> y <> 0%Z -> (x * y)%Z <> 0%Z.
Proof.
intros x y Hx Hy Hxy.
apply Hx.
apply Zmult_integral_l with y; assumption.
Qed.
Lemma Zopp_app : forall y : Z, y <> 0%Z -> (- y)%Z <> 0%Z.
Proof.
intros.
intro.
apply H.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
rewrite H0.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_neq_Zlt : forall a b : Z, (a <= b)%Z -> b <> a -> (a < b)%Z.
Proof.
intros a b H H0.
case (Z_le_lt_eq_dec _ _ H); trivial.
intro; apply False_ind; apply H0; symmetry in |- *; assumption.
Qed.
Lemma not_Zle_lt : forall x y : Z, ~ (y <= x)%Z -> (x < y)%Z.
Proof.
intros; apply Zgt_lt; apply Znot_le_gt; assumption.
Qed.
Lemma not_Zlt : forall x y : Z, ~ (y < x)%Z -> (x <= y)%Z.
Proof.
intros x y H1 H2; apply H1; apply Zgt_lt; assumption.
Qed.
Lemma Zmult_absorb :
forall x y z : Z, x <> 0%Z -> (x * y)%Z = (x * z)%Z -> y = z. (*QA*)
Proof.
intros.
case (dec_eq y z).
intro.
assumption.
intro.
case (not_Zeq y z).
assumption.
intro.
case (not_Zeq x 0).
assumption.
intro.
apply False_ind.
cut (x * y > x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zgt_not_eq (x * y) (x * z) H4).
exact (Zlt_conv_mult_l x y z H3 H2).
intro.
apply False_ind.
cut (x * y < x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zorder.Zlt_not_eq (x * y) (x * z) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x y z H4 H2).
exact (Zlt_gt 0 x H3).
intro.
apply False_ind.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H4.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H3).
apply False_ind.
case (not_Zeq x 0).
assumption.
intro.
cut (x * z > x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zgt_not_eq (x * z) (x * y) H4).
exact (Zlt_conv_mult_l x z y H3 H2).
intro.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x z y H4 H2).
exact (Zlt_gt 0 x H3).
Qed.
Lemma Zlt_mult_mult :
forall a b c d : Z,
(0 < a)%Z -> (0 < d)%Z -> (a < b)%Z -> (c < d)%Z -> (a * c < b * d)%Z.
Proof.
intros.
apply Zlt_trans with (a * d)%Z.
apply Zlt_reg_mult_l.
Flip.
assumption.
rewrite Zmult_comm.
rewrite Zmult_comm with b d.
apply Zlt_reg_mult_l.
Flip.
assumption.
Qed.
Lemma Zgt_mult_conv_absorb_l :
forall a x y : Z, (a < 0)%Z -> (a * x > a * y)%Z -> (x < y)%Z. (*QC*)
Proof.
intros.
case (dec_eq x y).
intro.
apply False_ind.
rewrite H1 in H0.
cut ((a * y)%Z = (a * y)%Z).
change ((a * y)%Z <> (a * y)%Z) in |- *.
apply Zgt_not_eq.
assumption.
trivial.
intro.
case (not_Zeq x y H1).
trivial.
intro.
apply False_ind.
cut (a * y > a * x)%Z.
apply Zgt_asym with (m := (a * y)%Z) (n := (a * x)%Z).
assumption.
apply Zlt_conv_mult_l.
assumption.
assumption.
Qed.
Lemma Zgt_mult_reg_absorb_l :
forall a x y : Z, (a > 0)%Z -> (a * x > a * y)%Z -> (x > y)%Z. (*QC*)
Proof.
intros.
cut (- - a > - - (0))%Z.
intro.
cut (- a < - (0))%Z.
simpl in |- *.
intro.
replace x with (- - x)%Z.
replace y with (- - y)%Z.
apply Zlt_opp.
apply Zgt_mult_conv_absorb_l with (a := (- a)%Z) (x := (- x)%Z).
assumption.
rewrite Zmult_opp_opp.
rewrite Zmult_opp_opp.
assumption.
apply Zopp_involutive.
apply Zopp_involutive.
apply Zgt_lt.
apply Zlt_opp.
apply Zgt_lt.
assumption.
simpl in |- *.
rewrite Zopp_involutive.
assumption.
Qed.
Lemma Zopp_Zlt : forall x y : Z, (y < x)%Z -> (- x < - y)%Z.
Proof.
intros x y Hyx.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
Flip.
ring.
ring.
Qed.
Lemma Zmin_cancel_Zlt : forall x y : Z, (- x < - y)%Z -> (y < x)%Z.
Proof.
intros.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
apply Zlt_gt.
assumption.
ring.
ring.
Qed.
Lemma Zmult_cancel_Zle :
forall a x y : Z, (a < 0)%Z -> (a * x <= a * y)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * x)).
apply Zle_lt_trans with (m := (a * y)%Z).
assumption.
apply Zgt_lt.
apply Zlt_conv_mult_l.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zlt_mult_cancel_l :
forall x y z : Z, (0 < x)%Z -> (x * y < x * z)%Z -> (y < z)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with x.
apply Zlt_gt.
assumption.
apply Zlt_gt.
assumption.
Qed.
Lemma Zmin_cancel_Zle : forall x y : Z, (- x <= - y)%Z -> (y <= x)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
assumption.
ring.
ring.
Qed.
Lemma Zmult_resp_Zle :
forall a x y : Z, (0 < a)%Z -> (a * y <= a * x)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * y)).
apply Zle_lt_trans with (m := (a * x)%Z).
assumption.
apply Zlt_reg_mult_l.
apply Zlt_gt.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zopp_Zle : forall x y : Z, (y <= x)%Z -> (- x <= - y)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
assumption.
clear y H; ring.
clear x H; ring.
Qed.
Lemma Zle_lt_eq_S : forall x y : Z, (x <= y)%Z -> (y < x + 1)%Z -> y = x.
Proof.
intros.
case (Z_le_lt_eq_dec x y H).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H1).
intro.
apply (Zlt_not_le y (x + 1) H0).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
intro H1.
symmetry in |- *.
assumption.
Qed.
Lemma Zlt_le_eq_S :
forall x y : Z, (x < y)%Z -> (y <= x + 1)%Z -> y = (x + 1)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec y (x + 1) H0).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H).
intro.
apply (Zlt_not_le y (x + 1) H1).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
trivial.
Qed.
Lemma double_not_equal_zero :
forall c d : Z, ~ (c = 0%Z /\ d = 0%Z) -> c <> d \/ c <> 0%Z.
Proof.
intros.
case (Z_zerop c).
intro.
rewrite e.
left.
apply sym_not_eq.
intro.
apply H; repeat split; assumption.
intro; right; assumption.
Qed.
Lemma triple_not_equal_zero :
forall a b c : Z,
~ (a = 0%Z /\ b = 0%Z /\ c = 0%Z) -> a <> 0%Z \/ b <> 0%Z \/ c <> 0%Z.
Proof.
intros a b c H; case (Z_zerop a); intro Ha;
[ case (Z_zerop b); intro Hb;
[ case (Z_zerop c); intro Hc;
[ apply False_ind; apply H; repeat split | right; right ]
| right; left ]
| left ]; assumption.
Qed.
Lemma mediant_1 :
forall m n m' n' : Z, (m' * n < m * n')%Z -> ((m + m') * n < m * (n + n'))%Z.
Proof.
intros.
rewrite Zmult_plus_distr_r.
rewrite Zmult_plus_distr_l.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma mediant_2 :
forall m n m' n' : Z,
(m' * n < m * n')%Z -> (m' * (n + n') < (m + m') * n')%Z.
Proof.
intros.
rewrite Zmult_plus_distr_l.
rewrite Zmult_plus_distr_r.
apply Zplus_lt_compat_r.
assumption.
Qed.
Lemma mediant_3 :
forall a b m n m' n' : Z,
(0 <= a * m + b * n)%Z ->
(0 <= a * m' + b * n')%Z -> (0 <= a * (m + m') + b * (n + n'))%Z.
Proof.
intros.
replace (a * (m + m') + b * (n + n'))%Z with
(a * m + b * n + (a * m' + b * n'))%Z.
apply Zplus_le_0_compat.
assumption.
assumption.
ring.
Qed.
Lemma fraction_lt_trans :
forall a b c d e f : Z,
(0 < b)%Z ->
(0 < d)%Z ->
(0 < f)%Z -> (a * d < c * b)%Z -> (c * f < e * d)%Z -> (a * f < e * b)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with d.
Flip.
apply Zgt_trans with (c * b * f)%Z.
replace (d * (e * b))%Z with (b * (e * d))%Z.
replace (c * b * f)%Z with (b * (c * f))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
replace (c * b * f)%Z with (f * (c * b))%Z.
replace (d * (a * f))%Z with (f * (a * d))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
Qed.
Lemma square_pos : forall a : Z, a <> 0%Z -> (0 < a * a)%Z.
Proof.
intros [| p| p]; intros; [ Falsum | constructor | constructor ].
Qed.
Hint Resolve square_pos: zarith.
(*###########################################################################*)
(** Properties of positive numbers, mapping between Z and nat *)
(*###########################################################################*)
Definition Z2positive (z : Z) :=
match z with
| Zpos p => p
| Zneg p => p
| Z0 => 1%positive
end.
Lemma ZL9 : forall p : positive, Z_of_nat (nat_of_P p) = Zpos p. (*QF*)
Proof.
intro.
cut (exists h : nat, nat_of_P p = S h).
intro.
case H.
intros.
unfold Z_of_nat in |- *.
rewrite H0.
apply f_equal with (A := positive) (B := Z) (f := Zpos).
cut (P_of_succ_nat (nat_of_P p) = P_of_succ_nat (S x)).
intro.
rewrite P_of_succ_nat_o_nat_of_P_eq_succ in H1.
cut (Ppred (Psucc p) = Ppred (P_of_succ_nat (S x))).
intro.
rewrite Ppred_succ in H2.
simpl in H2.
rewrite Ppred_succ in H2.
apply sym_eq.
assumption.
apply f_equal with (A := positive) (B := positive) (f := Ppred).
assumption.
apply f_equal with (f := P_of_succ_nat).
assumption.
apply ZL4.
Qed.
Coercion Z_of_nat : nat >-> Z.
Lemma ZERO_lt_POS : forall p : positive, (0 < Zpos p)%Z.
Proof.
intros.
constructor.
Qed.
Lemma POS_neq_ZERO : forall p : positive, Zpos p <> 0%Z.
Proof.
intros.
apply sym_not_eq.
apply Zorder.Zlt_not_eq.
apply ZERO_lt_POS.
Qed.
Lemma NEG_neq_ZERO : forall p : positive, Zneg p <> 0%Z.
Proof.
intros.
apply Zorder.Zlt_not_eq.
unfold Zlt in |- *.
constructor.
Qed.
Lemma POS_resp_eq : forall p0 p1 : positive, Zpos p0 = Zpos p1 -> p0 = p1.
Proof.
intros.
injection H.
trivial.
Qed.
Lemma nat_nat_pos : forall m n : nat, ((m + 1) * (n + 1) > 0)%Z. (*QF*)
Proof.
intros.
apply Zlt_gt.
cut (Z_of_nat m + 1 > 0)%Z.
intro.
cut (0 < Z_of_nat n + 1)%Z.
intro.
cut ((Z_of_nat m + 1) * 0 < (Z_of_nat m + 1) * (Z_of_nat n + 1))%Z.
rewrite Zmult_0_r.
intro.
assumption.
apply Zlt_reg_mult_l.
assumption.
assumption.
change (0 < Zsucc (Z_of_nat n))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat n)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
apply Zlt_gt.
change (0 < Zsucc (Z_of_nat m))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat m)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
Qed.
Theorem S_predn : forall m : nat, m <> 0 -> S (pred m) = m. (*QF*)
Proof.
intros.
case (O_or_S m).
intro.
case s.
intros.
rewrite <- e.
rewrite <- pred_Sn with (n := x).
trivial.
intro.
apply False_ind.
apply H.
apply sym_eq.
assumption.
Qed.
Lemma absolu_1 : forall x : Z, Zabs_nat x = 0 -> x = 0%Z. (*QF*)
Proof.
intros.
case (dec_eq x 0).
intro.
assumption.
intro.
apply False_ind.
cut ((x < 0)%Z \/ (x > 0)%Z).
intro.
ElimCompare x 0%Z.
intro.
cut (x = 0%Z).
assumption.
cut ((x ?= 0)%Z = Datatypes.Eq -> x = 0%Z).
intro.
apply H3.
assumption.
apply proj1 with (B := x = 0%Z -> (x ?= 0)%Z = Datatypes.Eq).
change ((x ?= 0)%Z = Datatypes.Eq <-> x = 0%Z) in |- *.
apply Zcompare_Eq_iff_eq.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
change (x < 0)%Z in H2.
cut (0 > x)%Z.
intro.
cut (exists p : positive, (0 + - x)%Z = Zpos p).
simpl in |- *.
intro.
case H4.
intros.
cut (exists q : positive, x = Zneg q).
intro.
case H6.
intros.
rewrite H7.
unfold Zabs_nat in |- *.
generalize x1.
exact ZL4.
cut (x = (- Zpos x0)%Z).
simpl in |- *.
intro.
exists x0.
assumption.
cut ((- - x)%Z = x).
intro.
rewrite <- H6.
exact (f_equal Zopp H5).
apply Zopp_involutive.
apply Zcompare_Gt_spec.
assumption.
apply Zlt_gt.
assumption.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
cut (exists p : positive, (x + - (0))%Z = Zpos p).
simpl in |- *.
rewrite Zplus_0_r.
intro.
case H3.
intros.
rewrite H4.
unfold Zabs_nat in |- *.
generalize x0.
exact ZL4.
apply Zcompare_Gt_spec.
assumption.
(***)
cut ((x < 0)%Z \/ (0 < x)%Z).
intro.
apply
or_ind with (A := (x < 0)%Z) (B := (0 < x)%Z) (P := (x < 0)%Z \/ (x > 0)%Z).
intro.
left.
assumption.
intro.
right.
apply Zlt_gt.
assumption.
assumption.
apply not_Zeq.
assumption.
Qed.
Lemma absolu_2 : forall x : Z, x <> 0%Z -> Zabs_nat x <> 0. (*QF*)
Proof.
intros.
intro.
apply H.
apply absolu_1.
assumption.
Qed.
Lemma absolu_inject_nat : forall n : nat, Zabs_nat (Z_of_nat n) = n.
Proof.
simple induction n; simpl in |- *.
reflexivity.
intros.
apply nat_of_P_o_P_of_succ_nat_eq_succ.
Qed.
Lemma eq_inj : forall m n : nat, m = n :>Z -> m = n.
Proof.
intros.
generalize (f_equal Zabs_nat H).
intro.
rewrite (absolu_inject_nat m) in H0.
rewrite (absolu_inject_nat n) in H0.
assumption.
Qed.
Lemma lt_inj : forall m n : nat, (m < n)%Z -> m < n.
Proof.
intros.
omega.
Qed.
Lemma le_inj : forall m n : nat, (m <= n)%Z -> m <= n.
Proof.
intros.
omega.
Qed.
Lemma inject_nat_S_inf : forall x : Z, (0 < x)%Z -> {n : nat | x = S n}.
Proof.
intros [| p| p] Hp; try discriminate Hp.
exists (pred (nat_of_P p)).
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hp;
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma le_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x <= y)%Z -> Zabs_nat x <= Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy;
apply le_O_n ||
(try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end).
simpl in |- *.
apply le_inj.
do 2 rewrite ZL9.
assumption.
Qed.
Lemma lt_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x < y)%Z -> Zabs_nat x < Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy; inversion Hxy;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end; simpl in |- *; apply lt_inj; repeat rewrite ZL9;
assumption.
Qed.
Lemma absolu_plus :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> Zabs_nat (x + y) = Zabs_nat x + Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy; trivial;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end.
rewrite <- BinInt.Zpos_plus_distr.
unfold Zabs_nat in |- *.
apply nat_of_P_plus_morphism.
Qed.
Lemma pred_absolu :
forall x : Z, (0 < x)%Z -> pred (Zabs_nat x) = Zabs_nat (x - 1).
Proof.
intros x Hx.
generalize (Z_lt_lt_S_eq_dec 0 x Hx); simpl in |- *; intros [H1| H1];
[ replace (Zabs_nat x) with (Zabs_nat (x - 1 + 1));
[ idtac | apply f_equal with Z; auto with zarith ];
rewrite absolu_plus;
[ unfold Zabs_nat at 2, nat_of_P, Piter_op in |- *; omega
| auto with zarith
| intro; discriminate ]
| rewrite <- H1; reflexivity ].
Qed.
Definition pred_nat : forall (x : Z) (Hx : (0 < x)%Z), nat.
intros [| px| px] Hx; try abstract (discriminate Hx).
exact (pred (nat_of_P px)).
Defined.
Lemma pred_nat_equal :
forall (x : Z) (Hx1 Hx2 : (0 < x)%Z), pred_nat x Hx1 = pred_nat x Hx2.
Proof.
intros [| px| px] Hx1 Hx2; try (discriminate Hx1); trivial.
Qed.
Let pred_nat_unfolded_subproof px :
Pos.to_nat px <> 0.
Proof.
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma pred_nat_unfolded :
forall (x : Z) (Hx : (0 < x)%Z), x = S (pred_nat x Hx).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hx; apply pred_nat_unfolded_subproof.
Qed.
Lemma absolu_pred_nat :
forall (m : Z) (Hm : (0 < m)%Z), S (pred_nat m Hm) = Zabs_nat m.
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
reflexivity.
apply pred_nat_unfolded_subproof.
Qed.
Lemma pred_nat_absolu :
forall (m : Z) (Hm : (0 < m)%Z), pred_nat m Hm = Zabs_nat (m - 1).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite <- pred_absolu; reflexivity || assumption.
Qed.
Lemma minus_pred_nat :
forall (n m : Z) (Hn : (0 < n)%Z) (Hm : (0 < m)%Z) (Hnm : (0 < n - m)%Z),
S (pred_nat n Hn) - S (pred_nat m Hm) = S (pred_nat (n - m) Hnm).
Proof.
intros.
simpl in |- *.
destruct n; try discriminate Hn.
destruct m; try discriminate Hm.
unfold pred_nat at 1 2 in |- *.
rewrite minus_pred; try apply lt_O_nat_of_P.
apply eq_inj.
rewrite <- pred_nat_unfolded.
rewrite Znat.inj_minus1.
repeat rewrite ZL9.
reflexivity.
apply le_inj.
apply Zlt_le_weak.
repeat rewrite ZL9.
apply Zlt_O_minus_lt.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zsgn *)
(*###########################################################################*)
Lemma Zsgn_1 :
forall x : Z, {Zsgn x = 0%Z} + {Zsgn x = 1%Z} + {Zsgn x = (-1)%Z}. (*QF*)
Proof.
intros.
case x.
left.
left.
unfold Zsgn in |- *.
reflexivity.
intro.
simpl in |- *.
left.
right.
reflexivity.
intro.
right.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_2 : forall x : Z, Zsgn x = 0%Z -> x = 0%Z. (*QF*)
Proof.
intros [| p1| p1]; simpl in |- *; intro H; constructor || discriminate H.
Qed.
Lemma Zsgn_3 : forall x : Z, x <> 0%Z -> Zsgn x <> 0%Z. (*QF*)
Proof.
intro.
case x.
intros.
apply False_ind.
apply H.
reflexivity.
intros.
simpl in |- *.
discriminate.
intros.
simpl in |- *.
discriminate.
Qed.
Theorem Zsgn_4 : forall a : Z, a = (Zsgn a * Zabs_nat a)%Z. (*QF*)
Proof.
intro.
case a.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite Zmult_1_l.
symmetry in |- *.
apply ZL9.
intros.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite ZL9.
constructor.
Qed.
Theorem Zsgn_5 :
forall a b x y : Z,
x <> 0%Z ->
y <> 0%Z ->
(Zsgn a * x)%Z = (Zsgn b * y)%Z -> (Zsgn a * y)%Z = (Zsgn b * x)%Z. (*QF*)
Proof.
intros a b x y H H0.
case a.
case b.
simpl in |- *.
trivial.
intro.
unfold Zsgn in |- *.
intro.
rewrite Zmult_1_l in H1.
simpl in H1.
apply False_ind.
apply H0.
symmetry in |- *.
assumption.
intro.
unfold Zsgn in |- *.
intro.
apply False_ind.
apply H0.
apply Zopp_inj.
simpl in |- *.
transitivity (-1 * y)%Z.
constructor.
transitivity (0 * x)%Z.
symmetry in |- *.
assumption.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity y.
rewrite Zmult_1_l.
reflexivity.
transitivity (Zsgn b * (Zsgn b * y))%Z.
case (Zsgn_1 b).
intro.
case s.
intro.
apply False_ind.
apply H.
rewrite e in H1.
change ((1 * x)%Z = 0%Z) in H1.
rewrite Zmult_1_l in H1.
assumption.
intro.
rewrite e.
rewrite Zmult_1_l.
rewrite Zmult_1_l.
reflexivity.
intro.
rewrite e.
ring.
rewrite Zmult_1_l in H1.
rewrite H1.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity (Zsgn b * (-1 * (Zsgn b * y)))%Z.
case (Zsgn_1 b).
intros.
case s.
intro.
apply False_ind.
apply H.
apply Zopp_inj.
transitivity (-1 * x)%Z.
ring.
unfold Zopp in |- *.
rewrite e in H1.
transitivity (0 * y)%Z.
assumption.
simpl in |- *.
reflexivity.
intro.
rewrite e.
ring.
intro.
rewrite e.
ring.
rewrite <- H1.
ring.
Qed.
Lemma Zsgn_6 : forall x : Z, x = 0%Z -> Zsgn x = 0%Z.
Proof.
intros.
rewrite H.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_7 : forall x : Z, (x > 0)%Z -> Zsgn x = 1%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
Flip.
intros.
simpl in |- *.
reflexivity.
intros.
apply False_ind.
apply (Zlt_irrefl (Zneg p)).
apply Zlt_trans with 0%Z.
constructor.
Flip.
Qed.
Lemma Zsgn_7' : forall x : Z, (0 < x)%Z -> Zsgn x = 1%Z.
Proof.
intros; apply Zsgn_7; Flip.
Qed.
Lemma Zsgn_8 : forall x : Z, (x < 0)%Z -> Zsgn x = (-1)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
assumption.
intros.
apply False_ind.
apply (Zlt_irrefl 0).
apply Zlt_trans with (Zpos p).
constructor.
assumption.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_9 : forall x : Z, Zsgn x = 1%Z -> (0 < x)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
simpl in H.
discriminate.
intros.
constructor.
intros.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_10 : forall x : Z, Zsgn x = (-1)%Z -> (x < 0)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
discriminate.
intros.
apply False_ind.
discriminate.
intros.
constructor.
Qed.
Lemma Zsgn_11 : forall x : Z, (Zsgn x < 0)%Z -> (x < 0)%Z.
Proof.
intros.
apply Zsgn_10.
case (Zsgn_1 x).
intro.
apply False_ind.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply (H0 e).
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
discriminate.
trivial.
Qed.
Lemma Zsgn_12 : forall x : Z, (0 < Zsgn x)%Z -> (0 < x)%Z.
Proof.
intros.
apply Zsgn_9.
case (Zsgn_1 x).
intro.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
generalize (sym_eq e).
intro.
apply False_ind.
apply (H0 H1).
trivial.
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_13 : forall x : Z, (0 <= Zsgn x)%Z -> (0 <= x)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec 0 (Zsgn x) H).
intro.
apply Zlt_le_weak.
apply Zsgn_12.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
symmetry in |- *.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_14 : forall x : Z, (Zsgn x <= 0)%Z -> (x <= 0)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec (Zsgn x) 0 H).
intro.
apply Zlt_le_weak.
apply Zsgn_11.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_15 : forall x y : Z, Zsgn (x * y) = (Zsgn x * Zsgn y)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; constructor.
Qed.
Lemma Zsgn_16 :
forall x y : Z,
Zsgn (x * y) = 1%Z -> {(0 < x)%Z /\ (0 < y)%Z} + {(x < 0)%Z /\ (y < 0)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_17 :
forall x y : Z,
Zsgn (x * y) = (-1)%Z -> {(0 < x)%Z /\ (y < 0)%Z} + {(x < 0)%Z /\ (0 < y)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_18 : forall x y : Z, Zsgn (x * y) = 0%Z -> {x = 0%Z} + {y = 0%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right | right ]; constructor.
Qed.
Lemma Zsgn_19 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 < x + y)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_12; assumption).
Qed.
Lemma Zsgn_20 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x + y < 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_11; assumption).
Qed.
Lemma Zsgn_21 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= x)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_22 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x <= 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_23 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= y)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_24 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (y <= 0)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_25 : forall x : Z, Zsgn (- x) = (- Zsgn x)%Z.
Proof.
intros [| p1| p1]; simpl in |- *; reflexivity.
Qed.
Lemma Zsgn_26 : forall x : Z, (0 < x)%Z -> (0 < Zsgn x)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Lemma Zsgn_27 : forall x : Z, (x < 0)%Z -> (Zsgn x < 0)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Hint Resolve Zsgn_1 Zsgn_2 Zsgn_3 Zsgn_4 Zsgn_5 Zsgn_6 Zsgn_7 Zsgn_7' Zsgn_8
Zsgn_9 Zsgn_10 Zsgn_11 Zsgn_12 Zsgn_13 Zsgn_14 Zsgn_15 Zsgn_16 Zsgn_17
Zsgn_18 Zsgn_19 Zsgn_20 Zsgn_21 Zsgn_22 Zsgn_23 Zsgn_24 Zsgn_25 Zsgn_26
Zsgn_27: zarith.
(*###########################################################################*)
(** Properties of Zabs *)
(*###########################################################################*)
Lemma Zabs_1 : forall z p : Z, (Zabs z < p)%Z -> (z < p)%Z /\ (- p < z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
split.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
assumption.
intros.
simpl in H.
split.
assumption.
apply Zlt_trans with (m := 0%Z).
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
constructor.
intros.
simpl in H.
split.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl;trivial.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (- Zneg p0)%Z.
replace (- Zneg p0)%Z with (Zpos p0).
apply Zlt_gt.
assumption.
symmetry in |- *.
apply Zopp_neg.
rewrite Zopp_mult_distr_l_reverse with (n := 1%Z).
simpl in |- *.
constructor.
Qed.
Lemma Zabs_2 : forall z p : Z, (Zabs z > p)%Z -> (z > p)%Z \/ (- p > z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
right.
apply Zlt_gt.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (Zpos p0).
assumption.
reflexivity.
Qed.
Lemma Zabs_3 : forall z p : Z, (z < p)%Z /\ (- p < z)%Z -> (Zabs z < p)%Z.
Proof.
intros z p.
case z.
intro.
simpl in |- *.
elim H.
intros.
assumption.
intros.
elim H.
intros.
simpl in |- *.
assumption.
intros.
elim H.
intros.
simpl in |- *.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * Zpos p0)%Z with (Zneg p0).
replace (-1 * p)%Z with (- p)%Z.
apply Zlt_gt.
assumption.
ring.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_4 : forall z p : Z, (Zabs z < p)%Z -> (- p < z < p)%Z.
Proof.
intros.
split.
apply proj2 with (A := (z < p)%Z).
apply Zabs_1.
assumption.
apply proj1 with (B := (- p < z)%Z).
apply Zabs_1.
assumption.
Qed.
Lemma Zabs_5 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z <= p)%Z.
Proof.
intros.
split.
replace (- p)%Z with (Zsucc (- Zsucc p)).
apply Zlt_le_succ.
apply proj2 with (A := (z < Zsucc p)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
unfold Zsucc in |- *.
ring.
apply Zlt_succ_le.
apply proj1 with (B := (- Zsucc p < z)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
Qed.
Lemma Zabs_6 : forall z p : Z, (Zabs z <= p)%Z -> (z <= p)%Z.
Proof.
intros.
apply proj2 with (A := (- p <= z)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_7 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z)%Z.
Proof.
intros.
apply proj1 with (B := (z <= p)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_8 : forall z p : Z, (- p <= z <= p)%Z -> (Zabs z <= p)%Z.
Proof.
intros.
apply Zlt_succ_le.
apply Zabs_3.
elim H.
intros.
split.
apply Zle_lt_succ.
assumption.
apply Zlt_le_trans with (m := (- p)%Z).
apply Zgt_lt.
apply Zlt_opp.
apply Zlt_succ.
assumption.
Qed.
Lemma Zabs_min : forall z : Z, Zabs z = Zabs (- z).
Proof.
intro.
case z.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_9 :
forall z p : Z, (0 <= p)%Z -> (p < z)%Z \/ (z < - p)%Z -> (p < Zabs z)%Z.
Proof.
intros.
case H0.
intro.
replace (Zabs z) with z.
assumption.
symmetry in |- *.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
assumption.
intro.
cut (Zabs z = (- z)%Z).
intro.
rewrite H2.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
rewrite Zabs_min.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
Qed.
Lemma Zabs_10 : forall z : Z, (0 <= Zabs z)%Z.
Proof.
intro.
case (Z_zerop z).
intro.
rewrite e.
simpl in |- *.
apply Zle_refl.
intro.
case (not_Zeq z 0 n).
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
right.
assumption.
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
left.
assumption.
Qed.
Lemma Zabs_11 : forall z : Z, z <> 0%Z -> (0 < Zabs z)%Z.
Proof.
intros.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
apply not_Zeq.
intro.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Zabs_12 : forall z m : Z, (m < Zabs z)%Z -> {(m < z)%Z} + {(z < - m)%Z}.
Proof.
intros [| p| p] m; simpl in |- *; intros H;
[ left | left | right; apply Zmin_cancel_Zlt; rewrite Zopp_involutive ];
assumption.
Qed.
Lemma Zabs_mult : forall z p : Z, Zabs (z * p) = (Zabs z * Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
reflexivity.
case p.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
case p.
intro.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_plus : forall z p : Z, (Zabs (z + p) <= Zabs z + Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
apply Zle_refl.
case p.
intro.
simpl in |- *.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 - Zneg p0)%Z.
replace (Zpos p1 - Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(- (Zpos p0 + Zneg p0))%Z.
replace (Zpos p1 - Zneg p0 + (Zpos p1 + Zneg p0))%Z with (2 * Zpos p1)%Z.
replace (- (Zpos p0 + Zneg p0))%Z with 0%Z.
apply Zmult_gt_0_le_0_compat.
constructor.
apply Zlt_le_weak.
constructor.
rewrite <- Zopp_neg with p0.
ring.
ring.
ring.
apply Zplus_le_compat.
apply Zle_refl.
apply Zlt_le_weak.
constructor.
case p.
simpl in |- *.
intro.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 + Zneg p0)%Z.
replace (Zpos p1 + Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(Zneg p0 - Zpos p0)%Z.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with 0%Z.
apply Zplus_le_reg_l with (Zpos p0).
replace (Zpos p0 + (Zneg p0 - Zpos p0))%Z with (Zneg p0).
simpl in |- *.
apply Zlt_le_weak.
constructor.
ring.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with
(Zpos p1 + Zneg p1 + (Zpos p0 + Zneg p0))%Z.
replace 0%Z with (0 + 0)%Z.
apply Zplus_eq_compat.
rewrite <- Zopp_neg with p1.
ring.
rewrite <- Zopp_neg with p0.
ring.
simpl in |- *.
constructor.
ring.
ring.
apply Zplus_le_compat.
apply Zlt_le_weak.
constructor.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
Qed.
Lemma Zabs_neg : forall z : Z, (z <= 0)%Z -> Zabs z = (- z)%Z.
Proof.
intro.
case z.
simpl in |- *.
intro.
reflexivity.
intros.
apply False_ind.
apply H.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_Zabs: forall z, (z <= Zabs z)%Z.
Proof.
intros [|z|z]; simpl; auto with zarith; apply Zle_neg_pos.
Qed.
Hint Resolve Zabs_1 Zabs_2 Zabs_3 Zabs_4 Zabs_5 Zabs_6 Zabs_7 Zabs_8 Zabs_9
Zabs_10 Zabs_11 Zabs_12 Zabs_min Zabs_neg Zabs_mult Zabs_plus Zle_Zabs: zarith.
(*###########################################################################*)
(** Induction on Z *)
(*###########################################################################*)
Lemma Zind :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> exists k : nat, q = (p + k)%Z).
intro.
cut (forall k : nat, P (p + k)%Z).
intro.
intros.
cut (exists k : nat, q = (p + Z_of_nat k)%Z).
intro.
case H4.
intros.
rewrite H5.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
ring_simplify (p + 0)%Z.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
ring_simplify (- p + (p + Z_of_nat k))%Z.
apply Znat.inj_le.
apply le_O_n.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (q - p)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> {k : nat | q = (p + k)%Z}).
intro.
cut (forall k : nat, F (p + k)%Z).
intro.
intros.
cut {k : nat | q = (p + Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
rewrite Zplus_0_r.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
replace (- p + (p + Z_of_nat k))%Z with (Z_of_nat k).
apply Znat.inj_le.
apply le_O_n.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
apply Zplus_assoc_reverse.
intros.
cut {k : nat | (q - p)%Z = Z_of_nat k}.
intro H2.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite e.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
unfold Zminus in |- *.
apply Zplus_comm.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_down :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> {k : nat | q = (p - k)%Z}).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut {k : nat | q = (p - Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
unfold Zminus in |- *.
unfold Zopp in |- *.
rewrite Zplus_0_r; reflexivity.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
unfold Zminus in |- *; rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
unfold Zminus at 1 2 in |- *.
rewrite Zplus_assoc_reverse.
rewrite <- Zopp_plus_distr.
reflexivity.
intros.
cut {k : nat | (p - q)%Z = Z_of_nat k}.
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- e.
reflexivity.
unfold Zminus in |- *.
rewrite Zopp_plus_distr.
rewrite Zplus_assoc.
rewrite Zplus_opp_r.
rewrite Zopp_involutive.
reflexivity.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zind_down :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> exists k : nat, q = (p - k)%Z).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut (exists k : nat, q = (p - Z_of_nat k)%Z).
intro.
case H4.
intros x e.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
ring.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
ring.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (p - q)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_wf :
forall (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zrec with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zrec_wf2 :
forall (q : Z) (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zrec_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zrec_wf_double :
forall (P : Z -> Z -> Set) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zrec_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zrec_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
Lemma Zind_wf :
forall (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zind with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zind_wf2 :
forall (q : Z) (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zind_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zind_wf_double :
forall (P : Z -> Z -> Prop) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zind_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zind_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zmax *)
(*###########################################################################*)
Definition Zmax (n m : Z) := (n + m - Zmin n m)%Z.
Lemma ZmaxSS : forall n m : Z, (Zmax n m + 1)%Z = Zmax (n + 1) (m + 1).
Proof.
intros.
unfold Zmax in |- *.
replace (Zmin (n + 1) (m + 1)) with (Zmin n m + 1)%Z.
ring.
symmetry in |- *.
change (Zmin (Zsucc n) (Zsucc m) = Zsucc (Zmin n m)) in |- *.
symmetry in |- *.
apply Zmin_SS.
Qed.
Lemma Zle_max_l : forall n m : Z, (n <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- n + Zmin n m)%Z).
ring_simplify (- n + Zmin n m + n)%Z.
ring_simplify (- n + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_r.
Qed.
Lemma Zle_max_r : forall n m : Z, (m <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- m + Zmin n m)%Z).
ring_simplify (- m + Zmin n m + m)%Z.
ring_simplify (- m + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_l.
Qed.
Lemma Zmin_or_informative : forall n m : Z, {Zmin n m = n} + {Zmin n m = m}.
Proof.
intros.
case (Z_lt_ge_dec n m).
unfold Zmin in |- *.
unfold Zlt in |- *.
intro z.
rewrite z.
left.
reflexivity.
intro.
cut ({(n > m)%Z} + {n = m :>Z}).
intro.
case H.
intros z0.
unfold Zmin in |- *.
unfold Zgt in z0.
rewrite z0.
right.
reflexivity.
intro.
rewrite e.
right.
apply Zmin_n_n.
cut ({(m < n)%Z} + {m = n :>Z}).
intro.
elim H.
intro.
left.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
apply Z_le_lt_eq_dec.
apply Zge_le.
assumption.
Qed.
Lemma Zmax_case : forall (n m : Z) (P : Z -> Set), P n -> P m -> P (Zmax n m).
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
cut ((n + m - n)%Z = m).
intro.
rewrite H1.
assumption.
ring.
intro.
rewrite e.
cut ((n + m - m)%Z = n).
intro.
rewrite H1.
assumption.
ring.
Qed.
Lemma Zmax_or_informative : forall n m : Z, {Zmax n m = n} + {Zmax n m = m}.
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
right.
ring.
intro.
rewrite e.
left.
ring.
Qed.
Lemma Zmax_n_n : forall n : Z, Zmax n n = n.
Proof.
intros.
unfold Zmax in |- *.
rewrite (Zmin_n_n n).
ring.
Qed.
Hint Resolve ZmaxSS Zle_max_r Zle_max_l Zmax_n_n: zarith.
(*###########################################################################*)
(** Properties of Arity *)
(*###########################################################################*)
Lemma Zeven_S : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x + 1).
Proof.
exact Zeven.Zeven_Sn.
Qed.
Lemma Zeven_pred : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x - 1).
Proof.
exact Zeven.Zeven_pred.
Qed.
(* This lemma used to be useful since it was mentioned with an unnecessary premise
`x>=0` as Z_modulo_2 in ZArith, but the ZArith version has been fixed. *)
Definition Z_modulo_2_always :
forall x : Z, {y : Z | x = (2 * y)%Z} + {y : Z | x = (2 * y + 1)%Z} :=
Zeven.Z_modulo_2.
(*###########################################################################*)
(** Properties of Zdiv *)
(*###########################################################################*)
Lemma Z_div_mod_eq_2 :
forall a b : Z, (0 < b)%Z -> (b * (a / b))%Z = (a - a mod b)%Z.
Proof.
intros.
apply Zplus_minus_eq.
rewrite Zplus_comm.
apply Z_div_mod_eq.
Flip.
Qed.
Lemma Z_div_le :
forall a b c : Z, (0 < c)%Z -> (b <= a)%Z -> (b / c <= a / c)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge; Flip; assumption.
Qed.
Lemma Z_div_nonneg :
forall a b : Z, (0 < b)%Z -> (0 <= a)%Z -> (0 <= a / b)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge0; Flip; assumption.
Qed.
Lemma Z_div_neg : forall a b : Z, (0 < b)%Z -> (a < 0)%Z -> (a / b < 0)%Z.
Proof.
intros.
rewrite (Z_div_mod_eq a b) in H0.
elim (Z_mod_lt a b).
intros H1 _.
apply Znot_ge_lt.
intro.
apply (Zlt_not_le (b * (a / b) + a mod b) 0 H0).
apply Zplus_le_0_compat.
apply Zmult_le_0_compat.
apply Zlt_le_weak; assumption.
Flip.
assumption.
Flip.
Flip.
Qed.
Hint Resolve Z_div_mod_eq_2 Z_div_le Z_div_nonneg Z_div_neg: zarith.
(*###########################################################################*)
(** Properties of Zpower *)
(*###########################################################################*)
Lemma Zpower_1 : forall a : Z, (a ^ 1)%Z = a.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
auto with zarith.
Qed.
Lemma Zpower_2 : forall a : Z, (a ^ 2)%Z = (a * a)%Z.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
ring.
Qed.
Hint Resolve Zpower_1 Zpower_2: zarith.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [15:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[15:0]),
// Inputs
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {48'h0, out};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h4afe43fb79d7b71e
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module callee (input [7:0] port [7:0], output [7:0] o);
assign o = ^{port[0], port[1], port[2], port[3],
port[4], port[5], port[6], port[7]};
endmodule // callee
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
in
);
input [31:0] in;
output reg [15:0] out;
wire [7:0] port [15:0];
wire [7:0] goodport [7:0];
always_comb begin
port[0][7:0] = in[7:0];
port[1][7:0] = in[16:8];
port[2] = '0;
port[3] = '0;
port[4] = '0;
port[5] = '0;
port[6] = '0;
port[7] = '0;
end
always_comb begin
goodport[0][7:0] = in[7:0];
goodport[1][7:0] = in[16:8];
goodport[2] = '0;
goodport[3] = '0;
goodport[4] = '0;
goodport[5] = '0;
goodport[6] = '0;
goodport[7] = '0;
end
callee good (.port(goodport), .o(out[7:0]));
// This is a slice, unsupported by other tools, bug711
callee bad (.port(port[7:0]), .o(out[15:8]));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [31:0] in = crc[31:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] out; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.out (out[3:0]),
// Inputs
.clk (clk),
.in (in[31:0]));
// Aggregate outputs into a single result vector
wire [63:0] result = {60'h0, out};
// What checksum will we end up with
`define EXPECTED_SUM 64'h1a0d07009b6a30d2
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
input clk;
input [31:0] in;
output [3:0] out;
assign out[0] = in[3:0] ==? 4'b1001;
assign out[1] = in[3:0] !=? 4'b1001;
assign out[2] = in[3:0] ==? 4'bx01x;
assign out[3] = in[3:0] !=? 4'bx01x;
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.2 Build 209 09/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rom (
address,
clock,
q);
parameter init_file = ""; //PG
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
parameter ram_type = "AUTO"; // M10K MLAB AUTO
input [13:0] address;
input clock;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({8{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = init_file,
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = lpm_hint,
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16384,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.widthad_a = 14,
altsyncram_component.width_a = 8,
altsyncram_component.ram_block_type = ram_type,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "rom/rom.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "rom/rom.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
(** * Smallstep: Small-step Operational Semantics *)
Require Export Imp.
(** The evaluators we have seen so far (e.g., the ones for
[aexp]s, [bexp]s, and commands) have been formulated in a
"big-step" style -- they specify how a given expression can be
evaluated to its final value (or a command plus a store to a final
store) "all in one big step."
This style is simple and natural for many purposes -- indeed,
Gilles Kahn, who popularized its use, called it _natural
semantics_. But there are some things it does not do well. In
particular, it does not give us a natural way of talking about
_concurrent_ programming languages, where the "semantics" of a
program -- i.e., the essence of how it behaves -- is not just
which input states get mapped to which output states, but also
includes the intermediate states that it passes through along the
way, since these states can also be observed by concurrently
executing code.
Another shortcoming of the big-step style is more technical, but
critical in some situations. To see the issue, suppose we wanted
to define a variant of Imp where variables could hold _either_
numbers _or_ lists of numbers (see the [HoareList] chapter for
details). In the syntax of this extended language, it will be
possible to write strange expressions like [2 + nil], and our
semantics for arithmetic expressions will then need to say
something about how such expressions behave. One
possibility (explored in the [HoareList] chapter) is to maintain
the convention that every arithmetic expressions evaluates to some
number by choosing some way of viewing a list as a number -- e.g.,
by specifying that a list should be interpreted as [0] when it
occurs in a context expecting a number. But this is really a bit
of a hack.
A much more natural approach is simply to say that the behavior of
an expression like [2+nil] is _undefined_ -- it doesn't evaluate
to any result at all. And we can easily do this: we just have to
formulate [aeval] and [beval] as [Inductive] propositions rather
than Fixpoints, so that we can make them partial functions instead
of total ones.
However, now we encounter a serious deficiency. In this language,
a command might _fail_ to map a given starting state to any ending
state for two quite different reasons: either because the
execution gets into an infinite loop or because, at some point,
the program tries to do an operation that makes no sense, such as
adding a number to a list, and none of the evaluation rules can be
applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a
different way of presenting the semantics that allows us to
distinguish nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ########################################################### *)
(** * Relations *)
(** A _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step and multi-step reduction relations on terms, [==>]
and [==>*], but there are many other examples -- some that come to
mind are the "equals," "less than," "less than or equal to," and
"is the square of" relations on numbers, and the "prefix of"
relation on lists and strings. *)
(* ########################################################### *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] -- for the
constructor names, for brevity.) At the end of the chapter, we'll
see how to apply the same techniques to the full Imp language. *)
Inductive tm : Type :=
| C : nat -> tm (* Constant *)
| P : tm -> tm -> tm. (* Plus *)
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P" ].
(** Here is a standard evaluator for this language, written in the
same (big-step) style as we've been using up to this point. *)
Fixpoint evalF (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => evalF a1 + evalF a2
end.
(** Now, here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t || n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n || n
t1 || n1
t2 || n2
---------------------- (E_Plus)
P t1 t2 || C (n1 + n2)
*)
Reserved Notation " t '||' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n || n
| E_Plus : forall t1 t2 n1 n2,
t1 || n1 ->
t2 || n2 ->
P t1 t2 || (n1 + n2)
where " t '||' n " := (eval t n).
Tactic Notation "eval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Const" | Case_aux c "E_Plus" ].
Module SimpleArith1.
(** Now, here is a small-step version. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** Let's pause and check a couple of examples of reasoning with
the [step] relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [P t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 1 star (test_step_2) *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
apply ST_Plus2. apply ST_Plus2. apply ST_PlusConstConst.
Qed.
(** [] *)
(** One simple property of the [==>] relation is that, like the
evaluation relation for our language of Imp programs, it is
_deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic. *)
(** _Proof sketch_: We show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal, by induction on a derivation of
[step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and in the given derivation
of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] has both the form [P t1 t2] and
the form [C n]. [] *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2.
Case "ST_PlusConstConst". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". reflexivity.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2". inversion H2.
Case "ST_Plus1". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H0 in Hy1. inversion Hy1.
SCase "ST_Plus1".
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
SCase "ST_Plus2". rewrite <- H in Hy1. inversion Hy1.
Case "ST_Plus2". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H1 in Hy1. inversion Hy1.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2".
rewrite <- (IHHy1 t2'0).
reflexivity. assumption. Qed.
End SimpleArith1.
(* ########################################################### *)
(** ** Values *)
(** Let's take a moment to slightly generalize the way we state the
definition of single-step reduction. *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done.
We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules, for the sake of brevity.) *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** **** Exercise: 3 stars (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism
Proof sketch: We must show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal. Consider the final rules used in
the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) AND one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] both has the form [P t1 t2] and
is a value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write it from
scratch and just use the earlier one if you get stuck. *)
Theorem step_deterministic :
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 H1 H2. generalize dependent y2.
step_cases (induction H1) Case; intros y2 H2; inversion H2; subst; auto.
Case "ST_PlusConstConst".
inversion H3.
inversion H4.
Case "ST_Plus1".
inversion H1.
apply IHstep in H4. rewrite H4. reflexivity.
inversion H3. rewrite <- H in H1. inversion H1.
Case "ST_Plus2".
inversion H1.
inversion H5; subst; inversion H.
apply IHstep in H6. rewrite H6. reflexivity.
Qed.
(** [] *)
(* ########################################################### *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language is
fairly simple, but for a larger language it would be pretty easy
to forget one of the rules and create a situation where some term
cannot take a step even though it has not been completely reduced
to a value. The following theorem shows that we did not, in fact,
make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): If [t] is a term, then either [t]
is a value, or there exists a term [t'] such that [t ==> t']. *)
(** _Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a [value].
- Suppose [t = P t1 t2], where (by the IH) [t1] is either a
value or can step to some [t1'], and where [t2] is either a
value or can step to some [t2']. We must show [P t1 t2] is
either a value or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. [] *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
tm_cases (induction t) Case.
Case "C". left. apply v_const.
Case "P". right. inversion IHt1.
SCase "l". inversion IHt2.
SSCase "l". inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
SSCase "r". inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
SCase "r". inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0. Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
simply "progress.") *)
(** The idea of "making progress" can be extended to tell us something
interesting about [value]s: in this language [value]s are exactly
the terms that _cannot_ make progress in this sense.
To state this observation formally, let's begin by giving a name
to terms that cannot make progress. We'll call them _normal
forms_. *)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** This definition actually specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall v,
value v -> normal_form step v.
Proof.
unfold normal_form. intros v H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
SCase "Proof of assertion". apply strong_progress.
inversion G.
SCase "l". apply H0.
SCase "r". apply ex_falso_quodlibet. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting?
Because [value] is a syntactic concept -- it is defined by looking
at the form of a term -- while [normal_form] is a semantic one --
it is defined by looking at how the term steps. It is not obvious
that these concepts should coincide!
Indeed, we could easily have written the definitions so that they
would not coincide... *)
(* ##################################################### *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
Module Temp1.
(* Open an inner module so we can redefine value and step. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** *)
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
exists (P (C 1) (C 2)).
split.
Case "l". apply v_funny.
Case "r".
unfold not, normal_form. intros.
apply H. exists (C 3). apply ST_PlusConstConst.
Qed.
(** [] *)
End Temp1.
(* ##################################################### *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** *)
(** **** Exercise: 2 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
exists (C 1). split.
constructor.
unfold not, normal_form, not. intros. apply H. exists (P (C 1) (C 0)). constructor.
Qed.
End Temp2.
(* ########################################################### *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, even in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
(** *)
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form') *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
exists (P (C 0) (P (C 1) (C 2))). split.
Case "l". unfold not. intro. inversion H.
Case "r". unfold normal_form, not. intro.
inversion H. inversion H0. inversion H4.
Qed.
(** [] *)
End Temp3.
(* ########################################################### *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just plus and numbers, are just the booleans true and false and a
conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first ;
[ Case_aux c "IfTrue" | Case_aux c "IfFalse" | Case_aux c "If" ].
(** **** Exercise: 1 star (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
(* not provable (tfalse is a value) *)
Lemma not_bool_step_prop1 : ~ bool_step_prop1.
Proof.
unfold not, bool_step_prop1. intros. inversion H.
Qed.
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
(* not provable - needs several steps *)
Lemma not_bool_step_prop2 : ~bool_step_prop2.
Proof.
unfold not, bool_step_prop2. intros. inversion H.
Qed.
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
Lemma bool_step_prop3_holds :
bool_step_prop3.
Proof.
unfold bool_step_prop3. apply ST_If. apply ST_IfTrue.
Qed.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (progress_bool) *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
intros t. tm_cases (induction t) Case.
Case "ttrue".
left. constructor.
Case "tfalse".
left. constructor.
Case "tif".
inversion IHt1; right;
inversion H; subst.
exists t2. constructor.
exists t3. constructor.
exists (tif x t2 t3). constructor. assumption.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
unfold deterministic. intros. generalize dependent y2.
step_cases (induction H) Case; intros; subst.
Case "IfTrue". inversion H0. reflexivity. subst. inversion H4.
Case "IfFalse". inversion H0. reflexivity. subst. inversion H4.
Case "If". inversion H0; subst. inversion H. inversion H. apply IHstep in H5. rewrite H5. reflexivity.
Qed.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
| ST_IfEq : forall t1 t2,
tif t1 t2 t2 ==> t2
(* FILL IN HERE *)
where " t '==>' t' " := (step t t').
(** [] *)
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
unfold bool_step_prop4. apply ST_IfEq.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
A: No it is not deterministic, because we can apply two different
rules to get reductions, even though both rules will lead us
eventually to the same normal forms.
Optional: prove your answer correct in Coq.
*)
Theorem step_not_deterministic :
~ (deterministic step).
Proof.
unfold not, deterministic. intro.
assert (tif ttrue tfalse tfalse = tfalse).
apply H with (x:=tif (tif ttrue ttrue ttrue) tfalse tfalse).
constructor. constructor.
constructor. inversion H0.
Qed.
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(*
A: Yes, this works, every expression evaluates in multiple
steps to the same value.
*)
Theorem strong_progress : forall t,
value t \/ exists t', t ==> t'.
Proof.
intro t. induction t.
Case "ttrue". left. constructor.
Case "tfalse". left. constructor.
Case "tif". right. inversion IHt1.
inversion H.
exists t2. constructor.
exists t3. constructor.
inversion H. exists (tif x t2 t3). constructor. assumption.
Qed.
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
(*
Yes, strong_progress would fail if any except for the short circuit
constructors would be removed from the step relation.
*)
*)
(** [] *)
End Temp5.
End Temp4.
(* ########################################################### *)
(** * Multi-Step Reduction *)
(** Until now, we've been working with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
_abstract machine_ for executing programs.
We can also use this machine to reduce programs to completion --
to find out what final result they yield. This can be formalized
as follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
of single reduction steps (including zero steps!).
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(* ########################################################### *)
(** Since we'll want to reuse the idea of multi-step reduction many
times in this and future chapters, let's take a little extra
trouble here and define it generically.
Given a relation [R], we define a relation [multi R], called the
_multi-step closure of [R]_ as follows: *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] if either
- [x = y], or else
- there is some sequence [z1], [z2], ..., [zn]
such that
R x z1
R z1 z2
...
R zn y.
Thus, if [R] describes a single-step of computation, [z1],
... [zn] is the sequence of intermediate steps of computation
between [x] and [y].
*)
Tactic Notation "multi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "multi_refl" | Case_aux c "multi_step" ].
(** We write [==>*] for the [multi step] relation -- i.e., the
relation that relates two terms [t] and [t'] if we can get from
[t] to [t'] using the [step] relation zero or more times. *)
Definition multistep := multi step.
Notation " t '==>*' t' " := (multistep t t') (at level 40).
(** The relation [multi R] has several crucial properties.
First, it is obviously _reflexive_ (that is, [forall x, multi R x
x]). In the case of the [==>*] (i.e. [multi step]) relation, the
intuition is that a term can execute to itself by taking zero
steps of execution.
Second, it contains [R] -- that is, single-step executions are a
particular case of multi-step executions. (It is this fact that
justifies the word "closure" in the term "multi-step closure of
[R].") *)
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl. Qed.
(** Third, [multi R] is _transitive_. *)
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
multi_cases (induction G) Case.
Case "multi_refl". assumption.
Case "multi_step".
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** That is, if [t1==>*t2] and [t2==>*t3], then [t1==>*t3]. *)
(* ########################################################### *)
(** ** Examples *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P
(C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P
(C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_R.
apply ST_PlusConstConst. Qed.
(** Here's an alternate proof that uses [eapply] to avoid explicitly
constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl. Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 ==>* C 3.
Proof.
constructor.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
constructor.
Qed.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
eapply multi_step. apply ST_Plus2. constructor. apply ST_Plus2. constructor. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. constructor. apply ST_PlusConstConst.
apply multi_refl.
Qed.
(** [] *)
(* ########################################################### *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
unfold deterministic, normal_form_of. intros x y1 y2 [P11 P12] [P21 P22].
(*inversion P1 as [P11 P12]; clear P1. inversion P2 as [P21 P22]; clear P2.*)
generalize dependent y2. (* remember (x ==>* y1) as Pxy1 eqn:HPxy1. rewrite HPxy1 in P11.*)
induction P11.
Case "Base".
intros. apply nf_is_value in P12. apply nf_is_value in P22.
inversion P12 as [n1]. inversion P22 as [n2]. subst. inversion P21. reflexivity. inversion H.
Case "IH".
intros. apply IHP11.
assumption.
inversion P21. subst. apply nf_is_value in P22. inversion P22. subst. inversion H. subst.
assert (y = y0). eapply step_deterministic. apply H. assumption. symmetry in H2. subst. assumption.
assumption.
Qed.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. multi_cases (induction H) Case.
Case "multi_refl". apply multi_refl.
Case "multi_step". apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
intros t1 t2 t2' H Ht2. multi_cases (induction Ht2) Case.
Case "multi_refl". constructor.
Case "multi_step". eapply multi_step. apply ST_Plus2. assumption. eassumption. assumption.
Qed.
(** [] *)
(** _Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step,
and we have [t' = t]. We can derive the left-hand side by
reflexivity and the right-hand side by observing (a) that values
are normal forms (by [nf_same_as_value]) and (b) that [t] is a
value (by [v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and
[t2] have normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we know that [t1' =
C n1] and [t2' = C n2], for some [n1] and [n2].
We can combine the [==>*] derivations for [t1] and [t2] to prove
that [P t1 t2] reduces in many steps to [C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a
value, which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
tm_cases (induction t) Case.
Case "C".
exists (C n).
split.
SCase "l". apply multi_refl.
SCase "r".
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
Case "P".
inversion IHt1 as [t1' H1]; clear IHt1. inversion IHt2 as [t2' H2]; clear IHt2.
inversion H1 as [H11 H12]; clear H1. inversion H2 as [H21 H22]; clear H2.
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1]. inversion H22 as [n2].
rewrite <- H in H11.
rewrite <- H0 in H21.
exists (C (n1 + n2)).
split.
SCase "l".
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. apply H11.
apply multi_trans with
(P (C n1) (C n2)).
apply multistep_congr_2. apply v_const. apply H21.
apply multi_R. apply ST_PlusConstConst.
SCase "r".
rewrite nf_same_as_value. apply v_const. Qed.
(* ########################################################### *)
(** ** Equivalence of Big-Step and Small-Step Reduction *)
(** Having defined the operational semantics of our tiny programming
language in two different styles, it makes sense to ask whether
these definitions actually define the same thing! They do, though
it takes a little work to show it. (The details are left as an
exercise). *)
(** **** Exercise: 3 stars (eval__multistep) *)
Theorem eval__multistep : forall t n,
t || n -> t ==>* C n.
(** The key idea behind the proof comes from the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)]. *)
(** To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
intro t. tm_cases (induction t) Case.
Case "C". intros. inversion H. subst. constructor.
Case "P". intros. inversion H. subst.
apply IHt1 in H2.
apply IHt2 in H4.
apply multi_trans with (P (C n1) t2). apply multistep_congr_1. assumption.
apply multi_trans with (P (C n1) (C n2)). apply multistep_congr_2. apply v_const. assumption.
eapply multi_step. apply ST_PlusConstConst. apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(* FILL IN HERE *)
[]
*)
(** For the other direction, we need one lemma, which establishes a
relation between single-step reduction and big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' || n ->
t || n.
Proof.
intros t t' n Hs. generalize dependent n.
induction Hs; intros.
Case "C".
inversion H. subst. constructor. constructor. constructor.
Case "1".
inversion H. subst. constructor. apply IHHs. assumption. assumption.
Case "2".
inversion H0. subst. constructor. assumption. apply IHHs. assumption.
Qed.
(** [] *)
(** The fact that small-step reduction implies big-step is now
straightforward to prove, once it is stated correctly.
The proof proceeds by induction on the multip-step reduction
sequence that is buried in the hypothesis [normal_form_of t t']. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
Theorem multistep__eval : forall t t',
normal_form_of t t' -> exists n, t' = C n /\ t || n.
Proof.
intros t t' H. unfold normal_form_of in H. inversion H as [H1 H2]. clear H.
multi_cases (induction H1) Case.
Case "multi_refl". apply nf_is_value in H2. inversion H2. exists n. split. reflexivity. constructor.
Case "multi_step".
apply IHmulti in H2. inversion H2 as [n H3]. inversion H3 as [Heq Hev]. apply step__eval with (n:=n) in H.
exists n. auto. assumption.
Qed.
(** [] *)
(* ########################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 3 stars, optional (interp_tm) *)
(** Remember that we also defined big-step evaluation of [tm]s as a
function [evalF]. Prove that it is equivalent to the existing
semantics.
Hint: we just proved that [eval] and [multistep] are
equivalent, so logically it doesn't matter which you choose.
One will be easier than the other, though! *)
Theorem evalF_eval : forall t n,
evalF t = n <-> t || n.
Proof.
intros t. tm_cases (induction t) Case; split; intros.
Case "C". simpl in H. subst. apply E_Const. inversion H. subst. reflexivity.
Case "P".
SCase "->".
simpl in H. rewrite <- H. apply E_Plus. apply IHt1. reflexivity. apply IHt2. reflexivity.
inversion H. subst. apply IHt1 in H2. apply IHt2 in H4. simpl. rewrite H2. rewrite H4. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars (combined_properties) *)
(** We've considered the arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
Lemma value_cannot_step : forall t t',
value t -> ~(t ==> t').
Proof.
intro t. tm_cases (induction t) Case; unfold not; intros t' Con1 Con2;
try (inversion Con1); try (inversion Con2).
Qed.
Lemma step_deterministic : forall t t1 t2,
t ==> t1 -> t ==> t2 -> t1 = t2.
Proof.
intros t t1 t2 H. generalize dependent t2. step_cases (induction H) Case; intros.
Case "ST_PlusConstConst".
inversion H. reflexivity. inversion H3. inversion H4.
Case "ST_Plus1".
inversion H0; subst. inversion H. apply IHstep in H4. rewrite H4. reflexivity.
eapply value_cannot_step in H3. unfold not in H3. apply H3 in H. inversion H.
Case "ST_Plus2".
inversion H1; subst. inversion H0.
apply value_cannot_step in H5. inversion H5. assumption. apply IHstep in H6. rewrite H6. reflexivity.
Case "ST_IfTrue". inversion H; subst. reflexivity. inversion H4.
Case "ST_IfFalse". inversion H; subst. reflexivity. inversion H4.
Case "ST_If". inversion H0; subst. inversion H. inversion H. apply IHstep in H5. rewrite H5. reflexivity.
Qed.
Lemma not_strong_progress : exists t,
~(value t) /\ forall t', ~ (t ==> t').
Proof.
exists (tif (C 0) ttrue ttrue). split.
Case "l". unfold not. intro. inversion H.
Case "r". intros t'. unfold not. intro Contra.
inversion Contra. inversion H3.
Qed.
(** [] *)
End Combined.
(* ########################################################### *)
(** * Small-Step Imp *)
(** For a more serious example, here is the small-step version of the
Imp operational semantics. *)
(** The small-step evaluation relations for arithmetic and boolean
expressions are straightforward extensions of the tiny language
we've been working up to now. To make them easier to read, we
introduce the symbolic notations [==>a] and [==>b], respectively,
for the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values, since they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' " (at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult (a1) (a2)) / st ==>a (AMult (a1') (a2))
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' " (at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (ble_nat n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 (a2'))
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being evaluated.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ########################################################### *)
(** * Concurrent Imp *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "PAR" ].
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' b 'THEN' c1 'ELSE' c2 'FI'" :=
(CIf b c1 c2) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st ==>
(IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value... *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (update st X (S n)).
Proof.
intros n st [Hx Hy]. eapply multi_step. unfold par_loop.
apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2.
apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. rewrite Hy. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. rewrite Hx. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
assert (n+1=S n) by omega. rewrite H.
unfold par_loop. apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
intros n. induction n as [|n']; intros st [Hx Hy].
Case "n=0".
exists st. split. apply multi_refl. omega.
Case "n=S n'".
assert (exists st' : state, par_loop / st ==>* par_loop / st' /\ st' X = n' /\ st' Y = 0)
by auto. inversion H as [st' [Hstep [Hx1 Hy1]]].
exists (update st' X (S n')). split. eapply multi_trans. apply Hstep.
apply par_body_n__Sn. auto.
auto.
Qed.
(** [] *)
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite update_neq. assumption. intro X; inversion X.
Qed.
End CImp.
(* ########################################################### *)
(** * A Small-Step Stack Machine *)
(** Last example: a small-step semantics for the stack machine example
from Imp.v. *)
Definition stack := list nat.
Definition prog := list sinstr.
Inductive stack_step : state -> prog * stack -> prog * stack -> Prop :=
| SS_Push : forall st stk n p',
stack_step st (SPush n :: p', stk) (p', n :: stk)
| SS_Load : forall st stk i p',
stack_step st (SLoad i :: p', stk) (p', st i :: stk)
| SS_Plus : forall st stk n m p',
stack_step st (SPlus :: p', n::m::stk) (p', (m+n)::stk)
| SS_Minus : forall st stk n m p',
stack_step st (SMinus :: p', n::m::stk) (p', (m-n)::stk)
| SS_Mult : forall st stk n m p',
stack_step st (SMult :: p', n::m::stk) (p', (m*n)::stk).
Theorem stack_step_deterministic : forall st,
deterministic (stack_step st).
Proof.
unfold deterministic. intros st x y1 y2 H1 H2.
induction H1; inversion H2; reflexivity.
Qed.
Definition stack_multistep st := multi (stack_step st).
(** **** Exercise: 3 stars, advanced (compiler_is_correct) *)
(** Remember the definition of [compile] for [aexp] given in the
[Imp] chapter. We want now to prove [compile] correct with respect
to the stack machine.
State what it means for the compiler to be correct according to
the stack machine small step semantics and then prove it. *)
Definition compiler_is_correct_statement : Prop :=
forall (e : aexp) (st : state),
stack_multistep st (s_compile e, []) ([], [aeval st e]).
(*
Theorem s_compile_correct : forall (e : aexp) (st : state),
s_execute st [] (s_compile e) = [aeval st e].
Lemma s_execute_app : forall (st : state) (e : aexp) (prog : list sinstr) (stk : list nat),
s_execute st stk (s_compile e ++ prog) = s_execute st (aeval st e :: stk) prog.
*)
Lemma compiler_partial : forall (st : state) (e : aexp) (prg : list sinstr) (stk : list nat),
stack_multistep st (s_compile e ++ prg, stk) (prg, aeval st e :: stk).
Proof.
intros st e.
aexp_cases (induction e) Case; intros.
Case "ANum". eapply multi_step. constructor. constructor.
Case "AId". eapply multi_step. constructor. constructor.
Case "APlus". simpl. rewrite app_assoc_4.
eapply multi_trans. apply IHe1.
eapply multi_trans. apply IHe2.
eapply multi_step. constructor. apply multi_refl.
Case "AMinus". simpl. rewrite app_assoc_4.
eapply multi_trans. apply IHe1.
eapply multi_trans. apply IHe2.
eapply multi_step. constructor. apply multi_refl.
Case "AMult". simpl. rewrite app_assoc_4.
eapply multi_trans. apply IHe1.
eapply multi_trans. apply IHe2.
eapply multi_step. constructor. apply multi_refl.
Qed.
Theorem compiler_is_correct : compiler_is_correct_statement.
Proof.
unfold compiler_is_correct_statement. intros e st.
assert (s_compile e ++ [] = s_compile e) by (apply app_nil_r). rewrite <- H.
apply compiler_partial.
Qed.
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2020 by Geza Lore. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef VCS
`define NO_REAL_EXPORT
`endif
`ifdef NC
`define NO_STRUCT_OR_UNION
`define NO_SHORTREAL
`endif
`ifdef MS
`define NO_STRUCT_OR_UNION
`define NO_ARRAY
`endif
`ifdef VERILATOR
`define NO_SHORTREAL
`define NULL 64'd0
`else
`define NULL null
`endif
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
`ifdef VERILATOR
wire _unused = &{1'b0, clk};
`endif
// Legal result types for DPI functions
//======================================================================
// Type definitions
//======================================================================
// Basic types as per IEEE 1800-2017 35.5.5
typedef byte byte_t;
typedef byte unsigned byte_unsigned_t;
typedef shortint shortint_t;
typedef shortint unsigned shortint_unsigned_t;
typedef int int_t;
typedef int unsigned int_unsigned_t;
typedef longint longint_t;
typedef longint unsigned longint_unsigned_t;
typedef real real_t;
`ifndef NO_SHORTREAL
typedef shortreal shortreal_t;
`endif
typedef chandle chandle_t;
typedef string string_t;
typedef bit bit_t;
typedef logic logic_t;
// 2-state packed structures of width <= 32
typedef struct packed { bit x; } struct_2_state_1;
typedef struct packed { bit [15:0] x; bit [15:0] y; } struct_2_state_32;
// 2-state packed unions of width <= 32
typedef union packed { bit x; bit y; } union_2_state_1;
typedef union packed { bit [31:0] x; bit [31:0] y; } union_2_state_32;
//======================================================================
// Imports
//======================================================================
// Basic types as per IEEE 1800-2017 35.5.5
import "DPI-C" function void i_void ();
import "DPI-C" function byte i_byte ();
import "DPI-C" function byte unsigned i_byte_unsigned ();
import "DPI-C" function shortint i_shortint ();
import "DPI-C" function shortint unsigned i_shortint_unsigned ();
import "DPI-C" function int i_int ();
import "DPI-C" function int unsigned i_int_unsigned ();
import "DPI-C" function longint i_longint ();
import "DPI-C" function longint unsigned i_longint_unsigned ();
import "DPI-C" function real i_real ();
`ifndef NO_SHORTREAL
import "DPI-C" function shortreal i_shortreal ();
`endif
import "DPI-C" function chandle i_chandle ();
import "DPI-C" function string i_string ();
import "DPI-C" function bit i_bit ();
import "DPI-C" function logic i_logic ();
// Basic types via typedef
import "DPI-C" function byte_t i_byte_t ();
import "DPI-C" function byte_unsigned_t i_byte_unsigned_t ();
import "DPI-C" function shortint_t i_shortint_t ();
import "DPI-C" function shortint_unsigned_t i_shortint_unsigned_t ();
import "DPI-C" function int_t i_int_t ();
import "DPI-C" function int_unsigned_t i_int_unsigned_t ();
import "DPI-C" function longint_t i_longint_t ();
import "DPI-C" function longint_unsigned_t i_longint_unsigned_t ();
import "DPI-C" function real_t i_real_t ();
`ifndef NO_SHORTREAL
import "DPI-C" function shortreal_t i_shortreal_t ();
`endif
import "DPI-C" function chandle_t i_chandle_t ();
import "DPI-C" function string_t i_string_t ();
import "DPI-C" function bit_t i_bit_t ();
import "DPI-C" function logic_t i_logic_t ();
`ifndef NO_ARRAY
// 2-state packed arrays of width <= 32
import "DPI-C" function bit [ 0:0] i_array_2_state_1 ();
import "DPI-C" function bit [31:0] i_array_2_state_32 ();
`endif
`ifndef NO_STRUCT_OR_UNION
// 2-state packed structures of width <= 32
import "DPI-C" function struct_2_state_1 i_struct_2_state_1 ();
import "DPI-C" function struct_2_state_32 i_struct_2_state_32();
// 2-state packed unions of width <= 32
import "DPI-C" function union_2_state_1 i_union_2_state_1 ();
import "DPI-C" function union_2_state_32 i_union_2_state_32();
`endif
//======================================================================
// Exports
//======================================================================
// Basic types as per IEEE 1800-2017 35.5.5
export "DPI-C" function e_void;
export "DPI-C" function e_byte;
export "DPI-C" function e_byte_unsigned;
export "DPI-C" function e_shortint;
export "DPI-C" function e_shortint_unsigned;
export "DPI-C" function e_int;
export "DPI-C" function e_int_unsigned;
export "DPI-C" function e_longint;
export "DPI-C" function e_longint_unsigned;
`ifndef NO_REAL_EXPORT
export "DPI-C" function e_real;
`endif
`ifndef NO_SHORTREAL
export "DPI-C" function e_shortreal;
`endif
export "DPI-C" function e_chandle;
export "DPI-C" function e_string;
export "DPI-C" function e_bit;
export "DPI-C" function e_logic;
// Basic types via typedef
export "DPI-C" function e_byte_t;
export "DPI-C" function e_byte_unsigned_t;
export "DPI-C" function e_shortint_t;
export "DPI-C" function e_shortint_unsigned_t;
export "DPI-C" function e_int_t;
export "DPI-C" function e_int_unsigned_t;
export "DPI-C" function e_longint_t;
export "DPI-C" function e_longint_unsigned_t;
`ifndef NO_REAL_EXPORT
export "DPI-C" function e_real_t;
`endif
`ifndef NO_SHORTREAL
export "DPI-C" function e_shortreal_t;
`endif
export "DPI-C" function e_chandle_t;
export "DPI-C" function e_string_t;
export "DPI-C" function e_bit_t;
export "DPI-C" function e_logic_t;
`ifndef NO_ARRAY
// 2-state packed arrays of width <= 32
export "DPI-C" function e_array_2_state_1;
export "DPI-C" function e_array_2_state_32;
`endif
`ifndef NO_STRUCT_OR_UNION
// 2-state packed structures of width <= 32
export "DPI-C" function e_struct_2_state_1;
export "DPI-C" function e_struct_2_state_32;
// 2-state packed unions of width <= 32
export "DPI-C" function e_union_2_state_1;
export "DPI-C" function e_union_2_state_32;
`endif
//======================================================================
// Definitions of exported functions
//======================================================================
// Static variables (Note: Verilator strangely assumes everything inside
// a function is automatic, which is exactly the opposite of the standard
// see IEEE 1800-2017 13.3.1 and 13.4.2
// Basic types as per IEEE 1800-2017 35.5.5
int n_void = 0;
function void e_void();
$display("e_void %1d", n_void);
n_void++;
endfunction
byte n_byte = 0;
function byte e_byte();
e_byte = 8'd10 + n_byte;
n_byte++;
endfunction
byte n_byte_unsigned = 0;
function byte unsigned e_byte_unsigned();
e_byte_unsigned = 8'd20 + n_byte_unsigned;
n_byte_unsigned++;
endfunction
shortint n_shortint = 0;
function shortint e_shortint();
e_shortint = 16'd30 + n_shortint;
n_shortint++;
endfunction
shortint n_shortint_unsigned = 0;
function shortint unsigned e_shortint_unsigned();
e_shortint_unsigned = 16'd40 + n_shortint_unsigned;
n_shortint_unsigned++;
endfunction
int n_int = 0;
function int e_int();
e_int = 32'd50 + n_int;
n_int++;
endfunction
int n_int_unsigned = 0;
function int unsigned e_int_unsigned();
e_int_unsigned = 32'd60 + n_int_unsigned;
n_int_unsigned++;
endfunction
longint n_longint = 0;
function longint e_longint();
e_longint = 64'd70 + n_longint;
n_longint++;
endfunction
longint n_longint_unsigned = 0;
function longint unsigned e_longint_unsigned();
e_longint_unsigned = 64'd80 + n_longint_unsigned;
n_longint_unsigned++;
endfunction
`ifndef NO_REAL_EXPORT
int n_real = 0;
function real e_real();
e_real = real'(2*n_real + 1) / 2.0;
n_real++;
endfunction
`endif
`ifndef NO_SHORTREAL
int n_shortreal = 0;
function shortreal e_shortreal();
e_shortreal = shortreal'(4*n_shortreal + 1)/ 4.0;
n_shortreal++;
endfunction
`endif
int n_chandle = 0;
function chandle e_chandle();
$display("e_chandle %1d", n_chandle);
e_chandle = `NULL;
n_chandle++;
endfunction
int n_string = 0;
function string e_string();
$display("e_string %1d", n_string);
e_string = n_string[0] ? "World" : "Hello";
n_string++;
endfunction
int n_bit = 0;
function bit e_bit();
$display("e_bit %1d", n_bit);
e_bit = n_bit[0];
n_bit++;
endfunction
int n_logic = 0;
function logic e_logic();
$display("e_logic %1d", n_logic);
e_logic = ~n_logic[0];
n_logic++;
endfunction
// Basic types via typedefs
byte_t n_byte_t = 0;
function byte_t e_byte_t();
e_byte_t = 8'd10 + n_byte_t;
n_byte_t += 2;
endfunction
byte n_byte_unsigned_t = 0;
function byte_unsigned_t e_byte_unsigned_t();
e_byte_unsigned_t = 8'd20 + n_byte_unsigned_t;
n_byte_unsigned_t += 2;
endfunction
shortint_t n_shortint_t = 0;
function shortint_t e_shortint_t();
e_shortint_t = 16'd30 + n_shortint_t;
n_shortint_t += 2;
endfunction
shortint n_shortint_unsigned_t = 0;
function shortint_unsigned_t e_shortint_unsigned_t();
e_shortint_unsigned_t = 16'd40 + n_shortint_unsigned_t;
n_shortint_unsigned_t += 2;
endfunction
int_t n_int_t = 0;
function int_t e_int_t();
e_int_t = 32'd50 + n_int_t;
n_int_t += 2;
endfunction
int n_int_unsigned_t = 0;
function int_unsigned_t e_int_unsigned_t();
e_int_unsigned_t = 32'd60 + n_int_unsigned_t;
n_int_unsigned_t += 2;
endfunction
longint_t n_longint_t = 0;
function longint_t e_longint_t();
e_longint_t = 64'd70 + n_longint_t;
n_longint_t += 2;
endfunction
longint n_longint_unsigned_t = 0;
function longint_unsigned_t e_longint_unsigned_t();
e_longint_unsigned_t = 64'd80 + n_longint_unsigned_t;
n_longint_unsigned_t += 2;
endfunction
`ifndef NO_REAL_EXPORT
int n_real_t = 0;
function real_t e_real_t();
e_real_t = real'(2*n_real_t + 1) / 2.0;
n_real_t += 2;
endfunction
`endif
`ifndef NO_SHORTREAL
int n_shortreal_t = 0;
function shortreal_t e_shortreal_t();
e_shortreal_t = shortreal'(4*n_shortreal_t + 1)/ 4.0;
n_shortreal_t += 2;
endfunction
`endif
int n_chandle_t = 0;
function chandle_t e_chandle_t();
$display("e_chandle_t %1d", n_chandle_t);
e_chandle_t = `NULL;
n_chandle_t++;
endfunction
int n_string_t = 0;
function string_t e_string_t();
$display("e_string_t %1d", n_string_t);
e_string_t = n_string_t[0] ? "World" : "Hello";
n_string_t++;
endfunction
int n_bit_t = 0;
function bit_t e_bit_t();
$display("e_bit_t %1d", n_bit_t);
e_bit_t = n_bit_t[0];
n_bit_t++;
endfunction
int n_logic_t = 0;
function logic_t e_logic_t();
$display("e_logic_t %1d", n_logic_t);
e_logic_t = ~n_logic_t[0];
n_logic_t++;
endfunction
`ifndef NO_ARRAY
// 2-state packed arrays of width <= 32
int n_array_2_state_1 = 0;
function bit [ 0:0] e_array_2_state_1();
$display("e_array_2_state_1 %1d", n_array_2_state_1);
e_array_2_state_1 = n_array_2_state_1[0];
n_array_2_state_1++;
endfunction
int n_array_2_state_32 = 0;
function bit [31:0] e_array_2_state_32();
$display("e_array_2_state_32 %1d", n_array_2_state_32);
e_array_2_state_32 = ~32'd0 >> n_array_2_state_32;
n_array_2_state_32++;
endfunction
`endif
`ifndef NO_STRUCT_OR_UNION
// 2-state packed structures of width <= 32
int n_struct_2_state_1 = 0;
function struct_2_state_1 e_struct_2_state_1();
$display("e_struct_2_state_1 %1d", n_struct_2_state_1);
e_struct_2_state_1 = n_struct_2_state_1[0];
n_struct_2_state_1++;
endfunction
int n_struct_2_state_32 = 0;
function struct_2_state_32 e_struct_2_state_32();
$display("e_struct_2_state_32 %1d", n_struct_2_state_32);
e_struct_2_state_32 = ~32'd0 >> n_struct_2_state_32;
n_struct_2_state_32++;
endfunction
// 2-state packed unions of width <= 32
int n_union_2_state_1 = 0;
function union_2_state_1 e_union_2_state_1();
$display("e_union_2_state_1 %1d", n_union_2_state_1);
e_union_2_state_1 = n_union_2_state_1[0];
n_union_2_state_1++;
endfunction
int n_union_2_state_32 = 0;
function union_2_state_32 e_union_2_state_32();
$display("e_union_2_state_32 %1d", n_union_2_state_32);
e_union_2_state_32 = ~32'd0 >> n_union_2_state_32;
n_union_2_state_32++;
endfunction
`endif
//======================================================================
// Invoke all functions 3 times (they have side effects)
//======================================================================
import "DPI-C" context function void check_exports();
initial begin
for (int i = 0 ; i < 3; i++) begin
// Check the imports
// Basic types as per IEEE 1800-2017 35.5.5
i_void();
if (i_byte() !== 8'd10 - 8'(i)) $stop;
if (i_byte_unsigned() !== 8'd20 - 8'(i)) $stop;
if (i_shortint() !== 16'd30 - 16'(i)) $stop;
if (i_shortint_unsigned() !== 16'd40 - 16'(i)) $stop;
if (i_int() !== 32'd50 - 32'(i)) $stop;
if (i_int_unsigned() !== 32'd60 - 32'(i)) $stop;
if (i_longint() !== 64'd70 - 64'(i)) $stop;
if (i_longint_unsigned() !== 64'd80 - 64'(i)) $stop;
if (i_real() != -1.0*i - 0.5 ) $stop;
`ifndef NO_SHORTREAL
if (i_shortreal() != -1.0*i - 0.25) $stop;
`endif
if (~i[0]) begin
if (i_chandle() !== `NULL) $stop;
if (i_string() != "World") $stop;
end else begin
if (i_chandle() === `NULL) $stop;
if (i_string() != "Hello") $stop;
end
if (i_bit() !== ~i[0]) $stop;
if (i_logic() !== i[0]) $stop;
// Basic types via typedefs
if (i_byte_t() !== 8'd10 - 8'(2*i)) $stop;
if (i_byte_unsigned_t() !== 8'd20 - 8'(2*i)) $stop;
if (i_shortint_t() !== 16'd30 - 16'(2*i)) $stop;
if (i_shortint_unsigned_t() !== 16'd40 - 16'(2*i)) $stop;
if (i_int_t() !== 32'd50 - 32'(2*i)) $stop;
if (i_int_unsigned_t() !== 32'd60 - 32'(2*i)) $stop;
if (i_longint_t() !== 64'd70 - 64'(2*i)) $stop;
if (i_longint_unsigned_t() !== 64'd80 - 64'(2*i)) $stop;
if (i_real_t() != -1.0*(2*i) - 0.5 ) $stop;
`ifndef NO_SHORTREAL
if (i_shortreal_t() != -1.0*(2*i) - 0.25) $stop;
`endif
if (~i[0]) begin
if (i_chandle_t() !== `NULL) $stop;
if (i_string_t() != "World") $stop;
end else begin
if (i_chandle_t() === `NULL) $stop;
if (i_string_t() != "Hello") $stop;
end
if (i_bit_t() !== ~i[0]) $stop;
if (i_logic_t() !== i[0]) $stop;
`ifndef NO_ARRAY
// 2-state packed arrays of width <= 32
if (i_array_2_state_1() !== ~i[0] ) $stop;
if (i_array_2_state_32() !== ~32'd0 << i) $stop;
`endif
`ifndef NO_STRUCT_OR_UNION
// 2-state packed structures of width <= 32
if (i_struct_2_state_1() !== ~i[0] ) $stop;
if (i_struct_2_state_32() !== ~32'd0 << i) $stop;
// 2-state packed unions of width <= 32
if (i_union_2_state_1() !== ~i[0] ) $stop;
if (i_union_2_state_32() !== ~32'd0 << i) $stop;
`endif
// Check the exports
check_exports();
end
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module win (
clka,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [13 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [11 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [11 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("win.mif"),
.C_INIT_FILE("win.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(0),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(12),
.C_READ_WIDTH_A(12),
.C_WRITE_DEPTH_A(15120),
.C_READ_DEPTH_A(15120),
.C_ADDRA_WIDTH(14),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(12),
.C_READ_WIDTH_B(12),
.C_WRITE_DEPTH_B(15120),
.C_READ_DEPTH_B(15120),
.C_ADDRB_WIDTH(14),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("5"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 6.227751 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(1'D0),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(14'B0),
.dinb(12'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(12'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Wojtek Gumua
//
// Create Date: 20:18:43 04/19/2015
// Design Name:
// Module Name: rgb2hsv
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rgb2hsv(
input clk,
input ce,
input [7:0] R,
input [7:0] G,
input [7:0] B,
input in_hsync, // hsync data
input in_vsync, // vsync data
input in_de,
output [7:0] H,
output [7:0] S,
output [7:0] V,
output out_hsync, // hsync data
output out_vsync, // vsync data
output out_de
);
wire [7:0] q_R;
wire [7:0] q_G;
wire [7:0] q_B;
wire [7:0] f_R;
wire [7:0] f_G;
wire [7:0] f_B;
wire signed [9:0] n_R;
wire signed [9:0] n_G;
wire signed [9:0] n_B;
wire signed [9:0] v_max;
wire signed [9:0] v_min;
wire signed [9:0] v_delta;
wire [1:0] index_min;
wire [1:0] index_max;
// moduly dzielce RGB / 255
div255 divR (
.clk(clk), // input clk
//.rfd(rfd), // output rfd
.dividend(R), // input [7 : 0] dividend
.divisor(8'hFF), // input [7 : 0] divisor
.quotient(q_R), // output [7 : 0] quotient
.fractional(f_R) // output [7 : 0] fractional
);
div255 divG (
.clk(clk), // input clk
//.rfd(rfd), // output rfd
.dividend(G), // input [7 : 0] dividend
.divisor(8'hFF), // input [7 : 0] divisor
.quotient(q_G), // output [7 : 0] quotient
.fractional(f_G) // output [7 : 0] fractional
);
div255 divB (
.clk(clk), // input clk
//.rfd(rfd), // output rfd
.dividend(B), // input [7 : 0] dividend
.divisor(8'hFF), // input [7 : 0] divisor
.quotient(q_B), // output [7 : 0] quotient
.fractional(f_B) // output [7 : 0] fractional
);
assign n_R = {1'b0, q_R[1:0], f_R[6:1]};
assign n_G = {1'b0, q_G[1:0], f_G[6:1]};
assign n_B = {1'b0, q_B[1:0], f_B[6:1]};
//wyznaczanie wartoci max i min z RGB
min minRGB
(
.a(n_R),
.b(n_G),
.c(n_B),
.o(v_min),
.index(index_min)
);
max maxRGB
(
.a(n_R),
.b(n_G),
.c(n_B),
.o(v_max),
.index(index_max)
);
//wyznaczanie max - min
sub10 sub_delta (
.a(v_max), // input [9 : 0] a
.b(v_min), // input [9 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(v_delta) // output [9 : 0] s
);
//wyznaczanie S
wire [9:0] f_S;
wire [9:0] q_S;
div10 delta_div_max (
.clk(clk), // input clk
//.rfd(rfd), // output rfd
.dividend(v_delta), // input [9 : 0] dividend
.divisor(v_max), // input [9 : 0] divisor
.quotient(q_S), // output [9 : 0] quotient
.fractional(f_S) // output [9 : 0] fractional
);
wire [9:0] v_S;
assign v_S = (v_delta > 0 ) ? {1'b0, q_S[0], f_S[8:1]} : 10'b0;
//wyznaczanie H
wire [9:0] v_H [3:0];
wire [9:0] v_Subs [2:0];
wire [9:0] f_Subs [2:0];
wire [9:0] q_Subs [2:0];
sub10 G_sub_B (
.a(n_G), // input [9 : 0] a
.b(n_B), // input [9 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(v_Subs[0]) // output [9 : 0] s
);
sub10 B_sub_R (
.a(n_B), // input [9 : 0] a
.b(n_R), // input [9 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(v_Subs[1]) // output [9 : 0] s
);
sub10 R_sub_G (
.a(n_R), // input [9 : 0] a
.b(n_G), // input [9 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(v_Subs[2]) // output [9 : 0] s
);
div10 G_sub_B_div (
.clk(clk), // input clk
// .rfd(rfd), // output rfd
.dividend(v_Subs[0]), // input [9 : 0] dividend
.divisor(v_delta), // input [9 : 0] divisor
.quotient(q_Subs[0]), // output [9 : 0] quotient
.fractional(f_Subs[0]) // output [9 : 0] fractional
);
div10 B_sub_R_div (
.clk(clk), // input clk
// .rfd(rfd), // output rfd
.dividend(v_Subs[1]), // input [9 : 0] dividend
.divisor(v_delta), // input [9 : 0] divisor
.quotient(q_Subs[1]), // output [9 : 0] quotient
.fractional(f_Subs[1]) // output [9 : 0] fractional
);
div10 R_sub_G_div (
.clk(clk), // input clk
// .rfd(rfd), // output rfd
.dividend(v_Subs[2]), // input [9 : 0] dividend
.divisor(v_delta), // input [9 : 0] divisor
.quotient(q_Subs[2]), // output [9 : 0] quotient
.fractional(f_Subs[2]) // output [9 : 0] fractional
);
wire [9:0] v_H2;
assign v_H2 = (v_delta > 0) ? {q_Subs[index_max + 1][9], q_Subs[index_max + 1][0], f_Subs[index_max + 1][8:1]} : 10'b0;
wire [11:0] const_H[3:0];
wire [11:0] v_const_H;
assign const_H[0] = 12'b0;
assign const_H[1] = 12'b0;
assign const_H[2] = 12'h20;
assign v_const_H = (v_delta > 0) ? const_H[index_max] : 12'h0;
//dodawanie staej
wire [11:0] v_H3;
add12 add_H_const (
.a({v_H2[9], 2'b0, v_H2}), // input [11 : 0] a
.b(v_const_H), // input [11 : 0] b
.clk(clk), // input clk
.ce(ce), // input ce
.s(v_H3) // output [11 : 0] s
);
//sprawdzanie, czy H < 0
wire signed [11:0] v_H4;
assign v_H4 = (v_H3 > 0) ? v_H3 : (v_H3 + 12'h600);
wire [11:0] q_H2;
wire [11:0] f_H2;
//dzielenie przez 6 (!!!)
div12 div_H_6 (
.clk(clk), // input clk
// .rfd(rfd), // output rfd
.dividend(v_H4), // input [11 : 0] dividend
.divisor({12'h600}), // input [11 : 0] divisor
.quotient(q_H2), // output [11 : 0] quotient
.fractional(f_H2) // output [11 : 0] fractional
);
wire signed [9:0] v_H5;
assign v_H5 = {q_H2[11], q_H2[0], f_H2[10:3]};
wire signed [16:0] H1;
wire signed [16:0] S1;
wire signed [16:0] V1;
mul9 mul_255_H (
.clk(clk), // input clk
.a(v_H5[7:0]), // input [8 : 0] a
.p(H1) // output [16 : 0] p
);
mul9 mul_255_S (
.clk(clk), // input clk
.a(v_S[7:0]), // input [8 : 0] a
.p(S1) // output [16 : 0] p
);
mul9 mul_255_V (
.clk(clk), // input clk
.a(v_max[7:0]), // input [8 : 0] a
.p(V1) // output [16 : 0] p
);
assign H = H1[15:8];
assign S = S1[15:8];
assign V = V1[15:8];
assign out_hsync = in_hsync;
assign out_vsync = in_vsync;
assign out_de = in_de;
endmodule
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export NthDerivative.
Opaque Min Max.
Section Intervals.
(** printing realline %\ensuremath{\RR}% #(-∞,+∞)# *)
(** printing openl %\ensuremath{(\cdot,+\infty)}% #(⋅,+∞)# *)
(** printing openr %\ensuremath{(-\infty,\cdot)}% #(-∞,⋅)# *)
(** printing closel %\ensuremath{[\cdot,+\infty)}% #[⋅,+∞)# *)
(** printing closer %\ensuremath{(-\infty,\cdot]}% #(-∞,⋅]# *)
(** printing olor %\ensuremath{(\cdot,\cdot)}% #(⋅,⋅)# *)
(** printing clor %\ensuremath{[\cdot,\cdot)}% #[⋅,⋅)# *)
(** printing olcr %\ensuremath{(\cdot,\cdot]}% #(⋅,⋅]# *)
(** printing clcr %\ensuremath{[\cdot,\cdot]}% #[⋅,⋅]# *)
(**
* Generalized Intervals
At this stage we have enough material to begin generalizing our
concepts in preparation for the fundamental theorem of calculus and
the definition of the main (non-polynomial) functions of analysis.
In order to define functions via power series (or any other kind of
series) we need to formalize a notion of convergence more general than
the one we already have on compact intervals. This is necessary for
practical reasons: we want to define a single exponential function
with domain [IR], not several exponential functions defined on compact
intervals which we prove to be the same wherever their domains
overlap. In a similar way, we want to define indefinite integrals on
infinite domains and not only on compact intervals.
Unfortunately, proceeding in a way analogous to how we defined the
concept of global continuity will lead us nowhere; the concept turns
out to be to general, and the behaviour on too small domains
(typically intervals [[a,a']] where [a [=] a'] is neither
provably true nor provably false) will be unsatisfactory.
There is a special family of sets, however, where this problems can be
avoided: intervals. Intervals have some nice properties that allow us
to prove good results, namely the facts that if [a] and [b] are
elements of an interval [I] then so are [Min(a,b)] and
[Max(a,b)] (which is in general not true) and also the
compact interval [[a,b]] is included in [I]. Furthermore, all
intervals are characterized by simple, well defined predicates, and
the nonempty and proper concepts become very easy to define.
** Definitions and Basic Results
We define an inductive type of intervals with nine constructors,
corresponding to the nine basic types of intervals. The reason why so
many constructors are needed is that we do not have a notion of real
line, for many reasons which we will not discuss here. Also it seems
simple to directly define finite intervals than to define then later
as intersections of infinite intervals, as it would only mess things
up.
The compact interval which we will define here is obviously the same
that we have been working with all the way through; why, then, the
different formulation? The reason is simple: if we had worked with
intervals from the beginning we would have had case definitions at
every spot, and our lemmas and proofs would have been very awkward.
Also, it seems more natural to characterize a compact interval by two
real numbers (and a proof) than as a particular case of a more general
concept which doesn't have an intuitive interpretation. Finally, the
definitions we will make here will have the elegant consequence that
from this point on we can work with any kind of intervals in exactly
the same way.
*)
Inductive interval : Type :=
| realline : interval
| openl : IR -> interval
| openr : IR -> interval
| closel : IR -> interval
| closer : IR -> interval
| olor : IR -> IR -> interval
| olcr : IR -> IR -> interval
| clor : IR -> IR -> interval
| clcr : IR -> IR -> interval.
(**
To each interval a predicate (set) is assigned by the following map:
*)
Definition iprop (I : interval) (x : IR) : CProp :=
match I with
| realline => True
| openr b => x [<] b
| openl a => a [<] x
| closer b => x [<=] b
| closel a => a [<=] x
| olor a b => a [<] x and x [<] b
| olcr a b => a [<] x and x [<=] b
| clor a b => a [<=] x and x [<] b
| clcr a b => a [<=] x and x [<=] b
end.
(* begin hide *)
Coercion iprop : interval >-> Funclass.
(* end hide *)
(**
This map is made into a coercion, so that intervals
%\emph{%#<i>#are%}%#</i># really subsets of reals.
We now define what it means for an interval to be nonvoid, proper,
finite and compact in the obvious way.
*)
Definition nonvoid (I : interval) : CProp :=
match I with
| realline => True
| openr b => True
| openl a => True
| closer b => True
| closel a => True
| olor a b => a [<] b
| olcr a b => a [<] b
| clor a b => a [<] b
| clcr a b => a [<=] b
end.
Definition proper (I : interval) : CProp :=
match I with
| realline => True
| openr b => True
| openl a => True
| closer b => True
| closel a => True
| olor a b => a [<] b
| olcr a b => a [<] b
| clor a b => a [<] b
| clcr a b => a [<] b
end.
Definition finite (I : interval) : CProp :=
match I with
| realline => False
| openr b => False
| openl a => False
| closer b => False
| closel a => False
| olor a b => True
| olcr a b => True
| clor a b => True
| clcr a b => True
end.
Definition compact_ (I : interval) : CProp :=
match I with
| realline => False
| openr b => False
| openl a => False
| closer b => False
| closel a => False
| olor a b => False
| olcr a b => False
| clor a b => False
| clcr a b => a [<=] b
end.
(** Finite intervals have a left end and a right end. *)
Definition left_end (I : interval) : finite I -> IR.
Proof.
intro.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; rename X into H.
inversion H.
inversion H.
inversion H.
inversion H.
inversion H.
apply c.
apply c.
apply c.
apply c.
Defined.
Definition right_end (I : interval) : finite I -> IR.
Proof.
intro.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; rename X into H.
inversion H.
inversion H.
inversion H.
inversion H.
inversion H.
apply c0.
apply c0.
apply c0.
apply c0.
Defined.
(**
Some trivia: compact intervals are finite; proper intervals are nonvoid; an interval is nonvoid iff it contains some point.
*)
Lemma compact_finite : forall I : interval, compact_ I -> finite I.
intros; induction I as [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; auto.
Qed.
Lemma proper_nonvoid : forall I : interval, proper I -> nonvoid I.
Proof.
intro.
elim I; simpl in |- *; intros; auto.
apply less_leEq; auto.
Qed.
Lemma nonvoid_point : forall I : interval, nonvoid I -> {x : IR | I x}.
Proof.
intro.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try rename X into H.
exists ZeroR; auto.
exists (c[+][1]); apply less_plusOne.
exists (c[-][1]); apply shift_minus_less; apply less_plusOne.
exists c; apply leEq_reflexive.
exists c; apply leEq_reflexive.
exists (c[+] (c0[-]c) [/]TwoNZ); split.
astepl (c[+][0]); apply plus_resp_less_lft.
apply div_resp_pos.
apply pos_two.
apply shift_less_minus; astepl c; auto.
rstepr (c[+] (c0[-]c)).
apply plus_resp_less_lft.
apply pos_div_two'.
apply shift_less_minus; astepl c; auto.
exists c0; split; auto; apply leEq_reflexive.
exists c; split; auto; apply leEq_reflexive.
exists c; split; [ apply leEq_reflexive | auto ].
Qed.
Lemma nonvoid_char : forall (I : interval) (x : IR), I x -> nonvoid I.
Proof.
intro; induction I; simpl in |- *; intros x H; auto; inversion_clear H.
apply less_transitive_unfolded with x; auto.
apply less_leEq_trans with x; auto.
apply leEq_less_trans with x; auto.
apply leEq_transitive with x; auto.
Qed.
(**
For practical reasons it helps to define left end and right end of compact intervals.
*)
Definition Lend I (H : compact_ I) := left_end I (compact_finite I H).
Definition Rend I (H : compact_ I) := right_end I (compact_finite I H).
(** In a compact interval, the left end is always less than or equal
to the right end.
*)
Lemma Lend_leEq_Rend : forall I cI, Lend I cI [<=] Rend I cI.
Proof.
intro; elim I; simpl in |- *; intros; try inversion cI; auto.
Qed.
(**
Some nice characterizations of inclusion:
*)
Lemma compact_included : forall a b Hab (I : interval),
I a -> I b -> included (compact a b Hab) I.
Proof.
induction I; red in |- *; simpl in |- *; intros X X0 x X1;
try inversion_clear X; try inversion_clear X0; try inversion_clear X1.
auto.
apply less_leEq_trans with a; auto.
apply leEq_less_trans with b; auto.
apply leEq_transitive with a; auto.
apply leEq_transitive with b; auto.
split; [ apply less_leEq_trans with a | apply leEq_less_trans with b ]; auto.
split; [ apply less_leEq_trans with a | apply leEq_transitive with b ]; auto.
split; [ apply leEq_transitive with a | apply leEq_less_trans with b ]; auto.
split; [ apply leEq_transitive with a | apply leEq_transitive with b ]; auto.
Qed.
Lemma included_interval' : forall (I : interval) x y z w, I x -> I y -> I z -> I w ->
forall H, included (compact (Min x z) (Max y w) H) I.
Proof.
intros I x y z w; induction I; simpl in |- *; intros X X0 X1 X2 H; red in |- *; intros t Ht;
inversion_clear Ht; simpl in |- *; try inversion_clear X;
try inversion_clear X0; try inversion_clear X1; try inversion_clear X2; try split.
apply less_leEq_trans with (Min x z); try apply less_Min; auto.
apply leEq_less_trans with (Max y w); try apply Max_less; auto.
apply leEq_transitive with (Min x z); try apply leEq_Min; auto.
apply leEq_transitive with (Max y w); try apply Max_leEq; auto.
apply less_leEq_trans with (Min x z); try apply less_Min; auto.
apply leEq_less_trans with (Max y w); try apply Max_less; auto.
apply less_leEq_trans with (Min x z); try apply less_Min; auto.
apply leEq_transitive with (Max y w); try apply Max_leEq; auto.
apply leEq_transitive with (Min x z); try apply leEq_Min; auto.
apply leEq_less_trans with (Max y w); try apply Max_less; auto.
apply leEq_transitive with (Min x z); try apply leEq_Min; auto.
apply leEq_transitive with (Max y w); try apply Max_leEq; auto.
Qed.
Lemma included_interval : forall (I : interval) x y, I x -> I y ->
forall H, included (compact (Min x y) (Max x y) H) I.
Proof.
intros; apply included_interval'; auto.
Qed.
(**
A weirder inclusion result.
*)
Lemma included3_interval : forall (I : interval) x y z Hxyz, I x -> I y -> I z ->
included (compact (Min (Min x y) z) (Max (Max x y) z) Hxyz) I.
Proof.
intros I x y z Hxyz H H0 H1.
apply included_interval'; auto.
apply (included_interval I x y H H0 (Min_leEq_Max _ _)).
apply compact_inc_lft.
apply (included_interval I x y H H0 (Min_leEq_Max _ _)).
apply compact_inc_rht.
Qed.
(**
Finally, all intervals are characterized by well defined predicates.
*)
Lemma iprop_wd : forall I : interval, pred_wd _ I.
Proof.
induction I; unfold iprop in |- *; red in |- *; intros x y X X0;
try inversion_clear X; try inversion X0.
auto.
astepr x; auto.
astepl x; auto.
astepr x; auto.
astepl x; auto.
split.
astepr x; auto.
astepl x; auto.
split.
astepr x; auto.
astepl x; auto.
split.
astepr x; auto.
astepl x; auto.
split.
astepr x; auto.
astepl x; auto.
Qed.
End Intervals.
Implicit Arguments Lend [I].
Implicit Arguments Rend [I].
Section Compact_Constructions.
Section Single_Compact_Interval.
(**
** Constructions with Compact Intervals
Several important constructions are now discussed.
We begin by defining the compact interval [[x,x]].
%\begin{convention}% Let [P:IR->CProp] be well defined, and [x:IR]
such that [P(x)] holds.
%\end{convention}%
*)
Variable P : IR -> CProp.
Hypothesis wdP : pred_wd IR P.
Variable x : IR.
Hypothesis Hx : P x.
Definition compact_single := Compact (leEq_reflexive _ x).
(**
This interval contains [x] and only (elements equal to) [x]; furthermore, for every (well-defined) [P], if $x\in P$#x∈P# then $[x,x]\subseteq P$#[x,x]⊆P#.
*)
Lemma compact_single_prop : compact_single x.
Proof.
split; apply leEq_reflexive.
Qed.
Lemma compact_single_pt : forall y : IR, compact_single y -> x [=] y.
Proof.
intros y H.
inversion_clear H; apply leEq_imp_eq; auto.
Qed.
Lemma compact_single_inc : included compact_single P.
Proof.
red in |- *; intros.
apply wdP with x.
auto.
apply compact_single_pt; auto.
Qed.
End Single_Compact_Interval.
(**
The special case of intervals is worth singling out, as one of the hypothesis becomes a theorem.
*)
Definition compact_single_iprop I := compact_single_inc _ (iprop_wd I).
(**
Now for more interesting and important results.
Let [I] be a proper interval and [x] be a point of [I]. Then there is
a proper compact interval [[a,b]] such that $x\in[a,b]\subseteq
I$#x∈[a,b]⊆I#.
*)
Section Proper_Compact_with_One_or_Two_Points.
(* begin hide *)
Let cip1' : forall c x : IR, c [<=] x -> x[-] (x[-]c) [/]TwoNZ [<=] x.
Proof.
intros.
astepr (x[-][0]).
unfold cg_minus at 1 3 in |- *; apply plus_resp_leEq_lft.
apply inv_resp_leEq; apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl c; auto.
Qed.
Let cip1'' : forall c x : IR, c [<] x -> x[-] (x[-]c) [/]TwoNZ [<] x.
Proof.
intros.
astepr (x[-][0]).
unfold cg_minus at 1 3 in |- *; apply plus_resp_less_lft.
apply inv_resp_less; apply shift_less_div.
apply pos_two.
apply shift_less_minus; rstepl c; auto.
Qed.
Let cip1''' : forall c0 x : IR, x [<=] c0 -> x [<=] x[+] (c0[-]x) [/]TwoNZ.
Proof.
intros.
astepl (x[+][0]).
apply plus_resp_leEq_lft.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl x; auto.
Qed.
Let cip1'''' : forall c0 x : IR, x [<] c0 -> x [<] x[+] (c0[-]x) [/]TwoNZ.
Proof.
intros.
astepl (x[+][0]).
apply plus_resp_less_lft.
apply shift_less_div.
apply pos_two.
apply shift_less_minus; rstepl x; auto.
Qed.
Let cip2 :
forall c x x0 : IR, c [<=] x -> x[-] (x[-]c) [/]TwoNZ [<=] x0 -> c [<=] x0.
Proof.
intros.
apply leEq_transitive with (c[+] (x[-]c) [/]TwoNZ).
astepl (c[+][0]); apply plus_resp_leEq_lft.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl c; auto.
eapply leEq_wdl.
apply H0.
rational.
Qed.
Let cip2' : forall c x x0 : IR, c [<] x -> x[-] (x[-]c) [/]TwoNZ [<=] x0 -> c [<] x0.
Proof.
intros c x x0 H H0.
apply less_leEq_trans with (c[+] (x[-]c) [/]TwoNZ).
astepl (c[+][0]); apply plus_resp_less_lft.
apply shift_less_div.
apply pos_two.
apply shift_less_minus; rstepl c; auto.
eapply leEq_wdl.
apply H0.
rational.
Qed.
Let cip2'' :
forall c x x0 : IR, c [<=] x -> x[-] (x[-]c) [/]TwoNZ [<] x0 -> c [<] x0.
Proof.
intros c x x0 H H0.
apply leEq_less_trans with (c[+] (x[-]c) [/]TwoNZ).
astepl (c[+][0]); apply plus_resp_leEq_lft.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl c; auto.
eapply less_wdl.
apply H0.
rational.
Qed.
Let cip2''' :
forall c x x0 : IR, c [<] x -> x[-] (x[-]c) [/]TwoNZ [<] x0 -> c [<] x0.
Proof.
intros c x x0 H H0.
apply cip2'' with x.
apply less_leEq; auto.
auto.
Qed.
Let cip3 :
forall c0 x x0 : IR, x [<=] c0 -> x0 [<=] x[+] (c0[-]x) [/]TwoNZ -> x0 [<=] c0.
Proof.
intros c0 x x0 H H0.
eapply leEq_transitive.
apply H0.
rstepl (c0[-] (c0[-]x) [/]TwoNZ).
astepr (c0[-][0]); unfold cg_minus at 1 3 in |- *; apply plus_resp_leEq_lft.
apply inv_resp_leEq.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl x; auto.
Qed.
Let cip3' :
forall c0 x x0 : IR, x [<] c0 -> x0 [<=] x[+] (c0[-]x) [/]TwoNZ -> x0 [<] c0.
Proof.
intros c0 x x0 H H0.
eapply leEq_less_trans.
apply H0.
rstepl (c0[-] (c0[-]x) [/]TwoNZ).
astepr (c0[-][0]); unfold cg_minus at 1 3 in |- *; apply plus_resp_less_lft.
apply inv_resp_less.
apply shift_less_div.
apply pos_two.
apply shift_less_minus; rstepl x; auto.
Qed.
Let cip3'' :
forall c0 x x0 : IR, x [<=] c0 -> x0 [<] x[+] (c0[-]x) [/]TwoNZ -> x0 [<] c0.
Proof.
intros c0 x x0 H H0.
eapply less_leEq_trans.
apply H0.
rstepl (c0[-] (c0[-]x) [/]TwoNZ).
astepr (c0[-][0]); unfold cg_minus at 1 3 in |- *; apply plus_resp_leEq_lft.
apply inv_resp_leEq.
apply shift_leEq_div.
apply pos_two.
apply shift_leEq_minus; rstepl x; auto.
Qed.
Let cip3''' :
forall c0 x x0 : IR, x [<] c0 -> x0 [<] x[+] (c0[-]x) [/]TwoNZ -> x0 [<] c0.
Proof.
intros c0 x x0 H H0.
apply cip3'' with x; try apply less_leEq; auto.
Qed.
(* end hide *)
Definition compact_in_interval I (pI : proper I) x (Hx : I x) : interval.
Proof.
intros; destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros.
apply (clcr x (x[+][1])).
apply (clcr x (x[+][1])).
apply (clcr (x[-][1]) x).
apply (clcr x (x[+][1])).
apply (clcr (x[-][1]) x).
apply (clcr (x[-] (x[-]c) [/]TwoNZ) (x[+] (c0[-]x) [/]TwoNZ)).
apply (clcr (x[-] (x[-]c) [/]TwoNZ) (x[+] (c0[-]x) [/]TwoNZ)).
apply (clcr (x[-] (x[-]c) [/]TwoNZ) (x[+] (c0[-]x) [/]TwoNZ)).
apply (clcr c c0).
Defined.
Lemma compact_compact_in_interval : forall I pI x Hx,
compact_ (compact_in_interval I pI x Hx).
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try apply ts; apply less_leEq.
apply less_plusOne.
apply less_plusOne.
apply shift_minus_less; apply less_plusOne.
apply less_plusOne.
apply shift_minus_less; apply less_plusOne.
eapply less_transitive_unfolded; [ apply cip1'' | apply cip1'''' ]; auto.
eapply less_leEq_trans; [ apply cip1'' | apply cip1''' ]; auto.
eapply leEq_less_trans; [ apply cip1' | apply cip1'''' ]; auto.
auto.
Qed.
Lemma proper_compact_in_interval : forall I pI x Hx,
proper (compact_in_interval I pI x Hx).
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx.
apply less_plusOne.
apply less_plusOne.
apply shift_minus_less; apply less_plusOne.
apply less_plusOne.
apply shift_minus_less; apply less_plusOne.
eapply less_transitive_unfolded; [ apply cip1'' | apply cip1'''' ]; auto.
eapply less_leEq_trans; [ apply cip1'' | apply cip1''' ]; auto.
eapply leEq_less_trans; [ apply cip1' | apply cip1'''' ]; auto.
auto.
Qed.
Lemma proper_compact_in_interval' : forall I pI x Hx
(H : compact_ (compact_in_interval I pI x Hx)), Lend H [<] Rend H.
Proof.
do 4 intro.
cut (proper (compact_in_interval I pI x Hx)).
2: apply proper_compact_in_interval.
elim (compact_in_interval I pI x Hx); intros; try inversion H.
simpl in |- *; simpl in H; auto.
Qed.
Lemma included_compact_in_interval : forall I pI x Hx,
included (compact_in_interval I pI x Hx) I.
Proof.
induction I; simpl in |- *; intros X x X0; try inversion_clear Hx; red in |- *;
simpl in |- *; intros x0 X1; try inversion_clear X; try inversion_clear X0;
try inversion_clear X1; auto.
apply less_leEq_trans with x; auto.
apply leEq_less_trans with x; auto.
apply leEq_transitive with x; auto.
apply leEq_transitive with x; auto.
split.
apply cip2' with x; auto.
apply cip3' with x; auto.
split.
apply cip2' with x; auto.
apply cip3 with x; auto.
split.
apply cip2 with x; auto.
apply cip3' with x; auto.
Qed.
Lemma iprop_compact_in_interval : forall I pI x Hx, compact_in_interval I pI x Hx x.
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; split; auto; try apply leEq_reflexive.
apply less_leEq; apply less_plusOne.
apply less_leEq; apply less_plusOne.
apply less_leEq; apply shift_minus_less; apply less_plusOne.
apply less_leEq; apply less_plusOne.
apply less_leEq; apply shift_minus_less; apply less_plusOne.
apply less_leEq; apply cip1''; auto.
apply less_leEq; apply cip1''''; auto.
apply less_leEq; apply cip1''; auto.
apply less_leEq; apply cip1''''; auto.
Qed.
Lemma iprop_compact_in_interval' : forall I pI x Hx
(H : compact_ (compact_in_interval I pI x Hx)) H', compact (Lend H) (Rend H) H' x.
Proof.
do 4 intro.
cut (compact_in_interval I pI x Hx x).
2: apply iprop_compact_in_interval.
elim (compact_in_interval I pI x Hx); intros; try inversion H.
simpl in |- *; auto.
Qed.
Lemma iprop_compact_in_interval_inc1 : forall I pI x Hx
(H : compact_ (compact_in_interval I pI x Hx)) H',
included (compact (Lend H) (Rend H) H') (compact_in_interval I pI x Hx).
Proof.
do 4 intro.
elim (compact_in_interval I pI x Hx); intros; try inversion H.
unfold compact in |- *; simpl in |- *; Included.
Qed.
Lemma iprop_compact_in_interval_inc2 : forall I pI x Hx
(H : compact_ (compact_in_interval I pI x Hx)) H',
included (compact_in_interval I pI x Hx) (compact (Lend H) (Rend H) H').
Proof.
do 4 intro.
elim (compact_in_interval I pI x Hx); intros; try inversion H.
unfold compact in |- *; simpl in |- *; Included.
Qed.
(**
If [x [=] y] then the construction yields the same interval whether we
use [x] or [y] in its definition. This property is required at some
stage, which is why we formalized this result as a functional
definition rather than as an existential formula.
*)
Lemma compact_in_interval_wd1 : forall I pI x Hx y Hy
(H : compact_ (compact_in_interval I pI x Hx))
(H' : compact_ (compact_in_interval I pI y Hy)),
x [=] y -> Lend H [=] Lend H'.
Proof.
intro I; elim I; simpl in |- *; intros; algebra.
Qed.
Lemma compact_in_interval_wd2 : forall I pI x Hx y Hy
(H : compact_ (compact_in_interval I pI x Hx))
(H' : compact_ (compact_in_interval I pI y Hy)),
x [=] y -> Rend H [=] Rend H'.
Proof.
intro I; elim I; simpl in |- *; intros; algebra.
Qed.
(**
We can make an analogous construction for two points.
*)
Definition compact_in_interval2 I (pI : proper I) x y : I x -> I y -> interval.
Proof.
intros.
set (z1 := Min x y) in *.
set (z2 := Max x y) in *.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros.
apply (clcr z1 (z2[+][1])).
apply (clcr z1 (z2[+][1])).
apply (clcr (z1[-][1]) z2).
apply (clcr z1 (z2[+][1])).
apply (clcr (z1[-][1]) z2).
apply (clcr (z1[-] (z1[-]c) [/]TwoNZ) (z2[+] (c0[-]z2) [/]TwoNZ)).
apply (clcr (z1[-] (z1[-]c) [/]TwoNZ) (z2[+] (c0[-]z2) [/]TwoNZ)).
apply (clcr (z1[-] (z1[-]c) [/]TwoNZ) (z2[+] (c0[-]z2) [/]TwoNZ)).
apply (clcr c c0).
Defined.
Lemma compact_compact_in_interval2 : forall I pI x y Hx Hy,
compact_ (compact_in_interval2 I pI x y Hx Hy).
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try inversion_clear Hy;
try apply ts; apply less_leEq.
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply shift_minus_less; apply leEq_less_trans with (Max x y);
[ apply Min_leEq_Max | apply less_plusOne ].
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply shift_minus_less; apply leEq_less_trans with (Max x y);
[ apply Min_leEq_Max | apply less_plusOne ].
eapply less_transitive_unfolded; [ apply cip1''
| eapply leEq_less_trans; [ apply Min_leEq_Max | apply cip1'''' ] ];
try apply less_Min; try apply Max_less; auto.
eapply less_leEq_trans; [ apply cip1''
| eapply leEq_transitive; [ apply Min_leEq_Max | apply cip1''' ] ];
try apply less_Min; try apply Max_leEq; auto.
eapply leEq_less_trans; [ apply cip1'
| eapply leEq_less_trans; [ apply Min_leEq_Max | apply cip1'''' ] ];
try apply leEq_Min; try apply Max_less; auto.
auto.
Qed.
Lemma proper_compact_in_interval2 : forall I pI x y Hx Hy,
proper (compact_in_interval2 I pI x y Hx Hy).
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try inversion_clear Hy.
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply shift_minus_less; apply leEq_less_trans with (Max x y);
[ apply Min_leEq_Max | apply less_plusOne ].
apply leEq_less_trans with (Max x y); [ apply Min_leEq_Max | apply less_plusOne ].
apply shift_minus_less; apply leEq_less_trans with (Max x y);
[ apply Min_leEq_Max | apply less_plusOne ].
eapply less_transitive_unfolded; [ apply cip1''
| eapply leEq_less_trans; [ apply Min_leEq_Max | apply cip1'''' ] ];
try apply less_Min; try apply Max_less; auto.
eapply less_leEq_trans; [ apply cip1''
| eapply leEq_transitive; [ apply Min_leEq_Max | apply cip1''' ] ];
try apply less_Min; try apply Max_leEq; auto.
eapply leEq_less_trans; [ apply cip1'
| eapply leEq_less_trans; [ apply Min_leEq_Max | apply cip1'''' ] ];
try apply leEq_Min; try apply Max_less; auto.
auto.
Qed.
Lemma proper_compact_in_interval2' : forall I pI x y Hx Hy H,
Lend (I:=compact_in_interval2 I pI x y Hx Hy) H [<]
Rend (I:=compact_in_interval2 I pI x y Hx Hy) H.
Proof.
do 6 intro.
cut (proper (compact_in_interval2 I pI x y Hx Hy)).
2: apply proper_compact_in_interval2.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
simpl in |- *; simpl in H; auto.
Qed.
Lemma included_compact_in_interval2 : forall I pI x y Hx Hy,
included (compact_in_interval2 I pI x y Hx Hy) I.
Proof.
induction I; simpl in |- *; intros; try inversion_clear Hx as (H,H0);
try inversion_clear Hy as (H1,H2); red in |- *; simpl in |- *;
intros x0 X; try inversion_clear X; auto.
apply less_leEq_trans with (Min x y); try apply less_Min; auto.
apply leEq_less_trans with (Max x y); try apply Max_less; auto.
apply leEq_transitive with (Min x y); try apply leEq_Min; auto.
apply leEq_transitive with (Max x y); try apply Max_leEq; auto.
split.
apply cip2' with (Min x y); try apply less_Min; auto.
apply cip3' with (Max x y); try apply Max_less; auto.
split.
apply cip2' with (Min x y); try apply less_Min; auto.
apply cip3 with (Max x y); try apply Max_leEq; auto.
split.
apply cip2 with (Min x y); try apply leEq_Min; auto.
apply cip3' with (Max x y); try apply Max_less; auto.
Qed.
Lemma iprop_compact_in_interval2x : forall I pI x y Hx Hy,
compact_in_interval2 I pI x y Hx Hy x.
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try inversion_clear Hy;
split; auto; try apply Min_leEq_lft; try apply lft_leEq_Max.
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply lft_leEq_Max | apply less_plusOne ].
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply lft_leEq_Max | apply less_plusOne ].
apply less_leEq; apply shift_minus_less; apply leEq_less_trans with x;
[ apply Min_leEq_lft | apply less_plusOne ].
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply lft_leEq_Max | apply less_plusOne ].
apply less_leEq; apply shift_minus_less; apply leEq_less_trans with x;
[ apply Min_leEq_lft | apply less_plusOne ].
apply less_leEq; eapply less_leEq_trans; [ apply cip1'' | apply Min_leEq_lft ]; try apply less_Min;
auto.
apply less_leEq; apply leEq_less_trans with (Max x y);
[ apply lft_leEq_Max | apply cip1'''' ]; try apply Max_less; auto.
apply less_leEq; eapply less_leEq_trans; [ apply cip1'' | apply Min_leEq_lft ]; try apply less_Min;
auto.
apply leEq_transitive with (Max x y); [ apply lft_leEq_Max | apply cip1''' ];
try apply Max_leEq; auto.
eapply leEq_transitive; [ apply cip1' | apply Min_leEq_lft ]; try apply leEq_Min; auto.
apply less_leEq; apply leEq_less_trans with (Max x y);
[ apply lft_leEq_Max | apply cip1'''' ]; try apply Max_less; auto.
Qed.
Lemma iprop_compact_in_interval2y : forall I pI x y Hx Hy,
compact_in_interval2 I pI x y Hx Hy y.
Proof.
intro.
elim I; simpl in |- *; intros; try inversion_clear Hx; try inversion_clear Hy;
split; auto; try apply Min_leEq_rht; try apply rht_leEq_Max.
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply rht_leEq_Max | apply less_plusOne ].
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply rht_leEq_Max | apply less_plusOne ].
apply less_leEq; apply shift_minus_less; apply leEq_less_trans with y;
[ apply Min_leEq_rht | apply less_plusOne ].
apply less_leEq; apply leEq_less_trans with (Max x y); [ apply rht_leEq_Max | apply less_plusOne ].
apply less_leEq; apply shift_minus_less; apply leEq_less_trans with y;
[ apply Min_leEq_rht | apply less_plusOne ].
apply less_leEq; eapply less_leEq_trans; [ apply cip1'' | apply Min_leEq_rht ]; try apply less_Min;
auto.
apply less_leEq; apply leEq_less_trans with (Max x y);
[ apply rht_leEq_Max | apply cip1'''' ]; try apply Max_less; auto.
apply less_leEq; eapply less_leEq_trans; [ apply cip1'' | apply Min_leEq_rht ]; try apply less_Min;
auto.
apply leEq_transitive with (Max x y); [ apply rht_leEq_Max | apply cip1''' ];
try apply Max_leEq; auto.
eapply leEq_transitive; [ apply cip1' | apply Min_leEq_rht ]; try apply leEq_Min; auto.
apply less_leEq; apply leEq_less_trans with (Max x y);
[ apply rht_leEq_Max | apply cip1'''' ]; try apply Max_less; auto.
Qed.
Lemma iprop_compact_in_interval2x' : forall I pI x y Hx Hy
(H : compact_ (compact_in_interval2 I pI x y Hx Hy)) H',
compact (Lend H) (Rend H) H' x.
Proof.
do 6 intro.
cut (compact_in_interval2 I pI x y Hx Hy x).
2: apply iprop_compact_in_interval2x.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
simpl in |- *; auto.
Qed.
Lemma iprop_compact_in_interval2y' : forall I pI x y Hx Hy
(H : compact_ (compact_in_interval2 I pI x y Hx Hy)) H',
compact (Lend H) (Rend H) H' y.
Proof.
do 6 intro.
cut (compact_in_interval2 I pI x y Hx Hy y).
2: apply iprop_compact_in_interval2y.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
simpl in |- *; auto.
Qed.
Lemma iprop_compact_in_interval2_inc1 : forall I pI x y Hx Hy
(H : compact_ (compact_in_interval2 I pI x y Hx Hy)) H',
included (compact (Lend H) (Rend H) H') (compact_in_interval2 I pI x y Hx Hy).
Proof.
do 6 intro.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
unfold compact in |- *; unfold iprop in |- *; simpl in |- *; Included.
Qed.
Lemma iprop_compact_in_interval2_inc2 : forall I pI x y Hx Hy
(H : compact_ (compact_in_interval2 I pI x y Hx Hy)) H',
included (compact_in_interval2 I pI x y Hx Hy) (compact (Lend H) (Rend H) H').
Proof.
do 6 intro.
elim (compact_in_interval2 I pI x y Hx Hy); intros; try inversion H.
unfold compact in |- *; unfold iprop in |- *; simpl in |- *; Included.
Qed.
Lemma compact_in_interval_x_lft : forall I pI x y Hx Hy H H',
Lend (I:=compact_in_interval2 I pI x y Hx Hy) H [<=]
Lend (I:=compact_in_interval I pI x Hx) H'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try apply minus_resp_leEq;
try apply Min_leEq_lft; try apply leEq_reflexive;
(rstepl (c[+] (Min x y[-]c) [/]TwoNZ); rstepr (c[+] (x[-]c) [/]TwoNZ);
apply plus_resp_leEq_lft; apply div_resp_leEq;
[ apply pos_two | apply minus_resp_leEq; apply Min_leEq_lft ]).
Qed.
Lemma compact_in_interval_y_lft : forall I pI x y Hx Hy H H',
Lend (I:=compact_in_interval2 I pI x y Hx Hy) H [<=]
Lend (I:=compact_in_interval I pI y Hy) H'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try apply minus_resp_leEq;
try apply Min_leEq_rht; try apply leEq_reflexive;
(rstepl (c[+] (Min x y[-]c) [/]TwoNZ); rstepr (c[+] (y[-]c) [/]TwoNZ);
apply plus_resp_leEq_lft; apply div_resp_leEq;
[ apply pos_two | apply minus_resp_leEq; apply Min_leEq_rht ]).
Qed.
Lemma compact_in_interval_x_rht : forall I pI x y Hx Hy H H',
Rend (I:=compact_in_interval I pI x Hx) H [<=]
Rend (I:=compact_in_interval2 I pI x y Hx Hy) H'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try apply plus_resp_leEq;
try apply lft_leEq_Max; try apply leEq_reflexive;
(rstepl (c0[-] (c0[-]x) [/]TwoNZ); rstepr (c0[-] (c0[-]Max x y) [/]TwoNZ);
unfold cg_minus in |- *; apply plus_resp_leEq_lft; apply inv_resp_leEq; apply div_resp_leEq;
[ apply pos_two | apply plus_resp_leEq_lft; apply inv_resp_leEq; apply lft_leEq_Max ]).
Qed.
Lemma compact_in_interval_y_rht : forall I pI x y Hx Hy H H',
Rend (I:=compact_in_interval I pI y Hy) H [<=]
Rend (I:=compact_in_interval2 I pI x y Hx Hy) H'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; simpl in |- *; intros; try apply plus_resp_leEq;
try apply rht_leEq_Max; try apply leEq_reflexive;
(rstepl (c0[-] (c0[-]y) [/]TwoNZ); rstepr (c0[-] (c0[-]Max x y) [/]TwoNZ);
unfold cg_minus in |- *; apply plus_resp_leEq_lft; apply inv_resp_leEq; apply div_resp_leEq;
[ apply pos_two | apply plus_resp_leEq_lft; apply inv_resp_leEq; apply rht_leEq_Max ]).
Qed.
End Proper_Compact_with_One_or_Two_Points.
(**
Compact intervals are exactly compact intervals(!).
*)
Lemma interval_compact_inc : forall I (cI : compact_ I) H,
included I (compact (Lend cI) (Rend cI) H).
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0];intros; try inversion cI.
generalize c c0 cI H; clear H cI c0 c.
simpl in |- *; intros a b Hab Hab'.
intros x H.
simpl in H.
inversion_clear H; split; auto.
Qed.
Lemma compact_interval_inc : forall I (cI : compact_ I) H,
included (compact (Lend cI) (Rend cI) H) I.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI H; clear H cI c0 c.
simpl in |- *; intros a b Hab.
intros H x H0.
inversion_clear H0; split; auto.
Qed.
(**
A generalization of the previous results: if $[a,b]\subseteq J$#[a,b]⊆J#
and [J] is proper, then we can find a proper interval [[a',b']] such that
$[a,b]\subseteq[a',b']\subseteq J$#[a,b]⊆[a',b']⊆J#.
*)
Lemma compact_proper_in_interval : forall (J : interval) a b Hab,
included (compact a b Hab) J -> proper J -> {a' : IR | {b' : IR | {Hab' : _ |
included (compact a' b' (less_leEq _ _ _ Hab')) J |
included (Compact Hab) (Compact (less_leEq _ _ _ Hab'))}}}.
Proof.
intros J a b Hab H H0.
exists (Lend (compact_compact_in_interval2 J H0 a b (H _ (compact_inc_lft _ _ Hab))
(H _ (compact_inc_rht _ _ Hab)))).
exists (Rend (compact_compact_in_interval2 J H0 a b (H _ (compact_inc_lft _ _ Hab))
(H _ (compact_inc_rht _ _ Hab)))).
exists (proper_compact_in_interval2' _ _ _ _ _ _
(compact_compact_in_interval2 J H0 a b (H _ (compact_inc_lft _ _ Hab))
(H _ (compact_inc_rht _ _ Hab)))).
eapply included_trans.
apply compact_interval_inc.
apply included_compact_in_interval2.
apply included_compact.
apply iprop_compact_in_interval2x'.
apply iprop_compact_in_interval2y'.
Qed.
End Compact_Constructions.
Section Functions.
(**
** Properties of Functions in Intervals
We now define notions of continuity, differentiability and so on on
arbitrary intervals. As expected, a function [F] has property [P] in
the (proper) interval [I] iff it has property [P] in every compact
interval included in [I]. We can formalize this in a nice way using
previously defined concepts.
%\begin{convention}% Let [n:nat] and [I:interval].
%\end{convention}%
*)
Variable n : nat.
Variable I : interval.
Definition Continuous F := included I (Dom F) and (forall a b (Hab : a [<=] b),
included (Compact Hab) I -> Continuous_I Hab F).
Definition Derivative (pI : proper I) F G := included I (Dom F) and included I (Dom G) and (forall a b Hab,
included (Compact (less_leEq _ a b Hab)) I -> Derivative_I Hab F G).
Definition Diffble (pI : proper I) F := included I (Dom F) and (forall a b Hab,
included (Compact (less_leEq _ a b Hab)) I -> Diffble_I Hab F).
Definition Derivative_n (pI : proper I) F G := included I (Dom F) and included I (Dom G) and
(forall a b Hab, included (Compact (less_leEq _ a b Hab)) I -> Derivative_I_n Hab n F G).
Definition Diffble_n (pI : proper I) F := included I (Dom F) and (forall a b Hab,
included (Compact (less_leEq _ a b Hab)) I -> Diffble_I_n Hab n F).
End Functions.
Section Reflexivity_Properties.
(**
In the case of compact intervals, this definitions collapse to the old ones.
*)
Lemma Continuous_Int :
forall (I : interval) (cI : compact_ I) H (F : PartIR),
Continuous_I (a:=Lend cI) (b:=Rend cI) H F -> Continuous I F.
Proof.
intros I cI H F H0.
cut (included I (compact (Lend cI) (Rend cI) H)).
2: apply interval_compact_inc; auto.
cut (included (compact (Lend cI) (Rend cI) H) I).
2: apply compact_interval_inc; auto.
generalize cI H H0; clear H0 H cI.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI H H0 X X0; clear X0 X H0 H cI c0 c.
simpl in |- *; intros a b Hab Hab' contF inc1 inc2.
split.
apply included_trans with (Compact Hab'); Included.
intros.
apply included_imp_contin with (Hab := Hab'); Included.
Qed.
Lemma Int_Continuous :
forall (I : interval) (cI : compact_ I) H (F : PartIR),
Continuous I F -> Continuous_I (a:=Lend cI) (b:=Rend cI) H F.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI H F X; clear X F H cI c0 c.
simpl in |- *; intros a b Hab Hab' F contF.
inversion_clear contF.
Contin.
Qed.
Lemma Derivative_Int :
forall (I : interval) (cI : compact_ I) (pI : proper I) H (F F' : PartIR),
Derivative_I (a:=Lend cI) (b:=Rend cI) H F F' -> Derivative I pI F F'.
Proof.
do 4 intro.
cut (included I (compact (Lend cI) (Rend cI) (less_leEq _ _ _ H))).
2: apply interval_compact_inc; auto.
cut (included (compact (Lend cI) (Rend cI) (less_leEq _ _ _ H)) I).
2: apply compact_interval_inc; auto.
generalize cI pI H; clear H cI pI.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI pI H X X0 F F' X1; clear X1 F' F X0 X H pI cI c0 c.
simpl in |- *; intros a b Hab Hnonv Hab' inc1 inc2 F F' derF.
split.
apply included_trans with (Compact (less_leEq _ _ _ Hab')); Included.
split.
apply included_trans with (Compact (less_leEq _ _ _ Hab')); Included.
intros c d Hcd' Hinc.
apply included_imp_deriv with (Hab := Hab'); Included.
Qed.
Lemma Int_Derivative :
forall (I : interval) (cI : compact_ I) (pI : proper I) H (F F' : PartIR),
Derivative I pI F F' -> Derivative_I (a:=Lend cI) (b:=Rend cI) H F F'.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI pI H F F' X; clear X F' F H pI cI c0 c.
simpl in |- *; intros a b Hab Hnonv Hab' F F' derF.
elim derF; intros H H0.
elim H0; intros H1 H2.
Included.
Qed.
Lemma Diffble_Int :
forall (I : interval) (cI : compact_ I) (pI : proper I) H (F : PartIR),
Diffble_I (a:=Lend cI) (b:=Rend cI) H F -> Diffble I pI F.
Proof.
do 4 intro.
cut (included I (compact (Lend cI) (Rend cI) (less_leEq _ _ _ H))).
2: apply interval_compact_inc; auto.
cut (included (compact (Lend cI) (Rend cI) (less_leEq _ _ _ H)) I).
2: apply compact_interval_inc; auto.
generalize cI pI H; clear H pI cI.
destruct I as [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI pI H X X0 F X1; clear X1 F X0 X H pI cI c0 c.
simpl in |- *; intros a b Hab Hnonv Hab' inc1 inc2 F diffF.
red in |- *; simpl in |- *.
split.
apply included_trans with (Compact (less_leEq _ _ _ Hab')); Included.
intros c d Hcd' Hinc.
apply included_imp_diffble with (Hab := Hab'); auto.
Qed.
Lemma Int_Diffble :
forall (I : interval) (cI : compact_ I) (pI : proper I) H (F : PartIR),
Diffble I pI F -> Diffble_I (a:=Lend cI) (b:=Rend cI) H F.
Proof.
intros [| c| c| c| c| c c0| c c0| c c0| c c0]; intros; try inversion cI.
generalize c c0 cI pI H F X; clear X F H pI cI c0 c.
simpl in |- *; intros a b Hab Hnonv Hab' F diffF.
inversion_clear diffF.
Included.
Qed.
End Reflexivity_Properties.
Section Lemmas.
(**
Interestingly, inclusion and equality in an interval are also characterizable in a similar way:
*)
Lemma included_imp_inc : forall (J : interval) P,
(forall a b Hab, included (compact a b Hab) J -> included (compact a b Hab) P) -> included J P.
Proof.
intros J P H x H0.
apply (H _ _ (leEq_reflexive _ _) (compact_single_iprop J x H0)).
apply compact_inc_lft.
Qed.
Lemma included_Feq'' : forall I F G, proper I -> (forall a b Hab (Hab':=(less_leEq _ a b Hab)),
included (Compact Hab') I -> Feq (Compact Hab') F G) -> Feq I F G.
Proof.
intros I F G H H0.
apply eq_imp_Feq.
intros x H1.
elim (compact_proper_in_interval I x x (leEq_reflexive _ x)); Included.
2: exact (compact_single_iprop I x H1).
intros a Ha.
elim Ha; clear Ha.
intros b Hb.
elim Hb; clear Hb.
intros Hab H2 H3.
elim (H0 _ _ _ H2); intros.
apply a0; apply H3; apply compact_single_prop.
intros x H1.
elim (compact_proper_in_interval I x x (leEq_reflexive _ x)); Included.
2: exact (compact_single_iprop I x H1).
intros a Ha.
elim Ha; clear Ha.
intros b Hb.
elim Hb; clear Hb.
intros Hab H2 H3.
elim (H0 _ _ _ H2); intros.
inversion_clear b0.
apply X; apply H3; apply compact_single_prop.
intros x H1 Hx Hx'.
elim (compact_proper_in_interval I x x (leEq_reflexive _ x)); Included.
2: exact (compact_single_iprop I x H1).
intros a Ha.
elim Ha; clear Ha.
intros b Hb.
elim Hb; clear Hb.
intros Hab H2 H3.
elim (H0 _ _ _ H2); intros.
inversion_clear b0.
apply H4; apply H3; apply compact_single_prop.
Qed.
Lemma included_Feq' : forall (I : interval) F G,
(forall a b Hab, included (compact a b Hab) I -> Feq (Compact Hab) F G) -> Feq I F G.
Proof.
intros I F G H.
apply eq_imp_Feq.
intros x H0.
elim (H x x (leEq_reflexive _ x) (compact_single_iprop I x H0)); intros.
apply a; apply compact_single_prop.
intros x H0.
elim (H x x (leEq_reflexive _ x) (compact_single_iprop I x H0)); intros.
inversion_clear b.
apply X; apply compact_single_prop.
intros x H0 Hx Hx'.
elim (H x x (leEq_reflexive _ x) (compact_single_iprop I x H0)); intros.
inversion_clear b.
apply H1; apply compact_single_prop.
Qed.
End Lemmas.
Hint Resolve included_interval included_interval' included3_interval
compact_single_inc compact_single_iprop included_compact_in_interval
iprop_compact_in_interval_inc1 iprop_compact_in_interval_inc2
included_compact_in_interval2 iprop_compact_in_interval2_inc1
iprop_compact_in_interval2_inc2 interval_compact_inc compact_interval_inc
iprop_wd: included.
|
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This tests that parameters can be used in concatenations if
* the expression it represents has definite width. This test
* is based on PR#282.
*/
module t;
parameter
SET = 1'b1,
CLR = 1'b0,
S1 = 2'd1,
HINC = 3'd4;
//bit signif 12:11, 10 , 9 , 8 , 7, 6 , 5 , 4 , 3 ,2:0
parameter
x = {S1,CLR,CLR,CLR,CLR,SET,SET,CLR,CLR,HINC };
initial begin
$display("x=%b, $sizeof(x)=%d", x, $sizeof(x));
if (x !== 13'b0100001100100) begin
$display("FAILED -- x is %b", x);
$finish;
end
if ($sizeof(x) != 13) begin
$display("FAILED -- x is %d'b%b", $sizeof(x), x);
$finish;
end
$display("PASSED");
end
endmodule
|
module cov_miss_fifo
import bsg_cache_non_blocking_pkg::*;
(
input clk_i
, input reset_i
, input v_i
, input ready_o
, input v_o
, input yumi_i
, input bsg_cache_non_blocking_miss_fifo_op_e yumi_op_i
, input scan_not_dq_i
, input read_write_same_addr
, input v_r
, input empty
, input rptr_valid
, input enque
, input rollback_i
);
covergroup cg_output_taken @ (negedge clk_i iff v_r & yumi_i & ~rollback_i);
coverpoint yumi_op_i;
coverpoint read_write_same_addr;
coverpoint enque;
cross yumi_op_i, read_write_same_addr, enque;
endgroup
covergroup cg_input_output @ (negedge clk_i);
coverpoint v_i;
coverpoint ready_o;
coverpoint v_o;
coverpoint yumi_i;
cross v_i, ready_o, v_o, yumi_i {
ignore_bins n_v_o =
binsof(v_o) intersect {1'b0} &&
binsof(yumi_i) intersect {1'b1};
}
endgroup
covergroup cg_output_not_valid @ (negedge clk_i iff ~rollback_i & ~v_r);
coverpoint empty;
coverpoint scan_not_dq_i;
coverpoint rptr_valid;
coverpoint enque;
cross empty, scan_not_dq_i, rptr_valid, enque {
ignore_bins ig0 =
binsof(empty) intersect {1'b1} &&
binsof(scan_not_dq_i) intersect {1'b0} &&
binsof(rptr_valid) intersect {1'b1};
ignore_bins ig1 =
binsof(empty) intersect {1'b1} &&
binsof(scan_not_dq_i) intersect {1'b1} &&
binsof(enque) intersect {1'b1};
}
endgroup
initial begin
cg_output_taken ot = new;
cg_input_output io = new;
cg_output_not_valid onv = new;
end
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Verilog implementation of MBUS
*
* This block is the new bus controller, maintaining the same interface
* as the previous I2C controller. However, the current implementation of
* MBUS makes certain assumptions about the transmissions:
*
* 1. The transmission each round is always 32-bits, i.e. TX_DATA is 32-bit
* wide. This could be changed in the definitions file include/mbus_def.v
*
* 2. Transmissions only use short (8-bit) addresses.
*
* In addition, MBUS adds new features:
*
* 1. The additional TX_PRIORITY input. This input sets the transmission
* priority. If the TX_PRIORITY input has been asserted, it gives additional
* flexibility for the lower layer to win bus arbitration.
*
* 2. TX_PEND, RX_PEND. These inputs indicate more data coming after first
* transmission, i.e. if TX_REQ and TX_PEND are asserted at the same time,
* when the MBUS controller latches the inputs the BUS controller knows more
* data to the same destination will follow. If the next TX_REQ does not assert
* in time, the bus controller experiences a TX_FAIL (tx buffer underflow).
* Similarly for RX_PEND, if RX_REQ is asserted the layer controller must also
* monitorthe RX_PEND signal, which indicates more data for the same message
* follows.
*
* 3. The broadcast message. Every layer in MBUS will receive and acknowledge
* broadcast messages. The destination address of broadcast message is 0x00.
*
* To create a simple node that wires up to an old layer controller that
* generates data in 32-bit segments:
*
* 1. connect all interfaces,
* 2. connect TX_PEND to 0, every transmit is 32-bits wide
* 3. float RX_PEND, old layer controller doesn't support this
* 4. connect PRIORITU to 0, every transmission is a regular transmission
* 5. set corresponding address and address mask by parameter, the address
* mask indicates which bits are comparing to:
* i.e. ADDRESS_MASK = 8'hff, all 8-bits of address must match.
* i.e. ADDRESS_MASK = 8'hf0, compare only upper 4-bit of address (from MSB)
*
*
* Last modified date: 09/05 '13
* Last modified by: Yoonmyung Lee <[email protected]>
*
* Update log:
* 9/5 '13
* Change port names:
* RELEASE_RST_FROM_SLEEP_CTRL -> MBC_RESET
* POWER_ON_TO_LAYER_CTRL -> LRC_SLEEP
* RELEASE_CLK_TO_LAYER_CTRL -> LRC_CLKENB
* RELEASE_ISO_TO_LAYER_CTRL -> LRC_ISOLATE
* RELEASE_RST_TO_LAYER_CTRL -> LRC_RESET
* 5/9 '13
* Change tx_broadcast_latched from TX_ADDR to ADDR
* 5/6 '13
* Rename PRIORITY -> TX_PRIORITY
* 5/1 '13
* Add CLR_BUSY Port
* 4/28 '13
* fixed streaming broadcast RX_REQ asserts in between
* 4/24 '13
* change RX_REQ, RX_FAIL and RX_PEND by asynchronize reset from RX_ACK
* 4/16 '13
* fixed reset state for control node, since control node has different sleep
* controller, it resets bus controller before clk chain ticks. Thus, it
* should go to BUS_ILDE state for control node
* 4/15 '13
* remove BUS_PWR_OVERRIDE port
* 4/14 '13
* Add power related signals, these signals are only for simulation, in real
* setting, the isolation block will assert these signals to layer controller
* Add a BUS_PWR_OVERRIDE port, this signal indicates ctrl_wrapper to switch
* the mux
* 4/09 '13
* changed to 32-bit long and short address scheme,
* add external int,
* 3/16 '13
* Add power gated signals, move reset state to RX_ADDR
* 3/6 '13
* switch clock mux to posedge edge trigger, clock holds at high if a node request
* interrupt, bypass clock once interrupt occurred
* 11/8 '13 by: Ye-Sheng Kuo
* fix POWER_GATING macro
* */
`include "include/mbus_def.v"
module mbus_node(
input CLKIN,
input RESETn,
input DIN,
output reg CLKOUT,
output reg DOUT,
input [`ADDR_WIDTH-1:0] TX_ADDR,
input [`DATA_WIDTH-1:0] TX_DATA,
input TX_PEND,
input TX_REQ,
output reg TX_ACK,
input TX_PRIORITY,
output reg [`ADDR_WIDTH-1:0] RX_ADDR,
output reg [`DATA_WIDTH-1:0] RX_DATA,
output reg RX_PEND,
output reg RX_REQ,
input RX_ACK,
output RX_BROADCAST,
output reg RX_FAIL,
output reg TX_FAIL,
output reg TX_SUCC,
input TX_RESP_ACK,
`ifdef POWER_GATING
// power gated signals from sleep controller
input MBC_RESET,
// power gated signals to layer controller
output reg LRC_SLEEP,
output reg LRC_CLKENB,
output reg LRC_RESET,
output reg LRC_ISOLATE,
// power gated signal to sleep controller
output reg SLEEP_REQUEST_TO_SLEEP_CTRL,
// External interrupt
input EXTERNAL_INT,
output reg CLR_EXT_INT,
output reg CLR_BUSY,
`endif
// interface with local register files (RF)
input [`DYNA_WIDTH-1:0] ASSIGNED_ADDR_IN,
output [`DYNA_WIDTH-1:0] ASSIGNED_ADDR_OUT,
input ASSIGNED_ADDR_VALID,
output reg ASSIGNED_ADDR_WRITE,
output reg ASSIGNED_ADDR_INVALIDn
);
`include "include/mbus_func.v"
parameter ADDRESS = 20'habcde;
parameter ADDRESS_MASK = {(`PRFIX_WIDTH){1'b1}};
parameter ADDRESS_MASK_SHORT = {`DYNA_WIDTH{1'b1}};
// Node mode
parameter MODE_TX_NON_PRIO = 2'd0;
parameter MODE_TX = 2'd1;
parameter MODE_RX = 2'd2;
parameter MODE_FWD = 2'd3;
// BUS state
parameter BUS_IDLE = 0;
parameter BUS_ARBITRATE = 1;
parameter BUS_PRIO = 2;
parameter BUS_ADDR = 3;
parameter BUS_DATA_RX_ADDI = 4;
parameter BUS_DATA = 5;
parameter BUS_DATA_RX_CHECK = 6;
parameter BUS_REQ_INTERRUPT = 7;
parameter BUS_CONTROL0 = 8;
parameter BUS_CONTROL1 = 9;
parameter BUS_BACK_TO_IDLE = 10;
parameter NUM_OF_BUS_STATE = 11;
// Address enumeration response type
parameter ADDR_ENUM_RESPOND_T1 = 2'b00;
parameter ADDR_ENUM_RESPOND_T2 = 2'b10;
parameter ADDR_ENUM_RESPOND_NONE = 2'b11;
// TX broadcast data length
parameter LENGTH_1BYTE = 2'b00;
parameter LENGTH_2BYTE = 2'b01;
parameter LENGTH_3BYTE = 2'b10;
parameter LENGTH_4BYTE = 2'b11;
parameter RX_ABOVE_TX = 1'b1;
parameter RX_BELOW_TX = 1'b0;
// override this parameter to "1'b1" if the node is master
parameter MASTER_NODE = 1'b0;
// override this parameter to "1'b1" if the layer is CPU
parameter CPU_LAYER = 1'b0;
wire [1:0] CONTROL_BITS = `CONTROL_SEQ; // EOM?, ~ACK?
// general registers
reg [1:0] mode, next_mode, mode_neg, mode_temp;
reg [log2(NUM_OF_BUS_STATE-1)-1:0] bus_state, next_bus_state, bus_state_neg;
reg [log2(`DATA_WIDTH-1)-1:0] bit_position, next_bit_position;
reg req_interrupt, next_req_interrupt;
reg out_reg_pos, next_out_reg_pos, out_reg_neg;
`ifdef POWER_GATING
reg next_clr_busy;
`endif
// tx registers
reg [`ADDR_WIDTH-1:0] ADDR, next_addr;
reg [`DATA_WIDTH-1:0] DATA, next_data;
reg tx_pend, next_tx_pend;
reg tx_underflow, next_tx_underflow;
reg ctrl_bit_buf, next_ctrl_bit_buf;
// rx registers
reg [`ADDR_WIDTH-1:0] next_rx_addr;
reg [`DATA_WIDTH-1:0] next_rx_data;
reg [`DATA_WIDTH+1:0] rx_data_buf, next_rx_data_buf;
reg next_rx_fail;
// address enumation registers
reg [1:0] enum_addr_resp, next_enum_addr_resp;
reg next_assigned_addr_write;
reg next_assigned_addr_invalidn;
// interrupt register
reg BUS_INT_RSTn;
wire BUS_INT;
// interface registers
reg next_tx_ack;
reg next_tx_fail;
reg next_tx_success;
reg next_rx_req;
reg next_rx_pend;
wire addr_bit_extract = ((ADDR & (1'b1<<bit_position))==0)? 1'b0 : 1'b1;
wire data_bit_extract = ((DATA & (1'b1<<bit_position))==0)? 1'b0 : 1'b1;
reg [1:0] addr_match_temp;
wire address_match = (addr_match_temp[1] | addr_match_temp[0]);
// Broadcast processing
reg [`BROADCAST_CMD_WIDTH -1:0] rx_broadcast_command;
wire rx_long_addr_en = (RX_ADDR[`ADDR_WIDTH-1:`ADDR_WIDTH-4]==4'hf)? 1'b1 : 1'b0;
wire tx_long_addr_en = (TX_ADDR[`ADDR_WIDTH-1:`ADDR_WIDTH-4]==4'hf)? 1'b1 : 1'b0;
wire tx_long_addr_en_latched = (ADDR[`ADDR_WIDTH-1:`ADDR_WIDTH-4]==4'hf)? 1'b1 : 1'b0;
reg tx_broadcast_latched;
reg [1:0] tx_dat_length, rx_dat_length;
reg rx_position, rx_dat_length_valid;
reg wakeup_req;
wire [`DATA_WIDTH-1:0] broadcast_addr = `BROADCAST_ADDR;
wire [`DATA_WIDTH-1:0] rx_data_buf_proc = (rx_dat_length_valid)? (rx_position==RX_BELOW_TX)? rx_data_buf[`DATA_WIDTH-1:0] : rx_data_buf[`DATA_WIDTH+1:2] : {`DATA_WIDTH{1'b0}};
// Power gating related signals
`ifdef POWER_GATING
wire RESETn_local = (RESETn & (~MBC_RESET));
`else
wire RESETn_local = RESETn;
`endif
`ifdef POWER_GATING
reg [1:0] powerup_seq_fsm;
reg shutdown, next_shutdown;
reg ext_int;
`endif
wire [15:0] layer_slot = (1'b1<<ASSIGNED_ADDR_IN);
// Assignments
assign RX_BROADCAST = addr_match_temp[0];
assign ASSIGNED_ADDR_OUT = DATA[`DYNA_WIDTH-1:0];
// Node priority
// Used only when the BUS_STATE == BUS_PRIO, determine the node should be RX or TX
always @ *
begin
mode_temp = MODE_RX;
if (mode==MODE_TX_NON_PRIO)
begin
// Other node request priority,
if (DIN & (~TX_PRIORITY))
mode_temp = MODE_RX;
else
mode_temp = MODE_TX;
end
else
begin
// the node won first trial doesn't request priority
if (TX_REQ & TX_PRIORITY & (~DIN))
mode_temp = MODE_TX;
else
mode_temp = MODE_RX;
end
end
// End of node priority
// TX Broadcast
// For some boradcast message, TX node should take apporiate action, ex: all node sleep
// determined by ADDR flops, not TX_ADDR
always @ *
begin
tx_broadcast_latched = 0;
if (tx_long_addr_en_latched)
begin
if (ADDR[`DATA_WIDTH-1:`FUNC_WIDTH]==broadcast_addr[`DATA_WIDTH-1:`FUNC_WIDTH])
tx_broadcast_latched = 1;
end
else
begin
if (ADDR[`SHORT_ADDR_WIDTH-1:`FUNC_WIDTH]==broadcast_addr[`SHORT_ADDR_WIDTH-1:`FUNC_WIDTH])
tx_broadcast_latched = 1;
end
end
// End of TX broadcast
// Wake up control
// What type of message should wake up the layer controller (LC)
always @ *
begin
wakeup_req = 0;
// normal messages
if (~RX_BROADCAST)
wakeup_req = address_match;
else
begin
// master node should wake up for every broadcast message
if (MASTER_NODE==1'b1)
wakeup_req = address_match;
// which channels should wake up
case (RX_ADDR[`FUNC_WIDTH-1:0])
`CHANNEL_POWER:
begin
case (rx_data_buf[`BROADCAST_CMD_WIDTH-1:0])
`CMD_CHANNEL_POWER_ALL_WAKE: begin wakeup_req = 1; end
endcase
end
default: begin end
endcase
end
end
// End of Wake up control
// Address compare
// This block determine the incoming message has match the address or not
always @ *
begin
addr_match_temp = 2'b00;
if (rx_long_addr_en)
begin
if (RX_ADDR[`DATA_WIDTH-1:`FUNC_WIDTH]==broadcast_addr[`DATA_WIDTH-1:`FUNC_WIDTH])
addr_match_temp[0] = 1;
if (((RX_ADDR[`DATA_WIDTH-`RSVD_WIDTH-1:`FUNC_WIDTH] ^ ADDRESS) & ADDRESS_MASK)==0)
addr_match_temp[1] = 1;
end
// short address assigned
else
begin
if (RX_ADDR[`SHORT_ADDR_WIDTH-1:`FUNC_WIDTH]==broadcast_addr[`SHORT_ADDR_WIDTH-1:`FUNC_WIDTH])
addr_match_temp[0] = 1;
if (ASSIGNED_ADDR_VALID)
begin
if (((RX_ADDR[`SHORT_ADDR_WIDTH-1:`FUNC_WIDTH] ^ ASSIGNED_ADDR_IN) & ADDRESS_MASK_SHORT)==0)
addr_match_temp[1] = 1;
end
end
end
// End of address compare
// TX broadcast command length
// This only take care the broadcast command issued from layer controller
// CANNOT use this in self generate enumerate response
always @ *
begin
tx_dat_length = LENGTH_4BYTE;
if (tx_broadcast_latched)
begin
case (ADDR[`FUNC_WIDTH-1:0])
`CHANNEL_ENUM:
begin
case (DATA[`DATA_WIDTH-1:`DATA_WIDTH-`BROADCAST_CMD_WIDTH])
`CMD_CHANNEL_ENUM_QUERRY: begin tx_dat_length = LENGTH_1BYTE; end
`CMD_CHANNEL_ENUM_RESPONSE: begin tx_dat_length = LENGTH_4BYTE; end
`CMD_CHANNEL_ENUM_ENUMERATE: begin tx_dat_length = LENGTH_1BYTE; end
`CMD_CHANNEL_ENUM_INVALIDATE: begin tx_dat_length = LENGTH_1BYTE; end
endcase
end
`CHANNEL_POWER:
begin
case (DATA[`DATA_WIDTH-1:`DATA_WIDTH-`BROADCAST_CMD_WIDTH])
`CMD_CHANNEL_POWER_ALL_SLEEP: begin tx_dat_length = LENGTH_1BYTE; end
`CMD_CHANNEL_POWER_ALL_WAKE: begin tx_dat_length = LENGTH_1BYTE; end
`CMD_CHANNEL_POWER_SEL_SLEEP: begin tx_dat_length = LENGTH_3BYTE; end
`CMD_CHANNEL_POWER_SEL_SLEEP_FULL: begin tx_dat_length = LENGTH_4BYTE; end
`CMD_CHANNEL_POWER_SEL_WAKE: begin tx_dat_length = LENGTH_3BYTE; end
endcase
end
endcase
end
end
// This block used to determine the received data length.
// only broadcast can be any byte aligned
// otherwise, regular message has to be word aligned
always @ *
begin
rx_dat_length = LENGTH_4BYTE;
rx_dat_length_valid = 0;
rx_position = RX_ABOVE_TX;
case (bit_position)
1: begin rx_dat_length = LENGTH_4BYTE; rx_dat_length_valid = 1; rx_position = RX_BELOW_TX; end
(`DATA_WIDTH-1'b1): begin rx_dat_length = LENGTH_4BYTE; rx_dat_length_valid = 1; rx_position = RX_ABOVE_TX; end
9: begin rx_dat_length = LENGTH_3BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_BELOW_TX; end
7: begin rx_dat_length = LENGTH_3BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_ABOVE_TX; end
17: begin rx_dat_length = LENGTH_2BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_BELOW_TX; end
15: begin rx_dat_length = LENGTH_2BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_ABOVE_TX; end
25: begin rx_dat_length = LENGTH_1BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_BELOW_TX; end
23: begin rx_dat_length = LENGTH_1BYTE; if (RX_BROADCAST) rx_dat_length_valid = 1; rx_position = RX_ABOVE_TX; end
endcase
end
always @ *
begin
rx_broadcast_command = rx_data_buf_proc[`DATA_WIDTH-1:`DATA_WIDTH-`BROADCAST_CMD_WIDTH];
case (rx_dat_length)
LENGTH_4BYTE: begin rx_broadcast_command = rx_data_buf_proc[`DATA_WIDTH-1:`DATA_WIDTH-`BROADCAST_CMD_WIDTH]; end
LENGTH_3BYTE: begin rx_broadcast_command = rx_data_buf_proc[`DATA_WIDTH-9:`DATA_WIDTH-`BROADCAST_CMD_WIDTH-8]; end
LENGTH_2BYTE: begin rx_broadcast_command = rx_data_buf_proc[`DATA_WIDTH-17:`DATA_WIDTH-`BROADCAST_CMD_WIDTH-16]; end
LENGTH_1BYTE: begin rx_broadcast_command = rx_data_buf_proc[`DATA_WIDTH-25:`DATA_WIDTH-`BROADCAST_CMD_WIDTH-24]; end
endcase
end
always @ (posedge CLKIN or negedge RESETn_local)
begin
if (~RESETn_local)
begin
`ifdef POWER_GATING
if (MASTER_NODE==1'b1)
bus_state <= BUS_IDLE;
else
bus_state <= BUS_PRIO;
`else
bus_state <= BUS_IDLE;
`endif
BUS_INT_RSTn <= 1;
end
else
begin
if (BUS_INT)
begin
bus_state <= BUS_CONTROL0;
BUS_INT_RSTn <= 0;
end
else
begin
bus_state <= next_bus_state;
BUS_INT_RSTn <= 1;
end
end
end
wire TX_RESP_RSTn = RESETn_local & (~TX_RESP_ACK);
always @ (posedge CLKIN or negedge TX_RESP_RSTn)
begin
if (~TX_RESP_RSTn)
begin
TX_FAIL <= 0;
TX_SUCC <= 0;
end
else
begin
TX_FAIL <= next_tx_fail;
TX_SUCC <= next_tx_success;
end
end
wire RX_ACK_RSTn = RESETn_local & (~RX_ACK);
always @ (posedge CLKIN or negedge RX_ACK_RSTn)
begin
if (~RX_ACK_RSTn)
begin
RX_REQ <= 0;
RX_PEND <= 0;
RX_FAIL <= 0;
end
else if (~BUS_INT)
begin
RX_REQ <= next_rx_req;
RX_PEND <= next_rx_pend;
RX_FAIL <= next_rx_fail;
end
end
always @ (posedge CLKIN or negedge RESETn_local)
begin
if (~RESETn_local)
begin
// general registers
mode <= MODE_RX;
bit_position <= `ADDR_WIDTH - 1'b1;
req_interrupt <= 0;
out_reg_pos <= 0;
`ifdef POWER_GATING
CLR_BUSY <= 0;
`endif
// Transmitter registers
ADDR <= 0;
DATA <= 0;
tx_pend <= 0;
tx_underflow <= 0;
ctrl_bit_buf <= 0;
// Receiver register
RX_ADDR <= 0;
RX_DATA <= 0;
rx_data_buf <= 0;
// Interface registers
TX_ACK <= 0;
`ifdef POWER_GATING
// power gated related signal
shutdown <= 0;
`endif
// address enumeration
enum_addr_resp <= ADDR_ENUM_RESPOND_NONE;
// address enumeration interface
ASSIGNED_ADDR_WRITE <= 0;
ASSIGNED_ADDR_INVALIDn <= 1;
end
else
begin
// general registers
mode <= next_mode;
if (~BUS_INT)
begin
bit_position <= next_bit_position;
rx_data_buf <= next_rx_data_buf;
// Receiver register
RX_ADDR <= next_rx_addr;
RX_DATA <= next_rx_data;
end
req_interrupt <= next_req_interrupt;
out_reg_pos <= next_out_reg_pos;
`ifdef POWER_GATING
CLR_BUSY <= next_clr_busy;
`endif
// Transmitter registers
ADDR <= next_addr;
DATA <= next_data;
tx_pend <= next_tx_pend;
tx_underflow <= next_tx_underflow;
ctrl_bit_buf <= next_ctrl_bit_buf;
// Interface registers
TX_ACK <= next_tx_ack;
`ifdef POWER_GATING
// power gated related signal
shutdown <= next_shutdown;
`endif
// address enumeration
enum_addr_resp <= next_enum_addr_resp;
// address enumeration interface
ASSIGNED_ADDR_WRITE <= next_assigned_addr_write;
ASSIGNED_ADDR_INVALIDn <= next_assigned_addr_invalidn;
end
end
always @ *
begin
// general registers
next_mode = mode;
next_bus_state = bus_state;
next_bit_position = bit_position;
next_req_interrupt = req_interrupt;
next_out_reg_pos = out_reg_pos;
`ifdef POWER_GATING
next_clr_busy = CLR_BUSY;
`endif
// Transmitter registers
next_addr = ADDR;
next_data = DATA;
next_tx_pend = tx_pend;
next_tx_underflow = tx_underflow;
next_ctrl_bit_buf = ctrl_bit_buf;
// Receiver register
next_rx_addr = RX_ADDR;
next_rx_data = RX_DATA;
next_rx_fail = RX_FAIL;
next_rx_data_buf = rx_data_buf;
// Interface registers
next_rx_req = RX_REQ;
next_rx_pend = RX_PEND;
next_tx_fail = TX_FAIL;
next_tx_success = TX_SUCC;
next_tx_ack = TX_ACK;
// Address enumeration
next_enum_addr_resp = enum_addr_resp;
// Address enumeratio interface
next_assigned_addr_write = 0;
next_assigned_addr_invalidn = 1;
// Asynchronous interface
if (TX_ACK & (~TX_REQ))
next_tx_ack = 0;
`ifdef POWER_GATING
// power gating signals
next_shutdown = shutdown;
`endif
case (bus_state)
BUS_IDLE:
begin
if (DIN^DOUT)
next_mode = MODE_TX_NON_PRIO;
else
next_mode = MODE_RX;
// general registers
next_bus_state = BUS_ARBITRATE;
next_bit_position = `ADDR_WIDTH - 1'b1;
end
BUS_ARBITRATE:
begin
next_bus_state = BUS_PRIO;
end
BUS_PRIO:
begin
`ifdef POWER_GATING
next_clr_busy = 0;
`endif
next_mode = mode_temp;
next_bus_state = BUS_ADDR;
// no matter this node wins the arbitration or not, must clear
// type T1
if (enum_addr_resp== ADDR_ENUM_RESPOND_T1)
next_enum_addr_resp = ADDR_ENUM_RESPOND_NONE;
if (mode_temp==MODE_TX)
begin
case (enum_addr_resp)
// respond to enumeration
ADDR_ENUM_RESPOND_T1:
begin
next_bit_position = `SHORT_ADDR_WIDTH - 1'b1;
next_assigned_addr_write = 1;
end
// respond to query
ADDR_ENUM_RESPOND_T2:
begin
next_bit_position = `SHORT_ADDR_WIDTH - 1'b1;
next_enum_addr_resp = ADDR_ENUM_RESPOND_NONE;
end
// TX initiated from layer controller
default:
begin
next_addr = TX_ADDR;
next_data = TX_DATA;
next_tx_ack = 1;
next_tx_pend = TX_PEND;
if (tx_long_addr_en)
next_bit_position = `ADDR_WIDTH - 1'b1;
else
next_bit_position = `SHORT_ADDR_WIDTH - 1'b1;
end
endcase
end
else
// RX mode
begin
next_rx_data_buf = 0;
next_rx_addr = 0;
end
end
BUS_ADDR:
begin
case (mode)
MODE_TX:
begin
if (bit_position)
next_bit_position = bit_position - 1'b1;
else
begin
next_bit_position = `DATA_WIDTH - 1'b1;
next_bus_state = BUS_DATA;
end
end
MODE_RX:
begin
// short address
if ((bit_position==`ADDR_WIDTH-3'd5)&&(RX_ADDR[3:0]!=4'hf))
next_bit_position = `SHORT_ADDR_WIDTH - 3'd6;
else
begin
if (bit_position)
next_bit_position = bit_position - 1'b1;
else
begin
next_bit_position = `DATA_WIDTH - 1'b1;
next_bus_state = BUS_DATA_RX_ADDI;
end
end
next_rx_addr = {RX_ADDR[`ADDR_WIDTH-2:0], DIN};
end
endcase
end
BUS_DATA_RX_ADDI:
begin
next_rx_data_buf = {rx_data_buf[`DATA_WIDTH:0], DIN};
next_bit_position = bit_position - 1'b1;
`ifdef POWER_GATING
next_shutdown = 0;
`endif
if (bit_position==(`DATA_WIDTH-2'b10))
begin
next_bus_state = BUS_DATA;
next_bit_position = `DATA_WIDTH - 1'b1;
end
if (address_match==0)
next_mode = MODE_FWD;
end
BUS_DATA:
begin
case (mode)
MODE_TX:
begin
// support variable tx length for broadcast messages
if (((tx_dat_length==LENGTH_4BYTE)&&(bit_position>0))||((tx_dat_length==LENGTH_3BYTE)&&(bit_position>8))||((tx_dat_length==LENGTH_2BYTE)&&(bit_position>16))||((tx_dat_length==LENGTH_1BYTE)&&(bit_position>24)))
//if (bit_position)
next_bit_position = bit_position - 1'b1;
else
begin
next_bit_position = `DATA_WIDTH - 1'b1;
case ({tx_pend, TX_REQ})
// continue next word
2'b11:
begin
next_tx_pend = TX_PEND;
next_data = TX_DATA;
next_tx_ack = 1;
end
// underflow
2'b10:
begin
next_bus_state = BUS_REQ_INTERRUPT;
next_tx_underflow = 1;
next_req_interrupt = 1;
next_tx_fail = 1;
end
default:
begin
next_bus_state = BUS_REQ_INTERRUPT;
next_req_interrupt = 1;
end
endcase
end
end
MODE_RX:
begin
next_rx_data_buf = {rx_data_buf[`DATA_WIDTH:0], DIN};
if (bit_position)
next_bit_position = bit_position - 1'b1;
else
begin
if (RX_REQ)
begin
// RX overflow
next_bus_state = BUS_REQ_INTERRUPT;
next_req_interrupt = 1;
next_rx_fail = 1;
end
else
begin
next_bus_state = BUS_DATA_RX_CHECK;
next_bit_position = `DATA_WIDTH - 1'b1;
end
end
end
endcase
end
BUS_DATA_RX_CHECK:
begin
next_bit_position = bit_position - 1'b1;
next_rx_data_buf = {rx_data_buf[`DATA_WIDTH:0], DIN};
if (RX_BROADCAST)
begin
if (CPU_LAYER==1'b1)
next_rx_req = 1;
else
next_rx_req = 0;
end
else
next_rx_req = 1;
next_rx_pend = 1;
next_rx_data = rx_data_buf[`DATA_WIDTH+1:2];
next_bus_state = BUS_DATA;
end
BUS_REQ_INTERRUPT:
begin
end
BUS_CONTROL0:
begin
next_bus_state = BUS_CONTROL1;
next_ctrl_bit_buf = DIN;
case (mode)
MODE_TX:
begin
if (req_interrupt)
begin
// Prevent wire floating
next_out_reg_pos = ~CONTROL_BITS[0];
if (tx_broadcast_latched)
begin
case (ADDR[`FUNC_WIDTH-1:0])
`CHANNEL_POWER:
begin
`ifdef POWER_GATING
case (DATA[`DATA_WIDTH-1:`DATA_WIDTH-`BROADCAST_CMD_WIDTH ])
`CMD_CHANNEL_POWER_ALL_SLEEP:
begin
next_shutdown = 1;
end
`CMD_CHANNEL_POWER_SEL_SLEEP:
begin
if ((DATA[27:12]&layer_slot)>0)
next_shutdown = 1;
end
`CMD_CHANNEL_POWER_SEL_SLEEP_FULL:
begin
if (((DATA[`PRFIX_WIDTH+3:4] ^ ADDRESS) & ADDRESS_MASK)==0)
next_shutdown = 1;
end
endcase
`endif
end
endcase
end
end
else
begin
next_tx_fail = 1;
end
end
MODE_RX:
begin
if (req_interrupt)
next_out_reg_pos = ~CONTROL_BITS[0];
else
begin
// End of Message
// correct ending state
// rx above tx = 31
// rx below tx = 1
if ((DIN==CONTROL_BITS[1])&&(rx_dat_length_valid))
begin
// rx overflow
if (RX_REQ)
begin
next_out_reg_pos = ~CONTROL_BITS[0];
next_rx_fail = 1;
end
else
// assert rx_req if not a broadcast
begin
next_rx_data = rx_data_buf_proc;
next_out_reg_pos = CONTROL_BITS[0];
if (~RX_BROADCAST)
next_rx_req = 1;
next_rx_pend = 0;
end
// broadcast message
if (RX_BROADCAST)
begin
// assert broadcast rx_req only in CPU layer
if ((CPU_LAYER==1'b1)&&(~RX_REQ))
next_rx_req = 1;
// broadcast channel
case (RX_ADDR[`FUNC_WIDTH-1:0])
`CHANNEL_ENUM:
begin
case (rx_broadcast_command)
// any node should report its full prefix and short prefix (dynamic allocated address)
// Pad "0" if the dynamic address is invalid
`CMD_CHANNEL_ENUM_QUERRY:
begin
// this node doesn't have a valid short address, active low
next_enum_addr_resp = ADDR_ENUM_RESPOND_T2;
next_addr = broadcast_addr[`SHORT_ADDR_WIDTH-1:0];
next_data = ((`CMD_CHANNEL_ENUM_RESPONSE<<(`DATA_WIDTH-`BROADCAST_CMD_WIDTH)) | (ADDRESS<<`DYNA_WIDTH) | ASSIGNED_ADDR_IN);
end
// request arbitration, set short prefix if successed
`CMD_CHANNEL_ENUM_ENUMERATE:
begin
if (~ASSIGNED_ADDR_VALID)
begin
next_enum_addr_resp = ADDR_ENUM_RESPOND_T1;
next_addr = broadcast_addr[`SHORT_ADDR_WIDTH-1:0];
next_data = ((`CMD_CHANNEL_ENUM_RESPONSE<<(`DATA_WIDTH-`BROADCAST_CMD_WIDTH)) | (ADDRESS<<`DYNA_WIDTH) | rx_data_buf_proc[`DYNA_WIDTH-1:0]);
end
end
`CMD_CHANNEL_ENUM_INVALIDATE:
begin
case (rx_data_buf_proc[`DYNA_WIDTH-1:0])
{`DYNA_WIDTH{1'b1}}: begin next_assigned_addr_invalidn = 0; end
ASSIGNED_ADDR_IN: begin next_assigned_addr_invalidn = 0; end
default: begin end
endcase
end
endcase
end
`ifdef POWER_GATING
`CHANNEL_POWER:
begin
// PWR Command
case (rx_broadcast_command)
`CMD_CHANNEL_POWER_ALL_SLEEP:
begin
next_shutdown = 1;
end
`CMD_CHANNEL_POWER_SEL_SLEEP:
begin
if ((rx_data_buf_proc[19:4]&layer_slot)>0)
next_shutdown = 1;
end
`CMD_CHANNEL_POWER_SEL_SLEEP_FULL:
begin
if (((rx_data_buf_proc[`PRFIX_WIDTH+3:4] ^ ADDRESS) & ADDRESS_MASK)==0)
next_shutdown = 1;
end
endcase
end
`endif
// shoud only be active at master
`CHANNEL_CTRL:
begin
if (MASTER_NODE==1'b1)
next_rx_req = 1;
end
endcase
end // endif rx_broadcast
end // endif valid reception
else
// invalid data length or invalid EOM
begin
next_out_reg_pos = ~CONTROL_BITS[0];
`ifdef POWER_GATING
if (~ext_int)
next_rx_fail = 1;
`else
next_rx_fail = 1;
`endif
end
end
end
endcase
end
BUS_CONTROL1:
begin
next_bus_state = BUS_BACK_TO_IDLE;
if (req_interrupt)
begin
if ((mode==MODE_TX)&&(~tx_underflow))
begin
// ACK received
if ({ctrl_bit_buf, DIN}==CONTROL_BITS)
next_tx_success = 1;
else
next_tx_fail = 1;
end
end
end
BUS_BACK_TO_IDLE:
begin
`ifdef POWER_GATING
next_clr_busy = 1;
`endif
next_bus_state = BUS_IDLE;
next_req_interrupt = 0;
next_mode = MODE_RX;
next_tx_underflow = 0;
end
endcase
end
`ifdef POWER_GATING
always @ (negedge CLKIN or negedge RESETn_local)
begin
if (~RESETn_local)
begin
powerup_seq_fsm <= 0;
LRC_SLEEP <= `IO_HOLD;
LRC_CLKENB <= `IO_HOLD;
LRC_ISOLATE <= `IO_HOLD;
LRC_RESET <= `IO_HOLD;
SLEEP_REQUEST_TO_SLEEP_CTRL <= 0;
ext_int <= 0;
CLR_EXT_INT <= 0;
end
else
begin
if (CLR_EXT_INT & (~EXTERNAL_INT))
CLR_EXT_INT <= 0;
// master node should wake up layer controller "early"
if (((bus_state==BUS_ADDR)&&(MASTER_NODE==1'b0))||((bus_state==BUS_IDLE)&&(MASTER_NODE==1'b1)))
begin
if (EXTERNAL_INT)
begin
ext_int <= 1;
powerup_seq_fsm <= 1;
LRC_SLEEP <= `IO_RELEASE;
end
else
powerup_seq_fsm <= 0;
end
if (bus_state==BUS_CONTROL1)
ext_int <= 0;
if (ext_int)
begin
case (powerup_seq_fsm)
1: begin LRC_CLKENB <= `IO_RELEASE; CLR_EXT_INT <= 1; powerup_seq_fsm <= powerup_seq_fsm + 1'b1; end
2: begin LRC_ISOLATE <= `IO_RELEASE; powerup_seq_fsm <= powerup_seq_fsm + 1'b1; end
3: begin LRC_RESET <= `IO_RELEASE; powerup_seq_fsm <= powerup_seq_fsm + 1'b1; end
0: begin end
endcase
end
else
begin
case (bus_state)
BUS_DATA:
begin
case (powerup_seq_fsm)
0:
begin
// only check the wakeup_req after received broadcast command
// FSM stays at BUS_ADDR_ADDI for 2 cycles before entering BUS_DATA
// the complete command should received after `DATA_WIDTH (32) - `BROADCAST_CMD_WIDTH(4) + 2(2 BUS_ADDR_ADDI) - 1
if ((wakeup_req)&&(bit_position==`DATA_WIDTH-`BROADCAST_CMD_WIDTH+1))
begin
LRC_SLEEP <= `IO_RELEASE;
powerup_seq_fsm <= powerup_seq_fsm + 1'b1;
end
end
1:
begin
LRC_CLKENB <= `IO_RELEASE;
powerup_seq_fsm <= powerup_seq_fsm + 1'b1;
end
2:
begin
LRC_ISOLATE <= `IO_RELEASE;
powerup_seq_fsm <= powerup_seq_fsm + 1'b1;
end
3:
begin
LRC_RESET <= `IO_RELEASE;
end
endcase
end
BUS_CONTROL1:
begin
if (shutdown)
begin
SLEEP_REQUEST_TO_SLEEP_CTRL <= 1;
LRC_ISOLATE <= `IO_HOLD;
end
end
BUS_BACK_TO_IDLE:
begin
end
endcase
end
end
end
`endif
always @ (negedge CLKIN or negedge RESETn_local)
begin
if (~RESETn_local)
begin
out_reg_neg <= 1;
`ifdef POWER_GATING
if (MASTER_NODE==1'b1)
bus_state_neg <= BUS_IDLE;
else
bus_state_neg <= BUS_PRIO;
`else
bus_state_neg <= BUS_IDLE;
`endif
mode_neg <= MODE_RX;
end
else
begin
if (req_interrupt & BUS_INT)
bus_state_neg <= BUS_CONTROL0;
else
bus_state_neg <= bus_state;
mode_neg <= mode;
case (bus_state)
BUS_ADDR:
begin
if (mode==MODE_TX)
out_reg_neg <= addr_bit_extract;
end
BUS_DATA:
begin
if (mode==MODE_TX)
out_reg_neg <= data_bit_extract;
end
BUS_CONTROL0:
begin
if (req_interrupt)
begin
if (mode==MODE_TX)
begin
if (tx_underflow)
out_reg_neg <= ~CONTROL_BITS[1];
else
out_reg_neg <= CONTROL_BITS[1];
end
else
out_reg_neg <= ~CONTROL_BITS[1];
end
end
BUS_CONTROL1:
begin
out_reg_neg <= out_reg_pos;
end
endcase
end
end
always @ *
begin
DOUT = DIN;
case (bus_state_neg)
BUS_IDLE:
begin
DOUT = ((~TX_REQ) & DIN & enum_addr_resp[0]);
end
BUS_ARBITRATE:
begin
if (mode_neg==MODE_TX_NON_PRIO)
DOUT = 0;
end
BUS_PRIO:
begin
if (mode_neg==MODE_TX_NON_PRIO)
begin
if (TX_PRIORITY)
DOUT = 1;
else
DOUT = 0;
end
else if ((mode_neg==MODE_RX)&&(TX_PRIORITY & TX_REQ))
DOUT = 1;
end
BUS_ADDR:
begin
// Drive value only if interrupt is low
if (~BUS_INT &(mode_neg==MODE_TX))
DOUT = out_reg_neg;
end
BUS_DATA:
begin
// Drive value only if interrupt is low
if (~BUS_INT &(mode_neg==MODE_TX))
DOUT = out_reg_neg;
end
BUS_CONTROL0:
begin
if (req_interrupt)
DOUT = out_reg_neg;
end
BUS_CONTROL1:
begin
if (mode_neg==MODE_RX)
DOUT = out_reg_neg;
else if (req_interrupt)
DOUT = out_reg_neg;
end
BUS_BACK_TO_IDLE:
begin
DOUT = ((~TX_REQ) & DIN & enum_addr_resp[0]);
end
endcase
end
always @ *
begin
// forward clock once interrupt occurred
CLKOUT = CLKIN;
if ((bus_state==BUS_REQ_INTERRUPT)&&(~BUS_INT))
CLKOUT = 1;
end
mbus_swapper swapper0(
// inputs
.CLK(CLKIN),
.RESETn(RESETn_local),
.DATA(DIN),
.INT_FLAG_RESETn(BUS_INT_RSTn),
//Outputs
.LAST_CLK(),
.INT_FLAG(BUS_INT));
endmodule
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 05/11/2009
Version 2.0
This logic recieves registers the byte address of the master when 'start'
is asserted. This block then barrelshifts the write data based on the byte
address to make sure that the input data (from the FIFO) is reformatted to
line up with memory properly.
The only throttling mechanism in this block is the FIFO not empty signal as
well as waitreqeust from the fabric.
Revision History:
1.0 Initial version
2.0 Removed 'bytes_to_next_boundary' and using the address to determine how
much out of alignment the master begins.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ST_to_MM_Adapter (
clk,
reset,
enable,
address,
start,
waitrequest,
stall,
write_data,
fifo_data,
fifo_empty,
fifo_readack
);
parameter DATA_WIDTH = 32;
parameter BYTEENABLE_WIDTH_LOG2 = 2;
parameter ADDRESS_WIDTH = 32;
parameter UNALIGNED_ACCESS_ENABLE = 0; // when set to 0 this block will be a pass through (save on resources when unaligned accesses are not needed)
localparam BYTES_TO_NEXT_BOUNDARY_WIDTH = BYTEENABLE_WIDTH_LOG2 + 1; // 2, 3, 4, 5, 6 for byte enable widths of 2, 4, 8, 16, 32
input clk;
input reset;
input enable; // must make sure that the adapter doesn't accept data when a transfer it doesn't know what "bytes_to_transfer" is yet
input [ADDRESS_WIDTH-1:0] address;
input start; // one cycle strobe at the start of a transfer used to determine bytes_to_transfer
input waitrequest;
input stall;
output wire [DATA_WIDTH-1:0] write_data;
input [DATA_WIDTH-1:0] fifo_data;
input fifo_empty;
output wire fifo_readack;
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-1:0] bytes_to_next_boundary;
wire [DATA_WIDTH-1:0] barrelshifter_A;
wire [DATA_WIDTH-1:0] barrelshifter_B;
reg [DATA_WIDTH-1:0] barrelshifter_B_d1;
wire [DATA_WIDTH-1:0] combined_word; // bitwise OR between barrelshifter_A and barrelshifter_B (each has zero padding so that bytelanes don't overlap)
wire [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one; // simplifies barrelshifter select logic
reg [BYTES_TO_NEXT_BOUNDARY_WIDTH-2:0] bytes_to_next_boundary_minus_one_d1;
wire [DATA_WIDTH-1:0] barrelshifter_input_A [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_A inputs
wire [DATA_WIDTH-1:0] barrelshifter_input_B [0:((DATA_WIDTH/8)-1)]; // will be used to create barrelshifter_B inputs
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
bytes_to_next_boundary_minus_one_d1 <= 0;
end
else if (start)
begin
bytes_to_next_boundary_minus_one_d1 <= bytes_to_next_boundary_minus_one;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
barrelshifter_B_d1 <= 0;
end
else
begin
if (start == 1)
begin
barrelshifter_B_d1 <= 0;
end
else if (fifo_readack == 1)
begin
barrelshifter_B_d1 <= barrelshifter_B;
end
end
end
assign bytes_to_next_boundary = (DATA_WIDTH/8) - address[BYTEENABLE_WIDTH_LOG2-1:0]; // bytes per word - unaligned byte offset = distance to next boundary
assign bytes_to_next_boundary_minus_one = bytes_to_next_boundary - 1;
assign combined_word = barrelshifter_A | barrelshifter_B_d1;
generate
genvar input_offset;
for(input_offset = 0; input_offset < (DATA_WIDTH/8); input_offset = input_offset + 1)
begin: barrel_shifter_inputs
assign barrelshifter_input_A[input_offset] = fifo_data << (8 * ((DATA_WIDTH/8)-(input_offset+1)));
assign barrelshifter_input_B[input_offset] = fifo_data >> (8 * (input_offset + 1));
end
endgenerate
assign barrelshifter_A = barrelshifter_input_A[bytes_to_next_boundary_minus_one_d1];
assign barrelshifter_B = barrelshifter_input_B[bytes_to_next_boundary_minus_one_d1];
generate
if (UNALIGNED_ACCESS_ENABLE == 1)
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1) & (start == 0);
assign write_data = combined_word;
end
else
begin
assign fifo_readack = (fifo_empty == 0) & (stall == 0) & (waitrequest == 0) & (enable == 1);
assign write_data = fifo_data;
end
endgenerate
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Two-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common two-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// two-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Double-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage 2-port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB4_S16_S16 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - fix Avant! ////
//// - xilinx rams need external tri-state logic ////
//// - add additional RAMs (VS etc) ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_tpram_32x32(
// Generic synchronous two-port RAM interface
clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a,
clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b
);
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
//
// Generic synchronous two-port RAM interface
//
input clk_a; // Clock
input rst_a; // Reset
input ce_a; // Chip enable input
input we_a; // Write enable input
input oe_a; // Output enable input
input [aw-1:0] addr_a; // address bus inputs
input [dw-1:0] di_a; // input data bus
output [dw-1:0] do_a; // output data bus
input clk_b; // Clock
input rst_b; // Reset
input ce_b; // Chip enable input
input we_b; // Write enable input
input oe_b; // Output enable input
input [aw-1:0] addr_b; // address bus inputs
input [dw-1:0] di_b; // input data bus
output [dw-1:0] do_b; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SDP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
`ifdef UNUSED
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
`else
art_hsdp_32x32 artisan_sdp(
`endif
.qa(do_a),
.clka(clk_a),
.cena(~ce_a),
.wena(~we_a),
.aa(addr_a),
.da(di_a),
.oena(~oe_a),
.qb(do_b),
.clkb(clk_b),
.cenb(~ce_b),
.wenb(~we_b),
.ab(addr_b),
.db(di_b),
.oenb(~oe_b)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_STP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
.QA(do_a),
.QB(do_b),
.ADRA(addr_a),
.DA(di_a),
.WEA(we_a),
.OEA(oe_a),
.MEA(ce_a),
.CLKA(clk_a),
.ADRB(adr_b),
.DB(di_b),
.WEB(we_b),
.OEB(oe_b),
.MEB(ce_b),
.CLKB(clk_b)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_s16_0(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(di_a[15:0]),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a[15:0]),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[15:0]),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b[15:0])
);
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_s16_1(
.CLKA(clk_a),
.RSTA(rst_a),
.ADDRA(addr_a),
.DIA(di_a[31:16]),
.ENA(ce_a),
.WEA(we_a),
.DOA(do_a[31:16]),
.CLKB(clk_b),
.RSTB(rst_b),
.ADDRB(addr_b),
.DIB(di_b[31:16]),
.ENB(ce_b),
.WEB(we_b),
.DOB(do_b[31:16])
);
`else
`ifdef OR1200_ALTERA_LPM_XXX
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
altqpram altqpram_component (
.wraddress_a (addr_a),
.inclocken_a (ce_a),
.wraddress_b (addr_b),
.wren_a (we_a),
.inclocken_b (ce_b),
.wren_b (we_b),
.inaclr_a (rst_a),
.inaclr_b (rst_b),
.inclock_a (clk_a),
.inclock_b (clk_b),
.data_a (di_a),
.data_b (di_b),
.q_a (do_a),
.q_b (do_b)
);
defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",
altqpram_component.width_write_a = dw,
altqpram_component.widthad_write_a = aw,
altqpram_component.numwords_write_a = dw,
altqpram_component.width_read_a = dw,
altqpram_component.widthad_read_a = aw,
altqpram_component.numwords_read_a = dw,
altqpram_component.width_write_b = dw,
altqpram_component.widthad_write_b = aw,
altqpram_component.numwords_write_b = dw,
altqpram_component.width_read_b = dw,
altqpram_component.widthad_read_b = aw,
altqpram_component.numwords_read_b = dw,
altqpram_component.indata_reg_a = "INCLOCK_A",
altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",
altqpram_component.outdata_reg_a = "INCLOCK_A",
altqpram_component.indata_reg_b = "INCLOCK_B",
altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",
altqpram_component.outdata_reg_b = "INCLOCK_B",
altqpram_component.indata_aclr_a = "INACLR_A",
altqpram_component.wraddress_aclr_a = "INACLR_A",
altqpram_component.wrcontrol_aclr_a = "INACLR_A",
altqpram_component.outdata_aclr_a = "INACLR_A",
altqpram_component.indata_aclr_b = "NONE",
altqpram_component.wraddress_aclr_b = "NONE",
altqpram_component.wrcontrol_aclr_b = "NONE",
altqpram_component.outdata_aclr_b = "INACLR_B",
altqpram_component.lpm_hint = "USE_ESB=ON";
//examplar attribute altqpram_component NOOPT TRUE
`else
//
// Generic two-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_a_reg; // RAM read address register
reg [aw-1:0] addr_b_reg; // RAM read address register
//
// Data output drivers
//
assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
assign do_b = (oe_b) ? mem[addr_b_reg] : {dw{1'b0}};
//
// RAM write
//
always @(posedge clk_a)
if (ce_a && we_a)
mem[addr_a] <= #1 di_a;
//
// RAM write
//
always @(posedge clk_b)
if (ce_b && we_b)
mem[addr_b] <= #1 di_b;
//
// RAM read address register
//
always @(posedge clk_a or posedge rst_a)
if (rst_a)
addr_a_reg <= #1 {aw{1'b0}};
else if (ce_a)
addr_a_reg <= #1 addr_a;
//
// RAM read address register
//
always @(posedge clk_b or posedge rst_b)
if (rst_b)
addr_b_reg <= #1 {aw{1'b0}};
else if (ce_b)
addr_b_reg <= #1 addr_b;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB4_S16_S16
`endif // !OR1200_VIRAGE_STP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SDP
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/23/2016 11:26:28 AM
// Design Name:
// Module Name: Sgf_Multiplication
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Sgf_Multiplication
#(parameter SW = 24)
//#(parameter SW = 54)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
//wire [SW-1:0] Data_A_i;
//wire [SW-1:0] Data_B_i;
//wire [2*(SW/2)-1:0] result_left_mult;
//wire [2*(SW/2+1)-1:0] result_right_mult;
wire [SW/2+1:0] result_A_adder;
//wire [SW/2+1:0] Q_result_A_adder;
wire [SW/2+1:0] result_B_adder;
//wire [SW/2+1:0] Q_result_B_adder;
//wire [2*(SW/2+2)-1:0] result_middle_mult;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
wire [2*(SW/2+2)-1:0] S_A;
wire [2*(SW/2+2)-1:0] S_B;
wire [4*(SW/2)+2:0] Result;
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 =2'b00;
assign zero2 =4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
wire [4*(SW/2)-1:0] sgf_r;
assign rightside1 = (SW/2) *1'b0;
assign rightside2 = (SW/2+1)*1'b0;
localparam half = SW/2;
//localparam level1=4;
//localparam level2=5;
////////////////////////////////////
generate
case (SW%2)
0:begin
//////////////////////////////////even//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level1)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(SW)) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
multiplier #(.W(SW/2)/*,.level(level1)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(/*result_right_mult[2*(SW/2)-1:0]*/Q_right[2*(SW/2)-1:0])
);
/*RegisterAdd #(.W(SW)) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult[2*(SW/2)-1:0]),
.Q(Q_right[2*(SW/2)-1:0])
);//*/
//Adders for middle
adder #(.W(SW/2)) A_operation (
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder[SW/2:0])
);
adder #(.W(SW/2)) B_operation (
.Data_A_i(Data_B_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder[SW/2:0])
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+1)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder[SW/2:0]),
.Q(Q_result_A_adder[SW/2:0])
);//
RegisterAdd #(.W(SW/2+1)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder[SW/2:0]),
.Q(Q_result_B_adder[SW/2:0])
);//*/
//multiplication for middle
multiplier #(.W(SW/2+1)/*,.level(level1)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder[SW/2:0]*/result_A_adder[SW/2:0]),
.Data_B_i(/*Q_result_B_adder[SW/2:0]*/result_B_adder[SW/2:0]),
.Data_S_o(/*result_middle_mult[2*(SW/2)+1:0]*/Q_middle[2*(SW/2)+1:0])
);
//segmentation registers array
/*RegisterAdd #(.W(SW+2)) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult[2*(SW/2)+1:0]),
.Q(Q_middle[2*(SW/2)+1:0])
);//*/
///Subtractors for middle
substractor #(.W(SW+2)) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A[2*(SW/2)+1:0])
);
substractor #(.W(SW+2)) Subtr_2 (
.Data_A_i(S_A[2*(SW/2)+1:0]),
.Data_B_i({zero1, /*result_right_mult//*/Q_right[2*(SW/2)-1:0]}),
.Data_S_o(S_B[2*(SW/2)+1:0])
);
//Final adder
adder #(.W(4*(SW/2))) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right[2*(SW/2)-1:0]}),
.Data_B_i({S_B[2*(SW/2)+1:0],rightside1}),
.Data_S_o(Result[4*(SW/2):0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin
//////////////////////////////////odd//////////////////////////////////
//Multiplier for left side and right side
multiplier #(.W(SW/2)/*,.level(level2)*/) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(/*result_left_mult*/Q_left)
);
/*RegisterAdd #(.W(2*(SW/2))) leftreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_left_mult),
.Q(Q_left)
);//*/
multiplier #(.W((SW/2)+1)/*,.level(level2)*/) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(/*result_right_mult*/Q_right)
);
/*RegisterAdd #(.W(2*((SW/2)+1))) rightreg( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_right_mult),
.Q(Q_right)
);//*/
//Adders for middle
adder #(.W(SW/2+1)) A_operation (
.Data_A_i({1'b0,Data_A_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_A_i[SW-SW/2-1:0]),
.Data_S_o(result_A_adder)
);
adder #(.W(SW/2+1)) B_operation (
.Data_A_i({1'b0,Data_B_i[SW-1:SW-SW/2]}),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(result_B_adder)
);
//segmentation registers for 64 bits
/*RegisterAdd #(.W(SW/2+2)) preAreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_A_adder),
.Q(Q_result_A_adder)
);//
RegisterAdd #(.W(SW/2+2)) preBreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_B_adder),
.Q(Q_result_B_adder)
);//*/
//multiplication for middle
multiplier #(.W(SW/2+2)/*,.level(level2)*/) middle (
.clk(clk),
.Data_A_i(/*Q_result_A_adder*/result_A_adder),
.Data_B_i(/*Q_result_B_adder*/result_B_adder),
.Data_S_o(/*result_middle_mult*/Q_middle)
);
//segmentation registers array
/*RegisterAdd #(.W(2*((SW/2)+2))) midreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(1'b1),
.D(result_middle_mult),
.Q(Q_middle)
);//*/
///Subtractors for middle
substractor #(.W(2*(SW/2+2))) Subtr_1 (
.Data_A_i(/*result_middle_mult//*/Q_middle),
.Data_B_i({zero2, /*result_left_mult//*/Q_left}),
.Data_S_o(S_A)
);
substractor #(.W(2*(SW/2+2))) Subtr_2 (
.Data_A_i(S_A),
.Data_B_i({zero1, /*result_right_mult//*/Q_right}),
.Data_S_o(S_B)
);
//Final adder
adder #(.W(4*(SW/2)+2)) Final(
.Data_A_i({/*result_left_mult,result_right_mult*/Q_left,Q_right}),
.Data_B_i({S_B,rightside2}),
.Data_S_o(Result[4*(SW/2)+2:0])
);
//Final Register
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_SYMBOL_V
`define SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_pwrgood_pp$PG$S (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input SLEEP ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_PWRGOOD_PP_PG_S_SYMBOL_V
|
`default_nettype none
`timescale 1ns/1ns
module tb_membusif();
wire clk, reset;
clock clock(clk, reset);
// avalon
reg a_write = 0;
reg a_read = 0;
reg [31:0] a_writedata = 0;
reg [1:0] a_address;
wire [31:0] a_readdata;
wire a_waitrequest;
// membus
wire b_rq_cyc;
wire b_rd_rq;
wire b_wr_rq;
wire [21:35] b_ma;
wire [18:21] b_sel;
wire b_fmc_select;
wire [0:35] b_mb_write;
wire b_wr_rs;
wire [0:35] b_mb_read = b_mb_read_0 | b_mb_read_1;
wire b_addr_ack = b_addr_ack_0 | b_addr_ack_1;
wire b_rd_rs = b_rd_rs_0 | b_rd_rs_1;
membusif membusif0(
.clk(clk),
.reset(reset),
.s_address(a_address),
.s_write(a_write),
.s_read(a_read),
.s_writedata(a_writedata),
.s_readdata(a_readdata),
.s_waitrequest(a_waitrequest),
.m_rq_cyc(b_rq_cyc),
.m_rd_rq(b_rd_rq),
.m_wr_rq(b_wr_rq),
.m_ma(b_ma),
.m_sel(b_sel),
.m_fmc_select(b_fmc_select),
.m_mb_write(b_mb_write),
.m_wr_rs(b_wr_rs),
.m_mb_read(b_mb_read),
.m_addr_ack(b_addr_ack),
.m_rd_rs(b_rd_rs));
// Memory
wire [17:0] cm_address;
wire cm_write;
wire cm_read;
wire [35:0] cm_writedata;
wire [35:0] cm_readdata;
wire cm_waitrequest;
wire [0:35] b_mb_read_0;
wire b_addr_ack_0;
wire b_rd_rs_0;
// core161c_x cmem(
// core164 cmem(
core32k cmem(
.clk(clk),
.reset(~reset),
.power(1'b1),
.sw_single_step(1'b0),
.sw_restart(1'b0),
.membus_rq_cyc_p0(b_rq_cyc),
.membus_rd_rq_p0(b_rd_rq),
.membus_wr_rq_p0(b_wr_rq),
.membus_ma_p0(b_ma),
.membus_sel_p0(b_sel),
.membus_fmc_select_p0(b_fmc_select),
.membus_mb_in_p0(b_mb_write),
.membus_wr_rs_p0(b_wr_rs),
.membus_mb_out_p0(b_mb_read_0),
.membus_addr_ack_p0(b_addr_ack_0),
.membus_rd_rs_p0(b_rd_rs_0),
.membus_wr_rs_p1(1'b0),
.membus_rq_cyc_p1(1'b0),
.membus_rd_rq_p1(1'b0),
.membus_wr_rq_p1(1'b0),
.membus_ma_p1(15'b0),
.membus_sel_p1(4'b0),
.membus_fmc_select_p1(1'b0),
.membus_mb_in_p1(36'b0),
.membus_wr_rs_p2(1'b0),
.membus_rq_cyc_p2(1'b0),
.membus_rd_rq_p2(1'b0),
.membus_wr_rq_p2(1'b0),
.membus_ma_p2(15'b0),
.membus_sel_p2(4'b0),
.membus_fmc_select_p2(1'b0),
.membus_mb_in_p2(36'b0),
.membus_wr_rs_p3(1'b0),
.membus_rq_cyc_p3(1'b0),
.membus_rd_rq_p3(1'b0),
.membus_wr_rq_p3(1'b0),
.membus_ma_p3(15'b0),
.membus_sel_p3(4'b0),
.membus_fmc_select_p3(1'b0),
.membus_mb_in_p3(36'b0),
.m_address(cm_address),
.m_write(cm_write),
.m_read(cm_read),
.m_writedata(cm_writedata),
.m_readdata(cm_readdata),
.m_waitrequest(cm_waitrequest)
);
// memory_16k cmem_x(
memory_32k cmem_x(
.i_clk(clk),
.i_reset_n(reset),
.i_address(cm_address),
.i_write(cm_write),
.i_read(cm_read),
.i_writedata(cm_writedata),
.o_readdata(cm_readdata),
.o_waitrequest(cm_waitrequest));
reg [17:0] fm_address = 0;
reg fm_write = 0;
reg fm_read = 0;
reg [35:0] fm_writedata = 0;
wire [35:0] fm_readdata;
wire fm_waitrequest;
wire [0:35] b_mb_read_1;
wire b_addr_ack_1;
wire b_rd_rs_1;
fast162_dp fmem(
.clk(clk),
.reset(~reset),
.power(1'b1),
.sw_single_step(1'b0),
.sw_restart(1'b0),
.membus_rq_cyc_p0(b_rq_cyc),
.membus_rd_rq_p0(b_rd_rq),
.membus_wr_rq_p0(b_wr_rq),
.membus_ma_p0(b_ma),
.membus_sel_p0(b_sel),
.membus_fmc_select_p0(b_fmc_select),
.membus_mb_in_p0(b_mb_write),
.membus_wr_rs_p0(b_wr_rs),
.membus_mb_out_p0(b_mb_read_1),
.membus_addr_ack_p0(b_addr_ack_1),
.membus_rd_rs_p0(b_rd_rs_1),
.membus_wr_rs_p1(1'b0),
.membus_rq_cyc_p1(1'b0),
.membus_rd_rq_p1(1'b0),
.membus_wr_rq_p1(1'b0),
.membus_ma_p1(15'b0),
.membus_sel_p1(4'b0),
.membus_fmc_select_p1(1'b0),
.membus_mb_in_p1(36'b0),
.membus_wr_rs_p2(1'b0),
.membus_rq_cyc_p2(1'b0),
.membus_rd_rq_p2(1'b0),
.membus_wr_rq_p2(1'b0),
.membus_ma_p2(15'b0),
.membus_sel_p2(4'b0),
.membus_fmc_select_p2(1'b0),
.membus_mb_in_p2(36'b0),
.membus_wr_rs_p3(1'b0),
.membus_rq_cyc_p3(1'b0),
.membus_rd_rq_p3(1'b0),
.membus_wr_rq_p3(1'b0),
.membus_ma_p3(15'b0),
.membus_sel_p3(4'b0),
.membus_fmc_select_p3(1'b0),
.membus_mb_in_p3(36'b0),
.s_address(fm_address),
.s_write(fm_write),
.s_read(fm_read),
.s_writedata(fm_writedata),
.s_readdata(fm_readdata),
.s_waitrequest(fm_waitrequest)
);
initial begin
$dumpfile("dump.vcd");
$dumpvars();
cmem_x.ram.ram[3] = 36'o101010101010;
cmem_x.ram.ram[4] = 123;
cmem_x.ram.ram[5] = 321;
cmem_x.ram.ram['o123] = 36'o112233445566;
cmem_x.ram.ram['o124] = 36'o111111111111;
cmem_x.ram.ram['o40123] = 36'o111111111111;
fmem.ff[3] = 36'o777777666666;
fmem.ff[4] = 36'o555555444444;
fmem.ff[5] = 36'o333333222222;
#5;
#200;
#5000;
/*
@(posedge clk);
fm_address <= 3;
fm_write <= 1;
fm_writedata <= 36'o1000123;
@(negedge fm_write);
@(posedge clk);
fm_address <= 5;
fm_write <= 1;
fm_writedata <= 36'o101202303404;
@(negedge fm_write);
@(posedge clk);
fm_address <= 3;
fm_read <= 1;
@(negedge fm_read);
*/
// write address
@(posedge clk);
a_address <= 0;
a_write <= 1;
a_writedata <= 32'o0040123;
@(negedge a_write);
@(posedge clk);
a_address <= 2;
a_read <= 1;
@(negedge a_read);
@(posedge clk);
a_address <= 1;
a_read <= 1;
@(negedge a_read);
#2000;
@(posedge clk);
a_address <= 1;
a_write <= 1;
a_writedata <= 32'o0000555;
@(negedge a_write);
@(posedge clk);
a_address <= 2;
a_write <= 1;
a_writedata <= 32'o101202;
@(negedge a_write);
/* // write address
@(posedge clk);
a_address <= 0;
a_write <= 1;
a_writedata <= 32'o0000124;
@(negedge a_write);
@(posedge clk);
a_address <= 2;
a_read <= 1;
@(negedge a_read);
@(posedge clk);
a_address <= 1;
a_read <= 1;
@(negedge a_read);
*/
/*
// write low word
@(posedge clk);
a_address <= 1;
a_write <= 1;
a_writedata <= 32'o111222;
@(negedge a_write);
// write high word
@(posedge clk);
a_address <= 2;
a_write <= 1;
a_writedata <= 32'o333444;
@(negedge a_write);
*/
end
initial begin
#40000;
$finish;
end
reg [0:35] data;
always @(posedge clk) begin
if(~a_waitrequest & a_write)
a_write <= 0;
if(~a_waitrequest & a_read) begin
a_read <= 0;
data <= a_readdata;
end
if(~fm_waitrequest & fm_write)
fm_write <= 0;
if(~fm_waitrequest & fm_read) begin
fm_read <= 0;
data <= fm_readdata;
end
end
endmodule
|
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_mc_b_channel.v
//
// Description:
// This module is responsible for returning the write response to the master
// that initiated the write. The write address channel module will push the
// transaction ID into a FIFO in the write response module after the
// completion of the address write phase of the transaction. If strict
// coherency is enabled (C_STRICT_COHERENCY == 1), then this module will
// monitor the MCB command/write FIFOs to determine when to send back the
// response. It will not send the response until it is guaranteed that the
// write has been committed completely to memory.
//
// ERROR RESPONSE
// If the MCB write channel indicates there is an error or write FIFO under
// run then the AXI SLVERR response is returned otherwise the OKAY response
// is returned.
//
// WRITE COHERENCY CHECKING
// The MCB hard block can have up to 6 independent ports to memory. If the
// MCB block is configured as single port or as multi-port with separate
// regions then write coherency logic is not required. In all other cases,
// once a transaction has been sent to the MCB CMD channel, it is not
// guaranteed that it will commit to memory before a transaction on another
// port. To ensure that the response is only sent after the data has been
// written to external memory the write response will not be sent until
// either the write data FIFO is empty or that the command FIFO is empty.
//
// Assertions:
// 1. Standard FIFO assertions on bid_fifo_0.
// 2. bvalid == 0, when C_STRICT_COHERENCY == 1 and mcb_empty == 0.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_0_axi_mc_b_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire reset,
// AXI signals
output wire [C_ID_WIDTH-1:0] bid,
output wire [1:0] bresp,
output wire bvalid,
input wire bready,
// Signals to/from the axi_mc_aw_channel modules
input wire b_push,
input wire [C_ID_WIDTH-1:0] b_awid,
input wire b_resp_rdy,
output wire b_full
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// FIFO settings
localparam P_WIDTH = C_ID_WIDTH;
localparam P_DEPTH = 8;
localparam P_AWIDTH = 3;
// AXI protocol responses:
localparam P_OKAY = 2'b00;
localparam P_EXOKAY = 2'b01;
localparam P_SLVERR = 2'b10;
localparam P_DECERR = 2'b11;
localparam B_RESP_PERF = 1'b1; // Set to 1 to increase the write response performance for back to back single beats.
// Set to 0 in case of timing issues, but performance degrades for back to back single beats.
wire empty;
wire bhandshake;
wire [C_ID_WIDTH-1:0] bid_i;
reg b_pop;
reg bvalid_i;
reg [C_ID_WIDTH-1:0] bid_t;
assign bresp = P_OKAY;
generate
if (B_RESP_PERF == 1) begin
assign bid = bid_t;
assign bvalid = bvalid_i;
assign bhandshake = ~bvalid | bready;
always @(*)
b_pop = bhandshake & ~empty;
always @(posedge clk) begin
if(reset) begin
bid_t <= 'b0;
bvalid_i <= 1'b0;
end else if(bhandshake) begin
bid_t <= bid_i;
bvalid_i <= ~empty;
end
end
end else begin // B_RESP_PERF
assign bid = bid_i;
assign bvalid = bvalid_i;
assign bhandshake = bvalid & bready;
always @(posedge clk)
b_pop <= bhandshake;
always @(posedge clk) begin
if (reset | bhandshake) begin
bvalid_i <= 1'b0;
end else if (~empty & (~b_pop)) begin
bvalid_i <= 1'b1;
end
end
end // B_RESP_PERF
endgenerate
mig_7series_v4_0_axi_mc_fifo #
(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
bid_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( b_push ) ,
.rd_en ( b_pop ) ,
.din ( b_awid ) ,
.dout ( bid_i ) ,
.a_full ( ) ,
.full ( b_full ) ,
.a_empty ( ) ,
.empty ( empty )
);
endmodule
`default_nettype wire
|
module mem_wait
(/*AUTOARG*/
// Outputs
mem_wait_arry,
// Inputs
clk, rst, lsu_valid, f_sgpr_lsu_instr_done, f_vgpr_lsu_wr_done,
lsu_wfid, f_sgpr_lsu_instr_done_wfid, f_vgpr_lsu_wr_done_wfid
);
input clk,rst;
input lsu_valid, f_sgpr_lsu_instr_done, f_vgpr_lsu_wr_done;
input [5:0] lsu_wfid, f_sgpr_lsu_instr_done_wfid, f_vgpr_lsu_wr_done_wfid;
output [`WF_PER_CU-1:0] mem_wait_arry;
wire [`WF_PER_CU-1:0] decoded_issue_value, decoded_sgpr_retire_value,
decoded_vgpr_retire_value,
mem_wait_reg_wr_en, mem_waiting_wf;
decoder_6b_40b_en issue_value_decoder
(
.addr_in(lsu_wfid),
.out(decoded_issue_value),
.en(lsu_valid)
);
decoder_6b_40b_en retire_sgpr_value_decoder
(
.addr_in(f_sgpr_lsu_instr_done_wfid),
.out(decoded_sgpr_retire_value),
.en(f_sgpr_lsu_instr_done)
);
decoder_6b_40b_en retire_vgpr_value_decoder
(
.addr_in(f_vgpr_lsu_wr_done_wfid),
.out(decoded_vgpr_retire_value),
.en(f_vgpr_lsu_wr_done)
);
dff_set_en_rst mem_wait[`WF_PER_CU-1:0]
(
.q(mem_waiting_wf),
.d(40'b0),
.en(mem_wait_reg_wr_en),
.clk(clk),
.set(decoded_issue_value),
.rst(rst)
);
assign mem_wait_reg_wr_en = decoded_vgpr_retire_value | decoded_sgpr_retire_value | decoded_issue_value;
assign mem_wait_arry = mem_waiting_wf;
endmodule
|
// $Header: $
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
// All Right Reserved.
/////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.71)
// \ \ Description :
// / /
// /__/ /\ Filename : FRAME_ECCE2.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 07/22/10 - Change Error to Message for input rbt file check (CR568991)
// 08/04/11 - Change FRAME_RBT_IN_FILENAME ot NONE (CR618399)
//////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module FRAME_ECCE2 (
CRCERROR,
ECCERROR,
ECCERRORSINGLE,
FAR,
SYNBIT,
SYNDROME,
SYNDROMEVALID,
SYNWORD
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif //
parameter FARSRC = "EFAR";
parameter FRAME_RBT_IN_FILENAME = "NONE";
localparam FRAME_ECC_OUT_RBT_FILENAME = "frame_rbt_out_e2.txt";
localparam FRAME_ECC_OUT_ECC_FILENAME = "frame_ecc_out_e2.txt";
output CRCERROR;
output ECCERROR;
output ECCERRORSINGLE;
output SYNDROMEVALID;
output [12:0] SYNDROME;
output [25:0] FAR;
output [4:0] SYNBIT;
output [6:0] SYNWORD;
reg clk_osc = 0;
integer rbt_fd;
integer ecc_ecc_out_fd;
integer ecc_rbt_out_fd;
reg [31:0] rb_data = 32'b0;
reg [31:0] data_rbt;
reg [31:0] tmpwd1;
reg [31:0] tmpwd2;
reg sim_file_flag = 0;
reg [31:0] frame_data_bak[255:174];
reg [31:0] frame_data[255:174];
integer frame_addr_i;
reg [31:0] frame_addr;
reg [31:0] rb_crc_rbt;
reg [31:0] crc_curr = 32'b0;
reg [31:0] crc_new = 32'b0;
reg [36:0] crc_input = 32'b0;
reg rbcrc_err = 0;
reg rd_rbt_hold = 0;
reg rd_rbt_hold1 = 0;
reg rd_rbt_hold2 = 0;
reg [6:0] ecc_wadr;
reg [4:0] ecc_badr;
reg [31:0] corr_wd;
reg [31:0] corr_wd1;
reg rb_data_en = 0;
reg end_rbt = 0;
reg rd_rbt_en = 0;
reg hamming_rst = 0;
integer i = 0;
integer bi = 174;
integer nbi = 174;
integer n = 174;
reg ecc_run = 0;
reg calc_syndrome = 1;
wire [12:0] new_S;
wire [12:0] next_S;
reg [12:0] S = 13'd0;
reg S_valid = 0;
reg S_valid_ungated = 0;
reg [31:0] ecc_corr_mask = 32'b0;
reg ecc_error = 0;
reg ecc_error_single = 0;
reg ecc_error_ungated = 0;
reg [4:0] ecc_synbit = 5'b0;
reg [6:0] ecc_synword = 7'b0;
reg [4:0] ecc_synbit_next = 5'b0;
reg [6:0] ecc_synword_next = 7'b0;
reg efar_save = 0;
reg [11:5] hiaddr = 7'd46;
wire [11:5] hiaddrp1;
wire hiaddr63;
wire hiaddr127;
wire hclk;
wire xorall;
wire overall;
wire S_valid_next;
wire S_valid_ungated_next;
wire next_error;
wire [12:0] new_S_xor_S;
wire [6:0] ecc_synword_next_not_par;
reg [160:0] tmps1;
reg [160:0] tmps2;
reg [160:0] tmps3;
initial begin
case (FARSRC)
"EFAR" : ;
"FAR" : ;
default : begin
$display("Attribute Syntax Error : The Attribute FARSRC on FRAME_ECCE2 instance %m is set to %s. Legal values for this attribute are EFAR, or FAR.", FARSRC);
$finish;
end
endcase
sim_file_flag = 0;
if (FRAME_RBT_IN_FILENAME == "NONE")
$display(" Message: The configuration frame data file for FRAME_ECCE2 instance %m was not found. Use ICAPE2 to generate frame data file and then use the FRAME_RBT_IN_FILENAME parameter to pass the file name.\n");
else begin
rbt_fd = $fopen(FRAME_RBT_IN_FILENAME, "r");
ecc_ecc_out_fd = $fopen(FRAME_ECC_OUT_ECC_FILENAME, "w");
ecc_rbt_out_fd = $fopen(FRAME_ECC_OUT_RBT_FILENAME, "w");
if (rbt_fd == 0)
$display(" Message: The configuration frame data file %s for FRAME_ECCE2 instance %m was not found. Use ICAPE2 to generate frame data file and then use the FRAME_RBT_IN_FILENAME parameter to pass the file name.\n", FRAME_RBT_IN_FILENAME);
else
if ($fscanf(rbt_fd, "%s\t%s\t%s", tmps1, tmps2, tmps3) != -1)
rd_rbt_en <= #1 1;
if (ecc_ecc_out_fd == 0)
$display(" Error: The ecc frame data out file frame_ecc_out_e2.txt for FRAME_ECCE2 instance %m can not created.\n");
if (ecc_rbt_out_fd == 0)
$display(" Error: The rbt frame data out file frame_rbt_out_e2.txt for FRAME_ECCE2 instance %m can not created.\n");
if (rbt_fd !=0 && ecc_ecc_out_fd != 0 && ecc_rbt_out_fd != 0 )
sim_file_flag = 1;
end
end
assign CRCERROR = rbcrc_err;
assign ECCERROR = ecc_error;
assign ECCERRORSINGLE = ecc_error_single;
assign SYNDROMEVALID = S_valid;
assign SYNDROME = S;
assign FAR = frame_addr[25:0];
assign SYNBIT = ecc_synbit;
assign SYNWORD = ecc_synword;
always
#2000 clk_osc <= ~clk_osc;
always @(negedge clk_osc )
if (sim_file_flag == 1 && rd_rbt_en == 1 && rd_rbt_hold1 == 0 ) begin
if ( $fscanf(rbt_fd, "%d\t%b\t%b", frame_addr_i, data_rbt, rb_crc_rbt) != -1) begin
rb_data_en <= 1;
frame_addr <= frame_addr_i;
rb_data <= data_rbt;
crc_input[36:0] = {5'b00011, data_rbt};
crc_new[31:0] = bcc_next(crc_curr, crc_input);
crc_curr[31:0] <= crc_new;
if (n <= 255) begin
frame_data[n] <= data_rbt[31:0];
if (n == 255)
n <= 174;
else if (n==191)
n <= 193;
else
n <= n+ 1;
end
end
else begin
rb_data_en <= 0;
end_rbt <= 1;
n <= 173;
if ( crc_new != rb_crc_rbt)
rbcrc_err <= 1;
else
rbcrc_err <= 0;
$fclose(rbt_fd);
end
end
always @(negedge clk_osc)
if (rb_data_en == 1) begin
if ( rd_rbt_hold1 == 1 && rd_rbt_hold == 1 && rd_rbt_hold2 == 0) begin
for (bi = 174; bi<= 255; bi=bi+1)
frame_data_bak[bi] = frame_data[bi];
if (ecc_error_single == 1) begin
ecc_wadr[6:0] = SYNDROME[11:5];
ecc_badr[4:0] = SYNDROME[4:0];
corr_wd = frame_data[ecc_wadr];
corr_wd1 = frame_data[ecc_wadr];
corr_wd[ecc_badr] = ~corr_wd1[ecc_badr];
frame_data_bak[ecc_wadr] = corr_wd;
end
for (nbi = 174; nbi<= 255; nbi=nbi+1) begin
if (nbi != 192) begin
tmpwd1 = frame_data[nbi];
tmpwd2 = frame_data_bak[nbi];
$fwriteb(ecc_rbt_out_fd, tmpwd1);
$fwriteb(ecc_rbt_out_fd, "\n");
$fwriteb(ecc_ecc_out_fd, tmpwd2);
$fwriteb(ecc_ecc_out_fd, "\n");
end
end
end
end
else if (end_rbt ==1) begin
$fclose(ecc_ecc_out_fd);
$fclose(ecc_rbt_out_fd);
end
always @(posedge clk_osc)
if (rb_data_en == 1) begin
if (n == 255)
rd_rbt_hold <= 1;
rd_rbt_hold2 <= rd_rbt_hold1;
rd_rbt_hold1 <= rd_rbt_hold;
if (rd_rbt_hold2 ==1) begin
rd_rbt_hold <= 0;
rd_rbt_hold1 <= 0;
rd_rbt_hold2 <= 0;
end
end
else if ( end_rbt == 1) begin
rd_rbt_hold <= 1;
rd_rbt_hold1 <= 1;
rd_rbt_hold2 <= 1;
end
always @(negedge clk_osc)
if (rd_rbt_hold2 == 1 && hamming_rst == 0)
hamming_rst <= 1;
else
hamming_rst <= 0;
assign S_valid_next = rb_data_en & hiaddr127 & ~ecc_run;
assign S_valid_ungated_next = rb_data_en & hiaddr127;
assign next_error = (| next_S);
assign hiaddrp1 = hiaddr + 1;
assign hiaddr63 = & hiaddr[10:5];
assign hiaddr127 = & hiaddr[11:5];
assign hclk = ( hiaddr == 7'd87 ) ? 1 : 0;
always @( posedge clk_osc or posedge hamming_rst)
if (hamming_rst == 1)
hiaddr <= 7'd46;
else if ( rb_data_en == 1 ) begin
if ( hiaddr127 )
hiaddr <= 7'd46;
else
hiaddr <= { hiaddrp1[11:6], ( hiaddr63 | hiaddrp1[5] ) };
end
assign xorall = ( ^ rb_data[31:13] ) ^ ( ( ~ hclk ) & ( ^ rb_data[12:0] ) );
assign overall = ( ^ rb_data[31:13] ) ^ ( ~(hclk & calc_syndrome) & ( ^ rb_data[12:0] ) );
assign new_S[12] = overall;
assign new_S[4] = rb_data[31] ^ rb_data[30] ^ rb_data[29] ^ rb_data[28] ^
rb_data[27] ^ rb_data[26] ^ rb_data[25] ^ rb_data[24] ^
rb_data[23] ^ rb_data[22] ^ rb_data[21] ^ rb_data[20] ^
rb_data[19] ^ rb_data[18] ^ rb_data[17] ^ rb_data[16] ^
( hclk & ~calc_syndrome & rb_data[4] );
assign new_S[3] = rb_data[31] ^ rb_data[30] ^ rb_data[29] ^ rb_data[28] ^
rb_data[27] ^ rb_data[26] ^ rb_data[25] ^ rb_data[24] ^
rb_data[15] ^ rb_data[14] ^ rb_data[13] ^
( hclk ? ~calc_syndrome & rb_data[3] :
( rb_data[12] ^ rb_data[11] ^ rb_data[10] ^ rb_data[9] ^ rb_data[8]) );
assign new_S[2] = rb_data[31] ^ rb_data[30] ^ rb_data[29] ^ rb_data[28] ^
rb_data[23] ^ rb_data[22] ^ rb_data[21] ^ rb_data[20] ^
rb_data[15] ^ rb_data[14] ^ rb_data[13] ^
( hclk ? ~calc_syndrome & rb_data[2] :
( rb_data[12] ^ rb_data[7] ^ rb_data[6] ^ rb_data[5] ^ rb_data[4] ) );
assign new_S[1] = rb_data[31] ^ rb_data[30] ^ rb_data[27] ^ rb_data[26] ^
rb_data[23] ^ rb_data[22] ^ rb_data[19] ^ rb_data[18] ^
rb_data[15] ^ rb_data[14] ^
( hclk ? ~calc_syndrome & rb_data[1] :
( rb_data[11] ^ rb_data[10] ^ rb_data[7] ^ rb_data[6] ^ rb_data[3] ^ rb_data[2] ));
assign new_S[0] = rb_data[31] ^ rb_data[29] ^ rb_data[27] ^ rb_data[25] ^
rb_data[23] ^ rb_data[21] ^ rb_data[19] ^ rb_data[17] ^
rb_data[15] ^ rb_data[13] ^
( hclk ? ~calc_syndrome & rb_data[0] :
( rb_data[11] ^ rb_data[9] ^ rb_data[7] ^ rb_data[5] ^ rb_data[3] ^ rb_data[1] ) );
assign new_S[11:5] = ( hiaddr & { 7 { xorall } } ) ^
( { 7 { hclk & ~calc_syndrome } } &
{ rb_data[11], rb_data[10], rb_data[9], rb_data[8],
rb_data[7], rb_data[6], rb_data[5] } );
assign new_S_xor_S = S ^ new_S;
assign next_S = (hiaddr127 & calc_syndrome) ? {(^new_S_xor_S), new_S_xor_S[11:0]} :
(hiaddr == 7'd46) ? new_S : new_S_xor_S;
assign ecc_synword_next_not_par = new_S_xor_S[11:5] - 7'd46 - {6'b0, new_S_xor_S[11]};
always @(ecc_synword_next_not_par, new_S_xor_S) begin
if (!new_S_xor_S[12]) begin
ecc_synword_next = 7'd0;
ecc_synbit_next = 5'd0;
end else begin
case (new_S_xor_S[11:0])
12'h000 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd12;
end
12'h001 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd0;
end
12'h002 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd1;
end
12'h004 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd2;
end
12'h008 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd3;
end
12'h010 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd4;
end
12'h020 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd5;
end
12'h040 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd6;
end
12'h080 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd7;
end
12'h100 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd8;
end
12'h200 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd9;
end
12'h400 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd10;
end
12'h800 : begin
ecc_synword_next = 7'd40;
ecc_synbit_next = 5'd11;
end
default : begin
ecc_synword_next = ecc_synword_next_not_par;
ecc_synbit_next = new_S_xor_S[4:0];
end
endcase
end
end
always @( posedge clk_osc or posedge hamming_rst) begin
if ( hamming_rst == 1 ) begin
S_valid <= 0;
S_valid_ungated <= 0;
S <= 13'd0;
end
else if ( rb_data_en == 1 ) begin
S_valid_ungated <= S_valid_ungated_next;
S_valid <= S_valid_next;
S <= next_S;
end else begin
S_valid_ungated <= 0;
S_valid <= 0;
end
if (hamming_rst == 1 ) begin
ecc_synword <= 7'd0;
ecc_synbit <= 5'd0;
end
else if ( S_valid_next & ~efar_save ) begin
ecc_synword <= ecc_synword_next;
ecc_synbit <= ecc_synbit_next;
end
if (hamming_rst == 1) begin
ecc_error <= 0;
ecc_error_single <= 0;
end
else if (S_valid_next == 1) begin
ecc_error <= next_error;
ecc_error_single <= next_S[12];
end
if (hamming_rst == 1)
ecc_error_ungated <= 0;
else if (S_valid_ungated_next == 1)
ecc_error_ungated <= next_error;
if (hamming_rst == 1)
efar_save <= 0;
else if (ecc_error == 1 | ((S_valid_ungated_next & next_error) == 1))
efar_save <= 1;
end
function [31:0] bcc_next;
input [31:0] bcc;
input [36:0] in;
reg [31:0] x;
reg [36:0] m;
begin
m = in;
x = in[31:0] ^ bcc;
bcc_next[31] = m[32]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[24]^x[20]^x[19]^x[18]^x[15]^x[13]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[1]^x[0];
bcc_next[30] = m[35]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[19]^x[18]^x[17]^x[14]^x[12]^x[10]^x[9]^x[8]^x[7]^x[5]^x[4]^x[0];
bcc_next[29] = m[34]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[18]^x[17]^x[16]^x[13]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[3];
bcc_next[28] = m[33]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[17]^x[16]^x[15]^x[12]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2];
bcc_next[27] = m[32]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[16]^x[15]^x[14]^x[11]^x[9]^x[7]^x[6]^x[5]^x[4]^x[2]^x[1];
bcc_next[26] = x[31]^x[27]^x[26]^x[25]^x[24]^x[23]^x[22]^x[19]^x[15]^x[14]^x[13]^x[10]^x[8]^x[6]^x[5]^x[4]^x[3]^x[1]^x[0];
bcc_next[25] = m[32]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[23]^x[22]^x[21]^x[20]^x[19]^x[15]^x[14]^x[12]^x[11]^x[10]^x[8]^x[7]^x[6]^x[4]^x[3]^x[2]^x[1];
bcc_next[24] = m[35]^x[31]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[22]^x[21]^x[20]^x[19]^x[18]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1]^x[0];
bcc_next[23] = m[32]^m[34]^m[36]^x[31]^x[28]^x[26]^x[25]^x[23]^x[21]^x[17]^x[15]^x[12]^x[11]^x[4]^x[2];
bcc_next[22] = m[32]^m[33]^m[35]^m[36]^x[29]^x[28]^x[25]^x[22]^x[19]^x[18]^x[16]^x[15]^x[14]^x[13]^x[9]^x[8]^x[6]^x[5]^x[3]^x[0];
bcc_next[21] = m[34]^m[35]^m[36]^x[30]^x[29]^x[21]^x[20]^x[19]^x[17]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0];
bcc_next[20] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[30]^x[27]^x[24]^x[16]^x[15]^x[3];
bcc_next[19] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[29]^x[26]^x[23]^x[15]^x[14]^x[2];
bcc_next[18] = m[33]^m[34]^m[36]^x[27]^x[25]^x[24]^x[22]^x[20]^x[19]^x[18]^x[15]^x[14]^x[11]^x[10]^x[9]^x[8]^x[6]^x[5]^x[0];
bcc_next[17] = m[33]^m[35]^m[36]^x[31]^x[30]^x[29]^x[28]^x[27]^x[26]^x[23]^x[21]^x[20]^x[17]^x[15]^x[14]^x[11]^x[7]^x[6]^x[4]^x[1]^x[0];
bcc_next[16] = m[32]^m[34]^m[35]^x[30]^x[29]^x[28]^x[27]^x[26]^x[25]^x[22]^x[20]^x[19]^x[16]^x[14]^x[13]^x[10]^x[6]^x[5]^x[3]^x[0];
bcc_next[15] = m[33]^m[34]^x[31]^x[29]^x[28]^x[27]^x[26]^x[25]^x[24]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[5]^x[4]^x[2];
bcc_next[14] = m[32]^m[33]^x[30]^x[28]^x[27]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[14]^x[12]^x[11]^x[8]^x[4]^x[3]^x[1];
bcc_next[13] = m[36]^x[30]^x[28]^x[26]^x[25]^x[23]^x[22]^x[20]^x[18]^x[17]^x[16]^x[15]^x[9]^x[8]^x[7]^x[6]^x[5]^x[3]^x[2]^x[1];
bcc_next[12] = m[32]^m[35]^m[36]^x[31]^x[30]^x[28]^x[25]^x[22]^x[21]^x[20]^x[18]^x[17]^x[16]^x[14]^x[13]^x[11]^x[10]^x[9]^x[7]^x[4]^x[2];
bcc_next[11] = m[32]^m[34]^m[35]^m[36]^x[28]^x[21]^x[18]^x[17]^x[16]^x[12]^x[11]^x[5]^x[3]^x[0];
bcc_next[10] = m[33]^m[34]^m[35]^x[31]^x[27]^x[20]^x[17]^x[16]^x[15]^x[11]^x[10]^x[4]^x[2];
bcc_next[9] = m[33]^m[34]^m[36]^x[31]^x[29]^x[28]^x[27]^x[26]^x[24]^x[20]^x[18]^x[16]^x[14]^x[13]^x[11]^x[8]^x[6]^x[5]^x[3]^x[0];
bcc_next[8] = m[33]^m[35]^m[36]^x[31]^x[29]^x[26]^x[25]^x[24]^x[23]^x[20]^x[18]^x[17]^x[12]^x[11]^x[9]^x[8]^x[7]^x[6]^x[4]^x[2]^x[1]^x[0];
bcc_next[7] = m[32]^m[34]^m[35]^x[30]^x[28]^x[25]^x[24]^x[23]^x[22]^x[19]^x[17]^x[16]^x[11]^x[10]^x[8]^x[7]^x[6]^x[5]^x[3]^x[1]^x[0];
bcc_next[6] = m[32]^m[33]^m[34]^m[36]^x[30]^x[28]^x[23]^x[22]^x[21]^x[20]^x[19]^x[16]^x[13]^x[11]^x[8]^x[7]^x[4]^x[2]^x[1];
bcc_next[5] = m[33]^m[35]^m[36]^x[30]^x[28]^x[24]^x[22]^x[21]^x[13]^x[12]^x[11]^x[9]^x[8]^x[7]^x[5]^x[3];
bcc_next[4] = m[34]^m[35]^m[36]^x[31]^x[30]^x[28]^x[24]^x[23]^x[21]^x[19]^x[18]^x[15]^x[13]^x[12]^x[9]^x[7]^x[5]^x[4]^x[2]^x[1]^x[0];
bcc_next[3] = m[32]^m[33]^m[34]^m[35]^m[36]^x[31]^x[28]^x[24]^x[23]^x[22]^x[19]^x[17]^x[15]^x[14]^x[13]^x[12]^x[10]^x[9]^x[5]^x[4]^x[3];
bcc_next[2] = m[32]^m[33]^m[34]^m[35]^x[31]^x[30]^x[27]^x[23]^x[22]^x[21]^x[18]^x[16]^x[14]^x[13]^x[12]^x[11]^x[9]^x[8]^x[4]^x[3]^x[2];
bcc_next[1] = m[32]^m[33]^m[34]^x[31]^x[30]^x[29]^x[26]^x[22]^x[21]^x[20]^x[17]^x[15]^x[13]^x[12]^x[11]^x[10]^x[8]^x[7]^x[3]^x[2]^x[1];
bcc_next[0] = m[32]^m[33]^x[31]^x[30]^x[29]^x[28]^x[25]^x[21]^x[20]^x[19]^x[16]^x[14]^x[12]^x[11]^x[10]^x[9]^x[7]^x[6]^x[2]^x[1]^x[0];
end
endfunction
specify
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
//-----------------------------------------------------------------------------
// (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Filename: axi_traffic_gen_v2_0_s_w_channel.v
// Version : v1.0
// Description: slave interface write channel.Write requests are processed
// to write to target location.
// Verilog-Standard:verilog-2001
//---------------------------------------------------------------------------
//Specific WARNINGs moved to INFO by Vivado Synthesis Tool
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_traffic_gen_v2_0_s_w_channel #(
parameter C_BASEADDR = 32'hffffffff,
parameter C_HIGHADDR = 32'h00000000,
parameter C_S_AXI_ID_WIDTH = 1 ,
parameter C_S_AXI_DATA_WIDTH = 32 ,
parameter C_S_AXI_AWUSER_WIDTH = 8 ,
parameter C_ZERO_INVALID = 1 ,
parameter C_NO_EXCL = 0 ,
parameter C_ATG_BASIC_AXI4 = 1 ,
parameter C_ATG_AXI4LITE = 0
) (
// system
input Clk ,
input rst_l ,
// AW
input [C_S_AXI_ID_WIDTH-1:0] awid_s ,
input [31:0] awaddr_s ,
input [7:0] awlen_s ,
input [2:0] awsize_s ,
input [1:0] awburst_s ,
input [0:0] awlock_s ,
input [3:0] awcache_s ,
input [2:0] awprot_s ,
input [3:0] awqos_s ,
input [C_S_AXI_AWUSER_WIDTH-1:0] awuser_s ,
input awvalid_s ,
output awready_s ,
// W
input wlast_s ,
input [C_S_AXI_DATA_WIDTH-1:0] wdata_s ,
input [C_S_AXI_DATA_WIDTH/8-1:0] wstrb_s ,
input wvalid_s ,
output wready_s ,
//B
output [C_S_AXI_ID_WIDTH-1:0] bid_s ,
output [1:0] bresp_s ,
output bvalid_s ,
input bready_s ,
// Register module
input reg1_disallow_excl ,
input reg1_sgl_slv_wr ,
input reg1_wrs_block_rds ,
output [15:0] err_new_slv ,
output [15:0] wr_reg_decode ,
output [31:0] wr_reg_data ,
// sr channel
input [71:0] slv_ex_info0_ff ,
output reg slv_ex_valid0_ff ,
input[71:0] slv_ex_info1_ff ,
output reg slv_ex_valid1_ff ,
input slv_ex_new_valid0 ,
input slv_ex_new_valid1 ,
input [15:0] ar_agen_addr ,
output [C_S_AXI_DATA_WIDTH-1:0] slvram_rd_out ,
//slvram
input [63:0] sram_rd_data_a ,
output [10:0] slvram_waddr_ff ,
output [7:0] slvram_we_ff ,
output [63:0] slvram_write_data_ff,
//axi_traffic_gen_v2_0_cmdram
output [15:0] aw_agen_addr ,
output [15:0] cmdram_we ,
output [64-1:0] slvram_wr_data ,
//paramram
output awfifo_valid ,
output [71:0] awfifo_out ,
output wfifo_valid ,
output [C_S_AXI_DATA_WIDTH*9/8+1-1:0] wfifo_out
);
wire [31:0] base_addr = C_BASEADDR;
wire [31:0] high_addr = C_HIGHADDR;
wire [31:0] addr_mask = base_addr[31:0] ^ high_addr[31:0];
//wire [7:0] awlen8_s = awlen_s[7:0] | { 4'h0, awlen3_s[3:0] };
wire [7:0] awlen8_s = awlen_s[7:0] | { 4'h0, 4'h0 };
wire [15:0] awbuf_id = awid_s[C_S_AXI_ID_WIDTH-1:0];
wire [31:0] aw_addr_masked = awaddr_s[31:0] & addr_mask[31:0];
//Address re-mapped
//wire aw_isslvram = ((aw_addr_masked[22:16] != 'h0 ));
wire aw_isslvram = ((aw_addr_masked[15:14]==2'b11));
wire aw_iscmd = ~aw_isslvram && awaddr_s[15];
wire [71:0] awbuf_rawdata = {
awbuf_id[15:0], //71:56
aw_isslvram, aw_iscmd, awprot_s[2:0], awsize_s[2:0], //55:48
awburst_s[1:0], 1'b0,awlock_s[0:0], awcache_s[3:0], //47:40 //awlock made 1-bit
awlen8_s[7:0], //39:32
awaddr_s[31:0] }; //31:0
wire awbuf_valid = awvalid_s && awready_s;
wire awfifo_notfull;
wire aw_agen_write;
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (72),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Awfifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (awbuf_rawdata[71:0]),
.in_push (awbuf_valid ),
.in_pop (aw_agen_write ),
.out_data (awfifo_out[71:0] ),
.is_full ( ),
.is_notfull (awfifo_notfull ),
.is_empty ( ),
.out_valid (awfifo_valid ),
.ex_fifo_dbgout ( )
);
assign awready_s = awfifo_notfull;
wire [15:0] aw_agen_id;
wire [C_S_AXI_DATA_WIDTH/8-1:0] aw_agen_be;
wire aw_agen_pop;
wire aw_agen_done;
wire aw_agen_valid;
wire awfifo_out_is_excl ;
wire aw_agen_pause = awfifo_valid && awfifo_out_is_excl && aw_agen_valid;
assign aw_agen_write = awfifo_valid && ~aw_agen_valid && ~aw_agen_pause;
wire [71:0] slv_ex_wr_info ;
wire slv_ex_addr_matches0 ;
wire slv_ex_id_matches0 ;
wire slv_ex_wr_matches0 ;
wire slv_ex_addr_matches1 ;
wire slv_ex_id_matches1 ;
wire slv_ex_wr_matches1 ;
wire slv_ex_wr_matches ;
wire [1:0] awfifo_out_excl ;
wire awfifo_out_null ;
wire aw_err ;
generate if(C_NO_EXCL == 0 ) begin : S_W_EXCL_0
assign awfifo_out_is_excl = (awfifo_out[45:44] == 2'b01);
assign slv_ex_wr_info = awfifo_out[71:0];
assign slv_ex_addr_matches0 = (slv_ex_wr_info[19:7] == slv_ex_info0_ff[19:7]);
assign slv_ex_id_matches0 = (slv_ex_wr_info[71:56] == slv_ex_info0_ff[71:56]);
assign slv_ex_wr_matches0 = (slv_ex_wr_info[55:20] ==slv_ex_info0_ff[55:20]) &&
(slv_ex_wr_info[6:0] == slv_ex_info0_ff[6:0]) &&
slv_ex_addr_matches0 && slv_ex_id_matches0 &&
slv_ex_valid0_ff;
assign slv_ex_addr_matches1 = (slv_ex_wr_info[19:7] == slv_ex_info1_ff[19:7]);
assign slv_ex_id_matches1 = (slv_ex_wr_info[71:56] == slv_ex_info1_ff[71:56]);
assign slv_ex_wr_matches1 = (slv_ex_wr_info[55:20] ==slv_ex_info1_ff[55:20]) &&
(slv_ex_wr_info[6:0] == slv_ex_info1_ff[6:0]) &&
slv_ex_addr_matches1 && slv_ex_id_matches1 &&
slv_ex_valid1_ff;
assign slv_ex_wr_matches = (C_NO_EXCL) ? 1'b0 :
slv_ex_wr_matches0 || slv_ex_wr_matches1;
assign awfifo_out_excl = (awfifo_out_is_excl && slv_ex_wr_matches) ? 2'b01 :
2'b00;
assign awfifo_out_null = aw_err ||
(awfifo_out_is_excl && ~reg1_disallow_excl &&
~slv_ex_wr_matches && (C_NO_EXCL == 0));
end
endgenerate
generate if(C_NO_EXCL == 1) begin : S_W_EXCL_1
assign awfifo_out_is_excl = 2'b00;
assign slv_ex_wr_matches = 1'b0 ;
assign awfifo_out_excl = 2'b00;
assign awfifo_out_null = aw_err ;
end
endgenerate
assign aw_err = (awfifo_out[55:54] == 2'b00) && (awfifo_out[5:2] == 4'hd) &&
awfifo_out[7] && ~awfifo_out[12];
// writing to reg13, at 0xb4
// and not 0x1XXX (for special queue ops)
wire [1:0] awfifo_out_resp = (reg1_disallow_excl) ? 2'b00 :
(aw_err) ? 2'b10 : awfifo_out_excl[1:0];
axi_traffic_gen_v2_0_addrgen #(
.USE_ADDR_OFFSET (0) ,
.C_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.IS_READ (0) ,
.C_ATG_BASIC_AXI4(C_ATG_BASIC_AXI4) ,
.C_ATG_AXI4LITE (C_ATG_AXI4LITE)
) Aw_agen (
.Clk (Clk ),
.rst_l (rst_l ),
.in_addr ({awfifo_out[55:54], awfifo_out[13:0]} ),
.in_addr_offset(awfifo_out[8:0] ),
.in_id ({ awfifo_out_resp[1:0], awfifo_out_null, awfifo_out[68:56]}),
.in_len (awfifo_out[39:32] ),
.in_size (awfifo_out[50:48] ),
.in_lastaddr (6'b000000 ),
.in_burst (awfifo_out[47:46] ),
.in_push (aw_agen_write ),
.in_pop (aw_agen_pop ),
.in_user (1'b0 ),
.out_user ( ),
.out_addr (aw_agen_addr[15:0] ),
.out_id (aw_agen_id[15:0] ),
.out_be (aw_agen_be[C_S_AXI_DATA_WIDTH/8-1:0] ),
.out_done (aw_agen_done ),
.out_valid (aw_agen_valid )
);
wire slv_ex_agen_id_matches0 ;
wire slv_ex_clr_valid0 ;
wire slv_ex_valid0 ;
wire slv_ex_agen_id_matches1 ;
wire slv_ex_clr_valid1 ;
wire slv_ex_valid1 ;
generate if(C_NO_EXCL == 0 ) begin : S_W1_EXCL_0
assign slv_ex_agen_id_matches0 = (aw_agen_id[13:0] == slv_ex_info0_ff[69:56]);
assign slv_ex_clr_valid0 = aw_agen_valid &&
(aw_agen_addr[13:3] == slv_ex_info0_ff[13:3]) &&
~slv_ex_agen_id_matches0 && ~aw_agen_id[13];
// Don't clear if its from the ex master, or if the write is
// nullified (aw_agen_id[13]).
assign slv_ex_valid0 = (C_NO_EXCL) ? 1'b0 :
slv_ex_new_valid0 || (~slv_ex_clr_valid0 && slv_ex_valid0_ff);
assign slv_ex_agen_id_matches1 = (aw_agen_id[13:0] == slv_ex_info1_ff[69:56]);
assign slv_ex_clr_valid1 = aw_agen_valid &&
(aw_agen_addr[13:3] == slv_ex_info1_ff[13:3]) &&
~slv_ex_agen_id_matches1 && ~aw_agen_id[13];
// Don't clear if its from the ex master, or if the write is
// nullified (aw_agen_id[13]).
assign slv_ex_valid1 = (C_NO_EXCL) ? 1'b0 :
slv_ex_new_valid1 || (~slv_ex_clr_valid1 && slv_ex_valid1_ff);
end
endgenerate
generate if(C_NO_EXCL == 1 ) begin : S_W1_EXCL_1
assign slv_ex_valid0 = 1'b0 ;
assign slv_ex_valid1 = 1'b0 ;
end
endgenerate
// Buffer write data in a fifo
wire wbuf_valid = wvalid_s && wready_s;
wire wbuf_pop;
wire wfifo_notfull;
//wire wfifo_valid;
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (C_S_AXI_DATA_WIDTH*9/8+1),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.FULL_LEVEL(6 )
) Wfifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data({ wlast_s, wstrb_s[C_S_AXI_DATA_WIDTH/8-1:0],
wdata_s[C_S_AXI_DATA_WIDTH-1:0] }),
.in_push (wbuf_valid ),
.in_pop (wbuf_pop ),
.out_data (wfifo_out[C_S_AXI_DATA_WIDTH*9/8+1-1:0] ),
.is_full ( ),
.is_notfull (wfifo_notfull ),
.is_empty ( ),
.out_valid (wfifo_valid ),
.ex_fifo_dbgout ( )
);
assign wready_s = wfifo_notfull;
// Buffer bresps in fifos as well
wire [15:0] bbuf_id = aw_agen_id[15:0];
wire [1:0] bbuf_resp = aw_agen_id[15:14];
wire [19:0] bbuf_rawdata = {
bbuf_id[15:0], //19:4
2'b00, bbuf_resp[1:0] }; //3:0
wire [3:0] btrk_fifo_num, btrk_free;
wire bfifo0_pop, bfifo1_pop, bfifo2_pop, bfifo3_pop;
wire bfifo0_notfull, bfifo1_notfull, bfifo2_notfull, bfifo3_notfull;
wire bfifo0_valid, bfifo1_valid, bfifo2_valid, bfifo3_valid;
wire [19:0] bfifo0_out, bfifo1_out, bfifo2_out, bfifo3_out;
wire [C_S_AXI_ID_WIDTH-1:0] btrk_in_push_id = bbuf_rawdata[19:0];
wire [3:0] b_fifo_valid = { bfifo3_valid, bfifo2_valid,
bfifo1_valid, bfifo0_valid };
wire [3:0] b_fifo_push = ~b_fifo_valid[3:0] & btrk_fifo_num[3:0];
wire [3:0] btrk_clear_pos = ~b_fifo_valid[3:0];
wire btrk_push = aw_agen_pop && aw_agen_done;
wire [C_S_AXI_ID_WIDTH-1:0] dummy_search_id = 32'h0;
wire dis_dis_out_of_order;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_W_OOO_YES
assign dis_dis_out_of_order = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_W_OOO_NO
assign dis_dis_out_of_order = 1'b1;
end
endgenerate
axi_traffic_gen_v2_0_id_track #(
.ID_WIDTH(C_S_AXI_ID_WIDTH)
) B_track (
.Clk (Clk ),
.rst_l (rst_l ),
.in_push_id (btrk_in_push_id[C_S_AXI_ID_WIDTH-1:0]),
.in_push (btrk_push ),
.in_search_id (dummy_search_id[C_S_AXI_ID_WIDTH-1:0]),
.in_clear_pos (btrk_clear_pos[3:0] ),
.in_only_entry0(dis_dis_out_of_order ),
.out_push_pos (btrk_fifo_num[3:0] ),
.out_search_hit( ),
.out_free (btrk_free[3:0] )
);
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (20),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (0 ),
.FULL_LEVEL(6 )
) B_fifo0 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bbuf_rawdata[19:0]),
.in_push (btrk_fifo_num[0] ),
.in_pop (bfifo0_pop ),
.out_data (bfifo0_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo0_notfull ),
.is_empty ( ),
.out_valid (bfifo0_valid ),
.ex_fifo_dbgout ( )
);
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_W_OOO_F_NO
assign bfifo1_notfull = 1'b1;
assign bfifo1_valid = 1'b0;
assign bfifo2_notfull = 1'b1;
assign bfifo2_valid = 1'b0;
assign bfifo3_notfull = 1'b1;
assign bfifo3_valid = 1'b0;
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_W_OOO_F_YES
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (20),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (0 ),
.FULL_LEVEL(6 )
) B_fifo1 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bbuf_rawdata[19:0]),
.in_push (btrk_fifo_num[1] ),
.in_pop (bfifo1_pop ),
.out_data (bfifo1_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo1_notfull ),
.is_empty ( ),
.out_valid (bfifo1_valid ),
.ex_fifo_dbgout ( )
);
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (20),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (0 ),
.FULL_LEVEL(6 )
) B_fifo2 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bbuf_rawdata[19:0]),
.in_push (btrk_fifo_num[2] ),
.in_pop (bfifo2_pop ),
.out_data (bfifo2_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo2_notfull ),
.is_empty ( ),
.out_valid (bfifo2_valid ),
.ex_fifo_dbgout ( )
);
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (20),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (0 ),
.FULL_LEVEL(6 )
) B_fifo3 (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bbuf_rawdata[19:0]),
.in_push (btrk_fifo_num[3] ),
.in_pop (bfifo3_pop ),
.out_data (bfifo3_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo3_notfull ),
.is_empty ( ),
.out_valid (bfifo3_valid ),
.ex_fifo_dbgout ( )
);
end
endgenerate
wire [19:0] bfifo_out;
wire bfifo_valid;
wire bfifo_notfull;
wire [3:0] bfifo_sel = (bfifo3_valid) ? 4'h8 :
(bfifo2_valid) ? 4'h4 :
(bfifo1_valid) ? 4'h2 :
(bfifo0_valid) ? 4'h1 : 4'h0;
assign bfifo0_pop = bfifo_notfull && bfifo_sel[0];
assign bfifo1_pop = bfifo_notfull && bfifo_sel[1];
assign bfifo2_pop = bfifo_notfull && bfifo_sel[2];
assign bfifo3_pop = bfifo_notfull && bfifo_sel[3];
wire [19:0] bfifo_in_data ;
generate if(C_ATG_BASIC_AXI4 == 0) begin : ATG_S_W1_OOO_YES
assign bfifo_in_data = ((bfifo_sel[0]) ? bfifo0_out[19:0] : 20'h0) |
((bfifo_sel[1]) ? bfifo1_out[19:0] : 20'h0) |
((bfifo_sel[2]) ? bfifo2_out[19:0] : 20'h0) |
((bfifo_sel[3]) ? bfifo3_out[19:0] : 20'h0);
end
endgenerate
generate if(C_ATG_BASIC_AXI4 == 1) begin : ATG_S_W1_OOO_NO
assign bfifo_in_data = ((bfifo_sel[0]) ? bfifo0_out[19:0] : 20'h0) ;
end
endgenerate
wire bfifo_pop = bfifo_valid && bready_s;
wire bfifo_push = bfifo_notfull && (bfifo_sel[3:0] != 4'h0);
axi_traffic_gen_v2_0_ex_fifo #(
.WIDTH (20 ),
.DEPTH (8 ),
.DEPTHBITS (3 ),
.HEADREG (1 ),
.ZERO_INVALID(C_ZERO_INVALID),
.FULL_LEVEL (6 )
) Bfifo (
.Clk (Clk ),
.rst_l (rst_l ),
.in_data (bfifo_in_data[19:0]),
.in_push (bfifo_push ),
.in_pop (bfifo_pop ),
.out_data (bfifo_out[19:0] ),
.is_full ( ),
.is_notfull (bfifo_notfull ),
.is_empty ( ),
.out_valid (bfifo_valid ),
.ex_fifo_dbgout ( )
);
assign wbuf_pop = wfifo_valid && aw_agen_valid &&
bfifo0_notfull && bfifo1_notfull && bfifo2_notfull &&
bfifo3_notfull && (btrk_free[3:0] != 4'h0);
assign aw_agen_pop = wbuf_pop;
wire wfifo_bad_last = wbuf_pop && (aw_agen_done != wfifo_out[C_S_AXI_DATA_WIDTH*9/8]);
wire [C_S_AXI_DATA_WIDTH/8-1:0] wfifo_out_be =
wfifo_out[C_S_AXI_DATA_WIDTH*9/8-1:C_S_AXI_DATA_WIDTH];
wire wfifo_bad_be_pre = (~aw_agen_be[C_S_AXI_DATA_WIDTH/8-1:0] &
wfifo_out_be[C_S_AXI_DATA_WIDTH/8-1:0]) != 8'h0;
wire wfifo_bad_be = wbuf_pop && wfifo_bad_be_pre;
assign bresp_s[1:0] = bfifo_out[1:0];
assign bid_s[C_S_AXI_ID_WIDTH-1:0] = bfifo_out[19:4];
assign bvalid_s = bfifo_valid;
wire slv_wr_pending = awfifo_valid || aw_agen_valid;
always @(posedge Clk) begin
slv_ex_valid0_ff <= (rst_l) ? slv_ex_valid0 : 1'b0;
slv_ex_valid1_ff <= (rst_l) ? slv_ex_valid1 : 1'b0;
end
//register interface information
wire wr_reg_isreg = (aw_agen_addr[15:14] == 2'b00) && aw_agen_pop &&
~aw_agen_addr[7]
&& ~aw_agen_addr[12]; // adding this for special_queue
assign wr_reg_decode = { 15'h0, wr_reg_isreg } << aw_agen_addr[5:2];
wire [11:0] wr_reg_shift = (C_S_AXI_DATA_WIDTH == 32) ? 12'h0 :
(C_S_AXI_DATA_WIDTH == 64) ? { 6'h0, aw_agen_addr[2], 5'h0 } :
(C_S_AXI_DATA_WIDTH == 128) ? { 5'h0, aw_agen_addr[3:2], 5'h0 }:
{ 4'h0, aw_agen_addr[4:2], 5'h0 };
assign wr_reg_data = wfifo_out[C_S_AXI_DATA_WIDTH-1:0] >>
wr_reg_shift[11:0];
//slv/mst ram decode
wire slvram_do_write = wbuf_pop && aw_agen_addr[15] && ~aw_agen_id[13];
wire [7:0] slvram_we = (slvram_do_write) ?
{4'h0,wfifo_out_be[C_S_AXI_DATA_WIDTH/8-1:0]} : 'h0;
assign slvram_wr_data = (C_S_AXI_DATA_WIDTH == 64) ? wfifo_out[C_S_AXI_DATA_WIDTH-1:0] :
{2{wfifo_out[C_S_AXI_DATA_WIDTH-1:0]}};
wire [63:0] slvram_rd_out_pre;
assign slvram_rd_out_pre[63:0] = sram_rd_data_a;
reg [63:0] slvram_wr_data64_ff;
reg [7:0] slvram_rdwr_mask8_ff;
reg [C_S_AXI_DATA_WIDTH-1:0] slvram_wr_datareg_ff;
reg [31:0] slvram_rdwr_mask_ff;
wire [13:0] rdwr_match_mask =
(C_S_AXI_DATA_WIDTH == 256) ? 14'h3fe0 :
(C_S_AXI_DATA_WIDTH == 128) ? 14'h1ff0 :
(C_S_AXI_DATA_WIDTH == 64) ? 14'h1ffe : 14'h1ffc;
wire slvram_rdwr_match = slvram_do_write &&
((ar_agen_addr[13:0] & rdwr_match_mask[13:0]) ==
(aw_agen_addr[13:0] & rdwr_match_mask[13:0]));
wire [C_S_AXI_DATA_WIDTH-1:0] slvram_wr_datareg = (slvram_rdwr_match) ?
slvram_wr_data[C_S_AXI_DATA_WIDTH-1:0] :
slvram_wr_datareg_ff[C_S_AXI_DATA_WIDTH-1:0];
wire [31:0] slvram_rdwr_mask = (slvram_rdwr_match) ?
wfifo_out_be[C_S_AXI_DATA_WIDTH/8-1:0] : 'h0;
wire [C_S_AXI_DATA_WIDTH-1:0] slvram_rdwr_mask_exp = {
{ 8 { slvram_rdwr_mask_ff[31] } }, { 8 { slvram_rdwr_mask_ff[30] } },
{ 8 { slvram_rdwr_mask_ff[29] } }, { 8 { slvram_rdwr_mask_ff[28] } },
{ 8 { slvram_rdwr_mask_ff[27] } }, { 8 { slvram_rdwr_mask_ff[26] } },
{ 8 { slvram_rdwr_mask_ff[25] } }, { 8 { slvram_rdwr_mask_ff[24] } },
{ 8 { slvram_rdwr_mask_ff[23] } }, { 8 { slvram_rdwr_mask_ff[22] } },
{ 8 { slvram_rdwr_mask_ff[21] } }, { 8 { slvram_rdwr_mask_ff[20] } },
{ 8 { slvram_rdwr_mask_ff[19] } }, { 8 { slvram_rdwr_mask_ff[18] } },
{ 8 { slvram_rdwr_mask_ff[17] } }, { 8 { slvram_rdwr_mask_ff[16] } },
{ 8 { slvram_rdwr_mask_ff[15] } }, { 8 { slvram_rdwr_mask_ff[14] } },
{ 8 { slvram_rdwr_mask_ff[13] } }, { 8 { slvram_rdwr_mask_ff[12] } },
{ 8 { slvram_rdwr_mask_ff[11] } }, { 8 { slvram_rdwr_mask_ff[10] } },
{ 8 { slvram_rdwr_mask_ff[9] } }, { 8 { slvram_rdwr_mask_ff[8] } },
{ 8 { slvram_rdwr_mask_ff[7] } }, { 8 { slvram_rdwr_mask_ff[6] } },
{ 8 { slvram_rdwr_mask_ff[5] } }, { 8 { slvram_rdwr_mask_ff[4] } },
{ 8 { slvram_rdwr_mask_ff[3] } }, { 8 { slvram_rdwr_mask_ff[2] } },
{ 8 { slvram_rdwr_mask_ff[1] } }, { 8 { slvram_rdwr_mask_ff[0] } } };
assign slvram_rd_out[C_S_AXI_DATA_WIDTH-1:0] =
(slvram_rdwr_mask_exp[C_S_AXI_DATA_WIDTH-1:0] &
slvram_wr_datareg_ff[C_S_AXI_DATA_WIDTH-1:0]) |
(~slvram_rdwr_mask_exp[C_S_AXI_DATA_WIDTH-1:0] &
slvram_rd_out_pre[C_S_AXI_DATA_WIDTH-1:0]);
always @(posedge Clk) begin
slvram_wr_datareg_ff[C_S_AXI_DATA_WIDTH-1:0] <= (rst_l) ?
slvram_wr_datareg[C_S_AXI_DATA_WIDTH-1:0] : 'h0;
slvram_rdwr_mask_ff[31:0] <= (rst_l) ? slvram_rdwr_mask[31:0] : 32'h0;
end
assign err_new_slv[15:0] = { 14'h0, wfifo_bad_be, wfifo_bad_last };
// adding sram regslice for timing closure
wire [82:0] sram_slvramwr_ff;
axi_traffic_gen_v2_0_regslice
#(
.DWIDTH (83),
.IDWIDTH (1) ,
.DATADEPTH(1 )
)
sram_slvramwr_regslice
(
.din ({aw_agen_addr[12:2],slvram_we,slvram_wr_data}),
.dout (sram_slvramwr_ff ),
.dout_early ( ),
.idin (1'b0 ),
.idout ( ),
.id_stable ( ),
.id_stable_ff( ),
.data_stable ( ),
.clk (Clk ),
.reset (~rst_l )
);
assign slvram_waddr_ff = sram_slvramwr_ff[82:72];
assign slvram_we_ff = sram_slvramwr_ff[71:64];
assign slvram_write_data_ff = sram_slvramwr_ff[63:0];
//cmdram decode
// sent out aw_agen_addr as output also.
// this is used along with ar_agen0_addr,maw_ptr_new,mar_ptr_new
// to select address to cmdram based on reg0_m_enable_ff
wire [31:0] cmdram_we32 = wfifo_out_be[C_S_AXI_DATA_WIDTH/8-1:0];
wire [3:0] cmdram_we4 ;
wire [7:0] cmdram_we8 ;
wire [7:0] cmdram_we_pre ;
generate if(C_S_AXI_DATA_WIDTH == 32) begin :CMD_WE_32
assign cmdram_we4 = cmdram_we32[31:28] | cmdram_we32[27:24] |
cmdram_we32[23:20] | cmdram_we32[19:16] |
cmdram_we32[15:12] | cmdram_we32[11:8] |
cmdram_we32[7:4] | cmdram_we32[3:0];
assign cmdram_we_pre = (wbuf_pop && aw_agen_addr[14]) ? cmdram_we4[3:0] :
4'h0;
assign cmdram_we =
(aw_agen_addr[3:2] == 2'b11) ? { cmdram_we_pre[3:0], 12'h0 } :
(aw_agen_addr[3:2] == 2'b10) ? { 4'h0, cmdram_we_pre[3:0], 8'h0 } :
(aw_agen_addr[3:2] == 2'b01) ? { 8'h0, cmdram_we_pre[3:0], 4'h0 } :
{ 12'h0, cmdram_we_pre[3:0] };
end
endgenerate
generate if(C_S_AXI_DATA_WIDTH == 64) begin :CMD_WE_64
assign cmdram_we8 = cmdram_we32[31:24] |
cmdram_we32[23:16] |
cmdram_we32[15:8] |
cmdram_we32[7:0] ;
assign cmdram_we_pre = (wbuf_pop && aw_agen_addr[14]) ? cmdram_we8[7:0] :
8'h0;
assign cmdram_we =
(aw_agen_addr[3] == 1'b1) ? { cmdram_we_pre[7:0], 8'h0 } :
{ 8'h0, cmdram_we_pre[7:0] };
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o31a (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31A_BEHAVIORAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: pcx_buf_pdl_even.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module pcx_buf_pdl_even(/*AUTOARG*/
// Outputs
arbpc0_pcxdp_grant_pa, arbpc0_pcxdp_q0_hold_pa_l,
arbpc0_pcxdp_qsel0_pa, arbpc0_pcxdp_qsel1_pa_l,
arbpc0_pcxdp_shift_px, arbpc2_pcxdp_grant_pa,
arbpc2_pcxdp_q0_hold_pa_l, arbpc2_pcxdp_qsel0_pa,
arbpc2_pcxdp_qsel1_pa_l, arbpc2_pcxdp_shift_px,
// Inputs
arbpc0_pcxdp_grant_bufp1_pa_l, arbpc0_pcxdp_q0_hold_bufp1_pa,
arbpc0_pcxdp_qsel0_bufp1_pa_l, arbpc0_pcxdp_qsel1_bufp1_pa,
arbpc0_pcxdp_shift_bufp1_px_l, arbpc2_pcxdp_grant_bufp1_pa_l,
arbpc2_pcxdp_q0_hold_bufp1_pa, arbpc2_pcxdp_qsel0_bufp1_pa_l,
arbpc2_pcxdp_qsel1_bufp1_pa, arbpc2_pcxdp_shift_bufp1_px_l
);
output arbpc0_pcxdp_grant_pa ;
output arbpc0_pcxdp_q0_hold_pa_l ;
output arbpc0_pcxdp_qsel0_pa ;
output arbpc0_pcxdp_qsel1_pa_l ;
output arbpc0_pcxdp_shift_px ;
output arbpc2_pcxdp_grant_pa ;
output arbpc2_pcxdp_q0_hold_pa_l ;
output arbpc2_pcxdp_qsel0_pa ;
output arbpc2_pcxdp_qsel1_pa_l ;
output arbpc2_pcxdp_shift_px ;
input arbpc0_pcxdp_grant_bufp1_pa_l;
input arbpc0_pcxdp_q0_hold_bufp1_pa;
input arbpc0_pcxdp_qsel0_bufp1_pa_l;
input arbpc0_pcxdp_qsel1_bufp1_pa;
input arbpc0_pcxdp_shift_bufp1_px_l;
input arbpc2_pcxdp_grant_bufp1_pa_l;
input arbpc2_pcxdp_q0_hold_bufp1_pa;
input arbpc2_pcxdp_qsel0_bufp1_pa_l;
input arbpc2_pcxdp_qsel1_bufp1_pa;
input arbpc2_pcxdp_shift_bufp1_px_l;
assign arbpc0_pcxdp_grant_pa = ~arbpc0_pcxdp_grant_bufp1_pa_l;
assign arbpc0_pcxdp_q0_hold_pa_l = ~arbpc0_pcxdp_q0_hold_bufp1_pa;
assign arbpc0_pcxdp_qsel0_pa = ~arbpc0_pcxdp_qsel0_bufp1_pa_l;
assign arbpc0_pcxdp_qsel1_pa_l = ~arbpc0_pcxdp_qsel1_bufp1_pa;
assign arbpc0_pcxdp_shift_px = ~arbpc0_pcxdp_shift_bufp1_px_l;
assign arbpc2_pcxdp_grant_pa = ~arbpc2_pcxdp_grant_bufp1_pa_l;
assign arbpc2_pcxdp_q0_hold_pa_l = ~arbpc2_pcxdp_q0_hold_bufp1_pa;
assign arbpc2_pcxdp_qsel0_pa = ~arbpc2_pcxdp_qsel0_bufp1_pa_l;
assign arbpc2_pcxdp_qsel1_pa_l = ~arbpc2_pcxdp_qsel1_bufp1_pa;
assign arbpc2_pcxdp_shift_px = ~arbpc2_pcxdp_shift_bufp1_px_l;
endmodule
|
/****************************************
Decode Unit
****************************************/
`include "core.h"
`default_nettype none
module decoder(
//System
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Free
input wire iEVENT_START,
//Previous
input wire iPREVIOUS_INST_VALID,
input wire iPREVIOUS_FAULT_PAGEFAULT,
input wire iPREVIOUS_FAULT_PRIVILEGE_ERROR,
input wire iPREVIOUS_FAULT_INVALID_INST,
input wire iPREVIOUS_PAGING_ENA,
input wire iPREVIOUS_KERNEL_ACCESS,
input wire iPREVIOUS_BRANCH_PREDICT,
input wire [31:0] iPREVIOUS_BRANCH_PREDICT_ADDR,
input wire [31:0] iPREVIOUS_INST,
input wire [31:0] iPREVIOUS_PC,
output wire oPREVIOUS_LOCK,
//Next-0
output wire oNEXT_VALID,
output wire oNEXT_FAULT_PAGEFAULT,
output wire oNEXT_FAULT_PRIVILEGE_ERROR,
output wire oNEXT_FAULT_INVALID_INST,
output wire oNEXT_PAGING_ENA,
output wire oNEXT_KERNEL_ACCESS,
output wire oNEXT_BRANCH_PREDICT,
output wire [31:0] oNEXT_BRANCH_PREDICT_ADDR,
output wire oNEXT_SOURCE0_ACTIVE,
output wire oNEXT_SOURCE1_ACTIVE,
output wire oNEXT_SOURCE0_SYSREG,
output wire oNEXT_SOURCE1_SYSREG,
output wire oNEXT_SOURCE0_SYSREG_RENAME,
output wire oNEXT_SOURCE1_SYSREG_RENAME,
output wire oNEXT_ADV_ACTIVE, //++
output wire oNEXT_DESTINATION_SYSREG,
output wire oNEXT_DEST_RENAME,
output wire oNEXT_WRITEBACK,
output wire oNEXT_FLAGS_WRITEBACK,
output wire oNEXT_FRONT_COMMIT_WAIT,
output wire [4:0] oNEXT_CMD,
output wire [3:0] oNEXT_CC_AFE,
output wire [4:0] oNEXT_SOURCE0,
output wire [31:0] oNEXT_SOURCE1,
output wire [5:0] oNEXT_ADV_DATA, //++
output wire oNEXT_SOURCE0_FLAGS,
output wire oNEXT_SOURCE1_IMM,
output wire [4:0] oNEXT_DESTINATION,
output wire oNEXT_EX_SYS_REG,
output wire oNEXT_EX_SYS_LDST,
output wire oNEXT_EX_LOGIC,
output wire oNEXT_EX_SHIFT,
output wire oNEXT_EX_ADDER,
output wire oNEXT_EX_MUL,
output wire oNEXT_EX_SDIV,
output wire oNEXT_EX_UDIV,
output wire oNEXT_EX_LDST,
output wire oNEXT_EX_BRANCH,
output wire [31:0] oNEXT_PC,
input wire iNEXT_LOCK
);
/****************************************
Decode Function Module
****************************************/
wire decode_source0_active;
wire decode_source1_active;
wire decode_source0_sysreg;
wire decode_source1_sysreg;
wire decode_source0_sysreg_rename;
wire decode_source1_sysreg_rename;
wire decode_adv_active;
wire decode_destination_sysreg;
wire decode_dest_rename;
wire decode_writeback;
wire decode_flags_writeback;
wire decode_front_commit_wait;
wire [4:0] decode_cmd;
wire [3:0] decode_cc_afe;
wire [4:0] decode_source0;
wire [31:0] decode_source1;
wire [5:0] decode_adv_data;
wire decode_source0_flags;
wire decode_source1_imm;
wire [4:0] decode_destination;
wire decode_ex_sys_reg;
wire decode_ex_sys_ldst;
wire decode_ex_logic;
wire decode_ex_shift;
wire decode_ex_adder;
wire decode_ex_mul;
wire decode_ex_sdiv;
wire decode_ex_udiv;
wire decode_ex_ldst;
wire decode_ex_branch;
decode_function DECODE_FUNCTION(
//Input
.iINSTLUCTION(iPREVIOUS_INST),
//Info
//.oINF_ERROR(),
//Decode
.oDECODE_SOURCE0_ACTIVE(decode_source0_active),
.oDECODE_SOURCE1_ACTIVE(decode_source1_active),
.oDECODE_SOURCE0_SYSREG(decode_source0_sysreg),
.oDECODE_SOURCE1_SYSREG(decode_source1_sysreg),
.oDECODE_SOURCE0_SYSREG_RENAME(decode_source0_sysreg_rename),
.oDECODE_SOURCE1_SYSREG_RENAME(decode_source1_sysreg_rename),
.oDECODE_ADV_ACTIVE(decode_adv_active),
.oDECODE_DESTINATION_SYSREG(decode_destination_sysreg),
.oDECODE_DEST_RENAME(decode_dest_rename),
.oDECODE_WRITEBACK(decode_writeback),
.oDECODE_FLAGS_WRITEBACK(decode_flags_writeback),
.oDECODE_FRONT_COMMIT_WAIT(decode_front_commit_wait), //???
.oDECODE_CMD(decode_cmd),
.oDECODE_CC_AFE(decode_cc_afe),
.oDECODE_SOURCE0(decode_source0),
.oDECODE_SOURCE1(decode_source1),
.oDECODE_ADV_DATA(decode_adv_data),
.oDECODE_SOURCE0_FLAGS(decode_source0_flags),
.oDECODE_SOURCE1_IMM(decode_source1_imm),
.oDECODE_DESTINATION(decode_destination),
.oDECODE_EX_SYS_REG(decode_ex_sys_reg),
.oDECODE_EX_SYS_LDST(decode_ex_sys_ldst),
.oDECODE_EX_LOGIC(decode_ex_logic),
.oDECODE_EX_SHIFT(decode_ex_shift),
.oDECODE_EX_ADDER(decode_ex_adder),
.oDECODE_EX_MUL(decode_ex_mul),
.oDECODE_EX_SDIV(decode_ex_sdiv),
.oDECODE_EX_UDIV(decode_ex_udiv),
.oDECODE_EX_LDST(decode_ex_ldst),
.oDECODE_EX_BRANCH(decode_ex_branch)
);
//Pipeline
reg b_valid;
reg b_fault_pagefault;
reg b_fault_page_privilege_error;
reg b_fault_page_invalid_inst;
reg b_paging_ena;
reg b_kernel_access;
reg b_branch_predict;
reg [31:0] b_branch_predict_addr;
reg [13:0] b_mmu_flags;
reg b_destination_sysreg;
reg b_dest_rename;
reg b_writeback;
reg b_flag_writeback;
reg b_commit_wait_inst;
reg [4:0] b_cmd;
reg [3:0] b_cc_afe;
reg [4:0] b_source0;
reg [31:0] b_source1;
reg b_source0_flags;
reg b_source1_imm;
reg b_source0_active;
reg b_source1_active;
reg b_source0_sysreg;
reg b_source1_sysreg;
reg b_source0_sysreg_rename;
reg b_source1_sysreg_rename;
reg [5:0] b_adv_data;
reg b_adv_active;
reg [4:0] b_destination;
reg b_ex_sys_reg;
reg b_ex_sys_ldst;
reg b_ex_logic;
reg b_ex_shift;
reg b_ex_adder;
reg b_ex_mul;
reg b_ex_sdiv;
reg b_ex_udiv;
reg b_ex_ldst;
reg b_ex_branch;
reg b_error;
reg [31:0] b_pc;
always@(posedge iCLOCK, negedge inRESET)begin
if(!inRESET)begin
b_valid <= 1'b0;
b_fault_pagefault <= 1'b0;
b_fault_page_privilege_error <= 1'b0;
b_fault_page_invalid_inst <= 1'b0;
b_paging_ena <= 1'b0;
b_kernel_access <= 1'b0;
b_branch_predict <= 1'b0;
b_branch_predict_addr <= 32'h0;
b_source0_active <= 1'b0;
b_source1_active <= 1'b0;
b_source0_sysreg <= 1'b0;
b_source1_sysreg <= 1'b0;
b_source0_sysreg_rename <= 1'b0;
b_source1_sysreg_rename <= 1'b0;
b_adv_data <= 6'h0;
b_adv_active <= 1'b0;
b_destination_sysreg <= 1'b0;
b_dest_rename <= 1'b0;
b_writeback <= 1'b0;
b_flag_writeback <= 1'b0;
b_commit_wait_inst <= 1'b0;
b_cmd <= {5{1'b0}};
b_cc_afe <= {4{1'b0}};
b_source0 <= {5{1'b0}};
b_source1 <= {32{1'b0}};
b_source0_flags <= 1'b0;
b_source1_imm <= 1'b0;
b_destination <= {5{1'b0}};
b_ex_sys_reg <= 1'b0;
b_ex_sys_ldst <= 1'b0;
b_ex_logic <= 1'b0;
b_ex_shift <= 1'b0;
b_ex_adder <= 1'b0;
b_ex_mul <= 1'b0;
b_ex_sdiv <= 1'b0;
b_ex_udiv <= 1'b0;
b_ex_ldst <= 1'b0;
b_ex_branch <= 1'b0;
b_error <= 1'b0;
b_pc <= 32'h0;
end
else if(iRESET_SYNC || iEVENT_START)begin
b_valid <= 1'b0;
b_fault_pagefault <= 1'b0;
b_fault_page_privilege_error <= 1'b0;
b_fault_page_invalid_inst <= 1'b0;
b_paging_ena <= 1'b0;
b_kernel_access <= 1'b0;
b_branch_predict <= 1'b0;
b_branch_predict_addr <= 32'h0;
b_source0_active <= 1'b0;
b_source1_active <= 1'b0;
b_source0_sysreg <= 1'b0;
b_source1_sysreg <= 1'b0;
b_source0_sysreg_rename <= 1'b0;
b_source1_sysreg_rename <= 1'b0;
b_adv_data <= 6'h0;
b_adv_active <= 1'b0;
b_destination_sysreg <= 1'b0;
b_dest_rename <= 1'b0;
b_writeback <= 1'b0;
b_flag_writeback <= 1'b0;
b_commit_wait_inst <= 1'b0;
b_cmd <= {5{1'b0}};
b_cc_afe <= {4{1'b0}};
b_source0 <= {5{1'b0}};
b_source1 <= {32{1'b0}};
b_source0_flags <= 1'b0;
b_source1_imm <= 1'b0;
b_destination <= {5{1'b0}};
b_ex_sys_reg <= 1'b0;
b_ex_sys_ldst <= 1'b0;
b_ex_logic <= 1'b0;
b_ex_shift <= 1'b0;
b_ex_adder <= 1'b0;
b_ex_mul <= 1'b0;
b_ex_sdiv <= 1'b0;
b_ex_udiv <= 1'b0;
b_ex_ldst <= 1'b0;
b_ex_branch <= 1'b0;
b_error <= 1'b0;
b_pc <= 32'h0;
end
else begin
if(!iNEXT_LOCK)begin
//Pipeline 1
b_valid <= iPREVIOUS_INST_VALID;
//Flag
b_fault_pagefault <= iPREVIOUS_FAULT_PAGEFAULT;
b_fault_page_privilege_error <= iPREVIOUS_FAULT_PRIVILEGE_ERROR;
b_fault_page_invalid_inst <= iPREVIOUS_FAULT_INVALID_INST;
b_paging_ena <= iPREVIOUS_PAGING_ENA;
b_kernel_access <= iPREVIOUS_KERNEL_ACCESS;
b_branch_predict <= iPREVIOUS_BRANCH_PREDICT;
b_branch_predict_addr <= iPREVIOUS_BRANCH_PREDICT_ADDR;
//Inst
/*{
b_error, b_commit_wait_inst, b_cc_afe,
b_source0, b_source1, b_source0_flags, b_source1_imm,
b_source0_active, b_source1_active,
b_source0_sysreg, b_source1_sysreg,
b_source0_sysreg_rename, b_source1_sysreg_rename,
b_adv_data, b_adv_active,
b_destination, b_writeback, b_flag_writeback,
b_destination_sysreg, b_dest_rename, b_cmd, b_ex_sys_reg, b_ex_sys_ldst,
b_ex_logic, b_ex_shift, b_ex_adder, b_ex_sdiv,
b_ex_udiv, b_ex_mul, b_ex_ldst, b_ex_branch
} <= f_decode(iPREVIOUS_INST);
*/
b_source0_active <= decode_source0_active;
b_source1_active <= decode_source1_active;
b_source0_sysreg <= decode_source0_sysreg;
b_source1_sysreg <= decode_source1_sysreg;
b_source0_sysreg_rename <= decode_source0_sysreg_rename;
b_source1_sysreg_rename <= decode_source1_sysreg_rename;
b_adv_data <= decode_adv_data;
b_adv_active <= decode_adv_active;
b_destination_sysreg <= decode_destination_sysreg;
b_dest_rename <= decode_dest_rename;
b_writeback <= decode_writeback;
b_flag_writeback <= decode_flags_writeback;
b_commit_wait_inst <= decode_front_commit_wait;
b_cmd <= decode_cmd;
b_cc_afe <= decode_cc_afe;
b_source0 <= decode_source0;
b_source1 <= decode_source1;
b_source0_flags <= decode_source0_flags;
b_source1_imm <= decode_source1_imm;
b_destination <= decode_destination;
b_ex_sys_reg <= decode_ex_sys_reg;
b_ex_sys_ldst <= decode_ex_sys_ldst;
b_ex_logic <= decode_ex_logic;
b_ex_shift <= decode_ex_shift;
b_ex_adder <= decode_ex_adder;
b_ex_mul <= decode_ex_mul;
b_ex_sdiv <= decode_ex_sdiv;
b_ex_udiv <= decode_ex_udiv;
b_ex_ldst <= decode_ex_ldst;
b_ex_branch <= decode_ex_branch;
b_error <= 1'b0;
//Program Counter
b_pc <= iPREVIOUS_PC;
end
end
end //always
/****************************************
This -> Previous
****************************************/
assign oPREVIOUS_LOCK = iNEXT_LOCK;
/****************************************
This -> Next
****************************************/
//Pipeline1
assign oNEXT_VALID = b_valid;
assign oNEXT_FAULT_PAGEFAULT = b_fault_pagefault;
assign oNEXT_FAULT_PRIVILEGE_ERROR = b_fault_page_privilege_error;
assign oNEXT_FAULT_INVALID_INST = b_fault_page_invalid_inst;
assign oNEXT_PAGING_ENA = b_paging_ena;
assign oNEXT_KERNEL_ACCESS = b_kernel_access;
assign oNEXT_BRANCH_PREDICT = b_branch_predict;
assign oNEXT_BRANCH_PREDICT_ADDR = b_branch_predict_addr;
assign oNEXT_SOURCE0_ACTIVE = b_source0_active;
assign oNEXT_SOURCE1_ACTIVE = b_source1_active;
assign oNEXT_SOURCE0_SYSREG = b_source0_sysreg;
assign oNEXT_SOURCE1_SYSREG = b_source1_sysreg;
assign oNEXT_SOURCE0_SYSREG_RENAME = b_source0_sysreg_rename;
assign oNEXT_SOURCE1_SYSREG_RENAME = b_source1_sysreg_rename;
assign oNEXT_ADV_DATA = b_adv_data;
assign oNEXT_ADV_ACTIVE = b_adv_active;
assign oNEXT_DESTINATION_SYSREG = b_destination_sysreg;
assign oNEXT_DEST_RENAME = b_dest_rename;
assign oNEXT_WRITEBACK = b_writeback;
assign oNEXT_FLAGS_WRITEBACK = b_flag_writeback;
assign oNEXT_FRONT_COMMIT_WAIT = b_commit_wait_inst;
assign oNEXT_CMD = b_cmd;
assign oNEXT_CC_AFE = b_cc_afe;
assign oNEXT_SOURCE0 = b_source0;
assign oNEXT_SOURCE1 = b_source1;
assign oNEXT_SOURCE0_FLAGS = b_source0_flags;
assign oNEXT_SOURCE1_IMM = b_source1_imm;
assign oNEXT_DESTINATION = b_destination;
assign oNEXT_EX_SYS_REG = b_ex_sys_reg;
assign oNEXT_EX_SYS_LDST = b_ex_sys_ldst;
assign oNEXT_EX_LOGIC = b_ex_logic;
assign oNEXT_EX_SHIFT = b_ex_shift;
assign oNEXT_EX_ADDER = b_ex_adder;
assign oNEXT_EX_MUL = b_ex_mul;
assign oNEXT_EX_SDIV = b_ex_sdiv;
assign oNEXT_EX_UDIV = b_ex_udiv;
assign oNEXT_EX_LDST = b_ex_ldst;
assign oNEXT_EX_BRANCH = b_ex_branch;
assign oNEXT_PC = b_pc;
endmodule
`default_nettype wire
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [4095:0] crc;
// Test loop
always @ (posedge clk) begin
cyc <= cyc + 1;
crc <= {crc[4094:0], crc[63]^crc[2]^crc[0]}; // not a good crc :)
if (cyc==0) begin
// Setup
crc <= 4096'h9f51804b5275c7b6ab9907144a58649bb778f9718062fa5c336fcc9edcad7cf17aad0a656244017bb21d9f97f7c0c147b6fa7488bb9d5bb8d3635b20fba1deab597121c502b21f49b18da998852d29a6b2b649315a3323a31e7e5f41e9bbb7e44046467438f37694857b963250bdb137a922cfce2af1defd1f93db5aa167f316d751bb274bda96fdee5e2c6eb21886633246b165341f0594c27697b06b62b1ad05ebe3c08909a54272de651296dcdd3d1774fc432d22210d8f6afa50b02cf23336f8cc3a0a2ebfd1a3a60366a1b66ef346e0379116d68caa01279ac2772d1f3cd76d2cbbc68ada6f83ec2441b2679b405486df8aa734ea1729b40c3f82210e8e42823eb3fd6ca77ee19f285741c4e8bac1ab7855c3138e84b6da1d897bbe37faf2d0256ad2f7ff9e704a63d824c1e97bddce990cae1578f9537ae2328d0afd69ffb317cbcf859696736e45e5c628b44727557c535a7d02c07907f2dccd6a21ca9ae9e1dbb1a135a8ebc2e0aa8c7329b898d02896273defe21beaa348e11165b71c48cf1c09714942a5a2ddc2adcb6e42c0f630117ee21205677d5128e8efc18c9a6f82a8475541fd722cca2dd829b7e78fef89dbeab63ab7b849910eb4fe675656c4b42b9452c81a4ca6296190a81dc63e6adfaa31995d7dfe3438ee9df66488d6cf569380569ffe6e5ea313d23af6ff08d979af29374ee9aff1fa143df238a1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x%x%x%x\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
$write("[%0t] cyc==%0d crc=%b%b%b%b\n",$time, cyc, crc[4095:3072], crc[2071:2048], crc[2047:1024], crc[1023:0]);
//Unsupported: $write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
if (crc != 4096'h2961926edde3e5c6018be970cdbf327b72b5f3c5eab42995891005eec8767e5fdf03051edbe9d222ee756ee34d8d6c83ee877aad65c487140ac87d26c636a66214b4a69acad924c568cc8e8c79f97d07a6eedf91011919d0e3cdda5215ee58c942f6c4dea48b3f38abc77bf47e4f6d6a859fcc5b5d46ec9d2f6a5bf7b978b1bac862198cc91ac594d07c165309da5ec1ad8ac6b417af8f0224269509cb79944a5b7374f45dd3f10cb48884363dabe942c0b3c8ccdbe330e828baff468e980d9a86d9bbcd1b80de445b5a32a8049e6b09dcb47cf35db4b2ef1a2b69be0fb09106c99e6d01521b7e2a9cd3a85ca6d030fe08843a390a08facff5b29dfb867ca15d0713a2eb06ade1570c4e3a12db687625eef8dfebcb4095ab4bdffe79c1298f609307a5ef773a6432b855e3e54deb88ca342bf5a7fecc5f2f3e165a59cdb9179718a2d11c9d55f14d69f40b01e41fcb7335a8872a6ba7876ec684d6a3af0b82aa31cca6e26340a2589cf7bf886faa8d23844596dc71233c7025c5250a968b770ab72db90b03d8c045fb8848159df544a3a3bf063269be0aa11d5507f5c8b328b760a6df9e3fbe276faad8eadee126443ad3f99d595b12d0ae514b20693298a58642a07718f9ab7ea8c66575f7f8d0e3ba77d992235b3d5a4e015a7ff9b97a8c4f48ebdbfc2365e6bca4dd3ba6bfc7e850f7c8e2842c717a1d85a977a033f564fc
) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*
* This demonstrates a basic dynamic array
*/
module main;
shortint foo[];
int idx;
initial begin
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d, s.b. 0", foo.size());
$finish;
end
foo = new[10];
if (foo.size() != 10) begin
$display("FAILED -- foo.size()=%0d, s.b. 10", foo.size());
$finish;
end
for (idx = 0 ; idx < foo.size() ; idx += 1) begin
foo[idx] = idx;
end
$display("foo[7] = %d", foo[7]);
if (foo[7] != 7) begin
$display("FAILED -- foo[7] = %0d (s.b. 7)", foo[7]);
$finish;
end
$display("foo[9] = %d", foo[9]);
if (foo[9] != 9) begin
$display("FAILED -- foo[9] = %0d (s.b. 9)", foo[9]);
$finish;
end
for (idx = 0 ; idx < 2*foo.size() ; idx += 1) begin
if (foo[idx%10] != (idx%10)) begin
$display("FAILED -- foo[%0d%%10] = %0d", idx, foo[idx%10]);
$finish;
end
end
foo.delete();
if (foo.size() != 0) begin
$display("FAILED -- foo.size()=%0d (after delete: s.b. 0)", foo.size());
$finish;
end
$display("PASSED");
end
endmodule // main
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_Sys_timer (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hC34F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 49999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21.02.2016 16:25:28
// Design Name:
// Module Name: SPI_SLAVE
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SPI_SLAVE#
(
parameter integer m = 15 // Data packet size
)
(
input wire RST,
input wire GCLK,
input wire SCLK,
output wire MISO,
input wire MOSI,
input wire SS,
input wire [m-1:0] DIN,
output reg [m-1:0] DOUT
);
reg [m-1:0] RXSHIFT = 0;
reg [m-1:0] TXSHIFT = 0;
reg in_progress = 1'b0;
assign MISO = TXSHIFT[m-1];
wire foo;
assign foo = SCLK | SS;
always @(negedge foo) begin
if (in_progress == 1'b1) begin
TXSHIFT <= TXSHIFT<<1;
end
else begin
TXSHIFT <= DIN;
end
end
always @(posedge GCLK) begin
in_progress <= (SS == 1'b1) ? 1'b0 : 1'b1;
end
always @(posedge SS) begin
DOUT <= (RST == 1'b1) ? 0 : RXSHIFT;
end
always @(posedge SCLK) begin
RXSHIFT <= (SS == 1'b1) ? 0 : RXSHIFT<<1 | MOSI;
end
endmodule |
//////////////////////////////////////////////////////////////////////////////////
// BCHEncoderCommandChannel for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH encoder controller command channel
// Module Name: BCHEncoderCommandChannel
// File Name: BCHEncoderCommandChannel.v
//
// Version: v1.0.0
//
// Description: BCH encoder controller command channel
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module BCHEncoderCommandChannel
#
(
parameter AddressWidth = 32 ,
parameter DataWidth = 32 ,
parameter InnerIFLengthWidth = 16 ,
parameter ThisID = 2
)
(
iClock ,
iReset ,
iSrcOpcode ,
iSrcTargetID ,
iSrcSourceID ,
iSrcAddress ,
iSrcLength ,
iSrcCmdValid ,
oSrcCmdReady ,
oOpQPushSignal ,
oOpQPushData ,
oDstOpcode ,
oDstTargetID ,
oDstSourceID ,
oDstAddress ,
oDstLength ,
oDstCmdValid ,
iDstCmdReady ,
iSrcValidCond
);
input iClock ;
input iReset ;
// Master side
input [5:0] iSrcOpcode ;
input [4:0] iSrcTargetID ;
input [4:0] iSrcSourceID ;
input [AddressWidth - 1:0] iSrcAddress ;
input [InnerIFLengthWidth - 1:0] iSrcLength ;
input iSrcCmdValid ;
output oSrcCmdReady ;
output oOpQPushSignal ;
output [InnerIFLengthWidth+2-1:0] oOpQPushData ;
// Slave side
output [5:0] oDstOpcode ;
output [4:0] oDstTargetID ;
output [4:0] oDstSourceID ;
output [AddressWidth - 1:0] oDstAddress ;
output [InnerIFLengthWidth - 1:0] oDstLength ;
output oDstCmdValid ;
input iDstCmdReady ;
input iSrcValidCond ;
reg [5:0] rOpcode ;
reg [4:0] rTargetID ;
reg [4:0] rSourceID ;
reg [AddressWidth - 1:0] rAddress ;
reg [InnerIFLengthWidth - 1:0] rLength ;
reg rDstCValid ;
reg [1:0] rOpType ;
assign oDstOpcode = rOpcode ;
assign oDstTargetID = rTargetID ;
assign oDstSourceID = rSourceID ;
assign oDstAddress = rAddress ;
assign oDstLength = rLength ;
assign oDstCmdValid = rDstCValid ;
parameter DispatchCmd_PageReadFromRAM = 6'b000001 ;
parameter DispatchCmd_SpareReadFromRAM = 6'b000010 ;
localparam PageSize = 4096;
localparam SpareSize = 64;
localparam State_Idle = 2'b00;
localparam State_EncodeReq = 2'b01;
localparam State_ForwardReq = 2'b11;
reg [1:0] rCmdChCurState ;
reg [1:0] rCmdChNextState ;
always @ (posedge iClock)
if (iReset)
rCmdChCurState <= State_Idle;
else
rCmdChCurState <= rCmdChNextState;
always @ (*)
case (rCmdChCurState)
State_Idle:
if (iSrcCmdValid && iSrcValidCond)
begin
if (
(iSrcTargetID == 0) &&
((iSrcOpcode == DispatchCmd_PageReadFromRAM) || (iSrcOpcode == DispatchCmd_SpareReadFromRAM))
)
rCmdChNextState <= State_EncodeReq;
else
rCmdChNextState <= State_ForwardReq;
end
else
rCmdChNextState <= State_Idle;
State_EncodeReq:
rCmdChNextState <= (iDstCmdReady)?State_Idle:State_EncodeReq;
State_ForwardReq:
rCmdChNextState <= (iDstCmdReady)?State_Idle:State_ForwardReq;
default:
rCmdChNextState <= State_Idle;
endcase
assign oSrcCmdReady = (rCmdChCurState == State_Idle) && (iSrcValidCond);
assign oOpQPushData = {rLength, rOpType};
assign oOpQPushSignal = oDstCmdValid && iDstCmdReady && (rLength != 0);
always @ (posedge iClock)
if (iReset)
begin
rOpcode <= 6'b0;
rTargetID <= 5'b0;
rSourceID <= 5'b0;
rAddress <= {(AddressWidth){1'b0}};
rLength <= {(InnerIFLengthWidth){1'b0}};
rOpType <= 2'b0;
end
else
begin
if (rCmdChCurState == State_Idle && iSrcCmdValid)
begin
rOpcode <= iSrcOpcode ;
rTargetID <= iSrcTargetID ;
rSourceID <= iSrcSourceID ;
rAddress <= iSrcAddress ;
rLength <= iSrcLength ;
rOpType <= 2'b0 ;
if (iSrcTargetID == 0)
begin
if (iSrcOpcode == DispatchCmd_PageReadFromRAM)
begin
rOpcode <= iSrcOpcode ;
rTargetID <= 5'b0 ;
rSourceID <= ThisID ;
rAddress <= iSrcAddress ;
rLength <= PageSize ;
rOpType <= 2'b01 ;
end
else if (iSrcOpcode == DispatchCmd_SpareReadFromRAM)
begin
rOpcode <= iSrcOpcode ;
rTargetID <= 5'b0 ;
rSourceID <= ThisID ;
rAddress <= iSrcAddress ;
rLength <= SpareSize ;
rOpType <= 2'b10 ;
end
end
end
end
always @ (*)
case (rCmdChCurState)
State_EncodeReq:
rDstCValid <= 1'b1;
State_ForwardReq:
rDstCValid <= 1'b1;
default:
rDstCValid <= 1'b0;
endcase
endmodule |
// Copyright (c) 2014 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for 'range, 'reverse_range, 'left and 'right attributes in VHDL.
module range_test;
range_entity dut();
initial begin
int i;
#1; // wait for signal assignments
if(dut.left_asc !== 2)
begin
$display("FAILED: left_asc should be %2d but is %2d", 2, dut.left_asc);
$finish();
end
if(dut.right_asc !== 4)
begin
$display("FAILED: right_asc should be %2d but is %2d", 2, dut.right_asc);
$finish();
end
if(dut.left_dsc !== 9)
begin
$display("FAILED: left_dsc should be %2d but is %2d", 2, dut.left_dsc);
$finish();
end
if(dut.right_dsc !== 3)
begin
$display("FAILED: right_dsc should be %2d but is %2d", 2, dut.right_dsc);
$finish();
end
if(dut.pow_left !== 16)
begin
$display("FAILED: pow_left should be %2d but is %2d", 16, dut.pow_left);
$finish();
end
if(dut.rem_left !== 2)
begin
$display("FAILED: rem_left should be %2d but is %2d", 2, dut.rem_left);
$finish();
end
for(i = $left(dut.ascending); i <= $right(dut.ascending); i++)
begin
if(2*i !== dut.ascending[i])
begin
$display("FAILED: ascending[%2d] should be %2d but is %2d", i, 2*i, dut.ascending[i]);
$finish();
end
end
for(i = $right(dut.descending); i <= $left(dut.descending); i++)
begin
if(3*i !== dut.descending[i])
begin
$display("FAILED: descending[%2d] should be %2d but is %2d", i, 3*i, dut.descending[i]);
$finish();
end
end
for(i = $left(dut.ascending_rev); i <= $right(dut.ascending_rev); i++)
begin
if(4*i !== dut.ascending_rev[i])
begin
$display("FAILED: ascending_rev[%2d] should be %2d but is %2d", i, 4*i, dut.ascending_rev[i]);
$finish();
end
end
for(i = $right(dut.descending_rev); i <= $left(dut.descending_rev); i++)
begin
if(5*i !== dut.descending_rev[i])
begin
$display("FAILED: descending_rev[%2d] should be %2d but is %2d", i, 5*i, dut.descending_rev[i]);
$finish();
end
end
$display("PASSED");
end
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the on board periphal devices *
* on the DE2-115 board. *
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_de2_115 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter AUD_LINE_IN_LC = 9'h01A;
parameter AUD_LINE_IN_RC = 9'h01A;
parameter AUD_LINE_OUT_LC = 9'h07B;
parameter AUD_LINE_OUT_RC = 9'h07B;
parameter AUD_ADC_PATH = 9'h0F8;
parameter AUD_DAC_PATH = 9'h006;
parameter AUD_POWER = 9'h000;
parameter AUD_DATA_FORMAT = 9'h001;
parameter AUD_SAMPLE_CTRL = 9'h002;
parameter AUD_SET_ACTIVE = 9'h001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [26: 0] audio_rom_data;
wire [26: 0] video_rom_data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = audio_rom_data | video_rom_data;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_av_config_auto_init_ob_audio Auto_Init_Audio_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (audio_rom_data)
);
defparam
Auto_Init_Audio_ROM.AUD_LINE_IN_LC = AUD_LINE_IN_LC,
Auto_Init_Audio_ROM.AUD_LINE_IN_RC = AUD_LINE_IN_RC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_LC = AUD_LINE_OUT_LC,
Auto_Init_Audio_ROM.AUD_LINE_OUT_RC = AUD_LINE_OUT_RC,
Auto_Init_Audio_ROM.AUD_ADC_PATH = AUD_ADC_PATH,
Auto_Init_Audio_ROM.AUD_DAC_PATH = AUD_DAC_PATH,
Auto_Init_Audio_ROM.AUD_POWER = AUD_POWER,
Auto_Init_Audio_ROM.AUD_DATA_FORMAT = AUD_DATA_FORMAT,
Auto_Init_Audio_ROM.AUD_SAMPLE_CTRL = AUD_SAMPLE_CTRL,
Auto_Init_Audio_ROM.AUD_SET_ACTIVE = AUD_SET_ACTIVE;
altera_up_av_config_auto_init_ob_adv7180 Auto_Init_Video_ROM (
// Inputs
.rom_address (rom_address),
// Bidirectionals
// Outputs
.rom_data (video_rom_data)
);
endmodule
|
// N64 controller read command generator/transmitter
//
// Inputs: clk_1M 1 MHz clock
// trigger On input pulse, transmit read command
// Outputs: enable_o Active when data is being transmitted
// dout Output data line
module n64_readcmd_tx(input wire clk_1M,
input wire trigger,
output wire enable_o,
output wire dout);
// Shift register parallel output
wire [33:0] data;
// dout is just the leftmost bit of data
assign dout = data[33];
// Only enable output when bit counter is not 0.
wire ctr_empty;
assign enable_o = ~ctr_empty;
// On 'trigger', counts from 34 to 0 (for counting output
// bits) and sets 'ctr_empty' active on finish.
counterM #(.M(34))
counter_signal_cycles (
.clk(clk_1M),
.reset(trigger),
.empty(ctr_empty)
);
// Shift register containing the raw waveform of the
// read command. Only enabled when counter is not 0.
shiftM #(.M(34), .INI(34'b0001000100010001000100010001011101))
shift_signal (
.clk(clk_1M),
.enable(~ctr_empty),
.serin(dout),
.data(data)
);
endmodule
|
/*
* Zet processor core
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet_core (
input clk,
input rst,
// interrupts
input intr,
output inta,
input nmi,
output nmia,
// interface to wishbone
output [19:0] cpu_adr_o,
input [15:0] iid_dat_i,
input [15:0] cpu_dat_i,
output [15:0] cpu_dat_o,
output cpu_byte_o,
input cpu_block,
output cpu_mem_op,
output cpu_m_io,
output cpu_we_o,
output [19:0] pc // for debugging purposes
);
// Net declarations
wire [`IR_SIZE-1:0] ir;
wire [15:0] off;
wire [15:0] imm;
wire wr_ip0;
wire [15:0] cs;
wire [15:0] ip;
wire of;
wire zf;
wire ifl;
wire iflm;
wire tfl;
wire tflm;
wire iflss;
wire wr_ss;
wire cx_zero;
wire div_exc;
wire [19:0] addr_exec;
wire byte_fetch;
wire byte_exec;
// wire decode - microcode
wire [`MICRO_ADDR_WIDTH-1:0] seq_addr;
wire [3:0] src;
wire [3:0] dst;
wire [3:0] base;
wire [3:0] index;
wire [1:0] seg;
wire end_seq;
wire [2:0] fdec;
wire div;
// wires fetch - decode
wire [7:0] opcode;
wire [7:0] modrm;
wire rep;
wire exec_st;
wire ld_base;
wire [2:0] sop_l;
wire need_modrm;
wire need_off;
wire need_imm;
wire off_size;
wire imm_size;
wire ext_int;
// wires fetch - microcode
wire [15:0] off_l;
wire [15:0] imm_l;
wire [15:0] imm_d;
wire [`IR_SIZE-1:0] rom_ir;
wire [5:0] ftype;
// wires fetch - exec
wire [15:0] imm_f;
// wires and regs for hlt
wire block_or_hlt;
wire hlt_op;
wire hlt_in;
wire hlt_out;
reg hlt_op_old;
reg hlt;
// regs for nmi
reg nmir;
reg nmi_old;
reg nmia_old;
wire use_eintp;
// Module instantiations
zet_fetch fetch (
.clk (clk),
.rst (rst),
// to decode
.opcode (opcode),
.modrm (modrm),
.rep (rep),
.exec_st (exec_st),
.ld_base (ld_base),
.sop_l (sop_l),
// from decode
.need_modrm (need_modrm),
.need_off (need_off),
.need_imm (need_imm),
.off_size (off_size),
.imm_size (imm_size),
.ext_int (ext_int),
.end_seq (end_seq),
// to microcode
.off_l (off_l),
.imm_l (imm_l),
// from microcode
.ftype (ftype),
// to exec
.imm_f (imm_f),
.wr_ip0 (wr_ip0),
// from exec
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.iflm (iflm),
.tflm (tflm),
.iflss (iflss),
.cx_zero (cx_zero),
.div_exc (div_exc),
// to wb
.data (cpu_dat_i),
.pc (pc),
.bytefetch (byte_fetch),
.block (block_or_hlt),
.intr (intr),
.nmir (nmir),
.use_eintp (use_eintp)
);
zet_decode decode (
.clk (clk),
.rst (rst),
.opcode (opcode),
.modrm (modrm),
.rep (rep),
.block (block_or_hlt),
.exec_st (exec_st),
.div_exc (div_exc),
.ld_base (ld_base),
.div (div),
.tfl (tfl),
.tflm (tflm),
.need_modrm (need_modrm),
.need_off (need_off),
.need_imm (need_imm),
.off_size (off_size),
.imm_size (imm_size),
.sop_l (sop_l),
.intr (intr),
.ifl (ifl),
.iflm (iflm),
.inta (inta),
.ext_int (ext_int),
.nmir (nmir),
.nmia (nmia),
.wr_ss (wr_ss),
.iflss (iflss),
.seq_addr (seq_addr),
.src (src),
.dst (dst),
.base (base),
.index (index),
.seg (seg),
.f (fdec),
.end_seq (end_seq),
.use_eintp (use_eintp)
);
zet_micro_data micro_data (
// from decode
.n_micro (seq_addr),
.off_i (off_l),
.imm_i (imm_l),
.src (src),
.dst (dst),
.base (base),
.index (index),
.seg (seg),
.fdec (fdec),
.div (div),
.end_seq (end_seq),
// to exec
.ir (rom_ir),
.off_o (off),
.imm_o (imm_d)
);
zet_exec exec (
.clk (clk),
.rst (rst),
// from fetch
.ir (ir),
.off (off),
.imm (imm),
.wrip0 (wr_ip0),
// to fetch
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.ifl (ifl),
.tfl (tfl),
.cx_zero (cx_zero),
.div_exc (div_exc),
.wr_ss (wr_ss),
// from wb
.memout (iid_dat_i),
.wr_data (cpu_dat_o),
.addr (addr_exec),
.we (cpu_we_o),
.m_io (cpu_m_io),
.byteop (byte_exec),
.block (block_or_hlt)
);
// Assignments
assign cpu_adr_o = exec_st ? addr_exec : pc;
assign cpu_byte_o = exec_st ? byte_exec : byte_fetch;
assign cpu_mem_op = ir[`MEM_OP];
assign ir = exec_st ? rom_ir : `ADD_IP;
assign imm = exec_st ? imm_d : imm_f;
assign ftype = rom_ir[28:23];
assign hlt_op = ((opcode == `OP_HLT) && exec_st);
assign hlt_in = (hlt_op && !hlt_op_old && !hlt_out);
assign hlt_out = (intr & ifl) | nmir;
assign block_or_hlt = cpu_block | hlt | hlt_in;
// Behaviour
always @(posedge clk)
if (rst)
hlt_op_old <= 1'b0;
else
if (hlt_op)
hlt_op_old <= 1'b1;
else
hlt_op_old <= 1'b0;
always @(posedge clk)
if (rst)
hlt <= 1'b0;
else
if (hlt_in)
hlt <= 1'b1;
else if (hlt_out)
hlt <= 1'b0;
always @(posedge clk)
if (rst)
begin
nmir <= 1'b0;
nmi_old <= 1'b0;
nmia_old <= 1'b0;
end
else
begin
nmi_old <= nmi;
nmia_old <= nmia;
if (nmi & ~nmi_old)
nmir <= 1'b1;
else if (nmia_old)
nmir <= 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR3B_1_V
`define SKY130_FD_SC_HS__NOR3B_1_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3b_1 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nor3b_1 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR3B_1_V
|
// Copyright (C) 2020-2021 The SymbiFlow Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier:ISC
module inv (
output Q,
input A
);
assign Q = A ? 0 : 1;
endmodule
module buff (
output Q,
input A
);
assign Q = A;
endmodule
module logic_0 (
output a
);
assign a = 0;
endmodule
module logic_1 (
output a
);
assign a = 1;
endmodule
module gclkbuff (
input A,
output Z
);
specify
(A => Z) = 0;
endspecify
assign Z = A;
endmodule
module inpad (
output Q,
(* iopad_external_pin *)
input P
);
specify
(P => Q) = 0;
endspecify
assign Q = P;
endmodule
module outpad (
(* iopad_external_pin *)
output P,
input A
);
specify
(A => P) = 0;
endspecify
assign P = A;
endmodule
module ckpad (
output Q,
(* iopad_external_pin *)
input P
);
specify
(P => Q) = 0;
endspecify
assign Q = P;
endmodule
module bipad (
input A,
input EN,
output Q,
(* iopad_external_pin *)
inout P
);
assign Q = P;
assign P = EN ? A : 1'bz;
endmodule
module dff (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK) Q <= D;
endmodule
module dffc (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK,
(* clkbuf_sink *)
input CLR
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK or posedge CLR)
if (CLR) Q <= 1'b0;
else Q <= D;
endmodule
module dffp (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK,
(* clkbuf_sink *)
input PRE
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK or posedge PRE)
if (PRE) Q <= 1'b1;
else Q <= D;
endmodule
module dffpc (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK,
(* clkbuf_sink *)
input CLR,
(* clkbuf_sink *)
input PRE
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK or posedge CLR or posedge PRE)
if (CLR) Q <= 1'b0;
else if (PRE) Q <= 1'b1;
else Q <= D;
endmodule
module dffe (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK,
input EN
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK) if (EN) Q <= D;
endmodule
module dffec (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK,
input EN,
(* clkbuf_sink *)
input CLR
);
parameter [0:0] INIT = 1'b0;
initial Q = INIT;
always @(posedge CLK or posedge CLR)
if (CLR) Q <= 1'b0;
else if (EN) Q <= D;
endmodule
(* lib_whitebox *)
module dffepc (
output reg Q,
input D,
(* clkbuf_sink *)
input CLK,
input EN,
(* clkbuf_sink *)
input CLR,
(* clkbuf_sink *)
input PRE
);
parameter [0:0] INIT = 1'b0;
specify
if (EN) (posedge CLK => (Q : D)) = 1701; // QCK -> QZ
if (CLR) (CLR => Q) = 967; // QRT -> QZ
if (PRE) (PRE => Q) = 1252; // QST -> QZ
$setup(D, posedge CLK, 216); // QCK -> QDS
$setup(EN, posedge CLK, 590); // QCK -> QEN
endspecify
initial Q = INIT;
always @(posedge CLK or posedge CLR or posedge PRE)
if (CLR) Q <= 1'b0;
else if (PRE) Q <= 1'b1;
else if (EN) Q <= D;
endmodule
// FZ FS F2 (F1 TO 0)
(* abc9_box, lib_whitebox *)
module AND2I0 (
output Q,
input A,
B
);
specify
(A => Q) = 698; // FS -> FZ
(B => Q) = 639; // F2 -> FZ
endspecify
assign Q = A ? B : 0;
endmodule
(* abc9_box, lib_whitebox *)
module mux2x0 (
output Q,
input S,
A,
B
);
specify
(S => Q) = 698; // FS -> FZ
(A => Q) = 639; // F1 -> FZ
(B => Q) = 639; // F2 -> FZ
endspecify
assign Q = S ? B : A;
endmodule
(* abc9_box, lib_whitebox *)
module mux2x1 (
output Q,
input S,
A,
B
);
specify
(S => Q) = 698; // FS -> FZ
(A => Q) = 639; // F1 -> FZ
(B => Q) = 639; // F2 -> FZ
endspecify
assign Q = S ? B : A;
endmodule
(* abc9_box, lib_whitebox *)
module mux4x0 (
output Q,
input S0,
S1,
A,
B,
C,
D
);
specify
(S0 => Q) = 1251; // TAB -> TZ
(S1 => Q) = 1406; // TSL -> TZ
(A => Q) = 1699; // TA1 -> TZ
(B => Q) = 1687; // TA2 -> TZ
(C => Q) = 1669; // TB1 -> TZ
(D => Q) = 1679; // TB2 -> TZ
endspecify
assign Q = S1 ? (S0 ? D : C) : (S0 ? B : A);
endmodule
// S0 BSL TSL
// S1 BAB TAB
// S2 TBS
// A TA1
// B TA2
// C TB1
// D TB2
// E BA1
// F BA2
// G BB1
// H BB2
// Q CZ
(* abc9_box, lib_whitebox *)
module mux8x0 (
output Q,
input S0,
S1,
S2,
A,
B,
C,
D,
E,
F,
G,
H
);
specify
(S0 => Q) = 1593; // ('TSL', 'BSL') -> CZ
(S1 => Q) = 1437; // ('TAB', 'BAB') -> CZ
(S2 => Q) = 995; // TBS -> CZ
(A => Q) = 1887; // TA1 -> CZ
(B => Q) = 1873; // TA2 -> CZ
(C => Q) = 1856; // TB1 -> CZ
(D => Q) = 1860; // TB2 -> CZ
(E => Q) = 1714; // BA1 -> CZ
(F => Q) = 1773; // BA2 -> CZ
(G => Q) = 1749; // BB1 -> CZ
(H => Q) = 1723; // BB2 -> CZ
endspecify
assign Q = S2 ? (S1 ? (S0 ? H : G) : (S0 ? F : E)) : (S1 ? (S0 ? D : C) : (S0 ? B : A));
endmodule
(* abc9_lut=1, lib_whitebox *)
module LUT1 (
output O,
input I0
);
parameter [1:0] INIT = 0;
parameter EQN = "(I0)";
// These timings are for PolarPro 3E; other families will need updating.
specify
(I0 => O) = 698; // FS -> FZ
endspecify
assign O = I0 ? INIT[1] : INIT[0];
endmodule
// TZ TSL TAB
(* abc9_lut=2, lib_whitebox *)
module LUT2 (
output O,
input I0,
I1
);
parameter [3:0] INIT = 4'h0;
parameter EQN = "(I0)";
// These timings are for PolarPro 3E; other families will need updating.
specify
(I0 => O) = 1251; // TAB -> TZ
(I1 => O) = 1406; // TSL -> TZ
endspecify
wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
(* abc9_lut=2, lib_whitebox *)
module LUT3 (
output O,
input I0,
I1,
I2
);
parameter [7:0] INIT = 8'h0;
parameter EQN = "(I0)";
// These timings are for PolarPro 3E; other families will need updating.
specify
(I0 => O) = 1251; // TAB -> TZ
(I1 => O) = 1406; // TSL -> TZ
(I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ
endspecify
wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0];
wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
(* abc9_lut=4, lib_whitebox *)
module LUT4 (
output O,
input I0,
I1,
I2,
I3
);
parameter [15:0] INIT = 16'h0;
parameter EQN = "(I0)";
// These timings are for PolarPro 3E; other families will need updating.
specify
(I0 => O) = 995; // TBS -> CZ
(I1 => O) = 1437; // ('TAB', 'BAB') -> CZ
(I2 => O) = 1593; // ('TSL', 'BSL') -> CZ
(I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ
endspecify
wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0];
wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0];
wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0];
assign O = I0 ? s1[1] : s1[0];
endmodule
module logic_cell_macro (
input BA1,
input BA2,
input BAB,
input BAS1,
input BAS2,
input BB1,
input BB2,
input BBS1,
input BBS2,
input BSL,
input F1,
input F2,
input FS,
input QCK,
input QCKS,
input QDI,
input QDS,
input QEN,
input QRT,
input QST,
input TA1,
input TA2,
input TAB,
input TAS1,
input TAS2,
input TB1,
input TB2,
input TBS,
input TBS1,
input TBS2,
input TSL,
output CZ,
output FZ,
output QZ,
output TZ
);
wire TAP1, TAP2, TBP1, TBP2, BAP1, BAP2, BBP1, BBP2, QCKP, TAI, TBI, BAI, BBI, TZI, BZI, CZI, QZI;
reg QZ_r;
initial begin
QZ_r = 1'b0;
end
assign QZ = QZ_r;
assign TAP1 = TAS1 ? ~TA1 : TA1;
assign TAP2 = TAS2 ? ~TA2 : TA2;
assign TBP1 = TBS1 ? ~TB1 : TB1;
assign TBP2 = TBS2 ? ~TB2 : TB2;
assign BAP1 = BAS1 ? ~BA1 : BA1;
assign BAP2 = BAS2 ? ~BA2 : BA2;
assign BBP1 = BBS1 ? ~BB1 : BB1;
assign BBP2 = BBS2 ? ~BB2 : BB2;
assign TAI = TSL ? TAP2 : TAP1;
assign TBI = TSL ? TBP2 : TBP1;
assign BAI = BSL ? BAP2 : BAP1;
assign BBI = BSL ? BBP2 : BBP1;
assign TZI = TAB ? TBI : TAI;
assign BZI = BAB ? BBI : BAI;
assign CZI = TBS ? BZI : TZI;
assign QZI = QDS ? QDI : CZI;
assign FZ = FS ? F2 : F1;
assign TZ = TZI;
assign CZ = CZI;
assign QCKP = QCKS ? QCK : ~QCK;
always @(posedge QCKP) if (~QRT && ~QST) if (QEN) QZ_r = QZI;
always @(QRT or QST)
if (QRT) QZ_r = 1'b0;
else if (QST) QZ_r = 1'b1;
endmodule
// Include simulation models of QLAL4S3B eFPGA interface
`include "qlal4s3b_sim.v"
// Include simulation models for QLAL3 hard blocks
`include "qlal3_sim.v"
// Include BRAM and FIFO simulation models
`include "brams_sim.v"
// Include MULT simulation models
`include "mult_sim.v"
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221O_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A221O_PP_BLACKBOX_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a221o (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221O_PP_BLACKBOX_V
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/13/2010
Version 2.5
This write master module is responsible for taking in streaming data and
writing the contents out to memory. It is controlled by a streaming
sink port called the 'command port'. Any information that must be communicated
back to a host such as an error in transfer is made available by the
streaming source port called the 'response port'.
There are various parameters to control the synthesis of this hardware
either for functionality changes or speed/resource optimizations. Some
of the parameters will be hidden in the component GUI since they are derived
from some other parameters. When this master module is used in a MM to MM
transfer disable the packet support since the packet hardware is not needed.
In order to increase the Fmax you should enable only full accesses so that
the unaligned access and byte enable blocks can be reduced to wires. Also
only configure the length width to be as wide as you need as it will typically
be the critical path of this module.
Revision History:
1.0 Initial version which used a simple exported hand shake control scheme.
2.0 Added support for unaligned accesses, stride, and streaming.
2.1 Fixed control logic and removed the early termination enable logic (it's
always on now so for packet transfers make sure the length register is
programmed accordingly.
2.2 Added burst support.
2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
2.4 Corrected burst bug that prevented full bursts from being presented to the
fabric. Corrected the stop/reset logic to ensure masters can be stopped
or reset while idle.
2.5 Corrected a packet problem where EOP wasn't qualified by ready and valid.
Added 64-bit addressing.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_master (
clk,
reset,
// descriptor commands sink port
snk_command_data,
snk_command_valid,
snk_command_ready,
// response source port
src_response_data,
src_response_valid,
src_response_ready,
// data path sink port
snk_data,
snk_valid,
snk_ready,
snk_sop,
snk_eop,
snk_empty,
snk_error,
// data path master port
master_address,
master_write,
master_byteenable,
master_writedata,
master_waitrequest,
master_burstcount
);
parameter UNALIGNED_ACCESSES_ENABLE = 0; // when enabled allows transfers to begin from off word boundaries
parameter ONLY_FULL_ACCESS_ENABLE = 0; // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
parameter STRIDE_ENABLE = 0; // stride support can only be enabled when unaligned accesses is disabled
parameter STRIDE_WIDTH = 1; // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width
parameter PACKET_ENABLE = 0;
parameter ERROR_ENABLE = 0;
parameter ERROR_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
parameter DATA_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // set by the .tcl file (hidden in GUI)
parameter BYTE_ENABLE_WIDTH_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter ADDRESS_WIDTH = 32; // set in the .tcl file (hidden in GUI) by the address span of the master
parameter LENGTH_WIDTH = 32; // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
parameter ACTUAL_BYTES_TRANSFERRED_WIDTH = 32; // GUI setting which can only be set when packet support is enabled (otherwise it'll be set to 32). A warning will be issued if overrun protection is enabled and this setting is less than the length width.
parameter FIFO_DEPTH = 32;
parameter FIFO_DEPTH_LOG2 = 5; // set by the .tcl file (hidden in GUI)
parameter FIFO_SPEED_OPTIMIZATION = 1; // set by the .tcl file (hidden in GUI) The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
parameter SYMBOL_WIDTH = 8; // set by the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS = 4; // set by the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter BURST_ENABLE = 0;
parameter MAX_BURST_COUNT = 2; // must be a power of 2, when BURST_ENABLE = 0 set the maximum burst count to 1 (automatically done in the .tcl file)
parameter MAX_BURST_COUNT_WIDTH = 2; // set by the .tcl file (hidden in GUI) = log2(MAX_BURST_COUNT) + 1
parameter PROGRAMMABLE_BURST_ENABLE = 0; // when enabled the user must set the burst count, if 0 is set then the value MAX_BURST_COUNT will be used instead
parameter BURST_WRAPPING_SUPPORT = 1; // will only be used when bursting is enabled. This cannot be enabled with programmable burst capabilities. Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
localparam FIFO_USE_MEMORY = 1; // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
localparam BIG_ENDIAN_ACCESS = 0; // hiding this since it can blow your foot off if you are not careful and it's not tested. It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
// handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
//need to buffer the empty, eop, sop, and error bits. If these are not needed then the logic will be synthesized away
localparam FIFO_WIDTH = (DATA_WIDTH + 2 + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH); // data, sop, eop, empty, and error bits
localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
localparam FIXED_STRIDE = 1'b1; // when stride isn't supported this will be the stride value used (i.e. sequential incrementing of the address)
input clk;
input reset;
// descriptor commands sink port
input [255:0] snk_command_data;
input snk_command_valid;
output reg snk_command_ready;
// response source port
output wire [255:0] src_response_data;
output reg src_response_valid;
input src_response_ready;
// data path sink port
input [DATA_WIDTH-1:0] snk_data;
input snk_valid;
output wire snk_ready;
input snk_sop;
input snk_eop;
input [NUMBER_OF_SYMBOLS_LOG2-1:0] snk_empty;
input [ERROR_WIDTH-1:0] snk_error;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESS_WIDTH-1:0] master_address;
output wire master_write;
output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
output wire [DATA_WIDTH-1:0] master_writedata;
output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
// internal wires and registers
wire [63:0] descriptor_address;
wire [31:0] descriptor_length;
wire [15:0] descriptor_stride;
wire descriptor_end_on_eop_enable;
wire [7:0] descriptor_programmable_burst_count;
reg [ADDRESS_WIDTH-1:0] address_counter;
wire [ADDRESS_WIDTH-1:0] address; // unfiltered version of master_address
wire write; // unfiltered version of master_write
reg [LENGTH_WIDTH-1:0] length_counter;
reg [STRIDE_WIDTH-1:0] stride_d1;
wire [STRIDE_WIDTH-1:0] stride_amount; // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
reg descriptor_end_on_eop_enable_d1;
reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address; // used to determine how far out of alignement the master started
reg first_access; // used to prevent extra writes when the unaligned access starts and ends during the same write
wire first_word_boundary_not_reached; // set when the first access doesn't reach the next word boundary
reg first_word_boundary_not_reached_d1;
wire increment_address; // enable the address incrementing
wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment; // amount of bytes to increment the address
wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
wire short_first_access_enable; // when starting unaligned and the amount of data to transfer reaches the next word boundary
wire short_last_access_enable; // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary
wire short_first_and_last_access_enable; // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;
wire [FIFO_WIDTH-1:0] fifo_write_data;
wire [FIFO_WIDTH-1:0] fifo_read_data;
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_write;
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire [DATA_WIDTH-1:0] fifo_read_data_rearranged; // if big endian support is enabled then this signal has the FIFO output byte lanes reversed
wire go;
wire done;
reg done_d1;
wire done_strobe;
wire [DATA_WIDTH-1:0] buffered_data;
wire [NUMBER_OF_SYMBOLS_LOG2-1:0] buffered_empty;
wire buffered_eop;
wire buffered_sop; // not wired to anything so synthesized away, included for debug purposes
wire [ERROR_WIDTH-1:0] buffered_error;
wire length_sync_reset; // syncronous reset for the length counter for eop support
reg [ACTUAL_BYTES_TRANSFERRED_WIDTH-1:0] actual_bytes_transferred_counter; // width will be in the range of 1-32
wire [31:0] response_actual_bytes_transferred;
wire early_termination;
reg early_termination_d1;
wire eop_enable;
reg [ERROR_WIDTH-1:0] error; // SRFF so that we don't loose any errors if EOP doesn't arrive right away
wire [7:0] response_error; // need to pad upper error bits with zeros if they are not present at the data streaming port
wire sw_stop_in;
wire sw_reset_in;
reg stopped; // SRFF to make sure we don't attempt to stop in the middle of a transfer
reg reset_taken; // FF to make sure we don't attempt to reset the master in the middle of a transfer
wire reset_taken_from_write_burst_control; // in the middle of a burst greater than one, the burst control block will assert this signal after the burst copmletes, 'reset_taken' will use this signal
wire stopped_from_write_burst_control; // in the middle of a burst greater than one, the burst control block will assert this signal after the burst completes, 'stopped' will use this signal
wire stop_state;
wire reset_delayed;
wire write_complete; // handy signal for determining when a write has occured and completed
wire write_stall_from_byte_enable_generator; // partial word access occuring which might take multiple write cycles to complete (or waitrequest has been asserted)
wire write_stall_from_write_burst_control; // when there isn't enough data buffered to start a burst this signal will be asserted
wire [BYTE_ENABLE_WIDTH-1:0] byteenable_masks [0:BYTE_ENABLE_WIDTH-1]; // a bunch of masks that will be provided to unsupported_byteenable
wire [BYTE_ENABLE_WIDTH-1:0] unsupported_byteenable; // input into the byte enable generation block which will take the unsupported byte enable and chop it up into supported transfers
wire [BYTE_ENABLE_WIDTH-1:0] supported_byteenable; // output from the byte enable generation block
wire extra_write; // when asserted master_write will be asserted but the FIFO will not be popped since it will not contain any more data for the transfer
wire st_to_mm_adapter_enable;
wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_beat_size; // number of bytes coming in from the data stream when packet support is enabled
wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered;
reg [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered_d1; // represents the number of bytes buffered in the ST to MM adapter (only applicable for unaligned accesses)
reg eop_seen; // when the beat containing EOP has been popped from the fifo this bit will be set, it will be reset when done is asserted. It is used to determine if an extra write must occur (unaligned accesses only)
/********************************************* REGISTERS ****************************************************************************************/
// registering the stride control bit
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stride_d1 <= 0;
end
else if (go == 1)
begin
stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
end
end
// registering the end on eop bit (will be optimized away if packet support is disabled)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
descriptor_end_on_eop_enable_d1 <= 1'b0;
end
else if (go == 1)
begin
descriptor_end_on_eop_enable_d1 <= descriptor_end_on_eop_enable;
end
end
// registering the programmable burst count (will be optimized away if this support is disabled)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
programmable_burst_count_d1 <= 0;
end
else if (go == 1)
begin
programmable_burst_count_d1 <= (descriptor_programmable_burst_count == 0)? MAX_BURST_COUNT : descriptor_programmable_burst_count;
end
end
// master address increment counter
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_counter <= 0;
end
else
begin
if (go == 1)
begin
address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
end
else if (increment_address == 1)
begin
address_counter <= address_counter + address_increment;
end
end
end
// master byte address, used to determine how far out of alignment the master began transfering data
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_byte_address <= 0;
end
else if (go == 1)
begin
start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
end
end
// first_access will be asserted only for the first write of a transaction, this will be used to filter 'extra_write' for unaligned accesses
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_access <= 0;
end
else
begin
if (go == 1)
begin
first_access <= 1;
end
else if ((first_access == 1) & (increment_address == 1))
begin
first_access <= 0;
end
end
end
// this register is used to determine if the first word boundary will be reached
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_word_boundary_not_reached_d1 <= 0;
end
else if (go == 1)
begin
first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
end
end
// master length logic, this will typically be the critical path followed by the FIFO
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
length_counter <= 0;
end
else
begin
if (length_sync_reset == 1) // when packet support is enabled the length register might roll over so this sync reset will prevent that from happening (it's also used when a soft reset is triggered)
begin
length_counter <= 0; // when EOP arrives need to stop counting, length=0 is the done condition
end
else if (go == 1)
begin
length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
end
else if (increment_address == 1)
begin
length_counter <= length_counter - bytes_to_transfer; // not using address_increment because stride might be enabled
end
end
end
// master actual bytes transferred logic, this will only be used when packet support is enabled, otherwise the value will be 0
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
actual_bytes_transferred_counter <= 0;
end
else
begin
if ((go == 1) | (reset_taken == 1))
begin
actual_bytes_transferred_counter <= 0;
end
else if(increment_address == 1)
begin
actual_bytes_transferred_counter <= actual_bytes_transferred_counter + bytes_to_transfer;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
done_d1 <= 1; // out of reset the master needs to be 'done' so that the done_strobe doesn't fire
end
else
begin
done_d1 <= done;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
early_termination_d1 <= 0;
end
else
begin
early_termination_d1 <= early_termination;
end
end
generate
genvar l;
for(l = 0; l < ERROR_WIDTH; l = l + 1)
begin: error_SRFF
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
error[l] <= 0;
end
else
begin
if ((go == 1) | (reset_taken == 1))
begin
error[l] <= 0;
end
else if ((buffered_error[l] == 1) & (done == 0))
begin
error[l] <= 1;
end
end
end
end
endgenerate
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
snk_command_ready <= 1; // have to start ready to take commands
end
else
begin
if (go == 1)
begin
snk_command_ready <= 0;
end
else if (((done == 1) & (src_response_valid == 0)) | (reset_taken == 1)) // need to make sure the response is popped before accepting more commands
begin
snk_command_ready <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
src_response_valid <= 0;
end
else
begin
if (reset_taken == 1)
begin
src_response_valid <= 0;
end
else if (done_strobe == 1)
begin
src_response_valid <= 1; // will be set only once
end
else if ((src_response_valid == 1) & (src_response_ready == 1))
begin
src_response_valid <= 0; // will be reset only once when the dispatcher captures the data
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped <= 0;
end
else
begin
if ((sw_stop_in == 0) | (reset_taken == 1))
begin
stopped <= 0;
end
else if ((sw_stop_in == 1) & (((write_complete == 1) & (stopped_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0))))
begin
stopped <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
reset_taken <= 0;
end
else
begin
reset_taken <= (sw_reset_in == 1) & (((write_complete == 1) & (reset_taken_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0)));
end
end
// eop_seen will be set when the last beat of a packet transfer has been popped from the fifo for ST to MM block flushing purposes (extra write)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
eop_seen <= 0;
end
else
begin
if (done == 1)
begin
eop_seen <= 0;
end
else if ((buffered_eop == 1) & (write_complete == 1))
begin
eop_seen <= 1;
end
end
end
// when unaligned accesses are enabled packet_bytes_buffered_d1 is the number of bytes buffered in the ST to MM block from the previous beat
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_bytes_buffered_d1 <= 0;
end
else
begin
if (go == 1)
begin
packet_bytes_buffered_d1 <= 0;
end
else if (write_complete == 1)
begin
packet_bytes_buffered_d1 <= packet_bytes_buffered;
end
end
end
/********************************************* END REGISTERS ************************************************************************************/
/********************************************* MODULE INSTANTIATIONS ****************************************************************************/
/* buffered sop, eop, empty, error, data (in that order). sop, eop, and empty are only used when packet support is enabled,
likewise error is only used when error support is enabled */
scfifo the_st_to_master_fifo (
.aclr (reset),
.clock (clk),
.data (fifo_write_data),
.full (fifo_full),
.empty (fifo_empty),
.q (fifo_read_data),
.rdreq (fifo_read),
.usedw (fifo_used),
.wrreq (fifo_write)
);
defparam the_st_to_master_fifo.lpm_width = FIFO_WIDTH;
defparam the_st_to_master_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_st_to_master_fifo.lpm_numwords = FIFO_DEPTH;
defparam the_st_to_master_fifo.lpm_showahead = "ON"; // slower but doesn't require complex control logic to time with waitrequest
defparam the_st_to_master_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
defparam the_st_to_master_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
defparam the_st_to_master_fifo.underflow_checking = "OFF";
defparam the_st_to_master_fifo.overflow_checking = "OFF";
/* This module will barrelshift the data from the FIFO when unaligned accesses is enabled (we are using
part of the FIFO word when off boundary). When unaligned accesses is disabled then the data passes
as wires. The byte enable generator might require multiple cycles to perform partial accesses so a
'stall' bit is used (triggers a stall like waitrequest)
*/
ST_to_MM_Adapter the_ST_to_MM_Adapter (
.clk (clk),
.reset (reset),
.enable (st_to_mm_adapter_enable),
.address (descriptor_address[ADDRESS_WIDTH-1:0]),
.start (go),
.waitrequest (master_waitrequest),
.stall (write_stall_from_byte_enable_generator | write_stall_from_write_burst_control),
.write_data (master_writedata),
.fifo_data (buffered_data),
.fifo_empty (fifo_empty),
.fifo_readack (fifo_read)
);
defparam the_ST_to_MM_Adapter.DATA_WIDTH = DATA_WIDTH;
defparam the_ST_to_MM_Adapter.BYTEENABLE_WIDTH_LOG2 = BYTE_ENABLE_WIDTH_LOG2;
defparam the_ST_to_MM_Adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_ST_to_MM_Adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
/* this block is responsible for presenting the fabric with supported byte enable combinations which can
take multiple cycles, if full word only support is enabled this block will reduce to wires during synthesis */
byte_enable_generator the_byte_enable_generator (
.clk (clk),
.reset (reset),
.write_in (write),
.byteenable_in (unsupported_byteenable),
.waitrequest_out (write_stall_from_byte_enable_generator),
.byteenable_out (supported_byteenable),
.waitrequest_in (master_waitrequest | write_stall_from_write_burst_control)
);
defparam the_byte_enable_generator.BYTEENABLE_WIDTH = BYTE_ENABLE_WIDTH;
// this block will be used to drive write, address, and burstcount to the fabric
write_burst_control the_write_burst_control (
.clk (clk),
.reset (reset),
.sw_reset (sw_reset_in),
.sw_stop (sw_stop_in),
.length (length_counter),
.eop_enabled (descriptor_end_on_eop_enable_d1),
.eop (snk_eop),
.ready (snk_ready),
.valid (snk_valid),
.early_termination (early_termination),
.address_in (address),
.write_in (write),
.max_burst_count (maximum_burst_count),
.write_fifo_used ({fifo_full,fifo_used}),
.waitrequest (master_waitrequest),
.short_first_access_enable (short_first_access_enable),
.short_last_access_enable (short_last_access_enable),
.short_first_and_last_access_enable (short_first_and_last_access_enable),
.address_out (master_address),
.write_out (master_write), // filtered version of 'write'
.burst_count (master_burstcount),
.stall (write_stall_from_write_burst_control),
.reset_taken (reset_taken_from_write_burst_control),
.stopped (stopped_from_write_burst_control)
);
defparam the_write_burst_control.BURST_ENABLE = BURST_ENABLE;
defparam the_write_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
defparam the_write_burst_control.WORD_SIZE = BYTE_ENABLE_WIDTH;
defparam the_write_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2; // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
defparam the_write_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_write_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_write_burst_control.WRITE_FIFO_USED_WIDTH = FIFO_DEPTH_LOG2;
defparam the_write_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
/********************************************* END MODULE INSTANTIATIONS ************************************************************************/
/********************************************* CONTROL AND COMBINATIONAL SIGNALS ****************************************************************/
// breakout the descriptor information into more manageable names
assign descriptor_address = {snk_command_data[123:92], snk_command_data[31:0]}; // 64-bit addressing support
assign descriptor_length = snk_command_data[63:32];
assign descriptor_programmable_burst_count = snk_command_data[75:68];
assign descriptor_stride = snk_command_data[91:76];
assign descriptor_end_on_eop_enable = snk_command_data[64];
assign sw_stop_in = snk_command_data[66];
assign sw_reset_in = snk_command_data[67];
assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE; // hardcoding to FIXED_STRIDE when stride capabilities are disabled
assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
assign eop_enable = (PACKET_ENABLE == 1)? descriptor_end_on_eop_enable_d1 : 1'b0; // no eop or early termination support when packet support is disabled
assign done_strobe = (done == 1) & (done_d1 == 0) & (reset_taken == 0); // set_done asserts the done register so this strobe fires when the last write completes
assign response_error = (ERROR_ENABLE == 1)? error : 8'b00000000;
assign response_actual_bytes_transferred = (PACKET_ENABLE == 1)? actual_bytes_transferred_counter : 32'h00000000;
// transfer size amounts for special cases (starting unaligned, ending with a partial word, starting unaligned and ending with a partial word on the same write)
assign short_first_access_size = BYTE_ENABLE_WIDTH - start_byte_address;
assign short_last_access_size = (eop_enable == 1)? (packet_beat_size + packet_bytes_buffered_d1) : (length_counter & LSB_MASK);
assign short_first_and_last_access_size = (eop_enable == 1)? (BYTE_ENABLE_WIDTH - buffered_empty) : (length_counter & LSB_MASK);
/* special case transfer enables and counter increment values (address_counter, length_counter, and actual_bytes_transferred)
short_first_access_enable is for transfers that start aligned but reach the next word boundary
short_last_access_enable is for transfers that are not the first transfer but don't end with on a word boundary
short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (may or may not be aligned)
*/
generate
if (UNALIGNED_ACCESSES_ENABLE == 1)
begin
// all three enables are mutually exclusive to provide one-hot encoding for the bytes to transfer mux
assign short_first_access_enable = (start_byte_address != 0) & (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) >= BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 0));
assign short_last_access_enable = (first_access == 0) & ((eop_enable == 1)? ((packet_beat_size + packet_bytes_buffered_d1) < BYTE_ENABLE_WIDTH): (length_counter < BYTE_ENABLE_WIDTH));
assign short_first_and_last_access_enable = (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) < BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 1));
assign bytes_to_transfer = bytes_to_transfer_mux;
assign address_increment = bytes_to_transfer_mux; // can't use stride when unaligned accesses are enabled
end
else if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = 0;
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = BYTE_ENABLE_WIDTH;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount; // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH; // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
end
end
else // must be aligned but can end with any number of bytes
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = (eop_enable == 1)? (buffered_eop == 1) : (length_counter < BYTE_ENABLE_WIDTH); // less than a word to transfer
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = bytes_to_transfer_mux;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount;
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH;
end
end
endgenerate
// the control logic ensures this mux is one-hot with the fall through being the typical full word aligned access
always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size)
begin
case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
3'b001: bytes_to_transfer_mux = short_first_access_size; // unaligned and reaches the next word boundary
3'b010: bytes_to_transfer_mux = short_last_access_size; // aligned and does not reach the next word boundary
3'b100: bytes_to_transfer_mux = short_first_and_last_access_size; // unaligned and does not reach the next word boundary
default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH; // aligned and reaches the next word boundary (i.e. a full word transfer)
endcase
end
// Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before jamming them into the FIFO, changing the symbol width to something other than 8 might break something...
generate
genvar i;
for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH) // the data width is always a multiple of the symbol width
begin: symbol_swap
assign fifo_write_data[i +SYMBOL_WIDTH -1: i] = snk_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
end
endgenerate
// sticking the error, empty, eop, and eop bits at the top of the FIFO write data, flooring empty to zero when eop is not asserted (empty is only valid on eop cycles)
assign fifo_write_data[FIFO_WIDTH-1:DATA_WIDTH] = {snk_error, (snk_eop == 1)? snk_empty:0, snk_sop, snk_eop};
// swap the bytes if big endian is enabled (remember that this isn't tested so use at your own risk and make sure you understand the software impact this has)
generate
if(BIG_ENDIAN_ACCESS == 1)
begin
genvar j;
for(j=0; j < DATA_WIDTH; j = j + 8)
begin: byte_swap
assign fifo_read_data_rearranged[j +8 -1: j] = fifo_read_data[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
assign master_byteenable[j/8] = supported_byteenable[(DATA_WIDTH -j -1)/8];
end
end
else
begin
assign fifo_read_data_rearranged = fifo_read_data[DATA_WIDTH-1:0]; // little endian so no byte swapping necessary
assign master_byteenable = supported_byteenable; // dito
end
endgenerate
// fifo read data is in the format of {error, empty, sop, eop, data} with the following widths {ERROR_WIDTH, NUMBER_OF_SYMBOLS_LOG2, 1, 1, DATA_WIDTH}
assign buffered_data = fifo_read_data_rearranged;
assign buffered_error = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH -1: DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2];
generate
if (PACKET_ENABLE == 1)
begin
assign buffered_eop = fifo_read_data[DATA_WIDTH];
assign buffered_sop = fifo_read_data[DATA_WIDTH +1];
if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign buffered_empty = 0; // ignore the empty signal and assume it was a full beat
end
else
begin
assign buffered_empty = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 -1: DATA_WIDTH +2]; // empty is packed into the upper FIFO bits
end
end
else
begin
assign buffered_empty = 0;
assign buffered_eop = 0;
assign buffered_sop = 0;
end
endgenerate
/* Generating mask bits based on the size of the transfer before the unaligned access adjustment. This is based on the
transfer size to determine how many byte enables would be asserted in the aligned case. Afterwards the
byte enables will be shifted left based on how far out of alignment the address counter is (should only happen for the
first transfer). If the data path is 32 bits wide then the following masks are generated:
Transfer Size Index Mask
1 0 0001
2 1 0011
3 2 0111
4 3 1111
Note that the index is just the transfer size minus one
*/
generate if (BYTE_ENABLE_WIDTH > 1)
begin
genvar k;
for (k = 0; k < BYTE_ENABLE_WIDTH; k = k + 1)
begin: byte_enable_loop
assign byteenable_masks[k] = { {(BYTE_ENABLE_WIDTH-k-1){1'b0}}, {(k+1){1'b1}} }; // Byte enable width - k zeros followed by k ones
end
end
else
begin
assign byteenable_masks[0] = 1'b1; // will be stubbed at top level
end
endgenerate
/* byteenable_mask is based on an aligned access determined by the transfer size. This value is then shifted
to the left by the unaligned offset (first transfer only) to compensate for the unaligned offset so that the
correct byte enables are enabled. When the accesses are aligned then no barrelshifting is needed and when full
accesses are used then all byte enables will be asserted always. */
generate if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign unsupported_byteenable = {BYTE_ENABLE_WIDTH{1'b1}}; // always full accesses so the byte enables are all ones
end
else if (UNALIGNED_ACCESSES_ENABLE == 0)
begin
assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1]; // aligned so no unaligned adjustment required
end
else // unaligned case
begin
assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1] << (address_counter & LSB_MASK); // barrelshift adjusts for unaligned start address
end
endgenerate
generate if (BYTE_ENABLE_WIDTH > 1)
begin
assign address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} }; // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
end
else
begin
assign address = address_counter; // don't need to mask any bits as the address will only advance one byte at a time
end
endgenerate
assign done = (length_counter == 0) | ((PACKET_ENABLE == 1) & (eop_enable == 1) & (eop_seen == 1) & (extra_write == 0));
assign packet_beat_size = (eop_seen == 1) ? 0 : (BYTE_ENABLE_WIDTH - buffered_empty); // when the eop arrives we can't add more to packet_bytes_buffered_d1
assign packet_bytes_buffered = packet_beat_size + packet_bytes_buffered_d1 - bytes_to_transfer;
// extra_write is only applicable when unaligned accesses are performed. This extra access gets the remaining data buffered in the ST to MM adapter block written to memory
assign extra_write = (UNALIGNED_ACCESSES_ENABLE == 1) & (((PACKET_ENABLE == 1) & (eop_enable == 1))?
((eop_seen == 1) & (packet_bytes_buffered_d1 != 0)) : // when packets are used if there are left over bytes buffered after eop is seen perform an extra write
((first_access == 0) & (start_byte_address != 0) & (short_last_access_enable == 1) & (start_byte_address >= length_counter[BYTE_ENABLE_WIDTH_LOG2-1:0]))); // non-packet transfer and there are extra bytes buffered so performing an extra access
assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) & // length is less than the word size
(((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH); // start address + length doesn't reach the next word boundary (not used for packet transfers)
assign write = ((fifo_empty == 0) | (extra_write == 1)) & (done == 0) & (stopped == 0);
assign st_to_mm_adapter_enable = (done == 0) & (extra_write == 0);
assign write_complete = (write == 1) & (master_waitrequest == 0) & (write_stall_from_byte_enable_generator == 0) & (write_stall_from_write_burst_control == 0); // writing still occuring and no reasons to prevent the write cycle from completing
assign increment_address = ((write == 1) & (write_complete == 1)) & (stopped == 0);
assign go = (snk_command_valid == 1) & (snk_command_ready == 1); // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
assign snk_ready = (fifo_full == 0) & // need to make sure more streaming data doesn't come in when the FIFO is full
(((PACKET_ENABLE == 1) & (snk_sop == 1) & (fifo_empty == 0)) != 1); // need to make sure that only one packet is buffered at any given time (sop will continue to be asserted until the buffer is written out)
assign length_sync_reset = (((reset_taken == 1) | (early_termination_d1 == 1)) & (done == 0)) | (done_strobe == 1); // abrupt stop cases or packet transfer just completed (otherwise the length register will reach 0 by itself)
assign fifo_write = (snk_ready == 1) & (snk_valid == 1);
assign early_termination = (eop_enable == 1) & (write_complete == 1) & (length_counter < bytes_to_transfer); // packet transfer and the length counter is about to roll over so stop transfering
assign stop_state = stopped;
assign reset_delayed = (reset_taken == 0) & (sw_reset_in == 1);
assign src_response_data = {{212{1'b0}}, done_strobe, early_termination_d1, response_error, stop_state, reset_delayed, response_actual_bytes_transferred};
/********************************************* END CONTROL AND COMBINATIONAL SIGNALS ************************************************************/
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_TX_FIFO.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core WISHBONE interface. ////
//// ////
//// Known problems (limits): ////
//// Inserts one wait state on all transfers. ////
//// Note affected signals and the way they are affected. ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Jacob Gorban, [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_wb.v,v $
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/21 19:12:01 gorban
// Corrected some Linter messages.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:13+02 jacob
// Initial revision
//
//
// UART core WISHBONE interface
//
// Author: Jacob Gorban ([email protected])
// Company: Flextronics Semiconductor
//
`include "timescale.v"
module uart_wb (clk,
wb_rst_i,
wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o,
we_o, re_o // Write and read enable output for the core
);
input clk;
// WISHBONE interface
input wb_rst_i;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
output wb_ack_o;
output we_o;
output re_o;
wire we_o;
reg wb_ack_o;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
wb_ack_o <= #1 1'b0;
end
else
begin
// wb_ack_o <= #1 wb_stb_i & wb_cyc_i; // 1 clock wait state on all transfers
wb_ack_o <= #1 wb_stb_i & wb_cyc_i & ~wb_ack_o; // 1 clock wait state on all transfers
end
end
assign we_o = wb_we_i & wb_cyc_i & wb_stb_i; //WE for registers
assign re_o = ~wb_we_i & wb_cyc_i & wb_stb_i; //RE for registers
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module serial_tx #(
parameter CLK_PER_BIT = 50
)(
input clk,
input rst,
output tx,
input block,
output busy,
input [7:0] data,
input new_data
);
// clog2 is 'ceiling of log base 2' which gives you the number of bits needed to store a value
parameter CTR_SIZE = $clog2(CLK_PER_BIT);
localparam STATE_SIZE = 2;
localparam IDLE = 2'd0,
START_BIT = 2'd1,
DATA = 2'd2,
STOP_BIT = 2'd3;
reg [CTR_SIZE-1:0] ctr_d, ctr_q;
reg [2:0] bit_ctr_d, bit_ctr_q;
reg [7:0] data_d, data_q;
reg [STATE_SIZE-1:0] state_d, state_q = IDLE;
reg tx_d, tx_q;
reg busy_d, busy_q;
reg block_d, block_q;
assign tx = tx_q;
assign busy = busy_q;
always @(*) begin
block_d = block;
ctr_d = ctr_q;
bit_ctr_d = bit_ctr_q;
data_d = data_q;
state_d = state_q;
busy_d = busy_q;
case (state_q)
IDLE: begin
if (block_q) begin
busy_d = 1'b1;
tx_d = 1'b1;
end else begin
busy_d = 1'b0;
tx_d = 1'b1;
bit_ctr_d = 3'b0;
ctr_d = 1'b0;
if (new_data) begin
data_d = data;
state_d = START_BIT;
busy_d = 1'b1;
end
end
end
START_BIT: begin
busy_d = 1'b1;
ctr_d = ctr_q + 1'b1;
tx_d = 1'b0;
if (ctr_q == CLK_PER_BIT - 1) begin
ctr_d = 1'b0;
state_d = DATA;
end
end
DATA: begin
busy_d = 1'b1;
tx_d = data_q[bit_ctr_q];
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
ctr_d = 1'b0;
bit_ctr_d = bit_ctr_q + 1'b1;
if (bit_ctr_q == 7) begin
state_d = STOP_BIT;
end
end
end
STOP_BIT: begin
busy_d = 1'b1;
tx_d = 1'b1;
ctr_d = ctr_q + 1'b1;
if (ctr_q == CLK_PER_BIT - 1) begin
state_d = IDLE;
end
end
default: begin
state_d = IDLE;
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_q <= IDLE;
tx_q <= 1'b1;
end else begin
state_q <= state_d;
tx_q <= tx_d;
end
block_q <= block_d;
data_q <= data_d;
bit_ctr_q <= bit_ctr_d;
ctr_q <= ctr_d;
busy_q <= busy_d;
end
endmodule |
// Copyright (C) 2014 John Leitch ([email protected])
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module Md5Core ( clk,
wb,
a0,
b0,
c0,
d0,
a64,
b64,
c64,
d64);
input clk;
input [511:0] wb;
input [31:0] a0;
input [31:0] b0;
input [31:0] c0;
input [31:0] d0;
output [31:0] a64;
reg [31:0] a64;
output [31:0] b64;
reg [31:0] b64;
output [31:0] c64;
reg [31:0] c64;
output [31:0] d64;
reg [31:0] d64;
wire [31:0] w0_0;
wire [31:0] w0_1;
wire [31:0] w0_2;
wire [31:0] w0_3;
wire [31:0] w0_4;
wire [31:0] w0_5;
wire [31:0] w0_6;
wire [31:0] w0_7;
wire [31:0] w0_8;
wire [31:0] w0_9;
wire [31:0] w0_10;
wire [31:0] w0_11;
wire [31:0] w0_12;
wire [31:0] w0_13;
wire [31:0] w0_14;
wire [31:0] w0_15;
assign w0_0 = wb[31:0];
assign w0_1 = wb[63:32];
assign w0_2 = wb[95:64];
assign w0_3 = wb[127:96];
assign w0_4 = wb[159:128];
assign w0_5 = wb[191:160];
assign w0_6 = wb[223:192];
assign w0_7 = wb[255:224];
assign w0_8 = wb[287:256];
assign w0_9 = wb[319:288];
assign w0_10 = wb[351:320];
assign w0_11 = wb[383:352];
assign w0_12 = wb[415:384];
assign w0_13 = wb[447:416];
assign w0_14 = wb[479:448];
assign w0_15 = wb[511:480];
reg [31:0]
a1, b1, c1, d1,
a2, b2, c2, d2,
a3, b3, c3, d3,
a4, b4, c4, d4,
a5, b5, c5, d5,
a6, b6, c6, d6,
a7, b7, c7, d7,
a8, b8, c8, d8,
a9, b9, c9, d9,
a10, b10, c10, d10,
a11, b11, c11, d11,
a12, b12, c12, d12,
a13, b13, c13, d13,
a14, b14, c14, d14,
a15, b15, c15, d15,
a16, b16, c16, d16,
a17, b17, c17, d17,
a18, b18, c18, d18,
a19, b19, c19, d19,
a20, b20, c20, d20,
a21, b21, c21, d21,
a22, b22, c22, d22,
a23, b23, c23, d23,
a24, b24, c24, d24,
a25, b25, c25, d25,
a26, b26, c26, d26,
a27, b27, c27, d27,
a28, b28, c28, d28,
a29, b29, c29, d29,
a30, b30, c30, d30,
a31, b31, c31, d31,
a32, b32, c32, d32,
a33, b33, c33, d33,
a34, b34, c34, d34,
a35, b35, c35, d35,
a36, b36, c36, d36,
a37, b37, c37, d37,
a38, b38, c38, d38,
a39, b39, c39, d39,
a40, b40, c40, d40,
a41, b41, c41, d41,
a42, b42, c42, d42,
a43, b43, c43, d43,
a44, b44, c44, d44,
a45, b45, c45, d45,
a46, b46, c46, d46,
a47, b47, c47, d47,
a48, b48, c48, d48,
a49, b49, c49, d49,
a50, b50, c50, d50,
a51, b51, c51, d51,
a52, b52, c52, d52,
a53, b53, c53, d53,
a54, b54, c54, d54,
a55, b55, c55, d55,
a56, b56, c56, d56,
a57, b57, c57, d57,
a58, b58, c58, d58,
a59, b59, c59, d59,
a60, b60, c60, d60,
a61, b61, c61, d61,
a62, b62, c62, d62,
a63, b63, c63, d63;
reg [31:0] w1_0;
reg [31:0] w1_1;
reg [31:0] w1_2;
reg [31:0] w1_3;
reg [31:0] w1_4;
reg [31:0] w1_5;
reg [31:0] w1_6;
reg [31:0] w1_7;
reg [31:0] w1_8;
reg [31:0] w1_9;
reg [31:0] w1_10;
reg [31:0] w1_11;
reg [31:0] w1_12;
reg [31:0] w1_13;
reg [31:0] w1_14;
reg [31:0] w1_15;
reg [31:0] w2_0;
reg [31:0] w2_1;
reg [31:0] w2_2;
reg [31:0] w2_3;
reg [31:0] w2_4;
reg [31:0] w2_5;
reg [31:0] w2_6;
reg [31:0] w2_7;
reg [31:0] w2_8;
reg [31:0] w2_9;
reg [31:0] w2_10;
reg [31:0] w2_11;
reg [31:0] w2_12;
reg [31:0] w2_13;
reg [31:0] w2_14;
reg [31:0] w2_15;
reg [31:0] w3_0;
reg [31:0] w3_1;
reg [31:0] w3_2;
reg [31:0] w3_3;
reg [31:0] w3_4;
reg [31:0] w3_5;
reg [31:0] w3_6;
reg [31:0] w3_7;
reg [31:0] w3_8;
reg [31:0] w3_9;
reg [31:0] w3_10;
reg [31:0] w3_11;
reg [31:0] w3_12;
reg [31:0] w3_13;
reg [31:0] w3_14;
reg [31:0] w3_15;
reg [31:0] w4_0;
reg [31:0] w4_1;
reg [31:0] w4_2;
reg [31:0] w4_3;
reg [31:0] w4_4;
reg [31:0] w4_5;
reg [31:0] w4_6;
reg [31:0] w4_7;
reg [31:0] w4_8;
reg [31:0] w4_9;
reg [31:0] w4_10;
reg [31:0] w4_11;
reg [31:0] w4_12;
reg [31:0] w4_13;
reg [31:0] w4_14;
reg [31:0] w4_15;
reg [31:0] w5_0;
reg [31:0] w5_1;
reg [31:0] w5_2;
reg [31:0] w5_3;
reg [31:0] w5_4;
reg [31:0] w5_5;
reg [31:0] w5_6;
reg [31:0] w5_7;
reg [31:0] w5_8;
reg [31:0] w5_9;
reg [31:0] w5_10;
reg [31:0] w5_11;
reg [31:0] w5_12;
reg [31:0] w5_13;
reg [31:0] w5_14;
reg [31:0] w5_15;
reg [31:0] w6_0;
reg [31:0] w6_1;
reg [31:0] w6_2;
reg [31:0] w6_3;
reg [31:0] w6_4;
reg [31:0] w6_5;
reg [31:0] w6_6;
reg [31:0] w6_7;
reg [31:0] w6_8;
reg [31:0] w6_9;
reg [31:0] w6_10;
reg [31:0] w6_11;
reg [31:0] w6_12;
reg [31:0] w6_13;
reg [31:0] w6_14;
reg [31:0] w6_15;
reg [31:0] w7_0;
reg [31:0] w7_1;
reg [31:0] w7_2;
reg [31:0] w7_3;
reg [31:0] w7_4;
reg [31:0] w7_5;
reg [31:0] w7_6;
reg [31:0] w7_7;
reg [31:0] w7_8;
reg [31:0] w7_9;
reg [31:0] w7_10;
reg [31:0] w7_11;
reg [31:0] w7_12;
reg [31:0] w7_13;
reg [31:0] w7_14;
reg [31:0] w7_15;
reg [31:0] w8_0;
reg [31:0] w8_1;
reg [31:0] w8_2;
reg [31:0] w8_3;
reg [31:0] w8_4;
reg [31:0] w8_5;
reg [31:0] w8_6;
reg [31:0] w8_7;
reg [31:0] w8_8;
reg [31:0] w8_9;
reg [31:0] w8_10;
reg [31:0] w8_11;
reg [31:0] w8_12;
reg [31:0] w8_13;
reg [31:0] w8_14;
reg [31:0] w8_15;
reg [31:0] w9_0;
reg [31:0] w9_1;
reg [31:0] w9_2;
reg [31:0] w9_3;
reg [31:0] w9_4;
reg [31:0] w9_5;
reg [31:0] w9_6;
reg [31:0] w9_7;
reg [31:0] w9_8;
reg [31:0] w9_9;
reg [31:0] w9_10;
reg [31:0] w9_11;
reg [31:0] w9_12;
reg [31:0] w9_13;
reg [31:0] w9_14;
reg [31:0] w9_15;
reg [31:0] w10_0;
reg [31:0] w10_1;
reg [31:0] w10_2;
reg [31:0] w10_3;
reg [31:0] w10_4;
reg [31:0] w10_5;
reg [31:0] w10_6;
reg [31:0] w10_7;
reg [31:0] w10_8;
reg [31:0] w10_9;
reg [31:0] w10_10;
reg [31:0] w10_11;
reg [31:0] w10_12;
reg [31:0] w10_13;
reg [31:0] w10_14;
reg [31:0] w10_15;
reg [31:0] w11_0;
reg [31:0] w11_1;
reg [31:0] w11_2;
reg [31:0] w11_3;
reg [31:0] w11_4;
reg [31:0] w11_5;
reg [31:0] w11_6;
reg [31:0] w11_7;
reg [31:0] w11_8;
reg [31:0] w11_9;
reg [31:0] w11_10;
reg [31:0] w11_11;
reg [31:0] w11_12;
reg [31:0] w11_13;
reg [31:0] w11_14;
reg [31:0] w11_15;
reg [31:0] w12_0;
reg [31:0] w12_1;
reg [31:0] w12_2;
reg [31:0] w12_3;
reg [31:0] w12_4;
reg [31:0] w12_5;
reg [31:0] w12_6;
reg [31:0] w12_7;
reg [31:0] w12_8;
reg [31:0] w12_9;
reg [31:0] w12_10;
reg [31:0] w12_11;
reg [31:0] w12_12;
reg [31:0] w12_13;
reg [31:0] w12_14;
reg [31:0] w12_15;
reg [31:0] w13_0;
reg [31:0] w13_1;
reg [31:0] w13_2;
reg [31:0] w13_3;
reg [31:0] w13_4;
reg [31:0] w13_5;
reg [31:0] w13_6;
reg [31:0] w13_7;
reg [31:0] w13_8;
reg [31:0] w13_9;
reg [31:0] w13_10;
reg [31:0] w13_11;
reg [31:0] w13_12;
reg [31:0] w13_13;
reg [31:0] w13_14;
reg [31:0] w13_15;
reg [31:0] w14_0;
reg [31:0] w14_1;
reg [31:0] w14_2;
reg [31:0] w14_3;
reg [31:0] w14_4;
reg [31:0] w14_5;
reg [31:0] w14_6;
reg [31:0] w14_7;
reg [31:0] w14_8;
reg [31:0] w14_9;
reg [31:0] w14_10;
reg [31:0] w14_11;
reg [31:0] w14_12;
reg [31:0] w14_13;
reg [31:0] w14_14;
reg [31:0] w14_15;
reg [31:0] w15_0;
reg [31:0] w15_1;
reg [31:0] w15_2;
reg [31:0] w15_3;
reg [31:0] w15_4;
reg [31:0] w15_5;
reg [31:0] w15_6;
reg [31:0] w15_7;
reg [31:0] w15_8;
reg [31:0] w15_9;
reg [31:0] w15_10;
reg [31:0] w15_11;
reg [31:0] w15_12;
reg [31:0] w15_13;
reg [31:0] w15_14;
reg [31:0] w15_15;
reg [31:0] w16_0;
reg [31:0] w16_1;
reg [31:0] w16_2;
reg [31:0] w16_3;
reg [31:0] w16_4;
reg [31:0] w16_5;
reg [31:0] w16_6;
reg [31:0] w16_7;
reg [31:0] w16_8;
reg [31:0] w16_9;
reg [31:0] w16_10;
reg [31:0] w16_11;
reg [31:0] w16_12;
reg [31:0] w16_13;
reg [31:0] w16_14;
reg [31:0] w16_15;
reg [31:0] w17_0;
reg [31:0] w17_1;
reg [31:0] w17_2;
reg [31:0] w17_3;
reg [31:0] w17_4;
reg [31:0] w17_5;
reg [31:0] w17_6;
reg [31:0] w17_7;
reg [31:0] w17_8;
reg [31:0] w17_9;
reg [31:0] w17_10;
reg [31:0] w17_11;
reg [31:0] w17_12;
reg [31:0] w17_13;
reg [31:0] w17_14;
reg [31:0] w17_15;
reg [31:0] w18_0;
reg [31:0] w18_1;
reg [31:0] w18_2;
reg [31:0] w18_3;
reg [31:0] w18_4;
reg [31:0] w18_5;
reg [31:0] w18_6;
reg [31:0] w18_7;
reg [31:0] w18_8;
reg [31:0] w18_9;
reg [31:0] w18_10;
reg [31:0] w18_11;
reg [31:0] w18_12;
reg [31:0] w18_13;
reg [31:0] w18_14;
reg [31:0] w18_15;
reg [31:0] w19_0;
reg [31:0] w19_1;
reg [31:0] w19_2;
reg [31:0] w19_3;
reg [31:0] w19_4;
reg [31:0] w19_5;
reg [31:0] w19_6;
reg [31:0] w19_7;
reg [31:0] w19_8;
reg [31:0] w19_9;
reg [31:0] w19_10;
reg [31:0] w19_11;
reg [31:0] w19_12;
reg [31:0] w19_13;
reg [31:0] w19_14;
reg [31:0] w19_15;
reg [31:0] w20_0;
reg [31:0] w20_1;
reg [31:0] w20_2;
reg [31:0] w20_3;
reg [31:0] w20_4;
reg [31:0] w20_5;
reg [31:0] w20_6;
reg [31:0] w20_7;
reg [31:0] w20_8;
reg [31:0] w20_9;
reg [31:0] w20_10;
reg [31:0] w20_11;
reg [31:0] w20_12;
reg [31:0] w20_13;
reg [31:0] w20_14;
reg [31:0] w20_15;
reg [31:0] w21_0;
reg [31:0] w21_1;
reg [31:0] w21_2;
reg [31:0] w21_3;
reg [31:0] w21_4;
reg [31:0] w21_5;
reg [31:0] w21_6;
reg [31:0] w21_7;
reg [31:0] w21_8;
reg [31:0] w21_9;
reg [31:0] w21_10;
reg [31:0] w21_11;
reg [31:0] w21_12;
reg [31:0] w21_13;
reg [31:0] w21_14;
reg [31:0] w21_15;
reg [31:0] w22_0;
reg [31:0] w22_1;
reg [31:0] w22_2;
reg [31:0] w22_3;
reg [31:0] w22_4;
reg [31:0] w22_5;
reg [31:0] w22_6;
reg [31:0] w22_7;
reg [31:0] w22_8;
reg [31:0] w22_9;
reg [31:0] w22_10;
reg [31:0] w22_11;
reg [31:0] w22_12;
reg [31:0] w22_13;
reg [31:0] w22_14;
reg [31:0] w22_15;
reg [31:0] w23_0;
reg [31:0] w23_1;
reg [31:0] w23_2;
reg [31:0] w23_3;
reg [31:0] w23_4;
reg [31:0] w23_5;
reg [31:0] w23_6;
reg [31:0] w23_7;
reg [31:0] w23_8;
reg [31:0] w23_9;
reg [31:0] w23_10;
reg [31:0] w23_11;
reg [31:0] w23_12;
reg [31:0] w23_13;
reg [31:0] w23_14;
reg [31:0] w23_15;
reg [31:0] w24_0;
reg [31:0] w24_1;
reg [31:0] w24_2;
reg [31:0] w24_3;
reg [31:0] w24_4;
reg [31:0] w24_5;
reg [31:0] w24_6;
reg [31:0] w24_7;
reg [31:0] w24_8;
reg [31:0] w24_9;
reg [31:0] w24_10;
reg [31:0] w24_11;
reg [31:0] w24_12;
reg [31:0] w24_13;
reg [31:0] w24_14;
reg [31:0] w24_15;
reg [31:0] w25_0;
reg [31:0] w25_1;
reg [31:0] w25_2;
reg [31:0] w25_3;
reg [31:0] w25_4;
reg [31:0] w25_5;
reg [31:0] w25_6;
reg [31:0] w25_7;
reg [31:0] w25_8;
reg [31:0] w25_9;
reg [31:0] w25_10;
reg [31:0] w25_11;
reg [31:0] w25_12;
reg [31:0] w25_13;
reg [31:0] w25_14;
reg [31:0] w25_15;
reg [31:0] w26_0;
reg [31:0] w26_1;
reg [31:0] w26_2;
reg [31:0] w26_3;
reg [31:0] w26_4;
reg [31:0] w26_5;
reg [31:0] w26_6;
reg [31:0] w26_7;
reg [31:0] w26_8;
reg [31:0] w26_9;
reg [31:0] w26_10;
reg [31:0] w26_11;
reg [31:0] w26_12;
reg [31:0] w26_13;
reg [31:0] w26_14;
reg [31:0] w26_15;
reg [31:0] w27_0;
reg [31:0] w27_1;
reg [31:0] w27_2;
reg [31:0] w27_3;
reg [31:0] w27_4;
reg [31:0] w27_5;
reg [31:0] w27_6;
reg [31:0] w27_7;
reg [31:0] w27_8;
reg [31:0] w27_9;
reg [31:0] w27_10;
reg [31:0] w27_11;
reg [31:0] w27_12;
reg [31:0] w27_13;
reg [31:0] w27_14;
reg [31:0] w27_15;
reg [31:0] w28_0;
reg [31:0] w28_1;
reg [31:0] w28_2;
reg [31:0] w28_3;
reg [31:0] w28_4;
reg [31:0] w28_5;
reg [31:0] w28_6;
reg [31:0] w28_7;
reg [31:0] w28_8;
reg [31:0] w28_9;
reg [31:0] w28_10;
reg [31:0] w28_11;
reg [31:0] w28_12;
reg [31:0] w28_13;
reg [31:0] w28_14;
reg [31:0] w28_15;
reg [31:0] w29_0;
reg [31:0] w29_1;
reg [31:0] w29_2;
reg [31:0] w29_3;
reg [31:0] w29_4;
reg [31:0] w29_5;
reg [31:0] w29_6;
reg [31:0] w29_7;
reg [31:0] w29_8;
reg [31:0] w29_9;
reg [31:0] w29_10;
reg [31:0] w29_11;
reg [31:0] w29_12;
reg [31:0] w29_13;
reg [31:0] w29_14;
reg [31:0] w29_15;
reg [31:0] w30_0;
reg [31:0] w30_1;
reg [31:0] w30_2;
reg [31:0] w30_3;
reg [31:0] w30_4;
reg [31:0] w30_5;
reg [31:0] w30_6;
reg [31:0] w30_7;
reg [31:0] w30_8;
reg [31:0] w30_9;
reg [31:0] w30_10;
reg [31:0] w30_11;
reg [31:0] w30_12;
reg [31:0] w30_13;
reg [31:0] w30_14;
reg [31:0] w30_15;
reg [31:0] w31_0;
reg [31:0] w31_1;
reg [31:0] w31_2;
reg [31:0] w31_3;
reg [31:0] w31_4;
reg [31:0] w31_5;
reg [31:0] w31_6;
reg [31:0] w31_7;
reg [31:0] w31_8;
reg [31:0] w31_9;
reg [31:0] w31_10;
reg [31:0] w31_11;
reg [31:0] w31_12;
reg [31:0] w31_13;
reg [31:0] w31_14;
reg [31:0] w31_15;
reg [31:0] w32_0;
reg [31:0] w32_1;
reg [31:0] w32_2;
reg [31:0] w32_3;
reg [31:0] w32_4;
reg [31:0] w32_5;
reg [31:0] w32_6;
reg [31:0] w32_7;
reg [31:0] w32_8;
reg [31:0] w32_9;
reg [31:0] w32_10;
reg [31:0] w32_11;
reg [31:0] w32_12;
reg [31:0] w32_13;
reg [31:0] w32_14;
reg [31:0] w32_15;
reg [31:0] w33_0;
reg [31:0] w33_1;
reg [31:0] w33_2;
reg [31:0] w33_3;
reg [31:0] w33_4;
reg [31:0] w33_5;
reg [31:0] w33_6;
reg [31:0] w33_7;
reg [31:0] w33_8;
reg [31:0] w33_9;
reg [31:0] w33_10;
reg [31:0] w33_11;
reg [31:0] w33_12;
reg [31:0] w33_13;
reg [31:0] w33_14;
reg [31:0] w33_15;
reg [31:0] w34_0;
reg [31:0] w34_1;
reg [31:0] w34_2;
reg [31:0] w34_3;
reg [31:0] w34_4;
reg [31:0] w34_5;
reg [31:0] w34_6;
reg [31:0] w34_7;
reg [31:0] w34_8;
reg [31:0] w34_9;
reg [31:0] w34_10;
reg [31:0] w34_11;
reg [31:0] w34_12;
reg [31:0] w34_13;
reg [31:0] w34_14;
reg [31:0] w34_15;
reg [31:0] w35_0;
reg [31:0] w35_1;
reg [31:0] w35_2;
reg [31:0] w35_3;
reg [31:0] w35_4;
reg [31:0] w35_5;
reg [31:0] w35_6;
reg [31:0] w35_7;
reg [31:0] w35_8;
reg [31:0] w35_9;
reg [31:0] w35_10;
reg [31:0] w35_11;
reg [31:0] w35_12;
reg [31:0] w35_13;
reg [31:0] w35_14;
reg [31:0] w35_15;
reg [31:0] w36_0;
reg [31:0] w36_1;
reg [31:0] w36_2;
reg [31:0] w36_3;
reg [31:0] w36_4;
reg [31:0] w36_5;
reg [31:0] w36_6;
reg [31:0] w36_7;
reg [31:0] w36_8;
reg [31:0] w36_9;
reg [31:0] w36_10;
reg [31:0] w36_11;
reg [31:0] w36_12;
reg [31:0] w36_13;
reg [31:0] w36_14;
reg [31:0] w36_15;
reg [31:0] w37_0;
reg [31:0] w37_1;
reg [31:0] w37_2;
reg [31:0] w37_3;
reg [31:0] w37_4;
reg [31:0] w37_5;
reg [31:0] w37_6;
reg [31:0] w37_7;
reg [31:0] w37_8;
reg [31:0] w37_9;
reg [31:0] w37_10;
reg [31:0] w37_11;
reg [31:0] w37_12;
reg [31:0] w37_13;
reg [31:0] w37_14;
reg [31:0] w37_15;
reg [31:0] w38_0;
reg [31:0] w38_1;
reg [31:0] w38_2;
reg [31:0] w38_3;
reg [31:0] w38_4;
reg [31:0] w38_5;
reg [31:0] w38_6;
reg [31:0] w38_7;
reg [31:0] w38_8;
reg [31:0] w38_9;
reg [31:0] w38_10;
reg [31:0] w38_11;
reg [31:0] w38_12;
reg [31:0] w38_13;
reg [31:0] w38_14;
reg [31:0] w38_15;
reg [31:0] w39_0;
reg [31:0] w39_1;
reg [31:0] w39_2;
reg [31:0] w39_3;
reg [31:0] w39_4;
reg [31:0] w39_5;
reg [31:0] w39_6;
reg [31:0] w39_7;
reg [31:0] w39_8;
reg [31:0] w39_9;
reg [31:0] w39_10;
reg [31:0] w39_11;
reg [31:0] w39_12;
reg [31:0] w39_13;
reg [31:0] w39_14;
reg [31:0] w39_15;
reg [31:0] w40_0;
reg [31:0] w40_1;
reg [31:0] w40_2;
reg [31:0] w40_3;
reg [31:0] w40_4;
reg [31:0] w40_5;
reg [31:0] w40_6;
reg [31:0] w40_7;
reg [31:0] w40_8;
reg [31:0] w40_9;
reg [31:0] w40_10;
reg [31:0] w40_11;
reg [31:0] w40_12;
reg [31:0] w40_13;
reg [31:0] w40_14;
reg [31:0] w40_15;
reg [31:0] w41_0;
reg [31:0] w41_1;
reg [31:0] w41_2;
reg [31:0] w41_3;
reg [31:0] w41_4;
reg [31:0] w41_5;
reg [31:0] w41_6;
reg [31:0] w41_7;
reg [31:0] w41_8;
reg [31:0] w41_9;
reg [31:0] w41_10;
reg [31:0] w41_11;
reg [31:0] w41_12;
reg [31:0] w41_13;
reg [31:0] w41_14;
reg [31:0] w41_15;
reg [31:0] w42_0;
reg [31:0] w42_1;
reg [31:0] w42_2;
reg [31:0] w42_3;
reg [31:0] w42_4;
reg [31:0] w42_5;
reg [31:0] w42_6;
reg [31:0] w42_7;
reg [31:0] w42_8;
reg [31:0] w42_9;
reg [31:0] w42_10;
reg [31:0] w42_11;
reg [31:0] w42_12;
reg [31:0] w42_13;
reg [31:0] w42_14;
reg [31:0] w42_15;
reg [31:0] w43_0;
reg [31:0] w43_1;
reg [31:0] w43_2;
reg [31:0] w43_3;
reg [31:0] w43_4;
reg [31:0] w43_5;
reg [31:0] w43_6;
reg [31:0] w43_7;
reg [31:0] w43_8;
reg [31:0] w43_9;
reg [31:0] w43_10;
reg [31:0] w43_11;
reg [31:0] w43_12;
reg [31:0] w43_13;
reg [31:0] w43_14;
reg [31:0] w43_15;
reg [31:0] w44_0;
reg [31:0] w44_1;
reg [31:0] w44_2;
reg [31:0] w44_3;
reg [31:0] w44_4;
reg [31:0] w44_5;
reg [31:0] w44_6;
reg [31:0] w44_7;
reg [31:0] w44_8;
reg [31:0] w44_9;
reg [31:0] w44_10;
reg [31:0] w44_11;
reg [31:0] w44_12;
reg [31:0] w44_13;
reg [31:0] w44_14;
reg [31:0] w44_15;
reg [31:0] w45_0;
reg [31:0] w45_1;
reg [31:0] w45_2;
reg [31:0] w45_3;
reg [31:0] w45_4;
reg [31:0] w45_5;
reg [31:0] w45_6;
reg [31:0] w45_7;
reg [31:0] w45_8;
reg [31:0] w45_9;
reg [31:0] w45_10;
reg [31:0] w45_11;
reg [31:0] w45_12;
reg [31:0] w45_13;
reg [31:0] w45_14;
reg [31:0] w45_15;
reg [31:0] w46_0;
reg [31:0] w46_1;
reg [31:0] w46_2;
reg [31:0] w46_3;
reg [31:0] w46_4;
reg [31:0] w46_5;
reg [31:0] w46_6;
reg [31:0] w46_7;
reg [31:0] w46_8;
reg [31:0] w46_9;
reg [31:0] w46_10;
reg [31:0] w46_11;
reg [31:0] w46_12;
reg [31:0] w46_13;
reg [31:0] w46_14;
reg [31:0] w46_15;
reg [31:0] w47_0;
reg [31:0] w47_1;
reg [31:0] w47_2;
reg [31:0] w47_3;
reg [31:0] w47_4;
reg [31:0] w47_5;
reg [31:0] w47_6;
reg [31:0] w47_7;
reg [31:0] w47_8;
reg [31:0] w47_9;
reg [31:0] w47_10;
reg [31:0] w47_11;
reg [31:0] w47_12;
reg [31:0] w47_13;
reg [31:0] w47_14;
reg [31:0] w47_15;
reg [31:0] w48_0;
reg [31:0] w48_1;
reg [31:0] w48_2;
reg [31:0] w48_3;
reg [31:0] w48_4;
reg [31:0] w48_5;
reg [31:0] w48_6;
reg [31:0] w48_7;
reg [31:0] w48_8;
reg [31:0] w48_9;
reg [31:0] w48_10;
reg [31:0] w48_11;
reg [31:0] w48_12;
reg [31:0] w48_13;
reg [31:0] w48_14;
reg [31:0] w48_15;
reg [31:0] w49_0;
reg [31:0] w49_1;
reg [31:0] w49_2;
reg [31:0] w49_3;
reg [31:0] w49_4;
reg [31:0] w49_5;
reg [31:0] w49_6;
reg [31:0] w49_7;
reg [31:0] w49_8;
reg [31:0] w49_9;
reg [31:0] w49_10;
reg [31:0] w49_11;
reg [31:0] w49_12;
reg [31:0] w49_13;
reg [31:0] w49_14;
reg [31:0] w49_15;
reg [31:0] w50_0;
reg [31:0] w50_1;
reg [31:0] w50_2;
reg [31:0] w50_3;
reg [31:0] w50_4;
reg [31:0] w50_5;
reg [31:0] w50_6;
reg [31:0] w50_7;
reg [31:0] w50_8;
reg [31:0] w50_9;
reg [31:0] w50_10;
reg [31:0] w50_11;
reg [31:0] w50_12;
reg [31:0] w50_13;
reg [31:0] w50_14;
reg [31:0] w50_15;
reg [31:0] w51_0;
reg [31:0] w51_1;
reg [31:0] w51_2;
reg [31:0] w51_3;
reg [31:0] w51_4;
reg [31:0] w51_5;
reg [31:0] w51_6;
reg [31:0] w51_7;
reg [31:0] w51_8;
reg [31:0] w51_9;
reg [31:0] w51_10;
reg [31:0] w51_11;
reg [31:0] w51_12;
reg [31:0] w51_13;
reg [31:0] w51_14;
reg [31:0] w51_15;
reg [31:0] w52_0;
reg [31:0] w52_1;
reg [31:0] w52_2;
reg [31:0] w52_3;
reg [31:0] w52_4;
reg [31:0] w52_5;
reg [31:0] w52_6;
reg [31:0] w52_7;
reg [31:0] w52_8;
reg [31:0] w52_9;
reg [31:0] w52_10;
reg [31:0] w52_11;
reg [31:0] w52_12;
reg [31:0] w52_13;
reg [31:0] w52_14;
reg [31:0] w52_15;
reg [31:0] w53_0;
reg [31:0] w53_1;
reg [31:0] w53_2;
reg [31:0] w53_3;
reg [31:0] w53_4;
reg [31:0] w53_5;
reg [31:0] w53_6;
reg [31:0] w53_7;
reg [31:0] w53_8;
reg [31:0] w53_9;
reg [31:0] w53_10;
reg [31:0] w53_11;
reg [31:0] w53_12;
reg [31:0] w53_13;
reg [31:0] w53_14;
reg [31:0] w53_15;
reg [31:0] w54_0;
reg [31:0] w54_1;
reg [31:0] w54_2;
reg [31:0] w54_3;
reg [31:0] w54_4;
reg [31:0] w54_5;
reg [31:0] w54_6;
reg [31:0] w54_7;
reg [31:0] w54_8;
reg [31:0] w54_9;
reg [31:0] w54_10;
reg [31:0] w54_11;
reg [31:0] w54_12;
reg [31:0] w54_13;
reg [31:0] w54_14;
reg [31:0] w54_15;
reg [31:0] w55_0;
reg [31:0] w55_1;
reg [31:0] w55_2;
reg [31:0] w55_3;
reg [31:0] w55_4;
reg [31:0] w55_5;
reg [31:0] w55_6;
reg [31:0] w55_7;
reg [31:0] w55_8;
reg [31:0] w55_9;
reg [31:0] w55_10;
reg [31:0] w55_11;
reg [31:0] w55_12;
reg [31:0] w55_13;
reg [31:0] w55_14;
reg [31:0] w55_15;
reg [31:0] w56_0;
reg [31:0] w56_1;
reg [31:0] w56_2;
reg [31:0] w56_3;
reg [31:0] w56_4;
reg [31:0] w56_5;
reg [31:0] w56_6;
reg [31:0] w56_7;
reg [31:0] w56_8;
reg [31:0] w56_9;
reg [31:0] w56_10;
reg [31:0] w56_11;
reg [31:0] w56_12;
reg [31:0] w56_13;
reg [31:0] w56_14;
reg [31:0] w56_15;
reg [31:0] w57_0;
reg [31:0] w57_1;
reg [31:0] w57_2;
reg [31:0] w57_3;
reg [31:0] w57_4;
reg [31:0] w57_5;
reg [31:0] w57_6;
reg [31:0] w57_7;
reg [31:0] w57_8;
reg [31:0] w57_9;
reg [31:0] w57_10;
reg [31:0] w57_11;
reg [31:0] w57_12;
reg [31:0] w57_13;
reg [31:0] w57_14;
reg [31:0] w57_15;
reg [31:0] w58_0;
reg [31:0] w58_1;
reg [31:0] w58_2;
reg [31:0] w58_3;
reg [31:0] w58_4;
reg [31:0] w58_5;
reg [31:0] w58_6;
reg [31:0] w58_7;
reg [31:0] w58_8;
reg [31:0] w58_9;
reg [31:0] w58_10;
reg [31:0] w58_11;
reg [31:0] w58_12;
reg [31:0] w58_13;
reg [31:0] w58_14;
reg [31:0] w58_15;
reg [31:0] w59_0;
reg [31:0] w59_1;
reg [31:0] w59_2;
reg [31:0] w59_3;
reg [31:0] w59_4;
reg [31:0] w59_5;
reg [31:0] w59_6;
reg [31:0] w59_7;
reg [31:0] w59_8;
reg [31:0] w59_9;
reg [31:0] w59_10;
reg [31:0] w59_11;
reg [31:0] w59_12;
reg [31:0] w59_13;
reg [31:0] w59_14;
reg [31:0] w59_15;
reg [31:0] w60_0;
reg [31:0] w60_1;
reg [31:0] w60_2;
reg [31:0] w60_3;
reg [31:0] w60_4;
reg [31:0] w60_5;
reg [31:0] w60_6;
reg [31:0] w60_7;
reg [31:0] w60_8;
reg [31:0] w60_9;
reg [31:0] w60_10;
reg [31:0] w60_11;
reg [31:0] w60_12;
reg [31:0] w60_13;
reg [31:0] w60_14;
reg [31:0] w60_15;
reg [31:0] w61_0;
reg [31:0] w61_1;
reg [31:0] w61_2;
reg [31:0] w61_3;
reg [31:0] w61_4;
reg [31:0] w61_5;
reg [31:0] w61_6;
reg [31:0] w61_7;
reg [31:0] w61_8;
reg [31:0] w61_9;
reg [31:0] w61_10;
reg [31:0] w61_11;
reg [31:0] w61_12;
reg [31:0] w61_13;
reg [31:0] w61_14;
reg [31:0] w61_15;
reg [31:0] w62_0;
reg [31:0] w62_1;
reg [31:0] w62_2;
reg [31:0] w62_3;
reg [31:0] w62_4;
reg [31:0] w62_5;
reg [31:0] w62_6;
reg [31:0] w62_7;
reg [31:0] w62_8;
reg [31:0] w62_9;
reg [31:0] w62_10;
reg [31:0] w62_11;
reg [31:0] w62_12;
reg [31:0] w62_13;
reg [31:0] w62_14;
reg [31:0] w62_15;
reg [31:0] w63_0;
reg [31:0] w63_1;
reg [31:0] w63_2;
reg [31:0] w63_3;
reg [31:0] w63_4;
reg [31:0] w63_5;
reg [31:0] w63_6;
reg [31:0] w63_7;
reg [31:0] w63_8;
reg [31:0] w63_9;
reg [31:0] w63_10;
reg [31:0] w63_11;
reg [31:0] w63_12;
reg [31:0] w63_13;
reg [31:0] w63_14;
reg [31:0] w63_15;
always @(posedge clk)
begin
a1 <= d0;
d1 <= c0;
c1 <= b0;
b1 <= b0 + ((((a0 + ((b0 & c0) | ((~b0) & d0)) + 'hd76aa478 + w0_0) << 7) | ((a0 + ((b0 & c0) | ((~b0) & d0)) + 'hd76aa478 + w0_0) >> (32 - 7))));
w1_0 <= w0_0;
w1_1 <= w0_1;
w1_2 <= w0_2;
w1_3 <= w0_3;
w1_4 <= w0_4;
w1_5 <= w0_5;
w1_6 <= w0_6;
w1_7 <= w0_7;
w1_8 <= w0_8;
w1_9 <= w0_9;
w1_10 <= w0_10;
w1_11 <= w0_11;
w1_12 <= w0_12;
w1_13 <= w0_13;
w1_14 <= w0_14;
w1_15 <= w0_15;
a2 <= d1;
d2 <= c1;
c2 <= b1;
b2 <= b1 + (((a1 + ((b1 & c1) | ((~b1) & d1)) + 'he8c7b756 + w1_1) << 12) | ((a1 + ((b1 & c1) | ((~b1) & d1)) + 'he8c7b756 + w1_1) >> (32 - 12)));
w2_0 <= w1_0;
w2_1 <= w1_1;
w2_2 <= w1_2;
w2_3 <= w1_3;
w2_4 <= w1_4;
w2_5 <= w1_5;
w2_6 <= w1_6;
w2_7 <= w1_7;
w2_8 <= w1_8;
w2_9 <= w1_9;
w2_10 <= w1_10;
w2_11 <= w1_11;
w2_12 <= w1_12;
w2_13 <= w1_13;
w2_14 <= w1_14;
w2_15 <= w1_15;
a3 <= d2;
d3 <= c2;
c3 <= b2;
b3 <= b2 + (((a2 + ((b2 & c2) | ((~b2) & d2)) + 'h242070db + w2_2) << 17) | ((a2 + ((b2 & c2) | ((~b2) & d2)) + 'h242070db + w2_2) >> (32 - 17)));
w3_0 <= w2_0;
w3_1 <= w2_1;
w3_2 <= w2_2;
w3_3 <= w2_3;
w3_4 <= w2_4;
w3_5 <= w2_5;
w3_6 <= w2_6;
w3_7 <= w2_7;
w3_8 <= w2_8;
w3_9 <= w2_9;
w3_10 <= w2_10;
w3_11 <= w2_11;
w3_12 <= w2_12;
w3_13 <= w2_13;
w3_14 <= w2_14;
w3_15 <= w2_15;
a4 <= d3;
d4 <= c3;
c4 <= b3;
b4 <= b3 + (((a3 + ((b3 & c3) | ((~b3) & d3)) + 'hc1bdceee + w3_3) << 22) | ((a3 + ((b3 & c3) | ((~b3) & d3)) + 'hc1bdceee + w3_3) >> (32 - 22)));
w4_0 <= w3_0;
w4_1 <= w3_1;
w4_2 <= w3_2;
w4_3 <= w3_3;
w4_4 <= w3_4;
w4_5 <= w3_5;
w4_6 <= w3_6;
w4_7 <= w3_7;
w4_8 <= w3_8;
w4_9 <= w3_9;
w4_10 <= w3_10;
w4_11 <= w3_11;
w4_12 <= w3_12;
w4_13 <= w3_13;
w4_14 <= w3_14;
w4_15 <= w3_15;
a5 <= d4;
d5 <= c4;
c5 <= b4;
b5 <= b4 + (((a4 + ((b4 & c4) | ((~b4) & d4)) + 'hf57c0faf + w4_4) << 7) | ((a4 + ((b4 & c4) | ((~b4) & d4)) + 'hf57c0faf + w4_4) >> (32 - 7)));
w5_0 <= w4_0;
w5_1 <= w4_1;
w5_2 <= w4_2;
w5_3 <= w4_3;
w5_4 <= w4_4;
w5_5 <= w4_5;
w5_6 <= w4_6;
w5_7 <= w4_7;
w5_8 <= w4_8;
w5_9 <= w4_9;
w5_10 <= w4_10;
w5_11 <= w4_11;
w5_12 <= w4_12;
w5_13 <= w4_13;
w5_14 <= w4_14;
w5_15 <= w4_15;
a6 <= d5;
d6 <= c5;
c6 <= b5;
b6 <= b5 + (((a5 + ((b5 & c5) | ((~b5) & d5)) + 'h4787c62a + w5_5) << 12) | ((a5 + ((b5 & c5) | ((~b5) & d5)) + 'h4787c62a + w5_5) >> (32 - 12)));
w6_0 <= w5_0;
w6_1 <= w5_1;
w6_2 <= w5_2;
w6_3 <= w5_3;
w6_4 <= w5_4;
w6_5 <= w5_5;
w6_6 <= w5_6;
w6_7 <= w5_7;
w6_8 <= w5_8;
w6_9 <= w5_9;
w6_10 <= w5_10;
w6_11 <= w5_11;
w6_12 <= w5_12;
w6_13 <= w5_13;
w6_14 <= w5_14;
w6_15 <= w5_15;
a7 <= d6;
d7 <= c6;
c7 <= b6;
b7 <= b6 + (((a6 + ((b6 & c6) | ((~b6) & d6)) + 'ha8304613 + w6_6) << 17) | ((a6 + ((b6 & c6) | ((~b6) & d6)) + 'ha8304613 + w6_6) >> (32 - 17)));
w7_0 <= w6_0;
w7_1 <= w6_1;
w7_2 <= w6_2;
w7_3 <= w6_3;
w7_4 <= w6_4;
w7_5 <= w6_5;
w7_6 <= w6_6;
w7_7 <= w6_7;
w7_8 <= w6_8;
w7_9 <= w6_9;
w7_10 <= w6_10;
w7_11 <= w6_11;
w7_12 <= w6_12;
w7_13 <= w6_13;
w7_14 <= w6_14;
w7_15 <= w6_15;
a8 <= d7;
d8 <= c7;
c8 <= b7;
b8 <= b7 + (((a7 + ((b7 & c7) | ((~b7) & d7)) + 'hfd469501 + w7_7) << 22) | ((a7 + ((b7 & c7) | ((~b7) & d7)) + 'hfd469501 + w7_7) >> (32 - 22)));
w8_0 <= w7_0;
w8_1 <= w7_1;
w8_2 <= w7_2;
w8_3 <= w7_3;
w8_4 <= w7_4;
w8_5 <= w7_5;
w8_6 <= w7_6;
w8_7 <= w7_7;
w8_8 <= w7_8;
w8_9 <= w7_9;
w8_10 <= w7_10;
w8_11 <= w7_11;
w8_12 <= w7_12;
w8_13 <= w7_13;
w8_14 <= w7_14;
w8_15 <= w7_15;
a9 <= d8;
d9 <= c8;
c9 <= b8;
b9 <= b8 + (((a8 + ((b8 & c8) | ((~b8) & d8)) + 'h698098d8 + w8_8) << 7) | ((a8 + ((b8 & c8) | ((~b8) & d8)) + 'h698098d8 + w8_8) >> (32 - 7)));
w9_0 <= w8_0;
w9_1 <= w8_1;
w9_2 <= w8_2;
w9_3 <= w8_3;
w9_4 <= w8_4;
w9_5 <= w8_5;
w9_6 <= w8_6;
w9_7 <= w8_7;
w9_8 <= w8_8;
w9_9 <= w8_9;
w9_10 <= w8_10;
w9_11 <= w8_11;
w9_12 <= w8_12;
w9_13 <= w8_13;
w9_14 <= w8_14;
w9_15 <= w8_15;
a10 <= d9;
d10 <= c9;
c10 <= b9;
b10 <= b9 + (((a9 + ((b9 & c9) | ((~b9) & d9)) + 'h8b44f7af + w9_9) << 12) | ((a9 + ((b9 & c9) | ((~b9) & d9)) + 'h8b44f7af + w9_9) >> (32 - 12)));
w10_0 <= w9_0;
w10_1 <= w9_1;
w10_2 <= w9_2;
w10_3 <= w9_3;
w10_4 <= w9_4;
w10_5 <= w9_5;
w10_6 <= w9_6;
w10_7 <= w9_7;
w10_8 <= w9_8;
w10_9 <= w9_9;
w10_10 <= w9_10;
w10_11 <= w9_11;
w10_12 <= w9_12;
w10_13 <= w9_13;
w10_14 <= w9_14;
w10_15 <= w9_15;
a11 <= d10;
d11 <= c10;
c11 <= b10;
b11 <= b10 + (((a10 + ((b10 & c10) | ((~b10) & d10)) + 'hffff5bb1 + w10_10) << 17) | ((a10 + ((b10 & c10) | ((~b10) & d10)) + 'hffff5bb1 + w10_10) >> (32 - 17)));
w11_0 <= w10_0;
w11_1 <= w10_1;
w11_2 <= w10_2;
w11_3 <= w10_3;
w11_4 <= w10_4;
w11_5 <= w10_5;
w11_6 <= w10_6;
w11_7 <= w10_7;
w11_8 <= w10_8;
w11_9 <= w10_9;
w11_10 <= w10_10;
w11_11 <= w10_11;
w11_12 <= w10_12;
w11_13 <= w10_13;
w11_14 <= w10_14;
w11_15 <= w10_15;
a12 <= d11;
d12 <= c11;
c12 <= b11;
b12 <= b11 + (((a11 + ((b11 & c11) | ((~b11) & d11)) + 'h895cd7be + w11_11) << 22) | ((a11 + ((b11 & c11) | ((~b11) & d11)) + 'h895cd7be + w11_11) >> (32 - 22)));
w12_0 <= w11_0;
w12_1 <= w11_1;
w12_2 <= w11_2;
w12_3 <= w11_3;
w12_4 <= w11_4;
w12_5 <= w11_5;
w12_6 <= w11_6;
w12_7 <= w11_7;
w12_8 <= w11_8;
w12_9 <= w11_9;
w12_10 <= w11_10;
w12_11 <= w11_11;
w12_12 <= w11_12;
w12_13 <= w11_13;
w12_14 <= w11_14;
w12_15 <= w11_15;
a13 <= d12;
d13 <= c12;
c13 <= b12;
b13 <= b12 + (((a12 + ((b12 & c12) | ((~b12) & d12)) + 'h6b901122 + w12_12) << 7) | ((a12 + ((b12 & c12) | ((~b12) & d12)) + 'h6b901122 + w12_12) >> (32 - 7)));
w13_0 <= w12_0;
w13_1 <= w12_1;
w13_2 <= w12_2;
w13_3 <= w12_3;
w13_4 <= w12_4;
w13_5 <= w12_5;
w13_6 <= w12_6;
w13_7 <= w12_7;
w13_8 <= w12_8;
w13_9 <= w12_9;
w13_10 <= w12_10;
w13_11 <= w12_11;
w13_12 <= w12_12;
w13_13 <= w12_13;
w13_14 <= w12_14;
w13_15 <= w12_15;
a14 <= d13;
d14 <= c13;
c14 <= b13;
b14 <= b13 + (((a13 + ((b13 & c13) | ((~b13) & d13)) + 'hfd987193 + w13_13) << 12) | ((a13 + ((b13 & c13) | ((~b13) & d13)) + 'hfd987193 + w13_13) >> (32 - 12)));
w14_0 <= w13_0;
w14_1 <= w13_1;
w14_2 <= w13_2;
w14_3 <= w13_3;
w14_4 <= w13_4;
w14_5 <= w13_5;
w14_6 <= w13_6;
w14_7 <= w13_7;
w14_8 <= w13_8;
w14_9 <= w13_9;
w14_10 <= w13_10;
w14_11 <= w13_11;
w14_12 <= w13_12;
w14_13 <= w13_13;
w14_14 <= w13_14;
w14_15 <= w13_15;
a15 <= d14;
d15 <= c14;
c15 <= b14;
b15 <= b14 + (((a14 + ((b14 & c14) | ((~b14) & d14)) + 'ha679438e + w14_14) << 17) | ((a14 + ((b14 & c14) | ((~b14) & d14)) + 'ha679438e + w14_14) >> (32 - 17)));
w15_0 <= w14_0;
w15_1 <= w14_1;
w15_2 <= w14_2;
w15_3 <= w14_3;
w15_4 <= w14_4;
w15_5 <= w14_5;
w15_6 <= w14_6;
w15_7 <= w14_7;
w15_8 <= w14_8;
w15_9 <= w14_9;
w15_10 <= w14_10;
w15_11 <= w14_11;
w15_12 <= w14_12;
w15_13 <= w14_13;
w15_14 <= w14_14;
w15_15 <= w14_15;
a16 <= d15;
d16 <= c15;
c16 <= b15;
b16 <= b15 + (((a15 + ((b15 & c15) | ((~b15) & d15)) + 'h49b40821 + w15_15) << 22) | ((a15 + ((b15 & c15) | ((~b15) & d15)) + 'h49b40821 + w15_15) >> (32 - 22)));
w16_0 <= w15_0;
w16_1 <= w15_1;
w16_2 <= w15_2;
w16_3 <= w15_3;
w16_4 <= w15_4;
w16_5 <= w15_5;
w16_6 <= w15_6;
w16_7 <= w15_7;
w16_8 <= w15_8;
w16_9 <= w15_9;
w16_10 <= w15_10;
w16_11 <= w15_11;
w16_12 <= w15_12;
w16_13 <= w15_13;
w16_14 <= w15_14;
w16_15 <= w15_15;
a17 <= d16;
d17 <= c16;
c17 <= b16;
b17 <= b16 + (((a16 + ((d16 & b16) | ((~d16) & c16)) + 'hf61e2562 + w16_1) << 5) | ((a16 + ((d16 & b16) | ((~d16) & c16)) + 'hf61e2562 + w16_1) >> (32 - 5)));
w17_0 <= w16_0;
w17_1 <= w16_1;
w17_2 <= w16_2;
w17_3 <= w16_3;
w17_4 <= w16_4;
w17_5 <= w16_5;
w17_6 <= w16_6;
w17_7 <= w16_7;
w17_8 <= w16_8;
w17_9 <= w16_9;
w17_10 <= w16_10;
w17_11 <= w16_11;
w17_12 <= w16_12;
w17_13 <= w16_13;
w17_14 <= w16_14;
w17_15 <= w16_15;
a18 <= d17;
d18 <= c17;
c18 <= b17;
b18 <= b17 + (((a17 + ((d17 & b17) | ((~d17) & c17)) + 'hc040b340 + w17_6) << 9) | ((a17 + ((d17 & b17) | ((~d17) & c17)) + 'hc040b340 + w17_6) >> (32 - 9)));
w18_0 <= w17_0;
w18_1 <= w17_1;
w18_2 <= w17_2;
w18_3 <= w17_3;
w18_4 <= w17_4;
w18_5 <= w17_5;
w18_6 <= w17_6;
w18_7 <= w17_7;
w18_8 <= w17_8;
w18_9 <= w17_9;
w18_10 <= w17_10;
w18_11 <= w17_11;
w18_12 <= w17_12;
w18_13 <= w17_13;
w18_14 <= w17_14;
w18_15 <= w17_15;
a19 <= d18;
d19 <= c18;
c19 <= b18;
b19 <= b18 + (((a18 + ((d18 & b18) | ((~d18) & c18)) + 'h265e5a51 + w18_11) << 14) | ((a18 + ((d18 & b18) | ((~d18) & c18)) + 'h265e5a51 + w18_11) >> (32 - 14)));
w19_0 <= w18_0;
w19_1 <= w18_1;
w19_2 <= w18_2;
w19_3 <= w18_3;
w19_4 <= w18_4;
w19_5 <= w18_5;
w19_6 <= w18_6;
w19_7 <= w18_7;
w19_8 <= w18_8;
w19_9 <= w18_9;
w19_10 <= w18_10;
w19_11 <= w18_11;
w19_12 <= w18_12;
w19_13 <= w18_13;
w19_14 <= w18_14;
w19_15 <= w18_15;
a20 <= d19;
d20 <= c19;
c20 <= b19;
b20 <= b19 + (((a19 + ((d19 & b19) | ((~d19) & c19)) + 'he9b6c7aa + w19_0) << 20) | ((a19 + ((d19 & b19) | ((~d19) & c19)) + 'he9b6c7aa + w19_0) >> (32 - 20)));
w20_0 <= w19_0;
w20_1 <= w19_1;
w20_2 <= w19_2;
w20_3 <= w19_3;
w20_4 <= w19_4;
w20_5 <= w19_5;
w20_6 <= w19_6;
w20_7 <= w19_7;
w20_8 <= w19_8;
w20_9 <= w19_9;
w20_10 <= w19_10;
w20_11 <= w19_11;
w20_12 <= w19_12;
w20_13 <= w19_13;
w20_14 <= w19_14;
w20_15 <= w19_15;
a21 <= d20;
d21 <= c20;
c21 <= b20;
b21 <= b20 + (((a20 + ((d20 & b20) | ((~d20) & c20)) + 'hd62f105d + w20_5) << 5) | ((a20 + ((d20 & b20) | ((~d20) & c20)) + 'hd62f105d + w20_5) >> (32 - 5)));
w21_0 <= w20_0;
w21_1 <= w20_1;
w21_2 <= w20_2;
w21_3 <= w20_3;
w21_4 <= w20_4;
w21_5 <= w20_5;
w21_6 <= w20_6;
w21_7 <= w20_7;
w21_8 <= w20_8;
w21_9 <= w20_9;
w21_10 <= w20_10;
w21_11 <= w20_11;
w21_12 <= w20_12;
w21_13 <= w20_13;
w21_14 <= w20_14;
w21_15 <= w20_15;
a22 <= d21;
d22 <= c21;
c22 <= b21;
b22 <= b21 + (((a21 + ((d21 & b21) | ((~d21) & c21)) + 'h02441453 + w21_10) << 9) | ((a21 + ((d21 & b21) | ((~d21) & c21)) + 'h02441453 + w21_10) >> (32 - 9)));
w22_0 <= w21_0;
w22_1 <= w21_1;
w22_2 <= w21_2;
w22_3 <= w21_3;
w22_4 <= w21_4;
w22_5 <= w21_5;
w22_6 <= w21_6;
w22_7 <= w21_7;
w22_8 <= w21_8;
w22_9 <= w21_9;
w22_10 <= w21_10;
w22_11 <= w21_11;
w22_12 <= w21_12;
w22_13 <= w21_13;
w22_14 <= w21_14;
w22_15 <= w21_15;
a23 <= d22;
d23 <= c22;
c23 <= b22;
b23 <= b22 + (((a22 + ((d22 & b22) | ((~d22) & c22)) + 'hd8a1e681 + w22_15) << 14) | ((a22 + ((d22 & b22) | ((~d22) & c22)) + 'hd8a1e681 + w22_15) >> (32 - 14)));
w23_0 <= w22_0;
w23_1 <= w22_1;
w23_2 <= w22_2;
w23_3 <= w22_3;
w23_4 <= w22_4;
w23_5 <= w22_5;
w23_6 <= w22_6;
w23_7 <= w22_7;
w23_8 <= w22_8;
w23_9 <= w22_9;
w23_10 <= w22_10;
w23_11 <= w22_11;
w23_12 <= w22_12;
w23_13 <= w22_13;
w23_14 <= w22_14;
w23_15 <= w22_15;
a24 <= d23;
d24 <= c23;
c24 <= b23;
b24 <= b23 + (((a23 + ((d23 & b23) | ((~d23) & c23)) + 'he7d3fbc8 + w23_4) << 20) | ((a23 + ((d23 & b23) | ((~d23) & c23)) + 'he7d3fbc8 + w23_4) >> (32 - 20)));
w24_0 <= w23_0;
w24_1 <= w23_1;
w24_2 <= w23_2;
w24_3 <= w23_3;
w24_4 <= w23_4;
w24_5 <= w23_5;
w24_6 <= w23_6;
w24_7 <= w23_7;
w24_8 <= w23_8;
w24_9 <= w23_9;
w24_10 <= w23_10;
w24_11 <= w23_11;
w24_12 <= w23_12;
w24_13 <= w23_13;
w24_14 <= w23_14;
w24_15 <= w23_15;
a25 <= d24;
d25 <= c24;
c25 <= b24;
b25 <= b24 + (((a24 + ((d24 & b24) | ((~d24) & c24)) + 'h21e1cde6 + w24_9) << 5) | ((a24 + ((d24 & b24) | ((~d24) & c24)) + 'h21e1cde6 + w24_9) >> (32 - 5)));
w25_0 <= w24_0;
w25_1 <= w24_1;
w25_2 <= w24_2;
w25_3 <= w24_3;
w25_4 <= w24_4;
w25_5 <= w24_5;
w25_6 <= w24_6;
w25_7 <= w24_7;
w25_8 <= w24_8;
w25_9 <= w24_9;
w25_10 <= w24_10;
w25_11 <= w24_11;
w25_12 <= w24_12;
w25_13 <= w24_13;
w25_14 <= w24_14;
w25_15 <= w24_15;
a26 <= d25;
d26 <= c25;
c26 <= b25;
b26 <= b25 + (((a25 + ((d25 & b25) | ((~d25) & c25)) + 'hc33707d6 + w25_14) << 9) | ((a25 + ((d25 & b25) | ((~d25) & c25)) + 'hc33707d6 + w25_14) >> (32 - 9)));
w26_0 <= w25_0;
w26_1 <= w25_1;
w26_2 <= w25_2;
w26_3 <= w25_3;
w26_4 <= w25_4;
w26_5 <= w25_5;
w26_6 <= w25_6;
w26_7 <= w25_7;
w26_8 <= w25_8;
w26_9 <= w25_9;
w26_10 <= w25_10;
w26_11 <= w25_11;
w26_12 <= w25_12;
w26_13 <= w25_13;
w26_14 <= w25_14;
w26_15 <= w25_15;
a27 <= d26;
d27 <= c26;
c27 <= b26;
b27 <= b26 + (((a26 + ((d26 & b26) | ((~d26) & c26)) + 'hf4d50d87 + w26_3) << 14) | ((a26 + ((d26 & b26) | ((~d26) & c26)) + 'hf4d50d87 + w26_3) >> (32 - 14)));
w27_0 <= w26_0;
w27_1 <= w26_1;
w27_2 <= w26_2;
w27_3 <= w26_3;
w27_4 <= w26_4;
w27_5 <= w26_5;
w27_6 <= w26_6;
w27_7 <= w26_7;
w27_8 <= w26_8;
w27_9 <= w26_9;
w27_10 <= w26_10;
w27_11 <= w26_11;
w27_12 <= w26_12;
w27_13 <= w26_13;
w27_14 <= w26_14;
w27_15 <= w26_15;
a28 <= d27;
d28 <= c27;
c28 <= b27;
b28 <= b27 + (((a27 + ((d27 & b27) | ((~d27) & c27)) + 'h455a14ed + w27_8) << 20) | ((a27 + ((d27 & b27) | ((~d27) & c27)) + 'h455a14ed + w27_8) >> (32 - 20)));
w28_0 <= w27_0;
w28_1 <= w27_1;
w28_2 <= w27_2;
w28_3 <= w27_3;
w28_4 <= w27_4;
w28_5 <= w27_5;
w28_6 <= w27_6;
w28_7 <= w27_7;
w28_8 <= w27_8;
w28_9 <= w27_9;
w28_10 <= w27_10;
w28_11 <= w27_11;
w28_12 <= w27_12;
w28_13 <= w27_13;
w28_14 <= w27_14;
w28_15 <= w27_15;
a29 <= d28;
d29 <= c28;
c29 <= b28;
b29 <= b28 + (((a28 + ((d28 & b28) | ((~d28) & c28)) + 'ha9e3e905 + w28_13) << 5) | ((a28 + ((d28 & b28) | ((~d28) & c28)) + 'ha9e3e905 + w28_13) >> (32 - 5)));
w29_0 <= w28_0;
w29_1 <= w28_1;
w29_2 <= w28_2;
w29_3 <= w28_3;
w29_4 <= w28_4;
w29_5 <= w28_5;
w29_6 <= w28_6;
w29_7 <= w28_7;
w29_8 <= w28_8;
w29_9 <= w28_9;
w29_10 <= w28_10;
w29_11 <= w28_11;
w29_12 <= w28_12;
w29_13 <= w28_13;
w29_14 <= w28_14;
w29_15 <= w28_15;
a30 <= d29;
d30 <= c29;
c30 <= b29;
b30 <= b29 + (((a29 + ((d29 & b29) | ((~d29) & c29)) + 'hfcefa3f8 + w29_2) << 9) | ((a29 + ((d29 & b29) | ((~d29) & c29)) + 'hfcefa3f8 + w29_2) >> (32 - 9)));
w30_0 <= w29_0;
w30_1 <= w29_1;
w30_2 <= w29_2;
w30_3 <= w29_3;
w30_4 <= w29_4;
w30_5 <= w29_5;
w30_6 <= w29_6;
w30_7 <= w29_7;
w30_8 <= w29_8;
w30_9 <= w29_9;
w30_10 <= w29_10;
w30_11 <= w29_11;
w30_12 <= w29_12;
w30_13 <= w29_13;
w30_14 <= w29_14;
w30_15 <= w29_15;
a31 <= d30;
d31 <= c30;
c31 <= b30;
b31 <= b30 + (((a30 + ((d30 & b30) | ((~d30) & c30)) + 'h676f02d9 + w30_7) << 14) | ((a30 + ((d30 & b30) | ((~d30) & c30)) + 'h676f02d9 + w30_7) >> (32 - 14)));
w31_0 <= w30_0;
w31_1 <= w30_1;
w31_2 <= w30_2;
w31_3 <= w30_3;
w31_4 <= w30_4;
w31_5 <= w30_5;
w31_6 <= w30_6;
w31_7 <= w30_7;
w31_8 <= w30_8;
w31_9 <= w30_9;
w31_10 <= w30_10;
w31_11 <= w30_11;
w31_12 <= w30_12;
w31_13 <= w30_13;
w31_14 <= w30_14;
w31_15 <= w30_15;
a32 <= d31;
d32 <= c31;
c32 <= b31;
b32 <= b31 + (((a31 + ((d31 & b31) | ((~d31) & c31)) + 'h8d2a4c8a + w31_12) << 20) | ((a31 + ((d31 & b31) | ((~d31) & c31)) + 'h8d2a4c8a + w31_12) >> (32 - 20)));
w32_0 <= w31_0;
w32_1 <= w31_1;
w32_2 <= w31_2;
w32_3 <= w31_3;
w32_4 <= w31_4;
w32_5 <= w31_5;
w32_6 <= w31_6;
w32_7 <= w31_7;
w32_8 <= w31_8;
w32_9 <= w31_9;
w32_10 <= w31_10;
w32_11 <= w31_11;
w32_12 <= w31_12;
w32_13 <= w31_13;
w32_14 <= w31_14;
w32_15 <= w31_15;
a33 <= d32;
d33 <= c32;
c33 <= b32;
b33 <= b32 + (((a32 + (b32 ^ c32 ^ d32) + 'hfffa3942 + w32_5) << 4) | ((a32 + (b32 ^ c32 ^ d32) + 'hfffa3942 + w32_5) >> (32 - 4)));
w33_0 <= w32_0;
w33_1 <= w32_1;
w33_2 <= w32_2;
w33_3 <= w32_3;
w33_4 <= w32_4;
w33_5 <= w32_5;
w33_6 <= w32_6;
w33_7 <= w32_7;
w33_8 <= w32_8;
w33_9 <= w32_9;
w33_10 <= w32_10;
w33_11 <= w32_11;
w33_12 <= w32_12;
w33_13 <= w32_13;
w33_14 <= w32_14;
w33_15 <= w32_15;
a34 <= d33;
d34 <= c33;
c34 <= b33;
b34 <= b33 + (((a33 + (b33 ^ c33 ^ d33) + 'h8771f681 + w33_8) << 11) | ((a33 + (b33 ^ c33 ^ d33) + 'h8771f681 + w33_8) >> (32 - 11)));
w34_0 <= w33_0;
w34_1 <= w33_1;
w34_2 <= w33_2;
w34_3 <= w33_3;
w34_4 <= w33_4;
w34_5 <= w33_5;
w34_6 <= w33_6;
w34_7 <= w33_7;
w34_8 <= w33_8;
w34_9 <= w33_9;
w34_10 <= w33_10;
w34_11 <= w33_11;
w34_12 <= w33_12;
w34_13 <= w33_13;
w34_14 <= w33_14;
w34_15 <= w33_15;
a35 <= d34;
d35 <= c34;
c35 <= b34;
b35 <= b34 + (((a34 + (b34 ^ c34 ^ d34) + 'h6d9d6122 + w34_11) << 16) | ((a34 + (b34 ^ c34 ^ d34) + 'h6d9d6122 + w34_11) >> (32 - 16)));
w35_0 <= w34_0;
w35_1 <= w34_1;
w35_2 <= w34_2;
w35_3 <= w34_3;
w35_4 <= w34_4;
w35_5 <= w34_5;
w35_6 <= w34_6;
w35_7 <= w34_7;
w35_8 <= w34_8;
w35_9 <= w34_9;
w35_10 <= w34_10;
w35_11 <= w34_11;
w35_12 <= w34_12;
w35_13 <= w34_13;
w35_14 <= w34_14;
w35_15 <= w34_15;
a36 <= d35;
d36 <= c35;
c36 <= b35;
b36 <= b35 + (((a35 + (b35 ^ c35 ^ d35) + 'hfde5380c + w35_14) << 23) | ((a35 + (b35 ^ c35 ^ d35) + 'hfde5380c + w35_14) >> (32 - 23)));
w36_0 <= w35_0;
w36_1 <= w35_1;
w36_2 <= w35_2;
w36_3 <= w35_3;
w36_4 <= w35_4;
w36_5 <= w35_5;
w36_6 <= w35_6;
w36_7 <= w35_7;
w36_8 <= w35_8;
w36_9 <= w35_9;
w36_10 <= w35_10;
w36_11 <= w35_11;
w36_12 <= w35_12;
w36_13 <= w35_13;
w36_14 <= w35_14;
w36_15 <= w35_15;
a37 <= d36;
d37 <= c36;
c37 <= b36;
b37 <= b36 + (((a36 + (b36 ^ c36 ^ d36) + 'ha4beea44 + w36_1) << 4) | ((a36 + (b36 ^ c36 ^ d36) + 'ha4beea44 + w36_1) >> (32 - 4)));
w37_0 <= w36_0;
w37_1 <= w36_1;
w37_2 <= w36_2;
w37_3 <= w36_3;
w37_4 <= w36_4;
w37_5 <= w36_5;
w37_6 <= w36_6;
w37_7 <= w36_7;
w37_8 <= w36_8;
w37_9 <= w36_9;
w37_10 <= w36_10;
w37_11 <= w36_11;
w37_12 <= w36_12;
w37_13 <= w36_13;
w37_14 <= w36_14;
w37_15 <= w36_15;
a38 <= d37;
d38 <= c37;
c38 <= b37;
b38 <= b37 + (((a37 + (b37 ^ c37 ^ d37) + 'h4bdecfa9 + w37_4) << 11) | ((a37 + (b37 ^ c37 ^ d37) + 'h4bdecfa9 + w37_4) >> (32 - 11)));
w38_0 <= w37_0;
w38_1 <= w37_1;
w38_2 <= w37_2;
w38_3 <= w37_3;
w38_4 <= w37_4;
w38_5 <= w37_5;
w38_6 <= w37_6;
w38_7 <= w37_7;
w38_8 <= w37_8;
w38_9 <= w37_9;
w38_10 <= w37_10;
w38_11 <= w37_11;
w38_12 <= w37_12;
w38_13 <= w37_13;
w38_14 <= w37_14;
w38_15 <= w37_15;
a39 <= d38;
d39 <= c38;
c39 <= b38;
b39 <= b38 + (((a38 + (b38 ^ c38 ^ d38) + 'hf6bb4b60 + w38_7) << 16) | ((a38 + (b38 ^ c38 ^ d38) + 'hf6bb4b60 + w38_7) >> (32 - 16)));
w39_0 <= w38_0;
w39_1 <= w38_1;
w39_2 <= w38_2;
w39_3 <= w38_3;
w39_4 <= w38_4;
w39_5 <= w38_5;
w39_6 <= w38_6;
w39_7 <= w38_7;
w39_8 <= w38_8;
w39_9 <= w38_9;
w39_10 <= w38_10;
w39_11 <= w38_11;
w39_12 <= w38_12;
w39_13 <= w38_13;
w39_14 <= w38_14;
w39_15 <= w38_15;
a40 <= d39;
d40 <= c39;
c40 <= b39;
b40 <= b39 + (((a39 + (b39 ^ c39 ^ d39) + 'hbebfbc70 + w39_10) << 23) | ((a39 + (b39 ^ c39 ^ d39) + 'hbebfbc70 + w39_10) >> (32 - 23)));
w40_0 <= w39_0;
w40_1 <= w39_1;
w40_2 <= w39_2;
w40_3 <= w39_3;
w40_4 <= w39_4;
w40_5 <= w39_5;
w40_6 <= w39_6;
w40_7 <= w39_7;
w40_8 <= w39_8;
w40_9 <= w39_9;
w40_10 <= w39_10;
w40_11 <= w39_11;
w40_12 <= w39_12;
w40_13 <= w39_13;
w40_14 <= w39_14;
w40_15 <= w39_15;
a41 <= d40;
d41 <= c40;
c41 <= b40;
b41 <= b40 + (((a40 + (b40 ^ c40 ^ d40) + 'h289b7ec6 + w40_13) << 4) | ((a40 + (b40 ^ c40 ^ d40) + 'h289b7ec6 + w40_13) >> (32 - 4)));
w41_0 <= w40_0;
w41_1 <= w40_1;
w41_2 <= w40_2;
w41_3 <= w40_3;
w41_4 <= w40_4;
w41_5 <= w40_5;
w41_6 <= w40_6;
w41_7 <= w40_7;
w41_8 <= w40_8;
w41_9 <= w40_9;
w41_10 <= w40_10;
w41_11 <= w40_11;
w41_12 <= w40_12;
w41_13 <= w40_13;
w41_14 <= w40_14;
w41_15 <= w40_15;
a42 <= d41;
d42 <= c41;
c42 <= b41;
b42 <= b41 + (((a41 + (b41 ^ c41 ^ d41) + 'heaa127fa + w41_0) << 11) | ((a41 + (b41 ^ c41 ^ d41) + 'heaa127fa + w41_0) >> (32 - 11)));
w42_0 <= w41_0;
w42_1 <= w41_1;
w42_2 <= w41_2;
w42_3 <= w41_3;
w42_4 <= w41_4;
w42_5 <= w41_5;
w42_6 <= w41_6;
w42_7 <= w41_7;
w42_8 <= w41_8;
w42_9 <= w41_9;
w42_10 <= w41_10;
w42_11 <= w41_11;
w42_12 <= w41_12;
w42_13 <= w41_13;
w42_14 <= w41_14;
w42_15 <= w41_15;
a43 <= d42;
d43 <= c42;
c43 <= b42;
b43 <= b42 + (((a42 + (b42 ^ c42 ^ d42) + 'hd4ef3085 + w42_3) << 16) | ((a42 + (b42 ^ c42 ^ d42) + 'hd4ef3085 + w42_3) >> (32 - 16)));
w43_0 <= w42_0;
w43_1 <= w42_1;
w43_2 <= w42_2;
w43_3 <= w42_3;
w43_4 <= w42_4;
w43_5 <= w42_5;
w43_6 <= w42_6;
w43_7 <= w42_7;
w43_8 <= w42_8;
w43_9 <= w42_9;
w43_10 <= w42_10;
w43_11 <= w42_11;
w43_12 <= w42_12;
w43_13 <= w42_13;
w43_14 <= w42_14;
w43_15 <= w42_15;
a44 <= d43;
d44 <= c43;
c44 <= b43;
b44 <= b43 + (((a43 + (b43 ^ c43 ^ d43) + 'h04881d05 + w43_6) << 23) | ((a43 + (b43 ^ c43 ^ d43) + 'h04881d05 + w43_6) >> (32 - 23)));
w44_0 <= w43_0;
w44_1 <= w43_1;
w44_2 <= w43_2;
w44_3 <= w43_3;
w44_4 <= w43_4;
w44_5 <= w43_5;
w44_6 <= w43_6;
w44_7 <= w43_7;
w44_8 <= w43_8;
w44_9 <= w43_9;
w44_10 <= w43_10;
w44_11 <= w43_11;
w44_12 <= w43_12;
w44_13 <= w43_13;
w44_14 <= w43_14;
w44_15 <= w43_15;
a45 <= d44;
d45 <= c44;
c45 <= b44;
b45 <= b44 + (((a44 + (b44 ^ c44 ^ d44) + 'hd9d4d039 + w44_9) << 4) | ((a44 + (b44 ^ c44 ^ d44) + 'hd9d4d039 + w44_9) >> (32 - 4)));
w45_0 <= w44_0;
w45_1 <= w44_1;
w45_2 <= w44_2;
w45_3 <= w44_3;
w45_4 <= w44_4;
w45_5 <= w44_5;
w45_6 <= w44_6;
w45_7 <= w44_7;
w45_8 <= w44_8;
w45_9 <= w44_9;
w45_10 <= w44_10;
w45_11 <= w44_11;
w45_12 <= w44_12;
w45_13 <= w44_13;
w45_14 <= w44_14;
w45_15 <= w44_15;
a46 <= d45;
d46 <= c45;
c46 <= b45;
b46 <= b45 + (((a45 + (b45 ^ c45 ^ d45) + 'he6db99e5 + w45_12) << 11) | ((a45 + (b45 ^ c45 ^ d45) + 'he6db99e5 + w45_12) >> (32 - 11)));
w46_0 <= w45_0;
w46_1 <= w45_1;
w46_2 <= w45_2;
w46_3 <= w45_3;
w46_4 <= w45_4;
w46_5 <= w45_5;
w46_6 <= w45_6;
w46_7 <= w45_7;
w46_8 <= w45_8;
w46_9 <= w45_9;
w46_10 <= w45_10;
w46_11 <= w45_11;
w46_12 <= w45_12;
w46_13 <= w45_13;
w46_14 <= w45_14;
w46_15 <= w45_15;
a47 <= d46;
d47 <= c46;
c47 <= b46;
b47 <= b46 + (((a46 + (b46 ^ c46 ^ d46) + 'h1fa27cf8 + w46_15) << 16) | ((a46 + (b46 ^ c46 ^ d46) + 'h1fa27cf8 + w46_15) >> (32 - 16)));
w47_0 <= w46_0;
w47_1 <= w46_1;
w47_2 <= w46_2;
w47_3 <= w46_3;
w47_4 <= w46_4;
w47_5 <= w46_5;
w47_6 <= w46_6;
w47_7 <= w46_7;
w47_8 <= w46_8;
w47_9 <= w46_9;
w47_10 <= w46_10;
w47_11 <= w46_11;
w47_12 <= w46_12;
w47_13 <= w46_13;
w47_14 <= w46_14;
w47_15 <= w46_15;
a48 <= d47;
d48 <= c47;
c48 <= b47;
b48 <= b47 + (((a47 + (b47 ^ c47 ^ d47) + 'hc4ac5665 + w47_2) << 23) | ((a47 + (b47 ^ c47 ^ d47) + 'hc4ac5665 + w47_2) >> (32 - 23)));
w48_0 <= w47_0;
w48_1 <= w47_1;
w48_2 <= w47_2;
w48_3 <= w47_3;
w48_4 <= w47_4;
w48_5 <= w47_5;
w48_6 <= w47_6;
w48_7 <= w47_7;
w48_8 <= w47_8;
w48_9 <= w47_9;
w48_10 <= w47_10;
w48_11 <= w47_11;
w48_12 <= w47_12;
w48_13 <= w47_13;
w48_14 <= w47_14;
w48_15 <= w47_15;
a49 <= d48;
d49 <= c48;
c49 <= b48;
b49 <= b48 + (((a48 + (c48 ^ (b48 | (~d48))) + 'hf4292244 + w48_0) << 6) | ((a48 + (c48 ^ (b48 | (~d48))) + 'hf4292244 + w48_0) >> (32 - 6)));
w49_0 <= w48_0;
w49_1 <= w48_1;
w49_2 <= w48_2;
w49_3 <= w48_3;
w49_4 <= w48_4;
w49_5 <= w48_5;
w49_6 <= w48_6;
w49_7 <= w48_7;
w49_8 <= w48_8;
w49_9 <= w48_9;
w49_10 <= w48_10;
w49_11 <= w48_11;
w49_12 <= w48_12;
w49_13 <= w48_13;
w49_14 <= w48_14;
w49_15 <= w48_15;
a50 <= d49;
d50 <= c49;
c50 <= b49;
b50 <= b49 + (((a49 + (c49 ^ (b49 | (~d49))) + 'h432aff97 + w49_7) << 10) | ((a49 + (c49 ^ (b49 | (~d49))) + 'h432aff97 + w49_7) >> (32 - 10)));
w50_0 <= w49_0;
w50_1 <= w49_1;
w50_2 <= w49_2;
w50_3 <= w49_3;
w50_4 <= w49_4;
w50_5 <= w49_5;
w50_6 <= w49_6;
w50_7 <= w49_7;
w50_8 <= w49_8;
w50_9 <= w49_9;
w50_10 <= w49_10;
w50_11 <= w49_11;
w50_12 <= w49_12;
w50_13 <= w49_13;
w50_14 <= w49_14;
w50_15 <= w49_15;
a51 <= d50;
d51 <= c50;
c51 <= b50;
b51 <= b50 + (((a50 + (c50 ^ (b50 | (~d50))) + 'hab9423a7 + w50_14) << 15) | ((a50 + (c50 ^ (b50 | (~d50))) + 'hab9423a7 + w50_14) >> (32 - 15)));
w51_0 <= w50_0;
w51_1 <= w50_1;
w51_2 <= w50_2;
w51_3 <= w50_3;
w51_4 <= w50_4;
w51_5 <= w50_5;
w51_6 <= w50_6;
w51_7 <= w50_7;
w51_8 <= w50_8;
w51_9 <= w50_9;
w51_10 <= w50_10;
w51_11 <= w50_11;
w51_12 <= w50_12;
w51_13 <= w50_13;
w51_14 <= w50_14;
w51_15 <= w50_15;
a52 <= d51;
d52 <= c51;
c52 <= b51;
b52 <= b51 + (((a51 + (c51 ^ (b51 | (~d51))) + 'hfc93a039 + w51_5) << 21) | ((a51 + (c51 ^ (b51 | (~d51))) + 'hfc93a039 + w51_5) >> (32 - 21)));
w52_0 <= w51_0;
w52_1 <= w51_1;
w52_2 <= w51_2;
w52_3 <= w51_3;
w52_4 <= w51_4;
w52_5 <= w51_5;
w52_6 <= w51_6;
w52_7 <= w51_7;
w52_8 <= w51_8;
w52_9 <= w51_9;
w52_10 <= w51_10;
w52_11 <= w51_11;
w52_12 <= w51_12;
w52_13 <= w51_13;
w52_14 <= w51_14;
w52_15 <= w51_15;
a53 <= d52;
d53 <= c52;
c53 <= b52;
b53 <= b52 + (((a52 + (c52 ^ (b52 | (~d52))) + 'h655b59c3 + w52_12) << 6) | ((a52 + (c52 ^ (b52 | (~d52))) + 'h655b59c3 + w52_12) >> (32 - 6)));
w53_0 <= w52_0;
w53_1 <= w52_1;
w53_2 <= w52_2;
w53_3 <= w52_3;
w53_4 <= w52_4;
w53_5 <= w52_5;
w53_6 <= w52_6;
w53_7 <= w52_7;
w53_8 <= w52_8;
w53_9 <= w52_9;
w53_10 <= w52_10;
w53_11 <= w52_11;
w53_12 <= w52_12;
w53_13 <= w52_13;
w53_14 <= w52_14;
w53_15 <= w52_15;
a54 <= d53;
d54 <= c53;
c54 <= b53;
b54 <= b53 + (((a53 + (c53 ^ (b53 | (~d53))) + 'h8f0ccc92 + w53_3) << 10) | ((a53 + (c53 ^ (b53 | (~d53))) + 'h8f0ccc92 + w53_3) >> (32 - 10)));
w54_0 <= w53_0;
w54_1 <= w53_1;
w54_2 <= w53_2;
w54_3 <= w53_3;
w54_4 <= w53_4;
w54_5 <= w53_5;
w54_6 <= w53_6;
w54_7 <= w53_7;
w54_8 <= w53_8;
w54_9 <= w53_9;
w54_10 <= w53_10;
w54_11 <= w53_11;
w54_12 <= w53_12;
w54_13 <= w53_13;
w54_14 <= w53_14;
w54_15 <= w53_15;
a55 <= d54;
d55 <= c54;
c55 <= b54;
b55 <= b54 + (((a54 + (c54 ^ (b54 | (~d54))) + 'hffeff47d + w54_10) << 15) | ((a54 + (c54 ^ (b54 | (~d54))) + 'hffeff47d + w54_10) >> (32 - 15)));
w55_0 <= w54_0;
w55_1 <= w54_1;
w55_2 <= w54_2;
w55_3 <= w54_3;
w55_4 <= w54_4;
w55_5 <= w54_5;
w55_6 <= w54_6;
w55_7 <= w54_7;
w55_8 <= w54_8;
w55_9 <= w54_9;
w55_10 <= w54_10;
w55_11 <= w54_11;
w55_12 <= w54_12;
w55_13 <= w54_13;
w55_14 <= w54_14;
w55_15 <= w54_15;
a56 <= d55;
d56 <= c55;
c56 <= b55;
b56 <= b55 + (((a55 + (c55 ^ (b55 | (~d55))) + 'h85845dd1 + w55_1) << 21) | ((a55 + (c55 ^ (b55 | (~d55))) + 'h85845dd1 + w55_1) >> (32 - 21)));
w56_0 <= w55_0;
w56_1 <= w55_1;
w56_2 <= w55_2;
w56_3 <= w55_3;
w56_4 <= w55_4;
w56_5 <= w55_5;
w56_6 <= w55_6;
w56_7 <= w55_7;
w56_8 <= w55_8;
w56_9 <= w55_9;
w56_10 <= w55_10;
w56_11 <= w55_11;
w56_12 <= w55_12;
w56_13 <= w55_13;
w56_14 <= w55_14;
w56_15 <= w55_15;
a57 <= d56;
d57 <= c56;
c57 <= b56;
b57 <= b56 + (((a56 + (c56 ^ (b56 | (~d56))) + 'h6fa87e4f + w56_8) << 6) | ((a56 + (c56 ^ (b56 | (~d56))) + 'h6fa87e4f + w56_8) >> (32 - 6)));
w57_0 <= w56_0;
w57_1 <= w56_1;
w57_2 <= w56_2;
w57_3 <= w56_3;
w57_4 <= w56_4;
w57_5 <= w56_5;
w57_6 <= w56_6;
w57_7 <= w56_7;
w57_8 <= w56_8;
w57_9 <= w56_9;
w57_10 <= w56_10;
w57_11 <= w56_11;
w57_12 <= w56_12;
w57_13 <= w56_13;
w57_14 <= w56_14;
w57_15 <= w56_15;
a58 <= d57;
d58 <= c57;
c58 <= b57;
b58 <= b57 + (((a57 + (c57 ^ (b57 | (~d57))) + 'hfe2ce6e0 + w57_15) << 10) | ((a57 + (c57 ^ (b57 | (~d57))) + 'hfe2ce6e0 + w57_15) >> (32 - 10)));
w58_0 <= w57_0;
w58_1 <= w57_1;
w58_2 <= w57_2;
w58_3 <= w57_3;
w58_4 <= w57_4;
w58_5 <= w57_5;
w58_6 <= w57_6;
w58_7 <= w57_7;
w58_8 <= w57_8;
w58_9 <= w57_9;
w58_10 <= w57_10;
w58_11 <= w57_11;
w58_12 <= w57_12;
w58_13 <= w57_13;
w58_14 <= w57_14;
w58_15 <= w57_15;
a59 <= d58;
d59 <= c58;
c59 <= b58;
b59 <= b58 + (((a58 + (c58 ^ (b58 | (~d58))) + 'ha3014314 + w58_6) << 15) | ((a58 + (c58 ^ (b58 | (~d58))) + 'ha3014314 + w58_6) >> (32 - 15)));
w59_0 <= w58_0;
w59_1 <= w58_1;
w59_2 <= w58_2;
w59_3 <= w58_3;
w59_4 <= w58_4;
w59_5 <= w58_5;
w59_6 <= w58_6;
w59_7 <= w58_7;
w59_8 <= w58_8;
w59_9 <= w58_9;
w59_10 <= w58_10;
w59_11 <= w58_11;
w59_12 <= w58_12;
w59_13 <= w58_13;
w59_14 <= w58_14;
w59_15 <= w58_15;
a60 <= d59;
d60 <= c59;
c60 <= b59;
b60 <= b59 + (((a59 + (c59 ^ (b59 | (~d59))) + 'h4e0811a1 + w59_13) << 21) | ((a59 + (c59 ^ (b59 | (~d59))) + 'h4e0811a1 + w59_13) >> (32 - 21)));
w60_0 <= w59_0;
w60_1 <= w59_1;
w60_2 <= w59_2;
w60_3 <= w59_3;
w60_4 <= w59_4;
w60_5 <= w59_5;
w60_6 <= w59_6;
w60_7 <= w59_7;
w60_8 <= w59_8;
w60_9 <= w59_9;
w60_10 <= w59_10;
w60_11 <= w59_11;
w60_12 <= w59_12;
w60_13 <= w59_13;
w60_14 <= w59_14;
w60_15 <= w59_15;
a61 <= d60;
d61 <= c60;
c61 <= b60;
b61 <= b60 + (((a60 + (c60 ^ (b60 | (~d60))) + 'hf7537e82 + w60_4) << 6) | ((a60 + (c60 ^ (b60 | (~d60))) + 'hf7537e82 + w60_4) >> (32 - 6)));
w61_0 <= w60_0;
w61_1 <= w60_1;
w61_2 <= w60_2;
w61_3 <= w60_3;
w61_4 <= w60_4;
w61_5 <= w60_5;
w61_6 <= w60_6;
w61_7 <= w60_7;
w61_8 <= w60_8;
w61_9 <= w60_9;
w61_10 <= w60_10;
w61_11 <= w60_11;
w61_12 <= w60_12;
w61_13 <= w60_13;
w61_14 <= w60_14;
w61_15 <= w60_15;
a62 <= d61;
d62 <= c61;
c62 <= b61;
b62 <= b61 + (((a61 + (c61 ^ (b61 | (~d61))) + 'hbd3af235 + w61_11) << 10) | ((a61 + (c61 ^ (b61 | (~d61))) + 'hbd3af235 + w61_11) >> (32 - 10)));
w62_0 <= w61_0;
w62_1 <= w61_1;
w62_2 <= w61_2;
w62_3 <= w61_3;
w62_4 <= w61_4;
w62_5 <= w61_5;
w62_6 <= w61_6;
w62_7 <= w61_7;
w62_8 <= w61_8;
w62_9 <= w61_9;
w62_10 <= w61_10;
w62_11 <= w61_11;
w62_12 <= w61_12;
w62_13 <= w61_13;
w62_14 <= w61_14;
w62_15 <= w61_15;
a63 <= d62;
d63 <= c62;
c63 <= b62;
b63 <= b62 + (((a62 + (c62 ^ (b62 | (~d62))) + 'h2ad7d2bb + w62_2) << 15) | ((a62 + (c62 ^ (b62 | (~d62))) + 'h2ad7d2bb + w62_2) >> (32 - 15)));
w63_0 <= w62_0;
w63_1 <= w62_1;
w63_2 <= w62_2;
w63_3 <= w62_3;
w63_4 <= w62_4;
w63_5 <= w62_5;
w63_6 <= w62_6;
w63_7 <= w62_7;
w63_8 <= w62_8;
w63_9 <= w62_9;
w63_10 <= w62_10;
w63_11 <= w62_11;
w63_12 <= w62_12;
w63_13 <= w62_13;
w63_14 <= w62_14;
w63_15 <= w62_15;
a64 <= d63;
d64 <= c63;
c64 <= b63;
b64 <= b63 + (((a63 + (c63 ^ (b63 | (~d63))) + 'heb86d391 + w63_9) << 21) | ((a63 + (c63 ^ (b63 | (~d63))) + 'heb86d391 + w63_9) >> (32 - 21)));
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/);
// IEEE: integer_atom_type
byte d_byte;
shortint d_shortint;
int d_int;
longint d_longint;
integer d_integer;
time d_time;
chandle d_chandle;
// IEEE: integer_atom_type
bit d_bit;
logic d_logic;
reg d_reg;
bit [0:0] d_bit1;
logic [0:0] d_logic1;
reg [0:0] d_reg1;
bit d_bitz;
logic d_logicz;
reg d_regz;
// IEEE: non_integer_type
//UNSUP shortreal d_shortreal;
real d_real;
realtime d_realtime;
initial begin
// below errors might cause spurious warnings
// verilator lint_off WIDTH
d_bitz[0] = 1'b1; // Illegal range
d_logicz[0] = 1'b1; // Illegal range
d_regz[0] = 1'b1; // Illegal range
`ifndef VERILATOR //UNSUPPORTED, it's just a 64 bit int right now
d_chandle[0] = 1'b1; // Illegal
`endif
d_real[0] = 1'b1; // Illegal
d_realtime[0] = 1'b1; // Illegal
// verilator lint_on WIDTH
d_byte[0] = 1'b1; // OK
d_shortint[0] = 1'b1; // OK
d_int[0] = 1'b1; // OK
d_longint[0] = 1'b1; // OK
d_integer[0] = 1'b1; // OK
d_time[0] = 1'b1; // OK
d_bit1[0] = 1'b1; // OK
d_logic1[0] = 1'b1; // OK
d_reg1[0] = 1'b1; // OK
end
endmodule
|
/*
ROM128X1: 128-Deep by 1-Wide ROM
ROM256X1: 256-Deep by 1-Wide ROM
ROM32X1: 32-Deep by 1-Wide ROM
ROM64X1: 64-Deep by 1-Wide ROM
*/
module top(input clk, stb, di, output do);
localparam integer DIN_N = 256;
localparam integer DOUT_N = 256;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [255:0] din, output [255:0] dout);
rom_ROM128X1 #(.LOC("XXX"))
rom_ROM128X1(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
rom_ROM256X1 #(.LOC("XXX"))
rom_ROM256X1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
rom_ROM32X1 #(.LOC("XXX"))
rom_ROM32X1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8]));
rom_ROM64X1 #(.LOC("XXX"))
rom_ROM64X1(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8]));
endmodule
//******************************************************************************
//BOUTMUX tests
/*
Cell as SLICEM D6LUT + C6LUT + F7BMUX
*/
module rom_ROM128X1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
//ROM128X1 #(.LOC(LOC), .N(N))
ROM128X1 #(.INIT(128'b0))
rom(
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.A6(din[6]));
endmodule
module rom_ROM256X1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
ROM256X1 #(.INIT(256'b0))
rom(
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]),
.A6(din[6]),
.A7(din[7]));
endmodule
module rom_ROM32X1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
ROM32X1 #(.INIT(32'b0))
rom(
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]));
endmodule
module rom_ROM64X1 (input clk, input [7:0] din, output [7:0] dout);
parameter LOC="SLICE_FIXME";
ROM64X1 #(.INIT(64'b0))
rom(
.O(dout[0]),
.A0(din[0]),
.A1(din[1]),
.A2(din[2]),
.A3(din[3]),
.A4(din[4]),
.A5(din[5]));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__BUF_BLACKBOX_V
`define SKY130_FD_SC_HVL__BUF_BLACKBOX_V
/**
* buf: Buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__buf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__BUF_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:18:54 03/22/2015
// Design Name: inverter
// Module Name: C:/Users/Joseph/Documents/Xilinx/HW1/gate_test.v
// Project Name: HW1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: inverter
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module gate_test;
// Inputs
reg X1, X2;
// Outputs
wire Y_inv, Y_nand2, Y_nor2, Y_xor2;
// Variables
integer i;
// Instantiate the Units Under Test (UUT)
// Inverter Single Input
inverter uut (
.Y(Y_inv),
.X(X1)
);
// 2-input NAND Gate
nand2 uut2 (
.Y(Y_nand2),
.X1(X1),
.X2(X2)
);
// 2-input NOR Gate
nor2 uut3 (
.Y(Y_nor2),
.X1(X1),
.X2(X2)
);
// 2-input XOR Gate
xor2 uut4 (
.Y(Y_xor2),
.X1(X1),
.X2(X2)
);
initial begin
// Initialize Inputs
X1 = 0;
X2 = 0;
// Loop Through All Possibilities
for(i=1; i<=4; i=i+1)
begin
#10 {X1, X2} = {X1, X2} + 1;
end
end
endmodule
|
// nios_solo_nios2_gen2_0.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_solo_nios2_gen2_0 (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [31:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [29:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
nios_solo_nios2_gen2_0_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
// amm_master_qsys_with_pcie.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module amm_master_qsys_with_pcie (
input wire clk_50_clk, // clk_50.clk
input wire custom_module_conduit_rdwr_cntl, // custom_module_conduit.rdwr_cntl
input wire custom_module_conduit_n_action, // .n_action
input wire custom_module_conduit_add_data_sel, // .add_data_sel
input wire [27:0] custom_module_conduit_rdwr_address, // .rdwr_address
output wire [31:0] custom_module_conduit_display_data, // .display_data
output wire pcie_ip_clocks_sim_clk250_export, // pcie_ip_clocks_sim.clk250_export
output wire pcie_ip_clocks_sim_clk500_export, // .clk500_export
output wire pcie_ip_clocks_sim_clk125_export, // .clk125_export
input wire pcie_ip_pcie_rstn_export, // pcie_ip_pcie_rstn.export
input wire pcie_ip_pipe_ext_pipe_mode, // pcie_ip_pipe_ext.pipe_mode
input wire pcie_ip_pipe_ext_phystatus_ext, // .phystatus_ext
output wire pcie_ip_pipe_ext_rate_ext, // .rate_ext
output wire [1:0] pcie_ip_pipe_ext_powerdown_ext, // .powerdown_ext
output wire pcie_ip_pipe_ext_txdetectrx_ext, // .txdetectrx_ext
input wire pcie_ip_pipe_ext_rxelecidle0_ext, // .rxelecidle0_ext
input wire [7:0] pcie_ip_pipe_ext_rxdata0_ext, // .rxdata0_ext
input wire [2:0] pcie_ip_pipe_ext_rxstatus0_ext, // .rxstatus0_ext
input wire pcie_ip_pipe_ext_rxvalid0_ext, // .rxvalid0_ext
input wire pcie_ip_pipe_ext_rxdatak0_ext, // .rxdatak0_ext
output wire [7:0] pcie_ip_pipe_ext_txdata0_ext, // .txdata0_ext
output wire pcie_ip_pipe_ext_txdatak0_ext, // .txdatak0_ext
output wire pcie_ip_pipe_ext_rxpolarity0_ext, // .rxpolarity0_ext
output wire pcie_ip_pipe_ext_txcompl0_ext, // .txcompl0_ext
output wire pcie_ip_pipe_ext_txelecidle0_ext, // .txelecidle0_ext
input wire pcie_ip_powerdown_pll_powerdown, // pcie_ip_powerdown.pll_powerdown
input wire pcie_ip_powerdown_gxb_powerdown, // .gxb_powerdown
input wire pcie_ip_reconfig_busy_busy_altgxb_reconfig, // pcie_ip_reconfig_busy.busy_altgxb_reconfig
output wire [4:0] pcie_ip_reconfig_fromgxb_0_data, // pcie_ip_reconfig_fromgxb_0.data
input wire [3:0] pcie_ip_reconfig_togxb_data, // pcie_ip_reconfig_togxb.data
input wire pcie_ip_refclk_export, // pcie_ip_refclk.export
input wire pcie_ip_rx_in_rx_datain_0, // pcie_ip_rx_in.rx_datain_0
input wire [39:0] pcie_ip_test_in_test_in, // pcie_ip_test_in.test_in
output wire pcie_ip_tx_out_tx_dataout_0, // pcie_ip_tx_out.tx_dataout_0
input wire reset_reset_n, // reset.reset_n
output wire [11:0] sdram_addr, // sdram.addr
output wire [1:0] sdram_ba, // .ba
output wire sdram_cas_n, // .cas_n
output wire sdram_cke, // .cke
output wire sdram_cs_n, // .cs_n
inout wire [31:0] sdram_dq, // .dq
output wire [3:0] sdram_dqm, // .dqm
output wire sdram_ras_n, // .ras_n
output wire sdram_we_n, // .we_n
output wire video_vga_controller_0_external_interface_CLK, // video_vga_controller_0_external_interface.CLK
output wire video_vga_controller_0_external_interface_HS, // .HS
output wire video_vga_controller_0_external_interface_VS, // .VS
output wire video_vga_controller_0_external_interface_BLANK, // .BLANK
output wire video_vga_controller_0_external_interface_SYNC, // .SYNC
output wire [7:0] video_vga_controller_0_external_interface_R, // .R
output wire [7:0] video_vga_controller_0_external_interface_G, // .G
output wire [7:0] video_vga_controller_0_external_interface_B // .B
);
wire video_dual_clock_buffer_0_avalon_dc_buffer_source_valid; // video_dual_clock_buffer_0:stream_out_valid -> video_vga_controller_0:valid
wire [29:0] video_dual_clock_buffer_0_avalon_dc_buffer_source_data; // video_dual_clock_buffer_0:stream_out_data -> video_vga_controller_0:data
wire video_dual_clock_buffer_0_avalon_dc_buffer_source_ready; // video_vga_controller_0:ready -> video_dual_clock_buffer_0:stream_out_ready
wire video_dual_clock_buffer_0_avalon_dc_buffer_source_startofpacket; // video_dual_clock_buffer_0:stream_out_startofpacket -> video_vga_controller_0:startofpacket
wire video_dual_clock_buffer_0_avalon_dc_buffer_source_endofpacket; // video_dual_clock_buffer_0:stream_out_endofpacket -> video_vga_controller_0:endofpacket
wire video_pixel_buffer_dma_0_avalon_pixel_source_valid; // video_pixel_buffer_dma_0:stream_valid -> video_rgb_resampler_0:stream_in_valid
wire [23:0] video_pixel_buffer_dma_0_avalon_pixel_source_data; // video_pixel_buffer_dma_0:stream_data -> video_rgb_resampler_0:stream_in_data
wire video_pixel_buffer_dma_0_avalon_pixel_source_ready; // video_rgb_resampler_0:stream_in_ready -> video_pixel_buffer_dma_0:stream_ready
wire video_pixel_buffer_dma_0_avalon_pixel_source_startofpacket; // video_pixel_buffer_dma_0:stream_startofpacket -> video_rgb_resampler_0:stream_in_startofpacket
wire video_pixel_buffer_dma_0_avalon_pixel_source_endofpacket; // video_pixel_buffer_dma_0:stream_endofpacket -> video_rgb_resampler_0:stream_in_endofpacket
wire video_rgb_resampler_0_avalon_rgb_source_valid; // video_rgb_resampler_0:stream_out_valid -> video_dual_clock_buffer_0:stream_in_valid
wire [29:0] video_rgb_resampler_0_avalon_rgb_source_data; // video_rgb_resampler_0:stream_out_data -> video_dual_clock_buffer_0:stream_in_data
wire video_rgb_resampler_0_avalon_rgb_source_ready; // video_dual_clock_buffer_0:stream_in_ready -> video_rgb_resampler_0:stream_out_ready
wire video_rgb_resampler_0_avalon_rgb_source_startofpacket; // video_rgb_resampler_0:stream_out_startofpacket -> video_dual_clock_buffer_0:stream_in_startofpacket
wire video_rgb_resampler_0_avalon_rgb_source_endofpacket; // video_rgb_resampler_0:stream_out_endofpacket -> video_dual_clock_buffer_0:stream_in_endofpacket
wire altpll_qsys_c1_clk; // altpll_qsys:c1 -> [mm_interconnect_0:altpll_qsys_c1_clk, rst_controller_002:clk, rst_controller_004:clk, sdram:clk, video_dual_clock_buffer_0:clk_stream_in, video_pixel_buffer_dma_0:clk, video_rgb_resampler_0:clk]
wire altpll_qsys_c2_clk; // altpll_qsys:c2 -> [rst_controller_005:clk, video_dual_clock_buffer_0:clk_stream_out, video_vga_controller_0:clk]
wire pcie_ip_pcie_core_clk_clk; // pcie_ip:pcie_core_clk_clk -> [irq_mapper:clk, mm_interconnect_0:pcie_ip_pcie_core_clk_clk, mm_interconnect_1:pcie_ip_pcie_core_clk_clk, mm_interconnect_2:pcie_ip_pcie_core_clk_clk, pcie_ip:cal_blk_clk_clk, pcie_ip:fixedclk_clk, pcie_ip:reconfig_gxbclk_clk, rst_controller_003:clk, rst_controller_006:clk, sgdma:clk]
wire [31:0] custom_module_avalon_master_readdata; // mm_interconnect_0:custom_module_avalon_master_readdata -> custom_module:master_readdata
wire custom_module_avalon_master_waitrequest; // mm_interconnect_0:custom_module_avalon_master_waitrequest -> custom_module:master_waitrequest
wire custom_module_avalon_master_read; // custom_module:master_read -> mm_interconnect_0:custom_module_avalon_master_read
wire [27:0] custom_module_avalon_master_address; // custom_module:master_address -> mm_interconnect_0:custom_module_avalon_master_address
wire custom_module_avalon_master_readdatavalid; // mm_interconnect_0:custom_module_avalon_master_readdatavalid -> custom_module:master_readdatavalid
wire [31:0] custom_module_avalon_master_writedata; // custom_module:master_writedata -> mm_interconnect_0:custom_module_avalon_master_writedata
wire custom_module_avalon_master_write; // custom_module:master_write -> mm_interconnect_0:custom_module_avalon_master_write
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_waitrequest; // mm_interconnect_0:video_pixel_buffer_dma_0_avalon_pixel_dma_master_waitrequest -> video_pixel_buffer_dma_0:master_waitrequest
wire [31:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdata; // mm_interconnect_0:video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdata -> video_pixel_buffer_dma_0:master_readdata
wire [31:0] video_pixel_buffer_dma_0_avalon_pixel_dma_master_address; // video_pixel_buffer_dma_0:master_address -> mm_interconnect_0:video_pixel_buffer_dma_0_avalon_pixel_dma_master_address
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_read; // video_pixel_buffer_dma_0:master_read -> mm_interconnect_0:video_pixel_buffer_dma_0_avalon_pixel_dma_master_read
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdatavalid; // mm_interconnect_0:video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdatavalid -> video_pixel_buffer_dma_0:master_readdatavalid
wire video_pixel_buffer_dma_0_avalon_pixel_dma_master_lock; // video_pixel_buffer_dma_0:master_arbiterlock -> mm_interconnect_0:video_pixel_buffer_dma_0_avalon_pixel_dma_master_lock
wire [63:0] sgdma_m_read_readdata; // mm_interconnect_0:sgdma_m_read_readdata -> sgdma:m_read_readdata
wire sgdma_m_read_waitrequest; // mm_interconnect_0:sgdma_m_read_waitrequest -> sgdma:m_read_waitrequest
wire [31:0] sgdma_m_read_address; // sgdma:m_read_address -> mm_interconnect_0:sgdma_m_read_address
wire sgdma_m_read_read; // sgdma:m_read_read -> mm_interconnect_0:sgdma_m_read_read
wire sgdma_m_read_readdatavalid; // mm_interconnect_0:sgdma_m_read_readdatavalid -> sgdma:m_read_readdatavalid
wire [3:0] sgdma_m_read_burstcount; // sgdma:m_read_burstcount -> mm_interconnect_0:sgdma_m_read_burstcount
wire sgdma_m_write_waitrequest; // mm_interconnect_0:sgdma_m_write_waitrequest -> sgdma:m_write_waitrequest
wire [31:0] sgdma_m_write_address; // sgdma:m_write_address -> mm_interconnect_0:sgdma_m_write_address
wire [7:0] sgdma_m_write_byteenable; // sgdma:m_write_byteenable -> mm_interconnect_0:sgdma_m_write_byteenable
wire sgdma_m_write_write; // sgdma:m_write_write -> mm_interconnect_0:sgdma_m_write_write
wire [63:0] sgdma_m_write_writedata; // sgdma:m_write_writedata -> mm_interconnect_0:sgdma_m_write_writedata
wire [7:0] sgdma_m_write_burstcount; // sgdma:m_write_burstcount -> mm_interconnect_0:sgdma_m_write_burstcount
wire [31:0] sgdma_descriptor_read_readdata; // mm_interconnect_0:sgdma_descriptor_read_readdata -> sgdma:descriptor_read_readdata
wire sgdma_descriptor_read_waitrequest; // mm_interconnect_0:sgdma_descriptor_read_waitrequest -> sgdma:descriptor_read_waitrequest
wire [31:0] sgdma_descriptor_read_address; // sgdma:descriptor_read_address -> mm_interconnect_0:sgdma_descriptor_read_address
wire sgdma_descriptor_read_read; // sgdma:descriptor_read_read -> mm_interconnect_0:sgdma_descriptor_read_read
wire sgdma_descriptor_read_readdatavalid; // mm_interconnect_0:sgdma_descriptor_read_readdatavalid -> sgdma:descriptor_read_readdatavalid
wire sgdma_descriptor_write_waitrequest; // mm_interconnect_0:sgdma_descriptor_write_waitrequest -> sgdma:descriptor_write_waitrequest
wire [31:0] sgdma_descriptor_write_address; // sgdma:descriptor_write_address -> mm_interconnect_0:sgdma_descriptor_write_address
wire sgdma_descriptor_write_write; // sgdma:descriptor_write_write -> mm_interconnect_0:sgdma_descriptor_write_write
wire [31:0] sgdma_descriptor_write_writedata; // sgdma:descriptor_write_writedata -> mm_interconnect_0:sgdma_descriptor_write_writedata
wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:sdram_s1_chipselect -> sdram:az_cs
wire [31:0] mm_interconnect_0_sdram_s1_readdata; // sdram:za_data -> mm_interconnect_0:sdram_s1_readdata
wire mm_interconnect_0_sdram_s1_waitrequest; // sdram:za_waitrequest -> mm_interconnect_0:sdram_s1_waitrequest
wire [23:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:sdram_s1_address -> sdram:az_addr
wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:sdram_s1_read -> sdram:az_rd_n
wire [3:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:sdram_s1_byteenable -> sdram:az_be_n
wire mm_interconnect_0_sdram_s1_readdatavalid; // sdram:za_valid -> mm_interconnect_0:sdram_s1_readdatavalid
wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:sdram_s1_write -> sdram:az_wr_n
wire [31:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:sdram_s1_writedata -> sdram:az_data
wire mm_interconnect_0_pcie_ip_txs_chipselect; // mm_interconnect_0:pcie_ip_txs_chipselect -> pcie_ip:txs_chipselect
wire [63:0] mm_interconnect_0_pcie_ip_txs_readdata; // pcie_ip:txs_readdata -> mm_interconnect_0:pcie_ip_txs_readdata
wire mm_interconnect_0_pcie_ip_txs_waitrequest; // pcie_ip:txs_waitrequest -> mm_interconnect_0:pcie_ip_txs_waitrequest
wire [30:0] mm_interconnect_0_pcie_ip_txs_address; // mm_interconnect_0:pcie_ip_txs_address -> pcie_ip:txs_address
wire mm_interconnect_0_pcie_ip_txs_read; // mm_interconnect_0:pcie_ip_txs_read -> pcie_ip:txs_read
wire [7:0] mm_interconnect_0_pcie_ip_txs_byteenable; // mm_interconnect_0:pcie_ip_txs_byteenable -> pcie_ip:txs_byteenable
wire mm_interconnect_0_pcie_ip_txs_readdatavalid; // pcie_ip:txs_readdatavalid -> mm_interconnect_0:pcie_ip_txs_readdatavalid
wire mm_interconnect_0_pcie_ip_txs_write; // mm_interconnect_0:pcie_ip_txs_write -> pcie_ip:txs_write
wire [63:0] mm_interconnect_0_pcie_ip_txs_writedata; // mm_interconnect_0:pcie_ip_txs_writedata -> pcie_ip:txs_writedata
wire [6:0] mm_interconnect_0_pcie_ip_txs_burstcount; // mm_interconnect_0:pcie_ip_txs_burstcount -> pcie_ip:txs_burstcount
wire [31:0] mm_interconnect_0_altpll_qsys_pll_slave_readdata; // altpll_qsys:readdata -> mm_interconnect_0:altpll_qsys_pll_slave_readdata
wire [1:0] mm_interconnect_0_altpll_qsys_pll_slave_address; // mm_interconnect_0:altpll_qsys_pll_slave_address -> altpll_qsys:address
wire mm_interconnect_0_altpll_qsys_pll_slave_read; // mm_interconnect_0:altpll_qsys_pll_slave_read -> altpll_qsys:read
wire mm_interconnect_0_altpll_qsys_pll_slave_write; // mm_interconnect_0:altpll_qsys_pll_slave_write -> altpll_qsys:write
wire [31:0] mm_interconnect_0_altpll_qsys_pll_slave_writedata; // mm_interconnect_0:altpll_qsys_pll_slave_writedata -> altpll_qsys:writedata
wire pcie_ip_bar1_0_waitrequest; // mm_interconnect_1:pcie_ip_bar1_0_waitrequest -> pcie_ip:bar1_0_waitrequest
wire [63:0] pcie_ip_bar1_0_readdata; // mm_interconnect_1:pcie_ip_bar1_0_readdata -> pcie_ip:bar1_0_readdata
wire [31:0] pcie_ip_bar1_0_address; // pcie_ip:bar1_0_address -> mm_interconnect_1:pcie_ip_bar1_0_address
wire pcie_ip_bar1_0_read; // pcie_ip:bar1_0_read -> mm_interconnect_1:pcie_ip_bar1_0_read
wire [7:0] pcie_ip_bar1_0_byteenable; // pcie_ip:bar1_0_byteenable -> mm_interconnect_1:pcie_ip_bar1_0_byteenable
wire pcie_ip_bar1_0_readdatavalid; // mm_interconnect_1:pcie_ip_bar1_0_readdatavalid -> pcie_ip:bar1_0_readdatavalid
wire pcie_ip_bar1_0_write; // pcie_ip:bar1_0_write -> mm_interconnect_1:pcie_ip_bar1_0_write
wire [63:0] pcie_ip_bar1_0_writedata; // pcie_ip:bar1_0_writedata -> mm_interconnect_1:pcie_ip_bar1_0_writedata
wire [6:0] pcie_ip_bar1_0_burstcount; // pcie_ip:bar1_0_burstcount -> mm_interconnect_1:pcie_ip_bar1_0_burstcount
wire mm_interconnect_1_custom_module_avalon_slave_chipselect; // mm_interconnect_1:custom_module_avalon_slave_chipselect -> custom_module:slave_chipselect
wire [31:0] mm_interconnect_1_custom_module_avalon_slave_readdata; // custom_module:slave_readdata -> mm_interconnect_1:custom_module_avalon_slave_readdata
wire [4:0] mm_interconnect_1_custom_module_avalon_slave_address; // mm_interconnect_1:custom_module_avalon_slave_address -> custom_module:slave_address
wire mm_interconnect_1_custom_module_avalon_slave_read; // mm_interconnect_1:custom_module_avalon_slave_read -> custom_module:slave_read
wire mm_interconnect_1_custom_module_avalon_slave_write; // mm_interconnect_1:custom_module_avalon_slave_write -> custom_module:slave_write
wire [31:0] mm_interconnect_1_custom_module_avalon_slave_writedata; // mm_interconnect_1:custom_module_avalon_slave_writedata -> custom_module:slave_writedata
wire pcie_ip_bar2_waitrequest; // mm_interconnect_2:pcie_ip_bar2_waitrequest -> pcie_ip:bar2_waitrequest
wire [63:0] pcie_ip_bar2_readdata; // mm_interconnect_2:pcie_ip_bar2_readdata -> pcie_ip:bar2_readdata
wire [31:0] pcie_ip_bar2_address; // pcie_ip:bar2_address -> mm_interconnect_2:pcie_ip_bar2_address
wire pcie_ip_bar2_read; // pcie_ip:bar2_read -> mm_interconnect_2:pcie_ip_bar2_read
wire [7:0] pcie_ip_bar2_byteenable; // pcie_ip:bar2_byteenable -> mm_interconnect_2:pcie_ip_bar2_byteenable
wire pcie_ip_bar2_readdatavalid; // mm_interconnect_2:pcie_ip_bar2_readdatavalid -> pcie_ip:bar2_readdatavalid
wire pcie_ip_bar2_write; // pcie_ip:bar2_write -> mm_interconnect_2:pcie_ip_bar2_write
wire [63:0] pcie_ip_bar2_writedata; // pcie_ip:bar2_writedata -> mm_interconnect_2:pcie_ip_bar2_writedata
wire [6:0] pcie_ip_bar2_burstcount; // pcie_ip:bar2_burstcount -> mm_interconnect_2:pcie_ip_bar2_burstcount
wire mm_interconnect_2_pcie_ip_cra_chipselect; // mm_interconnect_2:pcie_ip_cra_chipselect -> pcie_ip:cra_chipselect
wire [31:0] mm_interconnect_2_pcie_ip_cra_readdata; // pcie_ip:cra_readdata -> mm_interconnect_2:pcie_ip_cra_readdata
wire mm_interconnect_2_pcie_ip_cra_waitrequest; // pcie_ip:cra_waitrequest -> mm_interconnect_2:pcie_ip_cra_waitrequest
wire [11:0] mm_interconnect_2_pcie_ip_cra_address; // mm_interconnect_2:pcie_ip_cra_address -> pcie_ip:cra_address
wire mm_interconnect_2_pcie_ip_cra_read; // mm_interconnect_2:pcie_ip_cra_read -> pcie_ip:cra_read
wire [3:0] mm_interconnect_2_pcie_ip_cra_byteenable; // mm_interconnect_2:pcie_ip_cra_byteenable -> pcie_ip:cra_byteenable
wire mm_interconnect_2_pcie_ip_cra_write; // mm_interconnect_2:pcie_ip_cra_write -> pcie_ip:cra_write
wire [31:0] mm_interconnect_2_pcie_ip_cra_writedata; // mm_interconnect_2:pcie_ip_cra_writedata -> pcie_ip:cra_writedata
wire mm_interconnect_2_sgdma_csr_chipselect; // mm_interconnect_2:sgdma_csr_chipselect -> sgdma:csr_chipselect
wire [31:0] mm_interconnect_2_sgdma_csr_readdata; // sgdma:csr_readdata -> mm_interconnect_2:sgdma_csr_readdata
wire [3:0] mm_interconnect_2_sgdma_csr_address; // mm_interconnect_2:sgdma_csr_address -> sgdma:csr_address
wire mm_interconnect_2_sgdma_csr_read; // mm_interconnect_2:sgdma_csr_read -> sgdma:csr_read
wire mm_interconnect_2_sgdma_csr_write; // mm_interconnect_2:sgdma_csr_write -> sgdma:csr_write
wire [31:0] mm_interconnect_2_sgdma_csr_writedata; // mm_interconnect_2:sgdma_csr_writedata -> sgdma:csr_writedata
wire irq_mapper_receiver0_irq; // sgdma:csr_irq -> irq_mapper:receiver0_irq
wire [15:0] pcie_ip_rxm_irq_irq; // irq_mapper:sender_irq -> pcie_ip:rxm_irq_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [altpll_qsys:reset, mm_interconnect_0:altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset]
wire pcie_ip_pcie_core_reset_reset; // pcie_ip:pcie_core_reset_reset_n -> [rst_controller:reset_in1, rst_controller_002:reset_in1, rst_controller_003:reset_in1, rst_controller_006:reset_in0]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [custom_module:reset_n, mm_interconnect_0:custom_module_reset_reset_bridge_in_reset_reset, mm_interconnect_1:custom_module_reset_reset_bridge_in_reset_reset]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [mm_interconnect_0:sdram_reset_reset_bridge_in_reset_reset, sdram:reset_n]
wire rst_controller_003_reset_out_reset; // rst_controller_003:reset_out -> [mm_interconnect_0:sgdma_reset_reset_bridge_in_reset_reset, mm_interconnect_2:sgdma_reset_reset_bridge_in_reset_reset, sgdma:system_reset_n]
wire rst_controller_004_reset_out_reset; // rst_controller_004:reset_out -> [mm_interconnect_0:video_pixel_buffer_dma_0_reset_reset_bridge_in_reset_reset, video_dual_clock_buffer_0:reset_stream_in, video_pixel_buffer_dma_0:reset, video_rgb_resampler_0:reset]
wire rst_controller_005_reset_out_reset; // rst_controller_005:reset_out -> [video_dual_clock_buffer_0:reset_stream_out, video_vga_controller_0:reset]
wire rst_controller_006_reset_out_reset; // rst_controller_006:reset_out -> [irq_mapper:reset, mm_interconnect_0:pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset, mm_interconnect_1:pcie_ip_bar1_0_translator_reset_reset_bridge_in_reset_reset, mm_interconnect_2:pcie_ip_bar2_translator_reset_reset_bridge_in_reset_reset]
amm_master_qsys_with_pcie_altpll_qsys altpll_qsys (
.clk (clk_50_clk), // inclk_interface.clk
.reset (rst_controller_reset_out_reset), // inclk_interface_reset.reset
.read (mm_interconnect_0_altpll_qsys_pll_slave_read), // pll_slave.read
.write (mm_interconnect_0_altpll_qsys_pll_slave_write), // .write
.address (mm_interconnect_0_altpll_qsys_pll_slave_address), // .address
.readdata (mm_interconnect_0_altpll_qsys_pll_slave_readdata), // .readdata
.writedata (mm_interconnect_0_altpll_qsys_pll_slave_writedata), // .writedata
.c0 (), // c0.clk
.c1 (altpll_qsys_c1_clk), // c1.clk
.c2 (altpll_qsys_c2_clk), // c2.clk
.c3 (), // c3_conduit.export
.areset (), // areset_conduit.export
.locked (), // locked_conduit.export
.phasedone () // phasedone_conduit.export
);
custom_master_slave #(
.MASTER_ADDRESSWIDTH (28),
.SLAVE_ADDRESSWIDTH (5),
.DATAWIDTH (32),
.NUMREGS (32),
.REGWIDTH (32)
) custom_module (
.clk (clk_50_clk), // clock.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.master_writedata (custom_module_avalon_master_writedata), // avalon_master.writedata
.master_write (custom_module_avalon_master_write), // .write
.master_read (custom_module_avalon_master_read), // .read
.master_readdata (custom_module_avalon_master_readdata), // .readdata
.master_readdatavalid (custom_module_avalon_master_readdatavalid), // .readdatavalid
.master_waitrequest (custom_module_avalon_master_waitrequest), // .waitrequest
.master_address (custom_module_avalon_master_address), // .address
.slave_readdata (mm_interconnect_1_custom_module_avalon_slave_readdata), // avalon_slave.readdata
.slave_chipselect (mm_interconnect_1_custom_module_avalon_slave_chipselect), // .chipselect
.slave_read (mm_interconnect_1_custom_module_avalon_slave_read), // .read
.slave_write (mm_interconnect_1_custom_module_avalon_slave_write), // .write
.slave_writedata (mm_interconnect_1_custom_module_avalon_slave_writedata), // .writedata
.slave_address (mm_interconnect_1_custom_module_avalon_slave_address), // .address
.rdwr_cntl (custom_module_conduit_rdwr_cntl), // conduit_end.export
.n_action (custom_module_conduit_n_action), // .export
.add_data_sel (custom_module_conduit_add_data_sel), // .export
.rdwr_address (custom_module_conduit_rdwr_address), // .export
.display_data (custom_module_conduit_display_data) // .export
);
amm_master_qsys_with_pcie_pcie_ip #(
.p_pcie_hip_type ("2"),
.lane_mask (8'b11111110),
.max_link_width (1),
.millisecond_cycle_count ("125000"),
.enable_gen2_core ("false"),
.gen2_lane_rate_mode ("false"),
.no_soft_reset ("false"),
.core_clk_divider (2),
.enable_ch0_pclk_out ("true"),
.core_clk_source ("pclk"),
.CB_P2A_AVALON_ADDR_B0 (0),
.bar0_size_mask (7),
.bar0_io_space ("false"),
.bar0_64bit_mem_space ("true"),
.bar0_prefetchable ("true"),
.CB_P2A_AVALON_ADDR_B1 (0),
.bar1_size_mask (0),
.bar1_io_space ("false"),
.bar1_64bit_mem_space ("true"),
.bar1_prefetchable ("false"),
.CB_P2A_AVALON_ADDR_B2 (0),
.bar2_size_mask (15),
.bar2_io_space ("false"),
.bar2_64bit_mem_space ("false"),
.bar2_prefetchable ("false"),
.CB_P2A_AVALON_ADDR_B3 (0),
.bar3_size_mask (0),
.bar3_io_space ("false"),
.bar3_64bit_mem_space ("false"),
.bar3_prefetchable ("false"),
.CB_P2A_AVALON_ADDR_B4 (0),
.bar4_size_mask (0),
.bar4_io_space ("false"),
.bar4_64bit_mem_space ("false"),
.bar4_prefetchable ("false"),
.CB_P2A_AVALON_ADDR_B5 (0),
.bar5_size_mask (0),
.bar5_io_space ("false"),
.bar5_64bit_mem_space ("false"),
.bar5_prefetchable ("false"),
.vendor_id (4466),
.device_id (57345),
.revision_id (1),
.class_code (0),
.subsystem_vendor_id (4466),
.subsystem_device_id (4),
.port_link_number (1),
.msi_function_count (0),
.enable_msi_64bit_addressing ("true"),
.enable_function_msix_support ("false"),
.eie_before_nfts_count (4),
.enable_completion_timeout_disable ("false"),
.completion_timeout ("NONE"),
.enable_adapter_half_rate_mode ("false"),
.msix_pba_bir (0),
.msix_pba_offset (0),
.msix_table_bir (0),
.msix_table_offset (0),
.msix_table_size (0),
.use_crc_forwarding ("false"),
.surprise_down_error_support ("false"),
.dll_active_report_support ("false"),
.bar_io_window_size ("32BIT"),
.bar_prefetchable (32),
.hot_plug_support (7'b0000000),
.no_command_completed ("true"),
.slot_power_limit (0),
.slot_power_scale (0),
.slot_number (0),
.enable_slot_register ("false"),
.advanced_errors ("false"),
.enable_ecrc_check ("false"),
.enable_ecrc_gen ("false"),
.max_payload_size (0),
.retry_buffer_last_active_address (255),
.credit_buffer_allocation_aux ("ABSOLUTE"),
.vc0_rx_flow_ctrl_posted_header (28),
.vc0_rx_flow_ctrl_posted_data (198),
.vc0_rx_flow_ctrl_nonposted_header (30),
.vc0_rx_flow_ctrl_nonposted_data (0),
.vc0_rx_flow_ctrl_compl_header (48),
.vc0_rx_flow_ctrl_compl_data (256),
.RX_BUF (9),
.RH_NUM (7),
.G_TAG_NUM0 (32),
.endpoint_l0_latency (0),
.endpoint_l1_latency (0),
.enable_l1_aspm ("false"),
.l01_entry_latency (31),
.diffclock_nfts_count (255),
.sameclock_nfts_count (255),
.l1_exit_latency_sameclock (7),
.l1_exit_latency_diffclock (7),
.l0_exit_latency_sameclock (7),
.l0_exit_latency_diffclock (7),
.gen2_diffclock_nfts_count (255),
.gen2_sameclock_nfts_count (255),
.CG_COMMON_CLOCK_MODE (1),
.CB_PCIE_MODE (0),
.AST_LITE (0),
.CB_PCIE_RX_LITE (0),
.CG_RXM_IRQ_NUM (16),
.CG_AVALON_S_ADDR_WIDTH (20),
.bypass_tl ("false"),
.CG_IMPL_CRA_AV_SLAVE_PORT (1),
.CG_NO_CPL_REORDERING (0),
.CG_ENABLE_A2P_INTERRUPT (0),
.p_user_msi_enable (0),
.CG_IRQ_BIT_ENA (65535),
.CB_A2P_ADDR_MAP_IS_FIXED (1),
.CB_A2P_ADDR_MAP_NUM_ENTRIES (1),
.CB_A2P_ADDR_MAP_PASS_THRU_BITS (31),
.CB_A2P_ADDR_MAP_FIXED_TABLE_0_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_0_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_1_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_1_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_2_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_2_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_3_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_3_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_4_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_4_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_5_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_5_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_6_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_6_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_7_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_7_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_8_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_8_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_9_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_9_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_10_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_10_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_11_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_11_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_12_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_12_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_13_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_13_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_14_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_14_LOW (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_15_HIGH (32'b00000000000000000000000000000000),
.CB_A2P_ADDR_MAP_FIXED_TABLE_15_LOW (32'b00000000000000000000000000000000),
.RXM_DATA_WIDTH (64),
.RXM_BEN_WIDTH (8),
.TL_SELECTION (1),
.pcie_mode ("SHARED_MODE"),
.single_rx_detect (1),
.enable_coreclk_out_half_rate ("false"),
.low_priority_vc (0),
.link_width (1),
.cyclone4 (1)
) pcie_ip (
.pcie_core_clk_clk (pcie_ip_pcie_core_clk_clk), // pcie_core_clk.clk
.pcie_core_reset_reset_n (pcie_ip_pcie_core_reset_reset), // pcie_core_reset.reset_n
.cal_blk_clk_clk (pcie_ip_pcie_core_clk_clk), // cal_blk_clk.clk
.txs_address (mm_interconnect_0_pcie_ip_txs_address), // txs.address
.txs_chipselect (mm_interconnect_0_pcie_ip_txs_chipselect), // .chipselect
.txs_byteenable (mm_interconnect_0_pcie_ip_txs_byteenable), // .byteenable
.txs_readdata (mm_interconnect_0_pcie_ip_txs_readdata), // .readdata
.txs_writedata (mm_interconnect_0_pcie_ip_txs_writedata), // .writedata
.txs_read (mm_interconnect_0_pcie_ip_txs_read), // .read
.txs_write (mm_interconnect_0_pcie_ip_txs_write), // .write
.txs_burstcount (mm_interconnect_0_pcie_ip_txs_burstcount), // .burstcount
.txs_readdatavalid (mm_interconnect_0_pcie_ip_txs_readdatavalid), // .readdatavalid
.txs_waitrequest (mm_interconnect_0_pcie_ip_txs_waitrequest), // .waitrequest
.refclk_export (pcie_ip_refclk_export), // refclk.export
.test_in_test_in (pcie_ip_test_in_test_in), // test_in.test_in
.pcie_rstn_export (pcie_ip_pcie_rstn_export), // pcie_rstn.export
.clocks_sim_clk250_export (pcie_ip_clocks_sim_clk250_export), // clocks_sim.clk250_export
.clocks_sim_clk500_export (pcie_ip_clocks_sim_clk500_export), // .clk500_export
.clocks_sim_clk125_export (pcie_ip_clocks_sim_clk125_export), // .clk125_export
.reconfig_busy_busy_altgxb_reconfig (pcie_ip_reconfig_busy_busy_altgxb_reconfig), // reconfig_busy.busy_altgxb_reconfig
.pipe_ext_pipe_mode (pcie_ip_pipe_ext_pipe_mode), // pipe_ext.pipe_mode
.pipe_ext_phystatus_ext (pcie_ip_pipe_ext_phystatus_ext), // .phystatus_ext
.pipe_ext_rate_ext (pcie_ip_pipe_ext_rate_ext), // .rate_ext
.pipe_ext_powerdown_ext (pcie_ip_pipe_ext_powerdown_ext), // .powerdown_ext
.pipe_ext_txdetectrx_ext (pcie_ip_pipe_ext_txdetectrx_ext), // .txdetectrx_ext
.pipe_ext_rxelecidle0_ext (pcie_ip_pipe_ext_rxelecidle0_ext), // .rxelecidle0_ext
.pipe_ext_rxdata0_ext (pcie_ip_pipe_ext_rxdata0_ext), // .rxdata0_ext
.pipe_ext_rxstatus0_ext (pcie_ip_pipe_ext_rxstatus0_ext), // .rxstatus0_ext
.pipe_ext_rxvalid0_ext (pcie_ip_pipe_ext_rxvalid0_ext), // .rxvalid0_ext
.pipe_ext_rxdatak0_ext (pcie_ip_pipe_ext_rxdatak0_ext), // .rxdatak0_ext
.pipe_ext_txdata0_ext (pcie_ip_pipe_ext_txdata0_ext), // .txdata0_ext
.pipe_ext_txdatak0_ext (pcie_ip_pipe_ext_txdatak0_ext), // .txdatak0_ext
.pipe_ext_rxpolarity0_ext (pcie_ip_pipe_ext_rxpolarity0_ext), // .rxpolarity0_ext
.pipe_ext_txcompl0_ext (pcie_ip_pipe_ext_txcompl0_ext), // .txcompl0_ext
.pipe_ext_txelecidle0_ext (pcie_ip_pipe_ext_txelecidle0_ext), // .txelecidle0_ext
.powerdown_pll_powerdown (pcie_ip_powerdown_pll_powerdown), // powerdown.pll_powerdown
.powerdown_gxb_powerdown (pcie_ip_powerdown_gxb_powerdown), // .gxb_powerdown
.bar1_0_address (pcie_ip_bar1_0_address), // bar1_0.address
.bar1_0_read (pcie_ip_bar1_0_read), // .read
.bar1_0_waitrequest (pcie_ip_bar1_0_waitrequest), // .waitrequest
.bar1_0_write (pcie_ip_bar1_0_write), // .write
.bar1_0_readdatavalid (pcie_ip_bar1_0_readdatavalid), // .readdatavalid
.bar1_0_readdata (pcie_ip_bar1_0_readdata), // .readdata
.bar1_0_writedata (pcie_ip_bar1_0_writedata), // .writedata
.bar1_0_burstcount (pcie_ip_bar1_0_burstcount), // .burstcount
.bar1_0_byteenable (pcie_ip_bar1_0_byteenable), // .byteenable
.bar2_address (pcie_ip_bar2_address), // bar2.address
.bar2_read (pcie_ip_bar2_read), // .read
.bar2_waitrequest (pcie_ip_bar2_waitrequest), // .waitrequest
.bar2_write (pcie_ip_bar2_write), // .write
.bar2_readdatavalid (pcie_ip_bar2_readdatavalid), // .readdatavalid
.bar2_readdata (pcie_ip_bar2_readdata), // .readdata
.bar2_writedata (pcie_ip_bar2_writedata), // .writedata
.bar2_burstcount (pcie_ip_bar2_burstcount), // .burstcount
.bar2_byteenable (pcie_ip_bar2_byteenable), // .byteenable
.cra_chipselect (mm_interconnect_2_pcie_ip_cra_chipselect), // cra.chipselect
.cra_address (mm_interconnect_2_pcie_ip_cra_address), // .address
.cra_byteenable (mm_interconnect_2_pcie_ip_cra_byteenable), // .byteenable
.cra_read (mm_interconnect_2_pcie_ip_cra_read), // .read
.cra_readdata (mm_interconnect_2_pcie_ip_cra_readdata), // .readdata
.cra_write (mm_interconnect_2_pcie_ip_cra_write), // .write
.cra_writedata (mm_interconnect_2_pcie_ip_cra_writedata), // .writedata
.cra_waitrequest (mm_interconnect_2_pcie_ip_cra_waitrequest), // .waitrequest
.cra_irq_irq (), // cra_irq.irq
.rxm_irq_irq (pcie_ip_rxm_irq_irq), // rxm_irq.irq
.rx_in_rx_datain_0 (pcie_ip_rx_in_rx_datain_0), // rx_in.rx_datain_0
.tx_out_tx_dataout_0 (pcie_ip_tx_out_tx_dataout_0), // tx_out.tx_dataout_0
.reconfig_togxb_data (pcie_ip_reconfig_togxb_data), // reconfig_togxb.data
.reconfig_gxbclk_clk (pcie_ip_pcie_core_clk_clk), // reconfig_gxbclk.clk
.reconfig_fromgxb_0_data (pcie_ip_reconfig_fromgxb_0_data), // reconfig_fromgxb_0.data
.fixedclk_clk (pcie_ip_pcie_core_clk_clk) // fixedclk.clk
);
amm_master_qsys_with_pcie_sdram sdram (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.zs_addr (sdram_addr), // wire.export
.zs_ba (sdram_ba), // .export
.zs_cas_n (sdram_cas_n), // .export
.zs_cke (sdram_cke), // .export
.zs_cs_n (sdram_cs_n), // .export
.zs_dq (sdram_dq), // .export
.zs_dqm (sdram_dqm), // .export
.zs_ras_n (sdram_ras_n), // .export
.zs_we_n (sdram_we_n) // .export
);
amm_master_qsys_with_pcie_sgdma sgdma (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.system_reset_n (~rst_controller_003_reset_out_reset), // reset.reset_n
.csr_chipselect (mm_interconnect_2_sgdma_csr_chipselect), // csr.chipselect
.csr_address (mm_interconnect_2_sgdma_csr_address), // .address
.csr_read (mm_interconnect_2_sgdma_csr_read), // .read
.csr_write (mm_interconnect_2_sgdma_csr_write), // .write
.csr_writedata (mm_interconnect_2_sgdma_csr_writedata), // .writedata
.csr_readdata (mm_interconnect_2_sgdma_csr_readdata), // .readdata
.descriptor_read_readdata (sgdma_descriptor_read_readdata), // descriptor_read.readdata
.descriptor_read_readdatavalid (sgdma_descriptor_read_readdatavalid), // .readdatavalid
.descriptor_read_waitrequest (sgdma_descriptor_read_waitrequest), // .waitrequest
.descriptor_read_address (sgdma_descriptor_read_address), // .address
.descriptor_read_read (sgdma_descriptor_read_read), // .read
.descriptor_write_waitrequest (sgdma_descriptor_write_waitrequest), // descriptor_write.waitrequest
.descriptor_write_address (sgdma_descriptor_write_address), // .address
.descriptor_write_write (sgdma_descriptor_write_write), // .write
.descriptor_write_writedata (sgdma_descriptor_write_writedata), // .writedata
.csr_irq (irq_mapper_receiver0_irq), // csr_irq.irq
.m_read_readdata (sgdma_m_read_readdata), // m_read.readdata
.m_read_readdatavalid (sgdma_m_read_readdatavalid), // .readdatavalid
.m_read_waitrequest (sgdma_m_read_waitrequest), // .waitrequest
.m_read_address (sgdma_m_read_address), // .address
.m_read_read (sgdma_m_read_read), // .read
.m_read_burstcount (sgdma_m_read_burstcount), // .burstcount
.m_write_waitrequest (sgdma_m_write_waitrequest), // m_write.waitrequest
.m_write_address (sgdma_m_write_address), // .address
.m_write_write (sgdma_m_write_write), // .write
.m_write_writedata (sgdma_m_write_writedata), // .writedata
.m_write_byteenable (sgdma_m_write_byteenable), // .byteenable
.m_write_burstcount (sgdma_m_write_burstcount) // .burstcount
);
amm_master_qsys_with_pcie_video_dual_clock_buffer_0 video_dual_clock_buffer_0 (
.clk_stream_in (altpll_qsys_c1_clk), // clock_stream_in.clk
.reset_stream_in (rst_controller_004_reset_out_reset), // reset_stream_in.reset
.clk_stream_out (altpll_qsys_c2_clk), // clock_stream_out.clk
.reset_stream_out (rst_controller_005_reset_out_reset), // reset_stream_out.reset
.stream_in_ready (video_rgb_resampler_0_avalon_rgb_source_ready), // avalon_dc_buffer_sink.ready
.stream_in_startofpacket (video_rgb_resampler_0_avalon_rgb_source_startofpacket), // .startofpacket
.stream_in_endofpacket (video_rgb_resampler_0_avalon_rgb_source_endofpacket), // .endofpacket
.stream_in_valid (video_rgb_resampler_0_avalon_rgb_source_valid), // .valid
.stream_in_data (video_rgb_resampler_0_avalon_rgb_source_data), // .data
.stream_out_ready (video_dual_clock_buffer_0_avalon_dc_buffer_source_ready), // avalon_dc_buffer_source.ready
.stream_out_startofpacket (video_dual_clock_buffer_0_avalon_dc_buffer_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_dual_clock_buffer_0_avalon_dc_buffer_source_endofpacket), // .endofpacket
.stream_out_valid (video_dual_clock_buffer_0_avalon_dc_buffer_source_valid), // .valid
.stream_out_data (video_dual_clock_buffer_0_avalon_dc_buffer_source_data) // .data
);
amm_master_qsys_with_pcie_video_pixel_buffer_dma_0 video_pixel_buffer_dma_0 (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (rst_controller_004_reset_out_reset), // reset.reset
.master_readdatavalid (video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdatavalid), // avalon_pixel_dma_master.readdatavalid
.master_waitrequest (video_pixel_buffer_dma_0_avalon_pixel_dma_master_waitrequest), // .waitrequest
.master_address (video_pixel_buffer_dma_0_avalon_pixel_dma_master_address), // .address
.master_arbiterlock (video_pixel_buffer_dma_0_avalon_pixel_dma_master_lock), // .lock
.master_read (video_pixel_buffer_dma_0_avalon_pixel_dma_master_read), // .read
.master_readdata (video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdata), // .readdata
.slave_address (), // avalon_control_slave.address
.slave_byteenable (), // .byteenable
.slave_read (), // .read
.slave_write (), // .write
.slave_writedata (), // .writedata
.slave_readdata (), // .readdata
.stream_ready (video_pixel_buffer_dma_0_avalon_pixel_source_ready), // avalon_pixel_source.ready
.stream_startofpacket (video_pixel_buffer_dma_0_avalon_pixel_source_startofpacket), // .startofpacket
.stream_endofpacket (video_pixel_buffer_dma_0_avalon_pixel_source_endofpacket), // .endofpacket
.stream_valid (video_pixel_buffer_dma_0_avalon_pixel_source_valid), // .valid
.stream_data (video_pixel_buffer_dma_0_avalon_pixel_source_data) // .data
);
amm_master_qsys_with_pcie_video_rgb_resampler_0 video_rgb_resampler_0 (
.clk (altpll_qsys_c1_clk), // clk.clk
.reset (rst_controller_004_reset_out_reset), // reset.reset
.stream_in_startofpacket (video_pixel_buffer_dma_0_avalon_pixel_source_startofpacket), // avalon_rgb_sink.startofpacket
.stream_in_endofpacket (video_pixel_buffer_dma_0_avalon_pixel_source_endofpacket), // .endofpacket
.stream_in_valid (video_pixel_buffer_dma_0_avalon_pixel_source_valid), // .valid
.stream_in_ready (video_pixel_buffer_dma_0_avalon_pixel_source_ready), // .ready
.stream_in_data (video_pixel_buffer_dma_0_avalon_pixel_source_data), // .data
.stream_out_ready (video_rgb_resampler_0_avalon_rgb_source_ready), // avalon_rgb_source.ready
.stream_out_startofpacket (video_rgb_resampler_0_avalon_rgb_source_startofpacket), // .startofpacket
.stream_out_endofpacket (video_rgb_resampler_0_avalon_rgb_source_endofpacket), // .endofpacket
.stream_out_valid (video_rgb_resampler_0_avalon_rgb_source_valid), // .valid
.stream_out_data (video_rgb_resampler_0_avalon_rgb_source_data) // .data
);
amm_master_qsys_with_pcie_video_vga_controller_0 video_vga_controller_0 (
.clk (altpll_qsys_c2_clk), // clk.clk
.reset (rst_controller_005_reset_out_reset), // reset.reset
.data (video_dual_clock_buffer_0_avalon_dc_buffer_source_data), // avalon_vga_sink.data
.startofpacket (video_dual_clock_buffer_0_avalon_dc_buffer_source_startofpacket), // .startofpacket
.endofpacket (video_dual_clock_buffer_0_avalon_dc_buffer_source_endofpacket), // .endofpacket
.valid (video_dual_clock_buffer_0_avalon_dc_buffer_source_valid), // .valid
.ready (video_dual_clock_buffer_0_avalon_dc_buffer_source_ready), // .ready
.VGA_CLK (video_vga_controller_0_external_interface_CLK), // external_interface.export
.VGA_HS (video_vga_controller_0_external_interface_HS), // .export
.VGA_VS (video_vga_controller_0_external_interface_VS), // .export
.VGA_BLANK (video_vga_controller_0_external_interface_BLANK), // .export
.VGA_SYNC (video_vga_controller_0_external_interface_SYNC), // .export
.VGA_R (video_vga_controller_0_external_interface_R), // .export
.VGA_G (video_vga_controller_0_external_interface_G), // .export
.VGA_B (video_vga_controller_0_external_interface_B) // .export
);
amm_master_qsys_with_pcie_mm_interconnect_0 mm_interconnect_0 (
.altpll_qsys_c1_clk (altpll_qsys_c1_clk), // altpll_qsys_c1.clk
.clk_50_clk_clk (clk_50_clk), // clk_50_clk.clk
.pcie_ip_pcie_core_clk_clk (pcie_ip_pcie_core_clk_clk), // pcie_ip_pcie_core_clk.clk
.altpll_qsys_inclk_interface_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // altpll_qsys_inclk_interface_reset_reset_bridge_in_reset.reset
.custom_module_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // custom_module_reset_reset_bridge_in_reset.reset
.pcie_ip_txs_translator_reset_reset_bridge_in_reset_reset (rst_controller_006_reset_out_reset), // pcie_ip_txs_translator_reset_reset_bridge_in_reset.reset
.sdram_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // sdram_reset_reset_bridge_in_reset.reset
.sgdma_reset_reset_bridge_in_reset_reset (rst_controller_003_reset_out_reset), // sgdma_reset_reset_bridge_in_reset.reset
.video_pixel_buffer_dma_0_reset_reset_bridge_in_reset_reset (rst_controller_004_reset_out_reset), // video_pixel_buffer_dma_0_reset_reset_bridge_in_reset.reset
.custom_module_avalon_master_address (custom_module_avalon_master_address), // custom_module_avalon_master.address
.custom_module_avalon_master_waitrequest (custom_module_avalon_master_waitrequest), // .waitrequest
.custom_module_avalon_master_read (custom_module_avalon_master_read), // .read
.custom_module_avalon_master_readdata (custom_module_avalon_master_readdata), // .readdata
.custom_module_avalon_master_readdatavalid (custom_module_avalon_master_readdatavalid), // .readdatavalid
.custom_module_avalon_master_write (custom_module_avalon_master_write), // .write
.custom_module_avalon_master_writedata (custom_module_avalon_master_writedata), // .writedata
.sgdma_descriptor_read_address (sgdma_descriptor_read_address), // sgdma_descriptor_read.address
.sgdma_descriptor_read_waitrequest (sgdma_descriptor_read_waitrequest), // .waitrequest
.sgdma_descriptor_read_read (sgdma_descriptor_read_read), // .read
.sgdma_descriptor_read_readdata (sgdma_descriptor_read_readdata), // .readdata
.sgdma_descriptor_read_readdatavalid (sgdma_descriptor_read_readdatavalid), // .readdatavalid
.sgdma_descriptor_write_address (sgdma_descriptor_write_address), // sgdma_descriptor_write.address
.sgdma_descriptor_write_waitrequest (sgdma_descriptor_write_waitrequest), // .waitrequest
.sgdma_descriptor_write_write (sgdma_descriptor_write_write), // .write
.sgdma_descriptor_write_writedata (sgdma_descriptor_write_writedata), // .writedata
.sgdma_m_read_address (sgdma_m_read_address), // sgdma_m_read.address
.sgdma_m_read_waitrequest (sgdma_m_read_waitrequest), // .waitrequest
.sgdma_m_read_burstcount (sgdma_m_read_burstcount), // .burstcount
.sgdma_m_read_read (sgdma_m_read_read), // .read
.sgdma_m_read_readdata (sgdma_m_read_readdata), // .readdata
.sgdma_m_read_readdatavalid (sgdma_m_read_readdatavalid), // .readdatavalid
.sgdma_m_write_address (sgdma_m_write_address), // sgdma_m_write.address
.sgdma_m_write_waitrequest (sgdma_m_write_waitrequest), // .waitrequest
.sgdma_m_write_burstcount (sgdma_m_write_burstcount), // .burstcount
.sgdma_m_write_byteenable (sgdma_m_write_byteenable), // .byteenable
.sgdma_m_write_write (sgdma_m_write_write), // .write
.sgdma_m_write_writedata (sgdma_m_write_writedata), // .writedata
.video_pixel_buffer_dma_0_avalon_pixel_dma_master_address (video_pixel_buffer_dma_0_avalon_pixel_dma_master_address), // video_pixel_buffer_dma_0_avalon_pixel_dma_master.address
.video_pixel_buffer_dma_0_avalon_pixel_dma_master_waitrequest (video_pixel_buffer_dma_0_avalon_pixel_dma_master_waitrequest), // .waitrequest
.video_pixel_buffer_dma_0_avalon_pixel_dma_master_read (video_pixel_buffer_dma_0_avalon_pixel_dma_master_read), // .read
.video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdata (video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdata), // .readdata
.video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdatavalid (video_pixel_buffer_dma_0_avalon_pixel_dma_master_readdatavalid), // .readdatavalid
.video_pixel_buffer_dma_0_avalon_pixel_dma_master_lock (video_pixel_buffer_dma_0_avalon_pixel_dma_master_lock), // .lock
.altpll_qsys_pll_slave_address (mm_interconnect_0_altpll_qsys_pll_slave_address), // altpll_qsys_pll_slave.address
.altpll_qsys_pll_slave_write (mm_interconnect_0_altpll_qsys_pll_slave_write), // .write
.altpll_qsys_pll_slave_read (mm_interconnect_0_altpll_qsys_pll_slave_read), // .read
.altpll_qsys_pll_slave_readdata (mm_interconnect_0_altpll_qsys_pll_slave_readdata), // .readdata
.altpll_qsys_pll_slave_writedata (mm_interconnect_0_altpll_qsys_pll_slave_writedata), // .writedata
.pcie_ip_txs_address (mm_interconnect_0_pcie_ip_txs_address), // pcie_ip_txs.address
.pcie_ip_txs_write (mm_interconnect_0_pcie_ip_txs_write), // .write
.pcie_ip_txs_read (mm_interconnect_0_pcie_ip_txs_read), // .read
.pcie_ip_txs_readdata (mm_interconnect_0_pcie_ip_txs_readdata), // .readdata
.pcie_ip_txs_writedata (mm_interconnect_0_pcie_ip_txs_writedata), // .writedata
.pcie_ip_txs_burstcount (mm_interconnect_0_pcie_ip_txs_burstcount), // .burstcount
.pcie_ip_txs_byteenable (mm_interconnect_0_pcie_ip_txs_byteenable), // .byteenable
.pcie_ip_txs_readdatavalid (mm_interconnect_0_pcie_ip_txs_readdatavalid), // .readdatavalid
.pcie_ip_txs_waitrequest (mm_interconnect_0_pcie_ip_txs_waitrequest), // .waitrequest
.pcie_ip_txs_chipselect (mm_interconnect_0_pcie_ip_txs_chipselect), // .chipselect
.sdram_s1_address (mm_interconnect_0_sdram_s1_address), // sdram_s1.address
.sdram_s1_write (mm_interconnect_0_sdram_s1_write), // .write
.sdram_s1_read (mm_interconnect_0_sdram_s1_read), // .read
.sdram_s1_readdata (mm_interconnect_0_sdram_s1_readdata), // .readdata
.sdram_s1_writedata (mm_interconnect_0_sdram_s1_writedata), // .writedata
.sdram_s1_byteenable (mm_interconnect_0_sdram_s1_byteenable), // .byteenable
.sdram_s1_readdatavalid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.sdram_s1_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.sdram_s1_chipselect (mm_interconnect_0_sdram_s1_chipselect) // .chipselect
);
amm_master_qsys_with_pcie_mm_interconnect_1 mm_interconnect_1 (
.clk_50_clk_clk (clk_50_clk), // clk_50_clk.clk
.pcie_ip_pcie_core_clk_clk (pcie_ip_pcie_core_clk_clk), // pcie_ip_pcie_core_clk.clk
.custom_module_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // custom_module_reset_reset_bridge_in_reset.reset
.pcie_ip_bar1_0_translator_reset_reset_bridge_in_reset_reset (rst_controller_006_reset_out_reset), // pcie_ip_bar1_0_translator_reset_reset_bridge_in_reset.reset
.pcie_ip_bar1_0_address (pcie_ip_bar1_0_address), // pcie_ip_bar1_0.address
.pcie_ip_bar1_0_waitrequest (pcie_ip_bar1_0_waitrequest), // .waitrequest
.pcie_ip_bar1_0_burstcount (pcie_ip_bar1_0_burstcount), // .burstcount
.pcie_ip_bar1_0_byteenable (pcie_ip_bar1_0_byteenable), // .byteenable
.pcie_ip_bar1_0_read (pcie_ip_bar1_0_read), // .read
.pcie_ip_bar1_0_readdata (pcie_ip_bar1_0_readdata), // .readdata
.pcie_ip_bar1_0_readdatavalid (pcie_ip_bar1_0_readdatavalid), // .readdatavalid
.pcie_ip_bar1_0_write (pcie_ip_bar1_0_write), // .write
.pcie_ip_bar1_0_writedata (pcie_ip_bar1_0_writedata), // .writedata
.custom_module_avalon_slave_address (mm_interconnect_1_custom_module_avalon_slave_address), // custom_module_avalon_slave.address
.custom_module_avalon_slave_write (mm_interconnect_1_custom_module_avalon_slave_write), // .write
.custom_module_avalon_slave_read (mm_interconnect_1_custom_module_avalon_slave_read), // .read
.custom_module_avalon_slave_readdata (mm_interconnect_1_custom_module_avalon_slave_readdata), // .readdata
.custom_module_avalon_slave_writedata (mm_interconnect_1_custom_module_avalon_slave_writedata), // .writedata
.custom_module_avalon_slave_chipselect (mm_interconnect_1_custom_module_avalon_slave_chipselect) // .chipselect
);
amm_master_qsys_with_pcie_mm_interconnect_2 mm_interconnect_2 (
.pcie_ip_pcie_core_clk_clk (pcie_ip_pcie_core_clk_clk), // pcie_ip_pcie_core_clk.clk
.pcie_ip_bar2_translator_reset_reset_bridge_in_reset_reset (rst_controller_006_reset_out_reset), // pcie_ip_bar2_translator_reset_reset_bridge_in_reset.reset
.sgdma_reset_reset_bridge_in_reset_reset (rst_controller_003_reset_out_reset), // sgdma_reset_reset_bridge_in_reset.reset
.pcie_ip_bar2_address (pcie_ip_bar2_address), // pcie_ip_bar2.address
.pcie_ip_bar2_waitrequest (pcie_ip_bar2_waitrequest), // .waitrequest
.pcie_ip_bar2_burstcount (pcie_ip_bar2_burstcount), // .burstcount
.pcie_ip_bar2_byteenable (pcie_ip_bar2_byteenable), // .byteenable
.pcie_ip_bar2_read (pcie_ip_bar2_read), // .read
.pcie_ip_bar2_readdata (pcie_ip_bar2_readdata), // .readdata
.pcie_ip_bar2_readdatavalid (pcie_ip_bar2_readdatavalid), // .readdatavalid
.pcie_ip_bar2_write (pcie_ip_bar2_write), // .write
.pcie_ip_bar2_writedata (pcie_ip_bar2_writedata), // .writedata
.pcie_ip_cra_address (mm_interconnect_2_pcie_ip_cra_address), // pcie_ip_cra.address
.pcie_ip_cra_write (mm_interconnect_2_pcie_ip_cra_write), // .write
.pcie_ip_cra_read (mm_interconnect_2_pcie_ip_cra_read), // .read
.pcie_ip_cra_readdata (mm_interconnect_2_pcie_ip_cra_readdata), // .readdata
.pcie_ip_cra_writedata (mm_interconnect_2_pcie_ip_cra_writedata), // .writedata
.pcie_ip_cra_byteenable (mm_interconnect_2_pcie_ip_cra_byteenable), // .byteenable
.pcie_ip_cra_waitrequest (mm_interconnect_2_pcie_ip_cra_waitrequest), // .waitrequest
.pcie_ip_cra_chipselect (mm_interconnect_2_pcie_ip_cra_chipselect), // .chipselect
.sgdma_csr_address (mm_interconnect_2_sgdma_csr_address), // sgdma_csr.address
.sgdma_csr_write (mm_interconnect_2_sgdma_csr_write), // .write
.sgdma_csr_read (mm_interconnect_2_sgdma_csr_read), // .read
.sgdma_csr_readdata (mm_interconnect_2_sgdma_csr_readdata), // .readdata
.sgdma_csr_writedata (mm_interconnect_2_sgdma_csr_writedata), // .writedata
.sgdma_csr_chipselect (mm_interconnect_2_sgdma_csr_chipselect) // .chipselect
);
amm_master_qsys_with_pcie_irq_mapper irq_mapper (
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset (rst_controller_006_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (pcie_ip_rxm_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (~pcie_ip_pcie_core_reset_reset), // reset_in1.reset
.clk (clk_50_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_50_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (~pcie_ip_pcie_core_reset_reset), // reset_in1.reset
.clk (altpll_qsys_c1_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_003 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (~pcie_ip_pcie_core_reset_reset), // reset_in1.reset
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset_out (rst_controller_003_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_004 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (altpll_qsys_c1_clk), // clk.clk
.reset_out (rst_controller_004_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_005 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (altpll_qsys_c2_clk), // clk.clk
.reset_out (rst_controller_005_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_006 (
.reset_in0 (~pcie_ip_pcie_core_reset_reset), // reset_in0.reset
.clk (pcie_ip_pcie_core_clk_clk), // clk.clk
.reset_out (rst_controller_006_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// megafunction wizard: %ALTFP_EXP%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_EXP
// ============================================================
// File Name: acl_fp_exp_double.v
// Megafunction Name(s):
// ALTFP_EXP
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_exp CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=25 ROUNDING="TO_NEAREST" WIDTH_EXP=11 WIDTH_MAN=52 clk_en clock data result
//VERSION_BEGIN 10.0SP1 cbx_altfp_exp 2010:08:18:21:07:09:SJ cbx_altmult_opt 2010:08:18:21:07:09:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_clshift 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altmult_opt CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_PIPELINE=4 LPM_WIDTHA=60 LPM_WIDTHB=60 LPM_WIDTHP=120 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altmult_opt 2010:08:18:21:07:09:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//altmult_opt_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=1 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=90 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altmult_opt 2010:08:18:21:07:09:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_exp_double_altmult_opt_csa_ksf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [89:0] dataa;
input [89:0] datab;
output [89:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [89:0] dataa;
tri0 [89:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [89:0] wire_add_sub1_result;
wire [89:0] result_w;
lpm_add_sub add_sub1
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_pipeline = 1,
add_sub1.lpm_representation = "UNSIGNED",
add_sub1.lpm_width = 90,
add_sub1.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub1_result;
endmodule //acl_fp_exp_double_altmult_opt_csa_ksf
//synthesis_resources = lpm_add_sub 3 lpm_mult 3 reg 422
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_exp_double_altmult_opt_a9e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [59:0] dataa;
input [59:0] datab;
output [119:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [89:0] wire_sum_result;
reg [89:0] car_two_adj_reg0;
reg [29:0] lowest_bits_wi_reg0;
reg [29:0] lowest_bits_wi_reg1;
reg [59:0] lsb_prod_wi_reg0;
reg [61:0] mid_prod_wi_reg0;
reg [59:0] msb_prod_wi_reg0;
reg [89:0] sum_two_reg0;
wire wire_compress_a_cout;
wire [29:0] wire_compress_a_result;
wire wire_compress_b_cout;
wire [29:0] wire_compress_b_result;
wire [59:0] wire_lsb_prod_result;
wire [61:0] wire_mid_prod_result;
wire [59:0] wire_msb_prod_result;
wire [89:0] car_one;
wire [89:0] car_one_adj;
wire [89:0] car_two;
wire [89:0] car_two_adj;
wire [89:0] car_two_wo;
wire [29:0] lowest_bits_wi;
wire [29:0] lowest_bits_wo;
wire [59:0] lsb_prod_wi;
wire [59:0] lsb_prod_wo;
wire [61:0] mid_prod_wi;
wire [61:0] mid_prod_wo;
wire [59:0] msb_prod_out;
wire [59:0] msb_prod_wi;
wire [59:0] msb_prod_wo;
wire [89:0] neg_lsb;
wire [89:0] neg_msb;
wire [89:0] sum_one;
wire [89:0] sum_two;
wire [89:0] sum_two_wo;
wire [89:0] vector1;
wire [89:0] vector2;
wire [59:0] wire_a;
wire [59:0] wire_b;
acl_fp_exp_double_altmult_opt_csa_ksf sum
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa(car_two_wo),
.datab(sum_two_wo),
.result(wire_sum_result));
// synopsys translate_off
initial
car_two_adj_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) car_two_adj_reg0 <= 90'b0;
else if (clken == 1'b1) car_two_adj_reg0 <= car_two_adj;
// synopsys translate_off
initial
lowest_bits_wi_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lowest_bits_wi_reg0 <= 30'b0;
else if (clken == 1'b1) lowest_bits_wi_reg0 <= lowest_bits_wi;
// synopsys translate_off
initial
lowest_bits_wi_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lowest_bits_wi_reg1 <= 30'b0;
else if (clken == 1'b1) lowest_bits_wi_reg1 <= lowest_bits_wi_reg0;
// synopsys translate_off
initial
lsb_prod_wi_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lsb_prod_wi_reg0 <= 60'b0;
else if (clken == 1'b1) lsb_prod_wi_reg0 <= lsb_prod_wi;
// synopsys translate_off
initial
mid_prod_wi_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mid_prod_wi_reg0 <= 62'b0;
else if (clken == 1'b1) mid_prod_wi_reg0 <= mid_prod_wi;
// synopsys translate_off
initial
msb_prod_wi_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) msb_prod_wi_reg0 <= 60'b0;
else if (clken == 1'b1) msb_prod_wi_reg0 <= msb_prod_wi;
// synopsys translate_off
initial
sum_two_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sum_two_reg0 <= 90'b0;
else if (clken == 1'b1) sum_two_reg0 <= sum_two;
lpm_add_sub compress_a
(
.cout(wire_compress_a_cout),
.dataa(wire_a[59:30]),
.datab(wire_a[29:0]),
.overflow(),
.result(wire_compress_a_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
compress_a.lpm_direction = "ADD",
compress_a.lpm_representation = "UNSIGNED",
compress_a.lpm_width = 30,
compress_a.lpm_type = "lpm_add_sub";
lpm_add_sub compress_b
(
.cout(wire_compress_b_cout),
.dataa(wire_b[59:30]),
.datab(wire_b[29:0]),
.overflow(),
.result(wire_compress_b_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
compress_b.lpm_direction = "ADD",
compress_b.lpm_representation = "UNSIGNED",
compress_b.lpm_width = 30,
compress_b.lpm_type = "lpm_add_sub";
lpm_mult lsb_prod
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa(wire_a[29:0]),
.datab(wire_b[29:0]),
.result(wire_lsb_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
lsb_prod.lpm_pipeline = 1,
lsb_prod.lpm_representation = "UNSIGNED",
lsb_prod.lpm_widtha = 30,
lsb_prod.lpm_widthb = 30,
lsb_prod.lpm_widthp = 60,
lsb_prod.lpm_type = "lpm_mult",
lsb_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult mid_prod
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa({wire_compress_a_cout, wire_compress_a_result}),
.datab({wire_compress_b_cout, wire_compress_b_result}),
.result(wire_mid_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mid_prod.lpm_pipeline = 1,
mid_prod.lpm_representation = "UNSIGNED",
mid_prod.lpm_widtha = 31,
mid_prod.lpm_widthb = 31,
mid_prod.lpm_widthp = 62,
mid_prod.lpm_type = "lpm_mult",
mid_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult msb_prod
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa(wire_a[59:30]),
.datab(wire_b[59:30]),
.result(wire_msb_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
msb_prod.lpm_pipeline = 1,
msb_prod.lpm_representation = "UNSIGNED",
msb_prod.lpm_widtha = 30,
msb_prod.lpm_widthb = 30,
msb_prod.lpm_widthp = 60,
msb_prod.lpm_type = "lpm_mult",
msb_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign
car_one = {(((vector2[89] & neg_msb[89]) | (vector2[89] & neg_lsb[89])) | (neg_msb[89] & neg_lsb[89])), (((vector2[88] & neg_msb[88]) | (vector2[88] & neg_lsb[88])) | (neg_msb[88] & neg_lsb[88])), (((vector2[87] & neg_msb[87]) | (vector2[87] & neg_lsb[87])) | (neg_msb[87] & neg_lsb[87])), (((vector2[86] & neg_msb[86]) | (vector2[86] & neg_lsb[86])) | (neg_msb[86] & neg_lsb[86])), (((vector2[85] & neg_msb[85]) | (vector2[85] & neg_lsb[85])) | (neg_msb[85] & neg_lsb[85])), (((vector2[84] & neg_msb[84]) | (vector2[84] & neg_lsb[84])) | (neg_msb[84] & neg_lsb[84])), (((vector2[83] & neg_msb[83]) | (vector2[83] & neg_lsb[83])) | (neg_msb[83] & neg_lsb[83])), (((vector2[82] & neg_msb[82]) | (vector2[82] & neg_lsb[82])) | (neg_msb[82] & neg_lsb[82])), (((vector2[81] & neg_msb[81]) | (vector2[81] & neg_lsb[81])) | (neg_msb[81] & neg_lsb[81])), (((vector2[80] & neg_msb[80]) | (vector2[80] & neg_lsb[80])) | (neg_msb[80] & neg_lsb[80])), (((vector2[79] & neg_msb[79]) | (vector2[79] & neg_lsb[79])) | (neg_msb[79] & neg_lsb[79])), (((vector2[78] & neg_msb[78]) | (vector2[78] & neg_lsb[78])) | (neg_msb[78] & neg_lsb[78])), (((vector2[77] & neg_msb[77]) | (vector2[77] & neg_lsb[77])) | (neg_msb[77] & neg_lsb[77])), (((vector2[76] & neg_msb[76]) | (vector2[76] & neg_lsb[76])) | (neg_msb[76] & neg_lsb[76])), (((vector2[75] & neg_msb[75]) | (vector2[75] & neg_lsb[75])) | (neg_msb[75] & neg_lsb[75])), (((vector2[74] & neg_msb[74]) | (vector2[74] & neg_lsb[74])) | (neg_msb[74] & neg_lsb[74])), (((vector2[73] & neg_msb[73]) | (vector2[73] & neg_lsb[73])) | (neg_msb[73] & neg_lsb[73])), (((vector2[72] & neg_msb[72]) | (vector2[72] & neg_lsb[72])) | (neg_msb[72] & neg_lsb[72])), (((vector2[71] & neg_msb[71]) | (vector2[71] & neg_lsb[71])) | (neg_msb[71] & neg_lsb[71])), (((vector2[70] & neg_msb[70]) | (vector2[70] & neg_lsb[70])) | (neg_msb[70] & neg_lsb[70])), (((vector2[69] & neg_msb[69]) | (vector2[69] & neg_lsb[69])) | (neg_msb[69] & neg_lsb[69])), (((vector2[68] & neg_msb[68]) | (vector2[68] & neg_lsb[68])) | (neg_msb[68] & neg_lsb[68]
)), (((vector2[67] & neg_msb[67]) | (vector2[67] & neg_lsb[67])) | (neg_msb[67] & neg_lsb[67])), (((vector2[66] & neg_msb[66]) | (vector2[66] & neg_lsb[66])) | (neg_msb[66] & neg_lsb[66])), (((vector2[65] & neg_msb[65]) | (vector2[65] & neg_lsb[65])) | (neg_msb[65] & neg_lsb[65])), (((vector2[64] & neg_msb[64]) | (vector2[64] & neg_lsb[64])) | (neg_msb[64] & neg_lsb[64])), (((vector2[63] & neg_msb[63]) | (vector2[63] & neg_lsb[63])) | (neg_msb[63] & neg_lsb[63])), (((vector2[62] & neg_msb[62]) | (vector2[62] & neg_lsb[62])) | (neg_msb[62] & neg_lsb[62])), (((vector2[61] & neg_msb[61]) | (vector2[61] & neg_lsb[61])) | (neg_msb[61] & neg_lsb[61])), (((vector2[60] & neg_msb[60]) | (vector2[60] & neg_lsb[60])) | (neg_msb[60] & neg_lsb[60])), (((vector2[59] & neg_msb[59]) | (vector2[59] & neg_lsb[59])) | (neg_msb[59] & neg_lsb[59])), (((vector2[58] & neg_msb[58]) | (vector2[58] & neg_lsb[58])) | (neg_msb[58] & neg_lsb[58])), (((vector2[57] & neg_msb[57]) | (vector2[57] & neg_lsb[57])) | (neg_msb[57] & neg_lsb[57])), (((vector2[56] & neg_msb[56]) | (vector2[56] & neg_lsb[56])) | (neg_msb[56] & neg_lsb[56])), (((vector2[55] & neg_msb[55]) | (vector2[55] & neg_lsb[55])) | (neg_msb[55] & neg_lsb[55])), (((vector2[54] & neg_msb[54]) | (vector2[54] & neg_lsb[54])) | (neg_msb[54] & neg_lsb[54])), (((vector2[53] & neg_msb[53]) | (vector2[53] & neg_lsb[53])) | (neg_msb[53] & neg_lsb[53])), (((vector2[52] & neg_msb[52]) | (vector2[52] & neg_lsb[52])) | (neg_msb[52] & neg_lsb[52])), (((vector2[51] & neg_msb[51]) | (vector2[51] & neg_lsb[51])) | (neg_msb[51] & neg_lsb[51])), (((vector2[50] & neg_msb[50]) | (vector2[50] & neg_lsb[50])) | (neg_msb[50] & neg_lsb[50])), (((vector2[49] & neg_msb[49]) | (vector2[49] & neg_lsb[49])) | (neg_msb[49] & neg_lsb[49])), (((vector2[48] & neg_msb[48]) | (vector2[48] & neg_lsb[48])) | (neg_msb[48] & neg_lsb[48])), (((vector2[47] & neg_msb[47]) | (vector2[47] & neg_lsb[47])) | (neg_msb[47] & neg_lsb[47])), (((vector2[46] & neg_msb[46]) | (vector2[46] & neg_lsb[46])) | (neg_msb[46] & neg_lsb[46]))
, (((vector2[45] & neg_msb[45]) | (vector2[45] & neg_lsb[45])) | (neg_msb[45] & neg_lsb[45])), (((vector2[44] & neg_msb[44]) | (vector2[44] & neg_lsb[44])) | (neg_msb[44] & neg_lsb[44])), (((vector2[43] & neg_msb[43]) | (vector2[43] & neg_lsb[43])) | (neg_msb[43] & neg_lsb[43])), (((vector2[42] & neg_msb[42]) | (vector2[42] & neg_lsb[42])) | (neg_msb[42] & neg_lsb[42])), (((vector2[41] & neg_msb[41]) | (vector2[41] & neg_lsb[41])) | (neg_msb[41] & neg_lsb[41])), (((vector2[40] & neg_msb[40]) | (vector2[40] & neg_lsb[40])) | (neg_msb[40] & neg_lsb[40])), (((vector2[39] & neg_msb[39]) | (vector2[39] & neg_lsb[39])) | (neg_msb[39] & neg_lsb[39])), (((vector2[38] & neg_msb[38]) | (vector2[38] & neg_lsb[38])) | (neg_msb[38] & neg_lsb[38])), (((vector2[37] & neg_msb[37]) | (vector2[37] & neg_lsb[37])) | (neg_msb[37] & neg_lsb[37])), (((vector2[36] & neg_msb[36]) | (vector2[36] & neg_lsb[36])) | (neg_msb[36] & neg_lsb[36])), (((vector2[35] & neg_msb[35]) | (vector2[35] & neg_lsb[35])) | (neg_msb[35] & neg_lsb[35])), (((vector2[34] & neg_msb[34]) | (vector2[34] & neg_lsb[34])) | (neg_msb[34] & neg_lsb[34])), (((vector2[33] & neg_msb[33]) | (vector2[33] & neg_lsb[33])) | (neg_msb[33] & neg_lsb[33])), (((vector2[32] & neg_msb[32]) | (vector2[32] & neg_lsb[32])) | (neg_msb[32] & neg_lsb[32])), (((vector2[31] & neg_msb[31]) | (vector2[31] & neg_lsb[31])) | (neg_msb[31] & neg_lsb[31])), (((vector2[30] & neg_msb[30]) | (vector2[30] & neg_lsb[30])) | (neg_msb[30] & neg_lsb[30])), (((vector2[29] & neg_msb[29]) | (vector2[29] & neg_lsb[29])) | (neg_msb[29] & neg_lsb[29])), (((vector2[28] & neg_msb[28]) | (vector2[28] & neg_lsb[28])) | (neg_msb[28] & neg_lsb[28])), (((vector2[27] & neg_msb[27]) | (vector2[27] & neg_lsb[27])) | (neg_msb[27] & neg_lsb[27])), (((vector2[26] & neg_msb[26]) | (vector2[26] & neg_lsb[26])) | (neg_msb[26] & neg_lsb[26])), (((vector2[25] & neg_msb[25]) | (vector2[25] & neg_lsb[25])) | (neg_msb[25] & neg_lsb[25])), (((vector2[24] & neg_msb[24]) | (vector2[24] & neg_lsb[24])) | (neg_msb[24] & neg_lsb[24])),
(((vector2[23] & neg_msb[23]) | (vector2[23] & neg_lsb[23])) | (neg_msb[23] & neg_lsb[23])), (((vector2[22] & neg_msb[22]) | (vector2[22] & neg_lsb[22])) | (neg_msb[22] & neg_lsb[22])), (((vector2[21] & neg_msb[21]) | (vector2[21] & neg_lsb[21])) | (neg_msb[21] & neg_lsb[21])), (((vector2[20] & neg_msb[20]) | (vector2[20] & neg_lsb[20])) | (neg_msb[20] & neg_lsb[20])), (((vector2[19] & neg_msb[19]) | (vector2[19] & neg_lsb[19])) | (neg_msb[19] & neg_lsb[19])), (((vector2[18] & neg_msb[18]) | (vector2[18] & neg_lsb[18])) | (neg_msb[18] & neg_lsb[18])), (((vector2[17] & neg_msb[17]) | (vector2[17] & neg_lsb[17])) | (neg_msb[17] & neg_lsb[17])), (((vector2[16] & neg_msb[16]) | (vector2[16] & neg_lsb[16])) | (neg_msb[16] & neg_lsb[16])), (((vector2[15] & neg_msb[15]) | (vector2[15] & neg_lsb[15])) | (neg_msb[15] & neg_lsb[15])), (((vector2[14] & neg_msb[14]) | (vector2[14] & neg_lsb[14])) | (neg_msb[14] & neg_lsb[14])), (((vector2[13] & neg_msb[13]) | (vector2[13] & neg_lsb[13])) | (neg_msb[13] & neg_lsb[13])), (((vector2[12] & neg_msb[12]) | (vector2[12] & neg_lsb[12])) | (neg_msb[12] & neg_lsb[12])), (((vector2[11] & neg_msb[11]) | (vector2[11] & neg_lsb[11])) | (neg_msb[11] & neg_lsb[11])), (((vector2[10] & neg_msb[10]) | (vector2[10] & neg_lsb[10])) | (neg_msb[10] & neg_lsb[10])), (((vector2[9] & neg_msb[9]) | (vector2[9] & neg_lsb[9])) | (neg_msb[9] & neg_lsb[9])), (((vector2[8] & neg_msb[8]) | (vector2[8] & neg_lsb[8])) | (neg_msb[8] & neg_lsb[8])), (((vector2[7] & neg_msb[7]) | (vector2[7] & neg_lsb[7])) | (neg_msb[7] & neg_lsb[7])), (((vector2[6] & neg_msb[6]) | (vector2[6] & neg_lsb[6])) | (neg_msb[6] & neg_lsb[6])), (((vector2[5] & neg_msb[5]) | (vector2[5] & neg_lsb[5])) | (neg_msb[5] & neg_lsb[5])), (((vector2[4] & neg_msb[4]) | (vector2[4] & neg_lsb[4])) | (neg_msb[4] & neg_lsb[4])), (((vector2[3] & neg_msb[3]) | (vector2[3] & neg_lsb[3])) | (neg_msb[3] & neg_lsb[3])), (((vector2[2] & neg_msb[2]) | (vector2[2] & neg_lsb[2])) | (neg_msb[2] & neg_lsb[2])), (((vector2[1] & neg_msb[1]) | (vector2[1] & neg_lsb[1]
)) | (neg_msb[1] & neg_lsb[1])), (((vector2[0] & neg_msb[0]) | (vector2[0] & neg_lsb[0])) | (neg_msb[0] & neg_lsb[0]))},
car_one_adj = {car_one[88:0], 1'b1},
car_two = {(((vector1[89] & sum_one[89]) | (vector1[89] & car_one_adj[89])) | (sum_one[89] & car_one_adj[89])), (((vector1[88] & sum_one[88]) | (vector1[88] & car_one_adj[88])) | (sum_one[88] & car_one_adj[88])), (((vector1[87] & sum_one[87]) | (vector1[87] & car_one_adj[87])) | (sum_one[87] & car_one_adj[87])), (((vector1[86] & sum_one[86]) | (vector1[86] & car_one_adj[86])) | (sum_one[86] & car_one_adj[86])), (((vector1[85] & sum_one[85]) | (vector1[85] & car_one_adj[85])) | (sum_one[85] & car_one_adj[85])), (((vector1[84] & sum_one[84]) | (vector1[84] & car_one_adj[84])) | (sum_one[84] & car_one_adj[84])), (((vector1[83] & sum_one[83]) | (vector1[83] & car_one_adj[83])) | (sum_one[83] & car_one_adj[83])), (((vector1[82] & sum_one[82]) | (vector1[82] & car_one_adj[82])) | (sum_one[82] & car_one_adj[82])), (((vector1[81] & sum_one[81]) | (vector1[81] & car_one_adj[81])) | (sum_one[81] & car_one_adj[81])), (((vector1[80] & sum_one[80]) | (vector1[80] & car_one_adj[80])) | (sum_one[80] & car_one_adj[80])), (((vector1[79] & sum_one[79]) | (vector1[79] & car_one_adj[79])) | (sum_one[79] & car_one_adj[79])), (((vector1[78] & sum_one[78]) | (vector1[78] & car_one_adj[78])) | (sum_one[78] & car_one_adj[78])), (((vector1[77] & sum_one[77]) | (vector1[77] & car_one_adj[77])) | (sum_one[77] & car_one_adj[77])), (((vector1[76] & sum_one[76]) | (vector1[76] & car_one_adj[76])) | (sum_one[76] & car_one_adj[76])), (((vector1[75] & sum_one[75]) | (vector1[75] & car_one_adj[75])) | (sum_one[75] & car_one_adj[75])), (((vector1[74] & sum_one[74]) | (vector1[74] & car_one_adj[74])) | (sum_one[74] & car_one_adj[74])), (((vector1[73] & sum_one[73]) | (vector1[73] & car_one_adj[73])) | (sum_one[73] & car_one_adj[73])), (((vector1[72] & sum_one[72]) | (vector1[72] & car_one_adj[72])) | (sum_one[72] & car_one_adj[72])), (((vector1[71] & sum_one[71]) | (vector1[71] & car_one_adj[71])) | (sum_one[71] & car_one_adj[71])), (((vector1[70] & sum_one[70]) | (vector1[70] & car_one_adj[70])) | (sum_one[70] & car_one_adj[70])), (((vector1[69]
& sum_one[69]) | (vector1[69] & car_one_adj[69])) | (sum_one[69] & car_one_adj[69])), (((vector1[68] & sum_one[68]) | (vector1[68] & car_one_adj[68])) | (sum_one[68] & car_one_adj[68])), (((vector1[67] & sum_one[67]) | (vector1[67] & car_one_adj[67])) | (sum_one[67] & car_one_adj[67])), (((vector1[66] & sum_one[66]) | (vector1[66] & car_one_adj[66])) | (sum_one[66] & car_one_adj[66])), (((vector1[65] & sum_one[65]) | (vector1[65] & car_one_adj[65])) | (sum_one[65] & car_one_adj[65])), (((vector1[64] & sum_one[64]) | (vector1[64] & car_one_adj[64])) | (sum_one[64] & car_one_adj[64])), (((vector1[63] & sum_one[63]) | (vector1[63] & car_one_adj[63])) | (sum_one[63] & car_one_adj[63])), (((vector1[62] & sum_one[62]) | (vector1[62] & car_one_adj[62])) | (sum_one[62] & car_one_adj[62])), (((vector1[61] & sum_one[61]) | (vector1[61] & car_one_adj[61])) | (sum_one[61] & car_one_adj[61])), (((vector1[60] & sum_one[60]) | (vector1[60] & car_one_adj[60])) | (sum_one[60] & car_one_adj[60])), (((vector1[59] & sum_one[59]) | (vector1[59] & car_one_adj[59])) | (sum_one[59] & car_one_adj[59])), (((vector1[58] & sum_one[58]) | (vector1[58] & car_one_adj[58])) | (sum_one[58] & car_one_adj[58])), (((vector1[57] & sum_one[57]) | (vector1[57] & car_one_adj[57])) | (sum_one[57] & car_one_adj[57])), (((vector1[56] & sum_one[56]) | (vector1[56] & car_one_adj[56])) | (sum_one[56] & car_one_adj[56])), (((vector1[55] & sum_one[55]) | (vector1[55] & car_one_adj[55])) | (sum_one[55] & car_one_adj[55])), (((vector1[54] & sum_one[54]) | (vector1[54] & car_one_adj[54])) | (sum_one[54] & car_one_adj[54])), (((vector1[53] & sum_one[53]) | (vector1[53] & car_one_adj[53])) | (sum_one[53] & car_one_adj[53])), (((vector1[52] & sum_one[52]) | (vector1[52] & car_one_adj[52])) | (sum_one[52] & car_one_adj[52])), (((vector1[51] & sum_one[51]) | (vector1[51] & car_one_adj[51])) | (sum_one[51] & car_one_adj[51])), (((vector1[50] & sum_one[50]) | (vector1[50] & car_one_adj[50])) | (sum_one[50] & car_one_adj[50])), (((vector1[49] & sum_one[49]) | (vector1[49]
& car_one_adj[49])) | (sum_one[49] & car_one_adj[49])), (((vector1[48] & sum_one[48]) | (vector1[48] & car_one_adj[48])) | (sum_one[48] & car_one_adj[48])), (((vector1[47] & sum_one[47]) | (vector1[47] & car_one_adj[47])) | (sum_one[47] & car_one_adj[47])), (((vector1[46] & sum_one[46]) | (vector1[46] & car_one_adj[46])) | (sum_one[46] & car_one_adj[46])), (((vector1[45] & sum_one[45]) | (vector1[45] & car_one_adj[45])) | (sum_one[45] & car_one_adj[45])), (((vector1[44] & sum_one[44]) | (vector1[44] & car_one_adj[44])) | (sum_one[44] & car_one_adj[44])), (((vector1[43] & sum_one[43]) | (vector1[43] & car_one_adj[43])) | (sum_one[43] & car_one_adj[43])), (((vector1[42] & sum_one[42]) | (vector1[42] & car_one_adj[42])) | (sum_one[42] & car_one_adj[42])), (((vector1[41] & sum_one[41]) | (vector1[41] & car_one_adj[41])) | (sum_one[41] & car_one_adj[41])), (((vector1[40] & sum_one[40]) | (vector1[40] & car_one_adj[40])) | (sum_one[40] & car_one_adj[40])), (((vector1[39] & sum_one[39]) | (vector1[39] & car_one_adj[39])) | (sum_one[39] & car_one_adj[39])), (((vector1[38] & sum_one[38]) | (vector1[38] & car_one_adj[38])) | (sum_one[38] & car_one_adj[38])), (((vector1[37] & sum_one[37]) | (vector1[37] & car_one_adj[37])) | (sum_one[37] & car_one_adj[37])), (((vector1[36] & sum_one[36]) | (vector1[36] & car_one_adj[36])) | (sum_one[36] & car_one_adj[36])), (((vector1[35] & sum_one[35]) | (vector1[35] & car_one_adj[35])) | (sum_one[35] & car_one_adj[35])), (((vector1[34] & sum_one[34]) | (vector1[34] & car_one_adj[34])) | (sum_one[34] & car_one_adj[34])), (((vector1[33] & sum_one[33]) | (vector1[33] & car_one_adj[33])) | (sum_one[33] & car_one_adj[33])), (((vector1[32] & sum_one[32]) | (vector1[32] & car_one_adj[32])) | (sum_one[32] & car_one_adj[32])), (((vector1[31] & sum_one[31]) | (vector1[31] & car_one_adj[31])) | (sum_one[31] & car_one_adj[31])), (((vector1[30] & sum_one[30]) | (vector1[30] & car_one_adj[30])) | (sum_one[30] & car_one_adj[30])), (((vector1[29] & sum_one[29]) | (vector1[29] & car_one_adj[29])) | (sum_one[29]
& car_one_adj[29])), (((vector1[28] & sum_one[28]) | (vector1[28] & car_one_adj[28])) | (sum_one[28] & car_one_adj[28])), (((vector1[27] & sum_one[27]) | (vector1[27] & car_one_adj[27])) | (sum_one[27] & car_one_adj[27])), (((vector1[26] & sum_one[26]) | (vector1[26] & car_one_adj[26])) | (sum_one[26] & car_one_adj[26])), (((vector1[25] & sum_one[25]) | (vector1[25] & car_one_adj[25])) | (sum_one[25] & car_one_adj[25])), (((vector1[24] & sum_one[24]) | (vector1[24] & car_one_adj[24])) | (sum_one[24] & car_one_adj[24])), (((vector1[23] & sum_one[23]) | (vector1[23] & car_one_adj[23])) | (sum_one[23] & car_one_adj[23])), (((vector1[22] & sum_one[22]) | (vector1[22] & car_one_adj[22])) | (sum_one[22] & car_one_adj[22])), (((vector1[21] & sum_one[21]) | (vector1[21] & car_one_adj[21])) | (sum_one[21] & car_one_adj[21])), (((vector1[20] & sum_one[20]) | (vector1[20] & car_one_adj[20])) | (sum_one[20] & car_one_adj[20])), (((vector1[19] & sum_one[19]) | (vector1[19] & car_one_adj[19])) | (sum_one[19] & car_one_adj[19])), (((vector1[18] & sum_one[18]) | (vector1[18] & car_one_adj[18])) | (sum_one[18] & car_one_adj[18])), (((vector1[17] & sum_one[17]) | (vector1[17] & car_one_adj[17])) | (sum_one[17] & car_one_adj[17])), (((vector1[16] & sum_one[16]) | (vector1[16] & car_one_adj[16])) | (sum_one[16] & car_one_adj[16])), (((vector1[15] & sum_one[15]) | (vector1[15] & car_one_adj[15])) | (sum_one[15] & car_one_adj[15])), (((vector1[14] & sum_one[14]) | (vector1[14] & car_one_adj[14])) | (sum_one[14] & car_one_adj[14])), (((vector1[13] & sum_one[13]) | (vector1[13] & car_one_adj[13])) | (sum_one[13] & car_one_adj[13])), (((vector1[12] & sum_one[12]) | (vector1[12] & car_one_adj[12])) | (sum_one[12] & car_one_adj[12])), (((vector1[11] & sum_one[11]) | (vector1[11] & car_one_adj[11])) | (sum_one[11] & car_one_adj[11])), (((vector1[10] & sum_one[10]) | (vector1[10] & car_one_adj[10])) | (sum_one[10] & car_one_adj[10])), (((vector1[9] & sum_one[9]) | (vector1[9] & car_one_adj[9])) | (sum_one[9] & car_one_adj[9])), (((vector1[8]
& sum_one[8]) | (vector1[8] & car_one_adj[8])) | (sum_one[8] & car_one_adj[8])), (((vector1[7] & sum_one[7]) | (vector1[7] & car_one_adj[7])) | (sum_one[7] & car_one_adj[7])), (((vector1[6] & sum_one[6]) | (vector1[6] & car_one_adj[6])) | (sum_one[6] & car_one_adj[6])), (((vector1[5] & sum_one[5]) | (vector1[5] & car_one_adj[5])) | (sum_one[5] & car_one_adj[5])), (((vector1[4] & sum_one[4]) | (vector1[4] & car_one_adj[4])) | (sum_one[4] & car_one_adj[4])), (((vector1[3] & sum_one[3]) | (vector1[3] & car_one_adj[3])) | (sum_one[3] & car_one_adj[3])), (((vector1[2] & sum_one[2]) | (vector1[2] & car_one_adj[2])) | (sum_one[2] & car_one_adj[2])), (((vector1[1] & sum_one[1]) | (vector1[1] & car_one_adj[1])) | (sum_one[1] & car_one_adj[1])), (((vector1[0] & sum_one[0]) | (vector1[0] & car_one_adj[0])) | (sum_one[0] & car_one_adj[0]))},
car_two_adj = {car_two[88:0], 1'b1},
car_two_wo = car_two_adj_reg0,
lowest_bits_wi = lsb_prod_wo[29:0],
lowest_bits_wo = lowest_bits_wi_reg1,
lsb_prod_wi = wire_lsb_prod_result,
lsb_prod_wo = lsb_prod_wi_reg0,
mid_prod_wi = wire_mid_prod_result,
mid_prod_wo = mid_prod_wi_reg0,
msb_prod_out = wire_msb_prod_result,
msb_prod_wi = msb_prod_out,
msb_prod_wo = msb_prod_wi_reg0,
neg_lsb = {{30{1'b1}}, (~ lsb_prod_wo[59]), (~ lsb_prod_wo[58]), (~ lsb_prod_wo[57]), (~ lsb_prod_wo[56]), (~ lsb_prod_wo[55]), (~ lsb_prod_wo[54]), (~ lsb_prod_wo[53]), (~ lsb_prod_wo[52]), (~ lsb_prod_wo[51]), (~ lsb_prod_wo[50]), (~ lsb_prod_wo[49]), (~ lsb_prod_wo[48]), (~ lsb_prod_wo[47]), (~ lsb_prod_wo[46]), (~ lsb_prod_wo[45]), (~ lsb_prod_wo[44]), (~ lsb_prod_wo[43]), (~ lsb_prod_wo[42]), (~ lsb_prod_wo[41]), (~ lsb_prod_wo[40]), (~ lsb_prod_wo[39]), (~ lsb_prod_wo[38]), (~ lsb_prod_wo[37]), (~ lsb_prod_wo[36]), (~ lsb_prod_wo[35]), (~ lsb_prod_wo[34]), (~ lsb_prod_wo[33]), (~ lsb_prod_wo[32]), (~ lsb_prod_wo[31]), (~ lsb_prod_wo[30]), (~ lsb_prod_wo[29]), (~ lsb_prod_wo[28]), (~ lsb_prod_wo[27]), (~ lsb_prod_wo[26]), (~ lsb_prod_wo[25]), (~ lsb_prod_wo[24]), (~ lsb_prod_wo[23]), (~ lsb_prod_wo[22]), (~ lsb_prod_wo[21]), (~ lsb_prod_wo[20]), (~ lsb_prod_wo[19]), (~ lsb_prod_wo[18]), (~ lsb_prod_wo[17]), (~ lsb_prod_wo[16]), (~ lsb_prod_wo[15]), (~ lsb_prod_wo[14]), (~ lsb_prod_wo[13]), (~ lsb_prod_wo[12]), (~ lsb_prod_wo[11]), (~ lsb_prod_wo[10]), (~ lsb_prod_wo[9]), (~ lsb_prod_wo[8]), (~ lsb_prod_wo[7]), (~ lsb_prod_wo[6]), (~ lsb_prod_wo[5]), (~ lsb_prod_wo[4]), (~ lsb_prod_wo[3]), (~ lsb_prod_wo[2]), (~ lsb_prod_wo[1]), (~ lsb_prod_wo[0])},
neg_msb = {{30{1'b1}}, (~ msb_prod_wo[59]), (~ msb_prod_wo[58]), (~ msb_prod_wo[57]), (~ msb_prod_wo[56]), (~ msb_prod_wo[55]), (~ msb_prod_wo[54]), (~ msb_prod_wo[53]), (~ msb_prod_wo[52]), (~ msb_prod_wo[51]), (~ msb_prod_wo[50]), (~ msb_prod_wo[49]), (~ msb_prod_wo[48]), (~ msb_prod_wo[47]), (~ msb_prod_wo[46]), (~ msb_prod_wo[45]), (~ msb_prod_wo[44]), (~ msb_prod_wo[43]), (~ msb_prod_wo[42]), (~ msb_prod_wo[41]), (~ msb_prod_wo[40]), (~ msb_prod_wo[39]), (~ msb_prod_wo[38]), (~ msb_prod_wo[37]), (~ msb_prod_wo[36]), (~ msb_prod_wo[35]), (~ msb_prod_wo[34]), (~ msb_prod_wo[33]), (~ msb_prod_wo[32]), (~ msb_prod_wo[31]), (~ msb_prod_wo[30]), (~ msb_prod_wo[29]), (~ msb_prod_wo[28]), (~ msb_prod_wo[27]), (~ msb_prod_wo[26]), (~ msb_prod_wo[25]), (~ msb_prod_wo[24]), (~ msb_prod_wo[23]), (~ msb_prod_wo[22]), (~ msb_prod_wo[21]), (~ msb_prod_wo[20]), (~ msb_prod_wo[19]), (~ msb_prod_wo[18]), (~ msb_prod_wo[17]), (~ msb_prod_wo[16]), (~ msb_prod_wo[15]), (~ msb_prod_wo[14]), (~ msb_prod_wo[13]), (~ msb_prod_wo[12]), (~ msb_prod_wo[11]), (~ msb_prod_wo[10]), (~ msb_prod_wo[9]), (~ msb_prod_wo[8]), (~ msb_prod_wo[7]), (~ msb_prod_wo[6]), (~ msb_prod_wo[5]), (~ msb_prod_wo[4]), (~ msb_prod_wo[3]), (~ msb_prod_wo[2]), (~ msb_prod_wo[1]), (~ msb_prod_wo[0])},
result = {wire_sum_result[89:0], lowest_bits_wo},
sum_one = {((vector2[89] ^ neg_msb[89]) ^ neg_lsb[89]), ((vector2[88] ^ neg_msb[88]) ^ neg_lsb[88]), ((vector2[87] ^ neg_msb[87]) ^ neg_lsb[87]), ((vector2[86] ^ neg_msb[86]) ^ neg_lsb[86]), ((vector2[85] ^ neg_msb[85]) ^ neg_lsb[85]), ((vector2[84] ^ neg_msb[84]) ^ neg_lsb[84]), ((vector2[83] ^ neg_msb[83]) ^ neg_lsb[83]), ((vector2[82] ^ neg_msb[82]) ^ neg_lsb[82]), ((vector2[81] ^ neg_msb[81]) ^ neg_lsb[81]), ((vector2[80] ^ neg_msb[80]) ^ neg_lsb[80]), ((vector2[79] ^ neg_msb[79]) ^ neg_lsb[79]), ((vector2[78] ^ neg_msb[78]) ^ neg_lsb[78]), ((vector2[77] ^ neg_msb[77]) ^ neg_lsb[77]), ((vector2[76] ^ neg_msb[76]) ^ neg_lsb[76]), ((vector2[75] ^ neg_msb[75]) ^ neg_lsb[75]), ((vector2[74] ^ neg_msb[74]) ^ neg_lsb[74]), ((vector2[73] ^ neg_msb[73]) ^ neg_lsb[73]), ((vector2[72] ^ neg_msb[72]) ^ neg_lsb[72]), ((vector2[71] ^ neg_msb[71]) ^ neg_lsb[71]), ((vector2[70] ^ neg_msb[70]) ^ neg_lsb[70]), ((vector2[69] ^ neg_msb[69]) ^ neg_lsb[69]), ((vector2[68] ^ neg_msb[68]) ^ neg_lsb[68]), ((vector2[67] ^ neg_msb[67]) ^ neg_lsb[67]), ((vector2[66] ^ neg_msb[66]) ^ neg_lsb[66]), ((vector2[65] ^ neg_msb[65]) ^ neg_lsb[65]), ((vector2[64] ^ neg_msb[64]) ^ neg_lsb[64]), ((vector2[63] ^ neg_msb[63]) ^ neg_lsb[63]), ((vector2[62] ^ neg_msb[62]) ^ neg_lsb[62]), ((vector2[61] ^ neg_msb[61]) ^ neg_lsb[61]), ((vector2[60] ^ neg_msb[60]) ^ neg_lsb[60]), ((vector2[59] ^ neg_msb[59]) ^ neg_lsb[59]), ((vector2[58] ^ neg_msb[58]) ^ neg_lsb[58]), ((vector2[57] ^ neg_msb[57]) ^ neg_lsb[57]), ((vector2[56] ^ neg_msb[56]) ^ neg_lsb[56]), ((vector2[55] ^ neg_msb[55]) ^ neg_lsb[55]), ((vector2[54] ^ neg_msb[54]) ^ neg_lsb[54]), ((vector2[53] ^ neg_msb[53]) ^ neg_lsb[53]), ((vector2[52] ^ neg_msb[52]) ^ neg_lsb[52]), ((vector2[51] ^ neg_msb[51]) ^ neg_lsb[51]), ((vector2[50] ^ neg_msb[50]) ^ neg_lsb[50]), ((vector2[49] ^ neg_msb[49]) ^ neg_lsb[49]), ((vector2[48] ^ neg_msb[48]) ^ neg_lsb[48]), ((vector2[47] ^ neg_msb[47]) ^ neg_lsb[47]), ((vector2[46] ^ neg_msb[46]) ^ neg_lsb[46]), ((vector2[45] ^ neg_msb[45]) ^ neg_lsb[45]), ((vector2[44]
^ neg_msb[44]) ^ neg_lsb[44]), ((vector2[43] ^ neg_msb[43]) ^ neg_lsb[43]), ((vector2[42] ^ neg_msb[42]) ^ neg_lsb[42]), ((vector2[41] ^ neg_msb[41]) ^ neg_lsb[41]), ((vector2[40] ^ neg_msb[40]) ^ neg_lsb[40]), ((vector2[39] ^ neg_msb[39]) ^ neg_lsb[39]), ((vector2[38] ^ neg_msb[38]) ^ neg_lsb[38]), ((vector2[37] ^ neg_msb[37]) ^ neg_lsb[37]), ((vector2[36] ^ neg_msb[36]) ^ neg_lsb[36]), ((vector2[35] ^ neg_msb[35]) ^ neg_lsb[35]), ((vector2[34] ^ neg_msb[34]) ^ neg_lsb[34]), ((vector2[33] ^ neg_msb[33]) ^ neg_lsb[33]), ((vector2[32] ^ neg_msb[32]) ^ neg_lsb[32]), ((vector2[31] ^ neg_msb[31]) ^ neg_lsb[31]), ((vector2[30] ^ neg_msb[30]) ^ neg_lsb[30]), ((vector2[29] ^ neg_msb[29]) ^ neg_lsb[29]), ((vector2[28] ^ neg_msb[28]) ^ neg_lsb[28]), ((vector2[27] ^ neg_msb[27]) ^ neg_lsb[27]), ((vector2[26] ^ neg_msb[26]) ^ neg_lsb[26]), ((vector2[25] ^ neg_msb[25]) ^ neg_lsb[25]), ((vector2[24] ^ neg_msb[24]) ^ neg_lsb[24]), ((vector2[23] ^ neg_msb[23]) ^ neg_lsb[23]), ((vector2[22] ^ neg_msb[22]) ^ neg_lsb[22]), ((vector2[21] ^ neg_msb[21]) ^ neg_lsb[21]), ((vector2[20] ^ neg_msb[20]) ^ neg_lsb[20]), ((vector2[19] ^ neg_msb[19]) ^ neg_lsb[19]), ((vector2[18] ^ neg_msb[18]) ^ neg_lsb[18]), ((vector2[17] ^ neg_msb[17]) ^ neg_lsb[17]), ((vector2[16] ^ neg_msb[16]) ^ neg_lsb[16]), ((vector2[15] ^ neg_msb[15]) ^ neg_lsb[15]), ((vector2[14] ^ neg_msb[14]) ^ neg_lsb[14]), ((vector2[13] ^ neg_msb[13]) ^ neg_lsb[13]), ((vector2[12] ^ neg_msb[12]) ^ neg_lsb[12]), ((vector2[11] ^ neg_msb[11]) ^ neg_lsb[11]), ((vector2[10] ^ neg_msb[10]) ^ neg_lsb[10]), ((vector2[9] ^ neg_msb[9]) ^ neg_lsb[9]), ((vector2[8] ^ neg_msb[8]) ^ neg_lsb[8]), ((vector2[7] ^ neg_msb[7]) ^ neg_lsb[7]), ((vector2[6] ^ neg_msb[6]) ^ neg_lsb[6]), ((vector2[5] ^ neg_msb[5]) ^ neg_lsb[5]), ((vector2[4] ^ neg_msb[4]) ^ neg_lsb[4]), ((vector2[3] ^ neg_msb[3]) ^ neg_lsb[3]), ((vector2[2] ^ neg_msb[2]) ^ neg_lsb[2]), ((vector2[1] ^ neg_msb[1]) ^ neg_lsb[1]), ((vector2[0] ^ neg_msb[0]) ^ neg_lsb[0])},
sum_two = {((vector1[89] ^ sum_one[89]) ^ car_one_adj[89]), ((vector1[88] ^ sum_one[88]) ^ car_one_adj[88]), ((vector1[87] ^ sum_one[87]) ^ car_one_adj[87]), ((vector1[86] ^ sum_one[86]) ^ car_one_adj[86]), ((vector1[85] ^ sum_one[85]) ^ car_one_adj[85]), ((vector1[84] ^ sum_one[84]) ^ car_one_adj[84]), ((vector1[83] ^ sum_one[83]) ^ car_one_adj[83]), ((vector1[82] ^ sum_one[82]) ^ car_one_adj[82]), ((vector1[81] ^ sum_one[81]) ^ car_one_adj[81]), ((vector1[80] ^ sum_one[80]) ^ car_one_adj[80]), ((vector1[79] ^ sum_one[79]) ^ car_one_adj[79]), ((vector1[78] ^ sum_one[78]) ^ car_one_adj[78]), ((vector1[77] ^ sum_one[77]) ^ car_one_adj[77]), ((vector1[76] ^ sum_one[76]) ^ car_one_adj[76]), ((vector1[75] ^ sum_one[75]) ^ car_one_adj[75]), ((vector1[74] ^ sum_one[74]) ^ car_one_adj[74]), ((vector1[73] ^ sum_one[73]) ^ car_one_adj[73]), ((vector1[72] ^ sum_one[72]) ^ car_one_adj[72]), ((vector1[71] ^ sum_one[71]) ^ car_one_adj[71]), ((vector1[70] ^ sum_one[70]) ^ car_one_adj[70]), ((vector1[69] ^ sum_one[69]) ^ car_one_adj[69]), ((vector1[68] ^ sum_one[68]) ^ car_one_adj[68]), ((vector1[67] ^ sum_one[67]) ^ car_one_adj[67]), ((vector1[66] ^ sum_one[66]) ^ car_one_adj[66]), ((vector1[65] ^ sum_one[65]) ^ car_one_adj[65]), ((vector1[64] ^ sum_one[64]) ^ car_one_adj[64]), ((vector1[63] ^ sum_one[63]) ^ car_one_adj[63]), ((vector1[62] ^ sum_one[62]) ^ car_one_adj[62]), ((vector1[61] ^ sum_one[61]) ^ car_one_adj[61]), ((vector1[60] ^ sum_one[60]) ^ car_one_adj[60]), ((vector1[59] ^ sum_one[59]) ^ car_one_adj[59]), ((vector1[58] ^ sum_one[58]) ^ car_one_adj[58]), ((vector1[57] ^ sum_one[57]) ^ car_one_adj[57]), ((vector1[56] ^ sum_one[56]) ^ car_one_adj[56]), ((vector1[55] ^ sum_one[55]) ^ car_one_adj[55]), ((vector1[54] ^ sum_one[54]) ^ car_one_adj[54]), ((vector1[53] ^ sum_one[53]) ^ car_one_adj[53]), ((vector1[52] ^ sum_one[52]) ^ car_one_adj[52]), ((vector1[51] ^ sum_one[51]) ^ car_one_adj[51]), ((vector1[50] ^ sum_one[50]) ^ car_one_adj[50]), ((vector1[49] ^ sum_one[49]) ^ car_one_adj[49]), ((vector1[48] ^ sum_one[48]
) ^ car_one_adj[48]), ((vector1[47] ^ sum_one[47]) ^ car_one_adj[47]), ((vector1[46] ^ sum_one[46]) ^ car_one_adj[46]), ((vector1[45] ^ sum_one[45]) ^ car_one_adj[45]), ((vector1[44] ^ sum_one[44]) ^ car_one_adj[44]), ((vector1[43] ^ sum_one[43]) ^ car_one_adj[43]), ((vector1[42] ^ sum_one[42]) ^ car_one_adj[42]), ((vector1[41] ^ sum_one[41]) ^ car_one_adj[41]), ((vector1[40] ^ sum_one[40]) ^ car_one_adj[40]), ((vector1[39] ^ sum_one[39]) ^ car_one_adj[39]), ((vector1[38] ^ sum_one[38]) ^ car_one_adj[38]), ((vector1[37] ^ sum_one[37]) ^ car_one_adj[37]), ((vector1[36] ^ sum_one[36]) ^ car_one_adj[36]), ((vector1[35] ^ sum_one[35]) ^ car_one_adj[35]), ((vector1[34] ^ sum_one[34]) ^ car_one_adj[34]), ((vector1[33] ^ sum_one[33]) ^ car_one_adj[33]), ((vector1[32] ^ sum_one[32]) ^ car_one_adj[32]), ((vector1[31] ^ sum_one[31]) ^ car_one_adj[31]), ((vector1[30] ^ sum_one[30]) ^ car_one_adj[30]), ((vector1[29] ^ sum_one[29]) ^ car_one_adj[29]), ((vector1[28] ^ sum_one[28]) ^ car_one_adj[28]), ((vector1[27] ^ sum_one[27]) ^ car_one_adj[27]), ((vector1[26] ^ sum_one[26]) ^ car_one_adj[26]), ((vector1[25] ^ sum_one[25]) ^ car_one_adj[25]), ((vector1[24] ^ sum_one[24]) ^ car_one_adj[24]), ((vector1[23] ^ sum_one[23]) ^ car_one_adj[23]), ((vector1[22] ^ sum_one[22]) ^ car_one_adj[22]), ((vector1[21] ^ sum_one[21]) ^ car_one_adj[21]), ((vector1[20] ^ sum_one[20]) ^ car_one_adj[20]), ((vector1[19] ^ sum_one[19]) ^ car_one_adj[19]), ((vector1[18] ^ sum_one[18]) ^ car_one_adj[18]), ((vector1[17] ^ sum_one[17]) ^ car_one_adj[17]), ((vector1[16] ^ sum_one[16]) ^ car_one_adj[16]), ((vector1[15] ^ sum_one[15]) ^ car_one_adj[15]), ((vector1[14] ^ sum_one[14]) ^ car_one_adj[14]), ((vector1[13] ^ sum_one[13]) ^ car_one_adj[13]), ((vector1[12] ^ sum_one[12]) ^ car_one_adj[12]), ((vector1[11] ^ sum_one[11]) ^ car_one_adj[11]), ((vector1[10] ^ sum_one[10]) ^ car_one_adj[10]), ((vector1[9] ^ sum_one[9]) ^ car_one_adj[9]), ((vector1[8] ^ sum_one[8]) ^ car_one_adj[8]), ((vector1[7] ^ sum_one[7]) ^ car_one_adj[7]), ((vector1[6] ^ sum_one[6])
^ car_one_adj[6]), ((vector1[5] ^ sum_one[5]) ^ car_one_adj[5]), ((vector1[4] ^ sum_one[4]) ^ car_one_adj[4]), ((vector1[3] ^ sum_one[3]) ^ car_one_adj[3]), ((vector1[2] ^ sum_one[2]) ^ car_one_adj[2]), ((vector1[1] ^ sum_one[1]) ^ car_one_adj[1]), ((vector1[0] ^ sum_one[0]) ^ car_one_adj[0])},
sum_two_wo = sum_two_reg0,
vector1 = {msb_prod_wo, lsb_prod_wo[59:30]},
vector2 = {{28{1'b0}}, mid_prod_wo},
wire_a = dataa,
wire_b = datab;
endmodule //acl_fp_exp_double_altmult_opt_a9e
//altmult_opt CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_PIPELINE=5 LPM_WIDTHA=61 LPM_WIDTHB=61 LPM_WIDTHP=122 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altmult_opt 2010:08:18:21:07:09:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//altmult_opt_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=2 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=92 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altmult_opt 2010:08:18:21:07:09:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_exp_double_altmult_opt_csa_nsf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [91:0] dataa;
input [91:0] datab;
output [91:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [91:0] dataa;
tri0 [91:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [91:0] wire_add_sub2_result;
wire [91:0] result_w;
lpm_add_sub add_sub2
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub2.lpm_direction = "ADD",
add_sub2.lpm_pipeline = 2,
add_sub2.lpm_representation = "UNSIGNED",
add_sub2.lpm_width = 92,
add_sub2.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub2_result;
endmodule //acl_fp_exp_double_altmult_opt_csa_nsf
//synthesis_resources = lpm_add_sub 3 lpm_mult 3 reg 464
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_exp_double_altmult_opt_f9e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [60:0] dataa;
input [60:0] datab;
output [121:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [91:0] wire_sum_result;
reg [91:0] car_two_adj_reg0;
reg [30:0] lowest_bits_wi_reg0;
reg [30:0] lowest_bits_wi_reg1;
reg [30:0] lowest_bits_wi_reg2;
reg [61:0] lsb_prod_wi_reg0;
reg [63:0] mid_prod_wi_reg0;
reg [60:0] msb_prod_wi_reg0;
reg [91:0] sum_two_reg0;
wire wire_compress_a_cout;
wire [30:0] wire_compress_a_result;
wire wire_compress_b_cout;
wire [30:0] wire_compress_b_result;
wire [61:0] wire_lsb_prod_result;
wire [63:0] wire_mid_prod_result;
wire [60:0] wire_msb_prod_result;
wire [91:0] car_one;
wire [91:0] car_one_adj;
wire [91:0] car_two;
wire [91:0] car_two_adj;
wire [91:0] car_two_wo;
wire [30:0] lowest_bits_wi;
wire [30:0] lowest_bits_wo;
wire [61:0] lsb_prod_wi;
wire [61:0] lsb_prod_wo;
wire [63:0] mid_prod_wi;
wire [63:0] mid_prod_wo;
wire [60:0] msb_prod_out;
wire [60:0] msb_prod_wi;
wire [60:0] msb_prod_wo;
wire [91:0] neg_lsb;
wire [91:0] neg_msb;
wire [91:0] sum_one;
wire [91:0] sum_two;
wire [91:0] sum_two_wo;
wire [91:0] vector1;
wire [91:0] vector2;
wire [60:0] wire_a;
wire [60:0] wire_b;
acl_fp_exp_double_altmult_opt_csa_nsf sum
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa(car_two_wo),
.datab(sum_two_wo),
.result(wire_sum_result));
// synopsys translate_off
initial
car_two_adj_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) car_two_adj_reg0 <= 92'b0;
else if (clken == 1'b1) car_two_adj_reg0 <= car_two_adj;
// synopsys translate_off
initial
lowest_bits_wi_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lowest_bits_wi_reg0 <= 31'b0;
else if (clken == 1'b1) lowest_bits_wi_reg0 <= lowest_bits_wi;
// synopsys translate_off
initial
lowest_bits_wi_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lowest_bits_wi_reg1 <= 31'b0;
else if (clken == 1'b1) lowest_bits_wi_reg1 <= lowest_bits_wi_reg0;
// synopsys translate_off
initial
lowest_bits_wi_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lowest_bits_wi_reg2 <= 31'b0;
else if (clken == 1'b1) lowest_bits_wi_reg2 <= lowest_bits_wi_reg1;
// synopsys translate_off
initial
lsb_prod_wi_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lsb_prod_wi_reg0 <= 62'b0;
else if (clken == 1'b1) lsb_prod_wi_reg0 <= lsb_prod_wi;
// synopsys translate_off
initial
mid_prod_wi_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mid_prod_wi_reg0 <= 64'b0;
else if (clken == 1'b1) mid_prod_wi_reg0 <= mid_prod_wi;
// synopsys translate_off
initial
msb_prod_wi_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) msb_prod_wi_reg0 <= 61'b0;
else if (clken == 1'b1) msb_prod_wi_reg0 <= msb_prod_wi;
// synopsys translate_off
initial
sum_two_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sum_two_reg0 <= 92'b0;
else if (clken == 1'b1) sum_two_reg0 <= sum_two;
lpm_add_sub compress_a
(
.cout(wire_compress_a_cout),
.dataa({1'b0, wire_a[60:31]}),
.datab(wire_a[30:0]),
.overflow(),
.result(wire_compress_a_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
compress_a.lpm_direction = "ADD",
compress_a.lpm_representation = "UNSIGNED",
compress_a.lpm_width = 31,
compress_a.lpm_type = "lpm_add_sub";
lpm_add_sub compress_b
(
.cout(wire_compress_b_cout),
.dataa({1'b0, wire_b[60:31]}),
.datab(wire_b[30:0]),
.overflow(),
.result(wire_compress_b_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
compress_b.lpm_direction = "ADD",
compress_b.lpm_representation = "UNSIGNED",
compress_b.lpm_width = 31,
compress_b.lpm_type = "lpm_add_sub";
lpm_mult lsb_prod
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa(wire_a[30:0]),
.datab(wire_b[30:0]),
.result(wire_lsb_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
lsb_prod.lpm_pipeline = 1,
lsb_prod.lpm_representation = "UNSIGNED",
lsb_prod.lpm_widtha = 31,
lsb_prod.lpm_widthb = 31,
lsb_prod.lpm_widthp = 62,
lsb_prod.lpm_type = "lpm_mult",
lsb_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult mid_prod
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa({wire_compress_a_cout, wire_compress_a_result}),
.datab({wire_compress_b_cout, wire_compress_b_result}),
.result(wire_mid_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mid_prod.lpm_pipeline = 1,
mid_prod.lpm_representation = "UNSIGNED",
mid_prod.lpm_widtha = 32,
mid_prod.lpm_widthb = 32,
mid_prod.lpm_widthp = 64,
mid_prod.lpm_type = "lpm_mult",
mid_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult msb_prod
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa({1'b0, wire_a[60:31]}),
.datab(wire_b[60:31]),
.result(wire_msb_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
msb_prod.lpm_pipeline = 1,
msb_prod.lpm_representation = "UNSIGNED",
msb_prod.lpm_widtha = 31,
msb_prod.lpm_widthb = 30,
msb_prod.lpm_widthp = 61,
msb_prod.lpm_type = "lpm_mult",
msb_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign
car_one = {(((vector2[91] & neg_msb[91]) | (vector2[91] & neg_lsb[91])) | (neg_msb[91] & neg_lsb[91])), (((vector2[90] & neg_msb[90]) | (vector2[90] & neg_lsb[90])) | (neg_msb[90] & neg_lsb[90])), (((vector2[89] & neg_msb[89]) | (vector2[89] & neg_lsb[89])) | (neg_msb[89] & neg_lsb[89])), (((vector2[88] & neg_msb[88]) | (vector2[88] & neg_lsb[88])) | (neg_msb[88] & neg_lsb[88])), (((vector2[87] & neg_msb[87]) | (vector2[87] & neg_lsb[87])) | (neg_msb[87] & neg_lsb[87])), (((vector2[86] & neg_msb[86]) | (vector2[86] & neg_lsb[86])) | (neg_msb[86] & neg_lsb[86])), (((vector2[85] & neg_msb[85]) | (vector2[85] & neg_lsb[85])) | (neg_msb[85] & neg_lsb[85])), (((vector2[84] & neg_msb[84]) | (vector2[84] & neg_lsb[84])) | (neg_msb[84] & neg_lsb[84])), (((vector2[83] & neg_msb[83]) | (vector2[83] & neg_lsb[83])) | (neg_msb[83] & neg_lsb[83])), (((vector2[82] & neg_msb[82]) | (vector2[82] & neg_lsb[82])) | (neg_msb[82] & neg_lsb[82])), (((vector2[81] & neg_msb[81]) | (vector2[81] & neg_lsb[81])) | (neg_msb[81] & neg_lsb[81])), (((vector2[80] & neg_msb[80]) | (vector2[80] & neg_lsb[80])) | (neg_msb[80] & neg_lsb[80])), (((vector2[79] & neg_msb[79]) | (vector2[79] & neg_lsb[79])) | (neg_msb[79] & neg_lsb[79])), (((vector2[78] & neg_msb[78]) | (vector2[78] & neg_lsb[78])) | (neg_msb[78] & neg_lsb[78])), (((vector2[77] & neg_msb[77]) | (vector2[77] & neg_lsb[77])) | (neg_msb[77] & neg_lsb[77])), (((vector2[76] & neg_msb[76]) | (vector2[76] & neg_lsb[76])) | (neg_msb[76] & neg_lsb[76])), (((vector2[75] & neg_msb[75]) | (vector2[75] & neg_lsb[75])) | (neg_msb[75] & neg_lsb[75])), (((vector2[74] & neg_msb[74]) | (vector2[74] & neg_lsb[74])) | (neg_msb[74] & neg_lsb[74])), (((vector2[73] & neg_msb[73]) | (vector2[73] & neg_lsb[73])) | (neg_msb[73] & neg_lsb[73])), (((vector2[72] & neg_msb[72]) | (vector2[72] & neg_lsb[72])) | (neg_msb[72] & neg_lsb[72])), (((vector2[71] & neg_msb[71]) | (vector2[71] & neg_lsb[71])) | (neg_msb[71] & neg_lsb[71])), (((vector2[70] & neg_msb[70]) | (vector2[70] & neg_lsb[70])) | (neg_msb[70] & neg_lsb[70]
)), (((vector2[69] & neg_msb[69]) | (vector2[69] & neg_lsb[69])) | (neg_msb[69] & neg_lsb[69])), (((vector2[68] & neg_msb[68]) | (vector2[68] & neg_lsb[68])) | (neg_msb[68] & neg_lsb[68])), (((vector2[67] & neg_msb[67]) | (vector2[67] & neg_lsb[67])) | (neg_msb[67] & neg_lsb[67])), (((vector2[66] & neg_msb[66]) | (vector2[66] & neg_lsb[66])) | (neg_msb[66] & neg_lsb[66])), (((vector2[65] & neg_msb[65]) | (vector2[65] & neg_lsb[65])) | (neg_msb[65] & neg_lsb[65])), (((vector2[64] & neg_msb[64]) | (vector2[64] & neg_lsb[64])) | (neg_msb[64] & neg_lsb[64])), (((vector2[63] & neg_msb[63]) | (vector2[63] & neg_lsb[63])) | (neg_msb[63] & neg_lsb[63])), (((vector2[62] & neg_msb[62]) | (vector2[62] & neg_lsb[62])) | (neg_msb[62] & neg_lsb[62])), (((vector2[61] & neg_msb[61]) | (vector2[61] & neg_lsb[61])) | (neg_msb[61] & neg_lsb[61])), (((vector2[60] & neg_msb[60]) | (vector2[60] & neg_lsb[60])) | (neg_msb[60] & neg_lsb[60])), (((vector2[59] & neg_msb[59]) | (vector2[59] & neg_lsb[59])) | (neg_msb[59] & neg_lsb[59])), (((vector2[58] & neg_msb[58]) | (vector2[58] & neg_lsb[58])) | (neg_msb[58] & neg_lsb[58])), (((vector2[57] & neg_msb[57]) | (vector2[57] & neg_lsb[57])) | (neg_msb[57] & neg_lsb[57])), (((vector2[56] & neg_msb[56]) | (vector2[56] & neg_lsb[56])) | (neg_msb[56] & neg_lsb[56])), (((vector2[55] & neg_msb[55]) | (vector2[55] & neg_lsb[55])) | (neg_msb[55] & neg_lsb[55])), (((vector2[54] & neg_msb[54]) | (vector2[54] & neg_lsb[54])) | (neg_msb[54] & neg_lsb[54])), (((vector2[53] & neg_msb[53]) | (vector2[53] & neg_lsb[53])) | (neg_msb[53] & neg_lsb[53])), (((vector2[52] & neg_msb[52]) | (vector2[52] & neg_lsb[52])) | (neg_msb[52] & neg_lsb[52])), (((vector2[51] & neg_msb[51]) | (vector2[51] & neg_lsb[51])) | (neg_msb[51] & neg_lsb[51])), (((vector2[50] & neg_msb[50]) | (vector2[50] & neg_lsb[50])) | (neg_msb[50] & neg_lsb[50])), (((vector2[49] & neg_msb[49]) | (vector2[49] & neg_lsb[49])) | (neg_msb[49] & neg_lsb[49])), (((vector2[48] & neg_msb[48]) | (vector2[48] & neg_lsb[48])) | (neg_msb[48] & neg_lsb[48]))
, (((vector2[47] & neg_msb[47]) | (vector2[47] & neg_lsb[47])) | (neg_msb[47] & neg_lsb[47])), (((vector2[46] & neg_msb[46]) | (vector2[46] & neg_lsb[46])) | (neg_msb[46] & neg_lsb[46])), (((vector2[45] & neg_msb[45]) | (vector2[45] & neg_lsb[45])) | (neg_msb[45] & neg_lsb[45])), (((vector2[44] & neg_msb[44]) | (vector2[44] & neg_lsb[44])) | (neg_msb[44] & neg_lsb[44])), (((vector2[43] & neg_msb[43]) | (vector2[43] & neg_lsb[43])) | (neg_msb[43] & neg_lsb[43])), (((vector2[42] & neg_msb[42]) | (vector2[42] & neg_lsb[42])) | (neg_msb[42] & neg_lsb[42])), (((vector2[41] & neg_msb[41]) | (vector2[41] & neg_lsb[41])) | (neg_msb[41] & neg_lsb[41])), (((vector2[40] & neg_msb[40]) | (vector2[40] & neg_lsb[40])) | (neg_msb[40] & neg_lsb[40])), (((vector2[39] & neg_msb[39]) | (vector2[39] & neg_lsb[39])) | (neg_msb[39] & neg_lsb[39])), (((vector2[38] & neg_msb[38]) | (vector2[38] & neg_lsb[38])) | (neg_msb[38] & neg_lsb[38])), (((vector2[37] & neg_msb[37]) | (vector2[37] & neg_lsb[37])) | (neg_msb[37] & neg_lsb[37])), (((vector2[36] & neg_msb[36]) | (vector2[36] & neg_lsb[36])) | (neg_msb[36] & neg_lsb[36])), (((vector2[35] & neg_msb[35]) | (vector2[35] & neg_lsb[35])) | (neg_msb[35] & neg_lsb[35])), (((vector2[34] & neg_msb[34]) | (vector2[34] & neg_lsb[34])) | (neg_msb[34] & neg_lsb[34])), (((vector2[33] & neg_msb[33]) | (vector2[33] & neg_lsb[33])) | (neg_msb[33] & neg_lsb[33])), (((vector2[32] & neg_msb[32]) | (vector2[32] & neg_lsb[32])) | (neg_msb[32] & neg_lsb[32])), (((vector2[31] & neg_msb[31]) | (vector2[31] & neg_lsb[31])) | (neg_msb[31] & neg_lsb[31])), (((vector2[30] & neg_msb[30]) | (vector2[30] & neg_lsb[30])) | (neg_msb[30] & neg_lsb[30])), (((vector2[29] & neg_msb[29]) | (vector2[29] & neg_lsb[29])) | (neg_msb[29] & neg_lsb[29])), (((vector2[28] & neg_msb[28]) | (vector2[28] & neg_lsb[28])) | (neg_msb[28] & neg_lsb[28])), (((vector2[27] & neg_msb[27]) | (vector2[27] & neg_lsb[27])) | (neg_msb[27] & neg_lsb[27])), (((vector2[26] & neg_msb[26]) | (vector2[26] & neg_lsb[26])) | (neg_msb[26] & neg_lsb[26])),
(((vector2[25] & neg_msb[25]) | (vector2[25] & neg_lsb[25])) | (neg_msb[25] & neg_lsb[25])), (((vector2[24] & neg_msb[24]) | (vector2[24] & neg_lsb[24])) | (neg_msb[24] & neg_lsb[24])), (((vector2[23] & neg_msb[23]) | (vector2[23] & neg_lsb[23])) | (neg_msb[23] & neg_lsb[23])), (((vector2[22] & neg_msb[22]) | (vector2[22] & neg_lsb[22])) | (neg_msb[22] & neg_lsb[22])), (((vector2[21] & neg_msb[21]) | (vector2[21] & neg_lsb[21])) | (neg_msb[21] & neg_lsb[21])), (((vector2[20] & neg_msb[20]) | (vector2[20] & neg_lsb[20])) | (neg_msb[20] & neg_lsb[20])), (((vector2[19] & neg_msb[19]) | (vector2[19] & neg_lsb[19])) | (neg_msb[19] & neg_lsb[19])), (((vector2[18] & neg_msb[18]) | (vector2[18] & neg_lsb[18])) | (neg_msb[18] & neg_lsb[18])), (((vector2[17] & neg_msb[17]) | (vector2[17] & neg_lsb[17])) | (neg_msb[17] & neg_lsb[17])), (((vector2[16] & neg_msb[16]) | (vector2[16] & neg_lsb[16])) | (neg_msb[16] & neg_lsb[16])), (((vector2[15] & neg_msb[15]) | (vector2[15] & neg_lsb[15])) | (neg_msb[15] & neg_lsb[15])), (((vector2[14] & neg_msb[14]) | (vector2[14] & neg_lsb[14])) | (neg_msb[14] & neg_lsb[14])), (((vector2[13] & neg_msb[13]) | (vector2[13] & neg_lsb[13])) | (neg_msb[13] & neg_lsb[13])), (((vector2[12] & neg_msb[12]) | (vector2[12] & neg_lsb[12])) | (neg_msb[12] & neg_lsb[12])), (((vector2[11] & neg_msb[11]) | (vector2[11] & neg_lsb[11])) | (neg_msb[11] & neg_lsb[11])), (((vector2[10] & neg_msb[10]) | (vector2[10] & neg_lsb[10])) | (neg_msb[10] & neg_lsb[10])), (((vector2[9] & neg_msb[9]) | (vector2[9] & neg_lsb[9])) | (neg_msb[9] & neg_lsb[9])), (((vector2[8] & neg_msb[8]) | (vector2[8] & neg_lsb[8])) | (neg_msb[8] & neg_lsb[8])), (((vector2[7] & neg_msb[7]) | (vector2[7] & neg_lsb[7])) | (neg_msb[7] & neg_lsb[7])), (((vector2[6] & neg_msb[6]) | (vector2[6] & neg_lsb[6])) | (neg_msb[6] & neg_lsb[6])), (((vector2[5] & neg_msb[5]) | (vector2[5] & neg_lsb[5])) | (neg_msb[5] & neg_lsb[5])), (((vector2[4] & neg_msb[4]) | (vector2[4] & neg_lsb[4])) | (neg_msb[4] & neg_lsb[4])), (((vector2[3] & neg_msb[3]) | (vector2[3]
& neg_lsb[3])) | (neg_msb[3] & neg_lsb[3])), (((vector2[2] & neg_msb[2]) | (vector2[2] & neg_lsb[2])) | (neg_msb[2] & neg_lsb[2])), (((vector2[1] & neg_msb[1]) | (vector2[1] & neg_lsb[1])) | (neg_msb[1] & neg_lsb[1])), (((vector2[0] & neg_msb[0]) | (vector2[0] & neg_lsb[0])) | (neg_msb[0] & neg_lsb[0]))},
car_one_adj = {car_one[90:0], 1'b1},
car_two = {(((vector1[91] & sum_one[91]) | (vector1[91] & car_one_adj[91])) | (sum_one[91] & car_one_adj[91])), (((vector1[90] & sum_one[90]) | (vector1[90] & car_one_adj[90])) | (sum_one[90] & car_one_adj[90])), (((vector1[89] & sum_one[89]) | (vector1[89] & car_one_adj[89])) | (sum_one[89] & car_one_adj[89])), (((vector1[88] & sum_one[88]) | (vector1[88] & car_one_adj[88])) | (sum_one[88] & car_one_adj[88])), (((vector1[87] & sum_one[87]) | (vector1[87] & car_one_adj[87])) | (sum_one[87] & car_one_adj[87])), (((vector1[86] & sum_one[86]) | (vector1[86] & car_one_adj[86])) | (sum_one[86] & car_one_adj[86])), (((vector1[85] & sum_one[85]) | (vector1[85] & car_one_adj[85])) | (sum_one[85] & car_one_adj[85])), (((vector1[84] & sum_one[84]) | (vector1[84] & car_one_adj[84])) | (sum_one[84] & car_one_adj[84])), (((vector1[83] & sum_one[83]) | (vector1[83] & car_one_adj[83])) | (sum_one[83] & car_one_adj[83])), (((vector1[82] & sum_one[82]) | (vector1[82] & car_one_adj[82])) | (sum_one[82] & car_one_adj[82])), (((vector1[81] & sum_one[81]) | (vector1[81] & car_one_adj[81])) | (sum_one[81] & car_one_adj[81])), (((vector1[80] & sum_one[80]) | (vector1[80] & car_one_adj[80])) | (sum_one[80] & car_one_adj[80])), (((vector1[79] & sum_one[79]) | (vector1[79] & car_one_adj[79])) | (sum_one[79] & car_one_adj[79])), (((vector1[78] & sum_one[78]) | (vector1[78] & car_one_adj[78])) | (sum_one[78] & car_one_adj[78])), (((vector1[77] & sum_one[77]) | (vector1[77] & car_one_adj[77])) | (sum_one[77] & car_one_adj[77])), (((vector1[76] & sum_one[76]) | (vector1[76] & car_one_adj[76])) | (sum_one[76] & car_one_adj[76])), (((vector1[75] & sum_one[75]) | (vector1[75] & car_one_adj[75])) | (sum_one[75] & car_one_adj[75])), (((vector1[74] & sum_one[74]) | (vector1[74] & car_one_adj[74])) | (sum_one[74] & car_one_adj[74])), (((vector1[73] & sum_one[73]) | (vector1[73] & car_one_adj[73])) | (sum_one[73] & car_one_adj[73])), (((vector1[72] & sum_one[72]) | (vector1[72] & car_one_adj[72])) | (sum_one[72] & car_one_adj[72])), (((vector1[71]
& sum_one[71]) | (vector1[71] & car_one_adj[71])) | (sum_one[71] & car_one_adj[71])), (((vector1[70] & sum_one[70]) | (vector1[70] & car_one_adj[70])) | (sum_one[70] & car_one_adj[70])), (((vector1[69] & sum_one[69]) | (vector1[69] & car_one_adj[69])) | (sum_one[69] & car_one_adj[69])), (((vector1[68] & sum_one[68]) | (vector1[68] & car_one_adj[68])) | (sum_one[68] & car_one_adj[68])), (((vector1[67] & sum_one[67]) | (vector1[67] & car_one_adj[67])) | (sum_one[67] & car_one_adj[67])), (((vector1[66] & sum_one[66]) | (vector1[66] & car_one_adj[66])) | (sum_one[66] & car_one_adj[66])), (((vector1[65] & sum_one[65]) | (vector1[65] & car_one_adj[65])) | (sum_one[65] & car_one_adj[65])), (((vector1[64] & sum_one[64]) | (vector1[64] & car_one_adj[64])) | (sum_one[64] & car_one_adj[64])), (((vector1[63] & sum_one[63]) | (vector1[63] & car_one_adj[63])) | (sum_one[63] & car_one_adj[63])), (((vector1[62] & sum_one[62]) | (vector1[62] & car_one_adj[62])) | (sum_one[62] & car_one_adj[62])), (((vector1[61] & sum_one[61]) | (vector1[61] & car_one_adj[61])) | (sum_one[61] & car_one_adj[61])), (((vector1[60] & sum_one[60]) | (vector1[60] & car_one_adj[60])) | (sum_one[60] & car_one_adj[60])), (((vector1[59] & sum_one[59]) | (vector1[59] & car_one_adj[59])) | (sum_one[59] & car_one_adj[59])), (((vector1[58] & sum_one[58]) | (vector1[58] & car_one_adj[58])) | (sum_one[58] & car_one_adj[58])), (((vector1[57] & sum_one[57]) | (vector1[57] & car_one_adj[57])) | (sum_one[57] & car_one_adj[57])), (((vector1[56] & sum_one[56]) | (vector1[56] & car_one_adj[56])) | (sum_one[56] & car_one_adj[56])), (((vector1[55] & sum_one[55]) | (vector1[55] & car_one_adj[55])) | (sum_one[55] & car_one_adj[55])), (((vector1[54] & sum_one[54]) | (vector1[54] & car_one_adj[54])) | (sum_one[54] & car_one_adj[54])), (((vector1[53] & sum_one[53]) | (vector1[53] & car_one_adj[53])) | (sum_one[53] & car_one_adj[53])), (((vector1[52] & sum_one[52]) | (vector1[52] & car_one_adj[52])) | (sum_one[52] & car_one_adj[52])), (((vector1[51] & sum_one[51]) | (vector1[51]
& car_one_adj[51])) | (sum_one[51] & car_one_adj[51])), (((vector1[50] & sum_one[50]) | (vector1[50] & car_one_adj[50])) | (sum_one[50] & car_one_adj[50])), (((vector1[49] & sum_one[49]) | (vector1[49] & car_one_adj[49])) | (sum_one[49] & car_one_adj[49])), (((vector1[48] & sum_one[48]) | (vector1[48] & car_one_adj[48])) | (sum_one[48] & car_one_adj[48])), (((vector1[47] & sum_one[47]) | (vector1[47] & car_one_adj[47])) | (sum_one[47] & car_one_adj[47])), (((vector1[46] & sum_one[46]) | (vector1[46] & car_one_adj[46])) | (sum_one[46] & car_one_adj[46])), (((vector1[45] & sum_one[45]) | (vector1[45] & car_one_adj[45])) | (sum_one[45] & car_one_adj[45])), (((vector1[44] & sum_one[44]) | (vector1[44] & car_one_adj[44])) | (sum_one[44] & car_one_adj[44])), (((vector1[43] & sum_one[43]) | (vector1[43] & car_one_adj[43])) | (sum_one[43] & car_one_adj[43])), (((vector1[42] & sum_one[42]) | (vector1[42] & car_one_adj[42])) | (sum_one[42] & car_one_adj[42])), (((vector1[41] & sum_one[41]) | (vector1[41] & car_one_adj[41])) | (sum_one[41] & car_one_adj[41])), (((vector1[40] & sum_one[40]) | (vector1[40] & car_one_adj[40])) | (sum_one[40] & car_one_adj[40])), (((vector1[39] & sum_one[39]) | (vector1[39] & car_one_adj[39])) | (sum_one[39] & car_one_adj[39])), (((vector1[38] & sum_one[38]) | (vector1[38] & car_one_adj[38])) | (sum_one[38] & car_one_adj[38])), (((vector1[37] & sum_one[37]) | (vector1[37] & car_one_adj[37])) | (sum_one[37] & car_one_adj[37])), (((vector1[36] & sum_one[36]) | (vector1[36] & car_one_adj[36])) | (sum_one[36] & car_one_adj[36])), (((vector1[35] & sum_one[35]) | (vector1[35] & car_one_adj[35])) | (sum_one[35] & car_one_adj[35])), (((vector1[34] & sum_one[34]) | (vector1[34] & car_one_adj[34])) | (sum_one[34] & car_one_adj[34])), (((vector1[33] & sum_one[33]) | (vector1[33] & car_one_adj[33])) | (sum_one[33] & car_one_adj[33])), (((vector1[32] & sum_one[32]) | (vector1[32] & car_one_adj[32])) | (sum_one[32] & car_one_adj[32])), (((vector1[31] & sum_one[31]) | (vector1[31] & car_one_adj[31])) | (sum_one[31]
& car_one_adj[31])), (((vector1[30] & sum_one[30]) | (vector1[30] & car_one_adj[30])) | (sum_one[30] & car_one_adj[30])), (((vector1[29] & sum_one[29]) | (vector1[29] & car_one_adj[29])) | (sum_one[29] & car_one_adj[29])), (((vector1[28] & sum_one[28]) | (vector1[28] & car_one_adj[28])) | (sum_one[28] & car_one_adj[28])), (((vector1[27] & sum_one[27]) | (vector1[27] & car_one_adj[27])) | (sum_one[27] & car_one_adj[27])), (((vector1[26] & sum_one[26]) | (vector1[26] & car_one_adj[26])) | (sum_one[26] & car_one_adj[26])), (((vector1[25] & sum_one[25]) | (vector1[25] & car_one_adj[25])) | (sum_one[25] & car_one_adj[25])), (((vector1[24] & sum_one[24]) | (vector1[24] & car_one_adj[24])) | (sum_one[24] & car_one_adj[24])), (((vector1[23] & sum_one[23]) | (vector1[23] & car_one_adj[23])) | (sum_one[23] & car_one_adj[23])), (((vector1[22] & sum_one[22]) | (vector1[22] & car_one_adj[22])) | (sum_one[22] & car_one_adj[22])), (((vector1[21] & sum_one[21]) | (vector1[21] & car_one_adj[21])) | (sum_one[21] & car_one_adj[21])), (((vector1[20] & sum_one[20]) | (vector1[20] & car_one_adj[20])) | (sum_one[20] & car_one_adj[20])), (((vector1[19] & sum_one[19]) | (vector1[19] & car_one_adj[19])) | (sum_one[19] & car_one_adj[19])), (((vector1[18] & sum_one[18]) | (vector1[18] & car_one_adj[18])) | (sum_one[18] & car_one_adj[18])), (((vector1[17] & sum_one[17]) | (vector1[17] & car_one_adj[17])) | (sum_one[17] & car_one_adj[17])), (((vector1[16] & sum_one[16]) | (vector1[16] & car_one_adj[16])) | (sum_one[16] & car_one_adj[16])), (((vector1[15] & sum_one[15]) | (vector1[15] & car_one_adj[15])) | (sum_one[15] & car_one_adj[15])), (((vector1[14] & sum_one[14]) | (vector1[14] & car_one_adj[14])) | (sum_one[14] & car_one_adj[14])), (((vector1[13] & sum_one[13]) | (vector1[13] & car_one_adj[13])) | (sum_one[13] & car_one_adj[13])), (((vector1[12] & sum_one[12]) | (vector1[12] & car_one_adj[12])) | (sum_one[12] & car_one_adj[12])), (((vector1[11] & sum_one[11]) | (vector1[11] & car_one_adj[11])) | (sum_one[11] & car_one_adj[11])), (((vector1[10]
& sum_one[10]) | (vector1[10] & car_one_adj[10])) | (sum_one[10] & car_one_adj[10])), (((vector1[9] & sum_one[9]) | (vector1[9] & car_one_adj[9])) | (sum_one[9] & car_one_adj[9])), (((vector1[8] & sum_one[8]) | (vector1[8] & car_one_adj[8])) | (sum_one[8] & car_one_adj[8])), (((vector1[7] & sum_one[7]) | (vector1[7] & car_one_adj[7])) | (sum_one[7] & car_one_adj[7])), (((vector1[6] & sum_one[6]) | (vector1[6] & car_one_adj[6])) | (sum_one[6] & car_one_adj[6])), (((vector1[5] & sum_one[5]) | (vector1[5] & car_one_adj[5])) | (sum_one[5] & car_one_adj[5])), (((vector1[4] & sum_one[4]) | (vector1[4] & car_one_adj[4])) | (sum_one[4] & car_one_adj[4])), (((vector1[3] & sum_one[3]) | (vector1[3] & car_one_adj[3])) | (sum_one[3] & car_one_adj[3])), (((vector1[2] & sum_one[2]) | (vector1[2] & car_one_adj[2])) | (sum_one[2] & car_one_adj[2])), (((vector1[1] & sum_one[1]) | (vector1[1] & car_one_adj[1])) | (sum_one[1] & car_one_adj[1])), (((vector1[0] & sum_one[0]) | (vector1[0] & car_one_adj[0])) | (sum_one[0] & car_one_adj[0]))},
car_two_adj = {car_two[90:0], 1'b1},
car_two_wo = car_two_adj_reg0,
lowest_bits_wi = lsb_prod_wo[30:0],
lowest_bits_wo = lowest_bits_wi_reg2,
lsb_prod_wi = wire_lsb_prod_result,
lsb_prod_wo = lsb_prod_wi_reg0,
mid_prod_wi = wire_mid_prod_result,
mid_prod_wo = mid_prod_wi_reg0,
msb_prod_out = wire_msb_prod_result,
msb_prod_wi = msb_prod_out,
msb_prod_wo = msb_prod_wi_reg0,
neg_lsb = {{30{1'b1}}, (~ lsb_prod_wo[61]), (~ lsb_prod_wo[60]), (~ lsb_prod_wo[59]), (~ lsb_prod_wo[58]), (~ lsb_prod_wo[57]), (~ lsb_prod_wo[56]), (~ lsb_prod_wo[55]), (~ lsb_prod_wo[54]), (~ lsb_prod_wo[53]), (~ lsb_prod_wo[52]), (~ lsb_prod_wo[51]), (~ lsb_prod_wo[50]), (~ lsb_prod_wo[49]), (~ lsb_prod_wo[48]), (~ lsb_prod_wo[47]), (~ lsb_prod_wo[46]), (~ lsb_prod_wo[45]), (~ lsb_prod_wo[44]), (~ lsb_prod_wo[43]), (~ lsb_prod_wo[42]), (~ lsb_prod_wo[41]), (~ lsb_prod_wo[40]), (~ lsb_prod_wo[39]), (~ lsb_prod_wo[38]), (~ lsb_prod_wo[37]), (~ lsb_prod_wo[36]), (~ lsb_prod_wo[35]), (~ lsb_prod_wo[34]), (~ lsb_prod_wo[33]), (~ lsb_prod_wo[32]), (~ lsb_prod_wo[31]), (~ lsb_prod_wo[30]), (~ lsb_prod_wo[29]), (~ lsb_prod_wo[28]), (~ lsb_prod_wo[27]), (~ lsb_prod_wo[26]), (~ lsb_prod_wo[25]), (~ lsb_prod_wo[24]), (~ lsb_prod_wo[23]), (~ lsb_prod_wo[22]), (~ lsb_prod_wo[21]), (~ lsb_prod_wo[20]), (~ lsb_prod_wo[19]), (~ lsb_prod_wo[18]), (~ lsb_prod_wo[17]), (~ lsb_prod_wo[16]), (~ lsb_prod_wo[15]), (~ lsb_prod_wo[14]), (~ lsb_prod_wo[13]), (~ lsb_prod_wo[12]), (~ lsb_prod_wo[11]), (~ lsb_prod_wo[10]), (~ lsb_prod_wo[9]), (~ lsb_prod_wo[8]), (~ lsb_prod_wo[7]), (~ lsb_prod_wo[6]), (~ lsb_prod_wo[5]), (~ lsb_prod_wo[4]), (~ lsb_prod_wo[3]), (~ lsb_prod_wo[2]), (~ lsb_prod_wo[1]), (~ lsb_prod_wo[0])},
neg_msb = {{31{1'b1}}, (~ msb_prod_wo[60]), (~ msb_prod_wo[59]), (~ msb_prod_wo[58]), (~ msb_prod_wo[57]), (~ msb_prod_wo[56]), (~ msb_prod_wo[55]), (~ msb_prod_wo[54]), (~ msb_prod_wo[53]), (~ msb_prod_wo[52]), (~ msb_prod_wo[51]), (~ msb_prod_wo[50]), (~ msb_prod_wo[49]), (~ msb_prod_wo[48]), (~ msb_prod_wo[47]), (~ msb_prod_wo[46]), (~ msb_prod_wo[45]), (~ msb_prod_wo[44]), (~ msb_prod_wo[43]), (~ msb_prod_wo[42]), (~ msb_prod_wo[41]), (~ msb_prod_wo[40]), (~ msb_prod_wo[39]), (~ msb_prod_wo[38]), (~ msb_prod_wo[37]), (~ msb_prod_wo[36]), (~ msb_prod_wo[35]), (~ msb_prod_wo[34]), (~ msb_prod_wo[33]), (~ msb_prod_wo[32]), (~ msb_prod_wo[31]), (~ msb_prod_wo[30]), (~ msb_prod_wo[29]), (~ msb_prod_wo[28]), (~ msb_prod_wo[27]), (~ msb_prod_wo[26]), (~ msb_prod_wo[25]), (~ msb_prod_wo[24]), (~ msb_prod_wo[23]), (~ msb_prod_wo[22]), (~ msb_prod_wo[21]), (~ msb_prod_wo[20]), (~ msb_prod_wo[19]), (~ msb_prod_wo[18]), (~ msb_prod_wo[17]), (~ msb_prod_wo[16]), (~ msb_prod_wo[15]), (~ msb_prod_wo[14]), (~ msb_prod_wo[13]), (~ msb_prod_wo[12]), (~ msb_prod_wo[11]), (~ msb_prod_wo[10]), (~ msb_prod_wo[9]), (~ msb_prod_wo[8]), (~ msb_prod_wo[7]), (~ msb_prod_wo[6]), (~ msb_prod_wo[5]), (~ msb_prod_wo[4]), (~ msb_prod_wo[3]), (~ msb_prod_wo[2]), (~ msb_prod_wo[1]), (~ msb_prod_wo[0])},
result = {wire_sum_result[90:0], lowest_bits_wo},
sum_one = {((vector2[91] ^ neg_msb[91]) ^ neg_lsb[91]), ((vector2[90] ^ neg_msb[90]) ^ neg_lsb[90]), ((vector2[89] ^ neg_msb[89]) ^ neg_lsb[89]), ((vector2[88] ^ neg_msb[88]) ^ neg_lsb[88]), ((vector2[87] ^ neg_msb[87]) ^ neg_lsb[87]), ((vector2[86] ^ neg_msb[86]) ^ neg_lsb[86]), ((vector2[85] ^ neg_msb[85]) ^ neg_lsb[85]), ((vector2[84] ^ neg_msb[84]) ^ neg_lsb[84]), ((vector2[83] ^ neg_msb[83]) ^ neg_lsb[83]), ((vector2[82] ^ neg_msb[82]) ^ neg_lsb[82]), ((vector2[81] ^ neg_msb[81]) ^ neg_lsb[81]), ((vector2[80] ^ neg_msb[80]) ^ neg_lsb[80]), ((vector2[79] ^ neg_msb[79]) ^ neg_lsb[79]), ((vector2[78] ^ neg_msb[78]) ^ neg_lsb[78]), ((vector2[77] ^ neg_msb[77]) ^ neg_lsb[77]), ((vector2[76] ^ neg_msb[76]) ^ neg_lsb[76]), ((vector2[75] ^ neg_msb[75]) ^ neg_lsb[75]), ((vector2[74] ^ neg_msb[74]) ^ neg_lsb[74]), ((vector2[73] ^ neg_msb[73]) ^ neg_lsb[73]), ((vector2[72] ^ neg_msb[72]) ^ neg_lsb[72]), ((vector2[71] ^ neg_msb[71]) ^ neg_lsb[71]), ((vector2[70] ^ neg_msb[70]) ^ neg_lsb[70]), ((vector2[69] ^ neg_msb[69]) ^ neg_lsb[69]), ((vector2[68] ^ neg_msb[68]) ^ neg_lsb[68]), ((vector2[67] ^ neg_msb[67]) ^ neg_lsb[67]), ((vector2[66] ^ neg_msb[66]) ^ neg_lsb[66]), ((vector2[65] ^ neg_msb[65]) ^ neg_lsb[65]), ((vector2[64] ^ neg_msb[64]) ^ neg_lsb[64]), ((vector2[63] ^ neg_msb[63]) ^ neg_lsb[63]), ((vector2[62] ^ neg_msb[62]) ^ neg_lsb[62]), ((vector2[61] ^ neg_msb[61]) ^ neg_lsb[61]), ((vector2[60] ^ neg_msb[60]) ^ neg_lsb[60]), ((vector2[59] ^ neg_msb[59]) ^ neg_lsb[59]), ((vector2[58] ^ neg_msb[58]) ^ neg_lsb[58]), ((vector2[57] ^ neg_msb[57]) ^ neg_lsb[57]), ((vector2[56] ^ neg_msb[56]) ^ neg_lsb[56]), ((vector2[55] ^ neg_msb[55]) ^ neg_lsb[55]), ((vector2[54] ^ neg_msb[54]) ^ neg_lsb[54]), ((vector2[53] ^ neg_msb[53]) ^ neg_lsb[53]), ((vector2[52] ^ neg_msb[52]) ^ neg_lsb[52]), ((vector2[51] ^ neg_msb[51]) ^ neg_lsb[51]), ((vector2[50] ^ neg_msb[50]) ^ neg_lsb[50]), ((vector2[49] ^ neg_msb[49]) ^ neg_lsb[49]), ((vector2[48] ^ neg_msb[48]) ^ neg_lsb[48]), ((vector2[47] ^ neg_msb[47]) ^ neg_lsb[47]), ((vector2[46]
^ neg_msb[46]) ^ neg_lsb[46]), ((vector2[45] ^ neg_msb[45]) ^ neg_lsb[45]), ((vector2[44] ^ neg_msb[44]) ^ neg_lsb[44]), ((vector2[43] ^ neg_msb[43]) ^ neg_lsb[43]), ((vector2[42] ^ neg_msb[42]) ^ neg_lsb[42]), ((vector2[41] ^ neg_msb[41]) ^ neg_lsb[41]), ((vector2[40] ^ neg_msb[40]) ^ neg_lsb[40]), ((vector2[39] ^ neg_msb[39]) ^ neg_lsb[39]), ((vector2[38] ^ neg_msb[38]) ^ neg_lsb[38]), ((vector2[37] ^ neg_msb[37]) ^ neg_lsb[37]), ((vector2[36] ^ neg_msb[36]) ^ neg_lsb[36]), ((vector2[35] ^ neg_msb[35]) ^ neg_lsb[35]), ((vector2[34] ^ neg_msb[34]) ^ neg_lsb[34]), ((vector2[33] ^ neg_msb[33]) ^ neg_lsb[33]), ((vector2[32] ^ neg_msb[32]) ^ neg_lsb[32]), ((vector2[31] ^ neg_msb[31]) ^ neg_lsb[31]), ((vector2[30] ^ neg_msb[30]) ^ neg_lsb[30]), ((vector2[29] ^ neg_msb[29]) ^ neg_lsb[29]), ((vector2[28] ^ neg_msb[28]) ^ neg_lsb[28]), ((vector2[27] ^ neg_msb[27]) ^ neg_lsb[27]), ((vector2[26] ^ neg_msb[26]) ^ neg_lsb[26]), ((vector2[25] ^ neg_msb[25]) ^ neg_lsb[25]), ((vector2[24] ^ neg_msb[24]) ^ neg_lsb[24]), ((vector2[23] ^ neg_msb[23]) ^ neg_lsb[23]), ((vector2[22] ^ neg_msb[22]) ^ neg_lsb[22]), ((vector2[21] ^ neg_msb[21]) ^ neg_lsb[21]), ((vector2[20] ^ neg_msb[20]) ^ neg_lsb[20]), ((vector2[19] ^ neg_msb[19]) ^ neg_lsb[19]), ((vector2[18] ^ neg_msb[18]) ^ neg_lsb[18]), ((vector2[17] ^ neg_msb[17]) ^ neg_lsb[17]), ((vector2[16] ^ neg_msb[16]) ^ neg_lsb[16]), ((vector2[15] ^ neg_msb[15]) ^ neg_lsb[15]), ((vector2[14] ^ neg_msb[14]) ^ neg_lsb[14]), ((vector2[13] ^ neg_msb[13]) ^ neg_lsb[13]), ((vector2[12] ^ neg_msb[12]) ^ neg_lsb[12]), ((vector2[11] ^ neg_msb[11]) ^ neg_lsb[11]), ((vector2[10] ^ neg_msb[10]) ^ neg_lsb[10]), ((vector2[9] ^ neg_msb[9]) ^ neg_lsb[9]), ((vector2[8] ^ neg_msb[8]) ^ neg_lsb[8]), ((vector2[7] ^ neg_msb[7]) ^ neg_lsb[7]), ((vector2[6] ^ neg_msb[6]) ^ neg_lsb[6]), ((vector2[5] ^ neg_msb[5]) ^ neg_lsb[5]), ((vector2[4] ^ neg_msb[4]) ^ neg_lsb[4]), ((vector2[3] ^ neg_msb[3]) ^ neg_lsb[3]), ((vector2[2] ^ neg_msb[2]) ^ neg_lsb[2]), ((vector2[1] ^ neg_msb[1]) ^ neg_lsb[1]), ((vector2[0] ^ neg_msb[0]
) ^ neg_lsb[0])},
sum_two = {((vector1[91] ^ sum_one[91]) ^ car_one_adj[91]), ((vector1[90] ^ sum_one[90]) ^ car_one_adj[90]), ((vector1[89] ^ sum_one[89]) ^ car_one_adj[89]), ((vector1[88] ^ sum_one[88]) ^ car_one_adj[88]), ((vector1[87] ^ sum_one[87]) ^ car_one_adj[87]), ((vector1[86] ^ sum_one[86]) ^ car_one_adj[86]), ((vector1[85] ^ sum_one[85]) ^ car_one_adj[85]), ((vector1[84] ^ sum_one[84]) ^ car_one_adj[84]), ((vector1[83] ^ sum_one[83]) ^ car_one_adj[83]), ((vector1[82] ^ sum_one[82]) ^ car_one_adj[82]), ((vector1[81] ^ sum_one[81]) ^ car_one_adj[81]), ((vector1[80] ^ sum_one[80]) ^ car_one_adj[80]), ((vector1[79] ^ sum_one[79]) ^ car_one_adj[79]), ((vector1[78] ^ sum_one[78]) ^ car_one_adj[78]), ((vector1[77] ^ sum_one[77]) ^ car_one_adj[77]), ((vector1[76] ^ sum_one[76]) ^ car_one_adj[76]), ((vector1[75] ^ sum_one[75]) ^ car_one_adj[75]), ((vector1[74] ^ sum_one[74]) ^ car_one_adj[74]), ((vector1[73] ^ sum_one[73]) ^ car_one_adj[73]), ((vector1[72] ^ sum_one[72]) ^ car_one_adj[72]), ((vector1[71] ^ sum_one[71]) ^ car_one_adj[71]), ((vector1[70] ^ sum_one[70]) ^ car_one_adj[70]), ((vector1[69] ^ sum_one[69]) ^ car_one_adj[69]), ((vector1[68] ^ sum_one[68]) ^ car_one_adj[68]), ((vector1[67] ^ sum_one[67]) ^ car_one_adj[67]), ((vector1[66] ^ sum_one[66]) ^ car_one_adj[66]), ((vector1[65] ^ sum_one[65]) ^ car_one_adj[65]), ((vector1[64] ^ sum_one[64]) ^ car_one_adj[64]), ((vector1[63] ^ sum_one[63]) ^ car_one_adj[63]), ((vector1[62] ^ sum_one[62]) ^ car_one_adj[62]), ((vector1[61] ^ sum_one[61]) ^ car_one_adj[61]), ((vector1[60] ^ sum_one[60]) ^ car_one_adj[60]), ((vector1[59] ^ sum_one[59]) ^ car_one_adj[59]), ((vector1[58] ^ sum_one[58]) ^ car_one_adj[58]), ((vector1[57] ^ sum_one[57]) ^ car_one_adj[57]), ((vector1[56] ^ sum_one[56]) ^ car_one_adj[56]), ((vector1[55] ^ sum_one[55]) ^ car_one_adj[55]), ((vector1[54] ^ sum_one[54]) ^ car_one_adj[54]), ((vector1[53] ^ sum_one[53]) ^ car_one_adj[53]), ((vector1[52] ^ sum_one[52]) ^ car_one_adj[52]), ((vector1[51] ^ sum_one[51]) ^ car_one_adj[51]), ((vector1[50] ^ sum_one[50]
) ^ car_one_adj[50]), ((vector1[49] ^ sum_one[49]) ^ car_one_adj[49]), ((vector1[48] ^ sum_one[48]) ^ car_one_adj[48]), ((vector1[47] ^ sum_one[47]) ^ car_one_adj[47]), ((vector1[46] ^ sum_one[46]) ^ car_one_adj[46]), ((vector1[45] ^ sum_one[45]) ^ car_one_adj[45]), ((vector1[44] ^ sum_one[44]) ^ car_one_adj[44]), ((vector1[43] ^ sum_one[43]) ^ car_one_adj[43]), ((vector1[42] ^ sum_one[42]) ^ car_one_adj[42]), ((vector1[41] ^ sum_one[41]) ^ car_one_adj[41]), ((vector1[40] ^ sum_one[40]) ^ car_one_adj[40]), ((vector1[39] ^ sum_one[39]) ^ car_one_adj[39]), ((vector1[38] ^ sum_one[38]) ^ car_one_adj[38]), ((vector1[37] ^ sum_one[37]) ^ car_one_adj[37]), ((vector1[36] ^ sum_one[36]) ^ car_one_adj[36]), ((vector1[35] ^ sum_one[35]) ^ car_one_adj[35]), ((vector1[34] ^ sum_one[34]) ^ car_one_adj[34]), ((vector1[33] ^ sum_one[33]) ^ car_one_adj[33]), ((vector1[32] ^ sum_one[32]) ^ car_one_adj[32]), ((vector1[31] ^ sum_one[31]) ^ car_one_adj[31]), ((vector1[30] ^ sum_one[30]) ^ car_one_adj[30]), ((vector1[29] ^ sum_one[29]) ^ car_one_adj[29]), ((vector1[28] ^ sum_one[28]) ^ car_one_adj[28]), ((vector1[27] ^ sum_one[27]) ^ car_one_adj[27]), ((vector1[26] ^ sum_one[26]) ^ car_one_adj[26]), ((vector1[25] ^ sum_one[25]) ^ car_one_adj[25]), ((vector1[24] ^ sum_one[24]) ^ car_one_adj[24]), ((vector1[23] ^ sum_one[23]) ^ car_one_adj[23]), ((vector1[22] ^ sum_one[22]) ^ car_one_adj[22]), ((vector1[21] ^ sum_one[21]) ^ car_one_adj[21]), ((vector1[20] ^ sum_one[20]) ^ car_one_adj[20]), ((vector1[19] ^ sum_one[19]) ^ car_one_adj[19]), ((vector1[18] ^ sum_one[18]) ^ car_one_adj[18]), ((vector1[17] ^ sum_one[17]) ^ car_one_adj[17]), ((vector1[16] ^ sum_one[16]) ^ car_one_adj[16]), ((vector1[15] ^ sum_one[15]) ^ car_one_adj[15]), ((vector1[14] ^ sum_one[14]) ^ car_one_adj[14]), ((vector1[13] ^ sum_one[13]) ^ car_one_adj[13]), ((vector1[12] ^ sum_one[12]) ^ car_one_adj[12]), ((vector1[11] ^ sum_one[11]) ^ car_one_adj[11]), ((vector1[10] ^ sum_one[10]) ^ car_one_adj[10]), ((vector1[9] ^ sum_one[9]) ^ car_one_adj[9]), ((vector1[8] ^ sum_one[8]
) ^ car_one_adj[8]), ((vector1[7] ^ sum_one[7]) ^ car_one_adj[7]), ((vector1[6] ^ sum_one[6]) ^ car_one_adj[6]), ((vector1[5] ^ sum_one[5]) ^ car_one_adj[5]), ((vector1[4] ^ sum_one[4]) ^ car_one_adj[4]), ((vector1[3] ^ sum_one[3]) ^ car_one_adj[3]), ((vector1[2] ^ sum_one[2]) ^ car_one_adj[2]), ((vector1[1] ^ sum_one[1]) ^ car_one_adj[1]), ((vector1[0] ^ sum_one[0]) ^ car_one_adj[0])},
sum_two_wo = sum_two_reg0,
vector1 = {msb_prod_wo, lsb_prod_wo[61:31]},
vector2 = {{28{1'b0}}, mid_prod_wo},
wire_a = dataa,
wire_b = datab;
endmodule //acl_fp_exp_double_altmult_opt_f9e
//altmult_opt CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" LPM_PIPELINE=5 LPM_WIDTHA=61 LPM_WIDTHB=59 LPM_WIDTHP=120 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altmult_opt 2010:08:18:21:07:09:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//altmult_opt_csa CARRY_SELECT="NO" CBX_AUTO_BLACKBOX="ALL" LPM_DIRECTION="ADD" LPM_PIPELINE=2 LPM_REPRESENTATION="UNSIGNED" LPM_WIDTH=90 aclr clken clock dataa datab result
//VERSION_BEGIN 10.0SP1 cbx_altmult_opt 2010:08:18:21:07:09:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_mult 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_padd 2010:08:18:21:07:12:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
//synthesis_resources = lpm_add_sub 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_exp_double_altmult_opt_csa_lsf
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [89:0] dataa;
input [89:0] datab;
output [89:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
tri0 clock;
tri0 [89:0] dataa;
tri0 [89:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [89:0] wire_add_sub3_result;
wire [89:0] result_w;
lpm_add_sub add_sub3
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.cout(),
.dataa(dataa),
.datab(datab),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "ADD",
add_sub3.lpm_pipeline = 2,
add_sub3.lpm_representation = "UNSIGNED",
add_sub3.lpm_width = 90,
add_sub3.lpm_type = "lpm_add_sub";
assign
result = result_w,
result_w = wire_add_sub3_result;
endmodule //acl_fp_exp_double_altmult_opt_csa_lsf
//synthesis_resources = lpm_add_sub 3 lpm_mult 3 reg 458
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_exp_double_altmult_opt_k9e
(
aclr,
clken,
clock,
dataa,
datab,
result) ;
input aclr;
input clken;
input clock;
input [60:0] dataa;
input [58:0] datab;
output [119:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clken;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [89:0] wire_sum_result;
reg [89:0] car_two_adj_reg0;
reg [30:0] lowest_bits_wi_reg0;
reg [30:0] lowest_bits_wi_reg1;
reg [30:0] lowest_bits_wi_reg2;
reg [61:0] lsb_prod_wi_reg0;
reg [63:0] mid_prod_wi_reg0;
reg [58:0] msb_prod_wi_reg0;
reg [89:0] sum_two_reg0;
wire wire_compress_a_cout;
wire [30:0] wire_compress_a_result;
wire wire_compress_b_cout;
wire [30:0] wire_compress_b_result;
wire [61:0] wire_lsb_prod_result;
wire [63:0] wire_mid_prod_result;
wire [58:0] wire_msb_prod_result;
wire [89:0] car_one;
wire [89:0] car_one_adj;
wire [89:0] car_two;
wire [89:0] car_two_adj;
wire [89:0] car_two_wo;
wire [30:0] lowest_bits_wi;
wire [30:0] lowest_bits_wo;
wire [61:0] lsb_prod_wi;
wire [61:0] lsb_prod_wo;
wire [63:0] mid_prod_wi;
wire [63:0] mid_prod_wo;
wire [58:0] msb_prod_out;
wire [58:0] msb_prod_wi;
wire [58:0] msb_prod_wo;
wire [89:0] neg_lsb;
wire [89:0] neg_msb;
wire [89:0] sum_one;
wire [89:0] sum_two;
wire [89:0] sum_two_wo;
wire [89:0] vector1;
wire [89:0] vector2;
wire [60:0] wire_a;
wire [58:0] wire_b;
acl_fp_exp_double_altmult_opt_csa_lsf sum
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa(car_two_wo),
.datab(sum_two_wo),
.result(wire_sum_result));
// synopsys translate_off
initial
car_two_adj_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) car_two_adj_reg0 <= 90'b0;
else if (clken == 1'b1) car_two_adj_reg0 <= car_two_adj;
// synopsys translate_off
initial
lowest_bits_wi_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lowest_bits_wi_reg0 <= 31'b0;
else if (clken == 1'b1) lowest_bits_wi_reg0 <= lowest_bits_wi;
// synopsys translate_off
initial
lowest_bits_wi_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lowest_bits_wi_reg1 <= 31'b0;
else if (clken == 1'b1) lowest_bits_wi_reg1 <= lowest_bits_wi_reg0;
// synopsys translate_off
initial
lowest_bits_wi_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lowest_bits_wi_reg2 <= 31'b0;
else if (clken == 1'b1) lowest_bits_wi_reg2 <= lowest_bits_wi_reg1;
// synopsys translate_off
initial
lsb_prod_wi_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) lsb_prod_wi_reg0 <= 62'b0;
else if (clken == 1'b1) lsb_prod_wi_reg0 <= lsb_prod_wi;
// synopsys translate_off
initial
mid_prod_wi_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mid_prod_wi_reg0 <= 64'b0;
else if (clken == 1'b1) mid_prod_wi_reg0 <= mid_prod_wi;
// synopsys translate_off
initial
msb_prod_wi_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) msb_prod_wi_reg0 <= 59'b0;
else if (clken == 1'b1) msb_prod_wi_reg0 <= msb_prod_wi;
// synopsys translate_off
initial
sum_two_reg0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sum_two_reg0 <= 90'b0;
else if (clken == 1'b1) sum_two_reg0 <= sum_two;
lpm_add_sub compress_a
(
.cout(wire_compress_a_cout),
.dataa({1'b0, wire_a[60:31]}),
.datab(wire_a[30:0]),
.overflow(),
.result(wire_compress_a_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
compress_a.lpm_direction = "ADD",
compress_a.lpm_representation = "UNSIGNED",
compress_a.lpm_width = 31,
compress_a.lpm_type = "lpm_add_sub";
lpm_add_sub compress_b
(
.cout(wire_compress_b_cout),
.dataa({{3{1'b0}}, wire_b[58:31]}),
.datab(wire_b[30:0]),
.overflow(),
.result(wire_compress_b_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
compress_b.lpm_direction = "ADD",
compress_b.lpm_representation = "UNSIGNED",
compress_b.lpm_width = 31,
compress_b.lpm_type = "lpm_add_sub";
lpm_mult lsb_prod
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa(wire_a[30:0]),
.datab(wire_b[30:0]),
.result(wire_lsb_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
lsb_prod.lpm_pipeline = 1,
lsb_prod.lpm_representation = "UNSIGNED",
lsb_prod.lpm_widtha = 31,
lsb_prod.lpm_widthb = 31,
lsb_prod.lpm_widthp = 62,
lsb_prod.lpm_type = "lpm_mult",
lsb_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult mid_prod
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa({wire_compress_a_cout, wire_compress_a_result}),
.datab({wire_compress_b_cout, wire_compress_b_result}),
.result(wire_mid_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
mid_prod.lpm_pipeline = 1,
mid_prod.lpm_representation = "UNSIGNED",
mid_prod.lpm_widtha = 32,
mid_prod.lpm_widthb = 32,
mid_prod.lpm_widthp = 64,
mid_prod.lpm_type = "lpm_mult",
mid_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult msb_prod
(
.aclr(aclr),
.clken(clken),
.clock(clock),
.dataa({1'b0, wire_a[60:31]}),
.datab(wire_b[58:31]),
.result(wire_msb_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
msb_prod.lpm_pipeline = 1,
msb_prod.lpm_representation = "UNSIGNED",
msb_prod.lpm_widtha = 31,
msb_prod.lpm_widthb = 28,
msb_prod.lpm_widthp = 59,
msb_prod.lpm_type = "lpm_mult",
msb_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
assign
car_one = {(((vector2[89] & neg_msb[89]) | (vector2[89] & neg_lsb[89])) | (neg_msb[89] & neg_lsb[89])), (((vector2[88] & neg_msb[88]) | (vector2[88] & neg_lsb[88])) | (neg_msb[88] & neg_lsb[88])), (((vector2[87] & neg_msb[87]) | (vector2[87] & neg_lsb[87])) | (neg_msb[87] & neg_lsb[87])), (((vector2[86] & neg_msb[86]) | (vector2[86] & neg_lsb[86])) | (neg_msb[86] & neg_lsb[86])), (((vector2[85] & neg_msb[85]) | (vector2[85] & neg_lsb[85])) | (neg_msb[85] & neg_lsb[85])), (((vector2[84] & neg_msb[84]) | (vector2[84] & neg_lsb[84])) | (neg_msb[84] & neg_lsb[84])), (((vector2[83] & neg_msb[83]) | (vector2[83] & neg_lsb[83])) | (neg_msb[83] & neg_lsb[83])), (((vector2[82] & neg_msb[82]) | (vector2[82] & neg_lsb[82])) | (neg_msb[82] & neg_lsb[82])), (((vector2[81] & neg_msb[81]) | (vector2[81] & neg_lsb[81])) | (neg_msb[81] & neg_lsb[81])), (((vector2[80] & neg_msb[80]) | (vector2[80] & neg_lsb[80])) | (neg_msb[80] & neg_lsb[80])), (((vector2[79] & neg_msb[79]) | (vector2[79] & neg_lsb[79])) | (neg_msb[79] & neg_lsb[79])), (((vector2[78] & neg_msb[78]) | (vector2[78] & neg_lsb[78])) | (neg_msb[78] & neg_lsb[78])), (((vector2[77] & neg_msb[77]) | (vector2[77] & neg_lsb[77])) | (neg_msb[77] & neg_lsb[77])), (((vector2[76] & neg_msb[76]) | (vector2[76] & neg_lsb[76])) | (neg_msb[76] & neg_lsb[76])), (((vector2[75] & neg_msb[75]) | (vector2[75] & neg_lsb[75])) | (neg_msb[75] & neg_lsb[75])), (((vector2[74] & neg_msb[74]) | (vector2[74] & neg_lsb[74])) | (neg_msb[74] & neg_lsb[74])), (((vector2[73] & neg_msb[73]) | (vector2[73] & neg_lsb[73])) | (neg_msb[73] & neg_lsb[73])), (((vector2[72] & neg_msb[72]) | (vector2[72] & neg_lsb[72])) | (neg_msb[72] & neg_lsb[72])), (((vector2[71] & neg_msb[71]) | (vector2[71] & neg_lsb[71])) | (neg_msb[71] & neg_lsb[71])), (((vector2[70] & neg_msb[70]) | (vector2[70] & neg_lsb[70])) | (neg_msb[70] & neg_lsb[70])), (((vector2[69] & neg_msb[69]) | (vector2[69] & neg_lsb[69])) | (neg_msb[69] & neg_lsb[69])), (((vector2[68] & neg_msb[68]) | (vector2[68] & neg_lsb[68])) | (neg_msb[68] & neg_lsb[68]
)), (((vector2[67] & neg_msb[67]) | (vector2[67] & neg_lsb[67])) | (neg_msb[67] & neg_lsb[67])), (((vector2[66] & neg_msb[66]) | (vector2[66] & neg_lsb[66])) | (neg_msb[66] & neg_lsb[66])), (((vector2[65] & neg_msb[65]) | (vector2[65] & neg_lsb[65])) | (neg_msb[65] & neg_lsb[65])), (((vector2[64] & neg_msb[64]) | (vector2[64] & neg_lsb[64])) | (neg_msb[64] & neg_lsb[64])), (((vector2[63] & neg_msb[63]) | (vector2[63] & neg_lsb[63])) | (neg_msb[63] & neg_lsb[63])), (((vector2[62] & neg_msb[62]) | (vector2[62] & neg_lsb[62])) | (neg_msb[62] & neg_lsb[62])), (((vector2[61] & neg_msb[61]) | (vector2[61] & neg_lsb[61])) | (neg_msb[61] & neg_lsb[61])), (((vector2[60] & neg_msb[60]) | (vector2[60] & neg_lsb[60])) | (neg_msb[60] & neg_lsb[60])), (((vector2[59] & neg_msb[59]) | (vector2[59] & neg_lsb[59])) | (neg_msb[59] & neg_lsb[59])), (((vector2[58] & neg_msb[58]) | (vector2[58] & neg_lsb[58])) | (neg_msb[58] & neg_lsb[58])), (((vector2[57] & neg_msb[57]) | (vector2[57] & neg_lsb[57])) | (neg_msb[57] & neg_lsb[57])), (((vector2[56] & neg_msb[56]) | (vector2[56] & neg_lsb[56])) | (neg_msb[56] & neg_lsb[56])), (((vector2[55] & neg_msb[55]) | (vector2[55] & neg_lsb[55])) | (neg_msb[55] & neg_lsb[55])), (((vector2[54] & neg_msb[54]) | (vector2[54] & neg_lsb[54])) | (neg_msb[54] & neg_lsb[54])), (((vector2[53] & neg_msb[53]) | (vector2[53] & neg_lsb[53])) | (neg_msb[53] & neg_lsb[53])), (((vector2[52] & neg_msb[52]) | (vector2[52] & neg_lsb[52])) | (neg_msb[52] & neg_lsb[52])), (((vector2[51] & neg_msb[51]) | (vector2[51] & neg_lsb[51])) | (neg_msb[51] & neg_lsb[51])), (((vector2[50] & neg_msb[50]) | (vector2[50] & neg_lsb[50])) | (neg_msb[50] & neg_lsb[50])), (((vector2[49] & neg_msb[49]) | (vector2[49] & neg_lsb[49])) | (neg_msb[49] & neg_lsb[49])), (((vector2[48] & neg_msb[48]) | (vector2[48] & neg_lsb[48])) | (neg_msb[48] & neg_lsb[48])), (((vector2[47] & neg_msb[47]) | (vector2[47] & neg_lsb[47])) | (neg_msb[47] & neg_lsb[47])), (((vector2[46] & neg_msb[46]) | (vector2[46] & neg_lsb[46])) | (neg_msb[46] & neg_lsb[46]))
, (((vector2[45] & neg_msb[45]) | (vector2[45] & neg_lsb[45])) | (neg_msb[45] & neg_lsb[45])), (((vector2[44] & neg_msb[44]) | (vector2[44] & neg_lsb[44])) | (neg_msb[44] & neg_lsb[44])), (((vector2[43] & neg_msb[43]) | (vector2[43] & neg_lsb[43])) | (neg_msb[43] & neg_lsb[43])), (((vector2[42] & neg_msb[42]) | (vector2[42] & neg_lsb[42])) | (neg_msb[42] & neg_lsb[42])), (((vector2[41] & neg_msb[41]) | (vector2[41] & neg_lsb[41])) | (neg_msb[41] & neg_lsb[41])), (((vector2[40] & neg_msb[40]) | (vector2[40] & neg_lsb[40])) | (neg_msb[40] & neg_lsb[40])), (((vector2[39] & neg_msb[39]) | (vector2[39] & neg_lsb[39])) | (neg_msb[39] & neg_lsb[39])), (((vector2[38] & neg_msb[38]) | (vector2[38] & neg_lsb[38])) | (neg_msb[38] & neg_lsb[38])), (((vector2[37] & neg_msb[37]) | (vector2[37] & neg_lsb[37])) | (neg_msb[37] & neg_lsb[37])), (((vector2[36] & neg_msb[36]) | (vector2[36] & neg_lsb[36])) | (neg_msb[36] & neg_lsb[36])), (((vector2[35] & neg_msb[35]) | (vector2[35] & neg_lsb[35])) | (neg_msb[35] & neg_lsb[35])), (((vector2[34] & neg_msb[34]) | (vector2[34] & neg_lsb[34])) | (neg_msb[34] & neg_lsb[34])), (((vector2[33] & neg_msb[33]) | (vector2[33] & neg_lsb[33])) | (neg_msb[33] & neg_lsb[33])), (((vector2[32] & neg_msb[32]) | (vector2[32] & neg_lsb[32])) | (neg_msb[32] & neg_lsb[32])), (((vector2[31] & neg_msb[31]) | (vector2[31] & neg_lsb[31])) | (neg_msb[31] & neg_lsb[31])), (((vector2[30] & neg_msb[30]) | (vector2[30] & neg_lsb[30])) | (neg_msb[30] & neg_lsb[30])), (((vector2[29] & neg_msb[29]) | (vector2[29] & neg_lsb[29])) | (neg_msb[29] & neg_lsb[29])), (((vector2[28] & neg_msb[28]) | (vector2[28] & neg_lsb[28])) | (neg_msb[28] & neg_lsb[28])), (((vector2[27] & neg_msb[27]) | (vector2[27] & neg_lsb[27])) | (neg_msb[27] & neg_lsb[27])), (((vector2[26] & neg_msb[26]) | (vector2[26] & neg_lsb[26])) | (neg_msb[26] & neg_lsb[26])), (((vector2[25] & neg_msb[25]) | (vector2[25] & neg_lsb[25])) | (neg_msb[25] & neg_lsb[25])), (((vector2[24] & neg_msb[24]) | (vector2[24] & neg_lsb[24])) | (neg_msb[24] & neg_lsb[24])),
(((vector2[23] & neg_msb[23]) | (vector2[23] & neg_lsb[23])) | (neg_msb[23] & neg_lsb[23])), (((vector2[22] & neg_msb[22]) | (vector2[22] & neg_lsb[22])) | (neg_msb[22] & neg_lsb[22])), (((vector2[21] & neg_msb[21]) | (vector2[21] & neg_lsb[21])) | (neg_msb[21] & neg_lsb[21])), (((vector2[20] & neg_msb[20]) | (vector2[20] & neg_lsb[20])) | (neg_msb[20] & neg_lsb[20])), (((vector2[19] & neg_msb[19]) | (vector2[19] & neg_lsb[19])) | (neg_msb[19] & neg_lsb[19])), (((vector2[18] & neg_msb[18]) | (vector2[18] & neg_lsb[18])) | (neg_msb[18] & neg_lsb[18])), (((vector2[17] & neg_msb[17]) | (vector2[17] & neg_lsb[17])) | (neg_msb[17] & neg_lsb[17])), (((vector2[16] & neg_msb[16]) | (vector2[16] & neg_lsb[16])) | (neg_msb[16] & neg_lsb[16])), (((vector2[15] & neg_msb[15]) | (vector2[15] & neg_lsb[15])) | (neg_msb[15] & neg_lsb[15])), (((vector2[14] & neg_msb[14]) | (vector2[14] & neg_lsb[14])) | (neg_msb[14] & neg_lsb[14])), (((vector2[13] & neg_msb[13]) | (vector2[13] & neg_lsb[13])) | (neg_msb[13] & neg_lsb[13])), (((vector2[12] & neg_msb[12]) | (vector2[12] & neg_lsb[12])) | (neg_msb[12] & neg_lsb[12])), (((vector2[11] & neg_msb[11]) | (vector2[11] & neg_lsb[11])) | (neg_msb[11] & neg_lsb[11])), (((vector2[10] & neg_msb[10]) | (vector2[10] & neg_lsb[10])) | (neg_msb[10] & neg_lsb[10])), (((vector2[9] & neg_msb[9]) | (vector2[9] & neg_lsb[9])) | (neg_msb[9] & neg_lsb[9])), (((vector2[8] & neg_msb[8]) | (vector2[8] & neg_lsb[8])) | (neg_msb[8] & neg_lsb[8])), (((vector2[7] & neg_msb[7]) | (vector2[7] & neg_lsb[7])) | (neg_msb[7] & neg_lsb[7])), (((vector2[6] & neg_msb[6]) | (vector2[6] & neg_lsb[6])) | (neg_msb[6] & neg_lsb[6])), (((vector2[5] & neg_msb[5]) | (vector2[5] & neg_lsb[5])) | (neg_msb[5] & neg_lsb[5])), (((vector2[4] & neg_msb[4]) | (vector2[4] & neg_lsb[4])) | (neg_msb[4] & neg_lsb[4])), (((vector2[3] & neg_msb[3]) | (vector2[3] & neg_lsb[3])) | (neg_msb[3] & neg_lsb[3])), (((vector2[2] & neg_msb[2]) | (vector2[2] & neg_lsb[2])) | (neg_msb[2] & neg_lsb[2])), (((vector2[1] & neg_msb[1]) | (vector2[1] & neg_lsb[1]
)) | (neg_msb[1] & neg_lsb[1])), (((vector2[0] & neg_msb[0]) | (vector2[0] & neg_lsb[0])) | (neg_msb[0] & neg_lsb[0]))},
car_one_adj = {car_one[88:0], 1'b1},
car_two = {(((vector1[89] & sum_one[89]) | (vector1[89] & car_one_adj[89])) | (sum_one[89] & car_one_adj[89])), (((vector1[88] & sum_one[88]) | (vector1[88] & car_one_adj[88])) | (sum_one[88] & car_one_adj[88])), (((vector1[87] & sum_one[87]) | (vector1[87] & car_one_adj[87])) | (sum_one[87] & car_one_adj[87])), (((vector1[86] & sum_one[86]) | (vector1[86] & car_one_adj[86])) | (sum_one[86] & car_one_adj[86])), (((vector1[85] & sum_one[85]) | (vector1[85] & car_one_adj[85])) | (sum_one[85] & car_one_adj[85])), (((vector1[84] & sum_one[84]) | (vector1[84] & car_one_adj[84])) | (sum_one[84] & car_one_adj[84])), (((vector1[83] & sum_one[83]) | (vector1[83] & car_one_adj[83])) | (sum_one[83] & car_one_adj[83])), (((vector1[82] & sum_one[82]) | (vector1[82] & car_one_adj[82])) | (sum_one[82] & car_one_adj[82])), (((vector1[81] & sum_one[81]) | (vector1[81] & car_one_adj[81])) | (sum_one[81] & car_one_adj[81])), (((vector1[80] & sum_one[80]) | (vector1[80] & car_one_adj[80])) | (sum_one[80] & car_one_adj[80])), (((vector1[79] & sum_one[79]) | (vector1[79] & car_one_adj[79])) | (sum_one[79] & car_one_adj[79])), (((vector1[78] & sum_one[78]) | (vector1[78] & car_one_adj[78])) | (sum_one[78] & car_one_adj[78])), (((vector1[77] & sum_one[77]) | (vector1[77] & car_one_adj[77])) | (sum_one[77] & car_one_adj[77])), (((vector1[76] & sum_one[76]) | (vector1[76] & car_one_adj[76])) | (sum_one[76] & car_one_adj[76])), (((vector1[75] & sum_one[75]) | (vector1[75] & car_one_adj[75])) | (sum_one[75] & car_one_adj[75])), (((vector1[74] & sum_one[74]) | (vector1[74] & car_one_adj[74])) | (sum_one[74] & car_one_adj[74])), (((vector1[73] & sum_one[73]) | (vector1[73] & car_one_adj[73])) | (sum_one[73] & car_one_adj[73])), (((vector1[72] & sum_one[72]) | (vector1[72] & car_one_adj[72])) | (sum_one[72] & car_one_adj[72])), (((vector1[71] & sum_one[71]) | (vector1[71] & car_one_adj[71])) | (sum_one[71] & car_one_adj[71])), (((vector1[70] & sum_one[70]) | (vector1[70] & car_one_adj[70])) | (sum_one[70] & car_one_adj[70])), (((vector1[69]
& sum_one[69]) | (vector1[69] & car_one_adj[69])) | (sum_one[69] & car_one_adj[69])), (((vector1[68] & sum_one[68]) | (vector1[68] & car_one_adj[68])) | (sum_one[68] & car_one_adj[68])), (((vector1[67] & sum_one[67]) | (vector1[67] & car_one_adj[67])) | (sum_one[67] & car_one_adj[67])), (((vector1[66] & sum_one[66]) | (vector1[66] & car_one_adj[66])) | (sum_one[66] & car_one_adj[66])), (((vector1[65] & sum_one[65]) | (vector1[65] & car_one_adj[65])) | (sum_one[65] & car_one_adj[65])), (((vector1[64] & sum_one[64]) | (vector1[64] & car_one_adj[64])) | (sum_one[64] & car_one_adj[64])), (((vector1[63] & sum_one[63]) | (vector1[63] & car_one_adj[63])) | (sum_one[63] & car_one_adj[63])), (((vector1[62] & sum_one[62]) | (vector1[62] & car_one_adj[62])) | (sum_one[62] & car_one_adj[62])), (((vector1[61] & sum_one[61]) | (vector1[61] & car_one_adj[61])) | (sum_one[61] & car_one_adj[61])), (((vector1[60] & sum_one[60]) | (vector1[60] & car_one_adj[60])) | (sum_one[60] & car_one_adj[60])), (((vector1[59] & sum_one[59]) | (vector1[59] & car_one_adj[59])) | (sum_one[59] & car_one_adj[59])), (((vector1[58] & sum_one[58]) | (vector1[58] & car_one_adj[58])) | (sum_one[58] & car_one_adj[58])), (((vector1[57] & sum_one[57]) | (vector1[57] & car_one_adj[57])) | (sum_one[57] & car_one_adj[57])), (((vector1[56] & sum_one[56]) | (vector1[56] & car_one_adj[56])) | (sum_one[56] & car_one_adj[56])), (((vector1[55] & sum_one[55]) | (vector1[55] & car_one_adj[55])) | (sum_one[55] & car_one_adj[55])), (((vector1[54] & sum_one[54]) | (vector1[54] & car_one_adj[54])) | (sum_one[54] & car_one_adj[54])), (((vector1[53] & sum_one[53]) | (vector1[53] & car_one_adj[53])) | (sum_one[53] & car_one_adj[53])), (((vector1[52] & sum_one[52]) | (vector1[52] & car_one_adj[52])) | (sum_one[52] & car_one_adj[52])), (((vector1[51] & sum_one[51]) | (vector1[51] & car_one_adj[51])) | (sum_one[51] & car_one_adj[51])), (((vector1[50] & sum_one[50]) | (vector1[50] & car_one_adj[50])) | (sum_one[50] & car_one_adj[50])), (((vector1[49] & sum_one[49]) | (vector1[49]
& car_one_adj[49])) | (sum_one[49] & car_one_adj[49])), (((vector1[48] & sum_one[48]) | (vector1[48] & car_one_adj[48])) | (sum_one[48] & car_one_adj[48])), (((vector1[47] & sum_one[47]) | (vector1[47] & car_one_adj[47])) | (sum_one[47] & car_one_adj[47])), (((vector1[46] & sum_one[46]) | (vector1[46] & car_one_adj[46])) | (sum_one[46] & car_one_adj[46])), (((vector1[45] & sum_one[45]) | (vector1[45] & car_one_adj[45])) | (sum_one[45] & car_one_adj[45])), (((vector1[44] & sum_one[44]) | (vector1[44] & car_one_adj[44])) | (sum_one[44] & car_one_adj[44])), (((vector1[43] & sum_one[43]) | (vector1[43] & car_one_adj[43])) | (sum_one[43] & car_one_adj[43])), (((vector1[42] & sum_one[42]) | (vector1[42] & car_one_adj[42])) | (sum_one[42] & car_one_adj[42])), (((vector1[41] & sum_one[41]) | (vector1[41] & car_one_adj[41])) | (sum_one[41] & car_one_adj[41])), (((vector1[40] & sum_one[40]) | (vector1[40] & car_one_adj[40])) | (sum_one[40] & car_one_adj[40])), (((vector1[39] & sum_one[39]) | (vector1[39] & car_one_adj[39])) | (sum_one[39] & car_one_adj[39])), (((vector1[38] & sum_one[38]) | (vector1[38] & car_one_adj[38])) | (sum_one[38] & car_one_adj[38])), (((vector1[37] & sum_one[37]) | (vector1[37] & car_one_adj[37])) | (sum_one[37] & car_one_adj[37])), (((vector1[36] & sum_one[36]) | (vector1[36] & car_one_adj[36])) | (sum_one[36] & car_one_adj[36])), (((vector1[35] & sum_one[35]) | (vector1[35] & car_one_adj[35])) | (sum_one[35] & car_one_adj[35])), (((vector1[34] & sum_one[34]) | (vector1[34] & car_one_adj[34])) | (sum_one[34] & car_one_adj[34])), (((vector1[33] & sum_one[33]) | (vector1[33] & car_one_adj[33])) | (sum_one[33] & car_one_adj[33])), (((vector1[32] & sum_one[32]) | (vector1[32] & car_one_adj[32])) | (sum_one[32] & car_one_adj[32])), (((vector1[31] & sum_one[31]) | (vector1[31] & car_one_adj[31])) | (sum_one[31] & car_one_adj[31])), (((vector1[30] & sum_one[30]) | (vector1[30] & car_one_adj[30])) | (sum_one[30] & car_one_adj[30])), (((vector1[29] & sum_one[29]) | (vector1[29] & car_one_adj[29])) | (sum_one[29]
& car_one_adj[29])), (((vector1[28] & sum_one[28]) | (vector1[28] & car_one_adj[28])) | (sum_one[28] & car_one_adj[28])), (((vector1[27] & sum_one[27]) | (vector1[27] & car_one_adj[27])) | (sum_one[27] & car_one_adj[27])), (((vector1[26] & sum_one[26]) | (vector1[26] & car_one_adj[26])) | (sum_one[26] & car_one_adj[26])), (((vector1[25] & sum_one[25]) | (vector1[25] & car_one_adj[25])) | (sum_one[25] & car_one_adj[25])), (((vector1[24] & sum_one[24]) | (vector1[24] & car_one_adj[24])) | (sum_one[24] & car_one_adj[24])), (((vector1[23] & sum_one[23]) | (vector1[23] & car_one_adj[23])) | (sum_one[23] & car_one_adj[23])), (((vector1[22] & sum_one[22]) | (vector1[22] & car_one_adj[22])) | (sum_one[22] & car_one_adj[22])), (((vector1[21] & sum_one[21]) | (vector1[21] & car_one_adj[21])) | (sum_one[21] & car_one_adj[21])), (((vector1[20] & sum_one[20]) | (vector1[20] & car_one_adj[20])) | (sum_one[20] & car_one_adj[20])), (((vector1[19] & sum_one[19]) | (vector1[19] & car_one_adj[19])) | (sum_one[19] & car_one_adj[19])), (((vector1[18] & sum_one[18]) | (vector1[18] & car_one_adj[18])) | (sum_one[18] & car_one_adj[18])), (((vector1[17] & sum_one[17]) | (vector1[17] & car_one_adj[17])) | (sum_one[17] & car_one_adj[17])), (((vector1[16] & sum_one[16]) | (vector1[16] & car_one_adj[16])) | (sum_one[16] & car_one_adj[16])), (((vector1[15] & sum_one[15]) | (vector1[15] & car_one_adj[15])) | (sum_one[15] & car_one_adj[15])), (((vector1[14] & sum_one[14]) | (vector1[14] & car_one_adj[14])) | (sum_one[14] & car_one_adj[14])), (((vector1[13] & sum_one[13]) | (vector1[13] & car_one_adj[13])) | (sum_one[13] & car_one_adj[13])), (((vector1[12] & sum_one[12]) | (vector1[12] & car_one_adj[12])) | (sum_one[12] & car_one_adj[12])), (((vector1[11] & sum_one[11]) | (vector1[11] & car_one_adj[11])) | (sum_one[11] & car_one_adj[11])), (((vector1[10] & sum_one[10]) | (vector1[10] & car_one_adj[10])) | (sum_one[10] & car_one_adj[10])), (((vector1[9] & sum_one[9]) | (vector1[9] & car_one_adj[9])) | (sum_one[9] & car_one_adj[9])), (((vector1[8]
& sum_one[8]) | (vector1[8] & car_one_adj[8])) | (sum_one[8] & car_one_adj[8])), (((vector1[7] & sum_one[7]) | (vector1[7] & car_one_adj[7])) | (sum_one[7] & car_one_adj[7])), (((vector1[6] & sum_one[6]) | (vector1[6] & car_one_adj[6])) | (sum_one[6] & car_one_adj[6])), (((vector1[5] & sum_one[5]) | (vector1[5] & car_one_adj[5])) | (sum_one[5] & car_one_adj[5])), (((vector1[4] & sum_one[4]) | (vector1[4] & car_one_adj[4])) | (sum_one[4] & car_one_adj[4])), (((vector1[3] & sum_one[3]) | (vector1[3] & car_one_adj[3])) | (sum_one[3] & car_one_adj[3])), (((vector1[2] & sum_one[2]) | (vector1[2] & car_one_adj[2])) | (sum_one[2] & car_one_adj[2])), (((vector1[1] & sum_one[1]) | (vector1[1] & car_one_adj[1])) | (sum_one[1] & car_one_adj[1])), (((vector1[0] & sum_one[0]) | (vector1[0] & car_one_adj[0])) | (sum_one[0] & car_one_adj[0]))},
car_two_adj = {car_two[88:0], 1'b1},
car_two_wo = car_two_adj_reg0,
lowest_bits_wi = lsb_prod_wo[30:0],
lowest_bits_wo = lowest_bits_wi_reg2,
lsb_prod_wi = wire_lsb_prod_result,
lsb_prod_wo = lsb_prod_wi_reg0,
mid_prod_wi = wire_mid_prod_result,
mid_prod_wo = mid_prod_wi_reg0,
msb_prod_out = wire_msb_prod_result,
msb_prod_wi = msb_prod_out,
msb_prod_wo = msb_prod_wi_reg0,
neg_lsb = {{28{1'b1}}, (~ lsb_prod_wo[61]), (~ lsb_prod_wo[60]), (~ lsb_prod_wo[59]), (~ lsb_prod_wo[58]), (~ lsb_prod_wo[57]), (~ lsb_prod_wo[56]), (~ lsb_prod_wo[55]), (~ lsb_prod_wo[54]), (~ lsb_prod_wo[53]), (~ lsb_prod_wo[52]), (~ lsb_prod_wo[51]), (~ lsb_prod_wo[50]), (~ lsb_prod_wo[49]), (~ lsb_prod_wo[48]), (~ lsb_prod_wo[47]), (~ lsb_prod_wo[46]), (~ lsb_prod_wo[45]), (~ lsb_prod_wo[44]), (~ lsb_prod_wo[43]), (~ lsb_prod_wo[42]), (~ lsb_prod_wo[41]), (~ lsb_prod_wo[40]), (~ lsb_prod_wo[39]), (~ lsb_prod_wo[38]), (~ lsb_prod_wo[37]), (~ lsb_prod_wo[36]), (~ lsb_prod_wo[35]), (~ lsb_prod_wo[34]), (~ lsb_prod_wo[33]), (~ lsb_prod_wo[32]), (~ lsb_prod_wo[31]), (~ lsb_prod_wo[30]), (~ lsb_prod_wo[29]), (~ lsb_prod_wo[28]), (~ lsb_prod_wo[27]), (~ lsb_prod_wo[26]), (~ lsb_prod_wo[25]), (~ lsb_prod_wo[24]), (~ lsb_prod_wo[23]), (~ lsb_prod_wo[22]), (~ lsb_prod_wo[21]), (~ lsb_prod_wo[20]), (~ lsb_prod_wo[19]), (~ lsb_prod_wo[18]), (~ lsb_prod_wo[17]), (~ lsb_prod_wo[16]), (~ lsb_prod_wo[15]), (~ lsb_prod_wo[14]), (~ lsb_prod_wo[13]), (~ lsb_prod_wo[12]), (~ lsb_prod_wo[11]), (~ lsb_prod_wo[10]), (~ lsb_prod_wo[9]), (~ lsb_prod_wo[8]), (~ lsb_prod_wo[7]), (~ lsb_prod_wo[6]), (~ lsb_prod_wo[5]), (~ lsb_prod_wo[4]), (~ lsb_prod_wo[3]), (~ lsb_prod_wo[2]), (~ lsb_prod_wo[1]), (~ lsb_prod_wo[0])},
neg_msb = {{31{1'b1}}, (~ msb_prod_wo[58]), (~ msb_prod_wo[57]), (~ msb_prod_wo[56]), (~ msb_prod_wo[55]), (~ msb_prod_wo[54]), (~ msb_prod_wo[53]), (~ msb_prod_wo[52]), (~ msb_prod_wo[51]), (~ msb_prod_wo[50]), (~ msb_prod_wo[49]), (~ msb_prod_wo[48]), (~ msb_prod_wo[47]), (~ msb_prod_wo[46]), (~ msb_prod_wo[45]), (~ msb_prod_wo[44]), (~ msb_prod_wo[43]), (~ msb_prod_wo[42]), (~ msb_prod_wo[41]), (~ msb_prod_wo[40]), (~ msb_prod_wo[39]), (~ msb_prod_wo[38]), (~ msb_prod_wo[37]), (~ msb_prod_wo[36]), (~ msb_prod_wo[35]), (~ msb_prod_wo[34]), (~ msb_prod_wo[33]), (~ msb_prod_wo[32]), (~ msb_prod_wo[31]), (~ msb_prod_wo[30]), (~ msb_prod_wo[29]), (~ msb_prod_wo[28]), (~ msb_prod_wo[27]), (~ msb_prod_wo[26]), (~ msb_prod_wo[25]), (~ msb_prod_wo[24]), (~ msb_prod_wo[23]), (~ msb_prod_wo[22]), (~ msb_prod_wo[21]), (~ msb_prod_wo[20]), (~ msb_prod_wo[19]), (~ msb_prod_wo[18]), (~ msb_prod_wo[17]), (~ msb_prod_wo[16]), (~ msb_prod_wo[15]), (~ msb_prod_wo[14]), (~ msb_prod_wo[13]), (~ msb_prod_wo[12]), (~ msb_prod_wo[11]), (~ msb_prod_wo[10]), (~ msb_prod_wo[9]), (~ msb_prod_wo[8]), (~ msb_prod_wo[7]), (~ msb_prod_wo[6]), (~ msb_prod_wo[5]), (~ msb_prod_wo[4]), (~ msb_prod_wo[3]), (~ msb_prod_wo[2]), (~ msb_prod_wo[1]), (~ msb_prod_wo[0])},
result = {wire_sum_result[88:0], lowest_bits_wo},
sum_one = {((vector2[89] ^ neg_msb[89]) ^ neg_lsb[89]), ((vector2[88] ^ neg_msb[88]) ^ neg_lsb[88]), ((vector2[87] ^ neg_msb[87]) ^ neg_lsb[87]), ((vector2[86] ^ neg_msb[86]) ^ neg_lsb[86]), ((vector2[85] ^ neg_msb[85]) ^ neg_lsb[85]), ((vector2[84] ^ neg_msb[84]) ^ neg_lsb[84]), ((vector2[83] ^ neg_msb[83]) ^ neg_lsb[83]), ((vector2[82] ^ neg_msb[82]) ^ neg_lsb[82]), ((vector2[81] ^ neg_msb[81]) ^ neg_lsb[81]), ((vector2[80] ^ neg_msb[80]) ^ neg_lsb[80]), ((vector2[79] ^ neg_msb[79]) ^ neg_lsb[79]), ((vector2[78] ^ neg_msb[78]) ^ neg_lsb[78]), ((vector2[77] ^ neg_msb[77]) ^ neg_lsb[77]), ((vector2[76] ^ neg_msb[76]) ^ neg_lsb[76]), ((vector2[75] ^ neg_msb[75]) ^ neg_lsb[75]), ((vector2[74] ^ neg_msb[74]) ^ neg_lsb[74]), ((vector2[73] ^ neg_msb[73]) ^ neg_lsb[73]), ((vector2[72] ^ neg_msb[72]) ^ neg_lsb[72]), ((vector2[71] ^ neg_msb[71]) ^ neg_lsb[71]), ((vector2[70] ^ neg_msb[70]) ^ neg_lsb[70]), ((vector2[69] ^ neg_msb[69]) ^ neg_lsb[69]), ((vector2[68] ^ neg_msb[68]) ^ neg_lsb[68]), ((vector2[67] ^ neg_msb[67]) ^ neg_lsb[67]), ((vector2[66] ^ neg_msb[66]) ^ neg_lsb[66]), ((vector2[65] ^ neg_msb[65]) ^ neg_lsb[65]), ((vector2[64] ^ neg_msb[64]) ^ neg_lsb[64]), ((vector2[63] ^ neg_msb[63]) ^ neg_lsb[63]), ((vector2[62] ^ neg_msb[62]) ^ neg_lsb[62]), ((vector2[61] ^ neg_msb[61]) ^ neg_lsb[61]), ((vector2[60] ^ neg_msb[60]) ^ neg_lsb[60]), ((vector2[59] ^ neg_msb[59]) ^ neg_lsb[59]), ((vector2[58] ^ neg_msb[58]) ^ neg_lsb[58]), ((vector2[57] ^ neg_msb[57]) ^ neg_lsb[57]), ((vector2[56] ^ neg_msb[56]) ^ neg_lsb[56]), ((vector2[55] ^ neg_msb[55]) ^ neg_lsb[55]), ((vector2[54] ^ neg_msb[54]) ^ neg_lsb[54]), ((vector2[53] ^ neg_msb[53]) ^ neg_lsb[53]), ((vector2[52] ^ neg_msb[52]) ^ neg_lsb[52]), ((vector2[51] ^ neg_msb[51]) ^ neg_lsb[51]), ((vector2[50] ^ neg_msb[50]) ^ neg_lsb[50]), ((vector2[49] ^ neg_msb[49]) ^ neg_lsb[49]), ((vector2[48] ^ neg_msb[48]) ^ neg_lsb[48]), ((vector2[47] ^ neg_msb[47]) ^ neg_lsb[47]), ((vector2[46] ^ neg_msb[46]) ^ neg_lsb[46]), ((vector2[45] ^ neg_msb[45]) ^ neg_lsb[45]), ((vector2[44]
^ neg_msb[44]) ^ neg_lsb[44]), ((vector2[43] ^ neg_msb[43]) ^ neg_lsb[43]), ((vector2[42] ^ neg_msb[42]) ^ neg_lsb[42]), ((vector2[41] ^ neg_msb[41]) ^ neg_lsb[41]), ((vector2[40] ^ neg_msb[40]) ^ neg_lsb[40]), ((vector2[39] ^ neg_msb[39]) ^ neg_lsb[39]), ((vector2[38] ^ neg_msb[38]) ^ neg_lsb[38]), ((vector2[37] ^ neg_msb[37]) ^ neg_lsb[37]), ((vector2[36] ^ neg_msb[36]) ^ neg_lsb[36]), ((vector2[35] ^ neg_msb[35]) ^ neg_lsb[35]), ((vector2[34] ^ neg_msb[34]) ^ neg_lsb[34]), ((vector2[33] ^ neg_msb[33]) ^ neg_lsb[33]), ((vector2[32] ^ neg_msb[32]) ^ neg_lsb[32]), ((vector2[31] ^ neg_msb[31]) ^ neg_lsb[31]), ((vector2[30] ^ neg_msb[30]) ^ neg_lsb[30]), ((vector2[29] ^ neg_msb[29]) ^ neg_lsb[29]), ((vector2[28] ^ neg_msb[28]) ^ neg_lsb[28]), ((vector2[27] ^ neg_msb[27]) ^ neg_lsb[27]), ((vector2[26] ^ neg_msb[26]) ^ neg_lsb[26]), ((vector2[25] ^ neg_msb[25]) ^ neg_lsb[25]), ((vector2[24] ^ neg_msb[24]) ^ neg_lsb[24]), ((vector2[23] ^ neg_msb[23]) ^ neg_lsb[23]), ((vector2[22] ^ neg_msb[22]) ^ neg_lsb[22]), ((vector2[21] ^ neg_msb[21]) ^ neg_lsb[21]), ((vector2[20] ^ neg_msb[20]) ^ neg_lsb[20]), ((vector2[19] ^ neg_msb[19]) ^ neg_lsb[19]), ((vector2[18] ^ neg_msb[18]) ^ neg_lsb[18]), ((vector2[17] ^ neg_msb[17]) ^ neg_lsb[17]), ((vector2[16] ^ neg_msb[16]) ^ neg_lsb[16]), ((vector2[15] ^ neg_msb[15]) ^ neg_lsb[15]), ((vector2[14] ^ neg_msb[14]) ^ neg_lsb[14]), ((vector2[13] ^ neg_msb[13]) ^ neg_lsb[13]), ((vector2[12] ^ neg_msb[12]) ^ neg_lsb[12]), ((vector2[11] ^ neg_msb[11]) ^ neg_lsb[11]), ((vector2[10] ^ neg_msb[10]) ^ neg_lsb[10]), ((vector2[9] ^ neg_msb[9]) ^ neg_lsb[9]), ((vector2[8] ^ neg_msb[8]) ^ neg_lsb[8]), ((vector2[7] ^ neg_msb[7]) ^ neg_lsb[7]), ((vector2[6] ^ neg_msb[6]) ^ neg_lsb[6]), ((vector2[5] ^ neg_msb[5]) ^ neg_lsb[5]), ((vector2[4] ^ neg_msb[4]) ^ neg_lsb[4]), ((vector2[3] ^ neg_msb[3]) ^ neg_lsb[3]), ((vector2[2] ^ neg_msb[2]) ^ neg_lsb[2]), ((vector2[1] ^ neg_msb[1]) ^ neg_lsb[1]), ((vector2[0] ^ neg_msb[0]) ^ neg_lsb[0])},
sum_two = {((vector1[89] ^ sum_one[89]) ^ car_one_adj[89]), ((vector1[88] ^ sum_one[88]) ^ car_one_adj[88]), ((vector1[87] ^ sum_one[87]) ^ car_one_adj[87]), ((vector1[86] ^ sum_one[86]) ^ car_one_adj[86]), ((vector1[85] ^ sum_one[85]) ^ car_one_adj[85]), ((vector1[84] ^ sum_one[84]) ^ car_one_adj[84]), ((vector1[83] ^ sum_one[83]) ^ car_one_adj[83]), ((vector1[82] ^ sum_one[82]) ^ car_one_adj[82]), ((vector1[81] ^ sum_one[81]) ^ car_one_adj[81]), ((vector1[80] ^ sum_one[80]) ^ car_one_adj[80]), ((vector1[79] ^ sum_one[79]) ^ car_one_adj[79]), ((vector1[78] ^ sum_one[78]) ^ car_one_adj[78]), ((vector1[77] ^ sum_one[77]) ^ car_one_adj[77]), ((vector1[76] ^ sum_one[76]) ^ car_one_adj[76]), ((vector1[75] ^ sum_one[75]) ^ car_one_adj[75]), ((vector1[74] ^ sum_one[74]) ^ car_one_adj[74]), ((vector1[73] ^ sum_one[73]) ^ car_one_adj[73]), ((vector1[72] ^ sum_one[72]) ^ car_one_adj[72]), ((vector1[71] ^ sum_one[71]) ^ car_one_adj[71]), ((vector1[70] ^ sum_one[70]) ^ car_one_adj[70]), ((vector1[69] ^ sum_one[69]) ^ car_one_adj[69]), ((vector1[68] ^ sum_one[68]) ^ car_one_adj[68]), ((vector1[67] ^ sum_one[67]) ^ car_one_adj[67]), ((vector1[66] ^ sum_one[66]) ^ car_one_adj[66]), ((vector1[65] ^ sum_one[65]) ^ car_one_adj[65]), ((vector1[64] ^ sum_one[64]) ^ car_one_adj[64]), ((vector1[63] ^ sum_one[63]) ^ car_one_adj[63]), ((vector1[62] ^ sum_one[62]) ^ car_one_adj[62]), ((vector1[61] ^ sum_one[61]) ^ car_one_adj[61]), ((vector1[60] ^ sum_one[60]) ^ car_one_adj[60]), ((vector1[59] ^ sum_one[59]) ^ car_one_adj[59]), ((vector1[58] ^ sum_one[58]) ^ car_one_adj[58]), ((vector1[57] ^ sum_one[57]) ^ car_one_adj[57]), ((vector1[56] ^ sum_one[56]) ^ car_one_adj[56]), ((vector1[55] ^ sum_one[55]) ^ car_one_adj[55]), ((vector1[54] ^ sum_one[54]) ^ car_one_adj[54]), ((vector1[53] ^ sum_one[53]) ^ car_one_adj[53]), ((vector1[52] ^ sum_one[52]) ^ car_one_adj[52]), ((vector1[51] ^ sum_one[51]) ^ car_one_adj[51]), ((vector1[50] ^ sum_one[50]) ^ car_one_adj[50]), ((vector1[49] ^ sum_one[49]) ^ car_one_adj[49]), ((vector1[48] ^ sum_one[48]
) ^ car_one_adj[48]), ((vector1[47] ^ sum_one[47]) ^ car_one_adj[47]), ((vector1[46] ^ sum_one[46]) ^ car_one_adj[46]), ((vector1[45] ^ sum_one[45]) ^ car_one_adj[45]), ((vector1[44] ^ sum_one[44]) ^ car_one_adj[44]), ((vector1[43] ^ sum_one[43]) ^ car_one_adj[43]), ((vector1[42] ^ sum_one[42]) ^ car_one_adj[42]), ((vector1[41] ^ sum_one[41]) ^ car_one_adj[41]), ((vector1[40] ^ sum_one[40]) ^ car_one_adj[40]), ((vector1[39] ^ sum_one[39]) ^ car_one_adj[39]), ((vector1[38] ^ sum_one[38]) ^ car_one_adj[38]), ((vector1[37] ^ sum_one[37]) ^ car_one_adj[37]), ((vector1[36] ^ sum_one[36]) ^ car_one_adj[36]), ((vector1[35] ^ sum_one[35]) ^ car_one_adj[35]), ((vector1[34] ^ sum_one[34]) ^ car_one_adj[34]), ((vector1[33] ^ sum_one[33]) ^ car_one_adj[33]), ((vector1[32] ^ sum_one[32]) ^ car_one_adj[32]), ((vector1[31] ^ sum_one[31]) ^ car_one_adj[31]), ((vector1[30] ^ sum_one[30]) ^ car_one_adj[30]), ((vector1[29] ^ sum_one[29]) ^ car_one_adj[29]), ((vector1[28] ^ sum_one[28]) ^ car_one_adj[28]), ((vector1[27] ^ sum_one[27]) ^ car_one_adj[27]), ((vector1[26] ^ sum_one[26]) ^ car_one_adj[26]), ((vector1[25] ^ sum_one[25]) ^ car_one_adj[25]), ((vector1[24] ^ sum_one[24]) ^ car_one_adj[24]), ((vector1[23] ^ sum_one[23]) ^ car_one_adj[23]), ((vector1[22] ^ sum_one[22]) ^ car_one_adj[22]), ((vector1[21] ^ sum_one[21]) ^ car_one_adj[21]), ((vector1[20] ^ sum_one[20]) ^ car_one_adj[20]), ((vector1[19] ^ sum_one[19]) ^ car_one_adj[19]), ((vector1[18] ^ sum_one[18]) ^ car_one_adj[18]), ((vector1[17] ^ sum_one[17]) ^ car_one_adj[17]), ((vector1[16] ^ sum_one[16]) ^ car_one_adj[16]), ((vector1[15] ^ sum_one[15]) ^ car_one_adj[15]), ((vector1[14] ^ sum_one[14]) ^ car_one_adj[14]), ((vector1[13] ^ sum_one[13]) ^ car_one_adj[13]), ((vector1[12] ^ sum_one[12]) ^ car_one_adj[12]), ((vector1[11] ^ sum_one[11]) ^ car_one_adj[11]), ((vector1[10] ^ sum_one[10]) ^ car_one_adj[10]), ((vector1[9] ^ sum_one[9]) ^ car_one_adj[9]), ((vector1[8] ^ sum_one[8]) ^ car_one_adj[8]), ((vector1[7] ^ sum_one[7]) ^ car_one_adj[7]), ((vector1[6] ^ sum_one[6])
^ car_one_adj[6]), ((vector1[5] ^ sum_one[5]) ^ car_one_adj[5]), ((vector1[4] ^ sum_one[4]) ^ car_one_adj[4]), ((vector1[3] ^ sum_one[3]) ^ car_one_adj[3]), ((vector1[2] ^ sum_one[2]) ^ car_one_adj[2]), ((vector1[1] ^ sum_one[1]) ^ car_one_adj[1]), ((vector1[0] ^ sum_one[0]) ^ car_one_adj[0])},
sum_two_wo = sum_two_reg0,
vector1 = {msb_prod_wo, lsb_prod_wo[61:31]},
vector2 = {{26{1'b0}}, mid_prod_wo},
wire_a = dataa,
wire_b = datab;
endmodule //acl_fp_exp_double_altmult_opt_k9e
//synthesis_resources = lpm_add_sub 18 lpm_clshift 1 lpm_compare 3 lpm_mult 11 lpm_mux 3 mux21 224 reg 2890
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_exp_double_altfp_exp_79d
(
clk_en,
clock,
data,
result) ;
input clk_en;
input clock;
input [63:0] data;
output [63:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [119:0] wire_man_prod_result;
wire [121:0] wire_tbl1_tbl2_prod_result;
wire [119:0] wire_tbl3_taylor_prod_result;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes0;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes1;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes2;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes3;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes4;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes5;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes6;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes7;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes8;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes9;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes10;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes11;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes12;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes13;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes14;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes15;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes16;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes17;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes18;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes19;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes20;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes21;
reg [0:0] barrel_shifter_underflow_dffe2_23_pipes22;
reg [0:0] distance_overflow_dffe2_23_pipes0;
reg [0:0] distance_overflow_dffe2_23_pipes1;
reg [0:0] distance_overflow_dffe2_23_pipes2;
reg [0:0] distance_overflow_dffe2_23_pipes3;
reg [0:0] distance_overflow_dffe2_23_pipes4;
reg [0:0] distance_overflow_dffe2_23_pipes5;
reg [0:0] distance_overflow_dffe2_23_pipes6;
reg [0:0] distance_overflow_dffe2_23_pipes7;
reg [0:0] distance_overflow_dffe2_23_pipes8;
reg [0:0] distance_overflow_dffe2_23_pipes9;
reg [0:0] distance_overflow_dffe2_23_pipes10;
reg [0:0] distance_overflow_dffe2_23_pipes11;
reg [0:0] distance_overflow_dffe2_23_pipes12;
reg [0:0] distance_overflow_dffe2_23_pipes13;
reg [0:0] distance_overflow_dffe2_23_pipes14;
reg [0:0] distance_overflow_dffe2_23_pipes15;
reg [0:0] distance_overflow_dffe2_23_pipes16;
reg [0:0] distance_overflow_dffe2_23_pipes17;
reg [0:0] distance_overflow_dffe2_23_pipes18;
reg [0:0] distance_overflow_dffe2_23_pipes19;
reg [0:0] distance_overflow_dffe2_23_pipes20;
reg [0:0] distance_overflow_dffe2_23_pipes21;
reg [0:0] distance_overflow_dffe2_23_pipes22;
reg [10:0] exp_value_b4_bias_dffe_0;
reg [10:0] exp_value_b4_bias_dffe_1;
reg [10:0] exp_value_b4_bias_dffe_10;
reg [10:0] exp_value_b4_bias_dffe_11;
reg [10:0] exp_value_b4_bias_dffe_12;
reg [10:0] exp_value_b4_bias_dffe_13;
reg [10:0] exp_value_b4_bias_dffe_14;
reg [10:0] exp_value_b4_bias_dffe_15;
reg [10:0] exp_value_b4_bias_dffe_16;
reg [10:0] exp_value_b4_bias_dffe_17;
reg [10:0] exp_value_b4_bias_dffe_18;
reg [10:0] exp_value_b4_bias_dffe_2;
reg [10:0] exp_value_b4_bias_dffe_3;
reg [10:0] exp_value_b4_bias_dffe_4;
reg [10:0] exp_value_b4_bias_dffe_5;
reg [10:0] exp_value_b4_bias_dffe_6;
reg [10:0] exp_value_b4_bias_dffe_7;
reg [10:0] exp_value_b4_bias_dffe_8;
reg [10:0] exp_value_b4_bias_dffe_9;
reg [11:0] exp_value_dffe1;
reg extra_ln2_dffe_0;
reg extra_ln2_dffe_1;
reg extra_ln2_dffe_10;
reg extra_ln2_dffe_11;
reg extra_ln2_dffe_2;
reg extra_ln2_dffe_3;
reg extra_ln2_dffe_4;
reg extra_ln2_dffe_5;
reg extra_ln2_dffe_6;
reg extra_ln2_dffe_7;
reg extra_ln2_dffe_8;
reg extra_ln2_dffe_9;
reg [51:0] fraction_dffe1;
reg [0:0] input_is_infinity_24_pipes0;
reg [0:0] input_is_infinity_24_pipes1;
reg [0:0] input_is_infinity_24_pipes2;
reg [0:0] input_is_infinity_24_pipes3;
reg [0:0] input_is_infinity_24_pipes4;
reg [0:0] input_is_infinity_24_pipes5;
reg [0:0] input_is_infinity_24_pipes6;
reg [0:0] input_is_infinity_24_pipes7;
reg [0:0] input_is_infinity_24_pipes8;
reg [0:0] input_is_infinity_24_pipes9;
reg [0:0] input_is_infinity_24_pipes10;
reg [0:0] input_is_infinity_24_pipes11;
reg [0:0] input_is_infinity_24_pipes12;
reg [0:0] input_is_infinity_24_pipes13;
reg [0:0] input_is_infinity_24_pipes14;
reg [0:0] input_is_infinity_24_pipes15;
reg [0:0] input_is_infinity_24_pipes16;
reg [0:0] input_is_infinity_24_pipes17;
reg [0:0] input_is_infinity_24_pipes18;
reg [0:0] input_is_infinity_24_pipes19;
reg [0:0] input_is_infinity_24_pipes20;
reg [0:0] input_is_infinity_24_pipes21;
reg [0:0] input_is_infinity_24_pipes22;
reg [0:0] input_is_infinity_24_pipes23;
reg [0:0] input_is_nan_24_pipes0;
reg [0:0] input_is_nan_24_pipes1;
reg [0:0] input_is_nan_24_pipes2;
reg [0:0] input_is_nan_24_pipes3;
reg [0:0] input_is_nan_24_pipes4;
reg [0:0] input_is_nan_24_pipes5;
reg [0:0] input_is_nan_24_pipes6;
reg [0:0] input_is_nan_24_pipes7;
reg [0:0] input_is_nan_24_pipes8;
reg [0:0] input_is_nan_24_pipes9;
reg [0:0] input_is_nan_24_pipes10;
reg [0:0] input_is_nan_24_pipes11;
reg [0:0] input_is_nan_24_pipes12;
reg [0:0] input_is_nan_24_pipes13;
reg [0:0] input_is_nan_24_pipes14;
reg [0:0] input_is_nan_24_pipes15;
reg [0:0] input_is_nan_24_pipes16;
reg [0:0] input_is_nan_24_pipes17;
reg [0:0] input_is_nan_24_pipes18;
reg [0:0] input_is_nan_24_pipes19;
reg [0:0] input_is_nan_24_pipes20;
reg [0:0] input_is_nan_24_pipes21;
reg [0:0] input_is_nan_24_pipes22;
reg [0:0] input_is_nan_24_pipes23;
reg [0:0] input_is_zero_24_pipes0;
reg [0:0] input_is_zero_24_pipes1;
reg [0:0] input_is_zero_24_pipes2;
reg [0:0] input_is_zero_24_pipes3;
reg [0:0] input_is_zero_24_pipes4;
reg [0:0] input_is_zero_24_pipes5;
reg [0:0] input_is_zero_24_pipes6;
reg [0:0] input_is_zero_24_pipes7;
reg [0:0] input_is_zero_24_pipes8;
reg [0:0] input_is_zero_24_pipes9;
reg [0:0] input_is_zero_24_pipes10;
reg [0:0] input_is_zero_24_pipes11;
reg [0:0] input_is_zero_24_pipes12;
reg [0:0] input_is_zero_24_pipes13;
reg [0:0] input_is_zero_24_pipes14;
reg [0:0] input_is_zero_24_pipes15;
reg [0:0] input_is_zero_24_pipes16;
reg [0:0] input_is_zero_24_pipes17;
reg [0:0] input_is_zero_24_pipes18;
reg [0:0] input_is_zero_24_pipes19;
reg [0:0] input_is_zero_24_pipes20;
reg [0:0] input_is_zero_24_pipes21;
reg [0:0] input_is_zero_24_pipes22;
reg [0:0] input_is_zero_24_pipes23;
reg man_overflow_dffe15;
reg [51:0] man_round_dffe15;
reg [62:0] result_pipe_dffe16;
reg round_up_dffe15;
reg [0:0] sign_dffe0;
reg [0:0] sign_dffe1;
reg [0:0] sign_dffe2;
reg [0:0] sign_dffe3;
reg [0:0] sign_dffe4;
reg [0:0] sign_dffe5;
reg [0:0] sign_dffe6;
reg [0:0] sign_dffe7;
reg [0:0] sign_dffe8;
reg [0:0] sign_dffe9;
reg [0:0] sign_dffe10;
reg [0:0] sign_dffe11;
reg [0:0] sign_dffe12;
reg [0:0] sign_dffe13;
reg [0:0] sign_dffe14;
reg [0:0] sign_dffe15;
reg [0:0] sign_dffe16;
reg [0:0] sign_dffe17;
reg [0:0] sign_dffe18;
reg [0:0] sign_dffe19;
reg [0:0] sign_dffe20;
reg [0:0] sign_dffe21;
reg [0:0] sign_dffe22;
reg [0:0] sign_dffe23;
reg [60:0] table_one_dffe12;
reg [60:0] table_three_dffe12;
reg [60:0] table_two_dffe12;
reg [0:0] tbl1_compare_dffe11_10_pipes0;
reg [0:0] tbl1_compare_dffe11_10_pipes1;
reg [0:0] tbl1_compare_dffe11_10_pipes2;
reg [0:0] tbl1_compare_dffe11_10_pipes3;
reg [0:0] tbl1_compare_dffe11_10_pipes4;
reg [0:0] tbl1_compare_dffe11_10_pipes5;
reg [0:0] tbl1_compare_dffe11_10_pipes6;
reg [0:0] tbl1_compare_dffe11_10_pipes7;
reg [0:0] tbl1_compare_dffe11_10_pipes8;
reg [0:0] tbl1_compare_dffe11_10_pipes9;
reg [69:0] x_fixed_dffe_0;
reg [69:0] x_fixed_dffe_1;
reg [69:0] x_fixed_dffe_2;
reg [69:0] x_fixed_dffe_3;
reg [69:0] x_fixed_dffe_4;
reg [69:0] x_fixed_dffe_5;
reg [69:0] x_fixed_dffe_6;
reg [59:0] xf_pl_dffe12;
reg [69:0] xf_pre_2_dffe10;
reg [69:0] xf_pre_dffe9;
reg [10:0] xi_exp_value_dffe4;
reg [80:0] xi_ln2_prod_dffe7;
reg [26:0] xi_prod_dffe3;
wire [11:0] wire_exp_minus_bias_result;
wire [11:0] wire_exp_value_add_bias_result;
wire [11:0] wire_exp_value_man_over_result;
wire [10:0] wire_invert_exp_value_result;
wire [51:0] wire_man_round_result;
wire [59:0] wire_one_minus_xf_result;
wire [69:0] wire_x_fixed_minus_xiln2_result;
wire [59:0] wire_xf_minus_ln2_result;
wire [10:0] wire_xi_add_one_result;
wire [69:0] wire_rbarrel_shift_result;
wire wire_distance_overflow_comp_agb;
wire wire_tbl1_compare_ageb;
wire wire_underflow_compare_agb;
wire [80:0] wire_xi_ln2_prod_result;
wire [26:0] wire_xi_prod_result;
wire [60:0] wire_table_one_result;
wire [41:0] wire_table_three_result;
wire [50:0] wire_table_two_result;
wire wire_cin_to_bias_dataout;
wire [10:0]wire_exp_result_mux_prea_dataout;
wire [10:0]wire_exp_value_b4_biasa_dataout;
wire [6:0]wire_exp_value_selecta_dataout;
wire [10:0]wire_exp_value_to_compare_muxa_dataout;
wire [10:0]wire_exp_value_to_ln2a_dataout;
wire [59:0]wire_extra_ln2_muxa_dataout;
wire [51:0]wire_man_result_muxa_dataout;
wire [59:0]wire_xf_muxa_dataout;
wire aclr;
wire [8:0] addr_val_more_than_one;
wire [69:0] barrel_shifter_data;
wire [6:0] barrel_shifter_distance;
wire barrel_shifter_underflow;
wire barrel_shifter_underflow_wi;
wire distance_overflow;
wire [10:0] distance_overflow_val_w;
wire distance_overflow_wi;
wire [10:0] exp_bias;
wire [10:0] exp_bias_all_ones_w;
wire [10:0] exp_data_all_one_w;
wire [10:0] exp_data_not_zero_w;
wire [10:0] exp_invert;
wire [10:0] exp_one;
wire [10:0] exp_out_all_one_w;
wire [10:0] exp_out_not_zero_w;
wire [10:0] exp_result_out;
wire [10:0] exp_result_w;
wire [11:0] exp_value;
wire [11:0] exp_value_wi;
wire [11:0] exp_value_wo;
wire [10:0] exp_w;
wire extra_ln2;
wire [51:0] fraction;
wire [51:0] fraction_wi;
wire [51:0] fraction_wo;
wire gnd_w;
wire guard_bit;
wire input_is_infinity_wi;
wire input_is_infinity_wo;
wire input_is_nan_wi;
wire input_is_nan_wo;
wire input_is_zero_wi;
wire input_is_zero_wo;
wire [69:0] ln2_w;
wire [51:0] man_data_not_zero_w;
wire man_overflow;
wire man_overflow_wi;
wire man_overflow_wo;
wire [119:0] man_prod_result;
wire [119:0] man_prod_shifted;
wire [119:0] man_prod_wi;
wire [119:0] man_prod_wire;
wire [119:0] man_prod_wo;
wire [51:0] man_result_all_ones;
wire [51:0] man_result_w;
wire [51:0] man_round_wi;
wire [51:0] man_round_wo;
wire nan_w;
wire negative_infinity;
wire [11:0] one_over_ln2_w;
wire overflow_w;
wire positive_infinity;
wire [62:0] result_pipe_wi;
wire [62:0] result_pipe_wo;
wire result_underflow_w;
wire round_bit;
wire round_up;
wire round_up_wi;
wire round_up_wo;
wire shifted_value;
wire sign_w;
wire [4:0] sticky_bits;
wire [31231:0] table_one_data;
wire [60:0] table_one_out;
wire [60:0] table_one_out_pl;
wire [21503:0] table_three_data;
wire [60:0] table_three_out;
wire [60:0] table_three_out_pl;
wire [41:0] table_three_out_tmp;
wire [26111:0] table_two_data;
wire [60:0] table_two_out;
wire [60:0] table_two_out_pl;
wire [50:0] table_two_out_tmp;
wire tbl1_compare_wi;
wire tbl1_compare_wo;
wire [59:0] tbl1_tbl2_prod_wi;
wire [59:0] tbl1_tbl2_prod_wo;
wire [59:0] tbl3_taylor_prod_wi;
wire [59:0] tbl3_taylor_prod_wo;
wire [10:0] underflow_compare_val_w;
wire underflow_w;
wire [69:0] x_fixed;
wire [59:0] xf;
wire [59:0] xf_pl;
wire [69:0] xf_pre;
wire [69:0] xf_pre_2_wi;
wire [69:0] xf_pre_2_wo;
wire [69:0] xf_pre_wi;
wire [69:0] xf_pre_wo;
wire [10:0] xi_exp_value;
wire [10:0] xi_exp_value_wi;
wire [10:0] xi_exp_value_wo;
wire [80:0] xi_ln2_prod_wi;
wire [80:0] xi_ln2_prod_wo;
wire [26:0] xi_prod_wi;
wire [26:0] xi_prod_wo;
acl_fp_exp_double_altmult_opt_a9e man_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(tbl1_tbl2_prod_wo),
.datab(tbl3_taylor_prod_wo),
.result(wire_man_prod_result));
acl_fp_exp_double_altmult_opt_f9e tbl1_tbl2_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(table_one_out_pl),
.datab(table_two_out_pl),
.result(wire_tbl1_tbl2_prod_result));
acl_fp_exp_double_altmult_opt_k9e tbl3_taylor_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(table_three_out_pl),
.datab({1'b1, {27{1'b0}}, xf_pl[30:0]}),
.result(wire_tbl3_taylor_prod_result));
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes0 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes0 <= barrel_shifter_underflow_wi;
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes1 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes1 <= barrel_shifter_underflow_dffe2_23_pipes0[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes2 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes2 <= barrel_shifter_underflow_dffe2_23_pipes1[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes3 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes3 <= barrel_shifter_underflow_dffe2_23_pipes2[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes4 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes4 <= barrel_shifter_underflow_dffe2_23_pipes3[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes5 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes5 <= barrel_shifter_underflow_dffe2_23_pipes4[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes6 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes6 <= barrel_shifter_underflow_dffe2_23_pipes5[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes7 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes7 <= barrel_shifter_underflow_dffe2_23_pipes6[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes8 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes8 <= barrel_shifter_underflow_dffe2_23_pipes7[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes9 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes9 <= barrel_shifter_underflow_dffe2_23_pipes8[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes10 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes10 <= barrel_shifter_underflow_dffe2_23_pipes9[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes11 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes11 <= barrel_shifter_underflow_dffe2_23_pipes10[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes12 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes12 <= barrel_shifter_underflow_dffe2_23_pipes11[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes13 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes13 <= barrel_shifter_underflow_dffe2_23_pipes12[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes14 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes14 <= barrel_shifter_underflow_dffe2_23_pipes13[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes15 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes15 <= barrel_shifter_underflow_dffe2_23_pipes14[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes16 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes16 <= barrel_shifter_underflow_dffe2_23_pipes15[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes17 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes17 <= barrel_shifter_underflow_dffe2_23_pipes16[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes18 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes18 <= barrel_shifter_underflow_dffe2_23_pipes17[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes19 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes19 <= barrel_shifter_underflow_dffe2_23_pipes18[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes20 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes20 <= barrel_shifter_underflow_dffe2_23_pipes19[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes21 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes21 <= barrel_shifter_underflow_dffe2_23_pipes20[0:0];
// synopsys translate_off
initial
barrel_shifter_underflow_dffe2_23_pipes22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) barrel_shifter_underflow_dffe2_23_pipes22 <= 1'b0;
else if (clk_en == 1'b1) barrel_shifter_underflow_dffe2_23_pipes22 <= barrel_shifter_underflow_dffe2_23_pipes21[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes0 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes0 <= distance_overflow_wi;
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes1 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes1 <= distance_overflow_dffe2_23_pipes0[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes2 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes2 <= distance_overflow_dffe2_23_pipes1[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes3 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes3 <= distance_overflow_dffe2_23_pipes2[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes4 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes4 <= distance_overflow_dffe2_23_pipes3[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes5 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes5 <= distance_overflow_dffe2_23_pipes4[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes6 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes6 <= distance_overflow_dffe2_23_pipes5[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes7 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes7 <= distance_overflow_dffe2_23_pipes6[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes8 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes8 <= distance_overflow_dffe2_23_pipes7[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes9 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes9 <= distance_overflow_dffe2_23_pipes8[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes10 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes10 <= distance_overflow_dffe2_23_pipes9[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes11 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes11 <= distance_overflow_dffe2_23_pipes10[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes12 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes12 <= distance_overflow_dffe2_23_pipes11[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes13 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes13 <= distance_overflow_dffe2_23_pipes12[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes14 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes14 <= distance_overflow_dffe2_23_pipes13[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes15 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes15 <= distance_overflow_dffe2_23_pipes14[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes16 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes16 <= distance_overflow_dffe2_23_pipes15[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes17 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes17 <= distance_overflow_dffe2_23_pipes16[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes18 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes18 <= distance_overflow_dffe2_23_pipes17[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes19 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes19 <= distance_overflow_dffe2_23_pipes18[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes20 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes20 <= distance_overflow_dffe2_23_pipes19[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes21 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes21 <= distance_overflow_dffe2_23_pipes20[0:0];
// synopsys translate_off
initial
distance_overflow_dffe2_23_pipes22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) distance_overflow_dffe2_23_pipes22 <= 1'b0;
else if (clk_en == 1'b1) distance_overflow_dffe2_23_pipes22 <= distance_overflow_dffe2_23_pipes21[0:0];
// synopsys translate_off
initial
exp_value_b4_bias_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_0 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_0 <= wire_exp_value_b4_biasa_dataout;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_1 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_1 <= exp_value_b4_bias_dffe_0;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_10 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_10 <= exp_value_b4_bias_dffe_9;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_11 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_11 <= exp_value_b4_bias_dffe_10;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_12 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_12 <= exp_value_b4_bias_dffe_11;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_13 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_13 <= exp_value_b4_bias_dffe_12;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_14 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_14 <= exp_value_b4_bias_dffe_13;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_15 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_15 <= exp_value_b4_bias_dffe_14;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_16 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_16 <= exp_value_b4_bias_dffe_15;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_17 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_17 <= exp_value_b4_bias_dffe_16;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_18 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_18 <= exp_value_b4_bias_dffe_17;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_2 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_2 <= exp_value_b4_bias_dffe_1;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_3 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_3 <= exp_value_b4_bias_dffe_2;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_4 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_4 <= exp_value_b4_bias_dffe_3;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_5 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_5 <= exp_value_b4_bias_dffe_4;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_6 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_6 <= exp_value_b4_bias_dffe_5;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_7 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_7 <= exp_value_b4_bias_dffe_6;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_8 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_8 <= exp_value_b4_bias_dffe_7;
// synopsys translate_off
initial
exp_value_b4_bias_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_b4_bias_dffe_9 <= 11'b0;
else if (clk_en == 1'b1) exp_value_b4_bias_dffe_9 <= exp_value_b4_bias_dffe_8;
// synopsys translate_off
initial
exp_value_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exp_value_dffe1 <= 12'b0;
else if (clk_en == 1'b1) exp_value_dffe1 <= exp_value_wi;
// synopsys translate_off
initial
extra_ln2_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_0 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_0 <= extra_ln2;
// synopsys translate_off
initial
extra_ln2_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_1 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_1 <= extra_ln2_dffe_0;
// synopsys translate_off
initial
extra_ln2_dffe_10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_10 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_10 <= extra_ln2_dffe_9;
// synopsys translate_off
initial
extra_ln2_dffe_11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_11 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_11 <= extra_ln2_dffe_10;
// synopsys translate_off
initial
extra_ln2_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_2 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_2 <= extra_ln2_dffe_1;
// synopsys translate_off
initial
extra_ln2_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_3 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_3 <= extra_ln2_dffe_2;
// synopsys translate_off
initial
extra_ln2_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_4 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_4 <= extra_ln2_dffe_3;
// synopsys translate_off
initial
extra_ln2_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_5 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_5 <= extra_ln2_dffe_4;
// synopsys translate_off
initial
extra_ln2_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_6 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_6 <= extra_ln2_dffe_5;
// synopsys translate_off
initial
extra_ln2_dffe_7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_7 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_7 <= extra_ln2_dffe_6;
// synopsys translate_off
initial
extra_ln2_dffe_8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_8 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_8 <= extra_ln2_dffe_7;
// synopsys translate_off
initial
extra_ln2_dffe_9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) extra_ln2_dffe_9 <= 1'b0;
else if (clk_en == 1'b1) extra_ln2_dffe_9 <= extra_ln2_dffe_8;
// synopsys translate_off
initial
fraction_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) fraction_dffe1 <= 52'b0;
else if (clk_en == 1'b1) fraction_dffe1 <= fraction_wi;
// synopsys translate_off
initial
input_is_infinity_24_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes0 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes0 <= input_is_infinity_wi;
// synopsys translate_off
initial
input_is_infinity_24_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes1 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes1 <= input_is_infinity_24_pipes0[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes2 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes2 <= input_is_infinity_24_pipes1[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes3 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes3 <= input_is_infinity_24_pipes2[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes4 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes4 <= input_is_infinity_24_pipes3[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes5 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes5 <= input_is_infinity_24_pipes4[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes6 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes6 <= input_is_infinity_24_pipes5[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes7 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes7 <= input_is_infinity_24_pipes6[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes8 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes8 <= input_is_infinity_24_pipes7[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes9 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes9 <= input_is_infinity_24_pipes8[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes10 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes10 <= input_is_infinity_24_pipes9[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes11 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes11 <= input_is_infinity_24_pipes10[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes12 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes12 <= input_is_infinity_24_pipes11[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes13 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes13 <= input_is_infinity_24_pipes12[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes14 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes14 <= input_is_infinity_24_pipes13[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes15 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes15 <= input_is_infinity_24_pipes14[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes16 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes16 <= input_is_infinity_24_pipes15[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes17 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes17 <= input_is_infinity_24_pipes16[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes18 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes18 <= input_is_infinity_24_pipes17[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes19 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes19 <= input_is_infinity_24_pipes18[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes20 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes20 <= input_is_infinity_24_pipes19[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes21 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes21 <= input_is_infinity_24_pipes20[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes22 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes22 <= input_is_infinity_24_pipes21[0:0];
// synopsys translate_off
initial
input_is_infinity_24_pipes23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_infinity_24_pipes23 <= 1'b0;
else if (clk_en == 1'b1) input_is_infinity_24_pipes23 <= input_is_infinity_24_pipes22[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes0 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes0 <= input_is_nan_wi;
// synopsys translate_off
initial
input_is_nan_24_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes1 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes1 <= input_is_nan_24_pipes0[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes2 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes2 <= input_is_nan_24_pipes1[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes3 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes3 <= input_is_nan_24_pipes2[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes4 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes4 <= input_is_nan_24_pipes3[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes5 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes5 <= input_is_nan_24_pipes4[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes6 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes6 <= input_is_nan_24_pipes5[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes7 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes7 <= input_is_nan_24_pipes6[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes8 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes8 <= input_is_nan_24_pipes7[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes9 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes9 <= input_is_nan_24_pipes8[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes10 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes10 <= input_is_nan_24_pipes9[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes11 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes11 <= input_is_nan_24_pipes10[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes12 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes12 <= input_is_nan_24_pipes11[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes13 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes13 <= input_is_nan_24_pipes12[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes14 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes14 <= input_is_nan_24_pipes13[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes15 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes15 <= input_is_nan_24_pipes14[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes16 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes16 <= input_is_nan_24_pipes15[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes17 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes17 <= input_is_nan_24_pipes16[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes18 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes18 <= input_is_nan_24_pipes17[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes19 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes19 <= input_is_nan_24_pipes18[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes20 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes20 <= input_is_nan_24_pipes19[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes21 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes21 <= input_is_nan_24_pipes20[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes22 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes22 <= input_is_nan_24_pipes21[0:0];
// synopsys translate_off
initial
input_is_nan_24_pipes23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_nan_24_pipes23 <= 1'b0;
else if (clk_en == 1'b1) input_is_nan_24_pipes23 <= input_is_nan_24_pipes22[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes0 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes0 <= input_is_zero_wi;
// synopsys translate_off
initial
input_is_zero_24_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes1 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes1 <= input_is_zero_24_pipes0[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes2 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes2 <= input_is_zero_24_pipes1[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes3 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes3 <= input_is_zero_24_pipes2[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes4 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes4 <= input_is_zero_24_pipes3[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes5 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes5 <= input_is_zero_24_pipes4[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes6 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes6 <= input_is_zero_24_pipes5[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes7 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes7 <= input_is_zero_24_pipes6[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes8 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes8 <= input_is_zero_24_pipes7[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes9 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes9 <= input_is_zero_24_pipes8[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes10 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes10 <= input_is_zero_24_pipes9[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes11 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes11 <= input_is_zero_24_pipes10[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes12 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes12 <= input_is_zero_24_pipes11[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes13 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes13 <= input_is_zero_24_pipes12[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes14 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes14 <= input_is_zero_24_pipes13[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes15 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes15 <= input_is_zero_24_pipes14[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes16 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes16 <= input_is_zero_24_pipes15[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes17 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes17 <= input_is_zero_24_pipes16[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes18 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes18 <= input_is_zero_24_pipes17[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes19 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes19 <= input_is_zero_24_pipes18[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes20 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes20 <= input_is_zero_24_pipes19[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes21 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes21 <= input_is_zero_24_pipes20[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes22 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes22 <= input_is_zero_24_pipes21[0:0];
// synopsys translate_off
initial
input_is_zero_24_pipes23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) input_is_zero_24_pipes23 <= 1'b0;
else if (clk_en == 1'b1) input_is_zero_24_pipes23 <= input_is_zero_24_pipes22[0:0];
// synopsys translate_off
initial
man_overflow_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_overflow_dffe15 <= 1'b0;
else if (clk_en == 1'b1) man_overflow_dffe15 <= man_overflow_wi;
// synopsys translate_off
initial
man_round_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) man_round_dffe15 <= 52'b0;
else if (clk_en == 1'b1) man_round_dffe15 <= man_round_wi;
// synopsys translate_off
initial
result_pipe_dffe16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_pipe_dffe16 <= 63'b0;
else if (clk_en == 1'b1) result_pipe_dffe16 <= result_pipe_wi;
// synopsys translate_off
initial
round_up_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) round_up_dffe15 <= 1'b0;
else if (clk_en == 1'b1) round_up_dffe15 <= round_up_wi;
// synopsys translate_off
initial
sign_dffe0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe0 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe0 <= sign_w;
// synopsys translate_off
initial
sign_dffe1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe1 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe1 <= sign_dffe0[0:0];
// synopsys translate_off
initial
sign_dffe2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe2 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe2 <= sign_dffe1[0:0];
// synopsys translate_off
initial
sign_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe3 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe3 <= sign_dffe2[0:0];
// synopsys translate_off
initial
sign_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe4 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe4 <= sign_dffe3[0:0];
// synopsys translate_off
initial
sign_dffe5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe5 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe5 <= sign_dffe4[0:0];
// synopsys translate_off
initial
sign_dffe6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe6 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe6 <= sign_dffe5[0:0];
// synopsys translate_off
initial
sign_dffe7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe7 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe7 <= sign_dffe6[0:0];
// synopsys translate_off
initial
sign_dffe8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe8 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe8 <= sign_dffe7[0:0];
// synopsys translate_off
initial
sign_dffe9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe9 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe9 <= sign_dffe8[0:0];
// synopsys translate_off
initial
sign_dffe10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe10 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe10 <= sign_dffe9[0:0];
// synopsys translate_off
initial
sign_dffe11 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe11 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe11 <= sign_dffe10[0:0];
// synopsys translate_off
initial
sign_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe12 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe12 <= sign_dffe11[0:0];
// synopsys translate_off
initial
sign_dffe13 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe13 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe13 <= sign_dffe12[0:0];
// synopsys translate_off
initial
sign_dffe14 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe14 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe14 <= sign_dffe13[0:0];
// synopsys translate_off
initial
sign_dffe15 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe15 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe15 <= sign_dffe14[0:0];
// synopsys translate_off
initial
sign_dffe16 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe16 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe16 <= sign_dffe15[0:0];
// synopsys translate_off
initial
sign_dffe17 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe17 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe17 <= sign_dffe16[0:0];
// synopsys translate_off
initial
sign_dffe18 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe18 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe18 <= sign_dffe17[0:0];
// synopsys translate_off
initial
sign_dffe19 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe19 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe19 <= sign_dffe18[0:0];
// synopsys translate_off
initial
sign_dffe20 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe20 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe20 <= sign_dffe19[0:0];
// synopsys translate_off
initial
sign_dffe21 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe21 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe21 <= sign_dffe20[0:0];
// synopsys translate_off
initial
sign_dffe22 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe22 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe22 <= sign_dffe21[0:0];
// synopsys translate_off
initial
sign_dffe23 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_dffe23 <= 1'b0;
else if (clk_en == 1'b1) sign_dffe23 <= sign_dffe22[0:0];
// synopsys translate_off
initial
table_one_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) table_one_dffe12 <= 61'b0;
else if (clk_en == 1'b1) table_one_dffe12 <= table_one_out;
// synopsys translate_off
initial
table_three_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) table_three_dffe12 <= 61'b0;
else if (clk_en == 1'b1) table_three_dffe12 <= table_three_out;
// synopsys translate_off
initial
table_two_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) table_two_dffe12 <= 61'b0;
else if (clk_en == 1'b1) table_two_dffe12 <= table_two_out;
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes0 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes0 <= tbl1_compare_wi;
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes1 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes1 <= tbl1_compare_dffe11_10_pipes0[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes2 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes2 <= tbl1_compare_dffe11_10_pipes1[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes3 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes3 <= tbl1_compare_dffe11_10_pipes2[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes4 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes4 <= tbl1_compare_dffe11_10_pipes3[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes5 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes5 <= tbl1_compare_dffe11_10_pipes4[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes6 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes6 <= tbl1_compare_dffe11_10_pipes5[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes7 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes7 <= tbl1_compare_dffe11_10_pipes6[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes8 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes8 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes8 <= tbl1_compare_dffe11_10_pipes7[0:0];
// synopsys translate_off
initial
tbl1_compare_dffe11_10_pipes9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) tbl1_compare_dffe11_10_pipes9 <= 1'b0;
else if (clk_en == 1'b1) tbl1_compare_dffe11_10_pipes9 <= tbl1_compare_dffe11_10_pipes8[0:0];
// synopsys translate_off
initial
x_fixed_dffe_0 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_0 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_0 <= x_fixed;
// synopsys translate_off
initial
x_fixed_dffe_1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_1 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_1 <= x_fixed_dffe_0;
// synopsys translate_off
initial
x_fixed_dffe_2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_2 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_2 <= x_fixed_dffe_1;
// synopsys translate_off
initial
x_fixed_dffe_3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_3 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_3 <= x_fixed_dffe_2;
// synopsys translate_off
initial
x_fixed_dffe_4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_4 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_4 <= x_fixed_dffe_3;
// synopsys translate_off
initial
x_fixed_dffe_5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_5 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_5 <= x_fixed_dffe_4;
// synopsys translate_off
initial
x_fixed_dffe_6 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) x_fixed_dffe_6 <= 70'b0;
else if (clk_en == 1'b1) x_fixed_dffe_6 <= x_fixed_dffe_5;
// synopsys translate_off
initial
xf_pl_dffe12 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xf_pl_dffe12 <= 60'b0;
else if (clk_en == 1'b1) xf_pl_dffe12 <= xf;
// synopsys translate_off
initial
xf_pre_2_dffe10 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xf_pre_2_dffe10 <= 70'b0;
else if (clk_en == 1'b1) xf_pre_2_dffe10 <= xf_pre_2_wi;
// synopsys translate_off
initial
xf_pre_dffe9 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xf_pre_dffe9 <= 70'b0;
else if (clk_en == 1'b1) xf_pre_dffe9 <= xf_pre_wi;
// synopsys translate_off
initial
xi_exp_value_dffe4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xi_exp_value_dffe4 <= 11'b0;
else if (clk_en == 1'b1) xi_exp_value_dffe4 <= xi_exp_value_wi;
// synopsys translate_off
initial
xi_ln2_prod_dffe7 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xi_ln2_prod_dffe7 <= 81'b0;
else if (clk_en == 1'b1) xi_ln2_prod_dffe7 <= xi_ln2_prod_wi;
// synopsys translate_off
initial
xi_prod_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) xi_prod_dffe3 <= 27'b0;
else if (clk_en == 1'b1) xi_prod_dffe3 <= xi_prod_wi;
lpm_add_sub exp_minus_bias
(
.cout(),
.dataa({1'b0, exp_w}),
.datab({1'b0, exp_bias}),
.overflow(),
.result(wire_exp_minus_bias_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_minus_bias.lpm_direction = "SUB",
exp_minus_bias.lpm_representation = "SIGNED",
exp_minus_bias.lpm_width = 12,
exp_minus_bias.lpm_type = "lpm_add_sub";
lpm_add_sub exp_value_add_bias
(
.aclr(aclr),
.cin(wire_cin_to_bias_dataout),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({1'b0, exp_value_b4_bias_dffe_18}),
.datab({1'b0, exp_bias[10:1], (~ extra_ln2_dffe_11)}),
.overflow(),
.result(wire_exp_value_add_bias_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_value_add_bias.lpm_direction = "ADD",
exp_value_add_bias.lpm_pipeline = 1,
exp_value_add_bias.lpm_representation = "SIGNED",
exp_value_add_bias.lpm_width = 12,
exp_value_add_bias.lpm_type = "lpm_add_sub";
lpm_add_sub exp_value_man_over
(
.cout(),
.dataa(wire_exp_value_add_bias_result),
.datab({{11{1'b0}}, man_overflow_wo}),
.overflow(),
.result(wire_exp_value_man_over_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
exp_value_man_over.lpm_direction = "ADD",
exp_value_man_over.lpm_representation = "SIGNED",
exp_value_man_over.lpm_width = 12,
exp_value_man_over.lpm_type = "lpm_add_sub";
lpm_add_sub invert_exp_value
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({11{1'b0}}),
.datab(exp_value[10:0]),
.overflow(),
.result(wire_invert_exp_value_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
invert_exp_value.lpm_direction = "SUB",
invert_exp_value.lpm_pipeline = 1,
invert_exp_value.lpm_representation = "SIGNED",
invert_exp_value.lpm_width = 11,
invert_exp_value.lpm_type = "lpm_add_sub";
lpm_add_sub man_round
(
.cout(),
.dataa(man_round_wo),
.datab({{51{1'b0}}, round_up_wo}),
.overflow(),
.result(wire_man_round_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
man_round.lpm_direction = "ADD",
man_round.lpm_representation = "SIGNED",
man_round.lpm_width = 52,
man_round.lpm_type = "lpm_add_sub";
lpm_add_sub one_minus_xf
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa({1'b1, {59{1'b0}}}),
.datab(wire_extra_ln2_muxa_dataout),
.overflow(),
.result(wire_one_minus_xf_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
one_minus_xf.lpm_direction = "SUB",
one_minus_xf.lpm_pipeline = 1,
one_minus_xf.lpm_representation = "SIGNED",
one_minus_xf.lpm_width = 60,
one_minus_xf.lpm_type = "lpm_add_sub";
lpm_add_sub x_fixed_minus_xiln2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(x_fixed_dffe_6),
.datab({1'b0, xi_ln2_prod_wo[80:12]}),
.overflow(),
.result(wire_x_fixed_minus_xiln2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
x_fixed_minus_xiln2.lpm_direction = "SUB",
x_fixed_minus_xiln2.lpm_pipeline = 1,
x_fixed_minus_xiln2.lpm_representation = "SIGNED",
x_fixed_minus_xiln2.lpm_width = 70,
x_fixed_minus_xiln2.lpm_type = "lpm_add_sub";
lpm_add_sub xf_minus_ln2
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(xf_pre[59:0]),
.datab({{2{1'b0}}, ln2_w[69:12]}),
.overflow(),
.result(wire_xf_minus_ln2_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
xf_minus_ln2.lpm_direction = "SUB",
xf_minus_ln2.lpm_pipeline = 1,
xf_minus_ln2.lpm_representation = "SIGNED",
xf_minus_ln2.lpm_width = 60,
xf_minus_ln2.lpm_type = "lpm_add_sub";
lpm_add_sub xi_add_one
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.cout(),
.dataa(xi_exp_value),
.datab(11'b00000000001),
.overflow(),
.result(wire_xi_add_one_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.add_sub(1'b1),
.cin()
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
xi_add_one.lpm_direction = "ADD",
xi_add_one.lpm_pipeline = 1,
xi_add_one.lpm_representation = "SIGNED",
xi_add_one.lpm_width = 11,
xi_add_one.lpm_type = "lpm_add_sub";
lpm_clshift rbarrel_shift
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.data(barrel_shifter_data),
.direction(exp_value_wo[11]),
.distance(barrel_shifter_distance),
.overflow(),
.result(wire_rbarrel_shift_result),
.underflow());
defparam
rbarrel_shift.lpm_pipeline = 2,
rbarrel_shift.lpm_shifttype = "LOGICAL",
rbarrel_shift.lpm_width = 70,
rbarrel_shift.lpm_widthdist = 7,
rbarrel_shift.lpm_type = "lpm_clshift";
lpm_compare distance_overflow_comp
(
.aeb(),
.agb(wire_distance_overflow_comp_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(wire_exp_value_to_compare_muxa_dataout),
.datab(distance_overflow_val_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
distance_overflow_comp.lpm_representation = "UNSIGNED",
distance_overflow_comp.lpm_width = 11,
distance_overflow_comp.lpm_type = "lpm_compare";
lpm_compare tbl1_compare
(
.aeb(),
.agb(),
.ageb(wire_tbl1_compare_ageb),
.alb(),
.aleb(),
.aneb(),
.dataa(xf[57:49]),
.datab(addr_val_more_than_one)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
tbl1_compare.lpm_representation = "UNSIGNED",
tbl1_compare.lpm_width = 9,
tbl1_compare.lpm_type = "lpm_compare";
lpm_compare underflow_compare
(
.aeb(),
.agb(wire_underflow_compare_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(wire_exp_value_to_compare_muxa_dataout),
.datab(underflow_compare_val_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
underflow_compare.lpm_representation = "UNSIGNED",
underflow_compare.lpm_width = 11,
underflow_compare.lpm_type = "lpm_compare";
lpm_mult xi_ln2_prod
(
.aclr(aclr),
.clken(clk_en),
.clock(clock),
.dataa(wire_exp_value_to_ln2a_dataout),
.datab(ln2_w),
.result(wire_xi_ln2_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
xi_ln2_prod.lpm_pipeline = 4,
xi_ln2_prod.lpm_representation = "UNSIGNED",
xi_ln2_prod.lpm_widtha = 11,
xi_ln2_prod.lpm_widthb = 70,
xi_ln2_prod.lpm_widthp = 81,
xi_ln2_prod.lpm_type = "lpm_mult",
xi_ln2_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mult xi_prod
(
.dataa(x_fixed[69:55]),
.datab(one_over_ln2_w),
.result(wire_xi_prod_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0),
.sum({1{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
xi_prod.lpm_representation = "UNSIGNED",
xi_prod.lpm_widtha = 15,
xi_prod.lpm_widthb = 12,
xi_prod.lpm_widthp = 27,
xi_prod.lpm_type = "lpm_mult",
xi_prod.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES";
lpm_mux table_one
(
.data(table_one_data),
.result(wire_table_one_result),
.sel(xf[57:49])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
table_one.lpm_size = 512,
table_one.lpm_width = 61,
table_one.lpm_widths = 9,
table_one.lpm_type = "lpm_mux";
lpm_mux table_three
(
.data(table_three_data),
.result(wire_table_three_result),
.sel(xf[39:31])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
table_three.lpm_size = 512,
table_three.lpm_width = 42,
table_three.lpm_widths = 9,
table_three.lpm_type = "lpm_mux";
lpm_mux table_two
(
.data(table_two_data),
.result(wire_table_two_result),
.sel(xf[48:40])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
table_two.lpm_size = 512,
table_two.lpm_width = 51,
table_two.lpm_widths = 9,
table_two.lpm_type = "lpm_mux";
assign
wire_cin_to_bias_dataout = shifted_value;
assign wire_exp_result_mux_prea_dataout = (((((barrel_shifter_underflow | overflow_w) | input_is_zero_wo) | nan_w) | positive_infinity) === 1'b1) ? exp_one : exp_result_w;
assign wire_exp_value_b4_biasa_dataout = (sign_dffe3[0:0] === 1'b1) ? exp_invert : xi_exp_value;
assign wire_exp_value_selecta_dataout = (exp_value_wo[11] === 1'b1) ? wire_invert_exp_value_result[6:0] : exp_value_wo[6:0];
assign wire_exp_value_to_compare_muxa_dataout = (exp_value_wo[11] === 1'b1) ? wire_invert_exp_value_result : exp_value_wo[10:0];
assign wire_exp_value_to_ln2a_dataout = (sign_dffe4[0:0] === 1'b1) ? wire_xi_add_one_result : xi_exp_value_wo;
assign wire_extra_ln2_muxa_dataout = (extra_ln2_dffe_0 === 1'b1) ? wire_xf_minus_ln2_result : xf_pre_wo[59:0];
assign wire_man_result_muxa_dataout = (((((overflow_w | underflow_w) | nan_w) | input_is_zero_wo) | input_is_infinity_wo) === 1'b1) ? {nan_w, {51{1'b0}}} : wire_man_round_result;
assign wire_xf_muxa_dataout = (sign_dffe12[0:0] === 1'b1) ? wire_one_minus_xf_result : xf_pre_2_wo[59:0];
assign
aclr = 1'b0,
addr_val_more_than_one = 9'b101100011,
barrel_shifter_data = {{11{1'b0}}, 1'b1, fraction_wo, {6{1'b0}}},
barrel_shifter_distance = wire_exp_value_selecta_dataout,
barrel_shifter_underflow = barrel_shifter_underflow_dffe2_23_pipes22[0:0],
barrel_shifter_underflow_wi = (wire_underflow_compare_agb & exp_value_wo[11]),
distance_overflow = distance_overflow_dffe2_23_pipes22[0:0],
distance_overflow_val_w = 11'b00000001001,
distance_overflow_wi = (wire_distance_overflow_comp_agb & (~ exp_value_wo[11])),
exp_bias = 11'b01111111111,
exp_bias_all_ones_w = {11{1'b1}},
exp_data_all_one_w = {(data[62] & exp_data_all_one_w[9]), (data[61] & exp_data_all_one_w[8]), (data[60] & exp_data_all_one_w[7]), (data[59] & exp_data_all_one_w[6]), (data[58] & exp_data_all_one_w[5]), (data[57] & exp_data_all_one_w[4]), (data[56] & exp_data_all_one_w[3]), (data[55] & exp_data_all_one_w[2]), (data[54] & exp_data_all_one_w[1]), (data[53] & exp_data_all_one_w[0]), data[52]},
exp_data_not_zero_w = {(data[62] | exp_data_not_zero_w[9]), (data[61] | exp_data_not_zero_w[8]), (data[60] | exp_data_not_zero_w[7]), (data[59] | exp_data_not_zero_w[6]), (data[58] | exp_data_not_zero_w[5]), (data[57] | exp_data_not_zero_w[4]), (data[56] | exp_data_not_zero_w[3]), (data[55] | exp_data_not_zero_w[2]), (data[54] | exp_data_not_zero_w[1]), (data[53] | exp_data_not_zero_w[0]), data[52]},
exp_invert = (xi_exp_value ^ exp_bias_all_ones_w),
exp_one = {((overflow_w | nan_w) | positive_infinity), {10{1'b1}}},
exp_out_all_one_w = {(exp_result_w[10] & exp_out_all_one_w[9]), (exp_result_w[9] & exp_out_all_one_w[8]), (exp_result_w[8] & exp_out_all_one_w[7]), (exp_result_w[7] & exp_out_all_one_w[6]), (exp_result_w[6] & exp_out_all_one_w[5]), (exp_result_w[5] & exp_out_all_one_w[4]), (exp_result_w[4] & exp_out_all_one_w[3]), (exp_result_w[3] & exp_out_all_one_w[2]), (exp_result_w[2] & exp_out_all_one_w[1]), (exp_result_w[1] & exp_out_all_one_w[0]), exp_result_w[0]},
exp_out_not_zero_w = {(exp_result_w[10] | exp_out_not_zero_w[9]), (exp_result_w[9] | exp_out_not_zero_w[8]), (exp_result_w[8] | exp_out_not_zero_w[7]), (exp_result_w[7] | exp_out_not_zero_w[6]), (exp_result_w[6] | exp_out_not_zero_w[5]), (exp_result_w[5] | exp_out_not_zero_w[4]), (exp_result_w[4] | exp_out_not_zero_w[3]), (exp_result_w[3] | exp_out_not_zero_w[2]), (exp_result_w[2] | exp_out_not_zero_w[1]), (exp_result_w[1] | exp_out_not_zero_w[0]), exp_result_w[0]},
exp_result_out = (wire_exp_result_mux_prea_dataout & {11{(~ ((underflow_w & (~ barrel_shifter_underflow)) | negative_infinity))}}),
exp_result_w = wire_exp_value_man_over_result[10:0],
exp_value = wire_exp_minus_bias_result,
exp_value_wi = exp_value,
exp_value_wo = exp_value_dffe1,
exp_w = data[62:52],
extra_ln2 = ((~ xf_pre[69]) & sign_dffe10[0:0]),
fraction = {data[51:0]},
fraction_wi = fraction,
fraction_wo = fraction_dffe1,
gnd_w = 1'b0,
guard_bit = man_prod_result[64],
input_is_infinity_wi = (exp_data_all_one_w[10] & (~ man_data_not_zero_w[51])),
input_is_infinity_wo = input_is_infinity_24_pipes23[0:0],
input_is_nan_wi = (exp_data_all_one_w[10] & man_data_not_zero_w[51]),
input_is_nan_wo = input_is_nan_24_pipes23[0:0],
input_is_zero_wi = (~ exp_data_not_zero_w[10]),
input_is_zero_wo = input_is_zero_24_pipes23[0:0],
ln2_w = 70'b1011000101110010000101111111011111010001110011110111100110101011110010,
man_data_not_zero_w = {(data[51] | man_data_not_zero_w[50]), (data[50] | man_data_not_zero_w[49]), (data[49] | man_data_not_zero_w[48]), (data[48] | man_data_not_zero_w[47]), (data[47] | man_data_not_zero_w[46]), (data[46] | man_data_not_zero_w[45]), (data[45] | man_data_not_zero_w[44]), (data[44] | man_data_not_zero_w[43]), (data[43] | man_data_not_zero_w[42]), (data[42] | man_data_not_zero_w[41]), (data[41] | man_data_not_zero_w[40]), (data[40] | man_data_not_zero_w[39]), (data[39] | man_data_not_zero_w[38]), (data[38] | man_data_not_zero_w[37]), (data[37] | man_data_not_zero_w[36]), (data[36] | man_data_not_zero_w[35]), (data[35] | man_data_not_zero_w[34]), (data[34] | man_data_not_zero_w[33]), (data[33] | man_data_not_zero_w[32]), (data[32] | man_data_not_zero_w[31]), (data[31] | man_data_not_zero_w[30]), (data[30] | man_data_not_zero_w[29]), (data[29] | man_data_not_zero_w[28]), (data[28] | man_data_not_zero_w[27]), (data[27] | man_data_not_zero_w[26]), (data[26] | man_data_not_zero_w[25]), (data[25] | man_data_not_zero_w[24]), (data[24] | man_data_not_zero_w[23]), (data[23] | man_data_not_zero_w[22]), (data[22] | man_data_not_zero_w[21]), (data[21] | man_data_not_zero_w[20]), (data[20] | man_data_not_zero_w[19]), (data[19] | man_data_not_zero_w[18]), (data[18] | man_data_not_zero_w[17]), (data[17] | man_data_not_zero_w[16]), (data[16] | man_data_not_zero_w[15]), (data[15] | man_data_not_zero_w[14]), (data[14] | man_data_not_zero_w[13]), (data[13] | man_data_not_zero_w[12]), (data[12] | man_data_not_zero_w[11]), (data[11] | man_data_not_zero_w[10]), (data[10] | man_data_not_zero_w[9]), (data[9] | man_data_not_zero_w[8]), (data[8] | man_data_not_zero_w[7]), (data[7] | man_data_not_zero_w[6]), (data[6] | man_data_not_zero_w[5]), (data[5] | man_data_not_zero_w[4]), (data[4] | man_data_not_zero_w[3]), (data[3] | man_data_not_zero_w[2]), (data[2] | man_data_not_zero_w[1]), (data[1] | man_data_not_zero_w[0]), data[0]},
man_overflow = (round_up & man_result_all_ones[51]),
man_overflow_wi = man_overflow,
man_overflow_wo = man_overflow_dffe15,
man_prod_result = ((man_prod_shifted & {120{man_prod_wo[117]}}) | (man_prod_wire & {120{(~ man_prod_wo[117])}})),
man_prod_shifted = {gnd_w, man_prod_wo[119:1]},
man_prod_wi = wire_man_prod_result,
man_prod_wire = man_prod_wo,
man_prod_wo = man_prod_wi,
man_result_all_ones = {(man_round_wi[51] & man_result_all_ones[50]), (man_round_wi[50] & man_result_all_ones[49]), (man_round_wi[49] & man_result_all_ones[48]), (man_round_wi[48] & man_result_all_ones[47]), (man_round_wi[47] & man_result_all_ones[46]), (man_round_wi[46] & man_result_all_ones[45]), (man_round_wi[45] & man_result_all_ones[44]), (man_round_wi[44] & man_result_all_ones[43]), (man_round_wi[43] & man_result_all_ones[42]), (man_round_wi[42] & man_result_all_ones[41]), (man_round_wi[41] & man_result_all_ones[40]), (man_round_wi[40] & man_result_all_ones[39]), (man_round_wi[39] & man_result_all_ones[38]), (man_round_wi[38] & man_result_all_ones[37]), (man_round_wi[37] & man_result_all_ones[36]), (man_round_wi[36] & man_result_all_ones[35]), (man_round_wi[35] & man_result_all_ones[34]), (man_round_wi[34] & man_result_all_ones[33]), (man_round_wi[33] & man_result_all_ones[32]), (man_round_wi[32] & man_result_all_ones[31]), (man_round_wi[31] & man_result_all_ones[30]), (man_round_wi[30] & man_result_all_ones[29]), (man_round_wi[29] & man_result_all_ones[28]), (man_round_wi[28] & man_result_all_ones[27]), (man_round_wi[27] & man_result_all_ones[26]), (man_round_wi[26] & man_result_all_ones[25]), (man_round_wi[25] & man_result_all_ones[24]), (man_round_wi[24] & man_result_all_ones[23]), (man_round_wi[23] & man_result_all_ones[22]), (man_round_wi[22] & man_result_all_ones[21]), (man_round_wi[21] & man_result_all_ones[20]), (man_round_wi[20] & man_result_all_ones[19]), (man_round_wi[19] & man_result_all_ones[18]), (man_round_wi[18] & man_result_all_ones[17]), (man_round_wi[17] & man_result_all_ones[16]), (man_round_wi[16] & man_result_all_ones[15]), (man_round_wi[15] & man_result_all_ones[14]), (man_round_wi[14] & man_result_all_ones[13]), (man_round_wi[13] & man_result_all_ones[12]), (man_round_wi[12] & man_result_all_ones[11]), (man_round_wi[11] & man_result_all_ones[10]), (man_round_wi[10] & man_result_all_ones[9]), (man_round_wi[9] & man_result_all_ones[8]), (man_round_wi[8] & man_result_all_ones[7]), (man_round_wi[7]
& man_result_all_ones[6]), (man_round_wi[6] & man_result_all_ones[5]), (man_round_wi[5] & man_result_all_ones[4]), (man_round_wi[4] & man_result_all_ones[3]), (man_round_wi[3] & man_result_all_ones[2]), (man_round_wi[2] & man_result_all_ones[1]), (man_round_wi[1] & man_result_all_ones[0]), man_round_wi[0]},
man_result_w = wire_man_result_muxa_dataout,
man_round_wi = man_prod_result[115:64],
man_round_wo = man_round_dffe15,
nan_w = input_is_nan_wo,
negative_infinity = (sign_dffe23[0:0] & input_is_infinity_wo),
one_over_ln2_w = 12'b101110001010,
overflow_w = ((((~ sign_dffe23[0:0]) & (((distance_overflow | wire_exp_value_add_bias_result[11]) | exp_out_all_one_w[10]) | wire_exp_value_man_over_result[11])) & (~ underflow_w)) & (~ input_is_nan_wo)),
positive_infinity = ((~ sign_dffe23[0:0]) & input_is_infinity_wo),
result = {1'b0, result_pipe_wo},
result_pipe_wi = {exp_result_out, man_result_w},
result_pipe_wo = result_pipe_dffe16,
result_underflow_w = ((~ exp_out_not_zero_w[10]) & (((~ wire_exp_value_man_over_result[11]) & (~ sign_dffe23[0:0])) | sign_dffe23[0:0])),
round_bit = man_prod_result[63],
round_up = (round_bit & (guard_bit | sticky_bits[4])),
round_up_wi = round_up,
round_up_wo = round_up_dffe15,
shifted_value = (tbl1_compare_wo | man_prod_wo[117]),
sign_w = data[63],
sticky_bits = {(man_prod_result[58] | sticky_bits[3]), (man_prod_result[59] | sticky_bits[2]), (man_prod_result[60] | sticky_bits[1]), (man_prod_result[61] | sticky_bits[0]), man_prod_result[62]},
table_one_data = {61'b1010110110100001011011011110100111100001100100011101100101101, 61'b1010110101001010101100101110001101111100110010100110001010000, 61'b1010110011110100001000110010111111000101101000101101100100011, 61'b1010110010011101101111101011100100011000001011011101101111110, 61'b1010110001000111100001010110100111011011010011010100110010000, 61'b1010101111110001011101110010110010000000101011001110100010011, 61'b1010101110011011100100111110101110000100101111001110011011010, 61'b1010101101000101110110111001000101101110101011001001010110101, 61'b1010101011110000010011100000100011010000011001001111110101011, 61'b1010101010011010111010110011110001000110100000111000010000110, 61'b1010101001000101101100110001011001111000010101001001010111101, 61'b1010100111110000101001011000001000010111110011100100110101001, 61'b1010100110011011110000100110100111100001100010110010000011011, 61'b1010100101000111000010011011100010011100110001001001000111010, 61'b1010100011110010011110110101100100011011010011011101111000000, 61'b1010100010011110000101110011011000111001100011101011010001100, 61'b1010100001001001110111010011101011011110011111011110101111101, 61'b1010011111110101110011010101000111111011100111000011110110010, 61'b1010011110100001111001110110011010001100111011110000000010001, 61'b1010011101001110001010110110001110011000111110101110100101000, 61'b1010011011111010100110010011010000110000101111101100101100101, 61'b1010011010100111001100001100001101101111101011100101110010110, 61'b1010011001010011111100011111110001111011101011001111111001110, 61'b1010011000000000110111001100101010000101000010001000010001011, 61'b1010010110101101111100010001100011000110011101000000001000000, 61'b1010010101011011001011101101001010000101000000101001100100111, 61'b1010010100001000100101011110001100010000001000100100101101000, 61'b1010010010110110001001100011010111000001100101101100110011001, 61'b1010010001100011110111111011010111111101011101000101110001000, 61'b1010010000010001110000100100111100110010000110101001101011101, 61'b1010001110111111110011011110110011011000001011110110100001111
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, 61'b1100100101011111010011001101000001001101111101111111110110111, 61'b1100100011111010101101100101000110011101111101001111100100111, 61'b1100100010010110010100100001000110011100100100100101010100111, 61'b1100100000110010000111111111011100110000101111111000101101101, 61'b1100011111001110000111111110100101001101111101010111101101011, 61'b1100011101101010010100011100111011110100001100000010011011101, 61'b1100011100000110101101011000111100101111111010000111001010100, 61'b1100011010100011010010110001000100011010000011011110100010100, 61'b1100011001000000000100100011101111011000000000000111111011100, 61'b1100010111011101000010101111011010011011100010100110000010001, 61'b1100010101111010001101010010100010100010110110011011101010000, 61'b1100010100010111100100001011100100111000011110101000101011001, 61'b1100010010110101000111011000111110110011010100000111001101001, 61'b1100010001010010110110111001001101110110100100001000111101111, 61'b1100001111110000110010101010101111110001101110110100110100010, 61'b1100001110001110111010101100000010100000100101100100100000110, 61'b1100001100101101001110111011100100001011001001100010101000001, 61'b1100001011001011101111010111110011000101101010001000101011111, 61'b1100001001101010011011111111001101110000100011011101011110101, 61'b1100001000001001010100110000010010111000011100110011100100010, 61'b1100000110101000011001101001100001010110000111000111111110110, 61'b1100000101000111101010101001011000001110011011100001000110111, 61'b1100000011100111000111101110010110110010011001101101110001000, 61'b1100000010000110110000110110111100011111000110100100011110010, 61'b1100000000100110100110000001101000111101101010100010111001011, 61'b1011111111000110100111001100111100000011010000001101100000000, 61'b1011111101100110110100010111010101110001000010101111010111111, 61'b1011111100000111001101011111010110010100001100011010001111111, 61'b1011111010100111110010100011011110000101110101000110101101010, 61'b1011111001001000100011100010001101101011000000110100100100101, 61'b1011110111101001100000011010000101110100101110001011011111011
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, 61'b1011001001100111111010111010101000101010011101110011110111111, 61'b1011001000001110110011011111110110011011110011101001100000101, 61'b1011000110110101110111001101010011000001100100101100001001101, 61'b1011000101011101000110000001100101011111011110010000111110000, 61'b1011000100000100011111111011010101000100010100100011000010100, 61'b1011000010101100000100111001001001001010000001001010100011011, 61'b1011000001010011110100111001101001010101100001110100001110101, 61'b1010111111111011101111111011011101010110110110111000111001001, 61'b1010111110100011110101111101001101001001000010000101001110101, 61'b1010111101001100000110111101100000110010000101000001101100011, 61'b1010111011110100100010111011000000100010111111111010100111011, 61'b1010111010011101001001110100010100110111110000001000011101101, 61'b1010111001000101111011101000000110010111001110111000010001111, 61'b1010110111101110111000010100111101110011001111110100010010011, 61'b1010110110010111111111111001100100001000011111101100101010111, 61'b1010110101000001010010010100100010011110100011000000100001001, 61'b1010110011101010101111100100100010000111110100100110111100111, 61'b1010110010010100010111101000001100100001100100011000011001110, 61'b1010110000111110001010011110001011010011110101111000000100111, 61'b1010101111101000001000000101001000010001011110111101100100110, 61'b1010101110010010010000011011101101011000000110011110101100001, 61'b1010101100111100100011100000100100110000000010111001010111101, 61'b1010101011100111000001010010011000101100011000111101110110010, 61'b1010101010010001101001101111110011101010111010011000111100000, 61'b1010101000111100011100110111100000010100000100011110100000010, 61'b1010100111100111011010101000001001011010111110110100000101101, 61'b1010100110010010100011000000011001111101011001111011101101100, 61'b1010100100111101110101111110111101000011101101111110110101110, 61'b1010100011101001010011100010011110000000111001011001100001000, 61'b1010100010010100111011101001101000010010011111100101101001011, 61'b1010100001000000101110010011000111100000100111100110011110101
, 61'b1010011111101100101011011101100111011101111010110100001101110, 61'b1010011110011000110011000111110100000111100011100111110011110, 61'b1010011101000101000101010000011001100101001100000110111010111, 61'b1010011011110001100001110110000100001000111100110000000010011, 61'b1010011010011110001000110111100000001111011011000110110000011, 61'b1010011001001010111010010011011010011111101000100000001110100, 61'b1010010111110111110110001000011111101011000000101111110001001, 61'b1010010110100100111100010101011100101101011000110011101000110, 61'b1010010101010010001100111000111110101100111101100001111101011, 61'b1010010011111111100111110001110010111010010010010101110101100, 61'b1010010010101101001100111110100110110000001111111100100101110, 61'b1010010001011010111100011110000111110100000011000011001100111, 61'b1010010000001000110110001111000011110101001011000011110111110, 61'b1010001110110110111010010000001000101101011000110011110001101, 61'b1010001101100101001000100000000100100000101101010000111101110, 61'b1010001100010011100000111101100101011101011000010000011011011, 61'b1010001011000010000011100111011001111011110111001100010011110, 61'b1010001001110000110000011100010000011110110011110010010011000, 61'b1010001000011111100111011010110111110011000010110010001010100, 61'b1010000111001110101000100001111110101111100010101100011101110, 61'b1010000101111101110011110000010100010101011010100001011001001, 61'b1010000100101101001001000100100111101111111000011111110011110, 61'b1010000011011100101000011101101000010100010000110100011001101, 61'b1010000010001100010001111010000101100001111100011001000001111, 61'b1010000000111100000101011000101111000010010111100100001101100, 61'b1001111111101100000010111000010100101001000000111000110001011, 61'b1001111110011100001010010111100110010011010111110101101001001, 61'b1001111101001100011011110101010100001000111011100101110101010, 61'b1001111011111100110111010000001110011011001001110000100001111, 61'b1001111010101101011100100111000101100101011101001001011001000, 61'b1001111001011110001011111000101010001101001100100000111101011
, 61'b1001111000001111000101000011101101000001101001010101001111111, 61'b1001110111000000001000000110111110111011111110100010011111010, 61'b1001110101110001010101000001010000111111001111010100000000100, 61'b1001110100100010101011110001010100011000010101110101010010111, 61'b1001110011010100001100010101111010011110000010000011001011111, 61'b1001110010000101110110101101110100110000111000011101001110101, 61'b1001110000110111101010110111110100111011010000110111001100010, 61'b1001101111101001101000110010101100110001010101001010101110000, 61'b1001101110011011110000011101001110010001000000001001001001111, 61'b1001101101001110000001110110001011100001111100001101100000001, 61'b1001101100000000011100111100010110110101100010001110100011001, 61'b1001101010110011000001101110100010100110111000010001001000111, 61'b1001101001100101110000001011100001011010110000011010100101101, 61'b1001101000011000101000010010000101111111100111100011010001001, 61'b1001100111001011101010000001000011001101100100001001010101000, 61'b1001100101111110110101010111001100000110010101000011100100101, 61'b1001100100110010001010010011010011110101010000010100011111001, 61'b1001100011100101101000110100001101101111010001111101011010011, 61'b1001100010011001010000111000101101010010111010110001111000010, 61'b1001100001001101000010011111100110001000001111001011000101010, 61'b1001100000000000111101100111101100000000110101111011100000000, 61'b1001011110110101000010001111110010110111110111000010101011100, 61'b1001011101101001010000010110101110110001111010100001001001101, 61'b1001011100011101100111111011010011111101000111001100100000100, 61'b1001011011010010001000111100010110110001000001100011100111110, 61'b1001011010000110110011011000101011101110101010100011000000111, 61'b1001011000111011100111001111000111100000011110011001010111101, 61'b1001010111110000100100011110011110111010010011011100001100110, 61'b1001010110100101101011000101100110111001011000111100101010000, 61'b1001010101011010111011000011010100100100010101111100011110111, 61'b1001010100010000010100010110011101001011001000000011000111101
, 61'b1001010011000101110110111101110110000111000010010010111101011, 61'b1001010001111011100010111000010100111010101011111110101110101, 61'b1001010000110001011000000100101111010001111111011111000010111, 61'b1001001111100111010110100001111011000010001001001000000101111, 61'b1001001110011101011110001110101110001001100101111111011100111, 61'b1001001101010011101111001001111110110000000010110010000101011, 61'b1001001100001010001001010010100011000110011010101010011100100, 61'b1001001011000000101100100111010001100110110110000110110000010, 61'b1001001001110111011001000111000000110100101001101111011001001, 61'b1001001000101110001110110000100111011100010101001101011110010, 61'b1001000111100101001101100010111100010011100010000001100000111, 61'b1001000110011100010101011100110110011001000010011010010010111, 61'b1001000101010011100110011101001100110100110000001011110101000, 61'b1001000100001011000000100010110110110111101011100110011111001, 61'b1001000011000010100011101100101011111011111010001110010001001, 61'b1001000001111010001111111001100011100100100101110010001100100, 61'b1001000000110010000101001000010101011101111011000011111000101, 61'b1000111111101010000011010111111001011101001000101111001101110, 61'b1000111110100010001010100111000111100000011110010010001011000, 61'b1000111101011010011010110100110111101111001010110100110100011, 61'b1000111100010010110100000000000010011001011100000001011001110, 61'b1000111011001011010110000111011111111000011100111100100111101, 61'b1000111010000100000001001010001000101110010100111101111111110, 61'b1000111000111100110101000110110101100110000110101000011011110, 61'b1000110111110101110001111100011111010011101110100010110111100, 61'b1000110110101110110111101001111110110100000010010001000110000, 61'b1000110101101000000110001110001101001100101111001100101101001, 61'b1000110100100001011101101000000011101100011001011110001100001, 61'b1000110011011010111101110110011011101010011010110110001010001, 61'b1000110010010100100110111000001110100111000001100110101101000, 61'b1000110001001110011000101100010110001011001111011100111010010
, 61'b1000110000001000010011010001101100001000111000011010011111011, 61'b1000101111000010010110100111001010011010100001101111100100011, 61'b1000101101111100100010101011101011000011100000110100100101111, 61'b1000101100110110110111011110001000001111111010000100011000011, 61'b1000101011110001010100111101011100010100011111110110010100110, 61'b1000101010101011111011001000100001101110110001011000101100111, 61'b1000101001100110101001111110010011000100111001101011001000101, 61'b1000101000100001100001011101101011000101101110011001001100110, 61'b1000100111011100100001100101100100101000101110110101001001100, 61'b1000100110010111101010010100111010101110000010110010110001110, 61'b1000100101010010111011101010101000011110011001100010011011101, 61'b1000100100001110010101100101101001001011001000101100001000111, 61'b1000100011001001111000000100111000001110001011001010111000100, 61'b1000100010000101100011000111010001001010000000001000000000010, 61'b1000100001000001010110101011101111101001101001110110101111101, 61'b1000011111111101010010110001001111100000101100101111111010100, 61'b1000011110111001010111010110101100101011001110001101101101001, 61'b1000011101110101100100011011000011001101110011100111100111100, 61'b1000011100110001111001111101001111010101100001001110100010111, 61'b1000011011101110010111111100001101010111111001001000111101111, 61'b1000011010101010111110010110111001110010111010001111010010110, 61'b1000011001100111101101001100010001001100111111001000010101001, 61'b1000011000100100100100011011010000010100111101000101111000010, 61'b1000010111100001100100000010110100000010000011000001011110001, 61'b1000010110011110101100000001111001010011111000011001001110011, 61'b1000010101011011111100010111011101010010011100001100110110001, 61'b1000010100011001010101000010011101001110000011111010110000001, 61'b1000010011010110110110000001110110011111011010011101010100101, 61'b1000010010010100011111010100100110100111011111001000010010011, 61'b1000010001010010010000111001101011001111100100100110001111100, 61'b1000010000010000001010110000000010001001001111110110010011000
, 61'b1000001111001110001100110110101001001110010111001001110110001, 61'b1000001110001100010111001100011110100001000001000010011101111, 61'b1000001101001010101001110000100000001011100011001111111110000, 61'b1000001100001001000100100001101100100000100001101110100010100, 61'b1000001011000111100111011111000001111010101101100101000010101, 61'b1000001010000110010010100111011110111101000100000011011011100, 61'b1000001001000101000101111010000010010010101101100001010010111, 61'b1000001000000100000001010101101010101110111100011100100010111, 61'b1000000111000011000100111001010111001101001100011000001100101, 61'b1000000110000010010000100100000110110001000000111011010100000, 61'b1000000101000001100100010100111000100110000100110000000011001, 61'b1000000100000001000000001010101100000000001000100010110110000, 61'b1000000011000000100100000100100000011011000010000001101110100, 61'b1000000010000000010000000001010101011010101010111011101111101, 61'b1000000001000000000100000000001010101011000000000000100010001, 61'b1000000000000000000000000000000000000000000000000000000000000},
table_one_out = wire_table_one_result,
table_one_out_pl = table_one_dffe12,
table_three_data = {42'b111111111000000000011111111000000000101010, 42'b111111110000000000011111110000000010001010, 42'b111111101000000000011111101000000100101010, 42'b111111100000000000011111100000001000001010, 42'b111111011000000000011111011000001100101010, 42'b111111010000000000011111010000010010001010, 42'b111111001000000000011111001000011000101010, 42'b111111000000000000011111000000100000001010, 42'b111110111000000000011110111000101000101010, 42'b111110110000000000011110110000110010001010, 42'b111110101000000000011110101000111100101001, 42'b111110100000000000011110100001001000001001, 42'b111110011000000000011110011001010100101001, 42'b111110010000000000011110010001100010001001, 42'b111110001000000000011110001001110000101001, 42'b111110000000000000011110000010000000001001, 42'b111101111000000000011101111010010000101001, 42'b111101110000000000011101110010100010001001, 42'b111101101000000000011101101010110100101001, 42'b111101100000000000011101100011001000001001, 42'b111101011000000000011101011011011100101001, 42'b111101010000000000011101010011110010001001, 42'b111101001000000000011101001100001000101001, 42'b111101000000000000011101000100100000001001, 42'b111100111000000000011100111100111000101001, 42'b111100110000000000011100110101010010001001, 42'b111100101000000000011100101101101100101001, 42'b111100100000000000011100100110001000001001, 42'b111100011000000000011100011110100100101000, 42'b111100010000000000011100010111000010001000, 42'b111100001000000000011100001111100000101000, 42'b111100000000000000011100001000000000001000, 42'b111011111000000000011100000000100000101000, 42'b111011110000000000011011111001000010001000, 42'b111011101000000000011011110001100100101000, 42'b111011100000000000011011101010001000001000, 42'b111011011000000000011011100010101100101000, 42'b111011010000000000011011011011010010001000, 42'b111011001000000000011011010011111000101000, 42'b111011000000000000011011001100100000001000, 42'b111010111000000000011011000101001000101000, 42'b111010110000000000011010111101110010001000, 42'b111010101000000000011010110110011100101000
, 42'b111010100000000000011010101111001000001000, 42'b111010011000000000011010100111110100101000, 42'b111010010000000000011010100000100010001000, 42'b111010001000000000011010011001010000100111, 42'b111010000000000000011010010010000000000111, 42'b111001111000000000011010001010110000100111, 42'b111001110000000000011010000011100010000111, 42'b111001101000000000011001111100010100100111, 42'b111001100000000000011001110101001000000111, 42'b111001011000000000011001101101111100100111, 42'b111001010000000000011001100110110010000111, 42'b111001001000000000011001011111101000100111, 42'b111001000000000000011001011000100000000111, 42'b111000111000000000011001010001011000100111, 42'b111000110000000000011001001010010010000111, 42'b111000101000000000011001000011001100100111, 42'b111000100000000000011000111100001000000111, 42'b111000011000000000011000110101000100100111, 42'b111000010000000000011000101110000010000111, 42'b111000001000000000011000100111000000100111, 42'b111000000000000000011000100000000000000111, 42'b110111111000000000011000011001000000100111, 42'b110111110000000000011000010010000010000111, 42'b110111101000000000011000001011000100100111, 42'b110111100000000000011000000100001000000110, 42'b110111011000000000010111111101001100100110, 42'b110111010000000000010111110110010010000110, 42'b110111001000000000010111101111011000100110, 42'b110111000000000000010111101000100000000110, 42'b110110111000000000010111100001101000100110, 42'b110110110000000000010111011010110010000110, 42'b110110101000000000010111010011111100100110, 42'b110110100000000000010111001101001000000110, 42'b110110011000000000010111000110010100100110, 42'b110110010000000000010110111111100010000110, 42'b110110001000000000010110111000110000100110, 42'b110110000000000000010110110010000000000110, 42'b110101111000000000010110101011010000100110, 42'b110101110000000000010110100100100010000110, 42'b110101101000000000010110011101110100100110, 42'b110101100000000000010110010111001000000110, 42'b110101011000000000010110010000011100100110, 42'b110101010000000000010110001001110010000110
, 42'b110101001000000000010110000011001000100110, 42'b110101000000000000010101111100100000000110, 42'b110100111000000000010101110101111000100110, 42'b110100110000000000010101101111010010000101, 42'b110100101000000000010101101000101100100101, 42'b110100100000000000010101100010001000000101, 42'b110100011000000000010101011011100100100101, 42'b110100010000000000010101010101000010000101, 42'b110100001000000000010101001110100000100101, 42'b110100000000000000010101001000000000000101, 42'b110011111000000000010101000001100000100101, 42'b110011110000000000010100111011000010000101, 42'b110011101000000000010100110100100100100101, 42'b110011100000000000010100101110001000000101, 42'b110011011000000000010100100111101100100101, 42'b110011010000000000010100100001010010000101, 42'b110011001000000000010100011010111000100101, 42'b110011000000000000010100010100100000000101, 42'b110010111000000000010100001110001000100101, 42'b110010110000000000010100000111110010000101, 42'b110010101000000000010100000001011100100101, 42'b110010100000000000010011111011001000000101, 42'b110010011000000000010011110100110100100101, 42'b110010010000000000010011101110100010000101, 42'b110010001000000000010011101000010000100101, 42'b110010000000000000010011100010000000000101, 42'b110001111000000000010011011011110000100101, 42'b110001110000000000010011010101100010000101, 42'b110001101000000000010011001111010100100100, 42'b110001100000000000010011001001001000000100, 42'b110001011000000000010011000010111100100100, 42'b110001010000000000010010111100110010000100, 42'b110001001000000000010010110110101000100100, 42'b110001000000000000010010110000100000000100, 42'b110000111000000000010010101010011000100100, 42'b110000110000000000010010100100010010000100, 42'b110000101000000000010010011110001100100100, 42'b110000100000000000010010011000001000000100, 42'b110000011000000000010010010010000100100100, 42'b110000010000000000010010001100000010000100, 42'b110000001000000000010010000110000000100100, 42'b110000000000000000010010000000000000000100, 42'b101111111000000000010001111010000000100100
, 42'b101111110000000000010001110100000010000100, 42'b101111101000000000010001101110000100100100, 42'b101111100000000000010001101000001000000100, 42'b101111011000000000010001100010001100100100, 42'b101111010000000000010001011100010010000100, 42'b101111001000000000010001010110011000100100, 42'b101111000000000000010001010000100000000100, 42'b101110111000000000010001001010101000100100, 42'b101110110000000000010001000100110010000100, 42'b101110101000000000010000111110111100100100, 42'b101110100000000000010000111001001000000100, 42'b101110011000000000010000110011010100100100, 42'b101110010000000000010000101101100010000100, 42'b101110001000000000010000100111110000100011, 42'b101110000000000000010000100010000000000011, 42'b101101111000000000010000011100010000100011, 42'b101101110000000000010000010110100010000011, 42'b101101101000000000010000010000110100100011, 42'b101101100000000000010000001011001000000011, 42'b101101011000000000010000000101011100100011, 42'b101101010000000000001111111111110010000011, 42'b101101001000000000001111111010001000100011, 42'b101101000000000000001111110100100000000011, 42'b101100111000000000001111101110111000100011, 42'b101100110000000000001111101001010010000011, 42'b101100101000000000001111100011101100100011, 42'b101100100000000000001111011110001000000011, 42'b101100011000000000001111011000100100100011, 42'b101100010000000000001111010011000010000011, 42'b101100001000000000001111001101100000100011, 42'b101100000000000000001111001000000000000011, 42'b101011111000000000001111000010100000100011, 42'b101011110000000000001110111101000010000011, 42'b101011101000000000001110110111100100100011, 42'b101011100000000000001110110010001000000011, 42'b101011011000000000001110101100101100100011, 42'b101011010000000000001110100111010010000011, 42'b101011001000000000001110100001111000100011, 42'b101011000000000000001110011100100000000011, 42'b101010111000000000001110010111001000100011, 42'b101010110000000000001110010001110010000011, 42'b101010101000000000001110001100011100100011, 42'b101010100000000000001110000111001000000011
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, 42'b100101000000000000001010101100100000000010, 42'b100100111000000000001010100111111000100010, 42'b100100110000000000001010100011010010000010, 42'b100100101000000000001010011110101100100001, 42'b100100100000000000001010011010001000000001, 42'b100100011000000000001010010101100100100001, 42'b100100010000000000001010010001000010000001, 42'b100100001000000000001010001100100000100001, 42'b100100000000000000001010001000000000000001, 42'b100011111000000000001010000011100000100001, 42'b100011110000000000001001111111000010000001, 42'b100011101000000000001001111010100100100001, 42'b100011100000000000001001110110001000000001, 42'b100011011000000000001001110001101100100001, 42'b100011010000000000001001101101010010000001, 42'b100011001000000000001001101000111000100001, 42'b100011000000000000001001100100100000000001, 42'b100010111000000000001001100000001000100001, 42'b100010110000000000001001011011110010000001, 42'b100010101000000000001001010111011100100001, 42'b100010100000000000001001010011001000000001, 42'b100010011000000000001001001110110100100001, 42'b100010010000000000001001001010100010000001, 42'b100010001000000000001001000110010000100001, 42'b100010000000000000001001000010000000000001, 42'b100001111000000000001000111101110000100001, 42'b100001110000000000001000111001100010000001, 42'b100001101000000000001000110101010100100001, 42'b100001100000000000001000110001001000000001, 42'b100001011000000000001000101100111100100001, 42'b100001010000000000001000101000110010000001, 42'b100001001000000000001000100100101000100001, 42'b100001000000000000001000100000100000000001, 42'b100000111000000000001000011100011000100001, 42'b100000110000000000001000011000010010000001, 42'b100000101000000000001000010100001100100001, 42'b100000100000000000001000010000001000000001, 42'b100000011000000000001000001100000100100001, 42'b100000010000000000001000001000000010000001, 42'b100000001000000000001000000100000000100001, 42'b100000000000000000001000000000000000000001, 42'b011111111000000000000111111100000000100001, 42'b011111110000000000000111111000000010000001
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table_three_out = {1'b1, {18{1'b0}}, table_three_out_tmp},
table_three_out_pl = table_three_dffe12,
table_three_out_tmp = wire_table_three_result,
table_two_data = {51'b111111111011111111001010101011000000010101110111110, 51'b111111110011111110001010110011000001101011001001011, 51'b111111101011111101001011000011000100000000001111000, 51'b111111100011111100001011011011000111010101000000101, 51'b111111011011111011001011111011001011101001010110001, 51'b111111010011111010001100100011010000111101000111101, 51'b111111001011111001001101010011010111010000001100111, 51'b111111000011111000001110001011011110100010011110001, 51'b111110111011110111001111001011100110110011110011010, 51'b111110110011110110010000010011110000000100000100010, 51'b111110101011110101010001100011111010010011001001001, 51'b111110100011110100010010111100000101100000111001110, 51'b111110011011110011010100011100010001101101001110010, 51'b111110010011110010010110000100011110110111111110101, 51'b111110001011110001010111110100101101000001000010101, 51'b111110000011110000011001101100111100001000010010100, 51'b111101111011101111011011101101001100001101100110001, 51'b111101110011101110011101110101011101010000110101011, 51'b111101101011101101100000000101101111010001111000100, 51'b111101100011101100100010011110000010010000100111010, 51'b111101011011101011100100111110010110001100111001110, 51'b111101010011101010100111100110101011000110100111111, 51'b111101001011101001101010010111000000111101101001110, 51'b111101000011101000101101001111010111110001110111010, 51'b111100111011100111110000001111101111100011001000011, 51'b111100110011100110110011011000001000010001010101000, 51'b111100101011100101110110101000100001111100010101011, 51'b111100100011100100111010000000111100100100000001011, 51'b111100011011100011111101100001011000001000010000111, 51'b111100010011100011000001001001110100101000111011111, 51'b111100001011100010000100111010010010000101111010100, 51'b111100000011100001001000110010110000011111000100101, 51'b111011111011100000001100110011001111110100010010011, 51'b111011110011011111010000111011110000000101011011100, 51'b111011101011011110010101001100010001010010011000001, 51'b111011100011011101011001100100110011011011000000010
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, 51'b010111011000100010001010000101010001000001101100011, 51'b010111010000100001110010110000101111000011010010001, 51'b010111001000100001011011100100001101011100001000010, 51'b010111000000100001000100011111101100001100000111000, 51'b010110111000100000101101100011001011010011000110010, 51'b010110110000100000010110101110101010110000111110000, 51'b010110101000100000000000000010001010100101100110010, 51'b010110100000011111101001011101101010110000110111000, 51'b010110011000011111010011000001001011010010101000010, 51'b010110010000011110111100101100101100001010110010000, 51'b010110001000011110100110100000001101011001001100001, 51'b010110000000011110010000011011101110111101101110111, 51'b010101111000011101111010011111010000111000010010000, 51'b010101110000011101100100101010110011001000101101101, 51'b010101101000011101001110111110010101101110111001110, 51'b010101100000011100111001011001111000101010101110010, 51'b010101011000011100100011111101011011111100000011011, 51'b010101010000011100001110101000111111100010110000110, 51'b010101001000011011111001011100100011011110101110101, 51'b010101000000011011100100011000000111101111110101000, 51'b010100111000011011001111011011101100010101111011110, 51'b010100110000011010111010100111010001010000111010111, 51'b010100101000011010100101111010110110100000101010100, 51'b010100100000011010010001010110011100000101000010101, 51'b010100011000011001111100111010000001111101111011000, 51'b010100010000011001101000100101101000001011001011111, 51'b010100001000011001010100011001001110101100101101001, 51'b010100000000011001000000010100110101100010010110110, 51'b010011111000011000101100011000011100101100000000110, 51'b010011110000011000011000100100000100001001100011001, 51'b010011101000011000000100110111101011111010110101111, 51'b010011100000010111110001010011010011111111110001001, 51'b010011011000010111011101110110111100011000001100101, 51'b010011010000010111001010100010100101000100000000100, 51'b010011001000010110110111010110001110000011000100111, 51'b010011000000010110100100010001110111010101010001100
, 51'b010010111000010110010001010101100000111010011110011, 51'b010010110000010101111110100001001010110010100011110, 51'b010010101000010101101011110100110100111101011001011, 51'b010010100000010101011001010000011111011010110111011, 51'b010010011000010101000110110100001010001010110101110, 51'b010010010000010100110100011111110101001101001100011, 51'b010010001000010100100010010011100000100001110011011, 51'b010010000000010100010000001111001100001000100010110, 51'b010001111000010011111110010010111000000001010010011, 51'b010001110000010011101100011110100100001011111010011, 51'b010001101000010011011010110010010000101000010010101, 51'b010001100000010011001001001101111101010110010011001, 51'b010001011000010010110111110001101010010101110100000, 51'b010001010000010010100110011101010111100110101101001, 51'b010001001000010010010101010001000101001000110110101, 51'b010001000000010010000100001100110010111100001000011, 51'b010000111000010001110011010000100001000000011010011, 51'b010000110000010001100010011100001111010101100100101, 51'b010000101000010001010001101111111101111011011111001, 51'b010000100000010001000001001011101100110010000010000, 51'b010000011000010000110000101111011011111001000101001, 51'b010000010000010000100000011011001011010000100000100, 51'b010000001000010000010000001110111010111000001100001, 51'b010000000000010000000000001010101010110000000000000, 51'b001111111000001111110000001110011010110111110100001, 51'b001111110000001111100000011010001011001111100000100, 51'b001111101000001111010000101101111011110110111101001, 51'b001111100000001111000001001001101100101110000001111, 51'b001111011000001110110001101101011101110100100111000, 51'b001111010000001110100010011001001111001010100100011, 51'b001111001000001110010011001101000000101111110001111, 51'b001111000000001110000100001000110010100100000111101, 51'b001110111000001101110101001100100100100111011101101, 51'b001110110000001101100110011000010110111001101011111, 51'b001110101000001101010111101100001001011010101010010, 51'b001110100000001101001001000111111100001010010000111
, 51'b001110011000001100111010101011101111001000010111110, 51'b001110010000001100101100010111100010010100110110110, 51'b001110001000001100011110001011010101101111100110000, 51'b001110000000001100010000000111001001011000011101011, 51'b001101111000001100000010001010111101001111010101000, 51'b001101110000001011110100010110110001010100000100110, 51'b001101101000001011100110101010100101100110100100110, 51'b001101100000001011011001000110011010000110101101000, 51'b001101011000001011001011101010001110110100010101010, 51'b001101010000001010111110010110000011101111010101111, 51'b001101001000001010110001001001111000110111100110100, 51'b001101000000001010100100000101101110001100111111011, 51'b001100111000001010010111001001100011101111011000011, 51'b001100110000001010001010010101011001011110101001101, 51'b001100101000001001111101101001001111011010101010111, 51'b001100100000001001110001000101000101100011010100011, 51'b001100011000001001100100101000111011111000011110001, 51'b001100010000001001011000010100110010011001111111111, 51'b001100001000001001001100001000101001000111110001111, 51'b001100000000001001000000000100100000000001101100000, 51'b001011111000001000110100001000010111000111100110001, 51'b001011110000001000101000010100001110011001011000100, 51'b001011101000001000011100101000000101110110111011001, 51'b001011100000001000010001000011111101100000000101110, 51'b001011011000001000000101100111110101010100110000100, 51'b001011010000000111111010010011101101010100110011011, 51'b001011001000000111101111000111100101100000000110011, 51'b001011000000000111100100000011011101110110100001100, 51'b001010111000000111011001000111010110010111111100110, 51'b001010110000000111001110010011001111000100010000001, 51'b001010101000000111000011100111000111111011010011101, 51'b001010100000000110111001000011000000111100111111010, 51'b001010011000000110101110100110111010001001001011000, 51'b001010010000000110100100010010110011011111101110110, 51'b001010001000000110011010000110101101000000100010101, 51'b001010000000000110010000000010100110101011011110110
, 51'b001001111000000110000110000110100000100000011010110, 51'b001001110000000101111100010010011010011111001111000, 51'b001001101000000101110010100110010100100111110011010, 51'b001001100000000101101001000010001110111001111111110, 51'b001001011000000101011111100110001001010101101100001, 51'b001001010000000101010110010010000011111010110000110, 51'b001001001000000101001101000101111110101001000101011, 51'b001001000000000101000100000001111001100000100010001, 51'b001000111000000100111011000101110100100000111110111, 51'b001000110000000100110010010001101111101010010011110, 51'b001000101000000100101001100101101010111100011000110, 51'b001000100000000100100001000001100110010111000101110, 51'b001000011000000100011000100101100001111010010010111, 51'b001000010000000100010000010001011101100101111000001, 51'b001000001000000100001000000101011001011001101101010, 51'b001000000000000100000000000001010101010101101010101, 51'b000111111000000011111000000101010001011001101000000, 51'b000111110000000011110000010001001101100101011101011, 51'b000111101000000011101000100101001001111001000010111, 51'b000111100000000011100001000001000110010100010000011, 51'b000111011000000011011001100101000010110110111110000, 51'b000111010000000011010010010000111111100001000011101, 51'b000111001000000011001011000100111100010010011001011, 51'b000111000000000011000100000000111001001010110111001, 51'b000110111000000010111101000100110110001010010100111, 51'b000110110000000010110110010000110011010000101010110, 51'b000110101000000010101111100100110000011101110000101, 51'b000110100000000010101001000000101101110001011110101, 51'b000110011000000010100010100100101011001011101100100, 51'b000110010000000010011100010000101000101100010010100, 51'b000110001000000010010110000100100110010011001000101, 51'b000110000000000010010000000000100100000000000110101, 51'b000101111000000010001010000100100001110011000100110, 51'b000101110000000010000100010000011111101011111011000, 51'b000101101000000001111110100100011101101010100001001, 51'b000101100000000001111001000000011011101110101111011
, 51'b000101011000000001110011100100011001111000011101101, 51'b000101010000000001101110010000011000000111100011111, 51'b000101001000000001101001000100010110011011111010010, 51'b000101000000000001100100000000010100110101011000100, 51'b000100111000000001011111000100010011010011110110111, 51'b000100110000000001011010010000010001110111001101010, 51'b000100101000000001010101100100010000011111010011101, 51'b000100100000000001010001000000001111001100000010001, 51'b000100011000000001001100100100001101111101010000100, 51'b000100010000000001001000010000001100110010110111000, 51'b000100001000000001000100000100001011101100101101100, 51'b000100000000000001000000000000001010101010101011111, 51'b000011111000000000111100000100001001101100101010100, 51'b000011110000000000111000010000001000110010100001000, 51'b000011101000000000110100100100000111111100000111100, 51'b000011100000000000110001000000000111001001010110000, 51'b000011011000000000101101100100000110011010000100101, 51'b000011010000000000101010010000000101101110001011001, 51'b000011001000000000100111000100000101000101100001110, 51'b000011000000000000100100000000000100100000000000011, 51'b000010111000000000100001000100000011111101011111000, 51'b000010110000000000011110010000000011011101110101101, 51'b000010101000000000011011100100000011000000111100001, 51'b000010100000000000011001000000000010100110101010110, 51'b000010011000000000010110100100000010001110111001011, 51'b000010010000000000010100010000000001111001100000001, 51'b000010001000000000010010000100000001100110010110110, 51'b000010000000000000010000000000000001010101010101011, 51'b000001111000000000001110000100000001000110010100000, 51'b000001110000000000001100010000000000111001001010101, 51'b000001101000000000001010100100000000101101110001010, 51'b000001100000000000001001000000000000100100000000000, 51'b000001011000000000000111100100000000011011101110101, 51'b000001010000000000000110010000000000010100110101010, 51'b000001001000000000000101000100000000001111001100000, 51'b000001000000000000000100000000000000001010101010101
, 51'b000000111000000000000011000100000000000111001001010, 51'b000000110000000000000010010000000000000100100000000, 51'b000000101000000000000001100100000000000010100110101, 51'b000000100000000000000001000000000000000001010101010, 51'b000000011000000000000000100100000000000000100011111, 51'b000000010000000000000000010000000000000000001010101, 51'b000000001000000000000000000100000000000000000001010, {51{1'b0}}},
table_two_out = {1'b1, {9{1'b0}}, table_two_out_tmp},
table_two_out_pl = table_two_dffe12,
table_two_out_tmp = wire_table_two_result,
tbl1_compare_wi = wire_tbl1_compare_ageb,
tbl1_compare_wo = tbl1_compare_dffe11_10_pipes9[0:0],
tbl1_tbl2_prod_wi = wire_tbl1_tbl2_prod_result[121:62],
tbl1_tbl2_prod_wo = tbl1_tbl2_prod_wi,
tbl3_taylor_prod_wi = wire_tbl3_taylor_prod_result[119:60],
tbl3_taylor_prod_wo = tbl3_taylor_prod_wi,
underflow_compare_val_w = 11'b00000111010,
underflow_w = (((((result_underflow_w | barrel_shifter_underflow) | (sign_dffe23[0:0] & (distance_overflow | (~ wire_exp_value_add_bias_result[11])))) & (~ input_is_zero_wo)) & (~ input_is_infinity_wo)) & (~ input_is_nan_wo)),
x_fixed = wire_rbarrel_shift_result,
xf = wire_xf_muxa_dataout,
xf_pl = xf_pl_dffe12,
xf_pre = wire_x_fixed_minus_xiln2_result,
xf_pre_2_wi = xf_pre_wo,
xf_pre_2_wo = xf_pre_2_dffe10,
xf_pre_wi = xf_pre,
xf_pre_wo = xf_pre_dffe9,
xi_exp_value = xi_prod_wo[24:14],
xi_exp_value_wi = xi_exp_value,
xi_exp_value_wo = xi_exp_value_dffe4,
xi_ln2_prod_wi = wire_xi_ln2_prod_result,
xi_ln2_prod_wo = xi_ln2_prod_dffe7,
xi_prod_wi = wire_xi_prod_result,
xi_prod_wo = xi_prod_dffe3;
endmodule //acl_fp_exp_double_altfp_exp_79d
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_exp_double (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [63:0] dataa;
output [63:0] result;
wire [63:0] sub_wire0;
wire [63:0] result = sub_wire0[63:0];
acl_fp_exp_double_altfp_exp_79d acl_fp_exp_double_altfp_exp_79d_component (
.clk_en (enable),
.clock (clock),
.data (dataa),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_exp"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "25"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "52"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL "data[63..0]"
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: USED_PORT: result 0 0 64 0 OUTPUT NODEFVAL "result[63..0]"
// Retrieval info: CONNECT: result 0 0 64 0 @result 0 0 64 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_exp_double.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_exp_double.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_exp_double.bsf FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_exp_double_inst.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_exp_double_bb.v FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_exp_double.inc FALSE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_exp_double.cmp FALSE TRUE
// Retrieval info: LIB_FILE: lpm
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module start_for_CvtColoudo_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module start_for_CvtColoudo (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd5;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_CvtColoudo_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_start_for_CvtColoudo_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
// megafunction wizard: %In-System Sources and Probes%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsource_probe
// ============================================================
// File Name: hps_reset.v
// Megafunction Name(s):
// altsource_probe
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Internal Build 108 07/09/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module hps_reset (
probe,
source_clk,
source);
input probe;
input source_clk;
output [2:0] source;
wire [2:0] sub_wire0;
wire [2:0] source = sub_wire0[2:0];
altsource_probe altsource_probe_component (
.probe (probe),
.source_clk (source_clk),
.source (sub_wire0)
// synopsys translate_off
,
.clrn (),
.ena (),
.ir_in (),
.ir_out (),
.jtag_state_cdr (),
.jtag_state_cir (),
.jtag_state_e1dr (),
.jtag_state_sdr (),
.jtag_state_tlr (),
.jtag_state_udr (),
.jtag_state_uir (),
.raw_tck (),
.source_ena (),
.tdi (),
.tdo (),
.usr1 ()
// synopsys translate_on
);
defparam
altsource_probe_component.enable_metastability = "YES",
altsource_probe_component.instance_id = "RST",
altsource_probe_component.probe_width = 0,
altsource_probe_component.sld_auto_instance_index = "YES",
altsource_probe_component.sld_instance_index = 0,
altsource_probe_component.source_initial_value = " 0",
altsource_probe_component.source_width = 3;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES"
// Retrieval info: CONSTANT: INSTANCE_ID STRING "RST"
// Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0"
// Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES"
// Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0"
// Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0"
// Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3"
// Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe"
// Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]"
// Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk"
// Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0
// Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0
// Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/****************************************************************************
Generic Register
****************************************************************************/
module register(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk or negedge resetn) //asynchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Register - synchronous reset
****************************************************************************/
module register_sync(d,clk,resetn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Pipelined Register
- Special component, components starting with "pipereg" have
their enables treated independently of instructrions that use them.
- They are enabled whenever the stage is active and not stalled
****************************************************************************/
module pipereg(d,clk,resetn,en,squashn,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
endmodule
/****************************************************************************
Generic Pipelined Register 2 -OLD: If not enabled, queues squash
- This piperegister stalls the reset signal as well
module pipereg_full(d,clk,resetn,squashn,en,q);
parameter WIDTH=32;
input clk;
input resetn;
input en;
input squashn;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
reg squash_save;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || (squashn==0 && en==1) || (squash_save&en))
q<=0;
else if (en==1)
q<=d;
end
always @(posedge clk)
begin
if (resetn==1 && squashn==0 && en==0)
squash_save<=1;
else
squash_save<=0;
end
endmodule
****************************************************************************/
/****************************************************************************
One cycle Stall circuit
****************************************************************************/
module onecyclestall(request,clk,resetn,stalled);
input request;
input clk;
input resetn;
output stalled;
reg T,Tnext;
// State machine for Stalling 1 cycle
always@(request or T)
begin
case(T)
1'b0: Tnext=request;
1'b1: Tnext=0;
endcase
end
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=Tnext;
assign stalled=(request&~T);
endmodule
/****************************************************************************
Multi cycle Stall circuit - with wait signal
- One FF plus one 2:1 mux to stall 1st cycle on request, then wait
- this makes wait don't care for the first cycle
****************************************************************************/
module multicyclestall(request, devwait,clk,resetn,stalled);
input request;
input devwait;
input clk;
input resetn;
output stalled;
reg T;
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=stalled;
assign stalled=(T) ? devwait : request;
endmodule
/****************************************************************************
One cycle - Pipeline delay register
****************************************************************************/
module pipedelayreg(d,en,clk,resetn,squashn,dst,stalled,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
input [4:0] dst;
input en;
input clk;
input resetn;
input squashn;
output stalled;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
reg T,Tnext;
// State machine for Stalling 1 cycle
always@(en or T or dst)
begin
case(T)
0: Tnext=en&(|dst);
1: Tnext=0;
endcase
end
always@(posedge clk)
if (~resetn)
T<=0;
else
T<=Tnext;
always @(posedge clk) //synchronous reset
begin
if (resetn==0 || squashn==0)
q<=0;
else if (en==1)
q<=d;
end
assign stalled=(en&~T&(|dst));
endmodule
/****************************************************************************
Fake Delay
****************************************************************************/
module fakedelay(d,clk,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
input clk;
output [WIDTH-1:0] q;
assign q=d;
endmodule
/****************************************************************************
Zeroer
****************************************************************************/
module zeroer(d,en,q);
parameter WIDTH=32;
input en;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
assign q= (en) ? d : 0;
endmodule
/****************************************************************************
NOP - used to hack position of multiplexors
****************************************************************************/
module nop(d,q);
parameter WIDTH=32;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
assign q=d;
endmodule
/****************************************************************************
Const
****************************************************************************/
module const (out);
parameter WIDTH=32;
parameter VAL=31;
output [WIDTH-1:0] out;
assign out=VAL;
endmodule
/****************************************************************************
Branch detector
****************************************************************************/
module branch_detector(opcode, func, is_branch);
input [5:0] opcode;
input [5:0] func;
output is_branch;
wire is_special;
assign is_special=!(|opcode);
assign is_branch=((!(|opcode[5:3])) && !is_special) ||
((is_special)&&(func[5:3]==3'b001));
endmodule
|
// usb_avalon.v
`timescale 1 ns / 1 ps
module usb_avalon_16bit
(
input clk,
input reset,
// avs_ctrl
input avs_ctrl_address,
input avs_ctrl_write,
input [7:0]avs_ctrl_writedata,
input avs_ctrl_read,
output [7:0]avs_ctrl_readdata,
// asi_uplink
output ready,
input valid,
input [15:0]data,
input startofpacket,
input endofpacket,
input empty,
// tx fifo interface
output tx_write,
output [15:0]tx_data,
output [1:0]tx_mask,
input tx_full,
// rx fifo interface
output rx_read,
input [15:0]rx_data,
input rx_mask,
input rx_empty
);
// === avs_ctrl ===========================================================
wire [7:0]readdata_fifo;
wire [7:0]status = { 7'b0000000, !rx_empty };
wire si_request; // request for send immediate
assign si_request = avs_ctrl_write && avs_ctrl_address && avs_ctrl_writedata[0];
assign avs_ctrl_readdata = avs_ctrl_read ?
(avs_ctrl_address ? status : readdata_fifo) : 0;
// --- data register
reg rx_upper;
assign readdata_fifo = rx_upper ? rx_data[15:8] : rx_data[7:0];
assign rx_read = avs_ctrl_read && !avs_ctrl_address && !rx_empty && (!rx_mask || rx_upper);
always @(posedge clk or posedge reset)
begin
if (reset) rx_upper <= 0;
else if (avs_ctrl_read && !avs_ctrl_address && !rx_empty)
rx_upper <= !rx_upper && rx_mask;
end
// === asi_uplink =========================================================
assign ready = !tx_full;
wire tx_empty = endofpacket && empty;
wire tx_write_dat = valid && ready;
reg si; // send immediate request received
wire si_send = si && ready && !valid;
always @(posedge clk or posedge reset)
begin
if (reset) si <= 0;
else if (si_send) si <= 0;
else if (si_request) si <= 1;
end
assign tx_data = {data[7:0], data[15:8]};
assign tx_mask = si_send ? 2'b00 : {!tx_empty, 1'b1};
assign tx_write = si_send || tx_write_dat;
endmodule
|
`timescale 1ns/1ns
module sram_if_tb;
reg clk, rst;
initial begin
clk <= 0;
rst <= 1;
#105;
rst <= 0;
#10000
$display("test_tb done");
$finish;
end
always begin
#10 clk = ~clk;
end
reg [3:0] addr;
reg wen;
reg [31:0] wdata;
wire [31:0] rdata;
reg [2:0] st;
always @(posedge clk) begin
if (rst) begin
st <= 0;
addr <= 0;
wen <= 0;
wdata <= 0;
end else begin
case (st)
0: begin
addr <= 7;
wdata <= 5;
wen <= 1;
st <= 1;
end
1: begin
addr <= 8;
wdata <= 6;
wen <= 1;
st <= 2;
end
2: begin
addr <= 7;
wen <= 0;
st <= 3;
end
3: begin
addr <= 8;
if (rdata !== 5) begin
$display("ASSERTION FAILURE %x", rdata);
end
st <= 4;
end
4: begin
if (rdata !== 6) begin
$display("ASSERTION FAILURE %x", rdata);
end
st <= 5;
end
5: begin
end
endcase
end
end
mod_main m(.clk(clk), .rst(rst), .s_addr(addr), .s_wen(wen), .s_rdata(rdata), .s_wdata(wdata));
endmodule // sram_if_tb
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: LPM_ADD.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.0 Build 156 04/24/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module LPM_ADD (
cin,
dataa,
datab,
cout,
overflow,
result);
input cin;
input [15:0] dataa;
input [15:0] datab;
output cout;
output overflow;
output [15:0] result;
wire sub_wire0;
wire sub_wire1;
wire [15:0] sub_wire2;
wire overflow = sub_wire0;
wire cout = sub_wire1;
wire [15:0] result = sub_wire2[15:0];
lpm_add_sub LPM_ADD_SUB_component (
.cin (cin),
.datab (datab),
.dataa (dataa),
.overflow (sub_wire0),
.cout (sub_wire1),
.result (sub_wire2)
// synopsys translate_off
,
.aclr (),
.add_sub (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam
LPM_ADD_SUB_component.lpm_direction = "ADD",
LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
LPM_ADD_SUB_component.lpm_representation = "SIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB",
LPM_ADD_SUB_component.lpm_width = 16;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "1"
// Retrieval info: PRIVATE: CarryOut NUMERIC "1"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: Overflow NUMERIC "1"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "16"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: USED_PORT: cin 0 0 0 0 INPUT NODEFVAL "cin"
// Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL "cout"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: overflow 0 0 0 0 OUTPUT NODEFVAL "overflow"
// Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL "result[15..0]"
// Retrieval info: CONNECT: @cin 0 0 0 0 cin 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
// Retrieval info: CONNECT: overflow 0 0 0 0 @overflow 0 0 0 0
// Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL LPM_ADD.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL LPM_ADD.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LPM_ADD.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LPM_ADD.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LPM_ADD_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL LPM_ADD_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
//////////////////////////////////////////////////////////////////////////////
//
// Xilinx, Inc. 2010 www.xilinx.com
//
// XAPP xxx - TMDS serial stream phase aligner
//
//////////////////////////////////////////////////////////////////////////////
//
// File name : phasealigner.v
//
// Description : This module determines whether the Spartan-6 IOSERDES
// has validate the incoming TMDS data stream
//
//
// Note:
//
// Author : Bob Feng
//
// Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are
// provided to you "as is". Xilinx and its licensors make and you
// receive no warranties or conditions, express, implied,
// statutory or otherwise, and Xilinx specifically disclaims any
// implied warranties of merchantability, non-infringement,or
// fitness for a particular purpose. Xilinx does not warrant that
// the functions contained in these designs will meet your
// requirements, or that the operation of these designs will be
// uninterrupted or error free, or that defects in the Designs
// will be corrected. Furthermore, Xilinx does not warrantor
// make any representations regarding use or the results of the
// use of the designs in terms of correctness, accuracy,
// reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its
// licensors be liable for any loss of data, lost profits,cost
// or procurement of substitute goods or services, or for any
// special, incidental, consequential, or indirect damages
// arising from the use or operation of the designs or
// accompanying documentation, however caused and on any theory
// of liability. This limitation will apply even if Xilinx
// has been advised of the possibility of such damage. This
// limitation shall apply not-withstanding the failure of the
// essential purpose of any limited remedies herein.
//
// Copyright © 2006 Xilinx, Inc.
// All rights reserved
//
//////////////////////////////////////////////////////////////////////////////
//
`timescale 1 ns / 1ps
module phsaligner # (
parameter OPENEYE_CNT_WD = 3, // valid open eye counter width
parameter CTKNCNTWD = 7, // Control Token Counter Width
parameter SRCHTIMERWD = 12 // Idle Timer Width
)
(
input wire rst,
input wire clk,
input wire [9:0] sdata, // 10 bit serial stream sync. to clk
output reg flipgear,
output reg bitslip,
output reg psaligned // FSM output
);
parameter CTRLTOKEN0 = 10'b1101010100;
parameter CTRLTOKEN1 = 10'b0010101011;
parameter CTRLTOKEN2 = 10'b0101010100;
parameter CTRLTOKEN3 = 10'b1010101011;
///////////////////////////////////////////////////////
// Control Token Detection
///////////////////////////////////////////////////////
reg rcvd_ctkn, rcvd_ctkn_q;
reg blnkbgn; //blank period begins
always @ (posedge clk) begin
rcvd_ctkn <=#1 ((sdata == CTRLTOKEN0) || (sdata == CTRLTOKEN1) ||
(sdata == CTRLTOKEN2) || (sdata == CTRLTOKEN3));
rcvd_ctkn_q <=#1 rcvd_ctkn;
blnkbgn <=#1 !rcvd_ctkn_q & rcvd_ctkn;
end
/////////////////////////////////////////////////////
// Control Token Search Timer
//
// DVI 1.0 Spec. says periodic blanking should start
// no less than every 50ms or 20HZ
// 2^24 of 74.25MHZ cycles is about 200ms
/////////////////////////////////////////////////////
reg [(SRCHTIMERWD-1):0] ctkn_srh_timer;
reg ctkn_srh_rst; //FSM output
always @ (posedge clk) begin
if (ctkn_srh_rst)
ctkn_srh_timer <=#1 {SRCHTIMERWD{1'b0}};
else
ctkn_srh_timer <=#1 ctkn_srh_timer + 1'b1;
end
reg ctkn_srh_tout;
always @ (posedge clk) begin
ctkn_srh_tout <=#1 (ctkn_srh_timer == {SRCHTIMERWD{1'b1}});
end
/////////////////////////////////////////////////////
// Contorl Token Event Counter
//
// DVI 1.0 Spec. says the minimal blanking period
// is at least 128 pixels long in order to achieve
// synchronization
//
// HDMI reduces this to as little as 8
/////////////////////////////////////////////////////
reg [(CTKNCNTWD-1):0] ctkn_counter;
reg ctkn_cnt_rst; //FSM output
always @ (posedge clk) begin
if(ctkn_cnt_rst)
ctkn_counter <=#1 {CTKNCNTWD{1'b0}};
else
ctkn_counter <=#1 ctkn_counter + 1'b1;
end
reg ctkn_cnt_tout;
always @ (posedge clk) begin
ctkn_cnt_tout <=#1 (ctkn_counter == {CTKNCNTWD{1'b1}});
end
//////////////////////////////////////////////////////////
// Below starts the phase alignment state machine
//////////////////////////////////////////////////////////
parameter INIT = 6'b1 << 0;
parameter SEARCH = 6'b1 << 1; // Searching for control tokens
parameter BITSLIP = 6'b1 << 2;
parameter RCVDCTKN = 6'b1 << 3; // Received at one Control Token and check for more
parameter BLNKPRD = 6'b1 << 4;
parameter PSALGND = 6'b1 << 5; // Phase alignment achieved
parameter nSTATES = 6;
reg [(nSTATES-1):0] cstate = {{(nSTATES-1){1'b0}}, 1'b1}; //current and next states
reg [(nSTATES-1):0] nstate;
`ifdef SIMULATION
// synthesis translate_off
reg [8*20:1] state_ascii = "INIT ";
always @(cstate) begin
if (cstate == INIT ) state_ascii <= "INIT ";
else if (cstate == SEARCH ) state_ascii <= "SEARCH ";
else if (cstate == BITSLIP ) state_ascii <= "BITSLIP ";
else if (cstate == RCVDCTKN ) state_ascii <= "RCVDCTKN ";
else if (cstate == BLNKPRD ) state_ascii <= "BLNKPRD ";
else state_ascii <= "PSALGND ";
end
// synthesis translate_on
`endif
always @ (posedge clk or posedge rst) begin
if (rst)
cstate <= INIT;
else
cstate <=#1 nstate;
end
//////////////////////////////////////////////////////////
// Counter counts number of blank period detected
// in order to qualify the bitslip position
//////////////////////////////////////////////////////////
parameter BLNKPRD_CNT_WD = 1;
reg [(BLNKPRD_CNT_WD-1):0] blnkprd_cnt = {BLNKPRD_CNT_WD{1'b0}};
always @ (*) begin
case (cstate) //synthesis parallel_case full_case
INIT: begin
nstate = (ctkn_srh_tout) ? SEARCH : INIT;
end
SEARCH: begin
if(blnkbgn)
nstate = RCVDCTKN;
else
nstate = (ctkn_srh_tout) ? BITSLIP : SEARCH;
end
BITSLIP: begin
nstate = SEARCH;
end
RCVDCTKN: begin
if(rcvd_ctkn)
nstate = (ctkn_cnt_tout) ? BLNKPRD : RCVDCTKN;
else
nstate = SEARCH;
end
BLNKPRD: begin
nstate = (blnkprd_cnt == {BLNKPRD_CNT_WD{1'b1}}) ? PSALGND : SEARCH;
end
PSALGND: begin
nstate = PSALGND; // Phase aligned so hang around here
end
endcase
end
reg [2:0] bitslip_cnt;
always @ (posedge clk or posedge rst) begin
if(rst) begin
psaligned <=#1 1'b0; //phase alignment success flag
bitslip <=#1 1'b0;
ctkn_srh_rst <=#1 1'b1; //control token search timer reset
ctkn_cnt_rst <=#1 1'b1; //control token counter reset
bitslip <=#1 1'b0;
bitslip_cnt <=#1 3'h0;
flipgear <=#1 1'b0;
blnkprd_cnt <=#1 {BLNKPRD_CNT_WD{1'b0}};
end else begin
case (cstate) // synthesis parallel_case full_case
INIT: begin
ctkn_srh_rst <=#1 1'b0;
ctkn_cnt_rst <=#1 1'b1;
bitslip <=#1 1'b0;
psaligned <=#1 1'b0;
bitslip <=#1 1'b0;
bitslip_cnt <=#1 3'h0;
flipgear <=#1 1'b0;
blnkprd_cnt <=#1 {BLNKPRD_CNT_WD{1'b0}};
end
SEARCH: begin
ctkn_srh_rst <=#1 1'b0;
ctkn_cnt_rst <=#1 1'b1;
bitslip <=#1 1'b0;
psaligned <=#1 1'b0;
end
BITSLIP: begin
ctkn_srh_rst <=#1 1'b1;
bitslip <=#1 1'b1;
bitslip_cnt <=#1 bitslip_cnt + 1'b1;
flipgear <=#1 bitslip_cnt[2]; //bitslip has toggled for 4 times
end
RCVDCTKN: begin
ctkn_srh_rst <=#1 1'b0;
ctkn_cnt_rst <=#1 1'b0;
end
BLNKPRD: begin
blnkprd_cnt <=#1 blnkprd_cnt + 1'b1;
end
PSALGND: begin
psaligned <=#1 1'b1;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLRTP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DLRTP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLRTP_BLACKBOX_V
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:45:29 02/23/2009
// Design Name:
// Module Name: RCB_FRL_RX_MSG
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_RX_MSG(CLK, CLKDIV, DATA_IN, DATA_OUT, RST, RE_SIG, EN_SIG, CON_P, CON_N);
input CLK, CLKDIV;
input [7:0] DATA_IN;
output [39:0] DATA_OUT;
output CON_P, CON_N;
output RE_SIG, EN_SIG;
input RST;
// wire [7:0] DATA_IN;
wire [7:0] fifo_reg1;
wire [39:0] D;
// wire [39:0] DATA_OUT;
RCB_FRL_channel_MSG inst_channel1 (
.CLK(CLK),
.CLKDIV(CLKDIV),
.DATA_IN(DATA_IN),
.RST(RST),
.fifo_WREN1(EN_SIG),
.D(DATA_OUT),
.RE_SIG(RE_SIG),
.CON_P(CON_P),
.CON_N(CON_N)
);
endmodule
module RCB_FRL_channel_MSG (CLK, CLKDIV, DATA_IN, RST, fifo_WREN1, D, RE_SIG, CON_P, CON_N);
input CLK, CLKDIV, RST;
input [7:0] DATA_IN;
output fifo_WREN1, RE_SIG; //fifo_WREN1 is right signal RE_SIG is wrong signal
output [39:0] D;
output CON_P, CON_N;
//reg [39:0] D;
wire [7:0] input_reg1_wire, input_reg1_wire_inv;
wire CON_P, CON_N;
/*assign input_reg1_wire = {~input_reg1_wire_inv[7],
~input_reg1_wire_inv[6],
~input_reg1_wire_inv[5],
~input_reg1_wire_inv[4],
~input_reg1_wire_inv[3],
~input_reg1_wire_inv[2],
~input_reg1_wire_inv[1],
~input_reg1_wire_inv[0]};*/
assign input_reg1_wire = DATA_IN;
RCB_FRL_CMD_shift_MSG CMD_shift_inst
(
.data_in(input_reg1_wire),
.clk(CLKDIV),
.enable(~RST),
.data_out(),
.data_valid(),
.data_correct(fifo_WREN1),
.data_wrong(RE_SIG),
.data_all(D)
);
RCB_FRL_CMD_shift_MSG_CON CMD_shift_inst2
(
.data_in(input_reg1_wire),
.clk(CLKDIV),
.enable(~RST),
.CON_P(CON_P),
.CON_N(CON_N)
);
endmodule
module RCB_FRL_CMD_shift_MSG
(
data_in,
clk,
enable,
data_out,
data_valid,
data_correct, // Jiansong: one cycle signal
data_wrong,
data_all
);
parameter lock_pattern = 8'hff ; //Specifies the lock pattern
parameter pack_size = 100; // Current packet size
parameter word_size = 8; // Not currently used in code
input clk;
input enable; //Active low reset
input [7:0] data_in;
output data_valid;
output [7:0] data_out;
output data_correct;
output data_wrong;
output [39:0] data_all;
// output lockk;
reg [7:0] data_reg1; //First register used to re-align the data
reg [7:0] data_reg2; //Second register used to re-align the data
reg [7:0] data_reg3; //Third register used to re-align the data
reg [2:0] shift; //designate the bit shift value of the package
reg lock; //if high, then the correct shift value has been found.
reg [7:0] byte_count; //word count in packet
reg [2:0] front_count;
reg [7:0] data_out_tmp; //pipeline register
reg data_valid;
reg [7:0] frame_length;
reg [7:0] data_out; // output register
reg data_correct;
reg data_wrong;
reg [39:0] data_all;
wire end_pack = pack_size; // signifies end of packet
wire [7:0] CRC_ans;
RCB_FRL_CRC_gen RCB_FRL_CRC_gen_inst ( .D({{8'h06},data_all}), .NewCRC(CRC_ans));
always @(negedge clk) //????2¨||?|???¨a?¤¨o?3???3?
// always @(negedge clk) // timing broken to set data_valid flag
begin
if (!enable)
begin
data_out_tmp <= 8'h00; //test data_out_tmp <= 8'h00;
//data_valid<=1'b1;
end
else
begin
//data_valid<=1'b1;
case(shift) //Re-aligns the data depending on shift value
3'h0 : data_out_tmp <= data_reg3;
3'h1 : data_out_tmp <= ({data_reg3[6:0],data_reg2[7]});
3'h2 : data_out_tmp <= ({data_reg3[5:0],data_reg2[7:6]});
3'h3 : data_out_tmp <= ({data_reg3[4:0],data_reg2[7:5]});
3'h4 : data_out_tmp <= ({data_reg3[3:0],data_reg2[7:4]});
3'h5 : data_out_tmp <= ({data_reg3[2:0],data_reg2[7:3]});
3'h6 : data_out_tmp <= ({data_reg3[1:0],data_reg2[7:2]});
3'h7 : data_out_tmp <= ({data_reg3[0],data_reg2[7:1]});
default : data_out_tmp <= data_reg3;
endcase
end
end
// Word counter, counts words in packet
always@(negedge clk) //??¨oy??3?
begin
if(!enable || !lock) // Active low reset
begin
byte_count <= 0; //Initializes byte count
front_count <= 0;
//frame_length <= 0;
end
if(lock)//lock data_valid
begin
byte_count <= byte_count + 1; //Increments the byte count to keep track of packet boundry
front_count <= front_count+1;
end
end
// Data shift registers
always @(negedge clk) //
begin
if(!enable)
begin
data_reg1 <= 8'h00; //Initializes the registers
data_reg2 <= 8'h00;
data_reg3 <= 8'h00;
end
else
begin
data_reg1 <= data_in; // Registers incoming data, shifts to compare registers
data_reg2 <= data_reg1; // reg2 and reg3 are compare registers
data_reg3 <= data_reg2;
end
end
// Search and validate
always @(negedge clk) //
begin
if(!enable) // if (!enable)
begin
lock <= 0;
shift <= 0;
data_out <= 8'h00; ///data_out <= 8'h00; //////
data_valid <= 0;
frame_length <= 0;
end
else //else 1
begin //
//data_out <= 8'hff;
if(!lock) //If not locked, search for lock pattern
begin //begin search
// data_out <= data_reg2;
data_correct <= 1'b0;
data_wrong <= 1'b0;
if(data_reg3 === 8'hf5 )
begin
// data_out <= 8'hff;
//data_valid <= 1;
lock <= 1;
shift <= 3'h0;
end
else if({data_reg3[6:0],data_reg2[7]} === 8'hf5 )
begin
lock <= 1;
shift <= 3'h1;
end
else if({data_reg3[5:0],data_reg2[7:6]} === 8'hf5 )
begin
lock <= 1;
shift <= 3'h2;
end
else if({data_reg3[4:0],data_reg2[7:5]} === 8'hf5 )
begin
lock <= 1;
shift <= 3'h3;
end
else if({data_reg3[3:0],data_reg2[7:4]} === 8'hf5 )
begin
lock <= 1;
shift <= 3'h4;
end
else if({data_reg3[2:0],data_reg2[7:3]} === 8'hf5 )
begin
lock <= 1;
shift <= 3'h5;
end
else if({data_reg3[1:0],data_reg2[7:2]} === 8'hf5)
begin
lock <= 1;
shift <= 3'h6;
end
else if({data_reg3[0],data_reg2[7:1]} === 8'hf5) //lock_pattern
begin
lock <= 1;
shift <= 3'h7;
end
end //if (!lock) // end search
else if (lock)
begin //Confirms that data is valid
if( byte_count == 8'h00) //the frame head
begin
data_valid <= 0;
data_out <= 8'hff; //output the frame head
end
else if(byte_count == 8'h01) //the frame length
begin
data_valid <= 0;
data_out <= data_out_tmp;
frame_length <= data_out_tmp;
end
else if(byte_count < /*8'd7*/frame_length + 8'h1)
begin
data_valid <= 1;
data_out <= data_out_tmp;
if (byte_count == 8'h02)
begin
data_all[39:32] <= data_out_tmp;
end
else if (byte_count == 8'h03)
begin
data_all[31:24] <= data_out_tmp;
end
else if (byte_count == 8'h04)
begin
data_all[23:16] <= data_out_tmp;
end
else if (byte_count == 8'h05)
begin
data_all[15:8] <= data_out_tmp;
end
else if (byte_count == 8'h06)
begin
data_all[7:0] <= data_out_tmp;
end
end
else if (byte_count >= frame_length + 8'h1)
begin
data_valid <= 0;
lock <= 0;
shift <= 0;
frame_length <= 0;
if ( CRC_ans == data_out_tmp)
begin
data_correct <=1'b1;
end
else
begin
data_wrong <=1'b1;
end
end
end //end if(lock)
end //end else if(enable)
end //end always
endmodule
module RCB_FRL_CMD_shift_MSG_CON
(
data_in,
clk,
enable,
CON_P,
CON_N
);
parameter lock_pattern = 8'hff ; //Specifies the lock pattern
parameter pack_size = 100; // Current packet size
parameter word_size = 8; // Not currently used in code
input clk;
input enable; //Active low reset
input [7:0] data_in;
//output data_valid;
//output [7:0] data_out;
//output data_correct;
//output data_wrong;
//output [39:0] data_all;
// output lockk;
output CON_P, CON_N;
reg [7:0] data_reg1; //First register used to re-align the data
reg [7:0] data_reg2; //Second register used to re-align the data
reg [7:0] data_reg3; //Third register used to re-align the data
reg [2:0] shift; //designate the bit shift value of the package
reg lock; //if high, then the correct shift value has been found.
reg [7:0] byte_count; //word count in packet
reg [2:0] front_count;
reg [7:0] data_out_tmp; //pipeline register
reg data_valid;
reg [7:0] frame_length;
reg [7:0] data_out; // output register
reg data_correct;
reg data_wrong;
reg [39:0] data_all;
wire end_pack = pack_size; // signifies end of packet
reg CON_P, CON_N;
always @(negedge clk) //????2¨||?|???¨a?¤¨o?3???3?
// always @(negedge clk) // timing broken to set data_valid flag
begin
if (!enable)
begin
data_out_tmp <= 8'h00; //test data_out_tmp <= 8'h00;
//data_valid<=1'b1;
end
else
begin
//data_valid<=1'b1;
case(shift) //Re-aligns the data depending on shift value
3'h0 : data_out_tmp <= data_reg3;
3'h1 : data_out_tmp <= ({data_reg3[6:0],data_reg2[7]});
3'h2 : data_out_tmp <= ({data_reg3[5:0],data_reg2[7:6]});
3'h3 : data_out_tmp <= ({data_reg3[4:0],data_reg2[7:5]});
3'h4 : data_out_tmp <= ({data_reg3[3:0],data_reg2[7:4]});
3'h5 : data_out_tmp <= ({data_reg3[2:0],data_reg2[7:3]});
3'h6 : data_out_tmp <= ({data_reg3[1:0],data_reg2[7:2]});
3'h7 : data_out_tmp <= ({data_reg3[0],data_reg2[7:1]});
default : data_out_tmp <= data_reg3;
endcase
end
end
// Data shift registers
always @(negedge clk) //
begin
if(!enable)
begin
data_reg1 <= 8'h00; //Initializes the registers
data_reg2 <= 8'h00;
data_reg3 <= 8'h00;
end
else
begin
data_reg1 <= data_in; // Registers incoming data, shifts to compare registers
data_reg2 <= data_reg1; // reg2 and reg3 are compare registers
data_reg3 <= data_reg2;
end
end
// Search and validate
always @(negedge clk) //
begin
if(!enable) // if (!enable)
begin
lock <= 0;
shift <= 0;
data_out <= 8'h00; ///data_out <= 8'h00; //////
data_valid <= 0;
frame_length <= 0;
end
else //else 1
begin
if(data_reg3 === 8'h5f )
begin
CON_P <= 1'b1;
end
else if({data_reg3[6:0],data_reg2[7]} === 8'h5f )
begin
CON_P <= 1'b1;
end
else if({data_reg3[5:0],data_reg2[7:6]} === 8'h5f )
begin
CON_P <= 1'b1;
end
else if({data_reg3[4:0],data_reg2[7:5]} === 8'h5f )
begin
CON_P <= 1'b1;
end
else if({data_reg3[3:0],data_reg2[7:4]} === 8'h5f )
begin
CON_P <= 1'b1;
end
else if({data_reg3[2:0],data_reg2[7:3]} === 8'h5f )
begin
CON_P <= 1'b1;
end
else if({data_reg3[1:0],data_reg2[7:2]} === 8'h5f)
begin
CON_P <= 1'b1;
end
else if({data_reg3[0],data_reg2[7:1]} === 8'h5f) //lock_pattern
begin
CON_P <= 1'b1;
end
else begin
CON_P <= 1'b0;
end
if(data_reg3 === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[6:0],data_reg2[7]} === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[5:0],data_reg2[7:6]} === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[4:0],data_reg2[7:5]} === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[3:0],data_reg2[7:4]} === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[2:0],data_reg2[7:3]} === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[1:0],data_reg2[7:2]} === 8'haf )
begin
CON_N <= 1'b1;
end
else if({data_reg3[0],data_reg2[7:1]} === 8'haf )//lock_pattern
begin
CON_N <= 1'b1;
end
else begin
CON_N <= 1'b0;
end
end //if (!lock) // end search
end
endmodule
|
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_w_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_WUSER_WIDTH = 1
// Width of AWUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface (In)
input wire cmd_w_valid,
input wire cmd_w_check,
input wire [C_AXI_ID_WIDTH-1:0] cmd_w_id,
output wire cmd_w_ready,
// Command Interface (Out)
output wire cmd_b_push,
output wire cmd_b_error,
output reg [C_AXI_ID_WIDTH-1:0] cmd_b_id,
input wire cmd_b_full,
// Slave Interface Write Port
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Detecttion.
wire any_strb_deasserted;
wire incoming_strb_issue;
reg first_word;
reg strb_issue;
// Data flow.
wire data_pop;
wire cmd_b_push_blocked;
reg cmd_b_push_i;
/////////////////////////////////////////////////////////////////////////////
// Detect error:
//
// Detect and accumulate error when a transaction shall be scanned for
// potential issues.
// Accumulation of error is restarted for each ne transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Check stobe information
assign any_strb_deasserted = ( S_AXI_WSTRB != {C_AXI_DATA_WIDTH/8{1'b1}} );
assign incoming_strb_issue = cmd_w_valid & S_AXI_WVALID & cmd_w_check & any_strb_deasserted;
// Keep track of first word in a transaction.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
end else if ( data_pop ) begin
first_word <= S_AXI_WLAST;
end
end
// Keep track of error status.
always @ (posedge ACLK) begin
if (ARESET) begin
strb_issue <= 1'b0;
cmd_b_id <= {C_AXI_ID_WIDTH{1'b0}};
end else if ( data_pop ) begin
if ( first_word ) begin
strb_issue <= incoming_strb_issue;
end else begin
strb_issue <= incoming_strb_issue | strb_issue;
end
cmd_b_id <= cmd_w_id;
end
end
assign cmd_b_error = strb_issue;
/////////////////////////////////////////////////////////////////////////////
// Control command queue to B:
//
// Push command to B queue when all data for the transaction has flowed
// through.
// Delay pipelined command until there is room in the Queue.
//
/////////////////////////////////////////////////////////////////////////////
// Detect when data is popped.
assign data_pop = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Push command when last word in transfered (pipelined).
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_push_i <= 1'b0;
end else begin
cmd_b_push_i <= ( S_AXI_WLAST & data_pop ) | cmd_b_push_blocked;
end
end
// Detect if pipelined push is blocked.
assign cmd_b_push_blocked = cmd_b_push_i & cmd_b_full;
// Assign output.
assign cmd_b_push = cmd_b_push_i & ~cmd_b_full;
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Stall commands if FIFO is full or there is no valid command information
// from AW.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign M_AXI_WVALID = S_AXI_WVALID & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// Return ready with push back.
assign S_AXI_WREADY = M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked;
// End of burst.
assign cmd_w_ready = S_AXI_WVALID & M_AXI_WREADY & cmd_w_valid & ~cmd_b_full & ~cmd_b_push_blocked & S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Write propagation:
//
// All information is simply forwarded on from the SI- to MI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign M_AXI_WID = S_AXI_WID;
assign M_AXI_WDATA = S_AXI_WDATA;
assign M_AXI_WSTRB = S_AXI_WSTRB;
assign M_AXI_WLAST = S_AXI_WLAST;
assign M_AXI_WUSER = S_AXI_WUSER;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Glen Gibb.
//module t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
// The 'initial' code block below tests compilation-time
// evaluation/optimization of the stream operator. All occurences of the stream
// operator within this block are replaced prior to generation of C code.
logic [3:0] dout;
logic [31:0] dout32;
logic [10:0] dout11;
initial begin
// Stream operator: <<
// Location: rhs of assignment
//
// Test slice sizes from 1 - 5
dout = { << {4'b0001}}; if (dout != 4'b1000) $stop;
dout = { << 2 {4'b0001}}; if (dout != 4'b0100) $stop;
dout = { << 3 {4'b0001}}; if (dout != 4'b0010) $stop;
dout = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop;
dout = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop;
// Stream operator: >>
// Location: rhs of assignment
//
// Right-streaming operator on RHS does not reorder bits
dout = { >> {4'b0001}}; if (dout != 4'b0001) $stop;
dout = { >> 2 {4'b0001}}; if (dout != 4'b0001) $stop;
dout = { >> 3 {4'b0001}}; if (dout != 4'b0001) $stop;
dout = { >> 4 {4'b0001}}; if (dout != 4'b0001) $stop;
dout = { >> 5 {4'b0001}}; if (dout != 4'b0001) $stop;
// Stream operator: <<
// Location: lhs of assignment
{ << {dout}} = 4'b0001; if (dout != 4'b1000) $stop;
{ << 2 {dout}} = 4'b0001; if (dout != 4'b0100) $stop;
{ << 3 {dout}} = 4'b0001; if (dout != 4'b0010) $stop;
{ << 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
{ << 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
// Stream operator: >>
// Location: lhs of assignment
{ >> {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
{ >> 2 {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
{ >> 3 {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
{ >> 4 {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
{ >> 5 {dout}} = 4'b0001; if (dout != 4'b0001) $stop;
// Stream operator: <<
// Location: lhs of assignment
// RHS is *wider* than LHS
/* verilator lint_off WIDTH */
{ << {dout}} = 5'b00001; if (dout != 4'b1000) $stop;
{ << 2 {dout}} = 5'b00001; if (dout != 4'b0100) $stop;
{ << 3 {dout}} = 5'b00001; if (dout != 4'b0010) $stop;
{ << 4 {dout}} = 5'b00001; if (dout != 4'b0001) $stop;
{ << 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop;
/* verilator lint_on WIDTH */
// Stream operator: >>
// Location: lhs of assignment
// RHS is *wider* than LHS
/* verilator lint_off WIDTH */
{ >> {dout}} = 5'b01101; if (dout != 4'b0110) $stop;
{ >> 2 {dout}} = 5'b01101; if (dout != 4'b0110) $stop;
{ >> 3 {dout}} = 5'b01101; if (dout != 4'b0110) $stop;
{ >> 4 {dout}} = 5'b01101; if (dout != 4'b0110) $stop;
{ >> 5 {dout}} = 5'b01101; if (dout != 4'b0110) $stop;
/* verilator lint_on WIDTH */
// Stream operator: <<
// Location: both sides of assignment
{ << {dout}} = { << {4'b0001}}; if (dout != 4'b0001) $stop;
{ << 2 {dout}} = { << 2 {4'b0001}}; if (dout != 4'b0001) $stop;
{ << 3 {dout}} = { << 3 {4'b0001}}; if (dout != 4'b0100) $stop;
{ << 4 {dout}} = { << 4 {4'b0001}}; if (dout != 4'b0001) $stop;
{ << 5 {dout}} = { << 5 {4'b0001}}; if (dout != 4'b0001) $stop;
// Stream operator: <<
// Location: as an operand within a statement
//
// Test slice sizes from 1 - 5
if (4'({ << {4'b0001}}) != 4'b1000) $stop;
if (4'({ << 2 {4'b0001}}) != 4'b0100) $stop;
if (4'({ << 3 {4'b0001}}) != 4'b0010) $stop;
if (4'({ << 4 {4'b0001}}) != 4'b0001) $stop;
if (4'({ << 5 {4'b0001}}) != 4'b0001) $stop;
// case
dout32 = { << 3 { 32'b11010111000010100100010010010111 }}; if (dout32 != 32'he92910eb) $stop;
dout11 = { << 4 { 11'b10010010111 }}; if (dout11 != 11'h3cc) $stop;
end
// The two always blocks below test run-time evaluation of the stream
// operator in generated C code.
//
// Various stream operators are optimized away. Here's a brief summary:
//
// Stream op on RHS of assign
// --------------------------
// X = { << a { Y } } --- C function evaluates stream operator
// -- if log2(a) == int --> "fast" eval func
// -- if log2(a) != int --> "slow" eval func
// X = { >> a { Y } } --- stream operator is optimized away
//
// Stream op on LHS of assign
// --------------------------
// Note: if Y.width() > X.width, then the MSBs of Y are used, not the LSBs!
// { << a { X } } = Y --- stream operator is moved to RHS, eval as above
// { >> a { X } } = Y --- stream operator is optimized away
logic [31:0] din_i;
logic [63:0] din_q;
logic [95:0] din_w;
// Stream op on RHS, left-stream operator
logic [31:0] dout_rhs_ls_i;
logic [63:0] dout_rhs_ls_q;
logic [95:0] dout_rhs_ls_w;
// Stream op on RHS, right-stream operator
logic [31:0] dout_rhs_rs_i;
logic [63:0] dout_rhs_rs_q;
logic [95:0] dout_rhs_rs_w;
// Stream op on both sides, left-stream operator
logic [31:0] dout_bhs_ls_i;
logic [63:0] dout_bhs_ls_q;
logic [95:0] dout_bhs_ls_w;
// Stream op on both sides, right-stream operator
logic [31:0] dout_bhs_rs_i;
logic [63:0] dout_bhs_rs_q;
logic [95:0] dout_bhs_rs_w;
// Stream operator on LHS (with concatenation on LHS)
logic [3:0] din_lhs;
logic [1:0] dout_lhs_ls_a, dout_lhs_ls_b;
logic [1:0] dout_lhs_rs_a, dout_lhs_rs_b;
// Addition operator on LHS, right-shift tests:
// Testing various shift sizes to exercise fast + slow funcs
logic [22:0] dout_rhs_ls_i_23_3;
logic [22:0] dout_rhs_ls_i_23_4;
logic [36:0] dout_rhs_ls_q_37_3;
logic [36:0] dout_rhs_ls_q_37_4;
always @*
begin
// Stream operator: <<
// Location: rhs of assignment
//
// Test each data type (I, Q, W)
dout_rhs_ls_i = { << {din_i}};
dout_rhs_ls_q = { << {din_q}};
dout_rhs_ls_w = { << {din_w}};
// Stream operator: >>
// Location: rhs of assignment
dout_rhs_rs_i = { >> {din_i}};
dout_rhs_rs_q = { >> {din_q}};
dout_rhs_rs_w = { >> {din_w}};
// Stream operator: <<
// Location: lhs of assignment
{ << 2 {dout_lhs_ls_a, dout_lhs_ls_b}} = din_lhs;
// Stream operator: >>
// Location: lhs of assignment
{ >> 2 {dout_lhs_rs_a, dout_lhs_rs_b}} = din_lhs;
// Stream operator: <<
// Location: both sides of assignment
{ << 5 {dout_bhs_ls_i}} = { << 5 {din_i}};
{ << 5 {dout_bhs_ls_q}} = { << 5 {din_q}};
{ << 5 {dout_bhs_ls_w}} = { << 5 {din_w}};
// Stream operator: >>
// Location: both sides of assignment
{ >> 5 {dout_bhs_rs_i}} = { >> 5 {din_i}};
{ >> 5 {dout_bhs_rs_q}} = { >> 5 {din_q}};
{ >> 5 {dout_bhs_rs_w}} = { >> 5 {din_w}};
// Stream operator: <<
// Location: both sides of assignment
{ << 5 {dout_bhs_ls_i}} = { << 5 {din_i}};
{ << 5 {dout_bhs_ls_q}} = { << 5 {din_q}};
{ << 5 {dout_bhs_ls_w}} = { << 5 {din_w}};
// Stream operator: <<
// Location: rhs of assignment
//
// Verify both fast and slow paths (fast: sliceSize = power of 2)
dout_rhs_ls_i_23_3 = { << 3 {din_i[22:0]}}; // SLOW
dout_rhs_ls_i_23_4 = { << 4 {din_i[22:0]}}; // FAST
dout_rhs_ls_q_37_3 = { << 3 {din_q[36:0]}}; // SLOW
dout_rhs_ls_q_37_4 = { << 4 {din_q[36:0]}}; // FAST
end
always @(posedge clk)
begin
if (cyc != 0) begin
cyc <= cyc + 1;
if (cyc == 1) begin
din_i <= 32'h_00_00_00_01;
din_q <= 64'h_00_00_00_00_00_00_00_01;
din_w <= 96'h_00_00_00_00_00_00_00_00_00_00_00_01;
din_lhs <= 4'b_00_01;
end
if (cyc == 2) begin
din_i <= 32'h_04_03_02_01;
din_q <= 64'h_08_07_06_05_04_03_02_01;
din_w <= 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01;
din_lhs <= 4'b_01_11;
if (dout_rhs_ls_i != 32'h_80_00_00_00) $stop;
if (dout_rhs_ls_q != 64'h_80_00_00_00_00_00_00_00) $stop;
if (dout_rhs_ls_w != 96'h_80_00_00_00_00_00_00_00_00_00_00_00) $stop;
if (dout_rhs_rs_i != 32'h_00_00_00_01) $stop;
if (dout_rhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop;
if (dout_rhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop;
if (dout_lhs_ls_a != 2'b_01) $stop;
if (dout_lhs_ls_b != 2'b_00) $stop;
if (dout_lhs_rs_a != 2'b_00) $stop;
if (dout_lhs_rs_b != 2'b_01) $stop;
if (dout_bhs_rs_i != 32'h_00_00_00_01) $stop;
if (dout_bhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop;
if (dout_bhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop;
if (dout_bhs_ls_i != 32'h_00_00_00_10) $stop;
if (dout_bhs_ls_q != 64'h_00_00_00_00_00_00_01_00) $stop;
if (dout_bhs_ls_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_04) $stop;
if (dout_rhs_ls_i_23_3 != 23'h_10_00_00) $stop;
if (dout_rhs_ls_i_23_4 != 23'h_08_00_00) $stop;
if (dout_rhs_ls_q_37_3 != 37'h_04_00_00_00_00) $stop;
if (dout_rhs_ls_q_37_4 != 37'h_02_00_00_00_00) $stop;
end
if (cyc == 3) begin
// The values below test the strange shift-merge done at the end of
// the fast stream operators.
// All-1s in the bits being streamed should end up as all-1s.
din_i <= 32'h_00_7f_ff_ff;
din_q <= 64'h_00_00_00_1f_ff_ff_ff_ff;
if (dout_rhs_ls_i != 32'h_80_40_c0_20) $stop;
if (dout_rhs_ls_q != 64'h_80_40_c0_20_a0_60_e0_10) $stop;
if (dout_rhs_ls_w != 96'h_80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop;
if (dout_rhs_rs_i != 32'h_04_03_02_01) $stop;
if (dout_rhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop;
if (dout_rhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop;
if (dout_bhs_ls_i != 32'h_40_30_00_18) $stop;
if (dout_bhs_ls_q != 64'h_06_00_c1_81_41_00_c1_80) $stop;
if (dout_bhs_ls_w != 96'h_30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop;
if (dout_bhs_rs_i != 32'h_04_03_02_01) $stop;
if (dout_bhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop;
if (dout_bhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop;
if (dout_lhs_ls_a != 2'b_11) $stop;
if (dout_lhs_ls_b != 2'b_01) $stop;
if (dout_lhs_rs_a != 2'b_01) $stop;
if (dout_lhs_rs_b != 2'b_11) $stop;
if (dout_rhs_ls_i_23_3 != 23'h_10_08_c0) $stop;
if (dout_rhs_ls_i_23_4 != 23'h_08_10_18) $stop;
if (dout_rhs_ls_q_37_3 != 37'h_04_02_30_10_44) $stop;
if (dout_rhs_ls_q_37_4 != 37'h_02_04_06_08_0a) $stop;
end
if (cyc == 4) begin
if (dout_rhs_ls_i_23_3 != 23'h_7f_ff_ff) $stop;
if (dout_rhs_ls_i_23_4 != 23'h_7f_ff_ff) $stop;
if (dout_rhs_ls_q_37_3 != 37'h_1f_ff_ff_ff_ff) $stop;
if (dout_rhs_ls_q_37_4 != 37'h_1f_ff_ff_ff_ff) $stop;
end
if (cyc == 9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/*
* PS2 Mouse Interface
* Copyright (C) 2010 Donna Polehn <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module ps2_mouse (
input clk, // Clock Input
input reset, // Reset Input
inout ps2_clk, // PS2 Clock, Bidirectional
inout ps2_dat, // PS2 Data, Bidirectional
input [7:0] the_command, // Command to send to mouse
input send_command, // Signal to send
output command_was_sent, // Signal command finished sending
output error_communication_timed_out,
output [7:0] received_data, // Received data
output received_data_en, // If 1 - new data has been received
output start_receiving_data,
output wait_for_incoming_data
);
// --------------------------------------------------------------------
// Internal wires and registers Declarations
// --------------------------------------------------------------------
wire ps2_clk_posedge; // Internal Wires
wire ps2_clk_negedge;
reg [7:0] idle_counter; // Internal Registers
reg ps2_clk_reg;
reg ps2_data_reg;
reg last_ps2_clk;
reg [2:0] ns_ps2_transceiver; // State Machine Registers
reg [2:0] s_ps2_transceiver;
// --------------------------------------------------------------------
// Constant Declarations
// --------------------------------------------------------------------
localparam PS2_STATE_0_IDLE = 3'h0, // states
PS2_STATE_1_DATA_IN = 3'h1,
PS2_STATE_2_COMMAND_OUT = 3'h2,
PS2_STATE_3_END_TRANSFER = 3'h3,
PS2_STATE_4_END_DELAYED = 3'h4;
// --------------------------------------------------------------------
// Finite State Machine(s)
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) s_ps2_transceiver <= PS2_STATE_0_IDLE;
else s_ps2_transceiver <= ns_ps2_transceiver;
end
always @(*) begin
ns_ps2_transceiver = PS2_STATE_0_IDLE; // Defaults
case (s_ps2_transceiver)
PS2_STATE_0_IDLE:
begin
if((idle_counter == 8'hFF) && (send_command == 1'b1))
ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
else if ((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
else ns_ps2_transceiver = PS2_STATE_0_IDLE;
end
PS2_STATE_1_DATA_IN:
begin
// if((received_data_en == 1'b1) && (ps2_clk_posedge == 1'b1))
if((received_data_en == 1'b1)) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_1_DATA_IN;
end
PS2_STATE_2_COMMAND_OUT:
begin
if((command_was_sent == 1'b1) || (error_communication_timed_out == 1'b1))
ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
else ns_ps2_transceiver = PS2_STATE_2_COMMAND_OUT;
end
PS2_STATE_3_END_TRANSFER:
begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else if((ps2_data_reg == 1'b0) && (ps2_clk_posedge == 1'b1))
ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
PS2_STATE_4_END_DELAYED:
begin
if(received_data_en == 1'b1) begin
if(send_command == 1'b0) ns_ps2_transceiver = PS2_STATE_0_IDLE;
else ns_ps2_transceiver = PS2_STATE_3_END_TRANSFER;
end
else ns_ps2_transceiver = PS2_STATE_4_END_DELAYED;
end
default:
ns_ps2_transceiver = PS2_STATE_0_IDLE;
endcase
end
// --------------------------------------------------------------------
// Sequential logic
// --------------------------------------------------------------------
always @(posedge clk) begin
if(reset == 1'b1) begin
last_ps2_clk <= 1'b1;
ps2_clk_reg <= 1'b1;
ps2_data_reg <= 1'b1;
end
else begin
last_ps2_clk <= ps2_clk_reg;
ps2_clk_reg <= ps2_clk;
ps2_data_reg <= ps2_dat;
end
end
always @(posedge clk) begin
if(reset == 1'b1) idle_counter <= 6'h00;
else if((s_ps2_transceiver == PS2_STATE_0_IDLE) && (idle_counter != 8'hFF))
idle_counter <= idle_counter + 6'h01;
else if (s_ps2_transceiver != PS2_STATE_0_IDLE)
idle_counter <= 6'h00;
end
// --------------------------------------------------------------------
// Combinational logic
// --------------------------------------------------------------------
assign ps2_clk_posedge = ((ps2_clk_reg == 1'b1) && (last_ps2_clk == 1'b0)) ? 1'b1 : 1'b0;
assign ps2_clk_negedge = ((ps2_clk_reg == 1'b0) && (last_ps2_clk == 1'b1)) ? 1'b1 : 1'b0;
assign start_receiving_data = (s_ps2_transceiver == PS2_STATE_1_DATA_IN);
assign wait_for_incoming_data = (s_ps2_transceiver == PS2_STATE_3_END_TRANSFER);
// --------------------------------------------------------------------
// Internal Modules
// --------------------------------------------------------------------
ps2_mouse_cmdout mouse_cmdout (
.clk (clk), // Inputs
.reset (reset),
.the_command (the_command),
.send_command (send_command),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_clk (ps2_clk), // Bidirectionals
.ps2_dat (ps2_dat),
.command_was_sent (command_was_sent), // Outputs
.error_communication_timed_out (error_communication_timed_out)
);
ps2_mouse_datain mouse_datain (
.clk (clk), // Inputs
.reset (reset),
.wait_for_incoming_data (wait_for_incoming_data),
.start_receiving_data (start_receiving_data),
.ps2_clk_posedge (ps2_clk_posedge),
.ps2_clk_negedge (ps2_clk_negedge),
.ps2_data (ps2_data_reg),
.received_data (received_data), // Outputs
.received_data_en (received_data_en)
);
endmodule
|
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response Up-Sizer
// Extract SI-side Data from packed and unpacked MI-side data.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_r_upsizer #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_S_AXI_REGISTER = 0,
// Clock output data.
// Range: 0, 1
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con.)
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO = 2,
// Up-Sizing ratio for data.
parameter integer C_RATIO_LOG = 1
// Log2 of Up-Sizing ratio for data.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_fix,
input wire cmd_modified,
input wire cmd_complete_wrap,
input wire cmd_packed_wrap,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask,
input wire [C_S_AXI_BYTES_LOG:0] cmd_step,
input wire [8-1:0] cmd_length,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
output wire cmd_ready,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam integer C_NEVER_PACK = 0;
localparam integer C_DEFAULT_PACK = 1;
localparam integer C_ALWAYS_PACK = 2;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Sub-word handling.
wire sel_first_word;
reg first_word;
reg [C_M_AXI_BYTES_LOG-1:0] current_word_1;
reg [C_M_AXI_BYTES_LOG-1:0] current_word_cmb;
wire [C_M_AXI_BYTES_LOG-1:0] current_word;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_adjusted;
wire last_beat;
wire last_word;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_step_i;
// Sub-word handling for the next cycle.
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word;
reg [C_M_AXI_BYTES_LOG-1:0] pre_next_word_1;
wire [C_M_AXI_BYTES_LOG-1:0] next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] next_word;
// Burst length handling.
wire first_mi_word;
wire [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
// Handle wrap buffering.
wire store_in_wrap_buffer;
reg use_wrap_buffer;
reg wrap_buffer_available;
reg [2-1:0] rresp_wrap_buffer;
// Throttling help signals.
wire next_word_wrap;
wire word_complete_next_wrap;
wire word_complete_next_wrap_ready;
wire word_complete_next_wrap_pop;
wire word_complete_last_word;
wire word_complete_rest;
wire word_complete_rest_ready;
wire word_complete_rest_pop;
wire word_completed;
wire cmd_ready_i;
wire pop_si_data;
wire pop_mi_data;
wire si_stalling;
// Internal signals for MI-side.
reg [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA_I;
wire M_AXI_RLAST_I;
wire M_AXI_RVALID_I;
wire M_AXI_RREADY_I;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
wire [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Determine if a MI side word has been completely used. For FIX transactions
// the MI-side word is used to extract a single data word. This is also true
// for for an upsizer in Expander mode (Never Pack). Unmodified burst also
// only use the MI word to extract a single SI-side word (although with
// different offsets).
// Otherwise is the MI-side word considered to be used when last SI-side beat
// has been extracted or when the last (most significant) SI-side word has
// been extracted from ti MI word.
//
// Data on the SI-side is available when data is being taken from MI-side or
// from wrap buffer.
//
// The command is popped from the command queue once the last beat on the
// SI-side has been ackowledged.
//
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_RATIO_LOG > 1 ) begin : USE_LARGE_UPSIZING
assign cmd_step_i = {{C_RATIO_LOG-1{1'b0}}, cmd_step};
end else begin : NO_LARGE_UPSIZING
assign cmd_step_i = cmd_step;
end
endgenerate
generate
if ( C_FAMILY == "rtl" ||
( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_RTL_WORD_COMPLETED
// Detect when MI-side word is completely used.
assign word_completed = cmd_valid &
( ( cmd_fix ) |
( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( ~cmd_fix & last_word & ~use_wrap_buffer ) |
( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) ) |
( C_PACKING_LEVEL == C_NEVER_PACK ) );
// RTL equivalent of optimized partial extressions (address wrap for next word).
assign word_complete_next_wrap = ( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( C_PACKING_LEVEL == C_NEVER_PACK );
assign word_complete_next_wrap_ready = word_complete_next_wrap & M_AXI_RVALID_I & ~si_stalling;
assign word_complete_next_wrap_pop = word_complete_next_wrap_ready & M_AXI_RVALID_I;
// RTL equivalent of optimized partial extressions (last word and the remaining).
assign word_complete_last_word = last_word & (~cmd_fix & ~use_wrap_buffer);
assign word_complete_rest = word_complete_last_word | cmd_fix |
( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) );
assign word_complete_rest_ready = word_complete_rest & M_AXI_RVALID_I & ~si_stalling;
assign word_complete_rest_pop = word_complete_rest_ready & M_AXI_RVALID_I;
end else begin : USE_FPGA_WORD_COMPLETED
wire sel_word_complete_next_wrap;
wire sel_word_completed;
wire sel_m_axi_rready;
wire sel_word_complete_last_word;
wire sel_word_complete_rest;
// Optimize next word address wrap branch of expression.
//
generic_baseblocks_v2_1_comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE({C_M_AXI_BYTES_LOG{1'b0}}),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) next_word_wrap_inst
(
.CIN(1'b1),
.S(sel_first_word),
.A(pre_next_word_1),
.B(cmd_next_word),
.COUT(next_word_wrap)
);
assign sel_word_complete_next_wrap = ~cmd_fix & ~cmd_complete_wrap;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_inst
(
.CIN(next_word_wrap),
.S(sel_word_complete_next_wrap),
.COUT(word_complete_next_wrap)
);
assign sel_m_axi_rready = cmd_valid & S_AXI_RREADY_I;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_ready_inst
(
.CIN(word_complete_next_wrap),
.S(sel_m_axi_rready),
.COUT(word_complete_next_wrap_ready)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_pop_inst
(
.CIN(word_complete_next_wrap_ready),
.S(M_AXI_RVALID_I),
.COUT(word_complete_next_wrap_pop)
);
// Optimize last word and "rest" branch of expression.
//
assign sel_word_complete_last_word = ~cmd_fix & ~use_wrap_buffer;
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_last_word_inst
(
.CIN(last_word),
.S(sel_word_complete_last_word),
.COUT(word_complete_last_word)
);
assign sel_word_complete_rest = cmd_fix | ( ~cmd_modified & ( C_PACKING_LEVEL == C_DEFAULT_PACK ) );
generic_baseblocks_v2_1_carry_or #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_inst
(
.CIN(word_complete_last_word),
.S(sel_word_complete_rest),
.COUT(word_complete_rest)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_ready_inst
(
.CIN(word_complete_rest),
.S(sel_m_axi_rready),
.COUT(word_complete_rest_ready)
);
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_pop_inst
(
.CIN(word_complete_rest_ready),
.S(M_AXI_RVALID_I),
.COUT(word_complete_rest_pop)
);
// Combine the two branches to generate the full signal.
assign word_completed = word_complete_next_wrap | word_complete_rest;
end
endgenerate
// Only propagate Valid when there is command information available.
assign M_AXI_RVALID_I = M_AXI_RVALID & cmd_valid;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_CTRL
// Pop word from MI-side.
assign M_AXI_RREADY_I = word_completed & S_AXI_RREADY_I;
// Get MI-side data.
assign pop_mi_data = M_AXI_RVALID_I & M_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & S_AXI_RLAST_I & pop_si_data;
end else begin : USE_FPGA_CTRL
wire sel_cmd_ready;
assign M_AXI_RREADY_I = word_complete_next_wrap_ready | word_complete_rest_ready;
assign pop_mi_data = word_complete_next_wrap_pop | word_complete_rest_pop;
assign sel_cmd_ready = cmd_valid & pop_si_data;
generic_baseblocks_v2_1_carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) cmd_ready_inst
(
.CIN(S_AXI_RLAST_I),
.I(sel_cmd_ready),
.O(cmd_ready_i)
);
end
endgenerate
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = ( M_AXI_RVALID_I | use_wrap_buffer );
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Assign external signals.
assign M_AXI_RREADY = M_AXI_RREADY_I;
assign cmd_ready = cmd_ready_i;
// Detect when SI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data extraction:
//
// Current address is taken form the command buffer for the first data beat
// to handle unaligned Read transactions. After this is the extraction
// address usually calculated from this point.
// FIX transactions uses the same word address for all data beats.
//
// Next word address is generated as current word plus the current step
// size, with masking to facilitate sub-sized wraping. The Mask is all ones
// for normal wraping, and less when sub-sized wraping is used.
//
// The calculated word addresses (current and next) is offseted by the
// current Offset. For sub-sized transaction the Offset points to the least
// significant address of the included data beats. (The least significant
// word is not necessarily the first data to be extracted, consider WRAP).
// Offset is only used for sub-sized WRAP transcation that are Complete.
//
// First word is active during the first SI-side data beat.
//
// First MI is set while the entire first MI-side word is processed.
//
// The transaction length is taken from the command buffer combinatorialy
// during the First MI cycle. For each used MI word it is decreased until
// Last beat is reached.
//
// Last word is determined depending on the current command, i.e. modified
// burst has to scale since multiple words could be packed into one MI-side
// word.
// Last word is 1:1 for:
// FIX, when burst support is disabled or unmodified for Normal Pack.
// Last word is scaled for all other transactions.
//
/////////////////////////////////////////////////////////////////////////////
// Select if the offset comes from command queue directly or
// from a counter while when extracting multiple SI words per MI word
assign sel_first_word = first_word | cmd_fix;
assign current_word = sel_first_word ? cmd_first_word :
current_word_1;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_NEXT_WORD
// Calculate next word.
assign pre_next_word_i = ( next_word_i + cmd_step_i );
// Calculate next word.
assign next_word_i = sel_first_word ? cmd_next_word :
pre_next_word_1;
end else begin : USE_FPGA_NEXT_WORD
wire [C_M_AXI_BYTES_LOG-1:0] next_sel;
wire [C_M_AXI_BYTES_LOG:0] next_carry_local;
// Assign input to local vectors.
assign next_carry_local[0] = 1'b0;
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
LUT6_2 # (
.INIT(64'h5A5A_5A66_F0F0_F0CC)
) LUT6_2_inst (
.O6(next_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(next_word_i[bit_cnt]), // 5-LUT output (1-bit)
.I0(cmd_step_i[bit_cnt]), // LUT input (1-bit)
.I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)
.I2(cmd_next_word[bit_cnt]), // LUT input (1-bit)
.I3(first_word), // LUT input (1-bit)
.I4(cmd_fix), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY next_carry_inst
(
.O (next_carry_local[bit_cnt+1]),
.CI (next_carry_local[bit_cnt]),
.DI (cmd_step_i[bit_cnt]),
.S (next_sel[bit_cnt])
);
XORCY next_xorcy_inst
(
.O(pre_next_word_i[bit_cnt]),
.CI(next_carry_local[bit_cnt]),
.LI(next_sel[bit_cnt])
);
end // end for bit_cnt
end
endgenerate
// Calculate next word.
assign next_word = next_word_i & cmd_mask;
assign pre_next_word = pre_next_word_i & cmd_mask;
// Calculate the word address with offset.
assign current_word_adjusted = current_word | cmd_offset;
// Prepare next word address.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
current_word_1 <= 'b0;
pre_next_word_1 <= {C_M_AXI_BYTES_LOG{1'b0}};
end else begin
if ( pop_si_data ) begin
if ( last_word ) begin
// Prepare for next access.
first_word <= 1'b1;
end else begin
first_word <= 1'b0;
end
current_word_1 <= next_word;
pre_next_word_1 <= pre_next_word;
end
end
end
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_LENGTH
reg [8-1:0] length_counter_q;
reg first_mi_word_q;
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word_q <= 1'b1;
length_counter_q <= 8'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_RLAST ) begin
first_mi_word_q <= 1'b1;
end else begin
first_mi_word_q <= 1'b0;
end
length_counter_q <= next_length_counter;
end
end
end
assign first_mi_word = first_mi_word_q;
assign length_counter_1 = length_counter_q;
end else begin : USE_FPGA_LENGTH
wire [8-1:0] length_counter_i;
wire [8-1:0] length_sel;
wire [8-1:0] length_di;
wire [8:0] length_local_carry;
// Assign input to local vectors.
assign length_local_carry[0] = 1'b0;
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6_2 # (
.INIT(64'h333C_555A_FFF0_FFF0)
) LUT6_2_inst (
.O6(length_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(length_di[bit_cnt]), // 5-LUT output (1-bit)
.I0(length_counter_1[bit_cnt]), // LUT input (1-bit)
.I1(cmd_length[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_next_wrap_pop), // LUT input (1-bit)
.I3(word_complete_rest_pop), // LUT input (1-bit)
.I4(first_mi_word), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY and_inst
(
.O (length_local_carry[bit_cnt+1]),
.CI (length_local_carry[bit_cnt]),
.DI (length_di[bit_cnt]),
.S (length_sel[bit_cnt])
);
XORCY xorcy_inst
(
.O(length_counter_i[bit_cnt]),
.CI(length_local_carry[bit_cnt]),
.LI(length_sel[bit_cnt])
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(length_counter_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(length_counter_i[bit_cnt]) // Data input
);
end // end for bit_cnt
wire first_mi_word_i;
LUT6 # (
.INIT(64'hAAAC_AAAC_AAAC_AAAC)
) LUT6_cnt_inst (
.O(first_mi_word_i), // 6-LUT output (1-bit)
.I0(M_AXI_RLAST), // LUT input (1-bit)
.I1(first_mi_word), // LUT input (1-bit)
.I2(word_complete_next_wrap_pop), // LUT input (1-bit)
.I3(word_complete_rest_pop), // LUT input (1-bit)
.I4(1'b1), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
FDSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) FDRE_inst (
.Q(first_mi_word), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.S(ARESET), // Synchronous reset input
.D(first_mi_word_i) // Data input
);
end
endgenerate
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_LAST_WORD
// Detect last beat in a burst.
assign last_beat = ( length_counter == 8'b0 );
// Determine if this last word that shall be extracted from this MI-side word.
assign last_word = ( last_beat & ( current_word == cmd_last_word ) & ~wrap_buffer_available & ( current_word == cmd_last_word ) ) |
( use_wrap_buffer & ( current_word == cmd_last_word ) ) |
( last_beat & ( current_word == cmd_last_word ) & ( C_PACKING_LEVEL == C_NEVER_PACK ) );
end else begin : USE_FPGA_LAST_WORD
wire sel_last_word;
wire last_beat_ii;
comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE(8'b0),
.C_DATA_WIDTH(8)
) last_beat_inst
(
.CIN(1'b1),
.S(first_mi_word),
.A(length_counter_1),
.B(cmd_length),
.COUT(last_beat)
);
if ( C_PACKING_LEVEL != C_NEVER_PACK ) begin : USE_FPGA_PACK
//
//
wire sel_last_beat;
wire last_beat_i;
assign sel_last_beat = ~wrap_buffer_available;
carry_and #
(
.C_FAMILY(C_FAMILY)
) last_beat_inst_1
(
.CIN(last_beat),
.S(sel_last_beat),
.COUT(last_beat_i)
);
carry_or #
(
.C_FAMILY(C_FAMILY)
) last_beat_wrap_inst
(
.CIN(last_beat_i),
.S(use_wrap_buffer),
.COUT(last_beat_ii)
);
end else begin : NO_PACK
assign last_beat_ii = last_beat;
end
comparator_sel #
(
.C_FAMILY(C_FAMILY),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) last_beat_curr_word_inst
(
.CIN(last_beat_ii),
.S(sel_first_word),
.A(current_word_1),
.B(cmd_first_word),
.V(cmd_last_word),
.COUT(last_word)
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle wrap buffer:
//
// The wrap buffer is used to move data around in an unaligned WRAP
// transaction. The requested read address has been rounded down, meaning
// that parts of the first MI-side data beat has to be delayed for later use.
// The extraction starts at the origian unaligned address, the remaining data
// is stored in the wrap buffer to be extracted after the last MI-side data
// beat has been fully processed.
// For example: an 32bit to 64bit read upsizing @ 0x4 will request a MI-side
// read WRAP transaction 0x0. The 0x4 data word is used at once and the 0x0
// word is delayed to be used after all data in the last MI-side beat has
// arrived.
//
/////////////////////////////////////////////////////////////////////////////
// Save data to be able to perform buffer wraping.
assign store_in_wrap_buffer = M_AXI_RVALID_I & cmd_packed_wrap & first_mi_word & ~use_wrap_buffer;
// Mark that there are data available for wrap buffering.
always @ (posedge ACLK) begin
if (ARESET) begin
wrap_buffer_available <= 1'b0;
end else begin
if ( store_in_wrap_buffer & word_completed & pop_si_data ) begin
wrap_buffer_available <= 1'b1;
end else if ( last_beat & word_completed & pop_si_data ) begin
wrap_buffer_available <= 1'b0;
end
end
end
// Start using the wrap buffer.
always @ (posedge ACLK) begin
if (ARESET) begin
use_wrap_buffer <= 1'b0;
end else begin
if ( wrap_buffer_available & last_beat & word_completed & pop_si_data ) begin
use_wrap_buffer <= 1'b1;
end else if ( cmd_ready_i ) begin
use_wrap_buffer <= 1'b0;
end
end
end
// Store data in wrap buffer.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_RDATA_I <= {C_M_AXI_DATA_WIDTH{1'b0}};
rresp_wrap_buffer <= 2'b0;
end else begin
if ( store_in_wrap_buffer ) begin
M_AXI_RDATA_I <= M_AXI_RDATA;
rresp_wrap_buffer <= M_AXI_RRESP;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Select the SI-side word to read.
//
// Everything must be multiplexed since the next transfer can be arriving
// with a different set of signals while the wrap buffer is still being
// processed for the current transaction.
//
// Non modifiable word has a 1:1 ratio, i.e. only one SI-side word is
// generated per MI-side word.
// Data is taken either directly from the incomming MI-side data or the
// wrap buffer (for packed WRAP).
//
// Last need special handling since it is the last SI-side word generated
// from the MI-side word.
//
/////////////////////////////////////////////////////////////////////////////
// ID, RESP and USER has to be multiplexed.
assign S_AXI_RID_I = cmd_id;
assign S_AXI_RRESP_I = ( use_wrap_buffer ) ?
rresp_wrap_buffer :
M_AXI_RRESP;
// Data has to be multiplexed.
generate
if ( C_RATIO == 1 ) begin : SINGLE_WORD
assign S_AXI_RDATA_I = ( use_wrap_buffer ) ?
M_AXI_RDATA_I :
M_AXI_RDATA;
end else begin : MULTIPLE_WORD
// Get the ratio bits (MI-side words vs SI-side words).
wire [C_RATIO_LOG-1:0] current_index;
assign current_index = current_word_adjusted[C_M_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG];
assign S_AXI_RDATA_I = ( use_wrap_buffer ) ?
M_AXI_RDATA_I[current_index * C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] :
M_AXI_RDATA[current_index * C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH];
end
endgenerate
// Generate the true last flag including "keep" while using wrap buffer.
assign M_AXI_RLAST_I = ( M_AXI_RLAST | use_wrap_buffer );
// Handle last flag, i.e. set for SI-side last word.
assign S_AXI_RLAST_I = last_word;
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_S_AXI_REGISTER ) begin : USE_REGISTER
reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID_q;
reg [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_q;
reg [2-1:0] S_AXI_RRESP_q;
reg S_AXI_RLAST_q;
reg S_AXI_RVALID_q;
reg S_AXI_RREADY_q;
// Register SI-side Data.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_RID_q <= {C_AXI_ID_WIDTH{1'b0}};
S_AXI_RDATA_q <= {C_S_AXI_DATA_WIDTH{1'b0}};
S_AXI_RRESP_q <= 2'b0;
S_AXI_RLAST_q <= 1'b0;
S_AXI_RVALID_q <= 1'b0;
end else begin
if ( S_AXI_RREADY_I ) begin
S_AXI_RID_q <= S_AXI_RID_I;
S_AXI_RDATA_q <= S_AXI_RDATA_I;
S_AXI_RRESP_q <= S_AXI_RRESP_I;
S_AXI_RLAST_q <= S_AXI_RLAST_I;
S_AXI_RVALID_q <= S_AXI_RVALID_I;
end
end
end
assign S_AXI_RID = S_AXI_RID_q;
assign S_AXI_RDATA = S_AXI_RDATA_q;
assign S_AXI_RRESP = S_AXI_RRESP_q;
assign S_AXI_RLAST = S_AXI_RLAST_q;
assign S_AXI_RVALID = S_AXI_RVALID_q;
assign S_AXI_RREADY_I = ( S_AXI_RVALID_q & S_AXI_RREADY) | ~S_AXI_RVALID_q;
end else begin : NO_REGISTER
// Combinatorial SI-side Data.
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
end
endgenerate
endmodule
|
/*
* Copyright (C) 2009 Onno Kortmann <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* THIS FILE HAS BEEN AUTOMATICALLY GENERATED FROM avr_tmpl.v.
* --- DO NOT EDIT MANUALLY! ---
*/
module ATtiny25(clk, PB);
parameter progfile="UNSPECIFIED";
input clk;
inout [7:0] PB;
integer handle;
defparam core.progfile=progfile;
defparam core.name="attiny25";
AVRCORE core(clk);
avr_pin #("B0") pb0(PB[0]);
avr_pin #("B1") pb1(PB[1]);
avr_pin #("B2") pb2(PB[2]);
avr_pin #("B3") pb3(PB[3]);
avr_pin #("B4") pb4(PB[4]);
avr_pin #("B5") pb5(PB[5]);
endmodule
|
`include "nandc_def.vh"
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module nandc_ecc_inline_cpu #(
// base offset on the CPU wishbone bus that everything is located at
parameter WBCPU_FLASH_BASEADDR = `WBCPU_FLASH_BASEADDR,
// the offset to place CPU wishbone registers at on the bus
parameter WBCPU_REG_BASEADDR = `WBCPU_REG_BASEADDR,
// base offset on the NAND controller wishbone bus that everything is located at
parameter WB_FLASH_BASEADDR = `WB_FLASH_BASEADDR,
// the offset where the NAND controller wishbone registers are on the bus
parameter WB_REG_BASEADDR = `WB_REG_BASEADDR,
// the start block that this nand controller is able to address
parameter WB_FLASH_S = `WB_FLASH_S,
// the number of blocks this nand controller is able to address (out of 1024)
parameter WB_FLASH_N = `WB_FLASH_N
) (
input wire wb_clk, // clock - bus clock
input wire wb_rst, // reset synchronous with wb_clk
input wire [2:0] wbs_cti_i, // type - cycle type identifier, supports either 000 "Classic cycle" or 010 "Incrementing burst cycle"
input wire [1:0] wbs_bte_i, // exten - burst type extension, only supports 00 "Linear burst"
input wire [31:0] wbs_adr_i, // addr - bus address
output reg [31:0] wbs_dat_o, // data - write data output
input wire [31:0] wbs_dat_i, // data - write data input
input wire [3:0] wbs_sel_i, // select - 8-bit enable for data bus
input wire wbs_cyc_i, // cycle - valid bus cycle is in progress
input wire wbs_stb_i, // strobe - slave is selected
input wire wbs_we_i, // write - bus cycle is in write mode
output reg wbs_ack_o, // ack - end of a normal bus cycle
output reg [2:0] wbm_cti_o, // type - cycle type identifier, supports either 000 "Classic cycle" or 010 "Incrementing burst cycle"
output reg [1:0] wbm_bte_o, // exten - burst type extension, only supports 00 "Linear burst"
output reg [31:0] wbm_adr_o, // addr - bus address
input wire [31:0] wbm_dat_i, // data - write data input
output reg [31:0] wbm_dat_o, // data - write data output
output reg [3:0] wbm_sel_o, // select - 8-bit enable for data bus
output reg wbm_cyc_o, // cycle - valid bus cycle is in progress
output reg wbm_stb_o, // strobe - slave is selected
output reg wbm_we_o, // write - bus cycle is in write mode
input wire wbm_ack_i // ack - end of a normal bus cycle
);
`include "wb_common.v"
reg [31:0] adr_r;
wire valid = wbs_cyc_i & wbs_stb_i;
reg valid_r;
wire new_cycle = valid & !valid_r;
wire [31:0] next_adr = wb_next_adr(adr_r, wbs_cti_i, wbs_bte_i, 32);
wire [31:0] adr = new_cycle ? wbs_adr_i : next_adr;
always @(posedge wb_clk) begin
if(wb_rst) begin
adr_r <= 'h0;
valid_r <= 'b0;
wbs_ack_o <= 'b0;
end else begin
adr_r <= adr;
valid_r <= valid;
wbs_ack_o <= valid & (!((wbs_cti_i == 3'b000) | (wbs_cti_i == 3'b111)) | !wbs_ack_o);
end
end
wire ram_we = wbs_we_i & valid & wbs_ack_o;
reg [31:0] wbs_dat_o_r;
reg [31:0] wbm_dat_o_r;
`include "nandc_const.vh"
// Wishbone addresses on the CPU bus
//
// The main difference with the CPU bus is that the FLASH space is just the size of 1 page
// and acts as a scratch buffer for reads and writes. To initiate a READ or WRITE operation
// you write the address you wish to read/write to to the READ or WRITE address on the bus.
// To determine if the last operation (READ/WRITE/ERASE/STATUS/etc) is finished, you must
// read a 1 for the READY bit at the STATUS address before initiating another command:
//
// bit 0 - READY: 1 = Operation complete, 0 = Bus Busy, any transactions initiated while busy will be ignored
// bit 1 - STATUS: 1 = The last STATUS command reported back an error, 0 = No errors
//
// If you wish to read the STATUS of the last PROG or ERASE operation, you must write to
// the STATUS register and then poll the STATUS register until READY = 1 at which point
// the STATUS bit will reflect the result of the STATUS command.
//
parameter WBCPU_FLASH_HIGHADDR = WBCPU_FLASH_BASEADDR + (1 << `FCOLUMNS);
parameter WBCPU_PAGE_OFFSET_BASEADDR = WBCPU_REG_BASEADDR + `WB_PAGE_OFFSET_OFF;
parameter WBCPU_SPARE_SPACE_WR_BASEADDR = WBCPU_REG_BASEADDR + `WB_SPARE_SPACE_WR_OFF;
parameter WBCPU_SPARE_SPACE_RD_BASEADDR = WBCPU_REG_BASEADDR + `WB_SPARE_SPACE_RD_OFF;
parameter WBCPU_ERASE_BASEADDR = WBCPU_REG_BASEADDR + `WB_ERASE_OFF;
parameter WBCPU_STATUS_BASEADDR = WBCPU_REG_BASEADDR + `WB_STATUS_OFF;
parameter WBCPU_WRITE_BASEADDR = WBCPU_REG_BASEADDR + `WB_WRITE_OFF;
parameter WBCPU_READ_BASEADDR = WBCPU_REG_BASEADDR + `WB_READ_OFF;
// Wishbone addreses on the NANDC bus
parameter WB_FLASH_HIGHADDR = WB_FLASH_BASEADDR + (WB_FLASH_N << (`FPAGES + `FCOLUMNS));
parameter WB_FLASH_N_BASEADDR = 0;
parameter WB_FLASH_N_HIGHADDR = WB_FLASH_N << (`FPAGES + `FCOLUMNS);
parameter WB_PAGE_OFFSET_BASEADDR = WB_REG_BASEADDR + `WB_PAGE_OFFSET_OFF;
parameter WB_SPARE_SPACE_WR_BASEADDR = WB_REG_BASEADDR + `WB_SPARE_SPACE_WR_OFF;
parameter WB_SPARE_SPACE_RD_BASEADDR = WB_REG_BASEADDR + `WB_SPARE_SPACE_RD_OFF;
parameter WB_ERASE_BASEADDR = WB_REG_BASEADDR + `WB_ERASE_OFF;
parameter WB_STATUS_BASEADDR = WB_REG_BASEADDR + `WB_STATUS_OFF;
reg [31:0] data_i;
reg valid_i, sof_i, eof_i;
wire [31:0] data_o;
wire valid_o, sof_o, eof_o;
wire [23:0] ecc_o;
hamm_4096x1_512x32 hamm_4096x1_512x32 (
.clk ( wb_clk ),
.rst ( wb_rst ),
.data_i ( data_i ),
.valid_i ( valid_i ),
.sof_i ( sof_i ),
.eof_i ( eof_i ),
.data_o ( data_o ),
.valid_o ( valid_o ),
.sof_o ( sof_o ),
.eof_o ( eof_o ),
.ecc_o ( ecc_o )
);
reg a_wr;
reg [`FCOLUMNS-2:0] a_addr;
reg [31:0] a_din;
wire [31:0] a_dout;
reg b_wr;
reg [`FCOLUMNS-2:0] b_addr;
wire [31:0] b_dout;
parameter [4:0] ST_IDLE = 'd0,
ST_IDLE_0 = 'd1,
ST_ERASE = 'd2,
ST_STATUS = 'd3,
ST_WBWRITE = 'd4,
ST_WBWRITE_0 = 'd5,
ST_WBWRITE_1 = 'd6,
ST_WBWRITE_2 = 'd7,
ST_WBWRITE_3 = 'd8,
ST_WBWRITE_4 = 'd9,
ST_WBWRITE_5 = 'd10,
ST_WBREAD = 'd11,
ST_WBREAD_0 = 'd12,
ST_WBREAD_1 = 'd13,
ST_WBREAD_2 = 'd14,
ST_WBREAD_3 = 'd15,
ST_WBREAD_4 = 'd16;
reg page_offset;
reg [63:0] spare_space_wr, spare_space_rd;
reg [23:0] spare_space_ecc, spare_space_ecc_cmp;
reg spare_space_erased;
reg [1:0] ecc_addr;
reg [23:0] ecc0, ecc1, ecc2, ecc3;
reg [23:0] ecc0_cmp, ecc1_cmp, ecc2_cmp, ecc3_cmp;
reg [7:0] i;
reg [31:0] data, addr;
reg [13:0] fix_bit;
reg ready;
reg status;
reg [4:0] hstate;
always @(posedge wb_clk) begin
if(wb_rst) begin
wbs_dat_o_r <= 'h0;
wbm_cti_o <= WB_CTI_CLASSIC;
wbm_bte_o <= WB_BTE_LINEAR;
wbm_adr_o <= 'h0;
wbm_dat_o_r <= 'h0;
wbm_sel_o <= 'h0;
wbm_cyc_o <= 0;
wbm_stb_o <= 0;
wbm_we_o <= 0;
page_offset <= 0;
spare_space_wr <= 'h0;
spare_space_rd <= 'h0;
spare_space_ecc <= 'h0;
spare_space_ecc_cmp <= 'h0;
spare_space_erased <= 0;
ecc_addr <= 'h0;
ecc0 <= 'h0;
ecc1 <= 'h0;
ecc2 <= 'h0;
ecc3 <= 'h0;
ecc0_cmp <= 'h0;
ecc1_cmp <= 'h0;
ecc2_cmp <= 'h0;
ecc3_cmp <= 'h0;
i <= 'h0;
data <= 'h0;
fix_bit <= 'h0;
ready <= 1;
status <= 0;
hstate <= ST_IDLE;
end else begin
case(hstate)
ST_IDLE: begin
wbm_cti_o <= WB_CTI_CLASSIC;
wbm_bte_o <= WB_BTE_LINEAR;
wbm_adr_o <= 'h0;
wbm_dat_o_r <= 'h0;
wbm_sel_o <= 'h0;
wbm_stb_o <= 0;
wbm_we_o <= 0;
valid_i <= 0;
sof_i <= 0;
eof_i <= 0;
i <= 'h0;
data <= 'h0;
ready <= 1;
hstate <= ST_IDLE_0;
end
ST_IDLE_0: begin
if(valid) begin
if(wbs_we_i & wbs_ack_o) begin
case(adr_r)
// set ECC controller registers
WBCPU_PAGE_OFFSET_BASEADDR: begin
page_offset <= wbs_dat_i[0];
hstate <= ST_IDLE;
end
WBCPU_SPARE_SPACE_WR_BASEADDR + 'h0: begin
spare_space_wr[31:0] <= wbs_dat_i;
hstate <= ST_IDLE;
end
WBCPU_SPARE_SPACE_WR_BASEADDR + 'h4: begin
spare_space_wr[63:32] <= wbs_dat_i;
hstate <= ST_IDLE;
end
WBCPU_ERASE_BASEADDR: begin
// make sure we're erasing a block in our range
if(wbs_dat_i < WB_FLASH_N) begin
// offset erase by WB_FLASH_S
wbm_dat_o_r <= wbs_dat_i + WB_FLASH_S;
ready <= 0;
hstate <= ST_ERASE;
end else begin
hstate <= ST_IDLE;
end
end
WBCPU_STATUS_BASEADDR: begin
ready <= 0;
hstate <= ST_STATUS;
end
// handle flash read requests within our address boundary
WBCPU_READ_BASEADDR: begin
if((wbs_dat_i >= WB_FLASH_N_BASEADDR) && (wbs_dat_i <= WB_FLASH_N_HIGHADDR)) begin
// if we're reading from the correct range, then construct new address offset by WB_FLASH_S
wbm_adr_o <= {wbs_dat_i[31:`FALL+1], wbs_dat_i[`FALL-1:`FCOLUMNS], {`FCOLUMNS+1{1'b0}}} + {WB_FLASH_S, {`FCOLUMNS + `FPAGES + 1{1'b0}}};
ready <= 0;
hstate <= ST_WBREAD;
end else begin
hstate <= ST_IDLE;
end
end
// handle flash write requests within our address boundary
WBCPU_WRITE_BASEADDR: begin
if((wbs_dat_i >= WB_FLASH_N_BASEADDR) && (wbs_dat_i <= WB_FLASH_N_HIGHADDR) &&
// don't allow the user to write when page_offset is set
!page_offset) begin
// if we're writing to the correct range, then construct new address offset by WB_FLASH_S
wbm_adr_o <= {wbs_dat_i[31:`FALL+1], wbs_dat_i[`FALL-1:`FCOLUMNS], {`FCOLUMNS+1{1'b0}}} + {WB_FLASH_S, {`FCOLUMNS + `FPAGES + 1{1'b0}}};
ready <= 0;
hstate <= ST_WBWRITE;
end else begin
hstate <= ST_IDLE;
end
end
endcase
end else if(!wbs_we_i) begin
case(adr)
// read back ECC controller registers
WBCPU_PAGE_OFFSET_BASEADDR: begin
wbs_dat_o_r <= {31'h0, page_offset};
hstate <= ST_IDLE;
end
WBCPU_SPARE_SPACE_WR_BASEADDR + 'h0: begin
wbs_dat_o_r <= spare_space_wr[31:0];
hstate <= ST_IDLE;
end
WBCPU_SPARE_SPACE_WR_BASEADDR + 'h4: begin
wbs_dat_o_r <= spare_space_wr[63:32];
hstate <= ST_IDLE;
end
WBCPU_SPARE_SPACE_RD_BASEADDR + 'h0: begin
wbs_dat_o_r <= spare_space_erased ? 32'hffffffff : spare_space_rd[31:0];
hstate <= ST_IDLE;
end
WBCPU_SPARE_SPACE_RD_BASEADDR + 'h4: begin
wbs_dat_o_r <= spare_space_erased ? 32'hffffffff : spare_space_rd[63:32];
hstate <= ST_IDLE;
end
WBCPU_STATUS_BASEADDR: begin
wbs_dat_o_r <= {30'h0, status, ready};
hstate <= ST_IDLE;
end
endcase
end
end
end
//
// ERASE FORWARD
//
// forward this transaction until we get an ack
ST_ERASE: begin
if(!wbm_ack_i) begin
wbm_cti_o <= WB_CTI_CLASSIC;
wbm_bte_o <= WB_BTE_LINEAR;
wbm_adr_o <= WB_ERASE_BASEADDR;
wbm_sel_o <= 1;
wbm_cyc_o <= 1;
wbm_stb_o <= 1;
wbm_we_o <= 1;
end else begin
wbm_cti_o <= WB_CTI_CLASSIC;
wbm_bte_o <= WB_BTE_LINEAR;
wbm_adr_o <= 'h0;
wbm_dat_o_r <= 'h0;
wbm_sel_o <= 'h0;
wbm_cyc_o <= 0;
wbm_stb_o <= 0;
wbm_we_o <= 0;
hstate <= ST_IDLE;
end
end
//
// STATUS FORWARD
//
// forward this transaction until we get an ack
ST_STATUS: begin
if(!wbm_ack_i) begin
wbm_cti_o <= WB_CTI_CLASSIC;
wbm_bte_o <= WB_BTE_LINEAR;
wbm_adr_o <= WB_STATUS_BASEADDR;
wbm_sel_o <= 1;
wbm_cyc_o <= 1;
wbm_stb_o <= 1;
wbm_we_o <= 0;
end else begin
wbm_cti_o <= WB_CTI_CLASSIC;
wbm_bte_o <= WB_BTE_LINEAR;
wbm_adr_o <= 'h0;
wbm_dat_o_r <= 'h0;
wbm_sel_o <= 'h0;
wbm_cyc_o <= 0;
wbm_stb_o <= 0;
wbm_we_o <= 0;
status <= wbm_dat_i[0];
hstate <= ST_IDLE;
end
end
//
// WRITE WITH ECC
//
// forward this transaction to the slave and compute and add ecc while we're doing it
ST_WBWRITE: begin
// insert dummy cycle to read data from BRAM buffer
hstate <= ST_WBWRITE_0;
end
ST_WBWRITE_0: begin
wbm_cti_o <= WB_CTI_INCR_BURST;
wbm_bte_o <= WB_BTE_LINEAR;
wbm_sel_o <= 'b1111;
wbm_cyc_o <= 1;
wbm_we_o <= 1;
if(wbm_ack_i) begin
// drop strobe when we have an ack
wbm_stb_o <= 0;
wbm_adr_o <= wbm_adr_o + 'h4;
data_i <= wbm_dat_o;
valid_i <= 1;
sof_i <= wbm_adr_o[8:2] == {9-2{1'b0}};
eof_i <= wbm_adr_o[8:2] == {9-2{1'b1}};
ecc_addr <= wbm_adr_o[10:9];
// if we're in the last word of our 512-byte block then save ECC
if((wbm_adr_o[8:2] == {9-2{1'b1}}))
hstate <= ST_WBWRITE_1;
end else begin
// otherwise keep strobe high
wbm_stb_o <= 1;
valid_i <= 0;
sof_i <= 0;
eof_i <= 0;
end
end
ST_WBWRITE_1: begin
valid_i <= 0;
sof_i <= 0;
eof_i <= 0;
if(eof_o) begin
case(ecc_addr)
0: ecc0 <= ecc_o;
1: ecc1 <= ecc_o;
2: ecc2 <= ecc_o;
3: ecc3 <= ecc_o;
endcase
// if we're in the last 512-byte block, then also write ecc, spare_space, and spare_space_ecc
if(ecc_addr == 3) begin
hstate <= ST_WBWRITE_2;
// if we're not in the last 512-byte block, then ack and return to idle state
end else begin
hstate <= ST_WBWRITE_0;
end
end
end
ST_WBWRITE_2: begin
data_i <= spare_space_wr[31:0];
valid_i <= 1;
sof_i <= 1;
eof_i <= 0;
hstate <= ST_WBWRITE_3;
end
ST_WBWRITE_3: begin
data_i <= spare_space_wr[63:32];
valid_i <= 1;
sof_i <= 0;
eof_i <= 1;
hstate <= ST_WBWRITE_4;
end
ST_WBWRITE_4: begin
data_i <= 'h0;
valid_i <= 0;
sof_i <= 0;
eof_i <= 0;
if(eof_o) begin
wbm_adr_o <= wbm_adr_o + 'h4;
spare_space_ecc <= ecc_o;
i <= 0;
hstate <= ST_WBWRITE_5;
end
end
ST_WBWRITE_5: begin
case(wbm_ack_i ? i + 'h1 : i)
0: wbm_dat_o_r <= {ecc1[7:0], ecc0[23:0]};
1: wbm_dat_o_r <= {ecc2[15:0], ecc1[23:8]};
2: wbm_dat_o_r <= {ecc3[23:0], ecc2[23:16]};
3: wbm_dat_o_r <= {spare_space_wr[31:0]};
4: wbm_dat_o_r <= {spare_space_wr[63:32]};
5: wbm_dat_o_r <= {20'h0, spare_space_ecc[17:12], spare_space_ecc[5:0]};
endcase
wbm_cti_o <= i == 5 ? WB_CTI_EOB : WB_CTI_INCR_BURST;
wbm_bte_o <= WB_BTE_LINEAR;
wbm_sel_o <= 'b1111;
wbm_cyc_o <= 1;
wbm_stb_o <= 1;
wbm_we_o <= 1;
if(wbm_ack_i) begin
wbm_adr_o <= wbm_adr_o + 'h4;
if(i >= 5) begin
wbm_cyc_o <= 0;
hstate <= ST_IDLE;
end else
i <= i + 1;
end
end
//
// READ WITH ECC
//
ST_WBREAD: begin
// start read from address 0 of the selected page
hstate <= ST_WBREAD_0;
end
// perform read cycle
ST_WBREAD_0, ST_WBREAD_1: begin if(ST_WBREAD_0) begin
wbm_cti_o <= addr_page_end(wbm_adr_o) ? WB_CTI_EOB : WB_CTI_INCR_BURST;
wbm_bte_o <= WB_BTE_LINEAR;
wbm_sel_o <= 'b1111;
wbm_cyc_o <= 1;
wbm_stb_o <= 1;
wbm_we_o <= 0;
if(wbm_ack_i) begin
// calculate ECC on read data
data_i <= wbm_dat_i;
valid_i <= !wbm_adr_o[`FCOLUMNS] || (wbm_adr_o[5:2] == 3) || (wbm_adr_o[5:2] == 4);
sof_i <= (!wbm_adr_o[`FCOLUMNS] && (wbm_adr_o[8:2] == {9-2{1'b0}})) || (wbm_adr_o[`FCOLUMNS] && wbm_adr_o[5:2] == 3);
eof_i <= (!wbm_adr_o[`FCOLUMNS] && (wbm_adr_o[8:2] == {9-2{1'b1}})) || (wbm_adr_o[`FCOLUMNS] && wbm_adr_o[5:2] == 4);
if(wbm_adr_o[`FCOLUMNS]) begin
case(wbm_adr_o[5:2])
0: begin
ecc0_cmp[23:0] <= wbm_dat_i[23:0];
ecc1_cmp[7:0] <= wbm_dat_i[31:24];
end
1: begin
ecc1_cmp[23:8] <= wbm_dat_i[15:0];
ecc2_cmp[15:0] <= wbm_dat_i[31:16];
end
2: begin
ecc2_cmp[23:16] <= wbm_dat_i[7:0];
ecc3_cmp[23:0] <= wbm_dat_i[31:8];
end
3: spare_space_rd[31:0] <= wbm_dat_i;
4: spare_space_rd[63:32] <= wbm_dat_i;
5: begin
spare_space_erased <= |wbm_dat_i[31:12];
spare_space_ecc_cmp[23:0] <= {6'h0, wbm_dat_i[11:6], 6'h0, wbm_dat_i[5:0]};
end
endcase
end
if(addr_page_end(wbm_adr_o))
hstate <= ST_WBREAD_1;
else begin
wbm_adr_o <= wbm_adr_o + 'h4;
end
end else begin
valid_i <= 0;
sof_i <= 0;
eof_i <= 0;
end
end
// save ecc and keep looping if we haven't gotten the full page yet
if(eof_o) begin
case({wbm_adr_o[2], wbm_adr_o[`FCOLUMNS:9]})
1: ecc0 <= ecc_o;
2: ecc1 <= ecc_o;
3: ecc2 <= ecc_o;
4: ecc3 <= ecc_o;
12: spare_space_ecc <= ecc_o;
endcase
end
if(hstate == ST_WBREAD_1) begin
wbm_cti_o <= WB_CTI_CLASSIC;
wbm_bte_o <= WB_BTE_LINEAR;
wbm_adr_o <= 'h0;
wbm_sel_o <= 'b0000;
wbm_cyc_o <= 0;
wbm_stb_o <= 0;
wbm_we_o <= 0;
hstate <= ST_WBREAD_2;
end
end
// done reading full page, now fix bits
ST_WBREAD_2: begin
casez({ecc_err(spare_space_ecc, spare_space_ecc_cmp),
ecc_err(ecc3, ecc3_cmp),
ecc_err(ecc2, ecc2_cmp),
ecc_err(ecc1, ecc1_cmp),
ecc_err(ecc0, ecc0_cmp)})
5'bzzzz1: begin
fix_bit <= {2'h0, ecc_bit_pos(ecc0, ecc0_cmp)};
ecc0_cmp <= ecc0;
$display("fixing bit %d", ecc_bit_pos(ecc0, ecc0_cmp));
hstate <= ST_WBREAD_3;
end
5'bzzz10: begin
fix_bit <= {2'h1, ecc_bit_pos(ecc1, ecc1_cmp)};
ecc1_cmp <= ecc1;
$display("fixing bit %d", ecc_bit_pos(ecc1, ecc1_cmp) + 2048);
hstate <= ST_WBREAD_3;
end
5'bzz100: begin
fix_bit <= {2'h2, ecc_bit_pos(ecc2, ecc2_cmp)};
ecc2_cmp <= ecc2;
$display("fixing bit %d", ecc_bit_pos(ecc2, ecc2_cmp) + 4096);
hstate <= ST_WBREAD_3;
end
5'bz1000: begin
fix_bit <= {2'h3, ecc_bit_pos(ecc3, ecc2_cmp)};
ecc3_cmp <= ecc3;
$display("fixing bit %d", ecc_bit_pos(ecc3, ecc3_cmp) + 6144);
hstate <= ST_WBREAD_3;
end
5'b10000: begin
spare_space_rd[ecc_bit_pos(spare_space_ecc, spare_space_ecc_cmp)] <=
!spare_space_rd[ecc_bit_pos(spare_space_ecc, spare_space_ecc_cmp)];
$display("fixing spare_space bit %d", ecc_bit_pos(spare_space_ecc, spare_space_ecc_cmp));
hstate <= ST_IDLE;
end
default: begin
hstate <= ST_IDLE;
end
endcase
end
// to fix the bit error, first read from the bram
ST_WBREAD_3: begin
hstate <= ST_WBREAD_4;
end
// then fix it!
ST_WBREAD_4: begin
hstate <= ST_WBREAD_2;
end
endcase
end
end
//
// Scratch BRAM
//
nand_bram_block_dp #(
.DATA ( 32 ),
.ADDR ( `FCOLUMNS - 1 ),
.DEPTH ( `FCOLUMNS_AND_SPARE / 4 )
) nand_bram_block_dp (
.a_clk ( wb_clk ),
.a_wr ( a_wr ),
.a_addr ( a_addr ),
.a_din ( a_din ),
.a_dout ( a_dout ),
.b_clk ( wb_clk ),
.b_wr ( 1'b0 ), // read only port
.b_addr ( b_addr ),
.b_din ( 'h0 ),
.b_dout ( b_dout )
);
always @(*) begin
if(wb_rst) begin
a_wr <= 0;
a_addr <= 'h0;
a_din <= 'h0;
b_addr <= 'h0;
end else begin
// handle write to bram from wishbone bus
if((hstate == ST_IDLE_0) & ram_we & (adr_r >= WBCPU_FLASH_BASEADDR) & (adr_r <= WBCPU_FLASH_HIGHADDR)) begin
a_addr <= adr_r[`FCOLUMNS-1:2];
a_wr <= 1;
a_din <= wbs_dat_i;
// handle read from bram to wishbone bus
end else if((hstate == ST_IDLE_0) & valid & (adr >= WBCPU_FLASH_BASEADDR) & (adr <= WBCPU_FLASH_HIGHADDR)) begin
a_addr <= adr[`FCOLUMNS-1:2];
a_wr <= 0;
end else if((hstate == ST_WBREAD_0) & wbm_ack_i & (wbm_adr_o[`FCOLUMNS:2] < (`FCOLUMNS_AND_SPARE/4))) begin
a_wr <= 1;
a_addr <= wbm_adr_o[`FCOLUMNS:2];
a_din <= wbm_dat_i;
end else if(hstate == ST_WBREAD_4) begin
a_wr <= 1;
a_addr <= fix_bit[13:5];
a_din <= b_dout ^ (1'b1 << fix_bit[4:0]);
end else begin
a_wr <= 0;
a_addr <= 'h0;
a_din <= 'h0;
end
// return data for reads from bram on same clock cycle to wishbone bus
if((hstate == ST_IDLE_0) & valid & (adr_r >= WBCPU_FLASH_BASEADDR) & (adr_r <= WBCPU_FLASH_HIGHADDR)) begin
wbs_dat_o <= a_dout;
end else if(valid & !wbs_we_i & (adr == WBCPU_STATUS_BASEADDR)) begin
wbs_dat_o <= {30'h0, status, ready};
end else
wbs_dat_o <= wbs_dat_o_r;
if((hstate == ST_WBWRITE) || (hstate == ST_WBWRITE_0)) begin
b_addr <= wbm_adr_o[`FCOLUMNS-1:2];
end else if(hstate == ST_WBREAD) begin
b_addr <= {page_offset, wbs_adr_i[`FCOLUMNS-1:2]};
end else if(hstate == ST_WBREAD_3) begin
b_addr <= fix_bit[13:5];
end else if(hstate == ST_WBREAD_2) begin
b_addr <= {page_offset, wbs_adr_i[`FCOLUMNS-1:2]};
end else
b_addr <= 'h0;
// return data to NANDC wishbone bus when issuing writes directly from BRAM
if(hstate == ST_WBWRITE_0) begin
wbm_dat_o <= b_dout;
end else begin
wbm_dat_o <= wbm_dat_o_r;
end
end
end
//
// FUNCTIONS
//
// return true if there's 1 bit error
function ecc_err;
input [23:0] a;
input [23:0] b;
begin
ecc_err = (a[11:0] ^ a[23:12] ^ b[11:0] ^ b[23:12]) == {12{1'b1}};
end
endfunction
// return position of bit error
function [11:0] ecc_bit_pos;
input [23:0] a;
input [23:0] b;
begin
ecc_bit_pos = a[23:12] ^ b[23:12];
end
endfunction
endmodule
|
// DESCRIPTION: Verilator: System Verilog test of a complete CPU
//
// This code instantiates and runs a simple CPU written in System Verilog.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*AUTOWIRE*/
// **************************************************************************
// Regs and Wires
// **************************************************************************
reg rst;
integer rst_count;
integer clk_count;
testbench testbench_i (/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// **************************************************************************
// Reset Generation
// **************************************************************************
initial begin
rst = 1'b1;
rst_count = 0;
end
always @( posedge clk ) begin
if (rst_count < 2) begin
rst_count++;
end
else begin
rst = 1'b0;
end
end
// **************************************************************************
// Drive simulation for 500 clock cycles
// **************************************************************************
initial begin
`ifdef TEST_VERBOSE
$display( "[testbench] - Start of simulation ----------------------- " );
`endif
clk_count = 0;
end
always @( posedge clk ) begin
if (90 == clk_count) begin
$finish ();
end
else begin
clk_count++;
end
end
final begin
`ifdef TEST_VERBOSE
$display( "[testbench] - End of simulation ------------------------- " );
`endif
$write("*-* All Finished *-*\n");
end
endmodule
module testbench (/*AUTOARG*/
// Inputs
clk, rst
);
input clk;
input rst;
// **************************************************************************
// Local parameters
// **************************************************************************
localparam
NUMPADS = $size( pinout );
// **************************************************************************
// Regs and Wires
// **************************************************************************
// **** Pinout ****
`ifdef VERILATOR // see t_tri_array
wire [NUMPADS:1] pad; // GPIO Pads (PORT{A,...,R}).
`else
wire pad [1:NUMPADS]; // GPIO Pads (PORT{A,...,R}).
`endif
// **************************************************************************
// Regs and Wires, Automatics
// **************************************************************************
/*AUTOWIRE*/
// **************************************************************************
// Includes (Testbench extensions)
// **************************************************************************
// N/A
// **************************************************************************
// Chip Instance
// **************************************************************************
chip
i_chip
(
/*AUTOINST*/
// Inouts
.pad (pad[NUMPADS:1]),
// Inputs
.clk (clk),
.rst (rst));
endmodule // test
// Local Variables:
// verilog-library-directories:("." "t_sv_cpu_code")
// End:
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_cmd # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output pcie_rx_cmd_wr_en,
output [33:0] pcie_rx_cmd_wr_data,
input pcie_rx_cmd_full_n,
output pcie_tx_cmd_wr_en,
output [33:0] pcie_tx_cmd_wr_data,
input pcie_tx_cmd_full_n,
input dma_tx_done_wr_en,
input [20:0] dma_tx_done_wr_data,
output dma_tx_done_wr_rdy_n,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_dma_cmd_rd_en;
wire [49:0] w_dma_cmd_rd_data;
wire w_dma_cmd_empty_n;
wire w_pcie_cmd_wr_en;
wire [33:0] w_pcie_cmd_wr_data;
wire w_pcie_cmd_full_n;
wire w_pcie_cmd_rd_en;
wire [33:0] w_pcie_cmd_rd_data;
wire w_pcie_cmd_empty_n;
wire w_dma_done_rd_en;
wire [20:0] w_dma_done_rd_data;
wire w_dma_done_empty_n;
wire w_prp_pcie_alloc;
wire [7:0] w_prp_pcie_alloc_tag;
wire [5:4] w_prp_pcie_tag_alloc_len;
wire w_pcie_tag_full_n;
wire w_prp_fifo_wr_en;
wire [4:0] w_prp_fifo_wr_addr;
wire [C_PCIE_DATA_WIDTH-1:0] w_prp_fifo_wr_data;
wire [5:0] w_prp_rear_full_addr;
wire [5:0] w_prp_rear_addr;
wire w_prp_fifo_full_n;
wire w_prp_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_prp_fifo_rd_data;
wire w_prp_fifo_free_en;
wire [5:4] w_prp_fifo_free_len;
wire w_prp_fifo_empty_n;
dma_cmd_fifo
dma_cmd_fifo_inst0
(
.wr_clk (cpu_bus_clk),
.wr_rst_n (pcie_user_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.rd_clk (pcie_user_clk),
.rd_rst_n (pcie_user_rst_n),
.rd_en (w_dma_cmd_rd_en),
.rd_data (w_dma_cmd_rd_data),
.empty_n (w_dma_cmd_empty_n)
);
pcie_dma_cmd_fifo
pcie_dma_cmd_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_pcie_cmd_wr_en),
.wr_data (w_pcie_cmd_wr_data),
.full_n (w_pcie_cmd_full_n),
.rd_en (w_pcie_cmd_rd_en),
.rd_data (w_pcie_cmd_rd_data),
.empty_n (w_pcie_cmd_empty_n)
);
dma_done_fifo
dma_done_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr0_en (dma_tx_done_wr_en),
.wr0_data (dma_tx_done_wr_data),
.wr0_rdy_n (dma_tx_done_wr_rdy_n),
.full_n (),
.rd_en (w_dma_done_rd_en),
.rd_data (w_dma_done_rd_data),
.empty_n (w_dma_done_empty_n),
.wr1_clk (dma_bus_clk),
.wr1_rst_n (pcie_user_rst_n),
.wr1_en (dma_rx_done_wr_en),
.wr1_data (dma_rx_done_wr_data),
.wr1_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_prp_rx_fifo
pcie_prp_rx_fifo_inst0
(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
.wr_en (w_prp_fifo_wr_en),
.wr_addr (w_prp_fifo_wr_addr),
.wr_data (w_prp_fifo_wr_data),
.rear_full_addr (w_prp_rear_full_addr),
.rear_addr (w_prp_rear_addr),
.alloc_len (w_prp_pcie_tag_alloc_len),
.full_n (w_prp_fifo_full_n),
.rd_en (w_prp_fifo_rd_en),
.rd_data (w_prp_fifo_rd_data),
.free_en (w_prp_fifo_free_en),
.free_len (w_prp_fifo_free_len),
.empty_n (w_prp_fifo_empty_n)
);
pcie_prp_rx_tag
pcie_prp_rx_tag_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_tag_alloc (w_prp_pcie_alloc),
.pcie_alloc_tag (w_prp_pcie_alloc_tag),
.pcie_tag_alloc_len (w_prp_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.cpld_fifo_tag (cpld_prp_fifo_tag),
.cpld_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_fifo_tag_last (cpld_prp_fifo_tag_last),
.fifo_wr_en (w_prp_fifo_wr_en),
.fifo_wr_addr (w_prp_fifo_wr_addr),
.fifo_wr_data (w_prp_fifo_wr_data),
.rear_full_addr (w_prp_rear_full_addr),
.rear_addr (w_prp_rear_addr)
);
dma_cmd_gen
dma_cmd_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.dma_cmd_rd_en (w_dma_cmd_rd_en),
.dma_cmd_rd_data (w_dma_cmd_rd_data),
.dma_cmd_empty_n (w_dma_cmd_empty_n),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.pcie_cmd_wr_en (w_pcie_cmd_wr_en),
.pcie_cmd_wr_data (w_pcie_cmd_wr_data),
.pcie_cmd_full_n (w_pcie_cmd_full_n),
.prp_pcie_alloc (w_prp_pcie_alloc),
.prp_pcie_alloc_tag (w_prp_pcie_alloc_tag),
.prp_pcie_tag_alloc_len (w_prp_pcie_tag_alloc_len),
.pcie_tag_full_n (w_pcie_tag_full_n),
.prp_fifo_full_n (w_prp_fifo_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack)
);
pcie_dma_cmd_gen
pcie_dma_cmd_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_cmd_rd_en (w_pcie_cmd_rd_en),
.pcie_cmd_rd_data (w_pcie_cmd_rd_data),
.pcie_cmd_empty_n (w_pcie_cmd_empty_n),
.prp_fifo_rd_en (w_prp_fifo_rd_en),
.prp_fifo_rd_data (w_prp_fifo_rd_data),
.prp_fifo_free_en (w_prp_fifo_free_en),
.prp_fifo_free_len (w_prp_fifo_free_len),
.prp_fifo_empty_n (w_prp_fifo_empty_n),
.pcie_rx_cmd_wr_en (pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (pcie_tx_cmd_full_n)
);
dma_done
dma_done_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.dma_done_rd_en (w_dma_done_rd_en),
.dma_done_rd_data (w_dma_done_rd_data),
.dma_done_empty_n (w_dma_done_empty_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
// Date : Tue Sep 27 19:21:50 2016
// Host : jorge-pc running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file
// /home/jorge/Documents/Karatsuba_FPU/Add_Sub/ADD_SUB_PIPELINED/ADD_SUB_FUNCIONAL_v1.sim/bloody_simruns/synth/timing/tb_FPU_PIPELINED_FPADDSUB2_vector_testing_time_synth.v
// Design : FPU_PIPELINED_FPADDSUB
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING
module Comparator
(CO,
\Q_reg[0] ,
D,
DI,
S,
\Q_reg[14] ,
\Q_reg[14]_0 ,
\Q_reg[22] ,
\Q_reg[22]_0 ,
\Q_reg[30] ,
\Q_reg[30]_0 ,
\Q_reg[9] ,
\Q_reg[21] ,
\Q_reg[30]_1 ,
intAS,
Q,
\Q_reg[31] );
output [0:0]CO;
output [0:0]\Q_reg[0] ;
output [0:0]D;
input [3:0]DI;
input [3:0]S;
input [3:0]\Q_reg[14] ;
input [3:0]\Q_reg[14]_0 ;
input [3:0]\Q_reg[22] ;
input [3:0]\Q_reg[22]_0 ;
input [3:0]\Q_reg[30] ;
input [3:0]\Q_reg[30]_0 ;
input [3:0]\Q_reg[9] ;
input [3:0]\Q_reg[21] ;
input [2:0]\Q_reg[30]_1 ;
input intAS;
input [0:0]Q;
input [0:0]\Q_reg[31] ;
wire [0:0]CO;
wire [0:0]D;
wire [3:0]DI;
wire [0:0]Q;
wire [0:0]\Q_reg[0] ;
wire [3:0]\Q_reg[14] ;
wire [3:0]\Q_reg[14]_0 ;
wire [3:0]\Q_reg[21] ;
wire [3:0]\Q_reg[22] ;
wire [3:0]\Q_reg[22]_0 ;
wire [3:0]\Q_reg[30] ;
wire [3:0]\Q_reg[30]_0 ;
wire [2:0]\Q_reg[30]_1 ;
wire [0:0]\Q_reg[31] ;
wire [3:0]\Q_reg[9] ;
wire [3:0]S;
wire eqXY_o_carry__0_n_0;
wire eqXY_o_carry__0_n_1;
wire eqXY_o_carry__0_n_2;
wire eqXY_o_carry__0_n_3;
wire eqXY_o_carry__1_n_2;
wire eqXY_o_carry__1_n_3;
wire eqXY_o_carry_n_0;
wire eqXY_o_carry_n_1;
wire eqXY_o_carry_n_2;
wire eqXY_o_carry_n_3;
wire gtXY_o_carry__0_n_0;
wire gtXY_o_carry__0_n_1;
wire gtXY_o_carry__0_n_2;
wire gtXY_o_carry__0_n_3;
wire gtXY_o_carry__1_n_0;
wire gtXY_o_carry__1_n_1;
wire gtXY_o_carry__1_n_2;
wire gtXY_o_carry__1_n_3;
wire gtXY_o_carry__2_n_1;
wire gtXY_o_carry__2_n_2;
wire gtXY_o_carry__2_n_3;
wire gtXY_o_carry_n_0;
wire gtXY_o_carry_n_1;
wire gtXY_o_carry_n_2;
wire gtXY_o_carry_n_3;
wire intAS;
wire [3:0]NLW_eqXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__0_O_UNCONNECTED;
wire [3:3]NLW_eqXY_o_carry__1_CO_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__0_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__2_O_UNCONNECTED;
LUT4 #(
.INIT(16'h8228))
\Q[0]_i_1__1
(.I0(\Q_reg[0] ),
.I1(intAS),
.I2(Q),
.I3(\Q_reg[31] ),
.O(D));
CARRY4 eqXY_o_carry
(.CI(1'b0),
.CO({eqXY_o_carry_n_0,eqXY_o_carry_n_1,eqXY_o_carry_n_2,eqXY_o_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry_O_UNCONNECTED[3:0]),
.S(\Q_reg[9] ));
CARRY4 eqXY_o_carry__0
(.CI(eqXY_o_carry_n_0),
.CO({eqXY_o_carry__0_n_0,eqXY_o_carry__0_n_1,eqXY_o_carry__0_n_2,eqXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[21] ));
CARRY4 eqXY_o_carry__1
(.CI(eqXY_o_carry__0_n_0),
.CO({NLW_eqXY_o_carry__1_CO_UNCONNECTED[3],\Q_reg[0] ,eqXY_o_carry__1_n_2,eqXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__1_O_UNCONNECTED[3:0]),
.S({1'b0,\Q_reg[30]_1 }));
CARRY4 gtXY_o_carry
(.CI(1'b0),
.CO({gtXY_o_carry_n_0,gtXY_o_carry_n_1,gtXY_o_carry_n_2,gtXY_o_carry_n_3}),
.CYINIT(1'b0),
.DI(DI),
.O(NLW_gtXY_o_carry_O_UNCONNECTED[3:0]),
.S(S));
CARRY4 gtXY_o_carry__0
(.CI(gtXY_o_carry_n_0),
.CO({gtXY_o_carry__0_n_0,gtXY_o_carry__0_n_1,gtXY_o_carry__0_n_2,gtXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[14] ),
.O(NLW_gtXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[14]_0 ));
CARRY4 gtXY_o_carry__1
(.CI(gtXY_o_carry__0_n_0),
.CO({gtXY_o_carry__1_n_0,gtXY_o_carry__1_n_1,gtXY_o_carry__1_n_2,gtXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[22] ),
.O(NLW_gtXY_o_carry__1_O_UNCONNECTED[3:0]),
.S(\Q_reg[22]_0 ));
CARRY4 gtXY_o_carry__2
(.CI(gtXY_o_carry__1_n_0),
.CO({CO,gtXY_o_carry__2_n_1,gtXY_o_carry__2_n_2,gtXY_o_carry__2_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[30] ),
.O(NLW_gtXY_o_carry__2_O_UNCONNECTED[3:0]),
.S(\Q_reg[30]_0 ));
endmodule
(* EW = "8" *) (* EWR = "5" *) (* SW = "23" *)
(* SWR = "26" *) (* W = "32" *)
(* NotValidForBitStream *)
module FPU_PIPELINED_FPADDSUB
(clk,
rst,
beg_OP,
Data_X,
Data_Y,
add_subt,
busy,
overflow_flag,
underflow_flag,
zero_flag,
ready,
final_result_ieee);
input clk;
input rst;
input beg_OP;
input [31:0]Data_X;
input [31:0]Data_Y;
input add_subt;
output busy;
output overflow_flag;
output underflow_flag;
output zero_flag;
output ready;
output [31:0]final_result_ieee;
wire ADD_OVRFLW_NRM;
wire ADD_OVRFLW_NRM2;
wire [24:2]DMP_mant_SFG_SWR;
wire [31:0]Data_X;
wire [31:0]Data_X_IBUF;
wire [31:0]Data_Y;
wire [31:0]Data_Y_IBUF;
wire [25:0]\Data_array_SWR[2] ;
wire [25:18]\Data_array_SWR[3] ;
wire [15:14]\Data_array_SWR[4] ;
wire [17:2]\Data_array_SWR[5] ;
wire [25:1]\Data_array_SWR[6] ;
wire EXP_STAGE_DMP_n_1;
wire EXP_STAGE_DMP_n_10;
wire EXP_STAGE_DMP_n_11;
wire EXP_STAGE_DMP_n_12;
wire EXP_STAGE_DMP_n_13;
wire EXP_STAGE_DMP_n_14;
wire EXP_STAGE_DMP_n_15;
wire EXP_STAGE_DMP_n_16;
wire EXP_STAGE_DMP_n_17;
wire EXP_STAGE_DMP_n_18;
wire EXP_STAGE_DMP_n_19;
wire EXP_STAGE_DMP_n_2;
wire EXP_STAGE_DMP_n_20;
wire EXP_STAGE_DMP_n_21;
wire EXP_STAGE_DMP_n_22;
wire EXP_STAGE_DMP_n_23;
wire EXP_STAGE_DMP_n_24;
wire EXP_STAGE_DMP_n_25;
wire EXP_STAGE_DMP_n_26;
wire EXP_STAGE_DMP_n_27;
wire EXP_STAGE_DMP_n_28;
wire EXP_STAGE_DMP_n_29;
wire EXP_STAGE_DMP_n_3;
wire EXP_STAGE_DMP_n_30;
wire EXP_STAGE_DMP_n_31;
wire EXP_STAGE_DMP_n_32;
wire EXP_STAGE_DMP_n_4;
wire EXP_STAGE_DMP_n_5;
wire EXP_STAGE_DMP_n_6;
wire EXP_STAGE_DMP_n_7;
wire EXP_STAGE_DMP_n_8;
wire EXP_STAGE_DMP_n_9;
wire EXP_STAGE_DmP_n_10;
wire EXP_STAGE_DmP_n_11;
wire EXP_STAGE_DmP_n_12;
wire EXP_STAGE_DmP_n_13;
wire EXP_STAGE_DmP_n_14;
wire EXP_STAGE_DmP_n_15;
wire EXP_STAGE_DmP_n_16;
wire EXP_STAGE_DmP_n_17;
wire EXP_STAGE_DmP_n_18;
wire EXP_STAGE_DmP_n_19;
wire EXP_STAGE_DmP_n_20;
wire EXP_STAGE_DmP_n_21;
wire EXP_STAGE_DmP_n_22;
wire EXP_STAGE_DmP_n_23;
wire EXP_STAGE_DmP_n_24;
wire EXP_STAGE_DmP_n_25;
wire EXP_STAGE_DmP_n_26;
wire EXP_STAGE_DmP_n_27;
wire EXP_STAGE_DmP_n_28;
wire EXP_STAGE_DmP_n_3;
wire EXP_STAGE_DmP_n_4;
wire EXP_STAGE_DmP_n_5;
wire EXP_STAGE_DmP_n_6;
wire EXP_STAGE_DmP_n_7;
wire EXP_STAGE_DmP_n_8;
wire EXP_STAGE_DmP_n_9;
wire EXP_STAGE_FLAGS_n_0;
wire EXP_STAGE_FLAGS_n_1;
wire EXP_STAGE_FLAGS_n_2;
wire FSM_enable_input_internal;
wire INPUT_STAGE_OPERANDX_n_0;
wire INPUT_STAGE_OPERANDX_n_1;
wire INPUT_STAGE_OPERANDX_n_10;
wire INPUT_STAGE_OPERANDX_n_11;
wire INPUT_STAGE_OPERANDX_n_12;
wire INPUT_STAGE_OPERANDX_n_13;
wire INPUT_STAGE_OPERANDX_n_14;
wire INPUT_STAGE_OPERANDX_n_15;
wire INPUT_STAGE_OPERANDX_n_16;
wire INPUT_STAGE_OPERANDX_n_17;
wire INPUT_STAGE_OPERANDX_n_18;
wire INPUT_STAGE_OPERANDX_n_19;
wire INPUT_STAGE_OPERANDX_n_2;
wire INPUT_STAGE_OPERANDX_n_20;
wire INPUT_STAGE_OPERANDX_n_21;
wire INPUT_STAGE_OPERANDX_n_22;
wire INPUT_STAGE_OPERANDX_n_23;
wire INPUT_STAGE_OPERANDX_n_24;
wire INPUT_STAGE_OPERANDX_n_25;
wire INPUT_STAGE_OPERANDX_n_26;
wire INPUT_STAGE_OPERANDX_n_27;
wire INPUT_STAGE_OPERANDX_n_28;
wire INPUT_STAGE_OPERANDX_n_29;
wire INPUT_STAGE_OPERANDX_n_3;
wire INPUT_STAGE_OPERANDX_n_30;
wire INPUT_STAGE_OPERANDX_n_31;
wire INPUT_STAGE_OPERANDX_n_32;
wire INPUT_STAGE_OPERANDX_n_33;
wire INPUT_STAGE_OPERANDX_n_34;
wire INPUT_STAGE_OPERANDX_n_35;
wire INPUT_STAGE_OPERANDX_n_36;
wire INPUT_STAGE_OPERANDX_n_37;
wire INPUT_STAGE_OPERANDX_n_38;
wire INPUT_STAGE_OPERANDX_n_39;
wire INPUT_STAGE_OPERANDX_n_40;
wire INPUT_STAGE_OPERANDX_n_41;
wire INPUT_STAGE_OPERANDX_n_42;
wire INPUT_STAGE_OPERANDX_n_43;
wire INPUT_STAGE_OPERANDX_n_44;
wire INPUT_STAGE_OPERANDX_n_45;
wire INPUT_STAGE_OPERANDX_n_46;
wire INPUT_STAGE_OPERANDX_n_47;
wire INPUT_STAGE_OPERANDX_n_48;
wire INPUT_STAGE_OPERANDX_n_49;
wire INPUT_STAGE_OPERANDX_n_5;
wire INPUT_STAGE_OPERANDX_n_50;
wire INPUT_STAGE_OPERANDX_n_51;
wire INPUT_STAGE_OPERANDX_n_52;
wire INPUT_STAGE_OPERANDX_n_53;
wire INPUT_STAGE_OPERANDX_n_54;
wire INPUT_STAGE_OPERANDX_n_55;
wire INPUT_STAGE_OPERANDX_n_56;
wire INPUT_STAGE_OPERANDX_n_57;
wire INPUT_STAGE_OPERANDX_n_58;
wire INPUT_STAGE_OPERANDX_n_59;
wire INPUT_STAGE_OPERANDX_n_6;
wire INPUT_STAGE_OPERANDX_n_60;
wire INPUT_STAGE_OPERANDX_n_61;
wire INPUT_STAGE_OPERANDX_n_62;
wire INPUT_STAGE_OPERANDX_n_63;
wire INPUT_STAGE_OPERANDX_n_64;
wire INPUT_STAGE_OPERANDX_n_65;
wire INPUT_STAGE_OPERANDX_n_66;
wire INPUT_STAGE_OPERANDX_n_67;
wire INPUT_STAGE_OPERANDX_n_68;
wire INPUT_STAGE_OPERANDX_n_69;
wire INPUT_STAGE_OPERANDX_n_7;
wire INPUT_STAGE_OPERANDX_n_70;
wire INPUT_STAGE_OPERANDX_n_71;
wire INPUT_STAGE_OPERANDX_n_72;
wire INPUT_STAGE_OPERANDX_n_8;
wire INPUT_STAGE_OPERANDX_n_9;
wire INPUT_STAGE_OPERANDY_n_0;
wire INPUT_STAGE_OPERANDY_n_10;
wire INPUT_STAGE_OPERANDY_n_11;
wire INPUT_STAGE_OPERANDY_n_12;
wire INPUT_STAGE_OPERANDY_n_13;
wire INPUT_STAGE_OPERANDY_n_14;
wire INPUT_STAGE_OPERANDY_n_15;
wire INPUT_STAGE_OPERANDY_n_16;
wire INPUT_STAGE_OPERANDY_n_17;
wire INPUT_STAGE_OPERANDY_n_18;
wire INPUT_STAGE_OPERANDY_n_19;
wire INPUT_STAGE_OPERANDY_n_2;
wire INPUT_STAGE_OPERANDY_n_20;
wire INPUT_STAGE_OPERANDY_n_21;
wire INPUT_STAGE_OPERANDY_n_22;
wire INPUT_STAGE_OPERANDY_n_23;
wire INPUT_STAGE_OPERANDY_n_24;
wire INPUT_STAGE_OPERANDY_n_25;
wire INPUT_STAGE_OPERANDY_n_26;
wire INPUT_STAGE_OPERANDY_n_27;
wire INPUT_STAGE_OPERANDY_n_28;
wire INPUT_STAGE_OPERANDY_n_29;
wire INPUT_STAGE_OPERANDY_n_3;
wire INPUT_STAGE_OPERANDY_n_30;
wire INPUT_STAGE_OPERANDY_n_31;
wire INPUT_STAGE_OPERANDY_n_32;
wire INPUT_STAGE_OPERANDY_n_33;
wire INPUT_STAGE_OPERANDY_n_4;
wire INPUT_STAGE_OPERANDY_n_5;
wire INPUT_STAGE_OPERANDY_n_6;
wire INPUT_STAGE_OPERANDY_n_7;
wire INPUT_STAGE_OPERANDY_n_8;
wire INPUT_STAGE_OPERANDY_n_9;
wire [3:3]LZD_raw_out_EWR;
wire Magnitude_Comparator_n_2;
wire MuxXY_n_0;
wire MuxXY_n_1;
wire MuxXY_n_10;
wire MuxXY_n_11;
wire MuxXY_n_12;
wire MuxXY_n_13;
wire MuxXY_n_14;
wire MuxXY_n_15;
wire MuxXY_n_16;
wire MuxXY_n_17;
wire MuxXY_n_18;
wire MuxXY_n_19;
wire MuxXY_n_2;
wire MuxXY_n_20;
wire MuxXY_n_21;
wire MuxXY_n_22;
wire MuxXY_n_23;
wire MuxXY_n_24;
wire MuxXY_n_25;
wire MuxXY_n_26;
wire MuxXY_n_27;
wire MuxXY_n_28;
wire MuxXY_n_29;
wire MuxXY_n_3;
wire MuxXY_n_30;
wire MuxXY_n_31;
wire MuxXY_n_32;
wire MuxXY_n_33;
wire MuxXY_n_34;
wire MuxXY_n_35;
wire MuxXY_n_36;
wire MuxXY_n_37;
wire MuxXY_n_38;
wire MuxXY_n_39;
wire MuxXY_n_4;
wire MuxXY_n_40;
wire MuxXY_n_41;
wire MuxXY_n_42;
wire MuxXY_n_43;
wire MuxXY_n_44;
wire MuxXY_n_45;
wire MuxXY_n_46;
wire MuxXY_n_47;
wire MuxXY_n_48;
wire MuxXY_n_49;
wire MuxXY_n_5;
wire MuxXY_n_50;
wire MuxXY_n_51;
wire MuxXY_n_52;
wire MuxXY_n_53;
wire MuxXY_n_54;
wire MuxXY_n_55;
wire MuxXY_n_56;
wire MuxXY_n_57;
wire MuxXY_n_58;
wire MuxXY_n_6;
wire MuxXY_n_7;
wire MuxXY_n_8;
wire MuxXY_n_9;
wire NRM_STAGE_DMP_exp_n_0;
wire NRM_STAGE_DMP_exp_n_1;
wire NRM_STAGE_DMP_exp_n_2;
wire NRM_STAGE_DMP_exp_n_3;
wire NRM_STAGE_DMP_exp_n_4;
wire NRM_STAGE_DMP_exp_n_5;
wire NRM_STAGE_DMP_exp_n_6;
wire NRM_STAGE_DMP_exp_n_7;
wire NRM_STAGE_FLAGS_n_2;
wire NRM_STAGE_FLAGS_n_3;
wire NRM_STAGE_Raw_mant_n_26;
wire NRM_STAGE_Raw_mant_n_28;
wire NRM_STAGE_Raw_mant_n_29;
wire NRM_STAGE_Raw_mant_n_30;
wire OP_FLAG_INIT;
wire OVRFLW_FLAG_FRMT;
wire [25:0]Raw_mant_SGF;
wire SFT2FRMT_STAGE_FLAGS_n_0;
wire SFT2FRMT_STAGE_FLAGS_n_3;
wire SFT2FRMT_STAGE_VARS_n_0;
wire SFT2FRMT_STAGE_VARS_n_1;
wire SFT2FRMT_STAGE_VARS_n_10;
wire SFT2FRMT_STAGE_VARS_n_11;
wire SFT2FRMT_STAGE_VARS_n_12;
wire SFT2FRMT_STAGE_VARS_n_13;
wire SFT2FRMT_STAGE_VARS_n_14;
wire SFT2FRMT_STAGE_VARS_n_15;
wire SFT2FRMT_STAGE_VARS_n_2;
wire SFT2FRMT_STAGE_VARS_n_3;
wire SFT2FRMT_STAGE_VARS_n_4;
wire SFT2FRMT_STAGE_VARS_n_5;
wire SFT2FRMT_STAGE_VARS_n_6;
wire SFT2FRMT_STAGE_VARS_n_7;
wire SFT2FRMT_STAGE_VARS_n_8;
wire SFT2FRMT_STAGE_VARS_n_9;
wire SGF_STAGE_DMP_n_0;
wire SGF_STAGE_DMP_n_1;
wire SGF_STAGE_DMP_n_10;
wire SGF_STAGE_DMP_n_11;
wire SGF_STAGE_DMP_n_2;
wire SGF_STAGE_DMP_n_3;
wire SGF_STAGE_DMP_n_35;
wire SGF_STAGE_DMP_n_36;
wire SGF_STAGE_DMP_n_37;
wire SGF_STAGE_DMP_n_38;
wire SGF_STAGE_DMP_n_39;
wire SGF_STAGE_DMP_n_4;
wire SGF_STAGE_DMP_n_40;
wire SGF_STAGE_DMP_n_41;
wire SGF_STAGE_DMP_n_42;
wire SGF_STAGE_DMP_n_43;
wire SGF_STAGE_DMP_n_44;
wire SGF_STAGE_DMP_n_45;
wire SGF_STAGE_DMP_n_46;
wire SGF_STAGE_DMP_n_47;
wire SGF_STAGE_DMP_n_48;
wire SGF_STAGE_DMP_n_49;
wire SGF_STAGE_DMP_n_5;
wire SGF_STAGE_DMP_n_50;
wire SGF_STAGE_DMP_n_51;
wire SGF_STAGE_DMP_n_52;
wire SGF_STAGE_DMP_n_53;
wire SGF_STAGE_DMP_n_54;
wire SGF_STAGE_DMP_n_55;
wire SGF_STAGE_DMP_n_6;
wire SGF_STAGE_DMP_n_7;
wire SGF_STAGE_DMP_n_8;
wire SGF_STAGE_DMP_n_9;
wire SGF_STAGE_DmP_mant_n_0;
wire SGF_STAGE_DmP_mant_n_1;
wire SGF_STAGE_DmP_mant_n_10;
wire SGF_STAGE_DmP_mant_n_11;
wire SGF_STAGE_DmP_mant_n_12;
wire SGF_STAGE_DmP_mant_n_13;
wire SGF_STAGE_DmP_mant_n_14;
wire SGF_STAGE_DmP_mant_n_15;
wire SGF_STAGE_DmP_mant_n_16;
wire SGF_STAGE_DmP_mant_n_17;
wire SGF_STAGE_DmP_mant_n_18;
wire SGF_STAGE_DmP_mant_n_19;
wire SGF_STAGE_DmP_mant_n_2;
wire SGF_STAGE_DmP_mant_n_20;
wire SGF_STAGE_DmP_mant_n_21;
wire SGF_STAGE_DmP_mant_n_22;
wire SGF_STAGE_DmP_mant_n_23;
wire SGF_STAGE_DmP_mant_n_24;
wire SGF_STAGE_DmP_mant_n_26;
wire SGF_STAGE_DmP_mant_n_27;
wire SGF_STAGE_DmP_mant_n_28;
wire SGF_STAGE_DmP_mant_n_29;
wire SGF_STAGE_DmP_mant_n_3;
wire SGF_STAGE_DmP_mant_n_30;
wire SGF_STAGE_DmP_mant_n_31;
wire SGF_STAGE_DmP_mant_n_32;
wire SGF_STAGE_DmP_mant_n_33;
wire SGF_STAGE_DmP_mant_n_34;
wire SGF_STAGE_DmP_mant_n_35;
wire SGF_STAGE_DmP_mant_n_36;
wire SGF_STAGE_DmP_mant_n_37;
wire SGF_STAGE_DmP_mant_n_38;
wire SGF_STAGE_DmP_mant_n_39;
wire SGF_STAGE_DmP_mant_n_4;
wire SGF_STAGE_DmP_mant_n_40;
wire SGF_STAGE_DmP_mant_n_41;
wire SGF_STAGE_DmP_mant_n_42;
wire SGF_STAGE_DmP_mant_n_43;
wire SGF_STAGE_DmP_mant_n_44;
wire SGF_STAGE_DmP_mant_n_45;
wire SGF_STAGE_DmP_mant_n_46;
wire SGF_STAGE_DmP_mant_n_47;
wire SGF_STAGE_DmP_mant_n_48;
wire SGF_STAGE_DmP_mant_n_49;
wire SGF_STAGE_DmP_mant_n_5;
wire SGF_STAGE_DmP_mant_n_51;
wire SGF_STAGE_DmP_mant_n_6;
wire SGF_STAGE_DmP_mant_n_7;
wire SGF_STAGE_DmP_mant_n_8;
wire SGF_STAGE_DmP_mant_n_9;
wire SGF_STAGE_FLAGS_n_1;
wire SHT1_STAGE_DMP_n_0;
wire SHT1_STAGE_DMP_n_1;
wire SHT1_STAGE_DMP_n_10;
wire SHT1_STAGE_DMP_n_11;
wire SHT1_STAGE_DMP_n_12;
wire SHT1_STAGE_DMP_n_13;
wire SHT1_STAGE_DMP_n_14;
wire SHT1_STAGE_DMP_n_15;
wire SHT1_STAGE_DMP_n_16;
wire SHT1_STAGE_DMP_n_17;
wire SHT1_STAGE_DMP_n_18;
wire SHT1_STAGE_DMP_n_19;
wire SHT1_STAGE_DMP_n_2;
wire SHT1_STAGE_DMP_n_20;
wire SHT1_STAGE_DMP_n_21;
wire SHT1_STAGE_DMP_n_22;
wire SHT1_STAGE_DMP_n_23;
wire SHT1_STAGE_DMP_n_24;
wire SHT1_STAGE_DMP_n_25;
wire SHT1_STAGE_DMP_n_26;
wire SHT1_STAGE_DMP_n_27;
wire SHT1_STAGE_DMP_n_28;
wire SHT1_STAGE_DMP_n_29;
wire SHT1_STAGE_DMP_n_3;
wire SHT1_STAGE_DMP_n_30;
wire SHT1_STAGE_DMP_n_4;
wire SHT1_STAGE_DMP_n_5;
wire SHT1_STAGE_DMP_n_6;
wire SHT1_STAGE_DMP_n_7;
wire SHT1_STAGE_DMP_n_8;
wire SHT1_STAGE_DMP_n_9;
wire SHT1_STAGE_DmP_mant_n_0;
wire SHT1_STAGE_DmP_mant_n_1;
wire SHT1_STAGE_DmP_mant_n_10;
wire SHT1_STAGE_DmP_mant_n_11;
wire SHT1_STAGE_DmP_mant_n_12;
wire SHT1_STAGE_DmP_mant_n_13;
wire SHT1_STAGE_DmP_mant_n_14;
wire SHT1_STAGE_DmP_mant_n_15;
wire SHT1_STAGE_DmP_mant_n_16;
wire SHT1_STAGE_DmP_mant_n_17;
wire SHT1_STAGE_DmP_mant_n_18;
wire SHT1_STAGE_DmP_mant_n_19;
wire SHT1_STAGE_DmP_mant_n_2;
wire SHT1_STAGE_DmP_mant_n_20;
wire SHT1_STAGE_DmP_mant_n_21;
wire SHT1_STAGE_DmP_mant_n_22;
wire SHT1_STAGE_DmP_mant_n_3;
wire SHT1_STAGE_DmP_mant_n_4;
wire SHT1_STAGE_DmP_mant_n_5;
wire SHT1_STAGE_DmP_mant_n_6;
wire SHT1_STAGE_DmP_mant_n_7;
wire SHT1_STAGE_DmP_mant_n_8;
wire SHT1_STAGE_DmP_mant_n_9;
wire SHT1_STAGE_FLAGS_n_0;
wire SHT1_STAGE_FLAGS_n_1;
wire SHT1_STAGE_FLAGS_n_2;
wire SHT2_STAGE_DMP_n_0;
wire SHT2_STAGE_DMP_n_1;
wire SHT2_STAGE_DMP_n_10;
wire SHT2_STAGE_DMP_n_11;
wire SHT2_STAGE_DMP_n_12;
wire SHT2_STAGE_DMP_n_13;
wire SHT2_STAGE_DMP_n_14;
wire SHT2_STAGE_DMP_n_15;
wire SHT2_STAGE_DMP_n_16;
wire SHT2_STAGE_DMP_n_17;
wire SHT2_STAGE_DMP_n_18;
wire SHT2_STAGE_DMP_n_19;
wire SHT2_STAGE_DMP_n_2;
wire SHT2_STAGE_DMP_n_20;
wire SHT2_STAGE_DMP_n_21;
wire SHT2_STAGE_DMP_n_22;
wire SHT2_STAGE_DMP_n_23;
wire SHT2_STAGE_DMP_n_24;
wire SHT2_STAGE_DMP_n_25;
wire SHT2_STAGE_DMP_n_26;
wire SHT2_STAGE_DMP_n_27;
wire SHT2_STAGE_DMP_n_28;
wire SHT2_STAGE_DMP_n_29;
wire SHT2_STAGE_DMP_n_3;
wire SHT2_STAGE_DMP_n_30;
wire SHT2_STAGE_DMP_n_4;
wire SHT2_STAGE_DMP_n_5;
wire SHT2_STAGE_DMP_n_6;
wire SHT2_STAGE_DMP_n_7;
wire SHT2_STAGE_DMP_n_8;
wire SHT2_STAGE_DMP_n_9;
wire SHT2_STAGE_FLAGS_n_0;
wire SHT2_STAGE_FLAGS_n_1;
wire SHT2_STAGE_FLAGS_n_2;
wire SHT2_STAGE_SHFTVARS1_n_24;
wire SHT2_STAGE_SHFTVARS1_n_25;
wire SHT2_STAGE_SHFTVARS1_n_26;
wire SHT2_STAGE_SHFTVARS1_n_27;
wire SHT2_STAGE_SHFTVARS1_n_28;
wire SHT2_STAGE_SHFTVARS1_n_29;
wire SHT2_STAGE_SHFTVARS1_n_30;
wire SHT2_STAGE_SHFTVARS1_n_31;
wire SHT2_STAGE_SHFTVARS1_n_32;
wire SHT2_STAGE_SHFTVARS1_n_33;
wire SHT2_STAGE_SHFTVARS1_n_34;
wire SHT2_STAGE_SHFTVARS1_n_35;
wire SHT2_STAGE_SHFTVARS2_n_10;
wire SHT2_STAGE_SHFTVARS2_n_11;
wire SHT2_STAGE_SHFTVARS2_n_7;
wire SHT2_STAGE_SHFTVARS2_n_8;
wire SHT2_STAGE_SHFTVARS2_n_9;
wire SIGN_FLAG_INIT;
wire SIGN_FLAG_SHT1SHT2;
wire [4:1]Shift_amount_EXP_EW;
wire [4:0]Shift_amount_SHT1_EWR;
wire [1:1]Shift_reg_FLAGS_7;
wire UNDRFLW_FLAG_FRMT;
wire add_subt;
wire add_subt_IBUF;
wire beg_OP;
wire beg_OP_IBUF;
wire bit_shift_SHT1;
wire busy;
wire busy_OBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire enable_Pipeline_input;
wire eqXY;
wire [31:0]final_result_ieee;
wire [31:0]final_result_ieee_OBUF;
wire [31:31]formatted_number_W;
wire gtXY;
wire inst_FRMT_STAGE_n_1;
wire inst_FRMT_STAGE_n_10;
wire inst_FRMT_STAGE_n_11;
wire inst_FRMT_STAGE_n_12;
wire inst_FRMT_STAGE_n_13;
wire inst_FRMT_STAGE_n_14;
wire inst_FRMT_STAGE_n_15;
wire inst_FRMT_STAGE_n_2;
wire inst_FRMT_STAGE_n_3;
wire inst_FRMT_STAGE_n_4;
wire inst_FRMT_STAGE_n_5;
wire inst_FRMT_STAGE_n_6;
wire inst_FRMT_STAGE_n_7;
wire inst_FRMT_STAGE_n_8;
wire inst_FRMT_STAGE_n_9;
wire inst_ShiftRegister_n_0;
wire inst_ShiftRegister_n_1;
wire inst_ShiftRegister_n_2;
wire inst_ShiftRegister_n_4;
wire inst_ShiftRegister_n_6;
wire intAS;
wire [31:31]intDX_EWSW;
wire [31:31]intDY_EWSW;
wire left_right_SHT1;
wire left_right_SHT2;
wire load0;
wire load00_out;
wire overflow_flag;
wire overflow_flag_OBUF;
wire [0:0]p_0_in;
wire p_2_in;
wire [2:2]p_3_out;
wire ready;
wire ready_OBUF;
wire rst;
wire rst_IBUF;
wire [25:0]sftr_odat_SHT2_SWR;
wire [4:2]shft_value_mux_o_EWR;
wire [4:2]shift_value_SHT2_EWR;
wire underflow_flag;
wire underflow_flag_OBUF;
wire zero_flag;
wire zero_flag_OBUF;
initial begin
$sdf_annotate("tb_FPU_PIPELINED_FPADDSUB2_vector_testing_time_synth.sdf",,,,"tool_control");
end
IBUF \Data_X_IBUF[0]_inst
(.I(Data_X[0]),
.O(Data_X_IBUF[0]));
IBUF \Data_X_IBUF[10]_inst
(.I(Data_X[10]),
.O(Data_X_IBUF[10]));
IBUF \Data_X_IBUF[11]_inst
(.I(Data_X[11]),
.O(Data_X_IBUF[11]));
IBUF \Data_X_IBUF[12]_inst
(.I(Data_X[12]),
.O(Data_X_IBUF[12]));
IBUF \Data_X_IBUF[13]_inst
(.I(Data_X[13]),
.O(Data_X_IBUF[13]));
IBUF \Data_X_IBUF[14]_inst
(.I(Data_X[14]),
.O(Data_X_IBUF[14]));
IBUF \Data_X_IBUF[15]_inst
(.I(Data_X[15]),
.O(Data_X_IBUF[15]));
IBUF \Data_X_IBUF[16]_inst
(.I(Data_X[16]),
.O(Data_X_IBUF[16]));
IBUF \Data_X_IBUF[17]_inst
(.I(Data_X[17]),
.O(Data_X_IBUF[17]));
IBUF \Data_X_IBUF[18]_inst
(.I(Data_X[18]),
.O(Data_X_IBUF[18]));
IBUF \Data_X_IBUF[19]_inst
(.I(Data_X[19]),
.O(Data_X_IBUF[19]));
IBUF \Data_X_IBUF[1]_inst
(.I(Data_X[1]),
.O(Data_X_IBUF[1]));
IBUF \Data_X_IBUF[20]_inst
(.I(Data_X[20]),
.O(Data_X_IBUF[20]));
IBUF \Data_X_IBUF[21]_inst
(.I(Data_X[21]),
.O(Data_X_IBUF[21]));
IBUF \Data_X_IBUF[22]_inst
(.I(Data_X[22]),
.O(Data_X_IBUF[22]));
IBUF \Data_X_IBUF[23]_inst
(.I(Data_X[23]),
.O(Data_X_IBUF[23]));
IBUF \Data_X_IBUF[24]_inst
(.I(Data_X[24]),
.O(Data_X_IBUF[24]));
IBUF \Data_X_IBUF[25]_inst
(.I(Data_X[25]),
.O(Data_X_IBUF[25]));
IBUF \Data_X_IBUF[26]_inst
(.I(Data_X[26]),
.O(Data_X_IBUF[26]));
IBUF \Data_X_IBUF[27]_inst
(.I(Data_X[27]),
.O(Data_X_IBUF[27]));
IBUF \Data_X_IBUF[28]_inst
(.I(Data_X[28]),
.O(Data_X_IBUF[28]));
IBUF \Data_X_IBUF[29]_inst
(.I(Data_X[29]),
.O(Data_X_IBUF[29]));
IBUF \Data_X_IBUF[2]_inst
(.I(Data_X[2]),
.O(Data_X_IBUF[2]));
IBUF \Data_X_IBUF[30]_inst
(.I(Data_X[30]),
.O(Data_X_IBUF[30]));
IBUF \Data_X_IBUF[31]_inst
(.I(Data_X[31]),
.O(Data_X_IBUF[31]));
IBUF \Data_X_IBUF[3]_inst
(.I(Data_X[3]),
.O(Data_X_IBUF[3]));
IBUF \Data_X_IBUF[4]_inst
(.I(Data_X[4]),
.O(Data_X_IBUF[4]));
IBUF \Data_X_IBUF[5]_inst
(.I(Data_X[5]),
.O(Data_X_IBUF[5]));
IBUF \Data_X_IBUF[6]_inst
(.I(Data_X[6]),
.O(Data_X_IBUF[6]));
IBUF \Data_X_IBUF[7]_inst
(.I(Data_X[7]),
.O(Data_X_IBUF[7]));
IBUF \Data_X_IBUF[8]_inst
(.I(Data_X[8]),
.O(Data_X_IBUF[8]));
IBUF \Data_X_IBUF[9]_inst
(.I(Data_X[9]),
.O(Data_X_IBUF[9]));
IBUF \Data_Y_IBUF[0]_inst
(.I(Data_Y[0]),
.O(Data_Y_IBUF[0]));
IBUF \Data_Y_IBUF[10]_inst
(.I(Data_Y[10]),
.O(Data_Y_IBUF[10]));
IBUF \Data_Y_IBUF[11]_inst
(.I(Data_Y[11]),
.O(Data_Y_IBUF[11]));
IBUF \Data_Y_IBUF[12]_inst
(.I(Data_Y[12]),
.O(Data_Y_IBUF[12]));
IBUF \Data_Y_IBUF[13]_inst
(.I(Data_Y[13]),
.O(Data_Y_IBUF[13]));
IBUF \Data_Y_IBUF[14]_inst
(.I(Data_Y[14]),
.O(Data_Y_IBUF[14]));
IBUF \Data_Y_IBUF[15]_inst
(.I(Data_Y[15]),
.O(Data_Y_IBUF[15]));
IBUF \Data_Y_IBUF[16]_inst
(.I(Data_Y[16]),
.O(Data_Y_IBUF[16]));
IBUF \Data_Y_IBUF[17]_inst
(.I(Data_Y[17]),
.O(Data_Y_IBUF[17]));
IBUF \Data_Y_IBUF[18]_inst
(.I(Data_Y[18]),
.O(Data_Y_IBUF[18]));
IBUF \Data_Y_IBUF[19]_inst
(.I(Data_Y[19]),
.O(Data_Y_IBUF[19]));
IBUF \Data_Y_IBUF[1]_inst
(.I(Data_Y[1]),
.O(Data_Y_IBUF[1]));
IBUF \Data_Y_IBUF[20]_inst
(.I(Data_Y[20]),
.O(Data_Y_IBUF[20]));
IBUF \Data_Y_IBUF[21]_inst
(.I(Data_Y[21]),
.O(Data_Y_IBUF[21]));
IBUF \Data_Y_IBUF[22]_inst
(.I(Data_Y[22]),
.O(Data_Y_IBUF[22]));
IBUF \Data_Y_IBUF[23]_inst
(.I(Data_Y[23]),
.O(Data_Y_IBUF[23]));
IBUF \Data_Y_IBUF[24]_inst
(.I(Data_Y[24]),
.O(Data_Y_IBUF[24]));
IBUF \Data_Y_IBUF[25]_inst
(.I(Data_Y[25]),
.O(Data_Y_IBUF[25]));
IBUF \Data_Y_IBUF[26]_inst
(.I(Data_Y[26]),
.O(Data_Y_IBUF[26]));
IBUF \Data_Y_IBUF[27]_inst
(.I(Data_Y[27]),
.O(Data_Y_IBUF[27]));
IBUF \Data_Y_IBUF[28]_inst
(.I(Data_Y[28]),
.O(Data_Y_IBUF[28]));
IBUF \Data_Y_IBUF[29]_inst
(.I(Data_Y[29]),
.O(Data_Y_IBUF[29]));
IBUF \Data_Y_IBUF[2]_inst
(.I(Data_Y[2]),
.O(Data_Y_IBUF[2]));
IBUF \Data_Y_IBUF[30]_inst
(.I(Data_Y[30]),
.O(Data_Y_IBUF[30]));
IBUF \Data_Y_IBUF[31]_inst
(.I(Data_Y[31]),
.O(Data_Y_IBUF[31]));
IBUF \Data_Y_IBUF[3]_inst
(.I(Data_Y[3]),
.O(Data_Y_IBUF[3]));
IBUF \Data_Y_IBUF[4]_inst
(.I(Data_Y[4]),
.O(Data_Y_IBUF[4]));
IBUF \Data_Y_IBUF[5]_inst
(.I(Data_Y[5]),
.O(Data_Y_IBUF[5]));
IBUF \Data_Y_IBUF[6]_inst
(.I(Data_Y[6]),
.O(Data_Y_IBUF[6]));
IBUF \Data_Y_IBUF[7]_inst
(.I(Data_Y[7]),
.O(Data_Y_IBUF[7]));
IBUF \Data_Y_IBUF[8]_inst
(.I(Data_Y[8]),
.O(Data_Y_IBUF[8]));
IBUF \Data_Y_IBUF[9]_inst
(.I(Data_Y[9]),
.O(Data_Y_IBUF[9]));
RegisterAdd__parameterized1 EXP_STAGE_DMP
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({Shift_amount_EXP_EW[2],EXP_STAGE_DMP_n_1}),
.Q({EXP_STAGE_DMP_n_2,EXP_STAGE_DMP_n_3,EXP_STAGE_DMP_n_4,EXP_STAGE_DMP_n_5,EXP_STAGE_DMP_n_6,EXP_STAGE_DMP_n_7,EXP_STAGE_DMP_n_8,EXP_STAGE_DMP_n_9,EXP_STAGE_DMP_n_10,EXP_STAGE_DMP_n_11,EXP_STAGE_DMP_n_12,EXP_STAGE_DMP_n_13,EXP_STAGE_DMP_n_14,EXP_STAGE_DMP_n_15,EXP_STAGE_DMP_n_16,EXP_STAGE_DMP_n_17,EXP_STAGE_DMP_n_18,EXP_STAGE_DMP_n_19,EXP_STAGE_DMP_n_20,EXP_STAGE_DMP_n_21,EXP_STAGE_DMP_n_22,EXP_STAGE_DMP_n_23,EXP_STAGE_DMP_n_24,EXP_STAGE_DMP_n_25,EXP_STAGE_DMP_n_26,EXP_STAGE_DMP_n_27,EXP_STAGE_DMP_n_28,EXP_STAGE_DMP_n_29,EXP_STAGE_DMP_n_30,EXP_STAGE_DMP_n_31,EXP_STAGE_DMP_n_32}),
.\Q_reg[25]_0 ({EXP_STAGE_DmP_n_3,EXP_STAGE_DmP_n_4,EXP_STAGE_DmP_n_5}),
.\Q_reg[30]_0 ({MuxXY_n_0,MuxXY_n_1,MuxXY_n_2,MuxXY_n_3,MuxXY_n_4,MuxXY_n_5,MuxXY_n_6,MuxXY_n_7,MuxXY_n_8,MuxXY_n_9,MuxXY_n_10,MuxXY_n_11,MuxXY_n_12,MuxXY_n_13,MuxXY_n_14,MuxXY_n_15,MuxXY_n_16,MuxXY_n_17,MuxXY_n_18,MuxXY_n_19,MuxXY_n_20,MuxXY_n_21,MuxXY_n_22,MuxXY_n_23,MuxXY_n_24,MuxXY_n_25,MuxXY_n_26,MuxXY_n_27,MuxXY_n_28,MuxXY_n_29,MuxXY_n_30}),
.\Q_reg[6]_0 (inst_ShiftRegister_n_1));
RegisterAdd__parameterized2 EXP_STAGE_DmP
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({Shift_amount_EXP_EW[4:3],Shift_amount_EXP_EW[1]}),
.Q({EXP_STAGE_DmP_n_3,EXP_STAGE_DmP_n_4,EXP_STAGE_DmP_n_5,EXP_STAGE_DmP_n_6,EXP_STAGE_DmP_n_7,EXP_STAGE_DmP_n_8,EXP_STAGE_DmP_n_9,EXP_STAGE_DmP_n_10,EXP_STAGE_DmP_n_11,EXP_STAGE_DmP_n_12,EXP_STAGE_DmP_n_13,EXP_STAGE_DmP_n_14,EXP_STAGE_DmP_n_15,EXP_STAGE_DmP_n_16,EXP_STAGE_DmP_n_17,EXP_STAGE_DmP_n_18,EXP_STAGE_DmP_n_19,EXP_STAGE_DmP_n_20,EXP_STAGE_DmP_n_21,EXP_STAGE_DmP_n_22,EXP_STAGE_DmP_n_23,EXP_STAGE_DmP_n_24,EXP_STAGE_DmP_n_25,EXP_STAGE_DmP_n_26,EXP_STAGE_DmP_n_27,EXP_STAGE_DmP_n_28}),
.\Q_reg[27]_0 ({EXP_STAGE_DMP_n_5,EXP_STAGE_DMP_n_6,EXP_STAGE_DMP_n_7,EXP_STAGE_DMP_n_8,EXP_STAGE_DMP_n_9}),
.\Q_reg[27]_1 ({MuxXY_n_31,MuxXY_n_32,MuxXY_n_33,MuxXY_n_34,MuxXY_n_35,MuxXY_n_36,MuxXY_n_37,MuxXY_n_38,MuxXY_n_39,MuxXY_n_40,MuxXY_n_41,MuxXY_n_42,MuxXY_n_43,MuxXY_n_44,MuxXY_n_45,MuxXY_n_46,MuxXY_n_47,MuxXY_n_48,MuxXY_n_49,MuxXY_n_50,MuxXY_n_51,MuxXY_n_52,MuxXY_n_53,MuxXY_n_54,MuxXY_n_55,MuxXY_n_56,MuxXY_n_57,MuxXY_n_58}),
.\Q_reg[6]_0 (inst_ShiftRegister_n_1));
RegisterAdd__parameterized3 EXP_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({SIGN_FLAG_INIT,OP_FLAG_INIT,Magnitude_Comparator_n_2}),
.Q({EXP_STAGE_FLAGS_n_0,EXP_STAGE_FLAGS_n_1,EXP_STAGE_FLAGS_n_2}),
.\Q_reg[6] (inst_ShiftRegister_n_1));
RegisterAdd FRMT_STAGE_DATAOUT
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({formatted_number_W,inst_FRMT_STAGE_n_1,inst_FRMT_STAGE_n_2,inst_FRMT_STAGE_n_3,inst_FRMT_STAGE_n_4,inst_FRMT_STAGE_n_5,inst_FRMT_STAGE_n_6,inst_FRMT_STAGE_n_7,inst_FRMT_STAGE_n_8,inst_FRMT_STAGE_n_9,SHT2_STAGE_SHFTVARS1_n_24,SHT2_STAGE_SHFTVARS1_n_25,SHT2_STAGE_SHFTVARS1_n_26,SHT2_STAGE_SHFTVARS1_n_27,SHT2_STAGE_SHFTVARS1_n_28,SHT2_STAGE_SHFTVARS1_n_29,inst_FRMT_STAGE_n_10,inst_FRMT_STAGE_n_11,SHT2_STAGE_SHFTVARS2_n_8,SHT2_STAGE_SHFTVARS2_n_9,inst_FRMT_STAGE_n_12,inst_FRMT_STAGE_n_13,SHT2_STAGE_SHFTVARS2_n_10,SHT2_STAGE_SHFTVARS2_n_11,inst_FRMT_STAGE_n_14,inst_FRMT_STAGE_n_15,SHT2_STAGE_SHFTVARS1_n_30,SHT2_STAGE_SHFTVARS1_n_31,SHT2_STAGE_SHFTVARS1_n_32,SHT2_STAGE_SHFTVARS1_n_33,SHT2_STAGE_SHFTVARS1_n_34,SHT2_STAGE_SHFTVARS1_n_35}),
.Q(final_result_ieee_OBUF),
.\Q_reg[0]_0 (inst_ShiftRegister_n_6));
RegisterAdd__parameterized21 FRMT_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({overflow_flag_OBUF,underflow_flag_OBUF,zero_flag_OBUF}),
.\Q_reg[0]_0 (inst_ShiftRegister_n_6),
.\Q_reg[0]_1 (SFT2FRMT_STAGE_FLAGS_n_3),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
RegisterAdd__parameterized0 INPUT_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.E(enable_Pipeline_input),
.add_subt_IBUF(add_subt_IBUF),
.intAS(intAS));
RegisterAdd_0 INPUT_STAGE_OPERANDX
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D(OP_FLAG_INIT),
.DI({INPUT_STAGE_OPERANDX_n_0,INPUT_STAGE_OPERANDX_n_1,INPUT_STAGE_OPERANDX_n_2,INPUT_STAGE_OPERANDX_n_3}),
.\Data_X[31] (Data_X_IBUF),
.E(enable_Pipeline_input),
.Q({intDX_EWSW,INPUT_STAGE_OPERANDX_n_5,INPUT_STAGE_OPERANDX_n_6,INPUT_STAGE_OPERANDX_n_7,INPUT_STAGE_OPERANDX_n_8,INPUT_STAGE_OPERANDX_n_9,INPUT_STAGE_OPERANDX_n_10,INPUT_STAGE_OPERANDX_n_11,INPUT_STAGE_OPERANDX_n_12,INPUT_STAGE_OPERANDX_n_13,INPUT_STAGE_OPERANDX_n_14,INPUT_STAGE_OPERANDX_n_15,INPUT_STAGE_OPERANDX_n_16,INPUT_STAGE_OPERANDX_n_17,INPUT_STAGE_OPERANDX_n_18,INPUT_STAGE_OPERANDX_n_19,INPUT_STAGE_OPERANDX_n_20,INPUT_STAGE_OPERANDX_n_21,INPUT_STAGE_OPERANDX_n_22,INPUT_STAGE_OPERANDX_n_23,INPUT_STAGE_OPERANDX_n_24,INPUT_STAGE_OPERANDX_n_25,INPUT_STAGE_OPERANDX_n_26,INPUT_STAGE_OPERANDX_n_27,INPUT_STAGE_OPERANDX_n_28,INPUT_STAGE_OPERANDX_n_29,INPUT_STAGE_OPERANDX_n_30,INPUT_STAGE_OPERANDX_n_31,INPUT_STAGE_OPERANDX_n_32,INPUT_STAGE_OPERANDX_n_33,INPUT_STAGE_OPERANDX_n_34,INPUT_STAGE_OPERANDX_n_35}),
.\Q_reg[0]_0 ({INPUT_STAGE_OPERANDX_n_40,INPUT_STAGE_OPERANDX_n_41,INPUT_STAGE_OPERANDX_n_42,INPUT_STAGE_OPERANDX_n_43}),
.\Q_reg[0]_1 ({INPUT_STAGE_OPERANDX_n_56,INPUT_STAGE_OPERANDX_n_57,INPUT_STAGE_OPERANDX_n_58,INPUT_STAGE_OPERANDX_n_59}),
.\Q_reg[0]_2 ({INPUT_STAGE_OPERANDX_n_71,INPUT_STAGE_OPERANDX_n_72}),
.\Q_reg[2]_0 ({INPUT_STAGE_OPERANDX_n_44,INPUT_STAGE_OPERANDX_n_45,INPUT_STAGE_OPERANDX_n_46,INPUT_STAGE_OPERANDX_n_47}),
.\Q_reg[2]_1 ({INPUT_STAGE_OPERANDX_n_48,INPUT_STAGE_OPERANDX_n_49,INPUT_STAGE_OPERANDX_n_50,INPUT_STAGE_OPERANDX_n_51}),
.\Q_reg[2]_2 ({INPUT_STAGE_OPERANDX_n_52,INPUT_STAGE_OPERANDX_n_53,INPUT_STAGE_OPERANDX_n_54,INPUT_STAGE_OPERANDX_n_55}),
.\Q_reg[2]_3 ({INPUT_STAGE_OPERANDX_n_60,INPUT_STAGE_OPERANDX_n_61,INPUT_STAGE_OPERANDX_n_62,INPUT_STAGE_OPERANDX_n_63}),
.\Q_reg[2]_4 ({INPUT_STAGE_OPERANDX_n_64,INPUT_STAGE_OPERANDX_n_65,INPUT_STAGE_OPERANDX_n_66,INPUT_STAGE_OPERANDX_n_67}),
.\Q_reg[2]_5 ({INPUT_STAGE_OPERANDX_n_68,INPUT_STAGE_OPERANDX_n_69,INPUT_STAGE_OPERANDX_n_70}),
.\Q_reg[31]_0 ({intDY_EWSW,INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}),
.S({INPUT_STAGE_OPERANDX_n_36,INPUT_STAGE_OPERANDX_n_37,INPUT_STAGE_OPERANDX_n_38,INPUT_STAGE_OPERANDX_n_39}),
.intAS(intAS));
RegisterAdd_1 INPUT_STAGE_OPERANDY
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D(Data_Y_IBUF),
.E(enable_Pipeline_input),
.Q({intDY_EWSW,INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}),
.\Q_reg[2]_0 (INPUT_STAGE_OPERANDY_n_33),
.\Q_reg[30]_0 (INPUT_STAGE_OPERANDX_n_5),
.S(INPUT_STAGE_OPERANDY_n_0));
Comparator Magnitude_Comparator
(.CO(gtXY),
.D(Magnitude_Comparator_n_2),
.DI({INPUT_STAGE_OPERANDX_n_0,INPUT_STAGE_OPERANDX_n_1,INPUT_STAGE_OPERANDX_n_2,INPUT_STAGE_OPERANDX_n_3}),
.Q(intDY_EWSW),
.\Q_reg[0] (eqXY),
.\Q_reg[14] ({INPUT_STAGE_OPERANDX_n_44,INPUT_STAGE_OPERANDX_n_45,INPUT_STAGE_OPERANDX_n_46,INPUT_STAGE_OPERANDX_n_47}),
.\Q_reg[14]_0 ({INPUT_STAGE_OPERANDX_n_48,INPUT_STAGE_OPERANDX_n_49,INPUT_STAGE_OPERANDX_n_50,INPUT_STAGE_OPERANDX_n_51}),
.\Q_reg[21] ({INPUT_STAGE_OPERANDX_n_56,INPUT_STAGE_OPERANDX_n_57,INPUT_STAGE_OPERANDX_n_58,INPUT_STAGE_OPERANDX_n_59}),
.\Q_reg[22] ({INPUT_STAGE_OPERANDX_n_52,INPUT_STAGE_OPERANDX_n_53,INPUT_STAGE_OPERANDX_n_54,INPUT_STAGE_OPERANDX_n_55}),
.\Q_reg[22]_0 ({INPUT_STAGE_OPERANDX_n_60,INPUT_STAGE_OPERANDX_n_61,INPUT_STAGE_OPERANDX_n_62,INPUT_STAGE_OPERANDX_n_63}),
.\Q_reg[30] ({INPUT_STAGE_OPERANDX_n_64,INPUT_STAGE_OPERANDX_n_65,INPUT_STAGE_OPERANDX_n_66,INPUT_STAGE_OPERANDX_n_67}),
.\Q_reg[30]_0 ({INPUT_STAGE_OPERANDY_n_33,INPUT_STAGE_OPERANDX_n_68,INPUT_STAGE_OPERANDX_n_69,INPUT_STAGE_OPERANDX_n_70}),
.\Q_reg[30]_1 ({INPUT_STAGE_OPERANDY_n_0,INPUT_STAGE_OPERANDX_n_71,INPUT_STAGE_OPERANDX_n_72}),
.\Q_reg[31] (intDX_EWSW),
.\Q_reg[9] ({INPUT_STAGE_OPERANDX_n_40,INPUT_STAGE_OPERANDX_n_41,INPUT_STAGE_OPERANDX_n_42,INPUT_STAGE_OPERANDX_n_43}),
.S({INPUT_STAGE_OPERANDX_n_36,INPUT_STAGE_OPERANDX_n_37,INPUT_STAGE_OPERANDX_n_38,INPUT_STAGE_OPERANDX_n_39}),
.intAS(intAS));
MultiplexTxT MuxXY
(.CO(gtXY),
.Q({INPUT_STAGE_OPERANDX_n_5,INPUT_STAGE_OPERANDX_n_6,INPUT_STAGE_OPERANDX_n_7,INPUT_STAGE_OPERANDX_n_8,INPUT_STAGE_OPERANDX_n_9,INPUT_STAGE_OPERANDX_n_10,INPUT_STAGE_OPERANDX_n_11,INPUT_STAGE_OPERANDX_n_12,INPUT_STAGE_OPERANDX_n_13,INPUT_STAGE_OPERANDX_n_14,INPUT_STAGE_OPERANDX_n_15,INPUT_STAGE_OPERANDX_n_16,INPUT_STAGE_OPERANDX_n_17,INPUT_STAGE_OPERANDX_n_18,INPUT_STAGE_OPERANDX_n_19,INPUT_STAGE_OPERANDX_n_20,INPUT_STAGE_OPERANDX_n_21,INPUT_STAGE_OPERANDX_n_22,INPUT_STAGE_OPERANDX_n_23,INPUT_STAGE_OPERANDX_n_24,INPUT_STAGE_OPERANDX_n_25,INPUT_STAGE_OPERANDX_n_26,INPUT_STAGE_OPERANDX_n_27,INPUT_STAGE_OPERANDX_n_28,INPUT_STAGE_OPERANDX_n_29,INPUT_STAGE_OPERANDX_n_30,INPUT_STAGE_OPERANDX_n_31,INPUT_STAGE_OPERANDX_n_32,INPUT_STAGE_OPERANDX_n_33,INPUT_STAGE_OPERANDX_n_34,INPUT_STAGE_OPERANDX_n_35}),
.\Q_reg[27] ({MuxXY_n_31,MuxXY_n_32,MuxXY_n_33,MuxXY_n_34,MuxXY_n_35,MuxXY_n_36,MuxXY_n_37,MuxXY_n_38,MuxXY_n_39,MuxXY_n_40,MuxXY_n_41,MuxXY_n_42,MuxXY_n_43,MuxXY_n_44,MuxXY_n_45,MuxXY_n_46,MuxXY_n_47,MuxXY_n_48,MuxXY_n_49,MuxXY_n_50,MuxXY_n_51,MuxXY_n_52,MuxXY_n_53,MuxXY_n_54,MuxXY_n_55,MuxXY_n_56,MuxXY_n_57,MuxXY_n_58}),
.\Q_reg[30] ({MuxXY_n_0,MuxXY_n_1,MuxXY_n_2,MuxXY_n_3,MuxXY_n_4,MuxXY_n_5,MuxXY_n_6,MuxXY_n_7,MuxXY_n_8,MuxXY_n_9,MuxXY_n_10,MuxXY_n_11,MuxXY_n_12,MuxXY_n_13,MuxXY_n_14,MuxXY_n_15,MuxXY_n_16,MuxXY_n_17,MuxXY_n_18,MuxXY_n_19,MuxXY_n_20,MuxXY_n_21,MuxXY_n_22,MuxXY_n_23,MuxXY_n_24,MuxXY_n_25,MuxXY_n_26,MuxXY_n_27,MuxXY_n_28,MuxXY_n_29,MuxXY_n_30}),
.\Q_reg[30]_0 ({INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}));
RegisterAdd__parameterized19 NRM_STAGE_DMP_exp
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.Q({NRM_STAGE_DMP_exp_n_0,NRM_STAGE_DMP_exp_n_1,NRM_STAGE_DMP_exp_n_2,NRM_STAGE_DMP_exp_n_3,NRM_STAGE_DMP_exp_n_4,NRM_STAGE_DMP_exp_n_5,NRM_STAGE_DMP_exp_n_6,NRM_STAGE_DMP_exp_n_7}),
.\Q_reg[2]_0 (inst_ShiftRegister_n_4),
.\Q_reg[30] ({SGF_STAGE_DMP_n_4,SGF_STAGE_DMP_n_5,SGF_STAGE_DMP_n_6,SGF_STAGE_DMP_n_7,SGF_STAGE_DMP_n_8,SGF_STAGE_DMP_n_9,SGF_STAGE_DMP_n_10,SGF_STAGE_DMP_n_11}));
RegisterAdd__parameterized20 NRM_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D(bit_shift_SHT1),
.Q({ADD_OVRFLW_NRM,NRM_STAGE_FLAGS_n_2,NRM_STAGE_FLAGS_n_3}),
.\Q_reg[1]_0 ({p_3_out,SGF_STAGE_FLAGS_n_1,p_0_in}),
.\Q_reg[2]_0 ({inst_ShiftRegister_n_4,Shift_reg_FLAGS_7}));
RegisterAdd__parameterized18 NRM_STAGE_Raw_mant
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D(\Data_array_SWR[2] ),
.Q(ADD_OVRFLW_NRM),
.\Q_reg[12]_0 ({NRM_STAGE_Raw_mant_n_26,LZD_raw_out_EWR,NRM_STAGE_Raw_mant_n_28,NRM_STAGE_Raw_mant_n_29,NRM_STAGE_Raw_mant_n_30}),
.\Q_reg[1]_0 (Raw_mant_SGF),
.\Q_reg[22]_0 ({SHT1_STAGE_DmP_mant_n_0,SHT1_STAGE_DmP_mant_n_1,SHT1_STAGE_DmP_mant_n_2,SHT1_STAGE_DmP_mant_n_3,SHT1_STAGE_DmP_mant_n_4,SHT1_STAGE_DmP_mant_n_5,SHT1_STAGE_DmP_mant_n_6,SHT1_STAGE_DmP_mant_n_7,SHT1_STAGE_DmP_mant_n_8,SHT1_STAGE_DmP_mant_n_9,SHT1_STAGE_DmP_mant_n_10,SHT1_STAGE_DmP_mant_n_11,SHT1_STAGE_DmP_mant_n_12,SHT1_STAGE_DmP_mant_n_13,SHT1_STAGE_DmP_mant_n_14,SHT1_STAGE_DmP_mant_n_15,SHT1_STAGE_DmP_mant_n_16,SHT1_STAGE_DmP_mant_n_17,SHT1_STAGE_DmP_mant_n_18,SHT1_STAGE_DmP_mant_n_19,SHT1_STAGE_DmP_mant_n_20,SHT1_STAGE_DmP_mant_n_21,SHT1_STAGE_DmP_mant_n_22}),
.\Q_reg[2]_0 ({inst_ShiftRegister_n_4,Shift_reg_FLAGS_7}),
.\Q_reg[2]_1 (bit_shift_SHT1),
.\Q_reg[4]_0 (shft_value_mux_o_EWR),
.\Q_reg[4]_1 (Shift_amount_SHT1_EWR));
RegisterAdd__parameterized22 Ready_reg
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.Q(inst_ShiftRegister_n_6),
.ready_OBUF(ready_OBUF));
RegisterAdd__parameterized14 SFT2FRMT_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({ADD_OVRFLW_NRM,NRM_STAGE_FLAGS_n_2,NRM_STAGE_FLAGS_n_3}),
.DI(SFT2FRMT_STAGE_FLAGS_n_0),
.Q({ADD_OVRFLW_NRM2,SIGN_FLAG_SHT1SHT2,SFT2FRMT_STAGE_FLAGS_n_3}),
.\Q_reg[1]_0 (Shift_reg_FLAGS_7));
RegisterAdd__parameterized13 SFT2FRMT_STAGE_VARS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({NRM_STAGE_Raw_mant_n_26,LZD_raw_out_EWR,NRM_STAGE_Raw_mant_n_28,NRM_STAGE_Raw_mant_n_29,NRM_STAGE_Raw_mant_n_30,NRM_STAGE_DMP_exp_n_0,NRM_STAGE_DMP_exp_n_1,NRM_STAGE_DMP_exp_n_2,NRM_STAGE_DMP_exp_n_3,NRM_STAGE_DMP_exp_n_4,NRM_STAGE_DMP_exp_n_5,NRM_STAGE_DMP_exp_n_6,NRM_STAGE_DMP_exp_n_7}),
.Q(ADD_OVRFLW_NRM2),
.\Q_reg[1]_0 ({SFT2FRMT_STAGE_VARS_n_5,SFT2FRMT_STAGE_VARS_n_6,SFT2FRMT_STAGE_VARS_n_7,SFT2FRMT_STAGE_VARS_n_8,SFT2FRMT_STAGE_VARS_n_9,SFT2FRMT_STAGE_VARS_n_10,SFT2FRMT_STAGE_VARS_n_11}),
.\Q_reg[1]_1 ({SFT2FRMT_STAGE_VARS_n_12,SFT2FRMT_STAGE_VARS_n_13,SFT2FRMT_STAGE_VARS_n_14,SFT2FRMT_STAGE_VARS_n_15}),
.\Q_reg[1]_2 (Shift_reg_FLAGS_7),
.\Q_reg[2]_0 ({SFT2FRMT_STAGE_VARS_n_1,SFT2FRMT_STAGE_VARS_n_2,SFT2FRMT_STAGE_VARS_n_3,SFT2FRMT_STAGE_VARS_n_4}),
.S(SFT2FRMT_STAGE_VARS_n_0));
RegisterAdd__parameterized15 SGF_STAGE_DMP
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.CO(SGF_STAGE_DMP_n_51),
.E(load0),
.O({SGF_STAGE_DMP_n_0,SGF_STAGE_DMP_n_1,SGF_STAGE_DMP_n_2,SGF_STAGE_DMP_n_3}),
.Q({SGF_STAGE_DMP_n_4,SGF_STAGE_DMP_n_5,SGF_STAGE_DMP_n_6,SGF_STAGE_DMP_n_7,SGF_STAGE_DMP_n_8,SGF_STAGE_DMP_n_9,SGF_STAGE_DMP_n_10,SGF_STAGE_DMP_n_11,DMP_mant_SFG_SWR}),
.\Q_reg[12]_0 ({SGF_STAGE_DMP_n_39,SGF_STAGE_DMP_n_40,SGF_STAGE_DMP_n_41,SGF_STAGE_DMP_n_42}),
.\Q_reg[16]_0 ({SGF_STAGE_DMP_n_43,SGF_STAGE_DMP_n_44,SGF_STAGE_DMP_n_45,SGF_STAGE_DMP_n_46}),
.\Q_reg[20]_0 ({SGF_STAGE_DMP_n_47,SGF_STAGE_DMP_n_48,SGF_STAGE_DMP_n_49,SGF_STAGE_DMP_n_50}),
.\Q_reg[24]_0 ({SGF_STAGE_DMP_n_52,SGF_STAGE_DMP_n_53,SGF_STAGE_DMP_n_54,SGF_STAGE_DMP_n_55}),
.\Q_reg[24]_1 ({SGF_STAGE_DmP_mant_n_27,SGF_STAGE_DmP_mant_n_28,SGF_STAGE_DmP_mant_n_29,SGF_STAGE_DmP_mant_n_30,SGF_STAGE_DmP_mant_n_31,SGF_STAGE_DmP_mant_n_32,SGF_STAGE_DmP_mant_n_33,SGF_STAGE_DmP_mant_n_34,SGF_STAGE_DmP_mant_n_35,SGF_STAGE_DmP_mant_n_36,SGF_STAGE_DmP_mant_n_37,SGF_STAGE_DmP_mant_n_38,SGF_STAGE_DmP_mant_n_39,SGF_STAGE_DmP_mant_n_40,SGF_STAGE_DmP_mant_n_41,SGF_STAGE_DmP_mant_n_42,SGF_STAGE_DmP_mant_n_43,SGF_STAGE_DmP_mant_n_44,SGF_STAGE_DmP_mant_n_45,SGF_STAGE_DmP_mant_n_46,SGF_STAGE_DmP_mant_n_47,SGF_STAGE_DmP_mant_n_48,SGF_STAGE_DmP_mant_n_49}),
.\Q_reg[30]_0 ({SHT2_STAGE_DMP_n_0,SHT2_STAGE_DMP_n_1,SHT2_STAGE_DMP_n_2,SHT2_STAGE_DMP_n_3,SHT2_STAGE_DMP_n_4,SHT2_STAGE_DMP_n_5,SHT2_STAGE_DMP_n_6,SHT2_STAGE_DMP_n_7,SHT2_STAGE_DMP_n_8,SHT2_STAGE_DMP_n_9,SHT2_STAGE_DMP_n_10,SHT2_STAGE_DMP_n_11,SHT2_STAGE_DMP_n_12,SHT2_STAGE_DMP_n_13,SHT2_STAGE_DMP_n_14,SHT2_STAGE_DMP_n_15,SHT2_STAGE_DMP_n_16,SHT2_STAGE_DMP_n_17,SHT2_STAGE_DMP_n_18,SHT2_STAGE_DMP_n_19,SHT2_STAGE_DMP_n_20,SHT2_STAGE_DMP_n_21,SHT2_STAGE_DMP_n_22,SHT2_STAGE_DMP_n_23,SHT2_STAGE_DMP_n_24,SHT2_STAGE_DMP_n_25,SHT2_STAGE_DMP_n_26,SHT2_STAGE_DMP_n_27,SHT2_STAGE_DMP_n_28,SHT2_STAGE_DMP_n_29,SHT2_STAGE_DMP_n_30}),
.\Q_reg[8]_0 ({SGF_STAGE_DMP_n_35,SGF_STAGE_DMP_n_36,SGF_STAGE_DMP_n_37,SGF_STAGE_DMP_n_38}),
.S(SGF_STAGE_DmP_mant_n_51));
RegisterAdd__parameterized16 SGF_STAGE_DmP_mant
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.CO(p_2_in),
.D(sftr_odat_SHT2_SWR),
.E(load0),
.O({SGF_STAGE_DmP_mant_n_0,SGF_STAGE_DmP_mant_n_1,SGF_STAGE_DmP_mant_n_2,SGF_STAGE_DmP_mant_n_3}),
.Q(DMP_mant_SFG_SWR),
.\Q_reg[12]_0 ({SGF_STAGE_DmP_mant_n_8,SGF_STAGE_DmP_mant_n_9,SGF_STAGE_DmP_mant_n_10,SGF_STAGE_DmP_mant_n_11}),
.\Q_reg[16]_0 ({SGF_STAGE_DmP_mant_n_12,SGF_STAGE_DmP_mant_n_13,SGF_STAGE_DmP_mant_n_14,SGF_STAGE_DmP_mant_n_15}),
.\Q_reg[20]_0 ({SGF_STAGE_DmP_mant_n_16,SGF_STAGE_DmP_mant_n_17,SGF_STAGE_DmP_mant_n_18,SGF_STAGE_DmP_mant_n_19}),
.\Q_reg[22]_0 (SGF_STAGE_DMP_n_51),
.\Q_reg[24]_0 ({SGF_STAGE_DmP_mant_n_20,SGF_STAGE_DmP_mant_n_21,SGF_STAGE_DmP_mant_n_22,SGF_STAGE_DmP_mant_n_23}),
.\Q_reg[24]_1 ({SGF_STAGE_DmP_mant_n_27,SGF_STAGE_DmP_mant_n_28,SGF_STAGE_DmP_mant_n_29,SGF_STAGE_DmP_mant_n_30,SGF_STAGE_DmP_mant_n_31,SGF_STAGE_DmP_mant_n_32,SGF_STAGE_DmP_mant_n_33,SGF_STAGE_DmP_mant_n_34,SGF_STAGE_DmP_mant_n_35,SGF_STAGE_DmP_mant_n_36,SGF_STAGE_DmP_mant_n_37,SGF_STAGE_DmP_mant_n_38,SGF_STAGE_DmP_mant_n_39,SGF_STAGE_DmP_mant_n_40,SGF_STAGE_DmP_mant_n_41,SGF_STAGE_DmP_mant_n_42,SGF_STAGE_DmP_mant_n_43,SGF_STAGE_DmP_mant_n_44,SGF_STAGE_DmP_mant_n_45,SGF_STAGE_DmP_mant_n_46,SGF_STAGE_DmP_mant_n_47,SGF_STAGE_DmP_mant_n_48,SGF_STAGE_DmP_mant_n_49,Raw_mant_SGF[0]}),
.\Q_reg[25]_0 (SGF_STAGE_DmP_mant_n_24),
.\Q_reg[25]_1 (SGF_STAGE_DmP_mant_n_26),
.\Q_reg[8]_0 ({SGF_STAGE_DmP_mant_n_4,SGF_STAGE_DmP_mant_n_5,SGF_STAGE_DmP_mant_n_6,SGF_STAGE_DmP_mant_n_7}),
.S(SGF_STAGE_DmP_mant_n_51));
RegisterAdd__parameterized17 SGF_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.CO(p_2_in),
.E(load0),
.O({SGF_STAGE_DmP_mant_n_0,SGF_STAGE_DmP_mant_n_1,SGF_STAGE_DmP_mant_n_2,SGF_STAGE_DmP_mant_n_3}),
.Q({SHT2_STAGE_FLAGS_n_0,SHT2_STAGE_FLAGS_n_1,SHT2_STAGE_FLAGS_n_2}),
.\Q_reg[10] ({SGF_STAGE_DmP_mant_n_8,SGF_STAGE_DmP_mant_n_9,SGF_STAGE_DmP_mant_n_10,SGF_STAGE_DmP_mant_n_11}),
.\Q_reg[10]_0 ({SGF_STAGE_DMP_n_39,SGF_STAGE_DMP_n_40,SGF_STAGE_DMP_n_41,SGF_STAGE_DMP_n_42}),
.\Q_reg[14] ({SGF_STAGE_DmP_mant_n_12,SGF_STAGE_DmP_mant_n_13,SGF_STAGE_DmP_mant_n_14,SGF_STAGE_DmP_mant_n_15}),
.\Q_reg[14]_0 ({SGF_STAGE_DMP_n_43,SGF_STAGE_DMP_n_44,SGF_STAGE_DMP_n_45,SGF_STAGE_DMP_n_46}),
.\Q_reg[18] ({SGF_STAGE_DmP_mant_n_16,SGF_STAGE_DmP_mant_n_17,SGF_STAGE_DmP_mant_n_18,SGF_STAGE_DmP_mant_n_19}),
.\Q_reg[18]_0 ({SGF_STAGE_DMP_n_47,SGF_STAGE_DMP_n_48,SGF_STAGE_DMP_n_49,SGF_STAGE_DMP_n_50}),
.\Q_reg[22] ({SGF_STAGE_DmP_mant_n_20,SGF_STAGE_DmP_mant_n_21,SGF_STAGE_DmP_mant_n_22,SGF_STAGE_DmP_mant_n_23}),
.\Q_reg[22]_0 ({SGF_STAGE_DMP_n_52,SGF_STAGE_DMP_n_53,SGF_STAGE_DMP_n_54,SGF_STAGE_DMP_n_55}),
.\Q_reg[22]_1 (SGF_STAGE_DmP_mant_n_24),
.\Q_reg[25] (Raw_mant_SGF[25:1]),
.\Q_reg[25]_0 (SGF_STAGE_DmP_mant_n_26),
.\Q_reg[2]_0 ({p_3_out,SGF_STAGE_FLAGS_n_1,p_0_in}),
.\Q_reg[2]_1 ({SGF_STAGE_DMP_n_0,SGF_STAGE_DMP_n_1,SGF_STAGE_DMP_n_2,SGF_STAGE_DMP_n_3}),
.\Q_reg[6] ({SGF_STAGE_DmP_mant_n_4,SGF_STAGE_DmP_mant_n_5,SGF_STAGE_DmP_mant_n_6,SGF_STAGE_DmP_mant_n_7}),
.\Q_reg[6]_0 ({SGF_STAGE_DMP_n_35,SGF_STAGE_DMP_n_36,SGF_STAGE_DMP_n_37,SGF_STAGE_DMP_n_38}));
RegisterAdd__parameterized4 SHT1_STAGE_DMP
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({EXP_STAGE_DMP_n_2,EXP_STAGE_DMP_n_3,EXP_STAGE_DMP_n_4,EXP_STAGE_DMP_n_5,EXP_STAGE_DMP_n_6,EXP_STAGE_DMP_n_7,EXP_STAGE_DMP_n_8,EXP_STAGE_DMP_n_9,EXP_STAGE_DMP_n_10,EXP_STAGE_DMP_n_11,EXP_STAGE_DMP_n_12,EXP_STAGE_DMP_n_13,EXP_STAGE_DMP_n_14,EXP_STAGE_DMP_n_15,EXP_STAGE_DMP_n_16,EXP_STAGE_DMP_n_17,EXP_STAGE_DMP_n_18,EXP_STAGE_DMP_n_19,EXP_STAGE_DMP_n_20,EXP_STAGE_DMP_n_21,EXP_STAGE_DMP_n_22,EXP_STAGE_DMP_n_23,EXP_STAGE_DMP_n_24,EXP_STAGE_DMP_n_25,EXP_STAGE_DMP_n_26,EXP_STAGE_DMP_n_27,EXP_STAGE_DMP_n_28,EXP_STAGE_DMP_n_29,EXP_STAGE_DMP_n_30,EXP_STAGE_DMP_n_31,EXP_STAGE_DMP_n_32}),
.Q({SHT1_STAGE_DMP_n_0,SHT1_STAGE_DMP_n_1,SHT1_STAGE_DMP_n_2,SHT1_STAGE_DMP_n_3,SHT1_STAGE_DMP_n_4,SHT1_STAGE_DMP_n_5,SHT1_STAGE_DMP_n_6,SHT1_STAGE_DMP_n_7,SHT1_STAGE_DMP_n_8,SHT1_STAGE_DMP_n_9,SHT1_STAGE_DMP_n_10,SHT1_STAGE_DMP_n_11,SHT1_STAGE_DMP_n_12,SHT1_STAGE_DMP_n_13,SHT1_STAGE_DMP_n_14,SHT1_STAGE_DMP_n_15,SHT1_STAGE_DMP_n_16,SHT1_STAGE_DMP_n_17,SHT1_STAGE_DMP_n_18,SHT1_STAGE_DMP_n_19,SHT1_STAGE_DMP_n_20,SHT1_STAGE_DMP_n_21,SHT1_STAGE_DMP_n_22,SHT1_STAGE_DMP_n_23,SHT1_STAGE_DMP_n_24,SHT1_STAGE_DMP_n_25,SHT1_STAGE_DMP_n_26,SHT1_STAGE_DMP_n_27,SHT1_STAGE_DMP_n_28,SHT1_STAGE_DMP_n_29,SHT1_STAGE_DMP_n_30}),
.\Q_reg[5]_0 (inst_ShiftRegister_n_2));
RegisterAdd__parameterized5 SHT1_STAGE_DmP_mant
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({EXP_STAGE_DmP_n_6,EXP_STAGE_DmP_n_7,EXP_STAGE_DmP_n_8,EXP_STAGE_DmP_n_9,EXP_STAGE_DmP_n_10,EXP_STAGE_DmP_n_11,EXP_STAGE_DmP_n_12,EXP_STAGE_DmP_n_13,EXP_STAGE_DmP_n_14,EXP_STAGE_DmP_n_15,EXP_STAGE_DmP_n_16,EXP_STAGE_DmP_n_17,EXP_STAGE_DmP_n_18,EXP_STAGE_DmP_n_19,EXP_STAGE_DmP_n_20,EXP_STAGE_DmP_n_21,EXP_STAGE_DmP_n_22,EXP_STAGE_DmP_n_23,EXP_STAGE_DmP_n_24,EXP_STAGE_DmP_n_25,EXP_STAGE_DmP_n_26,EXP_STAGE_DmP_n_27,EXP_STAGE_DmP_n_28}),
.Q({SHT1_STAGE_DmP_mant_n_0,SHT1_STAGE_DmP_mant_n_1,SHT1_STAGE_DmP_mant_n_2,SHT1_STAGE_DmP_mant_n_3,SHT1_STAGE_DmP_mant_n_4,SHT1_STAGE_DmP_mant_n_5,SHT1_STAGE_DmP_mant_n_6,SHT1_STAGE_DmP_mant_n_7,SHT1_STAGE_DmP_mant_n_8,SHT1_STAGE_DmP_mant_n_9,SHT1_STAGE_DmP_mant_n_10,SHT1_STAGE_DmP_mant_n_11,SHT1_STAGE_DmP_mant_n_12,SHT1_STAGE_DmP_mant_n_13,SHT1_STAGE_DmP_mant_n_14,SHT1_STAGE_DmP_mant_n_15,SHT1_STAGE_DmP_mant_n_16,SHT1_STAGE_DmP_mant_n_17,SHT1_STAGE_DmP_mant_n_18,SHT1_STAGE_DmP_mant_n_19,SHT1_STAGE_DmP_mant_n_20,SHT1_STAGE_DmP_mant_n_21,SHT1_STAGE_DmP_mant_n_22}),
.\Q_reg[5]_0 (inst_ShiftRegister_n_2));
RegisterAdd__parameterized7 SHT1_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({EXP_STAGE_FLAGS_n_0,EXP_STAGE_FLAGS_n_1,EXP_STAGE_FLAGS_n_2}),
.Q({SHT1_STAGE_FLAGS_n_0,SHT1_STAGE_FLAGS_n_1,SHT1_STAGE_FLAGS_n_2}),
.\Q_reg[5] (inst_ShiftRegister_n_2));
RegisterAdd__parameterized6 SHT1_STAGE_sft_amount
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({Shift_amount_EXP_EW,EXP_STAGE_DMP_n_1}),
.Q(Shift_amount_SHT1_EWR),
.\Q_reg[5] (inst_ShiftRegister_n_2));
RegisterAdd__parameterized9 SHT2_SHIFT_DATA
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({sftr_odat_SHT2_SWR[25:24],sftr_odat_SHT2_SWR[13:12],sftr_odat_SHT2_SWR[0]}),
.\Data_array_SWR[4] (\Data_array_SWR[4] ),
.\Data_array_SWR[6] (\Data_array_SWR[6] [1]),
.E(inst_ShiftRegister_n_0),
.Q({left_right_SHT2,SHT2_STAGE_SHFTVARS2_n_7}),
.\Q_reg[0]_0 (\Data_array_SWR[2] ),
.\Q_reg[13]_0 (\Data_array_SWR[3] ),
.\Q_reg[4]_0 (shift_value_SHT2_EWR),
.\Q_reg[4]_1 (\Data_array_SWR[6] [25:24]),
.\Q_reg[8]_0 ({\Data_array_SWR[5] [17:16],\Data_array_SWR[5] [11:2]}));
RegisterAdd__parameterized8 SHT2_STAGE_DMP
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({SHT1_STAGE_DMP_n_0,SHT1_STAGE_DMP_n_1,SHT1_STAGE_DMP_n_2,SHT1_STAGE_DMP_n_3,SHT1_STAGE_DMP_n_4,SHT1_STAGE_DMP_n_5,SHT1_STAGE_DMP_n_6,SHT1_STAGE_DMP_n_7,SHT1_STAGE_DMP_n_8,SHT1_STAGE_DMP_n_9,SHT1_STAGE_DMP_n_10,SHT1_STAGE_DMP_n_11,SHT1_STAGE_DMP_n_12,SHT1_STAGE_DMP_n_13,SHT1_STAGE_DMP_n_14,SHT1_STAGE_DMP_n_15,SHT1_STAGE_DMP_n_16,SHT1_STAGE_DMP_n_17,SHT1_STAGE_DMP_n_18,SHT1_STAGE_DMP_n_19,SHT1_STAGE_DMP_n_20,SHT1_STAGE_DMP_n_21,SHT1_STAGE_DMP_n_22,SHT1_STAGE_DMP_n_23,SHT1_STAGE_DMP_n_24,SHT1_STAGE_DMP_n_25,SHT1_STAGE_DMP_n_26,SHT1_STAGE_DMP_n_27,SHT1_STAGE_DMP_n_28,SHT1_STAGE_DMP_n_29,SHT1_STAGE_DMP_n_30}),
.Q({SHT2_STAGE_DMP_n_0,SHT2_STAGE_DMP_n_1,SHT2_STAGE_DMP_n_2,SHT2_STAGE_DMP_n_3,SHT2_STAGE_DMP_n_4,SHT2_STAGE_DMP_n_5,SHT2_STAGE_DMP_n_6,SHT2_STAGE_DMP_n_7,SHT2_STAGE_DMP_n_8,SHT2_STAGE_DMP_n_9,SHT2_STAGE_DMP_n_10,SHT2_STAGE_DMP_n_11,SHT2_STAGE_DMP_n_12,SHT2_STAGE_DMP_n_13,SHT2_STAGE_DMP_n_14,SHT2_STAGE_DMP_n_15,SHT2_STAGE_DMP_n_16,SHT2_STAGE_DMP_n_17,SHT2_STAGE_DMP_n_18,SHT2_STAGE_DMP_n_19,SHT2_STAGE_DMP_n_20,SHT2_STAGE_DMP_n_21,SHT2_STAGE_DMP_n_22,SHT2_STAGE_DMP_n_23,SHT2_STAGE_DMP_n_24,SHT2_STAGE_DMP_n_25,SHT2_STAGE_DMP_n_26,SHT2_STAGE_DMP_n_27,SHT2_STAGE_DMP_n_28,SHT2_STAGE_DMP_n_29,SHT2_STAGE_DMP_n_30}),
.\Q_reg[4]_0 (busy_OBUF));
RegisterAdd__parameterized12 SHT2_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({SHT1_STAGE_FLAGS_n_0,SHT1_STAGE_FLAGS_n_1,SHT1_STAGE_FLAGS_n_2}),
.Q({SHT2_STAGE_FLAGS_n_0,SHT2_STAGE_FLAGS_n_1,SHT2_STAGE_FLAGS_n_2}),
.\Q_reg[4] (busy_OBUF));
RegisterAdd__parameterized10 SHT2_STAGE_SHFTVARS1
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({sftr_odat_SHT2_SWR[23:16],sftr_odat_SHT2_SWR[7:1]}),
.\Data_array_SWR[4] (\Data_array_SWR[4] ),
.E(inst_ShiftRegister_n_0),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({left_right_SHT2,SHT2_STAGE_SHFTVARS2_n_7}),
.\Q_reg[0] ({\Data_array_SWR[5] [17:16],\Data_array_SWR[5] [9:2]}),
.\Q_reg[16] (shift_value_SHT2_EWR),
.\Q_reg[21] ({SHT2_STAGE_SHFTVARS1_n_24,SHT2_STAGE_SHFTVARS1_n_25,SHT2_STAGE_SHFTVARS1_n_26,SHT2_STAGE_SHFTVARS1_n_27,SHT2_STAGE_SHFTVARS1_n_28,SHT2_STAGE_SHFTVARS1_n_29,SHT2_STAGE_SHFTVARS1_n_30,SHT2_STAGE_SHFTVARS1_n_31,SHT2_STAGE_SHFTVARS1_n_32,SHT2_STAGE_SHFTVARS1_n_33,SHT2_STAGE_SHFTVARS1_n_34,SHT2_STAGE_SHFTVARS1_n_35}),
.\Q_reg[25] ({\Data_array_SWR[6] [25:24],\Data_array_SWR[6] [15:14],\Data_array_SWR[6] [9:8]}),
.\Q_reg[25]_0 (\Data_array_SWR[3] ),
.\Q_reg[2]_0 (shft_value_mux_o_EWR),
.\Q_reg[4]_0 (\Data_array_SWR[6] [1]),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
RegisterAdd__parameterized11 SHT2_STAGE_SHFTVARS2
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({sftr_odat_SHT2_SWR[15:14],sftr_odat_SHT2_SWR[11:8]}),
.E(inst_ShiftRegister_n_0),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({left_right_SHT2,SHT2_STAGE_SHFTVARS2_n_7}),
.\Q_reg[0]_0 ({\Data_array_SWR[5] [17:16],\Data_array_SWR[5] [11:10]}),
.\Q_reg[13] ({SHT2_STAGE_SHFTVARS2_n_8,SHT2_STAGE_SHFTVARS2_n_9,SHT2_STAGE_SHFTVARS2_n_10,SHT2_STAGE_SHFTVARS2_n_11}),
.\Q_reg[1]_0 ({left_right_SHT1,bit_shift_SHT1}),
.\Q_reg[4] (shift_value_SHT2_EWR[4]),
.\Q_reg[4]_0 ({\Data_array_SWR[6] [15:14],\Data_array_SWR[6] [9:8]}),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
IBUF add_subt_IBUF_inst
(.I(add_subt),
.O(add_subt_IBUF));
IBUF beg_OP_IBUF_inst
(.I(beg_OP),
.O(beg_OP_IBUF));
OBUF busy_OBUF_inst
(.I(busy_OBUF),
.O(busy));
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
OBUF \final_result_ieee_OBUF[0]_inst
(.I(final_result_ieee_OBUF[0]),
.O(final_result_ieee[0]));
OBUF \final_result_ieee_OBUF[10]_inst
(.I(final_result_ieee_OBUF[10]),
.O(final_result_ieee[10]));
OBUF \final_result_ieee_OBUF[11]_inst
(.I(final_result_ieee_OBUF[11]),
.O(final_result_ieee[11]));
OBUF \final_result_ieee_OBUF[12]_inst
(.I(final_result_ieee_OBUF[12]),
.O(final_result_ieee[12]));
OBUF \final_result_ieee_OBUF[13]_inst
(.I(final_result_ieee_OBUF[13]),
.O(final_result_ieee[13]));
OBUF \final_result_ieee_OBUF[14]_inst
(.I(final_result_ieee_OBUF[14]),
.O(final_result_ieee[14]));
OBUF \final_result_ieee_OBUF[15]_inst
(.I(final_result_ieee_OBUF[15]),
.O(final_result_ieee[15]));
OBUF \final_result_ieee_OBUF[16]_inst
(.I(final_result_ieee_OBUF[16]),
.O(final_result_ieee[16]));
OBUF \final_result_ieee_OBUF[17]_inst
(.I(final_result_ieee_OBUF[17]),
.O(final_result_ieee[17]));
OBUF \final_result_ieee_OBUF[18]_inst
(.I(final_result_ieee_OBUF[18]),
.O(final_result_ieee[18]));
OBUF \final_result_ieee_OBUF[19]_inst
(.I(final_result_ieee_OBUF[19]),
.O(final_result_ieee[19]));
OBUF \final_result_ieee_OBUF[1]_inst
(.I(final_result_ieee_OBUF[1]),
.O(final_result_ieee[1]));
OBUF \final_result_ieee_OBUF[20]_inst
(.I(final_result_ieee_OBUF[20]),
.O(final_result_ieee[20]));
OBUF \final_result_ieee_OBUF[21]_inst
(.I(final_result_ieee_OBUF[21]),
.O(final_result_ieee[21]));
OBUF \final_result_ieee_OBUF[22]_inst
(.I(final_result_ieee_OBUF[22]),
.O(final_result_ieee[22]));
OBUF \final_result_ieee_OBUF[23]_inst
(.I(final_result_ieee_OBUF[23]),
.O(final_result_ieee[23]));
OBUF \final_result_ieee_OBUF[24]_inst
(.I(final_result_ieee_OBUF[24]),
.O(final_result_ieee[24]));
OBUF \final_result_ieee_OBUF[25]_inst
(.I(final_result_ieee_OBUF[25]),
.O(final_result_ieee[25]));
OBUF \final_result_ieee_OBUF[26]_inst
(.I(final_result_ieee_OBUF[26]),
.O(final_result_ieee[26]));
OBUF \final_result_ieee_OBUF[27]_inst
(.I(final_result_ieee_OBUF[27]),
.O(final_result_ieee[27]));
OBUF \final_result_ieee_OBUF[28]_inst
(.I(final_result_ieee_OBUF[28]),
.O(final_result_ieee[28]));
OBUF \final_result_ieee_OBUF[29]_inst
(.I(final_result_ieee_OBUF[29]),
.O(final_result_ieee[29]));
OBUF \final_result_ieee_OBUF[2]_inst
(.I(final_result_ieee_OBUF[2]),
.O(final_result_ieee[2]));
OBUF \final_result_ieee_OBUF[30]_inst
(.I(final_result_ieee_OBUF[30]),
.O(final_result_ieee[30]));
OBUF \final_result_ieee_OBUF[31]_inst
(.I(final_result_ieee_OBUF[31]),
.O(final_result_ieee[31]));
OBUF \final_result_ieee_OBUF[3]_inst
(.I(final_result_ieee_OBUF[3]),
.O(final_result_ieee[3]));
OBUF \final_result_ieee_OBUF[4]_inst
(.I(final_result_ieee_OBUF[4]),
.O(final_result_ieee[4]));
OBUF \final_result_ieee_OBUF[5]_inst
(.I(final_result_ieee_OBUF[5]),
.O(final_result_ieee[5]));
OBUF \final_result_ieee_OBUF[6]_inst
(.I(final_result_ieee_OBUF[6]),
.O(final_result_ieee[6]));
OBUF \final_result_ieee_OBUF[7]_inst
(.I(final_result_ieee_OBUF[7]),
.O(final_result_ieee[7]));
OBUF \final_result_ieee_OBUF[8]_inst
(.I(final_result_ieee_OBUF[8]),
.O(final_result_ieee[8]));
OBUF \final_result_ieee_OBUF[9]_inst
(.I(final_result_ieee_OBUF[9]),
.O(final_result_ieee[9]));
FRMT_STAGE inst_FRMT_STAGE
(.D({formatted_number_W,inst_FRMT_STAGE_n_1,inst_FRMT_STAGE_n_2,inst_FRMT_STAGE_n_3,inst_FRMT_STAGE_n_4,inst_FRMT_STAGE_n_5,inst_FRMT_STAGE_n_6,inst_FRMT_STAGE_n_7,inst_FRMT_STAGE_n_8,inst_FRMT_STAGE_n_9,inst_FRMT_STAGE_n_10,inst_FRMT_STAGE_n_11,inst_FRMT_STAGE_n_12,inst_FRMT_STAGE_n_13,inst_FRMT_STAGE_n_14,inst_FRMT_STAGE_n_15}),
.DI(SFT2FRMT_STAGE_FLAGS_n_0),
.\Data_array_SWR[6] ({\Data_array_SWR[6] [24],\Data_array_SWR[6] [1]}),
.OVRFLW_FLAG_FRMT(OVRFLW_FLAG_FRMT),
.Q({ADD_OVRFLW_NRM2,SIGN_FLAG_SHT1SHT2}),
.\Q_reg[1] ({sftr_odat_SHT2_SWR[17:16],sftr_odat_SHT2_SWR[13:12],sftr_odat_SHT2_SWR[9:8]}),
.\Q_reg[1]_0 (left_right_SHT2),
.\Q_reg[2] ({SFT2FRMT_STAGE_VARS_n_1,SFT2FRMT_STAGE_VARS_n_2,SFT2FRMT_STAGE_VARS_n_3,SFT2FRMT_STAGE_VARS_n_4}),
.\Q_reg[6] ({SFT2FRMT_STAGE_VARS_n_5,SFT2FRMT_STAGE_VARS_n_6,SFT2FRMT_STAGE_VARS_n_7,SFT2FRMT_STAGE_VARS_n_8,SFT2FRMT_STAGE_VARS_n_9,SFT2FRMT_STAGE_VARS_n_10,SFT2FRMT_STAGE_VARS_n_11}),
.\Q_reg[6]_0 ({SFT2FRMT_STAGE_VARS_n_12,SFT2FRMT_STAGE_VARS_n_13,SFT2FRMT_STAGE_VARS_n_14,SFT2FRMT_STAGE_VARS_n_15}),
.S(SFT2FRMT_STAGE_VARS_n_0),
.UNDRFLW_FLAG_FRMT(UNDRFLW_FLAG_FRMT));
FSM_INPUT_ENABLE inst_FSM_INPUT_ENABLE
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D(FSM_enable_input_internal),
.E(load00_out),
.\Q_reg[31] (enable_Pipeline_input),
.beg_OP_IBUF(beg_OP_IBUF));
ShiftRegister inst_ShiftRegister
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D(FSM_enable_input_internal),
.E(inst_ShiftRegister_n_0),
.\FSM_sequential_state_reg_reg[2] (load00_out),
.Q({inst_ShiftRegister_n_1,inst_ShiftRegister_n_2,busy_OBUF,inst_ShiftRegister_n_4,Shift_reg_FLAGS_7,inst_ShiftRegister_n_6}),
.\Q_reg[1]_0 (left_right_SHT1),
.\Q_reg[2]_0 (load0),
.\Q_reg[2]_1 (ADD_OVRFLW_NRM));
OBUF overflow_flag_OBUF_inst
(.I(overflow_flag_OBUF),
.O(overflow_flag));
OBUF ready_OBUF_inst
(.I(ready_OBUF),
.O(ready));
sgn_result result_sign_bit
(.CO(gtXY),
.D(SIGN_FLAG_INIT),
.Q(intDY_EWSW),
.\Q_reg[30] (eqXY),
.\Q_reg[31] (intDX_EWSW),
.intAS(intAS));
IBUF rst_IBUF_inst
(.I(rst),
.O(rst_IBUF));
OBUF underflow_flag_OBUF_inst
(.I(underflow_flag_OBUF),
.O(underflow_flag));
OBUF zero_flag_OBUF_inst
(.I(zero_flag_OBUF),
.O(zero_flag));
endmodule
module FRMT_STAGE
(D,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
\Q_reg[6] ,
DI,
\Q_reg[2] ,
Q,
\Q_reg[6]_0 ,
S,
\Q_reg[1] ,
\Data_array_SWR[6] ,
\Q_reg[1]_0 );
output [15:0]D;
output UNDRFLW_FLAG_FRMT;
output OVRFLW_FLAG_FRMT;
input [6:0]\Q_reg[6] ;
input [0:0]DI;
input [3:0]\Q_reg[2] ;
input [1:0]Q;
input [3:0]\Q_reg[6]_0 ;
input [0:0]S;
input [5:0]\Q_reg[1] ;
input [1:0]\Data_array_SWR[6] ;
input [0:0]\Q_reg[1]_0 ;
wire [15:0]D;
wire [0:0]DI;
wire [1:0]\Data_array_SWR[6] ;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [5:0]\Q_reg[1] ;
wire [0:0]\Q_reg[1]_0 ;
wire [3:0]\Q_reg[2] ;
wire [6:0]\Q_reg[6] ;
wire [3:0]\Q_reg[6]_0 ;
wire [0:0]S;
wire UNDRFLW_FLAG_FRMT;
Multiplexer_AC__parameterized1 Exp_Mux
(.D(D),
.DI(DI),
.\Data_array_SWR[6] (\Data_array_SWR[6] ),
.Q(Q),
.\Q_reg[1] (UNDRFLW_FLAG_FRMT),
.\Q_reg[1]_0 (\Q_reg[1] ),
.\Q_reg[1]_1 (\Q_reg[1]_0 ),
.\Q_reg[2] (OVRFLW_FLAG_FRMT),
.\Q_reg[2]_0 (\Q_reg[2] ),
.\Q_reg[6] (\Q_reg[6] ),
.\Q_reg[6]_0 (\Q_reg[6]_0 ),
.S(S));
endmodule
module FSM_INPUT_ENABLE
(E,
\Q_reg[31] ,
D,
beg_OP_IBUF,
CLK,
AR);
output [0:0]E;
output [0:0]\Q_reg[31] ;
output [0:0]D;
input beg_OP_IBUF;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [0:0]E;
wire \FSM_sequential_state_reg[0]_i_1_n_0 ;
wire \FSM_sequential_state_reg[1]_i_1_n_0 ;
wire \FSM_sequential_state_reg[2]_i_1_n_0 ;
wire [0:0]\Q_reg[31] ;
wire beg_OP_IBUF;
(* RTL_KEEP = "yes" *) wire [2:0]state_reg;
LUT4 #(
.INIT(16'h1154))
\FSM_sequential_state_reg[0]_i_1
(.I0(state_reg[0]),
.I1(state_reg[2]),
.I2(beg_OP_IBUF),
.I3(state_reg[1]),
.O(\FSM_sequential_state_reg[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'h06))
\FSM_sequential_state_reg[1]_i_1
(.I0(state_reg[1]),
.I1(state_reg[0]),
.I2(state_reg[2]),
.O(\FSM_sequential_state_reg[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'h24))
\FSM_sequential_state_reg[2]_i_1
(.I0(state_reg[0]),
.I1(state_reg[2]),
.I2(state_reg[1]),
.O(\FSM_sequential_state_reg[2]_i_1_n_0 ));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(AR),
.D(\FSM_sequential_state_reg[0]_i_1_n_0 ),
.Q(state_reg[0]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(AR),
.D(\FSM_sequential_state_reg[1]_i_1_n_0 ),
.Q(state_reg[1]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[2]
(.C(CLK),
.CE(1'b1),
.CLR(AR),
.D(\FSM_sequential_state_reg[2]_i_1_n_0 ),
.Q(state_reg[2]));
LUT4 #(
.INIT(16'h0700))
\Q[31]_i_1
(.I0(state_reg[0]),
.I1(state_reg[1]),
.I2(state_reg[2]),
.I3(beg_OP_IBUF),
.O(\Q_reg[31] ));
LUT4 #(
.INIT(16'h33FE))
\Q[6]_i_1__0
(.I0(beg_OP_IBUF),
.I1(state_reg[2]),
.I2(state_reg[0]),
.I3(state_reg[1]),
.O(E));
LUT3 #(
.INIT(8'h15))
\inst_FSM_INPUT_ENABLE/
(.I0(state_reg[2]),
.I1(state_reg[1]),
.I2(state_reg[0]),
.O(D));
endmodule
module MultiplexTxT
(\Q_reg[30] ,
\Q_reg[27] ,
Q,
\Q_reg[30]_0 ,
CO);
output [30:0]\Q_reg[30] ;
output [27:0]\Q_reg[27] ;
input [30:0]Q;
input [30:0]\Q_reg[30]_0 ;
input [0:0]CO;
wire [0:0]CO;
wire [30:0]Q;
wire [27:0]\Q_reg[27] ;
wire [30:0]\Q_reg[30] ;
wire [30:0]\Q_reg[30]_0 ;
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\Q[0]_i_1
(.I0(Q[0]),
.I1(\Q_reg[30]_0 [0]),
.I2(CO),
.O(\Q_reg[30] [0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\Q[0]_i_1__0
(.I0(\Q_reg[30]_0 [0]),
.I1(Q[0]),
.I2(CO),
.O(\Q_reg[27] [0]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1
(.I0(Q[10]),
.I1(\Q_reg[30]_0 [10]),
.I2(CO),
.O(\Q_reg[30] [10]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1__0
(.I0(\Q_reg[30]_0 [10]),
.I1(Q[10]),
.I2(CO),
.O(\Q_reg[27] [10]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1
(.I0(Q[11]),
.I1(\Q_reg[30]_0 [11]),
.I2(CO),
.O(\Q_reg[30] [11]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1__0
(.I0(\Q_reg[30]_0 [11]),
.I1(Q[11]),
.I2(CO),
.O(\Q_reg[27] [11]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1
(.I0(Q[12]),
.I1(\Q_reg[30]_0 [12]),
.I2(CO),
.O(\Q_reg[30] [12]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1__0
(.I0(\Q_reg[30]_0 [12]),
.I1(Q[12]),
.I2(CO),
.O(\Q_reg[27] [12]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1
(.I0(Q[13]),
.I1(\Q_reg[30]_0 [13]),
.I2(CO),
.O(\Q_reg[30] [13]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1__0
(.I0(\Q_reg[30]_0 [13]),
.I1(Q[13]),
.I2(CO),
.O(\Q_reg[27] [13]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1
(.I0(Q[14]),
.I1(\Q_reg[30]_0 [14]),
.I2(CO),
.O(\Q_reg[30] [14]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1__0
(.I0(\Q_reg[30]_0 [14]),
.I1(Q[14]),
.I2(CO),
.O(\Q_reg[27] [14]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1
(.I0(Q[15]),
.I1(\Q_reg[30]_0 [15]),
.I2(CO),
.O(\Q_reg[30] [15]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1__0
(.I0(\Q_reg[30]_0 [15]),
.I1(Q[15]),
.I2(CO),
.O(\Q_reg[27] [15]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1
(.I0(Q[16]),
.I1(\Q_reg[30]_0 [16]),
.I2(CO),
.O(\Q_reg[30] [16]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1__0
(.I0(\Q_reg[30]_0 [16]),
.I1(Q[16]),
.I2(CO),
.O(\Q_reg[27] [16]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1
(.I0(Q[17]),
.I1(\Q_reg[30]_0 [17]),
.I2(CO),
.O(\Q_reg[30] [17]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1__0
(.I0(\Q_reg[30]_0 [17]),
.I1(Q[17]),
.I2(CO),
.O(\Q_reg[27] [17]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1
(.I0(Q[18]),
.I1(\Q_reg[30]_0 [18]),
.I2(CO),
.O(\Q_reg[30] [18]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1__0
(.I0(\Q_reg[30]_0 [18]),
.I1(Q[18]),
.I2(CO),
.O(\Q_reg[27] [18]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1
(.I0(Q[19]),
.I1(\Q_reg[30]_0 [19]),
.I2(CO),
.O(\Q_reg[30] [19]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1__0
(.I0(\Q_reg[30]_0 [19]),
.I1(Q[19]),
.I2(CO),
.O(\Q_reg[27] [19]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1
(.I0(Q[1]),
.I1(\Q_reg[30]_0 [1]),
.I2(CO),
.O(\Q_reg[30] [1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1__0
(.I0(\Q_reg[30]_0 [1]),
.I1(Q[1]),
.I2(CO),
.O(\Q_reg[27] [1]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1
(.I0(Q[20]),
.I1(\Q_reg[30]_0 [20]),
.I2(CO),
.O(\Q_reg[30] [20]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1__0
(.I0(\Q_reg[30]_0 [20]),
.I1(Q[20]),
.I2(CO),
.O(\Q_reg[27] [20]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1
(.I0(Q[21]),
.I1(\Q_reg[30]_0 [21]),
.I2(CO),
.O(\Q_reg[30] [21]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1__0
(.I0(\Q_reg[30]_0 [21]),
.I1(Q[21]),
.I2(CO),
.O(\Q_reg[27] [21]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1
(.I0(Q[22]),
.I1(\Q_reg[30]_0 [22]),
.I2(CO),
.O(\Q_reg[30] [22]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1__0
(.I0(\Q_reg[30]_0 [22]),
.I1(Q[22]),
.I2(CO),
.O(\Q_reg[27] [22]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1
(.I0(Q[23]),
.I1(\Q_reg[30]_0 [23]),
.I2(CO),
.O(\Q_reg[30] [23]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1__0
(.I0(\Q_reg[30]_0 [23]),
.I1(Q[23]),
.I2(CO),
.O(\Q_reg[27] [23]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1
(.I0(Q[24]),
.I1(\Q_reg[30]_0 [24]),
.I2(CO),
.O(\Q_reg[30] [24]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1__0
(.I0(\Q_reg[30]_0 [24]),
.I1(Q[24]),
.I2(CO),
.O(\Q_reg[27] [24]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1
(.I0(Q[25]),
.I1(\Q_reg[30]_0 [25]),
.I2(CO),
.O(\Q_reg[30] [25]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1__0
(.I0(\Q_reg[30]_0 [25]),
.I1(Q[25]),
.I2(CO),
.O(\Q_reg[27] [25]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAC))
\Q[26]_i_1
(.I0(Q[26]),
.I1(\Q_reg[30]_0 [26]),
.I2(CO),
.O(\Q_reg[30] [26]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAC))
\Q[26]_i_1__0
(.I0(\Q_reg[30]_0 [26]),
.I1(Q[26]),
.I2(CO),
.O(\Q_reg[27] [26]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAC))
\Q[27]_i_1
(.I0(Q[27]),
.I1(\Q_reg[30]_0 [27]),
.I2(CO),
.O(\Q_reg[30] [27]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAC))
\Q[27]_i_1__0
(.I0(\Q_reg[30]_0 [27]),
.I1(Q[27]),
.I2(CO),
.O(\Q_reg[27] [27]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\Q[28]_i_1
(.I0(Q[28]),
.I1(\Q_reg[30]_0 [28]),
.I2(CO),
.O(\Q_reg[30] [28]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\Q[29]_i_1
(.I0(Q[29]),
.I1(\Q_reg[30]_0 [29]),
.I2(CO),
.O(\Q_reg[30] [29]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1
(.I0(Q[2]),
.I1(\Q_reg[30]_0 [2]),
.I2(CO),
.O(\Q_reg[30] [2]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1__0
(.I0(\Q_reg[30]_0 [2]),
.I1(Q[2]),
.I2(CO),
.O(\Q_reg[27] [2]));
LUT3 #(
.INIT(8'hAC))
\Q[30]_i_1
(.I0(Q[30]),
.I1(\Q_reg[30]_0 [30]),
.I2(CO),
.O(\Q_reg[30] [30]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1
(.I0(Q[3]),
.I1(\Q_reg[30]_0 [3]),
.I2(CO),
.O(\Q_reg[30] [3]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1__0
(.I0(\Q_reg[30]_0 [3]),
.I1(Q[3]),
.I2(CO),
.O(\Q_reg[27] [3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1
(.I0(Q[4]),
.I1(\Q_reg[30]_0 [4]),
.I2(CO),
.O(\Q_reg[30] [4]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1__0
(.I0(\Q_reg[30]_0 [4]),
.I1(Q[4]),
.I2(CO),
.O(\Q_reg[27] [4]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1
(.I0(Q[5]),
.I1(\Q_reg[30]_0 [5]),
.I2(CO),
.O(\Q_reg[30] [5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1__0
(.I0(\Q_reg[30]_0 [5]),
.I1(Q[5]),
.I2(CO),
.O(\Q_reg[27] [5]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1
(.I0(Q[6]),
.I1(\Q_reg[30]_0 [6]),
.I2(CO),
.O(\Q_reg[30] [6]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1__0
(.I0(\Q_reg[30]_0 [6]),
.I1(Q[6]),
.I2(CO),
.O(\Q_reg[27] [6]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1
(.I0(Q[7]),
.I1(\Q_reg[30]_0 [7]),
.I2(CO),
.O(\Q_reg[30] [7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1__0
(.I0(\Q_reg[30]_0 [7]),
.I1(Q[7]),
.I2(CO),
.O(\Q_reg[27] [7]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1
(.I0(Q[8]),
.I1(\Q_reg[30]_0 [8]),
.I2(CO),
.O(\Q_reg[30] [8]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1__0
(.I0(\Q_reg[30]_0 [8]),
.I1(Q[8]),
.I2(CO),
.O(\Q_reg[27] [8]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1
(.I0(Q[9]),
.I1(\Q_reg[30]_0 [9]),
.I2(CO),
.O(\Q_reg[30] [9]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1__0
(.I0(\Q_reg[30]_0 [9]),
.I1(Q[9]),
.I2(CO),
.O(\Q_reg[27] [9]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *)
module Multiplexer_AC__parameterized1
(D,
\Q_reg[1] ,
\Q_reg[2] ,
\Q_reg[6] ,
DI,
\Q_reg[2]_0 ,
Q,
\Q_reg[6]_0 ,
S,
\Q_reg[1]_0 ,
\Data_array_SWR[6] ,
\Q_reg[1]_1 );
output [15:0]D;
output \Q_reg[1] ;
output \Q_reg[2] ;
input [6:0]\Q_reg[6] ;
input [0:0]DI;
input [3:0]\Q_reg[2]_0 ;
input [1:0]Q;
input [3:0]\Q_reg[6]_0 ;
input [0:0]S;
input [5:0]\Q_reg[1]_0 ;
input [1:0]\Data_array_SWR[6] ;
input [0:0]\Q_reg[1]_1 ;
wire [15:0]D;
wire [0:0]DI;
wire [1:0]\Data_array_SWR[6] ;
wire [1:0]Q;
wire \Q[1]_i_2__0_n_0 ;
wire \Q[2]_i_2__0_n_0 ;
wire \Q_reg[1] ;
wire [5:0]\Q_reg[1]_0 ;
wire [0:0]\Q_reg[1]_1 ;
wire \Q_reg[2] ;
wire [3:0]\Q_reg[2]_0 ;
wire [6:0]\Q_reg[6] ;
wire [3:0]\Q_reg[6]_0 ;
wire [0:0]S;
wire S0_carry__0_n_0;
wire S0_carry__0_n_1;
wire S0_carry__0_n_2;
wire S0_carry__0_n_3;
wire S0_carry_n_0;
wire S0_carry_n_1;
wire S0_carry_n_2;
wire S0_carry_n_3;
wire [8:0]exp_rslt_NRM2_EW1;
wire [3:0]NLW_S0_carry__1_CO_UNCONNECTED;
wire [3:1]NLW_S0_carry__1_O_UNCONNECTED;
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'h02))
\Q[10]_i_1__0
(.I0(\Q_reg[1]_0 [2]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'h02))
\Q[11]_i_1__1
(.I0(\Q_reg[1]_0 [3]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'h02))
\Q[14]_i_1__0
(.I0(\Q_reg[1]_0 [4]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'h02))
\Q[15]_i_1__0
(.I0(\Q_reg[1]_0 [5]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[5]));
LUT5 #(
.INIT(32'h00000001))
\Q[1]_i_1__2
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(exp_rslt_NRM2_EW1[6]),
.I2(exp_rslt_NRM2_EW1[8]),
.I3(exp_rslt_NRM2_EW1[7]),
.I4(\Q[1]_i_2__0_n_0 ),
.O(\Q_reg[1] ));
LUT5 #(
.INIT(32'hFFFFFFFE))
\Q[1]_i_2__0
(.I0(exp_rslt_NRM2_EW1[2]),
.I1(exp_rslt_NRM2_EW1[0]),
.I2(exp_rslt_NRM2_EW1[1]),
.I3(exp_rslt_NRM2_EW1[4]),
.I4(exp_rslt_NRM2_EW1[3]),
.O(\Q[1]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'h000000B8))
\Q[22]_i_1__2
(.I0(\Data_array_SWR[6] [0]),
.I1(\Q_reg[1]_1 ),
.I2(\Data_array_SWR[6] [1]),
.I3(\Q_reg[1] ),
.I4(\Q_reg[2] ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hFE))
\Q[23]_i_1__0
(.I0(exp_rslt_NRM2_EW1[0]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hFE))
\Q[24]_i_1__0
(.I0(exp_rslt_NRM2_EW1[1]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hFE))
\Q[25]_i_1__0
(.I0(exp_rslt_NRM2_EW1[2]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[9]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hFE))
\Q[26]_i_1
(.I0(exp_rslt_NRM2_EW1[3]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hFE))
\Q[27]_i_1
(.I0(exp_rslt_NRM2_EW1[4]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hFE))
\Q[28]_i_1
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hFE))
\Q[29]_i_1
(.I0(exp_rslt_NRM2_EW1[6]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[13]));
LUT6 #(
.INIT(64'hEAAAAAAAAAAAAAAA))
\Q[2]_i_1__1
(.I0(exp_rslt_NRM2_EW1[8]),
.I1(\Q[2]_i_2__0_n_0 ),
.I2(exp_rslt_NRM2_EW1[1]),
.I3(exp_rslt_NRM2_EW1[0]),
.I4(exp_rslt_NRM2_EW1[3]),
.I5(exp_rslt_NRM2_EW1[2]),
.O(\Q_reg[2] ));
LUT4 #(
.INIT(16'h8000))
\Q[2]_i_2__0
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(exp_rslt_NRM2_EW1[4]),
.I2(exp_rslt_NRM2_EW1[6]),
.I3(exp_rslt_NRM2_EW1[7]),
.O(\Q[2]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hFE))
\Q[30]_i_1
(.I0(exp_rslt_NRM2_EW1[7]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[14]));
LUT3 #(
.INIT(8'h0E))
\Q[31]_i_1__0
(.I0(\Q_reg[1] ),
.I1(Q[0]),
.I2(\Q_reg[2] ),
.O(D[15]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'h02))
\Q[6]_i_1__1
(.I0(\Q_reg[1]_0 [0]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'h02))
\Q[7]_i_1__0
(.I0(\Q_reg[1]_0 [1]),
.I1(\Q_reg[1] ),
.I2(\Q_reg[2] ),
.O(D[1]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 S0_carry
(.CI(1'b0),
.CO({S0_carry_n_0,S0_carry_n_1,S0_carry_n_2,S0_carry_n_3}),
.CYINIT(\Q_reg[6] [0]),
.DI({\Q_reg[6] [3:1],DI}),
.O(exp_rslt_NRM2_EW1[3:0]),
.S(\Q_reg[2]_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 S0_carry__0
(.CI(S0_carry_n_0),
.CO({S0_carry__0_n_0,S0_carry__0_n_1,S0_carry__0_n_2,S0_carry__0_n_3}),
.CYINIT(1'b0),
.DI({\Q_reg[6] [6:5],Q[1],\Q_reg[6] [4]}),
.O(exp_rslt_NRM2_EW1[7:4]),
.S(\Q_reg[6]_0 ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 S0_carry__1
(.CI(S0_carry__0_n_0),
.CO(NLW_S0_carry__1_CO_UNCONNECTED[3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW_S0_carry__1_O_UNCONNECTED[3:1],exp_rslt_NRM2_EW1[8]}),
.S({1'b0,1'b0,1'b0,S}));
endmodule
module RegisterAdd
(Q,
\Q_reg[0]_0 ,
D,
CLK,
AR);
output [31:0]Q;
input [0:0]\Q_reg[0]_0 ;
input [31:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [31:0]Q;
wire [0:0]\Q_reg[0]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_0
(DI,
Q,
S,
\Q_reg[0]_0 ,
\Q_reg[2]_0 ,
\Q_reg[2]_1 ,
\Q_reg[2]_2 ,
\Q_reg[0]_1 ,
\Q_reg[2]_3 ,
\Q_reg[2]_4 ,
\Q_reg[2]_5 ,
\Q_reg[0]_2 ,
D,
\Q_reg[31]_0 ,
intAS,
E,
\Data_X[31] ,
CLK,
AR);
output [3:0]DI;
output [31:0]Q;
output [3:0]S;
output [3:0]\Q_reg[0]_0 ;
output [3:0]\Q_reg[2]_0 ;
output [3:0]\Q_reg[2]_1 ;
output [3:0]\Q_reg[2]_2 ;
output [3:0]\Q_reg[0]_1 ;
output [3:0]\Q_reg[2]_3 ;
output [3:0]\Q_reg[2]_4 ;
output [2:0]\Q_reg[2]_5 ;
output [1:0]\Q_reg[0]_2 ;
output [0:0]D;
input [31:0]\Q_reg[31]_0 ;
input intAS;
input [0:0]E;
input [31:0]\Data_X[31] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [3:0]DI;
wire [31:0]\Data_X[31] ;
wire [0:0]E;
wire [31:0]Q;
wire [3:0]\Q_reg[0]_0 ;
wire [3:0]\Q_reg[0]_1 ;
wire [1:0]\Q_reg[0]_2 ;
wire [3:0]\Q_reg[2]_0 ;
wire [3:0]\Q_reg[2]_1 ;
wire [3:0]\Q_reg[2]_2 ;
wire [3:0]\Q_reg[2]_3 ;
wire [3:0]\Q_reg[2]_4 ;
wire [2:0]\Q_reg[2]_5 ;
wire [31:0]\Q_reg[31]_0 ;
wire [3:0]S;
wire intAS;
LUT3 #(
.INIT(8'h96))
\Q[1]_i_1__1
(.I0(Q[31]),
.I1(\Q_reg[31]_0 [31]),
.I2(intAS),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [9]),
.Q(Q[9]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_1
(.I0(Q[21]),
.I1(\Q_reg[31]_0 [21]),
.I2(\Q_reg[31]_0 [23]),
.I3(Q[23]),
.I4(\Q_reg[31]_0 [22]),
.I5(Q[22]),
.O(\Q_reg[0]_1 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_2
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(\Q_reg[31]_0 [20]),
.I3(Q[20]),
.I4(\Q_reg[31]_0 [19]),
.I5(Q[19]),
.O(\Q_reg[0]_1 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_3
(.I0(Q[15]),
.I1(\Q_reg[31]_0 [15]),
.I2(\Q_reg[31]_0 [17]),
.I3(Q[17]),
.I4(\Q_reg[31]_0 [16]),
.I5(Q[16]),
.O(\Q_reg[0]_1 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_4
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(\Q_reg[31]_0 [14]),
.I3(Q[14]),
.I4(\Q_reg[31]_0 [13]),
.I5(Q[13]),
.O(\Q_reg[0]_1 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_2
(.I0(Q[27]),
.I1(\Q_reg[31]_0 [27]),
.I2(\Q_reg[31]_0 [29]),
.I3(Q[29]),
.I4(\Q_reg[31]_0 [28]),
.I5(Q[28]),
.O(\Q_reg[0]_2 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_3
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(\Q_reg[31]_0 [26]),
.I3(Q[26]),
.I4(\Q_reg[31]_0 [25]),
.I5(Q[25]),
.O(\Q_reg[0]_2 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_1
(.I0(Q[9]),
.I1(\Q_reg[31]_0 [9]),
.I2(\Q_reg[31]_0 [11]),
.I3(Q[11]),
.I4(\Q_reg[31]_0 [10]),
.I5(Q[10]),
.O(\Q_reg[0]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_2
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(\Q_reg[31]_0 [8]),
.I3(Q[8]),
.I4(\Q_reg[31]_0 [7]),
.I5(Q[7]),
.O(\Q_reg[0]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_3
(.I0(Q[3]),
.I1(\Q_reg[31]_0 [3]),
.I2(\Q_reg[31]_0 [5]),
.I3(Q[5]),
.I4(\Q_reg[31]_0 [4]),
.I5(Q[4]),
.O(\Q_reg[0]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_4
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(\Q_reg[31]_0 [2]),
.I3(Q[2]),
.I4(\Q_reg[31]_0 [1]),
.I5(Q[1]),
.O(\Q_reg[0]_0 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_1
(.I0(Q[14]),
.I1(\Q_reg[31]_0 [14]),
.I2(\Q_reg[31]_0 [15]),
.I3(Q[15]),
.O(\Q_reg[2]_0 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_2
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(\Q_reg[31]_0 [13]),
.I3(Q[13]),
.O(\Q_reg[2]_0 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_3
(.I0(Q[10]),
.I1(\Q_reg[31]_0 [10]),
.I2(\Q_reg[31]_0 [11]),
.I3(Q[11]),
.O(\Q_reg[2]_0 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_4
(.I0(Q[8]),
.I1(\Q_reg[31]_0 [8]),
.I2(\Q_reg[31]_0 [9]),
.I3(Q[9]),
.O(\Q_reg[2]_0 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_5
(.I0(Q[14]),
.I1(\Q_reg[31]_0 [14]),
.I2(Q[15]),
.I3(\Q_reg[31]_0 [15]),
.O(\Q_reg[2]_1 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_6
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(Q[13]),
.I3(\Q_reg[31]_0 [13]),
.O(\Q_reg[2]_1 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_7
(.I0(Q[10]),
.I1(\Q_reg[31]_0 [10]),
.I2(Q[11]),
.I3(\Q_reg[31]_0 [11]),
.O(\Q_reg[2]_1 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_8
(.I0(Q[8]),
.I1(\Q_reg[31]_0 [8]),
.I2(Q[9]),
.I3(\Q_reg[31]_0 [9]),
.O(\Q_reg[2]_1 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_1
(.I0(Q[22]),
.I1(\Q_reg[31]_0 [22]),
.I2(\Q_reg[31]_0 [23]),
.I3(Q[23]),
.O(\Q_reg[2]_2 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_2
(.I0(Q[20]),
.I1(\Q_reg[31]_0 [20]),
.I2(\Q_reg[31]_0 [21]),
.I3(Q[21]),
.O(\Q_reg[2]_2 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_3
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(\Q_reg[31]_0 [19]),
.I3(Q[19]),
.O(\Q_reg[2]_2 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_4
(.I0(Q[16]),
.I1(\Q_reg[31]_0 [16]),
.I2(\Q_reg[31]_0 [17]),
.I3(Q[17]),
.O(\Q_reg[2]_2 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_5
(.I0(Q[22]),
.I1(\Q_reg[31]_0 [22]),
.I2(Q[23]),
.I3(\Q_reg[31]_0 [23]),
.O(\Q_reg[2]_3 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_6
(.I0(Q[20]),
.I1(\Q_reg[31]_0 [20]),
.I2(Q[21]),
.I3(\Q_reg[31]_0 [21]),
.O(\Q_reg[2]_3 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_7
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(Q[19]),
.I3(\Q_reg[31]_0 [19]),
.O(\Q_reg[2]_3 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_8
(.I0(Q[16]),
.I1(\Q_reg[31]_0 [16]),
.I2(Q[17]),
.I3(\Q_reg[31]_0 [17]),
.O(\Q_reg[2]_3 [0]));
LUT2 #(
.INIT(4'h2))
gtXY_o_carry__2_i_1
(.I0(Q[30]),
.I1(\Q_reg[31]_0 [30]),
.O(\Q_reg[2]_4 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_2
(.I0(Q[28]),
.I1(\Q_reg[31]_0 [28]),
.I2(\Q_reg[31]_0 [29]),
.I3(Q[29]),
.O(\Q_reg[2]_4 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_3
(.I0(Q[26]),
.I1(\Q_reg[31]_0 [26]),
.I2(\Q_reg[31]_0 [27]),
.I3(Q[27]),
.O(\Q_reg[2]_4 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_4
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(\Q_reg[31]_0 [25]),
.I3(Q[25]),
.O(\Q_reg[2]_4 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_6
(.I0(Q[28]),
.I1(\Q_reg[31]_0 [28]),
.I2(Q[29]),
.I3(\Q_reg[31]_0 [29]),
.O(\Q_reg[2]_5 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_7
(.I0(Q[26]),
.I1(\Q_reg[31]_0 [26]),
.I2(Q[27]),
.I3(\Q_reg[31]_0 [27]),
.O(\Q_reg[2]_5 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_8
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(Q[25]),
.I3(\Q_reg[31]_0 [25]),
.O(\Q_reg[2]_5 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_1
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(\Q_reg[31]_0 [7]),
.I3(Q[7]),
.O(DI[3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_2
(.I0(Q[4]),
.I1(\Q_reg[31]_0 [4]),
.I2(\Q_reg[31]_0 [5]),
.I3(Q[5]),
.O(DI[2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_3
(.I0(Q[2]),
.I1(\Q_reg[31]_0 [2]),
.I2(\Q_reg[31]_0 [3]),
.I3(Q[3]),
.O(DI[1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_4
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(\Q_reg[31]_0 [1]),
.I3(Q[1]),
.O(DI[0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_5
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(Q[7]),
.I3(\Q_reg[31]_0 [7]),
.O(S[3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_6
(.I0(Q[4]),
.I1(\Q_reg[31]_0 [4]),
.I2(Q[5]),
.I3(\Q_reg[31]_0 [5]),
.O(S[2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_7
(.I0(Q[2]),
.I1(\Q_reg[31]_0 [2]),
.I2(Q[3]),
.I3(\Q_reg[31]_0 [3]),
.O(S[1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_8
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(Q[1]),
.I3(\Q_reg[31]_0 [1]),
.O(S[0]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_1
(S,
Q,
\Q_reg[2]_0 ,
\Q_reg[30]_0 ,
E,
D,
CLK,
AR);
output [0:0]S;
output [31:0]Q;
output [0:0]\Q_reg[2]_0 ;
input [0:0]\Q_reg[30]_0 ;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
wire [0:0]\Q_reg[2]_0 ;
wire [0:0]\Q_reg[30]_0 ;
wire [0:0]S;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
LUT2 #(
.INIT(4'h9))
eqXY_o_carry__1_i_1
(.I0(Q[30]),
.I1(\Q_reg[30]_0 ),
.O(S));
LUT2 #(
.INIT(4'h9))
gtXY_o_carry__2_i_5
(.I0(Q[30]),
.I1(\Q_reg[30]_0 ),
.O(\Q_reg[2]_0 ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized0
(intAS,
E,
add_subt_IBUF,
CLK,
AR);
output intAS;
input [0:0]E;
input add_subt_IBUF;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire add_subt_IBUF;
wire intAS;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(add_subt_IBUF),
.Q(intAS));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized1
(D,
Q,
\Q_reg[25]_0 ,
\Q_reg[6]_0 ,
\Q_reg[30]_0 ,
CLK,
AR);
output [1:0]D;
output [30:0]Q;
input [2:0]\Q_reg[25]_0 ;
input [0:0]\Q_reg[6]_0 ;
input [30:0]\Q_reg[30]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [1:0]D;
wire [30:0]Q;
wire [2:0]\Q_reg[25]_0 ;
wire [30:0]\Q_reg[30]_0 ;
wire [0:0]\Q_reg[6]_0 ;
LUT2 #(
.INIT(4'h6))
\Q[0]_i_1__2
(.I0(Q[23]),
.I1(\Q_reg[25]_0 [0]),
.O(D[0]));
LUT6 #(
.INIT(64'h4F04B0FBB0FB4F04))
\Q[2]_i_1__5
(.I0(Q[23]),
.I1(\Q_reg[25]_0 [0]),
.I2(Q[24]),
.I3(\Q_reg[25]_0 [1]),
.I4(\Q_reg[25]_0 [2]),
.I5(Q[25]),
.O(D[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized10
(D,
\Q_reg[25] ,
\Q_reg[16] ,
\Q_reg[21] ,
Q,
\Q_reg[4]_0 ,
\Q_reg[0] ,
\Q_reg[25]_0 ,
\Data_array_SWR[4] ,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
E,
\Q_reg[2]_0 ,
CLK,
AR);
output [14:0]D;
output [5:0]\Q_reg[25] ;
output [2:0]\Q_reg[16] ;
output [11:0]\Q_reg[21] ;
input [1:0]Q;
input [0:0]\Q_reg[4]_0 ;
input [9:0]\Q_reg[0] ;
input [7:0]\Q_reg[25]_0 ;
input [1:0]\Data_array_SWR[4] ;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [0:0]E;
input [2:0]\Q_reg[2]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [14:0]D;
wire [1:0]\Data_array_SWR[4] ;
wire [21:18]\Data_array_SWR[5] ;
wire [23:2]\Data_array_SWR[6] ;
wire [0:0]E;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [9:0]\Q_reg[0] ;
wire [2:0]\Q_reg[16] ;
wire [11:0]\Q_reg[21] ;
wire [5:0]\Q_reg[25] ;
wire [7:0]\Q_reg[25]_0 ;
wire [2:0]\Q_reg[2]_0 ;
wire [0:0]\Q_reg[4]_0 ;
wire UNDRFLW_FLAG_FRMT;
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[0]_i_1__3
(.I0(\Data_array_SWR[6] [23]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [2]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[21] [0]));
LUT6 #(
.INIT(64'hCDC8DDDDCDC88888))
\Q[14]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [1]),
.I5(\Data_array_SWR[4] [0]),
.O(\Q_reg[25] [2]));
LUT6 #(
.INIT(64'hCDC8DDDDCDC88888))
\Q[15]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [1]),
.I5(\Data_array_SWR[4] [1]),
.O(\Q_reg[25] [3]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[16]_i_1__0
(.I0(\Q_reg[25] [1]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[16] [2]),
.I4(\Q_reg[0] [8]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[16]_i_1__2
(.I0(\Data_array_SWR[6] [7]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [18]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[21] [6]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[16]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [7]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [7]),
.O(\Q_reg[25] [1]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[17]_i_1__0
(.I0(\Q_reg[25] [0]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[16] [2]),
.I4(\Q_reg[0] [9]),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[17]_i_1__2
(.I0(\Data_array_SWR[6] [6]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [19]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[21] [7]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[17]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [6]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [6]),
.O(\Q_reg[25] [0]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\Q[18]_i_1__0
(.I0(\Data_array_SWR[6] [7]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [18]),
.O(D[9]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[18]_i_1__2
(.I0(\Data_array_SWR[6] [5]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [20]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[21] [8]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[18]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [5]),
.O(\Data_array_SWR[6] [7]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[18]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [0]),
.O(\Data_array_SWR[6] [18]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\Q[19]_i_1__0
(.I0(\Data_array_SWR[6] [6]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [19]),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[19]_i_1__2
(.I0(\Data_array_SWR[6] [4]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [21]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[21] [9]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[19]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0] [4]),
.O(\Data_array_SWR[6] [6]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[19]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [1]),
.O(\Data_array_SWR[6] [19]));
LUT3 #(
.INIT(8'hB8))
\Q[1]_i_1__3
(.I0(\Q_reg[25] [4]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[1]_i_1__6
(.I0(\Data_array_SWR[6] [22]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [3]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[21] [1]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_1__0
(.I0(\Data_array_SWR[6] [5]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [20]),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[20]_i_1__2
(.I0(\Data_array_SWR[6] [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [22]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[21] [10]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_2__0
(.I0(\Data_array_SWR[5] [21]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [3]),
.O(\Data_array_SWR[6] [5]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[20]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [6]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [2]),
.O(\Data_array_SWR[6] [20]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[20]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [7]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [3]),
.O(\Data_array_SWR[5] [21]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_1__0
(.I0(\Data_array_SWR[6] [4]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [21]),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[21]_i_1__2
(.I0(\Data_array_SWR[6] [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [23]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[21] [11]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_2__0
(.I0(\Data_array_SWR[5] [20]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [2]),
.O(\Data_array_SWR[6] [4]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[21]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [7]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [3]),
.O(\Data_array_SWR[6] [21]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[21]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [6]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [2]),
.O(\Data_array_SWR[5] [20]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_1__0
(.I0(\Data_array_SWR[6] [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [22]),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_2__0
(.I0(\Data_array_SWR[5] [19]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [1]),
.O(\Data_array_SWR[6] [3]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[22]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [4]),
.O(\Data_array_SWR[6] [22]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[22]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [5]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [1]),
.O(\Data_array_SWR[5] [19]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\Q[23]_i_1__1
(.I0(\Data_array_SWR[6] [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [23]),
.O(D[14]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\Q[23]_i_2__0
(.I0(\Data_array_SWR[5] [18]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0] [0]),
.O(\Data_array_SWR[6] [2]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[23]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [5]),
.O(\Data_array_SWR[6] [23]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[23]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [4]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [0]),
.O(\Data_array_SWR[5] [18]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[24]_i_3__0
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [6]),
.O(\Q_reg[25] [4]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[25]_i_4__0
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [7]),
.O(\Q_reg[25] [5]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\Q[2]_i_1__2
(.I0(\Data_array_SWR[6] [23]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[2]_i_1__7
(.I0(\Data_array_SWR[6] [21]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [4]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[21] [2]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\Q[3]_i_1__1
(.I0(\Data_array_SWR[6] [22]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [3]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[3]_i_1__4
(.I0(\Data_array_SWR[6] [20]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [5]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[21] [3]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\Q[4]_i_1__1
(.I0(\Data_array_SWR[6] [21]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [4]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[4]_i_1__4
(.I0(\Data_array_SWR[6] [19]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [6]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[21] [4]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\Q[5]_i_1__0
(.I0(\Data_array_SWR[6] [20]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [5]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[5]_i_1__2
(.I0(\Data_array_SWR[6] [18]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [7]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[21] [5]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\Q[6]_i_1__2
(.I0(\Data_array_SWR[6] [19]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [6]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\Q[7]_i_1__1
(.I0(\Data_array_SWR[6] [18]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [7]),
.O(D[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [0]),
.Q(\Q_reg[16] [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [1]),
.Q(\Q_reg[16] [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [2]),
.Q(\Q_reg[16] [2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized11
(D,
Q,
\Q_reg[13] ,
\Q_reg[4] ,
\Q_reg[0]_0 ,
\Q_reg[4]_0 ,
UNDRFLW_FLAG_FRMT,
OVRFLW_FLAG_FRMT,
E,
\Q_reg[1]_0 ,
CLK,
AR);
output [5:0]D;
output [1:0]Q;
output [3:0]\Q_reg[13] ;
input [0:0]\Q_reg[4] ;
input [3:0]\Q_reg[0]_0 ;
input [3:0]\Q_reg[4]_0 ;
input UNDRFLW_FLAG_FRMT;
input OVRFLW_FLAG_FRMT;
input [0:0]E;
input [1:0]\Q_reg[1]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [5:0]D;
wire [11:10]\Data_array_SWR[6] ;
wire [0:0]E;
wire OVRFLW_FLAG_FRMT;
wire [1:0]Q;
wire [3:0]\Q_reg[0]_0 ;
wire [3:0]\Q_reg[13] ;
wire [1:0]\Q_reg[1]_0 ;
wire [0:0]\Q_reg[4] ;
wire [3:0]\Q_reg[4]_0 ;
wire UNDRFLW_FLAG_FRMT;
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\Q[10]_i_1__1
(.I0(\Q_reg[4]_0 [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [10]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\Q[11]_i_1__2
(.I0(\Q_reg[4]_0 [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [11]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[12]_i_1__3
(.I0(\Data_array_SWR[6] [11]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [2]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[13] [2]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[13]_i_1__2
(.I0(\Data_array_SWR[6] [10]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [3]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[13] [3]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_1__1
(.I0(\Data_array_SWR[6] [11]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [2]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_2__0
(.I0(Q[0]),
.I1(\Q_reg[4] ),
.I2(\Q_reg[0]_0 [1]),
.O(\Data_array_SWR[6] [11]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_1__1
(.I0(\Data_array_SWR[6] [10]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [3]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_2__0
(.I0(Q[0]),
.I1(\Q_reg[4] ),
.I2(\Q_reg[0]_0 [0]),
.O(\Data_array_SWR[6] [10]));
LUT5 #(
.INIT(32'hB8FFB800))
\Q[8]_i_1__0
(.I0(Q[0]),
.I1(\Q_reg[4] ),
.I2(\Q_reg[0]_0 [3]),
.I3(Q[1]),
.I4(\Q_reg[4]_0 [0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[8]_i_1__3
(.I0(\Q_reg[4]_0 [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [10]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[13] [0]));
LUT5 #(
.INIT(32'hB8FFB800))
\Q[9]_i_1__0
(.I0(Q[0]),
.I1(\Q_reg[4] ),
.I2(\Q_reg[0]_0 [2]),
.I3(Q[1]),
.I4(\Q_reg[4]_0 [1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[9]_i_1__3
(.I0(\Q_reg[4]_0 [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [11]),
.I3(UNDRFLW_FLAG_FRMT),
.I4(OVRFLW_FLAG_FRMT),
.O(\Q_reg[13] [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [1]),
.Q(Q[1]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized12
(Q,
\Q_reg[4] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[4] ;
input [2:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[4] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized13
(S,
\Q_reg[2]_0 ,
\Q_reg[1]_0 ,
\Q_reg[1]_1 ,
Q,
\Q_reg[1]_2 ,
D,
CLK,
AR);
output [0:0]S;
output [3:0]\Q_reg[2]_0 ;
output [6:0]\Q_reg[1]_0 ;
output [3:0]\Q_reg[1]_1 ;
input [0:0]Q;
input [0:0]\Q_reg[1]_2 ;
input [12:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [12:0]D;
wire [0:0]Q;
wire [6:0]\Q_reg[1]_0 ;
wire [3:0]\Q_reg[1]_1 ;
wire [0:0]\Q_reg[1]_2 ;
wire [3:0]\Q_reg[2]_0 ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
wire [0:0]S;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[0]),
.Q(\Q_reg[1]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[1]),
.Q(\Q_reg[1]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[2]),
.Q(\Q_reg[1]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[3]),
.Q(\Q_reg[1]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[4]),
.Q(\Q_reg[1]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[5]),
.Q(\Q_reg[1]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[6]),
.Q(\Q_reg[1]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[1]_2 ),
.CLR(AR),
.D(D[9]),
.Q(\Q_reg_n_0_[9] ));
LUT2 #(
.INIT(4'h9))
S0_carry__0_i_1
(.I0(\Q_reg[1]_0 [6]),
.I1(\Q_reg_n_0_[7] ),
.O(\Q_reg[1]_1 [3]));
LUT2 #(
.INIT(4'h9))
S0_carry__0_i_2
(.I0(\Q_reg[1]_0 [5]),
.I1(\Q_reg[1]_0 [6]),
.O(\Q_reg[1]_1 [2]));
LUT2 #(
.INIT(4'h9))
S0_carry__0_i_3
(.I0(\Q_reg[1]_0 [5]),
.I1(Q),
.O(\Q_reg[1]_1 [1]));
LUT3 #(
.INIT(8'hE1))
S0_carry__0_i_4
(.I0(Q),
.I1(\Q_reg_n_0_[12] ),
.I2(\Q_reg[1]_0 [4]),
.O(\Q_reg[1]_1 [0]));
LUT1 #(
.INIT(2'h1))
S0_carry__1_i_1
(.I0(\Q_reg_n_0_[7] ),
.O(S));
LUT3 #(
.INIT(8'hE1))
S0_carry_i_2
(.I0(Q),
.I1(\Q_reg_n_0_[11] ),
.I2(\Q_reg[1]_0 [3]),
.O(\Q_reg[2]_0 [3]));
LUT3 #(
.INIT(8'hE1))
S0_carry_i_3
(.I0(Q),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg[1]_0 [2]),
.O(\Q_reg[2]_0 [2]));
LUT3 #(
.INIT(8'hE1))
S0_carry_i_4
(.I0(Q),
.I1(\Q_reg_n_0_[9] ),
.I2(\Q_reg[1]_0 [1]),
.O(\Q_reg[2]_0 [1]));
LUT2 #(
.INIT(4'hE))
S0_carry_i_5
(.I0(\Q_reg_n_0_[8] ),
.I1(Q),
.O(\Q_reg[2]_0 [0]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized14
(DI,
Q,
\Q_reg[1]_0 ,
D,
CLK,
AR);
output [0:0]DI;
output [2:0]Q;
input [0:0]\Q_reg[1]_0 ;
input [2:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [2:0]D;
wire [0:0]DI;
wire [2:0]Q;
wire [0:0]\Q_reg[1]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
LUT1 #(
.INIT(2'h1))
S0_carry_i_1
(.I0(Q[2]),
.O(DI));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized15
(O,
Q,
\Q_reg[8]_0 ,
\Q_reg[12]_0 ,
\Q_reg[16]_0 ,
\Q_reg[20]_0 ,
CO,
\Q_reg[24]_0 ,
S,
E,
\Q_reg[30]_0 ,
CLK,
AR,
\Q_reg[24]_1 );
output [3:0]O;
output [30:0]Q;
output [3:0]\Q_reg[8]_0 ;
output [3:0]\Q_reg[12]_0 ;
output [3:0]\Q_reg[16]_0 ;
output [3:0]\Q_reg[20]_0 ;
output [0:0]CO;
output [3:0]\Q_reg[24]_0 ;
input [0:0]S;
input [0:0]E;
input [30:0]\Q_reg[30]_0 ;
input CLK;
input [0:0]AR;
input [22:0]\Q_reg[24]_1 ;
wire [0:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]E;
wire [3:0]O;
wire [30:0]Q;
wire \Q[12]_i_10_n_0 ;
wire \Q[12]_i_11_n_0 ;
wire \Q[12]_i_8_n_0 ;
wire \Q[12]_i_9_n_0 ;
wire \Q[16]_i_10_n_0 ;
wire \Q[16]_i_11_n_0 ;
wire \Q[16]_i_8_n_0 ;
wire \Q[16]_i_9_n_0 ;
wire \Q[20]_i_10_n_0 ;
wire \Q[20]_i_11_n_0 ;
wire \Q[20]_i_8_n_0 ;
wire \Q[20]_i_9_n_0 ;
wire \Q[24]_i_10_n_0 ;
wire \Q[24]_i_11_n_0 ;
wire \Q[24]_i_8_n_0 ;
wire \Q[24]_i_9_n_0 ;
wire \Q[4]_i_10_n_0 ;
wire \Q[4]_i_11_n_0 ;
wire \Q[4]_i_9_n_0 ;
wire \Q[8]_i_10_n_0 ;
wire \Q[8]_i_11_n_0 ;
wire \Q[8]_i_8_n_0 ;
wire \Q[8]_i_9_n_0 ;
wire [3:0]\Q_reg[12]_0 ;
wire \Q_reg[12]_i_3_n_0 ;
wire \Q_reg[12]_i_3_n_1 ;
wire \Q_reg[12]_i_3_n_2 ;
wire \Q_reg[12]_i_3_n_3 ;
wire [3:0]\Q_reg[16]_0 ;
wire \Q_reg[16]_i_3_n_0 ;
wire \Q_reg[16]_i_3_n_1 ;
wire \Q_reg[16]_i_3_n_2 ;
wire \Q_reg[16]_i_3_n_3 ;
wire [3:0]\Q_reg[20]_0 ;
wire \Q_reg[20]_i_3_n_0 ;
wire \Q_reg[20]_i_3_n_1 ;
wire \Q_reg[20]_i_3_n_2 ;
wire \Q_reg[20]_i_3_n_3 ;
wire [3:0]\Q_reg[24]_0 ;
wire [22:0]\Q_reg[24]_1 ;
wire \Q_reg[24]_i_3_n_1 ;
wire \Q_reg[24]_i_3_n_2 ;
wire \Q_reg[24]_i_3_n_3 ;
wire [30:0]\Q_reg[30]_0 ;
wire \Q_reg[4]_i_3_n_0 ;
wire \Q_reg[4]_i_3_n_1 ;
wire \Q_reg[4]_i_3_n_2 ;
wire \Q_reg[4]_i_3_n_3 ;
wire [3:0]\Q_reg[8]_0 ;
wire \Q_reg[8]_i_3_n_0 ;
wire \Q_reg[8]_i_3_n_1 ;
wire \Q_reg[8]_i_3_n_2 ;
wire \Q_reg[8]_i_3_n_3 ;
wire [0:0]S;
LUT2 #(
.INIT(4'h6))
\Q[12]_i_10
(.I0(Q[8]),
.I1(\Q_reg[24]_1 [8]),
.O(\Q[12]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_11
(.I0(Q[7]),
.I1(\Q_reg[24]_1 [7]),
.O(\Q[12]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_8
(.I0(Q[10]),
.I1(\Q_reg[24]_1 [10]),
.O(\Q[12]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_9
(.I0(Q[9]),
.I1(\Q_reg[24]_1 [9]),
.O(\Q[12]_i_9_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_10
(.I0(Q[12]),
.I1(\Q_reg[24]_1 [12]),
.O(\Q[16]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_11
(.I0(Q[11]),
.I1(\Q_reg[24]_1 [11]),
.O(\Q[16]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_8
(.I0(Q[14]),
.I1(\Q_reg[24]_1 [14]),
.O(\Q[16]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_9
(.I0(Q[13]),
.I1(\Q_reg[24]_1 [13]),
.O(\Q[16]_i_9_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_10
(.I0(Q[16]),
.I1(\Q_reg[24]_1 [16]),
.O(\Q[20]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_11
(.I0(Q[15]),
.I1(\Q_reg[24]_1 [15]),
.O(\Q[20]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_8
(.I0(Q[18]),
.I1(\Q_reg[24]_1 [18]),
.O(\Q[20]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_9
(.I0(Q[17]),
.I1(\Q_reg[24]_1 [17]),
.O(\Q[20]_i_9_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_10
(.I0(Q[20]),
.I1(\Q_reg[24]_1 [20]),
.O(\Q[24]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_11
(.I0(Q[19]),
.I1(\Q_reg[24]_1 [19]),
.O(\Q[24]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_8
(.I0(Q[22]),
.I1(\Q_reg[24]_1 [22]),
.O(\Q[24]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_9
(.I0(Q[21]),
.I1(\Q_reg[24]_1 [21]),
.O(\Q[24]_i_9_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_10
(.I0(Q[1]),
.I1(\Q_reg[24]_1 [1]),
.O(\Q[4]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_11
(.I0(Q[0]),
.I1(\Q_reg[24]_1 [0]),
.O(\Q[4]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_9
(.I0(Q[2]),
.I1(\Q_reg[24]_1 [2]),
.O(\Q[4]_i_9_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_10
(.I0(Q[4]),
.I1(\Q_reg[24]_1 [4]),
.O(\Q[8]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_11
(.I0(Q[3]),
.I1(\Q_reg[24]_1 [3]),
.O(\Q[8]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_8
(.I0(Q[6]),
.I1(\Q_reg[24]_1 [6]),
.O(\Q[8]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_9
(.I0(Q[5]),
.I1(\Q_reg[24]_1 [5]),
.O(\Q[8]_i_9_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [12]),
.Q(Q[12]));
CARRY4 \Q_reg[12]_i_3
(.CI(\Q_reg[8]_i_3_n_0 ),
.CO({\Q_reg[12]_i_3_n_0 ,\Q_reg[12]_i_3_n_1 ,\Q_reg[12]_i_3_n_2 ,\Q_reg[12]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[10:7]),
.O(\Q_reg[12]_0 ),
.S({\Q[12]_i_8_n_0 ,\Q[12]_i_9_n_0 ,\Q[12]_i_10_n_0 ,\Q[12]_i_11_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [16]),
.Q(Q[16]));
CARRY4 \Q_reg[16]_i_3
(.CI(\Q_reg[12]_i_3_n_0 ),
.CO({\Q_reg[16]_i_3_n_0 ,\Q_reg[16]_i_3_n_1 ,\Q_reg[16]_i_3_n_2 ,\Q_reg[16]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[14:11]),
.O(\Q_reg[16]_0 ),
.S({\Q[16]_i_8_n_0 ,\Q[16]_i_9_n_0 ,\Q[16]_i_10_n_0 ,\Q[16]_i_11_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [20]),
.Q(Q[20]));
CARRY4 \Q_reg[20]_i_3
(.CI(\Q_reg[16]_i_3_n_0 ),
.CO({\Q_reg[20]_i_3_n_0 ,\Q_reg[20]_i_3_n_1 ,\Q_reg[20]_i_3_n_2 ,\Q_reg[20]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[18:15]),
.O(\Q_reg[20]_0 ),
.S({\Q[20]_i_8_n_0 ,\Q[20]_i_9_n_0 ,\Q[20]_i_10_n_0 ,\Q[20]_i_11_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [24]),
.Q(Q[24]));
CARRY4 \Q_reg[24]_i_3
(.CI(\Q_reg[20]_i_3_n_0 ),
.CO({CO,\Q_reg[24]_i_3_n_1 ,\Q_reg[24]_i_3_n_2 ,\Q_reg[24]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[22:19]),
.O(\Q_reg[24]_0 ),
.S({\Q[24]_i_8_n_0 ,\Q[24]_i_9_n_0 ,\Q[24]_i_10_n_0 ,\Q[24]_i_11_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [4]),
.Q(Q[4]));
CARRY4 \Q_reg[4]_i_3
(.CI(1'b0),
.CO({\Q_reg[4]_i_3_n_0 ,\Q_reg[4]_i_3_n_1 ,\Q_reg[4]_i_3_n_2 ,\Q_reg[4]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({Q[2:0],1'b0}),
.O(O),
.S({\Q[4]_i_9_n_0 ,\Q[4]_i_10_n_0 ,\Q[4]_i_11_n_0 ,S}));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [8]),
.Q(Q[8]));
CARRY4 \Q_reg[8]_i_3
(.CI(\Q_reg[4]_i_3_n_0 ),
.CO({\Q_reg[8]_i_3_n_0 ,\Q_reg[8]_i_3_n_1 ,\Q_reg[8]_i_3_n_2 ,\Q_reg[8]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[6:3]),
.O(\Q_reg[8]_0 ),
.S({\Q[8]_i_8_n_0 ,\Q[8]_i_9_n_0 ,\Q[8]_i_10_n_0 ,\Q[8]_i_11_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized16
(O,
\Q_reg[8]_0 ,
\Q_reg[12]_0 ,
\Q_reg[16]_0 ,
\Q_reg[20]_0 ,
\Q_reg[24]_0 ,
\Q_reg[25]_0 ,
CO,
\Q_reg[25]_1 ,
\Q_reg[24]_1 ,
S,
Q,
\Q_reg[22]_0 ,
E,
D,
CLK,
AR);
output [3:0]O;
output [3:0]\Q_reg[8]_0 ;
output [3:0]\Q_reg[12]_0 ;
output [3:0]\Q_reg[16]_0 ;
output [3:0]\Q_reg[20]_0 ;
output [3:0]\Q_reg[24]_0 ;
output [0:0]\Q_reg[25]_0 ;
output [0:0]CO;
output [0:0]\Q_reg[25]_1 ;
output [23:0]\Q_reg[24]_1 ;
output [0:0]S;
input [22:0]Q;
input [0:0]\Q_reg[22]_0 ;
input [0:0]E;
input [25:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]CO;
wire [25:0]D;
wire [0:0]E;
wire [3:0]O;
wire [22:0]Q;
wire \Q[12]_i_4__0_n_0 ;
wire \Q[12]_i_5__0_n_0 ;
wire \Q[12]_i_6__0_n_0 ;
wire \Q[12]_i_7_n_0 ;
wire \Q[16]_i_4_n_0 ;
wire \Q[16]_i_5_n_0 ;
wire \Q[16]_i_6_n_0 ;
wire \Q[16]_i_7_n_0 ;
wire \Q[20]_i_4__0_n_0 ;
wire \Q[20]_i_5__0_n_0 ;
wire \Q[20]_i_6_n_0 ;
wire \Q[20]_i_7_n_0 ;
wire \Q[24]_i_4__0_n_0 ;
wire \Q[24]_i_5_n_0 ;
wire \Q[24]_i_6_n_0 ;
wire \Q[24]_i_7_n_0 ;
wire \Q[25]_i_5_n_0 ;
wire \Q[4]_i_5_n_0 ;
wire \Q[4]_i_6_n_0 ;
wire \Q[4]_i_7_n_0 ;
wire \Q[8]_i_4__0_n_0 ;
wire \Q[8]_i_5__0_n_0 ;
wire \Q[8]_i_6_n_0 ;
wire \Q[8]_i_7_n_0 ;
wire [3:0]\Q_reg[12]_0 ;
wire \Q_reg[12]_i_2_n_0 ;
wire \Q_reg[12]_i_2_n_1 ;
wire \Q_reg[12]_i_2_n_2 ;
wire \Q_reg[12]_i_2_n_3 ;
wire [3:0]\Q_reg[16]_0 ;
wire \Q_reg[16]_i_2_n_0 ;
wire \Q_reg[16]_i_2_n_1 ;
wire \Q_reg[16]_i_2_n_2 ;
wire \Q_reg[16]_i_2_n_3 ;
wire [3:0]\Q_reg[20]_0 ;
wire \Q_reg[20]_i_2_n_0 ;
wire \Q_reg[20]_i_2_n_1 ;
wire \Q_reg[20]_i_2_n_2 ;
wire \Q_reg[20]_i_2_n_3 ;
wire [0:0]\Q_reg[22]_0 ;
wire [3:0]\Q_reg[24]_0 ;
wire [23:0]\Q_reg[24]_1 ;
wire \Q_reg[24]_i_2_n_0 ;
wire \Q_reg[24]_i_2_n_1 ;
wire \Q_reg[24]_i_2_n_2 ;
wire \Q_reg[24]_i_2_n_3 ;
wire [0:0]\Q_reg[25]_0 ;
wire [0:0]\Q_reg[25]_1 ;
wire \Q_reg[4]_i_2_n_0 ;
wire \Q_reg[4]_i_2_n_1 ;
wire \Q_reg[4]_i_2_n_2 ;
wire \Q_reg[4]_i_2_n_3 ;
wire [3:0]\Q_reg[8]_0 ;
wire \Q_reg[8]_i_2_n_0 ;
wire \Q_reg[8]_i_2_n_1 ;
wire \Q_reg[8]_i_2_n_2 ;
wire \Q_reg[8]_i_2_n_3 ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[25] ;
wire [1:0]p_0_in__0;
wire [3:0]\NLW_Q_reg[25]_i_2_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[25]_i_2_O_UNCONNECTED ;
wire [3:0]\NLW_Q_reg[25]_i_3_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[25]_i_3_O_UNCONNECTED ;
assign S[0] = \Q_reg_n_0_[1] ;
LUT2 #(
.INIT(4'h9))
\Q[12]_i_4__0
(.I0(\Q_reg[24]_1 [11]),
.I1(Q[10]),
.O(\Q[12]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_5__0
(.I0(\Q_reg[24]_1 [10]),
.I1(Q[9]),
.O(\Q[12]_i_5__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_6__0
(.I0(\Q_reg[24]_1 [9]),
.I1(Q[8]),
.O(\Q[12]_i_6__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_7
(.I0(\Q_reg[24]_1 [8]),
.I1(Q[7]),
.O(\Q[12]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_4
(.I0(\Q_reg[24]_1 [15]),
.I1(Q[14]),
.O(\Q[16]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_5
(.I0(\Q_reg[24]_1 [14]),
.I1(Q[13]),
.O(\Q[16]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_6
(.I0(\Q_reg[24]_1 [13]),
.I1(Q[12]),
.O(\Q[16]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_7
(.I0(\Q_reg[24]_1 [12]),
.I1(Q[11]),
.O(\Q[16]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_4__0
(.I0(\Q_reg[24]_1 [19]),
.I1(Q[18]),
.O(\Q[20]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_5__0
(.I0(\Q_reg[24]_1 [18]),
.I1(Q[17]),
.O(\Q[20]_i_5__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_6
(.I0(\Q_reg[24]_1 [17]),
.I1(Q[16]),
.O(\Q[20]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_7
(.I0(\Q_reg[24]_1 [16]),
.I1(Q[15]),
.O(\Q[20]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_4__0
(.I0(\Q_reg[24]_1 [23]),
.I1(Q[22]),
.O(\Q[24]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_5
(.I0(\Q_reg[24]_1 [22]),
.I1(Q[21]),
.O(\Q[24]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_6
(.I0(\Q_reg[24]_1 [21]),
.I1(Q[20]),
.O(\Q[24]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_7
(.I0(\Q_reg[24]_1 [20]),
.I1(Q[19]),
.O(\Q[24]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[25]_i_5
(.I0(\Q_reg_n_0_[25] ),
.O(\Q[25]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_4
(.I0(\Q_reg[24]_1 [0]),
.O(p_0_in__0[0]));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_5
(.I0(\Q_reg[24]_1 [3]),
.I1(Q[2]),
.O(\Q[4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_6
(.I0(\Q_reg[24]_1 [2]),
.I1(Q[1]),
.O(\Q[4]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_7
(.I0(\Q_reg[24]_1 [1]),
.I1(Q[0]),
.O(\Q[4]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_8
(.I0(\Q_reg_n_0_[1] ),
.O(p_0_in__0[1]));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_4__0
(.I0(\Q_reg[24]_1 [7]),
.I1(Q[6]),
.O(\Q[8]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_5__0
(.I0(\Q_reg[24]_1 [6]),
.I1(Q[5]),
.O(\Q[8]_i_5__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_6
(.I0(\Q_reg[24]_1 [5]),
.I1(Q[4]),
.O(\Q[8]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_7
(.I0(\Q_reg[24]_1 [4]),
.I1(Q[3]),
.O(\Q[8]_i_7_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(\Q_reg[24]_1 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(\Q_reg[24]_1 [9]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(\Q_reg[24]_1 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(\Q_reg[24]_1 [11]));
CARRY4 \Q_reg[12]_i_2
(.CI(\Q_reg[8]_i_2_n_0 ),
.CO({\Q_reg[12]_i_2_n_0 ,\Q_reg[12]_i_2_n_1 ,\Q_reg[12]_i_2_n_2 ,\Q_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(Q[10:7]),
.O(\Q_reg[12]_0 ),
.S({\Q[12]_i_4__0_n_0 ,\Q[12]_i_5__0_n_0 ,\Q[12]_i_6__0_n_0 ,\Q[12]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(\Q_reg[24]_1 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(\Q_reg[24]_1 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(\Q_reg[24]_1 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(\Q_reg[24]_1 [15]));
CARRY4 \Q_reg[16]_i_2
(.CI(\Q_reg[12]_i_2_n_0 ),
.CO({\Q_reg[16]_i_2_n_0 ,\Q_reg[16]_i_2_n_1 ,\Q_reg[16]_i_2_n_2 ,\Q_reg[16]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(Q[14:11]),
.O(\Q_reg[16]_0 ),
.S({\Q[16]_i_4_n_0 ,\Q[16]_i_5_n_0 ,\Q[16]_i_6_n_0 ,\Q[16]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(\Q_reg[24]_1 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(\Q_reg[24]_1 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(\Q_reg[24]_1 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(\Q_reg[24]_1 [19]));
CARRY4 \Q_reg[20]_i_2
(.CI(\Q_reg[16]_i_2_n_0 ),
.CO({\Q_reg[20]_i_2_n_0 ,\Q_reg[20]_i_2_n_1 ,\Q_reg[20]_i_2_n_2 ,\Q_reg[20]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(Q[18:15]),
.O(\Q_reg[20]_0 ),
.S({\Q[20]_i_4__0_n_0 ,\Q[20]_i_5__0_n_0 ,\Q[20]_i_6_n_0 ,\Q[20]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(\Q_reg[24]_1 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(\Q_reg[24]_1 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(\Q_reg[24]_1 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(\Q_reg[24]_1 [23]));
CARRY4 \Q_reg[24]_i_2
(.CI(\Q_reg[20]_i_2_n_0 ),
.CO({\Q_reg[24]_i_2_n_0 ,\Q_reg[24]_i_2_n_1 ,\Q_reg[24]_i_2_n_2 ,\Q_reg[24]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(Q[22:19]),
.O(\Q_reg[24]_0 ),
.S({\Q[24]_i_4__0_n_0 ,\Q[24]_i_5_n_0 ,\Q[24]_i_6_n_0 ,\Q[24]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(\Q_reg_n_0_[25] ));
CARRY4 \Q_reg[25]_i_2
(.CI(\Q_reg[24]_i_2_n_0 ),
.CO(\NLW_Q_reg[25]_i_2_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_Q_reg[25]_i_2_O_UNCONNECTED [3:1],\Q_reg[25]_0 }),
.S({1'b0,1'b0,1'b0,\Q_reg_n_0_[25] }));
CARRY4 \Q_reg[25]_i_3
(.CI(\Q_reg[22]_0 ),
.CO({\NLW_Q_reg[25]_i_3_CO_UNCONNECTED [3:2],CO,\NLW_Q_reg[25]_i_3_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\Q_reg_n_0_[25] }),
.O({\NLW_Q_reg[25]_i_3_O_UNCONNECTED [3:1],\Q_reg[25]_1 }),
.S({1'b0,1'b0,1'b1,\Q[25]_i_5_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(\Q_reg[24]_1 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(\Q_reg[24]_1 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(\Q_reg[24]_1 [3]));
CARRY4 \Q_reg[4]_i_2
(.CI(1'b0),
.CO({\Q_reg[4]_i_2_n_0 ,\Q_reg[4]_i_2_n_1 ,\Q_reg[4]_i_2_n_2 ,\Q_reg[4]_i_2_n_3 }),
.CYINIT(p_0_in__0[0]),
.DI({Q[2:0],1'b0}),
.O(O),
.S({\Q[4]_i_5_n_0 ,\Q[4]_i_6_n_0 ,\Q[4]_i_7_n_0 ,p_0_in__0[1]}));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(\Q_reg[24]_1 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(\Q_reg[24]_1 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(\Q_reg[24]_1 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(\Q_reg[24]_1 [7]));
CARRY4 \Q_reg[8]_i_2
(.CI(\Q_reg[4]_i_2_n_0 ),
.CO({\Q_reg[8]_i_2_n_0 ,\Q_reg[8]_i_2_n_1 ,\Q_reg[8]_i_2_n_2 ,\Q_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(Q[6:3]),
.O(\Q_reg[8]_0 ),
.S({\Q[8]_i_4__0_n_0 ,\Q[8]_i_5__0_n_0 ,\Q[8]_i_6_n_0 ,\Q[8]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(\Q_reg[24]_1 [8]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized17
(\Q_reg[2]_0 ,
\Q_reg[25] ,
CO,
E,
Q,
CLK,
AR,
O,
\Q_reg[2]_1 ,
\Q_reg[6] ,
\Q_reg[6]_0 ,
\Q_reg[10] ,
\Q_reg[10]_0 ,
\Q_reg[14] ,
\Q_reg[14]_0 ,
\Q_reg[18] ,
\Q_reg[18]_0 ,
\Q_reg[22] ,
\Q_reg[22]_0 ,
\Q_reg[22]_1 ,
\Q_reg[25]_0 );
output [2:0]\Q_reg[2]_0 ;
output [24:0]\Q_reg[25] ;
input [0:0]CO;
input [0:0]E;
input [2:0]Q;
input CLK;
input [0:0]AR;
input [3:0]O;
input [3:0]\Q_reg[2]_1 ;
input [3:0]\Q_reg[6] ;
input [3:0]\Q_reg[6]_0 ;
input [3:0]\Q_reg[10] ;
input [3:0]\Q_reg[10]_0 ;
input [3:0]\Q_reg[14] ;
input [3:0]\Q_reg[14]_0 ;
input [3:0]\Q_reg[18] ;
input [3:0]\Q_reg[18]_0 ;
input [3:0]\Q_reg[22] ;
input [3:0]\Q_reg[22]_0 ;
input [0:0]\Q_reg[22]_1 ;
input [0:0]\Q_reg[25]_0 ;
wire [0:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]E;
wire [3:0]O;
wire [2:0]Q;
wire [3:0]\Q_reg[10] ;
wire [3:0]\Q_reg[10]_0 ;
wire [3:0]\Q_reg[14] ;
wire [3:0]\Q_reg[14]_0 ;
wire [3:0]\Q_reg[18] ;
wire [3:0]\Q_reg[18]_0 ;
wire [3:0]\Q_reg[22] ;
wire [3:0]\Q_reg[22]_0 ;
wire [0:0]\Q_reg[22]_1 ;
wire [24:0]\Q_reg[25] ;
wire [0:0]\Q_reg[25]_0 ;
wire [2:0]\Q_reg[2]_0 ;
wire [3:0]\Q_reg[2]_1 ;
wire [3:0]\Q_reg[6] ;
wire [3:0]\Q_reg[6]_0 ;
wire [1:1]p_0_in;
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1__2
(.I0(\Q_reg[10] [1]),
.I1(\Q_reg[10]_0 [1]),
.I2(p_0_in),
.O(\Q_reg[25] [9]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1__3
(.I0(\Q_reg[10] [2]),
.I1(\Q_reg[10]_0 [2]),
.I2(p_0_in),
.O(\Q_reg[25] [10]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1__1
(.I0(\Q_reg[10] [3]),
.I1(\Q_reg[10]_0 [3]),
.I2(p_0_in),
.O(\Q_reg[25] [11]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1__1
(.I0(\Q_reg[14] [0]),
.I1(\Q_reg[14]_0 [0]),
.I2(p_0_in),
.O(\Q_reg[25] [12]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1__2
(.I0(\Q_reg[14] [1]),
.I1(\Q_reg[14]_0 [1]),
.I2(p_0_in),
.O(\Q_reg[25] [13]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1__2
(.I0(\Q_reg[14] [2]),
.I1(\Q_reg[14]_0 [2]),
.I2(p_0_in),
.O(\Q_reg[25] [14]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1__1
(.I0(\Q_reg[14] [3]),
.I1(\Q_reg[14]_0 [3]),
.I2(p_0_in),
.O(\Q_reg[25] [15]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1__1
(.I0(\Q_reg[18] [0]),
.I1(\Q_reg[18]_0 [0]),
.I2(p_0_in),
.O(\Q_reg[25] [16]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1__1
(.I0(\Q_reg[18] [1]),
.I1(\Q_reg[18]_0 [1]),
.I2(p_0_in),
.O(\Q_reg[25] [17]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1__1
(.I0(\Q_reg[18] [2]),
.I1(\Q_reg[18]_0 [2]),
.I2(p_0_in),
.O(\Q_reg[25] [18]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1__4
(.I0(O[0]),
.I1(\Q_reg[2]_1 [0]),
.I2(p_0_in),
.O(\Q_reg[25] [0]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1__1
(.I0(\Q_reg[18] [3]),
.I1(\Q_reg[18]_0 [3]),
.I2(p_0_in),
.O(\Q_reg[25] [19]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1__1
(.I0(\Q_reg[22] [0]),
.I1(\Q_reg[22]_0 [0]),
.I2(p_0_in),
.O(\Q_reg[25] [20]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1__1
(.I0(\Q_reg[22] [1]),
.I1(\Q_reg[22]_0 [1]),
.I2(p_0_in),
.O(\Q_reg[25] [21]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1__2
(.I0(\Q_reg[22] [2]),
.I1(\Q_reg[22]_0 [2]),
.I2(p_0_in),
.O(\Q_reg[25] [22]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1__2
(.I0(\Q_reg[22] [3]),
.I1(\Q_reg[22]_0 [3]),
.I2(p_0_in),
.O(\Q_reg[25] [23]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1__1
(.I0(\Q_reg[22]_1 ),
.I1(\Q_reg[25]_0 ),
.I2(p_0_in),
.O(\Q_reg[25] [24]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1__3
(.I0(O[1]),
.I1(\Q_reg[2]_1 [1]),
.I2(p_0_in),
.O(\Q_reg[25] [1]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT2 #(
.INIT(4'h2))
\Q[2]_i_1__4
(.I0(CO),
.I1(p_0_in),
.O(\Q_reg[2]_0 [2]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1__2
(.I0(O[2]),
.I1(\Q_reg[2]_1 [2]),
.I2(p_0_in),
.O(\Q_reg[25] [2]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1__2
(.I0(O[3]),
.I1(\Q_reg[2]_1 [3]),
.I2(p_0_in),
.O(\Q_reg[25] [3]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1__1
(.I0(\Q_reg[6] [0]),
.I1(\Q_reg[6]_0 [0]),
.I2(p_0_in),
.O(\Q_reg[25] [4]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1__3
(.I0(\Q_reg[6] [1]),
.I1(\Q_reg[6]_0 [1]),
.I2(p_0_in),
.O(\Q_reg[25] [5]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1__2
(.I0(\Q_reg[6] [2]),
.I1(\Q_reg[6]_0 [2]),
.I2(p_0_in),
.O(\Q_reg[25] [6]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1__1
(.I0(\Q_reg[6] [3]),
.I1(\Q_reg[6]_0 [3]),
.I2(p_0_in),
.O(\Q_reg[25] [7]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1__1
(.I0(\Q_reg[10] [0]),
.I1(\Q_reg[10]_0 [0]),
.I2(p_0_in),
.O(\Q_reg[25] [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(Q[0]),
.Q(\Q_reg[2]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(p_0_in));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\Q_reg[2]_0 [1]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized18
(D,
\Q_reg[12]_0 ,
\Q_reg[4]_0 ,
Q,
\Q_reg[2]_0 ,
\Q_reg[2]_1 ,
\Q_reg[22]_0 ,
\Q_reg[4]_1 ,
\Q_reg[1]_0 ,
CLK,
AR);
output [25:0]D;
output [4:0]\Q_reg[12]_0 ;
output [2:0]\Q_reg[4]_0 ;
input [0:0]Q;
input [1:0]\Q_reg[2]_0 ;
input [0:0]\Q_reg[2]_1 ;
input [22:0]\Q_reg[22]_0 ;
input [4:0]\Q_reg[4]_1 ;
input [25:0]\Q_reg[1]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [25:0]D;
wire [25:0]\Data_array_SWR[0] ;
wire [0:0]Q;
wire \Q[10]_i_2__0_n_0 ;
wire \Q[10]_i_3_n_0 ;
wire \Q[10]_i_4_n_0 ;
wire \Q[11]_i_2_n_0 ;
wire \Q[11]_i_3_n_0 ;
wire \Q[11]_i_4_n_0 ;
wire \Q[11]_i_5_n_0 ;
wire \Q[11]_i_6_n_0 ;
wire \Q[12]_i_2_n_0 ;
wire \Q[12]_i_3_n_0 ;
wire \Q[12]_i_4_n_0 ;
wire \Q[12]_i_5_n_0 ;
wire \Q[12]_i_6_n_0 ;
wire \Q[12]_i_7__0_n_0 ;
wire \Q[8]_i_10__0_n_0 ;
wire \Q[8]_i_11__0_n_0 ;
wire \Q[8]_i_2__0_n_0 ;
wire \Q[8]_i_3_n_0 ;
wire \Q[8]_i_4_n_0 ;
wire \Q[8]_i_5_n_0 ;
wire \Q[8]_i_6__0_n_0 ;
wire \Q[8]_i_7__0_n_0 ;
wire \Q[8]_i_8__0_n_0 ;
wire \Q[8]_i_9__0_n_0 ;
wire \Q[9]_i_2_n_0 ;
wire \Q[9]_i_3_n_0 ;
wire \Q[9]_i_4_n_0 ;
wire \Q[9]_i_5_n_0 ;
wire \Q[9]_i_6_n_0 ;
wire [4:0]\Q_reg[12]_0 ;
wire [25:0]\Q_reg[1]_0 ;
wire [22:0]\Q_reg[22]_0 ;
wire [1:0]\Q_reg[2]_0 ;
wire [0:0]\Q_reg[2]_1 ;
wire [2:0]\Q_reg[4]_0 ;
wire [4:0]\Q_reg[4]_1 ;
wire \Q_reg_n_0_[0] ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[13] ;
wire \Q_reg_n_0_[14] ;
wire \Q_reg_n_0_[15] ;
wire \Q_reg_n_0_[16] ;
wire \Q_reg_n_0_[17] ;
wire \Q_reg_n_0_[18] ;
wire \Q_reg_n_0_[19] ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[20] ;
wire \Q_reg_n_0_[21] ;
wire \Q_reg_n_0_[22] ;
wire \Q_reg_n_0_[23] ;
wire \Q_reg_n_0_[24] ;
wire \Q_reg_n_0_[25] ;
wire \Q_reg_n_0_[2] ;
wire \Q_reg_n_0_[3] ;
wire \Q_reg_n_0_[4] ;
wire \Q_reg_n_0_[5] ;
wire \Q_reg_n_0_[6] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
wire [1:0]shft_value_mux_o_EWR__0;
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[0]_i_1__0
(.I0(\Data_array_SWR[0] [3]),
.I1(\Data_array_SWR[0] [2]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [1]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT4 #(
.INIT(16'hC808))
\Q[0]_i_2
(.I0(\Q_reg_n_0_[25] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[0] ),
.O(\Data_array_SWR[0] [0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[10]_i_1
(.I0(\Data_array_SWR[0] [13]),
.I1(\Data_array_SWR[0] [12]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [11]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [10]),
.O(D[10]));
LUT6 #(
.INIT(64'h000000000000000E))
\Q[10]_i_1__3
(.I0(\Q[10]_i_2__0_n_0 ),
.I1(\Q[12]_i_2_n_0 ),
.I2(\Q_reg_n_0_[24] ),
.I3(\Q_reg_n_0_[25] ),
.I4(\Q_reg_n_0_[22] ),
.I5(\Q_reg_n_0_[23] ),
.O(\Q_reg[12]_0 [2]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[10]_i_2
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[10] ),
.I4(\Q_reg[22]_0 [8]),
.O(\Data_array_SWR[0] [10]));
LUT6 #(
.INIT(64'h00000000FFFFFFFE))
\Q[10]_i_2__0
(.I0(\Q_reg_n_0_[13] ),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg_n_0_[12] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q[10]_i_3_n_0 ),
.I5(\Q[12]_i_6_n_0 ),
.O(\Q[10]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT5 #(
.INIT(32'h00000002))
\Q[10]_i_3
(.I0(\Q[10]_i_4_n_0 ),
.I1(\Q_reg_n_0_[6] ),
.I2(\Q_reg_n_0_[7] ),
.I3(\Q_reg_n_0_[9] ),
.I4(\Q_reg_n_0_[8] ),
.O(\Q[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF4))
\Q[10]_i_4
(.I0(\Q_reg_n_0_[1] ),
.I1(\Q_reg_n_0_[0] ),
.I2(\Q_reg_n_0_[3] ),
.I3(\Q_reg_n_0_[2] ),
.I4(\Q_reg_n_0_[4] ),
.I5(\Q_reg_n_0_[5] ),
.O(\Q[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[11]_i_1
(.I0(\Data_array_SWR[0] [14]),
.I1(\Data_array_SWR[0] [13]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [12]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [11]),
.O(D[11]));
LUT6 #(
.INIT(64'h1010101010101110))
\Q[11]_i_1__0
(.I0(\Q[11]_i_2_n_0 ),
.I1(\Q[12]_i_2_n_0 ),
.I2(\Q[11]_i_3_n_0 ),
.I3(\Q[11]_i_4_n_0 ),
.I4(\Q_reg_n_0_[7] ),
.I5(\Q[11]_i_5_n_0 ),
.O(\Q_reg[12]_0 [3]));
LUT4 #(
.INIT(16'hFFFE))
\Q[11]_i_2
(.I0(\Q_reg_n_0_[23] ),
.I1(\Q_reg_n_0_[22] ),
.I2(\Q_reg_n_0_[25] ),
.I3(\Q_reg_n_0_[24] ),
.O(\Q[11]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[11]_i_2__0
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q_reg[22]_0 [9]),
.O(\Data_array_SWR[0] [11]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\Q[11]_i_3
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg_n_0_[12] ),
.I2(\Q_reg_n_0_[10] ),
.I3(\Q_reg_n_0_[17] ),
.I4(\Q[11]_i_6_n_0 ),
.O(\Q[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000002))
\Q[11]_i_4
(.I0(\Q_reg_n_0_[1] ),
.I1(\Q_reg_n_0_[5] ),
.I2(\Q_reg_n_0_[2] ),
.I3(\Q_reg_n_0_[6] ),
.I4(\Q_reg_n_0_[4] ),
.I5(\Q_reg_n_0_[3] ),
.O(\Q[11]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'hE))
\Q[11]_i_5
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg_n_0_[9] ),
.O(\Q[11]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[11]_i_6
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg_n_0_[13] ),
.I2(\Q_reg_n_0_[16] ),
.I3(\Q_reg_n_0_[15] ),
.O(\Q[11]_i_6_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[12]_i_1
(.I0(\Data_array_SWR[0] [15]),
.I1(\Data_array_SWR[0] [14]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [13]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [12]),
.O(D[12]));
LUT6 #(
.INIT(64'h0000000000000001))
\Q[12]_i_1__2
(.I0(\Q[12]_i_2_n_0 ),
.I1(\Q[12]_i_3_n_0 ),
.I2(\Q_reg_n_0_[22] ),
.I3(\Q_reg_n_0_[23] ),
.I4(\Q[12]_i_4_n_0 ),
.I5(\Q_reg_n_0_[25] ),
.O(\Q_reg[12]_0 [4]));
LUT4 #(
.INIT(16'hFFFE))
\Q[12]_i_2
(.I0(\Q_reg_n_0_[19] ),
.I1(\Q_reg_n_0_[18] ),
.I2(\Q_reg_n_0_[21] ),
.I3(\Q_reg_n_0_[20] ),
.O(\Q[12]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[12]_i_2__0
(.I0(\Q_reg_n_0_[13] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[12] ),
.I4(\Q_reg[22]_0 [10]),
.O(\Data_array_SWR[0] [12]));
LUT5 #(
.INIT(32'hAAAAAAAB))
\Q[12]_i_3
(.I0(\Q_reg_n_0_[24] ),
.I1(\Q_reg_n_0_[8] ),
.I2(\Q[12]_i_5_n_0 ),
.I3(\Q_reg_n_0_[7] ),
.I4(\Q_reg_n_0_[9] ),
.O(\Q[12]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\Q[12]_i_4
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[13] ),
.I2(\Q_reg_n_0_[10] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q[12]_i_6_n_0 ),
.O(\Q[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFEFFFFFFFF))
\Q[12]_i_5
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg_n_0_[4] ),
.I2(\Q_reg_n_0_[5] ),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q_reg_n_0_[0] ),
.I5(\Q[12]_i_7__0_n_0 ),
.O(\Q[12]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[12]_i_6
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[14] ),
.I2(\Q_reg_n_0_[17] ),
.I3(\Q_reg_n_0_[16] ),
.O(\Q[12]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'h1))
\Q[12]_i_7__0
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg_n_0_[2] ),
.O(\Q[12]_i_7__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_1
(.I0(\Data_array_SWR[0] [16]),
.I1(\Data_array_SWR[0] [15]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [14]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [13]),
.O(D[13]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[13]_i_2
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[13] ),
.I4(\Q_reg[22]_0 [11]),
.O(\Data_array_SWR[0] [13]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[14]_i_1
(.I0(\Data_array_SWR[0] [17]),
.I1(\Data_array_SWR[0] [16]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [15]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [14]),
.O(D[14]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[14]_i_2
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[14] ),
.I4(\Q_reg[22]_0 [12]),
.O(\Data_array_SWR[0] [14]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[15]_i_1
(.I0(\Data_array_SWR[0] [18]),
.I1(\Data_array_SWR[0] [17]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [16]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [15]),
.O(D[15]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[15]_i_2
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[15] ),
.I4(\Q_reg[22]_0 [13]),
.O(\Data_array_SWR[0] [15]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_1
(.I0(\Data_array_SWR[0] [19]),
.I1(\Data_array_SWR[0] [18]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [17]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [16]),
.O(D[16]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[16]_i_2
(.I0(\Q_reg_n_0_[9] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[16] ),
.I4(\Q_reg[22]_0 [14]),
.O(\Data_array_SWR[0] [16]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_1
(.I0(\Data_array_SWR[0] [20]),
.I1(\Data_array_SWR[0] [19]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [18]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [17]),
.O(D[17]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[17]_i_2
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[17] ),
.I4(\Q_reg[22]_0 [15]),
.O(\Data_array_SWR[0] [17]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_1
(.I0(\Data_array_SWR[0] [21]),
.I1(\Data_array_SWR[0] [20]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [19]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [18]),
.O(D[18]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[18]_i_2
(.I0(\Q_reg_n_0_[7] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[18] ),
.I4(\Q_reg[22]_0 [16]),
.O(\Data_array_SWR[0] [18]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_1
(.I0(\Data_array_SWR[0] [22]),
.I1(\Data_array_SWR[0] [21]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [20]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [19]),
.O(D[19]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[19]_i_2
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[19] ),
.I4(\Q_reg[22]_0 [17]),
.O(\Data_array_SWR[0] [19]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[1]_i_1
(.I0(\Data_array_SWR[0] [4]),
.I1(\Data_array_SWR[0] [3]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [2]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT4 #(
.INIT(16'hC808))
\Q[1]_i_2
(.I0(\Q_reg_n_0_[24] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[1] ),
.O(\Data_array_SWR[0] [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_1
(.I0(\Data_array_SWR[0] [23]),
.I1(\Data_array_SWR[0] [22]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [21]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [20]),
.O(D[20]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[20]_i_2
(.I0(\Q_reg_n_0_[5] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[20] ),
.I4(\Q_reg[22]_0 [18]),
.O(\Data_array_SWR[0] [20]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_1
(.I0(\Data_array_SWR[0] [24]),
.I1(\Data_array_SWR[0] [23]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [22]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [21]),
.O(D[21]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[21]_i_2
(.I0(\Q_reg_n_0_[4] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q_reg[22]_0 [19]),
.O(\Data_array_SWR[0] [21]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_1
(.I0(\Data_array_SWR[0] [25]),
.I1(\Data_array_SWR[0] [24]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [23]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [22]),
.O(D[22]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[22]_i_2
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[22] ),
.I4(\Q_reg[22]_0 [20]),
.O(\Data_array_SWR[0] [22]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[23]_i_1
(.I0(\Q_reg[2]_1 ),
.I1(\Data_array_SWR[0] [25]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [24]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [23]),
.O(D[23]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[23]_i_2
(.I0(\Q_reg_n_0_[2] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[23] ),
.I4(\Q_reg[22]_0 [21]),
.O(\Data_array_SWR[0] [23]));
LUT6 #(
.INIT(64'h8F808F8F8F808080))
\Q[24]_i_1
(.I0(Q),
.I1(\Q_reg[2]_0 [0]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [25]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [24]),
.O(D[24]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT4 #(
.INIT(16'hFB3B))
\Q[24]_i_2
(.I0(\Q_reg_n_0_[0] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[25] ),
.O(\Data_array_SWR[0] [25]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT5 #(
.INIT(32'hFB3BC808))
\Q[24]_i_3
(.I0(\Q_reg_n_0_[1] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[24] ),
.I4(\Q_reg[22]_0 [22]),
.O(\Data_array_SWR[0] [24]));
LUT6 #(
.INIT(64'hFF111011EE111011))
\Q[25]_i_2
(.I0(shft_value_mux_o_EWR__0[1]),
.I1(shft_value_mux_o_EWR__0[0]),
.I2(\Q_reg_n_0_[0] ),
.I3(\Q_reg[2]_0 [0]),
.I4(Q),
.I5(\Q_reg_n_0_[25] ),
.O(D[25]));
LUT4 #(
.INIT(16'h2F20))
\Q[25]_i_3
(.I0(\Q_reg[12]_0 [1]),
.I1(Q),
.I2(\Q_reg[2]_0 [0]),
.I3(\Q_reg[4]_1 [1]),
.O(shft_value_mux_o_EWR__0[1]));
LUT4 #(
.INIT(16'hEEF0))
\Q[25]_i_4
(.I0(\Q_reg[12]_0 [0]),
.I1(Q),
.I2(\Q_reg[4]_1 [0]),
.I3(\Q_reg[2]_0 [0]),
.O(shft_value_mux_o_EWR__0[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[2]_i_1
(.I0(\Data_array_SWR[0] [5]),
.I1(\Data_array_SWR[0] [4]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [3]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [2]),
.O(D[2]));
LUT4 #(
.INIT(16'h2F20))
\Q[2]_i_1__0
(.I0(\Q_reg[12]_0 [2]),
.I1(Q),
.I2(\Q_reg[2]_0 [0]),
.I3(\Q_reg[4]_1 [2]),
.O(\Q_reg[4]_0 [0]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[2]_i_2
(.I0(\Q_reg_n_0_[23] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[2] ),
.I4(\Q_reg[22]_0 [0]),
.O(\Data_array_SWR[0] [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[3]_i_1
(.I0(\Data_array_SWR[0] [6]),
.I1(\Data_array_SWR[0] [5]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [4]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [3]),
.O(D[3]));
LUT4 #(
.INIT(16'h2F20))
\Q[3]_i_1__0
(.I0(\Q_reg[12]_0 [3]),
.I1(Q),
.I2(\Q_reg[2]_0 [0]),
.I3(\Q_reg[4]_1 [3]),
.O(\Q_reg[4]_0 [1]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[3]_i_2
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[3] ),
.I4(\Q_reg[22]_0 [1]),
.O(\Data_array_SWR[0] [3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[4]_i_1
(.I0(\Data_array_SWR[0] [7]),
.I1(\Data_array_SWR[0] [6]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [5]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [4]),
.O(D[4]));
LUT4 #(
.INIT(16'h2F20))
\Q[4]_i_1__0
(.I0(\Q_reg[12]_0 [4]),
.I1(Q),
.I2(\Q_reg[2]_0 [0]),
.I3(\Q_reg[4]_1 [4]),
.O(\Q_reg[4]_0 [2]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[4]_i_2
(.I0(\Q_reg_n_0_[21] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[4] ),
.I4(\Q_reg[22]_0 [2]),
.O(\Data_array_SWR[0] [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[5]_i_1
(.I0(\Data_array_SWR[0] [8]),
.I1(\Data_array_SWR[0] [7]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [6]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [5]),
.O(D[5]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[5]_i_2
(.I0(\Q_reg_n_0_[20] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[5] ),
.I4(\Q_reg[22]_0 [3]),
.O(\Data_array_SWR[0] [5]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[6]_i_1
(.I0(\Data_array_SWR[0] [9]),
.I1(\Data_array_SWR[0] [8]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [7]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [6]),
.O(D[6]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[6]_i_2
(.I0(\Q_reg_n_0_[19] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[6] ),
.I4(\Q_reg[22]_0 [4]),
.O(\Data_array_SWR[0] [6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[7]_i_1
(.I0(\Data_array_SWR[0] [10]),
.I1(\Data_array_SWR[0] [9]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [8]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [7]),
.O(D[7]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[7]_i_2
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[7] ),
.I4(\Q_reg[22]_0 [5]),
.O(\Data_array_SWR[0] [7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[8]_i_1
(.I0(\Data_array_SWR[0] [11]),
.I1(\Data_array_SWR[0] [10]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [9]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [8]),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h00004544))
\Q[8]_i_10__0
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg_n_0_[2] ),
.I2(\Q_reg_n_0_[1] ),
.I3(\Q_reg_n_0_[0] ),
.I4(\Q_reg_n_0_[5] ),
.O(\Q[8]_i_10__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT2 #(
.INIT(4'hE))
\Q[8]_i_11__0
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg_n_0_[12] ),
.O(\Q[8]_i_11__0_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFF888A))
\Q[8]_i_1__2
(.I0(\Q[8]_i_2__0_n_0 ),
.I1(\Q[8]_i_3_n_0 ),
.I2(\Q[8]_i_4_n_0 ),
.I3(\Q[8]_i_5_n_0 ),
.I4(\Q_reg_n_0_[24] ),
.I5(\Q_reg_n_0_[25] ),
.O(\Q_reg[12]_0 [0]));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[8]_i_2
(.I0(\Q_reg_n_0_[17] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[8] ),
.I4(\Q_reg[22]_0 [6]),
.O(\Data_array_SWR[0] [8]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h0000AAEF))
\Q[8]_i_2__0
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg_n_0_[20] ),
.I2(\Q_reg_n_0_[19] ),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q_reg_n_0_[23] ),
.O(\Q[8]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFF0F0FFF4))
\Q[8]_i_3
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[14] ),
.I2(\Q_reg_n_0_[18] ),
.I3(\Q_reg_n_0_[16] ),
.I4(\Q_reg_n_0_[17] ),
.I5(\Q[8]_i_6__0_n_0 ),
.O(\Q[8]_i_3_n_0 ));
LUT5 #(
.INIT(32'hFEFEFFFE))
\Q[8]_i_4
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[17] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q_reg_n_0_[12] ),
.O(\Q[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'h5555555577775557))
\Q[8]_i_5
(.I0(\Q[8]_i_7__0_n_0 ),
.I1(\Q[8]_i_8__0_n_0 ),
.I2(\Q[8]_i_9__0_n_0 ),
.I3(\Q[8]_i_10__0_n_0 ),
.I4(\Q_reg_n_0_[7] ),
.I5(\Q[8]_i_11__0_n_0 ),
.O(\Q[8]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'hE))
\Q[8]_i_6__0
(.I0(\Q_reg_n_0_[20] ),
.I1(\Q_reg_n_0_[22] ),
.O(\Q[8]_i_6__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT4 #(
.INIT(16'hAEFF))
\Q[8]_i_7__0
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg_n_0_[11] ),
.I3(\Q_reg_n_0_[9] ),
.O(\Q[8]_i_7__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT2 #(
.INIT(4'h2))
\Q[8]_i_8__0
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg_n_0_[11] ),
.O(\Q[8]_i_8__0_n_0 ));
LUT3 #(
.INIT(8'hAE))
\Q[8]_i_9__0
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg_n_0_[4] ),
.I2(\Q_reg_n_0_[5] ),
.O(\Q[8]_i_9__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[9]_i_1
(.I0(\Data_array_SWR[0] [12]),
.I1(\Data_array_SWR[0] [11]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [10]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [9]),
.O(D[9]));
LUT6 #(
.INIT(64'h000000000000FFF8))
\Q[9]_i_1__2
(.I0(\Q[9]_i_2_n_0 ),
.I1(\Q[9]_i_3_n_0 ),
.I2(\Q_reg_n_0_[22] ),
.I3(\Q_reg_n_0_[23] ),
.I4(\Q_reg_n_0_[25] ),
.I5(\Q_reg_n_0_[24] ),
.O(\Q_reg[12]_0 [1]));
LUT6 #(
.INIT(64'h1110111011101111))
\Q[9]_i_2
(.I0(\Q_reg_n_0_[21] ),
.I1(\Q_reg_n_0_[20] ),
.I2(\Q_reg_n_0_[19] ),
.I3(\Q_reg_n_0_[18] ),
.I4(\Q_reg_n_0_[16] ),
.I5(\Q_reg_n_0_[17] ),
.O(\Q[9]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFB3BC808))
\Q[9]_i_2__0
(.I0(\Q_reg_n_0_[16] ),
.I1(\Q_reg[2]_0 [0]),
.I2(Q),
.I3(\Q_reg_n_0_[9] ),
.I4(\Q_reg[22]_0 [7]),
.O(\Data_array_SWR[0] [9]));
LUT6 #(
.INIT(64'hFFFFFFFFAAAAAABA))
\Q[9]_i_3
(.I0(\Q[9]_i_4_n_0 ),
.I1(\Q_reg_n_0_[12] ),
.I2(\Q[9]_i_5_n_0 ),
.I3(\Q[11]_i_5_n_0 ),
.I4(\Q_reg_n_0_[13] ),
.I5(\Q[9]_i_6_n_0 ),
.O(\Q[9]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT4 #(
.INIT(16'h0302))
\Q[9]_i_4
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg_n_0_[12] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q_reg_n_0_[10] ),
.O(\Q[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFAFAFAFAFAFAFFFE))
\Q[9]_i_5
(.I0(\Q_reg_n_0_[7] ),
.I1(\Q_reg_n_0_[3] ),
.I2(\Q_reg_n_0_[6] ),
.I3(\Q_reg_n_0_[2] ),
.I4(\Q_reg_n_0_[5] ),
.I5(\Q_reg_n_0_[4] ),
.O(\Q[9]_i_5_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\Q[9]_i_6
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[14] ),
.I2(\Q_reg_n_0_[19] ),
.I3(\Q_reg_n_0_[18] ),
.O(\Q[9]_i_6_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [0]),
.Q(\Q_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [13]),
.Q(\Q_reg_n_0_[13] ));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [14]),
.Q(\Q_reg_n_0_[14] ));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [15]),
.Q(\Q_reg_n_0_[15] ));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [16]),
.Q(\Q_reg_n_0_[16] ));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [17]),
.Q(\Q_reg_n_0_[17] ));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [18]),
.Q(\Q_reg_n_0_[18] ));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [19]),
.Q(\Q_reg_n_0_[19] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [20]),
.Q(\Q_reg_n_0_[20] ));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [21]),
.Q(\Q_reg_n_0_[21] ));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [22]),
.Q(\Q_reg_n_0_[22] ));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [23]),
.Q(\Q_reg_n_0_[23] ));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [24]),
.Q(\Q_reg_n_0_[24] ));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [25]),
.Q(\Q_reg_n_0_[25] ));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [2]),
.Q(\Q_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [4]),
.Q(\Q_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [5]),
.Q(\Q_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [6]),
.Q(\Q_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [9]),
.Q(\Q_reg_n_0_[9] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized19
(Q,
\Q_reg[2]_0 ,
\Q_reg[30] ,
CLK,
AR);
output [7:0]Q;
input [0:0]\Q_reg[2]_0 ;
input [7:0]\Q_reg[30] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [7:0]Q;
wire [0:0]\Q_reg[2]_0 ;
wire [7:0]\Q_reg[30] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [7]),
.Q(Q[7]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized2
(D,
Q,
\Q_reg[27]_0 ,
\Q_reg[6]_0 ,
\Q_reg[27]_1 ,
CLK,
AR);
output [2:0]D;
output [25:0]Q;
input [4:0]\Q_reg[27]_0 ;
input [0:0]\Q_reg[6]_0 ;
input [27:0]\Q_reg[27]_1 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [2:0]D;
wire [25:0]Q;
wire \Q[4]_i_2__0_n_0 ;
wire [4:0]\Q_reg[27]_0 ;
wire [27:0]\Q_reg[27]_1 ;
wire [0:0]\Q_reg[6]_0 ;
wire \Q_reg_n_0_[26] ;
wire \Q_reg_n_0_[27] ;
LUT4 #(
.INIT(16'h2DD2))
\Q[1]_i_1__5
(.I0(Q[23]),
.I1(\Q_reg[27]_0 [0]),
.I2(Q[24]),
.I3(\Q_reg[27]_0 [1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h69))
\Q[3]_i_1__3
(.I0(\Q[4]_i_2__0_n_0 ),
.I1(\Q_reg_n_0_[26] ),
.I2(\Q_reg[27]_0 [3]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h718E8E71))
\Q[4]_i_1__3
(.I0(\Q[4]_i_2__0_n_0 ),
.I1(\Q_reg[27]_0 [3]),
.I2(\Q_reg_n_0_[26] ),
.I3(\Q_reg_n_0_[27] ),
.I4(\Q_reg[27]_0 [4]),
.O(D[2]));
LUT6 #(
.INIT(64'hD4DD4444DDDDD4DD))
\Q[4]_i_2__0
(.I0(Q[25]),
.I1(\Q_reg[27]_0 [2]),
.I2(\Q_reg[27]_0 [0]),
.I3(Q[23]),
.I4(\Q_reg[27]_0 [1]),
.I5(Q[24]),
.O(\Q[4]_i_2__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [26]),
.Q(\Q_reg_n_0_[26] ));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [27]),
.Q(\Q_reg_n_0_[27] ));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized20
(D,
Q,
\Q_reg[2]_0 ,
\Q_reg[1]_0 ,
CLK,
AR);
output [0:0]D;
output [2:0]Q;
input [1:0]\Q_reg[2]_0 ;
input [2:0]\Q_reg[1]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [2:0]Q;
wire [2:0]\Q_reg[1]_0 ;
wire [1:0]\Q_reg[2]_0 ;
LUT2 #(
.INIT(4'h8))
\Q[0]_i_1
(.I0(Q[2]),
.I1(\Q_reg[2]_0 [0]),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized21
(Q,
\Q_reg[0]_0 ,
OVRFLW_FLAG_FRMT,
CLK,
AR,
UNDRFLW_FLAG_FRMT,
\Q_reg[0]_1 );
output [2:0]Q;
input [0:0]\Q_reg[0]_0 ;
input OVRFLW_FLAG_FRMT;
input CLK;
input [0:0]AR;
input UNDRFLW_FLAG_FRMT;
input [0:0]\Q_reg[0]_1 ;
wire [0:0]AR;
wire CLK;
wire OVRFLW_FLAG_FRMT;
wire [2:0]Q;
wire [0:0]\Q_reg[0]_0 ;
wire [0:0]\Q_reg[0]_1 ;
wire UNDRFLW_FLAG_FRMT;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(\Q_reg[0]_1 ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(UNDRFLW_FLAG_FRMT),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(OVRFLW_FLAG_FRMT),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized22
(ready_OBUF,
Q,
CLK,
AR);
output ready_OBUF;
input [0:0]Q;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]Q;
wire ready_OBUF;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(AR),
.D(Q),
.Q(ready_OBUF));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized3
(Q,
\Q_reg[6] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[6] ;
input [2:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[6] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized4
(Q,
\Q_reg[5]_0 ,
D,
CLK,
AR);
output [30:0]Q;
input [0:0]\Q_reg[5]_0 ;
input [30:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [30:0]D;
wire [30:0]Q;
wire [0:0]\Q_reg[5]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized5
(Q,
\Q_reg[5]_0 ,
D,
CLK,
AR);
output [22:0]Q;
input [0:0]\Q_reg[5]_0 ;
input [22:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [22:0]D;
wire [22:0]Q;
wire [0:0]\Q_reg[5]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized6
(Q,
\Q_reg[5] ,
D,
CLK,
AR);
output [4:0]Q;
input [0:0]\Q_reg[5] ;
input [4:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [4:0]D;
wire [4:0]Q;
wire [0:0]\Q_reg[5] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized7
(Q,
\Q_reg[5] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[5] ;
input [2:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[5] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized8
(Q,
\Q_reg[4]_0 ,
D,
CLK,
AR);
output [30:0]Q;
input [0:0]\Q_reg[4]_0 ;
input [30:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [30:0]D;
wire [30:0]Q;
wire [0:0]\Q_reg[4]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized9
(D,
\Q_reg[8]_0 ,
\Data_array_SWR[6] ,
\Q_reg[13]_0 ,
\Data_array_SWR[4] ,
Q,
\Q_reg[4]_0 ,
\Q_reg[4]_1 ,
E,
\Q_reg[0]_0 ,
CLK,
AR);
output [4:0]D;
output [11:0]\Q_reg[8]_0 ;
output [0:0]\Data_array_SWR[6] ;
output [7:0]\Q_reg[13]_0 ;
output [1:0]\Data_array_SWR[4] ;
input [1:0]Q;
input [2:0]\Q_reg[4]_0 ;
input [1:0]\Q_reg[4]_1 ;
input [0:0]E;
input [25:0]\Q_reg[0]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [4:0]D;
wire [17:0]\Data_array_SWR[3] ;
wire [1:0]\Data_array_SWR[4] ;
wire [13:0]\Data_array_SWR[5] ;
wire [0:0]\Data_array_SWR[6] ;
wire [0:0]E;
wire [1:0]Q;
wire [25:0]\Q_reg[0]_0 ;
wire [7:0]\Q_reg[13]_0 ;
wire [2:0]\Q_reg[4]_0 ;
wire [1:0]\Q_reg[4]_1 ;
wire [11:0]\Q_reg[8]_0 ;
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT5 #(
.INIT(32'hFF00B8B8))
\Q[0]_i_1__4
(.I0(\Q_reg[8]_0 [10]),
.I1(\Q_reg[4]_0 [2]),
.I2(\Data_array_SWR[5] [0]),
.I3(\Q_reg[4]_1 [1]),
.I4(Q[1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT5 #(
.INIT(32'hF0BBF088))
\Q[12]_i_1__0
(.I0(\Data_array_SWR[5] [13]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[4]_0 [2]),
.I4(\Data_array_SWR[5] [12]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT5 #(
.INIT(32'hF0BBF088))
\Q[13]_i_1__0
(.I0(\Data_array_SWR[5] [12]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[4]_0 [2]),
.I4(\Data_array_SWR[5] [13]),
.O(D[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_2__0
(.I0(\Q_reg[13]_0 [6]),
.I1(\Q_reg[13]_0 [2]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [16]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [12]),
.O(\Data_array_SWR[5] [12]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_3
(.I0(\Q_reg[13]_0 [7]),
.I1(\Q_reg[13]_0 [3]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [17]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [13]),
.O(\Data_array_SWR[5] [13]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[14]_i_4
(.I0(\Q_reg[13]_0 [5]),
.I1(\Q_reg[13]_0 [1]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [15]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [11]),
.O(\Q_reg[8]_0 [9]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_5
(.I0(\Q_reg[13]_0 [0]),
.I1(\Q_reg[4]_0 [0]),
.I2(\Data_array_SWR[3] [14]),
.O(\Data_array_SWR[4] [0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[15]_i_4
(.I0(\Q_reg[13]_0 [4]),
.I1(\Q_reg[13]_0 [0]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [14]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [10]),
.O(\Q_reg[8]_0 [8]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_5
(.I0(\Q_reg[13]_0 [1]),
.I1(\Q_reg[4]_0 [0]),
.I2(\Data_array_SWR[3] [15]),
.O(\Data_array_SWR[4] [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_3
(.I0(\Q_reg[13]_0 [3]),
.I1(\Data_array_SWR[3] [17]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [13]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [9]),
.O(\Q_reg[8]_0 [7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_3
(.I0(Q[0]),
.I1(\Q_reg[13]_0 [7]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Q_reg[13]_0 [3]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [17]),
.O(\Q_reg[8]_0 [11]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_4
(.I0(\Q_reg[13]_0 [2]),
.I1(\Data_array_SWR[3] [16]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [12]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [8]),
.O(\Q_reg[8]_0 [6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_4
(.I0(\Q_reg[13]_0 [1]),
.I1(\Data_array_SWR[3] [15]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [11]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [7]),
.O(\Q_reg[8]_0 [5]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_4
(.I0(\Q_reg[13]_0 [0]),
.I1(\Data_array_SWR[3] [14]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [10]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [6]),
.O(\Q_reg[8]_0 [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_5
(.I0(\Data_array_SWR[3] [17]),
.I1(\Data_array_SWR[3] [13]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [9]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [5]),
.O(\Q_reg[8]_0 [3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_5
(.I0(\Data_array_SWR[3] [16]),
.I1(\Data_array_SWR[3] [12]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [8]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [4]),
.O(\Q_reg[8]_0 [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_5
(.I0(\Data_array_SWR[3] [15]),
.I1(\Data_array_SWR[3] [11]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [7]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [3]),
.O(\Q_reg[8]_0 [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[23]_i_5
(.I0(\Data_array_SWR[3] [14]),
.I1(\Data_array_SWR[3] [10]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [6]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [2]),
.O(\Q_reg[8]_0 [0]));
LUT3 #(
.INIT(8'hB8))
\Q[24]_i_1__1
(.I0(\Data_array_SWR[6] ),
.I1(Q[1]),
.I2(\Q_reg[4]_1 [0]),
.O(D[3]));
LUT3 #(
.INIT(8'hB8))
\Q[24]_i_2__0
(.I0(\Q_reg[8]_0 [11]),
.I1(\Q_reg[4]_0 [2]),
.I2(\Data_array_SWR[5] [1]),
.O(\Data_array_SWR[6] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[24]_i_4
(.I0(\Data_array_SWR[3] [13]),
.I1(\Data_array_SWR[3] [9]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [5]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [1]),
.O(\Data_array_SWR[5] [1]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT5 #(
.INIT(32'hB8FFB800))
\Q[25]_i_1__2
(.I0(\Q_reg[8]_0 [10]),
.I1(\Q_reg[4]_0 [2]),
.I2(\Data_array_SWR[5] [0]),
.I3(Q[1]),
.I4(\Q_reg[4]_1 [1]),
.O(D[4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[25]_i_2__0
(.I0(Q[0]),
.I1(\Q_reg[13]_0 [6]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Q_reg[13]_0 [2]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [16]),
.O(\Q_reg[8]_0 [10]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[25]_i_3__0
(.I0(\Data_array_SWR[3] [12]),
.I1(\Data_array_SWR[3] [8]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [4]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [0]),
.O(\Data_array_SWR[5] [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [0]),
.Q(\Data_array_SWR[3] [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [10]),
.Q(\Data_array_SWR[3] [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [11]),
.Q(\Data_array_SWR[3] [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [12]),
.Q(\Data_array_SWR[3] [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [13]),
.Q(\Data_array_SWR[3] [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [14]),
.Q(\Data_array_SWR[3] [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [15]),
.Q(\Data_array_SWR[3] [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [16]),
.Q(\Data_array_SWR[3] [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [17]),
.Q(\Data_array_SWR[3] [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [18]),
.Q(\Q_reg[13]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [19]),
.Q(\Q_reg[13]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [1]),
.Q(\Data_array_SWR[3] [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [20]),
.Q(\Q_reg[13]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [21]),
.Q(\Q_reg[13]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [22]),
.Q(\Q_reg[13]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [23]),
.Q(\Q_reg[13]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [24]),
.Q(\Q_reg[13]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [25]),
.Q(\Q_reg[13]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [2]),
.Q(\Data_array_SWR[3] [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [3]),
.Q(\Data_array_SWR[3] [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [4]),
.Q(\Data_array_SWR[3] [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [5]),
.Q(\Data_array_SWR[3] [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [6]),
.Q(\Data_array_SWR[3] [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [7]),
.Q(\Data_array_SWR[3] [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [8]),
.Q(\Data_array_SWR[3] [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[0]_0 [9]),
.Q(\Data_array_SWR[3] [9]));
endmodule
module ShiftRegister
(E,
Q,
\Q_reg[1]_0 ,
\Q_reg[2]_0 ,
\Q_reg[2]_1 ,
\FSM_sequential_state_reg_reg[2] ,
D,
CLK,
AR);
output [0:0]E;
output [5:0]Q;
output [0:0]\Q_reg[1]_0 ;
output [0:0]\Q_reg[2]_0 ;
input [0:0]\Q_reg[2]_1 ;
input [0:0]\FSM_sequential_state_reg_reg[2] ;
input [0:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[2] ;
wire [5:0]Q;
wire [0:0]\Q_reg[1]_0 ;
wire [0:0]\Q_reg[2]_0 ;
wire [0:0]\Q_reg[2]_1 ;
wire \Q_reg_n_0_[3] ;
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT2 #(
.INIT(4'h2))
\Q[1]_i_1__0
(.I0(Q[1]),
.I1(\Q_reg[2]_1 ),
.O(\Q_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT2 #(
.INIT(4'hE))
\Q[25]_i_1
(.I0(Q[1]),
.I1(Q[3]),
.O(E));
LUT2 #(
.INIT(4'h2))
\Q[2]_i_1__6
(.I0(\Q_reg_n_0_[3] ),
.I1(Q[0]),
.O(\Q_reg[2]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(Q[1]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(Q[2]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(\Q_reg_n_0_[3] ),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(Q[3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(Q[4]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(Q[5]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(D),
.Q(Q[5]));
endmodule
module sgn_result
(D,
\Q_reg[30] ,
Q,
intAS,
CO,
\Q_reg[31] );
output [0:0]D;
input [0:0]\Q_reg[30] ;
input [0:0]Q;
input intAS;
input [0:0]CO;
input [0:0]\Q_reg[31] ;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]Q;
wire [0:0]\Q_reg[30] ;
wire [0:0]\Q_reg[31] ;
wire intAS;
LUT5 #(
.INIT(32'hFF3C0014))
sgn_result_o
(.I0(\Q_reg[30] ),
.I1(Q),
.I2(intAS),
.I3(CO),
.I4(\Q_reg[31] ),
.O(D));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222O_TB_V
`define SKY130_FD_SC_LS__A222O_TB_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a222o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
C2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 C2 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A1 = 1'b1;
#240 A2 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 C1 = 1'b1;
#320 C2 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A1 = 1'b0;
#440 A2 = 1'b0;
#460 B1 = 1'b0;
#480 B2 = 1'b0;
#500 C1 = 1'b0;
#520 C2 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 C2 = 1'b1;
#720 C1 = 1'b1;
#740 B2 = 1'b1;
#760 B1 = 1'b1;
#780 A2 = 1'b1;
#800 A1 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 C2 = 1'bx;
#920 C1 = 1'bx;
#940 B2 = 1'bx;
#960 B1 = 1'bx;
#980 A2 = 1'bx;
#1000 A1 = 1'bx;
end
sky130_fd_sc_ls__a222o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222O_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__EDFXTP_PP_BLACKBOX_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__edfxtp (
Q ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXTP_PP_BLACKBOX_V
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// valid O 1
// word_fst O 64
// word_snd O 5
// verbosity I 4
// CLK I 1 clock
// RST_N I 1 reset
// req_opcode I 7
// req_f7 I 7
// req_rm I 3
// req_rs2 I 5
// req_v1 I 64
// req_v2 I 64
// req_v3 I 64
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFBox_Top(verbosity,
CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_opcode,
req_f7,
req_rm,
req_rs2,
req_v1,
req_v2,
req_v3,
EN_req,
valid,
word_fst,
word_snd);
input [3 : 0] verbosity;
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [6 : 0] req_opcode;
input [6 : 0] req_f7;
input [2 : 0] req_rm;
input [4 : 0] req_rs2;
input [63 : 0] req_v1;
input [63 : 0] req_v2;
input [63 : 0] req_v3;
input EN_req;
// value method valid
output valid;
// value method word_fst
output [63 : 0] word_fst;
// value method word_snd
output [4 : 0] word_snd;
// signals for module outputs
wire [63 : 0] word_fst;
wire [4 : 0] word_snd;
wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid;
// ports of submodule fbox_core
wire [63 : 0] fbox_core$req_v1,
fbox_core$req_v2,
fbox_core$req_v3,
fbox_core$word_fst;
wire [6 : 0] fbox_core$req_f7, fbox_core$req_opcode;
wire [4 : 0] fbox_core$req_rs2, fbox_core$word_snd;
wire [2 : 0] fbox_core$req_rm;
wire fbox_core$EN_req,
fbox_core$EN_server_reset_request_put,
fbox_core$EN_server_reset_response_get,
fbox_core$RDY_server_reset_request_put,
fbox_core$RDY_server_reset_response_get,
fbox_core$valid;
// rule scheduling signals
wire CAN_FIRE_req,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
WILL_FIRE_req,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get;
// action method server_reset_request_put
assign RDY_server_reset_request_put =
fbox_core$RDY_server_reset_request_put ;
assign CAN_FIRE_server_reset_request_put =
fbox_core$RDY_server_reset_request_put ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
fbox_core$RDY_server_reset_response_get ;
assign CAN_FIRE_server_reset_response_get =
fbox_core$RDY_server_reset_response_get ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = fbox_core$valid ;
// value method word_fst
assign word_fst = fbox_core$word_fst ;
// value method word_snd
assign word_snd = fbox_core$word_snd ;
// submodule fbox_core
mkFBox_Core fbox_core(.verbosity(verbosity),
.CLK(CLK),
.RST_N(RST_N),
.req_f7(fbox_core$req_f7),
.req_opcode(fbox_core$req_opcode),
.req_rm(fbox_core$req_rm),
.req_rs2(fbox_core$req_rs2),
.req_v1(fbox_core$req_v1),
.req_v2(fbox_core$req_v2),
.req_v3(fbox_core$req_v3),
.EN_server_reset_request_put(fbox_core$EN_server_reset_request_put),
.EN_server_reset_response_get(fbox_core$EN_server_reset_response_get),
.EN_req(fbox_core$EN_req),
.RDY_server_reset_request_put(fbox_core$RDY_server_reset_request_put),
.RDY_server_reset_response_get(fbox_core$RDY_server_reset_response_get),
.valid(fbox_core$valid),
.word_fst(fbox_core$word_fst),
.word_snd(fbox_core$word_snd));
// submodule fbox_core
assign fbox_core$req_f7 = req_f7 ;
assign fbox_core$req_opcode = req_opcode ;
assign fbox_core$req_rm = req_rm ;
assign fbox_core$req_rs2 = req_rs2 ;
assign fbox_core$req_v1 = req_v1 ;
assign fbox_core$req_v2 = req_v2 ;
assign fbox_core$req_v3 = req_v3 ;
assign fbox_core$EN_server_reset_request_put = EN_server_reset_request_put ;
assign fbox_core$EN_server_reset_response_get =
EN_server_reset_response_get ;
assign fbox_core$EN_req = EN_req ;
endmodule // mkFBox_Top
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
module \$__ECP5_DP16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 18;
parameter CFG_ENABLE_A = 2;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'bx;
parameter TRANSP2 = 0;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input [CFG_ENABLE_A-1:0] A1EN;
input [CFG_ABITS-1:0] B1ADDR;
output [CFG_DBITS-1:0] B1DATA;
input B1EN;
localparam CLKAMUX = CLKPOL2 ? "CLKA" : "INV";
localparam CLKBMUX = CLKPOL3 ? "CLKB" : "INV";
localparam WRITEMODE_A = TRANSP2 ? "WRITETHROUGH" : "READBEFOREWRITE";
generate if (CFG_DBITS == 1) begin
DP16KD #(
`include "bram_init_1_2_4.vh"
.DATA_WIDTH_A(1),
.DATA_WIDTH_B(1),
.CLKAMUX(CLKAMUX),
.CLKBMUX(CLKBMUX),
.WRITEMODE_A(WRITEMODE_A),
.WRITEMODE_B("READBEFOREWRITE"),
.GSR("AUTO")
) _TECHMAP_REPLACE_ (
`include "bram_conn_1.vh"
.CLKA(CLK2), .CLKB(CLK3),
.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
.RSTA(1'b0), .RSTB(1'b0)
);
end else if (CFG_DBITS == 2) begin
DP16KD #(
`include "bram_init_1_2_4.vh"
.DATA_WIDTH_A(2),
.DATA_WIDTH_B(2),
.CLKAMUX(CLKAMUX),
.CLKBMUX(CLKBMUX),
.WRITEMODE_A(WRITEMODE_A),
.WRITEMODE_B("READBEFOREWRITE"),
.GSR("AUTO")
) _TECHMAP_REPLACE_ (
`include "bram_conn_2.vh"
.CLKA(CLK2), .CLKB(CLK3),
.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
.RSTA(1'b0), .RSTB(1'b0)
);
end else if (CFG_DBITS <= 4) begin
DP16KD #(
`include "bram_init_1_2_4.vh"
.DATA_WIDTH_A(4),
.DATA_WIDTH_B(4),
.CLKAMUX(CLKAMUX),
.CLKBMUX(CLKBMUX),
.WRITEMODE_A(WRITEMODE_A),
.WRITEMODE_B("READBEFOREWRITE"),
.GSR("AUTO")
) _TECHMAP_REPLACE_ (
`include "bram_conn_4.vh"
.CLKA(CLK2), .CLKB(CLK3),
.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
.RSTA(1'b0), .RSTB(1'b0)
);
end else if (CFG_DBITS <= 9) begin
DP16KD #(
`include "bram_init_9_18_36.vh"
.DATA_WIDTH_A(9),
.DATA_WIDTH_B(9),
.CLKAMUX(CLKAMUX),
.CLKBMUX(CLKBMUX),
.WRITEMODE_A(WRITEMODE_A),
.WRITEMODE_B("READBEFOREWRITE"),
.GSR("AUTO")
) _TECHMAP_REPLACE_ (
`include "bram_conn_9.vh"
.CLKA(CLK2), .CLKB(CLK3),
.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
.RSTA(1'b0), .RSTB(1'b0)
);
end else if (CFG_DBITS <= 18) begin
DP16KD #(
`include "bram_init_9_18_36.vh"
.DATA_WIDTH_A(18),
.DATA_WIDTH_B(18),
.CLKAMUX(CLKAMUX),
.CLKBMUX(CLKBMUX),
.WRITEMODE_A(WRITEMODE_A),
.WRITEMODE_B("READBEFOREWRITE"),
.GSR("AUTO")
) _TECHMAP_REPLACE_ (
`include "bram_conn_18.vh"
.CLKA(CLK2), .CLKB(CLK3),
.WEA(|A1EN), .CEA(1'b1), .OCEA(1'b1),
.WEB(1'b0), .CEB(B1EN), .OCEB(1'b1),
.RSTA(1'b0), .RSTB(1'b0)
);
end else begin
wire TECHMAP_FAIL = 1'b1;
end endgenerate
endmodule
module \$__ECP5_PDPW16KD (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_A = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input [CFG_ENABLE_A-1:0] A1EN;
input [CFG_ABITS-1:0] B1ADDR;
output [CFG_DBITS-1:0] B1DATA;
input B1EN;
localparam CLKWMUX = CLKPOL2 ? "CLKA" : "INV";
localparam CLKRMUX = CLKPOL3 ? "CLKB" : "INV";
PDPW16KD #(
`include "bram_init_9_18_36.vh"
.DATA_WIDTH_W(36),
.DATA_WIDTH_R(36),
.CLKWMUX(CLKWMUX),
.CLKRMUX(CLKRMUX),
.GSR("AUTO")
) _TECHMAP_REPLACE_ (
`include "bram_conn_36.vh"
.CLKW(CLK2), .CLKR(CLK3),
.CEW(1'b1),
.CER(B1EN), .OCER(1'b1),
.RST(1'b0)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 29.11.2016 16:55:54
// Design Name:
// Module Name: frequency_analyzer_testbench
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module frequency_analyzer_testbench #
(
parameter FREQUENCY0 = 9000,
parameter FREQUENCY1 = 11000,
parameter FREQUENCY0_DEVIATION = 20,
parameter FREQUENCY1_DEVIATION = 20,
parameter CLOCK_FREQUENCY = 50000000
)
(
input wire sample_data,
input wire clock,
input wire enable,
input wire clear,
output wire[31:0] f0_value,
output wire[31:0] f1_value
);
frequency_analyzer #(.FREQUENCY0(FREQUENCY0), .FREQUENCY1(FREQUENCY1),
.FREQUENCY0_DEVIATION(FREQUENCY0_DEVIATION),
.FREQUENCY1_DEVIATION(FREQUENCY1_DEVIATION),
.CLOCK_FREQUENCYK(CLOCK_FREQUENCY))
frequency_analyzer_test (.sample_data(sample_data), .clock(clock), .enable(enable),
.clear(clear), .f0_value(f0_value), .f1_value(f1_value));
endmodule |
module top(
input PACKAGEPIN,
output [1:0] PLLOUTCORE,
output [1:0] PLLOUTGLOBAL,
input EXTFEEDBACK,
input [7:0] DYNAMICDELAY,
output LOCK,
input BYPASS,
input RESETB,
input LATCHINPUTVALUE,
//Test Pins
output SDO,
input SDI,
input SCLK
);
SB_PLL40_2_PAD #(
.FEEDBACK_PATH("DELAY"),
// .FEEDBACK_PATH("SIMPLE"),
// .FEEDBACK_PATH("PHASE_AND_DELAY"),
// .FEEDBACK_PATH("EXTERNAL"),
.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
// .DELAY_ADJUSTMENT_MODE_FEEDBACK("DYNAMIC"),
.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
// .DELAY_ADJUSTMENT_MODE_RELATIVE("DYNAMIC"),
.PLLOUT_SELECT_PORTB("GENCLK"),
// .PLLOUT_SELECT_PORTB("GENCLK_HALF"),
// .PLLOUT_SELECT_PORTB("SHIFTREG_90deg"),
// .PLLOUT_SELECT_PORTB("SHIFTREG_0deg"),
.SHIFTREG_DIV_MODE(1'b0),
.FDA_FEEDBACK(4'b1111),
.FDA_RELATIVE(4'b1111),
.DIVR(4'b0000),
.DIVF(7'b0000000),
.DIVQ(3'b001),
.FILTER_RANGE(3'b000),
.ENABLE_ICEGATE_PORTA(1'b0),
.ENABLE_ICEGATE_PORTB(1'b0),
.TEST_MODE(1'b0)
) uut (
.PACKAGEPIN (PACKAGEPIN ),
.PLLOUTCOREA (PLLOUTCORE [0]),
.PLLOUTGLOBALA (PLLOUTGLOBAL[0]),
.PLLOUTCOREB (PLLOUTCORE [1]),
.PLLOUTGLOBALB (PLLOUTGLOBAL[1]),
.EXTFEEDBACK (EXTFEEDBACK ),
.DYNAMICDELAY (DYNAMICDELAY ),
.LOCK (LOCK ),
.BYPASS (BYPASS ),
.RESETB (RESETB ),
.LATCHINPUTVALUE(LATCHINPUTVALUE),
.SDO (SDO ),
.SDI (SDI ),
.SCLK (SCLK )
);
endmodule
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_chipscope.v
// /___/ /\ Date Last Modified: $Data$
// \ \ / \ Date Created: 9/14/06
// \___\/\___\
//
//Device: Virtex-5
//Purpose:
// Skeleton Chipscope module declarations - for simulation only
//Reference:
//Revision History:
//
//*****************************************************************************
`timescale 1ns/1ps
module icon4
(
control0,
control1,
control2,
control3
)
/* synthesis syn_black_box syn_noprune = 1 */;
output [35:0] control0;
output [35:0] control1;
output [35:0] control2;
output [35:0] control3;
endmodule
module vio_async_in192
(
control,
async_in
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input [191:0] async_in;
endmodule
module vio_async_in96
(
control,
async_in
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input [95:0] async_in;
endmodule
module vio_async_in100
(
control,
async_in
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input [99:0] async_in;
endmodule
module vio_sync_out32
(
control,
clk,
sync_out
)
/* synthesis syn_black_box syn_noprune = 1 */;
input [35:0] control;
input clk;
output [31:0] sync_out;
endmodule |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's definitions ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// Defines for the OR1200 core ////
//// ////
//// To Do: ////
//// - add parameters that are missing ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_defines.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Defines added, bugs fixed.
//
// Dump VCD
//
//`define OR1200_VCD_DUMP
//
// Generate debug messages during simulation
//
//`define OR1200_VERBOSE
// `define OR1200_ASIC
////////////////////////////////////////////////////////
//
// Typical configuration for an ASIC
//
`ifdef OR1200_ASIC
//
// Target ASIC memories
//
//`define OR1200_ARTISAN_SSP
//`define OR1200_ARTISAN_SDP
//`define OR1200_ARTISAN_STP
`define OR1200_VIRTUALSILICON_SSP
//`define OR1200_VIRTUALSILICON_STP_T1
//`define OR1200_VIRTUALSILICON_STP_T2
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
//
// Do not implement Data MMU
//
//`define OR1200_NO_DMMU
//
// Do not implement Insn MMU
//
//`define OR1200_NO_IMMU
//
// Select between ASIC optimized and generic multiplier
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
//
// Size/type of insn/data cache if implemented
//
// `define OR1200_IC_1W_512B
// `define OR1200_IC_1W_4KB
`define OR1200_IC_1W_8KB
// `define OR1200_DC_1W_4KB
`define OR1200_DC_1W_8KB
`else
/////////////////////////////////////////////////////////
//
// Typical configuration for an FPGA
//
//
// Target FPGA memories
//
`define OR1200_ALTERA_LPM
//`define OR1200_XILINX_RAMB16
//`define OR1200_XILINX_RAMB4
//`define OR1200_XILINX_RAM32X1D
//`define OR1200_USE_RAM16X1D_FOR_RAM32X1D
// Generic models should infer RAM blocks at synthesis time (not only effects
// single port ram.)
//`define OR1200_GENERIC
//
// Do not implement Data cache
//
//`define OR1200_NO_DC
//
// Do not implement Insn cache
//
//`define OR1200_NO_IC
//
// Do not implement Data MMU
//
//`define OR1200_NO_DMMU
//
// Do not implement Insn MMU
//
//`define OR1200_NO_IMMU
//
// Select between ASIC and generic multiplier
//
// (Generic seems to trigger a bug in the Cadence Ncsim simulator)
//
//`define OR1200_ASIC_MULTP2_32X32
`define OR1200_GENERIC_MULTP2_32X32
//
// Size/type of insn/data cache if implemented
// (consider available FPGA memory resources)
//
//`define OR1200_IC_1W_512B
`define OR1200_IC_1W_4KB
//`define OR1200_IC_1W_8KB
//`define OR1200_IC_1W_16KB
//`define OR1200_IC_1W_32KB
`define OR1200_DC_1W_4KB
//`define OR1200_DC_1W_8KB
//`define OR1200_DC_1W_16KB
//`define OR1200_DC_1W_32KB
`endif
//////////////////////////////////////////////////////////
//
// Do not change below unless you know what you are doing
//
//
// Reset active low
//
//`define OR1200_RST_ACT_LOW
//
// Enable RAM BIST
//
// At the moment this only works for Virtual Silicon
// single port RAMs. For other RAMs it has not effect.
// Special wrapper for VS RAMs needs to be provided
// with scan flops to facilitate bist scan.
//
//`define OR1200_BIST
//
// Register OR1200 WISHBONE outputs
// (must be defined/enabled)
//
`define OR1200_REGISTERED_OUTPUTS
//
// Register OR1200 WISHBONE inputs
//
// (must be undefined/disabled)
//
//`define OR1200_REGISTERED_INPUTS
//
// Disable bursts if they are not supported by the
// memory subsystem (only affect cache line fill)
//
//`define OR1200_NO_BURSTS
//
//
// WISHBONE retry counter range
//
// 2^value range for retry counter. Retry counter
// is activated whenever *wb_rty_i is asserted and
// until retry counter expires, corresponding
// WISHBONE interface is deactivated.
//
// To disable retry counters and *wb_rty_i all together,
// undefine this macro.
//
//`define OR1200_WB_RETRY 7
//
// WISHBONE Consecutive Address Burst
//
// This was used prior to WISHBONE B3 specification
// to identify bursts. It is no longer needed but
// remains enabled for compatibility with old designs.
//
// To remove *wb_cab_o ports undefine this macro.
//
//`define OR1200_WB_CAB
//
// WISHBONE B3 compatible interface
//
// This follows the WISHBONE B3 specification.
// It is not enabled by default because most
// designs still don't use WB b3.
//
// To enable *wb_cti_o/*wb_bte_o ports,
// define this macro.
//
`define OR1200_WB_B3
//
// LOG all WISHBONE accesses
//
`define OR1200_LOG_WB_ACCESS
//
// Enable additional synthesis directives if using
// _Synopsys_ synthesis tool
//
//`define OR1200_ADDITIONAL_SYNOPSYS_DIRECTIVES
//
// Enables default statement in some case blocks
// and disables Synopsys synthesis directive full_case
//
// By default it is enabled. When disabled it
// can increase clock frequency.
//
`define OR1200_CASE_DEFAULT
//
// Operand width / register file address width
//
// (DO NOT CHANGE)
//
`define OR1200_OPERAND_WIDTH 32
`define OR1200_REGFILE_ADDR_WIDTH 5
//
// l.add/l.addi/l.and and optional l.addc/l.addic
// also set (compare) flag when result of their
// operation equals zero
//
// At the time of writing this, default or32
// C/C++ compiler doesn't generate code that
// would benefit from this optimization.
//
// By default this optimization is disabled to
// save area.
//
//`define OR1200_ADDITIONAL_FLAG_MODIFIERS
//
// Implement l.addc/l.addic instructions
//
// By default implementation of l.addc/l.addic
// instructions is enabled in case you need them.
// If you don't use them, then disable implementation
// to save area.
//
//`define OR1200_IMPL_ADDC
//
// Implement l.sub instruction
//
// By default implementation of l.sub instructions
// is enabled to be compliant with the simulator.
// If you don't use carry bit, then disable
// implementation to save area.
//
`define OR1200_IMPL_SUB
//
// Implement carry bit SR[CY]
//
//
// By default implementation of SR[CY] is enabled
// to be compliant with the simulator. However SR[CY]
// is explicitly only used by l.addc/l.addic/l.sub
// instructions and if these three insns are not
// implemented there is not much point having SR[CY].
//
//`define OR1200_IMPL_CY
//
// Implement carry bit SR[OV]
//
// Compiler doesn't use this, but other code may like
// to.
//
//`define OR1200_IMPL_OV
//
// Implement carry bit SR[OVE]
//
// Overflow interrupt indicator. When enabled, SR[OV] flag
// does not remain asserted after exception.
//
//`define OR1200_IMPL_OVE
//
// Implement rotate in the ALU
//
// At the time of writing this, or32
// C/C++ compiler doesn't generate rotate
// instructions. However or32 assembler
// can assemble code that uses rotate insn.
// This means that rotate instructions
// must be used manually inserted.
//
// By default implementation of rotate
// is disabled to save area and increase
// clock frequency.
//
//`define OR1200_IMPL_ALU_ROTATE
//
// Type of ALU compare to implement
//
// Try either one to find what yields
// higher clock frequencyin your case.
//
//`define OR1200_IMPL_ALU_COMP1
`define OR1200_IMPL_ALU_COMP2
//`define OR1200_IMPL_ALU_COMP3
//
// Implement Find First/Last '1'
//
`define OR1200_IMPL_ALU_FFL1
//
// Implement l.cust5 ALU instruction
//
//`define OR1200_IMPL_ALU_CUST5
//
// Implement l.extXs and l.extXz instructions
//
//`define OR1200_IMPL_ALU_EXT
//
// Implement multiplier
//
// By default multiplier is implemented
//
`define OR1200_MULT_IMPLEMENTED
//
// Implement multiply-and-accumulate
//
// By default MAC is implemented. To
// implement MAC, multiplier (non-serial) needs to be
// implemented.
//
//`define OR1200_MAC_IMPLEMENTED
//
// Implement optional l.div/l.divu instructions
//
// By default divide instructions are not implemented
// to save area.
//
//
`define OR1200_DIV_IMPLEMENTED
//
// Serial multiplier.
//
`define OR1200_MULT_SERIAL
//
// Serial divider.
// Uncomment to use a serial divider, otherwise will
// be a generic parallel implementation.
//
`define OR1200_DIV_SERIAL
//
// Implement HW Single Precision FPU
//
//`define OR1200_FPU_IMPLEMENTED
//
// Clock ratio RISC clock versus WB clock
//
// If you plan to run WB:RISC clock fixed to 1:1, disable
// both defines
//
// For WB:RISC 1:2 or 1:1, enable OR1200_CLKDIV_2_SUPPORTED
// and use clmode to set ratio
//
// For WB:RISC 1:4, 1:2 or 1:1, enable both defines and use
// clmode to set ratio
//
//`define OR1200_CLKDIV_2_SUPPORTED
//`define OR1200_CLKDIV_4_SUPPORTED
//
// Type of register file RAM
//
// Memory macro w/ two ports (see or1200_tpram_32x32.v)
//`define OR1200_RFRAM_TWOPORT
//
// Memory macro dual port (see or1200_dpram.v)
`define OR1200_RFRAM_DUALPORT
//
// Generic (flip-flop based) register file (see or1200_rfram_generic.v)
//`define OR1200_RFRAM_GENERIC
// Generic register file supports - 16 registers
`ifdef OR1200_RFRAM_GENERIC
// `define OR1200_RFRAM_16REG
`endif
//
// Type of mem2reg aligner to implement.
//
// Once OR1200_IMPL_MEM2REG2 yielded faster
// circuit, however with today tools it will
// most probably give you slower circuit.
//
`define OR1200_IMPL_MEM2REG1
//`define OR1200_IMPL_MEM2REG2
//
// Reset value and event
//
`ifdef OR1200_RST_ACT_LOW
`define OR1200_RST_VALUE (1'b0)
`define OR1200_RST_EVENT negedge
`else
`define OR1200_RST_VALUE (1'b1)
`define OR1200_RST_EVENT posedge
`endif
//
// ALUOPs
//
`define OR1200_ALUOP_WIDTH 5
`define OR1200_ALUOP_NOP 5'b0_0100
/* LS-nibble encodings correspond to bits [3:0] of instruction */
`define OR1200_ALUOP_ADD 5'b0_0000 // 0
`define OR1200_ALUOP_ADDC 5'b0_0001 // 1
`define OR1200_ALUOP_SUB 5'b0_0010 // 2
`define OR1200_ALUOP_AND 5'b0_0011 // 3
`define OR1200_ALUOP_OR 5'b0_0100 // 4
`define OR1200_ALUOP_XOR 5'b0_0101 // 5
`define OR1200_ALUOP_MUL 5'b0_0110 // 6
`define OR1200_ALUOP_RESERVED 5'b0_0111 // 7
`define OR1200_ALUOP_SHROT 5'b0_1000 // 8
`define OR1200_ALUOP_DIV 5'b0_1001 // 9
`define OR1200_ALUOP_DIVU 5'b0_1010 // a
`define OR1200_ALUOP_MULU 5'b0_1011 // b
`define OR1200_ALUOP_EXTHB 5'b0_1100 // c
`define OR1200_ALUOP_EXTW 5'b0_1101 // d
`define OR1200_ALUOP_CMOV 5'b0_1110 // e
`define OR1200_ALUOP_FFL1 5'b0_1111 // f
/* Values sent to ALU from decode unit - not defined by ISA */
`define OR1200_ALUOP_COMP 5'b1_0000 // Comparison
`define OR1200_ALUOP_MOVHI 5'b1_0001 // Move-high
`define OR1200_ALUOP_CUST5 5'b1_0010 // l.cust5
// ALU instructions second opcode field
`define OR1200_ALUOP2_POS 9:6
`define OR1200_ALUOP2_WIDTH 4
//
// MACOPs
//
`define OR1200_MACOP_WIDTH 3
`define OR1200_MACOP_NOP 3'b000
`define OR1200_MACOP_MAC 3'b001
`define OR1200_MACOP_MSB 3'b010
//
// Shift/rotate ops
//
`define OR1200_SHROTOP_WIDTH 4
`define OR1200_SHROTOP_NOP 4'd0
`define OR1200_SHROTOP_SLL 4'd0
`define OR1200_SHROTOP_SRL 4'd1
`define OR1200_SHROTOP_SRA 4'd2
`define OR1200_SHROTOP_ROR 4'd3
//
// Zero/Sign Extend ops
//
`define OR1200_EXTHBOP_WIDTH 4
`define OR1200_EXTHBOP_BS 4'h1
`define OR1200_EXTHBOP_HS 4'h0
`define OR1200_EXTHBOP_BZ 4'h3
`define OR1200_EXTHBOP_HZ 4'h2
`define OR1200_EXTWOP_WIDTH 4
`define OR1200_EXTWOP_WS 4'h0
`define OR1200_EXTWOP_WZ 4'h1
// Execution cycles per instruction
`define OR1200_MULTICYCLE_WIDTH 3
`define OR1200_ONE_CYCLE 3'd0
`define OR1200_TWO_CYCLES 3'd1
// Execution control which will "wait on" a module to finish
`define OR1200_WAIT_ON_WIDTH 2
`define OR1200_WAIT_ON_NOTHING `OR1200_WAIT_ON_WIDTH'd0
`define OR1200_WAIT_ON_MULTMAC `OR1200_WAIT_ON_WIDTH'd1
`define OR1200_WAIT_ON_FPU `OR1200_WAIT_ON_WIDTH'd2
`define OR1200_WAIT_ON_MTSPR `OR1200_WAIT_ON_WIDTH'd3
// Operand MUX selects
`define OR1200_SEL_WIDTH 2
`define OR1200_SEL_RF 2'd0
`define OR1200_SEL_IMM 2'd1
`define OR1200_SEL_EX_FORW 2'd2
`define OR1200_SEL_WB_FORW 2'd3
//
// BRANCHOPs
//
`define OR1200_BRANCHOP_WIDTH 3
`define OR1200_BRANCHOP_NOP 3'd0
`define OR1200_BRANCHOP_J 3'd1
`define OR1200_BRANCHOP_JR 3'd2
`define OR1200_BRANCHOP_BAL 3'd3
`define OR1200_BRANCHOP_BF 3'd4
`define OR1200_BRANCHOP_BNF 3'd5
`define OR1200_BRANCHOP_RFE 3'd6
//
// LSUOPs
//
// Bit 0: sign extend
// Bits 1-2: 00 doubleword, 01 byte, 10 halfword, 11 singleword
// Bit 3: 0 load, 1 store
`define OR1200_LSUOP_WIDTH 4
`define OR1200_LSUOP_NOP 4'b0000
`define OR1200_LSUOP_LBZ 4'b0010
`define OR1200_LSUOP_LBS 4'b0011
`define OR1200_LSUOP_LHZ 4'b0100
`define OR1200_LSUOP_LHS 4'b0101
`define OR1200_LSUOP_LWZ 4'b0110
`define OR1200_LSUOP_LWS 4'b0111
`define OR1200_LSUOP_LD 4'b0001
`define OR1200_LSUOP_SD 4'b1000
`define OR1200_LSUOP_SB 4'b1010
`define OR1200_LSUOP_SH 4'b1100
`define OR1200_LSUOP_SW 4'b1110
// Number of bits of load/store EA precalculated in ID stage
// for balancing ID and EX stages.
//
// Valid range: 2,3,...,30,31
`define OR1200_LSUEA_PRECALC 2
// FETCHOPs
`define OR1200_FETCHOP_WIDTH 1
`define OR1200_FETCHOP_NOP 1'b0
`define OR1200_FETCHOP_LW 1'b1
//
// Register File Write-Back OPs
//
// Bit 0: register file write enable
// Bits 3-1: write-back mux selects
//
`define OR1200_RFWBOP_WIDTH 4
`define OR1200_RFWBOP_NOP 4'b0000
`define OR1200_RFWBOP_ALU 3'b000
`define OR1200_RFWBOP_LSU 3'b001
`define OR1200_RFWBOP_SPRS 3'b010
`define OR1200_RFWBOP_LR 3'b011
`define OR1200_RFWBOP_FPU 3'b100
// Compare instructions
`define OR1200_COP_SFEQ 3'b000
`define OR1200_COP_SFNE 3'b001
`define OR1200_COP_SFGT 3'b010
`define OR1200_COP_SFGE 3'b011
`define OR1200_COP_SFLT 3'b100
`define OR1200_COP_SFLE 3'b101
`define OR1200_COP_X 3'b111
`define OR1200_SIGNED_COMPARE 'd3
`define OR1200_COMPOP_WIDTH 4
//
// FP OPs
//
// MSbit indicates FPU operation valid
//
`define OR1200_FPUOP_WIDTH 8
// FPU unit from Usselman takes 5 cycles from decode, so 4 ex. cycles
`define OR1200_FPUOP_CYCLES 3'd4
// FP instruction is double precision if bit 4 is set. We're a 32-bit
// implementation thus do not support double precision FP
`define OR1200_FPUOP_DOUBLE_BIT 4
`define OR1200_FPUOP_ADD 8'b0000_0000
`define OR1200_FPUOP_SUB 8'b0000_0001
`define OR1200_FPUOP_MUL 8'b0000_0010
`define OR1200_FPUOP_DIV 8'b0000_0011
`define OR1200_FPUOP_ITOF 8'b0000_0100
`define OR1200_FPUOP_FTOI 8'b0000_0101
`define OR1200_FPUOP_REM 8'b0000_0110
`define OR1200_FPUOP_RESERVED 8'b0000_0111
// FP Compare instructions
`define OR1200_FPCOP_SFEQ 8'b0000_1000
`define OR1200_FPCOP_SFNE 8'b0000_1001
`define OR1200_FPCOP_SFGT 8'b0000_1010
`define OR1200_FPCOP_SFGE 8'b0000_1011
`define OR1200_FPCOP_SFLT 8'b0000_1100
`define OR1200_FPCOP_SFLE 8'b0000_1101
//
// TAGs for instruction bus
//
`define OR1200_ITAG_IDLE 4'h0 // idle bus
`define OR1200_ITAG_NI 4'h1 // normal insn
`define OR1200_ITAG_BE 4'hb // Bus error exception
`define OR1200_ITAG_PE 4'hc // Page fault exception
`define OR1200_ITAG_TE 4'hd // TLB miss exception
//
// TAGs for data bus
//
`define OR1200_DTAG_IDLE 4'h0 // idle bus
`define OR1200_DTAG_ND 4'h1 // normal data
`define OR1200_DTAG_AE 4'ha // Alignment exception
`define OR1200_DTAG_BE 4'hb // Bus error exception
`define OR1200_DTAG_PE 4'hc // Page fault exception
`define OR1200_DTAG_TE 4'hd // TLB miss exception
//////////////////////////////////////////////
//
// ORBIS32 ISA specifics
//
// SHROT_OP position in machine word
`define OR1200_SHROTOP_POS 7:6
//
// Instruction opcode groups (basic)
//
`define OR1200_OR32_J 6'b000000
`define OR1200_OR32_JAL 6'b000001
`define OR1200_OR32_BNF 6'b000011
`define OR1200_OR32_BF 6'b000100
`define OR1200_OR32_NOP 6'b000101
`define OR1200_OR32_MOVHI 6'b000110
`define OR1200_OR32_MACRC 6'b000110
`define OR1200_OR32_XSYNC 6'b001000
`define OR1200_OR32_RFE 6'b001001
/* */
`define OR1200_OR32_JR 6'b010001
`define OR1200_OR32_JALR 6'b010010
`define OR1200_OR32_MACI 6'b010011
/* */
`define OR1200_OR32_LWZ 6'b100001
`define OR1200_OR32_LWS 6'b100010
`define OR1200_OR32_LBZ 6'b100011
`define OR1200_OR32_LBS 6'b100100
`define OR1200_OR32_LHZ 6'b100101
`define OR1200_OR32_LHS 6'b100110
`define OR1200_OR32_ADDI 6'b100111
`define OR1200_OR32_ADDIC 6'b101000
`define OR1200_OR32_ANDI 6'b101001
`define OR1200_OR32_ORI 6'b101010
`define OR1200_OR32_XORI 6'b101011
`define OR1200_OR32_MULI 6'b101100
`define OR1200_OR32_MFSPR 6'b101101
`define OR1200_OR32_SH_ROTI 6'b101110
`define OR1200_OR32_SFXXI 6'b101111
/* */
`define OR1200_OR32_MTSPR 6'b110000
`define OR1200_OR32_MACMSB 6'b110001
`define OR1200_OR32_FLOAT 6'b110010
/* */
`define OR1200_OR32_SW 6'b110101
`define OR1200_OR32_SB 6'b110110
`define OR1200_OR32_SH 6'b110111
`define OR1200_OR32_ALU 6'b111000
`define OR1200_OR32_SFXX 6'b111001
`define OR1200_OR32_CUST5 6'b111100
/////////////////////////////////////////////////////
//
// Exceptions
//
//
// Exception vectors per OR1K architecture:
// 0xPPPPP100 - reset
// 0xPPPPP200 - bus error
// ... etc
// where P represents exception prefix.
//
// Exception vectors can be customized as per
// the following formula:
// 0xPPPPPNVV - exception N
//
// P represents exception prefix
// N represents exception N
// VV represents length of the individual vector space,
// usually it is 8 bits wide and starts with all bits zero
//
//
// PPPPP and VV parts
//
// Sum of these two defines needs to be 28
//
`define OR1200_EXCEPT_EPH0_P 20'h00000
`define OR1200_EXCEPT_EPH1_P 20'hF0000
`define OR1200_EXCEPT_V 8'h00
//
// N part width
//
`define OR1200_EXCEPT_WIDTH 4
//
// Definition of exception vectors
//
// To avoid implementation of a certain exception,
// simply comment out corresponding line
//
`define OR1200_EXCEPT_UNUSED `OR1200_EXCEPT_WIDTH'hf
`define OR1200_EXCEPT_TRAP `OR1200_EXCEPT_WIDTH'he
`define OR1200_EXCEPT_FLOAT `OR1200_EXCEPT_WIDTH'hd
`define OR1200_EXCEPT_SYSCALL `OR1200_EXCEPT_WIDTH'hc
`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7
`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6
`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5
`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4
`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3
`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2
`define OR1200_EXCEPT_RESET `OR1200_EXCEPT_WIDTH'h1
`define OR1200_EXCEPT_NONE `OR1200_EXCEPT_WIDTH'h0
/////////////////////////////////////////////////////
//
// SPR groups
//
// Bits that define the group
`define OR1200_SPR_GROUP_BITS 15:11
// Width of the group bits
`define OR1200_SPR_GROUP_WIDTH 5
// Bits that define offset inside the group
`define OR1200_SPR_OFS_BITS 10:0
// List of groups
`define OR1200_SPR_GROUP_SYS 5'd00
`define OR1200_SPR_GROUP_DMMU 5'd01
`define OR1200_SPR_GROUP_IMMU 5'd02
`define OR1200_SPR_GROUP_DC 5'd03
`define OR1200_SPR_GROUP_IC 5'd04
`define OR1200_SPR_GROUP_MAC 5'd05
`define OR1200_SPR_GROUP_DU 5'd06
`define OR1200_SPR_GROUP_PM 5'd08
`define OR1200_SPR_GROUP_PIC 5'd09
`define OR1200_SPR_GROUP_TT 5'd10
`define OR1200_SPR_GROUP_FPU 5'd11
/////////////////////////////////////////////////////
//
// System group
//
//
// System registers
//
`define OR1200_SPR_CFGR 7'd0
`define OR1200_SPR_RF 6'd32 // 1024 >> 5
`define OR1200_SPR_NPC 11'd16
`define OR1200_SPR_SR 11'd17
`define OR1200_SPR_PPC 11'd18
`define OR1200_SPR_FPCSR 11'd20
`define OR1200_SPR_EPCR 11'd32
`define OR1200_SPR_EEAR 11'd48
`define OR1200_SPR_ESR 11'd64
//
// SR bits
//
`define OR1200_SR_WIDTH 17
`define OR1200_SR_SM 0
`define OR1200_SR_TEE 1
`define OR1200_SR_IEE 2
`define OR1200_SR_DCE 3
`define OR1200_SR_ICE 4
`define OR1200_SR_DME 5
`define OR1200_SR_IME 6
`define OR1200_SR_LEE 7
`define OR1200_SR_CE 8
`define OR1200_SR_F 9
`define OR1200_SR_CY 10 // Optional
`define OR1200_SR_OV 11 // Optional
`define OR1200_SR_OVE 12 // Optional
`define OR1200_SR_DSX 13 // Unused
`define OR1200_SR_EPH 14
`define OR1200_SR_FO 15
`define OR1200_SR_TED 16
`define OR1200_SR_CID 31:28 // Unimplemented
//
// Bits that define offset inside the group
//
`define OR1200_SPROFS_BITS 10:0
//
// Default Exception Prefix
//
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
//
`define OR1200_SR_EPH_DEF 1'b0
//
// FPCSR bits
//
`define OR1200_FPCSR_WIDTH 12
`define OR1200_FPCSR_FPEE 0
`define OR1200_FPCSR_RM 2:1
`define OR1200_FPCSR_OVF 3
`define OR1200_FPCSR_UNF 4
`define OR1200_FPCSR_SNF 5
`define OR1200_FPCSR_QNF 6
`define OR1200_FPCSR_ZF 7
`define OR1200_FPCSR_IXF 8
`define OR1200_FPCSR_IVF 9
`define OR1200_FPCSR_INF 10
`define OR1200_FPCSR_DZF 11
`define OR1200_FPCSR_RES 31:12
/////////////////////////////////////////////////////
//
// Power Management (PM)
//
// Define it if you want PM implemented
//`define OR1200_PM_IMPLEMENTED
// Bit positions inside PMR (don't change)
`define OR1200_PM_PMR_SDF 3:0
`define OR1200_PM_PMR_DME 4
`define OR1200_PM_PMR_SME 5
`define OR1200_PM_PMR_DCGE 6
`define OR1200_PM_PMR_UNUSED 31:7
// PMR offset inside PM group of registers
`define OR1200_PM_OFS_PMR 11'b0
// PM group
`define OR1200_SPRGRP_PM 5'd8
// Define if PMR can be read/written at any address inside PM group
`define OR1200_PM_PARTIAL_DECODING
// Define if reading PMR is allowed
`define OR1200_PM_READREGS
// Define if unused PMR bits should be zero
`define OR1200_PM_UNUSED_ZERO
/////////////////////////////////////////////////////
//
// Debug Unit (DU)
//
// Define it if you want DU implemented
`define OR1200_DU_IMPLEMENTED
//
// Define if you want HW Breakpoints
// (if HW breakpoints are not implemented
// only default software trapping is
// possible with l.trap insn - this is
// however already enough for use
// with or32 gdb)
//
//`define OR1200_DU_HWBKPTS
// Number of DVR/DCR pairs if HW breakpoints enabled
// Comment / uncomment DU_DVRn / DU_DCRn pairs bellow according to this number !
// DU_DVR0..DU_DVR7 should be uncommented for 8 DU_DVRDCR_PAIRS
`define OR1200_DU_DVRDCR_PAIRS 8
// Define if you want trace buffer
// (for now only available for Xilinx Virtex FPGAs)
//`define OR1200_DU_TB_IMPLEMENTED
//
// Address offsets of DU registers inside DU group
//
// To not implement a register, doq not define its address
//
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DVR0 11'd0
`define OR1200_DU_DVR1 11'd1
`define OR1200_DU_DVR2 11'd2
`define OR1200_DU_DVR3 11'd3
`define OR1200_DU_DVR4 11'd4
`define OR1200_DU_DVR5 11'd5
`define OR1200_DU_DVR6 11'd6
`define OR1200_DU_DVR7 11'd7
`define OR1200_DU_DCR0 11'd8
`define OR1200_DU_DCR1 11'd9
`define OR1200_DU_DCR2 11'd10
`define OR1200_DU_DCR3 11'd11
`define OR1200_DU_DCR4 11'd12
`define OR1200_DU_DCR5 11'd13
`define OR1200_DU_DCR6 11'd14
`define OR1200_DU_DCR7 11'd15
`endif
`define OR1200_DU_DMR1 11'd16
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DU_DMR2 11'd17
`define OR1200_DU_DWCR0 11'd18
`define OR1200_DU_DWCR1 11'd19
`endif
`define OR1200_DU_DSR 11'd20
`define OR1200_DU_DRR 11'd21
`ifdef OR1200_DU_TB_IMPLEMENTED
`define OR1200_DU_TBADR 11'h0ff
`define OR1200_DU_TBIA 11'h1??
`define OR1200_DU_TBIM 11'h2??
`define OR1200_DU_TBAR 11'h3??
`define OR1200_DU_TBTS 11'h4??
`endif
// Position of offset bits inside SPR address
`define OR1200_DUOFS_BITS 10:0
// DCR bits
`define OR1200_DU_DCR_DP 0
`define OR1200_DU_DCR_CC 3:1
`define OR1200_DU_DCR_SC 4
`define OR1200_DU_DCR_CT 7:5
// DMR1 bits
`define OR1200_DU_DMR1_CW0 1:0
`define OR1200_DU_DMR1_CW1 3:2
`define OR1200_DU_DMR1_CW2 5:4
`define OR1200_DU_DMR1_CW3 7:6
`define OR1200_DU_DMR1_CW4 9:8
`define OR1200_DU_DMR1_CW5 11:10
`define OR1200_DU_DMR1_CW6 13:12
`define OR1200_DU_DMR1_CW7 15:14
`define OR1200_DU_DMR1_CW8 17:16
`define OR1200_DU_DMR1_CW9 19:18
`define OR1200_DU_DMR1_CW10 21:20
`define OR1200_DU_DMR1_ST 22
`define OR1200_DU_DMR1_BT 23
`define OR1200_DU_DMR1_DXFW 24
`define OR1200_DU_DMR1_ETE 25
// DMR2 bits
`define OR1200_DU_DMR2_WCE0 0
`define OR1200_DU_DMR2_WCE1 1
`define OR1200_DU_DMR2_AWTC 12:2
`define OR1200_DU_DMR2_WGB 23:13
// DWCR bits
`define OR1200_DU_DWCR_COUNT 15:0
`define OR1200_DU_DWCR_MATCH 31:16
// DSR bits
`define OR1200_DU_DSR_WIDTH 14
`define OR1200_DU_DSR_RSTE 0
`define OR1200_DU_DSR_BUSEE 1
`define OR1200_DU_DSR_DPFE 2
`define OR1200_DU_DSR_IPFE 3
`define OR1200_DU_DSR_TTE 4
`define OR1200_DU_DSR_AE 5
`define OR1200_DU_DSR_IIE 6
`define OR1200_DU_DSR_IE 7
`define OR1200_DU_DSR_DME 8
`define OR1200_DU_DSR_IME 9
`define OR1200_DU_DSR_RE 10
`define OR1200_DU_DSR_SCE 11
`define OR1200_DU_DSR_FPE 12
`define OR1200_DU_DSR_TE 13
// DRR bits
`define OR1200_DU_DRR_RSTE 0
`define OR1200_DU_DRR_BUSEE 1
`define OR1200_DU_DRR_DPFE 2
`define OR1200_DU_DRR_IPFE 3
`define OR1200_DU_DRR_TTE 4
`define OR1200_DU_DRR_AE 5
`define OR1200_DU_DRR_IIE 6
`define OR1200_DU_DRR_IE 7
`define OR1200_DU_DRR_DME 8
`define OR1200_DU_DRR_IME 9
`define OR1200_DU_DRR_RE 10
`define OR1200_DU_DRR_SCE 11
`define OR1200_DU_DRR_FPE 12
`define OR1200_DU_DRR_TE 13
// Define if reading DU regs is allowed
`define OR1200_DU_READREGS
// Define if unused DU registers bits should be zero
`define OR1200_DU_UNUSED_ZERO
// Define if IF/LSU status is not needed by devel i/f
`define OR1200_DU_STATUS_UNIMPLEMENTED
/////////////////////////////////////////////////////
//
// Programmable Interrupt Controller (PIC)
//
// Define it if you want PIC implemented
`define OR1200_PIC_IMPLEMENTED
// Define number of interrupt inputs (2-31)
`define OR1200_PIC_INTS 31
// Address offsets of PIC registers inside PIC group
`define OR1200_PIC_OFS_PICMR 2'd0
`define OR1200_PIC_OFS_PICSR 2'd2
// Position of offset bits inside SPR address
`define OR1200_PICOFS_BITS 1:0
// Define if you want these PIC registers to be implemented
`define OR1200_PIC_PICMR
`define OR1200_PIC_PICSR
// Define if reading PIC registers is allowed
`define OR1200_PIC_READREGS
// Define if unused PIC register bits should be zero
`define OR1200_PIC_UNUSED_ZERO
/////////////////////////////////////////////////////
//
// Tick Timer (TT)
//
// Define it if you want TT implemented
`define OR1200_TT_IMPLEMENTED
// Address offsets of TT registers inside TT group
`define OR1200_TT_OFS_TTMR 1'd0
`define OR1200_TT_OFS_TTCR 1'd1
// Position of offset bits inside SPR group
`define OR1200_TTOFS_BITS 0
// Define if you want these TT registers to be implemented
`define OR1200_TT_TTMR
`define OR1200_TT_TTCR
// TTMR bits
`define OR1200_TT_TTMR_TP 27:0
`define OR1200_TT_TTMR_IP 28
`define OR1200_TT_TTMR_IE 29
`define OR1200_TT_TTMR_M 31:30
// Define if reading TT registers is allowed
`define OR1200_TT_READREGS
//////////////////////////////////////////////
//
// MAC
//
`define OR1200_MAC_ADDR 0 // MACLO 0xxxxxxxx1, MACHI 0xxxxxxxx0
`define OR1200_MAC_SPR_WE // Define if MACLO/MACHI are SPR writable
//
// Shift {MACHI,MACLO} into destination register when executing l.macrc
//
// According to architecture manual there is no shift, so default value is 0.
// However the implementation has deviated in this from the arch manual and had
// hard coded shift by 28 bits which is a useful optimization for MP3 decoding
// (if using libmad fixed point library). Shifts are no longer default setup,
// but if you need to remain backward compatible, define your shift bits, which
// were normally
// dest_GPR = {MACHI,MACLO}[59:28]
`define OR1200_MAC_SHIFTBY 0 // 0 = According to arch manual, 28 = obsolete backward compatibility
//////////////////////////////////////////////
//
// Data MMU (DMMU)
//
//
// Address that selects between TLB TR and MR
//
`define OR1200_DTLB_TM_ADDR 7
//
// DTLBMR fields
//
`define OR1200_DTLBMR_V_BITS 0
`define OR1200_DTLBMR_CID_BITS 4:1
`define OR1200_DTLBMR_RES_BITS 11:5
`define OR1200_DTLBMR_VPN_BITS 31:13
//
// DTLBTR fields
//
`define OR1200_DTLBTR_CC_BITS 0
`define OR1200_DTLBTR_CI_BITS 1
`define OR1200_DTLBTR_WBC_BITS 2
`define OR1200_DTLBTR_WOM_BITS 3
`define OR1200_DTLBTR_A_BITS 4
`define OR1200_DTLBTR_D_BITS 5
`define OR1200_DTLBTR_URE_BITS 6
`define OR1200_DTLBTR_UWE_BITS 7
`define OR1200_DTLBTR_SRE_BITS 8
`define OR1200_DTLBTR_SWE_BITS 9
`define OR1200_DTLBTR_RES_BITS 11:10
`define OR1200_DTLBTR_PPN_BITS 31:13
//
// DTLB configuration
//
`define OR1200_DMMU_PS 13 // 13 for 8KB page size
`define OR1200_DTLB_INDXW 6 // 6 for 64 entry DTLB 7 for 128 entries
`define OR1200_DTLB_INDXL `OR1200_DMMU_PS // 13 13
`define OR1200_DTLB_INDXH `OR1200_DMMU_PS+`OR1200_DTLB_INDXW-1 // 18 19
`define OR1200_DTLB_INDX `OR1200_DTLB_INDXH:`OR1200_DTLB_INDXL // 18:13 19:13
`define OR1200_DTLB_TAGW 32-`OR1200_DTLB_INDXW-`OR1200_DMMU_PS // 13 12
`define OR1200_DTLB_TAGL `OR1200_DTLB_INDXH+1 // 19 20
`define OR1200_DTLB_TAG 31:`OR1200_DTLB_TAGL // 31:19 31:20
`define OR1200_DTLBMRW `OR1200_DTLB_TAGW+1 // +1 because of V bit
`define OR1200_DTLBTRW 32-`OR1200_DMMU_PS+5 // +5 because of protection bits and CI
//
// Cache inhibit while DMMU is not enabled/implemented
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !dcpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !dcpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB dcpu_adr_i[30]
// cache inhibited 2GB-4GB (default) dcpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_DMMU_CI dcpu_adr_i[31]
//////////////////////////////////////////////
//
// Insn MMU (IMMU)
//
//
// Address that selects between TLB TR and MR
//
`define OR1200_ITLB_TM_ADDR 7
//
// ITLBMR fields
//
`define OR1200_ITLBMR_V_BITS 0
`define OR1200_ITLBMR_CID_BITS 4:1
`define OR1200_ITLBMR_RES_BITS 11:5
`define OR1200_ITLBMR_VPN_BITS 31:13
//
// ITLBTR fields
//
`define OR1200_ITLBTR_CC_BITS 0
`define OR1200_ITLBTR_CI_BITS 1
`define OR1200_ITLBTR_WBC_BITS 2
`define OR1200_ITLBTR_WOM_BITS 3
`define OR1200_ITLBTR_A_BITS 4
`define OR1200_ITLBTR_D_BITS 5
`define OR1200_ITLBTR_SXE_BITS 6
`define OR1200_ITLBTR_UXE_BITS 7
`define OR1200_ITLBTR_RES_BITS 11:8
`define OR1200_ITLBTR_PPN_BITS 31:13
//
// ITLB configuration
//
`define OR1200_IMMU_PS 13 // 13 for 8KB page size
`define OR1200_ITLB_INDXW 6 // 6 for 64 entry ITLB 7 for 128 entries
`define OR1200_ITLB_INDXL `OR1200_IMMU_PS // 13 13
`define OR1200_ITLB_INDXH `OR1200_IMMU_PS+`OR1200_ITLB_INDXW-1 // 18 19
`define OR1200_ITLB_INDX `OR1200_ITLB_INDXH:`OR1200_ITLB_INDXL // 18:13 19:13
`define OR1200_ITLB_TAGW 32-`OR1200_ITLB_INDXW-`OR1200_IMMU_PS // 13 12
`define OR1200_ITLB_TAGL `OR1200_ITLB_INDXH+1 // 19 20
`define OR1200_ITLB_TAG 31:`OR1200_ITLB_TAGL // 31:19 31:20
`define OR1200_ITLBMRW `OR1200_ITLB_TAGW+1 // +1 because of V bit
`define OR1200_ITLBTRW 32-`OR1200_IMMU_PS+3 // +3 because of protection bits and CI
//
// Cache inhibit while IMMU is not enabled/implemented
// Note: all combinations that use icpu_adr_i cause async loop
//
// cache inhibited 0GB-4GB 1'b1
// cache inhibited 0GB-2GB !icpu_adr_i[31]
// cache inhibited 0GB-1GB 2GB-3GB !icpu_adr_i[30]
// cache inhibited 1GB-2GB 3GB-4GB icpu_adr_i[30]
// cache inhibited 2GB-4GB (default) icpu_adr_i[31]
// cached 0GB-4GB 1'b0
//
`define OR1200_IMMU_CI 1'b0
/////////////////////////////////////////////////
//
// Insn cache (IC)
//
// 4 for 16 byte line, 5 for 32 byte lines.
`ifdef OR1200_IC_1W_32KB
`define OR1200_ICLS 5
`else
`define OR1200_ICLS 4
`endif
//
// IC configurations
//
`ifdef OR1200_IC_1W_512B
`define OR1200_ICSIZE 9 // 512
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 7
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 8
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 9
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 5
`define OR1200_ICTAG_W 24
`endif
`ifdef OR1200_IC_1W_4KB
`define OR1200_ICSIZE 12 // 4096
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 10
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 11
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 12
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 8
`define OR1200_ICTAG_W 21
`endif
`ifdef OR1200_IC_1W_8KB
`define OR1200_ICSIZE 13 // 8192
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 11
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 12
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 13
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9
`define OR1200_ICTAG_W 20
`endif
`ifdef OR1200_IC_1W_16KB
`define OR1200_ICSIZE 14 // 16384
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 12
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 13
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
`define OR1200_ICTAG_W 19
`endif
`ifdef OR1200_IC_1W_32KB
`define OR1200_ICSIZE 15 // 32768
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 13
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 14
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10
`define OR1200_ICTAG_W 18
`endif
/////////////////////////////////////////////////
//
// Data cache (DC)
//
// 4 for 16 bytes, 5 for 32 bytes
`ifdef OR1200_DC_1W_32KB
`define OR1200_DCLS 5
`else
`define OR1200_DCLS 4
`endif
// Define to enable default behavior of cache as write through
// Turning this off enabled write back statergy
//
`define OR1200_DC_WRITETHROUGH
// Define to enable stores from the stack not doing writethrough.
// EXPERIMENTAL
//`define OR1200_DC_NOSTACKWRITETHROUGH
// Data cache SPR definitions
`define OR1200_SPRGRP_DC_ADR_WIDTH 3
// Data cache group SPR addresses
`define OR1200_SPRGRP_DC_DCCR 3'd0 // Not implemented
`define OR1200_SPRGRP_DC_DCBPR 3'd1 // Not implemented
`define OR1200_SPRGRP_DC_DCBFR 3'd2
`define OR1200_SPRGRP_DC_DCBIR 3'd3
`define OR1200_SPRGRP_DC_DCBWR 3'd4 // Not implemented
`define OR1200_SPRGRP_DC_DCBLR 3'd5 // Not implemented
//
// DC configurations
//
`ifdef OR1200_DC_1W_4KB
`define OR1200_DCSIZE 12 // 4096
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 10
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 11
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 12
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 8
`define OR1200_DCTAG_W 21
`endif
`ifdef OR1200_DC_1W_8KB
`define OR1200_DCSIZE 13 // 8192
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 11
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 12
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 13
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9
`define OR1200_DCTAG_W 20
`endif
`ifdef OR1200_DC_1W_16KB
`define OR1200_DCSIZE 14 // 16384
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 12
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 13
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 14
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
`define OR1200_DCTAG_W 19
`endif
`ifdef OR1200_DC_1W_32KB
`define OR1200_DCSIZE 15 // 32768
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 13
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 14
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 15
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10
`define OR1200_DCTAG_W 18
`endif
/////////////////////////////////////////////////
//
// Store buffer (SB)
//
//
// Store buffer
//
// It will improve performance by "caching" CPU stores
// using store buffer. This is most important for function
// prologues because DC can only work in write though mode
// and all stores would have to complete external WB writes
// to memory.
// Store buffer is between DC and data BIU.
// All stores will be stored into store buffer and immediately
// completed by the CPU, even though actual external writes
// will be performed later. As a consequence store buffer masks
// all data bus errors related to stores (data bus errors
// related to loads are delivered normally).
// All pending CPU loads will wait until store buffer is empty to
// ensure strict memory model. Right now this is necessary because
// we don't make destinction between cached and cache inhibited
// address space, so we simply empty store buffer until loads
// can begin.
//
// It makes design a bit bigger, depending what is the number of
// entries in SB FIFO. Number of entries can be changed further
// down.
//
//`define OR1200_SB_IMPLEMENTED
//
// Number of store buffer entries
//
// Verified number of entries are 4 and 8 entries
// (2 and 3 for OR1200_SB_LOG). OR1200_SB_ENTRIES must
// always match 2**OR1200_SB_LOG.
// To disable store buffer, undefine
// OR1200_SB_IMPLEMENTED.
//
`define OR1200_SB_LOG 2 // 2 or 3
`define OR1200_SB_ENTRIES 4 // 4 or 8
/////////////////////////////////////////////////
//
// Quick Embedded Memory (QMEM)
//
//
// Quick Embedded Memory
//
// Instantiation of dedicated insn/data memory (RAM or ROM).
// Insn fetch has effective throughput 1insn / clock cycle.
// Data load takes two clock cycles / access, data store
// takes 1 clock cycle / access (if there is no insn fetch)).
// Memory instantiation is shared between insn and data,
// meaning if insn fetch are performed, data load/store
// performance will be lower.
//
// Main reason for QMEM is to put some time critical functions
// into this memory and to have predictable and fast access
// to these functions. (soft fpu, context switch, exception
// handlers, stack, etc)
//
// It makes design a bit bigger and slower. QMEM sits behind
// IMMU/DMMU so all addresses are physical (so the MMUs can be
// used with QMEM and QMEM is seen by the CPU just like any other
// memory in the system). IC/DC are sitting behind QMEM so the
// whole design timing might be worse with QMEM implemented.
//
//`define OR1200_QMEM_IMPLEMENTED
//
// Base address and mask of QMEM
//
// Base address defines first address of QMEM. Mask defines
// QMEM range in address space. Actual size of QMEM is however
// determined with instantiated RAM/ROM. However bigger
// mask will reserve more address space for QMEM, but also
// make design faster, while more tight mask will take
// less address space but also make design slower. If
// instantiated RAM/ROM is smaller than space reserved with
// the mask, instatiated RAM/ROM will also be shadowed
// at higher addresses in reserved space.
//
`define OR1200_QMEM_IADDR 32'h0080_0000
`define OR1200_QMEM_IMASK 32'hfff0_0000 // Max QMEM size 1MB
`define OR1200_QMEM_DADDR 32'h0080_0000
`define OR1200_QMEM_DMASK 32'hfff0_0000 // Max QMEM size 1MB
//
// QMEM interface byte-select capability
//
// To enable qmem_sel* ports, define this macro.
//
//`define OR1200_QMEM_BSEL
//
// QMEM interface acknowledge
//
// To enable qmem_ack port, define this macro.
//
//`define OR1200_QMEM_ACK
/////////////////////////////////////////////////////
//
// VR, UPR and Configuration Registers
//
//
// VR, UPR and configuration registers are optional. If
// implemented, operating system can automatically figure
// out how to use the processor because it knows
// what units are available in the processor and how they
// are configured.
//
// This section must be last in or1200_defines.v file so
// that all units are already configured and thus
// configuration registers are properly set.
//
// Define if you want configuration registers implemented
`define OR1200_CFGR_IMPLEMENTED
// Define if you want full address decode inside SYS group
`define OR1200_SYS_FULL_DECODE
// Offsets of VR, UPR and CFGR registers
`define OR1200_SPRGRP_SYS_VR 4'h0
`define OR1200_SPRGRP_SYS_UPR 4'h1
`define OR1200_SPRGRP_SYS_CPUCFGR 4'h2
`define OR1200_SPRGRP_SYS_DMMUCFGR 4'h3
`define OR1200_SPRGRP_SYS_IMMUCFGR 4'h4
`define OR1200_SPRGRP_SYS_DCCFGR 4'h5
`define OR1200_SPRGRP_SYS_ICCFGR 4'h6
`define OR1200_SPRGRP_SYS_DCFGR 4'h7
// VR fields
`define OR1200_VR_REV_BITS 5:0
`define OR1200_VR_RES1_BITS 15:6
`define OR1200_VR_CFG_BITS 23:16
`define OR1200_VR_VER_BITS 31:24
// VR values
`define OR1200_VR_REV 6'h08
`define OR1200_VR_RES1 10'h000
`define OR1200_VR_CFG 8'h00
`define OR1200_VR_VER 8'h12
// UPR fields
`define OR1200_UPR_UP_BITS 0
`define OR1200_UPR_DCP_BITS 1
`define OR1200_UPR_ICP_BITS 2
`define OR1200_UPR_DMP_BITS 3
`define OR1200_UPR_IMP_BITS 4
`define OR1200_UPR_MP_BITS 5
`define OR1200_UPR_DUP_BITS 6
`define OR1200_UPR_PCUP_BITS 7
`define OR1200_UPR_PMP_BITS 8
`define OR1200_UPR_PICP_BITS 9
`define OR1200_UPR_TTP_BITS 10
`define OR1200_UPR_FPP_BITS 11
`define OR1200_UPR_RES1_BITS 23:12
`define OR1200_UPR_CUP_BITS 31:24
// UPR values
`define OR1200_UPR_UP 1'b1
`ifdef OR1200_NO_DC
`define OR1200_UPR_DCP 1'b0
`else
`define OR1200_UPR_DCP 1'b1
`endif
`ifdef OR1200_NO_IC
`define OR1200_UPR_ICP 1'b0
`else
`define OR1200_UPR_ICP 1'b1
`endif
`ifdef OR1200_NO_DMMU
`define OR1200_UPR_DMP 1'b0
`else
`define OR1200_UPR_DMP 1'b1
`endif
`ifdef OR1200_NO_IMMU
`define OR1200_UPR_IMP 1'b0
`else
`define OR1200_UPR_IMP 1'b1
`endif
`ifdef OR1200_MAC_IMPLEMENTED
`define OR1200_UPR_MP 1'b1
`else
`define OR1200_UPR_MP 1'b0
`endif
`ifdef OR1200_DU_IMPLEMENTED
`define OR1200_UPR_DUP 1'b1
`else
`define OR1200_UPR_DUP 1'b0
`endif
`define OR1200_UPR_PCUP 1'b0 // Performance counters not present
`ifdef OR1200_PM_IMPLEMENTED
`define OR1200_UPR_PMP 1'b1
`else
`define OR1200_UPR_PMP 1'b0
`endif
`ifdef OR1200_PIC_IMPLEMENTED
`define OR1200_UPR_PICP 1'b1
`else
`define OR1200_UPR_PICP 1'b0
`endif
`ifdef OR1200_TT_IMPLEMENTED
`define OR1200_UPR_TTP 1'b1
`else
`define OR1200_UPR_TTP 1'b0
`endif
`ifdef OR1200_FPU_IMPLEMENTED
`define OR1200_UPR_FPP 1'b1
`else
`define OR1200_UPR_FPP 1'b0
`endif
`define OR1200_UPR_RES1 12'h000
`define OR1200_UPR_CUP 8'h00
// CPUCFGR fields
`define OR1200_CPUCFGR_NSGF_BITS 3:0
`define OR1200_CPUCFGR_HGF_BITS 4
`define OR1200_CPUCFGR_OB32S_BITS 5
`define OR1200_CPUCFGR_OB64S_BITS 6
`define OR1200_CPUCFGR_OF32S_BITS 7
`define OR1200_CPUCFGR_OF64S_BITS 8
`define OR1200_CPUCFGR_OV64S_BITS 9
`define OR1200_CPUCFGR_RES1_BITS 31:10
// CPUCFGR values
`define OR1200_CPUCFGR_NSGF 4'h0
`ifdef OR1200_RFRAM_16REG
`define OR1200_CPUCFGR_HGF 1'b1
`else
`define OR1200_CPUCFGR_HGF 1'b0
`endif
`define OR1200_CPUCFGR_OB32S 1'b1
`define OR1200_CPUCFGR_OB64S 1'b0
`ifdef OR1200_FPU_IMPLEMENTED
`define OR1200_CPUCFGR_OF32S 1'b1
`else
`define OR1200_CPUCFGR_OF32S 1'b0
`endif
`define OR1200_CPUCFGR_OF64S 1'b0
`define OR1200_CPUCFGR_OV64S 1'b0
`define OR1200_CPUCFGR_RES1 22'h000000
// DMMUCFGR fields
`define OR1200_DMMUCFGR_NTW_BITS 1:0
`define OR1200_DMMUCFGR_NTS_BITS 4:2
`define OR1200_DMMUCFGR_NAE_BITS 7:5
`define OR1200_DMMUCFGR_CRI_BITS 8
`define OR1200_DMMUCFGR_PRI_BITS 9
`define OR1200_DMMUCFGR_TEIRI_BITS 10
`define OR1200_DMMUCFGR_HTR_BITS 11
`define OR1200_DMMUCFGR_RES1_BITS 31:12
// DMMUCFGR values
`ifdef OR1200_NO_DMMU
`define OR1200_DMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_DMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_DMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_DMMUCFGR_RES1 20'h00000
`else
`define OR1200_DMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_DMMUCFGR_NTS 3'h`OR1200_DTLB_INDXW // Num TLB sets
`define OR1200_DMMUCFGR_NAE 3'h0 // No ATB entries
`define OR1200_DMMUCFGR_CRI 1'b0 // No control register
`define OR1200_DMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_DMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl.
`define OR1200_DMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_DMMUCFGR_RES1 20'h00000
`endif
// IMMUCFGR fields
`define OR1200_IMMUCFGR_NTW_BITS 1:0
`define OR1200_IMMUCFGR_NTS_BITS 4:2
`define OR1200_IMMUCFGR_NAE_BITS 7:5
`define OR1200_IMMUCFGR_CRI_BITS 8
`define OR1200_IMMUCFGR_PRI_BITS 9
`define OR1200_IMMUCFGR_TEIRI_BITS 10
`define OR1200_IMMUCFGR_HTR_BITS 11
`define OR1200_IMMUCFGR_RES1_BITS 31:12
// IMMUCFGR values
`ifdef OR1200_NO_IMMU
`define OR1200_IMMUCFGR_NTW 2'h0 // Irrelevant
`define OR1200_IMMUCFGR_NTS 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_NAE 3'h0 // Irrelevant
`define OR1200_IMMUCFGR_CRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_PRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_TEIRI 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_HTR 1'b0 // Irrelevant
`define OR1200_IMMUCFGR_RES1 20'h00000
`else
`define OR1200_IMMUCFGR_NTW 2'h0 // 1 TLB way
`define OR1200_IMMUCFGR_NTS 3'h`OR1200_ITLB_INDXW // Num TLB sets
`define OR1200_IMMUCFGR_NAE 3'h0 // No ATB entry
`define OR1200_IMMUCFGR_CRI 1'b0 // No control reg
`define OR1200_IMMUCFGR_PRI 1'b0 // No protection reg
`define OR1200_IMMUCFGR_TEIRI 1'b0 // TLB entry inv reg NOT impl
`define OR1200_IMMUCFGR_HTR 1'b0 // No HW TLB reload
`define OR1200_IMMUCFGR_RES1 20'h00000
`endif
// DCCFGR fields
`define OR1200_DCCFGR_NCW_BITS 2:0
`define OR1200_DCCFGR_NCS_BITS 6:3
`define OR1200_DCCFGR_CBS_BITS 7
`define OR1200_DCCFGR_CWS_BITS 8
`define OR1200_DCCFGR_CCRI_BITS 9
`define OR1200_DCCFGR_CBIRI_BITS 10
`define OR1200_DCCFGR_CBPRI_BITS 11
`define OR1200_DCCFGR_CBLRI_BITS 12
`define OR1200_DCCFGR_CBFRI_BITS 13
`define OR1200_DCCFGR_CBWBRI_BITS 14
`define OR1200_DCCFGR_RES1_BITS 31:15
// DCCFGR values
`ifdef OR1200_NO_DC
`define OR1200_DCCFGR_NCW 3'h0 // Irrelevant
`define OR1200_DCCFGR_NCS 4'h0 // Irrelevant
`define OR1200_DCCFGR_CBS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CWS 1'b0 // Irrelevant
`define OR1200_DCCFGR_CCRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBIRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBFRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_DCCFGR_RES1 17'h00000
`else
`define OR1200_DCCFGR_NCW 3'h0 // 1 cache way
`define OR1200_DCCFGR_NCS (`OR1200_DCTAG) // Num cache sets
`define OR1200_DCCFGR_CBS `OR1200_DCLS==4 ? 1'b0 : 1'b1 // 16 byte cache block
`ifdef OR1200_DC_WRITETHROUGH
`define OR1200_DCCFGR_CWS 1'b0 // Write-through strategy
`else
`define OR1200_DCCFGR_CWS 1'b1 // Write-back strategy
`endif
`define OR1200_DCCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_DCCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_DCCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_DCCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_DCCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`ifdef OR1200_DC_WRITETHROUGH
`define OR1200_DCCFGR_CBWBRI 1'b0 // Cache block WB reg not impl.
`else
`define OR1200_DCCFGR_CBWBRI 1'b1 // Cache block WB reg impl.
`endif
`define OR1200_DCCFGR_RES1 17'h00000
`endif
// ICCFGR fields
`define OR1200_ICCFGR_NCW_BITS 2:0
`define OR1200_ICCFGR_NCS_BITS 6:3
`define OR1200_ICCFGR_CBS_BITS 7
`define OR1200_ICCFGR_CWS_BITS 8
`define OR1200_ICCFGR_CCRI_BITS 9
`define OR1200_ICCFGR_CBIRI_BITS 10
`define OR1200_ICCFGR_CBPRI_BITS 11
`define OR1200_ICCFGR_CBLRI_BITS 12
`define OR1200_ICCFGR_CBFRI_BITS 13
`define OR1200_ICCFGR_CBWBRI_BITS 14
`define OR1200_ICCFGR_RES1_BITS 31:15
// ICCFGR values
`ifdef OR1200_NO_IC
`define OR1200_ICCFGR_NCW 3'h0 // Irrelevant
`define OR1200_ICCFGR_NCS 4'h0 // Irrelevant
`define OR1200_ICCFGR_CBS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBIRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBPRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBLRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBFRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`else
`define OR1200_ICCFGR_NCW 3'h0 // 1 cache way
`define OR1200_ICCFGR_NCS (`OR1200_ICTAG) // Num cache sets
`define OR1200_ICCFGR_CBS `OR1200_ICLS==4 ? 1'b0: 1'b1 // 16 byte cache block
`define OR1200_ICCFGR_CWS 1'b0 // Irrelevant
`define OR1200_ICCFGR_CCRI 1'b1 // Cache control reg impl.
`define OR1200_ICCFGR_CBIRI 1'b1 // Cache block inv reg impl.
`define OR1200_ICCFGR_CBPRI 1'b0 // Cache block prefetch reg not impl.
`define OR1200_ICCFGR_CBLRI 1'b0 // Cache block lock reg not impl.
`define OR1200_ICCFGR_CBFRI 1'b1 // Cache block flush reg impl.
`define OR1200_ICCFGR_CBWBRI 1'b0 // Irrelevant
`define OR1200_ICCFGR_RES1 17'h00000
`endif
// DCFGR fields
`define OR1200_DCFGR_NDP_BITS 3:0
`define OR1200_DCFGR_WPCI_BITS 4
`define OR1200_DCFGR_RES1_BITS 31:5
// DCFGR values
`ifdef OR1200_DU_HWBKPTS
`define OR1200_DCFGR_NDP 4'h`OR1200_DU_DVRDCR_PAIRS // # of DVR/DCR pairs
`ifdef OR1200_DU_DWCR0
`define OR1200_DCFGR_WPCI 1'b1
`else
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`else
`define OR1200_DCFGR_NDP 4'h0 // Zero DVR/DCR pairs
`define OR1200_DCFGR_WPCI 1'b0 // WP counters not impl.
`endif
`define OR1200_DCFGR_RES1 27'd0
///////////////////////////////////////////////////////////////////////////////
// Boot Address Selection //
// //
// Allows a definable boot address, potentially different to the usual reset //
// vector to allow for power-on code to be run, if desired. //
// //
// OR1200_BOOT_ADR should be the 32-bit address of the boot location //
// OR1200_BOOT_PCREG_DEFAULT should be ((OR1200_BOOT_ADR-4)>>2) //
// //
// For default reset behavior uncomment the settings under the "Boot 0x100" //
// comment below. //
// //
///////////////////////////////////////////////////////////////////////////////
// Boot from 0xf0000100
//`define OR1200_BOOT_PCREG_DEFAULT 30'h3c00003f
//`define OR1200_BOOT_ADR 32'hf0000100
// Boot from 0x100
`define OR1200_BOOT_PCREG_DEFAULT 30'h0000003f
`define OR1200_BOOT_ADR 32'h00000100
|
//////////////////////////////////////////////////////////////////////////////////
// CRC_serial_m_lfs_XOR.v for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Jinwoo Jeong <[email protected]>
// Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: BCH encoder/decoder
// Module Name: CRC_serial_m_lfs_XOR
// File Name: CRC_serial_m_lfs_XOR.v
//
// Version: v1.0.0
//
// Description: Serial linear feedback shift XOR for CRC code
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module CRC_serial_m_lfs_XOR
#(
parameter HASH_LENGTH = 64
)
(
i_message ,
i_cur_parity ,
o_next_parity
);
input i_message ;
input [HASH_LENGTH-1:0] i_cur_parity ;
output [HASH_LENGTH-1:0] o_next_parity ;
localparam [0:64] HASH_VALUE = 65'b11001001011011000101011110010101110101111000011100001111010000101;
wire w_feedback_term;
assign w_feedback_term = i_message ^ i_cur_parity[HASH_LENGTH-1];
assign o_next_parity[0] = w_feedback_term;
genvar i;
generate
for (i=1; i<HASH_LENGTH; i=i+1)
begin: linear_function
if (HASH_VALUE[i] == 1)
assign o_next_parity[i] = i_cur_parity[i-1] ^ w_feedback_term;
else
assign o_next_parity[i] = i_cur_parity[i-1];
end
endgenerate
endmodule |
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// MUXes mouse and kbd data in two single databusses for zports
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
`include "../include/tune.v"
module zkbdmus(
input wire fclk,
input wire rst_n,
input wire [39:0] kbd_in, // key bits
input wire kbd_stb, // and strobe
input wire [ 7:0] mus_in,
input wire mus_xstb,
input wire mus_ystb,
input wire mus_btnstb,
input wire kj_stb,
input wire [7:0] zah,
output wire [ 4:0] kbd_data,
output wire [ 7:0] mus_data,
output reg [ 4:0] kj_data
);
reg [39:0] kbd;
reg [ 7:0] musx,musy,musbtn;
wire [4:0] keys [0:7]; // key matrix
reg [4:0] kout; // wire AND
`ifdef SIMULATE
initial
begin
// force kbd_data = 5'b11111;
force mus_data = 8'hFF;
force kj_data = 5'b00000;
kbd = 40'd0;
end
`endif
// store data from slavespi
//
always @(posedge fclk)
begin
if( kbd_stb )
kbd <= kbd_in;
if( mus_xstb )
musx <= mus_in;
if( mus_ystb )
musy <= mus_in;
if( mus_btnstb )
musbtn <= mus_in;
if( kj_stb )
kj_data <= mus_in[4:0];
end
// make keys
//
assign keys[0]={kbd[00],kbd[08],kbd[16],kbd[24],kbd[32]};// v c x z CS
assign keys[1]={kbd[01],kbd[09],kbd[17],kbd[25],kbd[33]};// g f d s a
assign keys[2]={kbd[02],kbd[10],kbd[18],kbd[26],kbd[34]};// t r e w q
assign keys[3]={kbd[03],kbd[11],kbd[19],kbd[27],kbd[35]};// 5 4 3 2 1
assign keys[4]={kbd[04],kbd[12],kbd[20],kbd[28],kbd[36]};// 6 7 8 9 0
assign keys[5]={kbd[05],kbd[13],kbd[21],kbd[29],kbd[37]};// y u i o p
assign keys[6]={kbd[06],kbd[14],kbd[22],kbd[30],kbd[38]};// h j k l EN
assign keys[7]={kbd[07],kbd[15],kbd[23],kbd[31],kbd[39]};// b n m SS SP
//
always @*
begin
kout = 5'b11111;
kout = kout & ({5{zah[0]}} | (~keys[0]));
kout = kout & ({5{zah[1]}} | (~keys[1]));
kout = kout & ({5{zah[2]}} | (~keys[2]));
kout = kout & ({5{zah[3]}} | (~keys[3]));
kout = kout & ({5{zah[4]}} | (~keys[4]));
kout = kout & ({5{zah[5]}} | (~keys[5]));
kout = kout & ({5{zah[6]}} | (~keys[6]));
kout = kout & ({5{zah[7]}} | (~keys[7]));
end
//
assign kbd_data = kout;
// make mouse
// FADF - buttons, FBDF - x, FFDF - y
//
assign mus_data = zah[0] ? ( zah[2] ? musy : musx ) : musbtn;
endmodule
|
// nios_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_mm_interconnect_0 (
input wire mem_if_ddr2_emif_0_afi_clk_clk, // mem_if_ddr2_emif_0_afi_clk.clk
input wire mem32_to_avalon_0_reset_reset_bridge_in_reset_reset, // mem32_to_avalon_0_reset_reset_bridge_in_reset.reset
input wire mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset, // mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset.reset
input wire mem_if_ddr2_emif_0_soft_reset_reset_bridge_in_reset_reset, // mem_if_ddr2_emif_0_soft_reset_reset_bridge_in_reset.reset
input wire nios2_gen2_0_reset_reset_bridge_in_reset_reset, // nios2_gen2_0_reset_reset_bridge_in_reset.reset
input wire [25:0] mem32_to_avalon_0_avalon_master_address, // mem32_to_avalon_0_avalon_master.address
output wire mem32_to_avalon_0_avalon_master_waitrequest, // .waitrequest
input wire [3:0] mem32_to_avalon_0_avalon_master_byteenable, // .byteenable
input wire mem32_to_avalon_0_avalon_master_read, // .read
output wire [31:0] mem32_to_avalon_0_avalon_master_readdata, // .readdata
output wire mem32_to_avalon_0_avalon_master_readdatavalid, // .readdatavalid
input wire mem32_to_avalon_0_avalon_master_write, // .write
input wire [31:0] mem32_to_avalon_0_avalon_master_writedata, // .writedata
input wire [28:0] nios2_gen2_0_data_master_address, // nios2_gen2_0_data_master.address
output wire nios2_gen2_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_gen2_0_data_master_byteenable, // .byteenable
input wire nios2_gen2_0_data_master_read, // .read
output wire [31:0] nios2_gen2_0_data_master_readdata, // .readdata
input wire nios2_gen2_0_data_master_write, // .write
input wire [31:0] nios2_gen2_0_data_master_writedata, // .writedata
input wire nios2_gen2_0_data_master_debugaccess, // .debugaccess
input wire [28:0] nios2_gen2_0_instruction_master_address, // nios2_gen2_0_instruction_master.address
output wire nios2_gen2_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_gen2_0_instruction_master_read, // .read
output wire [31:0] nios2_gen2_0_instruction_master_readdata, // .readdata
output wire [19:0] io_bridge_0_avalon_slave_0_address, // io_bridge_0_avalon_slave_0.address
output wire io_bridge_0_avalon_slave_0_write, // .write
output wire io_bridge_0_avalon_slave_0_read, // .read
input wire [7:0] io_bridge_0_avalon_slave_0_readdata, // .readdata
output wire [7:0] io_bridge_0_avalon_slave_0_writedata, // .writedata
input wire io_bridge_0_avalon_slave_0_readdatavalid, // .readdatavalid
input wire io_bridge_0_avalon_slave_0_waitrequest, // .waitrequest
output wire [23:0] mem_if_ddr2_emif_0_avl_address, // mem_if_ddr2_emif_0_avl.address
output wire mem_if_ddr2_emif_0_avl_write, // .write
output wire mem_if_ddr2_emif_0_avl_read, // .read
input wire [31:0] mem_if_ddr2_emif_0_avl_readdata, // .readdata
output wire [31:0] mem_if_ddr2_emif_0_avl_writedata, // .writedata
output wire mem_if_ddr2_emif_0_avl_beginbursttransfer, // .beginbursttransfer
output wire [2:0] mem_if_ddr2_emif_0_avl_burstcount, // .burstcount
output wire [3:0] mem_if_ddr2_emif_0_avl_byteenable, // .byteenable
input wire mem_if_ddr2_emif_0_avl_readdatavalid, // .readdatavalid
input wire mem_if_ddr2_emif_0_avl_waitrequest, // .waitrequest
output wire [8:0] nios2_gen2_0_debug_mem_slave_address, // nios2_gen2_0_debug_mem_slave.address
output wire nios2_gen2_0_debug_mem_slave_write, // .write
output wire nios2_gen2_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_gen2_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_gen2_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_gen2_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_gen2_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_gen2_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [2:0] pio_0_s1_address, // pio_0_s1.address
output wire pio_0_s1_write, // .write
input wire [31:0] pio_0_s1_readdata, // .readdata
output wire [31:0] pio_0_s1_writedata, // .writedata
output wire pio_0_s1_chipselect // .chipselect
);
wire mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_waitrequest; // mem32_to_avalon_0_avalon_master_agent:av_waitrequest -> mem32_to_avalon_0_avalon_master_translator:uav_waitrequest
wire [31:0] mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_readdata; // mem32_to_avalon_0_avalon_master_agent:av_readdata -> mem32_to_avalon_0_avalon_master_translator:uav_readdata
wire mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_debugaccess; // mem32_to_avalon_0_avalon_master_translator:uav_debugaccess -> mem32_to_avalon_0_avalon_master_agent:av_debugaccess
wire [28:0] mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_address; // mem32_to_avalon_0_avalon_master_translator:uav_address -> mem32_to_avalon_0_avalon_master_agent:av_address
wire mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_read; // mem32_to_avalon_0_avalon_master_translator:uav_read -> mem32_to_avalon_0_avalon_master_agent:av_read
wire [3:0] mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_byteenable; // mem32_to_avalon_0_avalon_master_translator:uav_byteenable -> mem32_to_avalon_0_avalon_master_agent:av_byteenable
wire mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_readdatavalid; // mem32_to_avalon_0_avalon_master_agent:av_readdatavalid -> mem32_to_avalon_0_avalon_master_translator:uav_readdatavalid
wire mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_lock; // mem32_to_avalon_0_avalon_master_translator:uav_lock -> mem32_to_avalon_0_avalon_master_agent:av_lock
wire mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_write; // mem32_to_avalon_0_avalon_master_translator:uav_write -> mem32_to_avalon_0_avalon_master_agent:av_write
wire [31:0] mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_writedata; // mem32_to_avalon_0_avalon_master_translator:uav_writedata -> mem32_to_avalon_0_avalon_master_agent:av_writedata
wire [2:0] mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_burstcount; // mem32_to_avalon_0_avalon_master_translator:uav_burstcount -> mem32_to_avalon_0_avalon_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> mem32_to_avalon_0_avalon_master_agent:rp_valid
wire [104:0] rsp_mux_src_data; // rsp_mux:src_data -> mem32_to_avalon_0_avalon_master_agent:rp_data
wire rsp_mux_src_ready; // mem32_to_avalon_0_avalon_master_agent:rp_ready -> rsp_mux:src_ready
wire [3:0] rsp_mux_src_channel; // rsp_mux:src_channel -> mem32_to_avalon_0_avalon_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> mem32_to_avalon_0_avalon_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> mem32_to_avalon_0_avalon_master_agent:rp_endofpacket
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_data_master_agent:av_waitrequest -> nios2_gen2_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_data_master_agent:av_readdata -> nios2_gen2_0_data_master_translator:uav_readdata
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_data_master_translator:uav_debugaccess -> nios2_gen2_0_data_master_agent:av_debugaccess
wire [28:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_data_master_translator:uav_address -> nios2_gen2_0_data_master_agent:av_address
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_data_master_translator:uav_read -> nios2_gen2_0_data_master_agent:av_read
wire [3:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_data_master_translator:uav_byteenable -> nios2_gen2_0_data_master_agent:av_byteenable
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_data_master_agent:av_readdatavalid -> nios2_gen2_0_data_master_translator:uav_readdatavalid
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_data_master_translator:uav_lock -> nios2_gen2_0_data_master_agent:av_lock
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_data_master_translator:uav_write -> nios2_gen2_0_data_master_agent:av_write
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_data_master_translator:uav_writedata -> nios2_gen2_0_data_master_agent:av_writedata
wire [2:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_data_master_translator:uav_burstcount -> nios2_gen2_0_data_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_gen2_0_data_master_agent:rp_valid
wire [104:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_gen2_0_data_master_agent:rp_data
wire rsp_mux_001_src_ready; // nios2_gen2_0_data_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [3:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_gen2_0_data_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_gen2_0_data_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_gen2_0_data_master_agent:rp_endofpacket
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_instruction_master_agent:av_waitrequest -> nios2_gen2_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_instruction_master_agent:av_readdata -> nios2_gen2_0_instruction_master_translator:uav_readdata
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_instruction_master_translator:uav_debugaccess -> nios2_gen2_0_instruction_master_agent:av_debugaccess
wire [28:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_instruction_master_translator:uav_address -> nios2_gen2_0_instruction_master_agent:av_address
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_instruction_master_translator:uav_read -> nios2_gen2_0_instruction_master_agent:av_read
wire [3:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_instruction_master_translator:uav_byteenable -> nios2_gen2_0_instruction_master_agent:av_byteenable
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_instruction_master_agent:av_readdatavalid -> nios2_gen2_0_instruction_master_translator:uav_readdatavalid
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_instruction_master_translator:uav_lock -> nios2_gen2_0_instruction_master_agent:av_lock
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_instruction_master_translator:uav_write -> nios2_gen2_0_instruction_master_agent:av_write
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_instruction_master_translator:uav_writedata -> nios2_gen2_0_instruction_master_agent:av_writedata
wire [2:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_instruction_master_translator:uav_burstcount -> nios2_gen2_0_instruction_master_agent:av_burstcount
wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> nios2_gen2_0_instruction_master_agent:rp_valid
wire [104:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> nios2_gen2_0_instruction_master_agent:rp_data
wire rsp_mux_002_src_ready; // nios2_gen2_0_instruction_master_agent:rp_ready -> rsp_mux_002:src_ready
wire [3:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> nios2_gen2_0_instruction_master_agent:rp_channel
wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> nios2_gen2_0_instruction_master_agent:rp_startofpacket
wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> nios2_gen2_0_instruction_master_agent:rp_endofpacket
wire [31:0] mem_if_ddr2_emif_0_avl_agent_m0_readdata; // mem_if_ddr2_emif_0_avl_translator:uav_readdata -> mem_if_ddr2_emif_0_avl_agent:m0_readdata
wire mem_if_ddr2_emif_0_avl_agent_m0_waitrequest; // mem_if_ddr2_emif_0_avl_translator:uav_waitrequest -> mem_if_ddr2_emif_0_avl_agent:m0_waitrequest
wire mem_if_ddr2_emif_0_avl_agent_m0_debugaccess; // mem_if_ddr2_emif_0_avl_agent:m0_debugaccess -> mem_if_ddr2_emif_0_avl_translator:uav_debugaccess
wire [28:0] mem_if_ddr2_emif_0_avl_agent_m0_address; // mem_if_ddr2_emif_0_avl_agent:m0_address -> mem_if_ddr2_emif_0_avl_translator:uav_address
wire [3:0] mem_if_ddr2_emif_0_avl_agent_m0_byteenable; // mem_if_ddr2_emif_0_avl_agent:m0_byteenable -> mem_if_ddr2_emif_0_avl_translator:uav_byteenable
wire mem_if_ddr2_emif_0_avl_agent_m0_read; // mem_if_ddr2_emif_0_avl_agent:m0_read -> mem_if_ddr2_emif_0_avl_translator:uav_read
wire mem_if_ddr2_emif_0_avl_agent_m0_readdatavalid; // mem_if_ddr2_emif_0_avl_translator:uav_readdatavalid -> mem_if_ddr2_emif_0_avl_agent:m0_readdatavalid
wire mem_if_ddr2_emif_0_avl_agent_m0_lock; // mem_if_ddr2_emif_0_avl_agent:m0_lock -> mem_if_ddr2_emif_0_avl_translator:uav_lock
wire [31:0] mem_if_ddr2_emif_0_avl_agent_m0_writedata; // mem_if_ddr2_emif_0_avl_agent:m0_writedata -> mem_if_ddr2_emif_0_avl_translator:uav_writedata
wire mem_if_ddr2_emif_0_avl_agent_m0_write; // mem_if_ddr2_emif_0_avl_agent:m0_write -> mem_if_ddr2_emif_0_avl_translator:uav_write
wire [4:0] mem_if_ddr2_emif_0_avl_agent_m0_burstcount; // mem_if_ddr2_emif_0_avl_agent:m0_burstcount -> mem_if_ddr2_emif_0_avl_translator:uav_burstcount
wire mem_if_ddr2_emif_0_avl_agent_rf_source_valid; // mem_if_ddr2_emif_0_avl_agent:rf_source_valid -> mem_if_ddr2_emif_0_avl_agent_rsp_fifo:in_valid
wire [105:0] mem_if_ddr2_emif_0_avl_agent_rf_source_data; // mem_if_ddr2_emif_0_avl_agent:rf_source_data -> mem_if_ddr2_emif_0_avl_agent_rsp_fifo:in_data
wire mem_if_ddr2_emif_0_avl_agent_rf_source_ready; // mem_if_ddr2_emif_0_avl_agent_rsp_fifo:in_ready -> mem_if_ddr2_emif_0_avl_agent:rf_source_ready
wire mem_if_ddr2_emif_0_avl_agent_rf_source_startofpacket; // mem_if_ddr2_emif_0_avl_agent:rf_source_startofpacket -> mem_if_ddr2_emif_0_avl_agent_rsp_fifo:in_startofpacket
wire mem_if_ddr2_emif_0_avl_agent_rf_source_endofpacket; // mem_if_ddr2_emif_0_avl_agent:rf_source_endofpacket -> mem_if_ddr2_emif_0_avl_agent_rsp_fifo:in_endofpacket
wire mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_valid; // mem_if_ddr2_emif_0_avl_agent_rsp_fifo:out_valid -> mem_if_ddr2_emif_0_avl_agent:rf_sink_valid
wire [105:0] mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_data; // mem_if_ddr2_emif_0_avl_agent_rsp_fifo:out_data -> mem_if_ddr2_emif_0_avl_agent:rf_sink_data
wire mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_ready; // mem_if_ddr2_emif_0_avl_agent:rf_sink_ready -> mem_if_ddr2_emif_0_avl_agent_rsp_fifo:out_ready
wire mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_startofpacket; // mem_if_ddr2_emif_0_avl_agent_rsp_fifo:out_startofpacket -> mem_if_ddr2_emif_0_avl_agent:rf_sink_startofpacket
wire mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_endofpacket; // mem_if_ddr2_emif_0_avl_agent_rsp_fifo:out_endofpacket -> mem_if_ddr2_emif_0_avl_agent:rf_sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> mem_if_ddr2_emif_0_avl_agent:cp_valid
wire [104:0] cmd_mux_src_data; // cmd_mux:src_data -> mem_if_ddr2_emif_0_avl_agent:cp_data
wire cmd_mux_src_ready; // mem_if_ddr2_emif_0_avl_agent:cp_ready -> cmd_mux:src_ready
wire [3:0] cmd_mux_src_channel; // cmd_mux:src_channel -> mem_if_ddr2_emif_0_avl_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> mem_if_ddr2_emif_0_avl_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> mem_if_ddr2_emif_0_avl_agent:cp_endofpacket
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_readdata; // nios2_gen2_0_debug_mem_slave_translator:uav_readdata -> nios2_gen2_0_debug_mem_slave_agent:m0_readdata
wire nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest; // nios2_gen2_0_debug_mem_slave_translator:uav_waitrequest -> nios2_gen2_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess; // nios2_gen2_0_debug_mem_slave_agent:m0_debugaccess -> nios2_gen2_0_debug_mem_slave_translator:uav_debugaccess
wire [28:0] nios2_gen2_0_debug_mem_slave_agent_m0_address; // nios2_gen2_0_debug_mem_slave_agent:m0_address -> nios2_gen2_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_gen2_0_debug_mem_slave_agent_m0_byteenable; // nios2_gen2_0_debug_mem_slave_agent:m0_byteenable -> nios2_gen2_0_debug_mem_slave_translator:uav_byteenable
wire nios2_gen2_0_debug_mem_slave_agent_m0_read; // nios2_gen2_0_debug_mem_slave_agent:m0_read -> nios2_gen2_0_debug_mem_slave_translator:uav_read
wire nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_gen2_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_gen2_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_gen2_0_debug_mem_slave_agent_m0_lock; // nios2_gen2_0_debug_mem_slave_agent:m0_lock -> nios2_gen2_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_writedata; // nios2_gen2_0_debug_mem_slave_agent:m0_writedata -> nios2_gen2_0_debug_mem_slave_translator:uav_writedata
wire nios2_gen2_0_debug_mem_slave_agent_m0_write; // nios2_gen2_0_debug_mem_slave_agent:m0_write -> nios2_gen2_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_gen2_0_debug_mem_slave_agent_m0_burstcount; // nios2_gen2_0_debug_mem_slave_agent:m0_burstcount -> nios2_gen2_0_debug_mem_slave_translator:uav_burstcount
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_valid; // nios2_gen2_0_debug_mem_slave_agent:rf_source_valid -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [105:0] nios2_gen2_0_debug_mem_slave_agent_rf_source_data; // nios2_gen2_0_debug_mem_slave_agent:rf_source_data -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_ready; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_gen2_0_debug_mem_slave_agent:rf_source_ready
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_valid
wire [105:0] nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_gen2_0_debug_mem_slave_agent:rf_sink_ready -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> nios2_gen2_0_debug_mem_slave_agent:cp_valid
wire [104:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> nios2_gen2_0_debug_mem_slave_agent:cp_data
wire cmd_mux_001_src_ready; // nios2_gen2_0_debug_mem_slave_agent:cp_ready -> cmd_mux_001:src_ready
wire [3:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> nios2_gen2_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_endofpacket
wire [7:0] io_bridge_0_avalon_slave_0_agent_m0_readdata; // io_bridge_0_avalon_slave_0_translator:uav_readdata -> io_bridge_0_avalon_slave_0_agent:m0_readdata
wire io_bridge_0_avalon_slave_0_agent_m0_waitrequest; // io_bridge_0_avalon_slave_0_translator:uav_waitrequest -> io_bridge_0_avalon_slave_0_agent:m0_waitrequest
wire io_bridge_0_avalon_slave_0_agent_m0_debugaccess; // io_bridge_0_avalon_slave_0_agent:m0_debugaccess -> io_bridge_0_avalon_slave_0_translator:uav_debugaccess
wire [28:0] io_bridge_0_avalon_slave_0_agent_m0_address; // io_bridge_0_avalon_slave_0_agent:m0_address -> io_bridge_0_avalon_slave_0_translator:uav_address
wire [0:0] io_bridge_0_avalon_slave_0_agent_m0_byteenable; // io_bridge_0_avalon_slave_0_agent:m0_byteenable -> io_bridge_0_avalon_slave_0_translator:uav_byteenable
wire io_bridge_0_avalon_slave_0_agent_m0_read; // io_bridge_0_avalon_slave_0_agent:m0_read -> io_bridge_0_avalon_slave_0_translator:uav_read
wire io_bridge_0_avalon_slave_0_agent_m0_readdatavalid; // io_bridge_0_avalon_slave_0_translator:uav_readdatavalid -> io_bridge_0_avalon_slave_0_agent:m0_readdatavalid
wire io_bridge_0_avalon_slave_0_agent_m0_lock; // io_bridge_0_avalon_slave_0_agent:m0_lock -> io_bridge_0_avalon_slave_0_translator:uav_lock
wire [7:0] io_bridge_0_avalon_slave_0_agent_m0_writedata; // io_bridge_0_avalon_slave_0_agent:m0_writedata -> io_bridge_0_avalon_slave_0_translator:uav_writedata
wire io_bridge_0_avalon_slave_0_agent_m0_write; // io_bridge_0_avalon_slave_0_agent:m0_write -> io_bridge_0_avalon_slave_0_translator:uav_write
wire [0:0] io_bridge_0_avalon_slave_0_agent_m0_burstcount; // io_bridge_0_avalon_slave_0_agent:m0_burstcount -> io_bridge_0_avalon_slave_0_translator:uav_burstcount
wire io_bridge_0_avalon_slave_0_agent_rf_source_valid; // io_bridge_0_avalon_slave_0_agent:rf_source_valid -> io_bridge_0_avalon_slave_0_agent_rsp_fifo:in_valid
wire [78:0] io_bridge_0_avalon_slave_0_agent_rf_source_data; // io_bridge_0_avalon_slave_0_agent:rf_source_data -> io_bridge_0_avalon_slave_0_agent_rsp_fifo:in_data
wire io_bridge_0_avalon_slave_0_agent_rf_source_ready; // io_bridge_0_avalon_slave_0_agent_rsp_fifo:in_ready -> io_bridge_0_avalon_slave_0_agent:rf_source_ready
wire io_bridge_0_avalon_slave_0_agent_rf_source_startofpacket; // io_bridge_0_avalon_slave_0_agent:rf_source_startofpacket -> io_bridge_0_avalon_slave_0_agent_rsp_fifo:in_startofpacket
wire io_bridge_0_avalon_slave_0_agent_rf_source_endofpacket; // io_bridge_0_avalon_slave_0_agent:rf_source_endofpacket -> io_bridge_0_avalon_slave_0_agent_rsp_fifo:in_endofpacket
wire io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_valid; // io_bridge_0_avalon_slave_0_agent_rsp_fifo:out_valid -> io_bridge_0_avalon_slave_0_agent:rf_sink_valid
wire [78:0] io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_data; // io_bridge_0_avalon_slave_0_agent_rsp_fifo:out_data -> io_bridge_0_avalon_slave_0_agent:rf_sink_data
wire io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_ready; // io_bridge_0_avalon_slave_0_agent:rf_sink_ready -> io_bridge_0_avalon_slave_0_agent_rsp_fifo:out_ready
wire io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket; // io_bridge_0_avalon_slave_0_agent_rsp_fifo:out_startofpacket -> io_bridge_0_avalon_slave_0_agent:rf_sink_startofpacket
wire io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket; // io_bridge_0_avalon_slave_0_agent_rsp_fifo:out_endofpacket -> io_bridge_0_avalon_slave_0_agent:rf_sink_endofpacket
wire [31:0] pio_0_s1_agent_m0_readdata; // pio_0_s1_translator:uav_readdata -> pio_0_s1_agent:m0_readdata
wire pio_0_s1_agent_m0_waitrequest; // pio_0_s1_translator:uav_waitrequest -> pio_0_s1_agent:m0_waitrequest
wire pio_0_s1_agent_m0_debugaccess; // pio_0_s1_agent:m0_debugaccess -> pio_0_s1_translator:uav_debugaccess
wire [28:0] pio_0_s1_agent_m0_address; // pio_0_s1_agent:m0_address -> pio_0_s1_translator:uav_address
wire [3:0] pio_0_s1_agent_m0_byteenable; // pio_0_s1_agent:m0_byteenable -> pio_0_s1_translator:uav_byteenable
wire pio_0_s1_agent_m0_read; // pio_0_s1_agent:m0_read -> pio_0_s1_translator:uav_read
wire pio_0_s1_agent_m0_readdatavalid; // pio_0_s1_translator:uav_readdatavalid -> pio_0_s1_agent:m0_readdatavalid
wire pio_0_s1_agent_m0_lock; // pio_0_s1_agent:m0_lock -> pio_0_s1_translator:uav_lock
wire [31:0] pio_0_s1_agent_m0_writedata; // pio_0_s1_agent:m0_writedata -> pio_0_s1_translator:uav_writedata
wire pio_0_s1_agent_m0_write; // pio_0_s1_agent:m0_write -> pio_0_s1_translator:uav_write
wire [2:0] pio_0_s1_agent_m0_burstcount; // pio_0_s1_agent:m0_burstcount -> pio_0_s1_translator:uav_burstcount
wire pio_0_s1_agent_rf_source_valid; // pio_0_s1_agent:rf_source_valid -> pio_0_s1_agent_rsp_fifo:in_valid
wire [105:0] pio_0_s1_agent_rf_source_data; // pio_0_s1_agent:rf_source_data -> pio_0_s1_agent_rsp_fifo:in_data
wire pio_0_s1_agent_rf_source_ready; // pio_0_s1_agent_rsp_fifo:in_ready -> pio_0_s1_agent:rf_source_ready
wire pio_0_s1_agent_rf_source_startofpacket; // pio_0_s1_agent:rf_source_startofpacket -> pio_0_s1_agent_rsp_fifo:in_startofpacket
wire pio_0_s1_agent_rf_source_endofpacket; // pio_0_s1_agent:rf_source_endofpacket -> pio_0_s1_agent_rsp_fifo:in_endofpacket
wire pio_0_s1_agent_rsp_fifo_out_valid; // pio_0_s1_agent_rsp_fifo:out_valid -> pio_0_s1_agent:rf_sink_valid
wire [105:0] pio_0_s1_agent_rsp_fifo_out_data; // pio_0_s1_agent_rsp_fifo:out_data -> pio_0_s1_agent:rf_sink_data
wire pio_0_s1_agent_rsp_fifo_out_ready; // pio_0_s1_agent:rf_sink_ready -> pio_0_s1_agent_rsp_fifo:out_ready
wire pio_0_s1_agent_rsp_fifo_out_startofpacket; // pio_0_s1_agent_rsp_fifo:out_startofpacket -> pio_0_s1_agent:rf_sink_startofpacket
wire pio_0_s1_agent_rsp_fifo_out_endofpacket; // pio_0_s1_agent_rsp_fifo:out_endofpacket -> pio_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> pio_0_s1_agent:cp_valid
wire [104:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> pio_0_s1_agent:cp_data
wire cmd_mux_003_src_ready; // pio_0_s1_agent:cp_ready -> cmd_mux_003:src_ready
wire [3:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> pio_0_s1_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> pio_0_s1_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> pio_0_s1_agent:cp_endofpacket
wire mem32_to_avalon_0_avalon_master_agent_cp_valid; // mem32_to_avalon_0_avalon_master_agent:cp_valid -> router:sink_valid
wire [104:0] mem32_to_avalon_0_avalon_master_agent_cp_data; // mem32_to_avalon_0_avalon_master_agent:cp_data -> router:sink_data
wire mem32_to_avalon_0_avalon_master_agent_cp_ready; // router:sink_ready -> mem32_to_avalon_0_avalon_master_agent:cp_ready
wire mem32_to_avalon_0_avalon_master_agent_cp_startofpacket; // mem32_to_avalon_0_avalon_master_agent:cp_startofpacket -> router:sink_startofpacket
wire mem32_to_avalon_0_avalon_master_agent_cp_endofpacket; // mem32_to_avalon_0_avalon_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [104:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [3:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire nios2_gen2_0_data_master_agent_cp_valid; // nios2_gen2_0_data_master_agent:cp_valid -> router_001:sink_valid
wire [104:0] nios2_gen2_0_data_master_agent_cp_data; // nios2_gen2_0_data_master_agent:cp_data -> router_001:sink_data
wire nios2_gen2_0_data_master_agent_cp_ready; // router_001:sink_ready -> nios2_gen2_0_data_master_agent:cp_ready
wire nios2_gen2_0_data_master_agent_cp_startofpacket; // nios2_gen2_0_data_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_gen2_0_data_master_agent_cp_endofpacket; // nios2_gen2_0_data_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [104:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [3:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire nios2_gen2_0_instruction_master_agent_cp_valid; // nios2_gen2_0_instruction_master_agent:cp_valid -> router_002:sink_valid
wire [104:0] nios2_gen2_0_instruction_master_agent_cp_data; // nios2_gen2_0_instruction_master_agent:cp_data -> router_002:sink_data
wire nios2_gen2_0_instruction_master_agent_cp_ready; // router_002:sink_ready -> nios2_gen2_0_instruction_master_agent:cp_ready
wire nios2_gen2_0_instruction_master_agent_cp_startofpacket; // nios2_gen2_0_instruction_master_agent:cp_startofpacket -> router_002:sink_startofpacket
wire nios2_gen2_0_instruction_master_agent_cp_endofpacket; // nios2_gen2_0_instruction_master_agent:cp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> cmd_demux_002:sink_valid
wire [104:0] router_002_src_data; // router_002:src_data -> cmd_demux_002:sink_data
wire router_002_src_ready; // cmd_demux_002:sink_ready -> router_002:src_ready
wire [3:0] router_002_src_channel; // router_002:src_channel -> cmd_demux_002:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
wire mem_if_ddr2_emif_0_avl_agent_rp_valid; // mem_if_ddr2_emif_0_avl_agent:rp_valid -> router_003:sink_valid
wire [104:0] mem_if_ddr2_emif_0_avl_agent_rp_data; // mem_if_ddr2_emif_0_avl_agent:rp_data -> router_003:sink_data
wire mem_if_ddr2_emif_0_avl_agent_rp_ready; // router_003:sink_ready -> mem_if_ddr2_emif_0_avl_agent:rp_ready
wire mem_if_ddr2_emif_0_avl_agent_rp_startofpacket; // mem_if_ddr2_emif_0_avl_agent:rp_startofpacket -> router_003:sink_startofpacket
wire mem_if_ddr2_emif_0_avl_agent_rp_endofpacket; // mem_if_ddr2_emif_0_avl_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux:sink_valid
wire [104:0] router_003_src_data; // router_003:src_data -> rsp_demux:sink_data
wire router_003_src_ready; // rsp_demux:sink_ready -> router_003:src_ready
wire [3:0] router_003_src_channel; // router_003:src_channel -> rsp_demux:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux:sink_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_valid; // nios2_gen2_0_debug_mem_slave_agent:rp_valid -> router_004:sink_valid
wire [104:0] nios2_gen2_0_debug_mem_slave_agent_rp_data; // nios2_gen2_0_debug_mem_slave_agent:rp_data -> router_004:sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rp_ready; // router_004:sink_ready -> nios2_gen2_0_debug_mem_slave_agent:rp_ready
wire nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_001:sink_valid
wire [104:0] router_004_src_data; // router_004:src_data -> rsp_demux_001:sink_data
wire router_004_src_ready; // rsp_demux_001:sink_ready -> router_004:src_ready
wire [3:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_001:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire io_bridge_0_avalon_slave_0_agent_rp_valid; // io_bridge_0_avalon_slave_0_agent:rp_valid -> router_005:sink_valid
wire [77:0] io_bridge_0_avalon_slave_0_agent_rp_data; // io_bridge_0_avalon_slave_0_agent:rp_data -> router_005:sink_data
wire io_bridge_0_avalon_slave_0_agent_rp_ready; // router_005:sink_ready -> io_bridge_0_avalon_slave_0_agent:rp_ready
wire io_bridge_0_avalon_slave_0_agent_rp_startofpacket; // io_bridge_0_avalon_slave_0_agent:rp_startofpacket -> router_005:sink_startofpacket
wire io_bridge_0_avalon_slave_0_agent_rp_endofpacket; // io_bridge_0_avalon_slave_0_agent:rp_endofpacket -> router_005:sink_endofpacket
wire pio_0_s1_agent_rp_valid; // pio_0_s1_agent:rp_valid -> router_006:sink_valid
wire [104:0] pio_0_s1_agent_rp_data; // pio_0_s1_agent:rp_data -> router_006:sink_data
wire pio_0_s1_agent_rp_ready; // router_006:sink_ready -> pio_0_s1_agent:rp_ready
wire pio_0_s1_agent_rp_startofpacket; // pio_0_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire pio_0_s1_agent_rp_endofpacket; // pio_0_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_003:sink_valid
wire [104:0] router_006_src_data; // router_006:src_data -> rsp_demux_003:sink_data
wire router_006_src_ready; // rsp_demux_003:sink_ready -> router_006:src_ready
wire [3:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_003:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire io_bridge_0_avalon_slave_0_burst_adapter_source0_valid; // io_bridge_0_avalon_slave_0_burst_adapter:source0_valid -> io_bridge_0_avalon_slave_0_agent:cp_valid
wire [77:0] io_bridge_0_avalon_slave_0_burst_adapter_source0_data; // io_bridge_0_avalon_slave_0_burst_adapter:source0_data -> io_bridge_0_avalon_slave_0_agent:cp_data
wire io_bridge_0_avalon_slave_0_burst_adapter_source0_ready; // io_bridge_0_avalon_slave_0_agent:cp_ready -> io_bridge_0_avalon_slave_0_burst_adapter:source0_ready
wire [3:0] io_bridge_0_avalon_slave_0_burst_adapter_source0_channel; // io_bridge_0_avalon_slave_0_burst_adapter:source0_channel -> io_bridge_0_avalon_slave_0_agent:cp_channel
wire io_bridge_0_avalon_slave_0_burst_adapter_source0_startofpacket; // io_bridge_0_avalon_slave_0_burst_adapter:source0_startofpacket -> io_bridge_0_avalon_slave_0_agent:cp_startofpacket
wire io_bridge_0_avalon_slave_0_burst_adapter_source0_endofpacket; // io_bridge_0_avalon_slave_0_burst_adapter:source0_endofpacket -> io_bridge_0_avalon_slave_0_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [104:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [3:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [104:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [3:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink0_valid
wire [104:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux_001:src1_ready
wire [3:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink0_valid
wire [104:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux_001:src2_ready
wire [3:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink0_valid
wire [104:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_001_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux_001:src3_ready
wire [3:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> cmd_mux:sink2_valid
wire [104:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> cmd_mux:sink2_data
wire cmd_demux_002_src0_ready; // cmd_mux:sink2_ready -> cmd_demux_002:src0_ready
wire [3:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> cmd_mux:sink2_channel
wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> cmd_mux:sink2_startofpacket
wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> cmd_mux:sink2_endofpacket
wire cmd_demux_002_src1_valid; // cmd_demux_002:src1_valid -> cmd_mux_001:sink1_valid
wire [104:0] cmd_demux_002_src1_data; // cmd_demux_002:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_002_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_002:src1_ready
wire [3:0] cmd_demux_002_src1_channel; // cmd_demux_002:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_002_src1_startofpacket; // cmd_demux_002:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_002_src1_endofpacket; // cmd_demux_002:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [104:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [3:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [104:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [3:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_src2_valid; // rsp_demux:src2_valid -> rsp_mux_002:sink0_valid
wire [104:0] rsp_demux_src2_data; // rsp_demux:src2_data -> rsp_mux_002:sink0_data
wire rsp_demux_src2_ready; // rsp_mux_002:sink0_ready -> rsp_demux:src2_ready
wire [3:0] rsp_demux_src2_channel; // rsp_demux:src2_channel -> rsp_mux_002:sink0_channel
wire rsp_demux_src2_startofpacket; // rsp_demux:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
wire rsp_demux_src2_endofpacket; // rsp_demux:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux_001:sink1_valid
wire [104:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux_001:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src0_ready
wire [3:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_002:sink1_valid
wire [104:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_002:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_002:sink1_ready -> rsp_demux_001:src1_ready
wire [3:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_002:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_002:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_002:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux_001:sink2_valid
wire [104:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux_001:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src0_ready
wire [3:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux_001:sink3_valid
wire [104:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux_001:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src0_ready
wire [3:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux_001:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink3_endofpacket
wire router_005_src_valid; // router_005:src_valid -> io_bridge_0_avalon_slave_0_rsp_width_adapter:in_valid
wire [77:0] router_005_src_data; // router_005:src_data -> io_bridge_0_avalon_slave_0_rsp_width_adapter:in_data
wire router_005_src_ready; // io_bridge_0_avalon_slave_0_rsp_width_adapter:in_ready -> router_005:src_ready
wire [3:0] router_005_src_channel; // router_005:src_channel -> io_bridge_0_avalon_slave_0_rsp_width_adapter:in_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> io_bridge_0_avalon_slave_0_rsp_width_adapter:in_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> io_bridge_0_avalon_slave_0_rsp_width_adapter:in_endofpacket
wire io_bridge_0_avalon_slave_0_rsp_width_adapter_src_valid; // io_bridge_0_avalon_slave_0_rsp_width_adapter:out_valid -> rsp_demux_002:sink_valid
wire [104:0] io_bridge_0_avalon_slave_0_rsp_width_adapter_src_data; // io_bridge_0_avalon_slave_0_rsp_width_adapter:out_data -> rsp_demux_002:sink_data
wire io_bridge_0_avalon_slave_0_rsp_width_adapter_src_ready; // rsp_demux_002:sink_ready -> io_bridge_0_avalon_slave_0_rsp_width_adapter:out_ready
wire [3:0] io_bridge_0_avalon_slave_0_rsp_width_adapter_src_channel; // io_bridge_0_avalon_slave_0_rsp_width_adapter:out_channel -> rsp_demux_002:sink_channel
wire io_bridge_0_avalon_slave_0_rsp_width_adapter_src_startofpacket; // io_bridge_0_avalon_slave_0_rsp_width_adapter:out_startofpacket -> rsp_demux_002:sink_startofpacket
wire io_bridge_0_avalon_slave_0_rsp_width_adapter_src_endofpacket; // io_bridge_0_avalon_slave_0_rsp_width_adapter:out_endofpacket -> rsp_demux_002:sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> io_bridge_0_avalon_slave_0_cmd_width_adapter:in_valid
wire [104:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> io_bridge_0_avalon_slave_0_cmd_width_adapter:in_data
wire cmd_mux_002_src_ready; // io_bridge_0_avalon_slave_0_cmd_width_adapter:in_ready -> cmd_mux_002:src_ready
wire [3:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> io_bridge_0_avalon_slave_0_cmd_width_adapter:in_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> io_bridge_0_avalon_slave_0_cmd_width_adapter:in_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> io_bridge_0_avalon_slave_0_cmd_width_adapter:in_endofpacket
wire io_bridge_0_avalon_slave_0_cmd_width_adapter_src_valid; // io_bridge_0_avalon_slave_0_cmd_width_adapter:out_valid -> io_bridge_0_avalon_slave_0_burst_adapter:sink0_valid
wire [77:0] io_bridge_0_avalon_slave_0_cmd_width_adapter_src_data; // io_bridge_0_avalon_slave_0_cmd_width_adapter:out_data -> io_bridge_0_avalon_slave_0_burst_adapter:sink0_data
wire io_bridge_0_avalon_slave_0_cmd_width_adapter_src_ready; // io_bridge_0_avalon_slave_0_burst_adapter:sink0_ready -> io_bridge_0_avalon_slave_0_cmd_width_adapter:out_ready
wire [3:0] io_bridge_0_avalon_slave_0_cmd_width_adapter_src_channel; // io_bridge_0_avalon_slave_0_cmd_width_adapter:out_channel -> io_bridge_0_avalon_slave_0_burst_adapter:sink0_channel
wire io_bridge_0_avalon_slave_0_cmd_width_adapter_src_startofpacket; // io_bridge_0_avalon_slave_0_cmd_width_adapter:out_startofpacket -> io_bridge_0_avalon_slave_0_burst_adapter:sink0_startofpacket
wire io_bridge_0_avalon_slave_0_cmd_width_adapter_src_endofpacket; // io_bridge_0_avalon_slave_0_cmd_width_adapter:out_endofpacket -> io_bridge_0_avalon_slave_0_burst_adapter:sink0_endofpacket
wire mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_valid; // mem_if_ddr2_emif_0_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [33:0] mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_data; // mem_if_ddr2_emif_0_avl_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> mem_if_ddr2_emif_0_avl_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> mem_if_ddr2_emif_0_avl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> mem_if_ddr2_emif_0_avl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // mem_if_ddr2_emif_0_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> mem_if_ddr2_emif_0_avl_agent:rdata_fifo_sink_error
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_error
wire io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_valid; // io_bridge_0_avalon_slave_0_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [9:0] io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_data; // io_bridge_0_avalon_slave_0_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> io_bridge_0_avalon_slave_0_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> io_bridge_0_avalon_slave_0_agent:rdata_fifo_sink_valid
wire [9:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> io_bridge_0_avalon_slave_0_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // io_bridge_0_avalon_slave_0_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> io_bridge_0_avalon_slave_0_agent:rdata_fifo_sink_error
wire pio_0_s1_agent_rdata_fifo_src_valid; // pio_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] pio_0_s1_agent_rdata_fifo_src_data; // pio_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire pio_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> pio_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> pio_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> pio_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // pio_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> pio_0_s1_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (26),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) mem32_to_avalon_0_avalon_master_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_read), // .read
.uav_write (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (mem32_to_avalon_0_avalon_master_address), // avalon_anti_master_0.address
.av_waitrequest (mem32_to_avalon_0_avalon_master_waitrequest), // .waitrequest
.av_byteenable (mem32_to_avalon_0_avalon_master_byteenable), // .byteenable
.av_read (mem32_to_avalon_0_avalon_master_read), // .read
.av_readdata (mem32_to_avalon_0_avalon_master_readdata), // .readdata
.av_readdatavalid (mem32_to_avalon_0_avalon_master_readdatavalid), // .readdatavalid
.av_write (mem32_to_avalon_0_avalon_master_write), // .write
.av_writedata (mem32_to_avalon_0_avalon_master_writedata), // .writedata
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (29),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) nios2_gen2_0_data_master_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.av_read (nios2_gen2_0_data_master_read), // .read
.av_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.av_write (nios2_gen2_0_data_master_write), // .write
.av_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (29),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_instruction_master_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_gen2_0_instruction_master_read), // .read
.av_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (24),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (3),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (5),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) mem_if_ddr2_emif_0_avl_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mem_if_ddr2_emif_0_avl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (mem_if_ddr2_emif_0_avl_agent_m0_burstcount), // .burstcount
.uav_read (mem_if_ddr2_emif_0_avl_agent_m0_read), // .read
.uav_write (mem_if_ddr2_emif_0_avl_agent_m0_write), // .write
.uav_waitrequest (mem_if_ddr2_emif_0_avl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (mem_if_ddr2_emif_0_avl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (mem_if_ddr2_emif_0_avl_agent_m0_byteenable), // .byteenable
.uav_readdata (mem_if_ddr2_emif_0_avl_agent_m0_readdata), // .readdata
.uav_writedata (mem_if_ddr2_emif_0_avl_agent_m0_writedata), // .writedata
.uav_lock (mem_if_ddr2_emif_0_avl_agent_m0_lock), // .lock
.uav_debugaccess (mem_if_ddr2_emif_0_avl_agent_m0_debugaccess), // .debugaccess
.av_address (mem_if_ddr2_emif_0_avl_address), // avalon_anti_slave_0.address
.av_write (mem_if_ddr2_emif_0_avl_write), // .write
.av_read (mem_if_ddr2_emif_0_avl_read), // .read
.av_readdata (mem_if_ddr2_emif_0_avl_readdata), // .readdata
.av_writedata (mem_if_ddr2_emif_0_avl_writedata), // .writedata
.av_beginbursttransfer (mem_if_ddr2_emif_0_avl_beginbursttransfer), // .beginbursttransfer
.av_burstcount (mem_if_ddr2_emif_0_avl_burstcount), // .burstcount
.av_byteenable (mem_if_ddr2_emif_0_avl_byteenable), // .byteenable
.av_readdatavalid (mem_if_ddr2_emif_0_avl_readdatavalid), // .readdatavalid
.av_waitrequest (mem_if_ddr2_emif_0_avl_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_gen2_0_debug_mem_slave_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_gen2_0_debug_mem_slave_write), // .write
.av_read (nios2_gen2_0_debug_mem_slave_read), // .read
.av_readdata (nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (8),
.UAV_DATA_W (8),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (1),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (1),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (1),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) io_bridge_0_avalon_slave_0_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (io_bridge_0_avalon_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (io_bridge_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (io_bridge_0_avalon_slave_0_agent_m0_read), // .read
.uav_write (io_bridge_0_avalon_slave_0_agent_m0_write), // .write
.uav_waitrequest (io_bridge_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (io_bridge_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (io_bridge_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (io_bridge_0_avalon_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (io_bridge_0_avalon_slave_0_agent_m0_writedata), // .writedata
.uav_lock (io_bridge_0_avalon_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (io_bridge_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (io_bridge_0_avalon_slave_0_address), // avalon_anti_slave_0.address
.av_write (io_bridge_0_avalon_slave_0_write), // .write
.av_read (io_bridge_0_avalon_slave_0_read), // .read
.av_readdata (io_bridge_0_avalon_slave_0_readdata), // .readdata
.av_writedata (io_bridge_0_avalon_slave_0_writedata), // .writedata
.av_readdatavalid (io_bridge_0_avalon_slave_0_readdatavalid), // .readdatavalid
.av_waitrequest (io_bridge_0_avalon_slave_0_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) pio_0_s1_translator (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (pio_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (pio_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (pio_0_s1_agent_m0_read), // .read
.uav_write (pio_0_s1_agent_m0_write), // .write
.uav_waitrequest (pio_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (pio_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (pio_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (pio_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (pio_0_s1_agent_m0_writedata), // .writedata
.uav_lock (pio_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (pio_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (pio_0_s1_address), // avalon_anti_slave_0.address
.av_write (pio_0_s1_write), // .write
.av_readdata (pio_0_s1_readdata), // .readdata
.av_writedata (pio_0_s1_writedata), // .writedata
.av_chipselect (pio_0_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_QOS_H (87),
.PKT_QOS_L (87),
.PKT_DATA_SIDEBAND_H (85),
.PKT_DATA_SIDEBAND_L (85),
.PKT_ADDR_SIDEBAND_H (84),
.PKT_ADDR_SIDEBAND_L (84),
.PKT_BURST_TYPE_H (83),
.PKT_BURST_TYPE_L (82),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (90),
.ST_DATA_W (105),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) mem32_to_avalon_0_avalon_master_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_address), // av.address
.av_write (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_write), // .write
.av_read (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (mem32_to_avalon_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (mem32_to_avalon_0_avalon_master_agent_cp_valid), // cp.valid
.cp_data (mem32_to_avalon_0_avalon_master_agent_cp_data), // .data
.cp_startofpacket (mem32_to_avalon_0_avalon_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (mem32_to_avalon_0_avalon_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (mem32_to_avalon_0_avalon_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_QOS_H (87),
.PKT_QOS_L (87),
.PKT_DATA_SIDEBAND_H (85),
.PKT_DATA_SIDEBAND_L (85),
.PKT_ADDR_SIDEBAND_H (84),
.PKT_ADDR_SIDEBAND_L (84),
.PKT_BURST_TYPE_H (83),
.PKT_BURST_TYPE_L (82),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (90),
.ST_DATA_W (105),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_data_master_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_QOS_H (87),
.PKT_QOS_L (87),
.PKT_DATA_SIDEBAND_H (85),
.PKT_DATA_SIDEBAND_L (85),
.PKT_ADDR_SIDEBAND_H (84),
.PKT_ADDR_SIDEBAND_L (84),
.PKT_BURST_TYPE_H (83),
.PKT_BURST_TYPE_L (82),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (90),
.ST_DATA_W (105),
.ST_CHANNEL_W (4),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (2),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_instruction_master_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_002_src_valid), // rp.valid
.rp_data (rsp_mux_002_src_data), // .data
.rp_channel (rsp_mux_002_src_channel), // .channel
.rp_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_002_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (90),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (5),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) mem_if_ddr2_emif_0_avl_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (mem_if_ddr2_emif_0_avl_agent_m0_address), // m0.address
.m0_burstcount (mem_if_ddr2_emif_0_avl_agent_m0_burstcount), // .burstcount
.m0_byteenable (mem_if_ddr2_emif_0_avl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (mem_if_ddr2_emif_0_avl_agent_m0_debugaccess), // .debugaccess
.m0_lock (mem_if_ddr2_emif_0_avl_agent_m0_lock), // .lock
.m0_readdata (mem_if_ddr2_emif_0_avl_agent_m0_readdata), // .readdata
.m0_readdatavalid (mem_if_ddr2_emif_0_avl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (mem_if_ddr2_emif_0_avl_agent_m0_read), // .read
.m0_waitrequest (mem_if_ddr2_emif_0_avl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (mem_if_ddr2_emif_0_avl_agent_m0_writedata), // .writedata
.m0_write (mem_if_ddr2_emif_0_avl_agent_m0_write), // .write
.rp_endofpacket (mem_if_ddr2_emif_0_avl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (mem_if_ddr2_emif_0_avl_agent_rp_ready), // .ready
.rp_valid (mem_if_ddr2_emif_0_avl_agent_rp_valid), // .valid
.rp_data (mem_if_ddr2_emif_0_avl_agent_rp_data), // .data
.rp_startofpacket (mem_if_ddr2_emif_0_avl_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (mem_if_ddr2_emif_0_avl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (mem_if_ddr2_emif_0_avl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (mem_if_ddr2_emif_0_avl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (mem_if_ddr2_emif_0_avl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (mem_if_ddr2_emif_0_avl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (33),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) mem_if_ddr2_emif_0_avl_agent_rsp_fifo (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (mem_if_ddr2_emif_0_avl_agent_rf_source_data), // in.data
.in_valid (mem_if_ddr2_emif_0_avl_agent_rf_source_valid), // .valid
.in_ready (mem_if_ddr2_emif_0_avl_agent_rf_source_ready), // .ready
.in_startofpacket (mem_if_ddr2_emif_0_avl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (mem_if_ddr2_emif_0_avl_agent_rf_source_endofpacket), // .endofpacket
.out_data (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_data), // out.data
.out_valid (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_valid), // .valid
.out_ready (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (mem_if_ddr2_emif_0_avl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (90),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) nios2_gen2_0_debug_mem_slave_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_gen2_0_debug_mem_slave_agent_rsp_fifo (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (77),
.PKT_ORI_BURST_SIZE_L (75),
.PKT_RESPONSE_STATUS_H (74),
.PKT_RESPONSE_STATUS_L (73),
.PKT_BURST_SIZE_H (54),
.PKT_BURST_SIZE_L (52),
.PKT_TRANS_LOCK (42),
.PKT_BEGIN_BURST (59),
.PKT_PROTECTION_H (68),
.PKT_PROTECTION_L (66),
.PKT_BURSTWRAP_H (51),
.PKT_BURSTWRAP_L (49),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (44),
.PKT_ADDR_H (37),
.PKT_ADDR_L (9),
.PKT_TRANS_COMPRESSED_READ (38),
.PKT_TRANS_POSTED (39),
.PKT_TRANS_WRITE (40),
.PKT_TRANS_READ (41),
.PKT_DATA_H (7),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (8),
.PKT_BYTEEN_L (8),
.PKT_SRC_ID_H (62),
.PKT_SRC_ID_L (61),
.PKT_DEST_ID_H (64),
.PKT_DEST_ID_L (63),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (78),
.AVS_BURSTCOUNT_W (1),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) io_bridge_0_avalon_slave_0_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (io_bridge_0_avalon_slave_0_agent_m0_address), // m0.address
.m0_burstcount (io_bridge_0_avalon_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (io_bridge_0_avalon_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (io_bridge_0_avalon_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (io_bridge_0_avalon_slave_0_agent_m0_lock), // .lock
.m0_readdata (io_bridge_0_avalon_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (io_bridge_0_avalon_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (io_bridge_0_avalon_slave_0_agent_m0_read), // .read
.m0_waitrequest (io_bridge_0_avalon_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (io_bridge_0_avalon_slave_0_agent_m0_writedata), // .writedata
.m0_write (io_bridge_0_avalon_slave_0_agent_m0_write), // .write
.rp_endofpacket (io_bridge_0_avalon_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (io_bridge_0_avalon_slave_0_agent_rp_ready), // .ready
.rp_valid (io_bridge_0_avalon_slave_0_agent_rp_valid), // .valid
.rp_data (io_bridge_0_avalon_slave_0_agent_rp_data), // .data
.rp_startofpacket (io_bridge_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (io_bridge_0_avalon_slave_0_burst_adapter_source0_ready), // cp.ready
.cp_valid (io_bridge_0_avalon_slave_0_burst_adapter_source0_valid), // .valid
.cp_data (io_bridge_0_avalon_slave_0_burst_adapter_source0_data), // .data
.cp_startofpacket (io_bridge_0_avalon_slave_0_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (io_bridge_0_avalon_slave_0_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (io_bridge_0_avalon_slave_0_burst_adapter_source0_channel), // .channel
.rf_sink_ready (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (io_bridge_0_avalon_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (io_bridge_0_avalon_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (io_bridge_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (io_bridge_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (io_bridge_0_avalon_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (79),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) io_bridge_0_avalon_slave_0_agent_rsp_fifo (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (io_bridge_0_avalon_slave_0_agent_rf_source_data), // in.data
.in_valid (io_bridge_0_avalon_slave_0_agent_rf_source_valid), // .valid
.in_ready (io_bridge_0_avalon_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (io_bridge_0_avalon_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (io_bridge_0_avalon_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (io_bridge_0_avalon_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (104),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (69),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (89),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (90),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (4),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) pio_0_s1_agent (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (pio_0_s1_agent_m0_address), // m0.address
.m0_burstcount (pio_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (pio_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (pio_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (pio_0_s1_agent_m0_lock), // .lock
.m0_readdata (pio_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (pio_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (pio_0_s1_agent_m0_read), // .read
.m0_waitrequest (pio_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (pio_0_s1_agent_m0_writedata), // .writedata
.m0_write (pio_0_s1_agent_m0_write), // .write
.rp_endofpacket (pio_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (pio_0_s1_agent_rp_ready), // .ready
.rp_valid (pio_0_s1_agent_rp_valid), // .valid
.rp_data (pio_0_s1_agent_rp_data), // .data
.rp_startofpacket (pio_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (pio_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (pio_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (pio_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (pio_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (pio_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (pio_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (pio_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (pio_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (pio_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (pio_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (pio_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (pio_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (pio_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) pio_0_s1_agent_rsp_fifo (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (pio_0_s1_agent_rf_source_data), // in.data
.in_valid (pio_0_s1_agent_rf_source_valid), // .valid
.in_ready (pio_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (pio_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (pio_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (pio_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (pio_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (pio_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (pio_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (pio_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
nios_mm_interconnect_0_router router (
.sink_ready (mem32_to_avalon_0_avalon_master_agent_cp_ready), // sink.ready
.sink_valid (mem32_to_avalon_0_avalon_master_agent_cp_valid), // .valid
.sink_data (mem32_to_avalon_0_avalon_master_agent_cp_data), // .data
.sink_startofpacket (mem32_to_avalon_0_avalon_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (mem32_to_avalon_0_avalon_master_agent_cp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_gen2_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_router_002 router_002 (
.sink_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_router_003 router_003 (
.sink_ready (mem_if_ddr2_emif_0_avl_agent_rp_ready), // sink.ready
.sink_valid (mem_if_ddr2_emif_0_avl_agent_rp_valid), // .valid
.sink_data (mem_if_ddr2_emif_0_avl_agent_rp_data), // .data
.sink_startofpacket (mem_if_ddr2_emif_0_avl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (mem_if_ddr2_emif_0_avl_agent_rp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_router_004 router_004 (
.sink_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_router_005 router_005 (
.sink_ready (io_bridge_0_avalon_slave_0_agent_rp_ready), // sink.ready
.sink_valid (io_bridge_0_avalon_slave_0_agent_rp_valid), // .valid
.sink_data (io_bridge_0_avalon_slave_0_agent_rp_data), // .data
.sink_startofpacket (io_bridge_0_avalon_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (io_bridge_0_avalon_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_router_006 router_006 (
.sink_ready (pio_0_s1_agent_rp_ready), // sink.ready
.sink_valid (pio_0_s1_agent_rp_valid), // .valid
.sink_data (pio_0_s1_agent_rp_data), // .data
.sink_startofpacket (pio_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (pio_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (37),
.PKT_ADDR_L (9),
.PKT_BEGIN_BURST (59),
.PKT_BYTE_CNT_H (48),
.PKT_BYTE_CNT_L (44),
.PKT_BYTEEN_H (8),
.PKT_BYTEEN_L (8),
.PKT_BURST_SIZE_H (54),
.PKT_BURST_SIZE_L (52),
.PKT_BURST_TYPE_H (56),
.PKT_BURST_TYPE_L (55),
.PKT_BURSTWRAP_H (51),
.PKT_BURSTWRAP_L (49),
.PKT_TRANS_COMPRESSED_READ (38),
.PKT_TRANS_WRITE (40),
.PKT_TRANS_READ (41),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (78),
.ST_CHANNEL_W (4),
.OUT_BYTE_CNT_H (44),
.OUT_BURSTWRAP_H (51),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (7),
.BURSTWRAP_CONST_VALUE (7),
.ADAPTER_VERSION ("13.1")
) io_bridge_0_avalon_slave_0_burst_adapter (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // cr0.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_data), // .data
.sink0_channel (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_ready), // .ready
.source0_valid (io_bridge_0_avalon_slave_0_burst_adapter_source0_valid), // source0.valid
.source0_data (io_bridge_0_avalon_slave_0_burst_adapter_source0_data), // .data
.source0_channel (io_bridge_0_avalon_slave_0_burst_adapter_source0_channel), // .channel
.source0_startofpacket (io_bridge_0_avalon_slave_0_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (io_bridge_0_avalon_slave_0_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (io_bridge_0_avalon_slave_0_burst_adapter_source0_ready) // .ready
);
nios_mm_interconnect_0_cmd_demux cmd_demux (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_demux_001_src3_valid), // .valid
.src3_data (cmd_demux_001_src3_data), // .data
.src3_channel (cmd_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_demux_002_src0_valid), // .valid
.src0_data (cmd_demux_002_src0_data), // .data
.src0_channel (cmd_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_002_src1_ready), // src1.ready
.src1_valid (cmd_demux_002_src1_valid), // .valid
.src1_data (cmd_demux_002_src1_data), // .data
.src1_channel (cmd_demux_002_src1_channel), // .channel
.src1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_002_src1_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_mux cmd_mux (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_002_src0_ready), // sink2.ready
.sink2_valid (cmd_demux_002_src0_valid), // .valid
.sink2_channel (cmd_demux_002_src0_channel), // .channel
.sink2_data (cmd_demux_002_src0_data), // .data
.sink2_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src1_valid), // .valid
.sink0_channel (cmd_demux_001_src1_channel), // .channel
.sink0_data (cmd_demux_001_src1_data), // .data
.sink0_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_002_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_002_src1_valid), // .valid
.sink1_channel (cmd_demux_002_src1_channel), // .channel
.sink1_data (cmd_demux_002_src1_data), // .data
.sink1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_002_src1_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src2_valid), // .valid
.sink0_channel (cmd_demux_001_src2_channel), // .channel
.sink0_data (cmd_demux_001_src2_data), // .data
.sink0_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_mux_002 cmd_mux_003 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src3_valid), // .valid
.sink0_channel (cmd_demux_001_src3_channel), // .channel
.sink0_data (cmd_demux_001_src3_data), // .data
.sink0_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_rsp_demux rsp_demux (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_src2_ready), // src2.ready
.src2_valid (rsp_demux_src2_valid), // .valid
.src2_data (rsp_demux_src2_data), // .data
.src2_channel (rsp_demux_src2_channel), // .channel
.src2_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_src2_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_demux_002 rsp_demux_001 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_demux rsp_demux_002 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_channel), // .channel
.sink_data (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_data), // .data
.sink_startofpacket (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_cmd_demux rsp_demux_003 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_rsp_mux rsp_mux (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
nios_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_002_src_ready), // src.ready
.src_valid (rsp_mux_002_src_valid), // .valid
.src_data (rsp_mux_002_src_data), // .data
.src_channel (rsp_mux_002_src_channel), // .channel
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src2_ready), // sink0.ready
.sink0_valid (rsp_demux_src2_valid), // .valid
.sink0_channel (rsp_demux_src2_channel), // .channel
.sink0_data (rsp_demux_src2_data), // .data
.sink0_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src2_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (37),
.IN_PKT_ADDR_L (9),
.IN_PKT_DATA_H (7),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (8),
.IN_PKT_BYTEEN_L (8),
.IN_PKT_BYTE_CNT_H (48),
.IN_PKT_BYTE_CNT_L (44),
.IN_PKT_TRANS_COMPRESSED_READ (38),
.IN_PKT_TRANS_WRITE (40),
.IN_PKT_BURSTWRAP_H (51),
.IN_PKT_BURSTWRAP_L (49),
.IN_PKT_BURST_SIZE_H (54),
.IN_PKT_BURST_SIZE_L (52),
.IN_PKT_RESPONSE_STATUS_H (74),
.IN_PKT_RESPONSE_STATUS_L (73),
.IN_PKT_TRANS_EXCLUSIVE (43),
.IN_PKT_BURST_TYPE_H (56),
.IN_PKT_BURST_TYPE_L (55),
.IN_PKT_ORI_BURST_SIZE_L (75),
.IN_PKT_ORI_BURST_SIZE_H (77),
.IN_ST_DATA_W (78),
.OUT_PKT_ADDR_H (64),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (71),
.OUT_PKT_TRANS_COMPRESSED_READ (65),
.OUT_PKT_BURST_SIZE_H (81),
.OUT_PKT_BURST_SIZE_L (79),
.OUT_PKT_RESPONSE_STATUS_H (101),
.OUT_PKT_RESPONSE_STATUS_L (100),
.OUT_PKT_TRANS_EXCLUSIVE (70),
.OUT_PKT_BURST_TYPE_H (83),
.OUT_PKT_BURST_TYPE_L (82),
.OUT_PKT_ORI_BURST_SIZE_L (102),
.OUT_PKT_ORI_BURST_SIZE_H (104),
.OUT_ST_DATA_W (105),
.ST_CHANNEL_W (4),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) io_bridge_0_avalon_slave_0_rsp_width_adapter (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_005_src_valid), // sink.valid
.in_channel (router_005_src_channel), // .channel
.in_startofpacket (router_005_src_startofpacket), // .startofpacket
.in_endofpacket (router_005_src_endofpacket), // .endofpacket
.in_ready (router_005_src_ready), // .ready
.in_data (router_005_src_data), // .data
.out_endofpacket (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_data), // .data
.out_channel (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_channel), // .channel
.out_valid (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_valid), // .valid
.out_ready (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (io_bridge_0_avalon_slave_0_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (64),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (71),
.IN_PKT_TRANS_COMPRESSED_READ (65),
.IN_PKT_TRANS_WRITE (67),
.IN_PKT_BURSTWRAP_H (78),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (81),
.IN_PKT_BURST_SIZE_L (79),
.IN_PKT_RESPONSE_STATUS_H (101),
.IN_PKT_RESPONSE_STATUS_L (100),
.IN_PKT_TRANS_EXCLUSIVE (70),
.IN_PKT_BURST_TYPE_H (83),
.IN_PKT_BURST_TYPE_L (82),
.IN_PKT_ORI_BURST_SIZE_L (102),
.IN_PKT_ORI_BURST_SIZE_H (104),
.IN_ST_DATA_W (105),
.OUT_PKT_ADDR_H (37),
.OUT_PKT_ADDR_L (9),
.OUT_PKT_DATA_H (7),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (8),
.OUT_PKT_BYTEEN_L (8),
.OUT_PKT_BYTE_CNT_H (48),
.OUT_PKT_BYTE_CNT_L (44),
.OUT_PKT_TRANS_COMPRESSED_READ (38),
.OUT_PKT_BURST_SIZE_H (54),
.OUT_PKT_BURST_SIZE_L (52),
.OUT_PKT_RESPONSE_STATUS_H (74),
.OUT_PKT_RESPONSE_STATUS_L (73),
.OUT_PKT_TRANS_EXCLUSIVE (43),
.OUT_PKT_BURST_TYPE_H (56),
.OUT_PKT_BURST_TYPE_L (55),
.OUT_PKT_ORI_BURST_SIZE_L (75),
.OUT_PKT_ORI_BURST_SIZE_H (77),
.OUT_ST_DATA_W (78),
.ST_CHANNEL_W (4),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) io_bridge_0_avalon_slave_0_cmd_width_adapter (
.clk (mem_if_ddr2_emif_0_afi_clk_clk), // clk.clk
.reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_002_src_valid), // sink.valid
.in_channel (cmd_mux_002_src_channel), // .channel
.in_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_002_src_ready), // .ready
.in_data (cmd_mux_002_src_data), // .data
.out_endofpacket (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_data), // .data
.out_channel (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_channel), // .channel
.out_valid (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_valid), // .valid
.out_ready (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (io_bridge_0_avalon_slave_0_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
nios_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (mem_if_ddr2_emif_0_afi_clk_clk), // in_clk_0.clk
.in_rst_0_reset (mem_if_ddr2_emif_0_avl_translator_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (mem_if_ddr2_emif_0_avl_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
nios_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (mem_if_ddr2_emif_0_afi_clk_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
nios_mm_interconnect_0_avalon_st_adapter_002 #(
.inBitsPerSymbol (10),
.inUsePackets (0),
.inDataWidth (10),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (10),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (mem_if_ddr2_emif_0_afi_clk_clk), // in_clk_0.clk
.in_rst_0_reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (io_bridge_0_avalon_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
nios_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (mem_if_ddr2_emif_0_afi_clk_clk), // in_clk_0.clk
.in_rst_0_reset (mem32_to_avalon_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (pio_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (pio_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (pio_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
endmodule
|
module test;
reg [7:0] bus;
reg [7:0] skewed_bus;
integer delay0; initial delay0 = 4;
integer delay1; initial delay1 = 8;
integer delay2; initial delay2 = 12;
integer delay3; initial delay3 = 16;
integer delay4; initial delay4 = 20;
integer delay5; initial delay5 = 24;
integer delay6; initial delay6 = 28;
integer delay7; initial delay7 = 32;
/* model skew across the bus using transport delays */
always @( bus[0] )
begin
skewed_bus[0] <= #delay0 bus[0];
end
always @( bus[1] )
begin
skewed_bus[1] <= #delay1 bus[1];
end
always @( bus[2] )
begin
skewed_bus[2] <= #delay2 bus[2];
end
always @( bus[3] )
begin
skewed_bus[3] <= #delay3 bus[3];
end
always @( bus[4] )
begin
skewed_bus[4] <= #delay4 bus[4];
end
always @( bus[5] )
begin
skewed_bus[5] <= #delay5 bus[5];
end
always @( bus[6] )
begin
skewed_bus[6] <= #delay6 bus[6];
end
always @( bus[7] )
begin
skewed_bus[7] <= #delay7 bus[7];
end
initial
begin
bus = {8{1'b0}};
#4;
bus = 8'b00100100;
#4;
bus = 8'b10000001;
#4;
bus = 8'b00001001;
#4;
bus = 8'b01100011;
#4;
bus = 8'b00001101;
#4;
bus = 8'b10001101;
#4;
bus = 8'b01100101;
#4;
bus = 8'b00010010;
#4;
bus = 8'b00000001;
#4;
bus = 8'b00001101;
#4;
bus = 8'b01110110;
#4;
bus = 8'b00111101;
#4;
bus = 8'b11101101;
#4;
bus = 8'b10001100;
#4;
bus = 8'b11111001;
#4;
bus = 8'b11000110;
#4;
bus = 8'b11000101;
#4;
bus = 8'b10101010;
#4;
bus = 8'b11100101;
#4;
bus = 8'b01110111;
#4;
bus = 8'b00010010;
#4;
bus = 8'b10001111;
#4;
bus = 8'b11110010;
#4;
bus = 8'b11001110;
#4;
bus = 8'b11101000;
#4;
bus = 8'b11000101;
#4;
bus = 8'b01011100;
#4;
bus = 8'b10111101;
#4;
bus = 8'b00101101;
#4;
bus = 8'b01100101;
#4;
bus = 8'b01100011;
#4;
bus = 8'b00001010;
#4;
bus = 8'b10000000;
#4;
bus = 8'b00100000;
#4;
bus = 8'b10101010;
#4;
bus = 8'b10011101;
#4;
bus = 8'b10010110;
#4;
bus = 8'b00010011;
#4;
bus = 8'b00001101;
#4;
bus = 8'b01010011;
#4;
bus = 8'b01101011;
#4;
bus = 8'b11010101;
#4;
bus = 8'b00000010;
#4;
bus = 8'b10101110;
#4;
bus = 8'b00011101;
#4;
bus = 8'b11001111;
#4;
bus = 8'b00100011;
#4;
bus = 8'b00001010;
#4;
bus = 8'b11001010;
#4;
bus = 8'b00111100;
#4;
bus = 8'b11110010;
#4;
bus = 8'b10001010;
#4;
bus = 8'b01000001;
#4;
bus = 8'b11011000;
#4;
bus = 8'b01111000;
#4;
bus = 8'b10001001;
#4;
bus = 8'b11101011;
#4;
bus = 8'b10110110;
#4;
bus = 8'b11000110;
#4;
bus = 8'b10101110;
#4;
bus = 8'b10111100;
#4;
bus = 8'b00101010;
#4;
bus = 8'b00001011;
#4;
bus = 8'b01110001;
#4;
bus = 8'b10000101;
#4;
bus = 8'b01001111;
#4;
bus = 8'b00111011;
#4;
bus = 8'b00111010;
#4;
bus = 8'b01111110;
#4;
bus = 8'b00010101;
#4;
bus = 8'b11110001;
#4;
bus = 8'b11011001;
#4;
bus = 8'b01100010;
#4;
bus = 8'b01001100;
#4;
bus = 8'b10011111;
#4;
bus = 8'b10001111;
#4;
bus = 8'b11111000;
#4;
bus = 8'b10110111;
#4;
bus = 8'b10011111;
#4;
bus = 8'b01011100;
#4;
bus = 8'b01011011;
#4;
bus = 8'b10001001;
#4;
bus = 8'b01001001;
#4;
bus = 8'b11010000;
#4;
bus = 8'b11010111;
#4;
bus = 8'b01010001;
#4;
bus = 8'b10010110;
#4;
bus = 8'b00001100;
#4;
bus = 8'b11000010;
#4;
bus = 8'b11001000;
#4;
bus = 8'b01110111;
#4;
bus = 8'b00111101;
#4;
bus = 8'b00010010;
#4;
bus = 8'b01111110;
#4;
bus = 8'b01101101;
#4;
bus = 8'b00111001;
#4;
bus = 8'b00011111;
#4;
bus = 8'b11010011;
#4;
bus = 8'b10000101;
#4;
bus = 8'b01111000;
#4;
bus = 8'b01011011;
#4;
bus = 8'b01001001;
#4;
bus = 8'b00111111;
#4;
bus = 8'b00101010;
#4;
bus = 8'b01011000;
#4;
bus = 8'b10000110;
#4;
bus = 8'b10001110;
#4;
bus = 8'b10011100;
#4;
bus = 8'b11111010;
#4;
bus = 8'b00100110;
#4;
bus = 8'b01110011;
#4;
bus = 8'b10100011;
#4;
bus = 8'b00101111;
#4;
bus = 8'b10110011;
#4;
bus = 8'b01011111;
#4;
bus = 8'b01000100;
#4;
bus = 8'b11110111;
#4;
bus = 8'b11001011;
#4;
bus = 8'b11100110;
#4;
bus = 8'b01011010;
#4;
bus = 8'b00101001;
#4;
bus = 8'b11101101;
#4;
bus = 8'b11011010;
#4;
bus = 8'b01100101;
#4;
bus = 8'b10110101;
#4;
bus = 8'b11011111;
#4;
bus = 8'b01111001;
#4;
bus = 8'b01000100;
end
initial
begin
#2;
if (skewed_bus !== 8'bxxxxxxxx)
begin
$write("FAILED -- expected xxxxxxxx ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'bxxxxxxx0)
begin
$write("FAILED -- expected xxxxxxx0 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'bxxxxxx00)
begin
$write("FAILED -- expected xxxxxx00 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'bxxxxx001)
begin
$write("FAILED -- expected xxxxx001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'bxxxx0101)
begin
$write("FAILED -- expected xxxx0101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'bxxx00001)
begin
$write("FAILED -- expected xxx00001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'bxx000011)
begin
$write("FAILED -- expected xx000011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'bx0101001)
begin
$write("FAILED -- expected x0101001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00000101)
begin
$write("FAILED -- expected 00000101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00001100)
begin
$write("FAILED -- expected 00001100 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10101111)
begin
$write("FAILED -- expected 10101111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01000001)
begin
$write("FAILED -- expected 01000001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00000000)
begin
$write("FAILED -- expected 00000000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00110111)
begin
$write("FAILED -- expected 00110111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11001101)
begin
$write("FAILED -- expected 11001101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00000100)
begin
$write("FAILED -- expected 00000100 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00011101)
begin
$write("FAILED -- expected 00011101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00111100)
begin
$write("FAILED -- expected 00111100 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01101011)
begin
$write("FAILED -- expected 01101011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00101100)
begin
$write("FAILED -- expected 00101100 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01010111)
begin
$write("FAILED -- expected 01010111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10100001)
begin
$write("FAILED -- expected 10100001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11001110)
begin
$write("FAILED -- expected 11001110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11000111)
begin
$write("FAILED -- expected 11000111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11100010)
begin
$write("FAILED -- expected 11100010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10110110)
begin
$write("FAILED -- expected 10110110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11111010)
begin
$write("FAILED -- expected 11111010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11000101)
begin
$write("FAILED -- expected 11000101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00011000)
begin
$write("FAILED -- expected 00011000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00101101)
begin
$write("FAILED -- expected 00101101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11000101)
begin
$write("FAILED -- expected 11000101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11101101)
begin
$write("FAILED -- expected 11101101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11011101)
begin
$write("FAILED -- expected 11011101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11011110)
begin
$write("FAILED -- expected 11011110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11100010)
begin
$write("FAILED -- expected 11100010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00100000)
begin
$write("FAILED -- expected 00100000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10101000)
begin
$write("FAILED -- expected 10101000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01100011)
begin
$write("FAILED -- expected 01100011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01000000)
begin
$write("FAILED -- expected 01000000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00001111)
begin
$write("FAILED -- expected 00001111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00101111)
begin
$write("FAILED -- expected 00101111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10110001)
begin
$write("FAILED -- expected 10110001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00010111)
begin
$write("FAILED -- expected 00010111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10011011)
begin
$write("FAILED -- expected 10011011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10000000)
begin
$write("FAILED -- expected 10000000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10011110)
begin
$write("FAILED -- expected 10011110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00000011)
begin
$write("FAILED -- expected 00000011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01110101)
begin
$write("FAILED -- expected 01110101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01001111)
begin
$write("FAILED -- expected 01001111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01001110)
begin
$write("FAILED -- expected 01001110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10111010)
begin
$write("FAILED -- expected 10111010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00000010)
begin
$write("FAILED -- expected 00000010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10001000)
begin
$write("FAILED -- expected 10001000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01101110)
begin
$write("FAILED -- expected 01101110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10001011)
begin
$write("FAILED -- expected 10001011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00010000)
begin
$write("FAILED -- expected 00010000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01111000)
begin
$write("FAILED -- expected 01111000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10100001)
begin
$write("FAILED -- expected 10100001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01001001)
begin
$write("FAILED -- expected 01001001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10011010)
begin
$write("FAILED -- expected 10011010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11011010)
begin
$write("FAILED -- expected 11011010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01101110)
begin
$write("FAILED -- expected 01101110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11000110)
begin
$write("FAILED -- expected 11000110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00110100)
begin
$write("FAILED -- expected 00110100 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11101111)
begin
$write("FAILED -- expected 11101111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10001011)
begin
$write("FAILED -- expected 10001011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11111001)
begin
$write("FAILED -- expected 11111001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10101001)
begin
$write("FAILED -- expected 10101001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10100111)
begin
$write("FAILED -- expected 10100111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10010110)
begin
$write("FAILED -- expected 10010110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00101010)
begin
$write("FAILED -- expected 00101010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01001011)
begin
$write("FAILED -- expected 01001011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00011101)
begin
$write("FAILED -- expected 00011101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11111101)
begin
$write("FAILED -- expected 11111101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00110000)
begin
$write("FAILED -- expected 00110000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00110010)
begin
$write("FAILED -- expected 00110010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01011001)
begin
$write("FAILED -- expected 01011001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00110111)
begin
$write("FAILED -- expected 00110111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01001110)
begin
$write("FAILED -- expected 01001110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11101101)
begin
$write("FAILED -- expected 11101101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11011011)
begin
$write("FAILED -- expected 11011011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01001110)
begin
$write("FAILED -- expected 01001110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00010101)
begin
$write("FAILED -- expected 00010101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10111111)
begin
$write("FAILED -- expected 10111111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11111001)
begin
$write("FAILED -- expected 11111001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10011000)
begin
$write("FAILED -- expected 10011000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10011001)
begin
$write("FAILED -- expected 10011001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11001011)
begin
$write("FAILED -- expected 11001011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01000100)
begin
$write("FAILED -- expected 01000100 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00010010)
begin
$write("FAILED -- expected 00010010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11010100)
begin
$write("FAILED -- expected 11010100 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01010110)
begin
$write("FAILED -- expected 01010110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11011001)
begin
$write("FAILED -- expected 11011001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11000011)
begin
$write("FAILED -- expected 11000011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00001100)
begin
$write("FAILED -- expected 00001100 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10000110)
begin
$write("FAILED -- expected 10000110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01011011)
begin
$write("FAILED -- expected 01011011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11110101)
begin
$write("FAILED -- expected 11110101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11111101)
begin
$write("FAILED -- expected 11111101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00011011)
begin
$write("FAILED -- expected 00011011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00101111)
begin
$write("FAILED -- expected 00101111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01111000)
begin
$write("FAILED -- expected 01111000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01110101)
begin
$write("FAILED -- expected 01110101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00010011)
begin
$write("FAILED -- expected 00010011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00001001)
begin
$write("FAILED -- expected 00001001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01011010)
begin
$write("FAILED -- expected 01011010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10111110)
begin
$write("FAILED -- expected 10111110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11001000)
begin
$write("FAILED -- expected 11001000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01011010)
begin
$write("FAILED -- expected 01011010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01101110)
begin
$write("FAILED -- expected 01101110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00110100)
begin
$write("FAILED -- expected 00110100 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00001110)
begin
$write("FAILED -- expected 00001110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01001011)
begin
$write("FAILED -- expected 01001011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00011111)
begin
$write("FAILED -- expected 00011111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10010011)
begin
$write("FAILED -- expected 10010011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10100011)
begin
$write("FAILED -- expected 10100011 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11110111)
begin
$write("FAILED -- expected 11110111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10101010)
begin
$write("FAILED -- expected 10101010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01100101)
begin
$write("FAILED -- expected 01100101 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00111111)
begin
$write("FAILED -- expected 00111111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b10110110)
begin
$write("FAILED -- expected 10110110 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b00000010)
begin
$write("FAILED -- expected 00000010 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11011111)
begin
$write("FAILED -- expected 11011111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01100001)
begin
$write("FAILED -- expected 01100001 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b01001000)
begin
$write("FAILED -- expected 01001000 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11111111)
begin
$write("FAILED -- expected 11111111 ");
$display("received %b ", skewed_bus);
$finish;
end
#4;
if (skewed_bus !== 8'b11001001)
begin
$write("FAILED -- expected 11001001 ");
$display("received %b ", skewed_bus);
$finish;
end
$display("PASSED");
end
endmodule
|
// DESCRIPTION: Test that slice assignment overflows are handled correctly,
// i.e. that if you assign to a slice such that some of the bits you assign to
// do not actually exist, that those bits get correctly discarded.
// Issue #2803 existed in a number number of different codepaths in
// verilated.h and V3Expand.cpp. This test should cover all of these cases
// when run both with and without the -Ox flag to verilator.
// - Select offset constant, insert IData into CData
// - Select offset constant, insert IData into SData
// - Select offset constant, insert IData into IData
// - Select offset constant, insert QData into QData
// - Select offset constant, insert IData into WData within a word
// - Select offset constant, insert IData into WData crossing a word boundary
// - Select offset constant, insert IData into WData whole word insertion
// - Select offset constant, insert QData into WData
// - Select offset constant, insert WData into WData, several whole words
// - Select offset constant, insert WData into WData, starting at word-offset
// - Select offset constant, insert WData into WData, all other cases
// - Select offset is non-constant, destination is wide, bit-select width == 1
// - Select offset is non-constant, destination is wide, bit-select width != 1
// - Select offset is non-constant, destination is narrow
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by David Turner.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
// Non-constant offsets
reg varoffset1;
reg [6:0] varoffset2;
reg [6:0] varoffset3;
// Destinations for variable-offset assignments
reg [69:0] dstwide1;
reg [69:0] dstwide2;
reg [1:0] dstnarrow;
// Constant offsets
reg [6:0] constoffset;
// Destinations for constant-offset assignments
reg [2:0] dst_cdata;
reg [11:0] dst_sdata;
reg [29:0] dst_idata;
reg [59:0] dst_qdata;
reg [69:0] dst_wdata1; // assign idata within word
reg [69:0] dst_wdata2; // assign idata crossing word boundary
reg [69:0] dst_wdata3; // assign idata corresponding to whole word
reg [69:0] dst_wdata4; // assign qdata
reg [69:0] dst_wdata5; // assign wdata corresponding to several whole words
reg [69:0] dst_wdata6; // assign wdata starting at word-offset
reg [69:0] dst_wdata7; // assign wdata unaligned
always @(*) begin
// Non-constant select offset, destination narrow
dstnarrow = 2'd0;
dstnarrow[varoffset1 +: 2'd2] = 2'd2;
// Non-constant select offset, destination wide, width == 1
dstwide1 = 70'd0;
dstwide1[varoffset2 +: 1'd1] = 1'd1;
// Non-constant select offset, destination wide, width != 1
dstwide2 = 70'd0;
dstwide2[varoffset3 +: 2'd2] = 2'd2;
// Constant offset, IData into CData
constoffset = 7'd2;
dst_cdata = 3'd0;
dst_cdata[constoffset[0 +: 2] +: 3'd3] = 3'd6;
// Constant offset, IData into SData
constoffset = 7'd11;
dst_sdata = 12'd0;
dst_sdata[constoffset[0 +: 4] +: 2'd2] = 2'd2;
// Constant offset, IData into IData
constoffset = 7'd29;
dst_idata = 30'd0;
dst_idata[constoffset[0 +: 5] +: 2'd2] = 2'd2;
// Constant offset, QData into QData
constoffset = 7'd59;
dst_qdata = 60'd0;
dst_qdata[constoffset[0 +: 6] +: 2'd2] = 2'd2;
// Constant offset, IData into WData within word
constoffset = 7'd69;
dst_wdata1 = 70'd0;
dst_wdata1[constoffset +: 2'd2] = 2'd2;
// Constant offset, IData into WData crossing word boundary
constoffset = 7'd61;
dst_wdata2 = 70'd0;
dst_wdata2[constoffset +: 4'd10] = 10'd1 << 4'd9;
// Constant offset, IData into WData replacing a whole word
constoffset = 7'd64;
dst_wdata3 = 70'd0;
dst_wdata3[constoffset +: 6'd32] = 32'd1 << 3'd6;
// Constant offset, QData into WData
constoffset = 7'd31;
dst_wdata4 = 70'd0;
dst_wdata4[constoffset +: 7'd40] = 40'd1 << 7'd39;
// Constant offset, WData into WData replacing whole words
constoffset = 7'd32;
dst_wdata5 = 70'd0;
dst_wdata5[constoffset +: 7'd64] = 64'd1 << 7'd38;
// Constant offset, WData into WData offset word aligned
constoffset = 7'd32;
dst_wdata6 = 70'd0;
dst_wdata6[constoffset +: 7'd40] = 40'd1 << 7'd38;
// Constant offset, WData into WData unaligned
constoffset = 7'd1;
dst_wdata7 = 70'd0;
dst_wdata7[constoffset +: 7'd70] = 70'd1 << 7'd69;
end
// Test loop
always @ (posedge clk) begin
// State machine to avoid verilator constant-folding offset
if (cyc == 0) begin
// Initialisation
varoffset1 <= 1'd0;
varoffset2 <= 7'd0;
varoffset3 <= 7'd0;
end else if (cyc == 1) begin
// Variable offsets set here to avoid verilator constant folding
varoffset1 <= 1'd1;
varoffset2 <= 7'd70;
varoffset3 <= 7'd69;
end else if (cyc == 2) begin
// Check all destinations are 0
$write("dstwide1 = %23d, downshifted = %23d\n", dstwide1, dstwide1 >> 1);
$write("dstwide2 = %23d, downshifted = %23d\n", dstwide2, dstwide2 >> 1);
$write("dstnarrow = %23d, downshifted = %23d\n", dstnarrow, dstnarrow >> 1);
$write("dst_cdata = %23d, downshifted = %23d\n", dst_cdata, dst_cdata >> 1);
$write("dst_sdata = %23d, downshifted = %23d\n", dst_sdata, dst_sdata >> 1);
$write("dst_idata = %23d, downshifted = %23d\n", dst_idata, dst_idata >> 1);
$write("dst_qdata = %23d, downshifted = %23d\n", dst_qdata, dst_qdata >> 1);
$write("dst_wdata1 = %23d, downshifted = %23d\n", dst_wdata1, dst_wdata1 >> 1);
$write("dst_wdata2 = %23d, downshifted = %23d\n", dst_wdata2, dst_wdata2 >> 1);
$write("dst_wdata3 = %23d, downshifted = %23d\n", dst_wdata3, dst_wdata3 >> 1);
$write("dst_wdata4 = %23d, downshifted = %23d\n", dst_wdata4, dst_wdata4 >> 1);
$write("dst_wdata5 = %23d, downshifted = %23d\n", dst_wdata5, dst_wdata5 >> 1);
$write("dst_wdata6 = %23d, downshifted = %23d\n", dst_wdata6, dst_wdata6 >> 1);
$write("dst_wdata7 = %23d, downshifted = %23d\n", dst_wdata7, dst_wdata7 >> 1);
if (dstwide1 !== 70'd0 || (dstwide1 >> 1) !== 70'd0) $stop;
if (dstwide2 !== 70'd0 || (dstwide2 >> 1) !== 70'd0) $stop;
if (dstnarrow !== 2'd0 || (dstnarrow >> 1) !== 2'd0) $stop;
if (dst_cdata !== 3'd0 || (dst_cdata >> 1) !== 3'd0) $stop;
if (dst_sdata !== 12'd0 || (dst_sdata >> 1) !== 12'd0) $stop;
if (dst_idata !== 30'd0 || (dst_idata >> 1) !== 30'd0) $stop;
if (dst_qdata !== 60'd0 || (dst_qdata >> 1) !== 60'd0) $stop;
if (dst_wdata1 !== 70'd0 || (dst_wdata1 >> 1) !== 70'd0) $stop;
if (dst_wdata2 !== 70'd0 || (dst_wdata2 >> 1) !== 70'd0) $stop;
if (dst_wdata3 !== 70'd0 || (dst_wdata3 >> 1) !== 70'd0) $stop;
if (dst_wdata4 !== 70'd0 || (dst_wdata4 >> 1) !== 70'd0) $stop;
if (dst_wdata5 !== 70'd0 || (dst_wdata5 >> 1) !== 70'd0) $stop;
if (dst_wdata6 !== 70'd0 || (dst_wdata6 >> 1) !== 70'd0) $stop;
if (dst_wdata7 !== 70'd0 || (dst_wdata7 >> 1) !== 70'd0) $stop;
end else begin
$write("*-* All Finished *-*\n");
$finish;
end
cyc <= cyc + 1;
end
endmodule
|
/**********************************************************************
date:2016/3/26
designer:ZhaiShaoMin
project:ring network multicore
module name:tb_arbiter_OUT_rep
module function: figure out what's wrong with it
***********************************************************************/
`timescale 1ns/1ps
module tb_arbiter_for_OUT_rep();
//inputs
reg clk;
reg rst;
reg OUT_rep_rdy;
reg v_dc_rep;
reg v_mem_rep;
reg [15:0] dc_rep_flit;
reg [15:0] mem_rep_flit;
reg [1:0] dc_rep_ctrl;
reg [1:0] mem_rep_ctrl;
//output
wire ack_OUT_rep;
wire ack_dc_rep;
wire ack_mem_rep;
wire [1:0] select; // select 1/2
parameter SCflurep_cmd=5'b11100;
parameter nackrep_cmd=5'b10101;
//instante design
arbiter_for_OUT_rep uut (//input
.clk(clk),
.rst(rst),
.OUT_rep_rdy(OUT_rep_rdy),
.v_dc_rep(v_dc_rep),
.v_mem_rep(v_mem_rep),
.dc_rep_flit(dc_rep_flit),
.mem_rep_flit(mem_rep_flit),
.dc_rep_ctrl(dc_rep_ctrl),
.mem_rep_ctrl(mem_rep_ctrl),
//output
.ack_OUT_rep(ack_OUT_rep),
.ack_dc_rep(ack_dc_rep),
.ack_mem_rep(ack_mem_rep),
.select(select) // select 1/2
);
integer log_file;
//define task for cmp actual outputs and exp outputs
task cmp_outputs;
input exp_ack_OUT_rep;
input exp_ack_dc_rep;
input exp_ack_mem_rep;
input [1:0]exp_select;
begin
$display("Time:%t",$time);
$fdisplay (log_file, "Time: %t", $time);
if (ack_OUT_rep != exp_ack_OUT_rep)
begin
$display("ERROR: Invalid ack_OUT_rep\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_OUT_rep,ack_OUT_rep);
$fdisplay(log_file,"ERROR: Invalid ack_OUT_rep\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_OUT_rep,ack_OUT_rep);
end
if (ack_dc_rep != exp_ack_dc_rep)
begin
$display("ERROR: Invalid ack_dc_rep\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_dc_rep,ack_dc_rep);
$fdisplay(log_file,"ERROR: Invalid ack_dc_rep\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_dc_rep,ack_dc_rep);
end
if (ack_mem_rep != exp_ack_mem_rep)
begin
$display("ERROR: Invalid ack_mem_rep\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_mem_rep,ack_mem_rep);
$fdisplay(log_file,"ERROR: Invalid ack_mem_rep\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_mem_rep,ack_mem_rep);
end
if (select != exp_select)
begin
$display("ERROR: Invalid select\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_select,select);
$fdisplay(log_file,"ERROR: Invalid select\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_select,select);
end
if((ack_OUT_rep == exp_ack_OUT_rep)&&
(ack_dc_rep == exp_ack_dc_rep)&&
(ack_mem_rep == exp_ack_mem_rep)&&
(select == exp_select))
begin
$display("passed,test");
$fdisplay(log_file,"passed,test");
end
end
endtask
//initial inputs
initial begin
clk=1'b0;
rst=1'b1;
OUT_rep_rdy=1'b0;
v_dc_rep=1'b0;
v_mem_rep=1'b0;
dc_rep_flit=16'h0000;
mem_rep_flit=16'h0000;
dc_rep_ctrl=2'b00;
mem_rep_ctrl=2'b00;
log_file=$fopen("log_arbiter_for_OUT_rep.txt");
end
`define clk_step #14;
always #7 clk=~clk;
initial begin
// actural test arbiter_for_OUT_rep TEST//
`clk_step
$display("TEST BEGIN.......");
$fdisplay(log_file,"TEST BEGIN.......");
rst=1'b0;
`clk_step
////////////////////////////////////////////////////
//First case both v_dc_rep and v_mem_rep are valid//
$display("First case both v_dc_rep and v_mem_rep are valid");
$fdisplay(log_file,"First case both v_dc_rep and v_mem_rep are valid");
$display("First try");
$fdisplay(log_file,"First try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b0;//don't care
v_dc_rep=1'b1;
v_mem_rep=1'b1;
dc_rep_flit=16'habcd;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b0,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b0,//ack_mem_rep//
2'b00//select//
);
`clk_step
$display("2nd try ");
$fdisplay(log_file,"2nd try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b1;
v_mem_rep=1'b1;
dc_rep_flit=16'habcd;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b10//select//
);
`clk_step
$display("3rd try ");
$fdisplay(log_file,"3rd try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b1;
v_mem_rep=1'b1;
dc_rep_flit=16'habcd;
mem_rep_flit=16'h5678;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b10;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b10//select//
);
`clk_step
$display("4th try ");
$fdisplay(log_file,"4th try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b1;
v_mem_rep=1'b1;
dc_rep_flit=16'habcd;
mem_rep_flit=16'h2016;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b10;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b10//select//
);
/*.....*/
//assuming iit's time for tail flit of mem msg
`clk_step
$display("3rd try ");
$fdisplay(log_file,"3rd try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b1;
v_mem_rep=1'b1;
dc_rep_flit=16'habcd;
mem_rep_flit=16'h5678;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b11;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b10//select//
);
`clk_step
//////////////////////////////////////////////////
//2nd case both v_dc_rep and v_mem_rep are valid
$display("2nd case both v_dc_rep and v_mem_rep are valid ,but it's tme for dc");
$fdisplay(log_file,"2nd case both v_dc_rep and v_mem_rep are valid,but it's tme for dc");
$display("First try");
$fdisplay(log_file,"First try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b0;//don't care
v_dc_rep=1'b1;
v_mem_rep=1'b1;
dc_rep_flit=16'habcd;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b0,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b0,//ack_mem_rep//
2'b00//select//
);
`clk_step
$display("2nd try ");
$fdisplay(log_file,"2nd try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b1;
v_mem_rep=1'b1;
dc_rep_flit=16'habcd;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b1,//ack_dc_rep//
1'b0,//ack_mem_rep//
2'b01//select//
);
`clk_step
$display("3rd try ");
$fdisplay(log_file,"3rd try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b1;
v_mem_rep=1'b1;
dc_rep_flit=16'h5678;
mem_rep_flit=16'h5678;
dc_rep_ctrl=2'b10;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b01//select//
);
`clk_step
$display("4th try ");
$fdisplay(log_file,"4th try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b1;
v_mem_rep=1'b1;
dc_rep_flit=16'habcd;
mem_rep_flit=16'h2016;
dc_rep_ctrl=2'b10;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b1,//ack_dc_rep//
1'b0,//ack_mem_rep//
2'b01//select//
);
/*.....*/
//assuming iit's time for tail flit of mem msg
`clk_step
$display("3rd try ");
$fdisplay(log_file,"3rd try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b1;
v_mem_rep=1'b1;
dc_rep_flit=16'h2016;
mem_rep_flit=16'h5678;
dc_rep_ctrl=2'b11;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b1,//ack_dc_rep//
1'b0,//ack_mem_rep//
2'b01//select//
);
`clk_step
////////////////////////////////////////////////
/// 3rd case only v_dc_rep is valid
$display("3rd case only v_dc_rep is valid");
$fdisplay(log_file,"3rd case only v_dc_rep is valid");
$display("First try");
$fdisplay(log_file,"First try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b0;//don't care
v_dc_rep=1'b1;
v_mem_rep=1'b0;
dc_rep_flit=16'h2016;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b00;
cmp_outputs(1'b0,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b0,//ack_mem_rep//
2'b00//select//
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b1;
v_mem_rep=1'b0;
// make it scflushrep which is only one flit long to test another path
//no need to gen it ,because it imposible for dc
dc_rep_flit=16'h2016;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b00;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b1,//ack_dc_rep//
1'b0,//ack_mem_rep//
2'b01//select//
);
/*.....*/
//let's assum that there will be the tail flit of dc msg
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b1;
v_mem_rep=1'b0;
dc_rep_flit=16'h2016;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b11;
mem_rep_ctrl=2'b00;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b1,//ack_dc_rep//
1'b0,//ack_mem_rep//
2'b01//select//
);
/* //just test whether state jump to idle
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b1;
v_mem_rep=1'b0;
dc_rep_flit=16'h2016;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b00;
cmp_outputs(1'b0,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b0,//ack_mem_rep//
2'b00//select//
);
*/
/////////////////////////////////////////////
///4th case only v_mem_rep is valid
`clk_step
$display("3rd case only v_mem_rep is valid");
$fdisplay(log_file,"3rd case only v_mem_rep is valid");
$display("First try");
$fdisplay(log_file,"First try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;//don't care
v_dc_rep=1'b0;
v_mem_rep=1'b1;
dc_rep_flit=16'h2016;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b0,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b0,//ack_mem_rep//
2'b00//select//
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b0;
v_mem_rep=1'b1;
dc_rep_flit=16'h2016;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b10//select//
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b0;
v_mem_rep=1'b1;
dc_rep_flit=16'h0328;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b10;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b10//select//
);
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b0;
v_mem_rep=1'b1;
dc_rep_flit=16'hc0de;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b11;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b10//select//
);
/* `clk_step
$display("last try,just a test for whether jump to idle");
$fdisplay(log_file,"last try,just a test for whether jump to idle");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b0;
v_mem_rep=1'b1;
dc_rep_flit=16'hc0de;
mem_rep_flit=16'h1234;
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b11;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b10//select//
);
*/
/////////////////////////////////////////////
///5th case only v_mem_rep is valid and is SCflushrep
`clk_step
$display("5th case :only v_mem_rep is valid");
$fdisplay(log_file,"5th case :only v_mem_rep is valid");
$display("First try");
$fdisplay(log_file,"First try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;//don't care
v_dc_rep=1'b0;
v_mem_rep=1'b1;
dc_rep_flit=16'h2016;
mem_rep_flit={6'b110110,SCflurep_cmd,5'b00000};
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b0,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b0,//ack_mem_rep//
2'b00//select//
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b0;
v_mem_rep=1'b1;
dc_rep_flit=16'h2016;
mem_rep_flit={6'b110110,SCflurep_cmd,5'b00000};
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b10//select//
);
/* `clk_step
$display("last try,just a test for whether jump to idle");
$fdisplay(log_file,"last try,just a test for whether jump to idle");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b0;
v_mem_rep=1'b1;
dc_rep_flit=16'h2016;
mem_rep_flit={6'b110110,SCflurep_cmd,5'b00000};
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b10//select//
);
*/
/////////////////////////////////////////////
///6th case only v_mem_rep is valid and is nackrep
`clk_step
//nackrep_msg for test
$display("6th case :only v_mem_rep is valid");
$fdisplay(log_file,"6th case :only v_mem_rep is valid");
$display("First try");
$fdisplay(log_file,"First try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;//don't care
v_dc_rep=1'b0;
v_mem_rep=1'b1;
dc_rep_flit=16'h2016;
mem_rep_flit={6'b110110,nackrep_cmd,5'b00000};
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b0,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b0,//ack_mem_rep//
2'b00//select//
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b0;
v_mem_rep=1'b1;
dc_rep_flit=16'h2016;
mem_rep_flit={6'b110110,nackrep_cmd,5'b00000};
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b10//select//
);
/* `clk_step
$display("last try,just a test for whether jump to idle");
$fdisplay(log_file,"last try,just a test for whether jump to idle");
//it also means that both flits are head flit
OUT_rep_rdy=1'b1;
v_dc_rep=1'b0;
v_mem_rep=1'b1;
dc_rep_flit=16'h2016;
mem_rep_flit={6'b110110,nackrep_cmd,5'b00000};
dc_rep_ctrl=2'b01;
mem_rep_ctrl=2'b01;
cmp_outputs(1'b1,//ack_OUT_rep//
1'b0,//ack_dc_rep//
1'b1,//ack_mem_rep//
2'b10//select//
);
*/
`clk_step
$display("FINISH TEST!");
$fdisplay(log_file,"FINISH TEST!");
$stop;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Avalon memory interface functional model
// File : borealis_stim.v
// Author : Frank Bruno
// Created : 10-19-2010
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description : This models a memory based on the avalon interface to
// speed up simulations.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
module fast_mem_tasks;
// These tasks are for 128 bit version of the memory, 16 BYTES only
/**************************************************************************/
/* Behavioral tasks to move data to or from the RAMs */
task ram_fill32;
// This tasks initialize display buffer memory by writing requested number
// of 32 bit words of data with a initial location at start_addr.
// Start address is specifed for a 32bit word. (IT is not page_address as
// for EDO, and it is NOT byte address). The task can fill 8MB display
// buffer switching automaticaly to the proper 4MB bank.
// Data is placed in memories assuming an upgradable 2MB@64 ->4MB@128 board
// The amount of data written to the buffer is the same for 64 bit bus and
// 128 bit bus if the number of words passed to the task stays the same.
input [31:0] start_adr; // address in 32bit words
input [31:0] words;
input [31:0] data;
reg [31:0] i;
begin
// for (i = start_adr; i < (start_adr+words)<<2; i = i + 1) begin
for (i = start_adr; i < (start_adr+words); i = i + 1) begin
// U0.U_DDR3.mem[i] = data[i[1:0]*8+:8];
U0.U_DDR3.mem[{i, 2'b00}] = data[7:0];
U0.U_DDR3.mem[{i, 2'b01}] = data[15:8];
U0.U_DDR3.mem[{i, 2'b10}] = data[23:16];
U0.U_DDR3.mem[{i, 2'b11}] = data[31:24];
end
end
endtask // ram_fill32
/**************************************************************************/
task ram_loadh;
input [22:0] start_adr;
input [127:0] datar;
input [15:0] ben;
reg [31:0] indxw; // pointer to SGRAM buffer
begin
indxw = start_adr<<4;
for (int i = 0; i < 16; i++) begin
// $display("Writing %h: %h", indxw, datar[i[3:0]*8+:8]);
U0.U_DDR3.mem[indxw] = datar[i[3:0]*8+:8];
indxw++;
// #100 $stop;
end
// Read next line
//status_in = $fscanf(file_in, "%h\n", datar);
end
endtask // ram_loadh
/**************************************************************************/
task ram_floadh;
// This task loads a requested number of 128bit words of data from
// a file and places it in the display SGRAM buffer starting at start_addr.
// The start addr is in 32bit words.
// Written by Jack and _copied_ by hk for sgram
input [8*64:1] image_file;
input [21:0] start_adr; //start address in memory [32bit words]
input [16:0] lines; /* number of 128bit words to be read from temp
* buffer/into SGRAM models.
* In most cases this will be
* number of lines in a file ,
* But it can be smaller */
reg [127:0] datar; // data read from temp buffer
reg [31:0] indxw; // pointer to SGRAM buffer
integer file_in; // File pointer
integer status_in; // Status of file
begin
$display ("reading file %s", image_file);
file_in = $fopen(image_file, "r");
$display ("loading image into SGRAM RAM DISPLAY BUFFER ");
// indxw = start_adr<<4;
indxw = start_adr<<2;
while (!$feof(file_in)) begin
status_in = $fscanf(file_in, "%h\n", datar);
for (int i = 0; i < 16; i++) begin
// $display("Writing %h: %h", indxw, datar[i[3:0]*8+:8]);
U0.U_DDR3.mem[indxw] = datar[i[3:0]*8+:8];
indxw++;
// #100 $stop;
end
// Read next line
//status_in = $fscanf(file_in, "%h\n", datar);
end
end
endtask // ram_floadh
/**************************************************************************/
task ram_floadh2;
// This task loads a requested number of 128bit words of data from
// a file and places it in the display SGRAM buffer starting at start_addr.
// The start addr is in 32bit words.
input [8*64:1] image_file;
reg [127:0] datar; // data read from temp buffer
reg [22:0] adr; //start address in memory [32bit words]
reg [31:0] indxw; // pointer to SGRAM buffer
reg [15:0] mask;
integer file_in; // File pointer
integer status_in; // Status of file
begin
$display ("reading file %s", image_file);
file_in = $fopen(image_file, "r");
$display ("loading data into RAM\n");
while (!$feof(file_in)) begin
status_in = $fscanf(file_in, "%h %h %h\n", adr, datar, mask);
indxw = adr<<4;
for (int i = 0; i < 16; i++) begin
// $display("Writing %h: %h", indxw, datar[i[3:0]*8+:8]);
if (~mask[i]) U0.U_DDR3.mem[indxw] = datar[i[3:0]*8+:8];
indxw++;
// #100 $stop;
end
// Read next line
//status_in = $fscanf(file_in, "%h\n", datar);
end
end
endtask // ram_floadh
/**************************************************************************/
task ram_floadh_32_to_565;
// This task loads a requested number of 128bit words of data from
// a file and places it in the display SGRAM buffer starting at start_addr.
// The start addr is in 32bit words.
// Written by Jack and _copied_ by hk for sgram
input [8*64:1] image_file;
input [21:0] start_adr; //start address in memory [32bit words]
input [16:0] lines; /* number of 128bit words to be read from temp
* buffer/into SGRAM models.
* In most cases this will be
* number of lines in a file ,
* But it can be smaller */
reg [255:0] datar; // data read from temp buffer
reg [127:0] datar1; // data read from temp buffer
reg [31:0] indxw; // pointer to SGRAM buffer
integer file_in; // File pointer
integer status_in; // Status of file
begin
$display ("reading file %s", image_file);
file_in = $fopen(image_file, "r");
status_in = $fscanf(file_in, "%h\n", datar[127:0]);
status_in = $fscanf(file_in, "%h\n", datar[255:128]);
datar1[15:0] = {datar[(0*32)+23:(0*32)+19], datar[(0*32)+15:(0*32)+10], datar[(0*32)+7:(0*32)+3]};
datar1[31:16] = {datar[(1*32)+23:(1*32)+19], datar[(1*32)+15:(1*32)+10], datar[(1*32)+7:(1*32)+3]};
datar1[47:32] = {datar[(2*32)+23:(2*32)+19], datar[(2*32)+15:(2*32)+10], datar[(2*32)+7:(2*32)+3]};
datar1[63:48] = {datar[(3*32)+23:(3*32)+19], datar[(3*32)+15:(3*32)+10], datar[(3*32)+7:(3*32)+3]};
datar1[79:64] = {datar[(4*32)+23:(4*32)+19], datar[(4*32)+15:(4*32)+10], datar[(4*32)+7:(4*32)+3]};
datar1[95:80] = {datar[(5*32)+23:(5*32)+19], datar[(5*32)+15:(5*32)+10], datar[(5*32)+7:(5*32)+3]};
datar1[111:96] = {datar[(6*32)+23:(6*32)+19], datar[(6*32)+15:(6*32)+10], datar[(6*32)+7:(6*32)+3]};
datar1[127:112] = {datar[(7*32)+23:(7*32)+19], datar[(7*32)+15:(7*32)+10], datar[(7*32)+7:(7*32)+3]};
$display ("loading image into SGRAM RAM DISPLAY BUFFER ");
// indxw = start_adr<<4;
indxw = start_adr<<2;
while (!$feof(file_in)) begin
for (int i = 0; i < 16; i++) begin
// $display("Writing %h: %h", indxw, datar[i[3:0]*8+:8]);
U0.U_DDR3.mem[indxw] = datar1[i[3:0]*8+:8];
indxw++;
// #100 $stop;
end
// Read next line
status_in = $fscanf(file_in, "%h\n", datar[127:0]);
status_in = $fscanf(file_in, "%h\n", datar[255:128]);
datar1[15:0] = {datar[(0*32)+23:(0*32)+19], datar[(0*32)+15:(0*32)+10], datar[(0*32)+7:(0*32)+3]};
datar1[31:16] = {datar[(1*32)+23:(1*32)+19], datar[(1*32)+15:(1*32)+10], datar[(1*32)+7:(1*32)+3]};
datar1[47:32] = {datar[(2*32)+23:(2*32)+19], datar[(2*32)+15:(2*32)+10], datar[(2*32)+7:(2*32)+3]};
datar1[63:48] = {datar[(3*32)+23:(3*32)+19], datar[(3*32)+15:(3*32)+10], datar[(3*32)+7:(3*32)+3]};
datar1[79:64] = {datar[(4*32)+23:(4*32)+19], datar[(4*32)+15:(4*32)+10], datar[(4*32)+7:(4*32)+3]};
datar1[95:80] = {datar[(5*32)+23:(5*32)+19], datar[(5*32)+15:(5*32)+10], datar[(5*32)+7:(5*32)+3]};
datar1[111:96] = {datar[(6*32)+23:(6*32)+19], datar[(6*32)+15:(6*32)+10], datar[(6*32)+7:(6*32)+3]};
datar1[127:112] = {datar[(7*32)+23:(7*32)+19], datar[(7*32)+15:(7*32)+10], datar[(7*32)+7:(7*32)+3]};
end
end
endtask // ram_floadh
task vga_floadh;
// This task loads a VGA memory image into the I128 Memory system
input [8*64:1] image_file;
input [21:0] start_adr; // start address in memory [32bit words]
input [15:0] lines; /* number of 128bit words to be read from temp
* buffer/into SGRAM models.
* In most cases this will be number of lines
* in a file , But it can be smaller */
reg [32:0] tempbuff[0:131071]; // TWO meg !!, always loaded from addr=0
reg [127:0] datar; // data read from temp buffer
reg [16:0] indxr; // pointer to temp buffer
reg [1:0] indxwr;// Index write
reg [31:0] dataw; // data writen into SGRAM
reg [21:0] indxw; // pointer to SGRAM buffer
begin
$display ("reading file %s", image_file);
$readmemh(image_file, tempbuff); //load temp. buffer from a file
$display ("loading image into SGRAM RAM DISPLAY BUFFER ");
indxw = start_adr;
for (indxr = 0; indxr < lines; indxr = indxr + 1) begin
datar = tempbuff[indxr];
for (indxwr = 0; indxwr < 2; indxwr = indxwr + 1) begin
VR.ram_fill32(indxw, 1, datar);
indxw = indxw + 1;
end
end
end
endtask // ram_floadh
/**************************************************************************/
task save_fbmp;
//This task saves a bitmap in DISPLAY buffer to a file.
input [31:0] bitmap_address; // Byte address in DISPLAY buffer
input [15:0] x_size; /* X size (in pixels) of the image
* in the output file */
input [15:0] y_size; /* Y size (in pixels) of the image
* in the output file */
input [240:1] file_name; // name of the output file
input [31:0] i_pitch; /* Image pitch (in bytes) in the display
* buffer
* This may be set in local tasks
* arbitrarily or passed to this task
* as the result of testing of e.g.
* xx_DPTCH register, or other internal
* registers. */
input [1:0] i_psize; /* Image bpp in the display buffer
* This may be set in local tasks
* arbitrarily or passed to this task
* as the result of testing of e.g.
* xx_PSIZE register or other internal
* registers */
integer index;
integer x;
integer y;
integer pageindex;
integer dump_file;
integer data_file;
integer pitch;
integer bpp;
reg [15:0] temp_mem;
reg [32:0] data;
reg [7:0] c8;
reg [15:0] c16;
reg [31:0] c32;
integer i;
reg [127:0] data_0, data_1, data_2, data_3, data_4, data_5, data_6,
data_7;
begin
$display("Saving file '%s' ...", file_name);
dump_file = $fopen(file_name);
data_file = $fopen("data.bmp");
pitch = i_pitch ;
$display("pitch = %h ", pitch);
bpp = 8;
if (i_psize==2'b10)
bpp = 32;
else if (i_psize==2'b01 | i_psize==2'b11)
bpp = 16;
if (bpp == 8) index = bitmap_address;
else if (bpp == 16) index = bitmap_address >> 1;
else if (bpp == 32) index = bitmap_address >> 2;
// Write Bitmap Header information to file.
$fwrite(dump_file,"\nVerilog Simulation Data\n\n");
$fwrite(dump_file,"BitmapDX\t%d\n", x_size);
$fwrite(dump_file,"BitmapDY\t%d\n", y_size);
$fwrite(dump_file,"BitsPerPixel\t%d\n", bpp);
$fwrite(dump_file,"WidthBytes\t%d\n\n", x_size * bpp/8);
$fwrite(dump_file,"X\tY\tPixelValue\n");
for (y = 0; y < y_size; y = y + 1) begin
for (x = 0; x < x_size; x = x + 1) begin
pageindex = (index + x);
//if (bpp == 8) pageindex = (index + x);
//else if (bpp == 16) pageindex = (index + (x * 2));
//else if (bpp == 32) pageindex = (index + (x * 4));
// $display ("Direct Read %h", pageindex[20:0]);
if (bpp == 8) begin
c8 = U0.U_DDR3.mem[pageindex];
$display("Saving from %h", pageindex);
$fwrite(dump_file,"%d\t%d\t0x%0h\n", x, y, c8);
$fwrite(data_file,"%c", c8);
end else if (bpp == 16) begin
c16 = {U0.U_DDR3.mem[{pageindex,1'b1}],
U0.U_DDR3.mem[{pageindex,1'b0}]};
$fwrite(dump_file,"%d\t%d\t0x%0h\n", x, y, c16);
$fwrite(data_file,"%c", c16[7:0]);
$fwrite(data_file,"%c", c16[15:8]);
end else if (bpp == 32) begin
data = {U0.U_DDR3.mem[{pageindex,2'b11}],
U0.U_DDR3.mem[{pageindex,2'b10}],
U0.U_DDR3.mem[{pageindex,2'b01}],
U0.U_DDR3.mem[{pageindex,2'b00}]};
$fwrite(dump_file,"%d\t%d\t0x%0h\n", x, y, data);
$fwrite(data_file,"%c", data[7:0]);
$fwrite(data_file,"%c", data[15:8]);
$fwrite(data_file,"%c", data[23:16]);
$fwrite(data_file,"%c", data[31:24]);
$display("Saving %h from %h", U0.U_DDR3.mem[pageindex], pageindex>>2);
end
//$display("saving address %h,: %h", pageindex[20:2], c8);
end // for (x = 0; x < x_size; x = x + 1)
//index = index + pitch;
if (bpp == 8) index = index + pitch;
else if (bpp == 16)index = index + (pitch >> 1);
else index = index + (pitch >> 2);
end // for (y = 0; y < y_size; y = y + 1)
$fclose(dump_file);
$fclose(data_file);
$display("Done saving file '%s' ...", file_name);
end
endtask // save_fbmp
/****************************************************************/
/* For future reference, these are the commands availible */
/* for dynamic memory allocation. */
// $damem_read("MEM",adr,data_reg);
// $damem_write("MEM",adr,data_val);
// $damem_initb("MEM","file_name",addr_from,addr_to); //formatted for the readmemb system task.
// $damem_inith("MEM","file_name",addr_from,addr_to); //formatted for the readmemh system task.
/****************************************************************/
task rr;
input [19:0] start_adr;
input [19:0] words;
reg [31:0] i;
reg [127:0] ram_reg;
begin
$display("start addr= %h quan words= %h",start_adr,i);
for(i=start_adr;i<(start_adr+words*4);i=i+4) begin
ram_reg = {U0.U_DDR3.mem[{start_adr[19:0]+3, 2'b0}],
U0.U_DDR3.mem[{start_adr[19:0]+2, 2'b0}],
U0.U_DDR3.mem[{start_adr[19:0]+1, 2'b0}],
U0.U_DDR3.mem[{start_adr[19:0], 2'b0}]};
$display("addr= %h data= %h",i,ram_reg);
end
end
endtask
/****************************************************************/
task ram_dump; // modif
input [19:0] start_adr;
input [19:0] words;
input [80:1] file_name;
reg [31:0] i;
reg [127:0] ram_reg;
integer dump_file;
begin
dump_file = $fopen(file_name);
for(i=start_adr;i<(start_adr+words*4);i=i+4) begin
ram_reg = {U0.U_DDR3.mem[{start_adr[19:0]+3, 2'b0}],
U0.U_DDR3.mem[{start_adr[19:0]+2, 2'b0}],
U0.U_DDR3.mem[{start_adr[19:0]+1, 2'b0}],
U0.U_DDR3.mem[{start_adr[19:0], 2'b0}]};
$fdisplay(dump_file,"addr= %h data= %h",i,ram_reg);
end
$fclose(dump_file);
end
endtask
/****************************************************************/
task ram_fill; // modif
input [19:0] start_adr;
input [19:0] words;
input [31:0] data;
reg [31:0] i;
begin
for(i=start_adr;i<(start_adr+words*4);i=i+1) begin
U0.U_DDR3.mem[{start_adr[19:0], 2'b0}] = data;
end
end
endtask
/****************************************************************/
task wide_fill; // modif
input [17:0] start_adr;
input [17:0] words;
input [128:0] data;
reg [31:0] i, j;
reg [127:0] temp_0, temp_1, temp_2, temp_3;
begin
for (i=start_adr;i<(start_adr+words);i=i+4) begin
for (j = 0; j < 4; j = j + 1) begin
U0.U_DDR3.mem[{start_adr[17:0], 2'b0}] = data[31:0];
U0.U_DDR3.mem[{start_adr[17:0]+1, 2'b0}] = data[63:32];
U0.U_DDR3.mem[{start_adr[17:0]+2, 2'b0}] = data[95:64];
U0.U_DDR3.mem[{start_adr[17:0]+3, 2'b0}] = data[127:96];
end
end // for (i=start_adr;i<(start_adr+words);i=i+1)
end
endtask
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRTN_TB_V
`define SKY130_FD_SC_HS__DLRTN_TB_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlrtn.v"
module top();
// Inputs are registered
reg RESET_B;
reg D;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 RESET_B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 RESET_B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 RESET_B = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 RESET_B = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg GATE_N;
initial
begin
GATE_N = 1'b0;
end
always
begin
#5 GATE_N = ~GATE_N;
end
sky130_fd_sc_hs__dlrtn dut (.RESET_B(RESET_B), .D(D), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE_N(GATE_N));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRTN_TB_V
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconstant:1.1
// IP Revision: 1
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlconstant_0_1 (
dout
);
output wire [7-1 : 0] dout;
xlconstant #(
.CONST_VAL(7'd0),
.CONST_WIDTH(7)
) inst (
.dout(dout)
);
endmodule
|
/*!
* <b>Module:</b>sata_ahci_top
* @file sata_ahci_top.v
* @date 2015-07-11
* @author Alexey
*
* @brief Top of the AHCI implementation of the host adapter
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* sata_ahci_top.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sata_ahci_top.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
/*
* Takes commands from axi iface as a slave, transfers data with another axi iface as a master
*/
module sata_ahci_top#(
parameter PREFETCH_ALWAYS = 0,
// parameter READ_REG_LATENCY = 2, // 0 if reg_rdata is available with reg_re/reg_addr, 2 with re/regen
// parameter READ_CT_LATENCY = 1, // 0 if ct_rdata is available with reg_re/reg_addr, 2 with re/regen
parameter ADDRESS_BITS = 10, // number of memory address bits - now fixed. Low half - RO/RW/RWC,RW1 (2-cycle write), 2-nd just RW (single-cycle)
`ifdef USE_DATASCOPE
parameter DATASCOPE_START_BIT = 14, // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
parameter DATASCOPE_POST_MEAS = 256, // 16, // number of measurements to perform after event
`endif
parameter HBA_RESET_BITS = 9, // duration of HBA reset in aclk periods (9: ~10usec)
parameter RESET_TO_FIRST_ACCESS = 1, // keep port reset until first R/W any register by software
parameter BITS_TO_START_XMIT = 6, // wait H2D FIFO to have 1 << BITS_TO_START_XMIT to start FIS transmission (or all FIS fits)
parameter DATA_BYTE_WIDTH = 4,
parameter ELASTIC_DEPTH = 4, // 4, //5, With 4/7 got infrequent overflows!
parameter ELASTIC_OFFSET = 7, // 5 //10
parameter FREQ_METER_WIDTH = 16
)(
output wire sata_clk,
output wire sata_rst,
input wire arst, // extrst,
// reliable clock to source drp and cpll lock det circuits
input wire reliable_clk,
input wire hclk,
/*
* Commands interface
*/
input wire ACLK, // AXI PS Master GP1 Clock , input
input wire ARESETN, // AXI PS Master GP1 Reset, output // @SuppressThisWarning VEditor unused (arst instead)
// AXI PS Master GP1: Read Address
input wire [31:0] ARADDR, // AXI PS Master GP1 ARADDR[31:0], output
input wire ARVALID, // AXI PS Master GP1 ARVALID, output
output wire ARREADY, // AXI PS Master GP1 ARREADY, input
input wire [11:0] ARID, // AXI PS Master GP1 ARID[11:0], output
input wire [3:0] ARLEN, // AXI PS Master GP1 ARLEN[3:0], output
input wire [1:0] ARSIZE, // AXI PS Master GP1 ARSIZE[1:0], output
input wire [1:0] ARBURST, // AXI PS Master GP1 ARBURST[1:0], output
// AXI PS Master GP1: Read Data
output wire [31:0] RDATA, // AXI PS Master GP1 RDATA[31:0], input
output wire RVALID, // AXI PS Master GP1 RVALID, input
input wire RREADY, // AXI PS Master GP1 RREADY, output
output wire [11:0] RID, // AXI PS Master GP1 RID[11:0], input
output wire RLAST, // AXI PS Master GP1 RLAST, input
output wire [1:0] RRESP, // AXI PS Master GP1 RRESP[1:0], input
// AXI PS Master GP1: Write Address
input wire [31:0] AWADDR, // AXI PS Master GP1 AWADDR[31:0], output
input wire AWVALID, // AXI PS Master GP1 AWVALID, output
output wire AWREADY, // AXI PS Master GP1 AWREADY, input
input wire [11:0] AWID, // AXI PS Master GP1 AWID[11:0], output
input wire [3:0] AWLEN, // AXI PS Master GP1 AWLEN[3:0], outpu:t
input wire [1:0] AWSIZE, // AXI PS Master GP1 AWSIZE[1:0], output
input wire [1:0] AWBURST, // AXI PS Master GP1 AWBURST[1:0], output
// AXI PS Master GP1: Write Data
input wire [31:0] WDATA, // AXI PS Master GP1 WDATA[31:0], output
input wire WVALID, // AXI PS Master GP1 WVALID, output
output wire WREADY, // AXI PS Master GP1 WREADY, input
input wire [11:0] WID, // AXI PS Master GP1 WID[11:0], output
input wire WLAST, // AXI PS Master GP1 WLAST, output
input wire [3:0] WSTRB, // AXI PS Master GP1 WSTRB[3:0], output
// AXI PS Master GP1: Write response
output wire BVALID, // AXI PS Master GP1 BVALID, input
input wire BREADY, // AXI PS Master GP1 BREADY, output
output wire [11:0] BID, // AXI PS Master GP1 BID[11:0], input
output wire [1:0] BRESP, // AXI PS Master GP1 BRESP[1:0], input
/*
* Data interface
*/
output wire [31:0] afi_awaddr,
output wire afi_awvalid,
input wire afi_awready,
output wire [5:0] afi_awid,
output wire [1:0] afi_awlock,
output wire [3:0] afi_awcache,
output wire [2:0] afi_awprot,
output wire [3:0] afi_awlen,
output wire [1:0] afi_awsize,
output wire [1:0] afi_awburst,
output wire [3:0] afi_awqos,
// write data
output wire [63:0] afi_wdata,
output wire afi_wvalid,
input wire afi_wready,
output wire [5:0] afi_wid,
output wire afi_wlast,
output wire [7:0] afi_wstrb,
// write response
input wire afi_bvalid,
output wire afi_bready,
input wire [5:0] afi_bid,
input wire [1:0] afi_bresp,
// PL extra (non-AXI) signals
input wire [7:0] afi_wcount,
input wire [5:0] afi_wacount,
output wire afi_wrissuecap1en,
// AXI_HP signals - read channel
// read address
output wire [31:0] afi_araddr,
output wire afi_arvalid,
input wire afi_arready,
output wire [5:0] afi_arid,
output wire [1:0] afi_arlock,
output wire [3:0] afi_arcache,
output wire [2:0] afi_arprot,
output wire [3:0] afi_arlen,
output wire [1:0] afi_arsize,
output wire [1:0] afi_arburst,
output wire [3:0] afi_arqos,
// read data
input wire [63:0] afi_rdata,
input wire afi_rvalid,
output wire afi_rready,
input wire [5:0] afi_rid,
input wire afi_rlast,
input wire [1:0] afi_rresp,
// PL extra (non-AXI) signals
input wire [7:0] afi_rcount,
input wire [2:0] afi_racount,
output wire afi_rdissuecap1en,
output wire irq,
/*
* PHY
*/
output wire TXN,
output wire TXP,
input wire RXN,
input wire RXP,
input wire EXTCLK_P,
input wire EXTCLK_N
);
// wire sata_clk;
// wire sata_rst;
wire hba_arst; // @S uppressThisWarning VEditor unused
wire port_arst; // @SuppressThisWarning VEditor unused
wire port_arst_any;
// wire exrst = port_arst_any; // now both hba_arst and port_arst are the same?
wire exrst = port_arst_any || hba_arst; // now both hba_arst and port_arst are the same (only difference in fsm)
// Data/type FIFO, host -> device
// Data System memory or FIS -> device
wire [31:0] h2d_data; // 32-bit data from the system memory to HBA (dma data)
wire [ 1:0] h2d_type; // 0 - data, 1 - FIS head, 2 - FIS END (make FIS_Last?)
wire h2d_valid; // output register full
wire h2d_ready; // send FIFO has room for data (>= 8? dwords)
// Data/type FIFO, device -> host
wire [31:0] d2h_data; // FIFO output data
wire [ 1:0] d2h_type; // 0 - data, 1 - FIS head, 2 - R_OK, 3 - R_ERR
wire d2h_valid; // Data available from the transport layer in FIFO
wire d2h_many; // Multiple DWORDs available from the transport layer in FIFO
wire d2h_ready; // This module or DMA consumes DWORD
// communication with transport/link/phys layers
// wire phy_rst; // frome phy, as a response to hba_arst || port_arst. It is deasserted when clock is stable
wire [ 1:0] phy_speed; // 0 - not ready, 1..3 - negotiated speed
wire xmit_ok; // FIS transmission acknowledged OK
wire xmit_err; // Error during sending of a FIS
wire syncesc_recv; // These two inputs interrupt transmit
wire pcmd_st_cleared; // bit was cleared by software
wire syncesc_send; // Send sync escape
wire syncesc_send_done; // "SYNC escape until the interface is quiescent..."
wire comreset_send; // Not possible yet?
wire cominit_got;
wire set_offline; // electrically idle
wire x_rdy_collision; // X_RDY/X_RDY collision on interface
wire send_R_OK; // Should it be originated in this layer SM?
wire send_R_ERR;
// additional errors from SATA layers (single-clock pulses):
wire serr_DT; // RWC: Transport state transition error
wire serr_DS; // RWC: Link sequence error
wire serr_DH; // RWC: Handshake Error (i.e. Device got CRC error)
wire serr_DC; // RWC: CRC error in Link layer
wire serr_DB; // RWC: 10B to 8B decode error
wire serr_DW; // RWC: COMMWAKE signal was detected
wire serr_DI; // RWC: PHY Internal Error
// sirq_PRC,
wire serr_EE; // RWC: Internal error (such as elastic buffer overflow or primitive mis-alignment)
wire serr_EP; // RWC: Protocol Error - a violation of SATA protocol detected
wire serr_EC; // RWC: Persistent Communication or Data Integrity Error
wire serr_ET; // RWC: Transient Data Integrity Error (error not recovered by the interface)
wire serr_EM; // RWC: Communication between the device and host was lost but re-established
wire serr_EI; // RWC: Recovered Data integrity Error
// additional control signals for SATA layers
wire [3:0] sctl_ipm; // Interface power management transitions allowed
wire [3:0] sctl_spd; // Interface maximal speed
reg [2:0] nhrst_r;
wire hrst = !nhrst_r[2];
wire debug_link_send_data; // @sata clk - last symbol was data output
wire debug_link_dmatp; // @clk (sata clk) - received CODE_DMATP
wire [FREQ_METER_WIDTH-1:0] xclk_period;
`ifdef USE_DATASCOPE
// Datascope interface (write to memory that can be software-read)
wire datascope_clk;
wire [ADDRESS_BITS-1:0] datascope_waddr;
wire datascope_we;
wire [31:0] datascope_di;
`endif
`ifdef USE_DRP
wire drp_en;
wire drp_we;
wire [14:0] drp_addr;
wire [15:0] drp_di;
wire drp_rdy;
wire [15:0] drp_do;
`endif
wire [31:0] debug_phy;
wire [31:0] debug_link;
always @ (posedge hclk or posedge arst) begin
if (arst) nhrst_r <= 0;
else nhrst_r <= (nhrst_r << 1) | 1;
end
ahci_top #(
.PREFETCH_ALWAYS (PREFETCH_ALWAYS),
// .READ_REG_LATENCY (READ_REG_LATENCY),
// .READ_CT_LATENCY (READ_CT_LATENCY),
.ADDRESS_BITS (ADDRESS_BITS),
.HBA_RESET_BITS (HBA_RESET_BITS),
.RESET_TO_FIRST_ACCESS (RESET_TO_FIRST_ACCESS),
.FREQ_METER_WIDTH (FREQ_METER_WIDTH)
) ahci_top_i (
.aclk (ACLK), // input
.arst (arst), // input
.mclk (sata_clk), // input
.mrst (sata_rst), // input
.hba_arst (hba_arst), // output
.port_arst (port_arst), // output
.port_arst_any (port_arst_any), // port0 async set by software and by arst
.hclk (hclk), // input
.hrst (hrst), // input
.awaddr (AWADDR), // input[31:0]
.awvalid (AWVALID), // input
.awready (AWREADY), // output
.awid (AWID), // input[11:0]
.awlen (AWLEN), // input[3:0]
.awsize (AWSIZE), // input[1:0]
.awburst (AWBURST), // input[1:0]
.wdata (WDATA), // input[31:0]
.wvalid (WVALID), // input
.wready (WREADY), // output
.wid (WID), // input[11:0]
.wlast (WLAST), // input
.wstb (WSTRB), // input[3:0]
.bvalid (BVALID), // output
.bready (BREADY), // input
.bid (BID), // output[11:0]
.bresp (BRESP), // output[1:0]
.araddr (ARADDR), // input[31:0]
.arvalid (ARVALID), // input
.arready (ARREADY), // output
.arid (ARID), // input[11:0]
.arlen (ARLEN), // input[3:0]
.arsize (ARSIZE), // input[1:0]
.arburst (ARBURST), // input[1:0]
.rdata (RDATA), // output[31:0]
.rvalid (RVALID), // output
.rready (RREADY), // input
.rid (RID), // output[11:0]
.rlast (RLAST), // output
.rresp (RRESP), // output[1:0]
.afi_awaddr (afi_awaddr), // output[31:0]
.afi_awvalid (afi_awvalid), // output
.afi_awready (afi_awready), // input
.afi_awid (afi_awid), // output[5:0]
.afi_awlock (afi_awlock), // output[1:0]
.afi_awcache (afi_awcache), // output[3:0]
.afi_awprot (afi_awprot), // output[2:0]
.afi_awlen (afi_awlen), // output[3:0]
.afi_awsize (afi_awsize), // output[1:0]
.afi_awburst (afi_awburst), // output[1:0]
.afi_awqos (afi_awqos), // output[3:0]
.afi_wdata (afi_wdata), // output[63:0]
.afi_wvalid (afi_wvalid), // output
.afi_wready (afi_wready), // input
.afi_wid (afi_wid), // output[5:0]
.afi_wlast (afi_wlast), // output
.afi_wstrb (afi_wstrb), // output[7:0]
.afi_bvalid (afi_bvalid), // input
.afi_bready (afi_bready), // output
.afi_bid (afi_bid), // input[5:0]
.afi_bresp (afi_bresp), // input[1:0]
.afi_wcount (afi_wcount), // input[7:0]
.afi_wacount (afi_wacount), // input[5:0]
.afi_wrissuecap1en (afi_wrissuecap1en), // output
.afi_araddr (afi_araddr), // output[31:0]
.afi_arvalid (afi_arvalid), // output
.afi_arready (afi_arready), // input
.afi_arid (afi_arid), // output[5:0]
.afi_arlock (afi_arlock), // output[1:0]
.afi_arcache (afi_arcache), // output[3:0]
.afi_arprot (afi_arprot), // output[2:0]
.afi_arlen (afi_arlen), // output[3:0]
.afi_arsize (afi_arsize), // output[1:0]
.afi_arburst (afi_arburst), // output[1:0]
.afi_arqos (afi_arqos), // output[3:0]
.afi_rdata (afi_rdata), // input[63:0]
.afi_rvalid (afi_rvalid), // input
.afi_rready (afi_rready), // output
.afi_rid (afi_rid), // input[5:0]
.afi_rlast (afi_rlast), // input
.afi_rresp (afi_rresp), // input[1:0]
.afi_rcount (afi_rcount), // input[7:0]
.afi_racount (afi_racount), // input[2:0]
.afi_rdissuecap1en (afi_rdissuecap1en), // output
.h2d_data (h2d_data), // output[31:0]
.h2d_type (h2d_type), // output[1:0]
.h2d_valid (h2d_valid), // output
.h2d_ready (h2d_ready), // input
.d2h_data (d2h_data), // input[31:0]
.d2h_type (d2h_type), // input[1:0]
.d2h_valid (d2h_valid), // input
.d2h_many (d2h_many), // input
.d2h_ready (d2h_ready), // output
.phy_ready (phy_speed), // input[1:0]
.xmit_ok (xmit_ok), // input
.xmit_err (xmit_err), // input
.syncesc_recv (syncesc_recv), // input
.pcmd_st_cleared (pcmd_st_cleared), // output
.syncesc_send (syncesc_send), // output
.syncesc_send_done (syncesc_send_done), // input
.comreset_send (comreset_send), // output
.cominit_got (cominit_got), // input
.set_offline (set_offline), // output
.x_rdy_collision (x_rdy_collision), // input
.send_R_OK (send_R_OK), // output
.send_R_ERR (send_R_ERR), // output
.serr_DT (serr_DT), // input
.serr_DS (serr_DS), // input
.serr_DH (serr_DH), // input
.serr_DC (serr_DC), // input
.serr_DB (serr_DB), // input
.serr_DW (serr_DW), // input
.serr_DI (serr_DI), // input
.serr_EE (serr_EE), // input
.serr_EP (serr_EP), // input
.serr_EC (serr_EC), // input
.serr_ET (serr_ET), // input
.serr_EM (serr_EM), // input
.serr_EI (serr_EI), // input
.sctl_ipm (sctl_ipm), // output[3:0]
.sctl_spd (sctl_spd), // output[3:0]
.irq (irq), // output
.debug_link_send_data (debug_link_send_data), // input @posedge sata_clk - last symbol was data output (to count sent out)
.debug_link_dmatp (debug_link_dmatp), // link received DMATp from device
`ifdef USE_DATASCOPE
.datascope1_clk (datascope_clk), // input
.datascope1_waddr (datascope_waddr), // input[9:0]
.datascope1_we (datascope_we), // input
.datascope1_di (datascope_di), // input[31:0]
`endif
`ifdef USE_DRP
.drp_en (drp_en), // output reg
.drp_we (drp_we), // output reg
.drp_addr (drp_addr), // output[14:0] reg
.drp_di (drp_di), // output[15:0] reg
.drp_rdy (drp_rdy), // input
.drp_do (drp_do), // input[15:0]
`endif
.xclk_period (xclk_period), // input[11:0]
.debug_in_phy (debug_phy), // input[31:0]
.debug_in_link (debug_link) // input[31:0]
);
ahci_sata_layers #(
`ifdef USE_DATASCOPE
.ADDRESS_BITS (ADDRESS_BITS), // for datascope
.DATASCOPE_START_BIT (DATASCOPE_START_BIT), // bit of DRP "other_control" to start recording after 0->1 (needs DRP)
.DATASCOPE_POST_MEAS (DATASCOPE_POST_MEAS), // number of measurements to perform after event
`endif
.BITS_TO_START_XMIT (BITS_TO_START_XMIT),
.DATA_BYTE_WIDTH (DATA_BYTE_WIDTH),
.ELASTIC_DEPTH (ELASTIC_DEPTH),
.ELASTIC_OFFSET (ELASTIC_OFFSET),
.FREQ_METER_WIDTH (FREQ_METER_WIDTH)
) ahci_sata_layers_i (
.exrst (exrst), // input
.reliable_clk (reliable_clk), // input
.rst (sata_rst), // output
.clk (sata_clk), // output
.h2d_data (h2d_data), // input[31:0]
.h2d_mask (2'h3), //h2d_mask), // input[1:0]
.h2d_type (h2d_type), // input[1:0]
.h2d_valid (h2d_valid), // input
.h2d_ready (h2d_ready), // output
.d2h_data (d2h_data), // output[31:0]
.d2h_mask (), // 2h_mask), // output[1:0]
.d2h_type (d2h_type), // output[1:0]
.d2h_valid (d2h_valid), // output
.d2h_many (d2h_many), // output
.d2h_ready (d2h_ready), // input
.phy_speed (phy_speed), // output[1:0]
.gtx_ready(), // output
.xmit_ok (xmit_ok), // output
.xmit_err (xmit_err), // output
.x_rdy_collision (x_rdy_collision), // output
.syncesc_recv (syncesc_recv), // output
.pcmd_st_cleared (pcmd_st_cleared), // input
.syncesc_send (syncesc_send), // input
.syncesc_send_done (syncesc_send_done), // output
.comreset_send (comreset_send), // input
.cominit_got (cominit_got), // output
.set_offline (set_offline), // input
.send_R_OK (send_R_OK), // input
.send_R_ERR (send_R_ERR), // input
.serr_DT (serr_DT), // output
.serr_DS (serr_DS), // output
.serr_DH (serr_DH), // output
.serr_DC (serr_DC), // output
.serr_DB (serr_DB), // output
.serr_DW (serr_DW), // output
.serr_DI (serr_DI), // output
.serr_EE (serr_EE), // output
.serr_EP (serr_EP), // output
.serr_EC (serr_EC), // output
.serr_ET (serr_ET), // output
.serr_EM (serr_EM), // output
.serr_EI (serr_EI), // output
.sctl_ipm (sctl_ipm), // input[3:0]
.sctl_spd (sctl_spd), // input[3:0]
.extclk_p (EXTCLK_P), // input wire
.extclk_n (EXTCLK_N), // input wire
.txp_out (TXP), // output wire
.txn_out (TXN), // output wire
.rxp_in (RXP), // input wire
.rxn_in (RXN), // input wire
.debug_is_data (debug_link_send_data), //output @clk (sata clk) - last symbol was data output
.debug_dmatp (debug_link_dmatp), // @clk (sata clk) - received CODE_DMATP
`ifdef USE_DATASCOPE
.datascope_clk (datascope_clk), // output
.datascope_waddr (datascope_waddr), // output[9:0]
.datascope_we (datascope_we), // output
.datascope_di (datascope_di), // output[31:0]
`endif
`ifdef USE_DRP
.drp_rst (arst), // input
.drp_clk (ACLK), // input
.drp_en (drp_en), // input
.drp_we (drp_we), // input
.drp_addr (drp_addr), // input[14:0]
.drp_di (drp_di), // input[15:0]
.drp_rdy (drp_rdy), // output
.drp_do (drp_do), // output[15:0]
`endif
.xclk_period (xclk_period), // output[11:0]
.debug_phy (debug_phy), // output[31:0]
.debug_link (debug_link) // output[31:0]
,.hclk(hclk)
);
endmodule
|
(** * Types: Type Systems *)
Require Export Smallstep.
Ltac inv H := inversion H; subst; clear H.
Hint Constructors multi.
(** Our next major topic is _type systems_ -- static program
analyses that classify expressions according to the "shapes" of
their results. We'll begin with a typed version of a very simple
language with just booleans and numbers, to introduce the basic
ideas of types, typing rules, and the fundamental theorems about
type systems: _type preservation_ and _progress_. Then we'll move
on to the _simply typed lambda-calculus_, which lives at the core
of every modern functional programming language (including
Coq). *)
(* ###################################################################### *)
(** * Typed Arithmetic Expressions *)
(** To motivate the discussion of type systems, let's begin as
usual with an extremely simple toy language. We want it to have
the potential for programs "going wrong" because of runtime type
errors, so we need something a tiny bit more complex than the
language of constants and addition that we used in chapter
[Smallstep]: a single kind of data (just numbers) is too simple,
but just two kinds (numbers and booleans) already gives us enough
material to tell an interesting story.
The language definition is completely routine. The only thing to
notice is that we are _not_ using the [asnum]/[aslist] trick that
we used in chapter [HoareList] to make all the operations total by
forcibly coercing the arguments to [+] (for example) into numbers.
Instead, we simply let terms get stuck if they try to use an
operator with the wrong kind of operands: the [step] relation
doesn't relate them to anything. *)
(* ###################################################################### *)
(** ** Syntax *)
(** Informally:
t ::= true
| false
| if t then t else t
| 0
| succ t
| pred t
| iszero t
Formally:
*)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| tzero : tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tiszero : tm -> tm.
(** _Values_ are [true], [false], and numeric values... *)
Inductive bvalue : tm -> Prop :=
| bv_true : bvalue ttrue
| bv_false : bvalue tfalse.
Inductive nvalue : tm -> Prop :=
| nv_zero : nvalue tzero
| nv_succ : forall t, nvalue t -> nvalue (tsucc t).
Definition value (t:tm) := bvalue t \/ nvalue t.
Hint Constructors bvalue nvalue.
Hint Unfold value.
Hint Unfold extend.
(* ###################################################################### *)
(** ** Operational Semantics *)
(** Informally: *)
(**
------------------------------ (ST_IfTrue)
if true then t1 else t2 ==> t1
------------------------------- (ST_IfFalse)
if false then t1 else t2 ==> t2
t1 ==> t1'
------------------------- (ST_If)
if t1 then t2 else t3 ==>
if t1' then t2 else t3
t1 ==> t1'
-------------------- (ST_Succ)
succ t1 ==> succ t1'
------------ (ST_PredZero)
pred 0 ==> 0
numeric value v1
--------------------- (ST_PredSucc)
pred (succ v1) ==> v1
t1 ==> t1'
-------------------- (ST_Pred)
pred t1 ==> pred t1'
----------------- (ST_IszeroZero)
iszero 0 ==> true
numeric value v1
-------------------------- (ST_IszeroSucc)
iszero (succ v1) ==> false
t1 ==> t1'
------------------------ (ST_Iszero)
iszero t1 ==> iszero t1'
*)
(** Formally: *)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Succ : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_PredZero :
(tpred tzero) ==> tzero
| ST_PredSucc : forall t1,
nvalue t1 ->
(tpred (tsucc t1)) ==> t1
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_IszeroZero :
(tiszero tzero) ==> ttrue
| ST_IszeroSucc : forall t1,
nvalue t1 ->
(tiszero (tsucc t1)) ==> tfalse
| ST_Iszero : forall t1 t1',
t1 ==> t1' ->
(tiszero t1) ==> (tiszero t1')
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredZero"
| Case_aux c "ST_PredSucc" | Case_aux c "ST_Pred"
| Case_aux c "ST_IszeroZero" | Case_aux c "ST_IszeroSucc"
| Case_aux c "ST_Iszero" ].
Hint Constructors step.
(** Notice that the [step] relation doesn't care about whether
expressions make global sense -- it just checks that the operation
in the _next_ reduction step is being applied to the right kinds
of operands.
For example, the term [succ true] (i.e., [tsucc ttrue] in the
formal syntax) cannot take a step, but the almost as obviously
nonsensical term
succ (if true then true else true)
can take a step (once, before becoming stuck). *)
(* ###################################################################### *)
(** ** Normal Forms and Values *)
(** The first interesting thing about the [step] relation in this
language is that the strong progress theorem from the Smallstep
chapter fails! That is, there are terms that are normal
forms (they can't take a step) but not values (because we have not
included them in our definition of possible "results of
evaluation"). Such terms are _stuck_. *)
Notation step_normal_form := (normal_form step).
Definition stuck (t:tm) : Prop :=
step_normal_form t /\ ~ value t.
Hint Unfold stuck.
(** **** Exercise: 2 stars (some_term_is_stuck) *)
Example some_term_is_stuck :
exists t, stuck t.
Proof.
exists (tif tzero tzero tzero).
split.
unfold normal_form, not.
intros.
inv H.
inv H0.
inv H4.
unfold not.
intros.
inv H.
inv H0.
inv H0.
Qed.
(** However, although values and normal forms are not the same in this
language, the former set is included in the latter. This is
important because it shows we did not accidentally define things
so that some value could still take a step. *)
(** **** Exercise: 3 stars, advanced (value_is_nf) *)
(** Hint: You will reach a point in this proof where you need to
use an induction to reason about a term that is known to be a
numeric value. This induction can be performed either over the
term itself or over the evidence that it is a numeric value. The
proof goes through in either case, but you will find that one way
is quite a bit shorter than the other. For the sake of the
exercise, try to complete the proof both ways. *)
Lemma value_is_nf : forall t,
value t -> step_normal_form t.
Proof.
intros.
inv H;
unfold normal_form, not;
intros;
inv H. inv H0. inv H1. inv H1.
generalize dependent x.
induction H0; intros.
inv H1.
inv H1.
generalize (IHnvalue t1'); intro T.
apply T. auto.
Qed.
(** **** Exercise: 3 stars, optional (step_deterministic) *)
(** Using [value_is_nf], we can show that the [step] relation is
also deterministic... *)
Ltac find_eqn :=
match goal with
H1: forall x, ?P x -> ?L = ?R, H2: ?P ?X |- _ =>
rewrite (H1 X H2) in *
end.
Ltac rwinv H1 H2 := rewrite H1 in H2; inv H2.
Ltac find_rwinv :=
match goal with
H1: ?E = true, H2: ?E = false |- _ => rwinv H1 H2
end.
Ltac value_pre_fail :=
match goal with
H1: ?E ==> _, H2: value ?E |- _ => inv H1
end.
Ltac value_pre :=
match goal with
| H1: ttrue ==> _ |- _ => inv H1
| H1: tfalse ==> _ |- _ => inv H1
| H1: tzero ==> _ |- _ => inv H1
(* | H1: tsucc ?t ==> _ |- _ => inv H1 *)
(*
| H1: ?t ==> _, H2: nvalue ?t |- _ => inv H2; inv H1
| H1: ?t ==> _, H2: bvalue ?t |- _ => inv H2; inv H1
*)
end.
(*
Ltac value_inv :=
match goal with
| H1: nvalue ?t |- _ => inv H1
| H1: bvalue ?t |- _ => inv H1
end.
*)
(*
Hint Constructors nvalue.
Hint Constructors bvalue.
*)
(*
Ltac apply_subst :=
match goal with
| H1 : forall x, ?P x -> ?L = ?R, H2: ?P
*)
(*
Lemma nvalue_succ_pred : (forall t1 t2,
nvalue t1 ->
tsucc t1 ==> t2 ->
t1 = tpred t2).
Proof.
(*
unfold not; intros.
generalize (H tzero (tsucc tzero)); intro T.
assert(G : nvalue tzero) by constructor.
apply T in G. inv G.
inv G.
*)
intros. generalize dependent t2.
induction H; intros.
inv H0. inv H1.
inv H0. generalize (IHnvalue t1' H2); intro T.
rewrite T.
inv H2.
inv H.
(*
tsucc (tpred (tsucc t1'0)) = tpred (tsucc (tsucc t1'0))
t1 : tm
H : nvalue t1
t1' : tm
H1 : tsucc t1 ==> t1'
============================
t1 = tpred t1'
*)
(* pred -> not nvalue *)
Qed.
*)
Lemma nvalue_not_succ : forall t1 t2,
(*
~(nvalue t1 ->
tsucc t1 ==> t2).
*)
nvalue t1 ->
(* ~(tsucc t1 ==> t2). *)
tsucc t1 ==> t2 ->
False.
Proof.
(* unfold not. *)
induction t1; intros; inv H.
inv H0; inv H1.
inv H0.
generalize (IHt1 t1' H2 H1); intro T. auto.
Qed.
Theorem step_deterministic:
deterministic step.
Proof with eauto.
unfold deterministic.
intros.
generalize dependent y2.
induction H; intros st H2; inv H2;
auto; try value_pre; try find_eqn; try value_pre; auto.
assert(G : False) by (apply (nvalue_not_succ t1 t1' H H1)). inv G.
assert(G : False) by (apply (nvalue_not_succ st t1' H1 H)). inv G.
eapply nvalue_not_succ in H. inv H. eauto.
eapply nvalue_not_succ in H1. inv H1. eauto.
(*
apply nvalue_succ_pred; auto.
symmetry. apply nvalue_succ_pred; auto.
eapply nvalue_not_succ in H. unfold not in H. apply H in H1. inv H1.
eapply nvalue_not_succ in H. inv H. assumption.
*)
(*
inv H1. symmetry. apply ST_IszeroSucc. constructor.
generalize dependent t1'.
induction H; intros. inv H1. inv H0.
inv H1. generalize (IHnvalue t1'0 H2); intro T. rewrite T.
inv H1.
generalize dependent t1'0.
induction t1; inv H; intros. inv H2. inv H2.
generalize (IHt1 H1 t1' H0); intro T. rewrite T.
*)
Qed.
(* ###################################################################### *)
(** ** Typing *)
(** The next critical observation about this language is that,
although there are stuck terms, they are all "nonsensical", mixing
booleans and numbers in a way that we don't even _want_ to have a
meaning. We can easily exclude such ill-typed terms by defining a
_typing relation_ that relates terms to the types (either numeric
or boolean) of their final results. *)
Inductive ty : Type :=
| TBool : ty
| TNat : ty.
(** In informal notation, the typing relation is often written
[|- t \in T], pronounced "[t] has type [T]." The [|-] symbol is
called a "turnstile". (Below, we're going to see richer typing
relations where an additional "context" argument is written to the
left of the turnstile. Here, the context is always empty.) *)
(**
---------------- (T_True)
|- true \in Bool
----------------- (T_False)
|- false \in Bool
|- t1 \in Bool |- t2 \in T |- t3 \in T
-------------------------------------------- (T_If)
|- if t1 then t2 else t3 \in T
------------ (T_Zero)
|- 0 \in Nat
|- t1 \in Nat
------------------ (T_Succ)
|- succ t1 \in Nat
|- t1 \in Nat
------------------ (T_Pred)
|- pred t1 \in Nat
|- t1 \in Nat
--------------------- (T_IsZero)
|- iszero t1 \in Bool
*)
Reserved Notation "'|-' t '\in' T" (at level 40).
Inductive has_type : tm -> ty -> Prop :=
| T_True :
|- ttrue \in TBool
| T_False :
|- tfalse \in TBool
| T_If : forall t1 t2 t3 T,
|- t1 \in TBool ->
|- t2 \in T ->
|- t3 \in T ->
|- tif t1 t2 t3 \in T
| T_Zero :
|- tzero \in TNat
| T_Succ : forall t1,
|- t1 \in TNat ->
|- tsucc t1 \in TNat
| T_Pred : forall t1,
|- t1 \in TNat ->
|- tpred t1 \in TNat
| T_Iszero : forall t1,
|- t1 \in TNat ->
|- tiszero t1 \in TBool
where "'|-' t '\in' T" := (has_type t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_True" | Case_aux c "T_False" | Case_aux c "T_If"
| Case_aux c "T_Zero" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Iszero" ].
Hint Constructors has_type.
(* ###################################################################### *)
(** *** Examples *)
(** It's important to realize that the typing relation is a
_conservative_ (or _static_) approximation: it does not calculate
the type of the normal form of a term. *)
Example has_type_1 :
|- tif tfalse tzero (tsucc tzero) \in TNat.
Proof.
apply T_If.
apply T_False.
apply T_Zero.
apply T_Succ.
apply T_Zero.
Qed.
(** (Since we've included all the constructors of the typing relation
in the hint database, the [auto] tactic can actually find this
proof automatically.) *)
Example has_type_not :
~ (|- tif tfalse tzero ttrue \in TBool).
Proof.
intros Contra. solve by inversion 2. Qed.
(** **** Exercise: 1 star, optional (succ_hastype_nat__hastype_nat) *)
Example succ_hastype_nat__hastype_nat : forall t,
|- tsucc t \in TNat ->
|- t \in TNat.
Proof.
intros.
induction t; inv H; assumption.
Qed.
(* ###################################################################### *)
(** ** Canonical forms *)
(** The following two lemmas capture the basic property that defines
the shape of well-typed values. They say that the definition of value
and the typing relation agree. *)
Lemma bool_canonical : forall t,
|- t \in TBool -> value t -> bvalue t.
Proof.
intros t HT HV.
inversion HV; auto.
induction H; inversion HT; auto.
Qed.
Lemma nat_canonical : forall t,
|- t \in TNat -> value t -> nvalue t.
Proof.
intros t HT HV.
inversion HV.
inversion H; subst; inversion HT.
auto.
Qed.
Lemma not_TNat_implies_nvalue :
~(forall t,
|- t \in TNat -> nvalue t).
Proof.
unfold not; intros.
generalize (H (tif ttrue tzero tzero)); intro T.
assert(G : (|-tif ttrue tzero tzero \in TNat)) by repeat constructor.
apply T in G. inv G.
Qed.
(* ###################################################################### *)
(** ** Progress *)
(** The typing relation enjoys two critical properties. The first is
that well-typed normal forms are values (i.e., not stuck). *)
(*
Lemma bvalue_is_value : forall t,
bvalue t ->
value t.
Proof. intros. constructor. assumption. Qed.
Lemma nvalue_is_value : forall t,
nvalue t ->
value t.
Proof. intros. unfold value. right. assumption. Qed.
*)
Theorem progress : forall t T,
|- t \in T ->
value t \/ exists t', t ==> t'.
(** **** Exercise: 3 stars (finish_progress) *)
(** Complete the formal proof of the [progress] property. (Make sure
you understand the informal proof fragment in the following
exercise before starting -- this will save you a lot of time.) *)
Proof with auto.
intros t T HT.
has_type_cases (induction HT) Case...
(* The cases that were obviously values, like T_True and
T_False, were eliminated immediately by auto *)
Case "T_If".
right. inversion IHHT1; clear IHHT1.
SCase "t1 is a value".
apply (bool_canonical t1 HT1) in H.
inversion H; subst; clear H.
exists t2...
exists t3...
SCase "t1 can take a step".
inversion H as [t1' H1].
exists (tif t1' t2 t3)...
Case "T_Succ".
inv IHHT.
SCase "left".
left. apply nat_canonical in H. induction H.
unfold value; right. repeat constructor.
unfold value; right. constructor. constructor. assumption. assumption.
SCase "right".
inv H. right. exists (tsucc x)...
Case "T_Pred".
inv IHHT.
SCase "left".
apply nat_canonical in H.
inv H. right. exists tzero...
right. exists t... assumption.
SCase "right".
inv H. right. exists (tpred x)...
Case "T_Iszero".
right. inv IHHT.
SCase "left".
apply nat_canonical in H; auto.
inv H. exists ttrue... exists tfalse...
inv H.
exists (tiszero x)...
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (finish_progress_informal) *)
(** Complete the corresponding informal proof: *)
(** _Theorem_: If [|- t \in T], then either [t] is a value or else
[t ==> t'] for some [t']. *)
(** _Proof_: By induction on a derivation of [|- t \in T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3
\in T]. By the IH, either [t1] is a value or else [t1] can step
to some [t1'].
- If [t1] is a value, then by the canonical forms lemmas
and the fact that [|- t1 \in Bool] we have that [t1]
is a [bvalue] -- i.e., it is either [true] or [false].
If [t1 = true], then [t] steps to [t2] by [ST_IfTrue],
while if [t1 = false], then [t] steps to [t3] by
[ST_IfFalse]. Either way, [t] can step, which is what
we wanted to show.
- If [t1] itself can take a step, then, by [ST_If], so can
[t].
(* FILL IN HERE *)
[]
*)
(** This is more interesting than the strong progress theorem that we
saw in the Smallstep chapter, where _all_ normal forms were
values. Here, a term can be stuck, but only if it is ill
typed. *)
(** **** Exercise: 1 star (step_review) *)
(** Quick review. Answer _true_ or _false_. In this language...
- Every well-typed normal form is a value.
- Every value is a normal form.
- The single-step evaluation relation is
a partial function (i.e., it is deterministic).
- The single-step evaluation relation is a _total_ function.
*)
(** [] *)
(*
- Every well-typed normal form is a value.
*)
Example nf_is_not_always_value :
~(forall t, step_normal_form t -> value t).
Proof.
unfold normal_form, not.
intros.
generalize (H (tif tzero tzero tzero)); intro T.
assert(G : (exists t', tif tzero tzero tzero ==> t') -> False).
intros. inv H0. inv H1. inv H5.
apply T in G.
inv G. inv H0. inv H0.
Qed.
(*
- Every value is a normal form.
value_is_nf
: forall t : tm, value t -> step_normal_form t
*)
(*
- The single-step evaluation relation is
a partial function (i.e., it is deterministic).
Theorem step_deterministic:
deterministic step.
*)
(*
- The single-step evaluation relation is a _total_ function.
Theorem step_deterministic:
deterministic step.
*)
(* ###################################################################### *)
(** ** Type Preservation *)
(** The second critical property of typing is that, when a well-typed
term takes a step, the result is also a well-typed term.
This theorem is often called the _subject reduction_ property,
because it tells us what happens when the "subject" of the typing
relation is reduced. This terminology comes from thinking of
typing statements as sentences, where the term is the subject and
the type is the predicate. *)
Theorem preservation : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
(** **** Exercise: 2 stars (finish_preservation) *)
(** Complete the formal proof of the [preservation] property. (Again,
make sure you understand the informal proof fragment in the
following exercise first.) *)
Proof with auto.
intros t t' T HT HE.
generalize dependent t'.
has_type_cases (induction HT) Case;
(* every case needs to introduce a couple of things *)
intros t' HE;
(* and we can deal with several impossible
cases all at once *)
try (solve by inversion).
Case "T_If". inversion HE; subst; clear HE.
SCase "ST_IFTrue". assumption.
SCase "ST_IfFalse". assumption.
SCase "ST_If". apply T_If; try assumption.
apply IHHT1; assumption.
Case "T_Succ". inv HE. apply T_Succ. apply IHHT...
Case "T_Pred". inv HE... inv HT...
Case "T_Iszero". inv HE...
Qed.
(** **** Exercise: 3 stars, advanced (finish_preservation_informal) *)
(** Complete the following proof: *)
(** _Theorem_: If [|- t \in T] and [t ==> t'], then [|- t' \in T]. *)
(** _Proof_: By induction on a derivation of [|- t \in T].
- If the last rule in the derivation is [T_If], then [t = if t1
then t2 else t3], with [|- t1 \in Bool], [|- t2 \in T] and [|- t3
\in T].
Inspecting the rules for the small-step reduction relation and
remembering that [t] has the form [if ...], we see that the
only ones that could have been used to prove [t ==> t'] are
[ST_IfTrue], [ST_IfFalse], or [ST_If].
- If the last rule was [ST_IfTrue], then [t' = t2]. But we
know that [|- t2 \in T], so we are done.
- If the last rule was [ST_IfFalse], then [t' = t3]. But we
know that [|- t3 \in T], so we are done.
- If the last rule was [ST_If], then [t' = if t1' then t2
else t3], where [t1 ==> t1']. We know [|- t1 \in Bool] so,
by the IH, [|- t1' \in Bool]. The [T_If] rule then gives us
[|- if t1' then t2 else t3 \in T], as required.
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars (preservation_alternate_proof) *)
(** Now prove the same property again by induction on the
_evaluation_ derivation instead of on the typing derivation.
Begin by carefully reading and thinking about the first few
lines of the above proof to make sure you understand what
each one is doing. The set-up for this proof is similar, but
not exactly the same. *)
Theorem preservation' : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
Proof with eauto.
intros.
generalize dependent T.
induction H0; intros; inv H...
inv H0. inv H1. assumption.
inv H0. inv H2. assumption.
inv H0. constructor.
inv H0. constructor.
(*
intros.
generalize dependent t'.
induction H; intros; inv H0...
*)
Qed.
(* ###################################################################### *)
(** ** Type Soundness *)
(** Putting progress and preservation together, we can see that a
well-typed term can _never_ reach a stuck state. *)
Definition multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Corollary soundness : forall t t' T,
|- t \in T ->
t ==>* t' ->
~(stuck t').
Proof with auto.
(*
unfold stuck, not; intros.
induction H0; inv H1.
apply H2.
apply progress in H.
inv H... inv H1. unfold normal_form, not in H0. contradiction H0. exists x0...
apply IHmulti... eapply preservation in H0. apply H0. apply H.
*)
intros t t' T HT P. induction P; intros [R S].
destruct (progress x T HT); auto.
apply IHP. apply (preservation x y T HT H).
unfold stuck. split; auto. Qed.
(* ###################################################################### *)
(** * Aside: the [normalize] Tactic *)
(** When experimenting with definitions of programming languages in
Coq, we often want to see what a particular concrete term steps
to -- i.e., we want to find proofs for goals of the form [t ==>*
t'], where [t] is a completely concrete term and [t'] is unknown.
These proofs are simple but repetitive to do by hand. Consider for
example reducing an arithmetic expression using the small-step
relation [astep]. *)
Definition amultistep st := multi (astep st).
Notation " t '/' st '==>a*' t' " := (amultistep st t t')
(at level 40, st at level 39).
Example astep_example1 :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
apply multi_step with (APlus (ANum 3) (ANum 12)).
apply AS_Plus2.
apply av_num.
apply AS_Mult.
apply multi_step with (ANum 15).
apply AS_Plus.
apply multi_refl.
Qed.
(** We repeatedly apply [multi_step] until we get to a normal
form. The proofs that the intermediate steps are possible are
simple enough that [auto], with appropriate hints, can solve
them. *)
(* Hint Constructors astep aval.*)
Hint Constructors astep.
Hint Constructors aval.
Example astep_example1' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
eapply multi_step. auto. simpl.
eapply multi_step. auto. simpl.
apply multi_refl.
Qed.
(** The following custom [Tactic Notation] definition captures this
pattern. In addition, before each [multi_step] we print out the
current goal, so that the user can follow how the term is being
evaluated. *)
Tactic Notation "print_goal" := match goal with |- ?x => idtac x end.
Tactic Notation "normalize" :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; simpl)]);
apply multi_refl.
Example astep_example1'' :
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* (ANum 15).
Proof.
normalize.
(* At this point in the proof script, the Coq response shows
a trace of how the expression evaluated.
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ANum 15)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) (ANum 15))
(multi (astep empty_state) (ANum 15) (ANum 15))
*)
Qed.
(** The [normalize] tactic also provides a simple way to calculate
what the normal form of a term is, by proving a goal with an
existential variable in it. *)
Example astep_example1''' : exists e',
(APlus (ANum 3) (AMult (ANum 3) (ANum 4))) / empty_state
==>a* e'.
Proof.
eapply ex_intro. normalize.
(* This time, the trace will be:
(APlus (ANum 3) (AMult (ANum 3) (ANum 4)) / empty_state ==>a* ??)
(multi (astep empty_state) (APlus (ANum 3) (ANum 12)) ??)
(multi (astep empty_state) (ANum 15) ??)
where ?? is the variable ``guessed'' by eapply.
*)
Qed.
(** **** Exercise: 1 star (normalize_ex) *)
Theorem normalize_ex : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
eexists.
normalize.
Qed.
(** **** Exercise: 1 star, optional (normalize_ex') *)
(** For comparison, prove it using [apply] instead of [eapply]. *)
Theorem normalize_ex' : exists e',
(AMult (ANum 3) (AMult (ANum 2) (ANum 1))) / empty_state
==>a* e'.
Proof.
eexists. normalize.
Qed.
(* ###################################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 2 stars (subject_expansion) *)
(** Having seen the subject reduction property, it is reasonable to
wonder whether the opposity property -- subject _expansion_ --
also holds. That is, is it always the case that, if [t ==> t']
and [|- t' \in T], then [|- t \in T]? If so, prove it. If
not, give a counter-example. (You do not need to prove your
counter-example in Coq, but feel free to do so if you like.)
(* FILL IN HERE *)
[]
*)
Theorem not_subject_expansion :
~(forall t t' T,
|- t' \in T ->
t ==> t' ->
|- t \in T).
Proof with auto.
unfold not; intros.
assert(G : |-tzero \in TNat) by constructor.
assert(G2 : tif ttrue tzero tfalse ==> tzero) by constructor.
generalize (H (tif ttrue tzero tfalse) tzero TNat G G2); intro T.
inv T.
inv H6.
Qed.
(** **** Exercise: 2 stars (variation1) *)
(** Suppose, that we add this new rule to the typing relation:
| T_SuccBool : forall t,
|- t \in TBool ->
|- tsucc t \in TBool
Which of the following properties remain true in the presence of
this rule? For each one, write either "remains true" or
else "becomes false." If a property becomes false, give a
counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
Module variation1.
Reserved Notation "'|-' t '\in' T" (at level 40).
Inductive has_type : tm -> ty -> Prop :=
| T_True :
|- ttrue \in TBool
| T_False :
|- tfalse \in TBool
| T_If : forall t1 t2 t3 T,
|- t1 \in TBool ->
|- t2 \in T ->
|- t3 \in T ->
|- tif t1 t2 t3 \in T
| T_Zero :
|- tzero \in TNat
| T_Succ : forall t1,
|- t1 \in TNat ->
|- tsucc t1 \in TNat
| T_Pred : forall t1,
|- t1 \in TNat ->
|- tpred t1 \in TNat
| T_Iszero : forall t1,
|- t1 \in TNat ->
|- tiszero t1 \in TBool
| T_SuccBool : forall t,
|- t \in TBool ->
|- tsucc t \in TBool
where "'|-' t '\in' T" := (has_type t T).
(*
- Determinism of [step]
: not related to type
*)
(*
- Progress
*)
Theorem not_progress :
~(forall t T,
|- t \in T ->
value t \/ exists t', t ==> t').
Proof.
unfold not; intros.
assert(G : |-tsucc tfalse \in TBool) by repeat constructor.
generalize (H (tsucc tfalse) TBool G); intro T.
inv T.
inv H0. inv H1. inv H1. inv H2. inv H0. inv H1. inv H2.
Qed.
(*
- Preservation
added one more case in "has_type"
effect on conclusion (|- t' \in T) : more choice. no need to consider
effect on premise (t ==> t') : no effect
effect on premise (|- t \in T) : more choice,
but it is all eliminated in conclusion.
| T_SuccBool : forall tt,
|- tt \in TBool ->
|- tsucc tt \in TBool
Newly introduced case must be form of
t := (tsucc tt)
T := TBool
t' \in TBool.
| ST_Succ : forall t1 t1' : tm, t1 ==> t1' -> tsucc t1 ==> tsucc t1'
####################### TODO : It is provable, but simple explanation??????????????? #############################################
*)
Lemma pres : forall tt t',
|- (tsucc tt) \in TBool ->
(tsucc tt) ==> t' ->
|- t' \in TBool.
Proof with eauto.
(*
intros. generalize dependent t'.
induction H; intros; inv H0; try auto.
inv H2... constructor... constructor...
inv H2... constructor...
constructor... constructor.
inv H2. constructor... auto.
constructor.
*)
intros. inv H0.
induction H2; inv H.
constructor. inv H1...
constructor. inv H1...
inv H1. constructor. constructor... generalize (T_SuccBool t1 H4); intro T. apply IHstep in T. inv T. auto.
constructor. apply IHstep in H1. auto.
inv H1. inv H2. inv H1.
apply T_SuccBool. constructor.
apply T_SuccBool. constructor.
Abort.
(*
induction H2; intros.
inv H1; inv H0; repeat constructor; auto.
inv H1; inv H0; repeat constructor; auto.
inv H1; inv H0; repeat constructor; auto.
*)
(*
induction H2; intros; inv H1; repeat constructor; auto;
try inv H0; auto.
*)
(*
apply T_SuccBool.
constructor. inv H1.
induction H2.
inv H0; auto.
inv H0; auto.
inv H0; auto.
constructor; auto.
generalize dependent t1'.
induction H0; intros; inv H2.
*)
Theorem preservation : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
Proof with eauto.
intros.
generalize dependent T.
induction H0; intros; inv H...
constructor...
constructor...
constructor...
inv H0; constructor...
inv H0; constructor...
inv H2. inv H0...
constructor...
constructor...
inv H0. constructor...
inv H0. constructor...
constructor...
Qed.
Theorem not_preservation : ~(forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T).
Proof with eauto.
unfold not; intros.
intros.
assert(G: |-tsucc (tif ttrue tfalse tfalse) \in TBool).
repeat constructor...
assert(G2: tsucc (tif ttrue tfalse tfalse) ==> tsucc tfalse).
repeat constructor...
generalize (H (tsucc (tif ttrue tfalse tfalse)) (tsucc tfalse) TBool G G2); intro T.
Abort.
(*
Lemma T_SuccBool_cannot_step : forall t,
|- t \in TBool ->
~(exists t', (tsucc t) ==> t').
Proof with eauto.
unfold not; intros.
inv H0. inv H1.
generalize dependent t1'.
induction H; intros...
inv H2. inv H2. inv H2.
Qed.
*)
End variation1.
(** **** Exercise: 2 stars (variation2) *)
(** Suppose, instead, that we add this new rule to the [step] relation:
| ST_Funny1 : forall t2 t3,
(tif ttrue t2 t3) ==> t3
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
Lemma modusponens: forall (P Q: Prop), P -> (P -> Q) -> Q.
Proof. intros. apply H0. assumption. Qed.
Ltac exploit x :=
refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _ _) _)
|| refine (modusponens _ _ (x _ _ _) _)
|| refine (modusponens _ _ (x _ _) _)
|| refine (modusponens _ _ (x _) _).
Module variation2.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Succ : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_PredZero :
(tpred tzero) ==> tzero
| ST_PredSucc : forall t1,
nvalue t1 ->
(tpred (tsucc t1)) ==> t1
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_IszeroZero :
(tiszero tzero) ==> ttrue
| ST_IszeroSucc : forall t1,
nvalue t1 ->
(tiszero (tsucc t1)) ==> tfalse
| ST_Iszero : forall t1 t1',
t1 ==> t1' ->
(tiszero t1) ==> (tiszero t1')
| ST_Funny1 : forall t2 t3,
(tif ttrue t2 t3) ==> t3
where "t1 '==>' t2" := (step t1 t2).
Theorem not_step_deterministic:
~(deterministic step).
Proof.
unfold deterministic, not.
intros.
generalize (H (tif ttrue tzero tfalse) tzero tfalse); intro T.
exploit T.
constructor. constructor. intros. inv H0.
Qed.
Theorem progress :
(forall t T,
|- t \in T ->
value t \/ exists t', t ==> t').
Proof with eauto.
induction t; intros.
left...
left...
inv H.
generalize (IHt1 TBool H3); intro T1.
generalize (IHt2 T H5); intro T2.
generalize (IHt3 T H6); intro T3.
inv T1. apply bool_canonical in H...
inv H; right. exists t2; constructor. exists t3; constructor.
inv H; right. exists (tif x t2 t3); constructor...
left...
inv H. generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H. right. exists (tsucc x). constructor...
inv H. generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H; right. exists (tzero). constructor...
exists t0; constructor...
inv H.
right. exists (tpred x). constructor...
inv H.
generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H; right. exists ttrue; constructor. exists tfalse; constructor...
inv H. right. exists (tiszero x); constructor...
Qed.
Theorem preservation : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
Proof with eauto.
intros.
generalize dependent T.
induction H0; intros; inv H...
inv H0. inv H1. assumption.
inv H0. inv H2. assumption.
inv H0. constructor.
inv H0. constructor.
(*
intros.
generalize dependent t'.
induction H; intros; inv H0...
*)
Qed.
End variation2.
(** **** Exercise: 2 stars, optional (variation3) *)
(** Suppose instead that we add this rule:
| ST_Funny2 : forall t1 t2 t2' t3,
t2 ==> t2' ->
(tif t1 t2 t3) ==> (tif t1 t2' t3)
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
Module variation3.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Succ : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_PredZero :
(tpred tzero) ==> tzero
| ST_PredSucc : forall t1,
nvalue t1 ->
(tpred (tsucc t1)) ==> t1
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_IszeroZero :
(tiszero tzero) ==> ttrue
| ST_IszeroSucc : forall t1,
nvalue t1 ->
(tiszero (tsucc t1)) ==> tfalse
| ST_Iszero : forall t1 t1',
t1 ==> t1' ->
(tiszero t1) ==> (tiszero t1')
| ST_Funny2 : forall t1 t2 t2' t3,
t2 ==> t2' ->
(tif t1 t2 t3) ==> (tif t1 t2' t3)
where "t1 '==>' t2" := (step t1 t2).
Theorem not_step_deterministic:
~(deterministic step).
Proof.
unfold deterministic, not.
intros.
generalize (H (tif ttrue (tpred tzero) tfalse) (tpred tzero)
(tif ttrue tzero tfalse)); intro T.
exploit T.
constructor. constructor. constructor. intros. inv H0.
Qed.
Theorem progress : forall t T,
|- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
induction t; intros.
left...
left...
inv H.
generalize (IHt1 TBool H3); intro T1.
generalize (IHt2 T H5); intro T2.
generalize (IHt3 T H6); intro T3.
inv T1. apply bool_canonical in H...
inv H; right. exists t2; constructor. exists t3; constructor.
inv H; right. exists (tif x t2 t3); constructor...
left...
inv H. generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H. right. exists (tsucc x). constructor...
inv H. generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H; right. exists (tzero). constructor...
exists t0; constructor...
inv H.
right. exists (tpred x). constructor...
inv H.
generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H; right. exists ttrue; constructor. exists tfalse; constructor...
inv H. right. exists (tiszero x); constructor...
Qed.
Theorem preservation : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
Proof with eauto.
intros.
generalize dependent T.
induction H0; intros; inv H...
inv H0. inv H1. assumption.
inv H0. inv H2. assumption.
inv H0. constructor.
inv H0. constructor.
Qed.
End variation3.
(** **** Exercise: 2 stars, optional (variation4) *)
(** Suppose instead that we add this rule:
| ST_Funny3 :
(tpred tfalse) ==> (tpred (tpred tfalse))
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
Module variation4.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Succ : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_PredZero :
(tpred tzero) ==> tzero
| ST_PredSucc : forall t1,
nvalue t1 ->
(tpred (tsucc t1)) ==> t1
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_IszeroZero :
(tiszero tzero) ==> ttrue
| ST_IszeroSucc : forall t1,
nvalue t1 ->
(tiszero (tsucc t1)) ==> tfalse
| ST_Iszero : forall t1 t1',
t1 ==> t1' ->
(tiszero t1) ==> (tiszero t1')
| ST_Funny3 :
(tpred tfalse) ==> (tpred (tpred tfalse))
where "t1 '==>' t2" := (step t1 t2).
Ltac value_pre :=
match goal with
| H1: ttrue ==> _ |- _ => inv H1
| H1: tfalse ==> _ |- _ => inv H1
| H1: tzero ==> _ |- _ => inv H1
end.
Lemma nvalue_not_succ : forall t1 t2,
nvalue t1 ->
tsucc t1 ==> t2 ->
False.
Proof.
induction t1; intros; inv H.
inv H0; inv H1.
inv H0.
generalize (IHt1 t1' H2 H1); intro T. auto.
Qed.
Theorem step_deterministic :
deterministic step.
Proof with eauto.
unfold deterministic.
intros.
generalize dependent y2.
induction H; intros st H2; inv H2;
auto; try value_pre; try find_eqn; try value_pre; auto.
generalize (nvalue_not_succ t1 t1'); intro T; exploit T... intros Tmp; inv Tmp.
generalize (nvalue_not_succ st t1'); intro T; exploit T... intros Tmp; inv Tmp.
eapply nvalue_not_succ in H; inv H...
eapply nvalue_not_succ in H1; inv H1...
Qed.
Theorem progress : forall t T,
|- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
induction t; intros.
left...
left...
inv H...
generalize (IHt1 TBool H3); intro T1.
generalize (IHt2 T H5); intro T2.
generalize (IHt3 T H6); intro T3.
inv T1. apply bool_canonical in H...
inv H; right. exists t2; constructor. exists t3; constructor.
inv H; right. exists (tif x t2 t3); constructor...
left...
inv H. generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H. right. exists (tsucc x). constructor...
inv H. generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H; right. exists (tzero). constructor...
exists t0; constructor...
inv H.
right. exists (tpred x). constructor...
inv H.
generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H; right. exists ttrue; constructor. exists tfalse; constructor...
inv H. right. exists (tiszero x); constructor...
Qed.
Theorem preservation : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
Proof with eauto.
intros.
generalize dependent T.
induction H0; intros; inv H...
inv H0. inv H1. assumption.
inv H0. inv H2. assumption.
inv H0. constructor.
inv H0. constructor.
Qed.
End variation4.
(** **** Exercise: 2 stars, optional (variation5) *)
(** Suppose instead that we add this rule:
| T_Funny4 :
|- tzero \in TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
Module variation5.
Reserved Notation "'|-' t '\in' T" (at level 40).
Inductive has_type : tm -> ty -> Prop :=
| T_True :
|- ttrue \in TBool
| T_False :
|- tfalse \in TBool
| T_If : forall t1 t2 t3 T,
|- t1 \in TBool ->
|- t2 \in T ->
|- t3 \in T ->
|- tif t1 t2 t3 \in T
| T_Zero :
|- tzero \in TNat
| T_Succ : forall t1,
|- t1 \in TNat ->
|- tsucc t1 \in TNat
| T_Pred : forall t1,
|- t1 \in TNat ->
|- tpred t1 \in TNat
| T_Iszero : forall t1,
|- t1 \in TNat ->
|- tiszero t1 \in TBool
| T_Funny4 :
|- tzero \in TBool
where "'|-' t '\in' T" := (has_type t T).
(* step deterministic : same *)
Theorem not_progress :
~(forall t T,
|- t \in T ->
value t \/ exists t', t ==> t').
Proof with auto.
unfold not.
intros.
generalize (H ((tif tzero ttrue ttrue)) (TBool)); intro T; exploit T.
constructor. constructor. constructor. constructor.
intros.
inv H0.
inv H1. inv H0. inv H0.
inv H1. inv H0. inv H5.
Qed.
(*
Lemma bool_canonical : forall t,
|- t \in TBool -> value t -> bvalue t.
Proof.
intros t HT HV.
inversion HV; auto.
induction H; inversion HT; auto.
Qed.
Lemma nat_canonical : forall t,
|- t \in TNat -> value t -> nvalue t.
Proof.
intros t HT HV.
inversion HV.
inversion H; subst; inversion HT.
auto.
Qed.
Theorem progress : forall t T,
|- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
induction t; intros.
left...
left...
inv H...
generalize (IHt1 TBool H3); intro T1.
generalize (IHt2 T H5); intro T2.
generalize (IHt3 T H6); intro T3.
inv T1. apply bool_canonical in H...
inv H; right. exists t2; constructor. exists t3; constructor.
inv H; right. exists (tif x t2 t3); constructor...
left...
inv H. generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H. right. exists (tsucc x). constructor...
inv H. generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H; right. exists (tzero). constructor...
exists t0; constructor...
inv H.
right. exists (tpred x). constructor...
inv H.
generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H; right. exists ttrue; constructor. exists tfalse; constructor...
inv H. right. exists (tiszero x); constructor...
Qed.
*)
(*
Theorem preservation :
~(forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T).
Proof with eauto.
unfold not. intros.
generalize (H (tpred (tsucc tzero))
Qed.
T : ty
H0 : |-tpred (tsucc tzero) \in T
============================
|-tzero \in T
*)
Theorem preservation : forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T.
Proof with eauto.
intros.
generalize dependent T.
induction H0; intros; inv H...
constructor...
constructor. apply IHstep...
inv H0. inv H1. assumption.
inv H0. inv H2. assumption.
constructor. apply IHstep...
constructor.
inv H0. constructor.
inv H0. constructor.
constructor. apply IHstep...
Qed.
End variation5.
(** **** Exercise: 2 stars, optional (variation6) *)
(** Suppose instead that we add this rule:
| T_Funny5 :
|- tpred tzero \in TBool
]]
Which of the above properties become false in the presence of
this rule? For each one that does, give a counter-example.
[]
*)
Module variation6.
Reserved Notation "'|-' t '\in' T" (at level 40).
Inductive has_type : tm -> ty -> Prop :=
| T_True :
|- ttrue \in TBool
| T_False :
|- tfalse \in TBool
| T_If : forall t1 t2 t3 T,
|- t1 \in TBool ->
|- t2 \in T ->
|- t3 \in T ->
|- tif t1 t2 t3 \in T
| T_Zero :
|- tzero \in TNat
| T_Succ : forall t1,
|- t1 \in TNat ->
|- tsucc t1 \in TNat
| T_Pred : forall t1,
|- t1 \in TNat ->
|- tpred t1 \in TNat
| T_Iszero : forall t1,
|- t1 \in TNat ->
|- tiszero t1 \in TBool
| T_Funny5 :
|- (tpred tzero) \in TBool
where "'|-' t '\in' T" := (has_type t T).
(* step deterministic : same *)
Lemma bool_canonical : forall t,
|- t \in TBool -> value t -> bvalue t.
Proof.
intros t HT HV.
inversion HV; auto.
induction H; inversion HT; auto.
Qed.
Lemma nat_canonical : forall t,
|- t \in TNat -> value t -> nvalue t.
Proof.
intros t HT HV.
inversion HV.
inversion H; subst; inversion HT.
auto.
Qed.
Theorem progress : forall t T,
|- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
induction t; intros.
left...
left...
inv H.
generalize (IHt1 TBool H3); intro T1.
generalize (IHt2 T H5); intro T2.
generalize (IHt3 T H6); intro T3.
inv T1. apply bool_canonical in H...
inv H; right. exists t2; constructor. exists t3; constructor.
inv H; right. exists (tif x t2 t3); constructor...
left...
inv H. generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H. right. exists (tsucc x). constructor...
inv H. generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H; right. exists (tzero). constructor...
exists t0; constructor...
inv H.
right. exists (tpred x). constructor...
(* right. eexists. constructor. *)
right. eexists. constructor.
right.
inv H.
generalize (IHt TNat H1); intro T.
inv T.
apply nat_canonical in H...
destruct H. eexists; constructor. eexists; constructor...
inv H.
eexists; constructor...
(*
exists (tiszero x). constructor...
right.
eexists. constructor.
apply IHt in H.
inv H. apply nat_canonical in H1.
apply IHt in H1. inv H1.
inv H. inv H0.
inv H.
generalize (IHt TNat H1); intro T.
inv T. apply nat_canonical in H...
inv H; right. exists ttrue; constructor. exists tfalse; constructor...
inv H. right. exists (tiszero x); constructor...
*)
Qed.
Theorem not_preservation :
~(forall t t' T,
|- t \in T ->
t ==> t' ->
|- t' \in T).
Proof with eauto.
unfold not; intros.
generalize (H (tpred tzero) tzero TBool); intro T; exploit T.
constructor.
constructor.
intros.
inv H0.
Qed.
(*
Theorem not_progress :
~(forall t T,
|- t \in T ->
value t \/ exists t', t ==> t').
Proof with auto.
unfold not.
intros.
generalize (H (tpred tzero) (TBool)); intro T; exploit T.
constructor.
intros. inv H0. inv H1. inv H0. inv H0. inv H1.
remember x as xx.
inv H0. admit.
unfold not.
intros.
generalize (H ((tif (tpred tzero) ttrue ttrue)) (TBool)); intro T; exploit T.
constructor. constructor. constructor. constructor.
intros.
inv H0.
inv H1. inv H0. inv H0.
inv H1. inv H0. inv H5.
Qed.
| T_Funny5 :
|- (tpred tzero) \in TBool
*)
End variation6.
(** **** Exercise: 3 stars, optional (more_variations) *)
(** Make up some exercises of your own along the same lines as
the ones above. Try to find ways of selectively breaking
properties -- i.e., ways of changing the definitions that
break just one of the properties and leave the others alone.
[]
*)
(** **** Exercise: 1 star (remove_predzero) *)
(** The evaluation rule [E_PredZero] is a bit counter-intuitive: we
might feel that it makes more sense for the predecessor of zero to
be undefined, rather than being defined to be zero. Can we
achieve this simply by removing the rule from the definition of
[step]? Would doing so create any problems elsewhere?
(* FILL IN HERE *)
[] *)
Module remove_predzero.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Succ : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
(* | ST_PredZero :
(tpred tzero) ==> tzero *)
| ST_PredSucc : forall t1,
nvalue t1 ->
(tpred (tsucc t1)) ==> t1
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_IszeroZero :
(tiszero tzero) ==> ttrue
| ST_IszeroSucc : forall t1,
nvalue t1 ->
(tiszero (tsucc t1)) ==> tfalse
| ST_Iszero : forall t1 t1',
t1 ==> t1' ->
(tiszero t1) ==> (tiszero t1')
where "t1 '==>' t2" := (step t1 t2).
Reserved Notation "'|-' t '\in' T" (at level 40).
Inductive has_type : tm -> ty -> Prop :=
| T_True :
|- ttrue \in TBool
| T_False :
|- tfalse \in TBool
| T_If : forall t1 t2 t3 T,
|- t1 \in TBool ->
|- t2 \in T ->
|- t3 \in T ->
|- tif t1 t2 t3 \in T
| T_Zero :
|- tzero \in TNat
| T_Succ : forall t1,
|- t1 \in TNat ->
|- tsucc t1 \in TNat
| T_Pred : forall t1,
|- t1 \in TNat ->
|- tpred t1 \in TNat
| T_Iszero : forall t1,
|- t1 \in TNat ->
|- tiszero t1 \in TBool
where "'|-' t '\in' T" := (has_type t T).
Theorem not_progress :
~(forall t T,
|- t \in T ->
value t \/ exists t', t ==> t').
Proof with eauto.
unfold not; intros.
generalize (H (tpred tzero) TNat); intro T; exploit T...
constructor. constructor.
intros.
inv H0. inv H1. inv H0. inv H0. inv H1. inv H0. inv H2.
Qed.
End remove_predzero.
(** **** Exercise: 4 stars, advanced (prog_pres_bigstep) *)
(** Suppose our evaluation relation is defined in the big-step style.
What are the appropriate analogs of the progress and preservation
properties?
(* FILL IN HERE *)
[]
*)
(* progress ~= bigstep itself *)
(* preservation ~= aexp, bexp itself *)
(* $Date: 2014-04-08 23:31:16 -0400 (Tue, 08 Apr 2014) $ *)
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Drawing Engine Register Block Level 2
// File : der_reg_2.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// Second level register block
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module der_reg_2
(
input de_clk, // drawing engine clock input
input de_rstn, // de reset input
input load_actvn, // load active command parameters
input cmdcpyclr, // command copy clear.
input [12:0] buf_ctrl_1, // buffer control register input
input [31:0] sorg_1, // source origin register input
input [31:0] dorg_1, // destination origin register input
input [11:0] sptch_1, // source pitch register input
input [11:0] dptch_1, // destination pitch register input
input [3:0] opc_1, // opcode register input
input [3:0] rop_1, // raster opcode register input
input [4:0] style_1, // drawing style register input
input nlst_1, // drawing pattern style register input
input [1:0] apat_1, // drawing area pattern mode
input [2:0] clp_1, // drawing clip control register input
input [31:0] fore_1, // foreground color register input
input [31:0] back_1, // background color register input
input [3:0] mask_1, // plane mask register input
input [23:0] de_key_1, // Key data
input [15:0] alpha_1, // Alpha Register
input [17:0] acntrl_1, // Alpha Control Register
input [1:0] bc_lvl_1,
output [12:0] buf_ctrl_2, // buffer control register input
output reg [31:0] sorg_2, // source origin register input
output reg [31:0] dorg_2, // destination origin register input
output reg [11:0] sptch_2, // source pitch register input
output reg [11:0] dptch_2, // destination pitch register input
output reg [3:0] rop_2, // raster opcode register input
output reg [4:0] style_2, // drawing style register input
output reg nlst_2, // drawing pattern style register input
output reg [1:0] apat_2, // drawing area pattern mode.
output reg [2:0] clp_2, // drawing clip control register input
output reg [31:0] fore_2, // foreground color register input
output reg [31:0] back_2, // background color register input
output reg [3:0] mask_2, // plane mask register input
output reg [23:0] de_key_2, // Key data
output reg [15:0] alpha_2, // Alpha Register
output reg [17:0] acntrl_2, // Alpha Control Register
output reg [1:0] bc_lvl_2,
output reg [3:0] opc_2
);
reg [12:0] buf_ctrl_r; // buffer control register input
/***************************************************************************/
/* */
/* ASSIGN OUTPUTS TO REGISTERS */
/* */
/***************************************************************************/
assign buf_ctrl_2 = {
buf_ctrl_r[12:4],
(buf_ctrl_r[3] | (buf_ctrl_r[2] & buf_ctrl_r[0])),
buf_ctrl_r[2:0]
};
/***************************************************************************/
/* REGISTER WRITE FUNCTION */
/* BYTE SELECTION ORDER */
/* */
/* | 63-56 | 55-48 | 47-40 | 39-32 | 31-24 | 23-16 | 15-8 | 7-0 | */
/* | wb7n | wb6n | wb5n | wb4n | wb3n | wb2n | wb1n | wb0n| */
/* */
/***************************************************************************/
/* Replicate the foreground and background depending on the bits per pixel.*/
wire [1:0] psize;
reg [31:0] fore_rep;
reg [31:0] back_rep;
assign psize = buf_ctrl_1[8:7];
always @*
casex (psize)
2'b00: begin
// 8 Bpp
fore_rep = {4{fore_1[7:0]}};
back_rep = {4{back_1[7:0]}};
end
2'bx1: begin
// 16 Bpp
fore_rep = {2{fore_1[15:0]}};
back_rep = {2{back_1[15:0]}};
end
default: begin
// 32Bpp
fore_rep = fore_1;
back_rep = back_1;
end
endcase // casex(psize)
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) opc_2 <= 4'b0;
else if(cmdcpyclr) opc_2 <= 4'b0;
else if(!load_actvn) opc_2 <= opc_1;
end
always @(posedge de_clk or negedge de_rstn) begin
if(!de_rstn) begin
buf_ctrl_r <= 13'b0;
sorg_2 <= 32'b0;
dorg_2 <= 32'b0;
rop_2 <= 4'b0;
style_2 <= 5'b0;
nlst_2 <= 1'b0;
apat_2 <= 2'b0;
clp_2 <= 3'b0;
bc_lvl_2 <= 2'b0;
sptch_2 <= 12'b0;
dptch_2 <= 12'b0;
fore_2 <= 32'b0;
back_2 <= 32'b0;
mask_2 <= 4'b0;
de_key_2 <= 24'b0;
alpha_2 <= 16'b0;
acntrl_2 <= 18'b0;
end else if(!load_actvn) begin
buf_ctrl_r <= buf_ctrl_1;
sorg_2 <= sorg_1;
dorg_2 <= dorg_1;
rop_2 <= rop_1;
style_2 <= style_1;
nlst_2 <= nlst_1;
apat_2 <= apat_1;
clp_2 <= clp_1;
bc_lvl_2 <= bc_lvl_1;
sptch_2 <= sptch_1;
dptch_2 <= dptch_1;
fore_2 <= fore_rep;
back_2 <= back_rep;
mask_2 <= mask_1;
de_key_2 <= de_key_1;
alpha_2 <= alpha_1;
acntrl_2 <= acntrl_1;
end
end
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Euclidean Division *)
(** Initial Contribution by Claude Marché and Xavier Urbain *)
Require Export ZArith_base.
Require Import Zbool Omega ZArithRing Zcomplements Setoid Morphisms.
Local Open Scope Z_scope.
(** The definition of the division is now in [BinIntDef], the initial
specifications and properties are in [BinInt]. *)
Notation Zdiv_eucl_POS := Z.pos_div_eucl (compat "8.3").
Notation Zdiv_eucl := Z.div_eucl (compat "8.3").
Notation Zdiv := Z.div (compat "8.3").
Notation Zmod := Z.modulo (compat "8.3").
Notation Zdiv_eucl_eq := Z.div_eucl_eq (compat "8.3").
Notation Z_div_mod_eq_full := Z.div_mod (compat "8.3").
Notation Zmod_POS_bound := Z.pos_div_eucl_bound (compat "8.3").
Notation Zmod_pos_bound := Z.mod_pos_bound (compat "8.3").
Notation Zmod_neg_bound := Z.mod_neg_bound (compat "8.3").
(** * Main division theorems *)
(** NB: many things are stated twice for compatibility reasons *)
Lemma Z_div_mod_POS :
forall b:Z,
b > 0 ->
forall a:positive,
let (q, r) := Z.pos_div_eucl a b in Zpos a = b * q + r /\ 0 <= r < b.
Proof.
intros b Hb a. Z.swap_greater.
generalize (Z.pos_div_eucl_eq a b Hb) (Z.pos_div_eucl_bound a b Hb).
destruct Z.pos_div_eucl. rewrite Z.mul_comm. auto.
Qed.
Theorem Z_div_mod a b :
b > 0 ->
let (q, r) := Z.div_eucl a b in a = b * q + r /\ 0 <= r < b.
Proof.
Z.swap_greater. intros Hb.
assert (Hb' : b<>0) by (now destruct b).
generalize (Z.div_eucl_eq a b Hb') (Z.mod_pos_bound a b Hb).
unfold Z.modulo. destruct Z.div_eucl. auto.
Qed.
(** For stating the fully general result, let's give a short name
to the condition on the remainder. *)
Definition Remainder r b := 0 <= r < b \/ b < r <= 0.
(** Another equivalent formulation: *)
Definition Remainder_alt r b := Z.abs r < Z.abs b /\ Z.sgn r <> - Z.sgn b.
(* In the last formulation, [ Z.sgn r <> - Z.sgn b ] is less nice than saying
[ Z.sgn r = Z.sgn b ], but at least it works even when [r] is null. *)
Lemma Remainder_equiv : forall r b, Remainder r b <-> Remainder_alt r b.
Proof.
intros; unfold Remainder, Remainder_alt; omega with *.
Qed.
Hint Unfold Remainder.
(** Now comes the fully general result about Euclidean division. *)
Theorem Z_div_mod_full a b :
b <> 0 ->
let (q, r) := Z.div_eucl a b in a = b * q + r /\ Remainder r b.
Proof.
intros Hb.
generalize (Z.div_eucl_eq a b Hb)
(Z.mod_pos_bound a b) (Z.mod_neg_bound a b).
unfold Z.modulo. destruct Z.div_eucl as (q,r).
intros EQ POS NEG.
split; auto.
red; destruct b.
now destruct Hb. left; now apply POS. right; now apply NEG.
Qed.
(** The same results as before, stated separately in terms of Z.div and Z.modulo *)
Lemma Z_mod_remainder a b : b<>0 -> Remainder (a mod b) b.
Proof.
unfold Z.modulo; intros Hb; generalize (Z_div_mod_full a b Hb); auto.
destruct Z.div_eucl; tauto.
Qed.
Lemma Z_mod_lt a b : b > 0 -> 0 <= a mod b < b.
Proof (fun Hb => Z.mod_pos_bound a b (Z.gt_lt _ _ Hb)).
Lemma Z_mod_neg a b : b < 0 -> b < a mod b <= 0.
Proof (Z.mod_neg_bound a b).
Lemma Z_div_mod_eq a b : b > 0 -> a = b*(a/b) + (a mod b).
Proof.
intros Hb; apply Z.div_mod; auto with zarith.
Qed.
Lemma Zmod_eq_full a b : b<>0 -> a mod b = a - (a/b)*b.
Proof. intros. rewrite Z.mul_comm. now apply Z.mod_eq. Qed.
Lemma Zmod_eq a b : b>0 -> a mod b = a - (a/b)*b.
Proof. intros. apply Zmod_eq_full. now destruct b. Qed.
(** Existence theorem *)
Theorem Zdiv_eucl_exist : forall (b:Z)(Hb:b>0)(a:Z),
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < b}.
Proof.
intros b Hb a.
exists (Z.div_eucl a b).
exact (Z_div_mod a b Hb).
Qed.
Arguments Zdiv_eucl_exist : default implicits.
(** Uniqueness theorems *)
Theorem Zdiv_mod_unique b q1 q2 r1 r2 :
0 <= r1 < Z.abs b -> 0 <= r2 < Z.abs b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof.
intros Hr1 Hr2 H. rewrite <- (Z.abs_sgn b), <- !Z.mul_assoc in H.
destruct (Z.div_mod_unique (Z.abs b) (Z.sgn b * q1) (Z.sgn b * q2) r1 r2); auto.
split; trivial.
apply Z.mul_cancel_l with (Z.sgn b); trivial.
rewrite Z.sgn_null_iff, <- Z.abs_0_iff. destruct Hr1; Z.order.
Qed.
Theorem Zdiv_mod_unique_2 :
forall b q1 q2 r1 r2:Z,
Remainder r1 b -> Remainder r2 b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof Z.div_mod_unique.
Theorem Zdiv_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> q = a/b.
Proof Z.div_unique.
Theorem Zdiv_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> q = a/b.
Proof. intros; eapply Zdiv_unique_full; eauto. Qed.
Theorem Zmod_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> r = a mod b.
Proof Z.mod_unique.
Theorem Zmod_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> r = a mod b.
Proof. intros; eapply Zmod_unique_full; eauto. Qed.
(** * Basic values of divisions and modulo. *)
Lemma Zmod_0_l: forall a, 0 mod a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zmod_0_r: forall a, a mod 0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_l: forall a, 0/a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_r: forall a, a/0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Ltac zero_or_not a :=
destruct (Z.eq_dec a 0);
[subst; rewrite ?Zmod_0_l, ?Zdiv_0_l, ?Zmod_0_r, ?Zdiv_0_r;
auto with zarith|].
Lemma Zmod_1_r: forall a, a mod 1 = 0.
Proof. intros. zero_or_not a. apply Z.mod_1_r. Qed.
Lemma Zdiv_1_r: forall a, a/1 = a.
Proof. intros. zero_or_not a. apply Z.div_1_r. Qed.
Hint Resolve Zmod_0_l Zmod_0_r Zdiv_0_l Zdiv_0_r Zdiv_1_r Zmod_1_r
: zarith.
Lemma Zdiv_1_l: forall a, 1 < a -> 1/a = 0.
Proof Z.div_1_l.
Lemma Zmod_1_l: forall a, 1 < a -> 1 mod a = 1.
Proof Z.mod_1_l.
Lemma Z_div_same_full : forall a:Z, a<>0 -> a/a = 1.
Proof Z.div_same.
Lemma Z_mod_same_full : forall a, a mod a = 0.
Proof. intros. zero_or_not a. apply Z.mod_same; auto. Qed.
Lemma Z_mod_mult : forall a b, (a*b) mod b = 0.
Proof. intros. zero_or_not b. apply Z.mod_mul. auto. Qed.
Lemma Z_div_mult_full : forall a b:Z, b <> 0 -> (a*b)/b = a.
Proof Z.div_mul.
(** * Order results about Z.modulo and Z.div *)
(* Division of positive numbers is positive. *)
Lemma Z_div_pos: forall a b, b > 0 -> 0 <= a -> 0 <= a/b.
Proof. intros. apply Z.div_pos; auto with zarith. Qed.
Lemma Z_div_ge0: forall a b, b > 0 -> a >= 0 -> a/b >=0.
Proof.
intros; generalize (Z_div_pos a b H); auto with zarith.
Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_div_lt : forall a b:Z, b >= 2 -> a > 0 -> a/b < a.
Proof. intros. apply Z.div_lt; auto with zarith. Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem Zdiv_small: forall a b, 0 <= a < b -> a/b = 0.
Proof Z.div_small.
(** Same situation, in term of modulo: *)
Theorem Zmod_small: forall a n, 0 <= a < n -> a mod n = a.
Proof Z.mod_small.
(** [Z.ge] is compatible with a positive division. *)
Lemma Z_div_ge : forall a b c:Z, c > 0 -> a >= b -> a/c >= b/c.
Proof. intros. apply Z.le_ge. apply Z.div_le_mono; auto with zarith. Qed.
(** Same, with [Z.le]. *)
Lemma Z_div_le : forall a b c:Z, c > 0 -> a <= b -> a/c <= b/c.
Proof. intros. apply Z.div_le_mono; auto with zarith. Qed.
(** With our choice of division, rounding of (a/b) is always done toward bottom: *)
Lemma Z_mult_div_ge : forall a b:Z, b > 0 -> b*(a/b) <= a.
Proof. intros. apply Z.mul_div_le; auto with zarith. Qed.
Lemma Z_mult_div_ge_neg : forall a b:Z, b < 0 -> b*(a/b) >= a.
Proof. intros. apply Z.le_ge. apply Z.mul_div_ge; auto with zarith. Qed.
(** The previous inequalities are exact iff the modulo is zero. *)
Lemma Z_div_exact_full_1 : forall a b:Z, a = b*(a/b) -> a mod b = 0.
Proof. intros a b. zero_or_not b. rewrite Z.div_exact; auto. Qed.
Lemma Z_div_exact_full_2 : forall a b:Z, b <> 0 -> a mod b = 0 -> a = b*(a/b).
Proof. intros; rewrite Z.div_exact; auto. Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zmod_le: forall a b, 0 < b -> 0 <= a -> a mod b <= a.
Proof. intros. apply Z.mod_le; auto. Qed.
(** Some additionnal inequalities about Z.div. *)
Theorem Zdiv_lt_upper_bound:
forall a b q, 0 < b -> a < q*b -> a/b < q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.div_lt_upper_bound. Qed.
Theorem Zdiv_le_upper_bound:
forall a b q, 0 < b -> a <= q*b -> a/b <= q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.div_le_upper_bound. Qed.
Theorem Zdiv_le_lower_bound:
forall a b q, 0 < b -> q*b <= a -> q <= a/b.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.div_le_lower_bound. Qed.
(** A division of respect opposite monotonicity for the divisor *)
Lemma Zdiv_le_compat_l: forall p q r, 0 <= p -> 0 < q < r ->
p / r <= p / q.
Proof. intros; apply Z.div_le_compat_l; auto with zarith. Qed.
Theorem Zdiv_sgn: forall a b,
0 <= Z.sgn (a/b) * Z.sgn a * Z.sgn b.
Proof.
destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
generalize (Z.div_pos (Zpos a) (Zpos b)); unfold Z.div, Z.div_eucl;
destruct Z.pos_div_eucl as (q,r); destruct r; omega with *.
Qed.
(** * Relations between usual operations and Z.modulo and Z.div *)
Lemma Z_mod_plus_full : forall a b c:Z, (a + b * c) mod c = a mod c.
Proof. intros. zero_or_not c. apply Z.mod_add; auto. Qed.
Lemma Z_div_plus_full : forall a b c:Z, c <> 0 -> (a + b * c) / c = a / c + b.
Proof Z.div_add.
Theorem Z_div_plus_full_l: forall a b c : Z, b <> 0 -> (a * b + c) / b = a + c / b.
Proof Z.div_add_l.
(** [Z.opp] and [Z.div], [Z.modulo].
Due to the choice of convention for our Euclidean division,
some of the relations about [Z.opp] and divisions are rather complex. *)
Lemma Zdiv_opp_opp : forall a b:Z, (-a)/(-b) = a/b.
Proof. intros. zero_or_not b. apply Z.div_opp_opp; auto. Qed.
Lemma Zmod_opp_opp : forall a b:Z, (-a) mod (-b) = - (a mod b).
Proof. intros. zero_or_not b. apply Z.mod_opp_opp; auto. Qed.
Lemma Z_mod_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a) mod b = 0.
Proof. intros. zero_or_not b. apply Z.mod_opp_l_z; auto. Qed.
Lemma Z_mod_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a) mod b = b - (a mod b).
Proof. intros. zero_or_not b. apply Z.mod_opp_l_nz; auto. Qed.
Lemma Z_mod_zero_opp_r : forall a b:Z, a mod b = 0 -> a mod (-b) = 0.
Proof. intros. zero_or_not b. apply Z.mod_opp_r_z; auto. Qed.
Lemma Z_mod_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a mod (-b) = (a mod b) - b.
Proof. intros. zero_or_not b. apply Z.mod_opp_r_nz; auto. Qed.
Lemma Z_div_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a)/b = -(a/b).
Proof. intros. zero_or_not b. apply Z.div_opp_l_z; auto. Qed.
Lemma Z_div_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a)/b = -(a/b)-1.
Proof. intros a b. zero_or_not b. intros; rewrite Z.div_opp_l_nz; auto. Qed.
Lemma Z_div_zero_opp_r : forall a b:Z, a mod b = 0 -> a/(-b) = -(a/b).
Proof. intros. zero_or_not b. apply Z.div_opp_r_z; auto. Qed.
Lemma Z_div_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a/(-b) = -(a/b)-1.
Proof. intros a b. zero_or_not b. intros; rewrite Z.div_opp_r_nz; auto. Qed.
(** Cancellations. *)
Lemma Zdiv_mult_cancel_r : forall a b c:Z,
c <> 0 -> (a*c)/(b*c) = a/b.
Proof. intros. zero_or_not b. apply Z.div_mul_cancel_r; auto. Qed.
Lemma Zdiv_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)/(c*b) = a/b.
Proof.
intros. rewrite (Z.mul_comm c b); zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.div_mul_cancel_l; auto.
Qed.
Lemma Zmult_mod_distr_l: forall a b c,
(c*a) mod (c*b) = c * (a mod b).
Proof.
intros. zero_or_not c. rewrite (Z.mul_comm c b); zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.mul_mod_distr_l; auto.
Qed.
Lemma Zmult_mod_distr_r: forall a b c,
(a*c) mod (b*c) = (a mod b) * c.
Proof.
intros. zero_or_not b. rewrite (Z.mul_comm b c); zero_or_not c.
rewrite (Z.mul_comm c b). apply Z.mul_mod_distr_r; auto.
Qed.
(** Operations modulo. *)
Theorem Zmod_mod: forall a n, (a mod n) mod n = a mod n.
Proof. intros. zero_or_not n. apply Z.mod_mod; auto. Qed.
Theorem Zmult_mod: forall a b n,
(a * b) mod n = ((a mod n) * (b mod n)) mod n.
Proof. intros. zero_or_not n. apply Z.mul_mod; auto. Qed.
Theorem Zplus_mod: forall a b n,
(a + b) mod n = (a mod n + b mod n) mod n.
Proof. intros. zero_or_not n. apply Z.add_mod; auto. Qed.
Theorem Zminus_mod: forall a b n,
(a - b) mod n = (a mod n - b mod n) mod n.
Proof.
intros.
replace (a - b) with (a + (-1) * b); auto with zarith.
replace (a mod n - b mod n) with (a mod n + (-1) * (b mod n)); auto with zarith.
rewrite Zplus_mod.
rewrite Zmult_mod.
rewrite Zplus_mod with (b:=(-1) * (b mod n)).
rewrite Zmult_mod.
rewrite Zmult_mod with (b:= b mod n).
repeat rewrite Zmod_mod; auto.
Qed.
Lemma Zplus_mod_idemp_l: forall a b n, (a mod n + b) mod n = (a + b) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zplus_mod_idemp_r: forall a b n, (b + a mod n) mod n = (b + a) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_l: forall a b n, (a mod n - b) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_r: forall a b n, (a - b mod n) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zmult_mod_idemp_l: forall a b n, (a mod n * b) mod n = (a * b) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
Lemma Zmult_mod_idemp_r: forall a b n, (b * (a mod n)) mod n = (b * a) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
(** For a specific number N, equality modulo N is hence a nice setoid
equivalence, compatible with [+], [-] and [*]. *)
Section EqualityModulo.
Variable N:Z.
Definition eqm a b := (a mod N = b mod N).
Infix "==" := eqm (at level 70).
Lemma eqm_refl : forall a, a == a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_sym : forall a b, a == b -> b == a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_trans : forall a b c,
a == b -> b == c -> a == c.
Proof. unfold eqm; eauto with *. Qed.
Instance eqm_setoid : Equivalence eqm.
Proof.
constructor; [exact eqm_refl | exact eqm_sym | exact eqm_trans].
Qed.
Instance Zplus_eqm : Proper (eqm ==> eqm ==> eqm) Z.add.
Proof.
unfold eqm; repeat red; intros. rewrite Zplus_mod, H, H0, <- Zplus_mod; auto.
Qed.
Instance Zminus_eqm : Proper (eqm ==> eqm ==> eqm) Z.sub.
Proof.
unfold eqm; repeat red; intros. rewrite Zminus_mod, H, H0, <- Zminus_mod; auto.
Qed.
Instance Zmult_eqm : Proper (eqm ==> eqm ==> eqm) Z.mul.
Proof.
unfold eqm; repeat red; intros. rewrite Zmult_mod, H, H0, <- Zmult_mod; auto.
Qed.
Instance Zopp_eqm : Proper (eqm ==> eqm) Z.opp.
Proof.
intros x y H. change ((-x)==(-y)) with ((0-x)==(0-y)). now rewrite H.
Qed.
Lemma Zmod_eqm : forall a, (a mod N) == a.
Proof.
intros; exact (Zmod_mod a N).
Qed.
(* NB: Z.modulo and Z.div are not morphisms with respect to eqm.
For instance, let (==) be (eqm 2). Then we have (3 == 1) but:
~ (3 mod 3 == 1 mod 3)
~ (1 mod 3 == 1 mod 1)
~ (3/3 == 1/3)
~ (1/3 == 1/1)
*)
End EqualityModulo.
Lemma Zdiv_Zdiv : forall a b c, 0<=b -> 0<=c -> (a/b)/c = a/(b*c).
Proof.
intros. zero_or_not b. rewrite Z.mul_comm. zero_or_not c.
rewrite Z.mul_comm. apply Z.div_div; auto with zarith.
Qed.
(** Unfortunately, the previous result isn't always true on negative numbers.
For instance: 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) *)
(** A last inequality: *)
Theorem Zdiv_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof.
intros. zero_or_not b. apply Z.div_mul_le; auto with zarith. Qed.
(** Z.modulo is related to divisibility (see more in Znumtheory) *)
Lemma Zmod_divides : forall a b, b<>0 ->
(a mod b = 0 <-> exists c, a = b*c).
Proof.
intros. rewrite Z.mod_divide; trivial.
split; intros (c,Hc); exists c; subst; auto with zarith.
Qed.
(** Particular case : dividing by 2 is related with parity *)
Lemma Zdiv2_div : forall a, Z.div2 a = a/2.
Proof Z.div2_div.
Lemma Zmod_odd : forall a, a mod 2 = if Z.odd a then 1 else 0.
Proof.
intros a. now rewrite <- Z.bit0_odd, <- Z.bit0_mod.
Qed.
Lemma Zmod_even : forall a, a mod 2 = if Z.even a then 0 else 1.
Proof.
intros a. rewrite Zmod_odd, Zodd_even_bool. now destruct Z.even.
Qed.
Lemma Zodd_mod : forall a, Z.odd a = Zeq_bool (a mod 2) 1.
Proof.
intros a. rewrite Zmod_odd. now destruct Z.odd.
Qed.
Lemma Zeven_mod : forall a, Z.even a = Zeq_bool (a mod 2) 0.
Proof.
intros a. rewrite Zmod_even. now destruct Z.even.
Qed.
(** * Compatibility *)
(** Weaker results kept only for compatibility *)
Lemma Z_mod_same : forall a, a > 0 -> a mod a = 0.
Proof.
intros; apply Z_mod_same_full.
Qed.
Lemma Z_div_same : forall a, a > 0 -> a/a = 1.
Proof.
intros; apply Z_div_same_full; auto with zarith.
Qed.
Lemma Z_div_plus : forall a b c:Z, c > 0 -> (a + b * c) / c = a / c + b.
Proof.
intros; apply Z_div_plus_full; auto with zarith.
Qed.
Lemma Z_div_mult : forall a b:Z, b > 0 -> (a*b)/b = a.
Proof.
intros; apply Z_div_mult_full; auto with zarith.
Qed.
Lemma Z_mod_plus : forall a b c:Z, c > 0 -> (a + b * c) mod c = a mod c.
Proof.
intros; apply Z_mod_plus_full; auto with zarith.
Qed.
Lemma Z_div_exact_1 : forall a b:Z, b > 0 -> a = b*(a/b) -> a mod b = 0.
Proof.
intros; apply Z_div_exact_full_1; auto with zarith.
Qed.
Lemma Z_div_exact_2 : forall a b:Z, b > 0 -> a mod b = 0 -> a = b*(a/b).
Proof.
intros; apply Z_div_exact_full_2; auto with zarith.
Qed.
Lemma Z_mod_zero_opp : forall a b:Z, b > 0 -> a mod b = 0 -> (-a) mod b = 0.
Proof.
intros; apply Z_mod_zero_opp_full; auto with zarith.
Qed.
(** * A direct way to compute Z.modulo *)
Fixpoint Zmod_POS (a : positive) (b : Z) : Z :=
match a with
| xI a' =>
let r := Zmod_POS a' b in
let r' := (2 * r + 1) in
if r' <? b then r' else (r' - b)
| xO a' =>
let r := Zmod_POS a' b in
let r' := (2 * r) in
if r' <? b then r' else (r' - b)
| xH => if 2 <=? b then 1 else 0
end.
Definition Zmod' a b :=
match a with
| Z0 => 0
| Zpos a' =>
match b with
| Z0 => 0
| Zpos _ => Zmod_POS a' b
| Zneg b' =>
let r := Zmod_POS a' (Zpos b') in
match r with Z0 => 0 | _ => b + r end
end
| Zneg a' =>
match b with
| Z0 => 0
| Zpos _ =>
let r := Zmod_POS a' b in
match r with Z0 => 0 | _ => b - r end
| Zneg b' => - (Zmod_POS a' (Zpos b'))
end
end.
Theorem Zmod_POS_correct a b : Zmod_POS a b = snd (Z.pos_div_eucl a b).
Proof.
induction a as [a IH|a IH| ]; simpl; rewrite ?IH.
destruct (Z.pos_div_eucl a b) as (p,q); simpl;
case Z.ltb_spec; reflexivity.
destruct (Z.pos_div_eucl a b) as (p,q); simpl;
case Z.ltb_spec; reflexivity.
case Z.leb_spec; trivial.
Qed.
Theorem Zmod'_correct: forall a b, Zmod' a b = a mod b.
Proof.
intros a b; unfold Z.modulo; case a; simpl; auto.
intros p; case b; simpl; auto.
intros p1; refine (Zmod_POS_correct _ _); auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Z.pos_div_eucl p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p; case b; simpl; auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Z.pos_div_eucl p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p1; rewrite Zmod_POS_correct; simpl; auto.
case (Z.pos_div_eucl p (Zpos p1)); auto.
Qed.
(** Another convention is possible for division by negative numbers:
* quotient is always the biggest integer smaller than or equal to a/b
* remainder is hence always positive or null. *)
Theorem Zdiv_eucl_extended :
forall b:Z,
b <> 0 ->
forall a:Z,
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < Z.abs b}.
Proof.
intros b Hb a.
destruct (Z_le_gt_dec 0 b) as [Hb'|Hb'].
- assert (Hb'' : b > 0) by omega.
rewrite Z.abs_eq; [ apply Zdiv_eucl_exist; assumption | assumption ].
- assert (Hb'' : - b > 0) by omega.
destruct (Zdiv_eucl_exist Hb'' a) as ((q,r),[]).
exists (- q, r).
split.
+ rewrite <- Z.mul_opp_comm; assumption.
+ rewrite Z.abs_neq; [ assumption | omega ].
Qed.
Arguments Zdiv_eucl_extended : default implicits.
(** * Division and modulo in Z agree with same in nat: *)
Require Import PeanoNat.
Lemma div_Zdiv (n m: nat): m <> O ->
Z.of_nat (n / m) = Z.of_nat n / Z.of_nat m.
Proof.
intros.
apply (Zdiv_unique _ _ _ (Z.of_nat (n mod m))).
split. auto with zarith.
now apply inj_lt, Nat.mod_upper_bound.
rewrite <- Nat2Z.inj_mul, <- Nat2Z.inj_add.
now apply inj_eq, Nat.div_mod.
Qed.
Lemma mod_Zmod (n m: nat): m <> O ->
Z.of_nat (n mod m) = (Z.of_nat n) mod (Z.of_nat m).
Proof.
intros.
apply (Zmod_unique _ _ (Z.of_nat n / Z.of_nat m)).
split. auto with zarith.
now apply inj_lt, Nat.mod_upper_bound.
rewrite <- div_Zdiv, <- Nat2Z.inj_mul, <- Nat2Z.inj_add by trivial.
now apply inj_eq, Nat.div_mod.
Qed.
|
`timescale 1ns/1ps
module tb;
`include "useful_tasks.v" // some helper tasks
// `include "ahb_driver.v"
reg rst_async; // asynchronous reset
wire rst_n; // synchronous reset (falling edge)
wire done_r;
wire clk;
parameter AW = 12;
/*AUTOINPUT*/
/*AUTOOUTPUT*/
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [AW-1:0] HADDR; // From U_AHB_DRIVER of ahb_driver.v
wire [31:0] HRDATA; // From U_CHIP of chip.v
wire HREADY; // From U_AHB_DRIVER of ahb_driver.v
wire HREADYOUT; // From U_CHIP of chip.v
wire HRESP; // From U_CHIP of chip.v
wire HSEL; // From U_AHB_DRIVER of ahb_driver.v
wire [2:0] HSIZE; // From U_AHB_DRIVER of ahb_driver.v
wire [1:0] HTRANS; // From U_AHB_DRIVER of ahb_driver.v
wire [31:0] HWDATA; // From U_AHB_DRIVER of ahb_driver.v
wire HWRITE; // From U_AHB_DRIVER of ahb_driver.v
// End of automatics
/* chip AUTO_TEMPLATE(
.HRESETn (rst_n),
); */
chip #(.AW(AW)) U_CHIP
(
.HCLK (clk),
/*AUTOINST*/
// Outputs
.HRDATA (HRDATA[31:0]),
.HREADYOUT (HREADYOUT),
.HRESP (HRESP),
// Inputs
.HADDR (HADDR[AW-1:0]),
.HREADY (HREADY),
.HRESETn (rst_n), // Templated
.HSEL (HSEL),
.HSIZE (HSIZE[2:0]),
.HTRANS (HTRANS[1:0]),
.HWDATA (HWDATA[31:0]),
.HWRITE (HWRITE));
/* ahb_driver AUTO_TEMPLATE(
.HRESETn (rst_n),
); */
ahb_driver #(.AW(AW)) U_AHB_DRIVER (
.HCLK (clk),
/*AUTOINST*/
// Outputs
.HSEL (HSEL),
.HADDR (HADDR[AW-1:0]),
.HTRANS (HTRANS[1:0]),
.HSIZE (HSIZE[2:0]),
.HWRITE (HWRITE),
.HWDATA (HWDATA[31:0]),
.HREADY (HREADY),
// Inputs
.HRESETn (rst_n), // Templated
.HREADYOUT (HREADYOUT),
.HRDATA (HRDATA[31:0]),
.HRESP (HRESP));
clock_gen U_CLK_GEN (
/*AUTOINST*/
// Outputs
.clk (clk));
/* reset_generator AUTO_TEMPLATE(
); */
reset_generator U_RESET_GEN (
/*AUTOINST*/
// Outputs
.rst_n (rst_n),
// Inputs
.clk (clk),
.rst_async (rst_async));
// Dump all nets to a vcd file called tb.vcd
initial
begin
$dumpfile("tb.vcd");
$dumpvars(0,tb);
end
// Start by pulsing the reset low for some nanoseconds
reg [31:0] tmp;
reg [7:0] tmp8;
initial begin
rst_async = 1'b0;
#100;
rst_async = 1'b1;
@(posedge clk);
@(posedge clk);
#3;
U_AHB_DRIVER.t_write32bits_non_seq(12'h010,32'hCAFEBABE);
@(posedge clk);
#3;
U_AHB_DRIVER.t_write32bits_non_seq(12'h014,32'h12345678);
@(posedge clk);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read32bits_non_seq(12'h010,tmp);
check_32bits(tmp,32'hCAFEBABE);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read32bits_non_seq(12'h014,tmp);
check_32bits(tmp,32'h12345678);
@(posedge clk);
#3;
U_AHB_DRIVER.t_write8bits_non_seq(12'h010,8'h55);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read32bits_non_seq(12'h010,tmp);
check_32bits(tmp,32'hCAFEBA55);
@(posedge clk);
#3;
U_AHB_DRIVER.t_write8bits_non_seq(12'h011,8'hAA);
@(posedge clk);
#3;
U_AHB_DRIVER.t_write8bits_non_seq(12'h012,8'hBB);
@(posedge clk);
#3;
U_AHB_DRIVER.t_write8bits_non_seq(12'h013,8'hCC);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read32bits_non_seq(12'h010,tmp);
check_32bits(tmp,32'hCCBBAA55);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read8bits_non_seq(12'h010,tmp8);
check_8bits(tmp8,8'h55);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read8bits_non_seq(12'h011,tmp8);
check_8bits(tmp8,8'hAA);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read8bits_non_seq(12'h012,tmp8);
check_8bits(tmp8,8'hBB);
@(posedge clk);
#3;
U_AHB_DRIVER.t_read8bits_non_seq(12'h013,tmp8);
check_8bits(tmp8,8'hCC);
// Read immediatly followed by a write (Pipelining)
@(posedge clk);
#3;
U_AHB_DRIVER.t_read_then_write_32bits(12'h010,tmp,12'h014,32'hDEADBEEF);
check_32bits(tmp,32'hCCBBAA55);
U_AHB_DRIVER.t_read32bits_non_seq(12'h014,tmp);
check_32bits(tmp,32'h12345678);
@(posedge clk);
#1000;
$display("-I- Done !");
$finish;
end
// watchdog
initial begin
#100000;
$display("-E- Error (watchdog) !");
$finish;
end
endmodule // tb
/*
Local Variables:
verilog-library-directories:(
"."
)
End:
*/
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bram_2048_0 (
clka,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [10 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [19 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [19 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("bram_2048_0.mif"),
.C_INIT_FILE("bram_2048_0.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(20),
.C_READ_WIDTH_A(20),
.C_WRITE_DEPTH_A(2048),
.C_READ_DEPTH_A(2048),
.C_ADDRA_WIDTH(11),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(20),
.C_READ_WIDTH_B(20),
.C_WRITE_DEPTH_B(2048),
.C_READ_DEPTH_B(2048),
.C_ADDRB_WIDTH(11),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("1"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.9373 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(11'B0),
.dinb(20'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(20'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: demux.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: A simple demultiplexer
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "functions.vh"
module demux
#(
parameter C_OUTPUTS = 12,
parameter C_WIDTH = 1
)
(
input [C_WIDTH-1:0] WR_DATA,// Inputs
input [clog2s(C_OUTPUTS)-1:0] WR_SEL,// Selector
output [C_OUTPUTS*C_WIDTH-1:0] RD_DATA// Outputs
);
genvar i;
reg [C_OUTPUTS*C_WIDTH-1:0] _rOut;
assign RD_DATA = _rOut;
always @(*) begin
_rOut = 0;
_rOut[C_WIDTH*WR_SEL +: C_WIDTH] = WR_DATA;
end
endmodule
|
// Released under GPL2.0
// (c) 2002 Tom Verbeure
module main;
integer myInt;
reg [39:0] myReg40;
reg [0:39] myReg40r;
reg [0:38] myReg39r;
reg [13:0] myReg14;
reg [7:0] myReg8;
reg [31:0] myReg32;
initial begin
$display("============================ myReg14 = -10");
myReg14 = -10;
$display(">|16374|");
$display("*|%d|", myReg14);
$display("*|%0d|", myReg14);
$display("*|",myReg14,"|");
$display("============================ myReg14 = 65");
myReg14 = 65;
$display(">| 65|");
$display("*|%d|", myReg14);
$display("*|",myReg14,"|");
$display(">|65|");
$display("*|%0d|", myReg14);
$display(">|0041|");
$display("*|%h|", myReg14);
$display(">|41|");
$display("*|%0h|", myReg14);
$display(">|00101|");
$display("*|%o|", myReg14);
$display(">|101|");
$display("*|%0o|", myReg14);
$display(">|00000001000001|");
$display("*|%b|", myReg14);
$display(">|1000001|");
$display("*|%0b|", myReg14);
$display(">| A|");
$display("*|%s|", myReg14);
$display(">|A|");
$display("*|%0s|", myReg14);
$display("============================ myInt = -10");
myInt = -10;
$display(">| -10|");
$display("*|%d|", myInt);
$display("*|",myInt,"|");
$display(">|-10|");
$display("*|%0d|", myInt);
$display(">|fffffff6|");
$display("*|%h|", myInt);
$display("*|%0h|", myInt);
$display(">|37777777766|");
$display("*|%o|", myInt);
$display("*|%0o|", myInt);
$display(">|11111111111111111111111111110110|");
$display("*|%b|", myInt);
$display("*|%0b|", myInt);
$display("============================ myReg32 = -10");
myReg32 = -10;
$display(">|4294967286|");
$display("*|%d|", myReg32);
$display("*|%0d|", myReg32);
$display("*|",myReg32,"|");
$display(">|fffffff6|");
$display("*|%h|", myReg32);
$display("*|%0h|", myReg32);
$display(">|37777777766|");
$display("*|%o|", myReg32);
$display("*|%0o|", myReg32);
$display("============================ myInt = 65");
myInt = 65;
$display(">| 65|");
$display("*|%d|", myInt);
$display("*|",myInt,"|");
$display(">|65|");
$display("*|%0d|", myInt);
$display(">|00000041|");
$display("*|%h|", myInt);
$display(">|41|");
$display("*|%0h|", myInt);
$display(">|00000000101|");
$display("*|%o|", myInt);
$display(">|101|");
$display("*|%0o|", myInt);
$display(">|00000000000000000000000001000001|");
$display("*|%b|", myInt);
$display(">|1000001|");
$display("*|%0b|", myInt);
$display("*| A|");
$display(">|%s|", myInt);
$display("*|A|");
$display(">|%0s|", myInt);
$display("============================ Print \" A\"");
$display("*| A|");
$display(">|%s|", " A");
$display(">|%0s|", " A");
$display("============================ Print $time");
$display("*| 0|");
$display(">|%t|", $time);
$display("*|0|");
$display(">|%0t|", $time);
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Silicon Spectrum Corporation - All Rights Reserved
// Copyright (C) 2009 - All rights reserved
//
// This File is copyright Silicon Spectrum Corporation and is licensed for
// use by Conexant Systems, Inc., hereafter the "licensee", as defined by the NDA and the
// license agreement.
//
// This code may not be used as a basis for new development without a written
// agreement between Silicon Spectrum and the licensee.
//
// New development includes, but is not limited to new designs based on this
// code, using this code to aid verification or using this code to test code
// developed independently by the licensee.
//
// This copyright notice must be maintained as written, modifying or removing
// this copyright header will be considered a breach of the license agreement.
//
// The licensee may modify the code for the licensed project.
// Silicon Spectrum does not give up the copyright to the original
// file or encumber in any way.
//
// Use of this file is restricted by the license agreement between the
// licensee and Silicon Spectrum, Inc.
//
// Title : Drawing Engine Register block read mux
// File : der_rdmux.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module Reads back the DE registers
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module der_rdmux
(
input [8:2] hb_adr, // host bus address
input [1:0] intm, // Interrupt mask bits.
input [1:0] intp, // Interrupts {CL, DD}.
input [4:0] flow, // Flow Register {PRV, CLP, MCB, DEB}.
input busy, // Busy.
input [14:0] buf_ctrl_1, // buffer control register input
input [31:0] sorg_1, // source origin register input
input [31:0] dorg_1, // destination origin register input
input [11:0] sptch_1, // source pitch register input
input [11:0] dptch_1, // destination pitch register input
input [3:0] opc_1, // opcode register input
input [3:0] rop_1, // raster opcode register input
input [4:0] style_1, // drawing style register input
input [3:0] patrn_1, // drawing pattern style register input
input [2:0] hdf_1, // Host data format.
input [2:0] clp_1, // drawing clip control register input
input [31:0] fore_1, // foreground color register input
input [31:0] back_1, // background color register input
input [3:0] mask_1, // plane mask register input
input [23:0] de_key_1, // raster op mask register input
input [31:0] lpat_1, // line pattern register input
input [15:0] pctrl_1, // line pattern control register input
input [31:0] clptl_1, // clipping top left corner register input
input [31:0] clpbr_1, // clipping bottom right corner register in
input [31:0] xy0_1, // parameter register input XY0
input [31:0] xy1_1, // parameter register input XY1
input [31:0] xy2_1, // parameter register input XY2
input [31:0] xy3_1, // parameter register input XY3
input [31:0] xy4_1, // parameter register input XY4
input [15:0] alpha_1, // Alpha register
input [17:0] acntrl_1, // Alpha Control Register
input [15:0] lpat_state, // line pattern state
input [53:0] dl_rdback, // DLP host bus read back data.
input [1:0] bc_lvl_1,
input [6:0] mem_offset_1, // Select memory region
input [3:0] sorg_upper_1, // Select memory region
output [31:0] hb_dout // output to host bus interface
);
parameter
INTM_INTP = 6'b0_0000_0, // Interrupt mask/int, 0x00.
BUSY_FLOW = 6'b0_0000_1, // Busy/Flow Register, 0x08.
NA_TSORG = 6'b0_0001_1, // Text offset Sorg 0x18.
MEM_BCTRL = 6'b0_0010_0,
DORG_SORG = 6'b0_0010_1,
DPTCH_SPTCH = 6'b0_0100_0,
CMDR = 6'b0_0100_1,
ROP_OPC = 6'b0_0101_0,
PATRN_STYLE = 6'b0_0101_1,
SFD_CLP = 6'b0_0110_0,
BACK_FORE = 6'b0_0110_1,
DEKEY_MASK = 6'b0_0111_0,
PCTRL_LPAT = 6'b0_0111_1,
CLPBR_CLPTL = 6'b0_1000_0,
XY1_XY0 = 6'b0_1000_1,
XY3_XY2 = 6'b0_1001_0,
NA_XY4 = 6'b0_1001_1,
DLCNT_DLADR = 6'b0_1111_1,
TBOARD_ALPHA = 6'b1_0010_1,
ACNTRL_CMD = 6'b1_0110_1;
reg [63:0] hb_dout_i;
/**************************************************************************/
/* */
/* REGISTER READ BACK FUNCTION */
/* */
/**************************************************************************/
always @* begin
hb_dout_i = 64'h0;
case (hb_adr[8:3]) //synopsys parallel_case
INTM_INTP: begin
hb_dout_i[1:0] = intp;
hb_dout_i[33:32] = intm;
end
BUSY_FLOW: begin
hb_dout_i[4:0] = flow;
hb_dout_i[32] = busy;
end
NA_TSORG:
hb_dout_i[63:60] = sorg_upper_1;
MEM_BCTRL: begin
hb_dout_i[2:0] = buf_ctrl_1[2:0];
hb_dout_i[5] = buf_ctrl_1[3];
hb_dout_i[7:6] = bc_lvl_1;
hb_dout_i[8] = buf_ctrl_1[13];
hb_dout_i[15] = buf_ctrl_1[4];
hb_dout_i[23:22] = buf_ctrl_1[6:5];
hb_dout_i[27:24] = buf_ctrl_1[10:7];
hb_dout_i[31:29] = {buf_ctrl_1[14],buf_ctrl_1[12:11]};
hb_dout_i[63:57] = mem_offset_1;
end
DORG_SORG: begin
hb_dout_i[7:0] = sorg_1[7:0];
hb_dout_i[15:8] = sorg_1[15:8];
hb_dout_i[23:16] = sorg_1[23:16];
hb_dout_i[31:24] = sorg_1[31:24];
hb_dout_i[39:32] = dorg_1[7:0];
hb_dout_i[47:40] = dorg_1[15:8];
hb_dout_i[55:48] = dorg_1[23:16];
hb_dout_i[63:56] = dorg_1[31:24];
end
DPTCH_SPTCH: begin
hb_dout_i[7:4] = sptch_1[3:0];
hb_dout_i[15:8] = sptch_1[11:4];
hb_dout_i[39:36] = dptch_1[3:0];
hb_dout_i[47:40] = dptch_1[11:4];
end
CMDR: begin
hb_dout_i[3:0] = opc_1;
hb_dout_i[11:8] = rop_1;
hb_dout_i[20:16] = style_1;
hb_dout_i[23:21] = clp_1;
hb_dout_i[27:24] = patrn_1;
hb_dout_i[30:28] = hdf_1;
end
ROP_OPC: begin
hb_dout_i[3:0] = opc_1;
hb_dout_i[35:32] = rop_1;
end
PATRN_STYLE: begin
hb_dout_i[4:0] = style_1;
hb_dout_i[35:32] = patrn_1;
end
SFD_CLP: begin
hb_dout_i[2:0] = clp_1;
hb_dout_i[34:32] = hdf_1;
end
BACK_FORE: begin
hb_dout_i[7:0] = fore_1[7:0];
hb_dout_i[15:8] = fore_1[15:8];
hb_dout_i[23:16] = fore_1[23:16];
hb_dout_i[31:24] = fore_1[31:24];
hb_dout_i[39:32] = back_1[7:0];
hb_dout_i[47:40] = back_1[15:8];
hb_dout_i[55:48] = back_1[23:16];
hb_dout_i[63:56] = back_1[31:24];
end
DEKEY_MASK: begin
hb_dout_i[7:0] = {8{mask_1[0]}};
hb_dout_i[15:8] = {8{mask_1[1]}};
hb_dout_i[23:16] = {8{mask_1[2]}};
hb_dout_i[31:24] = {8{mask_1[3]}};
hb_dout_i[39:32] = de_key_1[7:0];
hb_dout_i[47:40] = de_key_1[15:8];
hb_dout_i[55:48] = de_key_1[23:16];
end
PCTRL_LPAT: begin
hb_dout_i[7:0] = lpat_1[7:0];
hb_dout_i[15:8] = lpat_1[15:8];
hb_dout_i[23:16] = lpat_1[23:16];
hb_dout_i[31:24] = lpat_1[31:24];
hb_dout_i[39:32] = pctrl_1[7:0];
hb_dout_i[47:40] = pctrl_1[15:8];
hb_dout_i[55:48] = lpat_state[7:0];
hb_dout_i[63:56] = lpat_state[15:8];
end
CLPBR_CLPTL: begin
hb_dout_i[7:0] = clptl_1[7:0];
hb_dout_i[15:8] = clptl_1[15:8];
hb_dout_i[23:16] = clptl_1[23:16];
hb_dout_i[31:24] = clptl_1[31:24];
hb_dout_i[39:32] = clpbr_1[7:0];
hb_dout_i[47:40] = clpbr_1[15:8];
hb_dout_i[55:48] = clpbr_1[23:16];
hb_dout_i[63:56] = clpbr_1[31:24];
end
XY1_XY0: begin
hb_dout_i[7:0] = xy0_1[7:0];
hb_dout_i[15:8] = xy0_1[15:8];
hb_dout_i[23:16] = xy0_1[23:16];
hb_dout_i[31:24] = xy0_1[31:24];
hb_dout_i[39:32] = xy1_1[7:0];
hb_dout_i[47:40] = xy1_1[15:8];
hb_dout_i[55:48] = xy1_1[23:16];
hb_dout_i[63:56] = xy1_1[31:24];
end
XY3_XY2: begin
hb_dout_i[7:0] = xy2_1[7:0];
hb_dout_i[15:8] = xy2_1[15:8];
hb_dout_i[23:16] = xy2_1[23:16];
hb_dout_i[31:24] = xy2_1[31:24];
hb_dout_i[39:32] = xy3_1[7:0];
hb_dout_i[47:40] = xy3_1[15:8];
hb_dout_i[55:48] = xy3_1[23:16];
hb_dout_i[63:56] = xy3_1[31:24];
end
NA_XY4: begin
hb_dout_i[7:0] = xy4_1[7:0];
hb_dout_i[15:8] = xy4_1[15:8];
hb_dout_i[23:16] = xy4_1[23:16];
hb_dout_i[31:24] = xy4_1[31:24];
end
DLCNT_DLADR: begin
hb_dout_i[7:4] = dl_rdback[3:0];
hb_dout_i[15:8] = dl_rdback[11:4];
hb_dout_i[23:16] = dl_rdback[19:12];
hb_dout_i[27:24] = {dl_rdback[53:51],dl_rdback[20]};
hb_dout_i[31:30] = dl_rdback[22:21];
hb_dout_i[39:36] = dl_rdback[26:23];
hb_dout_i[47:40] = dl_rdback[34:27];
hb_dout_i[55:48] = dl_rdback[42:35];
hb_dout_i[56] = dl_rdback[43];
hb_dout_i[63:60] = dl_rdback[47:44];
end
TBOARD_ALPHA: begin
hb_dout_i[7:0] = alpha_1[7:0];
hb_dout_i[15:8] = alpha_1[15:8];
end
ACNTRL_CMD: begin
hb_dout_i[3:0] = opc_1;
hb_dout_i[11:8] = rop_1;
hb_dout_i[20:16] = style_1;
hb_dout_i[23:21] = clp_1;
hb_dout_i[27:24] = patrn_1;
hb_dout_i[30:28] = hdf_1;
hb_dout_i[39:32] = acntrl_1[7:0];
hb_dout_i[42:40] = {acntrl_1[10:8]};
hb_dout_i[51:48] = {acntrl_1[14:11]};
hb_dout_i[58:56] = {acntrl_1[17:15]};
end
default: hb_dout_i = 64'h0;
endcase
end
assign hb_dout = (hb_adr[2]) ? hb_dout_i[63:32] : hb_dout_i[31:0];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
`define zednkw 200
module BreadAddrDP (zfghtn, cjtmau, vipmpg, knquim, kqxkkr);
input zfghtn;
input [4:0] cjtmau;
input vipmpg;
input [7:0] knquim;
input [7:0] kqxkkr;
reg covfok;
reg [15:0] xwieqw;
reg [2:0] ofnjjt;
reg [37:0] hdsejo[1:0];
reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq;
reg vrqrih, ryyjxy;
reg fgzsox;
wire xdjikl = ~wxxzgd & ~tceppr & ~ratebp & fjizkr;
wire iytyol = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & ~xwieqw[10];
wire dywooz = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & xwieqw[10];
wire qnpfus = ~wxxzgd & ~tceppr & ratebp & fjizkr;
wire fqlkrg = ~wxxzgd & tceppr & ~ratebp & ~fjizkr;
wire ktsveg = hdsejo[0][6] | (hdsejo[0][37:34] == 4'h1);
wire smxixw = vrqrih | (ryyjxy & ktsveg);
wire [7:0] grvsrs, kyxrft, uxhkka;
wire [7:0] eianuv = 8'h01 << ofnjjt;
wire [7:0] jvpnxn = {8{qnpfus}} & eianuv;
wire [7:0] zlnzlj = {8{fqlkrg}} & eianuv;
wire [7:0] nahzat = {8{iytyol}} & eianuv;
genvar i;
generate
for (i=0;i<8;i=i+1)
begin : dnlpyw
DecCountReg4 bzpytc (zfghtn, fgzsox, zlnzlj[i],
knquim[3:0], covfok, grvsrs[i]);
DecCountReg4 oghukp (zfghtn, fgzsox, zlnzlj[i],
knquim[7:4], covfok, kyxrft[i]);
DecCountReg4 ttvjoo (zfghtn, fgzsox, nahzat[i],
kqxkkr[3:0], covfok, uxhkka[i]);
end
endgenerate
endmodule
module DecCountReg4 (clk, fgzsox, fckiyr, uezcjy, covfok, juvlsh);
input clk, fgzsox, fckiyr, covfok;
input [3:0] uezcjy;
output juvlsh;
task Xinit;
begin
`ifdef TEST_HARNESS
khgawe = 1'b0;
`endif
end
endtask
function X;
input vrdejo;
begin
`ifdef TEST_HARNESS
if ((vrdejo & ~vrdejo) !== 1'h0) khgawe = 1'b1;
`endif
X = vrdejo;
end
endfunction
task Xcheck;
input vzpwwy;
begin
end
endtask
reg [3:0] udbvtl;
assign juvlsh = |udbvtl;
wire [3:0] mppedc = {4{fgzsox}} & (fckiyr ? uezcjy : (udbvtl - 4'h1));
wire qqibou = ((juvlsh | fckiyr) & covfok) | ~fgzsox;
always @(posedge clk)
begin
Xinit;
if (X(qqibou))
udbvtl <= #`zednkw mppedc;
Xcheck(fgzsox);
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// HashVoodoo Top Module
// Paul Mumby 2012
//////////////////////////////////////////////////////////////////////////////////
module HASHVOODOO (
clk_p,
clk_n,
clk_comm,
RxD,
TxD,
led,
dip,
reset_a,
reset_b,
reset_select
);
function integer clog2; // Courtesy of razorfishsl, replaces $clog2()
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
//Parameters:
//================================================
parameter CLOCK_RATE = 25000000; //Input Clock Output from Controller in Hz
parameter DCM_DIVIDER = 10; //Starting point for DCM divider (25Mhz / 10 = 2.5Mhz increments)
parameter DCM_MULTIPLIER_START = 70; //Starting point for DCM multiplier (2.5Mhz x 70 = 175Mhz)
parameter DCM_MULTIPLIER_CAP = 120; //Max Point Allowed for DCM multiplier (Safety ceiling) - KRAMBLE now 300MHz
parameter DCM_MULTIPLIER_MIN = 20; //Minimum Allowed for DCM multiplier (If it falls below this something is seriously wrong)
parameter UART_BAUD_RATE = 115200; //Baud Rate to use for UART (BPS)
parameter UART_SAMPLE_POINT = 8; //Point in the oversampled wave to sample the bit state for the UART (6-12 should be valid)
parameter CLOCK_FLASH_BITS = 26; //Number of bits for divider of flasher. (28bit = approx 67M Divider)
// `define DUALCORE // Comment out for single core (dual core does not currently route)
`ifdef DUALCORE
localparam LOCAL_MINERS = 2; // One or two cores (configures ADDRBITS automatically)
`else
localparam LOCAL_MINERS = 1; // One or two cores (configures ADDRBITS automatically)
`endif
localparam ADDRBITS = 12 - clog2(LOCAL_MINERS); // Automatically selects largest RAM that will fit LX150
localparam SBITS = 8; // Shift data path width
//IO Definitions:
//================================================
input clk_p; //Input Clock From Controller (P signal of diff pair)
input clk_n; //Input Clock From Controller (N signal of diff pair)
input clk_comm; //Input Comm Clock From Controller (Single ended)
input RxD; //UART RX Pin (From Controller)
output TxD; //UART TX Pin (To Controller)
output [3:0] led; //LED Array
input [3:0]dip; //DIP Switch Array
input reset_a; //Reset Signal A (position dependant) from Controller
input reset_b; //Reset Signal B (position dependant) from Controller
input reset_select; //Reset Selector (hard wired based on position)
//Register/Wire Definitions:
//================================================
reg reset; //Actual Reset Signal
wire clk_buf; //Actually Used Clock Signals
wire clk_dcm; //Output of hash clock DCM
wire clk_comm_buf;
wire clock_flash; //Flasher output (24bit divider of clock)
wire miner_busy; //Miner Busy Flag
wire serial_send; //Serial Send flag, Triggers UART to begin sending what's in it's buffer
wire serial_busy; //Serial Busy flag, Indicates the UART is currently working
wire [31:0] golden_nonce; //Overall Found Golden Nonce
wire [255:0] data1, data2;
wire [127:0] data3;
wire start_mining; //Start Mining flag. This flag going high will trigger the worker to begin hashing on it's buffer
wire syncstart_mining; //Clock crossing (redirected from reset_a in simulation)
reg syncstart_mining_d = 1'b0;
wire led_nonce_fade; //This is the output from the fader, jumps to full power when nonce found and fades out
wire led_serial_fade; //Output from fader for serial activity.
wire dcm_prog_en;
wire dcm_prog_data;
wire dcm_prog_done;
wire dcm_valid;
wire dcm_reset = 1'b0;
wire identify_flag;
wire identify_flasher;
reg [3:0] syncticket1 = 0; //Clock domain sync
wire got_ticket1; //Got Ticket flag indicates the local worker found a new nonce.
`ifdef DUALCORE
wire [63:0] slave_nonces; //Nonce found by worker
reg [1:0] new_nonces; //Flag indicating new nonces found
reg [3:0] syncticket2 = 0;
wire got_ticket2;
`else
wire [31:0] slave_nonces;
reg [0:0] new_nonces; //Flag indicating new nonces found
`endif
//Assignments:
//================================================
// KRAMBLE swapped blue and geen leds as blue is far brighter and better as nonce indicator
assign led[0] = (led_serial_fade || identify_flasher); //LED0 (Green): UART Activity (blinks and fades on either rx or tx)
assign led[1] = (clock_flash || ~dcm_valid || identify_flasher); //LED1 (Red): Clock Heartbeat (blinks to indicate working input clock)
// Off = no clock
// On Solid = dcm invalid.
assign led[2] = (led_nonce_fade || identify_flasher); //LED2 (Blue): New Nonce Beacon (fader)
assign led[3] = (~miner_busy || identify_flasher); //LED3 (Amber): Idle Indicator. Lights when miner has nothing to do.
assign identify_flasher = (clock_flash && identify_flag); //Identify Mode (ALL LEDs flash with heartbeat)
//Module Instantiation:
//================================================
`ifndef SIM
//LVDS Clock Buffer
IBUFGDS #(
.DIFF_TERM("TRUE"),
.IOSTANDARD("DEFAULT")
) CLK_LVDS_BUF (
.O(clk_buf),
.I(clk_p), //Diff_p clock input
.IB(clk_n) //Diff_n clock input
);
//Comm Clock Buffer
BUFG CLK_COMM_BUF
(
.I (clk_comm),
.O (clk_comm_buf)
);
//Dynamically Programmable Hash Clock DCM
main_dcm #(
.DCM_DIVIDER(DCM_DIVIDER),
.DCM_MULTIPLIER(DCM_MULTIPLIER_START)
) MAINDCM(
.RESET(dcm_reset),
.CLK_VALID(dcm_valid),
.CLK_OSC(clk_buf),
.CLK_HASH(clk_dcm), // KRAMBLE now divide 4 (typically 50MHz for nominal 200MHz)
.PROGCLK(clk_comm_buf),
.PROGDATA(dcm_prog_data),
.PROGEN(dcm_prog_en),
.PROGDONE(dcm_prog_done)
);
`else
assign clk_buf = clk_p;
assign clk_dcm = clk_buf;
assign clk_comm_buf = clk_comm;
`endif
//DCM Controller Core (controls dcm clock based on special (malformed) icarus work packets which act as "command" packets
dcm_controller #(
.MAXIMUM_MULTIPLIER(DCM_MULTIPLIER_CAP),
.MINIMUM_MULTIPLIER(DCM_MULTIPLIER_MIN),
.INITIAL_MULTIPLIER(DCM_MULTIPLIER_START),
.INITIAL_DIVIDER(DCM_DIVIDER)
) DCM_CONTROL (
.clk(clk_comm_buf),
.data2({data2[255:96], data3[95:0]}), // KRAMBLE Align with timestamp field in data3
.midstate(data1), // KRAMBLE all zero's for valid command packet
.start(start_mining),
.dcm_prog_clk(clk_comm_buf),
.dcm_prog_en(dcm_prog_en),
.dcm_prog_data(dcm_prog_data),
.dcm_prog_done(dcm_prog_done),
.identify(identify_flag)
);
//Hub core, this is a holdover from Icarus. KRAMBLE: now in use since multiple hasher cores.
hub_core #(
.SLAVES(LOCAL_MINERS)
) HUBCORE (
.hash_clk(clk_comm_buf),
.new_nonces(new_nonces),
.golden_nonce(golden_nonce),
.serial_send(serial_send),
.serial_busy(serial_busy),
.slave_nonces(slave_nonces)
);
//New Serial Core. Handles all communications in and out to the host.
wire unused_rx_busy;
serial_core #(
.CLOCK(CLOCK_RATE),
.BAUD(UART_BAUD_RATE),
.SAMPLE_POINT(UART_SAMPLE_POINT)
) SERIAL_COMM (
.clk(clk_comm_buf),
.rx(RxD),
.tx(TxD),
.rx_ready(start_mining),
.tx_ready(serial_send),
.data1(data1),
.data2(data2),
.data3(data3),
.word(golden_nonce),
.tx_busy(serial_busy),
.rx_busy(unused_rx_busy)
);
wire [31:0] unused_nonce_out1, unused_hash_out1;
wire [31:0] unused_nonce_out2, unused_hash_out2;
// NB For now using same clk for both P and S
reg loadnonce = 1'b0; // Generate loadnonce strobe for new work (NB this initiates a full engine reset)
reg [3:0]syncloadnonce = 3'd0;
wire [31:0] mod_target = 32'h00007fff; // Hard coded for diff=2
wire gn_match_1;
wire [31:0] golden_nonce_1;
wire [31:0] hash_1, nonce_out_1; // nonce_out_1 used for miner_busy
wire salsa_busy_1, salsa_result_1, salsa_reset_1, salsa_start_1, salsa_shift_1;
wire [SBITS-1:0] salsa_din_1;
wire [SBITS-1:0] salsa_dout_1;
pbkdfengine #(.SBITS(SBITS)) P1
(.hash_clk(clk_dcm), .pbkdf_clk(clk_dcm), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd0 ), .nonce_out(nonce_out_1), .golden_nonce_out(golden_nonce_1),
.golden_nonce_match(gn_match_1), .loadnonce(loadnonce),
.salsa_din(salsa_din_1), .salsa_dout(salsa_dout_1), .salsa_busy(salsa_busy_1), .salsa_result(salsa_result_1),
.salsa_reset(salsa_reset_1), .salsa_start(salsa_start_1), .salsa_shift(salsa_shift_1), .hash_out(hash_1));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S1
(.hash_clk(clk_dcm), .reset(salsa_reset_1), .din(salsa_din_1), .dout(salsa_dout_1),
.shift(salsa_shift_1), .start(salsa_start_1), .busy(salsa_busy_1), .result(salsa_result_1) );
`ifdef DUALCORE
wire gn_match_2;
wire [31:0] golden_nonce_2;
wire [31:0] hash_2, nonce_out_2; // both unused
wire salsa_busy_2, salsa_result_2, salsa_reset_2, salsa_start_2, salsa_shift_2;
wire [SBITS-1:0] salsa_din_2;
wire [SBITS-1:0] salsa_dout_2;
pbkdfengine #(.SBITS(SBITS)) P2
(.hash_clk(clk_dcm), .pbkdf_clk(clk_dcm), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb( 4'd8 ), .nonce_out(nonce_out_2), .golden_nonce_out(golden_nonce_2),
.golden_nonce_match(gn_match_2), .loadnonce(loadnonce),
.salsa_din(salsa_din_2), .salsa_dout(salsa_dout_2), .salsa_busy(salsa_busy_2), .salsa_result(salsa_result_2),
.salsa_reset(salsa_reset_2), .salsa_start(salsa_start_2), .salsa_shift(salsa_shift_2), .hash_out(hash_2));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S2
(.hash_clk(clk_dcm), .reset(salsa_reset_2), .din(salsa_din_2), .dout(salsa_dout_2),
.shift(salsa_shift_2), .start(salsa_start_2), .busy(salsa_busy_2), .result(salsa_result_2) );
assign got_ticket1 = gn_match_1;
assign got_ticket2 = gn_match_2;
assign slave_nonces = { golden_nonce_2 , golden_nonce_1 };
`else
// Single core
assign got_ticket1 = gn_match_1;
assign slave_nonces = golden_nonce_1;
`endif
assign miner_busy = ~ (|nonce_out_1[30:20]); // Set idle if nonce > 1M (ignore MSB)
//Flasher, this handles dividing down the comm clock by 24bits to blink the clock status LED
flasher #(
.BITS(CLOCK_FLASH_BITS)
) CLK_FLASH (
.clk(clk_dcm),
.flash(clock_flash)
);
//Nonce PWM Fader core. This triggers on a new nonce found, flashes to full brightness, then fades out for nonce found LED.
pwm_fade PWM_FADE_NONCE (
.clk(clk_comm_buf),
.trigger(|new_nonces),
.drive(led_nonce_fade)
);
//Serial PWM Fader core. This triggers on a new nonce found, flashes to full brightness, then fades out for nonce found LED.
pwm_fade PWM_FADE_COMM (
.clk(clk_comm_buf),
.trigger(~TxD || ~RxD),
.drive(led_serial_fade)
);
// Clock Crossing
`ifdef SIM
assign syncstart_mining = reset_a; // Used only for simulation
`else
assign syncstart_mining = start_mining;
`endif
always@ (posedge clk_dcm)
begin
if (got_ticket1)
syncticket1[0] <= ~syncticket1[0];
`ifdef DUALCORE
if (got_ticket2)
syncticket2[0] <= ~syncticket2[0];
`endif
syncloadnonce[3:1] <= syncloadnonce[2:0];
loadnonce <= (syncloadnonce[3] != syncloadnonce[2]);
end
always@ (posedge clk_comm_buf)
begin
syncticket1[3:1] <= syncticket1[2:0];
new_nonces[0] <= (syncticket1[3] != syncticket1[2]);
`ifdef DUALCORE
syncticket2[3:1] <= syncticket2[2:0];
new_nonces[1] <= (syncticket2[3] != syncticket2[2]);
`endif
syncstart_mining_d <= syncstart_mining;
if (syncstart_mining & ~syncstart_mining_d)
syncloadnonce[0] <= ~ syncloadnonce[0];
end
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ********************************************************************************************************************************
// File name: acv_hard_memphy.v
// This file instantiates all the main components of the PHY.
// ********************************************************************************************************************************
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_memphy (
global_reset_n,
soft_reset_n,
ctl_reset_n,
ctl_reset_export_n,
afi_reset_n,
pll_locked,
oct_ctl_rs_value,
oct_ctl_rt_value,
afi_addr,
afi_ba,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_we_n,
afi_cas_n,
afi_rst_n,
afi_odt,
afi_mem_clk_disable,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_rdata,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata_valid,
afi_wlat,
afi_rlat,
afi_cal_success,
afi_cal_fail,
avl_read,
avl_write,
avl_address,
avl_writedata,
avl_waitrequest,
avl_readdata,
cfg_addlat,
cfg_bankaddrwidth,
cfg_caswrlat,
cfg_coladdrwidth,
cfg_csaddrwidth,
cfg_devicewidth,
cfg_dramconfig,
cfg_interfacewidth,
cfg_rowaddrwidth,
cfg_tcl,
cfg_tmrd,
cfg_trefi,
cfg_trfc,
cfg_twr,
io_intaddrdout,
io_intbadout,
io_intcasndout,
io_intckdout,
io_intckedout,
io_intckndout,
io_intcsndout,
io_intdmdout,
io_intdqdin,
io_intdqdout,
io_intdqoe,
io_intdqsbdout,
io_intdqsboe,
io_intdqsdout,
io_intdqslogicdqsena,
io_intdqslogicfiforeset,
io_intdqslogicincrdataen,
io_intdqslogicincwrptr,
io_intdqslogicoct,
io_intdqslogicrdatavalid,
io_intdqslogicreadlatency,
io_intdqsoe,
io_intodtdout,
io_intrasndout,
io_intresetndout,
io_intwendout,
io_intafirlat,
io_intafiwlat,
io_intaficalfail,
io_intaficalsuccess,
mem_a,
mem_ba,
mem_cs_n,
mem_cke,
mem_odt,
mem_we_n,
mem_ras_n,
mem_cas_n,
mem_reset_n,
mem_dq,
mem_dm,
mem_ck,
mem_ck_n,
mem_dqs,
mem_dqs_n,
reset_n_scc_clk,
reset_n_avl_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
capture_strobe_tracking,
phy_clk,
ctl_clk,
phy_reset_n,
pll_afi_clk,
pll_afi_half_clk,
pll_addr_cmd_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_write_clk,
pll_write_clk_pre_phy_clk,
pll_dqs_ena_clk,
seq_clk,
pll_avl_clk,
pll_config_clk,
dll_clk,
dll_pll_locked,
dll_phy_delayctrl
);
// ********************************************************************************************************************************
// BEGIN PARAMETER SECTION
// All parameters default to "" will have their values passed in from higher level wrapper with the controller and driver
parameter DEVICE_FAMILY = "";
parameter IS_HHP_HPS = "false";
// On-chip termination
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
// PHY-Memory Interface
// Memory device specific parameters, they are set according to the memory spec
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_IF_CS_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
// PHY-Controller (AFI) Interface
// The AFI interface widths are derived from the memory interface widths based on full/half rate operations
// The calculations are done on higher level wrapper
// DLL Interface
// The DLL delay output control is always 6 bits for current existing devices
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter MR1_ODS = "";
parameter MR1_RTT = "";
parameter MR2_RTT_WR = "";
parameter TB_PROTOCOL = "";
parameter TB_MEM_CLK_FREQ = "";
parameter TB_RATE = "";
parameter TB_MEM_DQ_WIDTH = "";
parameter TB_MEM_DQS_WIDTH = "";
parameter TB_PLL_DLL_MASTER = "";
parameter FAST_SIM_MODEL = "";
parameter FAST_SIM_CALIBRATION = "";
// Width of the calibration status register used to control calibration skipping.
parameter CALIB_REG_WIDTH = "";
parameter AC_ROM_INIT_FILE_NAME = "";
parameter INST_ROM_INIT_FILE_NAME = "";
// The number of AFI Resets to generate
localparam NUM_AFI_RESET = 4;
// Addr/cmd clock phase
localparam ADC_PHASE_SETTING = 0;
localparam ADC_INVERT_PHASE = "true";
// END PARAMETER SECTION
// ********************************************************************************************************************************
// ********************************************************************************************************************************
// BEGIN PORT SECTION
// Reset Interface
input global_reset_n; // Resets (active-low) the whole system (all PHY logic + PLL)
input soft_reset_n; // Resets (active-low) PHY logic only, PLL is NOT reset
input pll_locked; // Indicates that PLL is locked
output ctl_reset_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output ctl_reset_export_n; // Asynchronously asserted and synchronously de-asserted on ctl_clk domain
output afi_reset_n; // Asynchronously asserted and synchronously de-asserted on afi_clk domain
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
// PHY-Controller Interface, AFI 2.0
// Control Interface
input [19:0] afi_addr;
input [2:0] afi_ba;
input [1:0] afi_cke;
input [1:0] afi_cs_n;
input [0:0] afi_cas_n;
input [1:0] afi_odt;
input [0:0] afi_ras_n;
input [0:0] afi_we_n;
input [0:0] afi_rst_n;
input [0:0] afi_mem_clk_disable;
input [4:0] afi_dqs_burst;
output [3:0] afi_wlat;
output [4:0] afi_rlat;
// Write data interface
input [79:0] afi_wdata; // write data
input [4:0] afi_wdata_valid; // write data valid, used to maintain write latency required by protocol spec
input [9:0] afi_dm; // write data mask
// Read data interface
output [79:0] afi_rdata; // read data
input [4:0] afi_rdata_en; // read enable, used to maintain the read latency calibrated by PHY
input [4:0] afi_rdata_en_full; // read enable full burst, used to create DQS enable
output [0:0] afi_rdata_valid; // read data valid
// Status interface
output afi_cal_success; // calibration success
output afi_cal_fail; // calibration failure
// Avalon interface to the sequencer
input [15:0] avl_address; //MarkW TODO: the sequencer only uses 13 bits
input avl_read;
output [31:0] avl_readdata;
output avl_waitrequest;
input avl_write;
input [31:0] avl_writedata;
// Configuration interface to the memory controller
input [7:0] cfg_addlat;
input [7:0] cfg_bankaddrwidth;
input [7:0] cfg_caswrlat;
input [7:0] cfg_coladdrwidth;
input [7:0] cfg_csaddrwidth;
input [7:0] cfg_devicewidth;
input [23:0] cfg_dramconfig;
input [7:0] cfg_interfacewidth;
input [7:0] cfg_rowaddrwidth;
input [7:0] cfg_tcl;
input [7:0] cfg_tmrd;
input [15:0] cfg_trefi;
input [7:0] cfg_trfc;
input [7:0] cfg_twr;
// IO/bypass interface to the core (or soft controller)
input [63:0] io_intaddrdout;
input [11:0] io_intbadout;
input [3:0] io_intcasndout;
input [3:0] io_intckdout;
input [7:0] io_intckedout;
input [3:0] io_intckndout;
input [7:0] io_intcsndout;
input [19:0] io_intdmdout;
output [179:0] io_intdqdin;
input [179:0] io_intdqdout;
input [89:0] io_intdqoe;
input [19:0] io_intdqsbdout;
input [9:0] io_intdqsboe;
input [19:0] io_intdqsdout;
input [9:0] io_intdqslogicdqsena;
input [4:0] io_intdqslogicfiforeset;
input [9:0] io_intdqslogicincrdataen;
input [9:0] io_intdqslogicincwrptr;
input [9:0] io_intdqslogicoct;
output [4:0] io_intdqslogicrdatavalid;
input [24:0] io_intdqslogicreadlatency;
input [9:0] io_intdqsoe;
input [7:0] io_intodtdout;
input [3:0] io_intrasndout;
input [3:0] io_intresetndout;
input [3:0] io_intwendout;
output [4:0] io_intafirlat;
output [3:0] io_intafiwlat;
output io_intaficalfail;
output io_intaficalsuccess;
// PHY-Memory Interface
output [MEM_ADDRESS_WIDTH-1:0] mem_a;
output [MEM_BANK_WIDTH-1:0] mem_ba;
output [MEM_IF_CS_WIDTH-1:0] mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] mem_cke;
output [MEM_ODT_WIDTH-1:0] mem_odt;
output [MEM_CONTROL_WIDTH-1:0] mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] mem_cas_n;
output mem_reset_n;
inout [MEM_DQ_WIDTH-1:0] mem_dq;
output [MEM_DM_WIDTH-1:0] mem_dm;
output [MEM_CK_WIDTH-1:0] mem_ck;
output [MEM_CK_WIDTH-1:0] mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
output reset_n_scc_clk;
output reset_n_avl_clk;
// Scan chain configuration manager interface
input scc_data;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH-1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH-1:0] scc_dq_ena;
input [MEM_DM_WIDTH-1:0] scc_dm_ena;
input [0:0] scc_upd;
output [MEM_READ_DQS_WIDTH-1:0] capture_strobe_tracking;
output phy_clk;
output ctl_clk;
output phy_reset_n;
// PLL Interface
input pll_afi_clk; // clocks AFI interface logic
input pll_afi_half_clk; //
input pll_addr_cmd_clk; // clocks address/command DDIO
input pll_mem_clk; // output clock to memory
input pll_write_clk; // clocks write data DDIO
input pll_write_clk_pre_phy_clk;
input pll_dqs_ena_clk;
input seq_clk;
input pll_avl_clk;
input pll_config_clk;
input pll_mem_phy_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
// DLL Interface
output dll_clk;
output dll_pll_locked;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl; // dll output used to control the input DQS phase shift
// END PARAMETER SECTION
// ********************************************************************************************************************************
wire [179:0] ddio_phy_dqdin;
wire [4:0] ddio_phy_dqslogic_rdatavalid;
wire [63:0] phy_ddio_address;
wire [11:0] phy_ddio_bank;
wire [3:0] phy_ddio_cas_n;
wire [3:0] phy_ddio_ck;
wire [7:0] phy_ddio_cke;
wire [3:0] phy_ddio_ck_n;
wire [7:0] phy_ddio_cs_n;
wire [19:0] phy_ddio_dmdout;
wire [179:0] phy_ddio_dqdout;
wire [89:0] phy_ddio_dqoe;
wire [9:0] phy_ddio_dqsb_oe;
wire [9:0] phy_ddio_dqslogic_dqsena;
wire [4:0] phy_ddio_dqslogic_fiforeset;
wire [4:0] phy_ddio_dqslogic_aclr_pstamble;
wire [4:0] phy_ddio_dqslogic_aclr_fifoctrl;
wire [9:0] phy_ddio_dqslogic_incrdataen;
wire [9:0] phy_ddio_dqslogic_incwrptr;
wire [9:0] phy_ddio_dqslogic_oct;
wire [24:0] phy_ddio_dqslogic_readlatency;
wire [9:0] phy_ddio_dqs_oe;
wire [19:0] phy_ddio_dqs_dout;
wire [7:0] phy_ddio_odt;
wire [3:0] phy_ddio_ras_n;
wire [3:0] phy_ddio_reset_n;
wire [3:0] phy_ddio_we_n;
wire read_capture_clk;
wire [NUM_AFI_RESET-1:0] reset_n_afi_clk;
wire reset_n_addr_cmd_clk;
wire reset_n_seq_clk;
wire reset_n_scc_clk;
wire reset_n_avl_clk;
wire reset_n_resync_clk;
localparam SKIP_CALIBRATION_STEPS = 7'b1111111;
localparam CALIBRATION_STEPS = SKIP_CALIBRATION_STEPS;
localparam SKIP_MEM_INIT = 1'b1;
localparam SEQ_CALIB_INIT = {CALIBRATION_STEPS, SKIP_MEM_INIT};
generate
if (IS_HHP_HPS != "true") begin
reg [CALIB_REG_WIDTH-1:0] seq_calib_init_reg /* synthesis syn_noprune syn_preserve = 1 */;
// Initialization of the sequencer status register. This register
// is preserved in the netlist so that it can be forced during simulation
always @(posedge pll_afi_clk)
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_off
`endif
seq_calib_init_reg <= SEQ_CALIB_INIT;
`ifdef SYNTH_FOR_SIM
`else
//synthesis translate_on
//synthesis read_comments_as_HDL on
`endif
// seq_calib_init_reg <= {CALIB_REG_WIDTH{1'b0}};
`ifdef SYNTH_FOR_SIM
`else
// synthesis read_comments_as_HDL off
`endif
end
endgenerate
// ********************************************************************************************************************************
// The reset scheme used in the UNIPHY is asynchronous assert and synchronous de-assert
// The reset block has 2 main functionalities:
// 1. Keep all the PHY logic in reset state until after the PLL is locked
// 2. Synchronize the reset to each clock domain
// ********************************************************************************************************************************
generate
if (IS_HHP_HPS != "true") begin
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
end else begin
// synthesis translate_off
hps_sdram_p0_reset ureset(
.pll_afi_clk (pll_afi_clk),
.pll_addr_cmd_clk (pll_addr_cmd_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.seq_clk (seq_clk),
.pll_avl_clk (pll_avl_clk),
.scc_clk (pll_config_clk),
.reset_n_scc_clk (reset_n_scc_clk),
.reset_n_avl_clk (reset_n_avl_clk),
.read_capture_clk (read_capture_clk),
.pll_locked (pll_locked),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.ctl_reset_export_n (ctl_reset_export_n),
.reset_n_afi_clk (reset_n_afi_clk),
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_seq_clk (reset_n_seq_clk),
.reset_n_resync_clk (reset_n_resync_clk)
);
defparam ureset.MEM_READ_DQS_WIDTH = MEM_READ_DQS_WIDTH;
defparam ureset.NUM_AFI_RESET = NUM_AFI_RESET;
// synthesis translate_on
// synthesis read_comments_as_HDL on
// assign reset_n_afi_clk = {NUM_AFI_RESET{global_reset_n}};
// assign reset_n_addr_cmd_clk = global_reset_n;
// assign reset_n_avl_clk = global_reset_n;
// assign reset_n_scc_clk = global_reset_n;
// synthesis read_comments_as_HDL off
end
endgenerate
assign phy_clk = seq_clk;
assign phy_reset_n = reset_n_seq_clk;
assign dll_clk = pll_write_clk_pre_phy_clk;
assign dll_pll_locked = pll_locked;
// PHY clock and LDC
wire afi_clk;
wire avl_clk;
wire adc_clk;
wire adc_clk_cps;
hps_sdram_p0_acv_ldc # (
.DLL_DELAY_CTRL_WIDTH (DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING (ADC_PHASE_SETTING),
.ADC_INVERT_PHASE (ADC_INVERT_PHASE),
.IS_HHP_HPS (IS_HHP_HPS)
) memphy_ldc (
.pll_hr_clk (pll_avl_phy_clk),
.pll_dq_clk (pll_write_clk),
.pll_dqs_clk (pll_mem_phy_clk),
.dll_phy_delayctrl (dll_phy_delayctrl),
.afi_clk (afi_clk),
.avl_clk (avl_clk),
.adc_clk (adc_clk),
.adc_clk_cps (adc_clk_cps)
);
assign ctl_clk = afi_clk;
assign afi_reset_n = reset_n_afi_clk;
// ********************************************************************************************************************************
// This is the hard PHY instance
// ********************************************************************************************************************************
cyclonev_mem_phy hphy_inst (
.pllaficlk (afi_clk),
.pllavlclk (avl_clk),
.plllocked (pll_locked),
.plladdrcmdclk (adc_clk),
.globalresetn (global_reset_n),
.softresetn (soft_reset_n),
.phyresetn (phy_reset_n),
.ctlresetn (ctl_reset_n),
.iointaddrdout (io_intaddrdout),
.iointbadout (io_intbadout),
.iointcasndout (io_intcasndout),
.iointckdout (io_intckdout),
.iointckedout (io_intckedout),
.iointckndout (io_intckndout),
.iointcsndout (io_intcsndout),
.iointdmdout (io_intdmdout),
.iointdqdin (io_intdqdin),
.iointdqdout (io_intdqdout),
.iointdqoe (io_intdqoe),
.iointdqsbdout (io_intdqsbdout),
.iointdqsboe (io_intdqsboe),
.iointdqsdout (io_intdqsdout),
.iointdqslogicdqsena (io_intdqslogicdqsena),
.iointdqslogicfiforeset (io_intdqslogicfiforeset),
.iointdqslogicincrdataen (io_intdqslogicincrdataen),
.iointdqslogicincwrptr (io_intdqslogicincwrptr),
.iointdqslogicoct (io_intdqslogicoct),
.iointdqslogicrdatavalid (io_intdqslogicrdatavalid),
.iointdqslogicreadlatency (io_intdqslogicreadlatency),
.iointdqsoe (io_intdqsoe),
.iointodtdout (io_intodtdout),
.iointrasndout (io_intrasndout),
.iointresetndout (io_intresetndout),
.iointwendout (io_intwendout),
.iointafirlat (io_intafirlat),
.iointafiwlat (io_intafiwlat),
.iointaficalfail (io_intaficalfail),
.iointaficalsuccess (io_intaficalsuccess),
.ddiophydqdin (ddio_phy_dqdin),
.ddiophydqslogicrdatavalid (ddio_phy_dqslogic_rdatavalid),
.phyddioaddrdout (phy_ddio_address),
.phyddiobadout (phy_ddio_bank),
.phyddiocasndout (phy_ddio_cas_n),
.phyddiockdout (phy_ddio_ck),
.phyddiockedout (phy_ddio_cke),
.phyddiockndout (),
.phyddiocsndout (phy_ddio_cs_n),
.phyddiodmdout (phy_ddio_dmdout),
.phyddiodqdout (phy_ddio_dqdout),
.phyddiodqoe (phy_ddio_dqoe),
.phyddiodqsbdout (),
.phyddiodqsboe (phy_ddio_dqsb_oe),
.phyddiodqslogicdqsena (phy_ddio_dqslogic_dqsena),
.phyddiodqslogicfiforeset (phy_ddio_dqslogic_fiforeset),
.phyddiodqslogicaclrpstamble (phy_ddio_dqslogic_aclr_pstamble),
.phyddiodqslogicaclrfifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phyddiodqslogicincrdataen (phy_ddio_dqslogic_incrdataen),
.phyddiodqslogicincwrptr (phy_ddio_dqslogic_incwrptr),
.phyddiodqslogicoct (phy_ddio_dqslogic_oct),
.phyddiodqslogicreadlatency (phy_ddio_dqslogic_readlatency),
.phyddiodqsoe (phy_ddio_dqs_oe),
.phyddiodqsdout (phy_ddio_dqs_dout),
.phyddioodtdout (phy_ddio_odt),
.phyddiorasndout (phy_ddio_ras_n),
.phyddioresetndout (phy_ddio_reset_n),
.phyddiowendout (phy_ddio_we_n),
.afiaddr (afi_addr),
.afiba (afi_ba),
.aficalfail (afi_cal_fail),
.aficalsuccess (afi_cal_success),
.aficasn (afi_cas_n),
.aficke (afi_cke),
.aficsn (afi_cs_n),
.afidm (afi_dm),
.afidqsburst (afi_dqs_burst),
.afimemclkdisable (afi_mem_clk_disable),
.afiodt (afi_odt),
.afirasn (afi_ras_n),
.afirdata (afi_rdata),
.afirdataen (afi_rdata_en),
.afirdataenfull (afi_rdata_en_full),
.afirdatavalid (afi_rdata_valid),
.afirlat (afi_rlat),
.afirstn (afi_rst_n),
.afiwdata (afi_wdata),
.afiwdatavalid (afi_wdata_valid),
.afiwen (afi_we_n),
.afiwlat (afi_wlat),
.avladdress (avl_address),
.avlread (avl_read),
.avlreaddata (avl_readdata),
.avlresetn (reset_n_avl_clk),
.avlwaitrequest (avl_waitrequest),
.avlwrite (avl_write),
.avlwritedata (avl_writedata),
.cfgaddlat (cfg_addlat),
.cfgbankaddrwidth (cfg_bankaddrwidth),
.cfgcaswrlat (cfg_caswrlat),
.cfgcoladdrwidth (cfg_coladdrwidth),
.cfgcsaddrwidth (cfg_csaddrwidth),
.cfgdevicewidth (cfg_devicewidth),
.cfgdramconfig (cfg_dramconfig),
.cfginterfacewidth (cfg_interfacewidth),
.cfgrowaddrwidth (cfg_rowaddrwidth),
.cfgtcl (cfg_tcl),
.cfgtmrd (cfg_tmrd),
.cfgtrefi (cfg_trefi),
.cfgtrfc (cfg_trfc),
.cfgtwr (cfg_twr),
.scanen ()
);
defparam hphy_inst.hphy_ac_ddr_disable = "true";
defparam hphy_inst.hphy_datapath_delay = "one_cycle";
defparam hphy_inst.hphy_datapath_ac_delay = "one_and_half_cycles";
defparam hphy_inst.hphy_reset_delay_en = "false";
defparam hphy_inst.m_hphy_ac_rom_init_file = AC_ROM_INIT_FILE_NAME;
defparam hphy_inst.m_hphy_inst_rom_init_file = INST_ROM_INIT_FILE_NAME;
defparam hphy_inst.hphy_wrap_back_en = "false";
defparam hphy_inst.hphy_atpg_en = "false";
defparam hphy_inst.hphy_use_hphy = "true";
defparam hphy_inst.hphy_csr_pipelineglobalenable = "true";
defparam hphy_inst.hphy_hhp_hps = IS_HHP_HPS;
// ********************************************************************************************************************************
// The I/O block is responsible for instantiating all the built-in I/O logic in the FPGA
// ********************************************************************************************************************************
hps_sdram_p0_acv_hard_io_pads #(
.DEVICE_FAMILY(DEVICE_FAMILY),
.FAST_SIM_MODEL(FAST_SIM_MODEL),
.OCT_SERIES_TERM_CONTROL_WIDTH(OCT_SERIES_TERM_CONTROL_WIDTH),
.OCT_PARALLEL_TERM_CONTROL_WIDTH(OCT_PARALLEL_TERM_CONTROL_WIDTH),
.MEM_ADDRESS_WIDTH(MEM_ADDRESS_WIDTH),
.MEM_BANK_WIDTH(MEM_BANK_WIDTH),
.MEM_CHIP_SELECT_WIDTH(MEM_IF_CS_WIDTH),
.MEM_CLK_EN_WIDTH(MEM_CLK_EN_WIDTH),
.MEM_CK_WIDTH(MEM_CK_WIDTH),
.MEM_ODT_WIDTH(MEM_ODT_WIDTH),
.MEM_DQS_WIDTH(MEM_DQS_WIDTH),
.MEM_DM_WIDTH(MEM_DM_WIDTH),
.MEM_CONTROL_WIDTH(MEM_CONTROL_WIDTH),
.MEM_DQ_WIDTH(MEM_DQ_WIDTH),
.MEM_READ_DQS_WIDTH(MEM_READ_DQS_WIDTH),
.MEM_WRITE_DQS_WIDTH(MEM_WRITE_DQS_WIDTH),
.DLL_DELAY_CTRL_WIDTH(DLL_DELAY_CTRL_WIDTH),
.ADC_PHASE_SETTING(ADC_PHASE_SETTING),
.ADC_INVERT_PHASE(ADC_INVERT_PHASE),
.IS_HHP_HPS(IS_HHP_HPS)
) uio_pads (
.reset_n_addr_cmd_clk (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk[1]),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (mem_a),
.phy_mem_bank (mem_ba),
.phy_mem_cs_n (mem_cs_n),
.phy_mem_cke (mem_cke),
.phy_mem_odt (mem_odt),
.phy_mem_we_n (mem_we_n),
.phy_mem_ras_n (mem_ras_n),
.phy_mem_cas_n (mem_cas_n),
.phy_mem_reset_n (mem_reset_n),
.pll_afi_clk (pll_afi_clk),
.pll_mem_clk (pll_mem_clk),
.pll_afi_phy_clk (pll_afi_phy_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_avl_clk (pll_avl_clk),
.avl_clk (avl_clk),
.pll_mem_phy_clk (pll_mem_phy_clk),
.pll_write_clk (pll_write_clk),
.pll_dqs_ena_clk (pll_dqs_ena_clk),
.pll_addr_cmd_clk (adc_clk_cps),
.phy_mem_dq (mem_dq),
.phy_mem_dm (mem_dm),
.phy_mem_ck (mem_ck),
.phy_mem_ck_n (mem_ck_n),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.dll_phy_delayctrl (dll_phy_delayctrl),
.scc_clk (pll_config_clk),
.scc_data (scc_data),
.scc_dqs_ena (scc_dqs_ena),
.scc_dqs_io_ena (scc_dqs_io_ena),
.scc_dq_ena (scc_dq_ena),
.scc_dm_ena (scc_dm_ena),
.scc_upd (scc_upd[0]),
.phy_ddio_dmdout (phy_ddio_dmdout),
.phy_ddio_dqdout (phy_ddio_dqdout),
.phy_ddio_dqs_oe (phy_ddio_dqs_oe),
.phy_ddio_dqsdout (phy_ddio_dqs_dout),
.phy_ddio_dqsb_oe (phy_ddio_dqsb_oe),
.phy_ddio_dqslogic_oct (phy_ddio_dqslogic_oct),
.phy_ddio_dqslogic_fiforeset (phy_ddio_dqslogic_fiforeset),
.phy_ddio_dqslogic_aclr_pstamble (phy_ddio_dqslogic_aclr_pstamble),
.phy_ddio_dqslogic_aclr_fifoctrl (phy_ddio_dqslogic_aclr_fifoctrl),
.phy_ddio_dqslogic_incwrptr (phy_ddio_dqslogic_incwrptr),
.phy_ddio_dqslogic_readlatency (phy_ddio_dqslogic_readlatency),
.ddio_phy_dqslogic_rdatavalid (ddio_phy_dqslogic_rdatavalid),
.ddio_phy_dqdin (ddio_phy_dqdin),
.phy_ddio_dqslogic_incrdataen (phy_ddio_dqslogic_incrdataen),
.phy_ddio_dqslogic_dqsena (phy_ddio_dqslogic_dqsena),
.phy_ddio_dqoe (phy_ddio_dqoe),
.capture_strobe_tracking (capture_strobe_tracking)
);
generate
if (IS_HHP_HPS != "true") begin
reg afi_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_clk)
afi_clk_reg <= ~afi_clk_reg;
reg afi_half_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_afi_half_clk)
afi_half_clk_reg <= ~afi_half_clk_reg;
reg avl_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_avl_clk)
avl_clk_reg <= ~avl_clk_reg;
reg config_clk_reg /* synthesis dont_merge syn_noprune syn_preserve = 1 */;
always @(posedge pll_config_clk)
config_clk_reg <= ~config_clk_reg;
end
endgenerate
// Calculate the ceiling of log_2 of the input value
function integer ceil_log2;
input integer value;
begin
value = value - 1;
for (ceil_log2 = 0; value > 0; ceil_log2 = ceil_log2 + 1)
value = value >> 1;
end
endfunction
endmodule
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 1
*/
/**
* Testbench for behavioral model for Finite State Machine model of the
* vending machine
*/
// Import the modules that will be tested for in this testbench
`include "ee577bHw2q1.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q1.f +gui
module tbfsm();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the couunter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire disp_Q,disp_D,disp_N,disp_P,done;
// Declare "reg" signals: inputs to the DUT
reg [6:0] money,price;
reg start,clk,reset;
/**
* Instantiate an instance of ee577bHw1q5model1() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
fsmVendingMachine fsm (
// instance_name(signal name),
// Signal name can be the same as the instance name
disp_Q,disp_D,disp_N,disp_P,done,money,price,start,clk,reset);
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen
#5 clk <= 0;
#5 clk <= 1;
end
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses/waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0,
money = 7'd75;
price = 7'd64;
reset = 1'b0;
start = 1'b1;
// @ t=50;
#50
money = 7'd100;
price = 7'd54;
reset = 1'b0;
start = 1'b1;
// @ t=100;
#50
money = 7'd50;
price = 7'd27;
reset = 1'b0;
start = 1'b1;
// @ t=150;
#50
money = 7'd50;
price = 7'd27;
reset = 1'b0;
start = 1'b1;
//
$display($time, " << Finishing the simulation >>");
end
endmodule
|