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// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
module dpram(wclk,wdata,waddr,wen,rclk,rdata,raddr);
parameter depth = 4;
parameter width = 16;
parameter size = 16;
input wclk;
input [width-1:0] wdata;
input [depth-1:0] waddr;
input wen;
input rclk;
output reg [width-1:0] rdata;
input [depth-1:0] raddr;
reg [width-1:0] ram [0:size-1];
always @(posedge wclk)
if(wen)
ram[waddr] <= #1 wdata;
always @(posedge rclk)
rdata <= #1 ram[raddr];
endmodule // dpram
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
///////////////////////////////////////////////////////////////////////////////
// $Id: small_fifo.v 4761 2008-12-27 01:11:00Z jnaous $
//
// Module: small_fifo.v
// Project: UNET
// Description: small fifo with no fallthrough i.e. data valid after rd is high
//
// Change history:
// 7/20/07 -- Set nearly full to 2^MAX_DEPTH_BITS - 1 by default so that it
// goes high a clock cycle early.
// 11/2/09 -- Modified to have both prog threshold and almost full
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
module small_fifo
#(parameter WIDTH = 72,
parameter MAX_DEPTH_BITS = 3,
parameter PROG_FULL_THRESHOLD = 2**MAX_DEPTH_BITS - 1
)
(
input [WIDTH-1:0] din, // Data in
input wr_en, // Write enable
input rd_en, // Read the next word
output reg [WIDTH-1:0] dout, // Data out
output full,
output nearly_full,
output prog_full,
output empty,
input reset,
input clk
);
localparam MAX_DEPTH = 2 ** MAX_DEPTH_BITS;
reg [WIDTH-1:0] queue [MAX_DEPTH - 1 : 0];
reg [MAX_DEPTH_BITS - 1 : 0] rd_ptr;
reg [MAX_DEPTH_BITS - 1 : 0] wr_ptr;
reg [MAX_DEPTH_BITS : 0] depth;
// Sample the data
always @(posedge clk)
if (wr_en)
queue[wr_ptr] <= din;
always@(posedge clk)
if(reset)
dout<=0;
else if (rd_en)
dout <=queue[rd_ptr];
always @(posedge clk)
begin
if (reset) begin
rd_ptr <= 'h0;
wr_ptr <= 'h0;
depth <= 'h0;
end
else begin
if (wr_en) wr_ptr <= wr_ptr + 'h1;
if (rd_en) rd_ptr <= rd_ptr + 'h1;
if (wr_en & ~rd_en) depth <= depth + 'h1;
else if (~wr_en & rd_en) depth <=depth - 'h1;
end
end
//assign dout = queue[rd_ptr];
assign full = depth == MAX_DEPTH;
assign prog_full = (depth >= PROG_FULL_THRESHOLD);
assign nearly_full = depth >= MAX_DEPTH-1;
assign empty = depth == 'h0;
// synthesis translate_off
always @(posedge clk)
begin
if (wr_en && depth == MAX_DEPTH && !rd_en)
$display($time, " ERROR: Attempt to write to full FIFO: %m");
if (rd_en && depth == 'h0)
$display($time, " ERROR: Attempt to read an empty FIFO: %m");
end
// synthesis translate_on
endmodule // small_fifo
/* vim:set shiftwidth=3 softtabstop=3 expandtab: */
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $File: //acds/rel/13.1/ip/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_base.v $
// $Revision: #1 $
// $Date: 2013/08/11 $
// $Author: swbranch $
//------------------------------------------------------------------------------
`timescale 1ns / 1ns
module altera_avalon_st_pipeline_base (
clk,
reset,
in_ready,
in_valid,
in_data,
out_ready,
out_valid,
out_data
);
parameter SYMBOLS_PER_BEAT = 1;
parameter BITS_PER_SYMBOL = 8;
parameter PIPELINE_READY = 1;
localparam DATA_WIDTH = SYMBOLS_PER_BEAT * BITS_PER_SYMBOL;
input clk;
input reset;
output in_ready;
input in_valid;
input [DATA_WIDTH-1:0] in_data;
input out_ready;
output out_valid;
output [DATA_WIDTH-1:0] out_data;
reg full0;
reg full1;
reg [DATA_WIDTH-1:0] data0;
reg [DATA_WIDTH-1:0] data1;
assign out_valid = full1;
assign out_data = data1;
generate if (PIPELINE_READY == 1)
begin : REGISTERED_READY_PLINE
assign in_ready = !full0;
always @(posedge clk, posedge reset) begin
if (reset) begin
data0 <= {DATA_WIDTH{1'b0}};
data1 <= {DATA_WIDTH{1'b0}};
end else begin
// ----------------------------
// always load the second slot if we can
// ----------------------------
if (~full0)
data0 <= in_data;
// ----------------------------
// first slot is loaded either from the second,
// or with new data
// ----------------------------
if (~full1 || (out_ready && out_valid)) begin
if (full0)
data1 <= data0;
else
data1 <= in_data;
end
end
end
always @(posedge clk or posedge reset) begin
if (reset) begin
full0 <= 1'b0;
full1 <= 1'b0;
end else begin
// no data in pipeline
if (~full0 & ~full1) begin
if (in_valid) begin
full1 <= 1'b1;
end
end // ~f1 & ~f0
// one datum in pipeline
if (full1 & ~full0) begin
if (in_valid & ~out_ready) begin
full0 <= 1'b1;
end
// back to empty
if (~in_valid & out_ready) begin
full1 <= 1'b0;
end
end // f1 & ~f0
// two data in pipeline
if (full1 & full0) begin
// go back to one datum state
if (out_ready) begin
full0 <= 1'b0;
end
end // end go back to one datum stage
end
end
end
else
begin : UNREGISTERED_READY_PLINE
// in_ready will be a pass through of the out_ready signal as it is not registered
assign in_ready = (~full1) | out_ready;
always @(posedge clk or posedge reset) begin
if (reset) begin
data1 <= 'b0;
full1 <= 1'b0;
end
else begin
if (in_ready) begin
data1 <= in_data;
full1 <= in_valid;
end
end
end
end
endgenerate
endmodule
|
/*
* Copyright (c) 2003 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* Test some multiply values for an 18*18-->36 multiply.
*/
module main;
wire [35:0] p;
reg [17:0] a, b;
reg clk, ce, reset;
parameter MAX_TRIALS = 1000;
integer idx;
MULT18X18S dut (p, a, b, clk, ce, reset);
initial begin
clk <= 0;
ce <= 1;
reset <= 1;
a <= 0;
b <= 0;
#5 clk <= 1;
#5 clk <= 0;
if (p !== 36'h0) begin
$display("FAILED -- reset p=%h", p);
$finish;
end
reset <= 0;
/* A magical value I know failed at one time. */
a <= 18'h3ff82;
b <= 18'h04000;
#5 clk <= 1;
#5 clk <= 0;
if (p !== 36'hfffe08000) begin
$display("FAILED -- %h * %h --> %h", a, b, p);
$finish;
end
for (idx = 0 ; idx < MAX_TRIALS ; idx = idx + 1) begin
a <= $random;
b <= $random;
#5 clk <= 1;
#5 clk <= 0;
if ($signed(p) !== ($signed(a) * $signed(b))) begin
$display("FAILED == %h * %h --> %h", a, b, p);
$finish;
end
end // for (idx = 0 ; idx < `MAX_TRIALS ; idx = idx + 1)
$display("PASSED");
end // initial begin
endmodule // main
module MULT18X18S (output reg [35:0] P,
input [17:0] A,
input [17:0] B,
input C, CE, R);
wire [35:0] a_in = { {18{A[17]}}, A[17:0] };
wire [35:0] b_in = { {18{B[17]}}, B[17:0] };
wire [35:0] p_in;
reg [35:0] p_out;
assign p_in = a_in * b_in;
always @(posedge C)
if (R)
P <= 36'b0;
else if (CE)
P <= p_in;
endmodule
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: ICACHE_SM.v
// Version: 1.0
// Date: 30 May 2015
//
// Copyright (C) 2015 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. KOLDETECT Collision Detection Unit
// 2. ICACHE_SM Instruction Cache State Machine
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 1. KOLDETECT Collision Detection Unit
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module KOLDETECT ( BCLK, BRESET, DRAM_WR, CVALID, ADDR, TAG0, TAG1 , CFG , C_VALID, READ_I, ACC_OK, HOLD, KDET, INVAL_A, ENA_HK,
NEWCVAL, KOLLISION, STOP_ICRD, RUN_ICRD, KILL, KILLADR, ICTODC, STOP_CINV );
input BCLK;
input BRESET;
input DRAM_WR;
input [23:0] CVALID; // Data from master Valid RAM
input [27:4] ADDR;
input [27:12] TAG0,TAG1;
input [1:0] CFG;
input [23:0] C_VALID; // Data from secondary Valid RAM
input READ_I;
input ACC_OK;
input HOLD; // active low
input KDET;
input INVAL_A; // Cache Invalidate All
input ENA_HK; // Enable HOLD and Kohaerenz
output [23:0] NEWCVAL;
output KOLLISION;
output STOP_ICRD;
output RUN_ICRD;
output KILL;
output [11:7] KILLADR;
output [2:0] ICTODC;
output STOP_CINV;
reg [27:4] addr_r;
reg [7:0] maske,clear;
reg do_koll;
reg [2:0] counter;
reg [1:0] wpointer,rpointer;
reg [35:0] adrfifo;
reg [8:0] fifo_q,fifo_c;
reg [1:0] state;
reg pipe;
reg do_kill;
reg dma;
wire [7:0] set_0,set_1;
wire match_0,match_1;
wire valid_0,valid_1;
wire found_0,found_1;
wire kolli,dma_kolli;
wire last_match;
wire wr_entry;
wire [23:0] cdaten;
wire [8:0] kaddr;
wire [7:0] new_0,new_1;
wire dma_mode,ic_dma;
wire free,ende;
wire init_b;
always @(posedge BCLK) do_koll <= DRAM_WR & CFG[0]; // one cycle pulse, without Cache Enable no collision
always @(posedge BCLK) addr_r <= ADDR;
// similar logic like in CA_MATCH
assign set_0 = C_VALID[7:0];
assign set_1 = C_VALID[15:8];
assign valid_0 = set_0[addr_r[6:4]];
assign valid_1 = set_1[addr_r[6:4]];
assign match_0 = ( TAG0 == addr_r[27:12] ); // 4KB
assign match_1 = ( TAG1 == addr_r[27:12] ); // 4KB
assign found_0 = valid_0 & match_0;
assign found_1 = valid_1 & match_1;
assign kolli = (found_0 | found_1) & ~CFG[1] & do_koll; // Action only if ICACHE is not locked
assign KOLLISION = (found_0 | found_1) & do_koll; // to Statistik Modul, Register there
assign dma_kolli = (found_0 | found_1) & ~CFG[1] & CFG[0];
// the FIFO with 4 entries :
assign init_b = CFG[0] & ~INVAL_A; // initialise if CINV A too
always @(posedge BCLK)
if (!init_b) wpointer <= 2'b00;
else
wpointer <= wpointer + {1'b0,wr_entry};
always @(posedge BCLK)
if (!init_b) rpointer <= 2'b00;
else
rpointer <= rpointer + {1'b0,do_kill};
always @(posedge BCLK)
begin
if (wr_entry && (wpointer == 2'b00)) adrfifo[8:0] <= {addr_r[11:4],found_1};
if (wr_entry && (wpointer == 2'b01)) adrfifo[17:9] <= {addr_r[11:4],found_1};
if (wr_entry && (wpointer == 2'b10)) adrfifo[26:18] <= {addr_r[11:4],found_1};
if (wr_entry && (wpointer == 2'b11)) adrfifo[35:27] <= {addr_r[11:4],found_1};
end
always @(adrfifo or rpointer)
case (rpointer)
2'b00 : fifo_q = adrfifo[8:0];
2'b01 : fifo_q = adrfifo[17:9];
2'b10 : fifo_q = adrfifo[26:18];
2'b11 : fifo_q = adrfifo[35:27];
endcase
always @(adrfifo or wpointer) // for Match of last entry use wpointer
case (wpointer)
2'b01 : fifo_c = adrfifo[8:0];
2'b10 : fifo_c = adrfifo[17:9];
2'b11 : fifo_c = adrfifo[26:18];
2'b00 : fifo_c = adrfifo[35:27];
endcase
// Control
assign last_match = counter[2] & (fifo_c == {addr_r[11:4],found_1}); // if Match with last Entry no new Entry
assign wr_entry = kolli & ~last_match;
always @(posedge BCLK)
casex ({init_b,wr_entry,do_kill,counter})
6'b0_xx_xxx : counter <= 3'b000;
6'b1_00_xxx : counter <= counter;
6'b1_11_xxx : counter <= counter;
6'b1_10_000 : counter <= 3'b100;
6'b1_10_1xx : counter <= (counter[1:0] == 2'b11) ? 3'b111 : {counter[2],(counter[1:0] + 2'b01)}; // Overflow avoid
6'b1_01_1xx : counter <= (counter[1:0] == 2'b00) ? 3'b000 : {counter[2],(counter[1:0] + 2'b11)};
default : counter <= counter;
endcase
// DMA Access
always @(posedge BCLK) dma <= ~HOLD; // there is only one FF for this , from here to DCACHE
// Controlling of ICACHE
assign free = (~READ_I | ACC_OK) & ENA_HK; // switch off if CINV
always @(posedge BCLK) // state[1] state[0]
casex ({BRESET,dma,counter[2],free,ende,STOP_ICRD,dma_mode})
7'b0_xx_xx_xx : state <= 2'b00;
7'b1_00_xx_00 : state <= 2'b00;
7'b1_01_1x_00 : state <= 2'b10; // Start of DCACHE Kohaerenz
7'b1_1x_1x_00 : state <= 2'b11; // Start of DMA
//
7'b1_xx_x0_10 : state <= 2'b10; // without "ende" it stays as is
7'b1_0x_x1_10 : state <= 2'b00; // DMA is not active
7'b1_1x_x1_10 : state <= 2'b11; // to DMA !
//
7'b1_00_xx_11 : state <= 2'b00;
7'b1_01_xx_11 : state <= 2'b10;
7'b1_1x_xx_11 : state <= 2'b11;
default : state <= 2'b00;
endcase
assign STOP_ICRD = state[1]; // used for Multiplexer
assign dma_mode = state[0]; // internal Multiplexer
assign STOP_CINV = state[1] & ~ENA_HK; // stops CINV if DMA access or Kohaerenz access
assign ende = (counter[1:0] == 2'b00) & do_kill;
assign ic_dma = STOP_ICRD & dma_mode; // Signal to DCACHE that ICACHE has stoped
always @(posedge BCLK) pipe <= STOP_ICRD;
assign RUN_ICRD = ~(STOP_ICRD | pipe); // Release for IC_READ
always @(posedge BCLK) do_kill <= STOP_ICRD & ~dma_mode & ~do_kill; // Write pulse in Cache Valid RAM, 1 cycle on, 1 cycle off
assign KILL = do_kill | (KDET & dma_kolli);
// Valid Daten prepare : different sources for DMA and DCACHE Kohaerenz
assign cdaten = dma_mode ? C_VALID : CVALID;
assign kaddr = dma_mode ? {addr_r[11:4],found_1} : fifo_q;
assign KILLADR = kaddr[8:4];
always @(kaddr)
case (kaddr[3:1])
3'h0 : clear = 8'hFE;
3'h1 : clear = 8'hFD;
3'h2 : clear = 8'hFB;
3'h3 : clear = 8'hF7;
3'h4 : clear = 8'hEF;
3'h5 : clear = 8'hDF;
3'h6 : clear = 8'hBF;
3'h7 : clear = 8'h7F;
endcase
assign new_0 = kaddr[0] ? cdaten[7:0] : (cdaten[7:0] & clear);
assign new_1 = kaddr[0] ? (cdaten[15:8] & clear) : cdaten[15:8];
assign NEWCVAL = {cdaten[23:16],new_1,new_0};
// multiple signals are needed in DCACHE :
assign ICTODC = {dma,ic_dma,~(counter[2:1] == 2'b11)};
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 2. ICACHE_SM Instruction Cache State Machine
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module ICACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, PTE_ACC,
USE_CA, PTB_WR, PTB_SEL, USER, PROT_ERROR,
DRAM_ACC, IO_RD, IO_ACC, IC_PREQ, ACC_OK, HIT_ALL, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE );
input BCLK;
input BRESET;
input IO_SPACE;
input MDONE; // Memory Done : Feedback from DRAM Controller, BCLK aligned
input IO_READY;
input MMU_HIT,CA_HIT;
input READ;
input PTE_ACC;
input USE_CA;
input PTB_WR,PTB_SEL;
input USER;
input PROT_ERROR;
output reg DRAM_ACC,IO_RD;
output IO_ACC;
output IC_PREQ;
output ACC_OK;
output HIT_ALL;
output CUPDATE;
output AUX_DAT;
output reg NEW_PTB,PTB_ONE;
reg [3:0] new_state;
reg rd_done;
reg card_flag;
reg rd_rdy;
wire io_busy;
wire dram_go;
wire rd_ende;
wire do_ca_rd;
// Cycle : /-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_
// Access : _/-----------------------------------\__
// State Machine : ____/----------------------------\______
// Busy status ...
assign rd_ende = CA_HIT | rd_rdy; // CA_HIT only if Cache activ !
always @( READ // only READ , global control
or PROT_ERROR // is not allowed !
//
or IO_SPACE // indicates access in the IO_WELT
or io_busy // is already active ?
//
or MMU_HIT // Hit in the MMU , now only a READ can be active
or rd_ende // Cache Hit
or DRAM_ACC // DRAM Access running
//
or PTE_ACC ) // PTE Access running
// #_# #_# #_#
casex ({READ,PROT_ERROR,IO_SPACE,io_busy,MMU_HIT,rd_ende,DRAM_ACC,PTE_ACC})
// MMU Miss : PTE load from memory
8'b10_xx_0xx_0 : new_state = 4'b0100; // start PTE access
// IO-Address selected : external access starts if not already BUSY
8'b10_10_1xx_x : new_state = 4'b0001;
// DRAM Access : Cache Miss at READ
8'b10_0x_100_x : new_state = 4'b1010; // can start directly
default : new_state = 4'b0;
endcase
assign IO_ACC = new_state[0]; // to load the Register for Data and Addr
assign dram_go = new_state[1];
assign IC_PREQ = new_state[2]; // MMU to DCACHE !
assign do_ca_rd = new_state[3];
assign HIT_ALL = MMU_HIT & CA_HIT; // for Update "Last-Set" , MMU_HIT contains ZUGRIFF
always @(posedge BCLK or negedge BRESET)
if (!BRESET) card_flag <= 1'b0;
else card_flag <= (do_ca_rd & ~rd_rdy) | (card_flag & ~MDONE);
assign CUPDATE = card_flag & USE_CA & MDONE; // USE_CA = ~CI & ~LDC;
always @(posedge BCLK) rd_rdy <= card_flag & MDONE;
// The cache RAM can not provide fast enough the data after an Update. In this case a secondary data path is activated
assign AUX_DAT = rd_rdy;
// DRAM Interface :
always @(posedge BCLK) if (dram_go) DRAM_ACC <= 1'b1;
else
DRAM_ACC <= DRAM_ACC & ~MDONE & BRESET;
// IO Interface :
always @(posedge BCLK)
begin
if (IO_ACC) IO_RD <= READ; else IO_RD <= IO_RD & ~IO_READY & BRESET;
end
assign io_busy = IO_RD | rd_done; // access is gone in next clock cycle, therefore blocked with "rd_done"
always @(posedge BCLK) rd_done <= READ & IO_READY; // For READ one clock later for data to come through
// global feedback to opcode fetch unit : you can continue
assign ACC_OK = IO_SPACE ? rd_done : (READ & MMU_HIT & rd_ende);
// PTB1 und PTB0
always @(posedge BCLK) NEW_PTB <= PTB_WR; // to MMU Update Block
always @(posedge BCLK) if (PTB_WR) PTB_ONE <= PTB_SEL;
endmodule
|
/*--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- File Name : diffeq.v
-- Author(s) : P. Sridhar
-- Affiliation : Laboratory for Digital Design Environments
-- Department of Electrical & Computer Engineering
-- University of Cincinnati
-- Date Created : June 1991.
-- Introduction : Behavioral description of a differential equation
-- solver written in a synthesizable subset of VHDL.
-- Source : Written in HardwareC by Rajesh Gupta, Stanford Univ.
-- Obtained from the Highlevel Synthesis Workshop
-- Repository.
--
-- Modified For Synthesis by Jay(anta) Roy, University of Cincinnati.
-- Date Modified : Sept, 91.
--
-- Disclaimer : This comes with absolutely no guarantees of any
-- kind (just stating the obvious ...)
--
-- Acknowledgement : The Distributed Synthesis Systems research at
-- the Laboratory for Digital Design Environments,
-- University of Cincinnati, is sponsored in part
-- by the Defense Advanced Research Projects Agency
-- under order number 7056 monitored by the Federal
-- Bureau of Investigation under contract number
-- J-FBI-89-094.
--
--------------------------------------------------------------------------
-------------------------------------------------------------------------*/
module diffeq_f_systemC(aport, dxport, xport, yport, uport, clk, reset);
input clk;
input reset;
input [31:0]aport;
input [31:0]dxport;
output [31:0]xport;
output [31:0]yport;
output [31:0]uport;
reg [31:0]xport;
reg [31:0]yport;
reg [31:0]uport;
wire [31:0]temp;
assign temp = uport * dxport;
always @(posedge clk )
begin
if (reset == 1'b1)
begin
xport <= 0;
yport <= 0;
uport <= 0;
end
else
if (xport < aport)
begin
xport <= xport + dxport;
yport <= yport + temp;//(uport * dxport);
uport <= (uport - (temp/*(uport * dxport)*/ * (5 * xport))) - (dxport * (3 * yport));
end
end
endmodule
|
/*
*
* Copyright (c) 2011-2012 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (
input CLK_100MHZ
);
//// Configuration Options
//
// Frequency (MHz) of the incoming clock (CLK_100MHZ)
localparam INPUT_CLOCK_FREQUENCY = 100;
// What frequency of operation Synthesis and P&R should target. If
// ISE can meet timing requirements, then this is the guaranteed
// frequency of operation.
localparam SYNTHESIS_FREQUENCY = 200;
// What frequency the FPGA should boot-up to.
localparam BOOTUP_FREQUENCY = 50;
// What is the maximum allowed overclock. User will not be able to set
// clock frequency above this threshold.
localparam MAXIMUM_FREQUENCY = 200;
// ONLY FOR DEV TESTING:
//`define DUMMY_ADDER
//`define DUMMY_HASHER
//// Clock Buffer
wire clkin_100MHZ;
IBUFG clkin1_buf ( .I (CLK_100MHZ), .O (clkin_100MHZ));
////
reg [255:0] midstate = 0;
reg [95:0] data = 0;
reg [31:0] nonce = 32'd253, nonce2 = 32'd0;
//// PLL
wire hash_clk;
wire dcm_progdata, dcm_progen, dcm_progdone;
`ifndef SIM
dynamic_clock # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.SYNTHESIS_FREQUENCY (SYNTHESIS_FREQUENCY)
) dynamic_clk_blk (
.CLK_IN1 (clkin_100MHZ),
.CLK_OUT1 (hash_clk),
.PROGCLK (clkin_100MHZ),
.PROGDATA (dcm_progdata),
.PROGEN (dcm_progen),
.PROGDONE (dcm_progdone)
);
`else
assign hash_clk = CLK_100MHZ;
`endif
//// ZTEX Hashers
`ifdef DUMMY_HASHER
wire [31:0] hash2_w;
dummy_pipe130 p1 (
.clk (hash_clk),
.state (midstate),
.state2 (midstate),
.data ({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash (hash2_w)
);
`else
`ifdef DUMMY_ADDR
reg [31:0] hash2_w;
reg [31:0] stage1, stage2, stage3, stage4, stage5;
always @ (posedge hash_clk)
begin
stage1 <= nonce + data[95:64] + data[63:32];
stage2 <= stage1 + data[31:0] + midstate[255:224];
stage3 <= stage2 + midstate[223:192] + midstate[191:160];
stage4 <= stage3 + midstate[159:128] + midstate[127:96];
stage5 <= stage4 + midstate[95:64] + midstate[63:32];
hash2_w <= stage5 + midstate[31:0];
end
`else
wire [255:0] hash;
wire [31:0] hash2_w;
sha256_pipe130 p1 (
.clk (hash_clk),
.state (midstate),
.state2 (midstate),
.data ({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash (hash)
);
sha256_pipe123 p2 (
.clk (hash_clk),
.data ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.hash (hash2_w)
);
`endif
`endif
//// Communication Module
wire comm_new_work;
wire [255:0] comm_midstate;
wire [95:0] comm_data;
reg is_golden_ticket = 1'b0;
reg [31:0] golden_nonce;
reg [3:0] golden_ticket_buf = 4'b0;
reg [127:0] golden_nonce_buf;
`ifndef SIM
jtag_comm # (
.INPUT_FREQUENCY (INPUT_CLOCK_FREQUENCY),
.MAXIMUM_FREQUENCY (MAXIMUM_FREQUENCY),
.INITIAL_FREQUENCY (BOOTUP_FREQUENCY)
) comm_blk (
.rx_hash_clk (hash_clk),
.rx_new_nonce (golden_ticket_buf[3]),
.rx_golden_nonce (golden_nonce_buf[127:96]),
.tx_new_work (comm_new_work),
.tx_midstate (comm_midstate),
.tx_data (comm_data),
.rx_dcm_progclk (clkin_100MHZ),
.tx_dcm_progdata (dcm_progdata),
.tx_dcm_progen (dcm_progen),
.rx_dcm_progdone (dcm_progdone)
);
`endif
//// Control Unit
// NOTE: When the hashers first start churning on new work, results
// will be invalid for ~253 cycles. Since returning invalid results is
// not very detrimental (controlling software double checks results)
// we sacrifice a small amount of accuracy in exchange for simple
// logic.
reg reset = 1'b1;
always @ (posedge hash_clk)
begin
// Counters
if (reset | comm_new_work)
begin
nonce <= 32'd253;
nonce2 <= 32'd0;
end
else
begin
nonce <= nonce + 32'd1;
nonce2 <= nonce2 + 32'd1;
end
// Give new data to the hasher
midstate <= comm_midstate;
data <= comm_data[95:0];
// Clear the reset signal when we get new work
if (comm_new_work)
reset <= 1'b0;
// Stop hashing if we've run out of nonces to check
else if (nonce2 == 32'hFFFFFFFF)
reset <= 1'b1;
// Check to see if the last hash generated is valid.
is_golden_ticket <= hash2_w == 32'hA41F32E7;
golden_nonce <= nonce2;
golden_ticket_buf <= {golden_ticket_buf[2:0], is_golden_ticket};
golden_nonce_buf <= {golden_nonce_buf[95:0], golden_nonce};
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s.v
//
// Description:
// To handle AXI4 transactions to external memory on Virtex-6 architectures
// requires a bridge to convert the AXI4 transactions to the memory
// controller(MC) user interface. The MC user interface has bidirectional
// data path and supports data width of 256/128/64/32 bits.
// The bridge is designed to allow AXI4 IP masters to communicate with
// the MC user interface.
//
//
// Specifications:
// AXI4 Slave Side:
// Configurable data width of 32, 64, 128, 256
// Read acceptance depth is:
// Write acceptance depth is:
//
// Structure:
// axi_protocol_converter_v2_1_b2s
// WRITE_BUNDLE
// aw_channel_0
// cmd_translator_0
// rd_cmd_fsm_0
// w_channel_0
// b_channel_0
// READ_BUNDLE
// ar_channel_0
// cmd_translator_0
// rd_cmd_fsm_0
// r_channel_0
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s #(
parameter C_S_AXI_PROTOCOL = 0,
// Width of all master and slave ID signals.
// Range: >= 1.
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 30,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire aclk ,
input wire aresetn ,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [2:0] s_axi_awsize ,
input wire [1:0] s_axi_awburst ,
input wire [2:0] s_axi_awprot ,
input wire s_axi_awvalid ,
output wire s_axi_awready ,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata ,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb ,
input wire s_axi_wlast ,
input wire s_axi_wvalid ,
output wire s_axi_wready ,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid ,
output wire [1:0] s_axi_bresp ,
output wire s_axi_bvalid ,
input wire s_axi_bready ,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr ,
input wire [((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [2:0] s_axi_arsize ,
input wire [1:0] s_axi_arburst ,
input wire [2:0] s_axi_arprot ,
input wire s_axi_arvalid ,
output wire s_axi_arready ,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid ,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata ,
output wire [1:0] s_axi_rresp ,
output wire s_axi_rlast ,
output wire s_axi_rvalid ,
input wire s_axi_rready ,
// Slave Interface Write Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr ,
output wire [2:0] m_axi_awprot ,
output wire m_axi_awvalid ,
input wire m_axi_awready ,
// Slave Interface Write Data Ports
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata ,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb ,
output wire m_axi_wvalid ,
input wire m_axi_wready ,
// Slave Interface Write Response Ports
input wire [1:0] m_axi_bresp ,
input wire m_axi_bvalid ,
output wire m_axi_bready ,
// Slave Interface Read Address Ports
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr ,
output wire [2:0] m_axi_arprot ,
output wire m_axi_arvalid ,
input wire m_axi_arready ,
// Slave Interface Read Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata ,
input wire [1:0] m_axi_rresp ,
input wire m_axi_rvalid ,
output wire m_axi_rready
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
reg areset_d1;
always @(posedge aclk)
areset_d1 <= ~aresetn;
// AW/W/B channel internal communication
wire b_push;
wire [C_AXI_ID_WIDTH-1:0] b_awid;
wire [7:0] b_awlen;
wire b_full;
wire [C_AXI_ID_WIDTH-1:0] si_rs_awid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_awaddr;
wire [8-1:0] si_rs_awlen;
wire [3-1:0] si_rs_awsize;
wire [2-1:0] si_rs_awburst;
wire [3-1:0] si_rs_awprot;
wire si_rs_awvalid;
wire si_rs_awready;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] si_rs_wstrb;
wire si_rs_wlast;
wire si_rs_wvalid;
wire si_rs_wready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_bid;
wire [2-1:0] si_rs_bresp;
wire si_rs_bvalid;
wire si_rs_bready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_arid;
wire [C_AXI_ADDR_WIDTH-1:0] si_rs_araddr;
wire [8-1:0] si_rs_arlen;
wire [3-1:0] si_rs_arsize;
wire [2-1:0] si_rs_arburst;
wire [3-1:0] si_rs_arprot;
wire si_rs_arvalid;
wire si_rs_arready;
wire [C_AXI_ID_WIDTH-1:0] si_rs_rid;
wire [C_AXI_DATA_WIDTH-1:0] si_rs_rdata;
wire [2-1:0] si_rs_rresp;
wire si_rs_rlast;
wire si_rs_rvalid;
wire si_rs_rready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_awaddr;
wire rs_mi_awvalid;
wire rs_mi_awready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_wdata;
wire [C_AXI_DATA_WIDTH/8-1:0] rs_mi_wstrb;
wire rs_mi_wvalid;
wire rs_mi_wready;
wire [2-1:0] rs_mi_bresp;
wire rs_mi_bvalid;
wire rs_mi_bready;
wire [C_AXI_ADDR_WIDTH-1:0] rs_mi_araddr;
wire rs_mi_arvalid;
wire rs_mi_arready;
wire [C_AXI_DATA_WIDTH-1:0] rs_mi_rdata;
wire [2-1:0] rs_mi_rresp;
wire rs_mi_rvalid;
wire rs_mi_rready;
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( C_S_AXI_PROTOCOL ) ,
.C_AXI_ID_WIDTH ( C_AXI_ID_WIDTH ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 1 ) ,
.C_REG_CONFIG_AR ( 1 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 1 ) ,
.C_REG_CONFIG_B ( 1 )
) SI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( s_axi_awid ) ,
.s_axi_awaddr ( s_axi_awaddr ) ,
.s_axi_awlen ( s_axi_awlen ) ,
.s_axi_awsize ( s_axi_awsize ) ,
.s_axi_awburst ( s_axi_awburst ) ,
.s_axi_awlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( s_axi_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( s_axi_awvalid ) ,
.s_axi_awready ( s_axi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( {C_AXI_ID_WIDTH{1'b0}} ) ,
.s_axi_wdata ( s_axi_wdata ) ,
.s_axi_wstrb ( s_axi_wstrb ) ,
.s_axi_wlast ( s_axi_wlast ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( s_axi_wvalid ) ,
.s_axi_wready ( s_axi_wready ) ,
.s_axi_bid ( s_axi_bid ) ,
.s_axi_bresp ( s_axi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( s_axi_bvalid ) ,
.s_axi_bready ( s_axi_bready ) ,
.s_axi_arid ( s_axi_arid ) ,
.s_axi_araddr ( s_axi_araddr ) ,
.s_axi_arlen ( s_axi_arlen ) ,
.s_axi_arsize ( s_axi_arsize ) ,
.s_axi_arburst ( s_axi_arburst ) ,
.s_axi_arlock ( {((C_S_AXI_PROTOCOL == 1) ? 2 : 1){1'b0}} ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( s_axi_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( s_axi_arvalid ) ,
.s_axi_arready ( s_axi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( s_axi_rid ) ,
.s_axi_rdata ( s_axi_rdata ) ,
.s_axi_rresp ( s_axi_rresp ) ,
.s_axi_rlast ( s_axi_rlast ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( s_axi_rvalid ) ,
.s_axi_rready ( s_axi_rready ) ,
.m_axi_awid ( si_rs_awid ) ,
.m_axi_awaddr ( si_rs_awaddr ) ,
.m_axi_awlen ( si_rs_awlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_awsize ( si_rs_awsize ) ,
.m_axi_awburst ( si_rs_awburst ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( si_rs_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( si_rs_awvalid ) ,
.m_axi_awready ( si_rs_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( si_rs_wdata ) ,
.m_axi_wstrb ( si_rs_wstrb ) ,
.m_axi_wlast ( si_rs_wlast ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( si_rs_wvalid ) ,
.m_axi_wready ( si_rs_wready ) ,
.m_axi_bid ( si_rs_bid ) ,
.m_axi_bresp ( si_rs_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( si_rs_bvalid ) ,
.m_axi_bready ( si_rs_bready ) ,
.m_axi_arid ( si_rs_arid ) ,
.m_axi_araddr ( si_rs_araddr ) ,
.m_axi_arlen ( si_rs_arlen[((C_S_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] ) ,
.m_axi_arsize ( si_rs_arsize ) ,
.m_axi_arburst ( si_rs_arburst ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( si_rs_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( si_rs_arvalid ) ,
.m_axi_arready ( si_rs_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( si_rs_rid ) ,
.m_axi_rdata ( si_rs_rdata ) ,
.m_axi_rresp ( si_rs_rresp ) ,
.m_axi_rlast ( si_rs_rlast ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( si_rs_rvalid ) ,
.m_axi_rready ( si_rs_rready )
);
generate
if (C_AXI_SUPPORTS_WRITE == 1) begin : WR
axi_protocol_converter_v2_1_b2s_aw_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
aw_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_awid ( si_rs_awid ) ,
.s_awaddr ( si_rs_awaddr ) ,
.s_awlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_awlen[3:0]} : si_rs_awlen),
.s_awsize ( si_rs_awsize ) ,
.s_awburst ( si_rs_awburst ) ,
.s_awvalid ( si_rs_awvalid ) ,
.s_awready ( si_rs_awready ) ,
.m_awvalid ( rs_mi_awvalid ) ,
.m_awaddr ( rs_mi_awaddr ) ,
.m_awready ( rs_mi_awready ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full )
);
axi_protocol_converter_v2_1_b2s_b_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH )
)
b_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_bid ( si_rs_bid ) ,
.s_bresp ( si_rs_bresp ) ,
.s_bvalid ( si_rs_bvalid ) ,
.s_bready ( si_rs_bready ) ,
.m_bready ( rs_mi_bready ) ,
.m_bvalid ( rs_mi_bvalid ) ,
.m_bresp ( rs_mi_bresp ) ,
.b_push ( b_push ) ,
.b_awid ( b_awid ) ,
.b_awlen ( b_awlen ) ,
.b_full ( b_full ) ,
.b_resp_rdy ( si_rs_awready )
);
assign rs_mi_wdata = si_rs_wdata;
assign rs_mi_wstrb = si_rs_wstrb;
assign rs_mi_wvalid = si_rs_wvalid;
assign si_rs_wready = rs_mi_wready;
end else begin : NO_WR
assign rs_mi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_awvalid = 1'b0;
assign si_rs_awready = 1'b0;
assign rs_mi_wdata = {C_AXI_DATA_WIDTH{1'b0}};
assign rs_mi_wstrb = {C_AXI_DATA_WIDTH/8{1'b0}};
assign rs_mi_wvalid = 1'b0;
assign si_rs_wready = 1'b0;
assign rs_mi_bready = 1'b0;
assign si_rs_bvalid = 1'b0;
assign si_rs_bresp = 2'b00;
assign si_rs_bid = {C_AXI_ID_WIDTH{1'b0}};
end
endgenerate
// AR/R channel communication
wire r_push ;
wire [C_AXI_ID_WIDTH-1:0] r_arid ;
wire r_rlast ;
wire r_full ;
generate
if (C_AXI_SUPPORTS_READ == 1) begin : RD
axi_protocol_converter_v2_1_b2s_ar_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
ar_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_arid ( si_rs_arid ) ,
.s_araddr ( si_rs_araddr ) ,
.s_arlen ( (C_S_AXI_PROTOCOL == 1) ? {4'h0,si_rs_arlen[3:0]} : si_rs_arlen),
.s_arsize ( si_rs_arsize ) ,
.s_arburst ( si_rs_arburst ) ,
.s_arvalid ( si_rs_arvalid ) ,
.s_arready ( si_rs_arready ) ,
.m_arvalid ( rs_mi_arvalid ) ,
.m_araddr ( rs_mi_araddr ) ,
.m_arready ( rs_mi_arready ) ,
.r_push ( r_push ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast ) ,
.r_full ( r_full )
);
axi_protocol_converter_v2_1_b2s_r_channel #
(
.C_ID_WIDTH ( C_AXI_ID_WIDTH ),
.C_DATA_WIDTH ( C_AXI_DATA_WIDTH )
)
r_channel_0
(
.clk ( aclk ) ,
.reset ( areset_d1 ) ,
.s_rid ( si_rs_rid ) ,
.s_rdata ( si_rs_rdata ) ,
.s_rresp ( si_rs_rresp ) ,
.s_rlast ( si_rs_rlast ) ,
.s_rvalid ( si_rs_rvalid ) ,
.s_rready ( si_rs_rready ) ,
.m_rvalid ( rs_mi_rvalid ) ,
.m_rready ( rs_mi_rready ) ,
.m_rdata ( rs_mi_rdata ) ,
.m_rresp ( rs_mi_rresp ) ,
.r_push ( r_push ) ,
.r_full ( r_full ) ,
.r_arid ( r_arid ) ,
.r_rlast ( r_rlast )
);
end else begin : NO_RD
assign rs_mi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign rs_mi_arvalid = 1'b0;
assign si_rs_arready = 1'b0;
assign si_rs_rlast = 1'b1;
assign si_rs_rdata = {C_AXI_DATA_WIDTH{1'b0}};
assign si_rs_rvalid = 1'b0;
assign si_rs_rresp = 2'b00;
assign si_rs_rid = {C_AXI_ID_WIDTH{1'b0}};
assign rs_mi_rready = 1'b0;
end
endgenerate
axi_register_slice_v2_1_axi_register_slice #(
.C_AXI_PROTOCOL ( 2 ) ,
.C_AXI_ID_WIDTH ( 1 ) ,
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH ) ,
.C_AXI_DATA_WIDTH ( C_AXI_DATA_WIDTH ) ,
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ) ,
.C_AXI_AWUSER_WIDTH ( 1 ) ,
.C_AXI_ARUSER_WIDTH ( 1 ) ,
.C_AXI_WUSER_WIDTH ( 1 ) ,
.C_AXI_RUSER_WIDTH ( 1 ) ,
.C_AXI_BUSER_WIDTH ( 1 ) ,
.C_REG_CONFIG_AW ( 0 ) ,
.C_REG_CONFIG_AR ( 0 ) ,
.C_REG_CONFIG_W ( 0 ) ,
.C_REG_CONFIG_R ( 0 ) ,
.C_REG_CONFIG_B ( 0 )
) MI_REG (
.aresetn ( aresetn ) ,
.aclk ( aclk ) ,
.s_axi_awid ( 1'b0 ) ,
.s_axi_awaddr ( rs_mi_awaddr ) ,
.s_axi_awlen ( 8'h00 ) ,
.s_axi_awsize ( 3'b000 ) ,
.s_axi_awburst ( 2'b01 ) ,
.s_axi_awlock ( 1'b0 ) ,
.s_axi_awcache ( 4'h0 ) ,
.s_axi_awprot ( si_rs_awprot ) ,
.s_axi_awqos ( 4'h0 ) ,
.s_axi_awuser ( 1'b0 ) ,
.s_axi_awvalid ( rs_mi_awvalid ) ,
.s_axi_awready ( rs_mi_awready ) ,
.s_axi_awregion ( 4'h0 ) ,
.s_axi_wid ( 1'b0 ) ,
.s_axi_wdata ( rs_mi_wdata ) ,
.s_axi_wstrb ( rs_mi_wstrb ) ,
.s_axi_wlast ( 1'b1 ) ,
.s_axi_wuser ( 1'b0 ) ,
.s_axi_wvalid ( rs_mi_wvalid ) ,
.s_axi_wready ( rs_mi_wready ) ,
.s_axi_bid ( ) ,
.s_axi_bresp ( rs_mi_bresp ) ,
.s_axi_buser ( ) ,
.s_axi_bvalid ( rs_mi_bvalid ) ,
.s_axi_bready ( rs_mi_bready ) ,
.s_axi_arid ( 1'b0 ) ,
.s_axi_araddr ( rs_mi_araddr ) ,
.s_axi_arlen ( 8'h00 ) ,
.s_axi_arsize ( 3'b000 ) ,
.s_axi_arburst ( 2'b01 ) ,
.s_axi_arlock ( 1'b0 ) ,
.s_axi_arcache ( 4'h0 ) ,
.s_axi_arprot ( si_rs_arprot ) ,
.s_axi_arqos ( 4'h0 ) ,
.s_axi_aruser ( 1'b0 ) ,
.s_axi_arvalid ( rs_mi_arvalid ) ,
.s_axi_arready ( rs_mi_arready ) ,
.s_axi_arregion ( 4'h0 ) ,
.s_axi_rid ( ) ,
.s_axi_rdata ( rs_mi_rdata ) ,
.s_axi_rresp ( rs_mi_rresp ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( rs_mi_rvalid ) ,
.s_axi_rready ( rs_mi_rready ) ,
.m_axi_awid ( ) ,
.m_axi_awaddr ( m_axi_awaddr ) ,
.m_axi_awlen ( ) ,
.m_axi_awsize ( ) ,
.m_axi_awburst ( ) ,
.m_axi_awlock ( ) ,
.m_axi_awcache ( ) ,
.m_axi_awprot ( m_axi_awprot ) ,
.m_axi_awqos ( ) ,
.m_axi_awuser ( ) ,
.m_axi_awvalid ( m_axi_awvalid ) ,
.m_axi_awready ( m_axi_awready ) ,
.m_axi_awregion ( ) ,
.m_axi_wid ( ) ,
.m_axi_wdata ( m_axi_wdata ) ,
.m_axi_wstrb ( m_axi_wstrb ) ,
.m_axi_wlast ( ) ,
.m_axi_wuser ( ) ,
.m_axi_wvalid ( m_axi_wvalid ) ,
.m_axi_wready ( m_axi_wready ) ,
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( m_axi_bresp ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( m_axi_bvalid ) ,
.m_axi_bready ( m_axi_bready ) ,
.m_axi_arid ( ) ,
.m_axi_araddr ( m_axi_araddr ) ,
.m_axi_arlen ( ) ,
.m_axi_arsize ( ) ,
.m_axi_arburst ( ) ,
.m_axi_arlock ( ) ,
.m_axi_arcache ( ) ,
.m_axi_arprot ( m_axi_arprot ) ,
.m_axi_arqos ( ) ,
.m_axi_aruser ( ) ,
.m_axi_arvalid ( m_axi_arvalid ) ,
.m_axi_arready ( m_axi_arready ) ,
.m_axi_arregion ( ) ,
.m_axi_rid ( 1'b0 ) ,
.m_axi_rdata ( m_axi_rdata ) ,
.m_axi_rresp ( m_axi_rresp ) ,
.m_axi_rlast ( 1'b1 ) ,
.m_axi_ruser ( 1'b0 ) ,
.m_axi_rvalid ( m_axi_rvalid ) ,
.m_axi_rready ( m_axi_rready )
);
endmodule
`default_nettype wire
|
//---------------------------------------------------------------------//
// Name: eval_node.v
// Author: Chris Wynnyk
// Date: 2/3/2008
// Purpose: Evaluates a single node in the Binomial Lattice.
//---------------------------------------------------------------------//
module eval_node(
clk,
nrst,
p_up,
p_down,
v_up,
v_down,
v_ex,
result
);
input clk;
input nrst;
input [63:0] p_up;
input [63:0] p_down;
input [63:0] v_up;
input [63:0] v_down;
input [63:0] v_ex;
output [63:0] result;
wire [63:0] upside_value;
wire [63:0] downside_value;
wire [63:0] v_hold;
wire [63:0] v_ex_delayed;
wire [63:0] v_hold_delayed;
wire exercise;
reg [63:0] result;
//---------------------------------------------------------------------//
// Instantiations
//---------------------------------------------------------------------//
fp_mult_v1 upside_mult (
.clock ( clk ),
.dataa ( p_up ),
.datab ( v_up ),
.result ( upside_value )
);
fp_mult_v1 downside_mult (
.clock ( clk ),
.dataa ( p_down ),
.datab ( v_down ),
.result ( downside_value )
);
fp_add_v1 fp_mult_vhold (
.clock ( clk ),
.dataa ( upside_value ),
.datab ( downside_value ),
.result ( v_hold )
);
// Exercise when v_ex > v_hold.
fp_compare_v1 fp_compare_v1_inst (
.clock ( clk ),
.dataa ( v_ex ),
.datab ( v_hold ),
.agb ( exercise )
);
// Delay v_hold, v_ex by 1 clock.
lpm_ff_v1 lpm_ff_v_ex (
.clock ( clk ),
.data ( v_ex ),
.q ( v_ex_delayed )
);
// Delay v_exercise by 1 clock.
lpm_ff_v1 lpm_ff_v_hold (
.clock ( clk ),
.data ( v_hold ),
.q ( v_hold_delayed )
);
// Assign output.
always@(posedge clk)
begin
if( exercise ) result <= v_ex_delayed[63:0];
else result <= v_hold_delayed[63:0];
end
endmodule
|
//bug844
module device(
input clk,
output logic [7:0] Q, out0,
output logic pass, fail
input [7:0] D, in0,in1 );
enum logic [2:0] {IDLE, START, RUN, PASS, FAIL } state, next_state;
logic ready, next_ready;
logic next_pass, next_fail;
always_ff @(posedge clk, negedge rstn)
if (!rstn) begin
state <= IDLE;
/*AUTORESET*/
end
else begin
state <= next_state;
ready <= next_ready;
pass <= next_pass;
fail <= next_fail;
end
always @* begin
if (!ready) begin
/*AUTORESET*/
end
else begin
out0 = sel ? in1 : in0;
end
end
always_comb begin
next_state = state;
/*AUTORESET*/
case (state)
IDLE : begin
// stuff ...
end
/* Other states */
PASS: begin
next_state = IDLE;
// stuff ...
next_pass = 1'b1;
next_ready = 1'b1;
end
FAIL: begin
next_state = IDLE;
// stuff ...
next_fail = 1'b1;
end
endcase
end
always_latch begin
if (!rstn) begin
/*AUTORESET*/
end
else if (clk) begin
Q <= D;
end
end
endmodule
|
/*
Copyright (c) 2015-2016 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1 ns / 1 ps
/*
* Wishbone 2 port multiplexer
*/
module wb_mux_2 #
(
parameter DATA_WIDTH = 32, // width of data bus in bits (8, 16, 32, or 64)
parameter ADDR_WIDTH = 32, // width of address bus in bits
parameter SELECT_WIDTH = (DATA_WIDTH/8) // width of word select bus (1, 2, 4, or 8)
)
(
input wire clk,
input wire rst,
/*
* Wishbone master input
*/
input wire [ADDR_WIDTH-1:0] wbm_adr_i, // ADR_I() address input
input wire [DATA_WIDTH-1:0] wbm_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbm_dat_o, // DAT_O() data out
input wire wbm_we_i, // WE_I write enable input
input wire [SELECT_WIDTH-1:0] wbm_sel_i, // SEL_I() select input
input wire wbm_stb_i, // STB_I strobe input
output wire wbm_ack_o, // ACK_O acknowledge output
output wire wbm_err_o, // ERR_O error output
output wire wbm_rty_o, // RTY_O retry output
input wire wbm_cyc_i, // CYC_I cycle input
/*
* Wishbone slave 0 output
*/
output wire [ADDR_WIDTH-1:0] wbs0_adr_o, // ADR_O() address output
input wire [DATA_WIDTH-1:0] wbs0_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs0_dat_o, // DAT_O() data out
output wire wbs0_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs0_sel_o, // SEL_O() select output
output wire wbs0_stb_o, // STB_O strobe output
input wire wbs0_ack_i, // ACK_I acknowledge input
input wire wbs0_err_i, // ERR_I error input
input wire wbs0_rty_i, // RTY_I retry input
output wire wbs0_cyc_o, // CYC_O cycle output
/*
* Wishbone slave 0 address configuration
*/
input wire [ADDR_WIDTH-1:0] wbs0_addr, // Slave address prefix
input wire [ADDR_WIDTH-1:0] wbs0_addr_msk, // Slave address prefix mask
/*
* Wishbone slave 1 output
*/
output wire [ADDR_WIDTH-1:0] wbs1_adr_o, // ADR_O() address output
input wire [DATA_WIDTH-1:0] wbs1_dat_i, // DAT_I() data in
output wire [DATA_WIDTH-1:0] wbs1_dat_o, // DAT_O() data out
output wire wbs1_we_o, // WE_O write enable output
output wire [SELECT_WIDTH-1:0] wbs1_sel_o, // SEL_O() select output
output wire wbs1_stb_o, // STB_O strobe output
input wire wbs1_ack_i, // ACK_I acknowledge input
input wire wbs1_err_i, // ERR_I error input
input wire wbs1_rty_i, // RTY_I retry input
output wire wbs1_cyc_o, // CYC_O cycle output
/*
* Wishbone slave 1 address configuration
*/
input wire [ADDR_WIDTH-1:0] wbs1_addr, // Slave address prefix
input wire [ADDR_WIDTH-1:0] wbs1_addr_msk // Slave address prefix mask
);
wire wbs0_match = ~|((wbm_adr_i ^ wbs0_addr) & wbs0_addr_msk);
wire wbs1_match = ~|((wbm_adr_i ^ wbs1_addr) & wbs1_addr_msk);
wire wbs0_sel = wbs0_match;
wire wbs1_sel = wbs1_match & ~(wbs0_match);
wire master_cycle = wbm_cyc_i & wbm_stb_i;
wire select_error = ~(wbs0_sel | wbs1_sel) & master_cycle;
// master
assign wbm_dat_o = wbs0_sel ? wbs0_dat_i :
wbs1_sel ? wbs1_dat_i :
{DATA_WIDTH{1'b0}};
assign wbm_ack_o = wbs0_ack_i |
wbs1_ack_i;
assign wbm_err_o = wbs0_err_i |
wbs1_err_i |
select_error;
assign wbm_rty_o = wbs0_rty_i |
wbs1_rty_i;
// slave 0
assign wbs0_adr_o = wbm_adr_i;
assign wbs0_dat_o = wbm_dat_i;
assign wbs0_we_o = wbm_we_i & wbs0_sel;
assign wbs0_sel_o = wbm_sel_i;
assign wbs0_stb_o = wbm_stb_i & wbs0_sel;
assign wbs0_cyc_o = wbm_cyc_i & wbs0_sel;
// slave 1
assign wbs1_adr_o = wbm_adr_i;
assign wbs1_dat_o = wbm_dat_i;
assign wbs1_we_o = wbm_we_i & wbs1_sel;
assign wbs1_sel_o = wbm_sel_i;
assign wbs1_stb_o = wbm_stb_i & wbs1_sel;
assign wbs1_cyc_o = wbm_cyc_i & wbs1_sel;
endmodule
|
// Model of FIFO in Altera
module fifo_1c_4k ( data, wrreq, rdreq, rdclk, wrclk, aclr, q,
rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw);
parameter width = 32;
parameter depth = 4096;
//`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req
input [31:0] data;
input wrreq;
input rdreq;
input rdclk;
input wrclk;
input aclr;
output [31:0] q;
output rdfull;
output rdempty;
output [7:0] rdusedw;
output wrfull;
output wrempty;
output [7:0] wrusedw;
reg [width-1:0] mem [0:depth-1];
reg [7:0] rdptr;
reg [7:0] wrptr;
`ifdef rd_req
reg [width-1:0] q;
`else
wire [width-1:0] q;
`endif
reg [7:0] rdusedw;
reg [7:0] wrusedw;
integer i;
always @( aclr)
begin
wrptr <= #1 0;
rdptr <= #1 0;
for(i=0;i<depth;i=i+1)
mem[i] <= #1 0;
end
always @(posedge wrclk)
if(wrreq)
begin
wrptr <= #1 wrptr+1;
mem[wrptr] <= #1 data;
end
always @(posedge rdclk)
if(rdreq)
begin
rdptr <= #1 rdptr+1;
`ifdef rd_req
q <= #1 mem[rdptr];
`endif
end
`ifdef rd_req
`else
assign q = mem[rdptr];
`endif
// Fix these
always @(posedge wrclk)
wrusedw <= #1 wrptr - rdptr;
always @(posedge rdclk)
rdusedw <= #1 wrptr - rdptr;
endmodule // fifo_1c_4k
|
// file: clk_wiz_v3_6_0.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___125.000______0.000______50.0______125.247_____98.575
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
module clk_wiz_v3_6_0
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
//assign clkin1 = CLK_IN1;
BUFG clkin1_buf (
.I (CLK_IN1),
.O (clkin1)
);
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (8.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// pipeline_registers.v
// Created: 4.4.2012
// Modified: 4.4.2012
//
// Implements a series of pipeline registers specified by the input
// parameters BIT_WIDTH and NUMBER_OF_STAGES. BIT_WIDTH determines the
// size of the signal passed through each of the pipeline
// registers. NUMBER_OF_STAGES is the number of pipeline registers
// generated. This accepts values of 0 (yes, it just passes data from
// input to output...) up to however many stages specified.
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pipeline_registers
(
input clk,
input reset_n,
input [BIT_WIDTH-1:0] pipe_in,
output reg [BIT_WIDTH-1:0] pipe_out
);
// WARNING!!! THESE PARAMETERS ARE INTENDED TO BE MODIFIED IN A TOP
// LEVEL MODULE. LOCAL CHANGES HERE WILL, MOST LIKELY, BE
// OVERWRITTEN!
parameter
BIT_WIDTH = 10,
NUMBER_OF_STAGES = 5;
// Main generate function for conditional hardware instantiation
generate
genvar i;
// Pass-through case for the odd event that no pipeline stages are
// specified.
if (NUMBER_OF_STAGES == 0) begin
always @ *
pipe_out = pipe_in;
end
// Single flop case for a single stage pipeline
else if (NUMBER_OF_STAGES == 1) begin
always @ (posedge clk or negedge reset_n)
pipe_out <= (!reset_n) ? 0 : pipe_in;
end
// Case for 2 or more pipeline stages
else begin
// Create the necessary regs
reg [BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:0] pipe_gen;
// Create logic for the initial and final pipeline registers
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
pipe_gen[BIT_WIDTH-1:0] <= 0;
pipe_out <= 0;
end
else begin
pipe_gen[BIT_WIDTH-1:0] <= pipe_in;
pipe_out <= pipe_gen[BIT_WIDTH*(NUMBER_OF_STAGES-1)-1:BIT_WIDTH*(NUMBER_OF_STAGES-2)];
end
end
// Create the intermediate pipeline registers if there are 3 or
// more pipeline stages
for (i = 1; i < NUMBER_OF_STAGES-1; i = i + 1) begin : pipeline
always @ (posedge clk or negedge reset_n)
pipe_gen[BIT_WIDTH*(i+1)-1:BIT_WIDTH*i] <= (!reset_n) ? 0 : pipe_gen[BIT_WIDTH*i-1:BIT_WIDTH*(i-1)];
end
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: infrastructure.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created:Tue Jun 30 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: infrastructure.v,v 1.1 2011/06/02 08:34:56 mishra Exp $
**$Date: 2011/06/02 08:34:56 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/infrastructure.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_infrastructure #
(
parameter SIMULATION = "FALSE", // Should be TRUE during design simulations and
// FALSE during implementations
parameter TCQ = 100, // clk->out delay (sim only)
parameter CLKIN_PERIOD = 3000, // Memory clock period
parameter nCK_PER_CLK = 2, // Fabric clk period:Memory clk period
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
// "DIFFERENTIAL","SINGLE_ENDED"
parameter UI_EXTRA_CLOCKS = "FALSE",
// Generates extra clocks as
// 1/2, 1/4 and 1/8 of fabrick clock.
// Valid for DDR2/DDR3 AXI interfaces
// based on GUI selection
parameter CLKFBOUT_MULT = 4, // write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor
parameter CLKOUT0_PHASE = 45.0, // VCO output divisor for clkout0
parameter CLKOUT0_DIVIDE = 16, // VCO output divisor for PLL clkout0
parameter CLKOUT1_DIVIDE = 4, // VCO output divisor for PLL clkout1
parameter CLKOUT2_DIVIDE = 64, // VCO output divisor for PLL clkout2
parameter CLKOUT3_DIVIDE = 16, // VCO output divisor for PLL clkout3
parameter MMCM_CLKOUT0_EN = "FALSE", // Enabled (or) Disable MMCM clkout0
parameter MMCM_CLKOUT1_EN = "FALSE", // Enabled (or) Disable MMCM clkout1
parameter MMCM_CLKOUT2_EN = "FALSE", // Enabled (or) Disable MMCM clkout2
parameter MMCM_CLKOUT3_EN = "FALSE", // Enabled (or) Disable MMCM clkout3
parameter MMCM_CLKOUT4_EN = "FALSE", // Enabled (or) Disable MMCM clkout4
parameter MMCM_CLKOUT0_DIVIDE = 1, // VCO output divisor for MMCM clkout0
parameter MMCM_CLKOUT1_DIVIDE = 1, // VCO output divisor for MMCM clkout1
parameter MMCM_CLKOUT2_DIVIDE = 1, // VCO output divisor for MMCM clkout2
parameter MMCM_CLKOUT3_DIVIDE = 1, // VCO output divisor for MMCM clkout3
parameter MMCM_CLKOUT4_DIVIDE = 1, // VCO output divisor for MMCM clkout4
parameter RST_ACT_LOW = 1
)
(
// Clock inputs
input mmcm_clk, // System clock diff input
// System reset input
input sys_rst, // core reset from user application
// PLLE2/IDELAYCTRL Lock status
input iodelay_ctrl_rdy, // IDELAYCTRL lock status
// Clock outputs
output clk, // fabric clock freq ; either half rate or quarter rate and is
// determined by PLL parameters settings.
output mem_refclk, // equal to memory clock
output freq_refclk, // freq above 400 MHz: set freq_refclk = mem_refclk
// freq below 400 MHz: set freq_refclk = 2* mem_refclk or 4* mem_refclk;
// to hard PHY for phaser
output sync_pulse, // exactly 1/16 of mem_refclk and the sync pulse is exactly 1 memref_clk wide
output auxout_clk, // IO clk used to clock out Aux_Out ports
output ui_addn_clk_0, // MMCM out0 clk
output ui_addn_clk_1, // MMCM out1 clk
output ui_addn_clk_2, // MMCM out2 clk
output ui_addn_clk_3, // MMCM out3 clk
output ui_addn_clk_4, // MMCM out4 clk
output pll_locked, // locked output from PLLE2_ADV
output mmcm_locked, // locked output from MMCME2_ADV
// Reset outputs
output rstdiv0 // Reset CLK and CLKDIV logic (incl I/O),
,output rst_phaser_ref
,input ref_dll_lock
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
localparam RST_SYNC_NUM = 25;
// Round up for clk reset delay to ensure that CLKDIV reset deassertion
// occurs at same time or after CLK reset deassertion (still need to
// consider route delay - add one or two extra cycles to be sure!)
localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2;
// Input clock is assumed to be equal to the memory clock frequency
// User should change the parameter as necessary if a different input
// clock frequency is used
localparam real CLKIN1_PERIOD_NS = CLKIN_PERIOD / 1000.0;
localparam CLKOUT4_DIVIDE = 2 * CLKOUT1_DIVIDE;
localparam integer VCO_PERIOD
= (CLKIN1_PERIOD_NS * DIVCLK_DIVIDE * 1000) / CLKFBOUT_MULT;
localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE;
localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE;
localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE;
localparam CLKOUT3_PERIOD = VCO_PERIOD * CLKOUT3_DIVIDE;
localparam CLKOUT4_PERIOD = VCO_PERIOD * CLKOUT4_DIVIDE;
localparam CLKOUT4_PHASE = (SIMULATION == "TRUE") ? 22.5 : 168.75;
localparam real CLKOUT3_PERIOD_NS = CLKOUT3_PERIOD / 1000.0;
localparam real CLKOUT4_PERIOD_NS = CLKOUT4_PERIOD / 1000.0;
//synthesis translate_off
initial begin
$display("############# Write Clocks PLLE2_ADV Parameters #############\n");
$display("nCK_PER_CLK = %7d", nCK_PER_CLK );
$display("CLK_PERIOD = %7d", CLKIN_PERIOD );
$display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD_NS);
$display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE );
$display("CLKFBOUT_MULT = %7d", CLKFBOUT_MULT );
$display("VCO_PERIOD = %7d", VCO_PERIOD );
$display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE );
$display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE );
$display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE );
$display("CLKOUT3_DIVIDE = %7d", CLKOUT3_DIVIDE );
$display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD );
$display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD );
$display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD );
$display("CLKOUT3_PERIOD = %7d", CLKOUT3_PERIOD );
$display("CLKOUT4_PERIOD = %7d", CLKOUT4_PERIOD );
$display("############################################################\n");
end
//synthesis translate_on
wire clk_bufg;
wire clk_pll;
wire clkfbout_pll;
wire mmcm_clkfbout;
(* keep = "true", max_fanout = 10 *) wire pll_locked_i
/* synthesis syn_maxfan = 10 */;
reg [RST_DIV_SYNC_NUM-2:0] rstdiv0_sync_r;
wire rst_tmp;
(* keep = "true", max_fanout = 10 *) reg rstdiv0_sync_r1
/* synthesis syn_maxfan = 10 */;
wire sys_rst_act_hi;
wire rst_tmp_phaser_ref;
(* keep = "true", max_fanout = 10 *) reg [RST_DIV_SYNC_NUM-1:0] rst_phaser_ref_sync_r
/* synthesis syn_maxfan = 10 */;
// Instantiation of the MMCM primitive
wire clkfbout;
wire MMCM_Locked_i;
wire mmcm_clkout0;
wire mmcm_clkout1;
wire mmcm_clkout2;
wire mmcm_clkout3;
wire mmcm_clkout4;
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst;
//***************************************************************************
// Assign global clocks:
// 2. clk : Half rate / Quarter rate(used for majority of internal logic)
//***************************************************************************
assign clk = clk_bufg;
assign pll_locked = pll_locked_i & MMCM_Locked_i;
assign mmcm_locked = MMCM_Locked_i;
//***************************************************************************
// Global base clock generation and distribution
//***************************************************************************
//*****************************************************************
// NOTES ON CALCULTING PROPER VCO FREQUENCY
// 1. VCO frequency =
// 1/((DIVCLK_DIVIDE * CLKIN_PERIOD)/(CLKFBOUT_MULT * nCK_PER_CLK))
// 2. VCO frequency must be in the range [TBD, TBD]
//*****************************************************************
PLLE2_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("INTERNAL"),
.STARTUP_WAIT ("FALSE"),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), // 4 freq_ref
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), // 4 mem_ref
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), // 16 sync
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), // 16 sysclk
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE (),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_PHASE (0.000),
.CLKIN1_PERIOD (CLKIN1_PERIOD_NS),
.CLKIN2_PERIOD (),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (1.0/16.0),
.CLKOUT2_PHASE (9.84375), // PHASE shift is required for sync pulse generation.
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_PHASE (CLKOUT4_PHASE),
.CLKOUT5_DUTY_CYCLE (0.500),
.CLKOUT5_PHASE (0.000),
.REF_JITTER1 (0.010),
.REF_JITTER2 (0.010)
)
plle2_i
(
.CLKFBOUT (pll_clkfbout),
.CLKOUT0 (freq_refclk),
.CLKOUT1 (mem_refclk),
.CLKOUT2 (sync_pulse), // always 1/16 of mem_ref_clk
.CLKOUT3 (pll_clk3),
.CLKOUT4 (auxout_clk_i),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (pll_locked_i),
.CLKFBIN (pll_clkfbout),
.CLKIN1 (mmcm_clk),
.CLKIN2 (),
.CLKINSEL (1'b1),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.PWRDWN (1'b0),
.RST ( sys_rst_act_hi)
);
BUFH u_bufh_auxout_clk
(
.O (auxout_clk),
.I (auxout_clk_i)
);
BUFG u_bufg_clkdiv0
(
.O (clk_bufg),
.I (clk_pll_i)
);
localparam integer MMCM_VCO_MIN_FREQ = 600;
localparam integer MMCM_VCO_MAX_FREQ = 1200; // This is the maximum VCO frequency for a -1 part
localparam real MMCM_VCO_MIN_PERIOD = 1000000.0/MMCM_VCO_MAX_FREQ;
localparam real MMCM_VCO_MAX_PERIOD = 1000000.0/MMCM_VCO_MIN_FREQ;
localparam real MMCM_MULT_F_MID = CLKOUT3_PERIOD/(MMCM_VCO_MAX_PERIOD*0.75);
localparam real MMCM_EXPECTED_PERIOD = CLKOUT3_PERIOD / MMCM_MULT_F_MID;
localparam real MMCM_MULT_F = ((MMCM_EXPECTED_PERIOD > MMCM_VCO_MAX_PERIOD) ? MMCM_MULT_F_MID + 1.0 : MMCM_MULT_F_MID);
localparam real MMCM_VCO_FREQ = MMCM_MULT_F / (1 * CLKOUT3_PERIOD_NS);
localparam real MMCM_VCO_PERIOD = (CLKOUT3_PERIOD_NS * 1000) / MMCM_MULT_F;
//synthesis translate_off
initial begin
$display("############# MMCME2_ADV Parameters #############\n");
$display("MMCM_VCO_MIN_PERIOD = %7.3f", MMCM_VCO_MIN_PERIOD);
$display("MMCM_VCO_MAX_PERIOD = %7.3f", MMCM_VCO_MAX_PERIOD);
$display("MMCM_MULT_F_MID = %7.3f", MMCM_MULT_F_MID);
$display("MMCM_EXPECTED_PERIOD = %7.3f", MMCM_EXPECTED_PERIOD);
$display("MMCM_MULT_F = %7.3f", MMCM_MULT_F);
$display("CLKOUT3_PERIOD_NS = %7.3f", CLKOUT3_PERIOD_NS);
$display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO_FREQ*1000.0);
$display("MMCM_VCO_PERIOD = %7.3f", MMCM_VCO_PERIOD);
$display("#################################################\n");
end
//synthesis translate_on
generate
if (UI_EXTRA_CLOCKS == "TRUE") begin: gen_ui_extra_clocks
localparam MMCM_CLKOUT0_DIVIDE_CAL = (MMCM_CLKOUT0_EN == "TRUE") ? MMCM_CLKOUT0_DIVIDE : MMCM_MULT_F;
localparam MMCM_CLKOUT1_DIVIDE_CAL = (MMCM_CLKOUT1_EN == "TRUE") ? MMCM_CLKOUT1_DIVIDE : MMCM_MULT_F;
localparam MMCM_CLKOUT2_DIVIDE_CAL = (MMCM_CLKOUT2_EN == "TRUE") ? MMCM_CLKOUT2_DIVIDE : MMCM_MULT_F;
localparam MMCM_CLKOUT3_DIVIDE_CAL = (MMCM_CLKOUT3_EN == "TRUE") ? MMCM_CLKOUT3_DIVIDE : MMCM_MULT_F;
localparam MMCM_CLKOUT4_DIVIDE_CAL = (MMCM_CLKOUT4_EN == "TRUE") ? MMCM_CLKOUT4_DIVIDE : MMCM_MULT_F;
MMCME2_ADV
#(.BANDWIDTH ("HIGH"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("BUF_IN"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (MMCM_MULT_F),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLKOUT0_DIVIDE_CAL),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE_CAL),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE_CAL),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE_CAL),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE_CAL),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (CLKOUT3_PERIOD_NS),
.REF_JITTER1 (0.000))
mmcm_i
// Output clocks
(.CLKFBOUT (clk_pll_i),
.CLKFBOUTB (),
.CLKOUT0 (mmcm_clkout0),
.CLKOUT0B (),
.CLKOUT1 (mmcm_clkout1),
.CLKOUT1B (),
.CLKOUT2 (mmcm_clkout2),
.CLKOUT2B (),
.CLKOUT3 (mmcm_clkout3),
.CLKOUT3B (),
.CLKOUT4 (mmcm_clkout4),
.CLKOUT5 (),
.CLKOUT6 (),
// Input clock control
.CLKFBIN (clk_bufg), // From BUFH network
.CLKIN1 (pll_clk3), // From PLL
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (),
.DRDY (),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (MMCM_Locked_i),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (~pll_locked_i));
BUFG u_bufg_ui_addn_clk_0
(
.O (ui_addn_clk_0),
.I (mmcm_clkout0)
);
BUFG u_bufg_ui_addn_clk_1
(
.O (ui_addn_clk_1),
.I (mmcm_clkout1)
);
BUFG u_bufg_ui_addn_clk_2
(
.O (ui_addn_clk_2),
.I (mmcm_clkout2)
);
BUFG u_bufg_ui_addn_clk_3
(
.O (ui_addn_clk_3),
.I (mmcm_clkout3)
);
BUFG u_bufg_ui_addn_clk_4
(
.O (ui_addn_clk_4),
.I (mmcm_clkout4)
);
end else begin: gen_mmcm
MMCME2_ADV
#(.BANDWIDTH ("HIGH"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("BUF_IN"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (MMCM_MULT_F),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_MULT_F),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (CLKOUT3_PERIOD_NS),
.REF_JITTER1 (0.000))
mmcm_i
// Output clocks
(.CLKFBOUT (clk_pll_i),
.CLKFBOUTB (),
.CLKOUT0 (),
.CLKOUT0B (),
.CLKOUT1 (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
// Input clock control
.CLKFBIN (clk_bufg), // From BUFH network
.CLKIN1 (pll_clk3), // From PLL
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (),
.DRDY (),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (MMCM_Locked_i),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (~pll_locked_i));
end
endgenerate
//***************************************************************************
// RESET SYNCHRONIZATION DESCRIPTION:
// Various resets are generated to ensure that:
// 1. All resets are synchronously deasserted with respect to the clock
// domain they are interfacing to. There are several different clock
// domains - each one will receive a synchronized reset.
// 2. The reset deassertion order starts with deassertion of SYS_RST,
// followed by deassertion of resets for various parts of the design
// (see "RESET ORDER" below) based on the lock status of PLLE2s.
// RESET ORDER:
// 1. User deasserts SYS_RST
// 2. Reset PLLE2 and IDELAYCTRL
// 3. Wait for PLLE2 and IDELAYCTRL to lock
// 4. Release reset for all I/O primitives and internal logic
// OTHER NOTES:
// 1. Asynchronously assert reset. This way we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers
// to prevent initial bus contention). Reset deassertion is synchronous.
//***************************************************************************
//*****************************************************************
// CLKDIV logic reset
//*****************************************************************
// Wait for PLLE2 and IDELAYCTRL to lock before releasing reset
// current O,25.0 unisim phaser_ref never locks. Need to find out why .
assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy |
~ref_dll_lock | ~MMCM_Locked_i;
always @(posedge clk_bufg or posedge rst_tmp) begin
if (rst_tmp) begin
rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}};
rstdiv0_sync_r1 <= #TCQ 1'b1 ;
end else begin
rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1;
rstdiv0_sync_r1 <= #TCQ rstdiv0_sync_r[RST_DIV_SYNC_NUM-2];
end
end
assign rstdiv0 = rstdiv0_sync_r1 ;
assign rst_tmp_phaser_ref = sys_rst_act_hi | ~pll_locked_i | ~iodelay_ctrl_rdy;
always @(posedge clk_bufg or posedge rst_tmp_phaser_ref)
if (rst_tmp_phaser_ref)
rst_phaser_ref_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}};
else
rst_phaser_ref_sync_r <= #TCQ rst_phaser_ref_sync_r << 1;
assign rst_phaser_ref = rst_phaser_ref_sync_r[RST_DIV_SYNC_NUM-1];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_SYMBOL_V
`define SKY130_FD_SC_LP__XOR2_SYMBOL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__xor2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_SYMBOL_V
|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Tested against an IDT 71v65603s150 in simulation and a Cypress 7C1356C in the real world.
module nobl_if
#(parameter WIDTH=18,DEPTH=19)
(
input clk,
input rst,
input [WIDTH-1:0] RAM_D_pi,
output [WIDTH-1:0] RAM_D_po,
output reg RAM_D_poe,
output [DEPTH-1:0] RAM_A,
output reg RAM_WEn,
output RAM_CENn,
output RAM_LDn,
output RAM_OEn,
output reg RAM_CE1n,
input [DEPTH-1:0] address,
input [WIDTH-1:0] data_out,
output reg [WIDTH-1:0] data_in,
output reg data_in_valid,
input write,
input enable
);
reg enable_pipe1;
reg [DEPTH-1:0] address_pipe1;
reg write_pipe1;
reg [WIDTH-1:0] data_out_pipe1;
reg enable_pipe2;
reg write_pipe2;
reg [WIDTH-1:0] data_out_pipe2;
reg enable_pipe3;
reg write_pipe3;
reg [WIDTH-1:0] data_out_pipe3;
assign RAM_LDn = 0;
// ZBT/NoBL RAM actually manages its own output enables very well.
assign RAM_OEn = 0;
// gray code the address to reduce EMI
wire [DEPTH-1:0] address_gray;
bin2gray #(.WIDTH(DEPTH)) bin2gray (.bin(address),.gray(address_gray));
//
// Pipeline stage 1
//
always @(posedge clk)
if (rst)
begin
enable_pipe1 <= 0;
address_pipe1 <= 0;
write_pipe1 <= 0;
data_out_pipe1 <= 0;
RAM_WEn <= 1;
RAM_CE1n <= 1;
end
else
begin
enable_pipe1 <= enable;
RAM_CE1n <= ~enable; // Creates IOB flop
RAM_WEn <= ~write; // Creates IOB flop
if (enable)
begin
address_pipe1 <= address_gray;
write_pipe1 <= write;
// RAM_WEn <= ~write; // Creates IOB flop
if (write)
data_out_pipe1 <= data_out;
end
end // always @ (posedge clk)
// Pipeline 1 drives address, write_enable, chip_select on NoBL SRAM
assign RAM_A = address_pipe1;
assign RAM_CENn = 1'b0;
// assign RAM_WEn = ~write_pipe1;
// assign RAM_CE1n = ~enable_pipe1;
//
// Pipeline stage2
//
always @(posedge clk)
if (rst)
begin
enable_pipe2 <= 0;
data_out_pipe2 <= 0;
write_pipe2 <= 0;
end
else
begin
data_out_pipe2 <= data_out_pipe1;
write_pipe2 <= write_pipe1;
enable_pipe2 <= enable_pipe1;
end
//
// Pipeline stage3
//
always @(posedge clk)
if (rst)
begin
enable_pipe3 <= 0;
data_out_pipe3 <= 0;
write_pipe3 <= 0;
RAM_D_poe <= 0;
end
else
begin
data_out_pipe3 <= data_out_pipe2;
write_pipe3 <= write_pipe2;
enable_pipe3 <= enable_pipe2;
RAM_D_poe <= ~(write_pipe2 & enable_pipe2); // Active low driver enable in Xilinx.
end
// Pipeline 3 drives write data on NoBL SRAM
assign RAM_D_po = data_out_pipe3;
//
// Pipeline stage4
//
always @(posedge clk)
if (rst)
begin
data_in_valid <= 0;
data_in <= 0;
end
else
begin
data_in <= RAM_D_pi;
if (enable_pipe3 & ~write_pipe3)
begin
// Read data now available to be registered.
data_in_valid <= 1'b1;
end
else
data_in_valid <= 1'b0;
end // always @ (posedge clk)
endmodule // nobl_if
|
/*
* DAC register file for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* VGA FML support
* Copyright (C) 2013 Charley Picker <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_dac_regs_fml (
input clk,
// VGA read interface
input [7:0] index,
output reg [3:0] red,
output reg [3:0] green,
output reg [3:0] blue,
// CPU interface
input write,
// CPU read interface
input [1:0] read_data_cycle,
input [7:0] read_data_register,
output reg [3:0] read_data,
// CPU write interface
input [1:0] write_data_cycle,
input [7:0] write_data_register,
input [3:0] write_data
);
// Registers, nets and parameters
reg [3:0] red_dac [0:255];
reg [3:0] green_dac [0:255];
reg [3:0] blue_dac [0:255];
// Behaviour
// VGA read interface
always @(posedge clk)
begin
red <= red_dac[index];
green <= green_dac[index];
blue <= blue_dac[index];
end
// CPU read interface
always @(posedge clk)
case (read_data_cycle)
2'b00: read_data <= red_dac[read_data_register];
2'b01: read_data <= green_dac[read_data_register];
2'b10: read_data <= blue_dac[read_data_register];
default: read_data <= 4'h0;
endcase
// CPU write interface
always @(posedge clk)
if (write)
case (write_data_cycle)
2'b00: red_dac[write_data_register] <= write_data;
2'b01: green_dac[write_data_register] <= write_data;
2'b10: blue_dac[write_data_register] <= write_data;
endcase
endmodule
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main(
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_ROMSEL_IN,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA_IN,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
inout [15:0] ROM_DATA,
output [22:0] ROM_ADDR,
output ROM_CE,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_CE,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
inout SPI_SCK,
input MCU_OVR,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK,
/* debug */
output p113_out
);
wire CLK2;
wire [7:0] CX4_SNES_DATA_IN;
wire [7:0] CX4_SNES_DATA_OUT;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [2:0] MAPPER;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
wire [2:0] dac_vol_select_out;
wire [7:0] msu_volumerq_out;
wire [7:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
wire [23:0] cx4_datrom_data;
wire [9:0] cx4_datrom_addr;
wire cx4_datrom_we;
wire [8:0] snescmd_addr_mcu;
wire [7:0] snescmd_data_out_mcu;
wire [7:0] snescmd_data_in_mcu;
reg [7:0] SNES_PARDr;
reg [7:0] SNES_READr;
reg [7:0] SNES_WRITEr;
reg [7:0] SNES_CPU_CLKr;
reg [7:0] SNES_ROMSELr;
reg [23:0] SNES_ADDRr [5:0];
reg [7:0] SNES_PAr [5:0];
reg [7:0] SNES_DATAr [4:0];
reg[17:0] SNES_DEAD_CNTr = 18'h00000;
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
wire SNES_PARD_start = ((SNES_PARDr[6:1] & SNES_PARDr[7:2]) == 6'b111110);
wire SNES_RD_start = ((SNES_READr[6:1] & SNES_READr[7:2]) == 6'b111110);
wire SNES_RD_end = ((SNES_READr[6:1] & SNES_READr[7:2]) == 6'b000001);
wire SNES_WR_end = ((SNES_WRITEr[6:1] & SNES_WRITEr[7:2]) == 6'b000001);
wire SNES_cycle_start = ((SNES_CPU_CLKr[4:1] & SNES_CPU_CLKr[5:2]) == 4'b0001);
wire SNES_cycle_end = ((SNES_CPU_CLKr[4:1] & SNES_CPU_CLKr[5:2]) == 4'b1110);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire SNES_ROMSEL = (SNES_ROMSELr[5] & SNES_ROMSELr[4]);
wire [23:0] SNES_ADDR = (SNES_ADDRr[5] & SNES_ADDRr[4]);
wire [7:0] SNES_PA = (SNES_PAr[5] & SNES_PAr[4]);
wire [7:0] SNES_DATA_IN = (SNES_DATAr[3] & SNES_DATAr[2]);
wire free_slot = SNES_cycle_end | free_strobe;
reg [7:0] BUS_DATA;
always @(posedge CLK2) begin
if(~SNES_READ) BUS_DATA <= SNES_DATA;
else if(~SNES_WRITE) BUS_DATA <= SNES_DATA_IN;
end
wire ROM_HIT;
assign DCM_RST=0;
always @(posedge CLK2) begin
free_strobe <= 1'b0;
if(SNES_cycle_start) free_strobe <= ~ROM_HIT;
end
always @(posedge CLK2) begin
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ROMSELr <= {SNES_ROMSELr[6:0], SNES_ROMSEL_IN};
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
SNES_PAr[5] <= SNES_PAr[4];
SNES_PAr[4] <= SNES_PAr[3];
SNES_PAr[3] <= SNES_PAr[2];
SNES_PAr[2] <= SNES_PAr[1];
SNES_PAr[1] <= SNES_PAr[0];
SNES_PAr[0] <= SNES_PA_IN;
SNES_DATAr[4] <= SNES_DATAr[3];
SNES_DATAr[3] <= SNES_DATAr[2];
SNES_DATAr[2] <= SNES_DATAr[1];
SNES_DATAr[1] <= SNES_DATAr[0];
SNES_DATAr[0] <= SNES_DATA;
end
parameter ST_IDLE = 7'b0000001;
parameter ST_MCU_RD_ADDR = 7'b0000010;
parameter ST_MCU_RD_END = 7'b0000100;
parameter ST_MCU_WR_ADDR = 7'b0001000;
parameter ST_MCU_WR_END = 7'b0010000;
parameter ST_CX4_RD_ADDR = 7'b0100000;
parameter ST_CX4_RD_END = 7'b1000000;
parameter ROM_CYCLE_LEN = 4'd6;
parameter SNES_DEAD_TIMEOUT = 17'd80000; // 1ms
reg [6:0] STATE;
initial STATE = ST_IDLE;
assign MSU_SNES_DATA_IN = BUS_DATA;
assign CX4_SNES_DATA_IN = BUS_DATA;
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK)
);
wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk_out(DAC_MCLK),
.lrck_out(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.vol_select(dac_vol_select_out),
.palmode(dac_palmode_out),
.play(dac_play),
.reset(dac_reset)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
reg [7:0] MCU_DINr;
wire [7:0] MCU_DOUT;
wire [7:0] featurebits;
wire [31:0] cheat_pgm_data;
wire [7:0] cheat_data_out;
wire [2:0] cheat_pgm_idx;
wire [15:0] dsp_feat;
wire [7:0] snescmd_data_in_mcu_dbg;
wire feat_cmd_unlock = featurebits[5];
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
// .dac_volume_out(dac_volume),
// .dac_volume_latch_out(dac_vol_latch),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.dac_vol_select_out(dac_vol_select_out),
.dac_palmode_out(dac_palmode_out),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY),
.featurebits_out(featurebits),
.cx4_reset_out(cx4_reset),
.region_out(mcu_region),
.snescmd_addr_out(snescmd_addr_mcu),
.snescmd_we_out(snescmd_we_mcu),
.snescmd_data_out(snescmd_data_out_mcu),
.snescmd_data_in(snescmd_data_in_mcu),
.cheat_pgm_idx_out(cheat_pgm_idx),
.cheat_pgm_data_out(cheat_pgm_data),
.cheat_pgm_we_out(cheat_pgm_we),
.dsp_feat_out(dsp_feat)
);
wire [7:0] DCM_STATUS;
// dcm1: dfs 4x
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST),
.STATUS(DCM_STATUS)
);
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_PA(SNES_PA),
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.ROM_HIT(ROM_HIT),
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
.featurebits(featurebits),
//MSU-1
.msu_enable(msu_enable),
//CX4
.cx4_enable(cx4_enable),
.cx4_vect_enable(cx4_vect_enable),
//region
.r213f_enable(r213f_enable),
//CMD Interface
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable)
);
assign DCM_RST=0;
//always @(posedge CLK2) begin
// non_hit_cycle <= 1'b0;
// if(SNES_cycle_start) non_hit_cycle <= ~ROM_HIT;
//end
reg [7:0] CX4_DINr;
wire [23:0] CX4_ADDR;
wire [2:0] cx4_busy;
cx4 snes_cx4 (
.DI(CX4_SNES_DATA_IN),
.DO(CX4_SNES_DATA_OUT),
.ADDR(SNES_ADDR[12:0]),
.CS(cx4_enable),
.SNES_VECT_EN(cx4_vect_enable),
.reg_we_rising(SNES_WR_end),
.CLK(CLK2),
.BUS_DI(CX4_DINr),
.BUS_ADDR(CX4_ADDR),
.BUS_RRQ(CX4_RRQ),
.BUS_RDY(CX4_RDY),
.cx4_active(cx4_active),
.cx4_busy_out(cx4_busy),
.speed(dsp_feat[0])
);
reg pad_latch = 0;
reg [4:0] pad_cnt = 0;
reg snes_ajr = 0;
cheat snes_cheat(
.clk(CLK2),
.SNES_ADDR(SNES_ADDR),
.SNES_PA(SNES_PA),
.SNES_DATA(SNES_DATA),
.SNES_reset_strobe(SNES_reset_strobe),
.SNES_cycle_start(SNES_cycle_start),
.SNES_wr_strobe(SNES_WR_end),
.SNES_rd_strobe(SNES_RD_start),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable),
.pad_latch(pad_latch),
.snes_ajr(snes_ajr),
.pgm_idx(cheat_pgm_idx),
.pgm_we(cheat_pgm_we),
.pgm_in(cheat_pgm_data),
.data_out(cheat_data_out),
.cheat_hit(cheat_hit),
.snescmd_unlock(snescmd_unlock)
);
wire [7:0] snescmd_dout;
reg [7:0] r213fr;
reg r213f_forceread;
reg [2:0] r213f_delay;
reg [1:0] r213f_state;
initial r213fr = 8'h55;
initial r213f_forceread = 0;
initial r213f_state = 2'b01;
initial r213f_delay = 3'b000;
wire snoop_4200_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04200;
wire r4016_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04016;
always @(posedge CLK2) begin
if(SNES_WR_end & snoop_4200_enable) begin
snes_ajr <= SNES_DATA[0];
end
end
always @(posedge CLK2) begin
if(SNES_WR_end & r4016_enable) begin
pad_latch <= 1'b1;
pad_cnt <= 5'h0;
end
if(SNES_RD_start & r4016_enable) begin
pad_cnt <= pad_cnt + 1;
if(&pad_cnt[3:0]) begin
pad_latch <= 1'b0;
end
end
end
assign SNES_DATA = (r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
:(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
? (msu_enable ? MSU_SNES_DATA_OUT
:cx4_enable ? CX4_SNES_DATA_OUT
:(cx4_active & cx4_vect_enable) ? CX4_SNES_DATA_OUT
:(cheat_hit & ~feat_cmd_unlock) ? cheat_data_out
:(snescmd_unlock | feat_cmd_unlock) & snescmd_enable ? snescmd_dout
:(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])
): 8'bZ;
reg [4:0] ST_MEM_DELAYr;
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg CX4_RD_PENDr = 0;
reg [23:0] ROM_ADDRr;
reg [23:0] CX4_ADDRr;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
assign MCU_RDY = RQ_MCU_RDYr;
reg RQ_CX4_RDYr;
initial RQ_CX4_RDYr = 1'b1;
assign CX4_RDY = RQ_CX4_RDYr;
wire MCU_WR_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_RD_HIT = |(STATE & ST_MCU_RD_ADDR);
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
wire CX4_HIT = |(STATE & ST_CX4_RD_ADDR);
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : CX4_HIT ? CX4_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : MCU_HIT ? ROM_ADDRr[0] : CX4_HIT ? CX4_ADDRr[0] : MAPPED_SNES_ADDR[0];
always @(posedge CLK2) begin
if(cx4_active) begin
if(CX4_RRQ) begin
CX4_RD_PENDr <= 1'b1;
RQ_CX4_RDYr <= 1'b0;
CX4_ADDRr <= CX4_ADDR;
end else if(STATE == ST_CX4_RD_END) begin
CX4_RD_PENDr <= 1'b0;
RQ_CX4_RDYr <= 1'b1;
end
end
end
always @(posedge CLK2) begin
if(MCU_RRQ) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 17'h0;
end
always @(posedge CLK2) begin
SNES_reset_strobe <= 1'b0;
if(SNES_CPU_CLKr[1]) begin
SNES_DEADr <= 1'b0;
if(SNES_DEADr) SNES_reset_strobe <= 1'b1;
end
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if(cx4_active) begin
if (CX4_RD_PENDr) begin
STATE <= ST_CX4_RD_ADDR;
ST_MEM_DELAYr <= 16;
end
end else if(free_slot | SNES_DEADr) begin
if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_MCU_RD_END, ST_MCU_WR_END: begin
STATE <= ST_IDLE;
end
ST_CX4_RD_ADDR: begin
STATE <= ST_CX4_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_CX4_RD_END;
CX4_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_CX4_RD_END: begin
STATE <= ST_IDLE;
end
endcase
end
always @(posedge CLK2) begin
if(SNES_cycle_end) r213f_forceread <= 1'b1;
else if(SNES_PARD_start & r213f_enable) begin
// r213f_delay <= 3'b000;
// r213f_state <= 2'b10;
// end else if(r213f_state == 2'b10) begin
// r213f_delay <= r213f_delay - 1;
// if(r213f_delay == 3'b000) begin
r213f_forceread <= 1'b0;
r213f_state <= 2'b01;
r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
// end
end
end
reg MCU_WRITE_1;
always @(posedge CLK2) MCU_WRITE_1<= MCU_WRITE;
assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = SD_DMA_TO_ROM
?MCU_WRITE
: (ROM_HIT & IS_WRITABLE & SNES_CPU_CLK) ? SNES_WRITE
: MCU_WR_HIT ? 1'b0
: 1'b1;
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
assign ROM_CE = 1'b0;
assign ROM_BHE = ROM_ADDR0;
assign ROM_BLE = !ROM_ADDR0;
assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
cx4_enable ? 1'b0 :
(cx4_active & cx4_vect_enable) ? 1'b0 :
r213f_enable & !SNES_PARD ? 1'b0 :
snoop_4200_enable ? SNES_WRITE :
snescmd_enable ? (~(snescmd_unlock | feat_cmd_unlock) | (SNES_READ & SNES_WRITE)) :
((IS_ROM & SNES_ROMSEL)
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
|(SNES_READ & SNES_WRITE)
);
assign SNES_DATABUS_DIR = (~SNES_READ | (~SNES_PARD & (r213f_enable)))
? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
: 1'b0;
assign SNES_IRQ = 1'b0;
assign p113_out = 1'b0;
snescmd_buf snescmd (
.clka(CLK2), // input clka
.wea(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable)), // input [0 : 0] wea
.addra(SNES_ADDR[8:0]), // input [8 : 0] addra
.dina(SNES_DATA), // input [7 : 0] dina
.douta(snescmd_dout), // output [7 : 0] douta
.clkb(CLK2), // input clkb
.web(snescmd_we_mcu), // input [0 : 0] web
.addrb(snescmd_addr_mcu), // input [8 : 0] addrb
.dinb(snescmd_data_out_mcu), // input [7 : 0] dinb
.doutb(snescmd_data_in_mcu) // output [7 : 0] doutb
);
/*
wire [35:0] CONTROL0;
icon icon (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
ila ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SNES_ADDR), // IN BUS [23:0]
.TRIG1(SNES_DATA), // IN BUS [7:0]
.TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, cx4_active, ROM_WE, ROM_DOUT_ENr, ROM_SA, CX4_RRQ, CX4_RDY, ROM_CA}), // IN BUS [15:0]
.TRIG3(ROM_ADDRr), // IN BUS [23:0]
.TRIG4(CX4_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(CX4_DINr), // IN BUS [7:0]
.TRIG7(STATE) // IN BUS [21:0]
);*/
/*
ila ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SNES_ADDR), // IN BUS [23:0]
.TRIG1(SNES_DATA), // IN BUS [7:0]
.TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
.TRIG3({bsx_data_ovr, SPI_SCK, SPI_MISO, SPI_MOSI, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(spi_byte_cnt[3:0])
);
*/
/*
ila_srtc ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
.TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
.TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
.TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(ST_MEM_DELAYr)
);
*/
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module feedforward_fdiv_32ns_32ns_32_16
#(parameter
ID = 2,
NUM_STAGE = 16,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
feedforward_ap_fdiv_14_no_dsp_32 feedforward_ap_fdiv_14_no_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data AXI3 Slave Converter
// Forward and split transactions as required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_w_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
input wire [4-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Burst length handling.
reg first_mi_word;
reg [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
wire last_beat;
wire last_word;
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal signals for MI-side.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from SI-Side to MI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid;
// Get MI-side data.
assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data forwarding:
//
// On the first cycle of the transaction is the length taken from the Command
// FIFO. The length is decreased until 0 is reached which indicates last data
// word.
//
// If bursts are unsupported will all data words be the last word, each one
// from a separate transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word <= 1'b1;
length_counter_1 <= 4'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word <= 1'b1;
end else begin
first_mi_word <= 1'b0;
end
length_counter_1 <= next_length_counter;
end
end
end
// Detect last beat in a burst.
assign last_beat = ( length_counter == 4'b0 );
// Determine if this last word that shall be extracted from this SI-side word.
assign last_word = ( last_beat ) |
( C_SUPPORT_BURSTS == 0 );
/////////////////////////////////////////////////////////////////////////////
// Select the SI-side word to write.
//
// Most information can be reused directly (DATA, STRB, ID and USER).
// ID is taken from the Command FIFO.
//
// Split transactions needs to insert new LAST transactions. So to simplify
// is the LAST signal always generated.
//
/////////////////////////////////////////////////////////////////////////////
// ID and USER is copied from the SI word to all MI word transactions.
assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}};
// Data has to be multiplexed.
assign M_AXI_WDATA_I = S_AXI_WDATA;
assign M_AXI_WSTRB_I = S_AXI_WSTRB;
// ID is taken directly from the command queue.
assign M_AXI_WID_I = cmd_id;
// Handle last flag, i.e. set for MI-side last word.
assign M_AXI_WLAST_I = last_word;
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign M_AXI_WID = M_AXI_WID_I;
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WUSER = M_AXI_WUSER_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2019.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / General Clock Control Buffer
// /___/ /\ Filename : BUFGCTRL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFGCTRL #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter CE_TYPE_CE0 = "SYNC",
parameter CE_TYPE_CE1 = "SYNC",
parameter integer INIT_OUT = 0,
parameter [0:0] IS_CE0_INVERTED = 1'b0,
parameter [0:0] IS_CE1_INVERTED = 1'b0,
parameter [0:0] IS_I0_INVERTED = 1'b0,
parameter [0:0] IS_I1_INVERTED = 1'b0,
parameter [0:0] IS_IGNORE0_INVERTED = 1'b0,
parameter [0:0] IS_IGNORE1_INVERTED = 1'b0,
parameter [0:0] IS_S0_INVERTED = 1'b0,
parameter [0:0] IS_S1_INVERTED = 1'b0,
parameter PRESELECT_I0 = "FALSE",
parameter PRESELECT_I1 = "FALSE",
parameter SIM_DEVICE = "ULTRASCALE",
parameter STARTUP_SYNC = "FALSE"
)(
output O,
input CE0,
input CE1,
input I0,
input I1,
input IGNORE0,
input IGNORE1,
input S0,
input S1
);
// define constants
localparam MODULE_NAME = "BUFGCTRL";
// Parameter encodings and registers
localparam CE_TYPE_CE0_HARDSYNC = 1;
localparam CE_TYPE_CE0_SYNC = 0;
localparam CE_TYPE_CE1_HARDSYNC = 1;
localparam CE_TYPE_CE1_SYNC = 0;
localparam PRESELECT_I0_FALSE = 0;
localparam PRESELECT_I0_TRUE = 1;
localparam PRESELECT_I1_FALSE = 0;
localparam PRESELECT_I1_TRUE = 1;
localparam SIM_DEVICE_7SERIES = 1;
localparam SIM_DEVICE_ULTRASCALE = 0;
localparam SIM_DEVICE_ULTRASCALE_PLUS = 2;
localparam SIM_DEVICE_VERSAL_AI_CORE = 4;
localparam SIM_DEVICE_VERSAL_AI_CORE_ES1 = 5;
localparam SIM_DEVICE_VERSAL_AI_CORE_ES2 = 6;
localparam SIM_DEVICE_VERSAL_AI_EDGE = 7;
localparam SIM_DEVICE_VERSAL_AI_EDGE_ES1 = 8;
localparam SIM_DEVICE_VERSAL_AI_EDGE_ES2 = 9;
localparam SIM_DEVICE_VERSAL_AI_RF = 10;
localparam SIM_DEVICE_VERSAL_AI_RF_ES1 = 11;
localparam SIM_DEVICE_VERSAL_AI_RF_ES2 = 12;
localparam SIM_DEVICE_VERSAL_HBM = 15;
localparam SIM_DEVICE_VERSAL_HBM_ES1 = 16;
localparam SIM_DEVICE_VERSAL_HBM_ES2 = 17;
localparam SIM_DEVICE_VERSAL_PREMIUM = 18;
localparam SIM_DEVICE_VERSAL_PREMIUM_ES1 = 19;
localparam SIM_DEVICE_VERSAL_PREMIUM_ES2 = 20;
localparam SIM_DEVICE_VERSAL_PRIME = 21;
localparam SIM_DEVICE_VERSAL_PRIME_ES1 = 22;
localparam SIM_DEVICE_VERSAL_PRIME_ES2 = 23;
localparam STARTUP_SYNC_FALSE = 0;
localparam STARTUP_SYNC_TRUE = 1;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "BUFGCTRL_dr.v"
`else
reg [64:1] CE_TYPE_CE0_REG = CE_TYPE_CE0;
reg [64:1] CE_TYPE_CE1_REG = CE_TYPE_CE1;
reg [31:0] INIT_OUT_REG = INIT_OUT;
reg [0:0] IS_CE0_INVERTED_REG = IS_CE0_INVERTED;
reg [0:0] IS_CE1_INVERTED_REG = IS_CE1_INVERTED;
reg [0:0] IS_I0_INVERTED_REG = IS_I0_INVERTED;
reg [0:0] IS_I1_INVERTED_REG = IS_I1_INVERTED;
reg [0:0] IS_IGNORE0_INVERTED_REG = IS_IGNORE0_INVERTED;
reg [0:0] IS_IGNORE1_INVERTED_REG = IS_IGNORE1_INVERTED;
reg [0:0] IS_S0_INVERTED_REG = IS_S0_INVERTED;
reg [0:0] IS_S1_INVERTED_REG = IS_S1_INVERTED;
reg [40:1] PRESELECT_I0_REG = PRESELECT_I0;
reg [40:1] PRESELECT_I1_REG = PRESELECT_I1;
reg [144:1] SIM_DEVICE_REG = SIM_DEVICE;
reg [40:1] STARTUP_SYNC_REG = STARTUP_SYNC;
`endif
`ifdef XIL_XECLIB
wire CE_TYPE_CE0_BIN;
wire CE_TYPE_CE1_BIN;
wire INIT_OUT_BIN;
wire PRESELECT_I0_BIN;
wire PRESELECT_I1_BIN;
wire [4:0] SIM_DEVICE_BIN;
wire STARTUP_SYNC_BIN;
`else
reg CE_TYPE_CE0_BIN;
reg CE_TYPE_CE1_BIN;
reg INIT_OUT_BIN;
reg PRESELECT_I0_BIN;
reg PRESELECT_I1_BIN;
reg [4:0] SIM_DEVICE_BIN;
reg STARTUP_SYNC_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
reg glblGRESTORE = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
tri0 glblGRESTORE = glbl.GRESTORE;
`endif
wire CE0_in;
wire CE1_in;
wire I0_in;
wire I1_in;
wire IGNORE0_in;
wire IGNORE1_in;
wire S0_in;
wire S1_in;
`ifdef XIL_TIMING
wire CE0_delay;
wire CE1_delay;
wire I0_delay;
wire I1_delay;
wire S0_delay;
wire S1_delay;
`endif
`ifdef XIL_TIMING
assign CE0_in = (CE0 !== 1'bz) && (CE0_delay ^ IS_CE0_INVERTED_REG); // rv 0
assign CE1_in = (CE1 !== 1'bz) && (CE1_delay ^ IS_CE1_INVERTED_REG); // rv 0
assign I0_in = I0_delay ^ IS_I0_INVERTED_REG;
assign I1_in = I1_delay ^ IS_I1_INVERTED_REG;
assign S0_in = (S0 !== 1'bz) && (S0_delay ^ IS_S0_INVERTED_REG); // rv 0
assign S1_in = (S1 !== 1'bz) && (S1_delay ^ IS_S1_INVERTED_REG); // rv 0
`else
assign CE0_in = (CE0 !== 1'bz) && (CE0 ^ IS_CE0_INVERTED_REG); // rv 0
assign CE1_in = (CE1 !== 1'bz) && (CE1 ^ IS_CE1_INVERTED_REG); // rv 0
assign I0_in = I0 ^ IS_I0_INVERTED_REG;
assign I1_in = I1 ^ IS_I1_INVERTED_REG;
assign S0_in = (S0 !== 1'bz) && (S0 ^ IS_S0_INVERTED_REG); // rv 0
assign S1_in = (S1 !== 1'bz) && (S1 ^ IS_S1_INVERTED_REG); // rv 0
`endif
assign IGNORE0_in = (IGNORE0 !== 1'bz) && (IGNORE0 ^ IS_IGNORE0_INVERTED_REG); // rv 0
assign IGNORE1_in = (IGNORE1 !== 1'bz) && (IGNORE1 ^ IS_IGNORE1_INVERTED_REG); // rv 0
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign CE_TYPE_CE0_BIN =
(CE_TYPE_CE0_REG == "SYNC") ? CE_TYPE_CE0_SYNC :
(CE_TYPE_CE0_REG == "HARDSYNC") ? CE_TYPE_CE0_HARDSYNC :
CE_TYPE_CE0_SYNC;
assign CE_TYPE_CE1_BIN =
(CE_TYPE_CE1_REG == "SYNC") ? CE_TYPE_CE1_SYNC :
(CE_TYPE_CE1_REG == "HARDSYNC") ? CE_TYPE_CE1_HARDSYNC :
CE_TYPE_CE1_SYNC;
assign INIT_OUT_BIN = INIT_OUT_REG[0];
assign PRESELECT_I0_BIN =
(PRESELECT_I0_REG == "FALSE") ? PRESELECT_I0_FALSE :
(PRESELECT_I0_REG == "TRUE") ? PRESELECT_I0_TRUE :
PRESELECT_I0_FALSE;
assign PRESELECT_I1_BIN =
(PRESELECT_I1_REG == "FALSE") ? PRESELECT_I1_FALSE :
(PRESELECT_I1_REG == "TRUE") ? PRESELECT_I1_TRUE :
PRESELECT_I1_FALSE;
assign SIM_DEVICE_BIN =
(SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE :
(SIM_DEVICE_REG == "7SERIES") ? SIM_DEVICE_7SERIES :
(SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS :
(SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE :
(SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 :
(SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 :
(SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE :
(SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 :
(SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 :
(SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF :
(SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 :
(SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 :
(SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM :
(SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 :
(SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 :
(SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM :
(SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 :
(SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 :
(SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME :
(SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 :
(SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 :
SIM_DEVICE_ULTRASCALE;
assign STARTUP_SYNC_BIN =
(STARTUP_SYNC_REG == "FALSE") ? STARTUP_SYNC_FALSE :
(STARTUP_SYNC_REG == "TRUE") ? STARTUP_SYNC_TRUE :
STARTUP_SYNC_FALSE;
`else
always @ (trig_attr) begin
#1;
CE_TYPE_CE0_BIN =
(CE_TYPE_CE0_REG == "SYNC") ? CE_TYPE_CE0_SYNC :
(CE_TYPE_CE0_REG == "HARDSYNC") ? CE_TYPE_CE0_HARDSYNC :
CE_TYPE_CE0_SYNC;
CE_TYPE_CE1_BIN =
(CE_TYPE_CE1_REG == "SYNC") ? CE_TYPE_CE1_SYNC :
(CE_TYPE_CE1_REG == "HARDSYNC") ? CE_TYPE_CE1_HARDSYNC :
CE_TYPE_CE1_SYNC;
INIT_OUT_BIN = INIT_OUT_REG[0];
PRESELECT_I0_BIN =
(PRESELECT_I0_REG == "FALSE") ? PRESELECT_I0_FALSE :
(PRESELECT_I0_REG == "TRUE") ? PRESELECT_I0_TRUE :
PRESELECT_I0_FALSE;
PRESELECT_I1_BIN =
(PRESELECT_I1_REG == "FALSE") ? PRESELECT_I1_FALSE :
(PRESELECT_I1_REG == "TRUE") ? PRESELECT_I1_TRUE :
PRESELECT_I1_FALSE;
SIM_DEVICE_BIN =
(SIM_DEVICE_REG == "ULTRASCALE") ? SIM_DEVICE_ULTRASCALE :
(SIM_DEVICE_REG == "7SERIES") ? SIM_DEVICE_7SERIES :
(SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS :
(SIM_DEVICE_REG == "VERSAL_AI_CORE") ? SIM_DEVICE_VERSAL_AI_CORE :
(SIM_DEVICE_REG == "VERSAL_AI_CORE_ES1") ? SIM_DEVICE_VERSAL_AI_CORE_ES1 :
(SIM_DEVICE_REG == "VERSAL_AI_CORE_ES2") ? SIM_DEVICE_VERSAL_AI_CORE_ES2 :
(SIM_DEVICE_REG == "VERSAL_AI_EDGE") ? SIM_DEVICE_VERSAL_AI_EDGE :
(SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES1") ? SIM_DEVICE_VERSAL_AI_EDGE_ES1 :
(SIM_DEVICE_REG == "VERSAL_AI_EDGE_ES2") ? SIM_DEVICE_VERSAL_AI_EDGE_ES2 :
(SIM_DEVICE_REG == "VERSAL_AI_RF") ? SIM_DEVICE_VERSAL_AI_RF :
(SIM_DEVICE_REG == "VERSAL_AI_RF_ES1") ? SIM_DEVICE_VERSAL_AI_RF_ES1 :
(SIM_DEVICE_REG == "VERSAL_AI_RF_ES2") ? SIM_DEVICE_VERSAL_AI_RF_ES2 :
(SIM_DEVICE_REG == "VERSAL_HBM") ? SIM_DEVICE_VERSAL_HBM :
(SIM_DEVICE_REG == "VERSAL_HBM_ES1") ? SIM_DEVICE_VERSAL_HBM_ES1 :
(SIM_DEVICE_REG == "VERSAL_HBM_ES2") ? SIM_DEVICE_VERSAL_HBM_ES2 :
(SIM_DEVICE_REG == "VERSAL_PREMIUM") ? SIM_DEVICE_VERSAL_PREMIUM :
(SIM_DEVICE_REG == "VERSAL_PREMIUM_ES1") ? SIM_DEVICE_VERSAL_PREMIUM_ES1 :
(SIM_DEVICE_REG == "VERSAL_PREMIUM_ES2") ? SIM_DEVICE_VERSAL_PREMIUM_ES2 :
(SIM_DEVICE_REG == "VERSAL_PRIME") ? SIM_DEVICE_VERSAL_PRIME :
(SIM_DEVICE_REG == "VERSAL_PRIME_ES1") ? SIM_DEVICE_VERSAL_PRIME_ES1 :
(SIM_DEVICE_REG == "VERSAL_PRIME_ES2") ? SIM_DEVICE_VERSAL_PRIME_ES2 :
SIM_DEVICE_ULTRASCALE;
STARTUP_SYNC_BIN =
(STARTUP_SYNC_REG == "FALSE") ? STARTUP_SYNC_FALSE :
(STARTUP_SYNC_REG == "TRUE") ? STARTUP_SYNC_TRUE :
STARTUP_SYNC_FALSE;
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((CE_TYPE_CE0_REG != "SYNC") &&
(CE_TYPE_CE0_REG != "HARDSYNC"))) begin
$display("Error: [Unisim %s-101] CE_TYPE_CE0 attribute is set to %s. Legal values for this attribute are SYNC or HARDSYNC. Instance: %m", MODULE_NAME, CE_TYPE_CE0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CE_TYPE_CE1_REG != "SYNC") &&
(CE_TYPE_CE1_REG != "HARDSYNC"))) begin
$display("Error: [Unisim %s-102] CE_TYPE_CE1 attribute is set to %s. Legal values for this attribute are SYNC or HARDSYNC. Instance: %m", MODULE_NAME, CE_TYPE_CE1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INIT_OUT_REG != 0) &&
(INIT_OUT_REG != 1))) begin
$display("Error: [Unisim %s-104] INIT_OUT attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, INIT_OUT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PRESELECT_I0_REG != "FALSE") &&
(PRESELECT_I0_REG != "TRUE"))) begin
$display("Error: [Unisim %s-113] PRESELECT_I0 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PRESELECT_I0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PRESELECT_I1_REG != "FALSE") &&
(PRESELECT_I1_REG != "TRUE"))) begin
$display("Error: [Unisim %s-114] PRESELECT_I1 attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PRESELECT_I1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "ULTRASCALE") &&
(SIM_DEVICE_REG != "7SERIES") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "VERSAL_AI_CORE") &&
(SIM_DEVICE_REG != "VERSAL_AI_CORE_ES1") &&
(SIM_DEVICE_REG != "VERSAL_AI_CORE_ES2") &&
(SIM_DEVICE_REG != "VERSAL_AI_EDGE") &&
(SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES1") &&
(SIM_DEVICE_REG != "VERSAL_AI_EDGE_ES2") &&
(SIM_DEVICE_REG != "VERSAL_AI_RF") &&
(SIM_DEVICE_REG != "VERSAL_AI_RF_ES1") &&
(SIM_DEVICE_REG != "VERSAL_AI_RF_ES2") &&
(SIM_DEVICE_REG != "VERSAL_HBM") &&
(SIM_DEVICE_REG != "VERSAL_HBM_ES1") &&
(SIM_DEVICE_REG != "VERSAL_HBM_ES2") &&
(SIM_DEVICE_REG != "VERSAL_PREMIUM") &&
(SIM_DEVICE_REG != "VERSAL_PREMIUM_ES1") &&
(SIM_DEVICE_REG != "VERSAL_PREMIUM_ES2") &&
(SIM_DEVICE_REG != "VERSAL_PRIME") &&
(SIM_DEVICE_REG != "VERSAL_PRIME_ES1") &&
(SIM_DEVICE_REG != "VERSAL_PRIME_ES2"))) begin
$display("Error: [Unisim %s-115] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE, 7SERIES, ULTRASCALE_PLUS, VERSAL_AI_CORE, VERSAL_AI_CORE_ES1, VERSAL_AI_CORE_ES2, VERSAL_AI_EDGE, VERSAL_AI_EDGE_ES1, VERSAL_AI_EDGE_ES2, VERSAL_AI_RF, VERSAL_AI_RF_ES1, VERSAL_AI_RF_ES2, VERSAL_HBM, VERSAL_HBM_ES1, VERSAL_HBM_ES2, VERSAL_PREMIUM, VERSAL_PREMIUM_ES1, VERSAL_PREMIUM_ES2, VERSAL_PRIME, VERSAL_PRIME_ES1 or VERSAL_PRIME_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((STARTUP_SYNC_REG != "FALSE") &&
(STARTUP_SYNC_REG != "TRUE"))) begin
$display("Error: [Unisim %s-116] STARTUP_SYNC attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, STARTUP_SYNC_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
reg O_out;
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
// *** both preselects can not be 1 simultaneously.
if ((PRESELECT_I0_REG == "TRUE") && (PRESELECT_I1_REG == "TRUE")) begin
$display("Error : [Unisim %s-1] The attributes PRESELECT_I0 and PRESELECT_I1 should not be set to TRUE simultaneously. Instance: %m", MODULE_NAME);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
always @ (trig_attr) begin
#1;
if (((SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES1 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES2 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES1 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES2 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES1 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES2 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES1 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES2 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES1 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES2 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES1 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES2 )) &&
(STARTUP_SYNC_BIN == STARTUP_SYNC_TRUE)) begin
$display("Warning: [Unisim %s-200] SIM_DEVICE attribute is set to %s and STARTUP_SYNC is set to %s. STARTUP_SYNC functionality is not supported for this DEVICE. Instance: %m", MODULE_NAME, SIM_DEVICE_REG, STARTUP_SYNC_REG);
STARTUP_SYNC_BIN = STARTUP_SYNC_FALSE; //force correct
end
if (((SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES1 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_CORE_ES2 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES1 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_EDGE_ES2 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES1 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_AI_RF_ES2 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES1 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_HBM_ES2 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES1 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PREMIUM_ES2 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES1 ) &&
(SIM_DEVICE_BIN != SIM_DEVICE_VERSAL_PRIME_ES2 )) &&
(CE_TYPE_CE0_BIN == CE_TYPE_CE0_HARDSYNC || CE_TYPE_CE1_BIN==CE_TYPE_CE1_HARDSYNC)) begin
$display("Warning: [Unisim %s-201] SIM_DEVICE attribute is set to %s; CE_TYPE_CE0 is set to %s and CE_TYPE_CE1 is set to %s. HARDSYNC functionality is not supported for this DEVICE. Instance: %m", MODULE_NAME, SIM_DEVICE_REG, CE_TYPE_CE0_REG, CE_TYPE_CE1_REG);
CE_TYPE_CE0_BIN = CE_TYPE_CE0_SYNC; //force correct
CE_TYPE_CE1_BIN = CE_TYPE_CE1_SYNC;
end
end //always
`endif
reg [2:0] gwe0_sync;
reg [2:0] gwe1_sync;
wire gwe_sync;
wire gwe;
wire gwe_muxed_sync;
reg [2:0] CE0_sync;
reg [2:0] CE1_sync;
wire ce0_muxed_sync;
wire ce1_muxed_sync;
reg CE0_in_dly;
reg CE1_in_dly;
wire I0_optinv;
wire I1_optinv;
wire d00;
wire d01;
wire d10;
wire d11;
reg qb00;
reg qb01;
reg qb10;
reg qb11;
wire cb00;
wire cb01;
wire cb10;
wire cb11;
reg state0;
reg state1;
initial begin
CE0_sync = 3'b000;
CE1_sync = 3'b000;
gwe0_sync = 3'b000;
gwe1_sync = 3'b000;
O_out = 1'b0;
#2;
qb00 = (PRESELECT_I0_BIN==PRESELECT_I0_TRUE)? 1'b1:1'b0;
qb01 = (PRESELECT_I0_BIN==PRESELECT_I0_TRUE)? 1'b1:1'b0;
qb10 = (PRESELECT_I1_BIN==PRESELECT_I1_TRUE)? 1'b1:1'b0;
qb11 = (PRESELECT_I1_BIN==PRESELECT_I1_TRUE)? 1'b1:1'b0;
//don't put anything after here
end
assign gwe = ~glblGSR;
assign I0_optinv = INIT_OUT_BIN ^ I0_in;
assign I1_optinv = INIT_OUT_BIN ^ I1_in;
always @ (negedge I0_optinv or posedge glblGRESTORE) begin
if(glblGRESTORE)
gwe0_sync <= 3'd0;
else
gwe0_sync <= {gwe0_sync[1:0], gwe};
end
always @ (negedge I1_optinv or posedge glblGRESTORE) begin
if(glblGRESTORE)
gwe1_sync <= 3'd0;
else
gwe1_sync <= {gwe1_sync[1:0], gwe};
end
assign gwe_sync = ((PRESELECT_I0_BIN==PRESELECT_I0_TRUE ) ? gwe0_sync[2] :
(PRESELECT_I1_BIN==PRESELECT_I1_TRUE ) ? gwe1_sync[2] :
(gwe0_sync[2] | gwe1_sync[2]));
assign gwe_muxed_sync = (STARTUP_SYNC_BIN==STARTUP_SYNC_TRUE) ? gwe_sync : gwe;
always @(*) CE0_in_dly = #1 CE0_in;
always @(*) CE1_in_dly = #1 CE1_in;
always @ (posedge I0_optinv or posedge glblGRESTORE)
if(glblGRESTORE)
CE0_sync <= 3'd0;
else
CE0_sync <= {CE0_sync[1:0], CE0_in_dly};
always @ (posedge I1_optinv or posedge glblGRESTORE)
if(glblGRESTORE)
CE1_sync <= 3'd0;
else
CE1_sync <= {CE1_sync[1:0], CE1_in_dly};
assign ce0_muxed_sync = (CE_TYPE_CE0_BIN==CE_TYPE_CE0_HARDSYNC) ? CE0_sync[2] : CE0_in;
assign ce1_muxed_sync = (CE_TYPE_CE1_BIN==CE_TYPE_CE1_HARDSYNC) ? CE1_sync[2] : CE1_in;
assign d00 = ~(state1 & S0_in);
assign d01 = ~(qb00 & ce0_muxed_sync);
assign d10 = ~(state0 & S1_in);
assign d11 = ~(qb10 & ce1_muxed_sync);
assign cb00 = ~( (~gwe_muxed_sync) | (~IGNORE0_in) & (~I0_optinv) );
assign cb01 = ~( (~gwe_muxed_sync) | (~IGNORE0_in) & ( I0_optinv) );
assign cb10 = ~( (~gwe_muxed_sync) | (~IGNORE1_in) & (~I1_optinv) );
assign cb11 = ~( (~gwe_muxed_sync) | (~IGNORE1_in) & ( I1_optinv) );
always@(*) begin
if (glblGRESTORE && ~PRESELECT_I0_BIN)
qb00 <= 1'b0;
else if (glblGRESTORE && PRESELECT_I0_BIN)
qb00 <= 1'b1;
else if(cb00)
qb00 <= #1 ~d00;
end
always@(*) begin
if (glblGRESTORE && ~PRESELECT_I0_BIN)
qb01 <= 1'b0;
else if (glblGRESTORE && PRESELECT_I0_BIN)
qb01 <= 1'b1;
else if(cb01)
qb01 <= #1 ~d01;
end
always @(*) begin
if (glblGRESTORE && ~PRESELECT_I1_BIN)
qb10 <= 1'b0;
else if (glblGRESTORE && PRESELECT_I1_BIN)
qb10 <= 1'b1;
else if(cb10)
qb10 <= #1 ~d10;
end
always@(*) begin
if (glblGRESTORE && ~PRESELECT_I1_BIN)
qb11 <= 1'b0;
else if (glblGRESTORE && PRESELECT_I1_BIN)
qb11 <= 1'b1;
else if(cb11)
qb11 <= #1 ~d11;
end
always@(*) begin
state0 = ~(qb01|(~gwe_muxed_sync));
state1 = ~(qb11|(~gwe_muxed_sync));
end
always @(*) begin
case ({state1,state0})
2'b00 : O_out = 1'b0;
2'b01 : O_out = I1_in;
2'b10 : O_out = I0_in;
2'b11 : O_out = INIT_OUT_BIN;
default : O_out = 1'bx;
endcase
end
assign O = O_out;
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
wire i0_en_n;
wire i0_en_p;
wire i1_en_n;
wire i1_en_p;
assign i0_en_n = IS_I0_INVERTED_REG;
assign i0_en_p = ~IS_I0_INVERTED_REG;
assign i1_en_n = IS_I1_INVERTED_REG;
assign i1_en_p = ~IS_I1_INVERTED_REG;
`endif
// I0/I1 are clocks but do not clock anything in this model. do not need the 100 ps.
// specify absorbs a potential glitch in functional simuation when S0/S1 switch
// that needs to remain to match rtl.
// IO paths are combinatorial through muxes and not registers
`ifdef XIL_TIMING
specify
(CE0 => O) = (0:0:0, 0:0:0);
(CE1 => O) = (0:0:0, 0:0:0);
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
$period (negedge I0, 0:0:0, notifier);
$period (negedge I1, 0:0:0, notifier);
$period (posedge I0, 0:0:0, notifier);
$period (posedge I1, 0:0:0, notifier);
$setuphold (negedge I0, negedge CE0, 0:0:0, 0:0:0, notifier,i0_en_n,i0_en_n, I0_delay, CE0_delay);
$setuphold (negedge I0, negedge S0, 0:0:0, 0:0:0, notifier,i0_en_n,i0_en_n, I0_delay, S0_delay);
$setuphold (negedge I0, posedge CE0, 0:0:0, 0:0:0, notifier,i0_en_n,i0_en_n, I0_delay, CE0_delay);
$setuphold (negedge I0, posedge S0, 0:0:0, 0:0:0, notifier,i0_en_n,i0_en_n, I0_delay, S0_delay);
$setuphold (negedge I1, negedge CE1, 0:0:0, 0:0:0, notifier,i1_en_n,i1_en_n, I1_delay, CE1_delay);
$setuphold (negedge I1, negedge S1, 0:0:0, 0:0:0, notifier,i1_en_n,i1_en_n, I1_delay, S1_delay);
$setuphold (negedge I1, posedge CE1, 0:0:0, 0:0:0, notifier,i1_en_n,i1_en_n, I1_delay, CE1_delay);
$setuphold (negedge I1, posedge S1, 0:0:0, 0:0:0, notifier,i1_en_n,i1_en_n, I1_delay, S1_delay);
$setuphold (posedge I0, negedge CE0, 0:0:0, 0:0:0, notifier,i0_en_p,i0_en_p, I0_delay, CE0_delay);
$setuphold (posedge I0, negedge S0, 0:0:0, 0:0:0, notifier,i0_en_p,i0_en_p, I0_delay, S0_delay);
$setuphold (posedge I0, posedge CE0, 0:0:0, 0:0:0, notifier,i0_en_p,i0_en_p, I0_delay, CE0_delay);
$setuphold (posedge I0, posedge S0, 0:0:0, 0:0:0, notifier,i0_en_p,i0_en_p, I0_delay, S0_delay);
$setuphold (posedge I1, negedge CE1, 0:0:0, 0:0:0, notifier,i1_en_p,i1_en_p, I1_delay, CE1_delay);
$setuphold (posedge I1, negedge S1, 0:0:0, 0:0:0, notifier,i1_en_p,i1_en_p, I1_delay, S1_delay);
$setuphold (posedge I1, posedge CE1, 0:0:0, 0:0:0, notifier,i1_en_p,i1_en_p, I1_delay, CE1_delay);
$setuphold (posedge I1, posedge S1, 0:0:0, 0:0:0, notifier,i1_en_p,i1_en_p, I1_delay, S1_delay);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
endmodule
`endcelldefine
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Create tags for the non-posted packet generators.
// Uses a simple 5-bit counter which rolls over
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module tag_generator(
input clk,
input rst,
output reg np_tag_gnt,
input np_tag_inc,
output [7:0] tag_value,
input [31:0] completion_pending);
reg rst_reg;
reg [4:0] tag_value_i;
always@(posedge clk) rst_reg <= rst;
//check to see if the tag is already in use
//assert the grant signal if it is not
always@(posedge clk)begin
if(completion_pending[tag_value_i[4:0]])
np_tag_gnt <= 1'b0;
else
np_tag_gnt <= 1'b1;
end
assign tag_value[7:0] = {3'b000,tag_value_i[4:0]};
//tag generator is simply a counter with enable
always@(posedge clk)begin
if(rst_reg)begin
tag_value_i[4:0] <= 5'b00000;
end else if(np_tag_inc)begin
tag_value_i <= tag_value_i + 1;
end
end
endmodule
|
// Spartan 3A DSP and Spartan 6 block RAM mapping (Spartan 6 is a superset of
// Spartan 3A DSP).
module \$__XILINX_RAMB8BWER_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [9215:0] INIT = 9216'bx;
input CLK2;
input CLK3;
input [7:0] A1ADDR;
output [35:0] A1DATA;
input A1EN;
input [7:0] B1ADDR;
input [35:0] B1DATA;
input [3:0] B1EN;
wire [12:0] A1ADDR_13 = {A1ADDR, 5'b0};
wire [12:0] B1ADDR_13 = {B1ADDR, 5'b0};
wire [3:0] DIP, DOP;
wire [31:0] DI, DO;
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
RAMB8BWER #(
.RAM_MODE("SDP"),
.DATA_WIDTH_A(36),
.DATA_WIDTH_B(36),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
`include "brams_init_9.vh"
) _TECHMAP_REPLACE_ (
.DOBDO(DO[31:16]),
.DOADO(DO[15:0]),
.DOPBDOP(DOP[3:2]),
.DOPADOP(DOP[1:0]),
.DIBDI(DI[31:16]),
.DIADI(DI[15:0]),
.DIPBDIP(DIP[3:2]),
.DIPADIP(DIP[1:0]),
.WEBWEU(B1EN[3:2]),
.WEAWEL(B1EN[1:0]),
.ADDRAWRADDR(B1ADDR_13),
.CLKAWRCLK(CLK3 ^ !CLKPOL3),
.ENAWREN(|1),
.REGCEA(|0),
.RSTA(|0),
.ADDRBRDADDR(A1ADDR_13),
.CLKBRDCLK(CLK2 ^ !CLKPOL2),
.ENBRDEN(A1EN),
.REGCEBREGCE(|1),
.RSTBRST(|0)
);
endmodule
// ------------------------------------------------------------------------
module \$__XILINX_RAMB16BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 36;
parameter CFG_ENABLE_B = 4;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [18431:0] INIT = 18432'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS);
wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS);
wire [3:0] B1EN_4 = {4{B1EN}};
wire [3:0] DIP, DOP;
wire [31:0] DI, DO;
wire [31:0] DOB;
wire [3:0] DOPB;
assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
generate if (CFG_DBITS > 8) begin
RAMB16BWER #(
.DATA_WIDTH_A(CFG_DBITS),
.DATA_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
`include "brams_init_18.vh"
) _TECHMAP_REPLACE_ (
.DIA(32'd0),
.DIPA(4'd0),
.DOA(DO[31:0]),
.DOPA(DOP[3:0]),
.ADDRA(A1ADDR_14),
.CLKA(CLK2 ^ !CLKPOL2),
.ENA(A1EN),
.REGCEA(|1),
.RSTA(|0),
.WEA(4'b0),
.DIB(DI),
.DIPB(DIP),
.DOB(DOB),
.DOPB(DOPB),
.ADDRB(B1ADDR_14),
.CLKB(CLK3 ^ !CLKPOL3),
.ENB(|1),
.REGCEB(|0),
.RSTB(|0),
.WEB(B1EN_4)
);
end else begin
RAMB16BWER #(
.DATA_WIDTH_A(CFG_DBITS),
.DATA_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
`include "brams_init_16.vh"
) _TECHMAP_REPLACE_ (
.DIA(32'd0),
.DIPA(4'd0),
.DOA(DO[31:0]),
.DOPA(DOP[3:0]),
.ADDRA(A1ADDR_14),
.CLKA(CLK2 ^ !CLKPOL2),
.ENA(A1EN),
.REGCEA(|1),
.RSTA(|0),
.WEA(4'b0),
.DIB(DI),
.DIPB(DIP),
.DOB(DOB),
.DOPB(DOPB),
.ADDRB(B1ADDR_14),
.CLKB(CLK3 ^ !CLKPOL3),
.ENB(|1),
.REGCEB(|0),
.RSTB(|0),
.WEB(B1EN_4)
);
end endgenerate
endmodule
// ------------------------------------------------------------------------
module \$__XILINX_RAMB8BWER_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 18;
parameter CFG_ENABLE_B = 2;
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
parameter [9215:0] INIT = 9216'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input [CFG_ENABLE_B-1:0] B1EN;
wire [12:0] A1ADDR_13 = A1ADDR << (13 - CFG_ABITS);
wire [12:0] B1ADDR_13 = B1ADDR << (13 - CFG_ABITS);
wire [1:0] B1EN_2 = {2{B1EN}};
wire [1:0] DIP, DOP;
wire [15:0] DI, DO;
wire [15:0] DOBDO;
wire [1:0] DOPBDOP;
assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
generate if (CFG_DBITS > 8) begin
RAMB8BWER #(
.RAM_MODE("TDP"),
.DATA_WIDTH_A(CFG_DBITS),
.DATA_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
`include "brams_init_9.vh"
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
.DOADO(DO),
.DOPADOP(DOP),
.ADDRAWRADDR(A1ADDR_13),
.CLKAWRCLK(CLK2 ^ !CLKPOL2),
.ENAWREN(A1EN),
.REGCEA(|1),
.RSTA(|0),
.WEAWEL(2'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
.ADDRBRDADDR(B1ADDR_13),
.CLKBRDCLK(CLK3 ^ !CLKPOL3),
.ENBRDEN(|1),
.REGCEBREGCE(|0),
.RSTBRST(|0),
.WEBWEU(B1EN_2)
);
end else begin
RAMB8BWER #(
.RAM_MODE("TDP"),
.DATA_WIDTH_A(CFG_DBITS),
.DATA_WIDTH_B(CFG_DBITS),
.WRITE_MODE_A("READ_FIRST"),
.WRITE_MODE_B("READ_FIRST"),
`include "brams_init_8.vh"
) _TECHMAP_REPLACE_ (
.DIADI(16'b0),
.DIPADIP(2'b0),
.DOADO(DO),
.DOPADOP(DOP),
.ADDRAWRADDR(A1ADDR_13),
.CLKAWRCLK(CLK2 ^ !CLKPOL2),
.ENAWREN(A1EN),
.REGCEA(|1),
.RSTA(|0),
.WEAWEL(2'b0),
.DIBDI(DI),
.DIPBDIP(DIP),
.DOBDO(DOBDO),
.DOPBDOP(DOPBDOP),
.ADDRBRDADDR(B1ADDR_13),
.CLKBRDCLK(CLK3 ^ !CLKPOL3),
.ENBRDEN(|1),
.REGCEBREGCE(|0),
.RSTBRST(|0),
.WEBWEU(B1EN_2)
);
end endgenerate
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always fork : id parallel_statements join
module main ;
reg [3:0] value1,value2,value3;
always fork : fork_id
#5 value1 = 1 ;
#10 value1 = 2;
join
initial
begin
value1 = 0;
value2 = 0;
#4 ;
if(value1 != 0)
begin
$display("FAILED - 3.1.12B always fork : id statements join (0)");
value2 = 1;
end
#2 ;
if(value1 != 1)
begin
$display("FAILED - 3.1.12B always fork : id statements join (1)");
value2 = 1;
end
#5 ;
if(value1 != 2)
begin
$display("FAILED - 3.1.12B always fork : id statements join (2)");
value2 = 1;
end
#5 ;
if(value1 != 1)
begin
$display("FAILED - 3.1.12B always fork : id statements join (3)");
value2 = 1;
end
if(value2 == 0) $display("PASSED");
$finish ;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_9_b2s_wrap_cmd.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s_wrap_cmd #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
input wire [C_AXI_ADDR_WIDTH-1:0] axaddr ,
input wire [7:0] axlen ,
input wire [2:0] axsize ,
// axhandshake = axvalid & axready
input wire axhandshake ,
output wire [C_AXI_ADDR_WIDTH-1:0] cmd_byte_addr ,
// Connections to/from fsm module
// signal to increment to the next mc transaction
input wire next ,
// signal to the fsm there is another transaction required
output reg next_pending
);
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
reg sel_first;
wire [11:0] axaddr_i;
wire [3:0] axlen_i;
reg [11:0] wrap_boundary_axaddr;
reg [3:0] axaddr_offset;
reg [3:0] wrap_second_len;
reg [11:0] wrap_boundary_axaddr_r;
reg [3:0] axaddr_offset_r;
reg [3:0] wrap_second_len_r;
reg [4:0] axlen_cnt;
reg [4:0] wrap_cnt_r;
wire [4:0] wrap_cnt;
reg [11:0] axaddr_wrap;
reg next_pending_r;
localparam L_AXI_ADDR_LOW_BIT = (C_AXI_ADDR_WIDTH >= 12) ? 12 : 11;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_ADDR_WIDTH > 12) begin : ADDR_GT_4K
assign cmd_byte_addr = (sel_first) ? axaddr : {axaddr[C_AXI_ADDR_WIDTH-1:L_AXI_ADDR_LOW_BIT],axaddr_wrap[11:0]};
end else begin : ADDR_4K
assign cmd_byte_addr = (sel_first) ? axaddr : axaddr_wrap[11:0];
end
endgenerate
assign axaddr_i = axaddr[11:0];
assign axlen_i = axlen[3:0];
// Mask bits based on transaction length to get wrap boundary low address
// Offset used to calculate the length of each transaction
always @( * ) begin
if(axhandshake) begin
wrap_boundary_axaddr = axaddr_i & ~(axlen_i << axsize[1:0]);
axaddr_offset = axaddr_i[axsize[1:0] +: 4] & axlen_i;
end else begin
wrap_boundary_axaddr = wrap_boundary_axaddr_r;
axaddr_offset = axaddr_offset_r;
end
end
// case (axsize[1:0])
// 2'b00 : axaddr_offset = axaddr_i[4:0] & axlen_i;
// 2'b01 : axaddr_offset = axaddr_i[5:1] & axlen_i;
// 2'b10 : axaddr_offset = axaddr_i[6:2] & axlen_i;
// 2'b11 : axaddr_offset = axaddr_i[7:3] & axlen_i;
// default : axaddr_offset = axaddr_i[7:3] & axlen_i;
// endcase
// The first and the second command from the wrap transaction could
// be of odd length or even length with address offset. This will be
// an issue with BL8, extra transactions have to be issued.
// Rounding up the length to account for extra transactions.
always @( * ) begin
if(axhandshake) begin
wrap_second_len = (axaddr_offset >0) ? axaddr_offset - 1 : 0;
end else begin
wrap_second_len = wrap_second_len_r;
end
end
// registering to be used in the combo logic.
always @(posedge clk) begin
wrap_boundary_axaddr_r <= wrap_boundary_axaddr;
axaddr_offset_r <= axaddr_offset;
wrap_second_len_r <= wrap_second_len;
end
// determining if extra data is required for even offsets
// wrap_cnt used to switch the address for first and second transaction.
assign wrap_cnt = {1'b0, wrap_second_len + {3'b000, (|axaddr_offset)}};
always @(posedge clk)
wrap_cnt_r <= wrap_cnt;
always @(posedge clk) begin
if (axhandshake) begin
axaddr_wrap <= axaddr[11:0];
end if(next)begin
if(axlen_cnt == wrap_cnt_r) begin
axaddr_wrap <= wrap_boundary_axaddr_r;
end else begin
axaddr_wrap <= axaddr_wrap + (1 << axsize[1:0]);
end
end
end
// Even numbber of transactions with offset, inc len by 2 for BL8
always @(posedge clk) begin
if (axhandshake)begin
axlen_cnt <= axlen_i;
next_pending_r <= axlen_i >= 1;
end else if (next) begin
if (axlen_cnt > 1) begin
axlen_cnt <= axlen_cnt - 1;
next_pending_r <= (axlen_cnt - 1) >= 1;
end else begin
axlen_cnt <= 5'd0;
next_pending_r <= 1'b0;
end
end
end
always @( * ) begin
if (axhandshake)begin
next_pending = axlen_i >= 1;
end else if (next) begin
if (axlen_cnt > 1) begin
next_pending = (axlen_cnt - 1) >= 1;
end else begin
next_pending = 1'b0;
end
end else begin
next_pending = next_pending_r;
end
end
// last and ignore signals to data channel. These signals are used for
// BL8 to ignore and insert data for even len transactions with offset
// and odd len transactions
// For odd len transactions with no offset the last read is ignored and
// last write is masked
// For odd len transactions with offset the first read is ignored and
// first write is masked
// For even len transactions with offset the last & first read is ignored and
// last& first write is masked
// For even len transactions no ingnores or masks.
// Indicates if we are on the first transaction of a mc translation with more
// than 1 transaction.
always @(posedge clk) begin
if (reset | axhandshake) begin
sel_first <= 1'b1;
end else if (next) begin
sel_first <= 1'b0;
end
end
endmodule
`default_nettype wire
|
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
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// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
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// (individually and collectively, "Critical
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.6
// \ \ Application : MIG
// / / Filename : memc_ui_top_std.v
// /___/ /\ Date Last Modified : $Date: 2011/06/17 11:11:25 $
// \ \ / \ Date Created : Fri Oct 08 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM & DDR3 SDRAM
// Purpose :
// Top level memory interface block. Instantiates a clock and
// reset generator, the memory controller, the phy and the
// user interface blocks.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
(* X_CORE_INFO = "mig_7series_v2_3_ddr3_7Series, 2013.4" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v2_3,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Vivado, LEVEL=CONTROLLER, AXI_ENABLE=0, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, AXI_ENABLE=0, CLK_PERIOD=1250, PHY_RATIO=4, CLKIN_PERIOD=5000, VCCAUX_IO=2.0V, MEMORY_TYPE=SODIMM, MEMORY_PART=mt8ktf51264hz-1g6, DQ_WIDTH=64, ECC=OFF, DATA_MASK=1, ORDERING=NORM, BURST_MODE=8, BURST_TYPE=SEQ, CA_MIRROR=OFF, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=40, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=0, SYSCLK_TYPE=DIFFERENTIAL, REFCLK_TYPE=USE_SYSTEM_CLOCK}" *)
module mig_7series_v2_3_memc_ui_top_std #
(
parameter TCQ = 100,
parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter ECC_TEST = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ORDERING = "NORM",
parameter IBUF_LPWR_MODE = "OFF",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP0 = "IODELAY_MIG0",
parameter IODELAY_GRP1 = "IODELAY_MIG1",
parameter FPGA_SPEED_GRADE = 1,
parameter OUTPUT_DRV = "HIGH",
parameter REG_CTRL = "OFF",
parameter RTT_NOM = "60",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tCKE = 10000, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter USER_REFRESH = "OFF", // Whether user manages REF
parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon
parameter WRLVL = "OFF",
parameter DEBUG_PORT = "OFF",
parameter CAL_WIDTH = "HALF",
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter ADDR_WIDTH = 32,
parameter APP_MASK_WIDTH = 8,
parameter APP_DATA_WIDTH = 64,
parameter [3:0] BYTE_LANES_B0 = 4'b1111,
parameter [3:0] BYTE_LANES_B1 = 4'b1111,
parameter [3:0] BYTE_LANES_B2 = 4'b1111,
parameter [3:0] BYTE_LANES_B3 = 4'b1111,
parameter [3:0] BYTE_LANES_B4 = 4'b1111,
parameter [3:0] DATA_CTL_B0 = 4'hc,
parameter [3:0] DATA_CTL_B1 = 4'hf,
parameter [3:0] DATA_CTL_B2 = 4'hf,
parameter [3:0] DATA_CTL_B3 = 4'h0,
parameter [3:0] DATA_CTL_B4 = 4'h0,
parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter [143:0] CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [191:0] ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter [35:0] BANK_MAP = 36'h000_000_000,
parameter [11:0] CAS_MAP = 12'h000,
parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00,
parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter [11:0] PARITY_MAP = 12'h000,
parameter [11:0] RAS_MAP = 12'h000,
parameter [11:0] WE_MAP = 12'h000,
parameter [143:0] DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address
parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address
parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change
parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl
parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation
parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering
parameter TAPSPERKCLK = 56
)
(
// Clock and reset ports
input clk,
input [1:0] clk_ref,
input mem_refclk ,
input freq_refclk ,
input pll_lock,
input sync_pulse ,
input mmcm_ps_clk,
input poc_sample_pd,
input rst,
// memory interface ports
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
// user interface ports
input [ADDR_WIDTH-1:0] app_addr,
input [2:0] app_cmd,
input app_en,
input app_hi_pri,
input [APP_DATA_WIDTH-1:0] app_wdf_data,
input app_wdf_end,
input [APP_MASK_WIDTH-1:0] app_wdf_mask,
input app_wdf_wren,
input app_correct_en_i,
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc,
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err,
output [APP_DATA_WIDTH-1:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
input app_sr_req,
output app_sr_active,
input app_ref_req,
output app_ref_ack,
input app_zq_req,
output app_zq_ack,
// temperature monitor ports
input [11:0] device_temp,
//phase shift clock control
output psen,
output psincdec,
input psdone,
// debug logic ports
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
output init_calib_complete,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output dbg_rddata_valid,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output ref_dll_lock,
input rst_phaser_ref,
input iddr_rst,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_calib_top,
output [255:0] dbg_phy_wrlvl,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_1,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_2,
output [5:0] dbg_data_offset,
output [5:0] dbg_data_offset_1,
output [5:0] dbg_data_offset_2,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_final_dqs_tap_cnt_r,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps
);
localparam IODELAY_GRP = (tCK <= 1500)? IODELAY_GRP1 : IODELAY_GRP0;
// wire [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;
wire correct_en;
wire [2*nCK_PER_CLK-1:0] raw_not_ecc;
wire [2*nCK_PER_CLK-1:0] ecc_single;
wire [2*nCK_PER_CLK-1:0] ecc_multiple;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
wire [DQ_WIDTH/8-1:0] fi_xor_we;
wire [DQ_WIDTH-1:0] fi_xor_wrdata;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
wire wr_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire rd_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
wire accept;
wire accept_ns;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
wire rd_data_end;
wire use_addr;
wire size;
wire [ROW_WIDTH-1:0] row;
wire [RANK_WIDTH-1:0] rank;
wire hi_priority;
wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
wire [COL_WIDTH-1:0] col;
wire [2:0] cmd;
wire [BANK_WIDTH-1:0] bank;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask;
wire app_sr_req_i;
wire app_sr_active_i;
wire app_ref_req_i;
wire app_ref_ack_i;
wire app_zq_req_i;
wire app_zq_ack_i;
wire rst_tg_mc;
wire error;
wire init_wrcal_complete;
reg reset /* synthesis syn_maxfan = 10 */;
//***************************************************************************
always @(posedge clk)
reset <= #TCQ (rst | rst_tg_mc);
assign fi_xor_we = {DQ_WIDTH/8{1'b0}} ;
assign fi_xor_wrdata = {DQ_WIDTH{1'b0}} ;
mig_7series_v2_3_mem_intfc #
(
.TCQ (TCQ),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CA_MIRROR (CA_MIRROR),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.TAPSPERKCLK (TAPSPERKCLK)
)
mem_intfc0
(
.clk (clk),
.clk_ref (tCK <= 1500 ? clk_ref[1] : clk_ref[0]),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.rst (rst),
.error (error),
.reset (reset),
.rst_tg_mc (rst_tg_mc),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs (ddr_dqs),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck (ddr_ck),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_we_n (ddr_we_n),
.slot_0_present (SLOT_0_CONFIG),
.slot_1_present (SLOT_1_CONFIG),
.correct_en (correct_en),
.bank (bank),
.cmd (cmd),
.col (col),
.data_buf_addr (data_buf_addr),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.rank (rank),
.raw_not_ecc (raw_not_ecc),
.row (row),
.hi_priority (hi_priority),
.size (size),
.use_addr (use_addr),
.accept (accept),
.accept_ns (accept_ns),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.bank_mach_next (bank_mach_next),
.init_calib_complete (init_calib_complete),
.init_wrcal_complete (init_wrcal_complete),
.app_sr_req (app_sr_req_i),
.app_sr_active (app_sr_active_i),
.app_ref_req (app_ref_req_i),
.app_ref_ack (app_ref_ack_i),
.app_zq_req (app_zq_req_i),
.app_zq_ack (app_zq_ack_i),
.device_temp (device_temp),
.psen (psen),
.psincdec (psincdec),
.psdone (psdone),
.fi_xor_we (fi_xor_we),
.fi_xor_wrdata (fi_xor_wrdata),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.iddr_rst (iddr_rst),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps)
);
mig_7series_v2_3_ui_top #
(
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER)
)
u_ui_top
(
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.use_addr (use_addr),
.size (size),
.row (row),
.raw_not_ecc (raw_not_ecc),
.rank (rank),
.hi_priority (hi_priority),
.data_buf_addr (data_buf_addr),
.col (col),
.cmd (cmd),
.bank (bank),
.app_wdf_rdy (app_wdf_rdy),
.app_rdy (app_rdy),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data),
.app_ecc_multiple_err (app_ecc_multiple_err),
.correct_en (correct_en),
.wr_data_offset (wr_data_offset),
.wr_data_en (wr_data_en),
.wr_data_addr (wr_data_addr),
.rst (reset),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.clk (clk),
.app_wdf_wren (app_wdf_wren),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_wdf_data (app_wdf_data),
.app_sz (1'b1),
.app_raw_not_ecc (app_raw_not_ecc),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.app_cmd (app_cmd),
.app_addr (app_addr),
.accept_ns (accept_ns),
.accept (accept),
.app_correct_en (app_correct_en_i),
.app_sr_req (app_sr_req),
.sr_req (app_sr_req_i),
.sr_active (app_sr_active_i),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.ref_req (app_ref_req_i),
.ref_ack (app_ref_ack_i),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.zq_req (app_zq_req_i),
.zq_ack (app_zq_ack_i),
.app_zq_ack (app_zq_ack)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// debounce # (
// .pCLKS(32'd 1_000_000) // number of clocks to count before signal is "stable"
// ) debounce_inst (
// .iCLK(), .iRESET(), .oSIG(), .iSIG()
// );
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module debounce # (
parameter pCLKS = 32'd 1_000_000) // around 20-50ms works OK for a button; 2-10us could work for an asynchronous machine source
(
input iCLK,
input iRESET, // active high reset
input iSIG,
output reg oSIG
);
integer debounceCtr = 0;
always @(posedge iCLK or posedge iRESET) begin
if (iRESET)
begin
debounceCtr <= 0;
oSIG <= 0;
end
else if (iSIG)
begin // iSIG trying to go high
if (!oSIG)
begin // output low, increment counter
if (debounceCtr < pCLKS)
begin
debounceCtr <= debounceCtr + 1;
oSIG <= 0;
end
else
begin
debounceCtr <= 0;
oSIG <= 1;
end
end
else
begin // output already high, do nothing
debounceCtr <= 0;
end
end
else
begin // iSIG trying to go low
if (oSIG)
begin
if (debounceCtr < pCLKS)
begin // output high, increment counter
debounceCtr <= debounceCtr + 1;
oSIG <= 1;
end
else
begin
debounceCtr <= 0;
oSIG <= 0;
end
end
else
begin // output already low, do nothing
debounceCtr <= 0;
end
end
end
endmodule
|
// soc_design_niosII_core.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_niosII_core (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [26:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire [3:0] d_burstcount, // .burstcount
input wire d_readdatavalid, // .readdatavalid
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [26:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
output wire [3:0] i_burstcount, // .burstcount
input wire i_readdatavalid, // .readdatavalid
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
soc_design_niosII_core_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.d_burstcount (d_burstcount), // .burstcount
.d_readdatavalid (d_readdatavalid), // .readdatavalid
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.i_burstcount (i_burstcount), // .burstcount
.i_readdatavalid (i_readdatavalid), // .readdatavalid
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
module var21_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29
+ T * 9'd23
+ U * 9'd24;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1
+ T * 9'd22
+ U * 9'd26;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28
+ T * 9'd13
+ U * 9'd18;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
// psi2c_control
`timescale 1 ps / 1 ps
/*
-- registers b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
-- 0 w: tbm go
-- 0 r: ful tbm run
-- 1 w: send raw S P D7 D6 D5 D4 !D4 D3 D2 D1 D0 !D0
-- 2 w: send D7 D6 D5 D4 D3 D2 D1 D0
-- 3 w: send S D7 D6 D5 D4 D3 D2 D1 D0
-- 4 w: send P D7 D6 D5 D4 D3 D2 D1 D0
-- 5 w: send SP D7 D6 D5 D4 D3 D2 D1 D0
-- 1 r: rdb raw run 0 0 _s3 _rw _d4 _d0 S ha4 ha3 ha2 ha1 ha0 pa2 pa1 pa0
-- ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0
--
-- tbm = read back on
-- ful = fifo full
-- go = start transmission
-- run = i2c running
-- S = Start Bit, P = Stop Bit
-- D = Send Data
-- ha = Hub Address
-- pa = Port Address
-- ra = Register Address
-- rd = Register Data
*/
module i2c_control
(
// avalon slave
input clk,
input reset,
// avalon slave interface
input [2:0]address,
input write,
input [31:0]writedata,
input read,
output reg [31:0]readdata,
output go,
input full,
output reg [11:0]memd,
output memw,
input busy,
output tbm,
input [31:0]rda
);
wire [9:0]i2c_data;
reg rdbff;
assign memw = write & (address>=1) & (address<=5);
assign i2c_data = {writedata[7:4], !writedata[4],
writedata[3:0], !writedata[0]};
always @(*)
case (address)
2: memd <= {2'b00, i2c_data};
3: memd <= {2'b10, i2c_data}; // S
4: memd <= {2'b01, i2c_data}; // P
5: memd <= {2'b11, i2c_data}; // SP
default: memd <= writedata[11:0];
endcase
always @(*)
case (address)
1: readdata <= rda;
default readdata <= {1'b0, full, rdbff, busy || rda[31]};
endcase
// tbm mode
always @(posedge clk or posedge reset)
begin
if (reset) rdbff <= 0;
else if (write && (address == 0))
rdbff = writedata[1];
end
assign tbm = rdbff;
// go signal
assign go = write & writedata[0] & (address == 0);
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_dbg_hwbrk.v
//
// *Module Description:
// Hardware Breakpoint / Watchpoint module
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_dbg_hwbrk (
// OUTPUTs
brk_halt, // Hardware breakpoint command
brk_pnd, // Hardware break/watch-point pending
brk_dout, // Hardware break/watch-point register data input
// INPUTs
brk_reg_rd, // Hardware break/watch-point register read select
brk_reg_wr, // Hardware break/watch-point register write select
dbg_clk, // Debug unit clock
dbg_din, // Debug register data input
dbg_rst, // Debug unit reset
decode_noirq, // Frontend decode instruction
eu_mab, // Execution-Unit Memory address bus
eu_mb_en, // Execution-Unit Memory bus enable
eu_mb_wr, // Execution-Unit Memory bus write transfer
pc // Program counter
);
// OUTPUTs
//=========
output brk_halt; // Hardware breakpoint command
output brk_pnd; // Hardware break/watch-point pending
output [15:0] brk_dout; // Hardware break/watch-point register data input
// INPUTs
//=========
input [3:0] brk_reg_rd; // Hardware break/watch-point register read select
input [3:0] brk_reg_wr; // Hardware break/watch-point register write select
input dbg_clk; // Debug unit clock
input [15:0] dbg_din; // Debug register data input
input dbg_rst; // Debug unit reset
input decode_noirq; // Frontend decode instruction
input [15:0] eu_mab; // Execution-Unit Memory address bus
input eu_mb_en; // Execution-Unit Memory bus enable
input [1:0] eu_mb_wr; // Execution-Unit Memory bus write transfer
input [15:0] pc; // Program counter
//=============================================================================
// 1) WIRE & PARAMETER DECLARATION
//=============================================================================
wire range_wr_set;
wire range_rd_set;
wire addr1_wr_set;
wire addr1_rd_set;
wire addr0_wr_set;
wire addr0_rd_set;
parameter BRK_CTL = 0,
BRK_STAT = 1,
BRK_ADDR0 = 2,
BRK_ADDR1 = 3;
//=============================================================================
// 2) CONFIGURATION REGISTERS
//=============================================================================
// BRK_CTL Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_MODE INST_EN BREAK_EN ACCESS_MODE
//
// ACCESS_MODE: - 00 : Disabled
// - 01 : Detect read access
// - 10 : Detect write access
// - 11 : Detect read/write access
// NOTE: '10' & '11' modes are not supported on the instruction flow
//
// BREAK_EN: - 0 : Watchmode enable
// - 1 : Break enable
//
// INST_EN: - 0 : Checks are done on the execution unit (data flow)
// - 1 : Checks are done on the frontend (instruction flow)
//
// RANGE_MODE: - 0 : Address match on BRK_ADDR0 or BRK_ADDR1
// - 1 : Address match on BRK_ADDR0->BRK_ADDR1 range
//
//-----------------------------------------------------------------------------
reg [4:0] brk_ctl;
wire brk_ctl_wr = brk_reg_wr[BRK_CTL];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_ctl <= 5'h00;
else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]};
wire [7:0] brk_ctl_full = {3'b000, brk_ctl};
// BRK_STAT Register
//-----------------------------------------------------------------------------
// 7 6 5 4 3 2 1 0
// Reserved RANGE_WR RANGE_RD ADDR1_WR ADDR1_RD ADDR0_WR ADDR0_RD
//-----------------------------------------------------------------------------
reg [5:0] brk_stat;
wire brk_stat_wr = brk_reg_wr[BRK_STAT];
wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE,
range_rd_set & `HWBRK_RANGE,
addr1_wr_set, addr1_rd_set,
addr0_wr_set, addr0_rd_set};
wire [5:0] brk_stat_clr = ~dbg_din[5:0];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_stat <= 6'h00;
else if (brk_stat_wr) brk_stat <= ((brk_stat & brk_stat_clr) | brk_stat_set);
else brk_stat <= (brk_stat | brk_stat_set);
wire [7:0] brk_stat_full = {2'b00, brk_stat};
wire brk_pnd = |brk_stat;
// BRK_ADDR0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr0;
wire brk_addr0_wr = brk_reg_wr[BRK_ADDR0];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr0 <= 16'h0000;
else if (brk_addr0_wr) brk_addr0 <= dbg_din;
// BRK_ADDR1/DATA0 Register
//-----------------------------------------------------------------------------
reg [15:0] brk_addr1;
wire brk_addr1_wr = brk_reg_wr[BRK_ADDR1];
always @ (posedge dbg_clk or posedge dbg_rst)
if (dbg_rst) brk_addr1 <= 16'h0000;
else if (brk_addr1_wr) brk_addr1 <= dbg_din;
//============================================================================
// 3) DATA OUTPUT GENERATION
//============================================================================
wire [15:0] brk_ctl_rd = {8'h00, brk_ctl_full} & {16{brk_reg_rd[BRK_CTL]}};
wire [15:0] brk_stat_rd = {8'h00, brk_stat_full} & {16{brk_reg_rd[BRK_STAT]}};
wire [15:0] brk_addr0_rd = brk_addr0 & {16{brk_reg_rd[BRK_ADDR0]}};
wire [15:0] brk_addr1_rd = brk_addr1 & {16{brk_reg_rd[BRK_ADDR1]}};
wire [15:0] brk_dout = brk_ctl_rd |
brk_stat_rd |
brk_addr0_rd |
brk_addr1_rd;
//============================================================================
// 4) BREAKPOINT / WATCHPOINT GENERATION
//============================================================================
// Comparators
//---------------------------
// Note: here the comparison logic is instanciated several times in order
// to improve the timings, at the cost of a bit more area.
wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
wire equ_i_addr0 = decode_noirq & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE];
wire equ_i_addr1 = decode_noirq & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE];
wire equ_i_range = decode_noirq & ((pc>=brk_addr0) & (pc<=brk_addr1)) &
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE;
// Detect accesses
//---------------------------
// Detect Instruction read access
wire i_addr0_rd = equ_i_addr0 & brk_ctl[`BRK_I_EN];
wire i_addr1_rd = equ_i_addr1 & brk_ctl[`BRK_I_EN];
wire i_range_rd = equ_i_range & brk_ctl[`BRK_I_EN];
// Detect Execution-Unit write access
wire d_addr0_wr = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_addr1_wr = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
wire d_range_wr = equ_d_range & ~brk_ctl[`BRK_I_EN] & |eu_mb_wr;
// Detect DATA read access
wire d_addr0_rd = equ_d_addr0 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
wire d_addr1_rd = equ_d_addr1 & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
wire d_range_rd = equ_d_range & ~brk_ctl[`BRK_I_EN] & ~|eu_mb_wr;
// Set flags
assign addr0_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr0_rd | i_addr0_rd);
assign addr0_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr0_wr;
assign addr1_rd_set = brk_ctl[`BRK_MODE_RD] & (d_addr1_rd | i_addr1_rd);
assign addr1_wr_set = brk_ctl[`BRK_MODE_WR] & d_addr1_wr;
assign range_rd_set = brk_ctl[`BRK_MODE_RD] & (d_range_rd | i_range_rd);
assign range_wr_set = brk_ctl[`BRK_MODE_WR] & d_range_wr;
// Break CPU
assign brk_halt = brk_ctl[`BRK_EN] & |brk_stat_set;
endmodule // omsp_dbg_hwbrk
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_cntl_rx_fifo # (
parameter P_FIFO_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 5
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
output full_n,
output almost_full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg r_almost_full_n;
wire w_almost_full_n;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_front_addr;
assign full_n = ~(( r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign almost_full_n = r_almost_full_n;
assign w_invalid_front_addr = {~r_front_addr[P_FIFO_DEPTH_WIDTH], r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]};
assign w_invalid_space = w_invalid_front_addr - r_rear_addr;
assign w_almost_full_n = (w_invalid_space > 8);
always @(posedge clk)
begin
r_almost_full_n <= w_almost_full_n;
end
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_FIFO_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// dbg_register.v ////
//// ////
//// ////
//// This file is part of the SoC/OpenRISC Development Interface ////
//// http://www.opencores.org/cores/DebugInterface/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000,2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_register.v,v $
// Revision 1.1.1.1 2002/03/21 16:55:44 lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.3 2001/11/26 10:47:09 mohor
// Crc generation is different for read or write commands. Small synthesys fixes.
//
// Revision 1.2 2001/10/19 11:40:02 mohor
// dbg_timescale.v changed to timescale.v This is done for the simulation of
// few different cores in a single project.
//
// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
// Initial official release.
//
//
//
//
//
// synopsys translate_off
`include "rtl/verilog/dbg_interface/timescale.v"
// synopsys translate_on
module dbg_register(DataIn, DataOut, Write, Clk, Reset, Default);
parameter WIDTH = 8; // default parameter of the register width
input [WIDTH-1:0] DataIn;
input Write;
input Clk;
input Reset;
input [WIDTH-1:0] Default;
output [WIDTH-1:0] DataOut;
reg [WIDTH-1:0] DataOut;
//always @ (posedge Clk or posedge Reset)
always @ (posedge Clk)
begin
if(Reset)
DataOut[WIDTH-1:0]<=#1 Default;
else
begin
if(Write) // write
DataOut[WIDTH-1:0]<=#1 DataIn[WIDTH-1:0];
end
end
endmodule // Register
|
/*
module flag_cdc(
clkA, FlagIn_clkA,
clkB, FlagOut_clkB,rst_n);
// clkA domain signals
input clkA, FlagIn_clkA;
input rst_n;
// clkB domain signals
input clkB;
output FlagOut_clkB;
reg FlagToggle_clkA;
reg [2:0] SyncA_clkB;
// this changes level when a flag is seen
always @(posedge clkA)
begin : cdc_clk_a
if (rst_n == 1'b0) begin
FlagToggle_clkA <= 1'b0;
end
else if(FlagIn_clkA == 1'b1) begin
FlagToggle_clkA <= ~FlagToggle_clkA;
end
end
// which can then be sync-ed to clkB
always @(posedge clkB) SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};
// and recreate the flag from the level change
assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);
endmodule
*/
module flag_cdc(
input clkA,
input FlagIn_clkA,
input clkB,
output FlagOut_clkB,
input rst_n
);
// this changes level when the FlagIn_clkA is seen in clkA
reg FlagToggle_clkA = 1'b0;
always @(posedge clkA or negedge rst_n)
if (rst_n == 1'b0) begin
FlagToggle_clkA <= 1'b0;
end else begin
FlagToggle_clkA <= FlagToggle_clkA ^ FlagIn_clkA;
end
// which can then be sync-ed to clkB
reg [2:0] SyncA_clkB = 3'b0;
always @(posedge clkB or negedge rst_n)
if (rst_n == 1'b0) begin
SyncA_clkB <= 3'b0;
end else begin
SyncA_clkB <= {SyncA_clkB[1:0], FlagToggle_clkA};
end
// and recreate the flag in clkB
assign FlagOut_clkB = (SyncA_clkB[2] ^ SyncA_clkB[1]);
endmodule |
/*
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*
*/
`timescale 1ns / 1ps
`include "config.vh"
module iddr_wrap(input c, input i, output[1:0] o);
`ifdef X7SERIES
IDDR #(.DDR_CLK_EDGE("SAME_EDGE"), .SRTYPE("ASYNC")) IDDR_i
(.Q1(o[0]), .Q2(o[1]),
.C(c),
.CE(1'b1),
.D(i),
.R(1'b0), .S(1'b0));
`else
IDDR2 #(.DDR_ALIGNMENT("C0"), .SRTYPE("ASYNC")) IDDR2_i
(.Q0(o[0]), .Q1(o[1]),
.C0(c), .C1(~c),
.CE(1'b1),
.D(i),
.R(1'b0), .S(1'b0)
);
`endif
endmodule
|
//Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
//Date : Tue Mar 8 16:35:05 2016
//Host : lubuntu running 64-bit Ubuntu 15.04
//Command : generate_target design_1.bd
//Design : design_1
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire [14:0]processing_system7_0_DDR_ADDR;
wire [2:0]processing_system7_0_DDR_BA;
wire processing_system7_0_DDR_CAS_N;
wire processing_system7_0_DDR_CKE;
wire processing_system7_0_DDR_CK_N;
wire processing_system7_0_DDR_CK_P;
wire processing_system7_0_DDR_CS_N;
wire [3:0]processing_system7_0_DDR_DM;
wire [31:0]processing_system7_0_DDR_DQ;
wire [3:0]processing_system7_0_DDR_DQS_N;
wire [3:0]processing_system7_0_DDR_DQS_P;
wire processing_system7_0_DDR_ODT;
wire processing_system7_0_DDR_RAS_N;
wire processing_system7_0_DDR_RESET_N;
wire processing_system7_0_DDR_WE_N;
wire processing_system7_0_FIXED_IO_DDR_VRN;
wire processing_system7_0_FIXED_IO_DDR_VRP;
wire [53:0]processing_system7_0_FIXED_IO_MIO;
wire processing_system7_0_FIXED_IO_PS_CLK;
wire processing_system7_0_FIXED_IO_PS_PORB;
wire processing_system7_0_FIXED_IO_PS_SRSTB;
GND GND
(.G(GND_1));
design_1_processing_system7_0_0 processing_system7_0
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.MIO(FIXED_IO_mio[53:0]),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.USB0_VBUS_PWRFAULT(GND_1));
endmodule
|
/*
* Copyright (c) 2001 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program tests the magic $signed system function.
*/
module main;
reg [3:0] a;
initial begin
a = 4'd12;
// The expression should not change the bit pattern in any way
if ($signed(a) !== 4'b1100) begin
$display("FAILED -- $signed(%b) === %b", a, $signed(a));
$finish;
end
if ($signed(a) == 4) begin
$display("FAILED -- $signed(%b) == 4", a);
$finish;
end
// The >= should do a signed comparison here.
if ($signed(a) >= 0) begin
$display("FAILED -- $signed(%b) > 0", a);
$finish;
end
$display("PASSED");
end // initial begin
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_sq_rx_fifo # (
parameter P_FIFO_DATA_WIDTH = 128,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input clk,
input rst_n,
input wr_en,
input [P_FIFO_DEPTH_WIDTH-1:0] wr_addr,
input [P_FIFO_DATA_WIDTH-1:0] wr_data,
input [P_FIFO_DEPTH_WIDTH:0] rear_full_addr,
input [P_FIFO_DEPTH_WIDTH:0] rear_addr,
input [6:4] alloc_len,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
input free_en,
input [6:4] free_len,
output empty_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_empty_addr;
wire [P_FIFO_DEPTH_WIDTH:0] w_valid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_space;
wire [P_FIFO_DEPTH_WIDTH:0] w_invalid_front_addr;
assign w_invalid_front_addr = {~r_front_addr[P_FIFO_DEPTH_WIDTH], r_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign w_invalid_space = w_invalid_front_addr - rear_full_addr;
assign full_n = (w_invalid_space >= alloc_len);
assign w_valid_space = rear_addr - r_front_empty_addr;
assign empty_n = (w_valid_space >= free_len);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_front_empty_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (free_en == 1)
r_front_empty_addr <= r_front_empty_addr + free_len;
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH/2;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = wr_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], wr_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_1(
.DO (rd_data[P_FIFO_DATA_WIDTH-1:LP_READ_WIDTH]),
.DI (wr_data[P_FIFO_DATA_WIDTH-1:LP_WRITE_WIDTH]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2017 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef VERILATOR
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
`else
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0)
`endif
module t (/*AUTOARG*/);
int i_i [2:0];
int o_i [2:0];
import "DPI-C" function int dpii_failure();
import "DPI-C" function void dpii_open_i(input int i [], output int o []);
reg [95:0] crc;
initial begin
crc = 96'h8a10a572_5aef0c8d_d70a4497;
i_i[0] = crc[31:0];
i_i[1] = crc[63:32];
i_i[2] = crc[95:64];
dpii_open_i(i_i, o_i);
`checkh(o_i[0], ~i_i[0]);
`checkh(o_i[1], ~i_i[1]);
`checkh(o_i[2], ~i_i[2]);
if (dpii_failure()!=0) begin
$write("%%Error: Failure in DPI tests\n");
$stop;
end
else begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
/******************************************************************************
* *
* This module writes data to the RS232 UART Port. *
* *
******************************************************************************/
module altera_up_rs232_out_serializer (
// Inputs
clk,
reset,
transmit_data,
transmit_data_en,
// Bidirectionals
// Outputs
fifo_write_space,
serial_data_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter CW = 9; // Baud counter width
parameter BAUD_TICK_COUNT = 433;
parameter HALF_BAUD_TICK_COUNT = 216;
parameter TDW = 11; // Total data width
parameter DW = 9; // Data width
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] transmit_data;
input transmit_data_en;
// Bidirectionals
// Outputs
output reg [ 7: 0] fifo_write_space;
output reg serial_data_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire shift_data_reg_en;
wire all_bits_transmitted;
wire read_fifo_en;
wire fifo_is_empty;
wire fifo_is_full;
wire [ 6: 0] fifo_used;
wire [DW: 0] data_from_fifo;
// Internal Registers
reg transmitting_data;
reg [DW+1:0] data_out_shift_reg;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset)
fifo_write_space <= 8'h00;
else
fifo_write_space <= 8'h80 - {fifo_is_full, fifo_used};
end
always @(posedge clk)
begin
if (reset)
serial_data_out <= 1'b1;
else
serial_data_out <= data_out_shift_reg[0];
end
always @(posedge clk)
begin
if (reset)
transmitting_data <= 1'b0;
else if (all_bits_transmitted)
transmitting_data <= 1'b0;
else if (fifo_is_empty == 1'b0)
transmitting_data <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
data_out_shift_reg <= {(DW + 2){1'b1}};
else if (read_fifo_en)
data_out_shift_reg <= {data_from_fifo, 1'b0};
else if (shift_data_reg_en)
data_out_shift_reg <=
{1'b1, data_out_shift_reg[DW+1:1]};
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
assign read_fifo_en =
~transmitting_data & ~fifo_is_empty & ~all_bits_transmitted;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altera_up_rs232_counters RS232_Out_Counters (
// Inputs
.clk (clk),
.reset (reset),
.reset_counters (~transmitting_data),
// Bidirectionals
// Outputs
.baud_clock_rising_edge (shift_data_reg_en),
.baud_clock_falling_edge (),
.all_bits_transmitted (all_bits_transmitted)
);
defparam
RS232_Out_Counters.CW = CW,
RS232_Out_Counters.BAUD_TICK_COUNT = BAUD_TICK_COUNT,
RS232_Out_Counters.HALF_BAUD_TICK_COUNT = HALF_BAUD_TICK_COUNT,
RS232_Out_Counters.TDW = TDW;
altera_up_sync_fifo RS232_Out_FIFO (
// Inputs
.clk (clk),
.reset (reset),
.write_en (transmit_data_en & ~fifo_is_full),
.write_data (transmit_data),
.read_en (read_fifo_en),
// Bidirectionals
// Outputs
.fifo_is_empty (fifo_is_empty),
.fifo_is_full (fifo_is_full),
.words_used (fifo_used),
.read_data (data_from_fifo)
);
defparam
RS232_Out_FIFO.DW = DW,
RS232_Out_FIFO.DATA_DEPTH = 128,
RS232_Out_FIFO.AW = 6;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:50:35 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57,
n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71,
n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99,
n100, n101, n102, n103, n104, n105, n106, n107, n108, n109, n110,
n111, n112, n113, n114, n115, n116, n117, n118, n119, n120, n121,
n122, n123, n124, n125, n126, n127, n128, n129, n130, n131, n132,
n133, n134, n135, n136, n137, n138, n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148;
OAI21X2TS U46 ( .A0(n113), .A1(n112), .B0(n46), .Y(res[16]) );
NAND2XLTS U47 ( .A(n68), .B(n117), .Y(n119) );
NAND2XLTS U48 ( .A(n39), .B(n114), .Y(n116) );
NAND2X4TS U49 ( .A(n113), .B(n71), .Y(n46) );
CLKBUFX2TS U50 ( .A(n137), .Y(n33) );
OR2X2TS U51 ( .A(n78), .B(in1[14]), .Y(n39) );
OAI21X1TS U52 ( .A0(n76), .A1(in2[14]), .B0(add_sub), .Y(n74) );
INVX4TS U53 ( .A(n34), .Y(n48) );
NAND2X1TS U54 ( .A(n76), .B(add_sub), .Y(n77) );
CLKXOR2X2TS U55 ( .A(n80), .B(in2[13]), .Y(n81) );
NOR2XLTS U56 ( .A(n79), .B(n101), .Y(n80) );
NAND2XLTS U57 ( .A(n82), .B(add_sub), .Y(n83) );
NAND2BX2TS U58 ( .AN(in2[13]), .B(n79), .Y(n76) );
NOR2X2TS U59 ( .A(n82), .B(in2[12]), .Y(n79) );
NAND2X1TS U60 ( .A(n86), .B(add_sub), .Y(n87) );
NAND2X2TS U61 ( .A(in1[8]), .B(n70), .Y(n31) );
NAND2BX2TS U62 ( .AN(in2[9]), .B(n102), .Y(n86) );
NOR2X4TS U63 ( .A(n99), .B(in2[8]), .Y(n102) );
NAND2X1TS U64 ( .A(n99), .B(add_sub), .Y(n100) );
NAND2X4TS U65 ( .A(n127), .B(in1[6]), .Y(n97) );
NOR2X6TS U66 ( .A(n95), .B(in2[6]), .Y(n88) );
OR2X6TS U67 ( .A(n137), .B(in1[5]), .Y(n69) );
NAND2X4TS U68 ( .A(n95), .B(add_sub), .Y(n96) );
INVX3TS U69 ( .A(n67), .Y(n54) );
INVX6TS U70 ( .A(n133), .Y(n94) );
INVX8TS U71 ( .A(in2[3]), .Y(n62) );
INVX6TS U72 ( .A(in2[2]), .Y(n63) );
INVX6TS U73 ( .A(in2[1]), .Y(n64) );
INVX6TS U74 ( .A(in2[0]), .Y(n65) );
NOR2XLTS U75 ( .A(n102), .B(n101), .Y(n103) );
NAND2X1TS U76 ( .A(add_sub), .B(in2[0]), .Y(n130) );
OR2X4TS U77 ( .A(n92), .B(n101), .Y(n93) );
NOR2XLTS U78 ( .A(n84), .B(n101), .Y(n85) );
ADDHXLTS U79 ( .A(in2[0]), .B(in1[0]), .CO(n140), .S(res[0]) );
NAND2X4TS U80 ( .A(n50), .B(n48), .Y(n47) );
XNOR2X2TS U81 ( .A(n83), .B(in2[12]), .Y(n109) );
NAND2BX4TS U82 ( .AN(in2[11]), .B(n84), .Y(n82) );
XNOR2X2TS U83 ( .A(n87), .B(in2[10]), .Y(n111) );
NOR2X4TS U84 ( .A(n86), .B(in2[10]), .Y(n84) );
NOR2X4TS U85 ( .A(in2[4]), .B(in2[3]), .Y(n72) );
XOR2X1TS U86 ( .A(n116), .B(n115), .Y(res[14]) );
AND2X2TS U87 ( .A(n71), .B(n112), .Y(n38) );
OR2X4TS U88 ( .A(n75), .B(in1[15]), .Y(n71) );
NAND2X2TS U89 ( .A(n75), .B(in1[15]), .Y(n112) );
OR2X4TS U90 ( .A(n81), .B(in1[13]), .Y(n68) );
XOR2X1TS U91 ( .A(n129), .B(n128), .Y(res[6]) );
XOR2X1TS U92 ( .A(n139), .B(n138), .Y(res[5]) );
OAI21X1TS U93 ( .A0(n33), .A1(in1[5]), .B0(n126), .Y(n129) );
NAND2BX1TS U94 ( .AN(n132), .B(n131), .Y(n134) );
OAI211X1TS U95 ( .A0(in1[2]), .A1(n143), .B0(in1[1]), .C0(n141), .Y(n132) );
OAI21X1TS U96 ( .A0(in2[0]), .A1(in2[1]), .B0(add_sub), .Y(n124) );
NAND2X8TS U97 ( .A(n47), .B(n49), .Y(n113) );
NAND2X8TS U98 ( .A(n44), .B(n121), .Y(n70) );
XOR3X1TS U99 ( .A(n70), .B(in1[8]), .C(n120), .Y(res[8]) );
NAND2X2TS U100 ( .A(n120), .B(n70), .Y(n30) );
NAND2X2TS U101 ( .A(in1[8]), .B(n120), .Y(n32) );
NAND3X6TS U102 ( .A(n31), .B(n30), .C(n32), .Y(n105) );
XNOR2X4TS U103 ( .A(n100), .B(in2[8]), .Y(n120) );
NOR2X4TS U104 ( .A(n101), .B(in2[4]), .Y(n60) );
AND2X8TS U105 ( .A(n145), .B(in1[3]), .Y(n66) );
NAND2X8TS U106 ( .A(n90), .B(n73), .Y(n95) );
AND2X6TS U107 ( .A(n92), .B(n72), .Y(n90) );
NOR2X2TS U108 ( .A(n88), .B(n101), .Y(n89) );
XNOR2X2TS U109 ( .A(n74), .B(in2[15]), .Y(n75) );
NOR2X4TS U110 ( .A(n51), .B(n114), .Y(n50) );
NAND2BX4TS U111 ( .AN(in2[7]), .B(n88), .Y(n99) );
NAND2X2TS U112 ( .A(n101), .B(in2[4]), .Y(n59) );
NAND2X6TS U113 ( .A(n58), .B(in2[4]), .Y(n57) );
NAND2X4TS U114 ( .A(n61), .B(n60), .Y(n56) );
AO22XLTS U115 ( .A0(n148), .A1(in1[4]), .B0(n145), .B1(in1[3]), .Y(n125) );
INVX4TS U116 ( .A(n61), .Y(n58) );
XNOR2X2TS U117 ( .A(n77), .B(in2[14]), .Y(n78) );
INVX12TS U118 ( .A(add_sub), .Y(n101) );
NAND2X2TS U119 ( .A(n78), .B(in1[14]), .Y(n114) );
XOR2XLTS U120 ( .A(n148), .B(n147), .Y(res[4]) );
XNOR2X1TS U121 ( .A(n127), .B(in1[6]), .Y(n128) );
NAND2X1TS U122 ( .A(n35), .B(n121), .Y(n123) );
INVX2TS U123 ( .A(in1[9]), .Y(n43) );
XNOR2X1TS U124 ( .A(n33), .B(n136), .Y(n138) );
OR2X1TS U125 ( .A(n145), .B(in1[3]), .Y(n131) );
NOR2X2TS U126 ( .A(n34), .B(n51), .Y(n115) );
NOR2X4TS U127 ( .A(n101), .B(n90), .Y(n91) );
XNOR2X1TS U128 ( .A(n105), .B(n42), .Y(res[9]) );
AND2X8TS U129 ( .A(n118), .B(n68), .Y(n34) );
OR2X4TS U130 ( .A(in1[7]), .B(n98), .Y(n35) );
NAND2X2TS U131 ( .A(n81), .B(in1[13]), .Y(n117) );
OR2X4TS U132 ( .A(n127), .B(in1[6]), .Y(n36) );
NAND2X2TS U133 ( .A(n137), .B(in1[5]), .Y(n37) );
NAND2X2TS U134 ( .A(n98), .B(in1[7]), .Y(n121) );
XOR2X1TS U135 ( .A(n104), .B(n43), .Y(n42) );
CLKXOR2X2TS U136 ( .A(n103), .B(in2[9]), .Y(n104) );
AOI31X1TS U137 ( .A0(n143), .A1(in1[2]), .A2(n131), .B0(n125), .Y(n135) );
XNOR2X2TS U138 ( .A(n124), .B(in2[2]), .Y(n143) );
NAND2X8TS U139 ( .A(n40), .B(n37), .Y(n52) );
NAND2X8TS U140 ( .A(n69), .B(n53), .Y(n40) );
XOR2X2TS U141 ( .A(n113), .B(n38), .Y(res[15]) );
OAI2BB1X4TS U142 ( .A0N(in1[9]), .A1N(n105), .B0(n41), .Y(n110) );
OAI21X4TS U143 ( .A0(n105), .A1(in1[9]), .B0(n104), .Y(n41) );
NAND2X8TS U144 ( .A(n122), .B(n35), .Y(n44) );
XOR2X4TS U145 ( .A(n89), .B(in2[7]), .Y(n98) );
NAND2X8TS U146 ( .A(n45), .B(n97), .Y(n122) );
NAND2X8TS U147 ( .A(n52), .B(n36), .Y(n45) );
NOR3X8TS U148 ( .A(in2[1]), .B(in2[0]), .C(in2[2]), .Y(n92) );
NOR2X8TS U149 ( .A(n118), .B(n117), .Y(n51) );
OAI21X4TS U150 ( .A0(n34), .A1(n51), .B0(n39), .Y(n49) );
NAND2X8TS U151 ( .A(n55), .B(n54), .Y(n53) );
NAND2X8TS U152 ( .A(n66), .B(n94), .Y(n55) );
NAND3X8TS U153 ( .A(n57), .B(n56), .C(n59), .Y(n148) );
NOR2X8TS U154 ( .A(n148), .B(in1[4]), .Y(n133) );
NAND4X8TS U155 ( .A(n65), .B(n64), .C(n63), .D(n62), .Y(n61) );
XNOR2X1TS U156 ( .A(n119), .B(n118), .Y(res[13]) );
XNOR2X1TS U157 ( .A(n123), .B(n122), .Y(res[7]) );
XNOR2X4TS U158 ( .A(n93), .B(in2[3]), .Y(n145) );
XNOR2X4TS U159 ( .A(n96), .B(in2[6]), .Y(n127) );
AND2X4TS U160 ( .A(n148), .B(in1[4]), .Y(n67) );
INVX2TS U161 ( .A(in2[5]), .Y(n73) );
CLKXOR2X2TS U162 ( .A(n85), .B(in2[11]), .Y(n107) );
XOR2X4TS U163 ( .A(n91), .B(in2[5]), .Y(n137) );
ADDFHX4TS U164 ( .A(n107), .B(in1[11]), .CI(n106), .CO(n108), .S(res[11]) );
ADDFHX4TS U165 ( .A(n109), .B(in1[12]), .CI(n108), .CO(n118), .S(res[12]) );
ADDFHX4TS U166 ( .A(n111), .B(in1[10]), .CI(n110), .CO(n106), .S(res[10]) );
OAI2BB2XLTS U167 ( .B0(n135), .B1(n133), .A0N(n137), .A1N(in1[5]), .Y(n126)
);
XNOR2X1TS U168 ( .A(n130), .B(in2[1]), .Y(n141) );
AOI21X1TS U169 ( .A0(n135), .A1(n134), .B0(n133), .Y(n139) );
INVX2TS U170 ( .A(in1[5]), .Y(n136) );
CMPR32X2TS U171 ( .A(in1[1]), .B(n141), .C(n140), .CO(n142), .S(res[1]) );
CMPR32X2TS U172 ( .A(in1[2]), .B(n143), .C(n142), .CO(n144), .S(res[2]) );
CMPR32X2TS U173 ( .A(in1[3]), .B(n145), .C(n144), .CO(n146), .S(res[3]) );
XOR2X1TS U174 ( .A(in1[4]), .B(n146), .Y(n147) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_ACAIN8Q5_syn.sdf");
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_axi_basic_rx.v
// Version : 3.0
// //
// Description: //
// TRN to AXI RX module. Instantiates pipeline and null generator RX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_axi_basic_rx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires
wire null_rx_tvalid;
wire null_rx_tlast;
wire [KEEP_WIDTH-1:0] null_rx_tkeep;
wire null_rdst_rdy;
wire [4:0] null_is_eof;
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
pcie_7x_0_core_top_axi_basic_rx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_pipeline_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// Null Inputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// RX Null Packet Generator //
//---------------------------------------------//
pcie_7x_0_core_top_axi_basic_rx_null_gen #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_null_gen_inst (
// Inputs
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Null Outputs
//-----------
.null_rx_tvalid( null_rx_tvalid ),
.null_rx_tlast( null_rx_tlast ),
.null_rx_tkeep( null_rx_tkeep ),
.null_rdst_rdy( null_rdst_rdy ),
.null_is_eof( null_is_eof ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ddr2_phy_alt_mem_phy_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 218 06/27/2010 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddr2_phy_alt_mem_phy_pll (
areset,
inclk0,
phasecounterselect,
phasestep,
phaseupdown,
scanclk,
c0,
c1,
c2,
c3,
c4,
c5,
locked,
phasedone);
input areset;
input inclk0;
input [3:0] phasecounterselect;
input phasestep;
input phaseupdown;
input scanclk;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output locked;
output phasedone;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
tri0 [3:0] phasecounterselect;
tri0 phasestep;
tri0 phaseupdown;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [6:0] sub_wire0;
wire sub_wire5;
wire sub_wire8;
wire [0:0] sub_wire11 = 1'h0;
wire [4:4] sub_wire7 = sub_wire0[4:4];
wire [0:0] sub_wire6 = sub_wire0[0:0];
wire [3:3] sub_wire4 = sub_wire0[3:3];
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [5:5] sub_wire2 = sub_wire0[5:5];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c5 = sub_wire2;
wire c2 = sub_wire3;
wire c3 = sub_wire4;
wire locked = sub_wire5;
wire c0 = sub_wire6;
wire c4 = sub_wire7;
wire phasedone = sub_wire8;
wire sub_wire9 = inclk0;
wire [1:0] sub_wire10 = {sub_wire11, sub_wire9};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire10),
.phasecounterselect (phasecounterselect),
.phasestep (phasestep),
.scanclk (scanclk),
.phaseupdown (phaseupdown),
.clk (sub_wire0),
.locked (sub_wire5),
.phasedone (sub_wire8),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "833",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 1,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 2,
altpll_component.clk2_phase_shift = "0",
altpll_component.clk3_divide_by = 1,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 2,
altpll_component.clk3_phase_shift = "-1250",
altpll_component.clk4_divide_by = 1,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 2,
altpll_component.clk4_phase_shift = "0",
altpll_component.clk5_divide_by = 1,
altpll_component.clk5_duty_cycle = 50,
altpll_component.clk5_multiply_by = 2,
altpll_component.clk5_phase_shift = "0",
altpll_component.inclk0_input_frequency = 10000,
altpll_component.intended_device_family = "Arria II GX",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.pll_type = "Left_Right",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_USED",
altpll_component.port_phasedone = "PORT_USED",
altpll_component.port_phasestep = "PORT_USED",
altpll_component.port_phaseupdown = "PORT_USED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_USED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_USED",
altpll_component.port_clk6 = "PORT_UNUSED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.vco_frequency_control = "MANUAL_PHASE",
altpll_component.vco_phase_shift_step = 78,
altpll_component.width_clock = 7;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "5"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "200.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "200.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "200.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "200.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "200.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_EDIT STRING "78.00000000"
// Retrieval info: PRIVATE: MANUAL_PHASE_SHIFT_STEP_UNIT STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "200.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "200.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "200.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "200.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "200.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "30.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "1"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_mem_phy_pll_siii.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK5 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLK5 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "833"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-1250"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "Left_Right"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: VCO_FREQUENCY_CONTROL STRING "MANUAL_PHASE"
// Retrieval info: CONSTANT: VCO_PHASE_SHIFT_STEP NUMERIC "78"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "7"
// Retrieval info: USED_PORT: @clk 0 0 7 0 OUTPUT_CLK_EXT VCC "@clk[6..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: USED_PORT: phasecounterselect 0 0 4 0 INPUT GND "phasecounterselect[3..0]"
// Retrieval info: USED_PORT: phasedone 0 0 0 0 OUTPUT GND "phasedone"
// Retrieval info: USED_PORT: phasestep 0 0 0 0 INPUT GND "phasestep"
// Retrieval info: USED_PORT: phaseupdown 0 0 0 0 INPUT GND "phaseupdown"
// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: @phasecounterselect 0 0 4 0 phasecounterselect 0 0 4 0
// Retrieval info: CONNECT: @phasestep 0 0 0 0 phasestep 0 0 0 0
// Retrieval info: CONNECT: @phaseupdown 0 0 0 0 phaseupdown 0 0 0 0
// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: phasedone 0 0 0 0 @phasedone 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2_phy_alt_mem_phy_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2_phy_alt_mem_phy_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2_phy_alt_mem_phy_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2_phy_alt_mem_phy_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2_phy_alt_mem_phy_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr2_phy_alt_mem_phy_pll_bb.v TRUE
|
//*****************************************************************************
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.92
// \ \ Application : MIG
// / / Filename : sim_tb_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
// \ \ / \ Date Created : Mon Mar 2 2009
// \___\/\___\
//
// Device : Spartan-6
// Design Name : DDR/DDR2/DDR3/LPDDR
// Purpose : This is the simulation testbench which is used to verify the
// design. The basic clocks and resets to the interface are
// generated here. This also connects the memory interface to the
// memory model.
//*****************************************************************************
`timescale 1ps/1ps
module sim_tb_top;
// ========================================================================== //
// Parameters //
// ========================================================================== //
parameter DEBUG_EN = 0;
localparam DBG_WR_STS_WIDTH = 32;
localparam DBG_RD_STS_WIDTH = 32;
parameter C1_MEMCLK_PERIOD = 3000;
parameter C1_RST_ACT_LOW = 0;
parameter C1_INPUT_CLK_TYPE = "SINGLE_ENDED";
parameter C1_NUM_DQ_PINS = 16;
parameter C1_MEM_ADDR_WIDTH = 13;
parameter C1_MEM_BANKADDR_WIDTH = 3;
parameter C1_MEM_ADDR_ORDER = "ROW_BANK_COLUMN";
parameter C1_P0_MASK_SIZE = 4;
parameter C1_P0_DATA_PORT_SIZE = 32;
parameter C1_P1_MASK_SIZE = 4;
parameter C1_P1_DATA_PORT_SIZE = 32;
parameter C1_CALIB_SOFT_IP = "TRUE";
parameter C1_SIMULATION = "TRUE";
parameter C1_HW_TESTING = "FALSE";
parameter C3_MEMCLK_PERIOD = 3000;
parameter C3_RST_ACT_LOW = 0;
parameter C3_INPUT_CLK_TYPE = "SINGLE_ENDED";
parameter C3_NUM_DQ_PINS = 16;
parameter C3_MEM_ADDR_WIDTH = 13;
parameter C3_MEM_BANKADDR_WIDTH = 3;
parameter C3_MEM_ADDR_ORDER = "ROW_BANK_COLUMN";
parameter C3_P0_MASK_SIZE = 4;
parameter C3_P0_DATA_PORT_SIZE = 32;
parameter C3_P1_MASK_SIZE = 4;
parameter C3_P1_DATA_PORT_SIZE = 32;
parameter C3_CALIB_SOFT_IP = "TRUE";
parameter C3_SIMULATION = "TRUE";
parameter C3_HW_TESTING = "FALSE";
// ========================================================================== //
// Signal Declarations //
// ========================================================================== //
// Clocks
reg c1_sys_clk;
wire c1_sys_clk_p;
wire c1_sys_clk_n;
// System Reset
reg c1_sys_rst;
wire c1_sys_rst_i;
// Design-Top Port Map
wire [C1_MEM_ADDR_WIDTH-1:0] mcb1_dram_a;
wire [C1_MEM_BANKADDR_WIDTH-1:0] mcb1_dram_ba;
wire mcb1_dram_ck;
wire mcb1_dram_ck_n;
wire [C1_NUM_DQ_PINS-1:0] mcb1_dram_dq;
wire mcb1_dram_dqs;
wire mcb1_dram_dqs_n;
wire mcb1_dram_dm;
wire mcb1_dram_ras_n;
wire mcb1_dram_cas_n;
wire mcb1_dram_we_n;
wire mcb1_dram_cke;
wire mcb1_dram_odt;
wire mcb1_dram_reset_n;
wire mcb1_dram_udqs; // for X16 parts
wire mcb1_dram_udqs_n; // for X16 parts
wire mcb1_dram_udm; // for X16 parts
// Clocks
reg c3_sys_clk;
wire c3_sys_clk_p;
wire c3_sys_clk_n;
// System Reset
reg c3_sys_rst;
wire c3_sys_rst_i;
// Design-Top Port Map
wire [C3_MEM_ADDR_WIDTH-1:0] mcb3_dram_a;
wire [C3_MEM_BANKADDR_WIDTH-1:0] mcb3_dram_ba;
wire mcb3_dram_ck;
wire mcb3_dram_ck_n;
wire [C3_NUM_DQ_PINS-1:0] mcb3_dram_dq;
wire mcb3_dram_dqs;
wire mcb3_dram_dqs_n;
wire mcb3_dram_dm;
wire mcb3_dram_ras_n;
wire mcb3_dram_cas_n;
wire mcb3_dram_we_n;
wire mcb3_dram_cke;
wire mcb3_dram_odt;
wire mcb3_dram_reset_n;
wire mcb3_dram_udqs; // for X16 parts
wire mcb3_dram_udqs_n; // for X16 parts
wire mcb3_dram_udm; // for X16 parts
// Error & Calib Signals
wire error;
wire calib_done;
wire rzq1;
wire rzq3; wire zio1;
wire zio3;
// ========================================================================== //
// Clocks Generation //
// ========================================================================== //
initial
c1_sys_clk = 1'b0;
always
#(C1_MEMCLK_PERIOD/2) c1_sys_clk = ~c1_sys_clk;
assign c1_sys_clk_p = c1_sys_clk;
assign c1_sys_clk_n = ~c1_sys_clk;
initial
c3_sys_clk = 1'b0;
always
#(C3_MEMCLK_PERIOD/2) c3_sys_clk = ~c3_sys_clk;
assign c3_sys_clk_p = c3_sys_clk;
assign c3_sys_clk_n = ~c3_sys_clk;
// ========================================================================== //
// Reset Generation //
// ========================================================================== //
initial begin
c1_sys_rst = 1'b0;
#20000;
c1_sys_rst = 1'b1;
end
assign c1_sys_rst_i = C1_RST_ACT_LOW ? c1_sys_rst : ~c1_sys_rst;
initial begin
c3_sys_rst = 1'b0;
#20000;
c3_sys_rst = 1'b1;
end
assign c3_sys_rst_i = C3_RST_ACT_LOW ? c3_sys_rst : ~c3_sys_rst;
// ========================================================================== //
// Error Grouping //
// ========================================================================== //
// The PULLDOWN component is connected to the ZIO signal primarily to avoid the
// unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
PULLDOWN zio_pulldown1 (.O(zio1));
PULLDOWN zio_pulldown3 (.O(zio3)); PULLDOWN rzq_pulldown1 (.O(rzq1));
PULLDOWN rzq_pulldown3 (.O(rzq3));
// ========================================================================== //
// DESIGN TOP INSTANTIATION //
// ========================================================================== //
example_top #(
.C1_P0_MASK_SIZE (C1_P0_MASK_SIZE ),
.C1_P0_DATA_PORT_SIZE (C1_P0_DATA_PORT_SIZE ),
.C1_P1_MASK_SIZE (C1_P1_MASK_SIZE ),
.C1_P1_DATA_PORT_SIZE (C1_P1_DATA_PORT_SIZE ),
.C1_MEMCLK_PERIOD (C1_MEMCLK_PERIOD),
.C1_RST_ACT_LOW (C1_RST_ACT_LOW),
.C1_INPUT_CLK_TYPE (C1_INPUT_CLK_TYPE),
.DEBUG_EN (DEBUG_EN),
.C1_MEM_ADDR_ORDER (C1_MEM_ADDR_ORDER ),
.C1_NUM_DQ_PINS (C1_NUM_DQ_PINS ),
.C1_MEM_ADDR_WIDTH (C1_MEM_ADDR_WIDTH ),
.C1_MEM_BANKADDR_WIDTH (C1_MEM_BANKADDR_WIDTH),
.C1_HW_TESTING (C1_HW_TESTING),
.C1_SIMULATION (C1_SIMULATION),
.C1_CALIB_SOFT_IP (C1_CALIB_SOFT_IP ),
.C3_P0_MASK_SIZE (C3_P0_MASK_SIZE ),
.C3_P0_DATA_PORT_SIZE (C3_P0_DATA_PORT_SIZE ),
.C3_P1_MASK_SIZE (C3_P1_MASK_SIZE ),
.C3_P1_DATA_PORT_SIZE (C3_P1_DATA_PORT_SIZE ),
.C3_MEMCLK_PERIOD (C3_MEMCLK_PERIOD),
.C3_RST_ACT_LOW (C3_RST_ACT_LOW),
.C3_INPUT_CLK_TYPE (C3_INPUT_CLK_TYPE),
.C3_MEM_ADDR_ORDER (C3_MEM_ADDR_ORDER ),
.C3_NUM_DQ_PINS (C3_NUM_DQ_PINS ),
.C3_MEM_ADDR_WIDTH (C3_MEM_ADDR_WIDTH ),
.C3_MEM_BANKADDR_WIDTH (C3_MEM_BANKADDR_WIDTH),
.C3_HW_TESTING (C3_HW_TESTING),
.C3_SIMULATION (C3_SIMULATION),
.C3_CALIB_SOFT_IP (C3_CALIB_SOFT_IP )
)
design_top (
.c1_sys_clk (c1_sys_clk),
.c1_sys_rst_i (c1_sys_rst_i),
.mcb1_dram_dq (mcb1_dram_dq),
.mcb1_dram_a (mcb1_dram_a),
.mcb1_dram_ba (mcb1_dram_ba),
.mcb1_dram_ras_n (mcb1_dram_ras_n),
.mcb1_dram_cas_n (mcb1_dram_cas_n),
.mcb1_dram_we_n (mcb1_dram_we_n),
.mcb1_dram_odt (mcb1_dram_odt),
.mcb1_dram_cke (mcb1_dram_cke),
.mcb1_dram_ck (mcb1_dram_ck),
.mcb1_dram_ck_n (mcb1_dram_ck_n),
.mcb1_dram_dqs (mcb1_dram_dqs),
.mcb1_dram_dqs_n (mcb1_dram_dqs_n),
.calib_done (calib_done),
.error (error),
.mcb1_dram_udqs (mcb1_dram_udqs), // for X16 parts
.mcb1_dram_udqs_n (mcb1_dram_udqs_n), // for X16 parts
.mcb1_dram_udm (mcb1_dram_udm), // for X16 parts
.mcb1_dram_dm (mcb1_dram_dm),
.mcb1_rzq (rzq1),
.mcb1_zio (zio1),
.mcb1_dram_reset_n (mcb1_dram_reset_n),
.c3_sys_clk (c3_sys_clk),
.c3_sys_rst_i (c3_sys_rst_i),
.mcb3_dram_dq (mcb3_dram_dq),
.mcb3_dram_a (mcb3_dram_a),
.mcb3_dram_ba (mcb3_dram_ba),
.mcb3_dram_ras_n (mcb3_dram_ras_n),
.mcb3_dram_cas_n (mcb3_dram_cas_n),
.mcb3_dram_we_n (mcb3_dram_we_n),
.mcb3_dram_odt (mcb3_dram_odt),
.mcb3_dram_cke (mcb3_dram_cke),
.mcb3_dram_ck (mcb3_dram_ck),
.mcb3_dram_ck_n (mcb3_dram_ck_n),
.mcb3_dram_dqs (mcb3_dram_dqs),
.mcb3_dram_dqs_n (mcb3_dram_dqs_n),
.mcb3_dram_udqs (mcb3_dram_udqs), // for X16 parts
.mcb3_dram_udqs_n (mcb3_dram_udqs_n), // for X16 parts
.mcb3_dram_udm (mcb3_dram_udm), // for X16 parts
.mcb3_dram_dm (mcb3_dram_dm),
.mcb3_rzq (rzq3),
.mcb3_zio (zio3),
.mcb3_dram_reset_n (mcb3_dram_reset_n)
);
// ========================================================================== //
// Memory model instances //
// ========================================================================== //
generate
if(C1_NUM_DQ_PINS == 16) begin : MEM_INST1
ddr3_model_c1 u_mem_c1(
.ck (mcb1_dram_ck),
.ck_n (mcb1_dram_ck_n),
.cke (mcb1_dram_cke),
.cs_n (1'b0),
.ras_n (mcb1_dram_ras_n),
.cas_n (mcb1_dram_cas_n),
.we_n (mcb1_dram_we_n),
.dm_tdqs ({mcb1_dram_udm,mcb1_dram_dm}),
.ba (mcb1_dram_ba),
.addr (mcb1_dram_a),
.dq (mcb1_dram_dq),
.dqs ({mcb1_dram_udqs,mcb1_dram_dqs}),
.dqs_n ({mcb1_dram_udqs_n,mcb1_dram_dqs_n}),
.tdqs_n (),
.odt (mcb1_dram_odt),
.rst_n (mcb1_dram_reset_n)
);
end else begin
ddr3_model_c1 u_mem_c1(
.ck (mcb1_dram_ck),
.ck_n (mcb1_dram_ck_n),
.cke (mcb1_dram_cke),
.cs_n (1'b0),
.ras_n (mcb1_dram_ras_n),
.cas_n (mcb1_dram_cas_n),
.we_n (mcb1_dram_we_n),
.dm_tdqs (mcb1_dram_dm),
.ba (mcb1_dram_ba),
.addr (mcb1_dram_a),
.dq (mcb1_dram_dq),
.dqs (mcb1_dram_dqs),
.dqs_n (mcb1_dram_dqs_n),
.tdqs_n (),
.odt (mcb1_dram_odt),
.rst_n (mcb1_dram_reset_n)
);
end
endgenerate
generate
if(C3_NUM_DQ_PINS == 16) begin : MEM_INST3
ddr3_model_c3 u_mem_c3(
.ck (mcb3_dram_ck),
.ck_n (mcb3_dram_ck_n),
.cke (mcb3_dram_cke),
.cs_n (1'b0),
.ras_n (mcb3_dram_ras_n),
.cas_n (mcb3_dram_cas_n),
.we_n (mcb3_dram_we_n),
.dm_tdqs ({mcb3_dram_udm,mcb3_dram_dm}),
.ba (mcb3_dram_ba),
.addr (mcb3_dram_a),
.dq (mcb3_dram_dq),
.dqs ({mcb3_dram_udqs,mcb3_dram_dqs}),
.dqs_n ({mcb3_dram_udqs_n,mcb3_dram_dqs_n}),
.tdqs_n (),
.odt (mcb3_dram_odt),
.rst_n (mcb3_dram_reset_n)
);
end else begin
ddr3_model_c3 u_mem_c3(
.ck (mcb3_dram_ck),
.ck_n (mcb3_dram_ck_n),
.cke (mcb3_dram_cke),
.cs_n (1'b0),
.ras_n (mcb3_dram_ras_n),
.cas_n (mcb3_dram_cas_n),
.we_n (mcb3_dram_we_n),
.dm_tdqs (mcb3_dram_dm),
.ba (mcb3_dram_ba),
.addr (mcb3_dram_a),
.dq (mcb3_dram_dq),
.dqs (mcb3_dram_dqs),
.dqs_n (mcb3_dram_dqs_n),
.tdqs_n (),
.odt (mcb3_dram_odt),
.rst_n (mcb3_dram_reset_n)
);
end
endgenerate
// ========================================================================== //
// Reporting the test case status
// ========================================================================== //
initial
begin : Logging
fork
begin : calibration_done
wait (calib_done);
$display("Calibration Done");
#50000000;
if (!error) begin
$display("TEST PASSED");
end
else begin
$display("TEST FAILED: DATA ERROR");
end
disable calib_not_done;
$finish;
end
begin : calib_not_done
#200000000;
if (!calib_done) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end
endmodule
|
// Copyright 2020-2022 F4PGA Authors
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
// SPDX-License-Identifier: Apache-2.0
module top(input clk, stb, di, output do);
localparam integer DIN_N = 160;
localparam integer DOUT_N = 160;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [159:0] din, output [159:0] dout);
my_RAMB36E2
#(
.LOC("RAMB36_X2Y60"),
.DOA_REG(1'b1),
.DOB_REG(1'b0),
.INIT_A(18'b001000001000010101),
.INIT_B(18'b001111100001101011),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b1),
.IS_RSTRAMB_INVERTED(1'b1),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b1),
.RDADDRCHANGEA("FALSE"),
.RDADDRCHANGEB("FALSE"),
.READ_WIDTH_A(4),
.READ_WIDTH_B(4),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(1),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SRVAL_A(18'b110111110110100101),
.SRVAL_B(18'b000001011100001111),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
)
inst_0 (
.clk(clk),
.din(din[ 0 +: 24]),
.dout(dout[ 0 +: 8])
);
endmodule
// ---------------------------------------------------------------------
module my_RAMB36E2 (input clk, input [23:0] din, output [7:0] dout);
parameter LOC = "";
parameter DOA_REG = 1'b0;
parameter DOB_REG = 1'b0;
parameter INIT_A = 18'b0;
parameter INIT_B = 18'b0;
parameter IS_CLKARDCLK_INVERTED = 1'b0;
parameter IS_CLKBWRCLK_INVERTED = 1'b0;
parameter IS_ENARDEN_INVERTED = 1'b0;
parameter IS_ENBWREN_INVERTED = 1'b0;
parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
parameter IS_RSTRAMB_INVERTED = 1'b0;
parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
parameter IS_RSTREGB_INVERTED = 1'b0;
parameter RDADDRCHANGEA = "FALSE";
parameter RDADDRCHANGEB = "FALSE";
parameter READ_WIDTH_A = 0;
parameter READ_WIDTH_B = 0;
parameter WRITE_WIDTH_A = 0;
parameter WRITE_WIDTH_B = 0;
parameter RSTREG_PRIORITY_A = "RSTREG";
parameter RSTREG_PRIORITY_B = "RSTREG";
parameter SRVAL_A = 18'b0;
parameter SRVAL_B = 18'b0;
parameter WRITE_MODE_A = "WRITE_FIRST";
parameter WRITE_MODE_B = "WRITE_FIRST";
(* LOC=LOC *)
RAMB36E2 #(
.INITP_00(256'b0),
.INITP_01(256'b0),
.INITP_02(256'b0),
.INITP_03(256'b0),
.INITP_04(256'b0),
.INITP_05(256'b0),
.INITP_06(256'b0),
.INITP_07(256'b0),
.INITP_08(256'b0),
.INITP_09(256'b0),
.INITP_0A(256'b0),
.INITP_0B(256'b0),
.INITP_0C(256'b0),
.INITP_0D(256'b0),
.INITP_0E(256'b0),
.INITP_0F(256'b0),
.INIT_00(256'b0),
.INIT_01(256'b0),
.INIT_02(256'b0),
.INIT_03(256'b0),
.INIT_04(256'b0),
.INIT_05(256'b0),
.INIT_06(256'b0),
.INIT_07(256'b0),
.INIT_08(256'b0),
.INIT_09(256'b0),
.INIT_0A(256'b0),
.INIT_0B(256'b0),
.INIT_0C(256'b0),
.INIT_0D(256'b0),
.INIT_0E(256'b0),
.INIT_0F(256'b0),
.INIT_10(256'b0),
.INIT_11(256'b0),
.INIT_12(256'b0),
.INIT_13(256'b0),
.INIT_14(256'b0),
.INIT_15(256'b0),
.INIT_16(256'b0),
.INIT_17(256'b0),
.INIT_18(256'b0),
.INIT_19(256'b0),
.INIT_1A(256'b0),
.INIT_1B(256'b0),
.INIT_1C(256'b0),
.INIT_1D(256'b0),
.INIT_1E(256'b0),
.INIT_1F(256'b0),
.INIT_20(256'b0),
.INIT_21(256'b0),
.INIT_22(256'b0),
.INIT_23(256'b0),
.INIT_24(256'b0),
.INIT_25(256'b0),
.INIT_26(256'b0),
.INIT_27(256'b0),
.INIT_28(256'b0),
.INIT_29(256'b0),
.INIT_2A(256'b0),
.INIT_2B(256'b0),
.INIT_2C(256'b0),
.INIT_2D(256'b0),
.INIT_2E(256'b0),
.INIT_2F(256'b0),
.INIT_30(256'b0),
.INIT_31(256'b0),
.INIT_32(256'b0),
.INIT_33(256'b0),
.INIT_34(256'b0),
.INIT_35(256'b0),
.INIT_36(256'b0),
.INIT_37(256'b0),
.INIT_38(256'b0),
.INIT_39(256'b0),
.INIT_3A(256'b0),
.INIT_3B(256'b0),
.INIT_3C(256'b0),
.INIT_3D(256'b0),
.INIT_3E(256'b0),
.INIT_3F(256'b0),
.INIT_40(256'b0),
.INIT_41(256'b0),
.INIT_42(256'b0),
.INIT_43(256'b0),
.INIT_44(256'b0),
.INIT_45(256'b0),
.INIT_46(256'b0),
.INIT_47(256'b0),
.INIT_48(256'b0),
.INIT_49(256'b0),
.INIT_4A(256'b0),
.INIT_4B(256'b0),
.INIT_4C(256'b0),
.INIT_4D(256'b0),
.INIT_4E(256'b0),
.INIT_4F(256'b0),
.INIT_50(256'b0),
.INIT_51(256'b0),
.INIT_52(256'b0),
.INIT_53(256'b0),
.INIT_54(256'b0),
.INIT_55(256'b0),
.INIT_56(256'b0),
.INIT_57(256'b0),
.INIT_58(256'b0),
.INIT_59(256'b0),
.INIT_5A(256'b0),
.INIT_5B(256'b0),
.INIT_5C(256'b0),
.INIT_5D(256'b0),
.INIT_5E(256'b0),
.INIT_5F(256'b0),
.INIT_60(256'b0),
.INIT_61(256'b0),
.INIT_62(256'b0),
.INIT_63(256'b0),
.INIT_64(256'b0),
.INIT_65(256'b0),
.INIT_66(256'b0),
.INIT_67(256'b0),
.INIT_68(256'b0),
.INIT_69(256'b0),
.INIT_6A(256'b0),
.INIT_6B(256'b0),
.INIT_6C(256'b0),
.INIT_6D(256'b0),
.INIT_6E(256'b0),
.INIT_6F(256'b0),
.INIT_70(256'b0),
.INIT_71(256'b0),
.INIT_72(256'b0),
.INIT_73(256'b0),
.INIT_74(256'b0),
.INIT_75(256'b0),
.INIT_76(256'b0),
.INIT_77(256'b0),
.INIT_78(256'b0),
.INIT_79(256'b0),
.INIT_7A(256'b0),
.INIT_7B(256'b0),
.INIT_7C(256'b0),
.INIT_7D(256'b0),
.INIT_7E(256'b0),
.INIT_7F(256'b0),
.DOA_REG(DOA_REG),
.DOB_REG(DOB_REG),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED),
.IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED),
.IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED),
.IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED),
.IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED),
.IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED),
.IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED),
.IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED),
.RDADDRCHANGEA(RDADDRCHANGEA),
.RDADDRCHANGEB(RDADDRCHANGEB),
.READ_WIDTH_A(READ_WIDTH_A),
.READ_WIDTH_B(READ_WIDTH_B),
.WRITE_WIDTH_A(WRITE_WIDTH_A),
.WRITE_WIDTH_B(WRITE_WIDTH_B),
.RSTREG_PRIORITY_A(RSTREG_PRIORITY_A),
.RSTREG_PRIORITY_B(RSTREG_PRIORITY_B),
.SRVAL_A(SRVAL_A),
.SRVAL_B(SRVAL_B),
.WRITE_MODE_A(WRITE_MODE_A),
.WRITE_MODE_B(WRITE_MODE_B)
) ram (
// Port A Address/Control Signals inputs: Port A address and control signals
.ADDRARDADDR(din[0]), // 14-bit input: A/Read port address
.ADDRENA(din[1]), // 1-bit input: Active-High A/Read port address enable
.CLKARDCLK(din[2]), // 1-bit input: A/Read port clock
.ENARDEN(din[3]), // 1-bit input: Port A enable/Read enable
.REGCEAREGCE(din[4]), // 1-bit input: Port A register enable/Register enable
.RSTRAMARSTRAM(din[5]), // 1-bit input: Port A set/reset
.RSTREGARSTREG(din[6]), // 1-bit input: Port A register set/reset
.WEA(1'b0), // 2-bit input: Port A write enable
// Port A Data inputs: Port A data
.DINADIN(din[7]), // 16-bit input: Port A data/LSB data
.DINPADINP(din[8]), // 2-bit input: Port A parity/LSB parity
// Port B Address/Control Signals inputs: Port B address and control signals
.ADDRBWRADDR(din[9]), // 14-bit input: B/Write port address
.ADDRENB(din[10]), // 1-bit input: Active-High B/Write port address enable
.CLKBWRCLK(din[11]), // 1-bit input: B/Write port clock
.ENBWREN(din[12]), // 1-bit input: Port B enable/Write enable
.REGCEB(din[13]), // 1-bit input: Port B register enable
.RSTRAMB(din[14]), // 1-bit input: Port B set/reset
.RSTREGB(din[15]), // 1-bit input: Port B register set/reset
.SLEEP(din[16]), // 1-bit input: Sleep Mode
.WEBWE(din[17]), // 4-bit input: Port B write enable/Write enable
// Port B Data inputs: Port B data
.DINBDIN(din[18]), // 16-bit input: Port B data/MSB data
.DINPBDINP(din[19]), // 2-bit input: Port B parity/MSB parity
// Port A Data outputs: Port A data
.DOUTADOUT(dout[0]), // 16-bit output: Port A data/LSB data
.DOUTPADOUTP(dout[1]), // 2-bit output: Port A parity/LSB parity
// Port B Data outputs: Port B data
.DOUTBDOUT(dout[2]), // 16-bit output: Port B data/MSB data
.DOUTPBDOUTP(dout[3])); // 2-bit output: Port B parity/MSB parity
endmodule
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: COMMAND_PAGE.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module COMMAND_PAGE (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [15:0] data;
input [7:0] rdaddress;
input [8:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
// Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL "wraddress[8..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL COMMAND_PAGE_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:36:16 10/29/2011
// Design Name: M_uxa_ps2_shfreg
// Module Name: /Users/kc5tja/tmp/kestrel/2/nexys2/uxa/ps2io/T_uxa_ps2_shfreg.v
// Project Name: ps2io
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: M_uxa_ps2_shfreg
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module T_uxa_ps2_shfreg;
// Inputs
reg ps2_d_i;
reg ps2_c_i;
reg reset_i;
reg sys_clk_i;
// Outputs
wire [7:0] d_o;
wire frame_o;
// Instantiate the Unit Under Test (UUT)
M_uxa_ps2_shfreg uut (
.ps2_d_i(ps2_d_i),
.ps2_c_i(ps2_c_i),
.d_o(d_o),
.frame_o(frame_o),
.reset_i(reset_i),
.sys_clk_i(sys_clk_i)
);
always begin
#40 sys_clk_i <= 1;
#40 sys_clk_i <= 0;
end
initial begin
// Initialize Inputs
ps2_d_i = 1;
ps2_c_i = 1;
reset_i = 1;
sys_clk_i = 0;
#80 reset_i = 0;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 0; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#50000 ps2_d_i = 1; ps2_c_i = 0;
#50000 ps2_c_i = 1;
#320 ;
if(d_o != 8'b01100100) begin
$display("Deserializer failed to grab byte correctly.");
$stop;
end
if(frame_o != 1) begin
$display("Deserializer failed to sync to the PS/2 frame.");
$stop;
end
reset_i = 1;
#80 reset_i = 0;
if(d_o != 8'b11111111) begin
$display("Deserializer didn't reset when instructed.");
$stop;
end
if(frame_o != 0) begin
$display("Frame indicator didn't reset when instructed.");
$stop;
end
end
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_register_bank_a_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_register_bank_b_module (
// inputs:
clock,
data,
rdaddress,
wraddress,
wren,
// outputs:
q
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q;
input clock;
input [ 31: 0] data;
input [ 4: 0] rdaddress;
input [ 4: 0] wraddress;
input wren;
wire [ 31: 0] q;
wire [ 31: 0] ram_q;
assign q = ram_q;
altsyncram the_altsyncram
(
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.q_b (ram_q),
.wren_a (wren)
);
defparam the_altsyncram.address_reg_b = "CLOCK0",
the_altsyncram.init_file = lpm_file,
the_altsyncram.maximum_depth = 0,
the_altsyncram.numwords_a = 32,
the_altsyncram.numwords_b = 32,
the_altsyncram.operation_mode = "DUAL_PORT",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.rdcontrol_reg_b = "CLOCK0",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.widthad_a = 5,
the_altsyncram.widthad_b = 5;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_debug (
// inputs:
clk,
dbrk_break,
debugreq,
hbreak_enabled,
jdo,
jrst_n,
ocireg_ers,
ocireg_mrs,
reset,
st_ready_test_idle,
take_action_ocimem_a,
take_action_ocireg,
xbrk_break,
// outputs:
debugack,
monitor_error,
monitor_go,
monitor_ready,
oci_hbreak_req,
resetlatch,
resetrequest
)
;
output debugack;
output monitor_error;
output monitor_go;
output monitor_ready;
output oci_hbreak_req;
output resetlatch;
output resetrequest;
input clk;
input dbrk_break;
input debugreq;
input hbreak_enabled;
input [ 37: 0] jdo;
input jrst_n;
input ocireg_ers;
input ocireg_mrs;
input reset;
input st_ready_test_idle;
input take_action_ocimem_a;
input take_action_ocireg;
input xbrk_break;
wire debugack;
reg jtag_break /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg monitor_error /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_go /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
reg monitor_ready /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire oci_hbreak_req;
reg probepresent /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetlatch /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg resetrequest /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
probepresent <= 1'b0;
resetrequest <= 1'b0;
jtag_break <= 1'b0;
end
else if (take_action_ocimem_a)
begin
resetrequest <= jdo[22];
jtag_break <= jdo[21] ? 1
: jdo[20] ? 0
: jtag_break;
probepresent <= jdo[19] ? 1
: jdo[18] ? 0
: probepresent;
resetlatch <= jdo[24] ? 0 : resetlatch;
end
else if (reset)
begin
jtag_break <= probepresent;
resetlatch <= 1;
end
else if (~debugack & debugreq & probepresent)
jtag_break <= 1'b1;
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
monitor_ready <= 1'b0;
monitor_error <= 1'b0;
monitor_go <= 1'b0;
end
else
begin
if (take_action_ocimem_a && jdo[25])
monitor_ready <= 1'b0;
else if (take_action_ocireg && ocireg_mrs)
monitor_ready <= 1'b1;
if (take_action_ocimem_a && jdo[25])
monitor_error <= 1'b0;
else if (take_action_ocireg && ocireg_ers)
monitor_error <= 1'b1;
if (take_action_ocimem_a && jdo[23])
monitor_go <= 1'b1;
else if (st_ready_test_idle)
monitor_go <= 1'b0;
end
end
assign oci_hbreak_req = jtag_break | dbrk_break | xbrk_break | debugreq;
assign debugack = ~hbreak_enabled;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_ociram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
byteena_a,
clock0,
clock1,
clocken0,
clocken1,
data_a,
data_b,
wren_a,
wren_b,
// outputs:
q_a,
q_b
)
;
parameter lpm_file = "UNUSED";
output [ 31: 0] q_a;
output [ 31: 0] q_b;
input [ 7: 0] address_a;
input [ 7: 0] address_b;
input [ 3: 0] byteena_a;
input clock0;
input clock1;
input clocken0;
input clocken1;
input [ 31: 0] data_a;
input [ 31: 0] data_b;
input wren_a;
input wren_b;
wire [ 31: 0] q_a;
wire [ 31: 0] q_b;
altsyncram the_altsyncram
(
.address_a (address_a),
.address_b (address_b),
.byteena_a (byteena_a),
.clock0 (clock0),
.clock1 (clock1),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.wren_a (wren_a),
.wren_b (wren_b)
);
defparam the_altsyncram.address_aclr_a = "NONE",
the_altsyncram.address_aclr_b = "NONE",
the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.indata_aclr_a = "NONE",
the_altsyncram.indata_aclr_b = "NONE",
the_altsyncram.init_file = lpm_file,
the_altsyncram.intended_device_family = "CYCLONEII",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.numwords_a = 256,
the_altsyncram.numwords_b = 256,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_aclr_a = "NONE",
the_altsyncram.outdata_aclr_b = "NONE",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
the_altsyncram.width_a = 32,
the_altsyncram.width_b = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 8,
the_altsyncram.widthad_b = 8,
the_altsyncram.wrcontrol_aclr_a = "NONE",
the_altsyncram.wrcontrol_aclr_b = "NONE";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_ocimem (
// inputs:
address,
begintransfer,
byteenable,
chipselect,
clk,
debugaccess,
jdo,
jrst_n,
resetrequest,
take_action_ocimem_a,
take_action_ocimem_b,
take_no_action_ocimem_a,
write,
writedata,
// outputs:
MonDReg,
oci_ram_readdata
)
;
output [ 31: 0] MonDReg;
output [ 31: 0] oci_ram_readdata;
input [ 8: 0] address;
input begintransfer;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input debugaccess;
input [ 37: 0] jdo;
input jrst_n;
input resetrequest;
input take_action_ocimem_a;
input take_action_ocimem_b;
input take_no_action_ocimem_a;
input write;
input [ 31: 0] writedata;
reg [ 10: 0] MonAReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg [ 31: 0] MonDReg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonRd /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonRd1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
reg MonWr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire avalon;
wire [ 31: 0] cfgdout;
wire [ 31: 0] oci_ram_readdata;
wire [ 31: 0] sramdout;
assign avalon = begintransfer & ~resetrequest;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
MonWr <= 1'b0;
MonRd <= 1'b0;
MonRd1 <= 1'b0;
MonAReg <= 0;
MonDReg <= 0;
end
else
begin
if (take_no_action_ocimem_a)
begin
MonAReg[10 : 2] <= MonAReg[10 : 2]+1;
MonRd <= 1'b1;
end
else if (take_action_ocimem_a)
begin
MonAReg[10 : 2] <= { jdo[17],
jdo[33 : 26] };
MonRd <= 1'b1;
end
else if (take_action_ocimem_b)
begin
MonAReg[10 : 2] <= MonAReg[10 : 2]+1;
MonDReg <= jdo[34 : 3];
MonWr <= 1'b1;
end
else
begin
if (~avalon)
begin
MonWr <= 0;
MonRd <= 0;
end
if (MonRd1)
MonDReg <= MonAReg[10] ? cfgdout : sramdout;
end
MonRd1 <= MonRd;
end
end
//video_sys_CPU_ociram_lpm_dram_bdp_component, which is an nios_tdp_ram
video_sys_CPU_ociram_lpm_dram_bdp_component_module video_sys_CPU_ociram_lpm_dram_bdp_component
(
.address_a (address[7 : 0]),
.address_b (MonAReg[9 : 2]),
.byteena_a (byteenable),
.clock0 (clk),
.clock1 (clk),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_a (writedata),
.data_b (MonDReg[31 : 0]),
.q_a (oci_ram_readdata),
.q_b (sramdout),
.wren_a (chipselect & write & debugaccess &
~address[8]
),
.wren_b (MonWr)
);
//synthesis translate_off
`ifdef NO_PLI
defparam video_sys_CPU_ociram_lpm_dram_bdp_component.lpm_file = "video_sys_CPU_ociram_default_contents.dat";
`else
defparam video_sys_CPU_ociram_lpm_dram_bdp_component.lpm_file = "video_sys_CPU_ociram_default_contents.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam video_sys_CPU_ociram_lpm_dram_bdp_component.lpm_file = "video_sys_CPU_ociram_default_contents.mif";
//synthesis read_comments_as_HDL off
assign cfgdout = (MonAReg[4 : 2] == 3'd0)? 32'h00084020 :
(MonAReg[4 : 2] == 3'd1)? 32'h00001919 :
(MonAReg[4 : 2] == 3'd2)? 32'h00040000 :
(MonAReg[4 : 2] == 3'd3)? 32'h00000000 :
(MonAReg[4 : 2] == 3'd4)? 32'h20000000 :
(MonAReg[4 : 2] == 3'd5)? 32'h00084000 :
(MonAReg[4 : 2] == 3'd6)? 32'h00000000 :
32'h00000000;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_avalon_reg (
// inputs:
address,
chipselect,
clk,
debugaccess,
monitor_error,
monitor_go,
monitor_ready,
reset_n,
write,
writedata,
// outputs:
oci_ienable,
oci_reg_readdata,
oci_single_step_mode,
ocireg_ers,
ocireg_mrs,
take_action_ocireg
)
;
output [ 31: 0] oci_ienable;
output [ 31: 0] oci_reg_readdata;
output oci_single_step_mode;
output ocireg_ers;
output ocireg_mrs;
output take_action_ocireg;
input [ 8: 0] address;
input chipselect;
input clk;
input debugaccess;
input monitor_error;
input monitor_go;
input monitor_ready;
input reset_n;
input write;
input [ 31: 0] writedata;
reg [ 31: 0] oci_ienable;
wire oci_reg_00_addressed;
wire oci_reg_01_addressed;
wire [ 31: 0] oci_reg_readdata;
reg oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire ocireg_sstep;
wire take_action_oci_intr_mask_reg;
wire take_action_ocireg;
wire write_strobe;
assign oci_reg_00_addressed = address == 9'h100;
assign oci_reg_01_addressed = address == 9'h101;
assign write_strobe = chipselect & write & debugaccess;
assign take_action_ocireg = write_strobe & oci_reg_00_addressed;
assign take_action_oci_intr_mask_reg = write_strobe & oci_reg_01_addressed;
assign ocireg_ers = writedata[1];
assign ocireg_mrs = writedata[0];
assign ocireg_sstep = writedata[3];
assign oci_reg_readdata = oci_reg_00_addressed ? {28'b0, oci_single_step_mode, monitor_go,
monitor_ready, monitor_error} :
oci_reg_01_addressed ? oci_ienable :
32'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_single_step_mode <= 1'b0;
else if (take_action_ocireg)
oci_single_step_mode <= ocireg_sstep;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
oci_ienable <= 32'b00000000000000000000000000000011;
else if (take_action_oci_intr_mask_reg)
oci_ienable <= writedata | ~(32'b00000000000000000000000000000011);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_break (
// inputs:
clk,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
jdo,
jrst_n,
reset_n,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
xbrk_goto0,
xbrk_goto1,
// outputs:
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
trigbrktype,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3
)
;
output [ 31: 0] break_readreg;
output dbrk_hit0_latch;
output dbrk_hit1_latch;
output dbrk_hit2_latch;
output dbrk_hit3_latch;
output trigbrktype;
output trigger_state_0;
output trigger_state_1;
output [ 7: 0] xbrk_ctrl0;
output [ 7: 0] xbrk_ctrl1;
output [ 7: 0] xbrk_ctrl2;
output [ 7: 0] xbrk_ctrl3;
input clk;
input dbrk_break;
input dbrk_goto0;
input dbrk_goto1;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_break_a;
input take_action_break_b;
input take_action_break_c;
input take_no_action_break_a;
input take_no_action_break_b;
input take_no_action_break_c;
input xbrk_goto0;
input xbrk_goto1;
wire [ 3: 0] break_a_wpr;
wire [ 1: 0] break_a_wpr_high_bits;
wire [ 1: 0] break_a_wpr_low_bits;
wire [ 1: 0] break_b_rr;
wire [ 1: 0] break_c_rr;
reg [ 31: 0] break_readreg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
wire dbrk0_high_value;
wire dbrk0_low_value;
wire dbrk1_high_value;
wire dbrk1_low_value;
wire dbrk2_high_value;
wire dbrk2_low_value;
wire dbrk3_high_value;
wire dbrk3_low_value;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire take_action_any_break;
reg trigbrktype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg trigger_state;
wire trigger_state_0;
wire trigger_state_1;
wire [ 31: 0] xbrk0_value;
wire [ 31: 0] xbrk1_value;
wire [ 31: 0] xbrk2_value;
wire [ 31: 0] xbrk3_value;
reg [ 7: 0] xbrk_ctrl0 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 7: 0] xbrk_ctrl3 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
assign break_a_wpr = jdo[35 : 32];
assign break_a_wpr_high_bits = break_a_wpr[3 : 2];
assign break_a_wpr_low_bits = break_a_wpr[1 : 0];
assign break_b_rr = jdo[33 : 32];
assign break_c_rr = jdo[33 : 32];
assign take_action_any_break = take_action_break_a | take_action_break_b | take_action_break_c;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
xbrk_ctrl0 <= 0;
xbrk_ctrl1 <= 0;
xbrk_ctrl2 <= 0;
xbrk_ctrl3 <= 0;
trigbrktype <= 0;
end
else
begin
if (take_action_any_break)
trigbrktype <= 0;
else if (dbrk_break)
trigbrktype <= 1;
if (take_action_break_b)
begin
if ((break_b_rr == 2'b00) && (0 >= 1))
begin
xbrk_ctrl0[0] <= jdo[27];
xbrk_ctrl0[1] <= jdo[28];
xbrk_ctrl0[2] <= jdo[29];
xbrk_ctrl0[3] <= jdo[30];
xbrk_ctrl0[4] <= jdo[21];
xbrk_ctrl0[5] <= jdo[20];
xbrk_ctrl0[6] <= jdo[19];
xbrk_ctrl0[7] <= jdo[18];
end
if ((break_b_rr == 2'b01) && (0 >= 2))
begin
xbrk_ctrl1[0] <= jdo[27];
xbrk_ctrl1[1] <= jdo[28];
xbrk_ctrl1[2] <= jdo[29];
xbrk_ctrl1[3] <= jdo[30];
xbrk_ctrl1[4] <= jdo[21];
xbrk_ctrl1[5] <= jdo[20];
xbrk_ctrl1[6] <= jdo[19];
xbrk_ctrl1[7] <= jdo[18];
end
if ((break_b_rr == 2'b10) && (0 >= 3))
begin
xbrk_ctrl2[0] <= jdo[27];
xbrk_ctrl2[1] <= jdo[28];
xbrk_ctrl2[2] <= jdo[29];
xbrk_ctrl2[3] <= jdo[30];
xbrk_ctrl2[4] <= jdo[21];
xbrk_ctrl2[5] <= jdo[20];
xbrk_ctrl2[6] <= jdo[19];
xbrk_ctrl2[7] <= jdo[18];
end
if ((break_b_rr == 2'b11) && (0 >= 4))
begin
xbrk_ctrl3[0] <= jdo[27];
xbrk_ctrl3[1] <= jdo[28];
xbrk_ctrl3[2] <= jdo[29];
xbrk_ctrl3[3] <= jdo[30];
xbrk_ctrl3[4] <= jdo[21];
xbrk_ctrl3[5] <= jdo[20];
xbrk_ctrl3[6] <= jdo[19];
xbrk_ctrl3[7] <= jdo[18];
end
end
end
end
assign dbrk_hit0_latch = 1'b0;
assign dbrk0_low_value = 0;
assign dbrk0_high_value = 0;
assign dbrk_hit1_latch = 1'b0;
assign dbrk1_low_value = 0;
assign dbrk1_high_value = 0;
assign dbrk_hit2_latch = 1'b0;
assign dbrk2_low_value = 0;
assign dbrk2_high_value = 0;
assign dbrk_hit3_latch = 1'b0;
assign dbrk3_low_value = 0;
assign dbrk3_high_value = 0;
assign xbrk0_value = 32'b0;
assign xbrk1_value = 32'b0;
assign xbrk2_value = 32'b0;
assign xbrk3_value = 32'b0;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
break_readreg <= 32'b0;
else if (take_action_any_break)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_a)
case (break_a_wpr_high_bits)
2'd0: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= xbrk0_value;
end // 2'd0
2'd1: begin
break_readreg <= xbrk1_value;
end // 2'd1
2'd2: begin
break_readreg <= xbrk2_value;
end // 2'd2
2'd3: begin
break_readreg <= xbrk3_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd0
2'd1: begin
break_readreg <= 32'b0;
end // 2'd1
2'd2: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_low_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_low_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_low_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_low_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd2
2'd3: begin
case (break_a_wpr_low_bits) // synthesis full_case
2'd0: begin
break_readreg <= dbrk0_high_value;
end // 2'd0
2'd1: begin
break_readreg <= dbrk1_high_value;
end // 2'd1
2'd2: begin
break_readreg <= dbrk2_high_value;
end // 2'd2
2'd3: begin
break_readreg <= dbrk3_high_value;
end // 2'd3
endcase // break_a_wpr_low_bits
end // 2'd3
endcase // break_a_wpr_high_bits
else if (take_no_action_break_b)
break_readreg <= jdo[31 : 0];
else if (take_no_action_break_c)
break_readreg <= jdo[31 : 0];
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trigger_state <= 0;
else if (trigger_state_1 & (xbrk_goto0 | dbrk_goto0))
trigger_state <= 0;
else if (trigger_state_0 & (xbrk_goto1 | dbrk_goto1))
trigger_state <= -1;
end
assign trigger_state_0 = ~trigger_state;
assign trigger_state_1 = trigger_state;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_xbrk (
// inputs:
D_valid,
E_valid,
F_pc,
clk,
reset_n,
trigger_state_0,
trigger_state_1,
xbrk_ctrl0,
xbrk_ctrl1,
xbrk_ctrl2,
xbrk_ctrl3,
// outputs:
xbrk_break,
xbrk_goto0,
xbrk_goto1,
xbrk_traceoff,
xbrk_traceon,
xbrk_trigout
)
;
output xbrk_break;
output xbrk_goto0;
output xbrk_goto1;
output xbrk_traceoff;
output xbrk_traceon;
output xbrk_trigout;
input D_valid;
input E_valid;
input [ 22: 0] F_pc;
input clk;
input reset_n;
input trigger_state_0;
input trigger_state_1;
input [ 7: 0] xbrk_ctrl0;
input [ 7: 0] xbrk_ctrl1;
input [ 7: 0] xbrk_ctrl2;
input [ 7: 0] xbrk_ctrl3;
wire D_cpu_addr_en;
wire E_cpu_addr_en;
reg E_xbrk_goto0;
reg E_xbrk_goto1;
reg E_xbrk_traceoff;
reg E_xbrk_traceon;
reg E_xbrk_trigout;
wire [ 24: 0] cpu_i_address;
wire xbrk0_armed;
wire xbrk0_break_hit;
wire xbrk0_goto0_hit;
wire xbrk0_goto1_hit;
wire xbrk0_toff_hit;
wire xbrk0_ton_hit;
wire xbrk0_tout_hit;
wire xbrk1_armed;
wire xbrk1_break_hit;
wire xbrk1_goto0_hit;
wire xbrk1_goto1_hit;
wire xbrk1_toff_hit;
wire xbrk1_ton_hit;
wire xbrk1_tout_hit;
wire xbrk2_armed;
wire xbrk2_break_hit;
wire xbrk2_goto0_hit;
wire xbrk2_goto1_hit;
wire xbrk2_toff_hit;
wire xbrk2_ton_hit;
wire xbrk2_tout_hit;
wire xbrk3_armed;
wire xbrk3_break_hit;
wire xbrk3_goto0_hit;
wire xbrk3_goto1_hit;
wire xbrk3_toff_hit;
wire xbrk3_ton_hit;
wire xbrk3_tout_hit;
reg xbrk_break;
wire xbrk_break_hit;
wire xbrk_goto0;
wire xbrk_goto0_hit;
wire xbrk_goto1;
wire xbrk_goto1_hit;
wire xbrk_toff_hit;
wire xbrk_ton_hit;
wire xbrk_tout_hit;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
assign cpu_i_address = {F_pc, 2'b00};
assign D_cpu_addr_en = D_valid;
assign E_cpu_addr_en = E_valid;
assign xbrk0_break_hit = 0;
assign xbrk0_ton_hit = 0;
assign xbrk0_toff_hit = 0;
assign xbrk0_tout_hit = 0;
assign xbrk0_goto0_hit = 0;
assign xbrk0_goto1_hit = 0;
assign xbrk1_break_hit = 0;
assign xbrk1_ton_hit = 0;
assign xbrk1_toff_hit = 0;
assign xbrk1_tout_hit = 0;
assign xbrk1_goto0_hit = 0;
assign xbrk1_goto1_hit = 0;
assign xbrk2_break_hit = 0;
assign xbrk2_ton_hit = 0;
assign xbrk2_toff_hit = 0;
assign xbrk2_tout_hit = 0;
assign xbrk2_goto0_hit = 0;
assign xbrk2_goto1_hit = 0;
assign xbrk3_break_hit = 0;
assign xbrk3_ton_hit = 0;
assign xbrk3_toff_hit = 0;
assign xbrk3_tout_hit = 0;
assign xbrk3_goto0_hit = 0;
assign xbrk3_goto1_hit = 0;
assign xbrk_break_hit = (xbrk0_break_hit) | (xbrk1_break_hit) | (xbrk2_break_hit) | (xbrk3_break_hit);
assign xbrk_ton_hit = (xbrk0_ton_hit) | (xbrk1_ton_hit) | (xbrk2_ton_hit) | (xbrk3_ton_hit);
assign xbrk_toff_hit = (xbrk0_toff_hit) | (xbrk1_toff_hit) | (xbrk2_toff_hit) | (xbrk3_toff_hit);
assign xbrk_tout_hit = (xbrk0_tout_hit) | (xbrk1_tout_hit) | (xbrk2_tout_hit) | (xbrk3_tout_hit);
assign xbrk_goto0_hit = (xbrk0_goto0_hit) | (xbrk1_goto0_hit) | (xbrk2_goto0_hit) | (xbrk3_goto0_hit);
assign xbrk_goto1_hit = (xbrk0_goto1_hit) | (xbrk1_goto1_hit) | (xbrk2_goto1_hit) | (xbrk3_goto1_hit);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
xbrk_break <= 0;
else if (E_cpu_addr_en)
xbrk_break <= xbrk_break_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceon <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceon <= xbrk_ton_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_traceoff <= 0;
else if (E_cpu_addr_en)
E_xbrk_traceoff <= xbrk_toff_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_trigout <= 0;
else if (E_cpu_addr_en)
E_xbrk_trigout <= xbrk_tout_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto0 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto0 <= xbrk_goto0_hit;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_xbrk_goto1 <= 0;
else if (E_cpu_addr_en)
E_xbrk_goto1 <= xbrk_goto1_hit;
end
assign xbrk_traceon = 1'b0;
assign xbrk_traceoff = 1'b0;
assign xbrk_trigout = 1'b0;
assign xbrk_goto0 = 1'b0;
assign xbrk_goto1 = 1'b0;
assign xbrk0_armed = (xbrk_ctrl0[4] & trigger_state_0) ||
(xbrk_ctrl0[5] & trigger_state_1);
assign xbrk1_armed = (xbrk_ctrl1[4] & trigger_state_0) ||
(xbrk_ctrl1[5] & trigger_state_1);
assign xbrk2_armed = (xbrk_ctrl2[4] & trigger_state_0) ||
(xbrk_ctrl2[5] & trigger_state_1);
assign xbrk3_armed = (xbrk_ctrl3[4] & trigger_state_0) ||
(xbrk_ctrl3[5] & trigger_state_1);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_dbrk (
// inputs:
E_st_data,
av_ld_data_aligned_filtered,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugack,
reset_n,
// outputs:
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
dbrk_break,
dbrk_goto0,
dbrk_goto1,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dbrk_trigout
)
;
output [ 24: 0] cpu_d_address;
output cpu_d_read;
output [ 31: 0] cpu_d_readdata;
output cpu_d_wait;
output cpu_d_write;
output [ 31: 0] cpu_d_writedata;
output dbrk_break;
output dbrk_goto0;
output dbrk_goto1;
output dbrk_traceme;
output dbrk_traceoff;
output dbrk_traceon;
output dbrk_trigout;
input [ 31: 0] E_st_data;
input [ 31: 0] av_ld_data_aligned_filtered;
input clk;
input [ 24: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugack;
input reset_n;
wire [ 24: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk0_armed;
wire dbrk0_break_pulse;
wire dbrk0_goto0;
wire dbrk0_goto1;
wire dbrk0_traceme;
wire dbrk0_traceoff;
wire dbrk0_traceon;
wire dbrk0_trigout;
wire dbrk1_armed;
wire dbrk1_break_pulse;
wire dbrk1_goto0;
wire dbrk1_goto1;
wire dbrk1_traceme;
wire dbrk1_traceoff;
wire dbrk1_traceon;
wire dbrk1_trigout;
wire dbrk2_armed;
wire dbrk2_break_pulse;
wire dbrk2_goto0;
wire dbrk2_goto1;
wire dbrk2_traceme;
wire dbrk2_traceoff;
wire dbrk2_traceon;
wire dbrk2_trigout;
wire dbrk3_armed;
wire dbrk3_break_pulse;
wire dbrk3_goto0;
wire dbrk3_goto1;
wire dbrk3_traceme;
wire dbrk3_traceoff;
wire dbrk3_traceon;
wire dbrk3_trigout;
reg dbrk_break;
reg dbrk_break_pulse;
wire [ 31: 0] dbrk_data;
reg dbrk_goto0;
reg dbrk_goto1;
reg dbrk_traceme;
reg dbrk_traceoff;
reg dbrk_traceon;
reg dbrk_trigout;
assign cpu_d_address = d_address;
assign cpu_d_readdata = av_ld_data_aligned_filtered;
assign cpu_d_read = d_read;
assign cpu_d_writedata = E_st_data;
assign cpu_d_write = d_write;
assign cpu_d_wait = d_waitrequest;
assign dbrk_data = cpu_d_write ? cpu_d_writedata : cpu_d_readdata;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbrk_break <= 0;
else
dbrk_break <= dbrk_break ? ~debugack
: dbrk_break_pulse;
end
assign dbrk0_armed = 1'b0;
assign dbrk0_trigout = 1'b0;
assign dbrk0_break_pulse = 1'b0;
assign dbrk0_traceoff = 1'b0;
assign dbrk0_traceon = 1'b0;
assign dbrk0_traceme = 1'b0;
assign dbrk0_goto0 = 1'b0;
assign dbrk0_goto1 = 1'b0;
assign dbrk1_armed = 1'b0;
assign dbrk1_trigout = 1'b0;
assign dbrk1_break_pulse = 1'b0;
assign dbrk1_traceoff = 1'b0;
assign dbrk1_traceon = 1'b0;
assign dbrk1_traceme = 1'b0;
assign dbrk1_goto0 = 1'b0;
assign dbrk1_goto1 = 1'b0;
assign dbrk2_armed = 1'b0;
assign dbrk2_trigout = 1'b0;
assign dbrk2_break_pulse = 1'b0;
assign dbrk2_traceoff = 1'b0;
assign dbrk2_traceon = 1'b0;
assign dbrk2_traceme = 1'b0;
assign dbrk2_goto0 = 1'b0;
assign dbrk2_goto1 = 1'b0;
assign dbrk3_armed = 1'b0;
assign dbrk3_trigout = 1'b0;
assign dbrk3_break_pulse = 1'b0;
assign dbrk3_traceoff = 1'b0;
assign dbrk3_traceon = 1'b0;
assign dbrk3_traceme = 1'b0;
assign dbrk3_goto0 = 1'b0;
assign dbrk3_goto1 = 1'b0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
dbrk_trigout <= 0;
dbrk_break_pulse <= 0;
dbrk_traceoff <= 0;
dbrk_traceon <= 0;
dbrk_traceme <= 0;
dbrk_goto0 <= 0;
dbrk_goto1 <= 0;
end
else
begin
dbrk_trigout <= dbrk0_trigout | dbrk1_trigout | dbrk2_trigout | dbrk3_trigout;
dbrk_break_pulse <= dbrk0_break_pulse | dbrk1_break_pulse | dbrk2_break_pulse | dbrk3_break_pulse;
dbrk_traceoff <= dbrk0_traceoff | dbrk1_traceoff | dbrk2_traceoff | dbrk3_traceoff;
dbrk_traceon <= dbrk0_traceon | dbrk1_traceon | dbrk2_traceon | dbrk3_traceon;
dbrk_traceme <= dbrk0_traceme | dbrk1_traceme | dbrk2_traceme | dbrk3_traceme;
dbrk_goto0 <= dbrk0_goto0 | dbrk1_goto0 | dbrk2_goto0 | dbrk3_goto0;
dbrk_goto1 <= dbrk0_goto1 | dbrk1_goto1 | dbrk2_goto1 | dbrk3_goto1;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_itrace (
// inputs:
clk,
dbrk_traceoff,
dbrk_traceon,
jdo,
jrst_n,
take_action_tracectrl,
trc_enb,
xbrk_traceoff,
xbrk_traceon,
xbrk_wrap_traceoff,
// outputs:
dct_buffer,
dct_count,
itm,
trc_ctrl,
trc_on
)
;
output [ 29: 0] dct_buffer;
output [ 3: 0] dct_count;
output [ 35: 0] itm;
output [ 15: 0] trc_ctrl;
output trc_on;
input clk;
input dbrk_traceoff;
input dbrk_traceon;
input [ 15: 0] jdo;
input jrst_n;
input take_action_tracectrl;
input trc_enb;
input xbrk_traceoff;
input xbrk_traceon;
input xbrk_wrap_traceoff;
wire curr_pid;
reg [ 29: 0] dct_buffer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] dct_code;
reg [ 3: 0] dct_count /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire dct_is_taken;
wire [ 31: 0] excaddr;
wire instr_retired;
wire is_advanced_exception;
wire is_cond_dct;
wire is_dct;
wire is_exception_no_break;
wire is_fast_tlb_miss_exception;
wire is_idct;
reg [ 35: 0] itm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire not_in_debug_mode;
reg pending_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 31: 0] pending_excaddr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_exctype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] pending_frametype /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg pending_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg prev_pid_valid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_dct_outcome_in_sync;
wire record_itrace;
wire [ 31: 0] retired_pcb;
reg snapped_curr_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg snapped_prev_pid /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 1: 0] sync_code;
wire [ 6: 0] sync_interval;
wire sync_pending;
reg [ 6: 0] sync_timer /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 6: 0] sync_timer_next;
reg trc_clear /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 15: 0] trc_ctrl;
reg [ 10: 0] trc_ctrl_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire trc_on;
assign is_cond_dct = 1'b0;
assign is_dct = 1'b0;
assign dct_is_taken = 1'b0;
assign is_idct = 1'b0;
assign retired_pcb = 32'b0;
assign not_in_debug_mode = 1'b0;
assign instr_retired = 1'b0;
assign is_advanced_exception = 1'b0;
assign is_exception_no_break = 1'b0;
assign is_fast_tlb_miss_exception = 1'b0;
assign curr_pid = 1'b0;
assign excaddr = 32'b0;
assign sync_code = trc_ctrl[3 : 2];
assign sync_interval = { sync_code[1] & sync_code[0], 1'b0, sync_code[1] & ~sync_code[0], 1'b0, ~sync_code[1] & sync_code[0], 2'b00 };
assign sync_pending = sync_timer == 0;
assign record_dct_outcome_in_sync = dct_is_taken & sync_pending;
assign sync_timer_next = sync_pending ? sync_timer : (sync_timer - 1);
assign record_itrace = trc_on & trc_ctrl[4];
assign dct_code = {is_cond_dct, dct_is_taken};
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
trc_clear <= 0;
else
trc_clear <= ~trc_enb &
take_action_tracectrl & jdo[4];
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else if (trc_clear || (!0 && !0))
begin
itm <= 0;
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= 0;
pending_frametype <= 4'b0000;
pending_exctype <= 1'b0;
pending_excaddr <= 0;
prev_pid <= 0;
prev_pid_valid <= 0;
snapped_pid <= 0;
snapped_curr_pid <= 0;
snapped_prev_pid <= 0;
pending_curr_pid <= 0;
pending_prev_pid <= 0;
end
else
begin
if (!prev_pid_valid)
begin
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if ((curr_pid != prev_pid) & prev_pid_valid & !snapped_pid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
prev_pid <= curr_pid;
prev_pid_valid <= 1;
end
if (instr_retired | is_advanced_exception)
begin
if (~record_itrace)
pending_frametype <= 4'b1010;
else if (is_exception_no_break)
begin
pending_frametype <= 4'b0010;
pending_excaddr <= excaddr;
if (is_fast_tlb_miss_exception)
pending_exctype <= 1'b1;
else
pending_exctype <= 1'b0;
end
else if (is_idct)
pending_frametype <= 4'b1001;
else if (record_dct_outcome_in_sync)
pending_frametype <= 4'b1000;
else if (!is_dct & snapped_pid)
begin
pending_frametype <= 4'b0011;
pending_curr_pid <= snapped_curr_pid;
pending_prev_pid <= snapped_prev_pid;
snapped_pid <= 0;
end
else
pending_frametype <= 4'b0000;
if ((dct_count != 0) &
(~record_itrace |
is_exception_no_break |
is_idct |
record_dct_outcome_in_sync |
(!is_dct & snapped_pid)))
begin
itm <= {4'b0001, dct_buffer, 2'b00};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
begin
if (record_itrace & (is_dct & (dct_count != 4'd15)) & ~record_dct_outcome_in_sync & ~is_advanced_exception)
begin
dct_buffer <= {dct_code, dct_buffer[29 : 2]};
dct_count <= dct_count + 1;
end
if (record_itrace & (pending_frametype == 4'b0010))
itm <= {4'b0010, pending_excaddr[31 : 1], pending_exctype};
else if (record_itrace & (
(pending_frametype == 4'b1000) |
(pending_frametype == 4'b1010) |
(pending_frametype == 4'b1001)))
begin
itm <= {pending_frametype, retired_pcb};
sync_timer <= sync_interval;
if (0 &
((pending_frametype == 4'b1000) | (pending_frametype == 4'b1010)) &
!snapped_pid & prev_pid_valid)
begin
snapped_pid <= 1;
snapped_curr_pid <= curr_pid;
snapped_prev_pid <= prev_pid;
end
end
else if (record_itrace &
0 & (pending_frametype == 4'b0011))
itm <= {4'b0011, 2'b00, pending_prev_pid, 2'b00, pending_curr_pid};
else if (record_itrace & is_dct)
begin
if (dct_count == 4'd15)
begin
itm <= {4'b0001, dct_code, dct_buffer};
dct_buffer <= 0;
dct_count <= 0;
sync_timer <= sync_timer_next;
end
else
itm <= 4'b0000;
end
else
itm <= {4'b0000, 32'b0};
end
end
else
itm <= {4'b0000, 32'b0};
end
end
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_ctrl_reg[0] <= 1'b0;
trc_ctrl_reg[1] <= 1'b0;
trc_ctrl_reg[3 : 2] <= 2'b00;
trc_ctrl_reg[4] <= 1'b0;
trc_ctrl_reg[7 : 5] <= 3'b000;
trc_ctrl_reg[8] <= 0;
trc_ctrl_reg[9] <= 1'b0;
trc_ctrl_reg[10] <= 1'b0;
end
else if (take_action_tracectrl)
begin
trc_ctrl_reg[0] <= jdo[5];
trc_ctrl_reg[1] <= jdo[6];
trc_ctrl_reg[3 : 2] <= jdo[8 : 7];
trc_ctrl_reg[4] <= jdo[9];
trc_ctrl_reg[9] <= jdo[14];
trc_ctrl_reg[10] <= jdo[2];
if (0)
trc_ctrl_reg[7 : 5] <= jdo[12 : 10];
if (0 & 0)
trc_ctrl_reg[8] <= jdo[13];
end
else if (xbrk_wrap_traceoff)
begin
trc_ctrl_reg[1] <= 0;
trc_ctrl_reg[0] <= 0;
end
else if (dbrk_traceoff | xbrk_traceoff)
trc_ctrl_reg[1] <= 0;
else if (trc_ctrl_reg[0] &
(dbrk_traceon | xbrk_traceon))
trc_ctrl_reg[1] <= 1;
end
assign trc_ctrl = (0 || 0) ? {6'b000000, trc_ctrl_reg} : 0;
assign trc_on = trc_ctrl[1] & (trc_ctrl[9] | not_in_debug_mode);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_td_mode (
// inputs:
ctrl,
// outputs:
td_mode
)
;
output [ 3: 0] td_mode;
input [ 8: 0] ctrl;
wire [ 2: 0] ctrl_bits_for_mux;
reg [ 3: 0] td_mode;
assign ctrl_bits_for_mux = ctrl[7 : 5];
always @(ctrl_bits_for_mux)
begin
case (ctrl_bits_for_mux)
3'b000: begin
td_mode = 4'b0000;
end // 3'b000
3'b001: begin
td_mode = 4'b1000;
end // 3'b001
3'b010: begin
td_mode = 4'b0100;
end // 3'b010
3'b011: begin
td_mode = 4'b1100;
end // 3'b011
3'b100: begin
td_mode = 4'b0010;
end // 3'b100
3'b101: begin
td_mode = 4'b1010;
end // 3'b101
3'b110: begin
td_mode = 4'b0101;
end // 3'b110
3'b111: begin
td_mode = 4'b1111;
end // 3'b111
endcase // ctrl_bits_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_dtrace (
// inputs:
clk,
cpu_d_address,
cpu_d_read,
cpu_d_readdata,
cpu_d_wait,
cpu_d_write,
cpu_d_writedata,
jrst_n,
trc_ctrl,
// outputs:
atm,
dtm
)
;
output [ 35: 0] atm;
output [ 35: 0] dtm;
input clk;
input [ 24: 0] cpu_d_address;
input cpu_d_read;
input [ 31: 0] cpu_d_readdata;
input cpu_d_wait;
input cpu_d_write;
input [ 31: 0] cpu_d_writedata;
input jrst_n;
input [ 15: 0] trc_ctrl;
reg [ 35: 0] atm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 31: 0] cpu_d_address_0_padded;
wire [ 31: 0] cpu_d_readdata_0_padded;
wire [ 31: 0] cpu_d_writedata_0_padded;
reg [ 35: 0] dtm /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire record_load_addr;
wire record_load_data;
wire record_store_addr;
wire record_store_data;
wire [ 3: 0] td_mode_trc_ctrl;
assign cpu_d_writedata_0_padded = cpu_d_writedata | 32'b0;
assign cpu_d_readdata_0_padded = cpu_d_readdata | 32'b0;
assign cpu_d_address_0_padded = cpu_d_address | 32'b0;
//video_sys_CPU_nios2_oci_trc_ctrl_td_mode, which is an e_instance
video_sys_CPU_nios2_oci_td_mode video_sys_CPU_nios2_oci_trc_ctrl_td_mode
(
.ctrl (trc_ctrl[8 : 0]),
.td_mode (td_mode_trc_ctrl)
);
assign {record_load_addr, record_store_addr,
record_load_data, record_store_data} = td_mode_trc_ctrl;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
atm <= 0;
dtm <= 0;
end
else if (0)
begin
if (cpu_d_write & ~cpu_d_wait & record_store_addr)
atm <= {4'b0101, cpu_d_address_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_addr)
atm <= {4'b0100, cpu_d_address_0_padded};
else
atm <= {4'b0000, cpu_d_address_0_padded};
if (cpu_d_write & ~cpu_d_wait & record_store_data)
dtm <= {4'b0111, cpu_d_writedata_0_padded};
else if (cpu_d_read & ~cpu_d_wait & record_load_data)
dtm <= {4'b0110, cpu_d_readdata_0_padded};
else
dtm <= {4'b0000, cpu_d_readdata_0_padded};
end
else
begin
atm <= 0;
dtm <= 0;
end
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_compute_tm_count (
// inputs:
atm_valid,
dtm_valid,
itm_valid,
// outputs:
compute_tm_count
)
;
output [ 1: 0] compute_tm_count;
input atm_valid;
input dtm_valid;
input itm_valid;
reg [ 1: 0] compute_tm_count;
wire [ 2: 0] switch_for_mux;
assign switch_for_mux = {itm_valid, atm_valid, dtm_valid};
always @(switch_for_mux)
begin
case (switch_for_mux)
3'b000: begin
compute_tm_count = 0;
end // 3'b000
3'b001: begin
compute_tm_count = 1;
end // 3'b001
3'b010: begin
compute_tm_count = 1;
end // 3'b010
3'b011: begin
compute_tm_count = 2;
end // 3'b011
3'b100: begin
compute_tm_count = 1;
end // 3'b100
3'b101: begin
compute_tm_count = 2;
end // 3'b101
3'b110: begin
compute_tm_count = 2;
end // 3'b110
3'b111: begin
compute_tm_count = 3;
end // 3'b111
endcase // switch_for_mux
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_fifowp_inc (
// inputs:
free2,
free3,
tm_count,
// outputs:
fifowp_inc
)
;
output [ 3: 0] fifowp_inc;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 3: 0] fifowp_inc;
always @(free2 or free3 or tm_count)
begin
if (free3 & (tm_count == 3))
fifowp_inc = 3;
else if (free2 & (tm_count >= 2))
fifowp_inc = 2;
else if (tm_count >= 1)
fifowp_inc = 1;
else
fifowp_inc = 0;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_fifocount_inc (
// inputs:
empty,
free2,
free3,
tm_count,
// outputs:
fifocount_inc
)
;
output [ 4: 0] fifocount_inc;
input empty;
input free2;
input free3;
input [ 1: 0] tm_count;
reg [ 4: 0] fifocount_inc;
always @(empty or free2 or free3 or tm_count)
begin
if (empty)
fifocount_inc = tm_count[1 : 0];
else if (free3 & (tm_count == 3))
fifocount_inc = 2;
else if (free2 & (tm_count >= 2))
fifocount_inc = 1;
else if (tm_count >= 1)
fifocount_inc = 0;
else
fifocount_inc = {5{1'b1}};
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_fifo (
// inputs:
atm,
clk,
dbrk_traceme,
dbrk_traceoff,
dbrk_traceon,
dct_buffer,
dct_count,
dtm,
itm,
jrst_n,
reset_n,
test_ending,
test_has_ended,
trc_on,
// outputs:
tw
)
;
output [ 35: 0] tw;
input [ 35: 0] atm;
input clk;
input dbrk_traceme;
input dbrk_traceoff;
input dbrk_traceon;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input [ 35: 0] dtm;
input [ 35: 0] itm;
input jrst_n;
input reset_n;
input test_ending;
input test_has_ended;
input trc_on;
wire atm_valid;
wire [ 1: 0] compute_tm_count_tm_count;
wire dtm_valid;
wire empty;
reg [ 35: 0] fifo_0;
wire fifo_0_enable;
wire [ 35: 0] fifo_0_mux;
reg [ 35: 0] fifo_1;
reg [ 35: 0] fifo_10;
wire fifo_10_enable;
wire [ 35: 0] fifo_10_mux;
reg [ 35: 0] fifo_11;
wire fifo_11_enable;
wire [ 35: 0] fifo_11_mux;
reg [ 35: 0] fifo_12;
wire fifo_12_enable;
wire [ 35: 0] fifo_12_mux;
reg [ 35: 0] fifo_13;
wire fifo_13_enable;
wire [ 35: 0] fifo_13_mux;
reg [ 35: 0] fifo_14;
wire fifo_14_enable;
wire [ 35: 0] fifo_14_mux;
reg [ 35: 0] fifo_15;
wire fifo_15_enable;
wire [ 35: 0] fifo_15_mux;
wire fifo_1_enable;
wire [ 35: 0] fifo_1_mux;
reg [ 35: 0] fifo_2;
wire fifo_2_enable;
wire [ 35: 0] fifo_2_mux;
reg [ 35: 0] fifo_3;
wire fifo_3_enable;
wire [ 35: 0] fifo_3_mux;
reg [ 35: 0] fifo_4;
wire fifo_4_enable;
wire [ 35: 0] fifo_4_mux;
reg [ 35: 0] fifo_5;
wire fifo_5_enable;
wire [ 35: 0] fifo_5_mux;
reg [ 35: 0] fifo_6;
wire fifo_6_enable;
wire [ 35: 0] fifo_6_mux;
reg [ 35: 0] fifo_7;
wire fifo_7_enable;
wire [ 35: 0] fifo_7_mux;
reg [ 35: 0] fifo_8;
wire fifo_8_enable;
wire [ 35: 0] fifo_8_mux;
reg [ 35: 0] fifo_9;
wire fifo_9_enable;
wire [ 35: 0] fifo_9_mux;
wire [ 35: 0] fifo_read_mux;
reg [ 4: 0] fifocount /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 4: 0] fifocount_inc_fifocount;
wire [ 35: 0] fifohead;
reg [ 3: 0] fiforp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg [ 3: 0] fifowp /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 3: 0] fifowp1;
wire [ 3: 0] fifowp2;
wire [ 3: 0] fifowp_inc_fifowp;
wire free2;
wire free3;
wire itm_valid;
reg ovf_pending /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 35: 0] ovr_pending_atm;
wire [ 35: 0] ovr_pending_dtm;
wire [ 1: 0] tm_count;
wire tm_count_ge1;
wire tm_count_ge2;
wire tm_count_ge3;
wire trc_this;
wire [ 35: 0] tw;
assign trc_this = trc_on | (dbrk_traceon & ~dbrk_traceoff) | dbrk_traceme;
assign itm_valid = |itm[35 : 32];
assign atm_valid = |atm[35 : 32] & trc_this;
assign dtm_valid = |dtm[35 : 32] & trc_this;
assign free2 = ~fifocount[4];
assign free3 = ~fifocount[4] & ~&fifocount[3 : 0];
assign empty = ~|fifocount;
assign fifowp1 = fifowp + 1;
assign fifowp2 = fifowp + 2;
//video_sys_CPU_nios2_oci_compute_tm_count_tm_count, which is an e_instance
video_sys_CPU_nios2_oci_compute_tm_count video_sys_CPU_nios2_oci_compute_tm_count_tm_count
(
.atm_valid (atm_valid),
.compute_tm_count (compute_tm_count_tm_count),
.dtm_valid (dtm_valid),
.itm_valid (itm_valid)
);
assign tm_count = compute_tm_count_tm_count;
//video_sys_CPU_nios2_oci_fifowp_inc_fifowp, which is an e_instance
video_sys_CPU_nios2_oci_fifowp_inc video_sys_CPU_nios2_oci_fifowp_inc_fifowp
(
.fifowp_inc (fifowp_inc_fifowp),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//video_sys_CPU_nios2_oci_fifocount_inc_fifocount, which is an e_instance
video_sys_CPU_nios2_oci_fifocount_inc video_sys_CPU_nios2_oci_fifocount_inc_fifocount
(
.empty (empty),
.fifocount_inc (fifocount_inc_fifocount),
.free2 (free2),
.free3 (free3),
.tm_count (tm_count)
);
//the_video_sys_CPU_oci_test_bench, which is an e_instance
video_sys_CPU_oci_test_bench the_video_sys_CPU_oci_test_bench
(
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.test_ending (test_ending),
.test_has_ended (test_has_ended)
);
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
fiforp <= 0;
fifowp <= 0;
fifocount <= 0;
ovf_pending <= 1;
end
else
begin
fifowp <= fifowp + fifowp_inc_fifowp;
fifocount <= fifocount + fifocount_inc_fifocount;
if (~empty)
fiforp <= fiforp + 1;
if (~trc_this || (~free2 & tm_count[1]) || (~free3 & (&tm_count)))
ovf_pending <= 1;
else if (atm_valid | dtm_valid)
ovf_pending <= 0;
end
end
assign fifohead = fifo_read_mux;
assign tw = 0 ? { (empty ? 4'h0 : fifohead[35 : 32]), fifohead[31 : 0]} : itm;
assign fifo_0_enable = ((fifowp == 4'd0) && tm_count_ge1) || (free2 && (fifowp1== 4'd0) && tm_count_ge2) ||(free3 && (fifowp2== 4'd0) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_0 <= 0;
else if (fifo_0_enable)
fifo_0 <= fifo_0_mux;
end
assign fifo_0_mux = (((fifowp == 4'd0) && itm_valid))? itm :
(((fifowp == 4'd0) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd0) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd0) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd0) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_1_enable = ((fifowp == 4'd1) && tm_count_ge1) || (free2 && (fifowp1== 4'd1) && tm_count_ge2) ||(free3 && (fifowp2== 4'd1) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_1 <= 0;
else if (fifo_1_enable)
fifo_1 <= fifo_1_mux;
end
assign fifo_1_mux = (((fifowp == 4'd1) && itm_valid))? itm :
(((fifowp == 4'd1) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd1) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd1) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd1) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_2_enable = ((fifowp == 4'd2) && tm_count_ge1) || (free2 && (fifowp1== 4'd2) && tm_count_ge2) ||(free3 && (fifowp2== 4'd2) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_2 <= 0;
else if (fifo_2_enable)
fifo_2 <= fifo_2_mux;
end
assign fifo_2_mux = (((fifowp == 4'd2) && itm_valid))? itm :
(((fifowp == 4'd2) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd2) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd2) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd2) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_3_enable = ((fifowp == 4'd3) && tm_count_ge1) || (free2 && (fifowp1== 4'd3) && tm_count_ge2) ||(free3 && (fifowp2== 4'd3) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_3 <= 0;
else if (fifo_3_enable)
fifo_3 <= fifo_3_mux;
end
assign fifo_3_mux = (((fifowp == 4'd3) && itm_valid))? itm :
(((fifowp == 4'd3) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd3) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd3) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd3) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_4_enable = ((fifowp == 4'd4) && tm_count_ge1) || (free2 && (fifowp1== 4'd4) && tm_count_ge2) ||(free3 && (fifowp2== 4'd4) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_4 <= 0;
else if (fifo_4_enable)
fifo_4 <= fifo_4_mux;
end
assign fifo_4_mux = (((fifowp == 4'd4) && itm_valid))? itm :
(((fifowp == 4'd4) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd4) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd4) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd4) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_5_enable = ((fifowp == 4'd5) && tm_count_ge1) || (free2 && (fifowp1== 4'd5) && tm_count_ge2) ||(free3 && (fifowp2== 4'd5) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_5 <= 0;
else if (fifo_5_enable)
fifo_5 <= fifo_5_mux;
end
assign fifo_5_mux = (((fifowp == 4'd5) && itm_valid))? itm :
(((fifowp == 4'd5) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd5) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd5) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd5) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_6_enable = ((fifowp == 4'd6) && tm_count_ge1) || (free2 && (fifowp1== 4'd6) && tm_count_ge2) ||(free3 && (fifowp2== 4'd6) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_6 <= 0;
else if (fifo_6_enable)
fifo_6 <= fifo_6_mux;
end
assign fifo_6_mux = (((fifowp == 4'd6) && itm_valid))? itm :
(((fifowp == 4'd6) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd6) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd6) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd6) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_7_enable = ((fifowp == 4'd7) && tm_count_ge1) || (free2 && (fifowp1== 4'd7) && tm_count_ge2) ||(free3 && (fifowp2== 4'd7) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_7 <= 0;
else if (fifo_7_enable)
fifo_7 <= fifo_7_mux;
end
assign fifo_7_mux = (((fifowp == 4'd7) && itm_valid))? itm :
(((fifowp == 4'd7) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd7) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd7) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd7) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_8_enable = ((fifowp == 4'd8) && tm_count_ge1) || (free2 && (fifowp1== 4'd8) && tm_count_ge2) ||(free3 && (fifowp2== 4'd8) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_8 <= 0;
else if (fifo_8_enable)
fifo_8 <= fifo_8_mux;
end
assign fifo_8_mux = (((fifowp == 4'd8) && itm_valid))? itm :
(((fifowp == 4'd8) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd8) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd8) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd8) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_9_enable = ((fifowp == 4'd9) && tm_count_ge1) || (free2 && (fifowp1== 4'd9) && tm_count_ge2) ||(free3 && (fifowp2== 4'd9) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_9 <= 0;
else if (fifo_9_enable)
fifo_9 <= fifo_9_mux;
end
assign fifo_9_mux = (((fifowp == 4'd9) && itm_valid))? itm :
(((fifowp == 4'd9) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd9) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd9) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd9) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_10_enable = ((fifowp == 4'd10) && tm_count_ge1) || (free2 && (fifowp1== 4'd10) && tm_count_ge2) ||(free3 && (fifowp2== 4'd10) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_10 <= 0;
else if (fifo_10_enable)
fifo_10 <= fifo_10_mux;
end
assign fifo_10_mux = (((fifowp == 4'd10) && itm_valid))? itm :
(((fifowp == 4'd10) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd10) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd10) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd10) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_11_enable = ((fifowp == 4'd11) && tm_count_ge1) || (free2 && (fifowp1== 4'd11) && tm_count_ge2) ||(free3 && (fifowp2== 4'd11) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_11 <= 0;
else if (fifo_11_enable)
fifo_11 <= fifo_11_mux;
end
assign fifo_11_mux = (((fifowp == 4'd11) && itm_valid))? itm :
(((fifowp == 4'd11) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd11) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd11) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd11) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_12_enable = ((fifowp == 4'd12) && tm_count_ge1) || (free2 && (fifowp1== 4'd12) && tm_count_ge2) ||(free3 && (fifowp2== 4'd12) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_12 <= 0;
else if (fifo_12_enable)
fifo_12 <= fifo_12_mux;
end
assign fifo_12_mux = (((fifowp == 4'd12) && itm_valid))? itm :
(((fifowp == 4'd12) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd12) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd12) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd12) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_13_enable = ((fifowp == 4'd13) && tm_count_ge1) || (free2 && (fifowp1== 4'd13) && tm_count_ge2) ||(free3 && (fifowp2== 4'd13) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_13 <= 0;
else if (fifo_13_enable)
fifo_13 <= fifo_13_mux;
end
assign fifo_13_mux = (((fifowp == 4'd13) && itm_valid))? itm :
(((fifowp == 4'd13) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd13) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd13) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd13) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_14_enable = ((fifowp == 4'd14) && tm_count_ge1) || (free2 && (fifowp1== 4'd14) && tm_count_ge2) ||(free3 && (fifowp2== 4'd14) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_14 <= 0;
else if (fifo_14_enable)
fifo_14 <= fifo_14_mux;
end
assign fifo_14_mux = (((fifowp == 4'd14) && itm_valid))? itm :
(((fifowp == 4'd14) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd14) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd14) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd14) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign fifo_15_enable = ((fifowp == 4'd15) && tm_count_ge1) || (free2 && (fifowp1== 4'd15) && tm_count_ge2) ||(free3 && (fifowp2== 4'd15) && tm_count_ge3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_15 <= 0;
else if (fifo_15_enable)
fifo_15 <= fifo_15_mux;
end
assign fifo_15_mux = (((fifowp == 4'd15) && itm_valid))? itm :
(((fifowp == 4'd15) && atm_valid))? ovr_pending_atm :
(((fifowp == 4'd15) && dtm_valid))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & atm_valid)))? ovr_pending_atm :
(((fifowp1 == 4'd15) && (free2 & itm_valid & dtm_valid)))? ovr_pending_dtm :
(((fifowp1 == 4'd15) && (free2 & atm_valid & dtm_valid)))? ovr_pending_dtm :
ovr_pending_dtm;
assign tm_count_ge1 = |tm_count;
assign tm_count_ge2 = tm_count[1];
assign tm_count_ge3 = &tm_count;
assign ovr_pending_atm = {ovf_pending, atm[34 : 0]};
assign ovr_pending_dtm = {ovf_pending, dtm[34 : 0]};
assign fifo_read_mux = (fiforp == 4'd0)? fifo_0 :
(fiforp == 4'd1)? fifo_1 :
(fiforp == 4'd2)? fifo_2 :
(fiforp == 4'd3)? fifo_3 :
(fiforp == 4'd4)? fifo_4 :
(fiforp == 4'd5)? fifo_5 :
(fiforp == 4'd6)? fifo_6 :
(fiforp == 4'd7)? fifo_7 :
(fiforp == 4'd8)? fifo_8 :
(fiforp == 4'd9)? fifo_9 :
(fiforp == 4'd10)? fifo_10 :
(fiforp == 4'd11)? fifo_11 :
(fiforp == 4'd12)? fifo_12 :
(fiforp == 4'd13)? fifo_13 :
(fiforp == 4'd14)? fifo_14 :
fifo_15;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_pib (
// inputs:
clk,
clkx2,
jrst_n,
tw,
// outputs:
tr_clk,
tr_data
)
;
output tr_clk;
output [ 17: 0] tr_data;
input clk;
input clkx2;
input jrst_n;
input [ 35: 0] tw;
wire phase;
wire tr_clk;
reg tr_clk_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
wire [ 17: 0] tr_data;
reg [ 17: 0] tr_data_reg /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x1 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg x2 /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */;
assign phase = x1^x2;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
x1 <= 0;
else
x1 <= ~x1;
end
always @(posedge clkx2 or negedge jrst_n)
begin
if (jrst_n == 0)
begin
x2 <= 0;
tr_clk_reg <= 0;
tr_data_reg <= 0;
end
else
begin
x2 <= x1;
tr_clk_reg <= ~phase;
tr_data_reg <= phase ? tw[17 : 0] : tw[35 : 18];
end
end
assign tr_clk = 0 ? tr_clk_reg : 0;
assign tr_data = 0 ? tr_data_reg : 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_traceram_lpm_dram_bdp_component_module (
// inputs:
address_a,
address_b,
clock0,
clock1,
clocken0,
clocken1,
data_a,
data_b,
wren_a,
wren_b,
// outputs:
q_a,
q_b
)
;
parameter lpm_file = "UNUSED";
output [ 35: 0] q_a;
output [ 35: 0] q_b;
input [ 6: 0] address_a;
input [ 6: 0] address_b;
input clock0;
input clock1;
input clocken0;
input clocken1;
input [ 35: 0] data_a;
input [ 35: 0] data_b;
input wren_a;
input wren_b;
wire [ 35: 0] q_a;
wire [ 35: 0] q_b;
altsyncram the_altsyncram
(
.address_a (address_a),
.address_b (address_b),
.clock0 (clock0),
.clock1 (clock1),
.clocken0 (clocken0),
.clocken1 (clocken1),
.data_a (data_a),
.data_b (data_b),
.q_a (q_a),
.q_b (q_b),
.wren_a (wren_a),
.wren_b (wren_b)
);
defparam the_altsyncram.address_aclr_a = "NONE",
the_altsyncram.address_aclr_b = "NONE",
the_altsyncram.address_reg_b = "CLOCK1",
the_altsyncram.indata_aclr_a = "NONE",
the_altsyncram.indata_aclr_b = "NONE",
the_altsyncram.init_file = lpm_file,
the_altsyncram.intended_device_family = "CYCLONEII",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.numwords_a = 128,
the_altsyncram.numwords_b = 128,
the_altsyncram.operation_mode = "BIDIR_DUAL_PORT",
the_altsyncram.outdata_aclr_a = "NONE",
the_altsyncram.outdata_aclr_b = "NONE",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.outdata_reg_b = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "OLD_DATA",
the_altsyncram.width_a = 36,
the_altsyncram.width_b = 36,
the_altsyncram.widthad_a = 7,
the_altsyncram.widthad_b = 7,
the_altsyncram.wrcontrol_aclr_a = "NONE",
the_altsyncram.wrcontrol_aclr_b = "NONE";
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci_im (
// inputs:
clk,
jdo,
jrst_n,
reset_n,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_tracemem_a,
trc_ctrl,
tw,
// outputs:
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_enb,
trc_im_addr,
trc_wrap,
xbrk_wrap_traceoff
)
;
output tracemem_on;
output [ 35: 0] tracemem_trcdata;
output tracemem_tw;
output trc_enb;
output [ 6: 0] trc_im_addr;
output trc_wrap;
output xbrk_wrap_traceoff;
input clk;
input [ 37: 0] jdo;
input jrst_n;
input reset_n;
input take_action_tracectrl;
input take_action_tracemem_a;
input take_action_tracemem_b;
input take_no_action_tracemem_a;
input [ 15: 0] trc_ctrl;
input [ 35: 0] tw;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire trc_enb;
reg [ 6: 0] trc_im_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire [ 35: 0] trc_im_data;
reg [ 16: 0] trc_jtag_addr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=D101" */;
wire [ 35: 0] trc_jtag_data;
wire trc_on_chip;
reg trc_wrap /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire tw_valid;
wire [ 35: 0] unused_bdpram_port_q_a;
wire xbrk_wrap_traceoff;
assign trc_im_data = tw;
always @(posedge clk or negedge jrst_n)
begin
if (jrst_n == 0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (!0)
begin
trc_im_addr <= 0;
trc_wrap <= 0;
end
else if (take_action_tracectrl &&
(jdo[4] | jdo[3]))
begin
if (jdo[4])
trc_im_addr <= 0;
if (jdo[3])
trc_wrap <= 0;
end
else if (trc_enb & trc_on_chip & tw_valid)
begin
trc_im_addr <= trc_im_addr+1;
if (&trc_im_addr)
trc_wrap <= 1;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
trc_jtag_addr <= 0;
else if (take_action_tracemem_a ||
take_no_action_tracemem_a ||
take_action_tracemem_b)
trc_jtag_addr <= take_action_tracemem_a ?
jdo[35 : 19] :
trc_jtag_addr + 1;
end
assign trc_enb = trc_ctrl[0];
assign trc_on_chip = ~trc_ctrl[8];
assign tw_valid = |trc_im_data[35 : 32];
assign xbrk_wrap_traceoff = trc_ctrl[10] & trc_wrap;
assign tracemem_trcdata = (0) ?
trc_jtag_data : 0;
assign tracemem_tw = trc_wrap;
assign tracemem_on = trc_enb;
//video_sys_CPU_traceram_lpm_dram_bdp_component, which is an nios_tdp_ram
video_sys_CPU_traceram_lpm_dram_bdp_component_module video_sys_CPU_traceram_lpm_dram_bdp_component
(
.address_a (trc_im_addr),
.address_b (trc_jtag_addr),
.clock0 (clk),
.clock1 (clk),
.clocken0 (1'b1),
.clocken1 (1'b1),
.data_a (trc_im_data),
.data_b (jdo[36 : 1]),
.q_a (unused_bdpram_port_q_a),
.q_b (trc_jtag_data),
.wren_a (tw_valid & trc_enb),
.wren_b (take_action_tracemem_b)
);
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_performance_monitors
;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU_nios2_oci (
// inputs:
D_valid,
E_st_data,
E_valid,
F_pc,
address,
av_ld_data_aligned_filtered,
begintransfer,
byteenable,
chipselect,
clk,
d_address,
d_read,
d_waitrequest,
d_write,
debugaccess,
hbreak_enabled,
reset,
reset_n,
test_ending,
test_has_ended,
write,
writedata,
// outputs:
jtag_debug_module_debugaccess_to_roms,
oci_hbreak_req,
oci_ienable,
oci_single_step_mode,
readdata,
resetrequest
)
;
output jtag_debug_module_debugaccess_to_roms;
output oci_hbreak_req;
output [ 31: 0] oci_ienable;
output oci_single_step_mode;
output [ 31: 0] readdata;
output resetrequest;
input D_valid;
input [ 31: 0] E_st_data;
input E_valid;
input [ 22: 0] F_pc;
input [ 8: 0] address;
input [ 31: 0] av_ld_data_aligned_filtered;
input begintransfer;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input [ 24: 0] d_address;
input d_read;
input d_waitrequest;
input d_write;
input debugaccess;
input hbreak_enabled;
input reset;
input reset_n;
input test_ending;
input test_has_ended;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] MonDReg;
wire [ 35: 0] atm;
wire [ 31: 0] break_readreg;
wire clkx2;
wire [ 24: 0] cpu_d_address;
wire cpu_d_read;
wire [ 31: 0] cpu_d_readdata;
wire cpu_d_wait;
wire cpu_d_write;
wire [ 31: 0] cpu_d_writedata;
wire dbrk_break;
wire dbrk_goto0;
wire dbrk_goto1;
wire dbrk_hit0_latch;
wire dbrk_hit1_latch;
wire dbrk_hit2_latch;
wire dbrk_hit3_latch;
wire dbrk_traceme;
wire dbrk_traceoff;
wire dbrk_traceon;
wire dbrk_trigout;
wire [ 29: 0] dct_buffer;
wire [ 3: 0] dct_count;
wire debugack;
wire debugreq;
wire [ 35: 0] dtm;
wire dummy_sink;
wire [ 35: 0] itm;
wire [ 37: 0] jdo;
wire jrst_n;
wire jtag_debug_module_debugaccess_to_roms;
wire monitor_error;
wire monitor_go;
wire monitor_ready;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire [ 31: 0] oci_ram_readdata;
wire [ 31: 0] oci_reg_readdata;
wire oci_single_step_mode;
wire ocireg_ers;
wire ocireg_mrs;
wire [ 31: 0] readdata;
wire resetlatch;
wire resetrequest;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_ocireg;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire tr_clk;
wire [ 17: 0] tr_data;
wire tracemem_on;
wire [ 35: 0] tracemem_trcdata;
wire tracemem_tw;
wire [ 15: 0] trc_ctrl;
wire trc_enb;
wire [ 6: 0] trc_im_addr;
wire trc_on;
wire trc_wrap;
wire trigbrktype;
wire trigger_state_0;
wire trigger_state_1;
wire trigout;
wire [ 35: 0] tw;
wire xbrk_break;
wire [ 7: 0] xbrk_ctrl0;
wire [ 7: 0] xbrk_ctrl1;
wire [ 7: 0] xbrk_ctrl2;
wire [ 7: 0] xbrk_ctrl3;
wire xbrk_goto0;
wire xbrk_goto1;
wire xbrk_traceoff;
wire xbrk_traceon;
wire xbrk_trigout;
wire xbrk_wrap_traceoff;
video_sys_CPU_nios2_oci_debug the_video_sys_CPU_nios2_oci_debug
(
.clk (clk),
.dbrk_break (dbrk_break),
.debugack (debugack),
.debugreq (debugreq),
.hbreak_enabled (hbreak_enabled),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_hbreak_req (oci_hbreak_req),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset (reset),
.resetlatch (resetlatch),
.resetrequest (resetrequest),
.st_ready_test_idle (st_ready_test_idle),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocireg (take_action_ocireg),
.xbrk_break (xbrk_break)
);
video_sys_CPU_nios2_ocimem the_video_sys_CPU_nios2_ocimem
(
.MonDReg (MonDReg),
.address (address),
.begintransfer (begintransfer),
.byteenable (byteenable),
.chipselect (chipselect),
.clk (clk),
.debugaccess (debugaccess),
.jdo (jdo),
.jrst_n (jrst_n),
.oci_ram_readdata (oci_ram_readdata),
.resetrequest (resetrequest),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.write (write),
.writedata (writedata)
);
video_sys_CPU_nios2_avalon_reg the_video_sys_CPU_nios2_avalon_reg
(
.address (address),
.chipselect (chipselect),
.clk (clk),
.debugaccess (debugaccess),
.monitor_error (monitor_error),
.monitor_go (monitor_go),
.monitor_ready (monitor_ready),
.oci_ienable (oci_ienable),
.oci_reg_readdata (oci_reg_readdata),
.oci_single_step_mode (oci_single_step_mode),
.ocireg_ers (ocireg_ers),
.ocireg_mrs (ocireg_mrs),
.reset_n (reset_n),
.take_action_ocireg (take_action_ocireg),
.write (write),
.writedata (writedata)
);
video_sys_CPU_nios2_oci_break the_video_sys_CPU_nios2_oci_break
(
.break_readreg (break_readreg),
.clk (clk),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.trigbrktype (trigbrktype),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1)
);
video_sys_CPU_nios2_oci_xbrk the_video_sys_CPU_nios2_oci_xbrk
(
.D_valid (D_valid),
.E_valid (E_valid),
.F_pc (F_pc),
.clk (clk),
.reset_n (reset_n),
.trigger_state_0 (trigger_state_0),
.trigger_state_1 (trigger_state_1),
.xbrk_break (xbrk_break),
.xbrk_ctrl0 (xbrk_ctrl0),
.xbrk_ctrl1 (xbrk_ctrl1),
.xbrk_ctrl2 (xbrk_ctrl2),
.xbrk_ctrl3 (xbrk_ctrl3),
.xbrk_goto0 (xbrk_goto0),
.xbrk_goto1 (xbrk_goto1),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_trigout (xbrk_trigout)
);
video_sys_CPU_nios2_oci_dbrk the_video_sys_CPU_nios2_oci_dbrk
(
.E_st_data (E_st_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.dbrk_break (dbrk_break),
.dbrk_goto0 (dbrk_goto0),
.dbrk_goto1 (dbrk_goto1),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dbrk_trigout (dbrk_trigout),
.debugack (debugack),
.reset_n (reset_n)
);
video_sys_CPU_nios2_oci_itrace the_video_sys_CPU_nios2_oci_itrace
(
.clk (clk),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.itm (itm),
.jdo (jdo),
.jrst_n (jrst_n),
.take_action_tracectrl (take_action_tracectrl),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_on (trc_on),
.xbrk_traceoff (xbrk_traceoff),
.xbrk_traceon (xbrk_traceon),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
video_sys_CPU_nios2_oci_dtrace the_video_sys_CPU_nios2_oci_dtrace
(
.atm (atm),
.clk (clk),
.cpu_d_address (cpu_d_address),
.cpu_d_read (cpu_d_read),
.cpu_d_readdata (cpu_d_readdata),
.cpu_d_wait (cpu_d_wait),
.cpu_d_write (cpu_d_write),
.cpu_d_writedata (cpu_d_writedata),
.dtm (dtm),
.jrst_n (jrst_n),
.trc_ctrl (trc_ctrl)
);
video_sys_CPU_nios2_oci_fifo the_video_sys_CPU_nios2_oci_fifo
(
.atm (atm),
.clk (clk),
.dbrk_traceme (dbrk_traceme),
.dbrk_traceoff (dbrk_traceoff),
.dbrk_traceon (dbrk_traceon),
.dct_buffer (dct_buffer),
.dct_count (dct_count),
.dtm (dtm),
.itm (itm),
.jrst_n (jrst_n),
.reset_n (reset_n),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.trc_on (trc_on),
.tw (tw)
);
video_sys_CPU_nios2_oci_pib the_video_sys_CPU_nios2_oci_pib
(
.clk (clk),
.clkx2 (clkx2),
.jrst_n (jrst_n),
.tr_clk (tr_clk),
.tr_data (tr_data),
.tw (tw)
);
video_sys_CPU_nios2_oci_im the_video_sys_CPU_nios2_oci_im
(
.clk (clk),
.jdo (jdo),
.jrst_n (jrst_n),
.reset_n (reset_n),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_ctrl (trc_ctrl),
.trc_enb (trc_enb),
.trc_im_addr (trc_im_addr),
.trc_wrap (trc_wrap),
.tw (tw),
.xbrk_wrap_traceoff (xbrk_wrap_traceoff)
);
assign trigout = dbrk_trigout | xbrk_trigout;
assign readdata = address[8] ? oci_reg_readdata : oci_ram_readdata;
assign jtag_debug_module_debugaccess_to_roms = debugack;
video_sys_CPU_jtag_debug_module_wrapper the_video_sys_CPU_jtag_debug_module_wrapper
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.clk (clk),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.jdo (jdo),
.jrst_n (jrst_n),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.st_ready_test_idle (st_ready_test_idle),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1)
);
//dummy sink, which is an e_mux
assign dummy_sink = tr_clk |
tr_data |
trigout |
debugack;
assign debugreq = 0;
assign clkx2 = 0;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_CPU (
// inputs:
clk,
d_irq,
d_readdata,
d_waitrequest,
i_readdata,
i_waitrequest,
jtag_debug_module_address,
jtag_debug_module_begintransfer,
jtag_debug_module_byteenable,
jtag_debug_module_debugaccess,
jtag_debug_module_select,
jtag_debug_module_write,
jtag_debug_module_writedata,
reset_n,
// outputs:
d_address,
d_byteenable,
d_read,
d_write,
d_writedata,
i_address,
i_read,
jtag_debug_module_debugaccess_to_roms,
jtag_debug_module_readdata,
jtag_debug_module_resetrequest,
no_ci_readra
)
;
output [ 24: 0] d_address;
output [ 3: 0] d_byteenable;
output d_read;
output d_write;
output [ 31: 0] d_writedata;
output [ 24: 0] i_address;
output i_read;
output jtag_debug_module_debugaccess_to_roms;
output [ 31: 0] jtag_debug_module_readdata;
output jtag_debug_module_resetrequest;
output no_ci_readra;
input clk;
input [ 31: 0] d_irq;
input [ 31: 0] d_readdata;
input d_waitrequest;
input [ 31: 0] i_readdata;
input i_waitrequest;
input [ 8: 0] jtag_debug_module_address;
input jtag_debug_module_begintransfer;
input [ 3: 0] jtag_debug_module_byteenable;
input jtag_debug_module_debugaccess;
input jtag_debug_module_select;
input jtag_debug_module_write;
input [ 31: 0] jtag_debug_module_writedata;
input reset_n;
wire [ 1: 0] D_compare_op;
wire D_ctrl_alu_force_xor;
wire D_ctrl_alu_signed_comparison;
wire D_ctrl_alu_subtract;
wire D_ctrl_b_is_dst;
wire D_ctrl_br;
wire D_ctrl_br_cmp;
wire D_ctrl_br_uncond;
wire D_ctrl_break;
wire D_ctrl_crst;
wire D_ctrl_custom;
wire D_ctrl_custom_multi;
wire D_ctrl_exception;
wire D_ctrl_force_src2_zero;
wire D_ctrl_hi_imm16;
wire D_ctrl_ignore_dst;
wire D_ctrl_implicit_dst_eretaddr;
wire D_ctrl_implicit_dst_retaddr;
wire D_ctrl_jmp_direct;
wire D_ctrl_jmp_indirect;
wire D_ctrl_ld;
wire D_ctrl_ld_io;
wire D_ctrl_ld_non_io;
wire D_ctrl_ld_signed;
wire D_ctrl_logic;
wire D_ctrl_rdctl_inst;
wire D_ctrl_retaddr;
wire D_ctrl_rot_right;
wire D_ctrl_shift_logical;
wire D_ctrl_shift_right_arith;
wire D_ctrl_shift_rot;
wire D_ctrl_shift_rot_right;
wire D_ctrl_src2_choose_imm;
wire D_ctrl_st;
wire D_ctrl_uncond_cti_non_br;
wire D_ctrl_unsigned_lo_imm16;
wire D_ctrl_wrctl_inst;
wire [ 4: 0] D_dst_regnum;
wire [ 55: 0] D_inst;
reg [ 31: 0] D_iw /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 4: 0] D_iw_a;
wire [ 4: 0] D_iw_b;
wire [ 4: 0] D_iw_c;
wire [ 2: 0] D_iw_control_regnum;
wire [ 7: 0] D_iw_custom_n;
wire D_iw_custom_readra;
wire D_iw_custom_readrb;
wire D_iw_custom_writerc;
wire [ 15: 0] D_iw_imm16;
wire [ 25: 0] D_iw_imm26;
wire [ 4: 0] D_iw_imm5;
wire [ 1: 0] D_iw_memsz;
wire [ 5: 0] D_iw_op;
wire [ 5: 0] D_iw_opx;
wire [ 4: 0] D_iw_shift_imm5;
wire [ 4: 0] D_iw_trap_break_imm5;
wire [ 22: 0] D_jmp_direct_target_waddr;
wire [ 1: 0] D_logic_op;
wire [ 1: 0] D_logic_op_raw;
wire D_mem16;
wire D_mem32;
wire D_mem8;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_opx;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_rsv02;
wire D_op_rsv09;
wire D_op_rsv10;
wire D_op_rsv17;
wire D_op_rsv18;
wire D_op_rsv25;
wire D_op_rsv26;
wire D_op_rsv33;
wire D_op_rsv34;
wire D_op_rsv41;
wire D_op_rsv42;
wire D_op_rsv49;
wire D_op_rsv57;
wire D_op_rsv61;
wire D_op_rsv62;
wire D_op_rsv63;
wire D_op_rsvx00;
wire D_op_rsvx10;
wire D_op_rsvx15;
wire D_op_rsvx17;
wire D_op_rsvx21;
wire D_op_rsvx25;
wire D_op_rsvx33;
wire D_op_rsvx34;
wire D_op_rsvx35;
wire D_op_rsvx42;
wire D_op_rsvx43;
wire D_op_rsvx44;
wire D_op_rsvx47;
wire D_op_rsvx50;
wire D_op_rsvx51;
wire D_op_rsvx55;
wire D_op_rsvx56;
wire D_op_rsvx60;
wire D_op_rsvx63;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
reg D_valid;
wire [ 55: 0] D_vinst;
wire D_wr_dst_reg;
wire [ 31: 0] E_alu_result;
reg E_alu_sub;
wire [ 32: 0] E_arith_result;
wire [ 31: 0] E_arith_src1;
wire [ 31: 0] E_arith_src2;
wire E_ci_multi_stall;
wire [ 31: 0] E_ci_result;
wire E_cmp_result;
wire [ 31: 0] E_control_rd_data;
wire E_eq;
reg E_invert_arith_src_msb;
wire E_ld_stall;
wire [ 31: 0] E_logic_result;
wire E_logic_result_is_0;
wire E_lt;
wire [ 24: 0] E_mem_baddr;
wire [ 3: 0] E_mem_byte_en;
reg E_new_inst;
reg [ 4: 0] E_shift_rot_cnt;
wire [ 4: 0] E_shift_rot_cnt_nxt;
wire E_shift_rot_done;
wire E_shift_rot_fill_bit;
reg [ 31: 0] E_shift_rot_result;
wire [ 31: 0] E_shift_rot_result_nxt;
wire E_shift_rot_stall;
reg [ 31: 0] E_src1;
reg [ 31: 0] E_src2;
wire [ 31: 0] E_st_data;
wire E_st_stall;
wire E_stall;
reg E_valid;
wire [ 55: 0] E_vinst;
wire E_wrctl_bstatus;
wire E_wrctl_estatus;
wire E_wrctl_ienable;
wire E_wrctl_status;
wire [ 31: 0] F_av_iw;
wire [ 4: 0] F_av_iw_a;
wire [ 4: 0] F_av_iw_b;
wire [ 4: 0] F_av_iw_c;
wire [ 2: 0] F_av_iw_control_regnum;
wire [ 7: 0] F_av_iw_custom_n;
wire F_av_iw_custom_readra;
wire F_av_iw_custom_readrb;
wire F_av_iw_custom_writerc;
wire [ 15: 0] F_av_iw_imm16;
wire [ 25: 0] F_av_iw_imm26;
wire [ 4: 0] F_av_iw_imm5;
wire [ 1: 0] F_av_iw_memsz;
wire [ 5: 0] F_av_iw_op;
wire [ 5: 0] F_av_iw_opx;
wire [ 4: 0] F_av_iw_shift_imm5;
wire [ 4: 0] F_av_iw_trap_break_imm5;
wire F_av_mem16;
wire F_av_mem32;
wire F_av_mem8;
wire [ 55: 0] F_inst;
wire [ 31: 0] F_iw;
wire [ 4: 0] F_iw_a;
wire [ 4: 0] F_iw_b;
wire [ 4: 0] F_iw_c;
wire [ 2: 0] F_iw_control_regnum;
wire [ 7: 0] F_iw_custom_n;
wire F_iw_custom_readra;
wire F_iw_custom_readrb;
wire F_iw_custom_writerc;
wire [ 15: 0] F_iw_imm16;
wire [ 25: 0] F_iw_imm26;
wire [ 4: 0] F_iw_imm5;
wire [ 1: 0] F_iw_memsz;
wire [ 5: 0] F_iw_op;
wire [ 5: 0] F_iw_opx;
wire [ 4: 0] F_iw_shift_imm5;
wire [ 4: 0] F_iw_trap_break_imm5;
wire F_mem16;
wire F_mem32;
wire F_mem8;
wire F_op_add;
wire F_op_addi;
wire F_op_and;
wire F_op_andhi;
wire F_op_andi;
wire F_op_beq;
wire F_op_bge;
wire F_op_bgeu;
wire F_op_blt;
wire F_op_bltu;
wire F_op_bne;
wire F_op_br;
wire F_op_break;
wire F_op_bret;
wire F_op_call;
wire F_op_callr;
wire F_op_cmpeq;
wire F_op_cmpeqi;
wire F_op_cmpge;
wire F_op_cmpgei;
wire F_op_cmpgeu;
wire F_op_cmpgeui;
wire F_op_cmplt;
wire F_op_cmplti;
wire F_op_cmpltu;
wire F_op_cmpltui;
wire F_op_cmpne;
wire F_op_cmpnei;
wire F_op_crst;
wire F_op_custom;
wire F_op_div;
wire F_op_divu;
wire F_op_eret;
wire F_op_flushd;
wire F_op_flushda;
wire F_op_flushi;
wire F_op_flushp;
wire F_op_hbreak;
wire F_op_initd;
wire F_op_initda;
wire F_op_initi;
wire F_op_intr;
wire F_op_jmp;
wire F_op_jmpi;
wire F_op_ldb;
wire F_op_ldbio;
wire F_op_ldbu;
wire F_op_ldbuio;
wire F_op_ldh;
wire F_op_ldhio;
wire F_op_ldhu;
wire F_op_ldhuio;
wire F_op_ldl;
wire F_op_ldw;
wire F_op_ldwio;
wire F_op_mul;
wire F_op_muli;
wire F_op_mulxss;
wire F_op_mulxsu;
wire F_op_mulxuu;
wire F_op_nextpc;
wire F_op_nor;
wire F_op_opx;
wire F_op_or;
wire F_op_orhi;
wire F_op_ori;
wire F_op_rdctl;
wire F_op_rdprs;
wire F_op_ret;
wire F_op_rol;
wire F_op_roli;
wire F_op_ror;
wire F_op_rsv02;
wire F_op_rsv09;
wire F_op_rsv10;
wire F_op_rsv17;
wire F_op_rsv18;
wire F_op_rsv25;
wire F_op_rsv26;
wire F_op_rsv33;
wire F_op_rsv34;
wire F_op_rsv41;
wire F_op_rsv42;
wire F_op_rsv49;
wire F_op_rsv57;
wire F_op_rsv61;
wire F_op_rsv62;
wire F_op_rsv63;
wire F_op_rsvx00;
wire F_op_rsvx10;
wire F_op_rsvx15;
wire F_op_rsvx17;
wire F_op_rsvx21;
wire F_op_rsvx25;
wire F_op_rsvx33;
wire F_op_rsvx34;
wire F_op_rsvx35;
wire F_op_rsvx42;
wire F_op_rsvx43;
wire F_op_rsvx44;
wire F_op_rsvx47;
wire F_op_rsvx50;
wire F_op_rsvx51;
wire F_op_rsvx55;
wire F_op_rsvx56;
wire F_op_rsvx60;
wire F_op_rsvx63;
wire F_op_sll;
wire F_op_slli;
wire F_op_sra;
wire F_op_srai;
wire F_op_srl;
wire F_op_srli;
wire F_op_stb;
wire F_op_stbio;
wire F_op_stc;
wire F_op_sth;
wire F_op_sthio;
wire F_op_stw;
wire F_op_stwio;
wire F_op_sub;
wire F_op_sync;
wire F_op_trap;
wire F_op_wrctl;
wire F_op_wrprs;
wire F_op_xor;
wire F_op_xorhi;
wire F_op_xori;
reg [ 22: 0] F_pc /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire F_pc_en;
wire [ 22: 0] F_pc_no_crst_nxt;
wire [ 22: 0] F_pc_nxt;
wire [ 22: 0] F_pc_plus_one;
wire [ 1: 0] F_pc_sel_nxt;
wire [ 24: 0] F_pcb;
wire [ 24: 0] F_pcb_nxt;
wire [ 24: 0] F_pcb_plus_four;
wire F_valid;
wire [ 55: 0] F_vinst;
reg [ 1: 0] R_compare_op;
reg R_ctrl_alu_force_xor;
wire R_ctrl_alu_force_xor_nxt;
reg R_ctrl_alu_signed_comparison;
wire R_ctrl_alu_signed_comparison_nxt;
reg R_ctrl_alu_subtract;
wire R_ctrl_alu_subtract_nxt;
reg R_ctrl_b_is_dst;
wire R_ctrl_b_is_dst_nxt;
reg R_ctrl_br;
reg R_ctrl_br_cmp;
wire R_ctrl_br_cmp_nxt;
wire R_ctrl_br_nxt;
reg R_ctrl_br_uncond;
wire R_ctrl_br_uncond_nxt;
reg R_ctrl_break;
wire R_ctrl_break_nxt;
reg R_ctrl_crst;
wire R_ctrl_crst_nxt;
reg R_ctrl_custom;
reg R_ctrl_custom_multi;
wire R_ctrl_custom_multi_nxt;
wire R_ctrl_custom_nxt;
reg R_ctrl_exception;
wire R_ctrl_exception_nxt;
reg R_ctrl_force_src2_zero;
wire R_ctrl_force_src2_zero_nxt;
reg R_ctrl_hi_imm16;
wire R_ctrl_hi_imm16_nxt;
reg R_ctrl_ignore_dst;
wire R_ctrl_ignore_dst_nxt;
reg R_ctrl_implicit_dst_eretaddr;
wire R_ctrl_implicit_dst_eretaddr_nxt;
reg R_ctrl_implicit_dst_retaddr;
wire R_ctrl_implicit_dst_retaddr_nxt;
reg R_ctrl_jmp_direct;
wire R_ctrl_jmp_direct_nxt;
reg R_ctrl_jmp_indirect;
wire R_ctrl_jmp_indirect_nxt;
reg R_ctrl_ld;
reg R_ctrl_ld_io;
wire R_ctrl_ld_io_nxt;
reg R_ctrl_ld_non_io;
wire R_ctrl_ld_non_io_nxt;
wire R_ctrl_ld_nxt;
reg R_ctrl_ld_signed;
wire R_ctrl_ld_signed_nxt;
reg R_ctrl_logic;
wire R_ctrl_logic_nxt;
reg R_ctrl_rdctl_inst;
wire R_ctrl_rdctl_inst_nxt;
reg R_ctrl_retaddr;
wire R_ctrl_retaddr_nxt;
reg R_ctrl_rot_right;
wire R_ctrl_rot_right_nxt;
reg R_ctrl_shift_logical;
wire R_ctrl_shift_logical_nxt;
reg R_ctrl_shift_right_arith;
wire R_ctrl_shift_right_arith_nxt;
reg R_ctrl_shift_rot;
wire R_ctrl_shift_rot_nxt;
reg R_ctrl_shift_rot_right;
wire R_ctrl_shift_rot_right_nxt;
reg R_ctrl_src2_choose_imm;
wire R_ctrl_src2_choose_imm_nxt;
reg R_ctrl_st;
wire R_ctrl_st_nxt;
reg R_ctrl_uncond_cti_non_br;
wire R_ctrl_uncond_cti_non_br_nxt;
reg R_ctrl_unsigned_lo_imm16;
wire R_ctrl_unsigned_lo_imm16_nxt;
reg R_ctrl_wrctl_inst;
wire R_ctrl_wrctl_inst_nxt;
reg [ 4: 0] R_dst_regnum /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire R_en;
reg [ 1: 0] R_logic_op;
wire [ 31: 0] R_rf_a;
wire [ 31: 0] R_rf_b;
wire [ 31: 0] R_src1;
wire [ 31: 0] R_src2;
wire [ 15: 0] R_src2_hi;
wire [ 15: 0] R_src2_lo;
reg R_src2_use_imm;
wire [ 7: 0] R_stb_data;
wire [ 15: 0] R_sth_data;
reg R_valid;
wire [ 55: 0] R_vinst;
reg R_wr_dst_reg;
reg [ 31: 0] W_alu_result;
wire W_br_taken;
reg W_bstatus_reg;
wire W_bstatus_reg_inst_nxt;
wire W_bstatus_reg_nxt;
reg W_cmp_result;
reg [ 31: 0] W_control_rd_data;
reg W_estatus_reg;
wire W_estatus_reg_inst_nxt;
wire W_estatus_reg_nxt;
reg [ 31: 0] W_ienable_reg;
wire [ 31: 0] W_ienable_reg_nxt;
reg [ 31: 0] W_ipending_reg;
wire [ 31: 0] W_ipending_reg_nxt;
wire [ 24: 0] W_mem_baddr;
wire [ 31: 0] W_rf_wr_data;
wire W_rf_wren;
wire W_status_reg;
reg W_status_reg_pie;
wire W_status_reg_pie_inst_nxt;
wire W_status_reg_pie_nxt;
reg W_valid /* synthesis ALTERA_IP_DEBUG_VISIBLE = 1 */;
wire [ 55: 0] W_vinst;
wire [ 31: 0] W_wr_data;
wire [ 31: 0] W_wr_data_non_zero;
wire av_fill_bit;
reg [ 1: 0] av_ld_align_cycle;
wire [ 1: 0] av_ld_align_cycle_nxt;
wire av_ld_align_one_more_cycle;
reg av_ld_aligning_data;
wire av_ld_aligning_data_nxt;
reg [ 7: 0] av_ld_byte0_data;
wire [ 7: 0] av_ld_byte0_data_nxt;
reg [ 7: 0] av_ld_byte1_data;
wire av_ld_byte1_data_en;
wire [ 7: 0] av_ld_byte1_data_nxt;
reg [ 7: 0] av_ld_byte2_data;
wire [ 7: 0] av_ld_byte2_data_nxt;
reg [ 7: 0] av_ld_byte3_data;
wire [ 7: 0] av_ld_byte3_data_nxt;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire [ 31: 0] av_ld_data_aligned_unfiltered;
wire av_ld_done;
wire av_ld_extend;
wire av_ld_getting_data;
wire av_ld_rshift8;
reg av_ld_waiting_for_data;
wire av_ld_waiting_for_data_nxt;
wire av_sign_bit;
wire [ 24: 0] d_address;
reg [ 3: 0] d_byteenable;
reg d_read;
wire d_read_nxt;
wire d_write;
wire d_write_nxt;
reg [ 31: 0] d_writedata;
reg hbreak_enabled;
reg hbreak_pending;
wire hbreak_pending_nxt;
wire hbreak_req;
wire [ 24: 0] i_address;
reg i_read;
wire i_read_nxt;
wire [ 31: 0] iactive;
wire intr_req;
wire jtag_debug_module_clk;
wire jtag_debug_module_debugaccess_to_roms;
wire [ 31: 0] jtag_debug_module_readdata;
wire jtag_debug_module_reset;
wire jtag_debug_module_resetrequest;
wire no_ci_readra;
wire oci_hbreak_req;
wire [ 31: 0] oci_ienable;
wire oci_single_step_mode;
wire oci_tb_hbreak_req;
wire test_ending;
wire test_has_ended;
reg wait_for_one_post_bret_inst;
//the_video_sys_CPU_test_bench, which is an e_instance
video_sys_CPU_test_bench the_video_sys_CPU_test_bench
(
.D_iw (D_iw),
.D_iw_op (D_iw_op),
.D_iw_opx (D_iw_opx),
.D_valid (D_valid),
.E_alu_result (E_alu_result),
.E_mem_byte_en (E_mem_byte_en),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pcb (F_pcb),
.F_valid (F_valid),
.R_ctrl_exception (R_ctrl_exception),
.R_ctrl_ld (R_ctrl_ld),
.R_ctrl_ld_non_io (R_ctrl_ld_non_io),
.R_dst_regnum (R_dst_regnum),
.R_wr_dst_reg (R_wr_dst_reg),
.W_bstatus_reg (W_bstatus_reg),
.W_cmp_result (W_cmp_result),
.W_estatus_reg (W_estatus_reg),
.W_ienable_reg (W_ienable_reg),
.W_ipending_reg (W_ipending_reg),
.W_mem_baddr (W_mem_baddr),
.W_rf_wr_data (W_rf_wr_data),
.W_status_reg (W_status_reg),
.W_valid (W_valid),
.W_vinst (W_vinst),
.W_wr_data (W_wr_data),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.av_ld_data_aligned_unfiltered (av_ld_data_aligned_unfiltered),
.clk (clk),
.d_address (d_address),
.d_byteenable (d_byteenable),
.d_read (d_read),
.d_write (d_write),
.d_write_nxt (d_write_nxt),
.i_address (i_address),
.i_read (i_read),
.i_readdata (i_readdata),
.i_waitrequest (i_waitrequest),
.reset_n (reset_n),
.test_has_ended (test_has_ended)
);
assign F_av_iw_a = F_av_iw[31 : 27];
assign F_av_iw_b = F_av_iw[26 : 22];
assign F_av_iw_c = F_av_iw[21 : 17];
assign F_av_iw_custom_n = F_av_iw[13 : 6];
assign F_av_iw_custom_readra = F_av_iw[16];
assign F_av_iw_custom_readrb = F_av_iw[15];
assign F_av_iw_custom_writerc = F_av_iw[14];
assign F_av_iw_opx = F_av_iw[16 : 11];
assign F_av_iw_op = F_av_iw[5 : 0];
assign F_av_iw_shift_imm5 = F_av_iw[10 : 6];
assign F_av_iw_trap_break_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm5 = F_av_iw[10 : 6];
assign F_av_iw_imm16 = F_av_iw[21 : 6];
assign F_av_iw_imm26 = F_av_iw[31 : 6];
assign F_av_iw_memsz = F_av_iw[4 : 3];
assign F_av_iw_control_regnum = F_av_iw[8 : 6];
assign F_av_mem8 = F_av_iw_memsz == 2'b00;
assign F_av_mem16 = F_av_iw_memsz == 2'b01;
assign F_av_mem32 = F_av_iw_memsz[1] == 1'b1;
assign F_iw_a = F_iw[31 : 27];
assign F_iw_b = F_iw[26 : 22];
assign F_iw_c = F_iw[21 : 17];
assign F_iw_custom_n = F_iw[13 : 6];
assign F_iw_custom_readra = F_iw[16];
assign F_iw_custom_readrb = F_iw[15];
assign F_iw_custom_writerc = F_iw[14];
assign F_iw_opx = F_iw[16 : 11];
assign F_iw_op = F_iw[5 : 0];
assign F_iw_shift_imm5 = F_iw[10 : 6];
assign F_iw_trap_break_imm5 = F_iw[10 : 6];
assign F_iw_imm5 = F_iw[10 : 6];
assign F_iw_imm16 = F_iw[21 : 6];
assign F_iw_imm26 = F_iw[31 : 6];
assign F_iw_memsz = F_iw[4 : 3];
assign F_iw_control_regnum = F_iw[8 : 6];
assign F_mem8 = F_iw_memsz == 2'b00;
assign F_mem16 = F_iw_memsz == 2'b01;
assign F_mem32 = F_iw_memsz[1] == 1'b1;
assign D_iw_a = D_iw[31 : 27];
assign D_iw_b = D_iw[26 : 22];
assign D_iw_c = D_iw[21 : 17];
assign D_iw_custom_n = D_iw[13 : 6];
assign D_iw_custom_readra = D_iw[16];
assign D_iw_custom_readrb = D_iw[15];
assign D_iw_custom_writerc = D_iw[14];
assign D_iw_opx = D_iw[16 : 11];
assign D_iw_op = D_iw[5 : 0];
assign D_iw_shift_imm5 = D_iw[10 : 6];
assign D_iw_trap_break_imm5 = D_iw[10 : 6];
assign D_iw_imm5 = D_iw[10 : 6];
assign D_iw_imm16 = D_iw[21 : 6];
assign D_iw_imm26 = D_iw[31 : 6];
assign D_iw_memsz = D_iw[4 : 3];
assign D_iw_control_regnum = D_iw[8 : 6];
assign D_mem8 = D_iw_memsz == 2'b00;
assign D_mem16 = D_iw_memsz == 2'b01;
assign D_mem32 = D_iw_memsz[1] == 1'b1;
assign F_op_call = F_iw_op == 0;
assign F_op_jmpi = F_iw_op == 1;
assign F_op_ldbu = F_iw_op == 3;
assign F_op_addi = F_iw_op == 4;
assign F_op_stb = F_iw_op == 5;
assign F_op_br = F_iw_op == 6;
assign F_op_ldb = F_iw_op == 7;
assign F_op_cmpgei = F_iw_op == 8;
assign F_op_ldhu = F_iw_op == 11;
assign F_op_andi = F_iw_op == 12;
assign F_op_sth = F_iw_op == 13;
assign F_op_bge = F_iw_op == 14;
assign F_op_ldh = F_iw_op == 15;
assign F_op_cmplti = F_iw_op == 16;
assign F_op_initda = F_iw_op == 19;
assign F_op_ori = F_iw_op == 20;
assign F_op_stw = F_iw_op == 21;
assign F_op_blt = F_iw_op == 22;
assign F_op_ldw = F_iw_op == 23;
assign F_op_cmpnei = F_iw_op == 24;
assign F_op_flushda = F_iw_op == 27;
assign F_op_xori = F_iw_op == 28;
assign F_op_stc = F_iw_op == 29;
assign F_op_bne = F_iw_op == 30;
assign F_op_ldl = F_iw_op == 31;
assign F_op_cmpeqi = F_iw_op == 32;
assign F_op_ldbuio = F_iw_op == 35;
assign F_op_muli = F_iw_op == 36;
assign F_op_stbio = F_iw_op == 37;
assign F_op_beq = F_iw_op == 38;
assign F_op_ldbio = F_iw_op == 39;
assign F_op_cmpgeui = F_iw_op == 40;
assign F_op_ldhuio = F_iw_op == 43;
assign F_op_andhi = F_iw_op == 44;
assign F_op_sthio = F_iw_op == 45;
assign F_op_bgeu = F_iw_op == 46;
assign F_op_ldhio = F_iw_op == 47;
assign F_op_cmpltui = F_iw_op == 48;
assign F_op_initd = F_iw_op == 51;
assign F_op_orhi = F_iw_op == 52;
assign F_op_stwio = F_iw_op == 53;
assign F_op_bltu = F_iw_op == 54;
assign F_op_ldwio = F_iw_op == 55;
assign F_op_rdprs = F_iw_op == 56;
assign F_op_flushd = F_iw_op == 59;
assign F_op_xorhi = F_iw_op == 60;
assign F_op_rsv02 = F_iw_op == 2;
assign F_op_rsv09 = F_iw_op == 9;
assign F_op_rsv10 = F_iw_op == 10;
assign F_op_rsv17 = F_iw_op == 17;
assign F_op_rsv18 = F_iw_op == 18;
assign F_op_rsv25 = F_iw_op == 25;
assign F_op_rsv26 = F_iw_op == 26;
assign F_op_rsv33 = F_iw_op == 33;
assign F_op_rsv34 = F_iw_op == 34;
assign F_op_rsv41 = F_iw_op == 41;
assign F_op_rsv42 = F_iw_op == 42;
assign F_op_rsv49 = F_iw_op == 49;
assign F_op_rsv57 = F_iw_op == 57;
assign F_op_rsv61 = F_iw_op == 61;
assign F_op_rsv62 = F_iw_op == 62;
assign F_op_rsv63 = F_iw_op == 63;
assign F_op_eret = F_op_opx & (F_iw_opx == 1);
assign F_op_roli = F_op_opx & (F_iw_opx == 2);
assign F_op_rol = F_op_opx & (F_iw_opx == 3);
assign F_op_flushp = F_op_opx & (F_iw_opx == 4);
assign F_op_ret = F_op_opx & (F_iw_opx == 5);
assign F_op_nor = F_op_opx & (F_iw_opx == 6);
assign F_op_mulxuu = F_op_opx & (F_iw_opx == 7);
assign F_op_cmpge = F_op_opx & (F_iw_opx == 8);
assign F_op_bret = F_op_opx & (F_iw_opx == 9);
assign F_op_ror = F_op_opx & (F_iw_opx == 11);
assign F_op_flushi = F_op_opx & (F_iw_opx == 12);
assign F_op_jmp = F_op_opx & (F_iw_opx == 13);
assign F_op_and = F_op_opx & (F_iw_opx == 14);
assign F_op_cmplt = F_op_opx & (F_iw_opx == 16);
assign F_op_slli = F_op_opx & (F_iw_opx == 18);
assign F_op_sll = F_op_opx & (F_iw_opx == 19);
assign F_op_wrprs = F_op_opx & (F_iw_opx == 20);
assign F_op_or = F_op_opx & (F_iw_opx == 22);
assign F_op_mulxsu = F_op_opx & (F_iw_opx == 23);
assign F_op_cmpne = F_op_opx & (F_iw_opx == 24);
assign F_op_srli = F_op_opx & (F_iw_opx == 26);
assign F_op_srl = F_op_opx & (F_iw_opx == 27);
assign F_op_nextpc = F_op_opx & (F_iw_opx == 28);
assign F_op_callr = F_op_opx & (F_iw_opx == 29);
assign F_op_xor = F_op_opx & (F_iw_opx == 30);
assign F_op_mulxss = F_op_opx & (F_iw_opx == 31);
assign F_op_cmpeq = F_op_opx & (F_iw_opx == 32);
assign F_op_divu = F_op_opx & (F_iw_opx == 36);
assign F_op_div = F_op_opx & (F_iw_opx == 37);
assign F_op_rdctl = F_op_opx & (F_iw_opx == 38);
assign F_op_mul = F_op_opx & (F_iw_opx == 39);
assign F_op_cmpgeu = F_op_opx & (F_iw_opx == 40);
assign F_op_initi = F_op_opx & (F_iw_opx == 41);
assign F_op_trap = F_op_opx & (F_iw_opx == 45);
assign F_op_wrctl = F_op_opx & (F_iw_opx == 46);
assign F_op_cmpltu = F_op_opx & (F_iw_opx == 48);
assign F_op_add = F_op_opx & (F_iw_opx == 49);
assign F_op_break = F_op_opx & (F_iw_opx == 52);
assign F_op_hbreak = F_op_opx & (F_iw_opx == 53);
assign F_op_sync = F_op_opx & (F_iw_opx == 54);
assign F_op_sub = F_op_opx & (F_iw_opx == 57);
assign F_op_srai = F_op_opx & (F_iw_opx == 58);
assign F_op_sra = F_op_opx & (F_iw_opx == 59);
assign F_op_intr = F_op_opx & (F_iw_opx == 61);
assign F_op_crst = F_op_opx & (F_iw_opx == 62);
assign F_op_rsvx00 = F_op_opx & (F_iw_opx == 0);
assign F_op_rsvx10 = F_op_opx & (F_iw_opx == 10);
assign F_op_rsvx15 = F_op_opx & (F_iw_opx == 15);
assign F_op_rsvx17 = F_op_opx & (F_iw_opx == 17);
assign F_op_rsvx21 = F_op_opx & (F_iw_opx == 21);
assign F_op_rsvx25 = F_op_opx & (F_iw_opx == 25);
assign F_op_rsvx33 = F_op_opx & (F_iw_opx == 33);
assign F_op_rsvx34 = F_op_opx & (F_iw_opx == 34);
assign F_op_rsvx35 = F_op_opx & (F_iw_opx == 35);
assign F_op_rsvx42 = F_op_opx & (F_iw_opx == 42);
assign F_op_rsvx43 = F_op_opx & (F_iw_opx == 43);
assign F_op_rsvx44 = F_op_opx & (F_iw_opx == 44);
assign F_op_rsvx47 = F_op_opx & (F_iw_opx == 47);
assign F_op_rsvx50 = F_op_opx & (F_iw_opx == 50);
assign F_op_rsvx51 = F_op_opx & (F_iw_opx == 51);
assign F_op_rsvx55 = F_op_opx & (F_iw_opx == 55);
assign F_op_rsvx56 = F_op_opx & (F_iw_opx == 56);
assign F_op_rsvx60 = F_op_opx & (F_iw_opx == 60);
assign F_op_rsvx63 = F_op_opx & (F_iw_opx == 63);
assign F_op_opx = F_iw_op == 58;
assign F_op_custom = F_iw_op == 50;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_rsv02 = D_iw_op == 2;
assign D_op_rsv09 = D_iw_op == 9;
assign D_op_rsv10 = D_iw_op == 10;
assign D_op_rsv17 = D_iw_op == 17;
assign D_op_rsv18 = D_iw_op == 18;
assign D_op_rsv25 = D_iw_op == 25;
assign D_op_rsv26 = D_iw_op == 26;
assign D_op_rsv33 = D_iw_op == 33;
assign D_op_rsv34 = D_iw_op == 34;
assign D_op_rsv41 = D_iw_op == 41;
assign D_op_rsv42 = D_iw_op == 42;
assign D_op_rsv49 = D_iw_op == 49;
assign D_op_rsv57 = D_iw_op == 57;
assign D_op_rsv61 = D_iw_op == 61;
assign D_op_rsv62 = D_iw_op == 62;
assign D_op_rsv63 = D_iw_op == 63;
assign D_op_eret = D_op_opx & (D_iw_opx == 1);
assign D_op_roli = D_op_opx & (D_iw_opx == 2);
assign D_op_rol = D_op_opx & (D_iw_opx == 3);
assign D_op_flushp = D_op_opx & (D_iw_opx == 4);
assign D_op_ret = D_op_opx & (D_iw_opx == 5);
assign D_op_nor = D_op_opx & (D_iw_opx == 6);
assign D_op_mulxuu = D_op_opx & (D_iw_opx == 7);
assign D_op_cmpge = D_op_opx & (D_iw_opx == 8);
assign D_op_bret = D_op_opx & (D_iw_opx == 9);
assign D_op_ror = D_op_opx & (D_iw_opx == 11);
assign D_op_flushi = D_op_opx & (D_iw_opx == 12);
assign D_op_jmp = D_op_opx & (D_iw_opx == 13);
assign D_op_and = D_op_opx & (D_iw_opx == 14);
assign D_op_cmplt = D_op_opx & (D_iw_opx == 16);
assign D_op_slli = D_op_opx & (D_iw_opx == 18);
assign D_op_sll = D_op_opx & (D_iw_opx == 19);
assign D_op_wrprs = D_op_opx & (D_iw_opx == 20);
assign D_op_or = D_op_opx & (D_iw_opx == 22);
assign D_op_mulxsu = D_op_opx & (D_iw_opx == 23);
assign D_op_cmpne = D_op_opx & (D_iw_opx == 24);
assign D_op_srli = D_op_opx & (D_iw_opx == 26);
assign D_op_srl = D_op_opx & (D_iw_opx == 27);
assign D_op_nextpc = D_op_opx & (D_iw_opx == 28);
assign D_op_callr = D_op_opx & (D_iw_opx == 29);
assign D_op_xor = D_op_opx & (D_iw_opx == 30);
assign D_op_mulxss = D_op_opx & (D_iw_opx == 31);
assign D_op_cmpeq = D_op_opx & (D_iw_opx == 32);
assign D_op_divu = D_op_opx & (D_iw_opx == 36);
assign D_op_div = D_op_opx & (D_iw_opx == 37);
assign D_op_rdctl = D_op_opx & (D_iw_opx == 38);
assign D_op_mul = D_op_opx & (D_iw_opx == 39);
assign D_op_cmpgeu = D_op_opx & (D_iw_opx == 40);
assign D_op_initi = D_op_opx & (D_iw_opx == 41);
assign D_op_trap = D_op_opx & (D_iw_opx == 45);
assign D_op_wrctl = D_op_opx & (D_iw_opx == 46);
assign D_op_cmpltu = D_op_opx & (D_iw_opx == 48);
assign D_op_add = D_op_opx & (D_iw_opx == 49);
assign D_op_break = D_op_opx & (D_iw_opx == 52);
assign D_op_hbreak = D_op_opx & (D_iw_opx == 53);
assign D_op_sync = D_op_opx & (D_iw_opx == 54);
assign D_op_sub = D_op_opx & (D_iw_opx == 57);
assign D_op_srai = D_op_opx & (D_iw_opx == 58);
assign D_op_sra = D_op_opx & (D_iw_opx == 59);
assign D_op_intr = D_op_opx & (D_iw_opx == 61);
assign D_op_crst = D_op_opx & (D_iw_opx == 62);
assign D_op_rsvx00 = D_op_opx & (D_iw_opx == 0);
assign D_op_rsvx10 = D_op_opx & (D_iw_opx == 10);
assign D_op_rsvx15 = D_op_opx & (D_iw_opx == 15);
assign D_op_rsvx17 = D_op_opx & (D_iw_opx == 17);
assign D_op_rsvx21 = D_op_opx & (D_iw_opx == 21);
assign D_op_rsvx25 = D_op_opx & (D_iw_opx == 25);
assign D_op_rsvx33 = D_op_opx & (D_iw_opx == 33);
assign D_op_rsvx34 = D_op_opx & (D_iw_opx == 34);
assign D_op_rsvx35 = D_op_opx & (D_iw_opx == 35);
assign D_op_rsvx42 = D_op_opx & (D_iw_opx == 42);
assign D_op_rsvx43 = D_op_opx & (D_iw_opx == 43);
assign D_op_rsvx44 = D_op_opx & (D_iw_opx == 44);
assign D_op_rsvx47 = D_op_opx & (D_iw_opx == 47);
assign D_op_rsvx50 = D_op_opx & (D_iw_opx == 50);
assign D_op_rsvx51 = D_op_opx & (D_iw_opx == 51);
assign D_op_rsvx55 = D_op_opx & (D_iw_opx == 55);
assign D_op_rsvx56 = D_op_opx & (D_iw_opx == 56);
assign D_op_rsvx60 = D_op_opx & (D_iw_opx == 60);
assign D_op_rsvx63 = D_op_opx & (D_iw_opx == 63);
assign D_op_opx = D_iw_op == 58;
assign D_op_custom = D_iw_op == 50;
assign R_en = 1'b1;
assign E_ci_result = 0;
//custom_instruction_master, which is an e_custom_instruction_master
assign no_ci_readra = 1'b0;
assign E_ci_multi_stall = 1'b0;
assign iactive = d_irq[31 : 0] & 32'b00000000000000000000000000000011;
assign F_pc_sel_nxt = R_ctrl_exception ? 2'b00 :
R_ctrl_break ? 2'b01 :
(W_br_taken | R_ctrl_uncond_cti_non_br) ? 2'b10 :
2'b11;
assign F_pc_no_crst_nxt = (F_pc_sel_nxt == 2'b00)? 135176 :
(F_pc_sel_nxt == 2'b01)? 139784 :
(F_pc_sel_nxt == 2'b10)? E_arith_result[24 : 2] :
F_pc_plus_one;
assign F_pc_nxt = F_pc_no_crst_nxt;
assign F_pcb_nxt = {F_pc_nxt, 2'b00};
assign F_pc_en = W_valid;
assign F_pc_plus_one = F_pc + 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
F_pc <= 135168;
else if (F_pc_en)
F_pc <= F_pc_nxt;
end
assign F_pcb = {F_pc, 2'b00};
assign F_pcb_plus_four = {F_pc_plus_one, 2'b00};
assign F_valid = i_read & ~i_waitrequest;
assign i_read_nxt = W_valid | (i_read & i_waitrequest);
assign i_address = {F_pc, 2'b00};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
i_read <= 1'b1;
else
i_read <= i_read_nxt;
end
assign oci_tb_hbreak_req = oci_hbreak_req;
assign hbreak_req = (oci_tb_hbreak_req | hbreak_pending) & hbreak_enabled & ~(wait_for_one_post_bret_inst & ~W_valid);
assign hbreak_pending_nxt = hbreak_pending ? hbreak_enabled
: hbreak_req;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
wait_for_one_post_bret_inst <= 1'b0;
else
wait_for_one_post_bret_inst <= (~hbreak_enabled & oci_single_step_mode) ? 1'b1 : (F_valid | ~oci_single_step_mode) ? 1'b0 : wait_for_one_post_bret_inst;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_pending <= 1'b0;
else
hbreak_pending <= hbreak_pending_nxt;
end
assign intr_req = W_status_reg_pie & (W_ipending_reg != 0);
assign F_av_iw = i_readdata;
assign F_iw = hbreak_req ? 4040762 :
1'b0 ? 127034 :
intr_req ? 3926074 :
F_av_iw;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_iw <= 0;
else if (F_valid)
D_iw <= F_iw;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
D_valid <= 0;
else
D_valid <= F_valid;
end
assign D_dst_regnum = D_ctrl_implicit_dst_retaddr ? 5'd31 :
D_ctrl_implicit_dst_eretaddr ? 5'd29 :
D_ctrl_b_is_dst ? D_iw_b :
D_iw_c;
assign D_wr_dst_reg = (D_dst_regnum != 0) & ~D_ctrl_ignore_dst;
assign D_logic_op_raw = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_logic_op = D_ctrl_alu_force_xor ? 2'b11 : D_logic_op_raw;
assign D_compare_op = D_op_opx ? D_iw_opx[4 : 3] :
D_iw_op[4 : 3];
assign D_jmp_direct_target_waddr = D_iw[31 : 6];
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_valid <= 0;
else
R_valid <= D_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_wr_dst_reg <= 0;
else
R_wr_dst_reg <= D_wr_dst_reg;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_dst_regnum <= 0;
else
R_dst_regnum <= D_dst_regnum;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_logic_op <= 0;
else
R_logic_op <= D_logic_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_compare_op <= 0;
else
R_compare_op <= D_compare_op;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_src2_use_imm <= 0;
else
R_src2_use_imm <= D_ctrl_src2_choose_imm | (D_ctrl_br & R_valid);
end
assign W_rf_wren = (R_wr_dst_reg & W_valid) | ~reset_n;
assign W_rf_wr_data = R_ctrl_ld ? av_ld_data_aligned_filtered : W_wr_data;
//video_sys_CPU_register_bank_a, which is an nios_sdp_ram
video_sys_CPU_register_bank_a_module video_sys_CPU_register_bank_a
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_a),
.rdaddress (D_iw_a),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam video_sys_CPU_register_bank_a.lpm_file = "video_sys_CPU_rf_ram_a.dat";
`else
defparam video_sys_CPU_register_bank_a.lpm_file = "video_sys_CPU_rf_ram_a.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam video_sys_CPU_register_bank_a.lpm_file = "video_sys_CPU_rf_ram_a.mif";
//synthesis read_comments_as_HDL off
//video_sys_CPU_register_bank_b, which is an nios_sdp_ram
video_sys_CPU_register_bank_b_module video_sys_CPU_register_bank_b
(
.clock (clk),
.data (W_rf_wr_data),
.q (R_rf_b),
.rdaddress (D_iw_b),
.wraddress (R_dst_regnum),
.wren (W_rf_wren)
);
//synthesis translate_off
`ifdef NO_PLI
defparam video_sys_CPU_register_bank_b.lpm_file = "video_sys_CPU_rf_ram_b.dat";
`else
defparam video_sys_CPU_register_bank_b.lpm_file = "video_sys_CPU_rf_ram_b.hex";
`endif
//synthesis translate_on
//synthesis read_comments_as_HDL on
//defparam video_sys_CPU_register_bank_b.lpm_file = "video_sys_CPU_rf_ram_b.mif";
//synthesis read_comments_as_HDL off
assign R_src1 = (((R_ctrl_br & E_valid) | (R_ctrl_retaddr & R_valid)))? {F_pc_plus_one, 2'b00} :
((R_ctrl_jmp_direct & E_valid))? {D_jmp_direct_target_waddr, 2'b00} :
R_rf_a;
assign R_src2_lo = ((R_ctrl_force_src2_zero|R_ctrl_hi_imm16))? 16'b0 :
(R_src2_use_imm)? D_iw_imm16 :
R_rf_b[15 : 0];
assign R_src2_hi = ((R_ctrl_force_src2_zero|R_ctrl_unsigned_lo_imm16))? 16'b0 :
(R_ctrl_hi_imm16)? D_iw_imm16 :
(R_src2_use_imm)? {16 {D_iw_imm16[15]}} :
R_rf_b[31 : 16];
assign R_src2 = {R_src2_hi, R_src2_lo};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_valid <= 0;
else
E_valid <= R_valid | E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_new_inst <= 0;
else
E_new_inst <= R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src1 <= 0;
else
E_src1 <= R_src1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_src2 <= 0;
else
E_src2 <= R_src2;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_invert_arith_src_msb <= 0;
else
E_invert_arith_src_msb <= D_ctrl_alu_signed_comparison & R_valid;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_alu_sub <= 0;
else
E_alu_sub <= D_ctrl_alu_subtract & R_valid;
end
assign E_stall = E_shift_rot_stall | E_ld_stall | E_st_stall | E_ci_multi_stall;
assign E_arith_src1 = { E_src1[31] ^ E_invert_arith_src_msb,
E_src1[30 : 0]};
assign E_arith_src2 = { E_src2[31] ^ E_invert_arith_src_msb,
E_src2[30 : 0]};
assign E_arith_result = E_alu_sub ?
E_arith_src1 - E_arith_src2 :
E_arith_src1 + E_arith_src2;
assign E_mem_baddr = E_arith_result[24 : 0];
assign E_logic_result = (R_logic_op == 2'b00)? (~(E_src1 | E_src2)) :
(R_logic_op == 2'b01)? (E_src1 & E_src2) :
(R_logic_op == 2'b10)? (E_src1 | E_src2) :
(E_src1 ^ E_src2);
assign E_logic_result_is_0 = E_logic_result == 0;
assign E_eq = E_logic_result_is_0;
assign E_lt = E_arith_result[32];
assign E_cmp_result = (R_compare_op == 2'b00)? E_eq :
(R_compare_op == 2'b01)? ~E_lt :
(R_compare_op == 2'b10)? E_lt :
~E_eq;
assign E_shift_rot_cnt_nxt = E_new_inst ? E_src2[4 : 0] : E_shift_rot_cnt-1;
assign E_shift_rot_done = (E_shift_rot_cnt == 0) & ~E_new_inst;
assign E_shift_rot_stall = R_ctrl_shift_rot & E_valid & ~E_shift_rot_done;
assign E_shift_rot_fill_bit = R_ctrl_shift_logical ? 1'b0 :
(R_ctrl_rot_right ? E_shift_rot_result[0] :
E_shift_rot_result[31]);
assign E_shift_rot_result_nxt = (E_new_inst)? E_src1 :
(R_ctrl_shift_rot_right)? {E_shift_rot_fill_bit, E_shift_rot_result[31 : 1]} :
{E_shift_rot_result[30 : 0], E_shift_rot_fill_bit};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_result <= 0;
else
E_shift_rot_result <= E_shift_rot_result_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
E_shift_rot_cnt <= 0;
else
E_shift_rot_cnt <= E_shift_rot_cnt_nxt;
end
assign E_control_rd_data = (D_iw_control_regnum == 3'd0)? W_status_reg :
(D_iw_control_regnum == 3'd1)? W_estatus_reg :
(D_iw_control_regnum == 3'd2)? W_bstatus_reg :
(D_iw_control_regnum == 3'd3)? W_ienable_reg :
(D_iw_control_regnum == 3'd4)? W_ipending_reg :
0;
assign E_alu_result = ((R_ctrl_br_cmp | R_ctrl_rdctl_inst))? 0 :
(R_ctrl_shift_rot)? E_shift_rot_result :
(R_ctrl_logic)? E_logic_result :
(R_ctrl_custom)? E_ci_result :
E_arith_result;
assign R_stb_data = R_rf_b[7 : 0];
assign R_sth_data = R_rf_b[15 : 0];
assign E_st_data = (D_mem8)? {R_stb_data, R_stb_data, R_stb_data, R_stb_data} :
(D_mem16)? {R_sth_data, R_sth_data} :
R_rf_b;
assign E_mem_byte_en = ({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b00})? 4'b0001 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b01})? 4'b0010 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b10})? 4'b0100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b00, 2'b11})? 4'b1000 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b00})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b01})? 4'b0011 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b10})? 4'b1100 :
({D_iw_memsz, E_mem_baddr[1 : 0]} == {2'b01, 2'b11})? 4'b1100 :
4'b1111;
assign d_read_nxt = (R_ctrl_ld & E_new_inst) | (d_read & d_waitrequest);
assign E_ld_stall = R_ctrl_ld & ((E_valid & ~av_ld_done) | E_new_inst);
assign d_write_nxt = (R_ctrl_st & E_new_inst) | (d_write & d_waitrequest);
assign E_st_stall = d_write_nxt;
assign d_address = W_mem_baddr;
assign av_ld_getting_data = d_read & ~d_waitrequest;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_read <= 0;
else
d_read <= d_read_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_writedata <= 0;
else
d_writedata <= E_st_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d_byteenable <= 0;
else
d_byteenable <= E_mem_byte_en;
end
assign av_ld_align_cycle_nxt = av_ld_getting_data ? 0 : (av_ld_align_cycle+1);
assign av_ld_align_one_more_cycle = av_ld_align_cycle == (D_mem16 ? 2 : 3);
assign av_ld_aligning_data_nxt = av_ld_aligning_data ?
~av_ld_align_one_more_cycle :
(~D_mem32 & av_ld_getting_data);
assign av_ld_waiting_for_data_nxt = av_ld_waiting_for_data ?
~av_ld_getting_data :
(R_ctrl_ld & E_new_inst);
assign av_ld_done = ~av_ld_waiting_for_data_nxt & (D_mem32 | ~av_ld_aligning_data_nxt);
assign av_ld_rshift8 = av_ld_aligning_data &
(av_ld_align_cycle < (W_mem_baddr[1 : 0]));
assign av_ld_extend = av_ld_aligning_data;
assign av_ld_byte0_data_nxt = av_ld_rshift8 ? av_ld_byte1_data :
av_ld_extend ? av_ld_byte0_data :
d_readdata[7 : 0];
assign av_ld_byte1_data_nxt = av_ld_rshift8 ? av_ld_byte2_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[15 : 8];
assign av_ld_byte2_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[23 : 16];
assign av_ld_byte3_data_nxt = av_ld_rshift8 ? av_ld_byte3_data :
av_ld_extend ? {8 {av_fill_bit}} :
d_readdata[31 : 24];
assign av_ld_byte1_data_en = ~(av_ld_extend & D_mem16 & ~av_ld_rshift8);
assign av_ld_data_aligned_unfiltered = {av_ld_byte3_data, av_ld_byte2_data,
av_ld_byte1_data, av_ld_byte0_data};
assign av_sign_bit = D_mem16 ? av_ld_byte1_data[7] : av_ld_byte0_data[7];
assign av_fill_bit = av_sign_bit & R_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_align_cycle <= 0;
else
av_ld_align_cycle <= av_ld_align_cycle_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_waiting_for_data <= 0;
else
av_ld_waiting_for_data <= av_ld_waiting_for_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_aligning_data <= 0;
else
av_ld_aligning_data <= av_ld_aligning_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte0_data <= 0;
else
av_ld_byte0_data <= av_ld_byte0_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte1_data <= 0;
else if (av_ld_byte1_data_en)
av_ld_byte1_data <= av_ld_byte1_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte2_data <= 0;
else
av_ld_byte2_data <= av_ld_byte2_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
av_ld_byte3_data <= 0;
else
av_ld_byte3_data <= av_ld_byte3_data_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_valid <= 0;
else
W_valid <= E_valid & ~E_stall;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_control_rd_data <= 0;
else
W_control_rd_data <= E_control_rd_data;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_cmp_result <= 0;
else
W_cmp_result <= E_cmp_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_alu_result <= 0;
else
W_alu_result <= E_alu_result;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_status_reg_pie <= 0;
else
W_status_reg_pie <= W_status_reg_pie_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_estatus_reg <= 0;
else
W_estatus_reg <= W_estatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_bstatus_reg <= 0;
else
W_bstatus_reg <= W_bstatus_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ienable_reg <= 0;
else
W_ienable_reg <= W_ienable_reg_nxt;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
W_ipending_reg <= 0;
else
W_ipending_reg <= W_ipending_reg_nxt;
end
assign W_wr_data_non_zero = R_ctrl_br_cmp ? W_cmp_result :
R_ctrl_rdctl_inst ? W_control_rd_data :
W_alu_result[31 : 0];
assign W_wr_data = W_wr_data_non_zero;
assign W_br_taken = R_ctrl_br & W_cmp_result;
assign W_mem_baddr = W_alu_result[24 : 0];
assign W_status_reg = W_status_reg_pie;
assign E_wrctl_status = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd0);
assign E_wrctl_estatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd1);
assign E_wrctl_bstatus = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd2);
assign E_wrctl_ienable = R_ctrl_wrctl_inst &
(D_iw_control_regnum == 3'd3);
assign W_status_reg_pie_inst_nxt = (R_ctrl_exception | R_ctrl_break | R_ctrl_crst) ? 1'b0 :
(D_op_eret) ? W_estatus_reg :
(D_op_bret) ? W_bstatus_reg :
(E_wrctl_status) ? E_src1[0] :
W_status_reg_pie;
assign W_status_reg_pie_nxt = E_valid ? W_status_reg_pie_inst_nxt : W_status_reg_pie;
assign W_estatus_reg_inst_nxt = (R_ctrl_crst) ? 0 :
(R_ctrl_exception) ? W_status_reg :
(E_wrctl_estatus) ? E_src1[0] :
W_estatus_reg;
assign W_estatus_reg_nxt = E_valid ? W_estatus_reg_inst_nxt : W_estatus_reg;
assign W_bstatus_reg_inst_nxt = (R_ctrl_break) ? W_status_reg :
(E_wrctl_bstatus) ? E_src1[0] :
W_bstatus_reg;
assign W_bstatus_reg_nxt = E_valid ? W_bstatus_reg_inst_nxt : W_bstatus_reg;
assign W_ienable_reg_nxt = ((E_wrctl_ienable & E_valid) ?
E_src1[31 : 0] : W_ienable_reg) & 32'b00000000000000000000000000000011;
assign W_ipending_reg_nxt = iactive & W_ienable_reg & oci_ienable & 32'b00000000000000000000000000000011;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
hbreak_enabled <= 1'b1;
else if (E_valid)
hbreak_enabled <= R_ctrl_break ? 1'b0 : D_op_bret ? 1'b1 : hbreak_enabled;
end
video_sys_CPU_nios2_oci the_video_sys_CPU_nios2_oci
(
.D_valid (D_valid),
.E_st_data (E_st_data),
.E_valid (E_valid),
.F_pc (F_pc),
.address (jtag_debug_module_address),
.av_ld_data_aligned_filtered (av_ld_data_aligned_filtered),
.begintransfer (jtag_debug_module_begintransfer),
.byteenable (jtag_debug_module_byteenable),
.chipselect (jtag_debug_module_select),
.clk (jtag_debug_module_clk),
.d_address (d_address),
.d_read (d_read),
.d_waitrequest (d_waitrequest),
.d_write (d_write),
.debugaccess (jtag_debug_module_debugaccess),
.hbreak_enabled (hbreak_enabled),
.jtag_debug_module_debugaccess_to_roms (jtag_debug_module_debugaccess_to_roms),
.oci_hbreak_req (oci_hbreak_req),
.oci_ienable (oci_ienable),
.oci_single_step_mode (oci_single_step_mode),
.readdata (jtag_debug_module_readdata),
.reset (jtag_debug_module_reset),
.reset_n (reset_n),
.resetrequest (jtag_debug_module_resetrequest),
.test_ending (test_ending),
.test_has_ended (test_has_ended),
.write (jtag_debug_module_write),
.writedata (jtag_debug_module_writedata)
);
//jtag_debug_module, which is an e_avalon_slave
assign jtag_debug_module_clk = clk;
assign jtag_debug_module_reset = ~reset_n;
assign D_ctrl_custom = 1'b0;
assign R_ctrl_custom_nxt = D_ctrl_custom;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom <= 0;
else if (R_en)
R_ctrl_custom <= R_ctrl_custom_nxt;
end
assign D_ctrl_custom_multi = 1'b0;
assign R_ctrl_custom_multi_nxt = D_ctrl_custom_multi;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_custom_multi <= 0;
else if (R_en)
R_ctrl_custom_multi <= R_ctrl_custom_multi_nxt;
end
assign D_ctrl_jmp_indirect = D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_jmp_indirect_nxt = D_ctrl_jmp_indirect;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_indirect <= 0;
else if (R_en)
R_ctrl_jmp_indirect <= R_ctrl_jmp_indirect_nxt;
end
assign D_ctrl_jmp_direct = D_op_call|D_op_jmpi;
assign R_ctrl_jmp_direct_nxt = D_ctrl_jmp_direct;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_jmp_direct <= 0;
else if (R_en)
R_ctrl_jmp_direct <= R_ctrl_jmp_direct_nxt;
end
assign D_ctrl_implicit_dst_retaddr = D_op_call|D_op_rsv02;
assign R_ctrl_implicit_dst_retaddr_nxt = D_ctrl_implicit_dst_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_retaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_retaddr <= R_ctrl_implicit_dst_retaddr_nxt;
end
assign D_ctrl_implicit_dst_eretaddr = D_op_div|D_op_divu|D_op_mul|D_op_muli|D_op_mulxss|D_op_mulxsu|D_op_mulxuu;
assign R_ctrl_implicit_dst_eretaddr_nxt = D_ctrl_implicit_dst_eretaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_implicit_dst_eretaddr <= 0;
else if (R_en)
R_ctrl_implicit_dst_eretaddr <= R_ctrl_implicit_dst_eretaddr_nxt;
end
assign D_ctrl_exception = D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60;
assign R_ctrl_exception_nxt = D_ctrl_exception;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_exception <= 0;
else if (R_en)
R_ctrl_exception <= R_ctrl_exception_nxt;
end
assign D_ctrl_break = D_op_break|D_op_hbreak;
assign R_ctrl_break_nxt = D_ctrl_break;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_break <= 0;
else if (R_en)
R_ctrl_break <= R_ctrl_break_nxt;
end
assign D_ctrl_crst = D_op_crst|D_op_rsvx63;
assign R_ctrl_crst_nxt = D_ctrl_crst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_crst <= 0;
else if (R_en)
R_ctrl_crst <= R_ctrl_crst_nxt;
end
assign D_ctrl_uncond_cti_non_br = D_op_call|
D_op_jmpi|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_callr;
assign R_ctrl_uncond_cti_non_br_nxt = D_ctrl_uncond_cti_non_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_uncond_cti_non_br <= 0;
else if (R_en)
R_ctrl_uncond_cti_non_br <= R_ctrl_uncond_cti_non_br_nxt;
end
assign D_ctrl_retaddr = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_div|
D_op_divu|
D_op_mul|
D_op_muli|
D_op_mulxss|
D_op_mulxsu|
D_op_mulxuu|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak;
assign R_ctrl_retaddr_nxt = D_ctrl_retaddr;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_retaddr <= 0;
else if (R_en)
R_ctrl_retaddr <= R_ctrl_retaddr_nxt;
end
assign D_ctrl_shift_logical = D_op_slli|D_op_sll|D_op_srli|D_op_srl;
assign R_ctrl_shift_logical_nxt = D_ctrl_shift_logical;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_logical <= 0;
else if (R_en)
R_ctrl_shift_logical <= R_ctrl_shift_logical_nxt;
end
assign D_ctrl_shift_right_arith = D_op_srai|D_op_sra;
assign R_ctrl_shift_right_arith_nxt = D_ctrl_shift_right_arith;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_right_arith <= 0;
else if (R_en)
R_ctrl_shift_right_arith <= R_ctrl_shift_right_arith_nxt;
end
assign D_ctrl_rot_right = D_op_rsvx10|D_op_ror|D_op_rsvx42|D_op_rsvx43;
assign R_ctrl_rot_right_nxt = D_ctrl_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rot_right <= 0;
else if (R_en)
R_ctrl_rot_right <= R_ctrl_rot_right_nxt;
end
assign D_ctrl_shift_rot_right = D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_right_nxt = D_ctrl_shift_rot_right;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot_right <= 0;
else if (R_en)
R_ctrl_shift_rot_right <= R_ctrl_shift_rot_right_nxt;
end
assign D_ctrl_shift_rot = D_op_slli|
D_op_rsvx50|
D_op_sll|
D_op_rsvx51|
D_op_roli|
D_op_rsvx34|
D_op_rol|
D_op_rsvx35|
D_op_srli|
D_op_srl|
D_op_srai|
D_op_sra|
D_op_rsvx10|
D_op_ror|
D_op_rsvx42|
D_op_rsvx43;
assign R_ctrl_shift_rot_nxt = D_ctrl_shift_rot;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_shift_rot <= 0;
else if (R_en)
R_ctrl_shift_rot <= R_ctrl_shift_rot_nxt;
end
assign D_ctrl_logic = D_op_and|
D_op_or|
D_op_xor|
D_op_nor|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori;
assign R_ctrl_logic_nxt = D_ctrl_logic;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_logic <= 0;
else if (R_en)
R_ctrl_logic <= R_ctrl_logic_nxt;
end
assign D_ctrl_hi_imm16 = D_op_andhi|D_op_orhi|D_op_xorhi;
assign R_ctrl_hi_imm16_nxt = D_ctrl_hi_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_hi_imm16 <= 0;
else if (R_en)
R_ctrl_hi_imm16 <= R_ctrl_hi_imm16_nxt;
end
assign D_ctrl_unsigned_lo_imm16 = D_op_cmpgeui|
D_op_cmpltui|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_unsigned_lo_imm16_nxt = D_ctrl_unsigned_lo_imm16;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_unsigned_lo_imm16 <= 0;
else if (R_en)
R_ctrl_unsigned_lo_imm16 <= R_ctrl_unsigned_lo_imm16_nxt;
end
assign D_ctrl_br_uncond = D_op_br|D_op_rsv02;
assign R_ctrl_br_uncond_nxt = D_ctrl_br_uncond;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_uncond <= 0;
else if (R_en)
R_ctrl_br_uncond <= R_ctrl_br_uncond_nxt;
end
assign D_ctrl_br = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62;
assign R_ctrl_br_nxt = D_ctrl_br;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br <= 0;
else if (R_en)
R_ctrl_br <= R_ctrl_br_nxt;
end
assign D_ctrl_alu_subtract = D_op_sub|
D_op_rsvx25|
D_op_cmplti|
D_op_cmpltui|
D_op_cmplt|
D_op_cmpltu|
D_op_blt|
D_op_bltu|
D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpge|
D_op_cmpgeu|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42;
assign R_ctrl_alu_subtract_nxt = D_ctrl_alu_subtract;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_subtract <= 0;
else if (R_en)
R_ctrl_alu_subtract <= R_ctrl_alu_subtract_nxt;
end
assign D_ctrl_alu_signed_comparison = D_op_cmpge|D_op_cmpgei|D_op_cmplt|D_op_cmplti|D_op_bge|D_op_blt;
assign R_ctrl_alu_signed_comparison_nxt = D_ctrl_alu_signed_comparison;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_signed_comparison <= 0;
else if (R_en)
R_ctrl_alu_signed_comparison <= R_ctrl_alu_signed_comparison_nxt;
end
assign D_ctrl_br_cmp = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_rsvx00|
D_op_cmpge|
D_op_cmplt|
D_op_cmpne|
D_op_cmpgeu|
D_op_cmpltu|
D_op_cmpeq|
D_op_rsvx56;
assign R_ctrl_br_cmp_nxt = D_ctrl_br_cmp;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_br_cmp <= 0;
else if (R_en)
R_ctrl_br_cmp <= R_ctrl_br_cmp_nxt;
end
assign D_ctrl_ld_signed = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63;
assign R_ctrl_ld_signed_nxt = D_ctrl_ld_signed;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_signed <= 0;
else if (R_en)
R_ctrl_ld_signed <= R_ctrl_ld_signed_nxt;
end
assign D_ctrl_ld = D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio;
assign R_ctrl_ld_nxt = D_ctrl_ld;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld <= 0;
else if (R_en)
R_ctrl_ld <= R_ctrl_ld_nxt;
end
assign D_ctrl_ld_non_io = D_op_ldbu|D_op_ldhu|D_op_ldb|D_op_ldh|D_op_ldw|D_op_ldl;
assign R_ctrl_ld_non_io_nxt = D_ctrl_ld_non_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_non_io <= 0;
else if (R_en)
R_ctrl_ld_non_io <= R_ctrl_ld_non_io_nxt;
end
assign D_ctrl_st = D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61;
assign R_ctrl_st_nxt = D_ctrl_st;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_st <= 0;
else if (R_en)
R_ctrl_st <= R_ctrl_st_nxt;
end
assign D_ctrl_ld_io = D_op_ldbuio|D_op_ldhuio|D_op_ldbio|D_op_ldhio|D_op_ldwio|D_op_rsv63;
assign R_ctrl_ld_io_nxt = D_ctrl_ld_io;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ld_io <= 0;
else if (R_en)
R_ctrl_ld_io <= R_ctrl_ld_io_nxt;
end
assign D_ctrl_b_is_dst = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda;
assign R_ctrl_b_is_dst_nxt = D_ctrl_b_is_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_b_is_dst <= 0;
else if (R_en)
R_ctrl_b_is_dst <= R_ctrl_b_is_dst_nxt;
end
assign D_ctrl_ignore_dst = D_op_br|
D_op_bge|
D_op_blt|
D_op_bne|
D_op_beq|
D_op_bgeu|
D_op_bltu|
D_op_rsv62|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57;
assign R_ctrl_ignore_dst_nxt = D_ctrl_ignore_dst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_ignore_dst <= 0;
else if (R_en)
R_ctrl_ignore_dst <= R_ctrl_ignore_dst_nxt;
end
assign D_ctrl_src2_choose_imm = D_op_addi|
D_op_andhi|
D_op_orhi|
D_op_xorhi|
D_op_andi|
D_op_ori|
D_op_xori|
D_op_call|
D_op_rdprs|
D_op_cmpgei|
D_op_cmplti|
D_op_cmpnei|
D_op_cmpgeui|
D_op_cmpltui|
D_op_cmpeqi|
D_op_jmpi|
D_op_rsv09|
D_op_rsv17|
D_op_rsv25|
D_op_rsv33|
D_op_rsv41|
D_op_rsv49|
D_op_rsv57|
D_op_ldb|
D_op_ldh|
D_op_ldl|
D_op_ldw|
D_op_ldbio|
D_op_ldhio|
D_op_ldwio|
D_op_rsv63|
D_op_ldbu|
D_op_ldhu|
D_op_ldbuio|
D_op_ldhuio|
D_op_initd|
D_op_initda|
D_op_flushd|
D_op_flushda|
D_op_stb|
D_op_sth|
D_op_stw|
D_op_stc|
D_op_stbio|
D_op_sthio|
D_op_stwio|
D_op_rsv61|
D_op_roli|
D_op_rsvx10|
D_op_slli|
D_op_srli|
D_op_rsvx34|
D_op_rsvx42|
D_op_rsvx50|
D_op_srai;
assign R_ctrl_src2_choose_imm_nxt = D_ctrl_src2_choose_imm;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_src2_choose_imm <= 0;
else if (R_en)
R_ctrl_src2_choose_imm <= R_ctrl_src2_choose_imm_nxt;
end
assign D_ctrl_wrctl_inst = D_op_wrctl;
assign R_ctrl_wrctl_inst_nxt = D_ctrl_wrctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_wrctl_inst <= 0;
else if (R_en)
R_ctrl_wrctl_inst <= R_ctrl_wrctl_inst_nxt;
end
assign D_ctrl_rdctl_inst = D_op_rdctl;
assign R_ctrl_rdctl_inst_nxt = D_ctrl_rdctl_inst;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_rdctl_inst <= 0;
else if (R_en)
R_ctrl_rdctl_inst <= R_ctrl_rdctl_inst_nxt;
end
assign D_ctrl_force_src2_zero = D_op_call|
D_op_rsv02|
D_op_nextpc|
D_op_callr|
D_op_trap|
D_op_rsvx44|
D_op_intr|
D_op_rsvx60|
D_op_break|
D_op_hbreak|
D_op_eret|
D_op_bret|
D_op_rsvx17|
D_op_rsvx25|
D_op_ret|
D_op_jmp|
D_op_rsvx21|
D_op_jmpi;
assign R_ctrl_force_src2_zero_nxt = D_ctrl_force_src2_zero;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_force_src2_zero <= 0;
else if (R_en)
R_ctrl_force_src2_zero <= R_ctrl_force_src2_zero_nxt;
end
assign D_ctrl_alu_force_xor = D_op_cmpgei|
D_op_cmpgeui|
D_op_cmpeqi|
D_op_cmpge|
D_op_cmpgeu|
D_op_cmpeq|
D_op_cmpnei|
D_op_cmpne|
D_op_bge|
D_op_rsv10|
D_op_bgeu|
D_op_rsv42|
D_op_beq|
D_op_rsv34|
D_op_bne|
D_op_rsv62|
D_op_br|
D_op_rsv02;
assign R_ctrl_alu_force_xor_nxt = D_ctrl_alu_force_xor;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
R_ctrl_alu_force_xor <= 0;
else if (R_en)
R_ctrl_alu_force_xor <= R_ctrl_alu_force_xor_nxt;
end
//data_master, which is an e_avalon_master
//instruction_master, which is an e_avalon_master
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign F_inst = (F_op_call)? 56'h20202063616c6c :
(F_op_jmpi)? 56'h2020206a6d7069 :
(F_op_ldbu)? 56'h2020206c646275 :
(F_op_addi)? 56'h20202061646469 :
(F_op_stb)? 56'h20202020737462 :
(F_op_br)? 56'h20202020206272 :
(F_op_ldb)? 56'h202020206c6462 :
(F_op_cmpgei)? 56'h20636d70676569 :
(F_op_ldhu)? 56'h2020206c646875 :
(F_op_andi)? 56'h202020616e6469 :
(F_op_sth)? 56'h20202020737468 :
(F_op_bge)? 56'h20202020626765 :
(F_op_ldh)? 56'h202020206c6468 :
(F_op_cmplti)? 56'h20636d706c7469 :
(F_op_initda)? 56'h20696e69746461 :
(F_op_ori)? 56'h202020206f7269 :
(F_op_stw)? 56'h20202020737477 :
(F_op_blt)? 56'h20202020626c74 :
(F_op_ldw)? 56'h202020206c6477 :
(F_op_cmpnei)? 56'h20636d706e6569 :
(F_op_flushda)? 56'h666c7573686461 :
(F_op_xori)? 56'h202020786f7269 :
(F_op_bne)? 56'h20202020626e65 :
(F_op_cmpeqi)? 56'h20636d70657169 :
(F_op_ldbuio)? 56'h206c646275696f :
(F_op_muli)? 56'h2020206d756c69 :
(F_op_stbio)? 56'h2020737462696f :
(F_op_beq)? 56'h20202020626571 :
(F_op_ldbio)? 56'h20206c6462696f :
(F_op_cmpgeui)? 56'h636d7067657569 :
(F_op_ldhuio)? 56'h206c646875696f :
(F_op_andhi)? 56'h2020616e646869 :
(F_op_sthio)? 56'h2020737468696f :
(F_op_bgeu)? 56'h20202062676575 :
(F_op_ldhio)? 56'h20206c6468696f :
(F_op_cmpltui)? 56'h636d706c747569 :
(F_op_initd)? 56'h2020696e697464 :
(F_op_orhi)? 56'h2020206f726869 :
(F_op_stwio)? 56'h2020737477696f :
(F_op_bltu)? 56'h202020626c7475 :
(F_op_ldwio)? 56'h20206c6477696f :
(F_op_flushd)? 56'h20666c75736864 :
(F_op_xorhi)? 56'h2020786f726869 :
(F_op_eret)? 56'h20202065726574 :
(F_op_roli)? 56'h202020726f6c69 :
(F_op_rol)? 56'h20202020726f6c :
(F_op_flushp)? 56'h20666c75736870 :
(F_op_ret)? 56'h20202020726574 :
(F_op_nor)? 56'h202020206e6f72 :
(F_op_mulxuu)? 56'h206d756c787575 :
(F_op_cmpge)? 56'h2020636d706765 :
(F_op_bret)? 56'h20202062726574 :
(F_op_ror)? 56'h20202020726f72 :
(F_op_flushi)? 56'h20666c75736869 :
(F_op_jmp)? 56'h202020206a6d70 :
(F_op_and)? 56'h20202020616e64 :
(F_op_cmplt)? 56'h2020636d706c74 :
(F_op_slli)? 56'h202020736c6c69 :
(F_op_sll)? 56'h20202020736c6c :
(F_op_or)? 56'h20202020206f72 :
(F_op_mulxsu)? 56'h206d756c787375 :
(F_op_cmpne)? 56'h2020636d706e65 :
(F_op_srli)? 56'h20202073726c69 :
(F_op_srl)? 56'h2020202073726c :
(F_op_nextpc)? 56'h206e6578747063 :
(F_op_callr)? 56'h202063616c6c72 :
(F_op_xor)? 56'h20202020786f72 :
(F_op_mulxss)? 56'h206d756c787373 :
(F_op_cmpeq)? 56'h2020636d706571 :
(F_op_divu)? 56'h20202064697675 :
(F_op_div)? 56'h20202020646976 :
(F_op_rdctl)? 56'h2020726463746c :
(F_op_mul)? 56'h202020206d756c :
(F_op_cmpgeu)? 56'h20636d70676575 :
(F_op_initi)? 56'h2020696e697469 :
(F_op_trap)? 56'h20202074726170 :
(F_op_wrctl)? 56'h2020777263746c :
(F_op_cmpltu)? 56'h20636d706c7475 :
(F_op_add)? 56'h20202020616464 :
(F_op_break)? 56'h2020627265616b :
(F_op_hbreak)? 56'h2068627265616b :
(F_op_sync)? 56'h20202073796e63 :
(F_op_sub)? 56'h20202020737562 :
(F_op_srai)? 56'h20202073726169 :
(F_op_sra)? 56'h20202020737261 :
(F_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign D_inst = (D_op_call)? 56'h20202063616c6c :
(D_op_jmpi)? 56'h2020206a6d7069 :
(D_op_ldbu)? 56'h2020206c646275 :
(D_op_addi)? 56'h20202061646469 :
(D_op_stb)? 56'h20202020737462 :
(D_op_br)? 56'h20202020206272 :
(D_op_ldb)? 56'h202020206c6462 :
(D_op_cmpgei)? 56'h20636d70676569 :
(D_op_ldhu)? 56'h2020206c646875 :
(D_op_andi)? 56'h202020616e6469 :
(D_op_sth)? 56'h20202020737468 :
(D_op_bge)? 56'h20202020626765 :
(D_op_ldh)? 56'h202020206c6468 :
(D_op_cmplti)? 56'h20636d706c7469 :
(D_op_initda)? 56'h20696e69746461 :
(D_op_ori)? 56'h202020206f7269 :
(D_op_stw)? 56'h20202020737477 :
(D_op_blt)? 56'h20202020626c74 :
(D_op_ldw)? 56'h202020206c6477 :
(D_op_cmpnei)? 56'h20636d706e6569 :
(D_op_flushda)? 56'h666c7573686461 :
(D_op_xori)? 56'h202020786f7269 :
(D_op_bne)? 56'h20202020626e65 :
(D_op_cmpeqi)? 56'h20636d70657169 :
(D_op_ldbuio)? 56'h206c646275696f :
(D_op_muli)? 56'h2020206d756c69 :
(D_op_stbio)? 56'h2020737462696f :
(D_op_beq)? 56'h20202020626571 :
(D_op_ldbio)? 56'h20206c6462696f :
(D_op_cmpgeui)? 56'h636d7067657569 :
(D_op_ldhuio)? 56'h206c646875696f :
(D_op_andhi)? 56'h2020616e646869 :
(D_op_sthio)? 56'h2020737468696f :
(D_op_bgeu)? 56'h20202062676575 :
(D_op_ldhio)? 56'h20206c6468696f :
(D_op_cmpltui)? 56'h636d706c747569 :
(D_op_initd)? 56'h2020696e697464 :
(D_op_orhi)? 56'h2020206f726869 :
(D_op_stwio)? 56'h2020737477696f :
(D_op_bltu)? 56'h202020626c7475 :
(D_op_ldwio)? 56'h20206c6477696f :
(D_op_flushd)? 56'h20666c75736864 :
(D_op_xorhi)? 56'h2020786f726869 :
(D_op_eret)? 56'h20202065726574 :
(D_op_roli)? 56'h202020726f6c69 :
(D_op_rol)? 56'h20202020726f6c :
(D_op_flushp)? 56'h20666c75736870 :
(D_op_ret)? 56'h20202020726574 :
(D_op_nor)? 56'h202020206e6f72 :
(D_op_mulxuu)? 56'h206d756c787575 :
(D_op_cmpge)? 56'h2020636d706765 :
(D_op_bret)? 56'h20202062726574 :
(D_op_ror)? 56'h20202020726f72 :
(D_op_flushi)? 56'h20666c75736869 :
(D_op_jmp)? 56'h202020206a6d70 :
(D_op_and)? 56'h20202020616e64 :
(D_op_cmplt)? 56'h2020636d706c74 :
(D_op_slli)? 56'h202020736c6c69 :
(D_op_sll)? 56'h20202020736c6c :
(D_op_or)? 56'h20202020206f72 :
(D_op_mulxsu)? 56'h206d756c787375 :
(D_op_cmpne)? 56'h2020636d706e65 :
(D_op_srli)? 56'h20202073726c69 :
(D_op_srl)? 56'h2020202073726c :
(D_op_nextpc)? 56'h206e6578747063 :
(D_op_callr)? 56'h202063616c6c72 :
(D_op_xor)? 56'h20202020786f72 :
(D_op_mulxss)? 56'h206d756c787373 :
(D_op_cmpeq)? 56'h2020636d706571 :
(D_op_divu)? 56'h20202064697675 :
(D_op_div)? 56'h20202020646976 :
(D_op_rdctl)? 56'h2020726463746c :
(D_op_mul)? 56'h202020206d756c :
(D_op_cmpgeu)? 56'h20636d70676575 :
(D_op_initi)? 56'h2020696e697469 :
(D_op_trap)? 56'h20202074726170 :
(D_op_wrctl)? 56'h2020777263746c :
(D_op_cmpltu)? 56'h20636d706c7475 :
(D_op_add)? 56'h20202020616464 :
(D_op_break)? 56'h2020627265616b :
(D_op_hbreak)? 56'h2068627265616b :
(D_op_sync)? 56'h20202073796e63 :
(D_op_sub)? 56'h20202020737562 :
(D_op_srai)? 56'h20202073726169 :
(D_op_sra)? 56'h20202020737261 :
(D_op_intr)? 56'h202020696e7472 :
56'h20202020424144;
assign F_vinst = F_valid ? F_inst : {7{8'h2d}};
assign D_vinst = D_valid ? D_inst : {7{8'h2d}};
assign R_vinst = R_valid ? D_inst : {7{8'h2d}};
assign E_vinst = E_valid ? D_inst : {7{8'h2d}};
assign W_vinst = W_valid ? D_inst : {7{8'h2d}};
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: mult_21_coeff_26561.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.3 Build 178 02/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mult_21_coeff_26561 (
clken,
clock,
dataa,
result);
input clken;
input clock;
input [20:0] dataa;
output [41:0] result;
wire [41:0] sub_wire0;
wire [20:0] sub_wire1 = 21'd26561;
wire [41:0] result = sub_wire0[41:0];
lpm_mult lpm_mult_component (
.clock (clock),
.datab (sub_wire1),
.clken (clken),
.dataa (dataa),
.result (sub_wire0),
.aclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=NO,INPUT_B_IS_CONSTANT=YES,MAXIMIZE_SPEED=1",
lpm_mult_component.lpm_pipeline = 3,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 21,
lpm_mult_component.lpm_widthb = 21,
lpm_mult_component.lpm_widthp = 42;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/fuji/BUFR.v,v 1.6 2011/08/09 22:45:10 yanx Exp $
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.i (O.72)
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Regional Clock Buffer
// /___/ /\ Filename : BUFR.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:06 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 04/04/2005 - Add SIM_DEVICE paramter to support rainier. CE pin has 4 clock
// latency for Virtex 4 and none for Rainier
// 07/25/05 - Updated names to Virtex5
// 08/31/05 - Add ce_en to sensitivity list of i_in which make ce asynch.
// 05/23/06 - Add count =0 and first_rise=1 when CE = 0 (CR232206).
// 07/19/06 - Add wire declaration for undeclared wire signals.
// 04/01/09 - CR 517236 -- Added VIRTEX6 support
// 11/13/09 - Added VIRTEX7
// 01/20/10 - Change VIRTEX7 to FUJI (CR545223)
// 02/23/10 - Use assign for o_out (CR543271)
// 06/09/10 - Change FUJI to 7_SERIES
// 08/18/10 - Change 7_SERIES to 7SERIES (CR571653)
// 08/09/11 - Add 7SERIES to ce_en logic (CR620544)
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 03/15/12 - Match with hardware (CR 650440)
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module BUFR (O, CE, CLR, I);
output O;
input CE;
input CLR;
input I;
parameter BUFR_DIVIDE = "BYPASS";
parameter SIM_DEVICE = "VIRTEX4";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
integer count, period_toggle, half_period_toggle;
reg first_rise, half_period_done;
reg notifier;
reg o_out_divide = 0;
wire o_out;
reg ce_enable1, ce_enable2, ce_enable3, ce_enable4;
tri0 GSR = glbl.GSR;
wire i_in, ce_in, clr_in, gsr_in, ce_en, i_ce;
buf buf_i (i_in, I);
buf buf_ce (ce_in, CE);
buf buf_clr (clr_in, CLR);
buf buf_gsr (gsr_in, GSR);
buf buf_o (O, o_out);
initial begin
case (BUFR_DIVIDE)
"BYPASS" : period_toggle = 0;
"1" : begin
period_toggle = 1;
half_period_toggle = 1;
end
"2" : begin
period_toggle = 2;
half_period_toggle = 2;
end
"3" : begin
period_toggle = 4;
half_period_toggle = 2;
end
"4" : begin
period_toggle = 4;
half_period_toggle = 4;
end
"5" : begin
period_toggle = 6;
half_period_toggle = 4;
end
"6" : begin
period_toggle = 6;
half_period_toggle = 6;
end
"7" : begin
period_toggle = 8;
half_period_toggle = 6;
end
"8" : begin
period_toggle = 8;
half_period_toggle = 8;
end
default : begin
$display("Attribute Syntax Error : The attribute BUFR_DIVIDE on BUFR instance %m is set to %s. Legal values for this attribute are BYPASS, 1, 2, 3, 4, 5, 6, 7 or 8.", BUFR_DIVIDE);
$finish;
end
endcase // case(BUFR_DIVIDE)
case (SIM_DEVICE)
"VIRTEX4" : ;
"VIRTEX5" : ;
"VIRTEX6" : ;
"7SERIES" : ;
default : begin
$display("Attribute Syntax Error : The attribute SIM_DEVICE on BUFR instance %m is set to %s. Legal values for this attribute are VIRTEX4 or VIRTEX5 or VIRTEX6 or 7SERIES.", SIM_DEVICE);
$finish;
end
endcase
end // initial begin
always @(gsr_in or clr_in)
if (gsr_in == 1'b1 || clr_in == 1'b1) begin
assign o_out_divide = 1'b0;
assign count = 0;
assign first_rise = 1'b1;
assign half_period_done = 1'b0;
if (gsr_in == 1'b1) begin
assign ce_enable1 = 1'b0;
assign ce_enable2 = 1'b0;
assign ce_enable3 = 1'b0;
assign ce_enable4 = 1'b0;
end
end
else if (gsr_in == 1'b0 || clr_in == 1'b0) begin
deassign o_out_divide;
deassign count;
deassign first_rise;
deassign half_period_done;
if (gsr_in == 1'b0) begin
deassign ce_enable1;
deassign ce_enable2;
deassign ce_enable3;
deassign ce_enable4;
end
end
always @(negedge i_in)
begin
ce_enable1 <= ce_in;
ce_enable2 <= ce_enable1;
ce_enable3 <= ce_enable2;
ce_enable4 <= ce_enable3;
end
assign ce_en = ((SIM_DEVICE == "VIRTEX5") || (SIM_DEVICE == "VIRTEX6") || (SIM_DEVICE == "7SERIES")) ? ce_in : ce_enable4;
assign i_ce = i_in & ce_en;
generate
case (SIM_DEVICE)
"VIRTEX4" : begin
always @(i_in or ce_en)
if (ce_en == 1'b1) begin
if (i_in == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
first_rise = 1'b0;
end
else if (count == half_period_toggle && half_period_done == 1'b0) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b1;
count = 0;
end
else if (count == period_toggle && half_period_done == 1'b1) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b0;
count = 0;
end
if (first_rise == 1'b0)
count = count + 1;
end // if (ce_in == 1'b1)
else begin
count = 0;
first_rise = 1;
end
end
"VIRTEX5","VIRTEX6","7SERIES" : begin
always @(i_ce)
begin
if (i_ce == 1'b1 && first_rise == 1'b1) begin
o_out_divide = 1'b1;
first_rise = 1'b0;
end
else if (count == half_period_toggle && half_period_done == 1'b0) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b1;
count = 0;
end
else if (count == period_toggle && half_period_done == 1'b1) begin
o_out_divide = ~o_out_divide;
half_period_done = 1'b0;
count = 0;
end
if (first_rise == 1'b0) begin
count = count + 1;
end // if (ce_in == 1'b1)
end
end
endcase
endgenerate
assign o_out = (period_toggle == 0) ? i_in : o_out_divide;
//*** Timing Checks Start here
always @(notifier) begin
o_out_divide <= 1'bx;
end
`ifdef XIL_TIMING
specify
(CLR => O) = (0:0:0, 0:0:0);
(I => O) = (0:0:0, 0:0:0);
$period (negedge I, 0:0:0, notifier);
$period (posedge I, 0:0:0, notifier);
$setuphold (posedge I, posedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (posedge I, negedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I, posedge CE, 0:0:0, 0:0:0, notifier);
$setuphold (negedge I, negedge CE, 0:0:0, 0:0:0, notifier);
$width (posedge CLR, 0:0:0, 0, notifier);
$width (posedge I, 0:0:0, 0, notifier);
$width (negedge I, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule // BUFR
`endcelldefine
|
(*
Copyright 2014 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Website: http://nuprl.org/html/verification/
Authors: Abhishek Anand & Vincent Rahli
*)
Require Export sovar.
Require Export alphaeq_sub.
Lemma range_combine {o} :
forall (ts : list (@NTerm o)) vs,
length vs = length ts
-> range (combine vs ts) = ts.
Proof.
induction ts; destruct vs; introv len; allsimpl; cpx.
rw IHts; sp.
Qed.
Lemma swap_apply_list {o} :
forall ts (t : @NTerm o) s,
swap s (apply_list t ts) = apply_list (swap s t) (map (swap s) ts).
Proof.
induction ts; simpl; introv; auto.
rw IHts; simpl; auto.
Qed.
Fixpoint so_swap {p} (l : swapping) (t : @SOTerm p) :=
match t with
| sovar v ts =>
if bnull ts
then sovar (swapvar l v) []
else sovar v (map (so_swap l) ts)
| soterm o bts => soterm o (map (so_swapbt l) bts)
end
with so_swapbt {p} (l : swapping) (bt : SOBTerm) :=
match bt with
| sobterm vs t => sobterm (swapbvars l vs) (so_swap l t)
end.
(*
Lemma soterm2nterm_so_swap {o} :
forall (t : @SOTerm o) s,
soterm2nterm (so_swap s t) = swap s (soterm2nterm t).
Proof.
soterm_ind t as [ v ts ind | op lbt ind ] Case; simpl; introv.
- Case "sovar".
rw @swap_apply_list; simpl.
allrw map_map; unfold compose.
f_equal.
apply eq_maps; introv i.
eapply ind in i; eauto.
- Case "soterm".
apply f_equal.
allrw map_map; unfold compose.
apply eq_maps; introv i.
destruct x; allsimpl.
f_equal.
eapply ind in i; eauto.
Qed.
*)
Lemma wf_soterm_so_swap {o} :
forall (t : @SOTerm o) s,
wf_soterm t <=> wf_soterm (so_swap s t).
Proof.
soterm_ind t as [ v ts ind | op lbt ind ] Case; simpl; introv.
- Case "sovar".
boolvar; subst; allsimpl; allrw @wf_sovar; tcsp.
split; introv k i; allsimpl.
+ rw in_map_iff in i; exrepnd; subst.
apply ind; auto.
+ pose proof (k (so_swap s t)) as h; autodimp h hyp.
rw in_map_iff; eexists; dands; eauto.
apply ind in h; tcsp.
- Case "soterm".
allrw @wf_soterm_iff; split; intro k; repnd; dands.
+ rw <- k0.
rw map_map; unfold compose; apply eq_maps; introv i.
destruct x; simpl.
rw length_swapbvars; auto.
+ introv i.
rw in_map_iff in i; exrepnd; subst.
destruct a; allsimpl; ginv.
dup i1 as i.
eapply ind in i; rw <- i.
apply k in i1; auto.
+ rw <- k0.
rw map_map; unfold compose; apply eq_maps; introv i.
destruct x; simpl.
rw length_swapbvars; auto.
+ introv i.
pose proof (k (swapbvars s vs) (so_swap s t)) as h; autodimp h hyp.
rw in_map_iff; eexists; dands; eauto.
dup i as j.
eapply ind in i; rw <- i in h; auto.
Qed.
Inductive so_alphaeq_vs {p} (l : list NVar) : @SOTerm p -> @SOTerm p -> Type :=
| soaeqv :
forall v ts1 ts2,
length ts1 = length ts2
-> (forall t1 t2, LIn (t1,t2) (combine ts1 ts2) -> so_alphaeq_vs l t1 t2)
-> so_alphaeq_vs l (sovar v ts1) (sovar v ts2)
| soaeqo :
forall o bts1 bts2,
length bts1 = length bts2
-> (forall b1 b2,
LIn (b1,b2) (combine bts1 bts2)
-> so_alphaeqbt_vs l b1 b2)
-> so_alphaeq_vs l (soterm o bts1) (soterm o bts2)
with so_alphaeqbt_vs {p} (l : list NVar) : @SOBTerm p -> @SOBTerm p -> Type :=
| soaeqbt :
forall vs vs1 vs2 t1 t2,
length vs = length vs1
-> length vs = length vs2
-> disjoint vs (l ++ vs1 ++ vs2 ++ all_fo_vars t1 ++ all_fo_vars t2)
-> no_repeats vs
-> so_alphaeq_vs l (so_swap (mk_swapping vs1 vs) t1) (so_swap (mk_swapping vs2 vs) t2)
-> so_alphaeqbt_vs l (sobterm vs1 t1) (sobterm vs2 t2).
Hint Constructors so_alphaeq_vs.
Hint Constructors so_alphaeqbt_vs.
Definition so_alphaeq {p} := @so_alphaeq_vs p [].
Definition so_alphaeqbt {p} := @so_alphaeqbt_vs p [].
Definition alphaeq_sk {o} (sk1 sk2 : @sosub_kind o) :=
alphaeqbt (sk2bterm sk1) (sk2bterm sk2).
Lemma alphaeq_sk_iff_alphaeq_bterm {o} :
forall vs1 vs2 (t1 t2 : @NTerm o),
alphaeqbt (bterm vs1 t1) (bterm vs2 t2)
<=> alphaeq_sk (sosk vs1 t1) (sosk vs2 t2).
Proof. sp. Qed.
Lemma symm_rel_alphaeq_sk {o} :
symm_rel (@alphaeq_sk o).
Proof.
unfold alphaeq_sk, symm_rel; introv h.
apply alphaeqbt_eq.
apply alpha_eq_bterm_sym.
apply alphaeqbt_eq; auto.
Qed.
Hint Immediate symm_rel_alphaeq_sk.
Lemma alphaeq_sk_eq_length {o} :
forall (a b : @sosub_kind o),
alphaeq_sk a b -> length (sosk_vs a) = length (sosk_vs b).
Proof.
introv aeq.
invertsn aeq; auto.
destruct a, b; allsimpl; ginv; omega.
Qed.
Definition default_soterm {o} : @SOTerm o := soterm (Can NAxiom) [].
Definition default_sobterm {o} : @SOBTerm o := sobterm [] default_soterm.
Definition default_sk {o} : @sosub_kind o := sosk [] mk_axiom.
Definition bin_rel_sk {p} := binrel_list (@default_sk p).
Lemma binrel_list_sym :
forall T (def : T) R,
symm_rel R
-> symm_rel (binrel_list def R).
Proof.
unfold binrel_list; introv sr h; allsimpl; repnd; dands; auto.
introv k; rw <- h0 in k; apply h in k.
apply sr; auto.
Qed.
Lemma bin_rel_sk_sym {o} :
forall R, symm_rel R -> symm_rel (@bin_rel_sk o R).
Proof.
unfold bin_rel_sk; introv sr h.
apply binrel_list_sym; auto.
Qed.
Lemma bin_rel_sk_cons {o} :
forall (sk1 sk2 : @sosub_kind o) sks1 sks2,
bin_rel_sk alphaeq_sk (sk1 :: sks1) (sk2 :: sks2)
<=> (bin_rel_sk alphaeq_sk sks1 sks2 # alphaeq_sk sk1 sk2).
Proof.
introv; unfold bin_rel_sk, binrel_list; simpl.
split; intro k; repnd; cpx; dands; auto.
- introv i.
pose proof (k (S n)) as h; autodimp h hyp; omega.
- pose proof (k 0) as h; autodimp h hyp; omega.
- introv i.
destruct n; cpx.
Qed.
Lemma alphaeq_sosub_kind_if_alphaeq_sosub_find {o} :
forall (vs : list NVar) (sks1 sks2 : list (@sosub_kind o)) (sk1 sk2 : sosub_kind) (sv : sovar_sig),
length vs = length sks1
-> length vs = length sks2
-> bin_rel_sk alphaeq_sk sks1 sks2
-> sosub_find (combine vs sks1) sv = Some sk1
-> sosub_find (combine vs sks2) sv = Some sk2
-> alphaeq_sk sk1 sk2.
Proof.
induction vs; introv len1 len2 aeq f1 f2; allsimpl; cpx.
destruct sks1; destruct sks2; allsimpl; cpx.
apply binrel_list_cons in aeq; repnd.
fold (@bin_rel_sk o) in aeq0.
applydup @alphaeq_sk_eq_length in aeq; allsimpl.
destruct s; destruct s0; boolvar; allsimpl; cpx;
try (complete (provefalse; apply n1; sp)).
apply IHvs with (sks1 := sks1) (sks2 := sks2) (sv := sv); auto.
Qed.
Lemma false_if_alphaeq_sosub_find {o} :
forall (vs : list NVar) (sks1 sks2 : list (@sosub_kind o)) (sk : sosub_kind) (sv : sovar_sig),
length vs = length sks1
-> length vs = length sks2
-> bin_rel_sk alphaeq_sk sks1 sks2
-> sosub_find (combine vs sks1) sv = Some sk
-> sosub_find (combine vs sks2) sv = None
-> False.
Proof.
induction vs; introv len1 len2 aeq f1 f2; allsimpl; cpx.
destruct sks1; destruct sks2; allsimpl; cpx.
apply binrel_list_cons in aeq; repnd.
fold (@bin_rel_sk o) in aeq0.
applydup @alphaeq_sk_eq_length in aeq; allsimpl.
destruct s; destruct s0; boolvar; allsimpl; cpx;
try (complete (provefalse; apply n1; sp)).
eapply IHvs in f1; eauto.
Qed.
Lemma alphaeq_apply_list {o} :
forall ts1 ts2 (t1 t2 : @NTerm o),
alphaeq t1 t2
-> bin_rel_nterm alpha_eq ts1 ts2
-> alphaeq (apply_list t1 ts1) (apply_list t2 ts2).
Proof.
induction ts1; introv aeq brel; destruct ts2; allsimpl; tcsp.
- unfold bin_rel_nterm, binrel_list in brel; repnd; allsimpl; cpx.
- unfold bin_rel_nterm, binrel_list in brel; repnd; allsimpl; cpx.
- apply binrel_list_cons in brel; repnd.
apply IHts1; auto.
apply alphaeq_eq.
apply alphaeq_eq in aeq.
prove_alpha_eq4.
introv h; destruct n0.
+ apply alphaeqbt_nilv2; auto.
+ destruct n0; sp.
apply alphaeqbt_nilv2; auto.
Qed.
Lemma sosize_so_swap {p} :
forall (t : @SOTerm p) l,
sosize (so_swap l t) = sosize t.
Proof.
soterm_ind1 t as [v ts Hind | o bts Hind] Case; introv; simpl; auto.
- boolvar; subst; simpl; auto.
f_equal; f_equal.
rw map_map; unfold compose.
apply eq_maps; introv i.
apply Hind; sp.
- f_equal; f_equal.
rw map_map; unfold compose.
apply eq_maps; introv i.
destruct x; simpl.
eapply Hind; eauto.
Qed.
Lemma sosize_so_swap_le {o} :
forall (t : @SOTerm o) sw,
sosize (so_swap sw t) <= sosize t.
Proof.
introv; rw @sosize_so_swap; sp.
Qed.
Lemma disjoint_all_fo_vars_so_swap {p} :
forall (t : @SOTerm p) vs vs1 vs2,
length vs1 = length vs2
-> disjoint vs vs1
-> disjoint vs vs2
-> disjoint vs (all_fo_vars t)
-> disjoint vs (all_fo_vars (so_swap (mk_swapping vs1 vs2) t)).
Proof.
soterm_ind1s t as [v ts Hind | o lbt Hind] Case; introv len disj1 disj2 disj3; allsimpl.
- Case "sovar".
boolvar; subst; simpl.
+ allrw disjoint_cons_r; repnd; dands; auto.
intro k; apply in_swapvar_disj_iff2 in k; auto.
+ allsimpl; allrw disjoint_cons_r; repnd.
dands; auto.
rw flat_map_map; unfold compose.
allrw disjoint_flat_map_r; introv i.
eapply Hind; eauto.
- Case "soterm".
rw flat_map_map.
rw disjoint_flat_map_r in disj3.
apply disjoint_flat_map_r; introv i.
applydup disj3 in i as d.
destruct x; unfold compose; allsimpl.
allrw disjoint_app_r; repnd.
dands; try (complete (eapply Hind; eauto)).
apply disjoint_swapbvars; auto.
Qed.
Lemma so_swap_so_swap {p} :
forall s1 s2 (t : @SOTerm p),
so_swap s1 (so_swap s2 t) = so_swap (s2 ++ s1) t.
Proof.
soterm_ind1 t as [v ts Hind | o lbt Hind] Case; simpl.
- Case "sovar".
boolvar; subst; allsimpl; boolvar; allsimpl; auto; tcsp;
try (complete (rw swapvar_swapvar; auto));
try (complete (destruct ts; allsimpl; tcsp)).
f_equal.
rw map_map; unfold compose.
apply eq_maps; introv i.
apply Hind; auto.
- Case "soterm".
f_equal.
rw map_map; unfold compose.
apply eq_maps; introv i.
destruct x; simpl.
apply Hind in i.
rw i.
rw swapbvars_swapbvars; auto.
Qed.
Lemma so_swap_app_so_swap {p} :
forall (t : @SOTerm p) vs1 vs2 vs3 vs4,
length vs1 = length vs3
-> length vs2 = length vs4
-> no_repeats vs3
-> no_repeats vs4
-> disjoint vs3 vs1
-> disjoint vs3 vs2
-> disjoint vs3 vs4
-> disjoint vs3 (all_fo_vars t)
-> disjoint vs4 (all_fo_vars t)
-> disjoint vs2 vs4
-> disjoint vs1 vs4
-> so_swap (mk_swapping (vs1 ++ vs2) (vs3 ++ vs4)) t
= so_swap
(mk_swapping (vs2 ++ swapbvars (mk_swapping vs2 vs4) vs1)
(vs4 ++ vs3))
t.
Proof.
soterm_ind1s t as [v ts Hind | o lbt Hind] Case;
introv len1 len2 norep2 norep3;
introv disj1 disj2 disj3 disj4 disj5 disj6 disj7.
- Case "sovar".
allsimpl; boolvar; subst; allsimpl.
+ allrw disjoint_singleton_r; repnd.
rw swapvar_app_swap; auto.
+ allrw disjoint_cons_r; repnd.
allrw disjoint_flat_map_r.
apply f_equal.
apply eq_maps; introv i.
apply Hind; auto.
- Case "soterm".
simpl.
f_equal.
apply eq_maps; introv i.
destruct x; simpl.
allsimpl.
allrw disjoint_flat_map_r.
applydup disj4 in i as d1.
applydup disj5 in i as d2.
allsimpl; allrw disjoint_app_r; repnd.
rw <- swapbvars_app_swap; auto.
f_equal.
eapply Hind; eauto.
Qed.
Lemma so_alphaeq_add_so_swap {p} :
forall vs vs1 vs2 (t1 t2 : @SOTerm p),
length vs1 = length vs2
-> no_repeats vs2
-> disjoint vs2 (vs1 ++ all_fo_vars t1 ++ all_fo_vars t2)
-> so_alphaeq_vs (vs1 ++ vs2 ++ vs) t1 t2
-> so_alphaeq_vs
(vs1 ++ vs2 ++ vs)
(so_swap (mk_swapping vs1 vs2) t1)
(so_swap (mk_swapping vs1 vs2) t2).
Proof.
soterm_ind1s t1 as [v1 ts1 Hind | o1 lbt1 Hind] Case; introv len norep2 disj aeq.
- Case "sovar".
inversion aeq as [? ? ? e imp|]; clear aeq; subst; allsimpl; auto.
boolvar; subst; allsimpl; tcsp;
try (complete (destruct ts2; allsimpl; cpx));
try (complete (destruct ts1; allsimpl; cpx)).
constructor; [allrw map_length; complete auto|].
introv i.
rw <- @map_combine in i.
rw in_map_iff in i; exrepnd; cpx; allsimpl.
applydup in_combine in i1; repnd.
apply Hind; auto.
repeat (first [ progress (allrw disjoint_app_r)
| progress (allrw disjoint_cons_r)
| progress (allrw disjoint_flat_map_r)
]); repnd.
dands; auto.
- Case "soterm".
allsimpl.
inversion aeq as [|? ? ? eqlens aeqbts e1 oeq]; subst; clear aeq.
allsimpl.
apply soaeqo; allrw map_length; auto.
introv lt.
rw <- @map_combine in lt; rw in_map_iff in lt; exrepnd; cpx; allsimpl.
applydup aeqbts in lt1 as aeq; repnd.
destruct a0 as [bvs1 t1].
destruct a as [bvs2 t2].
allsimpl.
applydup in_combine in lt1; repnd.
inversion aeq as [? ? ? ? ? leneq1 leneq2 d n a]; subst; clear aeq.
allrw disjoint_app_r; repnd.
allrw disjoint_flat_map_r.
applydup disj1 in lt2.
applydup disj in lt0.
allsimpl; allrw disjoint_app_r; repnd.
apply Hind with (vs0 := bvs1) (t := t1) in a; auto; allrw @sosize_so_swap; auto;
try (complete (allrw disjoint_app_r; dands; auto;
apply disjoint_all_fo_vars_so_swap; auto;
try (apply disjoint_sym; auto))).
repeat (rw @so_swap_so_swap in a).
repeat (rw mk_swapping_app in a; auto).
apply @soaeqbt with (vs := vs0); auto;
try (complete (rw length_swapbvars; omega)).
allrw disjoint_app_r; repnd.
pose proof (disjoint_swapbvars bvs1 vs0 vs1 vs2) as h1;
repeat (autodimp h1 hyp); try omega.
pose proof (disjoint_swapbvars bvs2 vs0 vs1 vs2) as h2;
repeat (autodimp h2 hyp); try omega.
pose proof (disjoint_all_fo_vars_so_swap t1 vs0 vs1 vs2) as h3;
repeat (autodimp h3 hyp); try omega.
pose proof (disjoint_all_fo_vars_so_swap t2 vs0 vs1 vs2) as h4;
repeat (autodimp h4 hyp); try omega.
allrw @so_swap_so_swap.
repeat (rw mk_swapping_app;[|complete omega]).
rw <- @so_swap_app_so_swap; auto; try (complete (apply disjoint_sym; auto)).
rw <- @so_swap_app_so_swap; auto; try (complete (apply disjoint_sym; auto)).
Qed.
Lemma so_swap_disj_chain {p} :
forall (t : @SOTerm p) vs1 vs vs2,
length vs = length vs1
-> length vs = length vs2
-> no_repeats vs
-> no_repeats vs2
-> disjoint vs (vs1 ++ vs2 ++ all_fo_vars t)
-> disjoint vs2 (vs1 ++ all_fo_vars t)
-> so_swap (mk_swapping (vs1 ++ vs) (vs ++ vs2)) t
= so_swap (mk_swapping vs1 vs2) t.
Proof.
soterm_ind1s t as [v ts Hind | o lbt Hind] Case;
introv len1 len2 norep1 norep2 disj1 disj2; allsimpl.
- Case "sovar".
allrw disjoint_app_r; allrw disjoint_cons_r; allrw disjoint_flat_map_r; repnd.
rw swapvar_disj_chain; auto;
try (complete (allrw disjoint_app_r; allrw disjoint_singleton_r; sp)).
boolvar; subst; allsimpl; tcsp.
f_equal.
apply eq_maps; introv i.
apply Hind; auto; allrw disjoint_app_r; sp.
- Case "soterm".
f_equal.
apply eq_maps; introv i.
destruct x; allsimpl.
allrw disjoint_app_r; repnd.
allrw disjoint_flat_map_r.
applydup disj1 in i; applydup disj2 in i; allsimpl.
allrw disjoint_app_r; repnd.
erewrite Hind; eauto; allrw disjoint_app_r; auto.
rw swapbvars_disj_chain; auto; allrw disjoint_app_r; auto.
Qed.
Lemma so_alphaeq_vs_implies_less {p} :
forall (t1 t2 : @SOTerm p) l1 l2,
so_alphaeq_vs l1 t1 t2
-> subvars l2 l1
-> so_alphaeq_vs l2 t1 t2.
Proof.
soterm_ind1s t1 as [v1 ts1 Hind | o1 lbt1 Hind] Case; introv aeq sv.
- Case "sovar".
inversion aeq as [? ? ? e imp|]; clear aeq; subst; auto.
constructor; auto.
introv i.
applydup imp in i.
apply in_combine in i; repnd.
eapply Hind; eauto.
- Case "soterm".
inversion aeq as [| ? ? ? len aeqbts]; subst; clear aeq.
constructor; auto.
introv i.
applydup aeqbts in i as h.
destruct b1 as [vs1 t1].
destruct b2 as [vs2 t2].
inversion h as [? ? ? ? ? len1 len2 disj norep a]; subst.
applydup in_combine in i; repnd.
pose proof (Hind
t1
(so_swap (mk_swapping vs1 vs) t1)
vs1
i1) as a1.
autodimp a1 hyp; try (complete (rw @sosize_so_swap; auto)).
pose proof (a1 (so_swap (mk_swapping vs2 vs) t2)
l1
l2
a
sv) as a2;
clear a1.
apply @soaeqbt with (vs := vs); auto; try omega.
allrw disjoint_app_r; repnd; dands; auto.
unfold disjoint; introv x y.
rw subvars_prop in sv.
apply disj0 in x.
apply sv in y; auto.
Qed.
Lemma so_alphaeq_implies_alphaeq_vs {p} :
forall t1 t2 : @SOTerm p, so_alphaeq t1 t2 -> forall l, so_alphaeq_vs l t1 t2.
Proof.
soterm_ind1s t1 as [v1 ts1 ind1 | o1 lbt1 ind1] Case; introv aeq; introv.
- Case "sovar".
inversion aeq as [? ? ? len imp|]; clear aeq; subst; auto.
constructor; auto.
introv i.
applydup imp in i.
apply ind1; auto.
apply in_combine in i; sp.
- inversion aeq as [| ? ? ? len aeqbts]; subst; clear aeq.
constructor; auto.
introv i.
applydup aeqbts in i as h.
destruct b1 as [l1 t1].
destruct b2 as [l2 t2].
inversion h as [? ? ? ? ? len1 len2 disj norep a]; subst.
pose proof (fresh_vars (length vs)
(l ++ vs
++ l1
++ l2
++ all_fo_vars t1
++ all_fo_vars t2))
as Hfresh.
destruct Hfresh as [l' d]; repnd.
apply @soaeqbt with (vs := l'); auto; try omega.
allrw disjoint_app_r; sp.
applydup in_combine in i; repnd.
pose proof (ind1
t1
(so_swap (mk_swapping l1 vs) t1)
l1
i1) as a1.
autodimp a1 hyp.
rw @sosize_so_swap; auto.
pose proof (a1 (so_swap (mk_swapping l2 vs) t2)
a
(vs ++ l' ++ l)) as a2;
clear a1.
allsimpl.
assert (disjoint l' vs) as disj1 by (allrw disjoint_app_r; sp).
assert (disjoint l' (all_fo_vars (so_swap (mk_swapping l1 vs) t1)))
as disj2 by (allrw disjoint_app_r; repnd;
apply disjoint_all_fo_vars_so_swap; auto).
assert (disjoint l' (all_fo_vars (so_swap (mk_swapping l2 vs) t2)))
as disj3 by (allrw disjoint_app_r; repnd;
apply disjoint_all_fo_vars_so_swap; auto).
applydup @so_alphaeq_add_so_swap in a2; auto;
try (complete (allrw disjoint_app_r; auto)).
allrw @so_swap_so_swap.
repeat (rw mk_swapping_app in a0; try omega).
rw @so_swap_disj_chain in a0; auto;
try (complete (allrw disjoint_app_r; sp; try (complete (apply disjoint_sym; auto)))).
rw @so_swap_disj_chain in a0; auto;
try (complete (allrw disjoint_app_r; sp; try (complete (apply disjoint_sym; auto)))).
apply @so_alphaeq_vs_implies_less with (l1 := vs ++ l' ++ l); auto.
rw app_assoc; apply subvars_app_trivial_r.
Qed.
Lemma so_alphaeq_vs_implies_more {p} :
forall (t1 t2 : @SOTerm p) l1 l2,
so_alphaeq_vs l1 t1 t2
-> subvars l1 l2
-> so_alphaeq_vs l2 t1 t2.
Proof.
introv aeq sv.
apply @so_alphaeq_vs_implies_less with (l2 := []) in aeq; auto.
apply so_alphaeq_implies_alphaeq_vs; auto.
Qed.
Lemma so_alphaeq_all {p} :
forall t1 t2 : @SOTerm p, so_alphaeq t1 t2 <=> (forall l, so_alphaeq_vs l t1 t2).
Proof.
introv; split; intro k.
- introv; apply so_alphaeq_implies_alphaeq_vs; auto.
- pose proof (k []); auto.
Qed.
Lemma so_alphaeq_exists {p} :
forall t1 t2 : @SOTerm p, so_alphaeq t1 t2 <=> {l : list NVar & so_alphaeq_vs l t1 t2}.
Proof.
introv; split; intro k.
- exists ([] : list NVar); auto.
- exrepnd; apply so_alphaeq_vs_implies_less with (l1 := l); auto.
Qed.
Lemma so_alphaeqbt_vs_implies_more {p} :
forall (t1 t2 : @SOBTerm p) l1 l2,
so_alphaeqbt_vs l1 t1 t2
-> subvars l1 l2
-> so_alphaeqbt_vs l2 t1 t2.
Proof.
introv aeq sv.
pose proof (so_alphaeq_vs_implies_more (soterm Exc [t1]) (soterm Exc [t2]) l1 l2) as h.
autodimp h hyp.
- constructor; simpl; auto.
introv k; sp; cpx.
- autodimp h hyp.
inversion h as [|? ? ? ? imp]; subst; allsimpl; GC.
apply imp; sp.
Qed.
Definition swap_sub {o} (sw : swapping) (sub : @Sub o) : Sub :=
map (fun x =>
match x with
| (v,t) => (swapvar sw v,swap sw t)
end)
sub.
Definition cswap_sub {o} (sw : swapping) (sub : @Sub o) : Sub :=
map (fun x =>
match x with
| (v,t) => (swapvar sw v,cswap sw t)
end)
sub.
Lemma sub_find_some_implies_swap {o} :
forall (sub : @Sub o) v t vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sub_find sub v = Some t
-> sub_find
(swap_sub (mk_swapping vs1 vs2) sub)
(swapvar (mk_swapping vs1 vs2) v)
= Some (swap (mk_swapping vs1 vs2) t).
Proof.
induction sub; introv norep disj f; allsimpl; cpx.
destruct a; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; tcsp.
provefalse.
destruct Heqb0.
eapply swapvars_eq; [|idtac|complete eauto]; auto.
Qed.
Lemma sub_find_some_implies_cswap {o} :
forall (sub : @Sub o) v t vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sub_find sub v = Some t
-> sub_find
(cswap_sub (mk_swapping vs1 vs2) sub)
(swapvar (mk_swapping vs1 vs2) v)
= Some (cswap (mk_swapping vs1 vs2) t).
Proof.
induction sub; introv norep disj f; allsimpl; cpx.
destruct a; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; tcsp.
provefalse.
destruct Heqb0.
eapply swapvars_eq; [|idtac|complete eauto]; auto.
Qed.
Lemma sub_find_none_implies_swap {o} :
forall (sub : @Sub o) v vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sub_find sub v = None
-> sub_find
(swap_sub (mk_swapping vs1 vs2) sub)
(swapvar (mk_swapping vs1 vs2) v)
= None.
Proof.
induction sub; introv norep disj f; allsimpl; cpx.
destruct a; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; tcsp.
provefalse.
destruct Heqb0.
eapply swapvars_eq; [|idtac|complete eauto]; auto.
Qed.
Lemma sub_find_none_implies_cswap {o} :
forall (sub : @Sub o) v vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sub_find sub v = None
-> sub_find
(cswap_sub (mk_swapping vs1 vs2) sub)
(swapvar (mk_swapping vs1 vs2) v)
= None.
Proof.
induction sub; introv norep disj f; allsimpl; cpx.
destruct a; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; tcsp.
provefalse.
destruct Heqb0.
eapply swapvars_eq; [|idtac|complete eauto]; auto.
Qed.
Lemma sub_filter_swap_sub {o} :
forall (sub : @Sub o) vs vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sub_filter
(swap_sub (mk_swapping vs1 vs2) sub)
(swapbvars (mk_swapping vs1 vs2) vs)
= swap_sub (mk_swapping vs1 vs2) (sub_filter sub vs).
Proof.
induction sub; introv norep disj; simpl; auto.
destruct a; boolvar; simpl; tcsp.
- provefalse.
apply in_swapbvars in Heqb; exrepnd.
apply swapvars_eq in Heqb1; auto; subst; tcsp.
- provefalse.
rw in_swapbvars in Heqb.
destruct Heqb.
eexists; dands; eauto.
- apply eq_cons; auto.
Qed.
Lemma sub_filter_cswap_sub {o} :
forall (sub : @Sub o) vs vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sub_filter
(cswap_sub (mk_swapping vs1 vs2) sub)
(swapbvars (mk_swapping vs1 vs2) vs)
= cswap_sub (mk_swapping vs1 vs2) (sub_filter sub vs).
Proof.
induction sub; introv norep disj; simpl; auto.
destruct a; boolvar; simpl; tcsp.
- provefalse.
apply in_swapbvars in Heqb; exrepnd.
apply swapvars_eq in Heqb1; auto; subst; tcsp.
- provefalse.
rw in_swapbvars in Heqb.
destruct Heqb.
eexists; dands; eauto.
- apply eq_cons; auto.
Qed.
Lemma swap_sub_combine {o} :
forall (ts : list (@NTerm o)) vs vs1 vs2,
swap_sub (mk_swapping vs1 vs2) (combine vs ts)
= combine (swapbvars (mk_swapping vs1 vs2) vs)
(map (swap (mk_swapping vs1 vs2)) ts).
Proof.
induction ts; destruct vs; introv; simpl; auto.
apply eq_cons; auto.
Qed.
Lemma cswap_sub_combine {o} :
forall (ts : list (@NTerm o)) vs vs1 vs2,
cswap_sub (mk_swapping vs1 vs2) (combine vs ts)
= combine (swapbvars (mk_swapping vs1 vs2) vs)
(map (cswap (mk_swapping vs1 vs2)) ts).
Proof.
induction ts; destruct vs; introv; simpl; auto.
apply eq_cons; auto.
Qed.
Lemma lsubst_aux_swap_swap {o} :
forall (t : @NTerm o) vs1 vs2 sub,
no_repeats vs2
-> disjoint vs1 vs2
-> swap (mk_swapping vs1 vs2) (lsubst_aux t sub)
= lsubst_aux
(swap (mk_swapping vs1 vs2) t)
(swap_sub (mk_swapping vs1 vs2) sub).
Proof.
nterm_ind1 t as [v|f ind|op bts Hind] Case; introv norep disj; simpl; auto.
- Case "vterm".
remember (sub_find sub v) as p; destruct p; symmetry in Heqp.
+ apply (sub_find_some_implies_swap sub v n vs1 vs2) in Heqp; auto.
rw Heqp; auto.
+ apply (sub_find_none_implies_swap sub v vs1 vs2) in Heqp; auto.
rw Heqp; auto.
- Case "oterm".
f_equal.
repeat (rw map_map); unfold compose.
apply eq_maps; introv i.
destruct x; simpl.
f_equal.
rw @sub_filter_swap_sub; auto.
eapply Hind; eauto.
Qed.
Lemma lsubst_aux_cswap_cswap {o} :
forall (t : @NTerm o) vs1 vs2 sub,
no_repeats vs2
-> disjoint vs1 vs2
-> cswap (mk_swapping vs1 vs2) (lsubst_aux t sub)
= lsubst_aux
(cswap (mk_swapping vs1 vs2) t)
(cswap_sub (mk_swapping vs1 vs2) sub).
Proof.
nterm_ind1 t as [v|f ind|op bts Hind] Case; introv norep disj; simpl; auto.
- Case "vterm".
remember (sub_find sub v) as p; destruct p; symmetry in Heqp.
+ apply (sub_find_some_implies_cswap sub v n vs1 vs2) in Heqp; auto.
rw Heqp; auto.
+ apply (sub_find_none_implies_cswap sub v vs1 vs2) in Heqp; auto.
rw Heqp; auto.
- Case "oterm".
f_equal.
repeat (rw map_map); unfold compose.
apply eq_maps; introv i.
destruct x; simpl.
f_equal.
rw @sub_filter_cswap_sub; auto.
eapply Hind; eauto.
Qed.
Definition swapsk {o} (sw : swapping) (sk : @sosub_kind o) : sosub_kind :=
match sk with
| sosk vs t => sosk (swapbvars sw vs) (swap sw t)
end.
Definition cswapsk {o} (sw : swapping) (sk : @sosub_kind o) : sosub_kind :=
match sk with
| sosk vs t => sosk (swapbvars sw vs) (cswap sw t)
end.
Definition swap_sosub {o} (sw : swapping) (sub : @SOSub o) : SOSub :=
map (fun x =>
match x with
| (v,sk) =>
(if bnull (sosk_vs sk) then swapvar sw v else v,swapsk sw sk)
end)
sub.
Definition cswap_sosub {o} (sw : swapping) (sub : @SOSub o) : SOSub :=
map (fun x =>
match x with
| (v,sk) =>
(if bnull (sosk_vs sk) then swapvar sw v else v,cswapsk sw sk)
end)
sub.
Definition swap_all_sosub {o} (sw : swapping) (sub : @SOSub o) : SOSub :=
map (fun x =>
match x with
| (v,sk) => (swapvar sw v,swapsk sw sk)
end)
sub.
Definition cswap_all_sosub {o} (sw : swapping) (sub : @SOSub o) : SOSub :=
map (fun x =>
match x with
| (v,sk) => (swapvar sw v,cswapsk sw sk)
end)
sub.
Definition swap_range_sosub {o} (sw : swapping) (sub : @SOSub o) : SOSub :=
map (fun x =>
match x with
| (v,sk) => (v,swapsk sw sk)
end)
sub.
Definition cswap_range_sosub {o} (sw : swapping) (sub : @SOSub o) : SOSub :=
map (fun x =>
match x with
| (v,sk) => (v,cswapsk sw sk)
end)
sub.
Lemma sosub_find_some_implies_swap_0 {o} :
forall (sub : @SOSub o) v t vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sosub_find sub (v,0) = Some (sosk [] t)
-> sosub_find
(swap_sosub (mk_swapping vs1 vs2) sub)
(swapvar (mk_swapping vs1 vs2) v, 0)
= Some (sosk [] (swap (mk_swapping vs1 vs2) t)).
Proof.
induction sub; introv norep disj f; allsimpl; cpx.
destruct a; destruct s; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; allsimpl; tcsp; GC;
try (complete (destruct l; allsimpl; cpx)).
provefalse; destruct n1.
f_equal.
eapply swapvars_eq; [|idtac|complete eauto]; auto.
Qed.
Lemma sosub_find_some_implies_cswap_0 {o} :
forall (sub : @SOSub o) v t vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sosub_find sub (v,0) = Some (sosk [] t)
-> sosub_find
(cswap_sosub (mk_swapping vs1 vs2) sub)
(swapvar (mk_swapping vs1 vs2) v, 0)
= Some (sosk [] (cswap (mk_swapping vs1 vs2) t)).
Proof.
induction sub; introv norep disj f; allsimpl; cpx.
destruct a; destruct s; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; allsimpl; tcsp; GC;
try (complete (destruct l; allsimpl; cpx)).
provefalse; destruct n1.
f_equal.
eapply swapvars_eq; [|idtac|complete eauto]; auto.
Qed.
Lemma sosub_find_some_implies_swap_S {o} :
forall (sub : @SOSub o) v n vs t vs1 vs2,
n > 0
-> no_repeats vs2
-> disjoint vs1 vs2
-> sosub_find sub (v,n) = Some (sosk vs t)
-> sosub_find (swap_sosub (mk_swapping vs1 vs2) sub) (v, n)
= Some (sosk (swapbvars (mk_swapping vs1 vs2) vs)
(swap (mk_swapping vs1 vs2) t)).
Proof.
induction sub; introv gt norep disj f; allsimpl; cpx.
destruct a; destruct s; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; allsimpl; tcsp; inversion gt.
Qed.
Lemma sosub_find_some_implies_cswap_S {o} :
forall (sub : @SOSub o) v n vs t vs1 vs2,
n > 0
-> no_repeats vs2
-> disjoint vs1 vs2
-> sosub_find sub (v,n) = Some (sosk vs t)
-> sosub_find (cswap_sosub (mk_swapping vs1 vs2) sub) (v, n)
= Some (sosk (swapbvars (mk_swapping vs1 vs2) vs)
(cswap (mk_swapping vs1 vs2) t)).
Proof.
induction sub; introv gt norep disj f; allsimpl; cpx.
destruct a; destruct s; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; allsimpl; tcsp; inversion gt.
Qed.
Lemma sosub_find_some_implies_swap_all {o} :
forall (sub : @SOSub o) v n vs t vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sosub_find sub (v,n) = Some (sosk vs t)
-> sosub_find (swap_all_sosub (mk_swapping vs1 vs2) sub)
(swapvar (mk_swapping vs1 vs2) v, n)
= Some (sosk (swapbvars (mk_swapping vs1 vs2) vs)
(swap (mk_swapping vs1 vs2) t)).
Proof.
induction sub; introv norep disj f; allsimpl; cpx.
destruct a; destruct s; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; allsimpl; tcsp.
provefalse; destruct n2.
f_equal.
eapply swapvars_eq; [|idtac|complete eauto]; auto.
Qed.
Lemma sosub_find_none_implies_swap_0 {o} :
forall (sub : @SOSub o) v vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sosub_find sub (v,0) = None
-> sosub_find
(swap_sosub (mk_swapping vs1 vs2) sub)
(swapvar (mk_swapping vs1 vs2) v, 0)
= None.
Proof.
induction sub; introv norep disj f; allsimpl; cpx.
destruct a; destruct s; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; tcsp; allsimpl; GC;
try (complete (destruct l; allsimpl; cpx)).
provefalse; destruct n1.
f_equal.
eapply swapvars_eq; [|idtac|complete eauto]; auto.
Qed.
Lemma sosub_find_none_implies_cswap_0 {o} :
forall (sub : @SOSub o) v vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sosub_find sub (v,0) = None
-> sosub_find
(cswap_sosub (mk_swapping vs1 vs2) sub)
(swapvar (mk_swapping vs1 vs2) v, 0)
= None.
Proof.
induction sub; introv norep disj f; allsimpl; cpx.
destruct a; destruct s; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; tcsp; allsimpl; GC;
try (complete (destruct l; allsimpl; cpx)).
provefalse; destruct n1.
f_equal.
eapply swapvars_eq; [|idtac|complete eauto]; auto.
Qed.
Lemma sosub_find_none_implies_swap_S {o} :
forall (sub : @SOSub o) v n vs1 vs2,
n > 0
-> no_repeats vs2
-> disjoint vs1 vs2
-> sosub_find sub (v,n) = None
-> sosub_find (swap_sosub (mk_swapping vs1 vs2) sub) (v, n) = None.
Proof.
induction sub; introv gt norep disj f; allsimpl; cpx.
destruct a; destruct s; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; tcsp; allsimpl; inversion gt.
Qed.
Lemma sosub_find_none_implies_swap_all {o} :
forall (sub : @SOSub o) v n vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sosub_find sub (v,n) = None
-> sosub_find (swap_all_sosub (mk_swapping vs1 vs2) sub)
(swapvar (mk_swapping vs1 vs2) v, n)
= None.
Proof.
induction sub; introv norep disj f; allsimpl; cpx.
destruct a; destruct s; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; tcsp; allsimpl.
provefalse; destruct n2.
f_equal.
eapply swapvars_eq; [|idtac|complete eauto]; auto.
Qed.
Lemma sosub_filter_swap_sosub {o} :
forall (sub : @SOSub o) vs vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sosub_filter
(swap_sosub (mk_swapping vs1 vs2) sub)
(vars2sovars (swapbvars (mk_swapping vs1 vs2) vs))
= swap_sosub (mk_swapping vs1 vs2) (sosub_filter sub (vars2sovars vs)).
Proof.
induction sub; introv norep disj; simpl; auto.
destruct a; destruct s; simpl;
repeat (progress (boolvar; try (subst); allsimpl)); tcsp; GC.
- provefalse.
allrw in_map_iff; exrepnd; allunfold var2sovar; cpx.
rw in_swapbvars in l0; exrepnd.
apply swapvars_eq in l1; auto; subst; tcsp.
destruct n1; eexists; dands; eauto.
- provefalse.
allrw in_map_iff; exrepnd; allunfold var2sovar; cpx.
allrw length_swapbvars; destruct l; allsimpl; cpx.
- provefalse.
allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx.
destruct n1; eexists; dands; eauto.
rw in_swapbvars; eexists; eauto.
- provefalse.
allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx.
destruct l; cpx.
- apply eq_cons; auto.
- apply eq_cons; auto.
Qed.
Lemma sosub_filter_cswap_sosub {o} :
forall (sub : @SOSub o) vs vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sosub_filter
(cswap_sosub (mk_swapping vs1 vs2) sub)
(vars2sovars (swapbvars (mk_swapping vs1 vs2) vs))
= cswap_sosub (mk_swapping vs1 vs2) (sosub_filter sub (vars2sovars vs)).
Proof.
induction sub; introv norep disj; simpl; auto.
destruct a; destruct s; simpl;
repeat (progress (boolvar; try (subst); allsimpl)); tcsp; GC.
- provefalse.
allrw in_map_iff; exrepnd; allunfold var2sovar; cpx.
rw in_swapbvars in l0; exrepnd.
apply swapvars_eq in l1; auto; subst; tcsp.
destruct n1; eexists; dands; eauto.
- provefalse.
allrw in_map_iff; exrepnd; allunfold var2sovar; cpx.
allrw length_swapbvars; destruct l; allsimpl; cpx.
- provefalse.
allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx.
destruct n1; eexists; dands; eauto.
rw in_swapbvars; eexists; eauto.
- provefalse.
allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx.
destruct l; cpx.
- apply eq_cons; auto.
- apply eq_cons; auto.
Qed.
Fixpoint filter_out_fo_vars (l : list sovar_sig) : list sovar_sig :=
match l with
| [] => []
| (v,0) :: vs => filter_out_fo_vars vs
| (v,S n) :: vs => (v,S n) :: filter_out_fo_vars vs
end.
Lemma subsovars_filter_out_fo_vars :
forall l, subsovars (filter_out_fo_vars l) l.
Proof.
induction l; simpl; auto.
destruct a; destruct n0; auto.
- apply subsovars_cons_weak_r; auto.
- apply subsovars_cons_lr; auto.
Qed.
Lemma in_filter_out_fo_vars :
forall v n l,
n > 0
-> (LIn (v, n) (filter_out_fo_vars l) <=> LIn (v, n) l).
Proof.
induction l; introv k; split; intro i; allsimpl; tcsp;
destruct a; destruct n1; tcsp.
- apply IHl in i; auto.
- simpl in i; dorn i; cpx.
apply IHl in i; auto.
- dorn i; cpx; try omega.
apply IHl; auto.
- dorn i; cpx; simpl.
right; apply IHl; auto.
Qed.
Lemma in_filter_out_fo_vars2 :
forall v n l,
LIn (v, S n) (filter_out_fo_vars l) <=> LIn (v, S n) l.
Proof.
introv; apply in_filter_out_fo_vars; omega.
Qed.
Lemma filter_out_fo_vars_app :
forall l1 l2,
filter_out_fo_vars (l1 ++ l2)
= filter_out_fo_vars l1 ++ filter_out_fo_vars l2.
Proof.
induction l1; introv; simpl; auto.
destruct a; destruct n0; auto.
apply eq_cons; auto.
Qed.
Lemma filter_out_fo_vars_flat_map :
forall {A} (x : A) f l,
LIn x l
-> subsovars (filter_out_fo_vars (f x)) (filter_out_fo_vars (flat_map f l)).
Proof.
induction l; introv i; allsimpl; tcsp.
dorn i; subst; auto; rw filter_out_fo_vars_app.
- apply subsovars_app_weak_r1; auto.
- apply subsovars_app_weak_r2; auto.
Qed.
Lemma subvars_filter_out_fo_vars_flat_map :
forall {A} f (l : list A) vs,
subsovars (filter_out_fo_vars (flat_map f l)) vs
<=> (forall x, LIn x l -> subsovars (filter_out_fo_vars (f x)) vs).
Proof.
induction l; introv; split; introv k; allsimpl; tcsp.
- rw filter_out_fo_vars_app in k; rw subsovars_app_l in k; repnd.
introv i; dorn i; subst; tcsp.
rw IHl in k; apply k; auto.
- rw filter_out_fo_vars_app; rw subsovars_app_l; dands; auto.
rw IHl; introv i.
apply k; sp.
Qed.
Definition cover_so_vars {o} (t : @SOTerm o) (sub : @SOSub o) :=
subsovars
(filter_out_fo_vars (so_free_vars t))
(filter_out_fo_vars (sodom sub)).
Lemma cover_so_vars_sovar {o} :
forall v (ts : list (@SOTerm o)) sub,
cover_so_vars (sovar v ts) sub
<=>
((!null ts -> LIn (v,length ts) (sodom sub))
# (forall t, LIn t ts -> cover_so_vars t sub)).
Proof.
introv; unfold cover_so_vars; simpl; boolvar;
destruct ts; allsimpl; cpx; allsimpl; GC.
- rw null_nil_iff.
split; intro k; repnd; dands; tcsp.
- rw subsovars_cons_l; split; intro k; repnd; dands; auto.
+ intro h.
pose proof (subsovars_filter_out_fo_vars (sodom sub)) as sv.
rw subsovars_prop in sv; apply sv in k0; auto.
+ rw filter_out_fo_vars_app in k.
rw subsovars_app_l in k; repnd.
introv i; dorn i; subst; auto.
pose proof (filter_out_fo_vars_flat_map t so_free_vars ts i) as sv.
eapply subsovars_trans; [exact sv|]; auto.
+ autodimp k0 hyp.
apply in_filter_out_fo_vars; auto; omega.
+ rw filter_out_fo_vars_app.
rw subsovars_app_l; dands; tcsp.
rw @subvars_filter_out_fo_vars_flat_map; introv i.
apply k; sp.
Qed.
Lemma filter_out_fo_vars_remove_fo_vars :
forall fovs sovs,
filter_out_fo_vars (remove_so_vars (vars2sovars fovs) sovs)
= filter_out_fo_vars sovs.
Proof.
induction sovs; simpl.
- rw remove_so_vars_nil_r; simpl; auto.
- destruct a; destruct n0; simpl;
rw remove_so_vars_cons_r; boolvar; simpl; auto.
+ allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx.
+ apply eq_cons; auto.
Qed.
Lemma cover_so_vars_soterm {o} :
forall op (bs : list (@SOBTerm o)) sub,
cover_so_vars (soterm op bs) sub
<=>
(forall vs t, LIn (sobterm vs t) bs -> cover_so_vars t sub).
Proof.
introv; unfold cover_so_vars; simpl; split; intro k.
- introv i.
rw @subvars_filter_out_fo_vars_flat_map in k.
apply k in i; simpl in i.
rw filter_out_fo_vars_remove_fo_vars in i; auto.
- rw @subvars_filter_out_fo_vars_flat_map; introv i.
destruct x; simpl.
rw filter_out_fo_vars_remove_fo_vars.
eapply k; eauto.
Qed.
Lemma cover_so_vars_sosub_filter {o} :
forall (sub : @SOSub o) t vs,
cover_so_vars t (sosub_filter sub (vars2sovars vs))
<=> cover_so_vars t sub.
Proof.
introv; unfold cover_so_vars.
rw @sodom_sosub_filter.
rw filter_out_fo_vars_remove_fo_vars; sp.
Qed.
(* vs2 can be disjoint from whatever we want *)
Lemma sosub_aux_swap_swap {p} :
forall (t : @SOTerm p) vs1 vs2 sub,
no_repeats vs2
-> disjoint vs1 vs2
-> cover_so_vars t sub
-> swap (mk_swapping vs1 vs2) (sosub_aux sub t)
= sosub_aux (swap_sosub (mk_swapping vs1 vs2) sub)
(so_swap (mk_swapping vs1 vs2) t).
Proof.
soterm_ind1s t as [v ts ind | o lbt Hind] Case;
introv norep disj cov.
- Case "sovar".
simpl.
remember (sosub_find sub (v,length ts)) as f;
symmetry in Heqf; destruct f;
boolvar; subst; allsimpl;
try (destruct s);
try (rw map_length).
+ applydup @sosub_find_some in Heqf; repnd.
destruct l; allsimpl; cpx; GC.
dup Heqf as e.
eapply sosub_find_some_implies_swap_0 in e; eauto.
rw e; clear e; simpl.
rw @lsubst_aux_swap_swap; auto.
+ dup Heqf as e.
eapply sosub_find_some_implies_swap_S in e; eauto;
try (complete (destruct ts; allsimpl; sp; apply gt_Sn_O)).
rw e; clear e.
rw @lsubst_aux_swap_swap; auto.
rw @swap_sub_combine.
f_equal; f_equal.
repeat (rw map_map); unfold compose.
apply eq_maps; introv i.
apply ind; auto.
rw @cover_so_vars_sovar in cov; repnd; apply cov; auto.
+ eapply sosub_find_none_implies_swap_0 in Heqf; eauto.
rw Heqf; clear Heqf; auto.
+ apply sosub_find_none in Heqf.
rw @cover_so_vars_sovar in cov; repnd.
autodimp cov0 hyp; tcsp.
rw null_iff_nil; auto.
- Case "soterm".
simpl.
f_equal.
repeat (rw map_map); unfold compose; apply eq_maps; introv i.
destruct x; simpl.
f_equal.
rw @sosub_filter_swap_sosub; auto.
eapply Hind; eauto.
rw @cover_so_vars_soterm in cov.
apply cov in i.
rw @cover_so_vars_sosub_filter; auto.
Qed.
Lemma sosub_aux_cswap_cswap {p} :
forall (t : @SOTerm p) vs1 vs2 sub,
no_repeats vs2
-> disjoint vs1 vs2
-> cover_so_vars t sub
-> cswap (mk_swapping vs1 vs2) (sosub_aux sub t)
= sosub_aux (cswap_sosub (mk_swapping vs1 vs2) sub)
(so_swap (mk_swapping vs1 vs2) t).
Proof.
soterm_ind1s t as [v ts ind | o lbt Hind] Case;
introv norep disj cov.
- Case "sovar".
simpl.
remember (sosub_find sub (v,length ts)) as f;
symmetry in Heqf; destruct f;
boolvar; subst; allsimpl;
try (destruct s);
try (rw map_length).
+ applydup @sosub_find_some in Heqf; repnd.
destruct l; allsimpl; cpx; GC.
dup Heqf as e.
eapply sosub_find_some_implies_cswap_0 in e; eauto.
rw e; clear e; simpl.
rw @lsubst_aux_cswap_cswap; auto.
+ dup Heqf as e.
eapply sosub_find_some_implies_cswap_S in e; eauto;
try (complete (destruct ts; allsimpl; sp; apply gt_Sn_O)).
rw e; clear e.
rw @lsubst_aux_cswap_cswap; auto.
rw @cswap_sub_combine.
f_equal; f_equal.
repeat (rw map_map); unfold compose.
apply eq_maps; introv i.
apply ind; auto.
rw @cover_so_vars_sovar in cov; repnd; apply cov; auto.
+ eapply sosub_find_none_implies_cswap_0 in Heqf; eauto.
rw Heqf; clear Heqf; auto.
+ apply sosub_find_none in Heqf.
rw @cover_so_vars_sovar in cov; repnd.
autodimp cov0 hyp; tcsp.
rw null_iff_nil; auto.
- Case "soterm".
simpl.
f_equal.
repeat (rw map_map); unfold compose; apply eq_maps; introv i.
destruct x; simpl.
f_equal.
rw @sosub_filter_cswap_sosub; auto.
eapply Hind; eauto.
rw @cover_so_vars_soterm in cov.
apply cov in i.
rw @cover_so_vars_sosub_filter; auto.
Qed.
Lemma in_swap_range_sosub_implies {o} :
forall (sub : @SOSub o) sw v vs t,
LIn (v,sosk vs t) (swap_range_sosub sw sub)
-> LIn (v,length vs) (sodom sub).
Proof.
introv i.
rw in_map_iff in i; exrepnd; cpx.
destruct a; allsimpl; ginv.
rw length_swapbvars.
eapply in_sodom_if in i1; eauto.
Qed.
Lemma sosub_find_some_implies_swap2 {o} :
forall (sub : @SOSub o) v n vs t vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sosub_find sub (v,n) = Some (sosk vs t)
-> sosub_find (swap_range_sosub (mk_swapping vs1 vs2) sub) (v,n)
= Some (sosk (swapbvars (mk_swapping vs1 vs2) vs)
(swap (mk_swapping vs1 vs2) t)).
Proof.
induction sub; introv norep disj f; allsimpl; cpx.
destruct a; destruct s; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; tcsp.
Qed.
Lemma sosub_find_none_implies_swap2 {o} :
forall (sub : @SOSub o) v n vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> sosub_find sub (v,n) = None
-> sosub_find (swap_range_sosub (mk_swapping vs1 vs2) sub) (v,n) = None.
Proof.
induction sub; introv norep disj f; allsimpl; cpx.
destruct a; destruct s; simpl; boolvar; cpx; ginv; tcsp;
allrw length_swapbvars; tcsp.
Qed.
Lemma sosub_filter_swap_range_sosub {o} :
forall (sub : @SOSub o) vs vs1 vs2,
sosub_filter (swap_range_sosub (mk_swapping vs1 vs2) sub) vs
= swap_range_sosub (mk_swapping vs1 vs2) (sosub_filter sub vs).
Proof.
induction sub; introv; simpl; auto.
destruct a; destruct s; simpl; boolvar; simpl; tcsp;
allrw length_swapbvars; tcsp.
apply eq_cons; auto.
Qed.
Lemma sosub_filter_cswap_range_sosub {o} :
forall (sub : @SOSub o) vs vs1 vs2,
sosub_filter (cswap_range_sosub (mk_swapping vs1 vs2) sub) vs
= cswap_range_sosub (mk_swapping vs1 vs2) (sosub_filter sub vs).
Proof.
induction sub; introv; simpl; auto.
destruct a; destruct s; simpl; boolvar; simpl; tcsp;
allrw length_swapbvars; tcsp.
apply eq_cons; auto.
Qed.
Lemma swap_range_sosub_eq {o} :
forall (sub : @SOSub o) vs1 vs2,
disjoint vs1 (sovars2vars (sodom sub))
-> disjoint vs2 (sovars2vars (sodom sub))
-> swap_range_sosub (mk_swapping vs1 vs2) sub
= swap_sosub (mk_swapping vs1 vs2) sub.
Proof.
introv disj1 disj2.
unfold swap_range_sosub, swap_sosub.
apply eq_maps; introv i.
destruct x; destruct s.
boolvar; auto.
destruct l; allsimpl; cpx; GC.
allrw disjoint_map_r.
eapply in_sodom_if in i; eauto.
applydup disj1 in i.
applydup disj2 in i.
allsimpl.
rw swapvar_not_in; auto.
Qed.
Lemma sosub_aux_swap_swap2 {o} :
forall (t : @SOTerm o) sub vs1 vs2,
disjoint vs2 (vs1 ++ sovars2vars (sodom sub))
-> disjoint vs1 (sovars2vars (sodom sub))
-> no_repeats vs2
-> cover_so_vars t sub
-> swap (mk_swapping vs1 vs2) (sosub_aux sub t)
= sosub_aux
(swap_range_sosub (mk_swapping vs1 vs2) sub)
(so_swap (mk_swapping vs1 vs2) t).
Proof.
introv disj1 disj2 norep cov.
allrw disjoint_app_r; repnd.
rw (sosub_aux_swap_swap t vs1 vs2 sub); eauto with slow.
f_equal.
rw @swap_range_sosub_eq; auto.
Qed.
Fixpoint get_fo_vars (l : list sovar_sig) : list NVar :=
match l with
| [] => []
| (v,0) :: vs => v :: get_fo_vars vs
| _ :: vs => get_fo_vars vs
end.
Lemma get_fo_vars_app :
forall vs1 vs2, get_fo_vars (vs1 ++ vs2) = get_fo_vars vs1 ++ get_fo_vars vs2.
Proof.
induction vs1; introv; simpl; auto.
destruct a; destruct n0; simpl; auto.
rw IHvs1; auto.
Qed.
Lemma in_get_fo_vars :
forall v vs, LIn v (get_fo_vars vs) <=> LIn (v,0) vs.
Proof.
induction vs; split; introv i; allsimpl; tcsp;
destruct a; destruct n0; allsimpl; tcsp;
try (dorn i; subst; cpx);
try (complete (try right; apply IHvs; auto)).
Qed.
Lemma swap_range_sosub_eq2 {o} :
forall (sub : @SOSub o) vs1 vs2,
disjoint vs1 (get_fo_vars (sodom sub))
-> disjoint vs2 (get_fo_vars (sodom sub))
-> swap_range_sosub (mk_swapping vs1 vs2) sub
= swap_sosub (mk_swapping vs1 vs2) sub.
Proof.
introv disj1 disj2.
apply eq_maps; introv i.
destruct x; destruct s.
boolvar; auto.
destruct l; allsimpl; cpx; GC.
eapply in_sodom_if in i; eauto; allsimpl.
apply in_get_fo_vars in i.
apply disjoint_sym in disj1.
apply disjoint_sym in disj2.
applydup disj1 in i.
applydup disj2 in i.
rw swapvar_not_in; auto.
Qed.
Lemma cswap_range_sosub_eq2 {o} :
forall (sub : @SOSub o) vs1 vs2,
disjoint vs1 (get_fo_vars (sodom sub))
-> disjoint vs2 (get_fo_vars (sodom sub))
-> cswap_range_sosub (mk_swapping vs1 vs2) sub
= cswap_sosub (mk_swapping vs1 vs2) sub.
Proof.
introv disj1 disj2.
apply eq_maps; introv i.
destruct x; destruct s.
boolvar; auto.
destruct l; allsimpl; cpx; GC.
eapply in_sodom_if in i; eauto; allsimpl.
apply in_get_fo_vars in i.
apply disjoint_sym in disj1.
apply disjoint_sym in disj2.
applydup disj1 in i.
applydup disj2 in i.
rw swapvar_not_in; auto.
Qed.
Lemma sosub_aux_swap_swap3 {o} :
forall (t : @SOTerm o) sub vs1 vs2,
disjoint vs2 (vs1 ++ get_fo_vars (sodom sub))
-> disjoint vs1 (get_fo_vars (sodom sub))
-> no_repeats vs2
-> cover_so_vars t sub
-> swap (mk_swapping vs1 vs2) (sosub_aux sub t)
= sosub_aux
(swap_range_sosub (mk_swapping vs1 vs2) sub)
(so_swap (mk_swapping vs1 vs2) t).
Proof.
introv disj1 disj2 norep cov.
allrw disjoint_app_r; repnd.
rw (sosub_aux_swap_swap t vs1 vs2 sub); eauto with slow.
f_equal.
rw @swap_range_sosub_eq2; auto.
Qed.
Lemma sosub_aux_cswap_cswap3 {o} :
forall (t : @SOTerm o) sub vs1 vs2,
disjoint vs2 (vs1 ++ get_fo_vars (sodom sub))
-> disjoint vs1 (get_fo_vars (sodom sub))
-> no_repeats vs2
-> cover_so_vars t sub
-> cswap (mk_swapping vs1 vs2) (sosub_aux sub t)
= sosub_aux
(cswap_range_sosub (mk_swapping vs1 vs2) sub)
(so_swap (mk_swapping vs1 vs2) t).
Proof.
introv disj1 disj2 norep cov.
allrw disjoint_app_r; repnd.
rw (sosub_aux_cswap_cswap t vs1 vs2 sub); eauto with slow.
f_equal.
rw @cswap_range_sosub_eq2; auto.
Qed.
(*
Lemma lsubst_aux_alpha_congr2 {p} :
forall (t1 t2 : @NTerm p) vs1 vs2 ts1 ts2,
alpha_eq_bterm (bterm vs1 t1) (bterm vs2 t2)
-> bin_rel_nterm alpha_eq ts1 ts2 (*enforces that the lengths are equal*)
-> alpha_eq (lsubst_aux t1 (combine vs1 ts1)) (lsubst_aux t2 (combine vs2 ts2)).
Proof.
introv aeq aeqs.
inversion aeq as [? ? ? ? ? disj len1 len2 norep a]; subst.
introv Hal Hbr Hl. unfold apply_bterm.
destruct bt1 as [lv1 nt1]. destruct bt2 as [lv2 nt2];allsimpl.
invertsna Hal Hal.
remember (change_bvars_alpha (lv++(flat_map free_vars lnt1)) nt1) as X99.
revert HeqX99. add_changebvar_spec nt1' Hnt1'. intro H99. clear dependent X99.
repnd. clear Heqnt1'.
remember (change_bvars_alpha (lv++(flat_map free_vars lnt2)) nt2) as X99.
revert HeqX99. add_changebvar_spec nt2' Hnt2'. intro H99. clear dependent X99.
repnd. clear Heqnt2'.
unfold num_bvars in Hl. allsimpl. duplicate Hbr.
destruct Hbr as [Hll X99]. clear X99.
alpharws Hnt1'.
alpharws Hnt2'.
alpharwh Hnt1' Hal3.
alpharwhs Hnt2' Hal3.
eapply lsubst_alpha_congr with (lvi:=lv) in Hal3; eauto.
Focus 2. spc;fail. Focus 2. spc;fail.
rewrite lsubst_nest_same in Hal3; spc; spcls;disjoint_reasoningv.
- rewrite lsubst_nest_same in Hal3; spc; spcls;disjoint_reasoningv.
alpharw_rev Hnt2'. trivial.
- alpharw_rev Hnt1'. trivial.
Qed.
*)
Lemma disjoint_bound_vars_prop1 {o} :
forall (sub : @SOSub o) v vs t ts,
disjoint (bound_vars_in_sosub sub) (free_vars_sosub sub)
-> disjoint (bound_vars_in_sosub sub) (flat_map all_fo_vars ts)
-> LIn (v, sosk vs t) sub
-> disjoint (bound_vars t) (flat_map (fun x => free_vars (sosub_aux sub x)) ts).
Proof.
introv disj1 disj2 insub.
apply disjoint_flat_map_r; introv i.
allrw disjoint_flat_map_l.
applydup disj1 in insub; allsimpl.
applydup disj2 in insub; allsimpl.
pose proof (isprogram_sosub_aux_free_vars x sub) as h.
eapply subvars_disjoint_r;[eauto|]; clear h.
rw disjoint_app_r; dands; auto.
apply disjoint_map_r; introv k.
rw in_remove_so_vars in k; repnd.
destruct x0; simpl.
apply so_free_vars_in_all_fo_vars in k0.
rw disjoint_flat_map_r in insub1.
apply insub1 in i.
apply disjoint_sym in i.
apply i in k0; auto.
Qed.
(*
Lemma swap_sosub_combine {o} :
forall sw (sks : list (@sosub_kind o)) vs,
swap_sosub sw (combine vs sks)
= combine (swapbvars sw vs) (map (swapsk sw) sks).
Proof.
induction sks; destruct vs; allsimpl; auto.
apply eq_cons; auto.
Qed.
*)
Lemma swap_range_sosub_combine {o} :
forall sw (sks : list (@sosub_kind o)) vs,
swap_range_sosub sw (combine vs sks)
= combine vs (map (swapsk sw) sks).
Proof.
induction sks; destruct vs; allsimpl; auto.
apply eq_cons; auto.
Qed.
Lemma cswap_range_sosub_combine {o} :
forall sw (sks : list (@sosub_kind o)) vs,
cswap_range_sosub sw (combine vs sks)
= combine vs (map (cswapsk sw) sks).
Proof.
induction sks; destruct vs; allsimpl; auto.
apply eq_cons; auto.
Qed.
Lemma get_fo_vars_remove_so_vars :
forall fovs sovs,
get_fo_vars (remove_so_vars (vars2sovars fovs) sovs)
= remove_nvars fovs (get_fo_vars sovs).
Proof.
induction sovs; simpl.
- rw remove_so_vars_nil_r.
rw remove_nvars_nil_r; auto.
- rw remove_so_vars_cons_r.
destruct a; destruct n0; boolvar; tcsp;
rw remove_nvars_cons_r; boolvar; simpl; tcsp.
+ allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx.
+ allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx.
provefalse; destruct n0.
eexists; eauto.
+ apply eq_cons; auto.
Qed.
Lemma disjoint_get_fo_vars_remove :
forall fovs sovs,
disjoint fovs (get_fo_vars (remove_so_vars (vars2sovars fovs) sovs)).
Proof.
introv.
rw get_fo_vars_remove_so_vars.
introv i j.
rw in_remove_nvars in j; sp.
Qed.
Lemma subvars_sovars2vars_prop2 :
forall vs1 vs2,
subsovars vs1 vs2
-> subvars (get_fo_vars vs1) (sovars2vars vs2).
Proof.
introv k.
rw subvars_prop; introv i.
allrw in_sovars2vars; exrepnd.
allrw in_get_fo_vars.
rw subsovars_prop in k.
apply k in i.
eexists; eauto.
Qed.
Lemma alphaeq_sks_implies_eq_sodom_combine {o} :
forall (sks1 sks2 : list (@sosub_kind o)) vs,
bin_rel_sk alphaeq_sk sks1 sks2
-> sodom (combine vs sks1) = sodom (combine vs sks2).
Proof.
induction sks1; destruct sks2; introv aeqs; allsimpl; auto.
- inversion aeqs; allsimpl; sp.
- inversion aeqs; allsimpl; sp.
- destruct vs; allsimpl; auto.
destruct a; destruct s.
rw @bin_rel_sk_cons in aeqs; repnd.
erewrite IHsks1; eauto.
inversion aeqs; subst.
apply eq_cons; auto.
f_equal; omega.
Qed.
Lemma swapvar_implies3 :
forall (vs1 vs2 : list NVar) (v : NVar),
no_repeats vs2
-> disjoint vs1 vs2
-> length vs1 = length vs2
-> LIn v vs1
-> LIn (swapvar (mk_swapping vs1 vs2) v) vs2.
Proof.
induction vs1; destruct vs2; introv norep disj len i; allsimpl; cpx; GC; tcsp.
allrw no_repeats_cons; repnd.
allrw disjoint_cons_l; allrw disjoint_cons_r; allsimpl.
allrw not_over_or; repnd.
unfold oneswapvar; boolvar; dorn i; subst; tcsp; GC;
rw swapvar_not_in; auto.
Qed.
Lemma disjoint_get_fo_vars_flat_map_r :
forall {T} (l : list T) f vs,
disjoint vs (get_fo_vars (flat_map f l))
<=>
(forall x, LIn x l -> disjoint vs (get_fo_vars (f x))).
Proof.
induction l; simpl; introv; split; intro k; tcsp.
- introv i; dorn i; subst; tcsp.
+ allrw get_fo_vars_app.
allrw disjoint_app_r; sp.
+ allrw get_fo_vars_app.
allrw disjoint_app_r; repnd.
rw IHl in k; apply k; auto.
- rw get_fo_vars_app.
rw disjoint_app_r; dands; auto.
apply IHl; introv i.
apply k; sp.
Qed.
Lemma disjoint_swapbvars2 :
forall bvs vs1 vs2 : list NVar,
disjoint vs1 vs2
-> no_repeats vs2
-> disjoint vs2 bvs
-> length vs1 = length vs2
-> disjoint vs1 (swapbvars (mk_swapping vs1 vs2) bvs).
Proof.
induction bvs; introv disj1 norep disj2 len; allsimpl; auto.
rw disjoint_cons_r in disj2; repnd.
rw disjoint_cons_r; dands; auto.
pose proof (in_deq NVar deq_nvar a vs1) as h; dorn h.
* pose proof (swapvar_implies3 vs1 vs2 a norep disj1 len h) as k.
rw disjoint_sym in disj1; apply disj1 in k; tcsp.
* rw swapvar_not_in; sp.
Qed.
Lemma free_fo_vars_so_swap {o} :
forall (t : @SOTerm o) vs1 vs2,
disjoint vs1 vs2
-> disjoint vs2 (all_fo_vars t)
-> no_repeats vs2
-> length vs1 = length vs2
-> disjoint vs1 (get_fo_vars (so_free_vars (so_swap (mk_swapping vs1 vs2) t))).
Proof.
soterm_ind t as [ v ts ind | op lbt ind ] Case; simpl;
introv disj1 disj2 norep len.
- Case "sovar".
boolvar; subst; allsimpl.
+ allrw disjoint_singleton_r.
pose proof (in_deq NVar deq_nvar v vs1) as h; dorn h.
* pose proof (swapvar_implies3 vs1 vs2 v norep disj1 len h) as k.
rw disjoint_sym in disj1; apply disj1 in k; tcsp.
* rw swapvar_not_in; sp.
+ rw map_length.
allrw disjoint_cons_r; repnd.
rw <- length0 in n.
destruct (length ts); cpx.
apply disjoint_get_fo_vars_flat_map_r; introv k.
rw in_map_iff in k; exrepnd; subst.
apply ind; auto.
allrw disjoint_flat_map_r.
apply disj0; auto.
- Case "soterm".
apply disjoint_get_fo_vars_flat_map_r; introv k.
rw in_map_iff in k; exrepnd; subst.
destruct a; simpl.
rw get_fo_vars_remove_so_vars.
pose proof (ind s l k1 vs1 vs2) as h; repeat (autodimp h hyp).
+ allrw disjoint_flat_map_r.
apply disj2 in k1; simpl in k1.
allrw disjoint_app_r; sp.
+ introv i j.
apply h in i.
rw in_remove_nvars in j; sp.
Qed.
Lemma fo_bound_vars_so_swap {o} :
forall (t : @SOTerm o) vs1 vs2,
disjoint vs1 vs2
-> disjoint vs2 (all_fo_vars t)
-> no_repeats vs2
-> length vs1 = length vs2
-> disjoint vs1 (fo_bound_vars (so_swap (mk_swapping vs1 vs2) t)).
Proof.
soterm_ind t as [ v ts ind | op lbt ind ] Case; simpl;
introv disj1 disj2 norep len.
- Case "sovar".
boolvar; subst; allsimpl; auto.
rw disjoint_flat_map_r; introv i.
rw in_map_iff in i; exrepnd; subst.
apply ind; auto.
allrw disjoint_cons_r; allrw disjoint_flat_map_r; repnd.
apply disj0; auto.
- Case "soterm".
rw flat_map_map; unfold compose.
rw disjoint_flat_map_r; introv i.
destruct x; simpl.
rw disjoint_app_r; dands; auto.
+ apply disjoint_swapbvars2; auto.
rw disjoint_flat_map_r in disj2.
apply disj2 in i; simpl in i.
rw disjoint_app_r in i; sp.
+ eapply ind; eauto.
rw disjoint_flat_map_r in disj2.
apply disj2 in i; simpl in i.
rw disjoint_app_r in i; sp.
Qed.
Lemma sosub_find_sosub_filter {o} :
forall (sub : @SOSub o) vs v,
!LIn v vs
-> sosub_find (sosub_filter sub vs) v
= sosub_find sub v.
Proof.
induction sub; introv i; simpl; auto.
destruct v; destruct a; destruct s;
boolvar; simpl; cpx;
boolvar; simpl; cpx.
Qed.
Lemma sosub_filter_swap {o} :
forall (sub : @SOSub o) vs1 vs2,
sosub_filter (sosub_filter sub vs1) vs2
= sosub_filter (sosub_filter sub vs2) vs1.
Proof.
induction sub; introv; simpl; auto.
destruct a; destruct s;
boolvar; simpl; tcsp;
boolvar; simpl; tcsp.
rw IHsub; auto.
Qed.
Fixpoint fovars {p} (t : @SOTerm p) : list NVar :=
match t with
| sovar v ts =>
if bnull ts
then v :: flat_map fovars ts
else flat_map fovars ts
| soterm op bs => flat_map fovars_bterm bs
end
with fovars_bterm {p} (bt : @SOBTerm p) : list NVar :=
match bt with
| sobterm lv nt => lv ++ fovars nt
end.
Lemma fovars_subvars_all_fo_vars {o} :
forall t : @SOTerm o,
subvars (fovars t) (all_fo_vars t).
Proof.
soterm_ind t as [ v ts ind | op lbt ind ] Case; simpl; introv.
- Case "sovar".
boolvar; subst; allsimpl; auto.
apply subvars_cons_r.
apply subvars_flat_map2; auto.
- Case "soterm".
apply subvars_flat_map2; introv i.
destruct x; simpl.
apply subvars_app_l; dands.
+ apply subvars_app_weak_l; auto.
+ apply subvars_app_weak_r; auto.
eapply ind; eauto.
Qed.
Lemma get_fo_vars_flat_map :
forall {T} f (l : list T),
get_fo_vars (flat_map f l)
= flat_map (fun x => get_fo_vars (f x)) l.
Proof.
induction l; simpl; auto.
rw get_fo_vars_app.
rw IHl; auto.
Qed.
Lemma flat_map_app_f :
forall {A B} (f g : A -> list B) (l : list A),
eqset
(flat_map f l ++ flat_map g l)
(flat_map (fun x => f x ++ g x) l).
Proof.
induction l; simpl; auto.
allunfold @eqset; introv; split; intro i; allrw in_app_iff.
- rw <- IHl; allrw in_app_iff; sp.
- rw <- IHl in i; allrw in_app_iff; sp.
Qed.
Lemma eqvars_is_eqset :
forall l1 l2,
eqvars l1 l2 <=> eqset l1 l2.
Proof.
introv; rw eqvars_prop; unfold eqset; sp.
Qed.
Lemma implies_eqvars_flat_map :
forall {A} f g (l : list A),
(forall x, LIn x l -> eqvars (f x) (g x))
-> eqvars (flat_map f l) (flat_map g l).
Proof.
induction l; introv h; allsimpl; auto.
apply eqvars_app; auto.
Qed.
Lemma eqvars_remove_nvars_app :
forall vs1 vs2 vs3,
eqvars (remove_nvars vs1 vs2 ++ vs1 ++ vs3)
(vs1 ++ vs2 ++ vs3).
Proof.
introv; rw eqvars_prop; introv; split; intro i;
allrw in_app_iff; allrw in_remove_nvars; sp.
destruct (in_deq NVar deq_nvar x vs1); sp.
Qed.
Lemma fovars_eqvars {o} :
forall (t : @SOTerm o),
eqvars
(fovars t)
(get_fo_vars (so_free_vars t) ++ fo_bound_vars t).
Proof.
soterm_ind t as [ v ts ind | op lbt ind ] Case; simpl; introv.
- Case "sovar".
boolvar; subst; simpl; auto.
rw <- length0 in n.
destruct (length ts); tcsp.
rw @get_fo_vars_flat_map.
pose proof (flat_map_app_f
(fun t : SOTerm => get_fo_vars (so_free_vars t))
fo_bound_vars
ts) as e.
rw <- eqvars_is_eqset in e.
eapply eqvars_trans;[|apply eqvars_sym; exact e].
apply implies_eqvars_flat_map; auto.
- Case "soterm".
rw @get_fo_vars_flat_map.
pose proof (flat_map_app_f
(fun t => get_fo_vars (so_free_vars_bterm t))
fo_bound_vars_bterm
lbt) as e.
rw <- eqvars_is_eqset in e.
eapply eqvars_trans;[|apply eqvars_sym; exact e].
apply implies_eqvars_flat_map; auto.
introv i; destruct x; simpl.
rw get_fo_vars_remove_so_vars.
pose proof (eqvars_remove_nvars_app
l (get_fo_vars (so_free_vars s))
(fo_bound_vars s)) as h.
eapply eqvars_trans; [|apply eqvars_sym; exact h].
apply eqvars_app; auto.
eapply ind; eauto.
Qed.
Lemma fo_free_vars_in_fovars {o} :
forall (t : @SOTerm o) v,
LIn (v, 0) (so_free_vars t)
-> LIn v (fovars t).
Proof.
introv i.
pose proof (fovars_eqvars t) as h.
rw eqvars_prop in h.
apply h.
rw in_app_iff.
left.
rw in_get_fo_vars; auto.
Qed.
Lemma disjoint_bound_vars_prop2 {o} :
forall (sub : @SOSub o) v vs t ts,
disjoint (bound_vars_in_sosub sub) (free_vars_sosub sub)
-> disjoint (bound_vars_in_sosub sub) (flat_map fovars ts)
-> LIn (v, sosk vs t) sub
-> (forall u, LIn u ts -> cover_so_vars u sub)
-> disjoint (bound_vars t) (flat_map (fun x => free_vars (sosub_aux sub x)) ts).
Proof.
introv disj1 disj2 insub cov.
apply disjoint_flat_map_r; introv i.
allrw disjoint_flat_map_l.
applydup disj1 in insub; allsimpl.
applydup disj2 in insub; allsimpl.
pose proof (isprogram_sosub_aux_free_vars x sub) as h.
eapply subvars_disjoint_r;[eauto|]; clear h.
rw disjoint_app_r; dands; auto.
applydup cov in i.
apply disjoint_map_r; introv k.
rw in_remove_so_vars in k; repnd.
destruct x0; simpl.
unfold cover_so_vars in i0.
destruct n0.
- rw disjoint_flat_map_r in insub1.
apply insub1 in i.
apply disjoint_sym in i.
apply fo_free_vars_in_fovars in k0.
apply i in k0; auto.
- rw subsovars_prop in i0.
pose proof (i0 (n,S n0)) as h; autodimp h hyp.
+ apply in_filter_out_fo_vars; auto; omega.
+ rw in_filter_out_fo_vars2 in h; tcsp.
Qed.
Lemma disjoint_bound_vars_prop3 {o} :
forall (sub : @SOSub o) v vs t ts,
disjoint (bound_vars_sosub sub) (free_vars_sosub sub)
-> disjoint (bound_vars_sosub sub) (flat_map fovars ts)
-> LIn (v, sosk vs t) sub
-> (forall u, LIn u ts -> cover_so_vars u sub)
-> disjoint (bound_vars t) (flat_map (fun x => free_vars (sosub_aux sub x)) ts).
Proof.
introv disj1 disj2 insub cov.
eapply disjoint_bound_vars_prop2; eauto;
eapply subvars_disjoint_l;[|eauto|idtac|eauto];
apply subvars_bound_vars_in_sosub_bound_vars_sosub.
Qed.
Lemma disjoint_fovars_so_swap {o} :
forall (t : @SOTerm o) vs1 vs2,
disjoint vs1 vs2
-> disjoint vs2 (all_fo_vars t)
-> no_repeats vs2
-> length vs1 = length vs2
-> disjoint vs1 (fovars (so_swap (mk_swapping vs1 vs2) t)).
Proof.
introv disj1 disj2 norep len.
eapply eqvars_disjoint_r;
[apply eqvars_sym;apply fovars_eqvars|].
rw disjoint_app_r; dands.
- apply free_fo_vars_so_swap; auto.
- apply fo_bound_vars_so_swap; auto.
Qed.
Lemma sosub_aux_sosub_filter {o} :
forall (t : @SOTerm o) (sub : @SOSub o) l,
disjoint l (fovars t)
-> sosub_aux (sosub_filter sub (vars2sovars l)) t
= sosub_aux sub t.
Proof.
soterm_ind t as [ v ts ind | op lbt ind ] Case; simpl; introv disj.
- Case "sovar".
boolvar; subst; allsimpl.
+ rw disjoint_singleton_r in disj; repnd.
rw @sosub_find_sosub_filter;
[|rw in_map_iff; unfold var2sovar; intro k; exrepnd; complete cpx].
remember (sosub_find sub (v, 0)) as f;
symmetry in Heqf; destruct f; auto.
+ rw @sosub_find_sosub_filter;
[|rw in_map_iff; unfold var2sovar; intro k; exrepnd;
cpx; destruct ts; allsimpl; complete cpx].
remember (sosub_find sub (v, length ts)) as f;
symmetry in Heqf; destruct f.
* destruct s.
f_equal; f_equal.
apply eq_maps; introv i.
apply ind; auto.
rw disjoint_flat_map_r in disj; apply disj; auto.
* f_equal.
apply eq_maps; introv i.
apply ind; auto.
rw disjoint_flat_map_r in disj; apply disj; auto.
- Case "soterm".
f_equal.
apply eq_maps; introv i.
destruct x; simpl.
f_equal.
rw @sosub_filter_swap.
eapply ind; eauto.
rw disjoint_flat_map_r in disj.
apply disj in i; simpl in i.
rw disjoint_app_r in i; sp.
Qed.
Lemma disjoint_swap :
forall vs1 vs2 l1 l2,
disjoint vs1 vs2
-> no_repeats vs2
-> disjoint l1 l2
-> disjoint
(swapbvars (mk_swapping vs1 vs2) l1)
(swapbvars (mk_swapping vs1 vs2) l2).
Proof.
introv disj1 norep disj2 i j.
allrw in_swapbvars; exrepnd; subst.
apply swapvars_eq in i0; subst; auto.
apply disj2 in j1; auto.
Qed.
Lemma fo_bound_var_so_swap {o} :
forall (t : @SOTerm o) vs1 vs2,
fo_bound_vars (so_swap (mk_swapping vs1 vs2) t)
= swapbvars (mk_swapping vs1 vs2) (fo_bound_vars t).
Proof.
soterm_ind t as [ v ts ind | op lbt ind ] Case; simpl; introv.
- Case "sovar".
boolvar; subst; simpl; auto.
unfold swapbvars; rw map_flat_map.
rw flat_map_map; unfold compose.
apply eq_flat_maps; introv i.
apply ind; auto.
- Case "soterm".
unfold swapbvars; rw map_flat_map.
rw flat_map_map; unfold compose.
apply eq_flat_maps; introv i.
destruct x; simpl.
rw map_app.
erewrite ind; eauto.
Qed.
Lemma swapbvars_app :
forall sw vs1 vs2,
swapbvars sw (vs1 ++ vs2) = swapbvars sw vs1 ++ swapbvars sw vs2.
Proof.
introv; unfold swapbvars; rw map_app; auto.
Qed.
Lemma swapbvars_flat_map :
forall {A} sw f (l : list A),
swapbvars sw (flat_map f l)
= flat_map (fun a => swapbvars sw (f a)) l.
Proof.
introv; unfold swapbvars.
rw map_flat_map; unfold compose; auto.
Qed.
Lemma fovars_so_swap {o} :
forall (t : @SOTerm o) vs1 vs2,
fovars (so_swap (mk_swapping vs1 vs2) t)
= swapbvars (mk_swapping vs1 vs2) (fovars t).
Proof.
soterm_ind t as [ v ts ind | op lbt ind ] Case; simpl; introv.
- Case "sovar".
boolvar; subst; simpl; boolvar; simpl; auto; cpx.
+ destruct ts; allsimpl; cpx.
+ rw flat_map_map; unfold compose.
rw @swapbvars_flat_map.
apply eq_flat_maps; introv i.
apply ind; auto.
- Case "soterm".
rw @swapbvars_flat_map.
rw flat_map_map; unfold compose.
apply eq_flat_maps; introv i.
destruct x; simpl.
rw swapbvars_app.
apply app_if; auto.
eapply ind; eauto.
Qed.
Lemma free_vars_sosub_kind_swapsk {o} :
forall (sk : @sosub_kind o) vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> free_vars_sosub_kind (swapsk (mk_swapping vs1 vs2) sk)
= swapbvars (mk_swapping vs1 vs2) (free_vars_sosub_kind sk).
Proof.
introv norep disj.
destruct sk; simpl.
unfold free_vars_sosub_kind; simpl.
revert l.
nterm_ind n as [v|f ind|op bs ind] Case; simpl; introv; auto.
- Case "vterm".
repeat (rw remove_nvars_cons_r); boolvar; simpl;
allrw remove_nvars_nil_r; auto; provefalse.
+ rw in_map_iff in Heqb; exrepnd.
apply swapvars_eq in Heqb1; subst; sp.
+ destruct Heqb.
rw in_map_iff.
eexists; eauto.
- Case "sterm".
allrw remove_nvars_nil_r.
unfold swapbvars; simpl; auto.
- Case "oterm".
repeat (rw remove_nvars_flat_map); unfold compose.
unfold swapbvars; rw map_flat_map; unfold compose.
rw flat_map_map; unfold compose.
apply eq_flat_maps; introv i; destruct x; simpl.
repeat (rw remove_nvars_app_l).
unfold swapbvars; rw <- map_app.
eapply ind; eauto.
Qed.
Lemma free_vars_sosub_kind_cswapsk {o} :
forall (sk : @sosub_kind o) vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> free_vars_sosub_kind (cswapsk (mk_swapping vs1 vs2) sk)
= swapbvars (mk_swapping vs1 vs2) (free_vars_sosub_kind sk).
Proof.
introv norep disj.
destruct sk; simpl.
unfold free_vars_sosub_kind; simpl.
revert l.
nterm_ind n as [v|f ind|op bs ind] Case; simpl; introv; auto.
- Case "vterm".
repeat (rw remove_nvars_cons_r); boolvar; simpl;
allrw remove_nvars_nil_r; auto; provefalse.
+ rw in_map_iff in Heqb; exrepnd.
apply swapvars_eq in Heqb1; subst; sp.
+ destruct Heqb.
rw in_map_iff.
eexists; eauto.
- Case "sterm".
allrw remove_nvars_nil_r.
unfold swapbvars; simpl; auto.
- Case "oterm".
repeat (rw remove_nvars_flat_map); unfold compose.
unfold swapbvars; rw map_flat_map; unfold compose.
rw flat_map_map; unfold compose.
apply eq_flat_maps; introv i; destruct x; simpl.
repeat (rw remove_nvars_app_l).
unfold swapbvars; rw <- map_app.
eapply ind; eauto.
Qed.
Lemma free_vars_sosub_kind_swapsks {o} :
forall (sks : list (@sosub_kind o)) vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> flat_map free_vars_sosub_kind (map (swapsk (mk_swapping vs1 vs2)) sks)
= swapbvars (mk_swapping vs1 vs2) (flat_map free_vars_sosub_kind sks).
Proof.
induction sks; introv norep disj; simpl; auto.
rw IHsks; auto; clear IHsks.
rw swapbvars_app.
rw @free_vars_sosub_kind_swapsk; auto.
Qed.
Lemma free_vars_sk_swapsks {o} :
forall (sks : list (@sosub_kind o)) vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> flat_map free_vars_sk (map (swapsk (mk_swapping vs1 vs2)) sks)
= swapbvars (mk_swapping vs1 vs2) (flat_map free_vars_sk sks).
Proof.
induction sks; introv norep disj; simpl; auto.
rw IHsks; auto; clear IHsks.
rw swapbvars_app.
allrw @free_vars_sk_is_free_vars_sosub_kind.
rw @free_vars_sosub_kind_swapsk; auto.
Qed.
Lemma free_vars_sk_cswapsks {o} :
forall (sks : list (@sosub_kind o)) vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> flat_map free_vars_sk (map (cswapsk (mk_swapping vs1 vs2)) sks)
= swapbvars (mk_swapping vs1 vs2) (flat_map free_vars_sk sks).
Proof.
induction sks; introv norep disj; simpl; auto.
rw IHsks; auto; clear IHsks.
rw swapbvars_app.
allrw @free_vars_sk_is_free_vars_sosub_kind.
rw @free_vars_sosub_kind_cswapsk; auto.
Qed.
Lemma bound_vars_swap {o} :
forall (t : @NTerm o) vs1 vs2,
bound_vars (swap (mk_swapping vs1 vs2) t)
= swapbvars (mk_swapping vs1 vs2) (bound_vars t).
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; introv; simpl; auto.
rw @swapbvars_flat_map.
rw flat_map_map; unfold compose.
apply eq_flat_maps; introv i; destruct x; simpl.
rw swapbvars_app.
apply app_if; auto.
eapply ind; eauto.
Qed.
Lemma bound_vars_cswap {o} :
forall (t : @NTerm o) vs1 vs2,
bound_vars (cswap (mk_swapping vs1 vs2) t)
= swapbvars (mk_swapping vs1 vs2) (bound_vars t).
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; introv; simpl; auto.
rw @swapbvars_flat_map.
rw flat_map_map; unfold compose.
apply eq_flat_maps; introv i; destruct x; simpl.
rw swapbvars_app.
apply app_if; auto.
eapply ind; eauto.
Qed.
Lemma bound_vars_in_sk_swapsk {o} :
forall (sk : @sosub_kind o) vs1 vs2,
bound_vars_in_sk (swapsk (mk_swapping vs1 vs2) sk)
= swapbvars (mk_swapping vs1 vs2) (bound_vars_in_sk sk).
Proof.
destruct sk; introv; simpl.
apply bound_vars_swap; auto.
Qed.
Lemma bound_vars_sk_swapsk {o} :
forall (sk : @sosub_kind o) vs1 vs2,
bound_vars_sk (swapsk (mk_swapping vs1 vs2) sk)
= swapbvars (mk_swapping vs1 vs2) (bound_vars_sk sk).
Proof.
destruct sk; introv; simpl.
rw swapbvars_app.
apply app_if; auto.
apply bound_vars_swap; auto.
Qed.
Lemma bound_vars_sk_cswapsk {o} :
forall (sk : @sosub_kind o) vs1 vs2,
bound_vars_sk (cswapsk (mk_swapping vs1 vs2) sk)
= swapbvars (mk_swapping vs1 vs2) (bound_vars_sk sk).
Proof.
destruct sk; introv; simpl.
rw swapbvars_app.
apply app_if; auto.
apply bound_vars_cswap; auto.
Qed.
Lemma bound_vars_in_sosub_combine_map_swapsk {o} :
forall (sks : list (@sosub_kind o)) vs1 vs2 vs,
bound_vars_in_sosub (combine vs (map (swapsk (mk_swapping vs1 vs2)) sks))
= swapbvars (mk_swapping vs1 vs2) (bound_vars_in_sosub (combine vs sks)).
Proof.
induction sks; destruct vs; introv; allsimpl; auto.
rw IHsks; clear IHsks.
rw swapbvars_app.
apply app_if; auto.
apply bound_vars_in_sk_swapsk; auto.
Qed.
Lemma bound_vars_sosub_combine_map_swapsk {o} :
forall (sks : list (@sosub_kind o)) vs1 vs2 vs,
bound_vars_sosub (combine vs (map (swapsk (mk_swapping vs1 vs2)) sks))
= swapbvars (mk_swapping vs1 vs2) (bound_vars_sosub (combine vs sks)).
Proof.
induction sks; destruct vs; introv; allsimpl; auto.
rw IHsks; clear IHsks.
rw swapbvars_app.
apply app_if; auto.
apply bound_vars_sk_swapsk; auto.
Qed.
Lemma bound_vars_sosub_combine_map_cswapsk {o} :
forall (sks : list (@sosub_kind o)) vs1 vs2 vs,
bound_vars_sosub (combine vs (map (cswapsk (mk_swapping vs1 vs2)) sks))
= swapbvars (mk_swapping vs1 vs2) (bound_vars_sosub (combine vs sks)).
Proof.
induction sks; destruct vs; introv; allsimpl; auto.
rw IHsks; clear IHsks.
rw swapbvars_app.
apply app_if; auto.
apply bound_vars_sk_cswapsk; auto.
Qed.
Lemma free_vars_sosub_combine_map_swapsk {o} :
forall (sks : list (@sosub_kind o)) vs vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> free_vars_sosub (combine vs (map (swapsk (mk_swapping vs1 vs2)) sks))
= swapbvars (mk_swapping vs1 vs2) (free_vars_sosub (combine vs sks)).
Proof.
induction sks; destruct vs; introv norep disj; allsimpl; auto.
rw IHsks; auto; clear IHsks.
rw swapbvars_app.
apply app_if; auto.
allrw @free_vars_sk_is_free_vars_sosub_kind.
apply free_vars_sosub_kind_swapsk; auto.
Qed.
Lemma free_vars_sosub_combine_map_cswapsk {o} :
forall (sks : list (@sosub_kind o)) vs vs1 vs2,
no_repeats vs2
-> disjoint vs1 vs2
-> free_vars_sosub (combine vs (map (cswapsk (mk_swapping vs1 vs2)) sks))
= swapbvars (mk_swapping vs1 vs2) (free_vars_sosub (combine vs sks)).
Proof.
induction sks; destruct vs; introv norep disj; allsimpl; auto.
rw IHsks; auto; clear IHsks.
rw swapbvars_app.
apply app_if; auto.
allrw @free_vars_sk_is_free_vars_sosub_kind.
apply free_vars_sosub_kind_cswapsk; auto.
Qed.
Lemma implies_subvars_flat_map_r :
forall {A} f (l : list A) k a,
LIn a l
-> subvars k (f a)
-> subvars k (flat_map f l).
Proof.
introv i s.
allrw subvars_prop; introv h.
rw lin_flat_map.
eexists; eauto.
Qed.
Lemma in_sodom_iff {o}:
forall (sub : @SOSub o) v k,
LIn (v, k) (sodom sub)
<=> {vs : list NVar
& {t : NTerm
& LIn (v, sosk vs t) sub
# k = length vs}}.
Proof.
induction sub; introv; simpl; split; intro h; exrepnd; tcsp;
destruct a; subst.
- dorn h; cpx.
+ exists l n; sp.
+ apply IHsub in h; exrepnd; subst.
exists vs t; sp.
- dorn h0; cpx; ginv; tcsp.
right; apply IHsub.
exists vs t; sp.
Qed.
Lemma select_map :
forall {A B} (l : list A) (f : A -> B) n,
select n (map f l) = option_map f (select n l).
Proof.
induction l; introv; simpl; auto.
- destruct n; simpl; auto.
- destruct n; simpl; auto.
Qed.
Lemma cover_so_vars_so_swap {o} :
forall (t : @SOTerm o) vs1 vs2 vs sks,
cover_so_vars t (combine vs sks)
-> cover_so_vars
(so_swap (mk_swapping vs1 vs2) t)
(combine vs (map (swapsk (mk_swapping vs1 vs2)) sks)).
Proof.
soterm_ind1s t as [ v ts ind | op lbt ind ] Case; simpl; introv cov.
- Case "sovar".
boolvar; subst; allsimpl; auto;
allrw @cover_so_vars_sovar; repnd; dands; allsimpl; tcsp; introv k.
+ rw null_nil_iff in k; provefalse; sp.
+ rw null_map in k.
apply cov0 in k; clear cov0.
rw map_length.
allrw @in_sodom_iff; exrepnd.
exists (swapbvars (mk_swapping vs1 vs2) vs0)
(swap (mk_swapping vs1 vs2) t).
rw length_swapbvars; dands; auto.
allrw in_combine_sel_iff; exrepnd.
exists n0; rw map_length; dands; auto.
rw @select_map; rw <- k2; simpl; auto.
+ rw in_map_iff in k; exrepnd; subst.
applydup cov in k1.
apply ind; auto.
- Case "soterm".
allrw @cover_so_vars_soterm; introv i.
rw in_map_iff in i; exrepnd.
destruct a; allsimpl; ginv.
applydup cov in i1.
eapply ind; eauto.
Qed.
Lemma cover_so_vars_so_swapc {o} :
forall (t : @SOTerm o) vs1 vs2 vs sks,
cover_so_vars t (combine vs sks)
-> cover_so_vars
(so_swap (mk_swapping vs1 vs2) t)
(combine vs (map (cswapsk (mk_swapping vs1 vs2)) sks)).
Proof.
soterm_ind1s t as [ v ts ind | op lbt ind ] Case; simpl; introv cov.
- Case "sovar".
boolvar; subst; allsimpl; auto;
allrw @cover_so_vars_sovar; repnd; dands; allsimpl; tcsp; introv k.
+ rw null_nil_iff in k; provefalse; sp.
+ rw null_map in k.
apply cov0 in k; clear cov0.
rw map_length.
allrw @in_sodom_iff; exrepnd.
exists (swapbvars (mk_swapping vs1 vs2) vs0)
(cswap (mk_swapping vs1 vs2) t).
rw length_swapbvars; dands; auto.
allrw in_combine_sel_iff; exrepnd.
exists n0; rw map_length; dands; auto.
rw @select_map; rw <- k2; simpl; auto.
+ rw in_map_iff in k; exrepnd; subst.
applydup cov in k1.
apply ind; auto.
- Case "soterm".
allrw @cover_so_vars_soterm; introv i.
rw in_map_iff in i; exrepnd.
destruct a; allsimpl; ginv.
applydup cov in i1.
eapply ind; eauto.
Qed.
Lemma bound_vars_in_sosub_combine {o} :
forall (sks : list (@sosub_kind o)) vs,
length vs = length sks
-> bound_vars_in_sosub (combine vs sks)
= flat_map bound_vars_in_sk sks.
Proof.
induction sks; destruct vs; introv len; allsimpl; cpx.
rw IHsks; sp.
Qed.
Lemma bound_vars_sosub_combine {o} :
forall (sks : list (@sosub_kind o)) vs,
length vs = length sks
-> bound_vars_sosub (combine vs sks)
= flat_map bound_vars_sk sks.
Proof.
induction sks; destruct vs; introv len; allsimpl; cpx.
rw IHsks; sp.
Qed.
Lemma free_vars_sosub_combine {o} :
forall (sks : list (@sosub_kind o)) vs,
length vs = length sks
-> free_vars_sosub (combine vs sks)
= flat_map free_vars_sk sks.
Proof.
induction sks; destruct vs; introv len; allsimpl; cpx.
rw IHsks; auto.
Qed.
Lemma swapbvars_trivial :
forall vs1 vs2 l,
disjoint l vs1
-> disjoint l vs2
-> swapbvars (mk_swapping vs1 vs2) l = l.
Proof.
induction l; introv d1 d2; allsimpl; auto.
allrw disjoint_cons_l; repnd.
rw IHl; auto.
rw swapvar_not_in; auto.
Qed.
Lemma eq_map_l :
forall A (f : A -> A) (l : list A),
(forall x, LIn x l -> f x = x)
-> map f l = l.
Proof.
induction l; intro h; allsimpl; tcsp.
rw IHl; auto.
rw h; auto.
Qed.
Lemma cswap_trivial {o} :
forall (t : @NTerm o) vs1 vs2,
disjoint (allvars t) vs1
-> disjoint (allvars t) vs2
-> cswap (mk_swapping vs1 vs2) t = t.
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; introv d1 d2; allsimpl; auto.
- Case "vterm".
allrw disjoint_singleton_l.
rw swapvar_not_in; auto.
- Case "oterm".
f_equal.
allrw disjoint_flat_map_l.
apply eq_map_l; introv i.
destruct x; allsimpl.
applydup d1 in i.
applydup d2 in i.
allsimpl; allrw disjoint_app_l; repnd.
rw swapbvars_trivial; auto.
f_equal.
eapply ind; eauto.
Qed.
Lemma cswapsk_trivial {o} :
forall (sk : @sosub_kind o) vs1 vs2,
disjoint (bound_vars_sk sk) vs1
-> disjoint (bound_vars_sk sk) vs2
-> disjoint (free_vars_sk sk) vs1
-> disjoint (free_vars_sk sk) vs2
-> cswapsk (mk_swapping vs1 vs2) sk = sk.
Proof.
destruct sk; introv d1 d2 d3 d4; allsimpl.
allrw disjoint_app_l; repnd.
rw swapbvars_trivial; auto.
f_equal.
pose proof (allvars_eq_all_vars n) as e.
apply eqvars_sym in e.
apply disjoint_sym in d3; apply disjoint_sym in d4.
apply disjoint_sym in d0; apply disjoint_sym in d5.
apply cswap_trivial.
- eapply eqvars_disjoint;[eauto|].
rw disjoint_app_l; dands; auto.
introv a b.
applydup d3 in b.
applydup d0 in b.
rw in_remove_nvars in b0; sp.
- eapply eqvars_disjoint;[eauto|].
rw disjoint_app_l; dands; auto.
introv a b.
applydup d4 in b.
applydup d5 in b.
rw in_remove_nvars in b0; sp.
Qed.
Lemma sosub_aux_alpha_congr {p} :
forall (t1 t2 : @SOTerm p) (vs : list NVar) (ts1 ts2 : list sosub_kind),
let sub1 := combine vs ts1 in
let sub2 := combine vs ts2 in
so_alphaeq t1 t2
-> length vs = length ts1
-> length vs = length ts2
-> disjoint (free_vars_sosub sub1) (fo_bound_vars t1)
-> disjoint (free_vars_sosub sub2) (fo_bound_vars t2)
(* These 2 disjoints we can always assume because they are ensured by sosub *)
-> disjoint (bound_vars_sosub sub1) (free_vars_sosub sub1 ++ fovars t1)
-> disjoint (bound_vars_sosub sub2) (free_vars_sosub sub2 ++ fovars t2)
-> cover_so_vars t1 sub1
-> cover_so_vars t2 sub2
-> bin_rel_sk alphaeq_sk ts1 ts2
-> alphaeq (sosub_aux sub1 t1) (sosub_aux sub2 t2).
Proof.
soterm_ind1s t1 as [ v1 ts1 ind1 | op1 lbt1 ind1 ] Case; simpl;
introv aeq len1 len2 d1 d2 d3 d4 cov1 cov2 ask.
- Case "sovar".
inversion aeq as [? ? ? len imp|]; subst; clear aeq; simpl.
remember (sosub_find (combine vs ts0) (v1, length ts1)) as o;
destruct o; symmetry in Heqo;
remember (sosub_find (combine vs ts2) (v1, length ts4)) as q;
destruct q; symmetry in Heqq;
try (destruct s); try (destruct s0).
+ rw len in Heqo.
pose proof (apply_bterm_alpha_congr
(bterm l n)
(bterm l0 n0)
(map (sosub_aux (combine vs ts0)) ts1)
(map (sosub_aux (combine vs ts2)) ts4)) as h.
unfold apply_bterm in h; simpl in h.
revert h.
change_to_lsubst_aux4.
* introv h; apply alphaeq_eq; apply h; clear h; auto.
{
apply alphaeqbt_eq.
apply alphaeq_sk_iff_alphaeq_bterm.
eapply alphaeq_sosub_kind_if_alphaeq_sosub_find;
[|idtac|idtac|exact Heqo|exact Heqq]; auto.
}
{
apply bin_rel_nterm_if_combine; allrw map_length; auto.
introv i.
rw <- @map_combine in i.
rw in_map_iff in i; exrepnd; cpx; allsimpl.
}
{
rw map_length; unfold num_bvars; simpl; auto.
apply sosub_find_some in Heqo; sp; omega.
}
* apply alphaeq_eq; apply h; clear h; auto.
{
apply alphaeqbt_eq.
apply alphaeq_sk_iff_alphaeq_bterm.
eapply alphaeq_sosub_kind_if_alphaeq_sosub_find;
[|idtac|idtac|exact Heqo|exact Heqq]; auto.
}
{
apply bin_rel_nterm_if_combine; allrw map_length; auto.
introv i.
rw <- @map_combine in i.
rw in_map_iff in i; exrepnd; cpx; allsimpl.
applydup imp in i1.
applydup in_combine in i1; repnd.
apply alphaeq_eq.
apply ind1; auto.
{
rw disjoint_flat_map_r in d1.
apply d1 in i3; auto.
}
{
rw disjoint_flat_map_r in d2.
apply d2 in i2; auto.
}
{
rw disjoint_app_r; dands; auto.
rw disjoint_flat_map_r in d3.
apply d3 in i3; auto.
}
{
rw disjoint_app_r; dands; auto.
boolvar.
{
rw disjoint_cons_r in d4; repnd.
rw disjoint_flat_map_r in d7.
apply d7 in i2; auto.
}
{
rw disjoint_flat_map_r in d4.
apply d4 in i2; auto.
}
}
{
rw @cover_so_vars_sovar in cov1; repnd.
apply cov1; auto.
}
{
rw @cover_so_vars_sovar in cov2; repnd.
apply cov2; auto.
}
}
{
unfold num_bvars; simpl.
apply sosub_find_some in Heqo; repnd; omega.
}
* clear h; allsimpl; clear d.
apply sosub_find_some in Heqq; repnd.
rw @range_combine;[|rw map_length; omega].
allrw disjoint_cons_r; repnd.
rw flat_map_map; unfold compose.
eapply disjoint_bound_vars_prop3; eauto.
{
boolvar; auto.
allrw disjoint_cons_r; sp.
}
{
allrw @cover_so_vars_sovar; sp.
}
* clear h; allsimpl; clear d.
apply sosub_find_some in Heqq; repnd.
rw @range_combine;[|rw map_length; omega].
allrw disjoint_cons_r; repnd.
rw flat_map_map; unfold compose.
eapply disjoint_bound_vars_prop3; eauto.
{
boolvar; auto.
allrw disjoint_cons_r; sp.
}
{
allrw @cover_so_vars_sovar; sp.
}
* clear h; allsimpl; clear d.
apply sosub_find_some in Heqo; repnd.
rw @range_combine;[|rw map_length; omega].
allrw disjoint_cons_r; repnd.
rw flat_map_map; unfold compose.
eapply disjoint_bound_vars_prop3; eauto.
allrw @cover_so_vars_sovar; sp.
* clear h; allsimpl; clear d.
apply sosub_find_some in Heqo; repnd.
rw @range_combine;[|rw map_length; omega].
allrw disjoint_cons_r; repnd.
rw flat_map_map; unfold compose.
eapply disjoint_bound_vars_prop3; eauto.
allrw @cover_so_vars_sovar; sp.
* clear h; allsimpl.
apply sosub_find_some in Heqq; repnd.
rw @range_combine;[|rw map_length; omega].
allrw disjoint_cons_r; repnd.
rw flat_map_map; unfold compose.
eapply disjoint_bound_vars_prop3; eauto.
allrw @cover_so_vars_sovar; sp.
{
boolvar; auto.
allrw disjoint_cons_r; sp.
}
{
allrw @cover_so_vars_sovar; sp.
}
* clear h; allsimpl.
apply sosub_find_some in Heqq; repnd.
rw @range_combine;[|rw map_length; omega].
allrw disjoint_cons_r; repnd.
rw flat_map_map; unfold compose.
eapply disjoint_bound_vars_prop3; eauto.
allrw @cover_so_vars_sovar; sp.
{
boolvar; auto.
allrw disjoint_cons_r; sp.
}
{
allrw @cover_so_vars_sovar; sp.
}
+ rw len in Heqo.
eapply false_if_alphaeq_sosub_find in Heqo; eauto; sp.
+ rw len in Heqo.
eapply false_if_alphaeq_sosub_find in Heqo; eauto; sp.
apply bin_rel_sk_sym; auto.
+ apply alphaeq_apply_list; auto.
* apply alphaeq_eq; auto.
* apply bin_rel_nterm_if_combine; allrw map_length; auto.
introv i.
rw <- @map_combine in i.
rw in_map_iff in i; exrepnd; cpx; allsimpl.
applydup imp in i1.
applydup in_combine in i1; repnd.
apply alphaeq_eq.
apply ind1; auto.
{
introv i j; apply d1 in i.
destruct i; rw lin_flat_map; eexists; eauto.
}
{
introv i j; apply d2 in i.
destruct i; rw lin_flat_map; eexists; eauto.
}
{
allrw disjoint_app_r; repnd; dands; auto.
boolvar; subst; allsimpl; cpx.
rw disjoint_flat_map_r in d3; apply d3 in i3; auto.
}
{
allrw disjoint_app_r; repnd; dands; auto.
boolvar; subst; allsimpl; cpx.
rw disjoint_flat_map_r in d4; apply d4 in i2; auto.
}
{
rw @cover_so_vars_sovar in cov1; repnd.
apply cov1; auto.
}
{
rw @cover_so_vars_sovar in cov2; repnd.
apply cov2; auto.
}
- Case "soterm".
inversion aeq as [|? ? ? len imp]; subst; clear aeq; simpl.
constructor; try (complete (repeat (rw map_length); auto)).
introv i.
rw map_length in i.
repeat (rw @selectbt_map_sosub_b_aux).
assert (LIn (selectsobt lbt1 n, selectsobt bts2 n) (combine lbt1 bts2))
as j by (apply in_combine_sel_iff; exists n; dands; auto; try omega;
apply selectsobt_as_select; auto; try omega).
remember (selectsobt lbt1 n) as bt1.
remember (selectsobt bts2 n) as bt2.
clear Heqbt1 Heqbt2.
applydup imp in j.
destruct bt1, bt2; simpl.
apply so_alphaeqbt_vs_implies_more
with (l2 := vs
++
allvars (sosub_aux (sosub_filter (combine vs ts1) (vars2sovars l)) s)
++
allvars (sosub_aux (sosub_filter (combine vs ts2) (vars2sovars l0)) s0)
++
bound_vars_sosub (combine vs ts1)
++
bound_vars_sosub (combine vs ts2)
++
free_vars_sosub (combine vs ts1)
++
free_vars_sosub (combine vs ts2)) in j0; auto.
inversion j0 as [? ? ? ? ? le1 le2 disj norep aeq]; subst; clear j0.
apply (aeqbt [] vs0); auto; simpl.
+ eapply subvars_disjoint_r;[|complete eauto].
repeat (rw subvars_app_l); dands.
* apply subvars_app_weak_r.
apply subvars_app_weak_l; auto.
* apply subvars_app_weak_r.
apply subvars_app_weak_r.
apply subvars_app_weak_l; auto.
* apply subvars_app_weak_l.
apply subvars_app_weak_r.
apply subvars_app_weak_l; auto.
* apply subvars_app_weak_l.
apply subvars_app_weak_r.
apply subvars_app_weak_r.
apply subvars_app_weak_l; auto.
+ assert (disjoint l vs0 # disjoint l0 vs0 # disjoint vs vs0)
as disjl by (allrw disjoint_app_r; sp; apply disjoint_sym; auto); repnd.
applydup in_combine in j; repnd.
simpl in d2.
rw disjoint_flat_map_r in d1; applydup d1 in j1 as disjb1.
rw disjoint_flat_map_r in d2; applydup d2 in j0 as disjb2.
simpl in disjb1, disjb2.
rw disjoint_app_r in disjb1; rw disjoint_app_r in disjb2; repnd.
apply so_alphaeq_vs_implies_less with (l2 := []) in aeq; auto.
repeat (rw @sosub_aux_cswap_cswap3; auto);
[
| allrw disjoint_app_r; sp;
rw @sodom_sosub_filter;
apply subvars_disjoint_r with (l2 := sovars2vars (sodom (combine vs ts2)));
[ apply subvars_sovars2vars_prop2;
apply subsovars_remove_so_vars
| rewrite @sovars2vars_sodom_combine; auto
]
| rw @sodom_sosub_filter; complete (apply disjoint_get_fo_vars_remove)
| rw @cover_so_vars_soterm in cov2;
apply cover_so_vars_sosub_filter;
eapply cov2; eauto
| allrw disjoint_app_r; sp;
rw @sodom_sosub_filter;
apply subvars_disjoint_r with (l2 := sovars2vars (sodom (combine vs ts2)));
[ apply subvars_sovars2vars_prop2;
erewrite alphaeq_sks_implies_eq_sodom_combine; eauto;
apply subsovars_remove_so_vars
| rewrite @sovars2vars_sodom_combine; auto
]
| rw @sodom_sosub_filter; complete (apply disjoint_get_fo_vars_remove)
| rw @cover_so_vars_soterm in cov1;
apply cover_so_vars_sosub_filter;
eapply cov1; eauto
].
repeat (rw <- @sosub_filter_cswap_range_sosub; auto).
repeat (rw @cswap_range_sosub_combine).
repeat (rw @sosub_aux_sosub_filter; auto);
[
| apply disjoint_fovars_so_swap; auto; allrw disjoint_app_r; repnd; complete auto
| apply disjoint_fovars_so_swap; auto; allrw disjoint_app_r; repnd; complete auto
].
pose proof (ind1
s
(so_swap (mk_swapping l vs0) s)
l
j1
(sosize_so_swap_le s (mk_swapping l vs0))
(so_swap (mk_swapping l0 vs0) s0)
vs
(map (cswapsk (mk_swapping l vs0)) ts1)
(map (cswapsk (mk_swapping l0 vs0)) ts2)
) as h; simpl in h.
repeat (autodimp h hyp); try (rw map_length; complete auto).
* rw @fo_bound_var_so_swap.
rw @free_vars_sosub_combine; [|rw map_length; complete auto].
rewrite free_vars_sk_cswapsks; auto.
apply disjoint_swap; auto.
rw @free_vars_sosub_combine in disjb1; auto.
* rw @fo_bound_var_so_swap.
rw @free_vars_sosub_combine; [|rw map_length; complete auto].
rewrite free_vars_sk_cswapsks; auto.
apply disjoint_swap; auto.
rw @free_vars_sosub_combine in disjb2; auto.
* rw @bound_vars_sosub_combine_map_cswapsk.
rw @free_vars_sosub_combine_map_cswapsk; auto.
rw @fovars_so_swap.
rw <- swapbvars_app.
apply disjoint_swap; auto.
eapply subvars_disjoint_r;[|exact d3].
apply subvars_app_l; dands; auto.
{
apply subvars_app_weak_l; auto.
}
{
apply subvars_app_weak_r.
eapply implies_subvars_flat_map_r; eauto; simpl.
apply subvars_app_weak_r; auto.
}
* rw @bound_vars_sosub_combine_map_cswapsk.
rw @free_vars_sosub_combine_map_cswapsk; auto.
rw @fovars_so_swap.
rw <- swapbvars_app.
apply disjoint_swap; auto.
eapply subvars_disjoint_r;[|exact d4].
apply subvars_app_l; dands; auto.
{
apply subvars_app_weak_l; auto.
}
{
apply subvars_app_weak_r.
eapply implies_subvars_flat_map_r; eauto; simpl.
apply subvars_app_weak_r; auto.
}
* rw @cover_so_vars_soterm in cov1.
apply cov1 in j1.
apply cover_so_vars_so_swapc; auto.
* rw @cover_so_vars_soterm in cov2.
apply cov2 in j0.
apply cover_so_vars_so_swapc; auto.
* allsimpl.
rw disjoint_app_r in d3; rw disjoint_app_r in d4; repnd.
rw disjoint_flat_map_r in d3; rw disjoint_flat_map_r in d4.
applydup d3 in j1.
applydup d4 in j0.
simpl in j2, j3.
rw disjoint_app_r in j2; rw disjoint_app_r in j3; repnd.
rw @bound_vars_sosub_combine in j4; auto.
rw @bound_vars_sosub_combine in j5; auto.
unfold bin_rel_sk, binrel_list.
allrw map_length.
unfold bin_rel_sk, binrel_list in ask; repnd.
dands; auto; introv x.
applydup ask in x.
assert (default_sk = cswapsk (mk_swapping l vs0) (@default_sk p))
as e1 by sp.
rw e1; clear e1; rw map_nth; simpl; fold (@mk_axiom p); fold (@default_sk p).
assert (default_sk = cswapsk (mk_swapping l0 vs0) (@default_sk p))
as e2 by sp.
rw e2; clear e2; rw map_nth; simpl; fold (@mk_axiom p); fold (@default_sk p).
pose proof (nth_in _ n0 ts1 default_sk) as i1.
pose proof (nth_in _ n0 ts2 default_sk) as i2.
autodimp i1 hyp; autodimp i2 hyp; try omega.
remember (nth n0 ts1 default_sk) as sk1.
remember (nth n0 ts2 default_sk) as sk2.
clear Heqsk1 Heqsk2.
rw @free_vars_sosub_combine in disjb3; auto.
rw @free_vars_sosub_combine in disjb0; auto.
rw disjoint_flat_map_l in j5.
rw disjoint_flat_map_l in j4.
rw disjoint_flat_map_l in disjb3.
rw disjoint_flat_map_l in disjb0.
applydup j5 in i1.
applydup j4 in i2.
applydup disjb3 in i1.
applydup disjb0 in i2.
repeat (rw @cswapsk_trivial; auto).
{
allrw disjoint_app_r; repnd.
rw @bound_vars_sosub_combine in disj8; auto.
rw disjoint_flat_map_r in disj8.
applydup disj8 in i2.
apply disjoint_sym; auto.
}
{
allrw disjoint_app_r; repnd.
rw @free_vars_sosub_combine in disj0; auto.
rw disjoint_flat_map_r in disj0.
applydup disj0 in i2.
apply disjoint_sym; auto.
}
{
allrw disjoint_app_r; repnd.
rw @bound_vars_sosub_combine in disj7; auto.
rw disjoint_flat_map_r in disj7.
applydup disj7 in i1.
apply disjoint_sym; auto.
}
{
allrw disjoint_app_r; repnd.
rw @free_vars_sosub_combine in disj9; auto.
rw disjoint_flat_map_r in disj9.
applydup disj9 in i1.
apply disjoint_sym; auto.
}
Qed.
Lemma sosub_change_bvars_alpha_combine {o} :
forall (sks : list (@sosub_kind o)) vs l,
sosub_change_bvars_alpha l (combine vs sks)
= combine vs (map (sk_change_bvars_alpha l) sks).
Proof.
induction sks; destruct vs; introv; allsimpl; auto.
rw IHsks; auto.
Qed.
Lemma free_vars_sk_change_bvars_alpha {o} :
forall (sk : @sosub_kind o) vs,
free_vars_sk (sk_change_bvars_alpha vs sk)
= free_vars_sk sk.
Proof.
destruct sk; introv; simpl.
match goal with
| [ |- context[fresh_distinct_vars ?a ?b] ] =>
remember (fresh_distinct_vars a b) as f
end.
apply fresh_distinct_vars_spec1 in Heqf; repnd.
allrw disjoint_app_r; repnd.
pose proof (free_vars_lsubst_aux_var_ren (change_bvars_alpha vs n) l f []) as h.
repeat (autodimp h hyp); allrw app_nil_r.
rw h; rw @free_vars_change_bvars_alpha; auto.
Qed.
Lemma allvars_range_sosub_combine {o} :
forall (sks : list (@sosub_kind o)) vs,
length vs = length sks
-> allvars_range_sosub (combine vs sks)
= flat_map allvars_sk sks.
Proof.
induction sks; destruct vs; introv len; allsimpl; tcsp.
rw IHsks; auto.
Qed.
Lemma free_vars_subvars_allvars_sk {o} :
forall sk : @sosub_kind o,
subvars (free_vars_sk sk) (allvars_sk sk).
Proof.
destruct sk; simpl.
rw subvars_prop; introv i.
rw in_remove_nvars in i; rw in_app_iff; repnd; right.
pose proof (allvars_eq_all_vars n) as e.
rw eqvars_prop in e; apply e; rw in_app_iff; sp.
Qed.
Lemma sodom_combine_sk_change_bvars_alpha {o} :
forall (sks : list (@sosub_kind o)) vs l,
sodom (combine vs (map (sk_change_bvars_alpha l) sks))
= sodom (combine vs sks).
Proof.
induction sks; destruct vs; introv; allsimpl; auto.
destruct a; rw IHsks.
simpl.
match goal with
| [ |- context[fresh_distinct_vars ?a ?b] ] =>
remember (fresh_distinct_vars a b) as f
end.
apply fresh_distinct_vars_spec1 in Heqf; repnd; allrw; sp.
Qed.
Lemma cover_so_vars_sk_change_bvars_alpha {o} :
forall (t : @SOTerm o) vs sks l,
cover_so_vars t (combine vs sks)
<=> cover_so_vars t (combine vs (map (sk_change_bvars_alpha l) sks)).
Proof.
introv.
unfold cover_so_vars.
rw @sodom_combine_sk_change_bvars_alpha; sp.
Qed.
Lemma alphaeq_sk_trans {o} :
forall sk1 sk2 sk3 : @sosub_kind o,
alphaeq_sk sk1 sk2
-> alphaeq_sk sk2 sk3
-> alphaeq_sk sk1 sk3.
Proof.
destruct sk1, sk2, sk3; introv aeq1 aeq2.
allunfold @alphaeq_sk; allsimpl.
allrw @alphaeqbt_eq.
eapply alpha_eq_bterm_trans; eauto.
Qed.
Lemma alphaeq_sk_sym {o} :
forall (sk1 sk2 : @sosub_kind o),
alphaeq_sk sk1 sk2 -> alphaeq_sk sk2 sk1.
Proof.
introv aeq.
destruct sk1, sk2.
allunfold @alphaeq_sk; allsimpl.
apply alphaeqbt_eq.
apply alphaeqbt_eq in aeq.
apply alpha_eq_bterm_sym; auto.
Qed.
Lemma alphaeq_sk_change_bvars_alpha {o} :
forall (sk : @sosub_kind o) l,
alphaeq_sk sk (sk_change_bvars_alpha l sk).
Proof.
destruct sk; introv.
unfold alphaeq_sk; simpl.
match goal with
| [ |- context[fresh_distinct_vars ?a ?b] ] =>
remember (fresh_distinct_vars a b) as f
end.
apply fresh_distinct_vars_spec1 in Heqf; repnd.
rw disjoint_app_r in Heqf1; repnd.
pose proof (btchange_alpha_aux l (change_bvars_alpha l0 n) f) as h;
repeat (autodimp h hyp); eauto with slow.
revert h.
change_to_lsubst_aux4; introv h.
apply alphaeqbt_eq.
eapply alpha_eq_bterm_trans;[|exact h].
apply alpha_eq_bterm_congr.
pose proof (change_bvars_alpha_spec n l0) as k; simpl in k; repnd; auto.
Qed.
Lemma so_alphaeq_vs_iff {p} :
forall l (t1 t2 : @SOTerm p),
so_alphaeq_vs l t1 t2
<=> so_alphaeq t1 t2.
Proof.
introv; split; intro k.
- apply so_alphaeq_exists; eexists; eauto.
- rw @so_alphaeq_all in k; sp.
Qed.
Lemma so_alphaeq_add_so_swap2 {p} :
forall vs1 vs2 (t1 t2 : @SOTerm p),
length vs1 = length vs2
-> no_repeats vs2
-> disjoint vs2 (vs1 ++ all_fo_vars t1 ++ all_fo_vars t2)
-> so_alphaeq t1 t2
-> so_alphaeq
(so_swap (mk_swapping vs1 vs2) t1)
(so_swap (mk_swapping vs1 vs2) t2).
Proof.
introv len norep2 disj aeq.
rw <- (@so_alphaeq_vs_iff p (vs1 ++ vs2 ++ [])).
apply so_alphaeq_add_so_swap; auto.
apply so_alphaeq_vs_iff; auto.
Qed.
Lemma so_alphaeq_vs_trans {o} :
forall (t1 t2 t3 : @SOTerm o) vs,
so_alphaeq_vs vs t1 t2
-> so_alphaeq_vs vs t2 t3
-> so_alphaeq_vs vs t1 t3.
Proof.
soterm_ind1s t1 as [v1 ts1 ind1|op1 bs1 ind1] Case; introv aeq1 aeq2; allsimpl.
- Case "sovar".
inversion aeq1 as [? ? ? len1 imp1|]; subst; clear aeq1.
inversion aeq2 as [? ? ? len2 imp2|]; subst; clear aeq2.
constructor; try omega.
introv i.
rw in_combine_sel_iff in i; exrepnd.
pose proof (nth_select1 n ts1 default_soterm i1) as h1.
pose proof (nth_select1 n ts3 default_soterm i2) as h2.
rw h1 in i3; rw h2 in i0; cpx; clear h1 h2.
pose proof (imp1 (nth n ts1 default_soterm) (nth n ts2 default_soterm)) as h1.
pose proof (imp2 (nth n ts2 default_soterm) (nth n ts3 default_soterm)) as h2.
autodimp h1 hyp.
{
apply in_combine_sel_iff; exists n; dands; auto; try omega;
symmetry; apply nth_select1; auto; omega.
}
autodimp h2 hyp.
{
apply in_combine_sel_iff; exists n; dands; auto; try omega;
symmetry; apply nth_select1; auto; omega.
}
eapply ind1; eauto.
apply nth_in; auto.
- Case "soterm".
inversion aeq1 as [|? ? ? len1 imp1]; subst; clear aeq1.
inversion aeq2 as [|? ? ? len2 imp2]; subst; clear aeq2.
constructor; try omega.
introv i.
destruct b1, b2.
rw in_combine_sel_iff in i; exrepnd.
pose proof (nth_select1 n bs1 default_sobterm i1) as h1.
pose proof (nth_select1 n bts0 default_sobterm i2) as h2.
rw h1 in i3; rw h2 in i0; cpx; clear h1 h2.
pose proof (imp1 (nth n bs1 default_sobterm) (nth n bts2 default_sobterm)) as h1; clear imp1.
pose proof (imp2 (nth n bts2 default_sobterm) (nth n bts0 default_sobterm)) as h2; clear imp2.
autodimp h1 hyp.
{
apply in_combine_sel_iff; exists n; dands; auto; try omega;
symmetry; apply nth_select1; auto; omega.
}
autodimp h2 hyp.
{
apply in_combine_sel_iff; exists n; dands; auto; try omega;
symmetry; apply nth_select1; auto; omega.
}
pose proof (nth_in _ n bs1 default_sobterm i1) as j1.
pose proof (nth_in _ n bts0 default_sobterm i2) as j2.
rw <- i3 in h1; rw <- i3 in j1; clear i3.
rw <- i0 in h2; rw <- i0 in j2; clear i0.
remember (nth n bts2 default_sobterm) as b; clear Heqb.
inversion h1 as [? ? ? ? ? l1 l2 disj1 norep1 aeq1]; subst; clear h1.
assert (subvars vs (vs
++ (vs0
++ l
++ all_fo_vars s
++ all_fo_vars t2
++ all_fo_vars (so_swap (mk_swapping l vs0) s)
++ all_fo_vars (so_swap (mk_swapping vs2 vs0) t2)
)
)
) as sv by (apply subvars_app_weak_l; auto).
eapply so_alphaeqbt_vs_implies_more in h2;[|exact sv].
inversion h2 as [? ? ? ? ? l3 l4 disj2 norep2 aeq2]; subst; clear h2.
apply (soaeqbt vs vs1); auto;
try omega;
try (complete (allrw disjoint_app_r; sp)).
apply so_alphaeq_vs_iff in aeq1.
apply so_alphaeq_vs_iff in aeq2.
apply (so_alphaeq_add_so_swap2 vs0 vs1) in aeq1; auto;
try omega;
try (complete (allrw disjoint_app_r; sp)).
repeat (rw @so_swap_so_swap in aeq1).
repeat (rw mk_swapping_app in aeq1; auto).
rw @so_swap_disj_chain in aeq1; auto;
try omega;
try (complete (allrw disjoint_app_r; sp; eauto with slow)).
rw @so_swap_disj_chain in aeq1; auto;
try omega;
try (complete (allrw disjoint_app_r; sp; eauto with slow)).
apply so_alphaeq_vs_iff.
eapply ind1;[exact j1|idtac|exact aeq1|exact aeq2].
rw @sosize_so_swap; auto.
Qed.
Lemma so_alphaeq_trans {o} :
forall (t1 t2 t3 : @SOTerm o),
so_alphaeq t1 t2
-> so_alphaeq t2 t3
-> so_alphaeq t1 t3.
Proof.
introv aeq1 aeq2.
pose proof (so_alphaeq_vs_trans t1 t2 t3 []); sp.
Qed.
Fixpoint soren_filter (ren : soren) (vars : list sovar_sig) : soren :=
match ren with
| nil => nil
| (sov,v) :: xs =>
if memsovar sov vars
then soren_filter xs vars
else (sov,v) :: soren_filter xs vars
end.
Fixpoint so_rename {p} (ren : soren) (t : @SOTerm p) :=
match t with
| sovar v ts =>
sovar
(sovar2var (rename_sovar ren (v,length ts)))
(map (so_rename ren) ts)
| soterm o bs => soterm o (map (so_rename_bt ren) bs)
end
with so_rename_bt {p} ren bt :=
match bt with
| sobterm vs t =>
sobterm vs (so_rename (soren_filter ren (vars2sovars vs)) t)
end.
Lemma swapvar_is_rename_var :
forall v vs1 vs2,
!LIn v vs2
-> no_repeats vs2
-> disjoint vs1 vs2
-> swapvar (mk_swapping vs1 vs2) v
= rename_var (mk_swapping vs1 vs2) v.
Proof.
induction vs1; destruct vs2; introv ni norep disj;
unfold rename_var; allsimpl; auto.
allrw not_over_or; repnd.
allrw disjoint_cons_l.
allrw disjoint_cons_r; allsimpl; repnd.
allrw not_over_or; repnd.
allrw no_repeats_cons; repnd.
unfold oneswapvar.
boolvar; tcsp.
- apply swapvar_not_in; auto.
- apply IHvs1; auto.
Qed.
Lemma in_combine_swap :
forall {A} (l1 l2 : list A) a1 a2,
length l1 = length l2
-> LIn (a1, a2) (combine l1 l2)
-> LIn (a2, a1) (combine l2 l1).
Proof.
induction l1; destruct l2; introv len i; allsimpl; cpx.
dorn i; cpx.
Qed.
Lemma so_alphaeq_vs_sym {o} :
forall (t1 t2 : @SOTerm o) vs,
so_alphaeq_vs vs t1 t2 -> so_alphaeq_vs vs t2 t1.
Proof.
soterm_ind1s t1 as [v ts ind|op bs ind] Case; introv aeq.
- Case "sovar".
inversion aeq as [? ? ? len imp|]; subst; clear aeq.
constructor; auto.
introv i.
apply in_combine_swap in i; auto.
applydup imp in i.
apply ind; auto.
apply in_combine in i; sp.
- Case "soterm".
inversion aeq as [|? ? ? len imp]; subst; clear aeq.
constructor; auto.
introv i.
apply in_combine_swap in i; auto.
applydup imp in i.
destruct b1, b2.
inversion i0 as [? ? ? ? ? len1 len2 disj norep ae]; subst; clear i0.
apply (soaeqbt vs vs0); auto;
try omega;
try (complete (allrw disjoint_app_r; sp)).
apply in_combine in i; repnd.
eapply ind; eauto.
rw @sosize_so_swap; auto.
Qed.
Lemma so_alphaeq_refl {o} :
forall t : @SOTerm o, so_alphaeq t t.
Proof.
soterm_ind1s t as [v ts ind|op bs ind] Case; auto.
- Case "sovar".
constructor; auto.
introv i.
apply in_combine_sel_iff in i; exrepnd.
rw <- i3 in i0; ginv; apply ind; auto.
symmetry in i3; apply select_in in i3; auto.
- Case "soterm".
constructor; auto.
introv i.
apply in_combine_sel_iff in i; exrepnd.
rw <- i3 in i0; ginv.
symmetry in i3; apply select_in in i3; auto.
destruct b1.
pose proof (fresh_vars (length l) (l ++ all_fo_vars s)) as h; exrepnd.
apply (soaeqbt [] lvn); allsimpl; auto;
[allrw disjoint_app_r; complete sp|].
eapply ind; eauto.
rw @sosize_so_swap; auto.
Qed.
Hint Immediate so_alphaeq_refl.
Lemma app_combine :
forall {A} (vs1 vs2 vs3 vs4 : list A),
length vs1 = length vs2
-> combine vs1 vs2 ++ combine vs3 vs4
= combine (vs1 ++ vs3) (vs2 ++ vs4).
Proof.
induction vs1; destruct vs2; introv len; allsimpl; cpx.
rw IHvs1; auto.
Qed.
Lemma foren_find_app :
forall v ren1 ren2,
foren_find (ren1 ++ ren2) v
= match foren_find ren1 v with
| Some w => Some w
| None => foren_find ren2 v
end.
Proof.
induction ren1; simpl; sp.
destruct a0; destruct v; boolvar; cpx.
Qed.
Lemma foren_find_none :
forall (ren : foren) v,
foren_find ren v = None
-> !LIn v (foren_dom ren).
Proof.
induction ren; introv k; allsimpl; tcsp.
destruct a; boolvar; cpx.
apply IHren in k.
apply not_over_or; sp.
Qed.
Lemma foren_find_filter_eq :
forall ren1 ren2 v,
!LIn v (foren_dom ren1)
-> foren_find (foren_filter ren2 (foren_dom ren1)) v
= foren_find ren2 v.
Proof.
induction ren2; introv ni; allsimpl; auto.
destruct a; boolvar; simpl; boolvar; tcsp.
Qed.
Lemma rename_var_filter :
forall ren1 ren2 v,
rename_var (ren1 ++ ren2) v
= rename_var (ren1 ++ foren_filter ren2 (foren_dom ren1)) v.
Proof.
unfold rename_var; introv.
allrw foren_find_app.
remember (foren_find ren1 v) as f1; destruct f1; symmetry in Heqf1; auto.
apply foren_find_none in Heqf1.
rw foren_find_filter_eq; auto.
Qed.
Lemma foren_vars_app :
forall ren1 ren2 : foren,
foren_vars (ren1 ++ ren2) = foren_vars ren1 ++ foren_vars ren2.
Proof.
induction ren1; introv; allsimpl; auto.
destruct a; simpl.
rw IHren1; auto.
Qed.
(*
Lemma fo_change_bvars_alpha_filter {o} :
forall (t : @SOTerm o) vs ren1 ren2,
so_alphaeq
(fo_change_bvars_alpha vs (ren1 ++ ren2) t)
(fo_change_bvars_alpha vs (ren1 ++ foren_filter ren2 (foren_dom ren1)) t).
Proof.
soterm_ind t as [v ts ind|op bs ind] Case; introv; simpl.
- Case "sovar".
boolvar; subst; allsimpl.
+ rw rename_var_filter; auto.
+ constructor; allrw map_length; auto.
introv i.
rw <- @map_combine in i.
rw in_map_iff in i; exrepnd; cpx.
apply in_combine_sel_iff in i1; exrepnd.
rw <- i3 in i0; ginv.
symmetry in i3; apply select_in in i3.
apply ind; simpl; auto.
- Case "soterm".
constructor; allrw map_length; auto.
introv i.
rw <- @map_combine in i.
rw in_map_iff in i; exrepnd; cpx; allsimpl.
apply in_combine_sel_iff in i1; exrepnd.
rw <- i3 in i0; ginv.
symmetry in i3; apply select_in in i3.
destruct a0; simpl.
repeat gen_fresh.
allrw foren_vars_app.
pose proof (fresh_vars
(length f)
(f
++ f0
++ vs
++ all_fo_vars s
++ foren_vars ren1
++ foren_vars ren2
++ all_fo_vars (fo_change_bvars_alpha vs (mk_foren l f ++ ren1 ++ ren2) s)
++ all_fo_vars (fo_change_bvars_alpha vs (mk_foren l f0 ++ ren1 ++ foren_filter ren2 (foren_dom ren1)) s)
)
) as fv; exrepnd.
apply (soaeqbt [] lvn); simpl; auto; try omega.
+ allrw disjoint_app_r; sp.
+
Qed.
*)
Lemma eqvars_move_around :
forall vs1 v vs2,
eqvars (v :: vs1 ++ vs2) (vs1 ++ v :: vs2).
Proof.
introv; rw eqvars_prop; introv; simpl.
allrw in_app_iff; allsimpl; split; sp.
Qed.
Lemma foren_vars_mk_swapping :
forall vs1 vs2,
length vs1 = length vs2
-> eqvars (foren_vars (mk_swapping vs1 vs2)) (vs1 ++ vs2).
Proof.
induction vs1; destruct vs2; introv len; allsimpl; cpx.
apply eqvars_cons_lr; auto.
pose proof (eqvars_move_around vs1 n vs2) as eqv.
eapply eqvars_trans;[|exact eqv].
apply eqvars_cons_lr; auto.
Qed.
Lemma subvars_eqvars_r :
forall s1 s2 s3 : list NVar,
subvars s1 s2 -> eqvars s2 s3 -> subvars s1 s3.
Proof.
introv sv eqv.
allrw subvars_prop.
allrw eqvars_prop.
introv i.
apply sv in i.
apply eqv in i; auto.
Qed.
Lemma swapvar_app :
forall sw2 sw1 v,
swapvar (sw1 ++ sw2) v = swapvar sw2 (swapvar sw1 v).
Proof.
induction sw1; introv; simpl; auto.
destruct a; simpl.
rw IHsw1; auto.
Qed.
Lemma mk_swapping_cons :
forall a b vs1 vs2,
mk_swapping (a :: vs1) (b :: vs2) = (a,b) :: mk_swapping vs1 vs2.
Proof. sp. Qed.
Lemma swapvar_cons :
forall a b sw v,
swapvar ((a,b) :: sw) v = swapvar sw (oneswapvar a b v).
Proof. sp. Qed.
Lemma swapvar_disj_chain2 :
forall vs1 vs2 vs3 vs4 vs v,
length vs1 = length vs
-> length vs2 = length vs3
-> length vs = length vs4
-> !LIn v vs
-> !LIn v vs4
-> disjoint vs vs1
-> disjoint vs vs2
-> disjoint vs vs3
-> disjoint vs vs4
-> disjoint vs4 vs1
-> disjoint vs4 vs2
-> disjoint vs4 vs3
-> no_repeats vs
-> no_repeats vs3
-> no_repeats vs4
-> swapvar (mk_swapping (vs1 ++ vs2 ++ vs) (vs ++ vs3 ++ vs4)) v
= swapvar (mk_swapping (vs1 ++ vs2) (vs4 ++ vs3)) v.
Proof.
induction vs1; destruct vs; allsimpl;
introv len1 len2 len3;
introv ni1 ni2;
introv disj1 disj2 disj3 disj4 disj5 disj6 disj7;
introv norep1 norep2 norep3;
allrw app_nil_r; cpx; allsimpl; allrw app_nil_r; auto.
destruct vs4; allsimpl; cpx.
unfold oneswapvar; boolvar; tcsp; allrw not_over_or; repnd;
allrw disjoint_cons_l; allrw disjoint_cons_r; repnd;
allsimpl; allrw not_over_or; repnd;
allrw no_repeats_cons; repnd; tcsp.
- rw app_assoc.
rw app_assoc.
rw <- mk_swapping_app; try (complete (allrw length_app; sp)).
rw swapvar_app.
rw (swapvar_not_in n (vs1 ++ vs2) (vs ++ vs3)); try (complete (rw in_app_iff; sp)).
rw mk_swapping_cons; simpl.
unfold oneswapvar; boolvar.
repeat (rw swapvar_not_in); auto; allrw in_app_iff; tcsp.
- rw app_assoc.
rw app_assoc.
rw <- mk_swapping_app; try (complete (allrw length_app; sp)).
rw swapvar_app.
rw mk_swapping_cons; simpl.
unfold oneswapvar; boolvar; auto.
+ provefalse.
pose proof (swapvar_implies (vs1 ++ vs2) (vs ++ vs3) v) as h.
rw e in h; simpl in h.
allrw in_app_iff; sp.
+ provefalse.
pose proof (swapvar_implies (vs1 ++ vs2) (vs ++ vs3) v) as h.
rw e in h; simpl in h.
allrw in_app_iff; sp.
+ rw <- swapvar_app.
rw mk_swapping_app; try (complete (allrw length_app; sp)).
allrw <- app_assoc.
apply IHvs1; auto.
Qed.
Lemma swapbvars_disj_chain2 :
forall vs1 vs2 vs3 vs4 vs l,
length vs1 = length vs
-> length vs2 = length vs3
-> length vs = length vs4
-> disjoint vs l
-> disjoint vs4 l
-> disjoint vs vs1
-> disjoint vs vs2
-> disjoint vs vs3
-> disjoint vs vs4
-> disjoint vs4 vs1
-> disjoint vs4 vs2
-> disjoint vs4 vs3
-> no_repeats vs
-> no_repeats vs3
-> no_repeats vs4
-> swapbvars (mk_swapping (vs1 ++ vs2 ++ vs) (vs ++ vs3 ++ vs4)) l
= swapbvars (mk_swapping (vs1 ++ vs2) (vs4 ++ vs3)) l.
Proof.
induction l;
introv len1 len2 len3;
introv ni1 ni2;
introv disj1 disj2 disj3 disj4 disj5 disj6 disj7;
introv norep1 norep2 norep3;
allsimpl; auto.
allrw disjoint_cons_r; repnd.
rw swapvar_disj_chain2; auto.
apply eq_cons; auto.
Qed.
Lemma so_swap_disj_chain2 {o} :
forall (t : @SOTerm o) (vs1 vs2 vs3 vs4 vs : list NVar),
length vs1 = length vs
-> length vs2 = length vs3
-> length vs = length vs4
-> disjoint vs (all_fo_vars t)
-> disjoint vs4 (all_fo_vars t)
-> disjoint vs vs1
-> disjoint vs vs2
-> disjoint vs vs3
-> disjoint vs vs4
-> disjoint vs4 vs1
-> disjoint vs4 vs2
-> disjoint vs4 vs3
-> no_repeats vs
-> no_repeats vs3
-> no_repeats vs4
-> so_swap (mk_swapping (vs1 ++ vs2 ++ vs) (vs ++ vs3 ++ vs4)) t
= so_swap (mk_swapping (vs1 ++ vs2) (vs4 ++ vs3)) t.
Proof.
soterm_ind1s t as [v ts ind|op bs ind] Case;
introv len1 len2 len3;
introv disj1 disj2 disj3 disj4 disj5 disj6 disj7 disj8 disj9;
introv norep1 norep2 norep3;
allsimpl.
- Case "sovar".
boolvar; subst; allsimpl; auto.
+ allrw disjoint_singleton_r.
rw swapvar_disj_chain2; auto.
+ f_equal.
allrw disjoint_cons_r; repnd.
allrw disjoint_flat_map_r.
apply eq_maps; introv i.
applydup disj0 in i.
applydup disj10 in i.
apply ind; auto.
- Case "soterm".
f_equal.
apply eq_maps; introv i.
destruct x; simpl.
allrw disjoint_flat_map_r.
applydup disj1 in i.
applydup disj2 in i.
allsimpl.
allrw disjoint_app_r; repnd.
rw swapbvars_disj_chain2; auto.
f_equal.
eapply ind; eauto.
Qed.
Lemma so_alphaeq_fo_change_bvars_alpha {o} :
forall (t : @SOTerm o) vs vs1 vs2,
length vs1 = length vs2
-> disjoint vs2 vs1
-> disjoint vs2 vs
-> disjoint vs2 (all_fo_vars t)
-> no_repeats vs2
-> so_alphaeq
(so_swap (mk_swapping vs1 vs2) t)
(fo_change_bvars_alpha vs (mk_swapping vs1 vs2) t).
Proof.
soterm_ind t as [v ts ind|op bs ind] Case; introv len disj1 disj2 disj3 norep; simpl.
- Case "sovar".
boolvar; subst; allsimpl; auto.
+ rw disjoint_singleton_r in disj3.
rw swapvar_is_rename_var; eauto with slow; auto.
+ constructor;[allrw map_length; complete auto|].
introv i.
rw <- @map_combine in i.
rw in_map_iff in i; exrepnd; cpx; allsimpl.
rw in_combine_sel_iff in i1; exrepnd.
rw <- i3 in i0; ginv.
symmetry in i3; apply select_in in i3.
eapply ind; auto.
allrw disjoint_cons_r; repnd.
allrw disjoint_flat_map_r.
apply disj0; auto.
- Case "soterm".
constructor;[allrw map_length; complete auto|].
introv i.
rw <- @map_combine in i.
rw in_map_iff in i; exrepnd; cpx; allsimpl.
rw in_combine_sel_iff in i1; exrepnd.
rw <- i3 in i0; ginv.
symmetry in i3; apply select_in in i3.
destruct a0; simpl.
gen_fresh.
rw @app_combine; auto.
pose proof (fresh_vars
(length l)
(l
++ vs1
++ vs2
++ swapbvars (mk_swapping vs1 vs2) l
++ f
++ all_fo_vars (so_swap (mk_swapping vs1 vs2) s)
++ all_fo_vars (fo_change_bvars_alpha vs (mk_swapping (l ++ vs1) (f ++ vs2)) s)
++ all_fo_vars (so_swap (mk_swapping (l ++ vs1) (f ++ vs2)) s)
++ all_fo_vars s)) as h; exrepnd.
apply (soaeqbt [] lvn); simpl; auto; try omega.
+ rw length_swapbvars; auto.
+ allrw disjoint_app_r; sp; eauto with slow.
+ pose proof (ind s l i3 vs (l ++ vs1) (f ++ vs2)) as h.
repeat (autodimp h hyp); auto.
* allrw length_app; omega.
* allrw disjoint_app_r; allrw disjoint_app_l; sp; eauto with slow.
{
rw disjoint_flat_map_r in disj3.
apply disj3 in i3; simpl in i3; rw disjoint_app_r in i3; sp.
}
{
pose proof (foren_vars_mk_swapping vs1 vs2) as eqv;
autodimp eqv hyp.
eapply subvars_disjoint_r;[|exact Heqf1].
apply eqvars_sym in eqv.
eapply subvars_eqvars_r;[|exact eqv].
apply subvars_app_weak_l; auto.
}
* allrw disjoint_app_r; allrw disjoint_app_l; sp; eauto with slow.
* allrw disjoint_app_r; allrw disjoint_app_l; sp; eauto with slow.
rw disjoint_flat_map_r in disj3.
apply disj3 in i3; simpl in i3; rw disjoint_app_r in i3; sp.
* rw no_repeats_app; sp.
allrw disjoint_app_r; sp.
pose proof (foren_vars_mk_swapping vs1 vs2) as eqv;
autodimp eqv hyp.
eapply subvars_disjoint_r;[|exact Heqf1].
apply eqvars_sym in eqv.
eapply subvars_eqvars_r;[|exact eqv].
apply subvars_app_weak_r; auto.
* pose proof (so_alphaeq_add_so_swap2
f lvn
(so_swap (mk_swapping (l ++ vs1) (f ++ vs2)) s)
(fo_change_bvars_alpha vs (mk_swapping (l ++ vs1) (f ++ vs2)) s)
) as k.
repeat (autodimp k hyp); try omega.
{
allrw disjoint_app_r; sp.
}
eapply so_alphaeq_trans;[|exact k]; clear h k.
allrw @so_swap_so_swap.
repeat (rw mk_swapping_app;[|auto; allrw length_app; complete sp]).
rw <- @so_swap_app_so_swap;
try (complete (allrw disjoint_app_r; sp; eauto with slow));
try (complete (allrw disjoint_flat_map_r;
apply disj3 in i3; simpl in i3;
rw disjoint_app_r in i3; sp; eauto with slow)).
allrw <- app_assoc.
rw @so_swap_disj_chain2; auto; try omega; eauto with slow;
try (complete (allrw disjoint_app_r; sp; eauto with slow));
try (complete (allrw disjoint_flat_map_r;
apply disj3 in i3; simpl in i3;
rw disjoint_app_r in i3; sp; eauto with slow)).
{
allrw disjoint_app_r; repnd.
pose proof (foren_vars_mk_swapping vs1 vs2) as eqv;
autodimp eqv hyp.
eapply subvars_disjoint_r;[|exact Heqf1].
apply eqvars_sym in eqv.
eapply subvars_eqvars_r;[|exact eqv].
apply subvars_app_weak_l; auto.
}
{
allrw disjoint_app_r; repnd.
pose proof (foren_vars_mk_swapping vs1 vs2) as eqv;
autodimp eqv hyp.
eapply subvars_disjoint_r;[|exact Heqf1].
apply eqvars_sym in eqv.
eapply subvars_eqvars_r;[|exact eqv].
apply subvars_app_weak_r; auto.
}
Qed.
Lemma swapbvars_nil_l :
forall l, swapbvars [] l = l.
Proof.
induction l; allsimpl; auto.
rw IHl; auto.
Qed.
Lemma so_swap_nil {o} :
forall t : @SOTerm o, so_swap [] t = t.
Proof.
soterm_ind t as [v ts ind|op bs ind] Case; introv; simpl.
- Case "sovar".
boolvar; subst; auto.
f_equal.
apply eq_map_l; auto.
- Case "soterm".
f_equal.
apply eq_map_l; introv i.
destruct x; simpl.
rw swapbvars_nil_l; f_equal.
eapply ind; eauto.
Qed.
Lemma so_alphaeq_fo_change_bvars_alpha2 {o} :
forall (t : @SOTerm o) vs,
so_alphaeq t (fo_change_bvars_alpha vs [] t).
Proof.
introv.
pose proof (so_alphaeq_fo_change_bvars_alpha t vs [] []) as h.
repeat (autodimp h hyp).
allsimpl; rw @so_swap_nil in h; auto.
Qed.
Lemma fo_bound_vars_fo_change_bvars_alpha {o} :
forall (t : @SOTerm o) vs ren,
disjoint vs (fo_bound_vars (fo_change_bvars_alpha vs ren t)).
Proof.
soterm_ind t as [v ts ind|op bs ind] Case; introv; simpl.
- Case "sovar".
boolvar; subst; allsimpl; auto.
rw disjoint_flat_map_r; introv i.
allrw in_map_iff; exrepnd; subst; auto.
- Case "soterm".
rw disjoint_flat_map_r; introv i.
allrw in_map_iff; exrepnd; subst.
destruct a; simpl.
gen_fresh; allrw disjoint_app_r; repnd; dands; eauto with slow.
Qed.
Lemma fo_bound_vars_fo_change_bvars_alpha2 {o} :
forall (t : @SOTerm o) vs1 vs2 ren,
subvars vs1 vs2
-> disjoint vs1 (fo_bound_vars (fo_change_bvars_alpha vs2 ren t)).
Proof.
introv sv.
eapply subvars_disjoint_l; eauto.
apply fo_bound_vars_fo_change_bvars_alpha.
Qed.
Lemma map_rename_sovar_nil :
forall vs, map (rename_sovar []) vs = vs.
Proof.
introv; apply eq_map_l; introv i.
unfold rename_sovar; simpl; auto.
Qed.
Lemma cover_so_vars_fo_change_bvars_alpha {o} :
forall (t : @SOTerm o) vs sub,
cover_so_vars (fo_change_bvars_alpha vs [] t) sub
<=> cover_so_vars t sub.
Proof.
introv.
unfold cover_so_vars.
rw @so_free_vars_fo_change_bvars_alpha; simpl.
rw map_rename_sovar_nil; sp.
Qed.
Lemma nth_map_sk_change_bvars_alpha {o} :
forall (sks : list (@sosub_kind o)) vs n,
nth n (map (sk_change_bvars_alpha vs) sks) default_sk
= sk_change_bvars_alpha vs (nth n sks default_sk).
Proof.
introv.
assert (default_sk = sk_change_bvars_alpha vs (@default_sk o)) as e by auto.
rw e; rw map_nth; clear e; auto.
Qed.
Inductive alphaeq_sosub {o} : @SOSub o -> @SOSub o -> Type :=
| aeqsosub_nil : alphaeq_sosub [] []
| aeqsosub_cons :
forall v sk1 sk2 sub1 sub2,
alphaeq_sk sk1 sk2
-> alphaeq_sosub sub1 sub2
-> alphaeq_sosub ((v,sk1) :: sub1) ((v,sk2) :: sub2).
Hint Constructors alphaeq_sosub.
Lemma sosub_as_combine {o} :
forall sub : @SOSub o,
sub = combine (so_dom sub) (so_range sub).
Proof.
induction sub; simpl; auto.
destruct a; simpl; rw <- IHsub; auto.
Qed.
Lemma sosub_change_bvars_alpha_spec {o} :
forall vars (sub : @SOSub o),
let sub' := sosub_change_bvars_alpha vars sub in
disjoint vars (bound_vars_sosub sub')
# alphaeq_sosub sub sub'.
Proof.
induction sub; introv; allsimpl; repnd; dands; allsimpl; auto.
- rw disjoint_app_r; dands; auto.
apply disjoint_bound_vars_sk; auto.
- constructor; auto.
apply alphaeq_sk_change_bvars_alpha.
Qed.
Ltac sosub_change s :=
match goal with
| [ |- context[sosub_change_bvars_alpha ?vs ?sub] ] =>
let h := fresh "h" in
pose proof (sosub_change_bvars_alpha_spec vs sub) as h;
simpl in h;
remember (sosub_change_bvars_alpha vs sub) as s;
clear_eq s (sosub_change_bvars_alpha vs sub);
repnd
end.
Lemma alphaeq_sosub_implies_eq_sodoms {o} :
forall (sub1 sub2 : @SOSub o),
alphaeq_sosub sub1 sub2 -> sodom sub1 = sodom sub2.
Proof.
induction sub1; destruct sub2; introv aeq; allsimpl; tcsp.
- inversion aeq.
- inversion aeq.
- inversion aeq; subst; clear aeq.
destruct sk1, sk2; f_equal; auto.
allapply @alphaeq_sk_eq_length; allsimpl; sp.
Qed.
Lemma alphaeq_sosub_implies_eq_lengths {o} :
forall (sub1 sub2 : @SOSub o),
alphaeq_sosub sub1 sub2 -> length sub1 = length sub2.
Proof.
induction sub1; destruct sub2; introv aeq; inversion aeq; tcsp; cpx.
Qed.
Lemma alphaeq_sosub_implies_alphaeq_sk {o} :
forall (sub1 sub2 : @SOSub o),
alphaeq_sosub sub1 sub2
-> bin_rel_sk alphaeq_sk (so_range sub1) (so_range sub2).
Proof.
induction sub1; destruct sub2; introv aeq; allsimpl; tcsp.
- unfold bin_rel_sk, binrel_list; simpl; sp.
- inversion aeq.
- inversion aeq.
- inversion aeq; subst; clear aeq.
simpl; apply bin_rel_sk_cons; dands; sp.
Qed.
Lemma alpha_eq_bterm_preserves_free_vars {o} :
forall (bt1 bt2 : @BTerm o),
alpha_eq_bterm bt1 bt2 -> free_vars_bterm bt1 = free_vars_bterm bt2.
Proof.
introv aeq.
pose proof (alphaeq_preserves_free_vars (oterm Exc [bt1]) (oterm Exc [bt2])) as h.
simpl in h; allrw app_nil_r; apply h.
constructor; simpl; auto.
introv i; destruct n; cpx.
Qed.
Lemma alphaeq_sk_preserves_free_vars {o} :
forall (sk1 sk2 : @sosub_kind o),
alphaeq_sk sk1 sk2
-> free_vars_sk sk1 = free_vars_sk sk2.
Proof.
destruct sk1, sk2; introv aeq.
apply alphaeq_sk_iff_alphaeq_bterm in aeq.
apply alphaeqbt_eq in aeq.
apply alpha_eq_bterm_preserves_free_vars in aeq; allsimpl; auto.
Qed.
Lemma alphaeq_sosub_preserves_free_vars {o} :
forall (sub1 sub2 : @SOSub o),
alphaeq_sosub sub1 sub2
-> free_vars_sosub sub1 = free_vars_sosub sub2.
Proof.
induction sub1; destruct sub2; introv aeq; inversion aeq; allsimpl; auto;
subst; clear aeq.
f_equal;[|apply IHsub1;auto].
apply alphaeq_sk_preserves_free_vars; auto.
Qed.
Lemma alphaeq_sosub_trans {o} :
forall (sub1 sub2 sub3 : @SOSub o),
alphaeq_sosub sub1 sub2
-> alphaeq_sosub sub2 sub3
-> alphaeq_sosub sub1 sub3.
Proof.
induction sub1; destruct sub2, sub3; introv aeq1 aeq2; tcsp;
inversion aeq1; inversion aeq2; subst; cpx; clear aeq1 aeq2.
constructor; eauto.
eapply alphaeq_sk_trans; eauto.
Qed.
Hint Resolve alphaeq_sosub_trans : slow.
Lemma alphaeq_sosub_sym {o} :
forall (sub1 sub2 : @SOSub o),
alphaeq_sosub sub1 sub2
-> alphaeq_sosub sub2 sub1.
Proof.
induction sub1; destruct sub2; introv aeq; tcsp;
inversion aeq; subst; cpx; clear aeq.
constructor; eauto.
eapply alphaeq_sk_sym; eauto.
Qed.
Hint Resolve alphaeq_sosub_sym : slow.
Lemma alphaeq_sosub_app {o} :
forall (sub1 sub2 sub3 sub4 :@SOSub o),
alphaeq_sosub sub1 sub2
-> alphaeq_sosub sub3 sub4
-> alphaeq_sosub (sub1 ++ sub3) (sub2 ++ sub4).
Proof.
induction sub1; destruct sub2; introv aeq1 aeq2; tcsp;
inversion aeq1; subst; clear aeq1; allsimpl.
constructor; auto.
Qed.
Lemma alphaeq_sk_iff_alphaeq_bterm2 {o} :
forall (sk1 sk2 : @sosub_kind o),
alphaeq_sk sk1 sk2 <=> alpha_eq_bterm (sk2bterm sk1) (sk2bterm sk2).
Proof.
destruct sk1, sk2.
pose proof (alphaeq_sk_iff_alphaeq_bterm l l0 n n0) as h; rw <- h.
rw @alphaeqbt_eq; simpl; sp.
Qed.
Lemma alphaeq_sk_refl {o} :
forall (sk : @sosub_kind o),
alphaeq_sk sk sk.
Proof.
introv.
apply alphaeq_sk_iff_alphaeq_bterm2.
apply alphaeqbt_refl.
Qed.
Lemma alphaeq_sosub_refl {o} :
forall (sub :@SOSub o),
alphaeq_sosub sub sub.
Proof.
induction sub; auto.
destruct a.
constructor; auto.
apply alphaeq_sk_refl.
Qed.
Hint Resolve alphaeq_sosub_refl : slow.
Lemma sosub_find_some_if_alphaeq_sosub {o} :
forall (sub1 sub2 : @SOSub o) v sk,
alphaeq_sosub sub1 sub2
-> sosub_find sub1 v = Some sk
-> {sk' : sosub_kind & alphaeq_sk sk sk' # sosub_find sub2 v = Some sk'}.
Proof.
induction sub1; destruct sub2; introv aeq sf; allsimpl; tcsp.
- inversion aeq.
- destruct a, p; destruct s, s0.
inversion aeq; subst; clear aeq.
boolvar; subst; cpx.
+ eexists; dands; eauto.
+ allapply @alphaeq_sk_eq_length; allsimpl.
destruct n; allrw; sp.
+ allapply @alphaeq_sk_eq_length; allsimpl.
destruct n; allrw; sp.
Qed.
Lemma eqvars_allvars_sk {o} :
forall (sk : @sosub_kind o),
eqvars (allvars_sk sk)
(free_vars_sk sk ++ bound_vars_sk sk).
Proof.
destruct sk; simpl.
rw eqvars_prop; introv; split; intro i;
allrw in_app_iff; allrw in_remove_nvars.
- destruct (in_deq _ deq_nvar x l); tcsp.
dorn i; tcsp.
pose proof (allvars_eq_all_vars n) as h; rw eqvars_prop in h; apply h in i.
rw in_app_iff in i; tcsp.
- dorn i; repnd.
+ right.
pose proof (allvars_eq_all_vars n) as h; rw eqvars_prop in h; apply h.
rw in_app_iff; sp.
+ dorn i; tcsp.
right.
pose proof (allvars_eq_all_vars n) as h; rw eqvars_prop in h; apply h.
rw in_app_iff; sp.
Qed.
Lemma eqvars_allvars_range_sosub {o} :
forall (sub : @SOSub o),
eqvars
(allvars_range_sosub sub)
(free_vars_sosub sub ++ bound_vars_sosub sub).
Proof.
induction sub; allsimpl; auto.
pose proof (eqvars_allvars_sk (snd a)) as h; rw eqvars_prop in h.
rw eqvars_prop in IHsub.
rw eqvars_prop; introv; split; intro i; allrw in_app_iff.
- dorn i.
+ apply h in i; allrw in_app_iff; sp.
+ apply IHsub in i; allrw in_app_iff; sp.
- dorn i; dorn i.
+ left; apply h; allrw in_app_iff; sp.
+ right; apply IHsub; allrw in_app_iff; sp.
+ left; apply h; allrw in_app_iff; sp.
+ right; apply IHsub; allrw in_app_iff; sp.
Qed.
Lemma fo_change_bvars_alpha_spec {o} :
forall vars (t : @SOTerm o),
let t' := fo_change_bvars_alpha vars [] t in
disjoint vars (fo_bound_vars t')
# so_alphaeq t t'.
Proof.
introv; simpl.
pose proof (so_alphaeq_fo_change_bvars_alpha2 t vars) as h1.
pose proof (fo_bound_vars_fo_change_bvars_alpha t vars []) as h2; sp.
Qed.
Ltac fo_change s :=
match goal with
| [ |- context[fo_change_bvars_alpha ?vs [] ?t] ] =>
let h := fresh "h" in
pose proof (fo_change_bvars_alpha_spec vs t) as h;
simpl in h;
remember (fo_change_bvars_alpha vs [] t) as s;
clear_eq s (fo_change_bvars_alpha vs [] t);
repnd
end.
Lemma unfold_sosub {o} :
forall (sub : @SOSub o) t,
{sub' : SOSub
& {t' : SOTerm
& alphaeq_sosub sub sub'
# so_alphaeq t t'
# disjoint (fo_bound_vars t') (free_vars_sosub sub')
# disjoint (free_vars_sosub sub') (bound_vars_sosub sub')
# disjoint (all_fo_vars t') (bound_vars_sosub sub')
# sosub sub t = sosub_aux sub' t'}}.
Proof.
introv.
unfold sosub; boolvar.
- allrw disjoint_app_l; repnd.
exists sub t; dands; auto.
apply alphaeq_sosub_refl.
- sosub_change sub'.
applydup @alphaeq_sosub_preserves_free_vars in h as eqfv.
pose proof (eqvars_allvars_range_sosub sub) as eqv.
allrw disjoint_app_l; repnd.
exists sub' t; dands; auto.
* rw <- eqfv; auto.
* rw <- eqfv.
eapply subvars_disjoint_l;[|exact h1].
eapply subvars_eqvars_r;[|apply eqvars_sym;exact eqv].
apply subvars_app_weak_l; auto.
- fo_change t'.
allrw disjoint_app_l; repnd.
exists sub t'; dands; eauto with slow.
- sosub_change sub'.
fo_change t'.
allrw disjoint_app_l; repnd.
applydup @alphaeq_sosub_preserves_free_vars in h as eqfv.
pose proof (eqvars_allvars_range_sosub sub) as eqv.
exists sub' t'; dands; eauto with slow.
* rw <- eqfv; eauto with slow.
* rw <- eqfv.
eapply subvars_disjoint_l;[|exact h3].
eapply subvars_eqvars_r;[|apply eqvars_sym;exact eqv].
apply subvars_app_weak_l; auto.
Qed.
Lemma eq_sodoms_implies_eq_so_doms {o} :
forall (sub1 sub2 : @SOSub o),
sodom sub1 = sodom sub2 -> so_dom sub1 = so_dom sub2.
Proof.
induction sub1; destruct sub2; introv e; allsimpl; tcsp.
destruct a; destruct p; destruct s; destruct s0; cpx; allsimpl.
f_equal.
apply IHsub1; auto.
Qed.
Lemma sosub_aux_alpha_congr2 {p} :
forall (t1 t2 : @SOTerm p) (sub1 sub2 : @SOSub p),
so_alphaeq t1 t2
-> disjoint (free_vars_sosub sub1) (fo_bound_vars t1)
-> disjoint (free_vars_sosub sub2) (fo_bound_vars t2)
-> disjoint (bound_vars_sosub sub1) (free_vars_sosub sub1 ++ fovars t1)
-> disjoint (bound_vars_sosub sub2) (free_vars_sosub sub2 ++ fovars t2)
-> cover_so_vars t1 sub1
-> cover_so_vars t2 sub2
-> alphaeq_sosub sub1 sub2
-> alphaeq (sosub_aux sub1 t1) (sosub_aux sub2 t2).
Proof.
introv aeqt disj1 disj2 disj3 disj4 cov1 cov2 aeqs.
pose proof (sosub_aux_alpha_congr
t1 t2
(so_dom sub1)
(so_range sub1) (so_range sub2)) as h; simpl in h.
allrw @length_so_dom.
allrw @length_so_range.
allrw <- @sosub_as_combine.
applydup @alphaeq_sosub_implies_eq_sodoms in aeqs as ed1.
applydup @eq_sodoms_implies_eq_so_doms in ed1 as ed2.
rw ed2 in h.
allrw <- @sosub_as_combine.
repeat (autodimp h hyp).
- apply alphaeq_sosub_implies_eq_lengths; auto.
- apply alphaeq_sosub_implies_alphaeq_sk; auto.
Qed.
Lemma so_alphaeq_sym {o} :
forall (t1 t2 : @SOTerm o),
so_alphaeq t1 t2 -> so_alphaeq t2 t1.
Proof.
introv aeq.
apply so_alphaeq_vs_sym; auto.
Qed.
Hint Resolve so_alphaeq_sym : slow.
Hint Resolve so_alphaeq_trans : slow.
Hint Resolve so_alphaeq_refl : slow.
Lemma cover_so_vars_if_alphaeq_sosub {o} :
forall (t : @SOTerm o) sub1 sub2,
cover_so_vars t sub1
-> alphaeq_sosub sub1 sub2
-> cover_so_vars t sub2.
Proof.
introv cov aeq.
allunfold @cover_so_vars.
apply alphaeq_sosub_implies_eq_sodoms in aeq; rw <- aeq; auto.
Qed.
Hint Resolve cover_so_vars_if_alphaeq_sosub : slow.
Fixpoint swap_fo_vars (s : swapping) (vs : list sovar_sig) :=
match vs with
| [] => []
| (v,0) :: vs => (swapvar s v,0) :: swap_fo_vars s vs
| (v,n) :: vs => (v,n) :: swap_fo_vars s vs
end.
Lemma swap_fo_vars_app :
forall (l1 l2 : list sovar_sig) s,
swap_fo_vars s (l1 ++ l2)
= swap_fo_vars s l1 ++ swap_fo_vars s l2.
Proof.
induction l1; introv; allsimpl; auto.
destruct a; destruct n0; simpl; rw IHl1; auto.
Qed.
Lemma swap_fo_vars_flat_map :
forall {A} (l : list A) (f : A -> list sovar_sig) s,
swap_fo_vars s (flat_map f l) = flat_map (fun a => swap_fo_vars s (f a)) l.
Proof.
induction l; introv; allsimpl; auto.
rw swap_fo_vars_app; rw IHl; auto.
Qed.
Lemma swap_fo_vars_implies_remove_fo_vars :
forall vs1 vs2 vs l1 l2,
no_repeats vs
-> disjoint vs vs1
-> disjoint vs vs2
-> disjoint vs (sovars2vars l1)
-> disjoint vs (sovars2vars l2)
-> length vs1 = length vs
-> length vs2 = length vs
-> swap_fo_vars (mk_swapping vs1 vs) l1 = swap_fo_vars (mk_swapping vs2 vs) l2
-> remove_so_vars (vars2sovars vs1) l1 = remove_so_vars (vars2sovars vs2) l2.
Proof.
induction l1; destruct l2;
introv norep disj1 disj2 disj3 disj4 len1 len2 e;
allsimpl; auto;
allrw remove_so_vars_nil_r; allrw remove_so_vars_cons_r; auto.
- destruct s; destruct n0; cpx.
- destruct a; destruct n0; cpx.
- allrw disjoint_cons_r; repnd.
destruct a, s.
destruct n0, n2.
inversion e as [e1].
allsimpl; boolvar; auto.
+ provefalse.
allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx.
pose proof (swapvar_in vs1 vs a) as h;
repeat (autodimp h hyp);
try (complete (apply disjoint_sym; auto)).
assert (LIn (swapvar (mk_swapping vs2 vs) n1) vs) as k by (allrw <-; auto).
pose proof (swapvar_implies2 vs2 vs n1) as x; simpl in x; dorn x;[|dorn x]; tcsp.
* rw x in k; sp.
* destruct n0; eexists; eauto.
+ provefalse.
allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx.
pose proof (swapvar_in vs2 vs a) as h;
repeat (autodimp h hyp);
try (complete (apply disjoint_sym; auto)).
assert (LIn (swapvar (mk_swapping vs1 vs) n) vs) as k by (allrw; auto).
pose proof (swapvar_implies2 vs1 vs n) as x; simpl in x; dorn x;[|dorn x]; tcsp.
* rw x in k; sp.
* destruct n0; eexists; eauto.
+ rw (IHl1 l2); auto; f_equal; f_equal.
allrw in_map_iff; allunfold var2sovar.
rw swapvar_not_in in e1; auto;[|introv k; destruct n0; eexists; complete eauto].
rw swapvar_not_in in e1; auto.
introv k; destruct n2; eexists; complete eauto.
+ boolvar; allsimpl; cpx.
+ boolvar; allsimpl; cpx.
+ boolvar; allsimpl; cpx.
* provefalse.
allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx.
* provefalse.
allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx.
* f_equal; auto.
Qed.
Lemma so_free_vars_so_swap {o} :
forall vs1 vs2 (t : @SOTerm o),
no_repeats vs2
-> disjoint vs1 vs2
-> so_free_vars (so_swap (mk_swapping vs1 vs2) t)
= swap_fo_vars (mk_swapping vs1 vs2) (so_free_vars t).
Proof.
soterm_ind t as [v ts ind|op bs ind] Case; introv norep disj; allsimpl.
- Case "sovar".
boolvar; subst; allsimpl; auto.
rw <- length0 in n.
remember (length ts) as l; destruct l; cpx.
rw map_length; f_equal; auto.
rw flat_map_map; unfold compose.
rw @swap_fo_vars_flat_map.
apply eq_flat_maps; introv i.
apply ind; auto.
- Case "soterm".
rw flat_map_map; unfold compose.
rw @swap_fo_vars_flat_map.
apply eq_flat_maps; introv i; destruct x; simpl.
rw (ind s l); auto.
remember (so_free_vars s) as vars; clear Heqvars.
induction vars; simpl; auto.
+ allrw remove_so_vars_nil_r; simpl; auto.
+ destruct a; destruct n0; simpl.
* allrw remove_so_vars_cons_r; simpl.
boolvar; allrw in_map_iff; exrepnd; cpx; allsimpl; auto.
{ unfold var2sovar in l1; cpx.
allrw in_swapbvars; exrepnd.
apply swapvars_eq in l1; auto; subst.
provefalse.
destruct n0; eexists; eauto. }
{ allunfold var2sovar; cpx.
provefalse.
destruct n0.
eexists; dands; eauto.
rw in_swapbvars; eexists; eauto. }
{ rw IHvars; auto. }
* allrw remove_so_vars_cons_r; simpl; boolvar; simpl; auto.
{ allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx. }
{ allrw in_map_iff; exrepnd.
allunfold var2sovar; cpx. }
{ rw IHvars; auto. }
Qed.
Lemma so_alphaeq_preserves_free_vars {o} :
forall (t1 t2 : @SOTerm o),
so_alphaeq t1 t2
-> so_free_vars t1 = so_free_vars t2.
Proof.
soterm_ind1s t1 as [v1 ts1 ind1|op1 bs1 ind1] Case; introv aeq.
- Case "sovar".
inversion aeq as [? ? ? len imp|]; subst; clear aeq.
simpl; rw len; f_equal.
apply eq_flat_maps_diff; auto.
introv i.
applydup imp in i.
apply ind1 in i0; auto.
apply in_combine in i; sp.
- Case "soterm".
inversion aeq as [|? ? ? len imp]; subst; clear aeq; simpl.
apply eq_flat_maps_diff; auto.
intros b1 b2 i.
applydup imp in i.
destruct b1 as [l1 t1].
destruct b2 as [l2 t2].
simpl.
inversion i0 as [? ? ? ? ? len1 len2 disj norep a]; subst.
applydup in_combine in i; repnd.
apply (ind1 t1 _ l1) in a; auto; allrw @sosize_so_swap; auto.
allsimpl; allrw disjoint_app_r; repnd.
rw @so_free_vars_so_swap in a; eauto with slow.
rw @so_free_vars_so_swap in a; eauto with slow.
apply swap_fo_vars_implies_remove_fo_vars in a; auto.
+ eapply subvars_disjoint_r;[|exact disj2].
apply sovars2vars_so_free_vars_subvars_all_fo_vars.
+ eapply subvars_disjoint_r;[|exact disj].
apply sovars2vars_so_free_vars_subvars_all_fo_vars.
Qed.
Lemma cover_so_vars_if_so_alphaeq {o} :
forall (t1 t2 : @SOTerm o) sub,
cover_so_vars t1 sub
-> so_alphaeq t1 t2
-> cover_so_vars t2 sub.
Proof.
introv cov aeq.
allunfold @cover_so_vars.
apply so_alphaeq_preserves_free_vars in aeq.
rw <- aeq; auto.
Qed.
Hint Resolve cover_so_vars_if_so_alphaeq : slow.
Lemma alphaeq_sosub_combine {o} :
forall vs (sks1 sks2 : list (@sosub_kind o)),
length vs = length sks1
-> length vs = length sks2
-> (alphaeq_sosub (combine vs sks1) (combine vs sks2)
<=> bin_rel_sk alphaeq_sk sks1 sks2).
Proof.
induction vs; destruct sks1, sks2; introv len1 len2; split; intro k;
repnd; dands; allsimpl; tcsp; cpx.
- constructor; simpl; sp.
- inversion k; subst.
apply bin_rel_sk_cons; sp.
apply IHvs; sp.
- allrw @bin_rel_sk_cons; repnd.
constructor; sp.
apply IHvs; sp.
Qed.
Lemma sosub_alpha_congr {p} :
forall (t1 t2 : @SOTerm p) (vs : list NVar) (ts1 ts2 : list sosub_kind),
so_alphaeq t1 t2
-> length vs = length ts1
-> length vs = length ts2
-> cover_so_vars t1 (combine vs ts1)
-> cover_so_vars t2 (combine vs ts2)
-> bin_rel_sk alphaeq_sk ts1 ts2
-> alphaeq (sosub (combine vs ts1) t1) (sosub (combine vs ts2) t2).
Proof.
introv Hal H1l H2l cov1 cov2 Hbr.
pose proof (fovars_subvars_all_fo_vars t1) as sv1.
pose proof (fovars_subvars_all_fo_vars t2) as sv2.
pose proof (unfold_sosub (combine vs ts1) t1) as h1.
pose proof (unfold_sosub (combine vs ts2) t2) as k1.
exrepnd.
rw h1; rw k1.
apply sosub_aux_alpha_congr2; eauto with slow.
- rw disjoint_app_r; dands; eauto with slow.
pose proof (fovars_subvars_all_fo_vars t'0) as h.
eapply subvars_disjoint_r;[exact h|]; eauto with slow.
- rw disjoint_app_r; dands; eauto with slow.
pose proof (fovars_subvars_all_fo_vars t') as h.
eapply subvars_disjoint_r;[exact h|]; eauto with slow.
- eapply alphaeq_sosub_trans;[|exact k0].
eapply alphaeq_sosub_trans;[apply alphaeq_sosub_sym;exact h0|].
apply alphaeq_sosub_combine; auto.
Qed.
Lemma sosub_alpha_congr2 {o} :
forall (t1 t2 : @SOTerm o) (sub1 sub2 : @SOSub o),
so_alphaeq t1 t2
-> alphaeq_sosub sub1 sub2
-> cover_so_vars t1 sub1
-> cover_so_vars t2 sub2
-> alphaeq (sosub sub1 t1) (sosub sub2 t2).
Proof.
introv aeqt aeqs cov1 cov2.
rw (sosub_as_combine sub1).
rw (sosub_as_combine sub2).
applydup @alphaeq_sosub_implies_eq_sodoms in aeqs as ed1.
applydup @eq_sodoms_implies_eq_so_doms in ed1 as ed2.
rw ed2.
apply sosub_alpha_congr; auto.
- rw <- ed2.
rw @length_so_dom; rw @length_so_range; auto.
- rw @length_so_dom; rw @length_so_range; auto.
- rw <- ed2.
rw <- @sosub_as_combine; auto.
- rw <- @sosub_as_combine; auto.
- apply alphaeq_sosub_implies_alphaeq_sk; auto.
Qed.
|
module cam_allocator
(/*AUTOARG*/
// Outputs
res_search_out,
// Inputs
clk, rst, res_search_en, res_search_size, cam_wr_en, cam_wr_addr,
cam_wr_data
);
parameter CU_ID_WIDTH = 6;
parameter NUMBER_CU = 64;
parameter RES_ID_WIDTH = 10;
parameter NUMBER_RES_SLOTS = 1024;
// Search port
input clk,rst;
input res_search_en;
input [RES_ID_WIDTH:0] res_search_size;
output [NUMBER_CU-1:0] res_search_out;
// Write port
input cam_wr_en;
input [CU_ID_WIDTH-1 : 0] cam_wr_addr;
input [RES_ID_WIDTH:0] cam_wr_data;
reg res_search_en_i;
reg [RES_ID_WIDTH:0] res_search_size_i;
// Table to implement the cam
reg [RES_ID_WIDTH:0] cam_ram[NUMBER_CU-1 :0];
reg [NUMBER_CU-1 :0] cam_valid_entry;
wire [NUMBER_CU-1 :0] decoded_output;
genvar i;
generate
for (i=0; i<NUMBER_CU; i=i+1) begin : LOOKUP
assign decoded_output[i] = (!res_search_en_i)? 1'b0 :
(!cam_valid_entry[i]) ? 1'b1 :
(cam_ram[i] >= res_search_size_i)? 1'b1:
1'b0;
end
endgenerate
assign res_search_out = decoded_output;
// Always block for the memory - no reset
always @(posedge clk) begin
if (cam_wr_en) begin
cam_ram[cam_wr_addr] <= cam_wr_data;
end
end
// For datapath - reset
always @(posedge clk or rst) begin
if(rst) begin
cam_valid_entry <= 0;
res_search_en_i <= 0;
res_search_size_i <= 0;
end else begin
res_search_en_i <= res_search_en;
res_search_size_i <= res_search_size;
if (cam_wr_en) begin
cam_valid_entry[cam_wr_addr] <= 1'b1;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:53:54 04/01/2013
// Design Name:
// Module Name: async_fifo
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module async_fifo(
i_push,
i_pop,
i_reset,
i_wclk,
i_rclk,
i_wdata,
o_rdata,
o_full,
o_empty
);
parameter F_WIDTH = 4;
parameter F_SIZE = 1 << F_WIDTH;
parameter F_MAX = 32; // max number of elements we want to store
input i_reset;
input i_rclk;
input i_wclk;
input i_push;
input i_pop;
input [65:0] i_wdata;
output reg [65:0] o_rdata;
output reg o_empty;
output reg o_full;
reg [F_WIDTH-1:0] read_pos;
reg [F_WIDTH-1:0] write_pos;
reg [65:0] memory[F_SIZE -1 : 0];
reg [7:0] total_count; // the number of elements currently in the FIFO
reg [7:0] read_counter;
reg [7:0] write_counter;
// Update empty and full indicators whenever total_count changes
always @(*) begin
total_count = write_counter - read_counter;
o_empty = (total_count == 0);
o_full = (total_count == F_MAX);
end
// Handle writes (push)
always @(posedge i_wclk) begin
if(i_reset) begin
write_counter <= 0;
write_pos <= 0;
end
else if(!o_full && i_push) begin
memory[write_pos] <= i_wdata;
write_pos <= write_pos + 1'b1;
write_counter <= write_counter + 1'b1;
end
end
// Handle reads (pop)
always @(posedge i_rclk) begin
if(i_reset) begin
read_counter <= 0;
read_pos <= 0;
end
else if(!o_empty && i_pop) begin
o_rdata <= memory[read_pos];
read_pos <= read_pos + 1'b1;
read_counter <= read_counter + 1'b1;
end
end
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_tck the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk the_altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_instance_index = 0,
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_ir_width = 2,
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_mfg_id = 110,
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_sim_action = "",
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_sim_n_scan = 0,
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_sim_total_length = 0,
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_type_id = 135,
// altera_mem_if_ddr3_phy_0001_qsys_sequencer_cpu_inst_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: VGA_Audio_PLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.1 Build 178 06/25/2007 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module VGA_Audio_PLL (
areset,
inclk0,
c0,
c1,
c2);
input areset;
input inclk0;
output c0;
output c1;
output c2;
wire [5:0] sub_wire0;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.areset (areset),
.clk (sub_wire0),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b1),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 15,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 14,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 3,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 15,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 14,
altpll_component.clk2_phase_shift = "-9921",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "SOURCE_SYNCHRONOUS",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "6"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "5"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.20000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.20000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-90.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "15"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "14"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "15"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "14"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-9921"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SOURCE_SYNCHRONOUS"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL_bb.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL_waveforms.html FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL_wave*.jpg FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL VGA_Audio_PLL.ppf TRUE FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD2_1_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD2_1_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog wrapper for clkdlyinv5sd2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__clkdlyinv5sd2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd2_1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__clkdlyinv5sd2 base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd2_1 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__clkdlyinv5sd2 base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD2_1_V
|
// Library - static, Cell - th33r, View - schematic
// LAST TIME SAVED: May 23 16:54:28 2014
// NETLIST TIME: May 23 16:54:34 2014
`timescale 1ns / 1ns
module th33r ( y, a, b, c, rsb );
output y;
input a, b, c, rsb;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "th33r";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N6 ( .d(net44), .g(y), .s(net018), .b(cds_globals.gnd_));
nfet_b N5 ( .d(net32), .g(b), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net035), .g(c), .s(net018), .b(cds_globals.gnd_));
nfet_b N15 ( .d(net32), .g(c), .s(net44), .b(cds_globals.gnd_));
nfet_b N10 ( .d(net32), .g(a), .s(net44), .b(cds_globals.gnd_));
nfet_b N16 ( .d(net018), .g(rsb), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N2 ( .d(net038), .g(b), .s(net035), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net32), .g(a), .s(net038), .b(cds_globals.gnd_));
pfet_b P13 ( .b(cds_globals.vdd_), .g(rsb), .s(cds_globals.vdd_),
.d(net32));
pfet_b P12 ( .b(cds_globals.vdd_), .g(c), .s(cds_globals.vdd_),
.d(net036));
pfet_b P5 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net036));
pfet_b P4 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net036));
pfet_b P3 ( .b(cds_globals.vdd_), .g(y), .s(net036), .d(net32));
pfet_b P2 ( .b(cds_globals.vdd_), .g(c), .s(net34), .d(net32));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net32);
endmodule
|
`default_nettype none
module latch_002_gate (dword, vect, sel, st);
output reg [63:0] dword;
input wire [7:0] vect;
input wire [7:0] sel;
input st;
always @*
case (|(st))
1'b 1:
case ((((8)*(sel)))+(0))
0:
dword[7:0] <= vect[7:0];
1:
dword[8:1] <= vect[7:0];
2:
dword[9:2] <= vect[7:0];
3:
dword[10:3] <= vect[7:0];
4:
dword[11:4] <= vect[7:0];
5:
dword[12:5] <= vect[7:0];
6:
dword[13:6] <= vect[7:0];
7:
dword[14:7] <= vect[7:0];
8:
dword[15:8] <= vect[7:0];
9:
dword[16:9] <= vect[7:0];
10:
dword[17:10] <= vect[7:0];
11:
dword[18:11] <= vect[7:0];
12:
dword[19:12] <= vect[7:0];
13:
dword[20:13] <= vect[7:0];
14:
dword[21:14] <= vect[7:0];
15:
dword[22:15] <= vect[7:0];
16:
dword[23:16] <= vect[7:0];
17:
dword[24:17] <= vect[7:0];
18:
dword[25:18] <= vect[7:0];
19:
dword[26:19] <= vect[7:0];
20:
dword[27:20] <= vect[7:0];
21:
dword[28:21] <= vect[7:0];
22:
dword[29:22] <= vect[7:0];
23:
dword[30:23] <= vect[7:0];
24:
dword[31:24] <= vect[7:0];
25:
dword[32:25] <= vect[7:0];
26:
dword[33:26] <= vect[7:0];
27:
dword[34:27] <= vect[7:0];
28:
dword[35:28] <= vect[7:0];
29:
dword[36:29] <= vect[7:0];
30:
dword[37:30] <= vect[7:0];
31:
dword[38:31] <= vect[7:0];
32:
dword[39:32] <= vect[7:0];
33:
dword[40:33] <= vect[7:0];
34:
dword[41:34] <= vect[7:0];
35:
dword[42:35] <= vect[7:0];
36:
dword[43:36] <= vect[7:0];
37:
dword[44:37] <= vect[7:0];
38:
dword[45:38] <= vect[7:0];
39:
dword[46:39] <= vect[7:0];
40:
dword[47:40] <= vect[7:0];
41:
dword[48:41] <= vect[7:0];
42:
dword[49:42] <= vect[7:0];
43:
dword[50:43] <= vect[7:0];
44:
dword[51:44] <= vect[7:0];
45:
dword[52:45] <= vect[7:0];
46:
dword[53:46] <= vect[7:0];
47:
dword[54:47] <= vect[7:0];
48:
dword[55:48] <= vect[7:0];
49:
dword[56:49] <= vect[7:0];
50:
dword[57:50] <= vect[7:0];
51:
dword[58:51] <= vect[7:0];
52:
dword[59:52] <= vect[7:0];
53:
dword[60:53] <= vect[7:0];
54:
dword[61:54] <= vect[7:0];
55:
dword[62:55] <= vect[7:0];
56:
dword[63:56] <= vect[7:0];
57:
dword[63:57] <= vect[7:0];
58:
dword[63:58] <= vect[7:0];
59:
dword[63:59] <= vect[7:0];
60:
dword[63:60] <= vect[7:0];
61:
dword[63:61] <= vect[7:0];
62:
dword[63:62] <= vect[7:0];
63:
dword[63:63] <= vect[7:0];
endcase
endcase
endmodule
|
// This is a component of pluto_servo, a PWM servo driver and quadrature
// counter for emc2
// Copyright 2006 Jeff Epler <[email protected]>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module pluto_servo(clk, led, nConfig, epp_nReset, pport_data, nWrite, nWait, nDataStr,
nAddrStr, dout, din, quadA, quadB, quadZ, up, down);
parameter QW=14;
input clk;
output led, nConfig;
inout [7:0] pport_data;
input nWrite;
output nWait;
input nDataStr, nAddrStr, epp_nReset;
wire do_tristate;
reg[9:0] real_dout; output [9:0] dout = do_tristate ? 10'bZZZZZZZZZZ : real_dout;
input [7:0] din;
input [3:0] quadA;
input [3:0] quadB;
input [3:0] quadZ;
wire[3:0] real_up; output [3:0] up = do_tristate ? 4'bZZZZ : real_up;
wire[3:0] real_down; output [3:0] down = do_tristate ? 4'bZZZZ : real_down;
reg Zpolarity;
wire [2*QW:0] quad0, quad1, quad2, quad3;
wire do_enable_wdt;
wire pwm_at_top;
wdt w(clk, do_enable_wdt, pwm_at_top, do_tristate);
// PWM stuff
// PWM clock is about 20kHz for clk @ 40MHz, 11-bit cnt
reg [10:0] pwmcnt;
wire [10:0] top = 11'd2046;
assign pwm_at_top = (pwmcnt == top);
reg [15:0] pwm0, pwm1, pwm2, pwm3;
always @(posedge clk) begin
if(pwm_at_top) pwmcnt <= 0;
else pwmcnt <= pwmcnt + 11'd1;
end
wire [10:0] pwmrev = {
pwmcnt[4], pwmcnt[5], pwmcnt[6], pwmcnt[7], pwmcnt[8], pwmcnt[9],
pwmcnt[10], pwmcnt[3:0]};
wire [10:0] pwmcmp0 = pwm0[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp1 = pwm1[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp2 = pwm2[14] ? pwmrev : pwmcnt;
// wire [10:0] pwmcmp3 = pwm3[14] ? pwmrev : pwmcnt;
wire pwmact0 = pwm0[10:0] > pwmcmp0;
wire pwmact1 = pwm1[10:0] > pwmcmp0;
wire pwmact2 = pwm2[10:0] > pwmcmp0;
wire pwmact3 = pwm3[10:0] > pwmcmp0;
assign real_up[0] = pwm0[12] ^ (pwm0[15] ? 1'd0 : pwmact0);
assign real_up[1] = pwm1[12] ^ (pwm1[15] ? 1'd0 : pwmact1);
assign real_up[2] = pwm2[12] ^ (pwm2[15] ? 1'd0 : pwmact2);
assign real_up[3] = pwm3[12] ^ (pwm3[15] ? 1'd0 : pwmact3);
assign real_down[0] = pwm0[13] ^ (~pwm0[15] ? 1'd0 : pwmact0);
assign real_down[1] = pwm1[13] ^ (~pwm1[15] ? 1'd0 : pwmact1);
assign real_down[2] = pwm2[13] ^ (~pwm2[15] ? 1'd0 : pwmact2);
assign real_down[3] = pwm3[13] ^ (~pwm3[15] ? 1'd0 : pwmact3);
// Quadrature stuff
// Quadrature is digitized at 40MHz into 14-bit counters
// Read up to 2^13 pulses / polling period = 8MHz for 1kHz servo period
reg qtest;
wire qr0, qr1, qr2, qr3;
quad q0(clk, qtest ? real_dout[0] : quadA[0], qtest ? real_dout[1] : quadB[0], qtest ? real_dout[2] : quadZ[0]^Zpolarity, qr0, quad0);
quad q1(clk, quadA[1], quadB[1], quadZ[1]^Zpolarity, qr1, quad1);
quad q2(clk, quadA[2], quadB[2], quadZ[2]^Zpolarity, qr2, quad2);
quad q3(clk, quadA[3], quadB[3], quadZ[3]^Zpolarity, qr3, quad3);
// EPP stuff
wire EPP_write = ~nWrite;
wire EPP_read = nWrite;
wire EPP_addr_strobe = ~nAddrStr;
wire EPP_data_strobe = ~nDataStr;
wire EPP_strobe = EPP_data_strobe | EPP_addr_strobe;
wire EPP_wait; assign nWait = ~EPP_wait;
wire [7:0] EPP_datain = pport_data;
wire [7:0] EPP_dataout; assign pport_data = EPP_dataout;
reg [4:0] EPP_strobe_reg;
always @(posedge clk) EPP_strobe_reg <= {EPP_strobe_reg[3:0], EPP_strobe};
wire EPP_strobe_edge1 = (EPP_strobe_reg[2:1]==2'b01);
// reg led;
assign EPP_wait = EPP_strobe_reg[4];
reg[4:0] addr_reg;
reg[7:0] lowbyte;
always @(posedge clk)
if(EPP_strobe_edge1 & EPP_write & EPP_addr_strobe) begin
addr_reg <= EPP_datain[4:0];
end
else if(EPP_strobe_edge1 & !EPP_addr_strobe) addr_reg <= addr_reg + 4'd1;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_write & EPP_data_strobe) begin
if(addr_reg[3:0] == 4'd1) pwm0 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd3) pwm1 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd5) pwm2 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd7) pwm3 <= { EPP_datain, lowbyte };
else if(addr_reg[3:0] == 4'd9) begin
real_dout <= { EPP_datain[1:0], lowbyte };
Zpolarity <= EPP_datain[7];
qtest <= EPP_datain[5];
end
else lowbyte <= EPP_datain;
end
end
reg [31:0] data_buf;
always @(posedge clk) begin
if(EPP_strobe_edge1 & EPP_read && addr_reg[1:0] == 2'd0) begin
if(addr_reg[4:2] == 3'd0) data_buf <= quad0;
else if(addr_reg[4:2] == 3'd1) data_buf <= quad1;
else if(addr_reg[4:2] == 3'd2) data_buf <= quad2;
else if(addr_reg[4:2] == 3'd3) data_buf <= quad3;
else if(addr_reg[4:2] == 3'd4)
data_buf <= {quadA, quadB, quadZ, din};
end
end
// the addr_reg test looks funny because it is auto-incremented in an always
// block so "1" reads the low byte, "2 and "3" read middle bytes, and "0"
// reads the high byte I have a feeling that I'm doing this in the wrong way.
wire [7:0] data_reg = addr_reg[1:0] == 2'd1 ? data_buf[7:0] :
(addr_reg[1:0] == 2'd2 ? data_buf[15:8] :
(addr_reg[1:0] == 2'd3 ? data_buf[23:16] :
data_buf[31:24]));
wire [7:0] EPP_data_mux = data_reg;
assign EPP_dataout = (EPP_read & EPP_wait) ? EPP_data_mux : 8'hZZ;
assign do_enable_wdt = EPP_strobe_edge1 & EPP_write & EPP_data_strobe & (addr_reg[3:0] == 4'd9) & EPP_datain[6];
assign qr0 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd0);
assign qr1 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd1);
assign qr2 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd2);
assign qr3 = EPP_strobe_edge1 & EPP_read & EPP_data_strobe & (addr_reg[4:2] == 3'd3);
assign led = do_tristate ? 1'BZ : (real_up[0] ^ real_down[0]);
assign nConfig = epp_nReset; // 1'b1;
endmodule
|
/*
Copyright 2010 David Fritz, Brian Gordon, Wira Mulia
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
David Fritz
timer module
a simple 32-bit timer. Timer increments on every edge.
*/
module mod_timer(rst, clk, ie, de, iaddr, daddr, drw, din, iout, dout, int);
input rst;
input clk;
input ie,de;
input [31:0] iaddr, daddr;
input [1:0] drw;
input [31:0] din;
output [31:0] iout, dout;
output int;
/* by spec, the iout and dout signals must go hiZ when we're not using them */
wire [31:0] idata, ddata;
assign iout = idata;
assign dout = ddata;
reg [31:0] timer;
assign int = timer == 32'hffffffff;
assign ddata = timer;
/* all data bus activity is negative edge triggered */
always @(negedge clk) begin
timer = timer + 1;
if (drw[0] && de && !rst) timer = din;
else if (rst) timer = 0;
end
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 12:17:59 11/12/2009
// Design Name:
// Module Name: performance_counter
// Project Name: Sora
// Target Devices: LX50T1136-1
// Tool versions: ISE 10.02
// Description: We measure the durations in this module (1) from TX_des request sent to tx_engine to new des
// received (2) from transfer start to transfer done.
// A counter (125MHz or 250MHz depends on DMA clock) is implemeted.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module performance_counter(
input clk,
input rst,
input transferstart_one,
input rd_dma_done_one,
input new_des_one,
output reg [23:0] round_trip_latency,
output reg [23:0] transfer_duration
);
reg [39:0] counter; /// free run 40bits counter, more than two hours per cycle on 125MHz clock
reg [23:0] snapshot_transferstart; /// record the lower 24 bit of counter when transferstart, more than 100ms per cycle on 125MHz clock
/// counter
always@(posedge clk) begin
if(rst)
counter <= 40'h00_0000_0000;
else
counter <= counter + 40'h00_0000_0001;
end
/// snapshot_transferstart
always@(posedge clk) begin
if(rst)
snapshot_transferstart <= 24'h00_0000;
else if (transferstart_one)
snapshot_transferstart <= counter[23:0];
else
snapshot_transferstart <= snapshot_transferstart;
end
/// round_trip_latency
always@(posedge clk) begin
if (rst)
round_trip_latency <= 24'h00_0000;
else if (new_des_one)
round_trip_latency <= counter[23:0] + (~snapshot_transferstart) + 24'h00_0001;
else
round_trip_latency <= round_trip_latency;
end
/// transfer_duration
always@(posedge clk) begin
if (rst)
transfer_duration <= 24'h00_0000;
else if (rd_dma_done_one)
transfer_duration <= counter[23:0] + (~snapshot_transferstart) + 24'h00_0001;
else
transfer_duration <= transfer_duration;
end
endmodule
|
//
// usb 3.0 protocol layer
//
// Copyright (c) 2013 Marshall H.
// All rights reserved.
// This code is released under the terms of the simplified BSD license.
// See LICENSE.TXT for details.
//
module usb3_protocol (
input wire slow_clk,
input wire local_clk,
input wire ext_clk,
input wire reset_n,
input wire [4:0] ltssm_state,
// link interface
input wire rx_tp,
input wire rx_tp_hosterr,
input wire rx_tp_retry,
input wire rx_tp_pktpend,
input wire [3:0] rx_tp_subtype,
input wire [3:0] rx_tp_endp,
input wire [4:0] rx_tp_nump,
input wire [4:0] rx_tp_seq,
input wire [15:0] rx_tp_stream,
input wire rx_dph,
input wire rx_dph_eob,
input wire rx_dph_setup,
input wire rx_dph_pktpend,
input wire [3:0] rx_dph_endp,
input wire [4:0] rx_dph_seq,
input wire [15:0] rx_dph_len,
input wire rx_dpp_start,
input wire rx_dpp_done,
input wire rx_dpp_crcgood,
output reg tx_tp_a,
output reg tx_tp_a_retry,
output reg tx_tp_a_dir,
output reg [3:0] tx_tp_a_subtype,
output reg [3:0] tx_tp_a_endp,
output reg [4:0] tx_tp_a_nump,
output reg [4:0] tx_tp_a_seq,
output reg [15:0] tx_tp_a_stream,
input wire tx_tp_a_ack,
output reg tx_tp_b,
output reg tx_tp_b_retry,
output reg tx_tp_b_dir,
output reg [3:0] tx_tp_b_subtype,
output reg [3:0] tx_tp_b_endp,
output reg [4:0] tx_tp_b_nump,
output reg [4:0] tx_tp_b_seq,
output reg [15:0] tx_tp_b_stream,
input wire tx_tp_b_ack,
output reg tx_tp_c,
output reg tx_tp_c_retry,
output reg tx_tp_c_dir,
output reg [3:0] tx_tp_c_subtype,
output reg [3:0] tx_tp_c_endp,
output reg [4:0] tx_tp_c_nump,
output reg [4:0] tx_tp_c_seq,
output reg [15:0] tx_tp_c_stream,
input wire tx_tp_c_ack,
output reg tx_dph,
output reg tx_dph_eob,
output reg tx_dph_dir,
output reg [3:0] tx_dph_endp,
output reg [4:0] tx_dph_seq,
output reg [15:0] tx_dph_len,
input wire tx_dpp_ack,
input wire tx_dpp_done,
input wire [8:0] buf_in_addr,
input wire [31:0] buf_in_data,
input wire buf_in_wren,
output wire buf_in_ready,
input wire buf_in_commit,
input wire [10:0] buf_in_commit_len,
output wire buf_in_commit_ack,
input wire [8:0] buf_out_addr,
output wire [31:0] buf_out_q,
output wire [10:0] buf_out_len,
output wire buf_out_hasdata,
input wire buf_out_arm,
output wire buf_out_arm_ack,
// external interface
input wire [8:0] ext_buf_in_addr,
input wire [31:0] ext_buf_in_data,
input wire ext_buf_in_wren,
output reg ext_buf_in_request,
output wire ext_buf_in_ready,
input wire ext_buf_in_commit,
input wire [10:0] ext_buf_in_commit_len,
output wire ext_buf_in_commit_ack,
input wire [8:0] ext_buf_out_addr,
output wire [31:0] ext_buf_out_q,
output wire [10:0] ext_buf_out_len,
output wire ext_buf_out_hasdata,
input wire ext_buf_out_arm,
output wire ext_buf_out_arm_ack,
output wire [1:0] endp_mode_rx,
output wire [1:0] endp_mode_tx,
output wire vend_req_act,
output wire [7:0] vend_req_request,
output wire [15:0] vend_req_val,
output wire [6:0] dev_addr,
output wire configured,
output reg err_miss_rx,
output reg err_miss_tx,
output reg err_tp_subtype,
output reg err_missed_dpp_start,
output reg err_missed_dpp_done
);
`include "usb3_const.v"
// mux bram signals
wire [8:0] ep0_buf_in_addr = rx_endp == SEL_ENDP0 ? buf_in_addr : 'h0;
wire [31:0] ep0_buf_in_data = rx_endp == SEL_ENDP0 ? buf_in_data : 'h0;
wire ep0_buf_in_wren = rx_endp == SEL_ENDP0 ? buf_in_wren : 'h0;
wire ep0_buf_in_ready;
wire ep0_buf_in_commit = rx_endp == SEL_ENDP0 ? buf_in_commit : 'h0;
wire [10:0] ep0_buf_in_commit_len = rx_endp == SEL_ENDP0 ? buf_in_commit_len : 'h0;
wire ep0_buf_in_commit_ack;
wire [8:0] ep0_buf_out_addr = tx_endp == SEL_ENDP0 ? buf_out_addr : 'h0;
wire [31:0] ep0_buf_out_q;
wire [10:0] ep0_buf_out_len;
wire ep0_buf_out_hasdata;
wire ep0_buf_out_arm = tx_endp == SEL_ENDP0 ? buf_out_arm : 'h0;
wire ep0_buf_out_arm_ack;
wire [8:0] ep1_buf_out_addr = tx_endp == SEL_ENDP1 ? buf_out_addr : 'h0;
wire [31:0] ep1_buf_out_q;
wire [10:0] ep1_buf_out_len;
wire ep1_buf_out_hasdata;
wire ep1_buf_out_arm = tx_endp == SEL_ENDP1 ? buf_out_arm : 'h0;
wire ep1_buf_out_arm_ack;
wire [8:0] ep2_buf_in_addr = rx_endp == SEL_ENDP2 ? buf_in_addr : 'h0;
wire [31:0] ep2_buf_in_data = rx_endp == SEL_ENDP2 ? buf_in_data : 'h0;
wire ep2_buf_in_wren = rx_endp == SEL_ENDP2 ? buf_in_wren : 'h0;
wire ep2_buf_in_ready;
wire ep2_buf_in_commit = rx_endp == SEL_ENDP2 ? buf_in_commit : 'h0;
wire [10:0] ep2_buf_in_commit_len = rx_endp == SEL_ENDP2 ? buf_in_commit_len : 'h0;
wire ep2_buf_in_commit_ack;
assign buf_in_ready = rx_endp == SEL_ENDP0 ? ep0_buf_in_ready :
rx_endp == SEL_ENDP2 ? ep2_buf_in_ready : 'h0;
assign buf_in_commit_ack = rx_endp == SEL_ENDP0 ? ep0_buf_in_commit_ack :
rx_endp == SEL_ENDP2 ? ep2_buf_in_commit_ack : 'h0;
assign buf_out_q = tx_endp == SEL_ENDP0 ? ep0_buf_out_q :
tx_endp == SEL_ENDP1 ? ep1_buf_out_q : 'h0;
assign buf_out_len = tx_endp == SEL_ENDP0 ? ep0_buf_out_len :
tx_endp == SEL_ENDP1 ? ep1_buf_out_len : 'h0;
assign buf_out_hasdata = tx_endp == SEL_ENDP0 ? ep0_buf_out_hasdata :
tx_endp == SEL_ENDP1 ? ep1_buf_out_hasdata : 'h0;
assign buf_out_arm_ack = tx_endp == SEL_ENDP0 ? ep0_buf_out_arm_ack :
tx_endp == SEL_ENDP1 ? ep1_buf_out_arm_ack : 'h0;
assign endp_mode_tx = tx_endp == SEL_ENDP1 ? EP1_MODE :
tx_endp == SEL_ENDP2 ? EP2_MODE : EP_MODE_CONTROL;
assign endp_mode_rx = rx_endp == SEL_ENDP1 ? EP1_MODE :
rx_endp == SEL_ENDP2 ? EP2_MODE : EP_MODE_CONTROL;
parameter [3:0] SEL_ENDP0 = 4'd0,
SEL_ENDP1 = 4'd1,
SEL_ENDP2 = 4'd2,
SEL_ENDP3 = 4'd3,
SEL_ENDP4 = 4'd4,
SEL_ENDP5 = 4'd5,
SEL_ENDP6 = 4'd6,
SEL_ENDP7 = 4'd7;
parameter [1:0] EP_MODE_CONTROL = 2'd0,
EP_MODE_ISOCH = 2'd1,
EP_MODE_BULK = 2'd2,
EP_MODE_INTERRUPT = 2'd3;
// assign endpoint modes here and also
// in the descriptor strings
wire [1:0] EP1_MODE = EP_MODE_BULK;
wire [1:0] EP2_MODE = EP_MODE_BULK;
reg [4:0] rx_state;
parameter [4:0] RX_RESET = 'd0,
RX_IDLE = 'd1,
RX_0 = 'd2,
RX_1 = 'd3,
RX_2 = 'd4,
RX_TP_0 = 'd10,
RX_TP_1 = 'd11,
RX_TP_2 = 'd12,
RX_DPH_0 = 'd20,
RX_DPH_1 = 'd21,
RX_DPH_2 = 'd22;
reg [4:0] tx_state;
parameter [4:0] TX_RESET = 'd0,
TX_IDLE = 'd1,
TX_DP_WAITDATA = 'd2,
TX_DP_0 = 'd3,
TX_DP_1 = 'd4,
TX_DP_2 = 'd5,
TX_DP_3 = 'd6,
TX_DP_NRDY = 'd7,
TX_DP_ERDY = 'd8;
reg [4:0] in_dpp_seq /* synthesis noprune */;
reg [4:0] out_dpp_seq /* synthesis noprune */;
wire reset_dp_seq;
reg [15:0] out_length;
reg [4:0] out_nump;
reg do_send_dpp;
reg [10:0] recv_count;
reg [10:0] dc;
reg [3:0] rx_endp;
reg [3:0] tx_endp;
always @(posedge local_clk) begin
tx_tp_a <= 0;
tx_tp_b <= 0;
tx_tp_c <= 0;
tx_dph <= 0;
do_send_dpp <= 0;
ext_buf_in_request <= 0;
`INC(dc);
`INC(recv_count);
case(rx_state)
RX_RESET: rx_state <= RX_IDLE;
RX_IDLE: begin
if(rx_dph) begin
// receiving data packet header, link layer is stuffing payload
// into the endpoint buffer
in_dpp_seq <= rx_dph_seq;
rx_endp <= rx_dph_endp;
rx_state <= RX_DPH_0;
recv_count <= 0;
end else
if(rx_tp) begin
// receving transaction packet, could be ACK or something else
rx_state <= RX_TP_0;
end
end
RX_DPH_0: begin
if(rx_dpp_start) begin
// received DPP start ordered set
rx_state <= RX_DPH_1;
end
if(ltssm_state != LT_U0 || recv_count == 20) begin
// we waited too long for DPP start and it hasn't come yet
err_missed_dpp_start <= 1;
rx_state <= RX_DPH_2;
end
end
RX_DPH_1: begin
if(rx_dpp_done) begin
if(rx_dpp_crcgood) `INC(in_dpp_seq);
err_missed_dpp_start <= 0;
err_missed_dpp_done <= 0;
rx_state <= RX_DPH_2;
end
if(ltssm_state != LT_U0 || recv_count == 270) begin
err_missed_dpp_done <= 1;
rx_state <= RX_DPH_2;
end
end
RX_DPH_2: begin
// send ACK
tx_tp_a <= 1'b1;
tx_tp_a_retry <= ( rx_dpp_crcgood &&
!err_missed_dpp_start &&
!err_missed_dpp_done
) ? LP_TP_NORETRY : LP_TP_RETRY;
tx_tp_a_dir <= LP_TP_HOSTTODEVICE;
tx_tp_a_subtype <= LP_TP_SUB_ACK;
tx_tp_a_endp <= rx_dph_endp;
tx_tp_a_nump <= 5'h1;
tx_tp_a_seq <= in_dpp_seq;
tx_tp_a_stream <= 16'h0;
if(tx_tp_a_ack) rx_state <= RX_IDLE;
end
RX_TP_0: begin
// unless otherwise directed, immediately return
rx_state <= RX_IDLE;
case(rx_tp_subtype)
LP_TP_SUB_ACK: begin
if(rx_tp_pktpend && rx_tp_nump > 0) begin
// IN, expecting us to send data
// switch endpoint mux
tx_endp <= rx_tp_endp;
out_nump <= rx_tp_nump;
out_dpp_seq <= rx_tp_seq;
do_send_dpp <= 1;
end else begin
// ACK from a previously sent packet
end
end
LP_TP_SUB_NRDY: begin
end
LP_TP_SUB_ERDY: begin
end
LP_TP_SUB_STATUS: begin
// for control transfers
tx_tp_b <= 1'b1;
tx_tp_b_retry <= LP_TP_NORETRY;
tx_tp_b_dir <= LP_TP_HOSTTODEVICE;
tx_tp_b_subtype <= LP_TP_SUB_ACK;
tx_tp_b_endp <= rx_tp_endp;
tx_tp_b_nump <= 5'h0;
tx_tp_b_seq <= in_dpp_seq;
tx_tp_b_stream <= 16'h0;
if(!tx_tp_b_ack) rx_state <= rx_state;
end
LP_TP_SUB_PING: begin
end
default: begin
// invalid subtype
err_tp_subtype <= 1;
end
endcase
end
RX_0: begin
end
RX_1: begin
end
endcase
case(tx_state)
TX_RESET: tx_state <= TX_IDLE;
TX_IDLE: begin
if(do_send_dpp) begin
// if you had multiple IN endpoints you would rewrite this part
if(tx_endp == SEL_ENDP1) ext_buf_in_request <= 1;
if(buf_out_hasdata) begin
// data is already in EP buffer
// note: overall transfer length
out_length <= buf_out_len;
tx_state <= TX_DP_0;
end else begin
// no data is ready yet, send NRDY and wait
tx_state <= TX_DP_NRDY;
end
end
end
TX_DP_NRDY: begin
tx_tp_c <= 1'b1;
tx_tp_c_retry <= LP_TP_NORETRY;
tx_tp_c_dir <= LP_TP_HOSTTODEVICE;
tx_tp_c_subtype <= LP_TP_SUB_NRDY;
tx_tp_c_endp <= tx_endp;
tx_tp_c_nump <= 5'h0;
tx_tp_c_seq <= 5'h0;
tx_tp_c_stream <= 16'h0;
if(tx_tp_c_ack) tx_state <= TX_DP_WAITDATA;
end
TX_DP_WAITDATA: begin
if(tx_endp == SEL_ENDP1) ext_buf_in_request <= 1;
if(buf_out_hasdata) begin
// data is already in EP buffer
// note: overall transfer length
out_length <= buf_out_len;
tx_state <= TX_DP_ERDY;
end
end
TX_DP_ERDY: begin
tx_tp_c <= 1'b1;
tx_tp_c_retry <= LP_TP_NORETRY;
tx_tp_c_dir <= LP_TP_HOSTTODEVICE;
tx_tp_c_subtype <= LP_TP_SUB_ERDY;
tx_tp_c_endp <= tx_endp;
tx_tp_c_nump <= 5'h1;
tx_tp_c_seq <= 5'h0;
tx_tp_c_stream <= 16'h0;
if(tx_tp_c_ack) tx_state <= TX_DP_0;
end
TX_DP_0: begin
tx_dph <= 1'b1;
tx_dph_eob <= 0; // TODO
tx_dph_dir <= tx_endp == 0 ? 0 : LP_TP_DEVICETOHOST; // rx_tp_endp
tx_dph_endp <= tx_endp;
tx_dph_seq <= out_dpp_seq;
tx_dph_len <= out_length; // TODO
dc <= 0;
if(tx_dpp_ack) tx_state <= TX_DP_1;
end
TX_DP_1: begin
if(tx_dpp_done) tx_state <= TX_IDLE;
end
endcase
if(rx_state != RX_IDLE) begin
// missed an incoming transaction!
if(rx_dph || rx_tp) err_miss_rx <= 1;
end
if(tx_state != TX_IDLE) begin
if(do_send_dpp) err_miss_tx <= 1;
end
if(~reset_n) begin
rx_state <= RX_RESET;
tx_state <= TX_RESET;
end
if(~reset_n) begin
err_miss_rx <= 0;
err_miss_tx <= 0;
err_tp_subtype <= 0;
err_missed_dpp_start <= 0;
err_missed_dpp_done <= 0;
end
end
////////////////////////////////////////////////////////////
//
// ENDPOINT 0 IN/OUT
//
////////////////////////////////////////////////////////////
usb3_ep0 iu3ep0 (
.slow_clk ( slow_clk ),
.local_clk ( local_clk ),
.reset_n ( reset_n ),
.buf_in_addr ( ep0_buf_in_addr ),
.buf_in_data ( ep0_buf_in_data ),
.buf_in_wren ( ep0_buf_in_wren ),
.buf_in_ready ( ep0_buf_in_ready ),
.buf_in_commit ( ep0_buf_in_commit ),
.buf_in_commit_len ( ep0_buf_in_commit_len ),
.buf_in_commit_ack ( ep0_buf_in_commit_ack ),
.buf_out_addr ( ep0_buf_out_addr ),
.buf_out_q ( ep0_buf_out_q ),
.buf_out_len ( ep0_buf_out_len ),
.buf_out_hasdata ( ep0_buf_out_hasdata ),
.buf_out_arm ( ep0_buf_out_arm ),
.buf_out_arm_ack ( ep0_buf_out_arm_ack ),
.vend_req_act ( vend_req_act ),
.vend_req_request ( vend_req_request ),
.vend_req_val ( vend_req_val ),
.dev_addr ( dev_addr ),
.configured ( configured ),
.reset_dp_seq ( reset_dp_seq )
//.err_setup_pkt ( err_setup_pkt )
);
////////////////////////////////////////////////////////////
//
// ENDPOINT 1 IN (DATA TO PC)
//
////////////////////////////////////////////////////////////
usb3_ep iu3ep1 (
.slow_clk ( slow_clk ),
.local_clk ( local_clk ),
.rd_clk ( local_clk ),
.wr_clk ( ext_clk ),
.reset_n ( reset_n ),
.buf_in_addr ( ext_buf_in_addr ),
.buf_in_data ( ext_buf_in_data ),
.buf_in_wren ( ext_buf_in_wren ),
.buf_in_ready ( ext_buf_in_ready ),
.buf_in_commit ( ext_buf_in_commit ),
.buf_in_commit_len ( ext_buf_in_commit_len ),
.buf_in_commit_ack ( ext_buf_in_commit_ack ),
.buf_out_addr ( ep1_buf_out_addr ),
.buf_out_q ( ep1_buf_out_q ),
.buf_out_len ( ep1_buf_out_len ),
.buf_out_hasdata ( ep1_buf_out_hasdata ),
.buf_out_arm ( ep1_buf_out_arm ),
.buf_out_arm_ack ( ep1_buf_out_arm_ack ),
.mode ( EP1_MODE )
);
////////////////////////////////////////////////////////////
//
// ENDPOINT 2 OUT (DATA FROM PC)
//
////////////////////////////////////////////////////////////
usb3_ep iu3ep2 (
.slow_clk ( slow_clk ),
.local_clk ( local_clk ),
.rd_clk ( ext_clk ),
.wr_clk ( local_clk ),
.reset_n ( reset_n ),
.buf_in_addr ( ep2_buf_in_addr ),
.buf_in_data ( ep2_buf_in_data ),
.buf_in_wren ( ep2_buf_in_wren ),
.buf_in_ready ( ep2_buf_in_ready ),
.buf_in_commit ( ep2_buf_in_commit ),
.buf_in_commit_len ( ep2_buf_in_commit_len ),
.buf_in_commit_ack ( ep2_buf_in_commit_ack ),
.buf_out_addr ( ext_buf_out_addr ),
.buf_out_q ( ext_buf_out_q ),
.buf_out_len ( ext_buf_out_len ),
.buf_out_hasdata ( ext_buf_out_hasdata ),
.buf_out_arm ( ext_buf_out_arm ),
.buf_out_arm_ack ( ext_buf_out_arm_ack ),
.mode ( EP2_MODE )
);
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the encoder
// Import the modules that will be tested for in this testbench
`include "encoder.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_arbiter();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [3:0] grant_vector;
// Declare "reg" signals: inputs to the DUT
reg [3:0] req_vector;
reg clk,reset,enable;
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is given in the question
#5 clk = 0;
#5 clk = 1;
end
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
arbiter_LRU4 arb (
// instance_name(signal name),
// Signal name can be the same as the instance name
grant_vector,req_vector,enable,clk,reset);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
reset = 1;
enable = 0;
req_vector = 4'b1010;
// @ t=0,
@(posedge clk);
#1;
reset = 0;
enable = 0;
req_vector = 4'b1110;
@(posedge clk);
#1;
reset = 0;
enable = 1;
req_vector = 4'b1111;
@(posedge clk);
#1;
reset = 0;
enable = 1;
req_vector = 4'b1000;
@(posedge clk);
#1;
reset = 0;
enable = 1;
req_vector = 4'b1011;
@(posedge clk);
#1;
reset = 0;
enable = 1;
req_vector = 4'b0111;
@(posedge clk);
#1;
reset = 0;
enable = 0;
req_vector = 4'b1110;
@(posedge clk);
#1;
reset = 1;
enable = 0;
req_vector = 4'b1011;
@(posedge clk);
#1;
reset = 0;
enable = 1;
req_vector = 4'b1100;
@(posedge clk);
#1;
reset = 0;
enable = 1;
req_vector = 4'b1101;
@(posedge clk);
#1;
reset = 0;
enable = 1;
req_vector = 4'b1010;
@(posedge clk);
#1;
reset = 0;
enable = 1;
req_vector = 4'b1111;
@(posedge clk);
#1;
reset = 0;
enable = 1;
req_vector = 4'b1110;
// Wait for another 20 ns
#20;
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_r_channel.v
//
// Description:
// Read data channel module to buffer read data from MC, ignore
// extra data in case of BL8 and send the data to AXI.
// The MC will send out the read data as it is ready and it has to be
// accepted. The read data FIFO in the axi_protocol_converter_v2_1_b2s_r_channel module will buffer
// the data before being sent to AXI. The address channel module will
// send the transaction information for every command that is sent to the
// MC. The transaction information will be buffered in a transaction FIFO.
// Based on the transaction FIFO information data will be ignored in
// BL8 mode and the last signal to the AXI will be asserted.
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_r_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AXI xDATA and MCB xx_data
// Range: 32, 64, 128.
parameter integer C_DATA_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire [C_ID_WIDTH-1:0] s_rid ,
output wire [C_DATA_WIDTH-1:0] s_rdata ,
output wire [1:0] s_rresp ,
output wire s_rlast ,
output wire s_rvalid ,
input wire s_rready ,
input wire [C_DATA_WIDTH-1:0] m_rdata ,
input wire [1:0] m_rresp ,
input wire m_rvalid ,
output wire m_rready ,
// Connections to/from axi_protocol_converter_v2_1_b2s_ar_channel module
input wire r_push ,
output wire r_full ,
// length not needed. Can be removed.
input wire [C_ID_WIDTH-1:0] r_arid ,
input wire r_rlast
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_WIDTH = 1+C_ID_WIDTH;
localparam P_DEPTH = 32;
localparam P_AWIDTH = 5;
localparam P_D_WIDTH = C_DATA_WIDTH + 2;
// rd data FIFO depth varies based on burst length.
// For Bl8 it is two times the size of transaction FIFO.
// Only in 2:1 mode BL8 transactions will happen which results in
// two beats of read data per read transaction.
localparam P_D_DEPTH = 32;
localparam P_D_AWIDTH = 5;
////////////////////////////////////////////////////////////////////////////////
// Wire and register declarations
////////////////////////////////////////////////////////////////////////////////
wire [C_ID_WIDTH+1-1:0] trans_in;
wire [C_ID_WIDTH+1-1:0] trans_out;
wire tr_empty;
wire rhandshake;
wire r_valid_i;
wire [P_D_WIDTH-1:0] rd_data_fifo_in;
wire [P_D_WIDTH-1:0] rd_data_fifo_out;
wire rd_en;
wire rd_full;
wire rd_empty;
wire rd_a_full;
wire fifo_a_full;
reg [C_ID_WIDTH-1:0] r_arid_r;
reg r_rlast_r;
reg r_push_r;
wire fifo_full;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
assign s_rresp = rd_data_fifo_out[P_D_WIDTH-1:C_DATA_WIDTH];
assign s_rid = trans_out[1+:C_ID_WIDTH];
assign s_rdata = rd_data_fifo_out[C_DATA_WIDTH-1:0];
assign s_rlast = trans_out[0];
assign s_rvalid = ~rd_empty & ~tr_empty;
// assign MCB outputs
assign rd_en = rhandshake & (~rd_empty);
assign rhandshake =(s_rvalid & s_rready);
// register for timing
always @(posedge clk) begin
r_arid_r <= r_arid;
r_rlast_r <= r_rlast;
r_push_r <= r_push;
end
assign trans_in[0] = r_rlast_r;
assign trans_in[1+:C_ID_WIDTH] = r_arid_r;
// rd data fifo
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_D_WIDTH),
.C_AWIDTH (P_D_AWIDTH),
.C_DEPTH (P_D_DEPTH)
)
rd_data_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( m_rvalid & m_rready ) ,
.rd_en ( rd_en ) ,
.din ( rd_data_fifo_in ) ,
.dout ( rd_data_fifo_out ) ,
.a_full ( rd_a_full ) ,
.full ( rd_full ) ,
.a_empty ( ) ,
.empty ( rd_empty )
);
assign rd_data_fifo_in = {m_rresp, m_rdata};
axi_protocol_converter_v2_1_b2s_simple_fifo #(
.C_WIDTH (P_WIDTH),
.C_AWIDTH (P_AWIDTH),
.C_DEPTH (P_DEPTH)
)
transaction_fifo_0
(
.clk ( clk ) ,
.rst ( reset ) ,
.wr_en ( r_push_r ) ,
.rd_en ( rd_en ) ,
.din ( trans_in ) ,
.dout ( trans_out ) ,
.a_full ( fifo_a_full ) ,
.full ( ) ,
.a_empty ( ) ,
.empty ( tr_empty )
);
assign fifo_full = fifo_a_full | rd_a_full ;
assign r_full = fifo_full ;
assign m_rready = ~rd_a_full;
endmodule
`default_nettype wire
|
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_dataid_manager
# (
parameter
CFG_DATA_ID_WIDTH = 8,
CFG_DRAM_WLAT_GROUP = 1,
CFG_LOCAL_WLAT_GROUP = 1,
CFG_BUFFER_ADDR_WIDTH = 6,
CFG_INT_SIZE_WIDTH = 1,
CFG_TBP_NUM = 4,
CFG_BURSTCOUNT_TRACKING_WIDTH = 7,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_DWIDTH_RATIO = 2,
CFG_ECC_BE_ALLLOW_RMW = 0
)
(
// clock & reset
ctl_clk,
ctl_reset_n,
// configuration signals
cfg_burst_length,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
// update cmd interface
update_cmd_if_ready,
update_cmd_if_valid,
update_cmd_if_data_id,
update_cmd_if_burstcount,
update_cmd_if_tbp_id,
// update data interface
update_data_if_valid,
update_data_if_data_id,
update_data_if_data_id_vector,
update_data_if_burstcount,
update_data_if_next_burstcount,
// notify burstcount consumed interface
notify_data_if_valid,
notify_data_if_burstcount,
// notify data ready interface (TBP)
notify_tbp_data_ready,
notify_tbp_data_partial_be,
// buffer write address generate interface
write_data_if_ready,
write_data_if_valid,
write_data_if_accepted,
write_data_if_address,
write_data_if_partial_be,
write_data_if_allzeros_be,
// buffer read addresss generate interface
read_data_if_valid,
read_data_if_data_id,
read_data_if_data_id_vector,
read_data_if_valid_first,
read_data_if_data_id_first,
read_data_if_data_id_vector_first,
read_data_if_valid_first_vector,
read_data_if_valid_last,
read_data_if_data_id_last,
read_data_if_data_id_vector_last,
read_data_if_address,
read_data_if_datavalid,
read_data_if_done
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam integer CFG_DATAID_ARRAY_DEPTH = (2**CFG_DATA_ID_WIDTH);
// -----------------------------
// port declaration
// -----------------------------
// clock & reset
input ctl_clk;
input ctl_reset_n;
// configuration signals
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input cfg_enable_ecc;
input cfg_enable_auto_corr;
input cfg_enable_no_dm;
// update cmd interface
output update_cmd_if_ready;
input update_cmd_if_valid;
input [CFG_DATA_ID_WIDTH-1:0] update_cmd_if_data_id;
input [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount;
input [CFG_TBP_NUM-1:0] update_cmd_if_tbp_id;
// update data interface
input update_data_if_valid;
input [CFG_DATA_ID_WIDTH-1:0] update_data_if_data_id;
input [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_data_id_vector;
input [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_burstcount;
input [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_next_burstcount;
// notify data interface
output notify_data_if_valid;
output [CFG_INT_SIZE_WIDTH-1:0] notify_data_if_burstcount;
// notify tbp interface
output [CFG_TBP_NUM-1:0] notify_tbp_data_ready;
output notify_tbp_data_partial_be;
// buffer write address generate interface
output write_data_if_ready;
input write_data_if_valid;
output write_data_if_accepted;
output [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_address;
input write_data_if_partial_be;
input write_data_if_allzeros_be;
// read data interface
input [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid;
input [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id;
input [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector;
input read_data_if_valid_first;
input [CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id_first;
input [CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector_first;
input [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid_first_vector;
input read_data_if_valid_last;
input [CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id_last;
input [CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector_last;
output [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] read_data_if_address;
output [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_datavalid;
output read_data_if_done;
// -----------------------------
// port type declaration
// -----------------------------
// clock and reset
wire ctl_clk;
wire ctl_reset_n;
// configuration signals
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire cfg_enable_ecc;
wire cfg_enable_auto_corr;
wire cfg_enable_no_dm;
// update cmd interface
wire update_cmd_if_ready;
wire update_cmd_if_valid;
wire [CFG_DATA_ID_WIDTH-1:0] update_cmd_if_data_id;
wire [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount;
reg [CFG_INT_SIZE_WIDTH-1:0] update_cmd_if_burstcount_r;
wire [CFG_TBP_NUM-1:0] update_cmd_if_tbp_id;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_address;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_address_r;
// update data interface
wire update_data_if_valid;
wire [CFG_DATA_ID_WIDTH-1:0] update_data_if_data_id;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_data_id_vector;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_data_if_next_burstcount;
// notify data interface
wire notify_data_if_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] notify_data_if_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_notify_data_if_valid;
reg [CFG_INT_SIZE_WIDTH-1:0] mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
// dataid array
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_valid;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_array_data_ready;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] dataid_array_address [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_INT_SIZE_WIDTH-1:0] dataid_array_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0]; // mano - this should be CFG_INT_SIZE_WIDTH?
reg [CFG_TBP_NUM-1:0] dataid_array_tbp_id [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_dataid_array_done;
// notify tbp interface
wire [CFG_TBP_NUM-1:0] notify_tbp_data_ready;
reg notify_tbp_data_partial_be;
reg [CFG_TBP_NUM-1:0] mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_TBP_NUM-1:0] tbp_data_ready_r;
// buffer write address generate interface
reg write_data_if_ready;
wire write_data_if_valid;
wire write_data_if_accepted;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_address;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] write_data_if_nextaddress;
wire write_data_if_partial_be;
wire write_data_if_allzeros_be;
// read data interface
wire [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_valid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] read_data_if_data_id;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] read_data_if_data_id_vector;
reg [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] read_data_if_address;
reg [CFG_DRAM_WLAT_GROUP-1:0] read_data_if_datavalid;
wire [CFG_INT_SIZE_WIDTH-1:0] read_data_if_burstcount; // used in assertion check
reg [CFG_BUFFER_ADDR_WIDTH-1:0] mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH-1:0];
reg [CFG_INT_SIZE_WIDTH-1:0] mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1:0];
wire read_data_if_done;
reg write_data_if_address_blocked;
// -----------------------------
// signal declaration
// -----------------------------
reg cfg_enable_partial_be_notification;
reg [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_max_cmd_burstcount;
reg [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_max_cmd_burstcount_2x;
wire update_cmd_if_accepted;
reg update_cmd_if_accepted_r;
wire update_cmd_if_address_blocked;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextaddress;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextaddress_r;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] update_cmd_if_nextmaxaddress;
reg update_cmd_if_nextmaxaddress_wrapped; // nextmaxaddress has wrapped around buffer max address
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_cmd_if_unnotified_burstcount;
reg [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] update_cmd_if_next_unnotified_burstcount;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_write_data_if_address_blocked;
reg [CFG_DATAID_ARRAY_DEPTH-1:0] mux_update_cmd_if_address_blocked;
reg mux_update_cmd_if_address_blocked_q1;
reg mux_update_cmd_if_address_blocked_q2;
reg mux_update_cmd_if_address_blocked_q3;
reg mux_update_cmd_if_address_blocked_q4;
// error debug signals - used in assertions
reg err_dataid_array_overwritten;
reg err_dataid_array_invalidread;
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_valid_counter; // increments on data write, decrements on data read
reg [CFG_BUFFER_ADDR_WIDTH-1:0] buffer_cmd_unallocated_counter; // increments by cmd burstcount on update cmd, decrements on data read
reg buffer_valid_counter_full;
reg err_buffer_valid_counter_overflow;
reg err_buffer_cmd_unallocated_counter_overflow;
reg partial_be_detected;
reg partial_be_when_no_cmd_tracked;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_burstcount_greatereq;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] update_data_if_burstcount_same;
wire update_data_bc_gt_update_cmd_unnotified_bc;
wire burstcount_list_read;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] burstcount_list_read_data;
wire burstcount_list_read_data_valid;
wire burstcount_list_write;
wire [CFG_INT_SIZE_WIDTH - 1 : 0] burstcount_list_write_data;
reg update_data_if_burstcount_greatereq_burstcount_list;
reg update_data_if_burstcount_same_burstcount_list;
integer k;
// -----------------------------
// module definition
// -----------------------------
always @ (*)
begin
cfg_enable_partial_be_notification = cfg_enable_ecc | cfg_enable_auto_corr | cfg_enable_no_dm;
end
always @ (*)
begin
cfg_max_cmd_burstcount = cfg_burst_length / CFG_DWIDTH_RATIO;
cfg_max_cmd_burstcount_2x = 2 * cfg_max_cmd_burstcount;
end
assign burstcount_list_write = update_cmd_if_accepted;
assign burstcount_list_write_data = {{(CFG_DATAID_ARRAY_DEPTH - CFG_INT_SIZE_WIDTH){1'b0}}, update_cmd_if_burstcount};
assign burstcount_list_read = notify_data_if_valid;
// Burst count list to keep track of burst count value,
// to be used for comparison with burst count value from burst tracking logic
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_INT_SIZE_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
burstcount_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (burstcount_list_read_data_valid),
.list_get_entry_ready (burstcount_list_read),
.list_get_entry_id (burstcount_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (burstcount_list_write),
.list_put_entry_ready (),
.list_put_entry_id (burstcount_list_write_data)
);
always @ (*)
begin
if (burstcount_list_read_data_valid && (update_data_if_burstcount >= burstcount_list_read_data))
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_greatereq_burstcount_list = 1'b0;
end
if (burstcount_list_read_data_valid && (update_data_if_burstcount == burstcount_list_read_data))
begin
update_data_if_burstcount_same_burstcount_list = 1'b1;
end
else
begin
update_data_if_burstcount_same_burstcount_list = 1'b0;
end
end
// dataid_array management
genvar i;
generate
for (i = 0; i < CFG_DATAID_ARRAY_DEPTH; i = i + 1)
begin : gen_dataid_array_management
assign update_data_if_burstcount_greatereq [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_greatereq_burstcount_list;
assign update_data_if_burstcount_same [i] = (update_data_if_valid & (update_data_if_data_id_vector [i])) & update_data_if_burstcount_same_burstcount_list;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
dataid_array_address [i] <= 0;
dataid_array_burstcount [i] <= 0;
dataid_array_tbp_id [i] <= 0;
dataid_array_data_ready [i] <= 1'b0;
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b0;
err_dataid_array_overwritten <= 0;
err_dataid_array_invalidread <= 0;
end
else
begin
// update cmd, update data & read data will not happen on same cycle
// update cmd interface
if (update_cmd_if_accepted && (update_cmd_if_data_id == i))
begin
dataid_array_address [i] <= update_cmd_if_address;
dataid_array_burstcount [i] <= update_cmd_if_burstcount;
dataid_array_tbp_id [i] <= update_cmd_if_tbp_id;
dataid_array_valid [i] <= 1'b1;
mux_dataid_array_done [i] <= 1'b0;
if (dataid_array_valid[i])
begin
err_dataid_array_overwritten <= 1;
end
end
// update data interface
if (update_data_if_burstcount_greatereq[i])
begin
dataid_array_data_ready [i] <= 1'b1;
end
// read data interface
if (read_data_if_valid_first && (read_data_if_data_id_vector_first[i]))
begin
dataid_array_address [i] <= dataid_array_address [i] + 1;
dataid_array_burstcount [i] <= dataid_array_burstcount [i] - 1;
dataid_array_data_ready [i] <= 0;
if (dataid_array_burstcount [i] == 1'b1)
begin
dataid_array_valid [i] <= 1'b0;
mux_dataid_array_done [i] <= 1'b1;
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
if (~dataid_array_valid[i])
begin
err_dataid_array_invalidread <= 1;
end
end
else
begin
mux_dataid_array_done [i] <= 1'b0;
end
end
end
always @ (*)
begin
if (update_data_if_burstcount_greatereq[i])
begin
mux_notify_data_if_valid [i] = 1'b1;
end
else
begin
mux_notify_data_if_valid [i] = 1'b0;
end
end
end
endgenerate
// mux to generate signals from output of dataid_array
// 1. notify TBP that data is ready to be read
// 2. notify other blocks burstcount consumed by dataid_array entry
// 3. generate read data address
assign notify_data_if_valid = update_data_if_burstcount_greatereq_burstcount_list;
assign notify_data_if_burstcount= burstcount_list_read_data;
assign read_data_if_burstcount = mux_read_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
assign read_data_if_done = |mux_dataid_array_done;
assign update_cmd_if_address_blocked= mux_update_cmd_if_address_blocked_q1 | mux_update_cmd_if_address_blocked_q2 | mux_update_cmd_if_address_blocked_q3 | mux_update_cmd_if_address_blocked_q4;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
mux_update_cmd_if_address_blocked_q1 <= 0;
mux_update_cmd_if_address_blocked_q2 <= 0;
mux_update_cmd_if_address_blocked_q3 <= 0;
mux_update_cmd_if_address_blocked_q4 <= 0;
end
else
begin
mux_update_cmd_if_address_blocked_q1 <= |mux_update_cmd_if_address_blocked[(CFG_DATAID_ARRAY_DEPTH-1):(CFG_DATAID_ARRAY_DEPTH/4*3)];
mux_update_cmd_if_address_blocked_q2 <= |mux_update_cmd_if_address_blocked[((CFG_DATAID_ARRAY_DEPTH/4*3)-1):(CFG_DATAID_ARRAY_DEPTH/2)];
mux_update_cmd_if_address_blocked_q3 <= |mux_update_cmd_if_address_blocked[((CFG_DATAID_ARRAY_DEPTH/2)-1):(CFG_DATAID_ARRAY_DEPTH/4)];
mux_update_cmd_if_address_blocked_q4 <= |mux_update_cmd_if_address_blocked[((CFG_DATAID_ARRAY_DEPTH/4)-1):0];
end
end
generate
if (CFG_DRAM_WLAT_GROUP == 1) // only one afi_wlat group
begin
always @ (*)
begin
read_data_if_address = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
end
end
else
begin
wire rdata_address_list_read;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_read_data;
wire rdata_address_list_read_data_valid;
wire rdata_address_list_write;
wire [CFG_BUFFER_ADDR_WIDTH - 1 : 0] rdata_address_list_write_data;
assign rdata_address_list_read = read_data_if_valid_last;
assign rdata_address_list_write = read_data_if_valid_first;
assign rdata_address_list_write_data = mux_read_data_if_address [CFG_DATAID_ARRAY_DEPTH - 1];
// Read data address list, to keep track of read address to different write data buffer group
alt_mem_ddrx_list
# (
.CTL_LIST_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CTL_LIST_DEPTH (CFG_DRAM_WLAT_GROUP),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
rdata_address_list
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_valid (rdata_address_list_read_data_valid),
.list_get_entry_ready (rdata_address_list_read),
.list_get_entry_id (rdata_address_list_read_data),
.list_get_entry_id_vector (),
.list_put_entry_valid (rdata_address_list_write),
.list_put_entry_ready (),
.list_put_entry_id (rdata_address_list_write_data)
);
for (i = 0;i < CFG_LOCAL_WLAT_GROUP;i = i + 1)
begin : rdata_if_address_per_dqs_group
always @ (*)
begin
if (read_data_if_valid_first_vector [i])
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_write_data;
end
else
begin
read_data_if_address [(i + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : i * CFG_BUFFER_ADDR_WIDTH] = rdata_address_list_read_data;
end
end
end
end
endgenerate
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
write_data_if_address_blocked <= 0;
end
else
begin
write_data_if_address_blocked <= |mux_write_data_if_address_blocked;
end
end
always @ (*)
begin
mux_tbp_data_ready [0] = (mux_notify_data_if_valid [0]) ? dataid_array_tbp_id [0] : {CFG_TBP_NUM{1'b0}};
mux_notify_data_if_burstcount [0] = (mux_notify_data_if_valid [0]) ? dataid_array_burstcount [0] : 0;
mux_read_data_if_address [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_address [0] : 0;
mux_read_data_if_burstcount [0] = (read_data_if_data_id_vector_first [0]) ? dataid_array_burstcount [0] : 0;
mux_write_data_if_address_blocked [0] = (dataid_array_data_ready[0] & ( (dataid_array_address[0] == write_data_if_nextaddress) | (dataid_array_address[0] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ~( (dataid_array_address[0] < update_cmd_if_address) & (dataid_array_address[0] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [0] = (dataid_array_valid[0] & ( (dataid_array_address[0] >= update_cmd_if_address) & (dataid_array_address[0] <= update_cmd_if_nextmaxaddress) ));
end
end
genvar j;
generate
for (j = 1; j < CFG_DATAID_ARRAY_DEPTH; j = j + 1)
begin : gen_mux_dataid_array_output
always @ (*)
begin
mux_tbp_data_ready [j] = mux_tbp_data_ready [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_tbp_id [j] : {CFG_TBP_NUM{1'b0}} );
mux_notify_data_if_burstcount [j] = mux_notify_data_if_burstcount [j-1] | ( (mux_notify_data_if_valid [j]) ? dataid_array_burstcount [j] : 0 );
mux_read_data_if_address [j] = mux_read_data_if_address [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_address [j] : 0 );
mux_read_data_if_burstcount [j] = mux_read_data_if_burstcount [j-1] | ( (read_data_if_data_id_vector_first [j]) ? dataid_array_burstcount [j] : 0 );
mux_write_data_if_address_blocked [j] = (dataid_array_data_ready[j] & ( (dataid_array_address[j] == write_data_if_nextaddress) | (dataid_array_address[j] == write_data_if_address) ) );
if (update_cmd_if_nextmaxaddress_wrapped)
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ~( (dataid_array_address[j] < update_cmd_if_address) & (dataid_array_address[j] > update_cmd_if_nextmaxaddress) ));
end
else
begin
mux_update_cmd_if_address_blocked [j] = (dataid_array_valid[j] & ( (dataid_array_address[j] >= update_cmd_if_address) & (dataid_array_address[j] <= update_cmd_if_nextmaxaddress) ));
end
end
end
endgenerate
assign notify_tbp_data_ready = mux_tbp_data_ready [CFG_DATAID_ARRAY_DEPTH-1];
// address generation for data location in buffer
assign update_cmd_if_accepted = update_cmd_if_ready & update_cmd_if_valid;
assign update_cmd_if_nextaddress = update_cmd_if_address + update_cmd_if_burstcount;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
update_cmd_if_accepted_r <= 0;
update_cmd_if_address_r <= 0;
update_cmd_if_nextaddress_r <= 0;
end
else
begin
update_cmd_if_accepted_r <= update_cmd_if_accepted;
update_cmd_if_address_r <= update_cmd_if_address;
update_cmd_if_nextaddress_r <= update_cmd_if_nextaddress;
end
end
always @ (*)
begin
if (update_cmd_if_accepted_r)
begin
update_cmd_if_address = update_cmd_if_nextaddress_r;
end
else
begin
update_cmd_if_address = update_cmd_if_address_r;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
write_data_if_address <= 0;
write_data_if_nextaddress <= 0;
end
else
begin
if (write_data_if_accepted)
begin
write_data_if_address <= write_data_if_address + 1;
write_data_if_nextaddress <= write_data_if_address + 2;
end
else
begin
write_data_if_nextaddress <= write_data_if_address + 1;
end
end
end
always @ (*)
begin
update_cmd_if_nextmaxaddress = update_cmd_if_address + cfg_max_cmd_burstcount_2x;
end
always @ (*)
begin
if (update_cmd_if_address > update_cmd_if_nextmaxaddress)
begin
update_cmd_if_nextmaxaddress_wrapped = 1'b1;
end
else
begin
update_cmd_if_nextmaxaddress_wrapped = 1'b0;
end
end
// un-notified burstcount counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
update_cmd_if_next_unnotified_burstcount <= 0;
end
else
begin
update_cmd_if_next_unnotified_burstcount <= update_cmd_if_unnotified_burstcount - mux_notify_data_if_burstcount [CFG_DATAID_ARRAY_DEPTH-1];
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
update_cmd_if_burstcount_r <= 0;
end
else
begin
update_cmd_if_burstcount_r <= update_cmd_if_burstcount;
end
end
always @ (*)
begin
if (update_cmd_if_accepted_r)
begin
update_cmd_if_unnotified_burstcount = update_cmd_if_next_unnotified_burstcount + update_cmd_if_burstcount_r;
end
else
begin
update_cmd_if_unnotified_burstcount = update_cmd_if_next_unnotified_burstcount;
end
end
// currently buffer_cmd_unallocated_counter only used for debug purposes
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_cmd_unallocated_counter <= {CFG_BUFFER_ADDR_WIDTH{1'b1}};
err_buffer_cmd_unallocated_counter_overflow <= 0;
end
else
begin
if (update_cmd_if_accepted & read_data_if_valid_last)
begin
// write & read at same time
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter- update_cmd_if_burstcount + 1;
end
else if (update_cmd_if_accepted)
begin
// write only
{err_buffer_cmd_unallocated_counter_overflow, buffer_cmd_unallocated_counter} <= buffer_cmd_unallocated_counter - update_cmd_if_burstcount;
end
else if (read_data_if_valid_last)
begin
// read only
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter + 1;
end
else
begin
buffer_cmd_unallocated_counter <= buffer_cmd_unallocated_counter;
end
end
end
assign update_cmd_if_ready = ~update_cmd_if_address_blocked;
assign write_data_if_accepted = write_data_if_ready & write_data_if_valid;
always @ (*)
begin
if (write_data_if_address_blocked)
begin
// can't write ahead of lowest address currently tracked by dataid array
write_data_if_ready = 1'b0;
end
else
begin
// buffer is full when every location has been written
// if cfg_enable_partial_be_notification, de-assert write read if partial be detected, and we have no commands being tracked currently
write_data_if_ready = ~buffer_valid_counter_full & ~partial_be_when_no_cmd_tracked;
end
end
// generate buffread_datavalid.
// data is valid one cycle after adddress is presented to the buffer
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
read_data_if_datavalid <= 0;
end
else
begin
read_data_if_datavalid <= read_data_if_valid;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
buffer_valid_counter <= 0;
buffer_valid_counter_full <= 1'b0;
err_buffer_valid_counter_overflow <= 0;
end
else
begin
if (write_data_if_accepted & read_data_if_valid_last)
begin
// write & read at same time
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
else if (write_data_if_accepted)
begin
// write only
{err_buffer_valid_counter_overflow, buffer_valid_counter} <= buffer_valid_counter + 1;
if (buffer_valid_counter == {{(CFG_BUFFER_ADDR_WIDTH - 1){1'b1}}, 1'b0}) // when valid counter is counting up to all_ones
begin
buffer_valid_counter_full <= 1'b1;
end
else
begin
buffer_valid_counter_full <= 1'b0;
end
end
else if (read_data_if_valid_last)
begin
// read only
buffer_valid_counter <= buffer_valid_counter - 1;
buffer_valid_counter_full <= 1'b0;
end
else
begin
buffer_valid_counter <= buffer_valid_counter;
buffer_valid_counter_full <= buffer_valid_counter_full;
end
end
end
// partial be generation logic
always @ (*)
begin
if (partial_be_when_no_cmd_tracked)
begin
notify_tbp_data_partial_be = update_data_if_valid & (|update_data_if_burstcount_same);
end
else
begin
notify_tbp_data_partial_be = partial_be_detected;
end
end
assign update_data_bc_gt_update_cmd_unnotified_bc = ~update_data_if_valid | (update_data_if_burstcount >= update_cmd_if_unnotified_burstcount);
generate
if (CFG_ECC_BE_ALLLOW_RMW) begin
reg detect_all_zeros_be;
reg detect_all_ones_be;
reg detect_partial_write_be;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
detect_all_zeros_be <= 1'b0;
detect_partial_write_be <= 1'b0;
detect_all_ones_be <= 1'b0;
end
else begin
if (write_data_if_accepted & write_data_if_allzeros_be)
begin
detect_all_zeros_be <= 1'b1;
end
else if (write_data_if_accepted & ~write_data_if_partial_be & ~write_data_if_allzeros_be)
begin
detect_all_ones_be <= 1'b1;
end
else if (write_data_if_accepted & write_data_if_partial_be)
begin
detect_partial_write_be <= 1'b1;
end
else if (|update_data_if_burstcount_same)
begin
detect_all_zeros_be <= 1'b0;
detect_partial_write_be <= 1'b0;
detect_all_ones_be <= 1'b0;
end
end
end
always @ (*)
begin
if (|update_data_if_burstcount_same)
begin
if (detect_partial_write_be)
begin
partial_be_detected = 1'b1;
end
else if (detect_all_zeros_be & ~detect_all_ones_be)
begin
partial_be_detected = 1'b1;
end
else
begin
partial_be_detected = 1'b0;
end
end
else
begin
partial_be_detected = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
end
else
begin
if (cfg_enable_partial_be_notification)
begin
if (partial_be_when_no_cmd_tracked)
begin
if (update_data_if_valid & ~notify_data_if_valid)
begin
// there's finally a cmd being tracked, but there's insufficient data in buffer
// this cmd has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
end
else if (update_data_if_valid & notify_data_if_valid)
begin
// there's finally a cmd being tracked, and there's sufficient data in buffer
if (|update_data_if_burstcount_same)
begin
// this command has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
end
else
begin
// this command doesnt have partial be
// let partial_be_when_no_cmd_tracked continue asserted
end
end
end
else
begin
partial_be_when_no_cmd_tracked <= write_data_if_accepted & write_data_if_partial_be & update_data_bc_gt_update_cmd_unnotified_bc;
end
end
else
begin
partial_be_when_no_cmd_tracked <= 1'b0;
end
end
end
end
else begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
else
begin
if (cfg_enable_partial_be_notification)
begin
if (partial_be_when_no_cmd_tracked)
begin
if (update_data_if_valid & ~notify_data_if_valid)
begin
// there's finally a cmd being tracked, but there's insufficient data in buffer
// this cmd has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
end
else if (update_data_if_valid & notify_data_if_valid)
begin
// there's finally a cmd being tracked, and there's sufficient data in buffer
if (|update_data_if_burstcount_same)
begin
// this command has partial be
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_be;
end
else
begin
// this command doesnt have partial be
// let partial_be_when_no_cmd_tracked continue asserted
end
end
end
else if (partial_be_detected & ~notify_data_if_valid)
begin
partial_be_detected <= partial_be_detected;
end
else
begin
partial_be_when_no_cmd_tracked <= write_data_if_accepted & write_data_if_partial_be & update_data_bc_gt_update_cmd_unnotified_bc;
partial_be_detected <= write_data_if_accepted & write_data_if_partial_be;
end
end
else
begin
partial_be_when_no_cmd_tracked <= 1'b0;
partial_be_detected <= 1'b0;
end
end
end
end
endgenerate
endmodule
|
`timescale 1ns/1ps
module search_engine(
clk,
reset,
key_in_valid,
key_in,
bv_out_valid,
bv_out,
localbus_cs_n,
localbus_rd_wr,
localbus_data,
localbus_ale,
localbus_ack_n,
localbus_data_out
);
input clk;
input reset;
input key_in_valid;
input [71:0] key_in;
output wire bv_out_valid;
output wire [35:0] bv_out;
input localbus_cs_n;
input localbus_rd_wr;
input [31:0] localbus_data;
input localbus_ale;
output reg localbus_ack_n;
output reg [31:0] localbus_data_out;
reg set_valid[0:7];
reg read_valid[0:7];
reg [8:0] addr;
wire data_out_valid[0:7];
wire [35:0] data_out[0:7];
wire stage_enable[0:1];
wire bv_valid_temp[0:7];
wire [35:0] bv_temp[0:7];
//---state----//
reg [3:0] set_state;
parameter idle = 4'd0,
ram_set = 4'd1,
ram_read = 4'd2,
wait_read = 4'd3,
wait_back = 4'd4;
//--------------reg--------------//
//--set--//
reg [31:0] localbus_addr;
reg [35:0] set_data_temp;
wire[35:0] data_out_temp;
wire data_out_valid_temp;
reg [35:0] data_out_temp_reg;
assign data_out_valid_temp = (data_out_valid[0] == 1'b1)? 1'b1:
(data_out_valid[1] == 1'b1)? 1'b1:
(data_out_valid[2] == 1'b1)? 1'b1:
(data_out_valid[3] == 1'b1)? 1'b1:
(data_out_valid[4] == 1'b1)? 1'b1:
(data_out_valid[5] == 1'b1)? 1'b1:
(data_out_valid[6] == 1'b1)? 1'b1:
(data_out_valid[7] == 1'b1)? 1'b1:
1'b0;
assign data_out_temp = (data_out_valid[0] == 1'b1)? data_out[0]:
(data_out_valid[1] == 1'b1)? data_out[1]:
(data_out_valid[2] == 1'b1)? data_out[2]:
(data_out_valid[3] == 1'b1)? data_out[3]:
(data_out_valid[4] == 1'b1)? data_out[4]:
(data_out_valid[5] == 1'b1)? data_out[5]:
(data_out_valid[6] == 1'b1)? data_out[6]:
(data_out_valid[7] == 1'b1)? data_out[7]:
36'b0;
//-----------------------set_state---------------//
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
set_state <= idle;
set_valid[0] <= 1'b0;set_valid[1] <= 1'b0;set_valid[2] <= 1'b0;
set_valid[3] <= 1'b0;set_valid[4] <= 1'b0;set_valid[5] <= 1'b0;
set_valid[6] <= 1'b0;set_valid[7] <= 1'b0;
read_valid[0]<= 1'b0;read_valid[1]<= 1'b0;read_valid[2]<= 1'b0;
read_valid[3]<= 1'b0;read_valid[4]<= 1'b0;read_valid[5]<= 1'b0;
read_valid[6]<= 1'b0;read_valid[7]<= 1'b0;
set_data_temp <= 36'b0;
localbus_ack_n <= 1'b1;
localbus_data_out <= 32'b0;
end
else
begin
case(set_state)
idle:
begin
if(localbus_ale == 1'b1)
begin
localbus_addr <= localbus_data;
if(localbus_rd_wr == 1'b0)
begin
set_state <= ram_set;
end
else
begin
set_state <= ram_read;
end
end
end
ram_set:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[0])
1'd0: set_data_temp[35:32] <= localbus_data[3:0];
1'd1:
begin
set_data_temp[31:0] <= localbus_data;
addr <= localbus_addr[11:3];
case(localbus_addr[14:12])
3'd0: set_valid[0] <= 1'b1;
3'd1: set_valid[1] <= 1'b1;
3'd2: set_valid[2] <= 1'b1;
3'd3: set_valid[3] <= 1'b1;
3'd4: set_valid[4] <= 1'b1;
3'd5: set_valid[5] <= 1'b1;
3'd6: set_valid[6] <= 1'b1;
3'd7: set_valid[7] <= 1'b1;
endcase
end
endcase
set_state <= wait_back;
localbus_ack_n <= 1'b0;
end
end
ram_read:
begin
if(localbus_cs_n == 1'b0)
begin
case(localbus_addr[0])
1'b0:
begin
addr <= localbus_addr[11:3];
case(localbus_addr[14:12])
3'd0: read_valid[0] <= 1'b1;
3'd1: read_valid[1] <= 1'b1;
3'd2: read_valid[2] <= 1'b1;
3'd3: read_valid[3] <= 1'b1;
3'd4: read_valid[4] <= 1'b1;
3'd5: read_valid[5] <= 1'b1;
3'd6: read_valid[6] <= 1'b1;
3'd7: read_valid[7] <= 1'b1;
endcase
end
1'b1: localbus_data_out <= data_out_temp_reg[31:0];
endcase
if(localbus_addr[0] == 1'b0)
begin
set_state <= wait_read;
end
else
begin
set_state <= wait_back;
localbus_ack_n <= 1'b0;
end
end
end
wait_read:
begin
read_valid[0]<= 1'b0;read_valid[1]<= 1'b0;read_valid[2]<= 1'b0;
read_valid[3]<= 1'b0;read_valid[4]<= 1'b0;read_valid[5]<= 1'b0;
read_valid[6]<= 1'b0;read_valid[7]<= 1'b0;
if(data_out_valid_temp == 1'b1)begin
localbus_data_out <={28'b0,data_out_temp[35:32]};
data_out_temp_reg <= data_out_temp;
localbus_ack_n <= 1'b0;
set_state <= wait_back;
end
end
wait_back:
begin
set_valid[0] <= 1'b0;set_valid[1] <= 1'b0;set_valid[2] <= 1'b0;
set_valid[3] <= 1'b0;set_valid[4] <= 1'b0;set_valid[5] <= 1'b0;
set_valid[6] <= 1'b0;set_valid[7] <= 1'b0;
if(localbus_cs_n == 1'b1)
begin
localbus_ack_n <= 1'b1;
set_state <= idle;
end
end
default:
begin
set_state <= idle;
end
endcase
end
end
generate
genvar i;
for(i=0; i<8; i= i+1) begin : lookup_bit
lookup_bit lb(
.clk(clk),
.reset(reset),
.set_valid(set_valid[i]),
.set_data(set_data_temp[35:0]),
.read_valid(read_valid[i]),
.addr(addr),
.data_out_valid(data_out_valid[i]),
.data_out(data_out[i]),
.key_valid(key_in_valid),
.key(key_in[((i+1)*9-1):i*9]),
.bv_valid(bv_valid_temp[i]),
.bv(bv_temp[i])
);
end
endgenerate
bv_and_8 bv_and_8(
.clk(clk),
.reset(reset),
.bv_in_valid(bv_valid_temp[0]),
.bv_1(bv_temp[0]),
.bv_2(bv_temp[1]),
.bv_3(bv_temp[2]),
.bv_4(bv_temp[3]),
.bv_5(bv_temp[4]),
.bv_6(bv_temp[5]),
.bv_7(bv_temp[6]),
.bv_8(bv_temp[7]),
.bv_out_valid(bv_out_valid),
.bv_out(bv_out)
);
endmodule
|
module scheduler1(clk, reset, wen, enablein, datain, dataout, full, empty, enableout);
parameter data_width = 32;
//parameter data_width1 = 34;
//
parameter data_width1 = 36;
parameter address_width = 5;
parameter FIFO_depth = 1024;
input clk,reset,wen,enablein;
input [data_width-1:0] datain;
output [data_width1-1:0] dataout;
output full,empty;
output enableout;
reg[31:0] write_p,read_p;
reg[address_width:0] counter;
reg[data_width-1:0] dataout1;
wire[data_width1-1:0] dataout;
reg [data_width-1:0] memory[FIFO_depth-1:0];
reg[data_width-1:0] keywordnumber,textfilenumber;
reg enableout1;
reg[3:0] routeraddress;
reg wen1;
reg [data_width-1:0] datain1;
reg ren;
reg counter1;
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
wen1=0;
else
if(wen)
wen1=1;
else
//if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
wen1=0;
else
wen1=wen1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
ren=0;
else
//if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
if(write_p!=0&&write_p!=1&&datain1==32'b11111111111111111111111111111111)
ren=1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
counter1=0;
else
if(wen&&counter1<2)
counter1=counter1+1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
dataout1=0;
else
if(wen1&&(write_p<FIFO_depth-1)&&(enableout1==1))
dataout1=dataout1+1;
// Added by me.
else
dataout1=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
//routeraddress=0;
routeraddress=4'b0000;
else
if(wen1&&(write_p<FIFO_depth-1)&&(enableout1==1))
//routeraddress=2;
routeraddress=4'b0001;
else
if(ren&&(read_p<write_p)&&(write_p<FIFO_depth-1))
//routeraddress=1;
routeraddress=4'b1001;
else
//routeraddress=0;
routeraddress=4'b0000;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
enableout1=0;
else
if(wen1)
enableout1=1;
else
if(ren&&(read_p<write_p))
enableout1=1;
else
enableout1=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
read_p=2;
else if(ren&&(read_p<write_p)&&(read_p<FIFO_depth))
read_p=read_p+1;
else
read_p=read_p;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
dataout1=0;
else if(ren&&(read_p<=write_p)&&(enableout1==1))
dataout1=memory[read_p];
end
//*************
reg end_f;
always@(posedge clk or negedge reset)
if(!reset)
end_f <= 0;
else if(datain == 32'hffffffff)
end_f <= 1'b1;
else
end_f <= end_f;
//*************
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
write_p=0;
else
if(enablein&&(write_p<FIFO_depth-1)&&(end_f==0))
write_p=write_p+1;
else
write_p=write_p;
end
always@(posedge clk)
begin
if(wen1&&enablein==1)
memory[write_p]=datain;
datain1=datain;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
counter=0;
else if(wen1&&!ren&&(counter!=FIFO_depth))
counter=counter+1;
else if(ren&&!wen1&&(counter!=0))
counter=counter-1;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
keywordnumber=0;
else if (write_p>=3)
keywordnumber=memory[2];
else
keywordnumber=0;
end
always@(posedge clk,negedge reset)
begin
//if(reset)
if(!reset)
textfilenumber=0;
else if (write_p>=4)
textfilenumber=memory[3];
else
textfilenumber=0;
end
assign full=(counter==(FIFO_depth-1));
assign empty=(counter==0);
//
//assign dataout[31:0]=dataout1;
//assign dataout[33:32]=routeraddress;
assign dataout[35:4]=dataout1;
assign dataout[3:0]=routeraddress;
//
assign enableout=enableout1;
endmodule
|
module mytb
#(
parameter integer register_size = 32,
parameter integer register_count = 32,
parameter integer input_vector_size = 32,
parameter integer output_vector_size = 32,
parameter integer fifo_depth = 512,
parameter integer saddr_w = 24
)
();
// testbench controlled signals
reg logic_reset;
reg clk;
// hack: stuff all configuration registers into an array
reg [register_size-1:0] config_regs [0:register_count-1];
reg [input_vector_size-1:0] input_vector;
wire [output_vector_size-1:0] output_vector;
// load configuration
integer configfile, inputfile, outputfile;
integer configline = 0;
string configfname, inputfname, outputfname;
initial begin
if (!$value$plusargs("configfile=%s", configfname)) begin
$display("FATAL: specify configuration file name with +configfile=<FILE>");
$finish();
end
configfile=$fopen(configfname, "r");
if (!configfile) begin
$display("FATAL: could not open configuration file");
$finish();
end
while (!$feof(configfile)) begin
if (configline < register_count) begin
$fscanf(configfile, "%h\n", config_regs[configline]);
configline = configline + 1;
end
else begin
$display("WARNING: too many values in configuration file");
end
end
$display("INFO: loaded configuration");
end
initial begin
$dumpfile("mytb.vcd");
$dumpvars(0, mytb);
input_vector <= 0;
logic_reset <= 1;
clk <= 0;
#10 logic_reset <= 0;
#10000 $finish();
end
// generate clock
always begin
#1 clk <= !clk;
end
// read input vector
initial begin
#10; //wait for reset to clear
if (!$value$plusargs("inputfile=%s", inputfname)) begin
$display("FATAL: specify input file name with +inputfile=<FILE>");
$finish();
end
inputfile=$fopen(inputfname, "r");
if (!inputfile) begin
$display("FATAL: could not open input file");
$finish();
end
while(!$feof(inputfile)) begin
$fscanf(inputfile, "%h\n", input_vector);
#2; // wait for next clock cycle
end
// finish simulation if we get here, as there is no more input
$display("INFO: no more input available, terminating");
$finish();
end
// write output vector
initial begin
if (!$value$plusargs("outputfile=%s", outputfname)) begin
$display("WARN: using default output.txt as output file");
outputfname = "output.txt";
end
outputfile=$fopen(outputfname, "w");
if (!outputfile) begin
$display("FATAL: could not open output file for writing");
$finish();
end
while (1) begin
$fwrite(outputfile, "%h\n", output_vector);
#2; // wait for next clock cycle
end
end
// instantiate here
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rw_manager_ac_ROM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Internal Build 144 10/27/2010 TO Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rw_manager_ac_ROM_no_ifdef_params (
clock,
data,
rdaddress,
wraddress,
wren,
q);
parameter ROM_INIT_FILE_NAME = "AC_ROM.hex";
input clock;
input [31:0] data;
input [5:0] rdaddress;
input [5:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b0),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "AC_ROM.rif"
`else
altsyncram_component.init_file = ROM_INIT_FILE_NAME
`endif
,
altsyncram_component.intended_device_family = "Stratix III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 40,
altsyncram_component.numwords_b = 40,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "MLAB",
altsyncram_component.widthad_a = 6,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "992"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "AC_ROM.hex"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "AC_ROM.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "40"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "40"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "MLAB"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 6 0 INPUT NODEFVAL "rdaddress[5..0]"
// Retrieval info: USED_PORT: wraddress 0 0 6 0 INPUT NODEFVAL "wraddress[5..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 6 0 wraddress 0 0 6 0
// Retrieval info: CONNECT: @address_b 0 0 6 0 rdaddress 0 0 6 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rw_manager_ac_ROM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rw_manager_ac_ROM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rw_manager_ac_ROM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rw_manager_ac_ROM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rw_manager_ac_ROM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rw_manager_ac_ROM_bb.v TRUE
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Read Data Response Down-Sizer
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// r_downsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_r_downsizer #
(
parameter C_FAMILY = "none",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI and MI side of converter.
// Range: >= 1.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always smaller than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512.
// S_DATA_WIDTH = M_DATA_WIDTH not allowed.
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 2,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO_LOG = 1
// Log2 of Up-Sizing ratio for data.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_split,
input wire cmd_mirror,
input wire cmd_fix,
input wire [C_S_AXI_BYTES_LOG-1:0] cmd_first_word,
input wire [C_S_AXI_BYTES_LOG-1:0] cmd_offset,
input wire [C_S_AXI_BYTES_LOG-1:0] cmd_mask,
input wire [C_M_AXI_BYTES_LOG:0] cmd_step,
input wire [3-1:0] cmd_size,
input wire [8-1:0] cmd_length,
output wire cmd_ready,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for MI-side word lanes on SI-side.
genvar word_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// .
localparam [24-1:0] C_DOUBLE_LEN = 24'b0000_0000_0000_0000_1111_1111;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Sub-word handling.
reg first_word;
reg [C_S_AXI_BYTES_LOG-1:0] current_word_1;
reg [C_S_AXI_BYTES_LOG-1:0] current_word;
wire [C_S_AXI_BYTES_LOG-1:0] current_word_adjusted;
wire [C_RATIO_LOG-1:0] current_index;
wire last_beat;
wire last_word;
wire new_si_word;
reg [C_S_AXI_BYTES_LOG-1:0] size_mask;
// Sub-word handling for the next cycle.
wire [C_S_AXI_BYTES_LOG-1:0] next_word;
// Burst length handling.
reg first_mi_word;
reg [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
// Loading of new rresp data.
wire load_rresp;
reg need_to_update_rresp;
reg [2-1:0] S_AXI_RRESP_ACC;
// Detect start of MI word.
wire first_si_in_mi;
wire first_mi_in_si;
// Throttling help signals.
wire word_completed;
wire cmd_ready_i;
wire pop_si_data;
wire pop_mi_data;
wire si_stalling;
// Internal MI-side control signals.
wire M_AXI_RREADY_I;
// Internal SI-side control signals.
reg [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_II;
// Internal signals for SI-side.
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID_I;
reg [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA_I;
reg [2-1:0] S_AXI_RRESP_I;
wire S_AXI_RLAST_I;
wire S_AXI_RVALID_I;
wire S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
//
/////////////////////////////////////////////////////////////////////////////
// Generate address bits used for SI-side transaction size.
always @ *
begin
case (cmd_size)
3'b000: size_mask = C_DOUBLE_LEN[8 +: C_S_AXI_BYTES_LOG];
3'b001: size_mask = C_DOUBLE_LEN[7 +: C_S_AXI_BYTES_LOG];
3'b010: size_mask = C_DOUBLE_LEN[6 +: C_S_AXI_BYTES_LOG];
3'b011: size_mask = C_DOUBLE_LEN[5 +: C_S_AXI_BYTES_LOG];
3'b100: size_mask = C_DOUBLE_LEN[4 +: C_S_AXI_BYTES_LOG];
3'b101: size_mask = C_DOUBLE_LEN[3 +: C_S_AXI_BYTES_LOG];
3'b110: size_mask = C_DOUBLE_LEN[2 +: C_S_AXI_BYTES_LOG];
3'b111: size_mask = C_DOUBLE_LEN[1 +: C_S_AXI_BYTES_LOG]; // Illegal setting.
endcase
end
// Detect when MI-side word is completely assembled.
assign word_completed = ( cmd_fix ) |
( cmd_mirror ) |
( ~cmd_fix & ( ( next_word & size_mask ) == {C_S_AXI_BYTES_LOG{1'b0}} ) ) |
( ~cmd_fix & last_word );
// Pop word from SI-side.
assign M_AXI_RREADY_I = cmd_valid & (S_AXI_RREADY_I | ~word_completed);
assign M_AXI_RREADY = M_AXI_RREADY_I;
// Indicate when there is data available @ SI-side.
assign S_AXI_RVALID_I = M_AXI_RVALID & word_completed & cmd_valid;
// Get MI-side data.
assign pop_mi_data = M_AXI_RVALID & M_AXI_RREADY_I;
// Get SI-side data.
assign pop_si_data = S_AXI_RVALID_I & S_AXI_RREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_si_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign si_stalling = S_AXI_RVALID_I & ~S_AXI_RREADY_I;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Keep track of data extraction:
//
// Current address is taken form the command buffer for the first data beat
// to handle unaligned Read transactions. After this is the extraction
// address usually calculated from this point.
// FIX transactions uses the same word address for all data beats.
//
// Next word address is generated as current word plus the current step
// size, with masking to facilitate sub-sized wraping. The Mask is all ones
// for normal wraping, and less when sub-sized wraping is used.
//
// The calculated word addresses (current and next) is offseted by the
// current Offset. For sub-sized transaction the Offset points to the least
// significant address of the included data beats. (The least significant
// word is not necessarily the first data to be extracted, consider WRAP).
// Offset is only used for sub-sized WRAP transcation that are Complete.
//
// First word is active during the first MI-side data beat.
//
// First MI is set during the first MI-side data beat.
//
// The transaction length is taken from the command buffer combinatorialy
// during the First MI cycle. For each generated MI word it is decreased
// until Last Beat is reached.
//
// Last word is determined depending as the last MI-side word generated for
// the command (generated from the AW translation).
// If burst aren't supported all MI-side words are concidered to be the last.
//
/////////////////////////////////////////////////////////////////////////////
// Select if the offset comes from command queue directly or
// from a counter while when extracting multiple MI words per SI word
always @ *
begin
if ( first_word | cmd_fix )
current_word = cmd_first_word;
else
current_word = current_word_1;
end
// Calculate next word.
assign next_word = ( current_word + cmd_step ) & cmd_mask;
// Calculate the word address with offset.
assign current_word_adjusted = current_word + cmd_offset;
// Get the ratio bits (MI-side words vs SI-side words).
assign current_index = current_word_adjusted[C_S_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG];
// Prepare next word address.
always @ (posedge ACLK) begin
if (ARESET) begin
first_word <= 1'b1;
current_word_1 <= 'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_RLAST ) begin
// Prepare for next access.
first_word <= 1'b1;
end else begin
first_word <= 1'b0;
end
current_word_1 <= next_word;
end
end
end
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word <= 1'b1;
length_counter_1 <= 8'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_RLAST ) begin
first_mi_word <= 1'b1;
end else begin
first_mi_word <= 1'b0;
end
length_counter_1 <= next_length_counter;
end
end
end
// Detect last beat in a burst.
assign last_beat = ( length_counter == 8'b0 );
// Determine if this last word that shall be extracted from this SI-side word.
assign last_word = ( last_beat );
// Detect new SI-side data word.
assign new_si_word = ( current_word == {C_S_AXI_BYTES_LOG{1'b0}} );
/////////////////////////////////////////////////////////////////////////////
// Simple AXI signal forwarding:
//
// LAST has to be filtered to remove any intermediate LAST (due to split
// trasactions).
//
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_RID_I = cmd_id;
// Handle last flag, i.e. set for SI-side last word.
assign S_AXI_RLAST_I = M_AXI_RLAST & ~cmd_split;
/////////////////////////////////////////////////////////////////////////////
// Handle the accumulation of RRESP.
//
// The accumulated RRESP register is updated for each MI-side response that
// is used in an SI-side word, i.e. the worst status for all included data
// so far.
//
/////////////////////////////////////////////////////////////////////////////
// Detect first SI-side word per MI-side word.
assign first_si_in_mi = cmd_mirror |
first_mi_word |
( ~cmd_mirror & ( ( current_word & size_mask ) == {C_S_AXI_BYTES_LOG{1'b0}} ) );
// Force load accumulated RRESPs to first value or continously for non split.
assign load_rresp = first_si_in_mi;
// Update if more critical.
always @ *
begin
case (S_AXI_RRESP_ACC)
C_RESP_EXOKAY: need_to_update_rresp = ( M_AXI_RRESP == C_RESP_OKAY |
M_AXI_RRESP == C_RESP_SLVERROR |
M_AXI_RRESP == C_RESP_DECERR );
C_RESP_OKAY: need_to_update_rresp = ( M_AXI_RRESP == C_RESP_SLVERROR |
M_AXI_RRESP == C_RESP_DECERR );
C_RESP_SLVERROR: need_to_update_rresp = ( M_AXI_RRESP == C_RESP_DECERR );
C_RESP_DECERR: need_to_update_rresp = 1'b0;
endcase
end
// Select accumultated or direct depending on setting.
always @ *
begin
if ( load_rresp || need_to_update_rresp ) begin
S_AXI_RRESP_I = M_AXI_RRESP;
end else begin
S_AXI_RRESP_I = S_AXI_RRESP_ACC;
end
end
// Accumulate MI-side RRESP.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_RRESP_ACC <= C_RESP_OKAY;
end else begin
if ( pop_mi_data ) begin
S_AXI_RRESP_ACC <= S_AXI_RRESP_I;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Demultiplex data to form complete data word.
//
/////////////////////////////////////////////////////////////////////////////
// Registers and combinatorial data MI-word size mux.
generate
for (word_cnt = 0; word_cnt < (2 ** C_RATIO_LOG) ; word_cnt = word_cnt + 1) begin : WORD_LANE
// Generate extended write data and strobe.
always @ (posedge ACLK) begin
if (ARESET) begin
S_AXI_RDATA_II[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] <= {C_M_AXI_DATA_WIDTH{1'b0}};
end else begin
if ( pop_si_data ) begin
S_AXI_RDATA_II[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] <= {C_M_AXI_DATA_WIDTH{1'b0}};
end else if ( current_index == word_cnt & pop_mi_data ) begin
S_AXI_RDATA_II[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] <= M_AXI_RDATA;
end
end
end
// Select packed or extended data.
always @ *
begin
// Multiplex data.
if ( ( current_index == word_cnt ) | cmd_mirror ) begin
S_AXI_RDATA_I[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] = M_AXI_RDATA;
end else begin
S_AXI_RDATA_I[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH] =
S_AXI_RDATA_II[word_cnt*C_M_AXI_DATA_WIDTH +: C_M_AXI_DATA_WIDTH];
end
end
end // end for word_cnt
endgenerate
/////////////////////////////////////////////////////////////////////////////
// SI-side output handling
/////////////////////////////////////////////////////////////////////////////
assign S_AXI_RREADY_I = S_AXI_RREADY;
assign S_AXI_RVALID = S_AXI_RVALID_I;
assign S_AXI_RID = S_AXI_RID_I;
assign S_AXI_RDATA = S_AXI_RDATA_I;
assign S_AXI_RRESP = S_AXI_RRESP_I;
assign S_AXI_RLAST = S_AXI_RLAST_I;
endmodule
|
// --------------------------------------------------------------------
// Copyright (c) 2005 by Terasic Technologies Inc.
// --------------------------------------------------------------------
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altrea Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// --------------------------------------------------------------------
//
// Terasic Technologies Inc
// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
// HsinChu County, Taiwan
// 302
//
// web: http://www.terasic.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
// Major Functions:i2c controller
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
// Ver :| Author :| Mod. Date :| Changes Made:
// V1.0 :| Joe Yang :| 05/07/10 :| Initial Revision
// --------------------------------------------------------------------
module I2C_Controller (
CLOCK,
I2C_SCLK,//I2C CLOCK
I2C_SDAT,//I2C DATA
I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
GO, //GO transfor
END, //END transfor
ACK, //ACK
RESET
);
input CLOCK;
input [31:0]I2C_DATA;
input GO;
input RESET;
inout I2C_SDAT;
output I2C_SCLK;
output END;
output ACK;
reg SDO;
reg SCLK;
reg END;
reg [31:0]SD;
reg [6:0]SD_COUNTER;
wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=39))? ~CLOCK :0 );
wire I2C_SDAT=SDO?1'bz:0 ;
reg ACK1,ACK2,ACK3,ACK4;
wire ACK=ACK1 | ACK2 |ACK3 |ACK4;
//--I2C COUNTER
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) SD_COUNTER=6'b111111;
else begin
if (GO==0)
SD_COUNTER=0;
else
if (SD_COUNTER < 41) SD_COUNTER=SD_COUNTER+1;
end
end
//----
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) begin SCLK=1;SDO=1; ACK1=0;ACK2=0;ACK3=0;ACK4=0; END=1; end
else
case (SD_COUNTER)
6'd0 : begin ACK1=0 ;ACK2=0 ;ACK3=0 ;ACK4=0 ; END=0; SDO=1; SCLK=1;end
//start
6'd1 : begin SD=I2C_DATA;SDO=0;end
6'd2 : SCLK=0;
//SLAVE ADDR
6'd3 : SDO=SD[31];
6'd4 : SDO=SD[30];
6'd5 : SDO=SD[29];
6'd6 : SDO=SD[28];
6'd7 : SDO=SD[27];
6'd8 : SDO=SD[26];
6'd9 : SDO=SD[25];
6'd10 : SDO=SD[24];
6'd11 : SDO=1'b1;//ACK
//SUB ADDR
6'd12 : begin SDO=SD[23]; ACK1=I2C_SDAT; end
6'd13 : SDO=SD[22];
6'd14 : SDO=SD[21];
6'd15 : SDO=SD[20];
6'd16 : SDO=SD[19];
6'd17 : SDO=SD[18];
6'd18 : SDO=SD[17];
6'd19 : SDO=SD[16];
6'd20 : SDO=1'b1;//ACK
//DATA
6'd21 : begin SDO=SD[15]; ACK2=I2C_SDAT; end
6'd22 : SDO=SD[14];
6'd23 : SDO=SD[13];
6'd24 : SDO=SD[12];
6'd25 : SDO=SD[11];
6'd26 : SDO=SD[10];
6'd27 : SDO=SD[9];
6'd28 : SDO=SD[8];
6'd29 : SDO=1'b1;//ACK
//DATA
6'd30 : begin SDO=SD[7]; ACK3=I2C_SDAT; end
6'd31 : SDO=SD[6];
6'd32 : SDO=SD[5];
6'd33 : SDO=SD[4];
6'd34 : SDO=SD[3];
6'd35 : SDO=SD[2];
6'd36 : SDO=SD[1];
6'd37 : SDO=SD[0];
6'd38 : SDO=1'b1;//ACK
//stop
6'd39 : begin SDO=1'b0; SCLK=1'b0; ACK4=I2C_SDAT; end
6'd40 : SCLK=1'b1;
6'd41 : begin SDO=1'b1; END=1; end
endcase
end
endmodule
|
// dtb.v
module dtb
(
// where to connect ???
input reset_n,
input clkin_125,
// --- EPCS
output EPCS_DCLK,
output EPCS_nCSO,
output EPCS_ASDO,
input EPCS_DATA0,
// --- 40 MHz clock oscillator input
input clk40,
// --- ROC control
output Chip_HV, // High Voltage on
output Chip_reset_n, // ROC Reset disable (open drain)
output Chip_term, // Termination 1=LCDS, 0=LVDS
output [0:3] Chip_addr,// ROC address select (opendrain)
// ---
//(* altera_attribute = "-name IO_STANDARD \"2.5-V\"" *)(* chip_pin = "B15" *)
output Power_run, // VA/VD on
inout Power_scl, // DAC/ADC
inout Power_sda, // DAC/ADC
// --- to ROC/Module interfaces (SCSI cable)
inout Plug_scl2, // I2C extern
inout Plug_sda2, // I2C extern
input [0:7] Plug_IOs,
input [0:1] Switches,
output [0:3] LEDs,
// --- Cross Point Switch
output CPS_clk,
output CPS_ce_n,
output CPS_datain,
input CPS_dataout,
output CPS_reset_n,
output CPS_update_n,
// --- ROC/Module interface
output LVDS2LCDS_clk, // LVDS
output LVDS2LCDS_ctr, // LVDS
output LVDS2LCDS_sda, // LVDS
output LVDS2LCDS_tin, // LVDS
input LVDS2LCDS_tout, // tout/RDA // LVDS
input LVDS2LCDS_sdata_I, // LVDS
input LVDS2LCDS_sdata_II, // LVDS
output LVDS2LCDS_reset_n,
output LVDS2LCDS_scl,
output LVDS2LCDS_sdi,
input LVDS2LCDS_sdo,
output LVDS2LCDS_sld,
// --- ADC
output ADC_clk, // ADC clock // LVDS
input ADC_dco, // Data clock output
output ADC_pdwn,// ADC power down
input [0:11] ADC_data,// data
input ADC_or, // overrange
// --- DDR2 RAM
inout RAM_clk,
inout RAM_clk_n,
output RAM_cke,
output RAM_cs_n,
output RAM_ras_n,
output RAM_cas_n,
output RAM_we_n,
output RAM_odt,
output [0:12] RAM_addr,
output [0:1] RAM_ba,
output [0:3] RAM_dm,
inout [0:31] RAM_dq,
inout [0:3] RAM_dqs,
// --- USB interface
input USB_clk, // clock
output USB_rd_n, // !read
output USB_wr_n, // !write
input USB_rxf_n,// !receiver full
input USB_txe_n,// !transmitter empty
output USB_siwua,// send immediate/wake up
output USB_oe_n, // output enable
inout [0:7] USB_data, // data bus
// --- Marvell 88E1111 Gigabit Ethernet
output Ethernet_gtx_clk,
output [0:3] Ethernet_txd,
output Ethernet_tx_en,
input Ethernet_rx_clk,
input [0:3] Ethernet_rxd,
input Ethernet_rx_dv,
input Ethernet_int_n,
output Ethernet_mdc,
inout Ethernet_mdio,
output Ethernet_reset_n,
// --- Micro SD Card
output SD_clk,
output SD_cs,
output SD_mosi,
input SD_miso,
input SD_cd, // card detect
// --- Cyclic Redundance Check
input CRC_error_in,
// --- external clock & general purpose IO (LEMO)
input UI_clk,
inout UI_GPIO0,
inout UI_GPIO1,
inout UI_GPIO2,
// --- User Interface IOs (spares)
inout [0:15] UI_IOs
);
// --- Chip -----------------------------------------------------------------
assign Chip_HV = 1'b0; // High Voltage on
assign Chip_reset_n = 1'bx; // ROC Reset disable
assign Chip_term = 1'b0; // LVDS Termination
assign Chip_addr = 4'b0000; // ROC address select
// --- Power control --------------------------------------------------------
assign Power_run = 1'b0;
assign Power_scl = 1'bz;
assign Power_sda = 1'bz;
assign Plug_scl2 = 1'bz;
assign Plug_sda2 = 1'bz;
// --- Cross point switch --------------------------------------------------
assign CPS_clk = 1'b0;
assign CPS_ce_n = 1'b1;
assign CPS_datain = 1'b0;
assign CPS_reset_n = 1'b0;
assign CPS_update_n = 1'b1;
// --- ROC/Module interface -------------------------------------------------
assign LVDS2LCDS_clk = 1'b0;
assign LVDS2LCDS_ctr = 1'b0;
assign LVDS2LCDS_sda = 1'b0;
assign LVDS2LCDS_tin = 1'b0;
assign LVDS2LCDS_reset_n = 1'b0;
assign LVDS2LCDS_scl = 1'b0;
assign LVDS2LCDS_sdi = 1'b0;
assign LVDS2LCDS_sld = 1'b0;
// --- ADC ------------------------------------------------------------------
assign ADC_clk = 1'b0; // ADC clock
assign ADC_pdwn = 1'b1; // ADC power down
// --- USB interface --------------------------------------------------------
assign USB_rd_n = 1'b1; // !read
assign USB_wr_n = 1'b1; // !write
assign USB_siwua = 1'b0; // send immediate/wake up
assign USB_oe_n = 1'b1; // output enable
assign USB_data = 8'hzz; // data bus
// --- Micro SD Card --------------------------------------------------------
assign SD_clk = 1'b0;
assign SD_cs = 1'b0;
assign SD_mosi = 1'b0;
// --- User IO (LEMO) -------------------------------------------------------
assign UI_GPIO0 = 1'bz;
assign UI_GPIO1 = 1'bz;
assign UI_GPIO2 = 1'bz;
// --- User IOs (spares) ---------------------------------------------------
assign UI_IOs = 16'hzzzz;
// --- Ethernet interface assignments ---------------------------------------
wire mdio_in;
wire mdio_oen;
wire mdio_out;
wire eth_mode;
wire ena_10;
wire tx_clk;
wire enet_tx_125;
wire enet_tx_25;
wire enet_tx_2p5;
assign mdio_in = Ethernet_mdio;
assign Ethernet_mdio = mdio_oen == 0 ? mdio_out : 1'bz;
assign Ethernet_reset_n = reset_n;
altddio_out altddio_out_component
(
.outclock ( tx_clk ),
.dataout ( Ethernet_gtx_clk ),
.aclr (!reset_n),
.datain_h (1'b1),
.datain_l (1'b0),
.outclocken (1'b1),
.aset (1'b0),
.sclr (1'b0),
.sset (1'b0),
.oe_out (),
.oe (1'b1)
);
defparam
altddio_out_component.extend_oe_disable = "UNUSED",
altddio_out_component.intended_device_family = "Cyclone III",
altddio_out_component.invert_output = "OFF",
altddio_out_component.lpm_type = "altddio_out",
altddio_out_component.oe_reg = "UNUSED",
altddio_out_component.width = 1;
assign tx_clk = (eth_mode) ? (enet_tx_125) : // GbE Mode = 125MHz clock
(ena_10) ? (enet_tx_2p5) : // 10Mb Mode = 2.5MHz clock
(enet_tx_25); // 100Mb Mode = 25MHz clock
enet_pll enet_pll_inst
(
.areset (!reset_n),
.inclk0 (clkin_125),
.c0 (enet_tx_125),
.c1 (enet_tx_25),
.c2 (enet_tx_2p5),
.locked ()
);
// --- QSYS system instantiation --------------------------------------------
dtb_system dtb_sys
(
.clkin_50 (clk40),
.reset_n (reset_n),
.sdram_aux_full_rate_clk_out (),
.sdram_phy_clk_out (),
.sdram_aux_half_rate_clk_out (),
// ddr2 sdram
.sdram_reset_n (reset_n),
.local_init_done_from_the_sdram (),
.local_refresh_ack_from_the_sdram (),
.local_wdata_req_from_the_sdram (),
.mem_addr_from_the_sdram (RAM_addr),
.mem_ba_from_the_sdram (RAM_ba),
.mem_cas_n_from_the_sdram (RAM_cas_n),
.mem_cke_from_the_sdram (RAM_cke),
.mem_clk_n_to_and_from_the_sdram (RAM_clk_n),
.mem_clk_to_and_from_the_sdram (RAM_clk),
.mem_cs_n_from_the_sdram (RAM_cs_n),
.mem_dm_from_the_sdram (RAM_dm),
.mem_dq_to_and_from_the_sdram (RAM_dq),
.mem_dqs_to_and_from_the_sdram (RAM_dqs),
.mem_odt_from_the_sdram (RAM_odt),
.mem_ras_n_from_the_sdram (RAM_ras_n),
.mem_we_n_from_the_sdram (RAM_we_n),
.reset_phy_clk_n_from_the_sdram (),
// tse mac
.ena_10_from_the_tse_mac (ena_10),
.eth_mode_from_the_tse_mac (eth_mode),
.mdc_from_the_tse_mac (Ethernet_mdc),
.mdio_in_to_the_tse_mac (mdio_in),
.mdio_oen_from_the_tse_mac (mdio_oen),
.mdio_out_from_the_tse_mac (mdio_out),
.rgmii_in_to_the_tse_mac (Ethernet_rxd),
.rgmii_out_from_the_tse_mac (Ethernet_txd),
.rx_clk_to_the_tse_mac (Ethernet_rx_clk),
.rx_control_to_the_tse_mac (Ethernet_rx_dv),
.set_1000_to_the_tse_mac (),
.set_10_to_the_tse_mac (),
.tx_clk_to_the_tse_mac (tx_clk),
.tx_control_from_the_tse_mac (Ethernet_tx_en),
// epcs
.epcs_dclk (EPCS_DCLK),
.epcs_sce (EPCS_nCSO),
.epcs_sdo (EPCS_ASDO),
.epcs_data0 (EPCS_DATA0),
// button pio
.in_port_to_the_button_pio (Switches),
// led pio
.out_port_from_the_led_pio (LEDs)
);
endmodule
|
/**
* @module regfile
* @author sabertazimi
* @email [email protected]
* @brief register files for MIPS CPU, contains 32 D flip-flop registers
* @param DATA_WIDTH data width
* @input clk clock signal
* @input we write enable signal
* @input raddrA read address (No.register) for A out port
* @input raddrB read address (No.register) for B out port
* @input waddr write address (No.register) for wdata (in port)
* @input wdata data to write into regfile
* @output regA A port output
* @output regB B port output
*/
module regfile
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input we,
input [4:0] raddrA,
input [4:0] raddrB,
input [4:0] waddr,
input [DATA_WIDTH-1:0] wdata,
output [DATA_WIDTH-1:0] regA,
output [DATA_WIDTH-1:0] regB,
output [DATA_WIDTH-1:0] v0_data,
output [DATA_WIDTH-1:0] a0_data
);
`include "defines.vh"
reg [4:0] i;
reg [DATA_WIDTH-1:0] regfile [0:31]; ///< three ported regfile contains 32 registers
initial begin
i <= 0;
end
always @ (posedge clk) begin
if (rst) begin
for (i = 0; i < 31; i = i + 1)
begin
regfile[i] <= 0;
end
end else if (we && waddr != 0) begin
regfile[waddr] <= wdata;
end
end
assign regA = (raddrA != 0) ? regfile[raddrA] : 0;
assign regB = (raddrB != 0) ? regfile[raddrB] : 0;
assign v0_data = regfile[`V0];
assign a0_data = regfile[`A0];
endmodule // regfile
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v4_0_phy_ocd_edge.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Detects and stores edges as the test pattern is scanned via
// manipulating the phaser out stage 3 taps.
//
// Scanning always proceeds from the left to the right. For more
// on the scanning algorithm, see the _po_cntlr block.
//
// Four scan results are reported. The edges at fuzz2zero,
// zero2fuzz, fuzz2oneeighty, and oneeighty2fuzz. Each edge
// has a 6 bit stg3 tap value and a valid bit. The valid bits
// are reset before the scan starts.
//
// Once reset_scan is set low, this block waits for the first
// samp_done while scanning_right. This marks the left end
// of the scan, and initializes prev_samp_r with samp_result and
// sets the prev_samp_r valid bit to one.
//
// At each subesquent samp_done, the previous samp is compared
// to the current samp_result. The case statement details how
// edges are identified.
//
// Original design assumed fuzz between valid regions. Design
// has been updated to tolerate transitions from zero to oneeight
// and vice-versa without fuzz in between.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v4_0_ddr_phy_ocd_edge #
(parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
scan_right, z2f, f2z, o2f, f2o, zero2fuzz, fuzz2zero,
oneeighty2fuzz, fuzz2oneeighty,
// Inputs
clk, samp_done, phy_rddata_en_2, reset_scan, scanning_right,
samp_result, stg3
);
localparam [1:0] NULL = 2'b11,
FUZZ = 2'b00,
ONEEIGHTY = 2'b10,
ZERO = 2'b01;
input clk;
input samp_done;
input phy_rddata_en_2;
wire samp_valid = samp_done && phy_rddata_en_2;
input reset_scan;
input scanning_right;
reg prev_samp_valid_ns, prev_samp_valid_r;
always @(posedge clk) prev_samp_valid_r <= #TCQ prev_samp_valid_ns;
always @(*) begin
prev_samp_valid_ns = prev_samp_valid_r;
if (reset_scan) prev_samp_valid_ns = 1'b0;
else if (samp_valid) prev_samp_valid_ns = 1'b1;
end
input [1:0] samp_result;
reg [1:0] prev_samp_ns, prev_samp_r;
always @(posedge clk) prev_samp_r <= #TCQ prev_samp_ns;
always @(*)
if (samp_valid) prev_samp_ns = samp_result;
else prev_samp_ns = prev_samp_r;
reg scan_right_ns, scan_right_r;
always @(posedge clk) scan_right_r <= #TCQ scan_right_ns;
output scan_right;
assign scan_right = scan_right_r;
input [5:0] stg3;
reg z2f_ns, z2f_r, f2z_ns, f2z_r, o2f_ns, o2f_r, f2o_ns, f2o_r;
always @(posedge clk) z2f_r <= #TCQ z2f_ns;
always @(posedge clk) f2z_r <= #TCQ f2z_ns;
always @(posedge clk) o2f_r <= #TCQ o2f_ns;
always @(posedge clk) f2o_r <= #TCQ f2o_ns;
output z2f, f2z, o2f, f2o;
assign z2f = z2f_r;
assign f2z = f2z_r;
assign o2f = o2f_r;
assign f2o = f2o_r;
reg [5:0] zero2fuzz_ns, zero2fuzz_r, fuzz2zero_ns, fuzz2zero_r,
oneeighty2fuzz_ns, oneeighty2fuzz_r, fuzz2oneeighty_ns, fuzz2oneeighty_r;
always @(posedge clk) zero2fuzz_r <= #TCQ zero2fuzz_ns;
always @(posedge clk) fuzz2zero_r <= #TCQ fuzz2zero_ns;
always @(posedge clk) oneeighty2fuzz_r <= #TCQ oneeighty2fuzz_ns;
always @(posedge clk) fuzz2oneeighty_r <= #TCQ fuzz2oneeighty_ns;
output [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
assign zero2fuzz = zero2fuzz_r;
assign fuzz2zero = fuzz2zero_r;
assign oneeighty2fuzz = oneeighty2fuzz_r;
assign fuzz2oneeighty = fuzz2oneeighty_r;
always @(*) begin
z2f_ns = z2f_r;
f2z_ns = f2z_r;
o2f_ns = o2f_r;
f2o_ns = f2o_r;
zero2fuzz_ns = zero2fuzz_r;
fuzz2zero_ns = fuzz2zero_r;
oneeighty2fuzz_ns = oneeighty2fuzz_r;
fuzz2oneeighty_ns = fuzz2oneeighty_r;
scan_right_ns = 1'b0;
if (reset_scan) begin
z2f_ns = 1'b0;
f2z_ns = 1'b0;
o2f_ns = 1'b0;
f2o_ns = 1'b0;
end
else if (samp_valid && prev_samp_valid_r)
case (prev_samp_r)
FUZZ :
if (scanning_right) begin
if (samp_result == ZERO) begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
ZERO : begin
if (samp_result == FUZZ || samp_result == ONEEIGHTY) scan_right_ns = !scanning_right;
if (scanning_right) begin
if (samp_result == FUZZ) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
end
ONEEIGHTY :
if (scanning_right) begin
if (samp_result == FUZZ) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end
if (samp_result == ZERO)
if (f2o_r) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end else begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
end // if (scanning_right)
// NULL : // Should never happen
endcase
end
endmodule // mig_7series_v4_0_ddr_phy_ocd_edge
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data AXI3 Slave Converter
// Forward and split transactions as required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_axi3_conv
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_8_w_axi3_conv #
(
parameter C_FAMILY = "none",
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_SUPPORT_SPLITTING = 1,
// Implement transaction splitting logic.
// Disabled whan all connected masters are AXI3 and have same or narrower data width.
parameter integer C_SUPPORT_BURSTS = 1
// Disabled when all connected masters are AxiLite,
// allowing logic to be simplified.
)
(
// System Signals
input wire ACLK,
input wire ARESET,
// Command Interface
input wire cmd_valid,
input wire [C_AXI_ID_WIDTH-1:0] cmd_id,
input wire [4-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Burst length handling.
reg first_mi_word;
reg [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
wire last_beat;
wire last_word;
// Throttling help signals.
wire cmd_ready_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal signals for MI-side.
wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID_I;
wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Forward data from SI-Side to MI-Side while a command is available. When
// the transaction has completed the command is popped from the Command FIFO.
//
/////////////////////////////////////////////////////////////////////////////
// Pop word from SI-side.
assign S_AXI_WREADY_I = S_AXI_WVALID & cmd_valid & ~mi_stalling;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
assign M_AXI_WVALID_I = S_AXI_WVALID & cmd_valid;
// Get MI-side data.
assign pop_mi_data = M_AXI_WVALID_I & M_AXI_WREADY_I;
// Signal that the command is done (so that it can be poped from command queue).
assign cmd_ready_i = cmd_valid & pop_mi_data & last_word;
assign cmd_ready = cmd_ready_i;
// Detect when MI-side is stalling.
assign mi_stalling = M_AXI_WVALID_I & ~M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data forwarding:
//
// On the first cycle of the transaction is the length taken from the Command
// FIFO. The length is decreased until 0 is reached which indicates last data
// word.
//
// If bursts are unsupported will all data words be the last word, each one
// from a separate transaction.
//
/////////////////////////////////////////////////////////////////////////////
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word <= 1'b1;
length_counter_1 <= 4'b0;
end else begin
if ( pop_mi_data ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word <= 1'b1;
end else begin
first_mi_word <= 1'b0;
end
length_counter_1 <= next_length_counter;
end
end
end
// Detect last beat in a burst.
assign last_beat = ( length_counter == 4'b0 );
// Determine if this last word that shall be extracted from this SI-side word.
assign last_word = ( last_beat ) |
( C_SUPPORT_BURSTS == 0 );
/////////////////////////////////////////////////////////////////////////////
// Select the SI-side word to write.
//
// Most information can be reused directly (DATA, STRB, ID and USER).
// ID is taken from the Command FIFO.
//
// Split transactions needs to insert new LAST transactions. So to simplify
// is the LAST signal always generated.
//
/////////////////////////////////////////////////////////////////////////////
// ID and USER is copied from the SI word to all MI word transactions.
assign M_AXI_WUSER_I = ( C_AXI_SUPPORTS_USER_SIGNALS ) ? S_AXI_WUSER : {C_AXI_WUSER_WIDTH{1'b0}};
// Data has to be multiplexed.
assign M_AXI_WDATA_I = S_AXI_WDATA;
assign M_AXI_WSTRB_I = S_AXI_WSTRB;
// ID is taken directly from the command queue.
assign M_AXI_WID_I = cmd_id;
// Handle last flag, i.e. set for MI-side last word.
assign M_AXI_WLAST_I = last_word;
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
//
/////////////////////////////////////////////////////////////////////////////
// TODO: registered?
assign M_AXI_WID = M_AXI_WID_I;
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WUSER = M_AXI_WUSER_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** This library has been deprecated since Coq version 8.10. *)
(** * Int31 numbers defines indeed a cyclic structure : Z/(2^31)Z *)
(**
Author: Arnaud Spiwack (+ Pierre Letouzey)
*)
Require Import List.
Require Import Min.
Require Export Int31.
Require Import Znumtheory.
Require Import Zgcd_alt.
Require Import Zpow_facts.
Require Import CyclicAxioms.
Require Import Lia.
Local Open Scope nat_scope.
Local Open Scope int31_scope.
Local Hint Resolve Z.lt_gt Z.div_pos : zarith.
Section Basics.
(** * Basic results about [iszero], [shiftl], [shiftr] *)
Lemma iszero_eq0 : forall x, iszero x = true -> x=0.
Proof.
destruct x; simpl; intros.
repeat
match goal with H:(if ?d then _ else _) = true |- _ =>
destruct d; try discriminate
end.
reflexivity.
Qed.
Lemma iszero_not_eq0 : forall x, iszero x = false -> x<>0.
Proof.
intros x H Eq; rewrite Eq in H; simpl in *; discriminate.
Qed.
Lemma sneakl_shiftr : forall x,
x = sneakl (firstr x) (shiftr x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma sneakr_shiftl : forall x,
x = sneakr (firstl x) (shiftl x).
Proof.
destruct x; simpl; auto.
Qed.
Lemma twice_zero : forall x,
twice x = 0 <-> twice_plus_one x = 1.
Proof.
destruct x; simpl in *; split;
intro H; injection H; intros; subst; auto.
Qed.
Lemma twice_or_twice_plus_one : forall x,
x = twice (shiftr x) \/ x = twice_plus_one (shiftr x).
Proof.
intros; case_eq (firstr x); intros.
destruct x; simpl in *; rewrite H; auto.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** * Iterated shift to the right *)
Definition nshiftr x := nat_rect _ x (fun _ => shiftr).
Lemma nshiftr_S :
forall n x, nshiftr x (S n) = shiftr (nshiftr x n).
Proof.
reflexivity.
Qed.
Lemma nshiftr_S_tail :
forall n x, nshiftr x (S n) = nshiftr (shiftr x) n.
Proof.
intros n; elim n; simpl; auto.
intros; now f_equal.
Qed.
Lemma nshiftr_n_0 : forall n, nshiftr 0 n = 0.
Proof.
induction n; simpl; auto.
rewrite IHn; auto.
Qed.
Lemma nshiftr_size : forall x, nshiftr x size = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftr_above_size : forall k x, size<=k ->
nshiftr x k = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by lia.
induction (k-size)%nat; auto.
rewrite nshiftr_size; auto.
simpl; rewrite IHn; auto.
Qed.
(** * Iterated shift to the left *)
Definition nshiftl x := nat_rect _ x (fun _ => shiftl).
Lemma nshiftl_S :
forall n x, nshiftl x (S n) = shiftl (nshiftl x n).
Proof.
reflexivity.
Qed.
Lemma nshiftl_S_tail :
forall n x, nshiftl x (S n) = nshiftl (shiftl x) n.
Proof.
intros n; elim n; simpl; intros; now f_equal.
Qed.
Lemma nshiftl_n_0 : forall n, nshiftl 0 n = 0.
Proof.
induction n; simpl; auto.
rewrite IHn; auto.
Qed.
Lemma nshiftl_size : forall x, nshiftl x size = 0.
Proof.
destruct x; simpl; auto.
Qed.
Lemma nshiftl_above_size : forall k x, size<=k ->
nshiftl x k = 0.
Proof.
intros.
replace k with ((k-size)+size)%nat by lia.
induction (k-size)%nat; auto.
rewrite nshiftl_size; auto.
simpl; rewrite IHn; auto.
Qed.
Lemma firstr_firstl :
forall x, firstr x = firstl (nshiftl x (pred size)).
Proof.
destruct x; simpl; auto.
Qed.
Lemma firstl_firstr :
forall x, firstl x = firstr (nshiftr x (pred size)).
Proof.
destruct x; simpl; auto.
Qed.
(** More advanced results about [nshiftr] *)
Lemma nshiftr_predsize_0_firstl : forall x,
nshiftr x (pred size) = 0 -> firstl x = D0.
Proof.
destruct x; compute; intros H; injection H; intros; subst; auto.
Qed.
Lemma nshiftr_0_propagates : forall n p x, n <= p ->
nshiftr x n = 0 -> nshiftr x p = 0.
Proof.
intros.
replace p with ((p-n)+n)%nat by lia.
induction (p-n)%nat.
simpl; auto.
simpl; rewrite IHn0; auto.
Qed.
Lemma nshiftr_0_firstl : forall n x, n < size ->
nshiftr x n = 0 -> firstl x = D0.
Proof.
intros.
apply nshiftr_predsize_0_firstl.
apply nshiftr_0_propagates with n; auto; lia.
Qed.
(** * Some induction principles over [int31] *)
(** Not used for the moment. Are they really useful ? *)
Lemma int31_ind_sneakl : forall P : int31->Prop,
P 0 ->
(forall x d, P x -> P (sneakl d x)) ->
forall x, P x.
Proof.
intros.
assert (forall n, n<=size -> P (nshiftr x (size - n))).
induction n; intros.
rewrite nshiftr_size; auto.
rewrite sneakl_shiftr.
apply H0.
change (P (nshiftr x (S (size - S n)))).
replace (S (size - S n))%nat with (size - n)%nat by lia.
apply IHn; lia.
change x with (nshiftr x (size-size)); auto.
Qed.
Lemma int31_ind_twice : forall P : int31->Prop,
P 0 ->
(forall x, P x -> P (twice x)) ->
(forall x, P x -> P (twice_plus_one x)) ->
forall x, P x.
Proof.
induction x using int31_ind_sneakl; auto.
destruct d; auto.
Qed.
(** * Some generic results about [recr] *)
Section Recr.
(** [recr] satisfies the fixpoint equation used for its definition. *)
Variable (A:Type)(case0:A)(caserec:digits->int31->A->A).
Lemma recr_aux_eqn : forall n x, iszero x = false ->
recr_aux (S n) A case0 caserec x =
caserec (firstr x) (shiftr x) (recr_aux n A case0 caserec (shiftr x)).
Proof.
intros; simpl; rewrite H; auto.
Qed.
Lemma recr_aux_converges :
forall n p x, n <= size -> n <= p ->
recr_aux n A case0 caserec (nshiftr x (size - n)) =
recr_aux p A case0 caserec (nshiftr x (size - n)).
Proof.
induction n.
simpl minus; intros.
rewrite nshiftr_size; destruct p; simpl; auto.
intros.
destruct p.
inversion H0.
unfold recr_aux; fold recr_aux.
destruct (iszero (nshiftr x (size - S n))); auto.
f_equal.
change (shiftr (nshiftr x (size - S n))) with (nshiftr x (S (size - S n))).
replace (S (size - S n))%nat with (size - n)%nat by lia.
apply IHn; auto with arith.
Qed.
Lemma recr_eqn : forall x, iszero x = false ->
recr A case0 caserec x =
caserec (firstr x) (shiftr x) (recr A case0 caserec (shiftr x)).
Proof.
intros.
unfold recr.
change x with (nshiftr x (size - size)).
rewrite (recr_aux_converges size (S size)); auto with arith.
rewrite recr_aux_eqn; auto.
Qed.
(** [recr] is usually equivalent to a variant [recrbis]
written without [iszero] check. *)
Fixpoint recrbis_aux (n:nat)(A:Type)(case0:A)(caserec:digits->int31->A->A)
(i:int31) : A :=
match n with
| O => case0
| S next =>
let si := shiftr i in
caserec (firstr i) si (recrbis_aux next A case0 caserec si)
end.
Definition recrbis := recrbis_aux size.
Hypothesis case0_caserec : caserec D0 0 case0 = case0.
Lemma recrbis_aux_equiv : forall n x,
recrbis_aux n A case0 caserec x = recr_aux n A case0 caserec x.
Proof.
induction n; simpl; auto; intros.
case_eq (iszero x); intros; [ | f_equal; auto ].
rewrite (iszero_eq0 _ H); simpl; auto.
replace (recrbis_aux n A case0 caserec 0) with case0; auto.
clear H IHn; induction n; simpl; congruence.
Qed.
Lemma recrbis_equiv : forall x,
recrbis A case0 caserec x = recr A case0 caserec x.
Proof.
intros; apply recrbis_aux_equiv; auto.
Qed.
End Recr.
(** * Incrementation *)
Section Incr.
(** Variant of [incr] via [recrbis] *)
Let Incr (b : digits) (si rec : int31) :=
match b with
| D0 => sneakl D1 si
| D1 => sneakl D0 rec
end.
Definition incrbis_aux n x := recrbis_aux n _ In Incr x.
Lemma incrbis_aux_equiv : forall x, incrbis_aux size x = incr x.
Proof.
unfold incr, recr, incrbis_aux; fold Incr; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [incr] *)
Lemma incr_eqn1 :
forall x, firstr x = D0 -> incr x = twice_plus_one (shiftr x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_eqn2 :
forall x, firstr x = D1 -> incr x = twice (incr (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
unfold incr; rewrite recr_eqn; fold incr; auto.
rewrite H; auto.
Qed.
Lemma incr_twice : forall x, incr (twice x) = twice_plus_one x.
Proof.
intros.
rewrite incr_eqn1; destruct x; simpl; auto.
Qed.
Lemma incr_twice_plus_one_firstl :
forall x, firstl x = D0 -> incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
(** The previous result is actually true even without the
constraint on [firstl], but this is harder to prove
(see later). *)
End Incr.
(** * Conversion to [Z] : the [phi] function *)
Section Phi.
(** Variant of [phi] via [recrbis] *)
Let Phi := fun b (_:int31) =>
match b with D0 => Z.double | D1 => Z.succ_double end.
Definition phibis_aux n x := recrbis_aux n _ Z0 Phi x.
Lemma phibis_aux_equiv : forall x, phibis_aux size x = phi x.
Proof.
unfold phi, recr, phibis_aux; fold Phi; intros.
apply recrbis_aux_equiv; auto.
Qed.
(** Recursive equations satisfied by [phi] *)
Lemma phi_eqn1 : forall x, firstr x = D0 ->
phi x = Z.double (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0); simpl; auto.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_eqn2 : forall x, firstr x = D1 ->
phi x = Z.succ_double (phi (shiftr x)).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in H; simpl in H; discriminate.
intros; unfold phi; rewrite recr_eqn; fold phi; auto.
rewrite H; auto.
Qed.
Lemma phi_twice_firstl : forall x, firstl x = D0 ->
phi (twice x) = Z.double (phi x).
Proof.
intros.
rewrite phi_eqn1; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
Lemma phi_twice_plus_one_firstl : forall x, firstl x = D0 ->
phi (twice_plus_one x) = Z.succ_double (phi x).
Proof.
intros.
rewrite phi_eqn2; auto; [ | destruct x; auto ].
f_equal; f_equal.
destruct x; simpl in *; rewrite H; auto.
Qed.
End Phi.
(** [phi x] is positive and lower than [2^31] *)
Lemma phibis_aux_pos : forall n x, (0 <= phibis_aux n x)%Z.
Proof.
induction n.
simpl; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr x)).
destruct (firstr x).
specialize IHn with (shiftr x); rewrite Z.double_spec; lia.
specialize IHn with (shiftr x); rewrite Z.succ_double_spec; lia.
Qed.
Lemma phibis_aux_bounded :
forall n x, n <= size ->
(phibis_aux n (nshiftr x (size-n)) < 2 ^ (Z.of_nat n))%Z.
Proof.
induction n.
simpl minus; unfold phibis_aux; simpl; auto with zarith.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr x (size - S n)))).
assert (shiftr (nshiftr x (size - S n)) = nshiftr x (size-n)).
replace (size - n)%nat with (S (size - (S n))) by lia.
simpl; auto.
rewrite H0.
assert (H1 : n <= size) by lia.
specialize (IHn x H1).
set (y:=phibis_aux n (nshiftr x (size - n))) in *.
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
case_eq (firstr (nshiftr x (size - S n))); intros.
rewrite Z.double_spec. lia.
rewrite Z.succ_double_spec; lia.
Qed.
Lemma phi_nonneg : forall x, (0 <= phi x)%Z.
Proof.
intros.
rewrite <- phibis_aux_equiv.
apply phibis_aux_pos.
Qed.
#[local]
Hint Resolve phi_nonneg : zarith.
Lemma phi_bounded : forall x, (0 <= phi x < 2 ^ (Z.of_nat size))%Z.
Proof.
intros. split; [auto with zarith|].
rewrite <- phibis_aux_equiv.
change x with (nshiftr x (size-size)).
apply phibis_aux_bounded; auto.
Qed.
Lemma phibis_aux_lowerbound :
forall n x, firstr (nshiftr x n) = D1 ->
(2 ^ Z.of_nat n <= phibis_aux (S n) x)%Z.
Proof.
induction n.
intros.
unfold nshiftr in H; simpl in *.
unfold phibis_aux, recrbis_aux.
rewrite H, Z.succ_double_spec; lia.
intros.
remember (S n) as m.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux m (shiftr x)).
subst m.
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
assert (2^(Z.of_nat n) <= phibis_aux (S n) (shiftr x))%Z.
apply IHn.
rewrite <- nshiftr_S_tail; auto.
destruct (firstr x).
change (Z.double (phibis_aux (S n) (shiftr x))) with
(2*(phibis_aux (S n) (shiftr x)))%Z.
lia.
rewrite Z.succ_double_spec; lia.
Qed.
Lemma phi_lowerbound :
forall x, firstl x = D1 -> (2^(Z.of_nat (pred size)) <= phi x)%Z.
Proof.
intros.
generalize (phibis_aux_lowerbound (pred size) x).
rewrite <- firstl_firstr.
change (S (pred size)) with size; auto.
rewrite phibis_aux_equiv; auto.
Qed.
(** * Equivalence modulo [2^n] *)
Section EqShiftL.
(** After killing [n] bits at the left, are the numbers equal ?*)
Definition EqShiftL n x y :=
nshiftl x n = nshiftl y n.
Lemma EqShiftL_zero : forall x y, EqShiftL O x y <-> x = y.
Proof.
unfold EqShiftL; intros; unfold nshiftl; simpl; split; auto.
Qed.
Lemma EqShiftL_size : forall k x y, size<=k -> EqShiftL k x y.
Proof.
red; intros; rewrite 2 nshiftl_above_size; auto.
Qed.
Lemma EqShiftL_le : forall k k' x y, k <= k' ->
EqShiftL k x y -> EqShiftL k' x y.
Proof.
unfold EqShiftL; intros.
replace k' with ((k'-k)+k)%nat by lia.
remember (k'-k)%nat as n.
clear Heqn H k'.
induction n; simpl; auto.
f_equal; auto.
Qed.
Lemma EqShiftL_firstr : forall k x y, k < size ->
EqShiftL k x y -> firstr x = firstr y.
Proof.
intros.
rewrite 2 firstr_firstl.
f_equal.
apply EqShiftL_le with k; auto.
unfold size.
auto with arith.
Qed.
Lemma EqShiftL_twice : forall k x y,
EqShiftL k (twice x) (twice y) <-> EqShiftL (S k) x y.
Proof.
intros; unfold EqShiftL.
rewrite 2 nshiftl_S_tail; split; auto.
Qed.
(** * From int31 to list of digits. *)
(** Lower (=rightmost) bits comes first. *)
Definition i2l := recrbis _ nil (fun d _ rec => d::rec).
Lemma i2l_length : forall x, length (i2l x) = size.
Proof.
intros; reflexivity.
Qed.
Fixpoint lshiftl l x :=
match l with
| nil => x
| d::l => sneakl d (lshiftl l x)
end.
Definition l2i l := lshiftl l On.
Lemma l2i_i2l : forall x, l2i (i2l x) = x.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakr : forall x d,
i2l (sneakr d x) = tail (i2l x) ++ d::nil.
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_sneakl : forall x d,
i2l (sneakl d x) = d :: removelast (i2l x).
Proof.
destruct x; compute; auto.
Qed.
Lemma i2l_l2i : forall l, length l = size ->
i2l (l2i l) = l.
Proof.
repeat (destruct l as [ |? l]; [intros; discriminate | ]).
destruct l; [ | intros; discriminate].
intros _; compute; auto.
Qed.
Fixpoint cstlist (A:Type)(a:A) n :=
match n with
| O => nil
| S n => a::cstlist _ a n
end.
Lemma i2l_nshiftl : forall n x, n<=size ->
i2l (nshiftl x n) = cstlist _ D0 n ++ firstn (size-n) (i2l x).
Proof.
induction n.
intros.
assert (firstn (size-0) (i2l x) = i2l x).
rewrite <- minus_n_O, <- (i2l_length x).
induction (i2l x); simpl; f_equal; auto.
rewrite H0; clear H0.
reflexivity.
intros.
rewrite nshiftl_S.
unfold shiftl; rewrite i2l_sneakl.
simpl cstlist.
rewrite <- app_comm_cons; f_equal.
rewrite IHn; [ | lia].
rewrite removelast_app.
apply f_equal.
replace (size-n)%nat with (S (size - S n))%nat by lia.
rewrite removelast_firstn; auto.
rewrite i2l_length; lia.
generalize (firstn_length (size-n) (i2l x)).
rewrite i2l_length.
intros H0 H1. rewrite H1 in H0.
rewrite min_l in H0 by lia.
simpl length in H0.
lia.
Qed.
(** [i2l] can be used to define a relation equivalent to [EqShiftL] *)
Lemma EqShiftL_i2l : forall k x y,
EqShiftL k x y <-> firstn (size-k) (i2l x) = firstn (size-k) (i2l y).
Proof.
intros.
destruct (le_lt_dec size k) as [Hle|Hlt].
split; intros.
replace (size-k)%nat with O by lia.
unfold firstn; auto.
apply EqShiftL_size; auto.
unfold EqShiftL.
assert (k <= size) by lia.
split; intros.
assert (i2l (nshiftl x k) = i2l (nshiftl y k)) by (f_equal; auto).
rewrite 2 i2l_nshiftl in H1; auto.
eapply app_inv_head; eauto.
assert (i2l (nshiftl x k) = i2l (nshiftl y k)).
rewrite 2 i2l_nshiftl; auto.
f_equal; auto.
rewrite <- (l2i_i2l (nshiftl x k)), <- (l2i_i2l (nshiftl y k)).
f_equal; auto.
Qed.
(** This equivalence allows proving easily the following delicate
result *)
Lemma EqShiftL_twice_plus_one : forall k x y,
EqShiftL k (twice_plus_one x) (twice_plus_one y) <-> EqShiftL (S k) x y.
Proof.
intros.
destruct (le_lt_dec size k) as [Hle|Hlt].
split; intros; apply EqShiftL_size; auto.
rewrite 2 EqShiftL_i2l.
unfold twice_plus_one.
rewrite 2 i2l_sneakl.
replace (size-k)%nat with (S (size - S k))%nat by lia.
remember (size - S k)%nat as n.
remember (i2l x) as lx.
remember (i2l y) as ly.
simpl.
rewrite 2 firstn_removelast.
split; intros.
injection H; auto.
f_equal; auto.
subst ly n; rewrite i2l_length; lia.
subst lx n; rewrite i2l_length; lia.
Qed.
Lemma EqShiftL_shiftr : forall k x y, EqShiftL k x y ->
EqShiftL (S k) (shiftr x) (shiftr y).
Proof.
intros.
destruct (le_lt_dec size (S k)) as [Hle|Hlt].
apply EqShiftL_size; auto.
case_eq (firstr x); intros.
rewrite <- EqShiftL_twice.
unfold twice; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
lia.
rewrite <- EqShiftL_twice_plus_one.
unfold twice_plus_one; rewrite <- H0.
rewrite <- sneakl_shiftr.
rewrite (EqShiftL_firstr k x y); auto.
rewrite <- sneakl_shiftr; auto.
lia.
Qed.
Lemma EqShiftL_incrbis : forall n k x y, n<=size ->
(n+k=S size)%nat ->
EqShiftL k x y ->
EqShiftL k (incrbis_aux n x) (incrbis_aux n y).
Proof.
induction n; simpl; intros.
red; auto.
destruct (eq_nat_dec k size).
subst k; apply EqShiftL_size; auto.
unfold incrbis_aux; simpl;
fold (incrbis_aux n (shiftr x)); fold (incrbis_aux n (shiftr y)).
rewrite (EqShiftL_firstr k x y); auto; try lia.
case_eq (firstr y); intros.
rewrite EqShiftL_twice_plus_one.
apply EqShiftL_shiftr; auto.
rewrite EqShiftL_twice.
apply IHn; try lia.
apply EqShiftL_shiftr; auto.
Qed.
Lemma EqShiftL_incr : forall x y,
EqShiftL 1 x y -> EqShiftL 1 (incr x) (incr y).
Proof.
intros.
rewrite <- 2 incrbis_aux_equiv.
apply EqShiftL_incrbis; auto.
Qed.
End EqShiftL.
(** * More equations about [incr] *)
Lemma incr_twice_plus_one :
forall x, incr (twice_plus_one x) = twice (incr x).
Proof.
intros.
rewrite incr_eqn2; [ | destruct x; simpl; auto].
apply EqShiftL_incr.
red; destruct x; simpl; auto.
Qed.
Lemma incr_firstr : forall x, firstr (incr x) <> firstr x.
Proof.
intros.
case_eq (firstr x); intros.
rewrite incr_eqn1; auto.
destruct (shiftr x); simpl; discriminate.
rewrite incr_eqn2; auto.
destruct (incr (shiftr x)); simpl; discriminate.
Qed.
Lemma incr_inv : forall x y,
incr x = twice_plus_one y -> x = twice y.
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H0) in *; simpl in *.
change (incr 0) with 1 in H.
symmetry; rewrite twice_zero; auto.
case_eq (firstr x); intros.
rewrite incr_eqn1 in H; auto.
clear H0; destruct x; destruct y; simpl in *.
injection H; intros; subst; auto.
elim (incr_firstr x).
rewrite H1, H; destruct y; simpl; auto.
Qed.
(** * Conversion from [Z] : the [phi_inv] function *)
(** First, recursive equations *)
Lemma phi_inv_double_plus_one : forall z,
phi_inv (Z.succ_double z) = twice_plus_one (phi_inv z).
Proof.
destruct z; simpl; auto.
induction p; simpl.
rewrite 2 incr_twice; auto.
rewrite incr_twice, incr_twice_plus_one.
f_equal.
apply incr_inv; auto.
auto.
Qed.
Lemma phi_inv_double : forall z,
phi_inv (Z.double z) = twice (phi_inv z).
Proof.
destruct z; simpl; auto.
rewrite incr_twice_plus_one; auto.
Qed.
Lemma phi_inv_incr : forall z,
phi_inv (Z.succ z) = incr (phi_inv z).
Proof.
destruct z.
simpl; auto.
simpl; auto.
induction p; simpl; auto.
rewrite <- Pos.add_1_r, IHp, incr_twice_plus_one; auto.
rewrite incr_twice; auto.
simpl; auto.
destruct p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
induction p; simpl; auto.
rewrite incr_twice; auto.
f_equal.
rewrite incr_twice_plus_one; auto.
Qed.
(** [phi_inv o inv], the always-exact and easy-to-prove trip :
from int31 to Z and then back to int31. *)
Lemma phi_inv_phi_aux :
forall n x, n <= size ->
phi_inv (phibis_aux n (nshiftr x (size-n))) =
nshiftr x (size-n).
Proof.
induction n.
intros; simpl minus.
rewrite nshiftr_size; auto.
intros.
unfold phibis_aux, recrbis_aux; fold recrbis_aux;
fold (phibis_aux n (shiftr (nshiftr x (size-S n)))).
assert (shiftr (nshiftr x (size - S n)) = nshiftr x (size-n)).
replace (size - n)%nat with (S (size - (S n))); auto; lia.
rewrite H0.
case_eq (firstr (nshiftr x (size - S n))); intros.
rewrite phi_inv_double.
rewrite IHn by lia.
rewrite <- H0.
remember (nshiftr x (size - S n)) as y.
destruct y; simpl in H1; rewrite H1; auto.
rewrite phi_inv_double_plus_one.
rewrite IHn by lia.
rewrite <- H0.
remember (nshiftr x (size - S n)) as y.
destruct y; simpl in H1; rewrite H1; auto.
Qed.
Lemma phi_inv_phi : forall x, phi_inv (phi x) = x.
Proof.
intros.
rewrite <- phibis_aux_equiv.
replace x with (nshiftr x (size - size)) by auto.
apply phi_inv_phi_aux; auto.
Qed.
(** The other composition [phi o phi_inv] is harder to prove correct.
In particular, an overflow can happen, so a modulo is needed.
For the moment, we proceed via several steps, the first one
being a detour to [positive_to_in31]. *)
(** * [positive_to_int31] *)
(** A variant of [p2i] with [twice] and [twice_plus_one] instead of
[2*i] and [2*i+1] *)
Fixpoint p2ibis n p : (N*int31)%type :=
match n with
| O => (Npos p, On)
| S n => match p with
| xO p => let (r,i) := p2ibis n p in (r, twice i)
| xI p => let (r,i) := p2ibis n p in (r, twice_plus_one i)
| xH => (N0, In)
end
end.
Lemma p2ibis_bounded : forall n p,
nshiftr (snd (p2ibis n p)) n = 0.
Proof.
induction n.
simpl; intros; auto.
simpl p2ibis; intros.
destruct p; simpl snd.
specialize IHn with p.
destruct (p2ibis n p). simpl @snd in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n) as [Hle|Hlt].
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ Hlt IHn).
replace (shiftr (twice_plus_one i)) with i; auto.
destruct i; simpl in *. rewrite H; auto.
specialize IHn with p.
destruct (p2ibis n p); simpl @snd in *.
rewrite nshiftr_S_tail.
destruct (le_lt_dec size n) as [Hle|Hlt].
rewrite nshiftr_above_size; auto.
assert (H:=nshiftr_0_firstl _ _ Hlt IHn).
replace (shiftr (twice i)) with i; auto.
destruct i; simpl in *; rewrite H; auto.
rewrite nshiftr_S_tail; auto.
replace (shiftr In) with 0; auto.
apply nshiftr_n_0.
Qed.
Local Open Scope Z_scope.
Lemma p2ibis_spec : forall n p, (n<=size)%nat ->
Zpos p = (Z.of_N (fst (p2ibis n p)))*2^(Z.of_nat n) +
phi (snd (p2ibis n p)).
Proof.
induction n; intros.
simpl; rewrite Pos.mul_1_r; auto.
replace (2^(Z.of_nat (S n)))%Z with (2*2^(Z.of_nat n))%Z by
(rewrite <- Z.pow_succ_r, <- Zpos_P_of_succ_nat;
auto with zarith).
rewrite (Z.mul_comm 2).
assert (n<=size)%nat by lia.
destruct p; simpl; [ | | auto];
specialize (IHn p H0);
generalize (p2ibis_bounded n p);
destruct (p2ibis n p) as (r,i); simpl in *; intros.
change (Zpos p~1) with (2*Zpos p + 1)%Z.
rewrite phi_twice_plus_one_firstl, Z.succ_double_spec.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try lia.
change (Zpos p~0) with (2*Zpos p)%Z.
rewrite phi_twice_firstl.
change (Z.double (phi i)) with (2*(phi i))%Z.
rewrite IHn; ring.
apply (nshiftr_0_firstl n); auto; try lia.
Qed.
(** We now prove that this [p2ibis] is related to [phi_inv_positive] *)
Lemma phi_inv_positive_p2ibis : forall n p, (n<=size)%nat ->
EqShiftL (size-n) (phi_inv_positive p) (snd (p2ibis n p)).
Proof.
induction n.
intros.
apply EqShiftL_size; auto.
intros.
simpl p2ibis; destruct p; [ | | red; auto];
specialize IHn with p;
destruct (p2ibis n p); simpl @snd in *; simpl phi_inv_positive;
rewrite ?EqShiftL_twice_plus_one, ?EqShiftL_twice;
replace (S (size - S n))%nat with (size - n)%nat by lia;
apply IHn; lia.
Qed.
(** This gives the expected result about [phi o phi_inv], at least
for the positive case. *)
Lemma phi_phi_inv_positive : forall p,
phi (phi_inv_positive p) = (Zpos p) mod (2^(Z.of_nat size)).
Proof.
intros.
replace (phi_inv_positive p) with (snd (p2ibis size p)).
rewrite (p2ibis_spec size p) by auto.
rewrite Z.add_comm, Z_mod_plus.
symmetry; apply Zmod_small.
apply phi_bounded.
auto with zarith.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size p); auto.
Qed.
(** Moreover, [p2ibis] is also related with [p2i] and hence with
[positive_to_int31]. *)
Lemma double_twice_firstl : forall x, firstl x = D0 ->
(Twon*x = twice x)%int31.
Proof.
intros.
unfold mul31.
rewrite <- Z.double_spec, <- phi_twice_firstl, phi_inv_phi; auto.
Qed.
Lemma double_twice_plus_one_firstl : forall x, firstl x = D0 ->
(Twon*x+In = twice_plus_one x)%int31.
Proof.
intros.
rewrite double_twice_firstl; auto.
unfold add31.
rewrite phi_twice_firstl, <- Z.succ_double_spec,
<- phi_twice_plus_one_firstl, phi_inv_phi; auto.
Qed.
Lemma p2i_p2ibis : forall n p, (n<=size)%nat ->
p2i n p = p2ibis n p.
Proof.
induction n; simpl; auto; intros.
destruct p; auto; specialize IHn with p;
generalize (p2ibis_bounded n p);
rewrite IHn; try lia; destruct (p2ibis n p); simpl; intros;
f_equal; auto.
apply double_twice_plus_one_firstl.
apply (nshiftr_0_firstl n); auto; lia.
apply double_twice_firstl.
apply (nshiftr_0_firstl n); auto; lia.
Qed.
Lemma positive_to_int31_phi_inv_positive : forall p,
snd (positive_to_int31 p) = phi_inv_positive p.
Proof.
intros; unfold positive_to_int31.
rewrite p2i_p2ibis; auto.
symmetry.
rewrite <- EqShiftL_zero.
apply (phi_inv_positive_p2ibis size); auto.
Qed.
Lemma positive_to_int31_spec : forall p,
Zpos p = (Z.of_N (fst (positive_to_int31 p)))*2^(Z.of_nat size) +
phi (snd (positive_to_int31 p)).
Proof.
unfold positive_to_int31.
intros; rewrite p2i_p2ibis; auto.
apply p2ibis_spec; auto.
Qed.
(** Thanks to the result about [phi o phi_inv_positive], we can
now establish easily the most general results about
[phi o twice] and so one. *)
Lemma phi_twice : forall x,
phi (twice x) = (Z.double (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double.
assert (0 <= Z.double (phi x)).
rewrite Z.double_spec; generalize (phi_bounded x); lia.
destruct (Z.double (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_twice_plus_one : forall x,
phi (twice_plus_one x) = (Z.succ_double (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_double_plus_one.
assert (0 <= Z.succ_double (phi x)).
rewrite Z.succ_double_spec; generalize (phi_bounded x); lia.
destruct (Z.succ_double (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
Lemma phi_incr : forall x,
phi (incr x) = (Z.succ (phi x)) mod 2^(Z.of_nat size).
Proof.
intros.
pattern x at 1; rewrite <- (phi_inv_phi x).
rewrite <- phi_inv_incr.
assert (0 <= Z.succ (phi x)).
change (Z.succ (phi x)) with ((phi x)+1)%Z;
generalize (phi_bounded x); lia.
destruct (Z.succ (phi x)).
simpl; auto.
apply phi_phi_inv_positive.
compute in H; elim H; auto.
Qed.
(** With the previous results, we can deal with [phi o phi_inv] even
in the negative case *)
Lemma phi_phi_inv_negative :
forall p, phi (incr (complement_negative p)) = (Zneg p) mod 2^(Z.of_nat size).
Proof.
induction p.
simpl complement_negative.
rewrite phi_incr in IHp.
rewrite incr_twice, phi_twice_plus_one.
remember (phi (complement_negative p)) as q.
rewrite Z.succ_double_spec.
replace (2*q+1) with (2*(Z.succ q)-1) by lia.
rewrite <- Zminus_mod_idemp_l, <- Zmult_mod_idemp_r, IHp.
rewrite Zmult_mod_idemp_r, Zminus_mod_idemp_l; auto with zarith.
simpl complement_negative.
rewrite incr_twice_plus_one, phi_twice.
remember (phi (incr (complement_negative p))) as q.
rewrite Z.double_spec, IHp, Zmult_mod_idemp_r; auto with zarith.
simpl; auto.
Qed.
Lemma phi_phi_inv :
forall z, phi (phi_inv z) = z mod 2 ^ (Z.of_nat size).
Proof.
destruct z.
simpl; auto.
apply phi_phi_inv_positive.
apply phi_phi_inv_negative.
Qed.
End Basics.
Instance int31_ops : ZnZ.Ops int31 :=
{
digits := 31%positive; (* number of digits *)
zdigits := 31; (* number of digits *)
to_Z := phi; (* conversion to Z *)
of_pos := positive_to_int31; (* positive -> N*int31 : p => N,i
where p = N*2^31+phi i *)
head0 := head031; (* number of head 0 *)
tail0 := tail031; (* number of tail 0 *)
zero := 0;
one := 1;
minus_one := Tn; (* 2^31 - 1 *)
compare := compare31;
eq0 := fun i => match i ?= 0 with Eq => true | _ => false end;
opp_c := fun i => 0 -c i;
opp := opp31;
opp_carry := fun i => 0-i-1;
succ_c := fun i => i +c 1;
add_c := add31c;
add_carry_c := add31carryc;
succ := fun i => i + 1;
add := add31;
add_carry := fun i j => i + j + 1;
pred_c := fun i => i -c 1;
sub_c := sub31c;
sub_carry_c := sub31carryc;
pred := fun i => i - 1;
sub := sub31;
sub_carry := fun i j => i - j - 1;
mul_c := mul31c;
mul := mul31;
square_c := fun x => x *c x;
div21 := div3121;
div_gt := div31; (* this is supposed to be the special case of
division a/b where a > b *)
div := div31;
modulo_gt := fun i j => let (_,r) := i/j in r;
modulo := fun i j => let (_,r) := i/j in r;
gcd_gt := gcd31;
gcd := gcd31;
add_mul_div := addmuldiv31;
pos_mod := (* modulo 2^p *)
fun p i =>
match p ?= 31 with
| Lt => addmuldiv31 p 0 (addmuldiv31 (31-p) i 0)
| _ => i
end;
is_even :=
fun i => let (_,r) := i/2 in
match r ?= 0 with Eq => true | _ => false end;
sqrt2 := sqrt312;
sqrt := sqrt31;
lor := lor31;
land := land31;
lxor := lxor31
}.
Section Int31_Specs.
Local Open Scope Z_scope.
Notation "[| x |]" := (phi x) (at level 0, x at level 99).
Local Notation wB := (2 ^ (Z.of_nat size)).
Lemma wB_pos : wB > 0.
Proof.
auto with zarith.
Qed.
Notation "[+| c |]" :=
(interp_carry 1 wB phi c) (at level 0, c at level 99).
Notation "[-| c |]" :=
(interp_carry (-1) wB phi c) (at level 0, c at level 99).
Notation "[|| x ||]" :=
(zn2z_to_Z wB phi x) (at level 0, x at level 99).
Lemma spec_zdigits : [| 31 |] = 31.
Proof.
reflexivity.
Qed.
Lemma spec_more_than_1_digit: 1 < 31.
Proof. reflexivity. Qed.
Lemma spec_0 : [| 0 |] = 0.
Proof.
reflexivity.
Qed.
Lemma spec_1 : [| 1 |] = 1.
Proof.
reflexivity.
Qed.
Lemma spec_m1 : [| Tn |] = wB - 1.
Proof.
reflexivity.
Qed.
Lemma spec_compare : forall x y,
(x ?= y)%int31 = ([|x|] ?= [|y|]).
Proof. reflexivity. Qed.
(** Addition *)
Lemma spec_add_c : forall x y, [+|add31c x y|] = [|x|] + [|y|].
Proof.
intros; unfold add31c, add31, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y) mod wB ?= X+Y <> Eq -> [+|C1 (phi_inv (X+Y))|] = X+Y).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X+Y) wB).
contradict H1; apply Zmod_small; lia.
rewrite <- (Z_mod_plus_full (X+Y) (-1) wB).
rewrite Zmod_small; lia.
generalize (Z.compare_eq ((X+Y) mod wB) (X+Y)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_succ_c : forall x, [+|add31c x 1|] = [|x|] + 1.
Proof.
intros; apply spec_add_c.
Qed.
Lemma spec_add_carry_c : forall x y, [+|add31carryc x y|] = [|x|] + [|y|] + 1.
Proof.
intros.
unfold add31carryc, interp_carry; rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X+Y+1) mod wB ?= X+Y+1 <> Eq -> [+|C1 (phi_inv (X+Y+1))|] = X+Y+1).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X+Y+1) wB).
contradict H1; apply Zmod_small; lia.
rewrite <- (Z_mod_plus_full (X+Y+1) (-1) wB).
rewrite Zmod_small; lia.
generalize (Z.compare_eq ((X+Y+1) mod wB) (X+Y+1)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_add : forall x y, [|x+y|] = ([|x|] + [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_add_carry :
forall x y, [|x+y+1|] = ([|x|] + [|y|] + 1) mod wB.
Proof.
unfold add31; intros.
repeat rewrite phi_phi_inv.
apply Zplus_mod_idemp_l.
Qed.
Lemma spec_succ : forall x, [|x+1|] = ([|x|] + 1) mod wB.
Proof.
intros; rewrite <- spec_1; apply spec_add.
Qed.
(** Subtraction *)
Lemma spec_sub_c : forall x y, [-|sub31c x y|] = [|x|] - [|y|].
Proof.
unfold sub31c, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y) mod wB ?= X-Y <> Eq -> [-|C1 (phi_inv (X-Y))|] = X-Y).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X-Y) 0).
rewrite <- (Z_mod_plus_full (X-Y) 1 wB).
rewrite Zmod_small; lia.
contradict H1; apply Zmod_small; lia.
generalize (Z.compare_eq ((X-Y) mod wB) (X-Y)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub_carry_c : forall x y, [-|sub31carryc x y|] = [|x|] - [|y|] - 1.
Proof.
unfold sub31carryc, sub31, interp_carry; intros.
rewrite phi_phi_inv.
generalize (phi_bounded x)(phi_bounded y); intros.
set (X:=[|x|]) in *; set (Y:=[|y|]) in *; clearbody X Y.
assert ((X-Y-1) mod wB ?= X-Y-1 <> Eq -> [-|C1 (phi_inv (X-Y-1))|] = X-Y-1).
unfold interp_carry; rewrite phi_phi_inv, Z.compare_eq_iff; intros.
destruct (Z_lt_le_dec (X-Y-1) 0).
rewrite <- (Z_mod_plus_full (X-Y-1) 1 wB).
rewrite Zmod_small; lia.
contradict H1; apply Zmod_small; lia.
generalize (Z.compare_eq ((X-Y-1) mod wB) (X-Y-1)); intros Heq.
destruct Z.compare; intros;
[ rewrite phi_phi_inv; auto | now apply H1 | now apply H1].
Qed.
Lemma spec_sub : forall x y, [|x-y|] = ([|x|] - [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_sub_carry :
forall x y, [|x-y-1|] = ([|x|] - [|y|] - 1) mod wB.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
apply Zminus_mod_idemp_l.
Qed.
Lemma spec_opp_c : forall x, [-|sub31c 0 x|] = -[|x|].
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_opp : forall x, [|0 - x|] = (-[|x|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_opp_carry : forall x, [|0 - x - 1|] = wB - [|x|] - 1.
Proof.
unfold sub31; intros.
repeat rewrite phi_phi_inv.
change [|1|] with 1; change [|0|] with 0.
rewrite <- (Z_mod_plus_full (0-[|x|]) 1 wB).
rewrite Zminus_mod_idemp_l.
rewrite Zmod_small; generalize (phi_bounded x); lia.
Qed.
Lemma spec_pred_c : forall x, [-|sub31c x 1|] = [|x|] - 1.
Proof.
intros; apply spec_sub_c.
Qed.
Lemma spec_pred : forall x, [|x-1|] = ([|x|] - 1) mod wB.
Proof.
intros; apply spec_sub.
Qed.
(** Multiplication *)
Lemma phi2_phi_inv2 : forall x, [||phi_inv2 x||] = x mod (wB^2).
Proof.
assert (forall z, (z / wB) mod wB * wB + z mod wB = z mod wB ^ 2).
intros.
assert ((z/wB) mod wB = z/wB - (z/wB/wB)*wB).
rewrite (Z_div_mod_eq (z/wB) wB wB_pos) at 2; ring.
assert (z mod wB = z - (z/wB)*wB).
rewrite (Z_div_mod_eq z wB wB_pos) at 2; ring.
rewrite H.
rewrite H0 at 1.
ring_simplify.
rewrite Zdiv_Zdiv; auto with zarith.
rewrite (Z_div_mod_eq z (wB*wB)) at 2; auto with zarith.
change (wB*wB) with (wB^2); ring.
unfold phi_inv2.
destruct x; unfold zn2z_to_Z; rewrite ?phi_phi_inv;
change base with wB; auto.
Qed.
Lemma spec_mul_c : forall x y, [|| mul31c x y ||] = [|x|] * [|y|].
Proof.
unfold mul31c; intros.
rewrite phi2_phi_inv2.
apply Zmod_small.
generalize (phi_bounded x)(phi_bounded y); intros.
nia.
Qed.
Lemma spec_mul : forall x y, [|x*y|] = ([|x|] * [|y|]) mod wB.
Proof.
intros; apply phi_phi_inv.
Qed.
Lemma spec_square_c : forall x, [|| mul31c x x ||] = [|x|] * [|x|].
Proof.
intros; apply spec_mul_c.
Qed.
(** Division *)
Lemma spec_div21 : forall a1 a2 b,
wB/2 <= [|b|] ->
[|a1|] < [|b|] ->
let (q,r) := div3121 a1 a2 b in
[|a1|] *wB+ [|a2|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div3121; intros.
generalize (phi_bounded a1)(phi_bounded a2)(phi_bounded b); intros.
assert ([|b|]>0) by lia.
generalize (Z_div_mod (phi2 a1 a2) [|b|] H4) (Z_div_pos (phi2 a1 a2) [|b|] H4).
unfold Z.div; destruct (Z.div_eucl (phi2 a1 a2) [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
unfold phi2 in *.
change base with wB; change base with wB in H5.
change (Z.pow_pos 2 31) with wB; change (Z.pow_pos 2 31) with wB in H.
rewrite H5, Z.mul_comm.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; lia).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split.
apply H7; change base with wB. nia.
apply Z.mul_lt_mono_pos_r with [|b|]; [lia| ].
rewrite Z.mul_comm.
apply Z.le_lt_trans with ([|b|]*z+z0); [lia| ].
rewrite <- H5.
apply Z.le_lt_trans with ([|a1|]*wB+(wB-1)); [lia | ].
replace ([|a1|]*wB+(wB-1)) with (wB*([|a1|]+1)-1) by ring.
assert (wB*([|a1|]+1) <= wB*[|b|]); try lia.
apply Z.mul_le_mono_nonneg; lia.
Qed.
Lemma spec_div : forall a b, 0 < [|b|] ->
let (q,r) := div31 a b in
[|a|] = [|q|] * [|b|] + [|r|] /\
0 <= [|r|] < [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
generalize (Z_div_mod [|a|] [|b|] H0) (Z_div_pos [|a|] [|b|] H0).
unfold Z.div; destruct (Z.div_eucl [|a|] [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
rewrite H1, Z.mul_comm.
generalize (phi_bounded a)(phi_bounded b); intros.
replace (z0 mod wB) with z0 by (symmetry; apply Zmod_small; lia).
replace (z mod wB) with z; auto with zarith.
symmetry; apply Zmod_small.
split. lia.
apply Z.le_lt_trans with [|a|]. 2: lia.
rewrite H1.
apply Z.le_trans with ([|b|]*z); try lia.
rewrite <- (Z.mul_1_l z) at 1.
nia.
Qed.
Lemma spec_mod : forall a b, 0 < [|b|] ->
[|let (_,r) := (a/b)%int31 in r|] = [|a|] mod [|b|].
Proof.
unfold div31; intros.
assert ([|b|]>0) by (auto with zarith).
unfold Z.modulo.
generalize (Z_div_mod [|a|] [|b|] H0).
destruct (Z.div_eucl [|a|] [|b|]).
rewrite ?phi_phi_inv.
destruct 1; intros.
generalize (phi_bounded b); intros.
apply Zmod_small; lia.
Qed.
Lemma phi_gcd : forall i j,
[|gcd31 i j|] = Zgcdn (2*size) [|j|] [|i|].
Proof.
unfold gcd31.
induction (2*size)%nat; intros.
reflexivity.
simpl euler.
unfold compare31.
change [|On|] with 0.
generalize (phi_bounded j)(phi_bounded i); intros.
case_eq [|j|]; intros.
simpl; intros.
generalize (Zabs_spec [|i|]); lia.
simpl. rewrite IHn, H1; f_equal.
rewrite spec_mod, H1; auto.
rewrite H1; compute; auto.
rewrite H1 in H; destruct H as [H _]; compute in H; elim H; auto.
Qed.
Lemma spec_gcd : forall a b, Zis_gcd [|a|] [|b|] [|gcd31 a b|].
Proof.
intros.
rewrite phi_gcd.
apply Zis_gcd_sym.
apply Zgcdn_is_gcd.
unfold Zgcd_bound.
generalize (phi_bounded b).
destruct [|b|].
unfold size; lia.
intros (_,H).
cut (Pos.size_nat p <= size)%nat; [ lia | rewrite <- Zpower2_Psize; auto].
intros (H,_); compute in H; elim H; auto.
Qed.
Lemma iter_int31_iter_nat : forall A f i a,
iter_int31 i A f a = iter_nat (Z.abs_nat [|i|]) A f a.
Proof.
intros.
unfold iter_int31.
rewrite <- recrbis_equiv; auto; unfold recrbis.
rewrite <- phibis_aux_equiv.
revert i a; induction size.
simpl; auto.
simpl; intros.
case_eq (firstr i); intros H; rewrite 2 IHn;
unfold phibis_aux; simpl; rewrite ?H; fold (phibis_aux n (shiftr i));
generalize (phibis_aux_pos n (shiftr i)); intros;
set (z := phibis_aux n (shiftr i)) in *; clearbody z;
rewrite <- nat_rect_plus.
f_equal.
rewrite Z.double_spec, <- Z.add_diag.
symmetry; apply Zabs2Nat.inj_add; auto with zarith.
change (iter_nat (S (Z.abs_nat z) + (Z.abs_nat z))%nat A f a =
iter_nat (Z.abs_nat (Z.succ_double z)) A f a); f_equal.
rewrite Z.succ_double_spec, <- Z.add_diag.
lia.
Qed.
Fixpoint addmuldiv31_alt n i j :=
match n with
| O => i
| S n => addmuldiv31_alt n (sneakl (firstl j) i) (shiftl j)
end.
Lemma addmuldiv31_equiv : forall p x y,
addmuldiv31 p x y = addmuldiv31_alt (Z.abs_nat [|p|]) x y.
Proof.
intros.
unfold addmuldiv31.
rewrite iter_int31_iter_nat.
set (n:=Z.abs_nat [|p|]); clearbody n; clear p.
revert x y; induction n.
simpl; auto.
intros.
simpl addmuldiv31_alt.
replace (S n) with (n+1)%nat by (rewrite plus_comm; auto).
rewrite nat_rect_plus; simpl; auto.
Qed.
Lemma spec_add_mul_div : forall x y p, [|p|] <= Zpos 31 ->
[| addmuldiv31 p x y |] =
([|x|] * (2 ^ [|p|]) + [|y|] / (2 ^ ((Zpos 31) - [|p|]))) mod wB.
Proof.
intros.
rewrite addmuldiv31_equiv.
assert ([|p|] = Z.of_nat (Z.abs_nat [|p|])).
rewrite Zabs2Nat.id_abs; symmetry; apply Z.abs_eq.
destruct (phi_bounded p); auto.
rewrite H0; rewrite H0 in H; clear H0; rewrite Zabs2Nat.id.
set (n := Z.abs_nat [|p|]) in *; clearbody n.
assert (n <= 31)%nat.
rewrite Nat2Z.inj_le; auto with zarith.
clear p H; revert x y.
induction n.
simpl Z.of_nat; intros.
rewrite Z.mul_1_r.
replace ([|y|] / 2^(31-0)) with 0.
rewrite Z.add_0_r.
symmetry; apply Zmod_small; apply phi_bounded.
symmetry; apply Zdiv_small; apply phi_bounded.
simpl addmuldiv31_alt; intros.
rewrite IHn; [ | lia ].
case_eq (firstl y); intros.
rewrite phi_twice, Z.double_spec.
rewrite phi_twice_firstl; auto.
change (Z.double [|y|]) with (2*[|y|]).
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
f_equal.
f_equal.
ring.
replace (31-Z.of_nat n) with (Z.succ(31-Z.succ(Z.of_nat n))) by ring.
rewrite Z.pow_succ_r, <- Zdiv_Zdiv.
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
lia. auto with zarith. lia.
rewrite phi_twice_plus_one, Z.succ_double_spec.
rewrite phi_twice; auto.
change (Z.double [|y|]) with (2*[|y|]).
rewrite Nat2Z.inj_succ, Z.pow_succ_r; auto with zarith.
rewrite Zplus_mod; rewrite Zmult_mod_idemp_l; rewrite <- Zplus_mod.
rewrite Z.mul_add_distr_r, Z.mul_1_l, <- Z.add_assoc.
f_equal.
f_equal.
ring.
assert ((2*[|y|]) mod wB = 2*[|y|] - wB).
clear - H. symmetry. apply Zmod_unique with 1; [ | ring ].
generalize (phi_lowerbound _ H) (phi_bounded y).
set (wB' := 2^Z.of_nat (pred size)).
replace wB with (2*wB'); [ lia | ].
unfold wB'. rewrite <- Z.pow_succ_r, <- Nat2Z.inj_succ by (auto with zarith).
f_equal.
rewrite H1.
replace wB with (2^(Z.of_nat n)*2^(31-Z.of_nat n)) by
(rewrite <- Zpower_exp by lia; f_equal; unfold size; ring).
unfold Z.sub; rewrite <- Z.mul_opp_l.
rewrite Z_div_plus.
ring_simplify.
replace (31+-Z.of_nat n) with (Z.succ(31-Z.succ(Z.of_nat n))) by ring.
rewrite Z.pow_succ_r, <- Zdiv_Zdiv.
rewrite Z.mul_comm, Z_div_mult; auto with zarith.
lia. auto with zarith. lia.
apply Z.lt_gt; apply Z.pow_pos_nonneg; lia.
Qed.
Lemma shift_unshift_mod_2 : forall n p a, 0 <= p <= n ->
((a * 2 ^ (n - p)) mod (2^n) / 2 ^ (n - p)) mod (2^n) =
a mod 2 ^ p.
Proof.
intros n p a H.
assert (2 ^ n > 0 /\ 2 ^ p > 0 /\ 2 ^ (n - p) > 0) as [ X [ Y Z ] ]
by (split; [ | split ]; apply Z.lt_gt, Z.pow_pos_nonneg; lia).
rewrite Zmod_small.
rewrite Zmod_eq by assumption.
unfold Z.sub at 1.
rewrite Z_div_plus_full_l by lia.
assert (2^n = 2^(n-p)*2^p).
rewrite <- Zpower_exp by lia.
replace (n-p+p) with n; lia.
rewrite H0.
rewrite <- Zdiv_Zdiv, Z_div_mult; auto with zarith.
rewrite (Z.mul_comm (2^(n-p))), Z.mul_assoc.
rewrite <- Z.mul_opp_l.
rewrite Z_div_mult by assumption.
symmetry; apply Zmod_eq; auto with zarith.
remember (a * 2 ^ (n - p)) as b.
destruct (Z_mod_lt b (2^n)); auto with zarith.
split.
apply Z_div_pos; auto with zarith.
apply Zdiv_lt_upper_bound. lia.
nia.
Qed.
Lemma spec_pos_mod : forall w p,
[|ZnZ.pos_mod p w|] = [|w|] mod (2 ^ [|p|]).
Proof.
unfold int31_ops, ZnZ.pos_mod, compare31.
change [|31|] with 31%Z.
assert (forall w p, 31<=p -> [|w|] = [|w|] mod 2^p).
intros.
generalize (phi_bounded w).
symmetry; apply Zmod_small.
split. lia.
apply Z.lt_le_trans with wB. lia.
apply Zpower_le_monotone; auto with zarith.
intros.
case_eq ([|p|] ?= 31); intros;
[ apply H; rewrite (Z.compare_eq _ _ H0); auto with zarith | |
apply H; change ([|p|]>31)%Z in H0; lia ].
change ([|p|]<31) in H0.
rewrite spec_add_mul_div by lia.
change [|0|] with 0%Z; rewrite Z.mul_0_l, Z.add_0_l.
generalize (phi_bounded p)(phi_bounded w); intros.
assert (31-[|p|]<wB).
apply Z.le_lt_trans with 31%Z. lia.
compute; auto.
assert ([|31-p|]=31-[|p|]).
unfold sub31; rewrite phi_phi_inv.
change [|31|] with 31%Z.
apply Zmod_small. lia.
rewrite spec_add_mul_div by (rewrite H4; lia).
change [|0|] with 0%Z; rewrite Zdiv_0_l, Z.add_0_r.
rewrite H4.
apply shift_unshift_mod_2; simpl; lia.
Qed.
(** Shift operations *)
Lemma spec_head00: forall x, [|x|] = 0 -> [|head031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl phi_inv.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint head031_alt n x :=
match n with
| O => 0%nat
| S n => match firstl x with
| D0 => S (head031_alt n (shiftl x))
| D1 => 0%nat
end
end.
Lemma head031_equiv :
forall x, [|head031 x|] = Z.of_nat (head031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold head031, recl.
change On with (phi_inv (Z.of_nat (31-size))).
replace (head031_alt size x) with
(head031_alt size x + (31 - size))%nat by auto.
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recl_aux; fold recl_aux.
unfold head031_alt; fold head031_alt.
rewrite H.
assert ([|phi_inv (Z.of_nat (31-S n))|] = Z.of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z.of_nat O); apply inj_le; lia.
apply Z.le_lt_trans with (Z.of_nat 31).
apply inj_le; lia.
compute; auto.
case_eq (firstl x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by lia.
rewrite <- IHn; [ | lia | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by lia.
rewrite Nat2Z.inj_succ; ring.
clear - H H2.
rewrite (sneakr_shiftl x) in H.
rewrite H2 in H.
case_eq (iszero (shiftl x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma phi_nz : forall x, 0 < [|x|] <-> x <> 0%int31.
Proof.
split; intros.
red; intro; subst x; discriminate.
assert ([|x|]<>0%Z).
contradict H.
rewrite <- (phi_inv_phi x); rewrite H; auto.
generalize (phi_bounded x); lia.
Qed.
Lemma spec_head0 : forall x, 0 < [|x|] ->
wB/ 2 <= 2 ^ ([|head031 x|]) * [|x|] < wB.
Proof.
intros.
rewrite head031_equiv.
assert (nshiftl x size = 0%int31).
apply nshiftl_size.
revert x H H0.
unfold size at 2 5.
induction size.
simpl Z.of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl head031_alt.
case_eq (firstl x); intros.
rewrite (Nat2Z.inj_succ (head031_alt n (shiftl x))), Z.pow_succ_r; auto with zarith.
rewrite <- Z.mul_assoc, Z.mul_comm, <- Z.mul_assoc, <-(Z.mul_comm 2).
rewrite <- Z.double_spec, <- (phi_twice_firstl _ H1).
apply IHn.
rewrite phi_nz; rewrite phi_nz in H; contradict H.
change twice with shiftl in H.
rewrite (sneakr_shiftl x), H1, H; auto.
rewrite <- nshiftl_S_tail; auto.
change (2^(Z.of_nat 0)) with 1; rewrite Z.mul_1_l.
generalize (phi_bounded x); unfold size; split. 2: lia.
change (2^(Z.of_nat 31)/2) with (2^(Z.of_nat (pred size))).
apply phi_lowerbound; auto.
Qed.
Lemma spec_tail00: forall x, [|x|] = 0 -> [|tail031 x|] = Zpos 31.
Proof.
intros.
generalize (phi_inv_phi x).
rewrite H; simpl phi_inv.
intros H'; rewrite <- H'.
simpl; auto.
Qed.
Fixpoint tail031_alt n x :=
match n with
| O => 0%nat
| S n => match firstr x with
| D0 => S (tail031_alt n (shiftr x))
| D1 => 0%nat
end
end.
Lemma tail031_equiv :
forall x, [|tail031 x|] = Z.of_nat (tail031_alt size x).
Proof.
intros.
case_eq (iszero x); intros.
rewrite (iszero_eq0 _ H).
simpl; auto.
unfold tail031, recr.
change On with (phi_inv (Z.of_nat (31-size))).
replace (tail031_alt size x) with
(tail031_alt size x + (31 - size))%nat by auto.
assert (size <= 31)%nat by auto with arith.
revert x H; induction size; intros.
simpl; auto.
unfold recr_aux; fold recr_aux.
unfold tail031_alt; fold tail031_alt.
rewrite H.
assert ([|phi_inv (Z.of_nat (31-S n))|] = Z.of_nat (31 - S n)).
rewrite phi_phi_inv.
apply Zmod_small.
split.
change 0 with (Z.of_nat O); apply inj_le; lia.
apply Z.le_lt_trans with (Z.of_nat 31).
apply inj_le; lia.
compute; auto.
case_eq (firstr x); intros; auto.
rewrite plus_Sn_m, plus_n_Sm.
replace (S (31 - S n)) with (31 - n)%nat by lia.
rewrite <- IHn; [ | lia | ].
f_equal; f_equal.
unfold add31.
rewrite H1.
f_equal.
change [|In|] with 1.
replace (31-n)%nat with (S (31 - S n))%nat by lia.
rewrite Nat2Z.inj_succ; ring.
clear - H H2.
rewrite (sneakl_shiftr x) in H.
rewrite H2 in H.
case_eq (iszero (shiftr x)); intros; auto.
rewrite (iszero_eq0 _ H0) in H; discriminate.
Qed.
Lemma spec_tail0 : forall x, 0 < [|x|] ->
exists y, 0 <= y /\ [|x|] = (2 * y + 1) * (2 ^ [|tail031 x|]).
Proof.
intros.
rewrite tail031_equiv.
assert (nshiftr x size = 0%int31).
apply nshiftr_size.
revert x H H0.
induction size.
simpl Z.of_nat.
intros.
compute in H0; rewrite H0 in H; discriminate.
intros.
simpl tail031_alt.
case_eq (firstr x); intros.
rewrite (Nat2Z.inj_succ (tail031_alt n (shiftr x))), Z.pow_succ_r; auto with zarith.
destruct (IHn (shiftr x)) as (y & Hy1 & Hy2).
rewrite phi_nz; rewrite phi_nz in H; contradict H.
rewrite (sneakl_shiftr x), H1, H; auto.
rewrite <- nshiftr_S_tail; auto.
exists y; split; auto.
rewrite phi_eqn1; auto.
rewrite Z.double_spec, Hy2; ring.
exists [|shiftr x|].
split.
generalize (phi_bounded (shiftr x)); lia.
rewrite phi_eqn2; auto.
rewrite Z.succ_double_spec; simpl; ring.
Qed.
(* Sqrt *)
(* Direct transcription of an old proof
of a fortran program in boyer-moore *)
Lemma quotient_by_2 a: a - 1 <= (a/2) + (a/2).
Proof.
case (Z_mod_lt a 2); auto with zarith.
intros H1; rewrite Zmod_eq_full; lia.
Qed.
Lemma sqrt_main_trick j k: 0 <= j -> 0 <= k ->
(j * k) + j <= ((j + k)/2 + 1) ^ 2.
Proof.
intros Hj; generalize Hj k; pattern j; apply natlike_ind;
auto; clear k j Hj.
intros _ k Hk; repeat rewrite Z.add_0_l.
apply Z.mul_nonneg_nonneg; generalize (Z_div_pos k 2); auto with zarith.
intros j Hj Hrec _ k Hk; pattern k; apply natlike_ind; auto; clear k Hk.
rewrite Z.mul_0_r, Z.add_0_r, Z.add_0_l.
generalize (sqr_pos (Z.succ j / 2)) (quotient_by_2 (Z.succ j));
unfold Z.succ.
rewrite Z.pow_2_r, Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
lia.
intros k Hk _.
replace ((Z.succ j + Z.succ k) / 2) with ((j + k)/2 + 1).
generalize (Hrec Hj k Hk) (quotient_by_2 (j + k)).
unfold Z.succ; repeat rewrite Z.pow_2_r;
repeat rewrite Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
repeat rewrite Z.mul_1_l; repeat rewrite Z.mul_1_r.
lia.
rewrite Z.add_comm, <- Z_div_plus_full_l by lia.
apply f_equal2 with (f := Z.div); lia.
Qed.
Lemma sqrt_main i j: 0 <= i -> 0 < j -> i < ((j + (i/j))/2 + 1) ^ 2.
Proof.
intros Hi Hj.
assert (Hij: 0 <= i/j) by (apply Z_div_pos; auto with zarith).
apply Z.lt_le_trans with (2 := sqrt_main_trick _ _ (Z.lt_le_incl _ _ Hj) Hij).
pattern i at 1; rewrite (Z_div_mod_eq i j); case (Z_mod_lt i j); auto with zarith.
Qed.
Lemma sqrt_init i: 1 < i -> i < (i/2 + 1) ^ 2.
Proof.
intros Hi.
assert (H1: 0 <= i - 2) by lia.
assert (H2: 1 <= (i / 2) ^ 2).
replace i with (1* 2 + (i - 2)) by lia.
rewrite Z.pow_2_r, Z_div_plus_full_l by lia.
generalize (sqr_pos ((i - 2)/ 2)) (Z_div_pos (i - 2) 2).
rewrite Z.mul_add_distr_r; repeat rewrite Z.mul_add_distr_l.
lia.
generalize (quotient_by_2 i).
rewrite Z.pow_2_r in H2 |- *;
repeat (rewrite Z.mul_add_distr_r ||
rewrite Z.mul_add_distr_l ||
rewrite Z.mul_1_l || rewrite Z.mul_1_r).
lia.
Qed.
Lemma sqrt_test_true i j: 0 <= i -> 0 < j -> i/j >= j -> j ^ 2 <= i.
Proof.
intros Hi Hj Hd; rewrite Z.pow_2_r.
apply Z.le_trans with (j * (i/j)). nia.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt_test_false i j: 0 <= i -> 0 < j -> i/j < j -> (j + (i/j))/2 < j.
Proof.
intros Hi Hj H; case (Z.le_gt_cases j ((j + (i/j))/2)); auto.
intros H1; contradict H; apply Z.le_ngt.
assert (2 * j <= j + (i/j)). 2: lia.
apply Z.le_trans with (2 * ((j + (i/j))/2)); auto with zarith.
apply Z_mult_div_ge; auto with zarith.
Qed.
Lemma sqrt31_step_def rec i j:
sqrt31_step rec i j =
match (fst (i/j) ?= j)%int31 with
Lt => rec i (fst ((j + fst(i/j))/2))%int31
| _ => j
end.
Proof.
unfold sqrt31_step; case div31; intros.
simpl; case compare31; auto.
Qed.
Lemma div31_phi i j: 0 < [|j|] -> [|fst (i/j)%int31|] = [|i|]/[|j|].
intros Hj; generalize (spec_div i j Hj).
case div31; intros q r; simpl @fst.
intros (H1,H2); apply Zdiv_unique with [|r|]; lia.
Qed.
Lemma sqrt31_step_correct rec i j:
0 < [|i|] -> 0 < [|j|] -> [|i|] < ([|j|] + 1) ^ 2 ->
2 * [|j|] < wB ->
(forall j1 : int31,
0 < [|j1|] < [|j|] -> [|i|] < ([|j1|] + 1) ^ 2 ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|sqrt31_step rec i j|] ^ 2 <= [|i|] < ([|sqrt31_step rec i j|] + 1) ^ 2.
Proof.
assert (Hp2: 0 < [|2|]) by exact (eq_refl Lt).
intros Hi Hj Hij H31 Hrec; rewrite sqrt31_step_def.
rewrite spec_compare, div31_phi; auto.
case Z.compare_spec; intros Hc.
1, 3: split; [ apply sqrt_test_true; lia | assumption ].
assert (E : [|(j + fst (i / j)%int31)|] = [|j|] + [|i|] / [|j|]).
{ rewrite spec_add, div31_phi by lia. apply Z.mod_small. split. 2: lia.
generalize (Z.div_pos [|i|] [|j|]); lia. }
apply Hrec; rewrite !div31_phi, E; auto.
2: apply sqrt_main; lia.
split. 2: apply sqrt_test_false; lia.
apply Z.le_succ_l in Hj. change (1 <= [|j|]) in Hj.
Z.le_elim Hj.
- replace ([|j|] + [|i|]/[|j|]) with
(1 * 2 + (([|j|] - 2) + [|i|] / [|j|])) by ring.
rewrite Z_div_plus_full_l by lia.
assert (0 <= [|i|]/ [|j|]) by (generalize (Z.div_pos [|i|] [|j|]); lia).
assert (0 <= ([|j|] - 2 + [|i|] / [|j|]) / [|2|]). 2: lia.
apply Z.div_pos; lia.
- rewrite <- Hj, Zdiv_1_r.
replace (1 + [|i|]) with (1 * 2 + ([|i|] - 1)) by ring.
rewrite Z_div_plus_full_l by lia.
assert (0 <= ([|i|] - 1) /2) by (apply Z.div_pos; lia).
change [|2|] with 2. lia.
Qed.
Lemma iter31_sqrt_correct n rec i j: 0 < [|i|] -> 0 < [|j|] ->
[|i|] < ([|j|] + 1) ^ 2 -> 2 * [|j|] < 2 ^ (Z.of_nat size) ->
(forall j1, 0 < [|j1|] -> 2^(Z.of_nat n) + [|j1|] <= [|j|] ->
[|i|] < ([|j1|] + 1) ^ 2 -> 2 * [|j1|] < 2 ^ (Z.of_nat size) ->
[|rec i j1|] ^ 2 <= [|i|] < ([|rec i j1|] + 1) ^ 2) ->
[|iter31_sqrt n rec i j|] ^ 2 <= [|i|] < ([|iter31_sqrt n rec i j|] + 1) ^ 2.
Proof.
revert rec i j; elim n; unfold iter31_sqrt; fold iter31_sqrt; clear n.
intros rec i j Hi Hj Hij H31 Hrec; apply sqrt31_step_correct; auto.
intros; apply Hrec. 2: rewrite Z.pow_0_r. 1-4: lia.
intros n Hrec rec i j Hi Hj Hij H31 HHrec.
apply sqrt31_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec. 1-4: lia.
intros j2 Hj2 H2j2 Hjp2 Hj31; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite Nat2Z.inj_succ, Z.pow_succ_r by lia.
apply Z.le_trans with (2 ^Z.of_nat n + [|j2|]); lia.
Qed.
Lemma spec_sqrt : forall x,
[|sqrt31 x|] ^ 2 <= [|x|] < ([|sqrt31 x|] + 1) ^ 2.
Proof.
intros i; unfold sqrt31.
rewrite spec_compare. case Z.compare_spec; change [|1|] with 1;
intros Hi. lia.
2: case (phi_bounded i); repeat rewrite Z.pow_2_r; auto with zarith.
apply iter31_sqrt_correct. lia.
rewrite div31_phi; change ([|2|]) with 2. 2: lia.
replace ([|i|]) with (1 * 2 + ([|i|] - 2))%Z; try ring.
assert (0 <= ([|i|] - 2)/2)%Z by (apply Z_div_pos; lia).
rewrite Z_div_plus_full_l; lia.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply sqrt_init; auto.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
apply Z.le_lt_trans with ([|i|]).
apply Z_mult_div_ge; auto with zarith.
case (phi_bounded i); auto.
intros j2 H1 H2; contradict H2; apply Z.lt_nge.
rewrite div31_phi; change ([|2|]) with 2; auto with zarith.
case (phi_bounded i); unfold size; intros X Y.
apply Z.lt_le_trans with ([|i|]). apply Z.div_lt; lia.
lia.
Qed.
Lemma sqrt312_step_def rec ih il j:
sqrt312_step rec ih il j =
match (ih ?= j)%int31 with
Eq => j
| Gt => j
| _ =>
match (fst (div3121 ih il j) ?= j)%int31 with
Lt => let m := match j +c fst (div3121 ih il j) with
C0 m1 => fst (m1/2)%int31
| C1 m1 => (fst (m1/2) + v30)%int31
end in rec ih il m
| _ => j
end
end.
Proof.
unfold sqrt312_step; case div3121; intros.
simpl; case compare31; auto.
Qed.
Lemma sqrt312_lower_bound ih il j:
phi2 ih il < ([|j|] + 1) ^ 2 -> [|ih|] <= [|j|].
Proof.
intros H1.
case (phi_bounded j); intros Hbj _.
case (phi_bounded il); intros Hbil _.
case (phi_bounded ih); intros Hbih Hbih1.
assert ([|ih|] < [|j|] + 1). 2: lia.
apply Z.square_lt_simpl_nonneg; auto with zarith.
rewrite <- ?Z.pow_2_r; apply Z.le_lt_trans with (2 := H1).
apply Z.le_trans with ([|ih|] * wB).
- rewrite ? Z.pow_2_r; nia.
- unfold phi2. change base with wB; lia.
Qed.
Lemma div312_phi ih il j: (2^30 <= [|j|] -> [|ih|] < [|j|] ->
[|fst (div3121 ih il j)|] = phi2 ih il/[|j|])%Z.
Proof.
intros Hj Hj1.
generalize (spec_div21 ih il j Hj Hj1).
case div3121; intros q r (Hq, Hr).
apply Zdiv_unique with (phi r); auto with zarith.
simpl @fst; apply eq_trans with (1 := Hq); ring.
Qed.
Lemma sqrt312_step_correct rec ih il j:
2 ^ 29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] < [|j|] -> phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|sqrt312_step rec ih il j|] ^ 2 <= phi2 ih il
< ([|sqrt312_step rec ih il j|] + 1) ^ 2.
Proof.
assert (Hp2: (0 < [|2|])%Z) by exact (eq_refl Lt).
intros Hih Hj Hij Hrec; rewrite sqrt312_step_def.
assert (H1: ([|ih|] <= [|j|])) by (apply sqrt312_lower_bound with il; auto).
case (phi_bounded ih); intros Hih1 _.
case (phi_bounded il); intros Hil1 _.
case (phi_bounded j); intros _ Hj1.
assert (Hp3: (0 < phi2 ih il)).
{ unfold phi2; apply Z.lt_le_trans with ([|ih|] * base). 2: lia.
apply Z.mul_pos_pos. lia. auto with zarith. }
rewrite spec_compare. case Z.compare_spec; intros Hc1.
- split; auto.
apply sqrt_test_true; auto.
+ unfold phi2, base; auto with zarith.
+ unfold phi2; rewrite Hc1.
assert (0 <= [|il|]/[|j|]) by (apply Z_div_pos; auto with zarith).
rewrite Z.mul_comm, Z_div_plus_full_l by lia.
change base with wB. lia.
- case (Z.le_gt_cases (2 ^ 30) [|j|]); intros Hjj.
+ rewrite spec_compare; case Z.compare_spec;
rewrite div312_phi; auto; intros Hc.
1, 3: split; auto; apply sqrt_test_true; lia.
apply Hrec.
* assert (Hf1: 0 <= phi2 ih il/ [|j|]). { apply Z.div_pos; lia. }
apply Z.le_succ_l in Hj. change (1 <= [|j|]) in Hj.
Z.le_elim Hj;
[ | contradict Hc; apply Z.le_ngt;
rewrite <- Hj, Zdiv_1_r; lia ].
assert (Hf3: 0 < ([|j|] + phi2 ih il / [|j|]) / 2).
{ replace ([|j|] + phi2 ih il/ [|j|]) with
(1 * 2 + (([|j|] - 2) + phi2 ih il / [|j|])) by ring.
rewrite Z_div_plus_full_l by lia.
assert (0 <= ([|j|] - 2 + phi2 ih il / [|j|]) / 2).
apply Z.div_pos; lia.
lia. }
assert (Hf4: ([|j|] + phi2 ih il / [|j|]) / 2 < [|j|]).
{ apply sqrt_test_false; lia. }
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi by lia.
{ rewrite div31_phi; change [|2|] with 2; auto with zarith.
intros HH; rewrite HH; clear HH; auto with zarith. }
{ rewrite spec_add, div31_phi; change [|2|] with 2; auto.
rewrite Z.mul_1_l; intros HH.
rewrite Z.add_comm, <- Z_div_plus_full_l by lia.
change (phi v30 * 2) with (2 ^ Z.of_nat size).
rewrite HH, Zmod_small; lia. }
* replace (phi _) with (([|j|] + (phi2 ih il)/([|j|]))/2);
[ apply sqrt_main; lia | ].
generalize (spec_add_c j (fst (div3121 ih il j))).
unfold interp_carry; case add31c; intros r;
rewrite div312_phi by lia.
{ rewrite div31_phi; auto with zarith.
intros HH; rewrite HH; auto with zarith. }
{ intros HH; rewrite <- HH.
change (1 * 2 ^ Z.of_nat size) with (phi (v30) * 2).
rewrite Z_div_plus_full_l by lia.
rewrite Z.add_comm.
rewrite spec_add, Zmod_small.
- rewrite div31_phi; auto.
- split.
+ case (phi_bounded (fst (r/2)%int31));
case (phi_bounded v30); auto with zarith.
+ rewrite div31_phi; change (phi 2) with 2; auto.
change (2 ^Z.of_nat size) with (base/2 + phi v30).
assert (phi r / 2 < base/2); auto with zarith.
apply Z.mul_lt_mono_pos_r with 2; auto with zarith.
change (base/2 * 2) with base.
apply Z.le_lt_trans with (phi r).
* rewrite Z.mul_comm; apply Z_mult_div_ge; auto with zarith.
* case (phi_bounded r); auto with zarith. }
+ contradict Hij; apply Z.le_ngt.
assert ((1 + [|j|]) <= 2 ^ 30). lia.
apply Z.le_trans with ((2 ^ 30) * (2 ^ 30)); auto with zarith.
* assert (0 <= 1 + [|j|]). lia.
apply Z.mul_le_mono_nonneg; lia.
* change ((2 ^ 30) * (2 ^ 30)) with ((2 ^ 29) * base).
apply Z.le_trans with ([|ih|] * base);
change wB with base in *;
unfold phi2, base; lia.
- split; auto.
apply sqrt_test_true; auto.
+ unfold phi2, base; auto with zarith.
+ apply Z.le_ge; apply Z.le_trans with (([|j|] * base)/[|j|]).
* rewrite Z.mul_comm, Z_div_mult; lia.
* apply Z.ge_le; apply Z_div_ge; lia.
Qed.
Lemma iter312_sqrt_correct n rec ih il j:
2^29 <= [|ih|] -> 0 < [|j|] -> phi2 ih il < ([|j|] + 1) ^ 2 ->
(forall j1, 0 < [|j1|] -> 2^(Z.of_nat n) + [|j1|] <= [|j|] ->
phi2 ih il < ([|j1|] + 1) ^ 2 ->
[|rec ih il j1|] ^ 2 <= phi2 ih il < ([|rec ih il j1|] + 1) ^ 2) ->
[|iter312_sqrt n rec ih il j|] ^ 2 <= phi2 ih il
< ([|iter312_sqrt n rec ih il j|] + 1) ^ 2.
Proof.
revert rec ih il j; elim n; unfold iter312_sqrt; fold iter312_sqrt; clear n.
intros rec ih il j Hi Hj Hij Hrec; apply sqrt312_step_correct. 1-3: lia.
intros; apply Hrec. 2: rewrite Z.pow_0_r. 1-3: lia.
intros n Hrec rec ih il j Hi Hj Hij HHrec.
apply sqrt312_step_correct; auto.
intros j1 Hj1 Hjp1; apply Hrec. 1-3: lia.
intros j2 Hj2 H2j2 Hjp2; apply Hrec; auto with zarith.
intros j3 Hj3 Hpj3.
apply HHrec; auto.
rewrite Nat2Z.inj_succ, Z.pow_succ_r by lia.
lia.
Qed.
(* Avoid expanding [iter312_sqrt] before variables in the context. *)
Strategy 1 [iter312_sqrt].
Lemma spec_sqrt2 : forall x y,
wB/ 4 <= [|x|] ->
let (s,r) := sqrt312 x y in
[||WW x y||] = [|s|] ^ 2 + [+|r|] /\
[+|r|] <= 2 * [|s|].
Proof.
intros ih il Hih; unfold sqrt312.
change [||WW ih il||] with (phi2 ih il).
assert (Hbin: forall s, s * s + 2* s + 1 = (s + 1) ^ 2) by
(intros s; ring).
assert (Hb: 0 <= base) by (red; intros HH; discriminate).
assert (Hi2: phi2 ih il < (phi Tn + 1) ^ 2).
{ change ((phi Tn + 1) ^ 2) with (2^62).
apply Z.le_lt_trans with ((2^31 -1) * base + (2^31 - 1)).
2: simpl; unfold Z.pow_pos; simpl; lia.
case (phi_bounded ih); case (phi_bounded il); intros H1 H2 H3 H4.
unfold base, Z.pow, Z.pow_pos in H2,H4; simpl in H2,H4.
unfold phi2. nia. }
case (iter312_sqrt_correct 31 (fun _ _ j => j) ih il Tn); auto with zarith.
change [|Tn|] with 2147483647; auto with zarith.
intros j1 _ HH; contradict HH.
apply Z.lt_nge.
change [|Tn|] with 2147483647; auto with zarith.
change (2 ^ Z.of_nat 31) with 2147483648; auto with zarith.
case (phi_bounded j1); lia.
set (s := iter312_sqrt 31 (fun _ _ j : int31 => j) ih il Tn).
intros Hs1 Hs2.
generalize (spec_mul_c s s); case mul31c.
simpl zn2z_to_Z; intros HH.
assert ([|s|] = 0).
{ symmetry in HH. rewrite Z.mul_eq_0 in HH. destruct HH; auto. }
contradict Hs2; apply Z.le_ngt; rewrite H.
change ((0 + 1) ^ 2) with 1.
apply Z.le_trans with (2 ^ Z.of_nat size / 4 * base).
simpl; auto with zarith.
apply Z.le_trans with ([|ih|] * base); auto with zarith.
unfold phi2; case (phi_bounded il); lia.
intros ih1 il1.
change [||WW ih1 il1||] with (phi2 ih1 il1).
intros Hihl1.
generalize (spec_sub_c il il1).
case sub31c; intros il2 Hil2.
- rewrite spec_compare; case Z.compare_spec.
+ unfold interp_carry in *.
intros H1; split.
rewrite Z.pow_2_r, <- Hihl1.
unfold phi2; ring[Hil2 H1].
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; lia.
unfold phi2; rewrite H1, Hil2; ring.
+ unfold interp_carry.
intros H1; contradict Hs1.
apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2.
case (phi_bounded il); intros _ H2.
apply Z.lt_le_trans with (([|ih|] + 1) * base + 0).
rewrite Z.mul_add_distr_r, Z.add_0_r; auto with zarith.
case (phi_bounded il1); intros H3 _.
nia.
+ unfold interp_carry in *; change (1 * 2 ^ Z.of_nat size) with base.
rewrite Z.pow_2_r, <- Hihl1, Hil2.
intros H1.
rewrite <- Z.le_succ_l, <- Z.add_1_r in H1.
Z.le_elim H1.
* contradict Hs2; apply Z.le_ngt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
case (phi_bounded il); intros Hpil _.
assert (Hl1l: [|il1|] <= [|il|]).
{ case (phi_bounded il2); rewrite Hil2; lia. }
assert ([|ih1|] * base + 2 * [|s|] + 1 <= [|ih|] * base). 2: lia.
case (phi_bounded s); change (2 ^ Z.of_nat size) with base; intros _ Hps.
case (phi_bounded ih1); intros Hpih1 _; auto with zarith.
apply Z.le_trans with (([|ih1|] + 2) * base). lia.
rewrite Z.mul_add_distr_r.
nia.
rewrite Hihl1, Hbin; auto.
* split.
unfold phi2; rewrite <- H1; ring.
replace (base + ([|il|] - [|il1|])) with (phi2 ih il - ([|s|] * [|s|])).
rewrite <-Hbin in Hs2; lia.
rewrite <- Hihl1; unfold phi2; rewrite <- H1; ring.
- unfold interp_carry in Hil2 |- *.
unfold interp_carry; change (1 * 2 ^ Z.of_nat size) with base.
assert (Hsih: [|ih - 1|] = [|ih|] - 1).
{ rewrite spec_sub, Zmod_small; auto; change [|1|] with 1.
case (phi_bounded ih); intros H1 H2.
generalize Hih; change (2 ^ Z.of_nat size / 4) with 536870912.
lia. }
rewrite spec_compare; case Z.compare_spec.
+ rewrite Hsih.
intros H1; split.
rewrite Z.pow_2_r, <- Hihl1.
unfold phi2; rewrite <-H1.
transitivity ([|ih|] * base + [|il1|] + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z.of_nat size) with base; ring.
replace [|il2|] with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; lia.
unfold phi2.
rewrite <-H1.
ring_simplify.
transitivity (base + ([|il|] - [|il1|])).
ring.
rewrite <-Hil2.
change (2 ^ Z.of_nat size) with base; ring.
+ rewrite Hsih; intros H1.
assert (He: [|ih|] = [|ih1|]).
{ apply Z.le_antisymm. lia.
case (Z.le_gt_cases [|ih1|] [|ih|]); auto; intros H2.
contradict Hs1; apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2.
case (phi_bounded il); change (2 ^ Z.of_nat size) with base;
intros _ Hpil1.
apply Z.lt_le_trans with (([|ih|] + 1) * base).
rewrite Z.mul_add_distr_r, Z.mul_1_l; auto with zarith.
case (phi_bounded il1); intros Hpil2 _.
nia. }
rewrite Z.pow_2_r, <-Hihl1; unfold phi2; rewrite <-He.
contradict Hs1; apply Z.lt_nge; rewrite Z.pow_2_r, <-Hihl1.
unfold phi2; rewrite He.
assert (phi il - phi il1 < 0). 2: lia.
rewrite <-Hil2.
case (phi_bounded il2); lia.
+ intros H1.
rewrite Z.pow_2_r, <-Hihl1.
assert (H2 : [|ih1|]+2 <= [|ih|]). lia.
Z.le_elim H2.
* contradict Hs2; apply Z.le_ngt.
replace (([|s|] + 1) ^ 2) with (phi2 ih1 il1 + 2 * [|s|] + 1).
unfold phi2.
assert ([|ih1|] * base + 2 * phi s + 1 <= [|ih|] * base + ([|il|] - [|il1|])).
2: lia.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base).
case (phi_bounded il2); intros Hpil2 _.
apply Z.le_trans with ([|ih|] * base + - base). 2: lia.
case (phi_bounded s); change (2 ^ Z.of_nat size) with base; intros _ Hps.
assert (2 * [|s|] + 1 <= 2 * base). lia.
apply Z.le_trans with ([|ih1|] * base + 2 * base). lia.
assert (Hi: ([|ih1|] + 3) * base <= [|ih|] * base). nia. lia.
rewrite Hihl1, Hbin; auto.
* unfold phi2; rewrite <-H2.
split.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]) by ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base); ring.
replace (base + [|il2|]) with (phi2 ih il - phi2 ih1 il1).
rewrite Hihl1.
rewrite <-Hbin in Hs2; lia.
unfold phi2; rewrite <-H2.
replace [|il|] with (([|il|] - [|il1|]) + [|il1|]) by ring.
rewrite <-Hil2.
change (-1 * 2 ^ Z.of_nat size) with (-base); ring.
Qed.
(** [iszero] *)
Lemma spec_eq0 : forall x, ZnZ.eq0 x = true -> [|x|] = 0.
Proof.
clear; unfold ZnZ.eq0, int31_ops.
unfold compare31; intros.
change [|0|] with 0 in H.
apply Z.compare_eq.
now destruct ([|x|] ?= 0).
Qed.
(* Even *)
Lemma spec_is_even : forall x,
if ZnZ.is_even x then [|x|] mod 2 = 0 else [|x|] mod 2 = 1.
Proof.
unfold ZnZ.is_even, int31_ops; intros.
generalize (spec_div x 2).
destruct (x/2)%int31 as (q,r); intros.
unfold compare31.
change [|2|] with 2 in H.
change [|0|] with 0.
destruct H; auto with zarith.
replace ([|x|] mod 2) with [|r|].
destruct H; auto with zarith.
case Z.compare_spec; lia.
apply Zmod_unique with [|q|]; lia.
Qed.
(* Bitwise *)
Lemma log2_phi_bounded x : Z.log2 [|x|] < Z.of_nat size.
Proof.
destruct (phi_bounded x) as (H,H').
Z.le_elim H.
- now apply Z.log2_lt_pow2.
- now rewrite <- H.
Qed.
Lemma spec_lor x y : [| ZnZ.lor x y |] = Z.lor [|x|] [|y|].
Proof.
unfold ZnZ.lor,int31_ops. unfold lor31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.lor_nonneg; split; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
rewrite Z.log2_lor; try apply phi_bounded.
apply Z.max_lub_lt; apply log2_phi_bounded.
Qed.
Lemma spec_land x y : [| ZnZ.land x y |] = Z.land [|x|] [|y|].
Proof.
unfold ZnZ.land, int31_ops. unfold land31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.land_nonneg; left; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
eapply Z.le_lt_trans.
apply Z.log2_land; try apply phi_bounded.
apply Z.min_lt_iff; left; apply log2_phi_bounded.
Qed.
Lemma spec_lxor x y : [| ZnZ.lxor x y |] = Z.lxor [|x|] [|y|].
Proof.
unfold ZnZ.lxor, int31_ops. unfold lxor31.
rewrite phi_phi_inv.
apply Z.mod_small; split; trivial.
- apply Z.lxor_nonneg; split; intros; apply phi_bounded.
- apply Z.log2_lt_cancel. rewrite Z.log2_pow2 by easy.
eapply Z.le_lt_trans.
apply Z.log2_lxor; try apply phi_bounded.
apply Z.max_lub_lt; apply log2_phi_bounded.
Qed.
Global Instance int31_specs : ZnZ.Specs int31_ops := {
spec_to_Z := phi_bounded;
spec_of_pos := positive_to_int31_spec;
spec_zdigits := spec_zdigits;
spec_more_than_1_digit := spec_more_than_1_digit;
spec_0 := spec_0;
spec_1 := spec_1;
spec_m1 := spec_m1;
spec_compare := spec_compare;
spec_eq0 := spec_eq0;
spec_opp_c := spec_opp_c;
spec_opp := spec_opp;
spec_opp_carry := spec_opp_carry;
spec_succ_c := spec_succ_c;
spec_add_c := spec_add_c;
spec_add_carry_c := spec_add_carry_c;
spec_succ := spec_succ;
spec_add := spec_add;
spec_add_carry := spec_add_carry;
spec_pred_c := spec_pred_c;
spec_sub_c := spec_sub_c;
spec_sub_carry_c := spec_sub_carry_c;
spec_pred := spec_pred;
spec_sub := spec_sub;
spec_sub_carry := spec_sub_carry;
spec_mul_c := spec_mul_c;
spec_mul := spec_mul;
spec_square_c := spec_square_c;
spec_div21 := spec_div21;
spec_div_gt := fun a b _ => spec_div a b;
spec_div := spec_div;
spec_modulo_gt := fun a b _ => spec_mod a b;
spec_modulo := spec_mod;
spec_gcd_gt := fun a b _ => spec_gcd a b;
spec_gcd := spec_gcd;
spec_head00 := spec_head00;
spec_head0 := spec_head0;
spec_tail00 := spec_tail00;
spec_tail0 := spec_tail0;
spec_add_mul_div := spec_add_mul_div;
spec_pos_mod := spec_pos_mod;
spec_is_even := spec_is_even;
spec_sqrt2 := spec_sqrt2;
spec_sqrt := spec_sqrt;
spec_lor := spec_lor;
spec_land := spec_land;
spec_lxor := spec_lxor }.
End Int31_Specs.
Module Int31Cyclic <: CyclicType.
Definition t := int31.
Definition ops := int31_ops.
Definition specs := int31_specs.
End Int31Cyclic.
|
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 17
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_pc_0 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4\
, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 50000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS\
4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_17_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_merge_enc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ecc_merge_enc
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter CODE_WIDTH = 72,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter DQ_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
mc_wrdata, mc_wrdata_mask,
// Inputs
clk, rst, wr_data, wr_data_mask, rd_merge_data, h_rows, raw_not_ecc
);
input clk;
input rst;
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
input [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
reg [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data_r;
reg [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask_r;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data_r;
always @(posedge clk) wr_data_r <= #TCQ wr_data;
always @(posedge clk) wr_data_mask_r <= #TCQ wr_data_mask;
always @(posedge clk) rd_merge_data_r <= #TCQ rd_merge_data;
// Merge new data with memory read data.
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] merged_data;
genvar h;
genvar i;
generate
for (h=0; h<2*nCK_PER_CLK; h=h+1) begin : merge_data_outer
for (i=0; i<DATA_WIDTH/8; i=i+1) begin : merge_data_inner
assign merged_data[h*PAYLOAD_WIDTH+i*8+:8] =
wr_data_mask[h*DATA_WIDTH/8+i]
? rd_merge_data[h*DATA_WIDTH+i*8+:8]
: wr_data[h*PAYLOAD_WIDTH+i*8+:8];
end
if (PAYLOAD_WIDTH > DATA_WIDTH)
assign merged_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH]=
wr_data[(h+1)*PAYLOAD_WIDTH-1-:PAYLOAD_WIDTH-DATA_WIDTH];
end
endgenerate
// Generate ECC and overlay onto mc_wrdata.
input [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
input [2*nCK_PER_CLK-1:0] raw_not_ecc;
reg [2*nCK_PER_CLK-1:0] raw_not_ecc_r;
always @(posedge clk) raw_not_ecc_r <= #TCQ raw_not_ecc;
output reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata_c;
genvar j;
integer k;
generate
for (j=0; j<2*nCK_PER_CLK; j=j+1) begin : ecc_word
always @(/*AS*/h_rows or merged_data or raw_not_ecc_r) begin
mc_wrdata_c[j*DQ_WIDTH+:DQ_WIDTH] =
{{DQ_WIDTH-PAYLOAD_WIDTH{1'b0}},
merged_data[j*PAYLOAD_WIDTH+:PAYLOAD_WIDTH]};
for (k=0; k<ECC_WIDTH; k=k+1)
if (~raw_not_ecc_r[j])
mc_wrdata_c[j*DQ_WIDTH+CODE_WIDTH-k-1] =
^(merged_data[j*PAYLOAD_WIDTH+:DATA_WIDTH] &
h_rows[k*CODE_WIDTH+:DATA_WIDTH]);
end
end
endgenerate
always @(posedge clk) mc_wrdata <= mc_wrdata_c;
// Set all DRAM masks to zero.
output wire[2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
assign mc_wrdata_mask = {2*nCK_PER_CLK*DQ_WIDTH/8{1'b0}};
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_8_qpll_drp.v
// Version : 1.7
//------------------------------------------------------------------------------
// Filename : qpll_drp.v
// Description : QPLL DRP Module for 7 Series Transceiver
// Version : 15.2
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- QPLL DRP Module ---------------------------------------------------
module pcie_7x_v1_8_qpll_drp #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter INDEX_MAX = 3'd6 // Index max count
)
(
//---------- Input -------------------------------------
input DRP_CLK,
input DRP_RST_N,
input DRP_OVRD,
input DRP_GEN3,
input DRP_QPLLLOCK,
input DRP_START,
input [15:0] DRP_DO,
input DRP_RDY,
//---------- Output ------------------------------------
output [ 7:0] DRP_ADDR,
output DRP_EN,
output [15:0] DRP_DI,
output DRP_WE,
output DRP_DONE,
output DRP_QPLLRESET,
output [ 5:0] DRP_CRSCODE,
output [ 8:0] DRP_FSM
);
//---------- Input Registers ---------------------------
reg ovrd_reg1;
reg gen3_reg1;
reg qplllock_reg1;
reg start_reg1;
reg [15:0] do_reg1;
reg rdy_reg1;
reg ovrd_reg2;
reg gen3_reg2;
reg qplllock_reg2;
reg start_reg2;
reg [15:0] do_reg2;
reg rdy_reg2;
//---------- Internal Signals --------------------------
reg [ 2:0] index = 3'd0;
reg mode = 1'd0;
reg [ 5:0] crscode = 6'd0;
//---------- Output Registers --------------------------
reg [ 7:0] addr = 8'd0;
reg [15:0] di = 16'd0;
reg done = 1'd0;
reg [ 8:0] fsm = 7'd1;
//---------- DRP Address -------------------------------
localparam ADDR_QPLL_FBDIV = 8'h36;
localparam ADDR_QPLL_CFG = 8'h32;
localparam ADDR_QPLL_LPF = 8'h31;
localparam ADDR_CRSCODE = 8'h88;
localparam ADDR_QPLL_COARSE_FREQ_OVRD = 8'h35;
localparam ADDR_QPLL_COARSE_FREQ_OVRD_EN = 8'h36;
localparam ADDR_QPLL_LOCK_CFG = 8'h34;
//---------- DRP Mask ----------------------------------
localparam MASK_QPLL_FBDIV = 16'b1111110000000000; // Unmask bit [ 9: 0]
localparam MASK_QPLL_CFG = 16'b1111111110111111; // Unmask bit [ 6]
localparam MASK_QPLL_LPF = 16'b1000011111111111; // Unmask bit [14:11]
localparam MASK_QPLL_COARSE_FREQ_OVRD = 16'b0000001111111111; // Unmask bit [15:10]
localparam MASK_QPLL_COARSE_FREQ_OVRD_EN = 16'b1111011111111111; // Unmask bit [ 11]
localparam MASK_QPLL_LOCK_CFG = 16'b1110011111111111; // Unmask bit [12:11]
//---------- DRP Data for Normal QPLLLOCK Mode ---------
localparam NORM_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
localparam NORM_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000000000000000; // Normal QPLL lock
localparam NORM_QPLL_LOCK_CFG = 16'b0000000000000000; // Normal QPLL lock config
//---------- DRP Data for Optimize QPLLLOCK Mode -------
localparam OVRD_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
localparam OVRD_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000100000000000; // Override QPLL lock
localparam OVRD_QPLL_LOCK_CFG = 16'b0000000000000000; // Override QPLL lock config
//---------- Select QPLL Feedback Divider --------------
// N = 100 for 100 MHz ref clk and 10Gb/s line rate
// N = 80 for 125 MHz ref clk and 10Gb/s line rate
// N = 40 for 250 MHz ref clk and 10Gb/s line rate
//------------------------------------------------------
// N = 80 for 100 MHz ref clk and 8Gb/s line rate
// N = 64 for 125 MHz ref clk and 8Gb/s line rate
// N = 32 for 250 MHz ref clk and 8Gb/s line rate
//------------------------------------------------------
localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000010000000 :
(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000100100000 :
(PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000101110000 :
(PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000001100000 :
(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000011100000 : 16'b0000000100100000;
localparam GEN12_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000010000000 :
(PCIE_REFCLK_FREQ == 1) ? 16'b0000000100100000 : 16'b0000000101110000;
localparam GEN3_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000001100000 :
(PCIE_REFCLK_FREQ == 1) ? 16'b0000000011100000 : 16'b0000000100100000;
//---------- Select QPLL Configuration ---------------------------
// QPLL_CFG[6] = 0 for upper band
// = 1 for lower band
//----------------------------------------------------------------
localparam GEN12_QPLL_CFG = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000000 : 16'b0000000001000000;
localparam GEN3_QPLL_CFG = 16'b0000000001000000;
//---------- Select QPLL LPF -------------------------------------
localparam GEN12_QPLL_LPF = (PCIE_PLL_SEL == "QPLL") ? 16'b0_0100_00000000000 : 16'b0_1101_00000000000;
localparam GEN3_QPLL_LPF = 16'b0_1101_00000000000;
//---------- DRP Data ----------------------------------
wire [15:0] data_qpll_fbdiv;
wire [15:0] data_qpll_cfg;
wire [15:0] data_qpll_lpf;
wire [15:0] data_qpll_coarse_freq_ovrd;
wire [15:0] data_qpll_coarse_freq_ovrd_en;
wire [15:0] data_qpll_lock_cfg;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 9'b000000001;
localparam FSM_LOAD = 9'b000000010;
localparam FSM_READ = 9'b000000100;
localparam FSM_RRDY = 9'b000001000;
localparam FSM_WRITE = 9'b000010000;
localparam FSM_WRDY = 9'b000100000;
localparam FSM_DONE = 9'b001000000;
localparam FSM_QPLLRESET = 9'b010000000;
localparam FSM_QPLLLOCK = 9'b100000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
//---------- 1st Stage FF --------------------------
ovrd_reg1 <= 1'd0;
gen3_reg1 <= 1'd0;
qplllock_reg1 <= 1'd0;
start_reg1 <= 1'd0;
do_reg1 <= 16'd0;
rdy_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
ovrd_reg2 <= 1'd0;
gen3_reg2 <= 1'd0;
qplllock_reg2 <= 1'd0;
start_reg2 <= 1'd0;
do_reg2 <= 16'd0;
rdy_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
ovrd_reg1 <= DRP_OVRD;
gen3_reg1 <= DRP_GEN3;
qplllock_reg1 <= DRP_QPLLLOCK;
start_reg1 <= DRP_START;
do_reg1 <= DRP_DO;
rdy_reg1 <= DRP_RDY;
//---------- 2nd Stage FF --------------------------
ovrd_reg2 <= ovrd_reg1;
gen3_reg2 <= gen3_reg1;
qplllock_reg2 <= qplllock_reg1;
start_reg2 <= start_reg1;
do_reg2 <= do_reg1;
rdy_reg2 <= rdy_reg1;
end
end
//---------- Select DRP Data ---------------------------------------------------
assign data_qpll_fbdiv = (gen3_reg2) ? GEN3_QPLL_FBDIV : GEN12_QPLL_FBDIV;
assign data_qpll_cfg = (gen3_reg2) ? GEN3_QPLL_CFG : GEN12_QPLL_CFG;
assign data_qpll_lpf = (gen3_reg2) ? GEN3_QPLL_LPF : GEN12_QPLL_LPF;
assign data_qpll_coarse_freq_ovrd = NORM_QPLL_COARSE_FREQ_OVRD;
assign data_qpll_coarse_freq_ovrd_en = (ovrd_reg2) ? OVRD_QPLL_COARSE_FREQ_OVRD_EN : NORM_QPLL_COARSE_FREQ_OVRD_EN;
assign data_qpll_lock_cfg = (ovrd_reg2) ? OVRD_QPLL_LOCK_CFG : NORM_QPLL_LOCK_CFG;
//---------- Update DRP Address and Data ---------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
addr <= 8'd0;
di <= 16'd0;
crscode <= 6'd0;
end
else
begin
case (index)
//--------------------------------------------------
3'd0 :
begin
addr <= ADDR_QPLL_FBDIV;
di <= (do_reg2 & MASK_QPLL_FBDIV) | (mode ? data_qpll_fbdiv : QPLL_FBDIV);
crscode <= crscode;
end
//--------------------------------------------------
3'd1 :
begin
addr <= ADDR_QPLL_CFG;
if (PCIE_GT_DEVICE == "GTX")
di <= (do_reg2 & MASK_QPLL_CFG) | data_qpll_cfg;
else
di <= (do_reg2 & 16'hFFFF) | data_qpll_cfg;
crscode <= crscode;
end
//--------------------------------------------------
3'd2 :
begin
addr <= ADDR_QPLL_LPF;
if (PCIE_GT_DEVICE == "GTX")
di <= (do_reg2 & MASK_QPLL_LPF) | data_qpll_lpf;
else
di <= (do_reg2 & 16'hFFFF) | data_qpll_lpf;
crscode <= crscode;
end
//--------------------------------------------------
3'd3 :
begin
addr <= ADDR_CRSCODE;
di <= do_reg2;
//---------- Latch CRS Code --------------------
if (ovrd_reg2)
crscode <= do_reg2[6:1];
else
crscode <= crscode;
end
//--------------------------------------------------
3'd4 :
begin
addr <= ADDR_QPLL_COARSE_FREQ_OVRD;
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD) | {(crscode - 6'd1), data_qpll_coarse_freq_ovrd[9:0]};
crscode <= crscode;
end
//--------------------------------------------------
3'd5 :
begin
addr <= ADDR_QPLL_COARSE_FREQ_OVRD_EN;
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD_EN) | data_qpll_coarse_freq_ovrd_en;
crscode <= crscode;
end
//--------------------------------------------------
3'd6 :
begin
addr <= ADDR_QPLL_LOCK_CFG;
di <= (do_reg2 & MASK_QPLL_LOCK_CFG) | data_qpll_lock_cfg;
crscode <= crscode;
end
//--------------------------------------------------
default :
begin
addr <= 8'd0;
di <= 16'd0;
crscode <= 6'd0;
end
endcase
end
end
//---------- QPLL DRP FSM ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
fsm <= FSM_IDLE;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (start_reg2)
begin
fsm <= FSM_LOAD;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd0;
end
else if ((gen3_reg2 != gen3_reg1) && (PCIE_PLL_SEL == "QPLL"))
begin
fsm <= FSM_LOAD;
index <= 3'd0;
mode <= 1'd1;
done <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd1;
end
end
//---------- Load DRP Address ---------------------
FSM_LOAD :
begin
fsm <= FSM_READ;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP ------------------------------
FSM_READ :
begin
fsm <= FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP Ready ------------------------
FSM_RRDY :
begin
fsm <= (rdy_reg2 ? FSM_WRITE : FSM_RRDY);
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP -----------------------------
FSM_WRITE :
begin
fsm <= FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP Ready -----------------------
FSM_WRDY :
begin
fsm <= (rdy_reg2 ? FSM_DONE : FSM_WRDY);
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- DRP Done ------------------------------
FSM_DONE :
begin
if ((index == INDEX_MAX) || (mode && (index == 3'd2)))
begin
fsm <= mode ? FSM_QPLLRESET : FSM_IDLE;
index <= 3'd0;
mode <= mode;
done <= 1'd0;
end
else
begin
fsm <= FSM_LOAD;
index <= index + 3'd1;
mode <= mode;
done <= 1'd0;
end
end
//---------- QPLL Reset ----------------------------
FSM_QPLLRESET :
begin
fsm <= !qplllock_reg2 ? FSM_QPLLLOCK : FSM_QPLLRESET;
index <= 3'd0;
mode <= mode;
done <= 1'd0;
end
//---------- QPLL Reset ----------------------------
FSM_QPLLLOCK :
begin
fsm <= qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK;
index <= 3'd0;
mode <= mode;
done <= 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd0;
end
endcase
end
end
//---------- QPLL DRP Output ---------------------------------------------------
assign DRP_ADDR = addr;
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
assign DRP_DI = di;
assign DRP_WE = (fsm == FSM_WRITE) || (fsm == FSM_WRDY);
assign DRP_DONE = done;
assign DRP_QPLLRESET = (fsm == FSM_QPLLRESET);
assign DRP_CRSCODE = crscode;
assign DRP_FSM = fsm;
endmodule
|
// file: io_clock_gen_600mhz.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___600.000______0.000______50.0_______83.768_____87.180
// CLK_OUT2___300.000______0.000______50.0_______94.862_____87.180
// CLK_OUT3____75.000______0.000______50.0______122.158_____87.180
// CLK_OUT4___300.000_____90.000______50.0_______94.862_____87.180
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "io_clock_gen_600mhz,clk_wiz_v3_6,{component_name=io_clock_gen_600mhz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=4,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module io_clock_gen_600mhz
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
output CLK_OUT3,
output CLK_OUT4,
// Status and control signals
input RESET,
output LOCKED
);
// Input buffering
//------------------------------------
BUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (12.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (2.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (4),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (16),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (4),
.CLKOUT3_PHASE (90.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (LOCKED),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
BUFG clkout3_buf
(.O (CLK_OUT3),
.I (clkout2));
BUFG clkout4_buf
(.O (CLK_OUT4),
.I (clkout3));
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
// MMCM_OR_BUFR_N with DRP and device specific
`timescale 1ns/100ps
module ad_mmcm_drp #(
parameter MMCM_DEVICE_TYPE = 0,
parameter MMCM_CLKIN_PERIOD = 1.667,
parameter MMCM_CLKIN2_PERIOD = 1.667,
parameter MMCM_VCO_DIV = 6,
parameter MMCM_VCO_MUL = 12.000,
parameter MMCM_CLK0_DIV = 2.000,
parameter MMCM_CLK0_PHASE = 0.000,
parameter MMCM_CLK1_DIV = 6,
parameter MMCM_CLK1_PHASE = 0.000,
parameter MMCM_CLK2_DIV = 2.000,
parameter MMCM_CLK2_PHASE = 0.000) (
// clocks
input clk,
input clk2,
input clk_sel,
input mmcm_rst,
output mmcm_clk_0,
output mmcm_clk_1,
output mmcm_clk_2,
// drp interface
input up_clk,
input up_rstn,
input up_drp_sel,
input up_drp_wr,
input [11:0] up_drp_addr,
input [15:0] up_drp_wdata,
output reg [15:0] up_drp_rdata,
output reg up_drp_ready,
output reg up_drp_locked);
localparam MMCM_DEVICE_7SERIES = 0;
localparam MMCM_DEVICE_ULTRASCALE = 2;
// internal registers
reg up_drp_locked_m1 = 'd0;
// internal signals
wire bufg_fb_clk_s;
wire mmcm_fb_clk_s;
wire mmcm_clk_0_s;
wire mmcm_clk_1_s;
wire mmcm_clk_2_s;
wire mmcm_locked_s;
wire [15:0] up_drp_rdata_s;
wire up_drp_ready_s;
// drp read and locked
always @(posedge up_clk) begin
if (up_rstn == 1'b0) begin
up_drp_rdata <= 'd0;
up_drp_ready <= 'd0;
up_drp_locked_m1 <= 1'd0;
up_drp_locked <= 1'd0;
end else begin
up_drp_rdata <= up_drp_rdata_s;
up_drp_ready <= up_drp_ready_s;
up_drp_locked_m1 <= mmcm_locked_s;
up_drp_locked <= up_drp_locked_m1;
end
end
// instantiations
generate
if (MMCM_DEVICE_TYPE == MMCM_DEVICE_7SERIES) begin
MMCME2_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
.CLKOUT2_PHASE (MMCM_CLK2_PHASE),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
.REF_JITTER1 (0.010))
i_mmcm (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.CLKOUT2 (mmcm_clk_2_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (clk2),
.CLKINSEL (clk_sel),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (mmcm_rst));
BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2));
end else if (MMCM_DEVICE_TYPE == MMCM_DEVICE_ULTRASCALE) begin
MMCME3_ADV #(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("AUTO"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (MMCM_VCO_DIV),
.CLKFBOUT_MULT_F (MMCM_VCO_MUL),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLK0_DIV),
.CLKOUT0_PHASE (MMCM_CLK0_PHASE),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLK1_DIV),
.CLKOUT1_PHASE (MMCM_CLK1_PHASE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (MMCM_CLK2_DIV),
.CLKOUT2_PHASE (MMCM_CLK2_PHASE),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (MMCM_CLKIN_PERIOD),
.CLKIN2_PERIOD (MMCM_CLKIN2_PERIOD),
.REF_JITTER1 (0.010))
i_mmcme3 (
.CLKIN1 (clk),
.CLKFBIN (bufg_fb_clk_s),
.CLKFBOUT (mmcm_fb_clk_s),
.CLKOUT0 (mmcm_clk_0_s),
.CLKOUT1 (mmcm_clk_1_s),
.CLKOUT2 (mmcm_clk_2_s),
.LOCKED (mmcm_locked_s),
.DCLK (up_clk),
.DEN (up_drp_sel),
.DADDR (up_drp_addr[6:0]),
.DWE (up_drp_wr),
.DI (up_drp_wdata),
.DO (up_drp_rdata_s),
.DRDY (up_drp_ready_s),
.CLKFBOUTB (),
.CLKOUT0B (),
.CLKOUT1B (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKIN2 (clk2),
.CLKINSEL (clk_sel),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.CDDCREQ (1'b0),
.CDDCDONE (),
.RST (mmcm_rst));
BUFG i_fb_clk_bufg (.I (mmcm_fb_clk_s), .O (bufg_fb_clk_s));
BUFG i_clk_0_bufg (.I (mmcm_clk_0_s), .O (mmcm_clk_0));
BUFG i_clk_1_bufg (.I (mmcm_clk_1_s), .O (mmcm_clk_1));
BUFG i_clk_2_bufg (.I (mmcm_clk_2_s), .O (mmcm_clk_2));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
`include "defines.vh"
module primogen #(
parameter WIDTH_LOG = 4
) (clk, go, rst, ready, error, res);
localparam WIDTH = 1 << WIDTH_LOG;
localparam HI = WIDTH - 1;
input clk;
input go;
input rst;
output reg ready;
output reg error;
output reg [HI:0] res;
localparam MAX = {WIDTH{1'b1}};
// Note that incrementing address width
// by 1 bit would double BRAM consumption
localparam ADDR_WIDTH = 8;
localparam ADDR_HI = ADDR_WIDTH - 1;
`ifdef SIM
// Use reduced RAM for tests
localparam ADDR_MAX = 4'd8;
`else
localparam ADDR_MAX = {ADDR_WIDTH{1'b1}};
`endif
localparam XW = {WIDTH{1'bx}};
localparam X7 = 7'bx;
localparam XA = {ADDR_WIDTH{1'bx}};
localparam READY = 4'd0;
localparam ERROR = 4'd1;
localparam NEXT_CANDIDATE = 4'd2;
localparam NEXT_PRIME_DIVISOR = 4'd3;
localparam PRIME_DIVIDE_START = 4'd4; // TODO: can we get rid of this?
localparam PRIME_DIVIDE_WAIT = 4'd5;
localparam NEXT_DIVISOR = 4'd6;
localparam DIVIDE_START = 4'd7; // TODO: can we get rid of this?
localparam DIVIDE_WAIT = 4'd8;
// Combinational logic for outputs
reg [HI:0] next_res;
wire next_ready;
wire next_error;
// State
reg [3:0] state;
reg [HI:0] res_squared;
// And it's combinational logic
reg [3:0] next_state;
reg [HI:0] next_res_squared;
// Submodule inputs
reg [HI:0] div;
reg [HI:0] div_squared;
reg div_go;
reg [ADDR_HI:0] addr;
reg [ADDR_HI:0] naddrs;
reg write_en;
// And their combinational logic
reg [HI:0] next_div;
reg [HI:0] next_div_squared;
reg next_div_go;
reg [ADDR_HI:0] next_addr;
reg [ADDR_HI:0] next_naddrs;
reg next_write_en;
// Submodule outputs
wire div_ready;
wire div_error;
wire [HI:0] rem;
wire [HI:0] dout;
wire [HI:0] dout_squared;
// We store both primes and their squares
ram #(.WIDTH(2*WIDTH), .ADDR_WIDTH(ADDR_WIDTH)) primes(
.din({res, res_squared}),
.addr(addr),
.write_en(write_en),
.clk(clk),
.dout({dout, dout_squared})
);
divrem #(.WIDTH_LOG(WIDTH_LOG)) dr(
.clk(clk),
.go(div_go),
.rst(rst),
.num(res),
.den(div),
.ready(div_ready),
.error(div_error),
.rem(rem));
assign next_ready = next_state == READY || next_state == ERROR;
assign next_error = next_state == ERROR;
always @* begin
next_state = state;
next_res = res;
next_res_squared = res_squared;
next_div = div;
next_div_squared = div_squared;
next_div_go = 0;
next_addr = addr;
next_naddrs = naddrs;
next_write_en = 0;
case (state)
READY:
begin
if (go) begin
next_state = NEXT_CANDIDATE;
next_addr = 0;
end
end
ERROR:
; // Do nothing
NEXT_CANDIDATE: // TODO: can probably be merged with NEXT_PRIME_DIVISOR
begin
// Search for next prime
case (res)
1:
begin
next_res = 8'd2;
next_res_squared = 8'd4;
end
2:
begin
next_res = 8'd3;
next_res_squared = 8'd9;
end
default:
begin
next_res = res + 8'd2;
// Square is subject to overflow
if (next_res < (1'd1 << (WIDTH / 2))) begin
next_res_squared = res_squared + (res << 2) + 8'd4;
`assert_lt(res_squared, next_res_squared);
end else
next_res_squared = MAX;
end
endcase
next_addr = 0;
// Check for overflow
next_state = next_res > res ? NEXT_PRIME_DIVISOR : ERROR;
end
NEXT_PRIME_DIVISOR:
if (naddrs == 0 || dout_squared > res) begin
next_state = READY;
// Store found prime
if (res != 1'd1 && res != 2'd2) begin
next_write_en = 1'd1;
next_addr = naddrs;
next_naddrs = naddrs + 1'd1;
end
end else if (addr < naddrs) begin
next_state = PRIME_DIVIDE_START;
next_div = dout;
next_div_squared = dout_squared;
next_div_go = 1;
end else if (naddrs == ADDR_MAX) begin
// Prime table overflow => use slow check
next_state = NEXT_DIVISOR;
next_div = div + 8'd2;
next_div_squared = div_squared + (div << 2) + 8'd4;
`assert_lt(div_squared, next_div_squared);
end else begin
next_state = ERROR;
`unreachable;
end
PRIME_DIVIDE_START:
// Wait state to allow divrem to register inputs and update ready bit
next_state = PRIME_DIVIDE_WAIT;
PRIME_DIVIDE_WAIT:
if (div_error) begin
next_state = ERROR;
end else if (!div_ready)
; // Keep waiting
else if (rem == 0) begin
// Divisable => abort and try next candidate
next_state = NEXT_CANDIDATE;
next_addr = 0;
end else begin
// Not divisable => try next divisor
next_state = NEXT_PRIME_DIVISOR;
next_addr = addr + 1'd1;
end
NEXT_DIVISOR:
if (div_squared > res) begin
// None of potential divisors matched => number is prime!
next_state = READY;
end else begin
next_state = DIVIDE_START;
next_div_go = 1;
end
DIVIDE_START:
// Wait state to allow divrem to register inputs and update ready bit
next_state = DIVIDE_WAIT;
DIVIDE_WAIT:
if (div_error) begin
next_state = ERROR;
end else if (!div_ready)
; // Keep waiting
else if (rem == 0) begin
// Divisable => abort and try next candidate
next_state = NEXT_CANDIDATE;
end else begin
// Not divisable => try next divisor
case (div)
2:
begin
next_div = 8'd3;
next_div_squared = 8'd9;
end
7:
begin
next_div = 8'd11;
next_div_squared = 8'd121;
end
// 3, 5 and 11 are covered by default branch
default:
begin
next_div = div + 8'd2;
next_div_squared = div_squared + (div << 2) + 8'd4;
end
endcase
// div * div < res so shouldn't overflow
`assert_lt(next_div, div);
// Clamp square as it's subject to overflow
// TODO: this may not be necessary
if (next_div_squared <= div_squared)
next_div_squared = MAX;
next_state = NEXT_DIVISOR;
end
default:
begin
next_state = 3'bx;
next_res = XW;
next_res_squared = XW;
next_div = XW;
next_div_squared = XW;
next_div_go = 1'bx;
next_addr = XA;
end
endcase
end
always @(posedge clk)
if (rst) begin
// Start by outputting the very first prime...
state <= READY;
res_squared <= 1;
res <= 1;
ready <= 1;
error <= 0;
div <= XW;
div_squared <= XW;
div_go <= 0;
addr <= XA;
naddrs <= 0;
write_en <= 0;
end else begin
state <= next_state;
res_squared <= next_res_squared;
res <= next_res;
ready <= next_ready;
error <= next_error;
div <= next_div;
div_squared <= next_div_squared;
div_go <= next_div_go;
addr <= next_addr;
naddrs <= next_naddrs;
write_en <= next_write_en;
end
`ifdef SIM
always @(posedge clk) begin
// Precondition: core signals must always be valid
`assert_nox(rst);
`assert_nox(clk);
if (!rst) begin
// Invariant: output looks like prime
`assert(res[0] || (res == 2));
end
end
`endif
`ifdef SIM
// initial
// $monitor("%t: clk=%b, go=%b, state=%h, res=%0d, res_squared=%0d, addr=%0d, next_addr=%0d, naddrs=%0d, write_en=%0d, div=%0d, div_squared=%0d, div_go=%b, rem=%0d, div_ready=%b, dout=%0d, dout_squared=%0d", $time, clk, go, state, res, res_squared, addr, next_addr, naddrs, write_en, div, div_squared, div_go, rem, div_ready, dout, dout_squared);
`endif
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.1
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sample_iterator_next (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
indices_req_din,
indices_req_full_n,
indices_req_write,
indices_rsp_empty_n,
indices_rsp_read,
indices_address,
indices_datain,
indices_dataout,
indices_size,
ap_ce,
i_index,
i_sample,
ap_return_0,
ap_return_1
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_pp0_stg0_fsm_0 = 1'b0;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_20 = 32'b100000;
parameter ap_const_lv32_2F = 32'b101111;
parameter ap_const_lv17_1FFFF = 17'b11111111111111111;
parameter ap_const_lv16_1 = 16'b1;
parameter ap_const_lv16_0 = 16'b0000000000000000;
parameter ap_const_lv56_0 = 56'b00000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output indices_req_din;
input indices_req_full_n;
output indices_req_write;
input indices_rsp_empty_n;
output indices_rsp_read;
output [31:0] indices_address;
input [55:0] indices_datain;
output [55:0] indices_dataout;
output [31:0] indices_size;
input ap_ce;
input [15:0] i_index;
input [15:0] i_sample;
output [15:0] ap_return_0;
output [15:0] ap_return_1;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg indices_req_write;
reg indices_rsp_read;
reg [0:0] ap_CS_fsm = 1'b0;
wire ap_reg_ppiten_pp0_it0;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
reg ap_reg_ppiten_pp0_it2 = 1'b0;
reg ap_reg_ppiten_pp0_it3 = 1'b0;
reg [15:0] i_sample_read_reg_147;
reg [15:0] ap_reg_ppstg_i_sample_read_reg_147_pp0_it1;
reg [15:0] ap_reg_ppstg_i_sample_read_reg_147_pp0_it2;
reg [15:0] i_index_read_reg_153;
reg [15:0] ap_reg_ppstg_i_index_read_reg_153_pp0_it1;
reg [15:0] ap_reg_ppstg_i_index_read_reg_153_pp0_it2;
reg [15:0] indices_samples_load_new5_reg_165;
wire [63:0] tmp_s_fu_67_p1;
wire [16:0] tmp_6_cast_fu_91_p1;
wire [16:0] tmp_7_fu_94_p2;
wire [17:0] tmp_cast_fu_88_p1;
wire [17:0] tmp_8_fu_104_p1;
wire [0:0] tmp_8_fu_104_p2;
wire [15:0] tmp_1_fu_115_p2;
wire [15:0] tmp_9_fu_110_p2;
wire [15:0] agg_result_index_write_assign_fu_128_p3;
wire [15:0] agg_result_sample_write_assign_fu_120_p3;
reg [0:0] ap_NS_fsm;
reg ap_sig_pprstidle_pp0;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0)) | ~(ap_const_logic_1 == ap_ce)))) begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
ap_reg_ppstg_i_index_read_reg_153_pp0_it1 <= i_index_read_reg_153;
ap_reg_ppstg_i_index_read_reg_153_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_153_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_147_pp0_it1 <= i_sample_read_reg_147;
ap_reg_ppstg_i_sample_read_reg_147_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_147_pp0_it1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
i_index_read_reg_153 <= i_index;
i_sample_read_reg_147 <= i_sample;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_samples_load_new5_reg_165 <= {{indices_datain[ap_const_lv32_2F : ap_const_lv32_20]}};
end
end
/// ap_done assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3 or indices_rsp_empty_n or ap_ce)
begin
if (((~(ap_const_logic_1 == ap_start) & (ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0)) | ((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it3) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2 or ap_reg_ppiten_pp0_it3)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it3))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or indices_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_pprstidle_pp0 assign process. ///
always @ (ap_start or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it2)
begin
if (((ap_const_logic_0 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it1) & (ap_const_logic_0 == ap_reg_ppiten_pp0_it2) & (ap_const_logic_0 == ap_start))) begin
ap_sig_pprstidle_pp0 = ap_const_logic_1;
end else begin
ap_sig_pprstidle_pp0 = ap_const_logic_0;
end
end
/// indices_req_write assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or indices_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_req_write = ap_const_logic_1;
end else begin
indices_req_write = ap_const_logic_0;
end
end
/// indices_rsp_read assign process. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or indices_rsp_empty_n or ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 == ap_CS_fsm) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & ~(((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_start == ap_const_logic_0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it2) & (indices_rsp_empty_n == ap_const_logic_0))) & (ap_const_logic_1 == ap_ce))) begin
indices_rsp_read = ap_const_logic_1;
end else begin
indices_rsp_read = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it2 or indices_rsp_empty_n or ap_ce or ap_sig_pprstidle_pp0)
begin
case (ap_CS_fsm)
ap_ST_pp0_stg0_fsm_0 :
ap_NS_fsm = ap_ST_pp0_stg0_fsm_0;
default :
ap_NS_fsm = 'bx;
endcase
end
assign agg_result_index_write_assign_fu_128_p3 = ((tmp_8_fu_104_p2)? ap_reg_ppstg_i_index_read_reg_153_pp0_it2: tmp_9_fu_110_p2);
assign agg_result_sample_write_assign_fu_120_p3 = ((tmp_8_fu_104_p2)? tmp_1_fu_115_p2: ap_const_lv16_0);
assign ap_reg_ppiten_pp0_it0 = ap_start;
assign ap_return_0 = agg_result_index_write_assign_fu_128_p3;
assign ap_return_1 = agg_result_sample_write_assign_fu_120_p3;
assign indices_address = tmp_s_fu_67_p1;
assign indices_dataout = ap_const_lv56_0;
assign indices_req_din = ap_const_logic_0;
assign indices_size = ap_const_lv32_1;
assign tmp_1_fu_115_p2 = (ap_reg_ppstg_i_sample_read_reg_147_pp0_it2 + ap_const_lv16_1);
assign tmp_6_cast_fu_91_p1 = $unsigned(indices_samples_load_new5_reg_165);
assign tmp_7_fu_94_p2 = (tmp_6_cast_fu_91_p1 + ap_const_lv17_1FFFF);
assign tmp_8_fu_104_p1 = $signed(tmp_7_fu_94_p2);
assign tmp_8_fu_104_p2 = ($signed(tmp_cast_fu_88_p1) < $signed(tmp_8_fu_104_p1)? 1'b1: 1'b0);
assign tmp_9_fu_110_p2 = (ap_reg_ppstg_i_index_read_reg_153_pp0_it2 + ap_const_lv16_1);
assign tmp_cast_fu_88_p1 = $unsigned(ap_reg_ppstg_i_sample_read_reg_147_pp0_it2);
assign tmp_s_fu_67_p1 = $unsigned(i_index);
endmodule //sample_iterator_next
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:14:01 03/09/2017
// Design Name:
// Module Name: SimpleAI_TB
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SimpleAI_TB;
reg [8:0] X_state;
reg [8:0] O_state;
wire [8:0] AI_move;
integer i, j;
initial begin
#10;
// do stuff
/*X_state = 9'b000000000;
O_state = 9'b000000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
// do stuff
X_state = 9'b000010000;
O_state = 9'b100000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
// do stuff
X_state = 9'b000010001;
O_state = 9'b101000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
// do stuff
X_state = 9'b010010001;
O_state = 9'b101100000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
*/
X_state = 9'b00010000;
O_state = 9'b01000000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b100000000;
O_state = 9'b000010000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b110000000;
O_state = 9'b000110000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#10;
X_state = 9'b10001001;
O_state = 9'b001101000;
#5;
$display("X-state: %b O-state: %b Predicted Move: %b", X_state, O_state, AI_move);
#200;
$finish;
end
//always #5 clk = ~clk;
SimpleAI sa (
X_state,
O_state,
AI_move
);
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:46:27 02/23/2009
// Design Name:
// Module Name: MSG_utils
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_TX_MSG (
input clk,
input clkdiv,
input rst,
input [39:0] data_in,
input empty,
output reg rden,
output OSER_OQ,
input ack_r_one,
input nack_r_one,
output reg txmsg_miss_one, // one cycle signal to indicate a TXMSG wasn't correctly received by another Sora-FRL end
output reg txmsg_pass_one, // one cycle signal to indicate a TXMSG was correctly received by another Sora-FRL end
input msg_r_p_one,
input msg_r_n_one,
input training_done
);
reg [7:0] frame_data;
wire NotReady;
reg msg_r_p_signal;
reg msg_r_n_signal;
// reg [8:0] count;
parameter MSG_HEADER = 8'hF5;
parameter MSG_SIZE = 8'h06;
parameter ACK_SYM = 8'h5F;
parameter NACK_SYM = 8'hAF;
parameter DUMMY_WAIT = 8'h44;
parameter TIME_OUT = 9'h150;
parameter RETRY_MAX = 3'b011; // retransmit 3 times
// reg RDEN_REG;
// assign RDEN = RDEN_REG;
parameter IDLE = 10'b00_0000_0001;
parameter HEADER = 10'b00_0000_0010;
parameter SIZE = 10'b00_0000_0100;
parameter ADDR = 10'b00_0000_1000;
parameter DATA_1 = 10'b00_0001_0000;
parameter DATA_2 = 10'b00_0010_0000;
parameter DATA_3 = 10'b00_0100_0000;
parameter DATA_4 = 10'b00_1000_0000;
parameter CRC = 10'b01_0000_0000;
parameter WAIT_FOR_ACK = 10'b10_0000_0000;
reg [9:0] msg_framer_state;
reg [8:0] cnt;
// calculate CRC8
wire [7:0] CRC8;
// RCB_FRL_CRC_gen RCB_FRL_CRC_gen_inst (
CRC8_gen RCB_FRL_CRC_gen_inst (
.D({MSG_SIZE,data_in[39:0]}),
.NewCRC(CRC8)
);
// Do not send out control message in training stage
assign NotReady = empty | (~training_done);
// reg [3:0] times; // for each control message, we will retransmit up to 3 times
reg [3:0] retry_cnt;
always@(posedge clkdiv) begin
if (rst) begin
rden <= 1'b0;
retry_cnt <= 3'b000;
cnt <= 9'h000;
frame_data[7:0] <= 8'h00;
msg_framer_state <= IDLE;
end else begin
case(msg_framer_state)
IDLE: begin
cnt <= 9'h000;
retry_cnt <= 3'b000;
if(msg_r_p_signal) begin
rden <= 1'b0;
frame_data[7:0] <= ACK_SYM;
msg_framer_state <= IDLE;
end else if (msg_r_n_signal) begin
rden <= 1'b0;
frame_data[7:0] <= NACK_SYM;
msg_framer_state <= IDLE;
end else if (!NotReady) begin
rden <= 1'b1;
frame_data[7:0] <= 8'h00;
msg_framer_state <= HEADER;
end else begin
rden <= 1'b0;
frame_data[7:0] <= 8'h00;
msg_framer_state <= IDLE;
end
end
HEADER: begin
rden <= 1'b0;
retry_cnt <= retry_cnt;
cnt <= 9'h000;
frame_data[7:0] <= MSG_HEADER;
msg_framer_state <= SIZE;
end
SIZE: begin
rden <= 1'b0;
retry_cnt <= retry_cnt;
cnt <= 9'h000;
frame_data[7:0] <= MSG_SIZE;
msg_framer_state <= ADDR;
end
ADDR: begin
rden <= 1'b0;
retry_cnt <= retry_cnt;
cnt <= 9'h000;
frame_data[7:0] <= data_in[39:32];
msg_framer_state <= DATA_1;
end
DATA_1: begin
rden <= 1'b0;
retry_cnt <= retry_cnt;
cnt <= 9'h000;
frame_data[7:0] <= data_in[31:24];
msg_framer_state <= DATA_2;
end
DATA_2: begin
rden <= 1'b0;
retry_cnt <= retry_cnt;
cnt <= 9'h000;
frame_data[7:0] <= data_in[23:16];
msg_framer_state <= DATA_3;
end
DATA_3: begin
rden <= 1'b0;
retry_cnt <= retry_cnt;
cnt <= 9'h000;
frame_data[7:0] <= data_in[15:8];
msg_framer_state <= DATA_4;
end
DATA_4: begin
rden <= 1'b0;
retry_cnt <= retry_cnt;
cnt <= 9'h000;
frame_data[7:0] <= data_in[7:0];
msg_framer_state <= CRC;
end
CRC: begin
rden <= 1'b0;
retry_cnt <= retry_cnt;
cnt <= 9'h000;
frame_data[7:0] <= CRC8;
msg_framer_state <= WAIT_FOR_ACK;
end
WAIT_FOR_ACK: begin
rden <= 1'b0;
cnt <= cnt + 9'h001;
if (cnt > 9'h001) begin // leave two cycle space between a message and an ACK/NACK,
// it will be easier for decoder to handle
if (msg_r_p_signal)
frame_data[7:0] <= ACK_SYM;
else if (msg_r_n_signal)
frame_data[7:0] <= NACK_SYM;
else
frame_data[7:0] <= DUMMY_WAIT;
end else
frame_data[7:0] <= DUMMY_WAIT;
if (ack_r_one) begin
retry_cnt <= 3'b000;
msg_framer_state <= IDLE;
end else if ( nack_r_one | (cnt > TIME_OUT) ) begin
if (retry_cnt >= RETRY_MAX) begin
retry_cnt <= 3'b000;
msg_framer_state <= IDLE;
end else begin
retry_cnt <= retry_cnt + 3'b001;
msg_framer_state <= HEADER;
end
end else begin
retry_cnt <= retry_cnt;
msg_framer_state <= WAIT_FOR_ACK;
end
end
default: begin
rden <= 1'b0;
retry_cnt <= 3'b000;
cnt <= 9'h000;
frame_data[7:0] <= 8'h00;
msg_framer_state <= IDLE;
end
endcase
end
end
// msg_r_p_signal
always@(posedge clkdiv) begin
if (rst)
msg_r_p_signal <= 1'b0;
else if (msg_r_p_one)
msg_r_p_signal <= 1'b1;
else if ( (msg_framer_state == IDLE) | ((msg_framer_state == WAIT_FOR_ACK)&(cnt > 9'h001)) )
msg_r_p_signal <= 1'b0;
else
msg_r_p_signal <= msg_r_p_signal;
end
// msg_r_n_signal
always@(posedge clkdiv) begin
if (rst)
msg_r_n_signal <= 1'b0;
else if (msg_r_n_one)
msg_r_n_signal <= 1'b1;
else if ( (msg_framer_state == IDLE) | ((msg_framer_state == WAIT_FOR_ACK)&(cnt > 9'h001)) )
msg_r_n_signal <= 1'b0;
else
msg_r_n_signal <= msg_r_n_signal;
end
// txmsg_miss_one
always@(posedge clkdiv) begin
if(rst)
txmsg_miss_one <= 1'b0;
else if ( (retry_cnt >= RETRY_MAX) & (cnt > TIME_OUT | nack_r_one) )
txmsg_miss_one <= 1'b1;
else
txmsg_miss_one <= 1'b0;
end
// txmsg_pass_one
always@(posedge clkdiv) begin
if(rst)
txmsg_pass_one <= 1'b0;
else if ( (msg_framer_state == WAIT_FOR_ACK) & (ack_r_one) )
txmsg_pass_one <= 1'b1;
else
txmsg_pass_one <= 1'b0;
end
// // main msg_framer_state machine
// always@(posedge clkdiv) begin
// if (rst) begin
// count <= 9'h000;
// RDEN_REG <= 1'b0;
// TXMSG_MISS <= 1'b0;
// TXMSG_PASS <= 1'b0;
// times <= 4'h0;
// end
// else begin
// if (count == 9'h1FF | count == 9'h1FE) begin
// count <= 9'h000;
// end else if (count == 9'h000) begin
// if (msg_r_p) begin // Jiansong: ACK or NACK first
// count <= 9'h1FF;
// end else if (msg_r_n) begin
// count <= 9'h1FE;
// end else begin
// if ( NotReady && (times == 4'h0) ) begin
// count <= 9'h000;
// end else begin // (!NotReady | times == 4'h1 | times ==4'h2)
// count <= 9'h001;
// end
// end
// RDEN_REG <= 1'b0;
// TXMSG_MISS <= 1'b0;
// TXMSG_PASS <= 1'b0;
// times <= times;
// end else if (count == 9'h001) begin
// count <= 9'h002;
//
// if (times == 4'h0)
// RDEN_REG <= 1'b1;
// else
// RDEN_REG <= 1'b0;
//
// times <= times + 4'h1;
//
// TXMSG_MISS <= 1'b0;
// TXMSG_PASS <= 1'b0;
// end else if (count == 9'h002) begin
// count <= 9'h003;
// RDEN_REG <= 1'b0;
// TXMSG_MISS <= 1'b0;
// TXMSG_PASS <= 1'b0;
// times <= times;
// end else if (count < 9'h009) begin // ignore ACK/NACK in message transmission period
// count <= count + 9'h001;
// RDEN_REG <= 1'b0;
// TXMSG_MISS <= 1'b0;
// TXMSG_PASS <= 1'b0;
// times <= times;
// end else begin
// if(ACK | NACK | count == 9'h150)
// count <= 9'h000;
// else
// count <= count + 9'h001;
//
// RDEN_REG <= 1'b0;
//
// if(ACK) begin
// times <= 4'h0;
// TXMSG_PASS <= 1'b1;
// TXMSG_MISS <= 1'b0;
// end else if (NACK | count == 9'h150) begin
// if (times == 4'h3) begin
// times <= 4'h0;
// TXMSG_MISS <= 1'b1;
// end else begin
// times <= times;
// TXMSG_MISS <= 1'b0;
// end
// TXMSG_PASS <= 1'b0;
// end else begin
// times <= times;
// TXMSG_PASS <= 1'b0;
// TXMSG_MISS <= 1'b0;
// end
// end
// end
// end
//
// // frame encapsulation
// always@(posedge clkdiv) begin
// if (rst)
// frame_data[7:0] <= 8'h00;
// else if (count == 9'h001)
// frame_data[7:0] <= 8'hF5;
// else if (count == 9'h002)
// frame_data[7:0] <= MSG_SIZE;
// else if (count == 9'h000)
// frame_data[7:0] <= 8'h44; // send 8'h44 on idle msg_framer_state
// else if (count == 9'h003)
// frame_data[7:0] <= data_in[39:32];
// else if (count == 9'h004)
// frame_data[7:0] <= data_in[31:24];
// else if (count == 9'h005)
// frame_data[7:0] <= data_in[23:16];
// else if (count == 9'h006)
// frame_data[7:0] <= data_in[15:8];
// else if (count == 9'h007)
// frame_data[7:0] <= data_in[7:0];
// else if (count == 9'h008)
// frame_data[7:0] <= CRC[7:0];
// else if (count == 9'h1FF)
// frame_data[7:0] <= 8'h5f;
// else if (count == 9'h1FE)
// frame_data[7:0] <= 8'haf;
// else
// frame_data[7:0] <= 8'h00;
// end
// wire [7:0] PATTERN;
// RCB_FRL_TrainingPattern RCB_FRL_TrainingPattern_inst(
// .clk(clkdiv),
// .rst(rst),
// .trainingpattern(PATTERN)
// );
wire [7:0] data_to_oserdes;
// assign data_to_oserdes = training_done ? frame_data : PATTERN;
assign data_to_oserdes = training_done ? frame_data : 8'h5c; // training pattern for spartan6
RCB_FRL_OSERDES_MSG RCB_FRL_OSERDES_MSG_inst (
.OQ(OSER_OQ),
.clk(clk),
.clkdiv(clkdiv),
.DI(data_to_oserdes),
.OCE(1'b1),
.SR(rst)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_regs.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// Registers of the uart 16550 core ////
//// ////
//// Known problems (limits): ////
//// Inserts 1 wait state in all WISHBONE transfers ////
//// ////
//// To Do: ////
//// Nothing or verification. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: (See log for the revision history ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Jacob Gorban, [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_regs.v,v $
// Revision 1.10 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.9 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.8 2001/05/29 20:05:04 gorban
// Fixed some bugs and synthesis problems.
//
// Revision 1.7 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.6 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.5 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
`include "timescale.v"
`include "uart_defines.v"
`define UART_DL1 7:0
`define UART_DL2 15:8
module uart_regs (clk,
wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
// additional signals
modem_inputs,
stx_pad_o, srx_pad_i,
enable,
rts_pad_o, dtr_pad_o, int_o
);
input clk;
input wb_rst_i;
input [`UART_ADDR_WIDTH-1:0] wb_addr_i;
input [7:0] wb_dat_i;
output [7:0] wb_dat_o;
input wb_we_i;
input wb_re_i;
output stx_pad_o;
input srx_pad_i;
input [3:0] modem_inputs;
output enable;
output rts_pad_o;
output dtr_pad_o;
output int_o;
wire [3:0] modem_inputs;
reg enable;
wire stx_pad_o; // received from transmitter module
wire srx_pad_i;
reg [7:0] wb_dat_o;
wire [`UART_ADDR_WIDTH-1:0] wb_addr_i;
wire [7:0] wb_dat_i;
reg [3:0] ier;
reg [3:0] iir;
reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
reg [4:0] mcr;
reg [7:0] lcr;
reg [7:0] lsr;
reg [7:0] msr;
reg [15:0] dl; // 32-bit divisor latch
reg start_dlc; // activate dlc on writing to UART_DL1
reg lsr_mask;
reg msi_reset; // reset MSR 4 lower bits indicator
reg threi_clear; // THRE interrupt clear flag
reg [15:0] dlc; // 32-bit divisor latch counter
reg int_o;
reg [3:0] trigger_level; // trigger level of the receiver FIFO
reg rx_reset;
reg tx_reset;
wire dlab; // divisor latch access bit
wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
wire loopback; // loopback bit (MCR bit 4)
wire cts, dsr, ri, dcd; // effective signals (considering loopback)
wire rts_pad_o, dtr_pad_o; // modem control outputs
//
// ASSINGS
//
assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
: ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign dlab = lcr[`UART_LC_DL];
assign loopback = mcr[4];
// assign modem outputs
assign rts_pad_o = mcr[`UART_MC_RTS];
assign dtr_pad_o = mcr[`UART_MC_DTR];
// Interrupt signals
reg rls_int; // receiver line status interrupt
reg rda_int; // receiver data available interrupt
reg ti_int; // timeout indicator interrupt
reg thre_int; // transmitter holding register empty interrupt
reg ms_int; // modem status interrupt
// FIFO signals
reg tf_push;
reg rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] state;
wire [5:0] counter_t;
wire [3:0] counter_b;
wire rx_lsr_mask;
// Transmitter Instance
uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, state, tf_count, tx_reset);
// Receiver Instance
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable, rda_int,
counter_t, counter_b, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, rx_lsr_mask);
/*
always @(posedge clk or posedge wb_rst_i) // synchrounous reading
begin
if (wb_rst_i)
begin
wb_dat_o <= #1 8'b0;
end
else
if (wb_re_i) //if (we're not writing)
case (wb_addr_i)
`UART_REG_RB : if (dlab) // Receiver FIFO or DL byte 1
wb_dat_o <= #1 dl[`UART_DL1];
else
wb_dat_o <= #1 rf_data_out[9:2];
`UART_REG_IE : wb_dat_o <= #1 dlab ? dl[`UART_DL2] : ier;
`UART_REG_II : wb_dat_o <= #1 {4'b1100,iir};
`UART_REG_LC : wb_dat_o <= #1 lcr;
`UART_REG_LS : wb_dat_o <= #1 lsr;
`UART_REG_MS : wb_dat_o <= #1 msr;
default: wb_dat_o <= #1 8'b0; // ??
endcase
else
wb_dat_o <= #1 8'b0;
end
*/
always @(wb_addr_i or dlab or dl or rf_data_out or ier or iir or lcr or lsr or msr)
begin
case (wb_addr_i)
`UART_REG_RB : if (dlab) // Receiver FIFO or DL byte 1
wb_dat_o <= dl[`UART_DL1];
else
wb_dat_o <= rf_data_out[9:2];
`UART_REG_IE : wb_dat_o <= dlab ? dl[`UART_DL2] : ier;
`UART_REG_II : wb_dat_o <= {4'b1100,iir};
`UART_REG_LC : wb_dat_o <= lcr;
`UART_REG_LS : wb_dat_o <= lsr;
`UART_REG_MS : wb_dat_o <= msr;
default: wb_dat_o <= 8'b0; // ??
endcase
end
// rf_pop signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
rf_pop <= #1 0;
else
if (rf_pop) // restore the signal to 0 after one clock cycle
rf_pop <= #1 0;
else
if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
rf_pop <= #1 1; // advance read pointer
end
// lsr_mask signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
lsr_mask <= #1 0;
else
if (lsr_mask)
lsr_mask <= #1 0;
else
if (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab)
lsr_mask <= #1 1; // reset bits in the Line Status Register
end
assign rx_lsr_mask = lsr_mask;
// msi_reset signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
msi_reset <= #1 0;
else
if (msi_reset)
msi_reset <= #1 0;
else
if (wb_re_i && wb_addr_i == `UART_REG_MS)
msi_reset <= #1 1; // reset bits in Modem Status Register
end
// threi_clear signal handling
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
threi_clear <= #1 0;
else
if (threi_clear && !lsr[`UART_LS_TFE] && (tf_count==0)) // reset clear flag when tx fifo clears
threi_clear <= #1 0;
else
if (wb_re_i && wb_addr_i == `UART_REG_II)
threi_clear <= #1 1; // reset bits in Modem Status Register
end
//
// WRITES AND RESETS //
//
// Line Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
lcr <= #1 8'b00000011; // 8n1 setting
else
if (wb_we_i && wb_addr_i==`UART_REG_LC)
lcr <= #1 wb_dat_i;
// Interrupt Enable Register or UART_DL2
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
ier <= #1 4'b0000; // no interrupts after reset
dl[`UART_DL2] <= #1 8'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_IE)
if (dlab)
begin
dl[`UART_DL2] <= #1 wb_dat_i;
end
else
ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb
// FIFO Control Register and rx_reset, tx_reset signals
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i) begin
fcr <= #1 2'b11;
rx_reset <= #1 0;
tx_reset <= #1 0;
end else
if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
fcr <= #1 wb_dat_i[7:6];
rx_reset <= #1 wb_dat_i[1];
tx_reset <= #1 wb_dat_i[2];
end else begin // clear rx_reset, tx_reset signals when not written to
rx_reset <= #1 0;
tx_reset <= #1 0;
end
// Modem Control Register
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
mcr <= #1 5'b0;
else
if (wb_we_i && wb_addr_i==`UART_REG_MC)
mcr <= #1 wb_dat_i[4:0];
// TX_FIFO or UART_DL1
always @(posedge clk or posedge wb_rst_i)
if (wb_rst_i)
begin
dl[`UART_DL1] <= #1 8'b0;
tf_push <= #1 1'b0;
start_dlc <= #1 1'b0;
end
else
if (wb_we_i && wb_addr_i==`UART_REG_TR)
if (dlab)
begin
dl[`UART_DL1] <= #1 wb_dat_i;
start_dlc <= #1 1'b1; // enable DL counter
tf_push <= #1 1'b0;
end
else
begin
tf_push <= #1 1'b1;
start_dlc <= #1 1'b0;
end
else
begin
start_dlc <= #1 1'b0;
tf_push <= #1 1'b0;
end
// Receiver FIFO trigger level selection logic (asynchronous mux)
always @(fcr[`UART_FC_TL])
case (fcr[`UART_FC_TL])
2'b00 : trigger_level = 1;
2'b01 : trigger_level = 4;
2'b10 : trigger_level = 8;
2'b11 : trigger_level = 14;
endcase
//
// STATUS REGISTERS //
//
// Modem Status Register
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
msr <= #1 0;
else begin
msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ msr[`UART_MS_CDCD:`UART_MS_CCTS]);
msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd, ri, dsr, cts};
end
end
// Line Status Register
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
lsr <= #1 8'b01100000;
else
if (lsr_mask)
lsr <= #1 lsr & 8'b00000001;
else
begin
lsr[0] <= #1 (rf_count!=4'b0); // data in receiver fifo available
lsr[1] <= #1 rf_overrun; // Receiver overrun error
lsr[2] <= #1 rf_data_out[1]; // parity error bit
lsr[3] <= #1 rf_data_out[0]; // framing error bit
lsr[4] <= #1 (counter_b==4'b0); // break counter reached 0
lsr[5] <= #1 (tf_count==5'b0); // transmitter fifo is empty
lsr[6] <= #1 (tf_count==5'b0 && (state == /*`S_IDLE */ 0)); // transmitter empty
lsr[7] <= #1 rf_error_bit;
end
end
// Enable signal generation logic
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
dlc <= #1 0;
enable <= #1 1'b0;
end
else
begin
if (start_dlc)
begin
enable <= #1 1'b0;
dlc <= #1 dl;
end
else
begin
if (dl!=0)
begin
if ( (dlc-1)==0 )
begin
enable <= #1 1'b1;
dlc <= #1 dl;
end
else
begin
enable <= #1 1'b0;
dlc <= #1 dlc - 1;
end
end
else
begin
dlc <= #1 0;
enable <= #1 1'b0;
end
end
end
end
//
// INTERRUPT LOGIC
//
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
rls_int <= #1 1'b0;
rda_int <= #1 1'b0;
ti_int <= #1 1'b0;
thre_int <= #1 1'b0;
ms_int <= #1 1'b0;
end
else
begin
rls_int <= #1 ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
rda_int <= #1 ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
thre_int <= #1 threi_clear ? 0 : ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
ms_int <= #1 ier[`UART_IE_MS] && (| msr[3:0]);
ti_int <= #1 ier[`UART_IE_RDA] && (counter_t == 6'b0);
end
end
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
int_o <= #1 1'b0;
else
if (| {rls_int,rda_int,thre_int,ms_int,ti_int})
int_o <= #1 1'b1;
else
int_o <= #1 1'b0;
end
// Interrupt Identification register
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
iir <= #1 1;
else
if (rls_int) // interrupt occured and is enabled (not masked)
begin
iir[`UART_II_II] <= #1 `UART_II_RLS; // set identification register to correct value
iir[`UART_II_IP] <= #1 1'b0; // and clear the IIR bit 0 (interrupt pending)
end
else
if (rda_int)
begin
iir[`UART_II_II] <= #1 `UART_II_RDA;
iir[`UART_II_IP] <= #1 1'b0;
end
else
if (ti_int)
begin
iir[`UART_II_II] <= #1 `UART_II_TI;
iir[`UART_II_IP] <= #1 1'b0;
end
else
if (thre_int)
begin
iir[`UART_II_II] <= #1 `UART_II_THRE;
iir[`UART_II_IP] <= #1 1'b0;
end
else
if (ms_int)
begin
iir[`UART_II_II] <= #1 `UART_II_MS;
iir[`UART_II_IP] <= #1 1'b0;
end
else // no interrupt is pending
begin
iir[`UART_II_IP] <= #1 1'b1;
end
end
endmodule
|
module loopback (
vjtag_byteenable,
vjtag_writedata,
vjtag_address,
sdram_readdatavalid,
sdram_waitrequest,
sdram_readdata,
vjtag_write,
vjtag_read,
rst,
clk,
leds,
vjtag_readdata,
vjtag_waitrequest,
vjtag_readdatavalid,
sdram_address,
sdram_read,
sdram_write,
sdram_writedata,
sdram_byteenable
);
input [3:0] vjtag_byteenable;
input [31:0] vjtag_writedata;
input [31:0] vjtag_address;
input sdram_readdatavalid;
input sdram_waitrequest;
input [31:0] sdram_readdata;
input vjtag_write;
input vjtag_read;
input rst;
input clk;
output [7:0] leds;
output [31:0] vjtag_readdata;
output vjtag_waitrequest;
output vjtag_readdatavalid;
output [31:0] sdram_address;
output sdram_read;
output sdram_write;
output [31:0] sdram_writedata;
output [3:0] sdram_byteenable;
/* signal declarations */
wire _48;
wire [7:0] _50 = 8'b00000000;
wire vdd = 1'b1;
wire [7:0] _51 = 8'b00000000;
wire _47;
wire [7:0] _53 = 8'b00000001;
wire [7:0] _54;
wire [7:0] _49;
reg [7:0] _52;
/* logic */
assign _48 = vjtag_read | vjtag_write;
assign _47 = ~ rst;
assign _54 = _52 + _53;
assign _49 = _54;
always @(posedge clk or posedge _47) begin
if (_47)
_52 <= _51;
else
if (_48)
_52 <= _49;
end
/* aliases */
/* output assignments */
assign leds = _52;
assign vjtag_readdata = sdram_readdata;
assign vjtag_waitrequest = sdram_waitrequest;
assign vjtag_readdatavalid = sdram_readdatavalid;
assign sdram_address = vjtag_address;
assign sdram_read = vjtag_read;
assign sdram_write = vjtag_write;
assign sdram_writedata = vjtag_writedata;
assign sdram_byteenable = vjtag_byteenable;
endmodule
module de0_nano_sdram
(
input [1:0] GPIO_1_IN,
input [1:0] GPIO_0_IN,
input [2:0] GPIO_2_IN,
input ADC_SDAT,
input G_SENSOR_INT,
input EPCS_DATA0,
input [3:0] SW,
input [1:0] KEY,
input CLOCK_50,
output ADC_SCLK,
output ADC_SADDR,
output ADC_CS_N,
output I2C_SCLK,
output G_SENSOR_CS_N,
output EPCS_NCSO,
output EPCS_DCLK,
output EPCS_ASDO,
output DRAM_WE_N,
output DRAM_RAS_N,
output [1:0] DRAM_DQM,
output DRAM_CS_N,
output DRAM_CKE,
output DRAM_CAS_N,
output [1:0] DRAM_BA,
output [12:0] DRAM_ADDR,
output DRAM_CLK,
output [7:0] LED,
inout [33:0] GPIO_1,
inout [33:0] GPIO_0,
inout [12:0] GPIO_2,
inout I2C_SDAT,
inout [15:0] DRAM_DQ
);
wire _1;
wire _2;
wire _3;
wire _4;
wire _5;
wire _6;
wire _39;
wire _40;
wire _41;
wire _43;
wire _44;
wire [31:0] _45;
wire _46;
wire _47;
wire [3:0] _48;
wire [31:0] _49;
wire _50;
wire _51;
wire [31:0] _52;
wire [3:0] _54;
wire [31:0] _55;
wire _56;
wire _57;
wire [31:0] _58;
wire _59;
wire _60;
wire _61;
wire _62;
wire _63;
wire _64;
wire [1:0] _65;
wire _66;
wire _67;
wire _68;
wire [1:0] _69;
wire [12:0] _70;
wire _71;
wire _72;
wire [31:0] _73;
wire [3:0] _75;
wire [31:0] _76;
wire _77;
wire _78;
wire [31:0] _79;
wire _80;
wire _81;
wire [31:0] _82;
wire [7:0] _83;
wire [33:0] _85;
wire [12:0] _86;
wire _87;
assign _1 = 1'b1;
assign _2 = 1'b0;
assign _43 = _80;
assign _44 = _81;
assign _45 = _82;
assign _46 = _39;
assign _47 = _41;
assign _54 = _75;
assign _55 = _76;
assign _56 = _77;
assign _57 = _78;
assign _58 = _79;
assign _59 = _2;
assign _60 = _1;
assign _61 = _39;
assign _62 = _41;
assign _85 = 34'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
assign _86 = 13'bzzzzzzzzzzzzz;
assign _87 = 1'bz;
assign ADC_SCLK = _2;
assign ADC_SADDR = _2;
assign ADC_CS_N = _1;
assign I2C_SCLK = _2;
assign G_SENSOR_CS_N = _1;
assign EPCS_NCSO = _2;
assign EPCS_DCLK = _2;
assign EPCS_ASDO = _2;
assign DRAM_WE_N = _63;
assign DRAM_RAS_N = _64;
assign DRAM_DQM = _65;
assign DRAM_CS_N = _66;
assign DRAM_CKE = _67;
assign DRAM_CAS_N = _68;
assign DRAM_BA = _69;
assign DRAM_ADDR = _70;
assign DRAM_CLK = _40;
assign LED = _83;
assign GPIO_1 = _85;
assign GPIO_0 = _85;
assign GPIO_2 = _86;
assign I2C_SDAT = _87;
pll50 _42
(
.inclk0(CLOCK_50),
.c0(_41),
.c1(_40),
.locked(_39)
);
vjtag_mm _53
(
.clk_clk(_47),
.reset_reset_n(_46),
.vjtag_mm_readdata(_45),
.vjtag_mm_waitrequest(_44),
.vjtag_mm_readdatavalid(_43),
.vjtag_mm_address(_52),
.vjtag_mm_read(_51),
.vjtag_mm_write(_50),
.vjtag_mm_writedata(_49),
.vjtag_mm_byteenable(_48)
);
sdram _74
(
.clk_clk(_62),
.reset_reset_n(_61),
.mm_burstcount(_60),
.mm_debugaccess(_59),
.mm_address(_58),
.mm_read(_57),
.mm_write(_56),
.mm_writedata(_55),
.mm_byteenable(_54),
.mm_readdata(_73),
.mm_waitrequest(_72),
.mm_readdatavalid(_71),
.io_addr(_70),
.io_ba(_69),
.io_cas_n(_68),
.io_cke(_67),
.io_cs_n(_66),
.io_dqm(_65),
.io_ras_n(_64),
.io_we_n(_63),
.io_dq(DRAM_DQ)
);
loopback _84
(
.clk(_41),
.rst(_39),
.vjtag_address(_52),
.vjtag_read(_51),
.vjtag_write(_50),
.vjtag_writedata(_49),
.vjtag_byteenable(_48),
.sdram_readdata(_73),
.sdram_waitrequest(_72),
.sdram_readdatavalid(_71),
.leds(_83),
.vjtag_readdata(_82),
.vjtag_waitrequest(_81),
.vjtag_readdatavalid(_80),
.sdram_address(_79),
.sdram_read(_78),
.sdram_write(_77),
.sdram_writedata(_76),
.sdram_byteenable(_75)
);
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2016 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`timescale 1ps / 1ps
`define MAJOR_VERSION 1
`define MINOR_VERSION 0
`define REVISION 0
`define MAJOR_RANGE 31:28
`define MINOR_RANGE 27:20
`define REVISION_RANGE 19:16
`define FRAME_STORE_COUNT 3
module axi_atomic_gpio #(
parameter integer C_S_AXI_ADDR_WIDTH = 8,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter STROBE_WIDTH = (C_S_AXI_DATA_WIDTH / 8)
)(
input axi_clk,
input axi_rst_n,
//AXI Lite Interface
//Write Address Channel
input i_awvalid,
input [C_S_AXI_ADDR_WIDTH - 1: 0] i_awaddr,
output o_awready,
//Write Data Channel
input i_wvalid,
output o_wready,
input [C_S_AXI_DATA_WIDTH - 1: 0] i_wdata,
//Write Response Channel
output o_bvalid,
input i_bready,
output [1:0] o_bresp,
//Read Address Channel
input i_arvalid,
output o_arready,
input [C_S_AXI_ADDR_WIDTH - 1: 0] i_araddr,
//Read Data Channel
output o_rvalid,
input i_rready,
output [1:0] o_rresp,
output [C_S_AXI_DATA_WIDTH - 1: 0] o_rdata,
//GPO
output reg [15:0] o_gpo,
//Frame Pointer
input [5:0] i_cam0_slave_frame_ptr,
input [5:0] i_cam1_slave_frame_ptr,
input [5:0] i_cam2_slave_frame_ptr,
output reg [5:0] o_master_frame_ptr = 1,
//Interrupt For the MCU
output reg o_interrupt
);
//local parameters
//Address Map
localparam REG_CONTROL = 0;
localparam REG_GPO_VALUE = 1;
localparam REG_GPO_ACK = 2;
localparam REG_MASTER_FRAME_PTR = 3;
localparam REG_CAM0_SLAVE_FRAME_PTR = 4;
localparam REG_CAM1_SLAVE_FRAME_PTR = 5;
localparam REG_CAM2_SLAVE_FRAME_PTR = 6;
localparam REG_VERSION = 7;
localparam CTRL_BIT_ENABLE = 0;
//Register/Wire
//AXI Signals
wire [31:0] status;
//Simple User Interface
wire [C_S_AXI_ADDR_WIDTH - 1: 0] w_reg_address;
wire [((C_S_AXI_ADDR_WIDTH - 1) - 2): 0] w_reg_32bit_address;
reg r_reg_invalid_addr;
wire w_reg_in_rdy;
reg r_reg_in_ack_stb;
wire [C_S_AXI_DATA_WIDTH - 1: 0] w_reg_in_data;
wire w_reg_out_req;
reg r_reg_out_rdy_stb;
reg [C_S_AXI_DATA_WIDTH - 1: 0] r_reg_out_data;
wire w_axi_rst;
reg [15: 0] r_gpo_value;
reg r_enable;
reg r_new_value_stb;
//Submodules
//Convert AXI Slave signals to a simple register/address strobe
axi_lite_slave #(
.ADDR_WIDTH (C_S_AXI_ADDR_WIDTH ),
.DATA_WIDTH (C_S_AXI_DATA_WIDTH )
) axi_lite_reg_interface (
.clk (axi_clk ),
.rst (w_axi_rst ),
.i_awvalid (i_awvalid ),
.i_awaddr (i_awaddr ),
.o_awready (o_awready ),
.i_wvalid (i_wvalid ),
.o_wready (o_wready ),
.i_wdata (i_wdata ),
.o_bvalid (o_bvalid ),
.i_bready (i_bready ),
.o_bresp (o_bresp ),
.i_arvalid (i_arvalid ),
.o_arready (o_arready ),
.i_araddr (i_araddr ),
.o_rvalid (o_rvalid ),
.i_rready (i_rready ),
.o_rresp (o_rresp ),
.o_rdata (o_rdata ),
.o_reg_address (w_reg_address ),
.i_reg_invalid_addr (r_reg_invalid_addr ),
.o_reg_in_rdy (w_reg_in_rdy ),
.i_reg_in_ack_stb (r_reg_in_ack_stb ),
.o_reg_in_data (w_reg_in_data ),
.o_reg_out_req (w_reg_out_req ),
.i_reg_out_rdy_stb (r_reg_out_rdy_stb ),
.i_reg_out_data (r_reg_out_data )
);
//Asynchronous Logic
assign w_axi_rst = ~axi_rst_n;
assign w_reg_32bit_address = w_reg_address[(C_S_AXI_ADDR_WIDTH - 1): 2];
always @(*) begin
if (w_axi_rst) begin
r_gpo_value <= 0;
end
else begin
if (r_enable) begin
case(o_master_frame_ptr)
6'h01: begin
//r_gpo_value = 16'h1 << 2;
r_gpo_value = 16'h4 << 2;
end
6'h03: begin
//r_gpo_value = 16'h2 << 2;
r_gpo_value = 16'h1 << 2;
end
6'h02: begin
//r_gpo_value = 16'h4 << 2;
r_gpo_value = 16'h2 << 2;
end
6'h06: begin
//r_gpo_value = 16'h1 << 2;
r_gpo_value = 16'h4 << 2;
end
6'h07: begin
//r_gpo_value = 16'h2 << 2;
r_gpo_value = 16'h1 << 2;
end
6'h05: begin
//r_gpo_value = 16'h4 << 2;
r_gpo_value = 16'h2 << 2;
end
default: begin
r_gpo_value = 0;
end
endcase
end
end
end
//blocks
always @ (posedge axi_clk) begin
//De-assert Strobes
r_reg_in_ack_stb <= 0;
r_reg_out_rdy_stb <= 0;
r_reg_invalid_addr <= 0;
r_new_value_stb <= 0;
if (w_axi_rst) begin
o_gpo <= 0;
r_reg_out_data <= 0;
r_enable <= 0;
o_master_frame_ptr <= 0;
o_interrupt <= 0;
end
else begin
if (r_new_value_stb) begin
o_gpo <= r_gpo_value;
end
if (w_reg_in_rdy && !r_reg_in_ack_stb) begin
//From master
case (w_reg_32bit_address)
REG_CONTROL: begin
r_enable <= w_reg_in_data[CTRL_BIT_ENABLE];
o_interrupt <= 0;
end
REG_GPO_ACK: begin
o_gpo <= 0;
o_interrupt <= 1;
end
REG_MASTER_FRAME_PTR: begin
o_master_frame_ptr <= w_reg_in_data[5:0];
o_interrupt <= 0;
r_new_value_stb <= 1;
end
default: begin
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_in_ack_stb <= 1;
end
else if (w_reg_out_req && !r_reg_out_rdy_stb) begin
//To master
case (w_reg_32bit_address)
REG_CONTROL: begin
r_reg_out_data[CTRL_BIT_ENABLE] <= r_enable;
end
REG_GPO_VALUE: begin
r_reg_out_data <= o_gpo;
end
REG_MASTER_FRAME_PTR: begin
r_reg_out_data <= {26'h0, o_master_frame_ptr};
end
REG_CAM0_SLAVE_FRAME_PTR: begin
r_reg_out_data <= {26'h0, i_cam0_slave_frame_ptr};
end
REG_CAM1_SLAVE_FRAME_PTR: begin
r_reg_out_data <= {26'h0, i_cam1_slave_frame_ptr};
end
REG_CAM2_SLAVE_FRAME_PTR: begin
r_reg_out_data <= {26'h0, i_cam2_slave_frame_ptr};
end
REG_VERSION: begin
r_reg_out_data <= 32'h00;
r_reg_out_data[`MAJOR_RANGE] <= `MAJOR_VERSION;
r_reg_out_data[`MINOR_RANGE] <= `MINOR_VERSION;
r_reg_out_data[`REVISION_RANGE] <= `REVISION;
end
default: begin
r_reg_out_data <= 32'h00;
end
endcase
if (w_reg_32bit_address > REG_VERSION) begin
r_reg_invalid_addr <= 1;
end
r_reg_out_rdy_stb <= 1;
end
end
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_write_decoder(
ck,
reset_n,
do_lfsr,
dm_lfsr,
do_lfsr_step,
dm_lfsr_step,
do_code,
dm_code,
do_data,
dm_data
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
localparam DO_LFSR_WIDTH = ((AFI_RATIO == 4) ? 72 : 36);
input ck;
input reset_n;
input do_lfsr;
input dm_lfsr;
input do_lfsr_step;
input dm_lfsr_step;
input [3:0] do_code;
input [2:0] dm_code;
output [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] do_data;
output [NUMBER_OF_WORDS-1:0] dm_data;
reg do_lfsr_r;
reg dm_lfsr_r;
wire [DO_LFSR_WIDTH-1:0] do_lfsr_word;
wire [11:0] dm_lfsr_word;
wire [2 * DATA_WIDTH * AFI_RATIO - 1 : 0] do_word;
wire [NUMBER_OF_WORDS -1 : 0] dm_word;
rw_manager_data_decoder DO_decoder(
.ck(ck),
.reset_n(reset_n),
.code(do_code),
.pattern(do_word)
);
defparam DO_decoder.DATA_WIDTH = DATA_WIDTH;
defparam DO_decoder.AFI_RATIO = AFI_RATIO;
rw_manager_dm_decoder DM_decoder_i(
.ck(ck),
.reset_n(reset_n),
.code(dm_code),
.pattern(dm_word)
);
defparam DM_decoder_i.AFI_RATIO = AFI_RATIO;
generate
begin
if (AFI_RATIO == 4) begin
rw_manager_lfsr72 do_lfsr_i(
.clk(ck),
.nrst(reset_n),
.ena(do_lfsr_step),
.word(do_lfsr_word)
);
end else begin
rw_manager_lfsr36 do_lfsr_i(
.clk(ck),
.nrst(reset_n),
.ena(do_lfsr_step),
.word(do_lfsr_word)
);
end
end
endgenerate
rw_manager_lfsr12 dm_lfsr_i(
.clk(ck),
.nrst(reset_n),
.ena(dm_lfsr_step),
.word(dm_lfsr_word)
);
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
do_lfsr_r <= 1'b0;
dm_lfsr_r <= 1'b0;
end
else begin
do_lfsr_r <= do_lfsr;
dm_lfsr_r <= dm_lfsr;
end
end
assign do_data = (do_lfsr_r) ? do_lfsr_word[2 * DATA_WIDTH * AFI_RATIO - 1 : 0] : do_word;
assign dm_data = (dm_lfsr_r) ? dm_lfsr_word[NUMBER_OF_WORDS+1: 2] : dm_word;
endmodule
|
// This tests unalligned write/read access to packed arrays
module test ();
// parameters for array sizes
localparam WA = 4;
localparam WB = 4;
// 2D packed array parameters
// localparam [WA-1:0] [WB-1:0] param_bg = {WA*WB{1'b1}};
// 2D packed arrays
logic [WA-1:0] [WB-1:0] array_bg0, array_bg1, array_bg2, array_bg3, array_bg4, array_bg5, array_bg6, array_bg7, array_bg8, array_bg9; // big endian array
logic [0:WA-1] [0:WB-1] array_lt0, array_lt1, array_lt2, array_lt3, array_lt4, array_lt5, array_lt6, array_lt7, array_lt8, array_lt9; // little endian array
logic [WA*WB:0] array_1d0, array_1d1, array_1d2, array_1d3, array_1d4, array_1d5, array_1d6, array_1d7, array_1d8, array_1d9; // 1D array
logic signed [WA-1:0] [WB-1:0] array_sg0, array_sg1, array_sg2, array_sg3, array_sg4, array_sg5, array_sg6, array_sg7, array_sg8, array_sg9; // signed big endian array
// error counter
int err = 0;
initial begin
// test write to array LHS=RHS
array_bg0 = {WA*WB{1'bx}};
array_bg1 = {WA*WB{1'bx}}; array_bg1 = {WA *WB +0{1'b1}};
array_bg2 = {WA*WB{1'bx}}; array_bg2 [WA/2-1:0 ] = {WA/2*WB +0{1'b1}};
array_bg3 = {WA*WB{1'bx}}; array_bg3 [WA -1:WA/2] = {WA/2*WB +0{1'b1}};
array_bg4 = {WA*WB{1'bx}}; array_bg4 [ 0 ] = {1 *WB +0{1'b1}};
array_bg5 = {WA*WB{1'bx}}; array_bg5 [WA -1 ] = {1 *WB +0{1'b1}};
array_bg6 = {WA*WB{1'bx}}; array_bg6 [ 0 ][WB/2-1:0 ] = {1 *WB/2+0{1'b1}};
array_bg7 = {WA*WB{1'bx}}; array_bg7 [WA -1 ][WB -1:WB/2] = {1 *WB/2+0{1'b1}};
array_bg8 = {WA*WB{1'bx}}; array_bg8 [ 0 ][ 0 ] = {1 *1 +0{1'b1}};
array_bg9 = {WA*WB{1'bx}}; array_bg9 [WA -1 ][WB -1 ] = {1 *1 +0{1'b1}};
// check
if (array_bg0 !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_bg0 = 'b%b", array_bg0); err=err+1; end
if (array_bg1 !== 16'b1111_1111_1111_1111) begin $display("FAILED -- LHS=RHS -- array_bg1 = 'b%b", array_bg1); err=err+1; end
if (array_bg2 !== 16'bxxxx_xxxx_1111_1111) begin $display("FAILED -- LHS=RHS -- array_bg2 = 'b%b", array_bg2); err=err+1; end
if (array_bg3 !== 16'b1111_1111_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_bg3 = 'b%b", array_bg3); err=err+1; end
if (array_bg4 !== 16'bxxxx_xxxx_xxxx_1111) begin $display("FAILED -- LHS=RHS -- array_bg4 = 'b%b", array_bg4); err=err+1; end
if (array_bg5 !== 16'b1111_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_bg5 = 'b%b", array_bg5); err=err+1; end
if (array_bg6 !== 16'bxxxx_xxxx_xxxx_xx11) begin $display("FAILED -- LHS=RHS -- array_bg6 = 'b%b", array_bg6); err=err+1; end
if (array_bg7 !== 16'b11xx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_bg7 = 'b%b", array_bg7); err=err+1; end
if (array_bg8 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS=RHS -- array_bg8 = 'b%b", array_bg8); err=err+1; end
if (array_bg9 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_bg9 = 'b%b", array_bg9); err=err+1; end
// test write to array LHS<RHS
array_bg0 = {WA*WB{1'bx}};
array_bg1 = {WA*WB{1'bx}}; array_bg1 = {WA *WB +1{1'b1}};
array_bg2 = {WA*WB{1'bx}}; array_bg2 [WA/2-1:0 ] = {WA/2*WB +1{1'b1}};
array_bg3 = {WA*WB{1'bx}}; array_bg3 [WA -1:WA/2] = {WA/2*WB +1{1'b1}};
array_bg4 = {WA*WB{1'bx}}; array_bg4 [ 0 ] = {1 *WB +1{1'b1}};
array_bg5 = {WA*WB{1'bx}}; array_bg5 [WA -1 ] = {1 *WB +1{1'b1}};
array_bg6 = {WA*WB{1'bx}}; array_bg6 [ 0 ][WB/2-1:0 ] = {1 *WB/2+1{1'b1}};
array_bg7 = {WA*WB{1'bx}}; array_bg7 [WA -1 ][WB -1:WB/2] = {1 *WB/2+1{1'b1}};
array_bg8 = {WA*WB{1'bx}}; array_bg8 [ 0 ][ 0 ] = {1 *1 +1{1'b1}};
array_bg9 = {WA*WB{1'bx}}; array_bg9 [WA -1 ][WB -1 ] = {1 *1 +1{1'b1}};
// check
if (array_bg0 !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS<RHS -- array_bg0 = 'b%b", array_bg0); err=err+1; end
if (array_bg1 !== 16'b1111_1111_1111_1111) begin $display("FAILED -- LHS<RHS -- array_bg1 = 'b%b", array_bg1); err=err+1; end
if (array_bg2 !== 16'bxxxx_xxxx_1111_1111) begin $display("FAILED -- LHS<RHS -- array_bg2 = 'b%b", array_bg2); err=err+1; end
if (array_bg3 !== 16'b1111_1111_xxxx_xxxx) begin $display("FAILED -- LHS<RHS -- array_bg3 = 'b%b", array_bg3); err=err+1; end
if (array_bg4 !== 16'bxxxx_xxxx_xxxx_1111) begin $display("FAILED -- LHS<RHS -- array_bg4 = 'b%b", array_bg4); err=err+1; end
if (array_bg5 !== 16'b1111_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS<RHS -- array_bg5 = 'b%b", array_bg5); err=err+1; end
if (array_bg6 !== 16'bxxxx_xxxx_xxxx_xx11) begin $display("FAILED -- LHS<RHS -- array_bg6 = 'b%b", array_bg6); err=err+1; end
if (array_bg7 !== 16'b11xx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS<RHS -- array_bg7 = 'b%b", array_bg7); err=err+1; end
if (array_bg8 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS<RHS -- array_bg8 = 'b%b", array_bg8); err=err+1; end
if (array_bg9 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS<RHS -- array_bg9 = 'b%b", array_bg9); err=err+1; end
// test write to array LHS>RHS
array_bg0 = {WA*WB{1'bx}};
array_bg1 = {WA*WB{1'bx}}; array_bg1 = {WA *WB -1{1'b1}};
array_bg2 = {WA*WB{1'bx}}; array_bg2 [WA/2-1:0 ] = {WA/2*WB -1{1'b1}};
array_bg3 = {WA*WB{1'bx}}; array_bg3 [WA -1:WA/2] = {WA/2*WB -1{1'b1}};
array_bg4 = {WA*WB{1'bx}}; array_bg4 [ 0 ] = {1 *WB -1{1'b1}};
array_bg5 = {WA*WB{1'bx}}; array_bg5 [WA -1 ] = {1 *WB -1{1'b1}};
array_bg6 = {WA*WB{1'bx}}; array_bg6 [ 0 ][WB/2-1:0 ] = {1 *WB/2-1{1'b1}};
array_bg7 = {WA*WB{1'bx}}; array_bg7 [WA -1 ][WB -1:WB/2] = {1 *WB/2-1{1'b1}};
//array_bg8 = {WA*WB{1'bx}}; array_bg8 [ 0 ][ 0 ] = {1 *1 -1{1'b1}};
//array_bg9 = {WA*WB{1'bx}}; array_bg9 [WA -1 ][WB -1 ] = {1 *1 -1{1'b1}};
// check
if (array_bg0 !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_bg0 = 'b%b", array_bg0); err=err+1; end
if (array_bg1 !== 16'b0111_1111_1111_1111) begin $display("FAILED -- LHS>RHS -- array_bg1 = 'b%b", array_bg1); err=err+1; end
if (array_bg2 !== 16'bxxxx_xxxx_0111_1111) begin $display("FAILED -- LHS>RHS -- array_bg2 = 'b%b", array_bg2); err=err+1; end
if (array_bg3 !== 16'b0111_1111_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_bg3 = 'b%b", array_bg3); err=err+1; end
if (array_bg4 !== 16'bxxxx_xxxx_xxxx_0111) begin $display("FAILED -- LHS>RHS -- array_bg4 = 'b%b", array_bg4); err=err+1; end
if (array_bg5 !== 16'b0111_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_bg5 = 'b%b", array_bg5); err=err+1; end
if (array_bg6 !== 16'bxxxx_xxxx_xxxx_xx01) begin $display("FAILED -- LHS>RHS -- array_bg6 = 'b%b", array_bg6); err=err+1; end
if (array_bg7 !== 16'b01xx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_bg7 = 'b%b", array_bg7); err=err+1; end
//if (array_bg8 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS>RHS -- array_bg8 = 'b%b", array_bg8); err=err+1; end
//if (array_bg9 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_bg9 = 'b%b", array_bg9); err=err+1; end
// test write to array LHS=RHS
array_lt0 = {WA*WB{1'bx}};
array_lt1 = {WA*WB{1'bx}}; array_lt1 = {WA *WB +0{1'b1}};
array_lt2 = {WA*WB{1'bx}}; array_lt2 [0 :WA/2-1] = {WA/2*WB +0{1'b1}};
array_lt3 = {WA*WB{1'bx}}; array_lt3 [WA/2:WA -1] = {WA/2*WB +0{1'b1}};
array_lt4 = {WA*WB{1'bx}}; array_lt4 [0 ] = {1 *WB +0{1'b1}};
array_lt5 = {WA*WB{1'bx}}; array_lt5 [ WA -1] = {1 *WB +0{1'b1}};
array_lt6 = {WA*WB{1'bx}}; array_lt6 [0 ][0 :WB/2-1] = {1 *WB/2+0{1'b1}};
array_lt7 = {WA*WB{1'bx}}; array_lt7 [ WA -1][WB/2:WB -1] = {1 *WB/2+0{1'b1}};
array_lt8 = {WA*WB{1'bx}}; array_lt8 [0 ][0 ] = {1 *1 +0{1'b1}};
array_lt9 = {WA*WB{1'bx}}; array_lt9 [ WA -1][ WB -1] = {1 *1 +0{1'b1}};
// check
if (array_lt0 !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_lt0 = 'b%b", array_lt0); err=err+1; end
if (array_lt1 !== 16'b1111_1111_1111_1111) begin $display("FAILED -- LHS=RHS -- array_lt1 = 'b%b", array_lt1); err=err+1; end
if (array_lt2 !== 16'b1111_1111_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_lt2 = 'b%b", array_lt2); err=err+1; end
if (array_lt3 !== 16'bxxxx_xxxx_1111_1111) begin $display("FAILED -- LHS=RHS -- array_lt3 = 'b%b", array_lt3); err=err+1; end
if (array_lt4 !== 16'b1111_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_lt4 = 'b%b", array_lt4); err=err+1; end
if (array_lt5 !== 16'bxxxx_xxxx_xxxx_1111) begin $display("FAILED -- LHS=RHS -- array_lt5 = 'b%b", array_lt5); err=err+1; end
if (array_lt6 !== 16'b11xx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_lt6 = 'b%b", array_lt6); err=err+1; end
if (array_lt7 !== 16'bxxxx_xxxx_xxxx_xx11) begin $display("FAILED -- LHS=RHS -- array_lt7 = 'b%b", array_lt7); err=err+1; end
if (array_lt8 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS=RHS -- array_lt8 = 'b%b", array_lt8); err=err+1; end
if (array_lt9 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS=RHS -- array_lt9 = 'b%b", array_lt9); err=err+1; end
// test write to array LHS<RHS
array_lt0 = {WA*WB{1'bx}};
array_lt1 = {WA*WB{1'bx}}; array_lt1 = {WA *WB +1{1'b1}};
array_lt2 = {WA*WB{1'bx}}; array_lt2 [0 :WA/2-1] = {WA/2*WB +1{1'b1}};
array_lt3 = {WA*WB{1'bx}}; array_lt3 [WA/2:WA -1] = {WA/2*WB +1{1'b1}};
array_lt4 = {WA*WB{1'bx}}; array_lt4 [0 ] = {1 *WB +1{1'b1}};
array_lt5 = {WA*WB{1'bx}}; array_lt5 [ WA -1] = {1 *WB +1{1'b1}};
array_lt6 = {WA*WB{1'bx}}; array_lt6 [0 ][0 :WB/2-1] = {1 *WB/2+1{1'b1}};
array_lt7 = {WA*WB{1'bx}}; array_lt7 [ WA -1][WB/2:WB -1] = {1 *WB/2+1{1'b1}};
array_lt8 = {WA*WB{1'bx}}; array_lt8 [0 ][0 ] = {1 *1 +1{1'b1}};
array_lt9 = {WA*WB{1'bx}}; array_lt9 [ WA -1][ WB -1] = {1 *1 +1{1'b1}};
// check
if (array_lt0 !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS<RHS -- array_lt0 = 'b%b", array_lt0); err=err+1; end
if (array_lt1 !== 16'b1111_1111_1111_1111) begin $display("FAILED -- LHS<RHS -- array_lt1 = 'b%b", array_lt1); err=err+1; end
if (array_lt2 !== 16'b1111_1111_xxxx_xxxx) begin $display("FAILED -- LHS<RHS -- array_lt2 = 'b%b", array_lt2); err=err+1; end
if (array_lt3 !== 16'bxxxx_xxxx_1111_1111) begin $display("FAILED -- LHS<RHS -- array_lt3 = 'b%b", array_lt3); err=err+1; end
if (array_lt4 !== 16'b1111_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS<RHS -- array_lt4 = 'b%b", array_lt4); err=err+1; end
if (array_lt5 !== 16'bxxxx_xxxx_xxxx_1111) begin $display("FAILED -- LHS<RHS -- array_lt5 = 'b%b", array_lt5); err=err+1; end
if (array_lt6 !== 16'b11xx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS<RHS -- array_lt6 = 'b%b", array_lt6); err=err+1; end
if (array_lt7 !== 16'bxxxx_xxxx_xxxx_xx11) begin $display("FAILED -- LHS<RHS -- array_lt7 = 'b%b", array_lt7); err=err+1; end
if (array_lt8 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS<RHS -- array_lt8 = 'b%b", array_lt8); err=err+1; end
if (array_lt9 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS<RHS -- array_lt9 = 'b%b", array_lt9); err=err+1; end
// test write to array LHS>RHS
array_lt0 = {WA*WB{1'bx}};
array_lt1 = {WA*WB{1'bx}}; array_lt1 = {WA *WB -1{1'b1}};
array_lt2 = {WA*WB{1'bx}}; array_lt2 [0 :WA/2-1] = {WA/2*WB -1{1'b1}};
array_lt3 = {WA*WB{1'bx}}; array_lt3 [WA/2:WA -1] = {WA/2*WB -1{1'b1}};
array_lt4 = {WA*WB{1'bx}}; array_lt4 [0 ] = {1 *WB -1{1'b1}};
array_lt5 = {WA*WB{1'bx}}; array_lt5 [ WA -1] = {1 *WB -1{1'b1}};
array_lt6 = {WA*WB{1'bx}}; array_lt6 [0 ][0 :WB/2-1] = {1 *WB/2-1{1'b1}};
array_lt7 = {WA*WB{1'bx}}; array_lt7 [ WA -1][WB/2:WB -1] = {1 *WB/2-1{1'b1}};
//array_lt8 = {WA*WB{1'bx}}; array_lt8 [0 ][0 ] = {1 *1 -1{1'b1}};
//array_lt9 = {WA*WB{1'bx}}; array_lt9 [ WA -1][ WB -1] = {1 *1 -1{1'b1}};
// check
if (array_lt0 !== 16'bxxxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_lt0 = 'b%b", array_lt0); err=err+1; end
if (array_lt1 !== 16'b0111_1111_1111_1111) begin $display("FAILED -- LHS>RHS -- array_lt1 = 'b%b", array_lt1); err=err+1; end
if (array_lt2 !== 16'b0111_1111_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_lt2 = 'b%b", array_lt2); err=err+1; end
if (array_lt3 !== 16'bxxxx_xxxx_0111_1111) begin $display("FAILED -- LHS>RHS -- array_lt3 = 'b%b", array_lt3); err=err+1; end
if (array_lt4 !== 16'b0111_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_lt4 = 'b%b", array_lt4); err=err+1; end
if (array_lt5 !== 16'bxxxx_xxxx_xxxx_0111) begin $display("FAILED -- LHS>RHS -- array_lt5 = 'b%b", array_lt5); err=err+1; end
if (array_lt6 !== 16'b01xx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_lt6 = 'b%b", array_lt6); err=err+1; end
if (array_lt7 !== 16'bxxxx_xxxx_xxxx_xx01) begin $display("FAILED -- LHS>RHS -- array_lt7 = 'b%b", array_lt7); err=err+1; end
//if (array_lt8 !== 16'b1xxx_xxxx_xxxx_xxxx) begin $display("FAILED -- LHS>RHS -- array_lt8 = 'b%b", array_lt8); err=err+1; end
//if (array_lt9 !== 16'bxxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS>RHS -- array_lt9 = 'b%b", array_lt9); err=err+1; end
// assign a constant value to the array
array_bg1 = {WA*WB{1'b1}};
array_bg2 = {WA*WB{1'b1}};
array_bg3 = {WA*WB{1'b1}};
array_bg4 = {WA*WB{1'b1}};
array_bg5 = {WA*WB{1'b1}};
array_bg6 = {WA*WB{1'b1}};
array_bg7 = {WA*WB{1'b1}};
array_bg8 = {WA*WB{1'b1}};
array_bg9 = {WA*WB{1'b1}};
// test read from array LHS=RHS
array_1d1 = {WA*WB+1{1'bx}}; array_1d1[WA *WB -1+0:0] = array_bg1 ;
array_1d2 = {WA*WB+1{1'bx}}; array_1d2[WA/2*WB -1+0:0] = array_bg2 [WA/2-1:0 ] ;
array_1d3 = {WA*WB+1{1'bx}}; array_1d3[WA/2*WB -1+0:0] = array_bg3 [WA -1:WA/2] ;
array_1d4 = {WA*WB+1{1'bx}}; array_1d4[1 *WB -1+0:0] = array_bg4 [ 0 ] ;
array_1d5 = {WA*WB+1{1'bx}}; array_1d5[1 *WB -1+0:0] = array_bg5 [WA -1 ] ;
array_1d6 = {WA*WB+1{1'bx}}; array_1d6[1 *WB/2-1+0:0] = array_bg6 [ 0 ][WB/2-1:0 ];
array_1d7 = {WA*WB+1{1'bx}}; array_1d7[1 *WB/2-1+0:0] = array_bg7 [WA -1 ][WB -1:WB/2];
array_1d8 = {WA*WB+1{1'bx}}; array_1d8[1 *1 -1+0:0] = array_bg8 [ 0 ][ 0 ];
array_1d9 = {WA*WB+1{1'bx}}; array_1d9[1 *1 -1+0:0] = array_bg9 [WA -1 ][WB -1 ];
// check
if (array_1d1 !== 17'bx_1111_1111_1111_1111) begin $display("FAILED -- LHS=RHS BE -- array_1d1 = 'b%b", array_1d1); err=err+1; end
if (array_1d2 !== 17'bx_xxxx_xxxx_1111_1111) begin $display("FAILED -- LHS=RHS BE -- array_1d2 = 'b%b", array_1d2); err=err+1; end
if (array_1d3 !== 17'bx_xxxx_xxxx_1111_1111) begin $display("FAILED -- LHS=RHS BE -- array_1d3 = 'b%b", array_1d3); err=err+1; end
if (array_1d4 !== 17'bx_xxxx_xxxx_xxxx_1111) begin $display("FAILED -- LHS=RHS BE -- array_1d4 = 'b%b", array_1d4); err=err+1; end
if (array_1d5 !== 17'bx_xxxx_xxxx_xxxx_1111) begin $display("FAILED -- LHS=RHS BE -- array_1d5 = 'b%b", array_1d5); err=err+1; end
if (array_1d6 !== 17'bx_xxxx_xxxx_xxxx_xx11) begin $display("FAILED -- LHS=RHS BE -- array_1d6 = 'b%b", array_1d6); err=err+1; end
if (array_1d7 !== 17'bx_xxxx_xxxx_xxxx_xx11) begin $display("FAILED -- LHS=RHS BE -- array_1d7 = 'b%b", array_1d7); err=err+1; end
if (array_1d8 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS=RHS BE -- array_1d8 = 'b%b", array_1d8); err=err+1; end
if (array_1d9 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS=RHS BE -- array_1d9 = 'b%b", array_1d9); err=err+1; end
// test read from array LHS>RHS
array_1d1 = {WA*WB+1{1'bx}}; array_1d1[WA *WB -1+1:0] = array_bg1 ;
array_1d2 = {WA*WB+1{1'bx}}; array_1d2[WA/2*WB -1+1:0] = array_bg2 [WA/2-1:0 ] ;
array_1d3 = {WA*WB+1{1'bx}}; array_1d3[WA/2*WB -1+1:0] = array_bg3 [WA -1:WA/2] ;
array_1d4 = {WA*WB+1{1'bx}}; array_1d4[1 *WB -1+1:0] = array_bg4 [ 0 ] ;
array_1d5 = {WA*WB+1{1'bx}}; array_1d5[1 *WB -1+1:0] = array_bg5 [WA -1 ] ;
array_1d6 = {WA*WB+1{1'bx}}; array_1d6[1 *WB/2-1+1:0] = array_bg6 [ 0 ][WB/2-1:0 ];
array_1d7 = {WA*WB+1{1'bx}}; array_1d7[1 *WB/2-1+1:0] = array_bg7 [WA -1 ][WB -1:WB/2];
array_1d8 = {WA*WB+1{1'bx}}; array_1d8[1 *1 -1+1:0] = array_bg8 [ 0 ][ 0 ];
array_1d9 = {WA*WB+1{1'bx}}; array_1d9[1 *1 -1+1:0] = array_bg9 [WA -1 ][WB -1 ];
// check
if (array_1d1 !== 17'b0_1111_1111_1111_1111) begin $display("FAILED -- LHS>RHS BE -- array_1d1 = 'b%b", array_1d1); err=err+1; end
if (array_1d2 !== 17'bx_xxxx_xxx0_1111_1111) begin $display("FAILED -- LHS>RHS BE -- array_1d2 = 'b%b", array_1d2); err=err+1; end
if (array_1d3 !== 17'bx_xxxx_xxx0_1111_1111) begin $display("FAILED -- LHS>RHS BE -- array_1d3 = 'b%b", array_1d3); err=err+1; end
if (array_1d4 !== 17'bx_xxxx_xxxx_xxx0_1111) begin $display("FAILED -- LHS>RHS BE -- array_1d4 = 'b%b", array_1d4); err=err+1; end
if (array_1d5 !== 17'bx_xxxx_xxxx_xxx0_1111) begin $display("FAILED -- LHS>RHS BE -- array_1d5 = 'b%b", array_1d5); err=err+1; end
if (array_1d6 !== 17'bx_xxxx_xxxx_xxxx_x011) begin $display("FAILED -- LHS>RHS BE -- array_1d6 = 'b%b", array_1d6); err=err+1; end
if (array_1d7 !== 17'bx_xxxx_xxxx_xxxx_x011) begin $display("FAILED -- LHS>RHS BE -- array_1d7 = 'b%b", array_1d7); err=err+1; end
if (array_1d8 !== 17'bx_xxxx_xxxx_xxxx_xx01) begin $display("FAILED -- LHS>RHS BE -- array_1d8 = 'b%b", array_1d8); err=err+1; end
if (array_1d9 !== 17'bx_xxxx_xxxx_xxxx_xx01) begin $display("FAILED -- LHS>RHS BE -- array_1d9 = 'b%b", array_1d9); err=err+1; end
// test read from array LHS<RHS
array_1d1 = {WA*WB+1{1'bx}}; array_1d1[WA *WB -1-1:0] = array_bg1 ;
array_1d2 = {WA*WB+1{1'bx}}; array_1d2[WA/2*WB -1-1:0] = array_bg2 [WA/2-1:0 ] ;
array_1d3 = {WA*WB+1{1'bx}}; array_1d3[WA/2*WB -1-1:0] = array_bg3 [WA -1:WA/2] ;
array_1d4 = {WA*WB+1{1'bx}}; array_1d4[1 *WB -1-1:0] = array_bg4 [ 0 ] ;
array_1d5 = {WA*WB+1{1'bx}}; array_1d5[1 *WB -1-1:0] = array_bg5 [WA -1 ] ;
array_1d6 = {WA*WB+1{1'bx}}; array_1d6[1 *WB/2-1-1:0] = array_bg6 [ 0 ][WB/2-1:0 ];
array_1d7 = {WA*WB+1{1'bx}}; array_1d7[1 *WB/2-1-1:0] = array_bg7 [WA -1 ][WB -1:WB/2];
//array_1d8 = {WA*WB+1{1'bx}}; array_1d8[1 *1 -1-1:0] = array_bg8 [ 0 ][ 0 ];
//array_1d9 = {WA*WB+1{1'bx}}; array_1d9[1 *1 -1-1:0] = array_bg9 [WA -1 ][WB -1 ];
// check
if (array_1d1 !== 17'bx_x111_1111_1111_1111) begin $display("FAILED -- LHS<RHS BE -- array_1d1 = 'b%b", array_1d1); err=err+1; end
if (array_1d2 !== 17'bx_xxxx_xxxx_x111_1111) begin $display("FAILED -- LHS<RHS BE -- array_1d2 = 'b%b", array_1d2); err=err+1; end
if (array_1d3 !== 17'bx_xxxx_xxxx_x111_1111) begin $display("FAILED -- LHS<RHS BE -- array_1d3 = 'b%b", array_1d3); err=err+1; end
if (array_1d4 !== 17'bx_xxxx_xxxx_xxxx_x111) begin $display("FAILED -- LHS<RHS BE -- array_1d4 = 'b%b", array_1d4); err=err+1; end
if (array_1d5 !== 17'bx_xxxx_xxxx_xxxx_x111) begin $display("FAILED -- LHS<RHS BE -- array_1d5 = 'b%b", array_1d5); err=err+1; end
if (array_1d6 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS<RHS BE -- array_1d6 = 'b%b", array_1d6); err=err+1; end
if (array_1d7 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS<RHS BE -- array_1d7 = 'b%b", array_1d7); err=err+1; end
//if (array_1d8 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS<RHS BE -- array_1d8 = 'b%b", array_1d8); err=err+1; end
//if (array_1d9 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS<RHS BE -- array_1d9 = 'b%b", array_1d9); err=err+1; end
// assign a constant value to the array
array_lt1 = {WA*WB{1'b1}};
array_lt2 = {WA*WB{1'b1}};
array_lt3 = {WA*WB{1'b1}};
array_lt4 = {WA*WB{1'b1}};
array_lt5 = {WA*WB{1'b1}};
array_lt6 = {WA*WB{1'b1}};
array_lt7 = {WA*WB{1'b1}};
array_lt8 = {WA*WB{1'b1}};
array_lt9 = {WA*WB{1'b1}};
// test read from array LHS=RHS
array_1d1 = {WA*WB+1{1'bx}}; array_1d1[WA *WB -1+0:0] = array_lt1 ;
array_1d2 = {WA*WB+1{1'bx}}; array_1d2[WA/2*WB -1+0:0] = array_lt2 [0 :WA/2-1] ;
array_1d3 = {WA*WB+1{1'bx}}; array_1d3[WA/2*WB -1+0:0] = array_lt3 [WA/2:WA -1] ;
array_1d4 = {WA*WB+1{1'bx}}; array_1d4[1 *WB -1+0:0] = array_lt4 [0 ] ;
array_1d5 = {WA*WB+1{1'bx}}; array_1d5[1 *WB -1+0:0] = array_lt5 [ WA -1] ;
array_1d6 = {WA*WB+1{1'bx}}; array_1d6[1 *WB/2-1+0:0] = array_lt6 [0 ][0 :WB/2-1];
array_1d7 = {WA*WB+1{1'bx}}; array_1d7[1 *WB/2-1+0:0] = array_lt7 [ WA -1][WB/2:WB -1];
array_1d8 = {WA*WB+1{1'bx}}; array_1d8[1 *1 -1+0:0] = array_lt8 [0 ][0 ];
array_1d9 = {WA*WB+1{1'bx}}; array_1d9[1 *1 -1+0:0] = array_lt9 [ WA -1][ WB -1];
// check
if (array_1d1 !== 17'bx_1111_1111_1111_1111) begin $display("FAILED -- LHS=RHS LE -- array_1d1 = 'b%b", array_1d1); err=err+1; end
if (array_1d2 !== 17'bx_xxxx_xxxx_1111_1111) begin $display("FAILED -- LHS=RHS LE -- array_1d2 = 'b%b", array_1d2); err=err+1; end
if (array_1d3 !== 17'bx_xxxx_xxxx_1111_1111) begin $display("FAILED -- LHS=RHS LE -- array_1d3 = 'b%b", array_1d3); err=err+1; end
if (array_1d4 !== 17'bx_xxxx_xxxx_xxxx_1111) begin $display("FAILED -- LHS=RHS LE -- array_1d4 = 'b%b", array_1d4); err=err+1; end
if (array_1d5 !== 17'bx_xxxx_xxxx_xxxx_1111) begin $display("FAILED -- LHS=RHS LE -- array_1d5 = 'b%b", array_1d5); err=err+1; end
if (array_1d6 !== 17'bx_xxxx_xxxx_xxxx_xx11) begin $display("FAILED -- LHS=RHS LE -- array_1d6 = 'b%b", array_1d6); err=err+1; end
if (array_1d7 !== 17'bx_xxxx_xxxx_xxxx_xx11) begin $display("FAILED -- LHS=RHS LE -- array_1d7 = 'b%b", array_1d7); err=err+1; end
if (array_1d8 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS=RHS LE -- array_1d8 = 'b%b", array_1d8); err=err+1; end
if (array_1d9 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS=RHS LE -- array_1d9 = 'b%b", array_1d9); err=err+1; end
// test read from array LHS>RHS
array_1d1 = {WA*WB+1{1'bx}}; array_1d1[WA *WB -1+1:0] = array_lt1 ;
array_1d2 = {WA*WB+1{1'bx}}; array_1d2[WA/2*WB -1+1:0] = array_lt2 [0 :WA/2-1] ;
array_1d3 = {WA*WB+1{1'bx}}; array_1d3[WA/2*WB -1+1:0] = array_lt3 [WA/2:WA -1] ;
array_1d4 = {WA*WB+1{1'bx}}; array_1d4[1 *WB -1+1:0] = array_lt4 [0 ] ;
array_1d5 = {WA*WB+1{1'bx}}; array_1d5[1 *WB -1+1:0] = array_lt5 [ WA -1] ;
array_1d6 = {WA*WB+1{1'bx}}; array_1d6[1 *WB/2-1+1:0] = array_lt6 [0 ][0 :WB/2-1];
array_1d7 = {WA*WB+1{1'bx}}; array_1d7[1 *WB/2-1+1:0] = array_lt7 [ WA -1][WB/2:WB -1];
array_1d8 = {WA*WB+1{1'bx}}; array_1d8[1 *1 -1+1:0] = array_lt8 [0 ][0 ];
array_1d9 = {WA*WB+1{1'bx}}; array_1d9[1 *1 -1+1:0] = array_lt9 [ WA -1][ WB -1];
// check
if (array_1d1 !== 17'b0_1111_1111_1111_1111) begin $display("FAILED -- LHS>RHS LE -- array_1d1 = 'b%b", array_1d1); err=err+1; end
if (array_1d2 !== 17'bx_xxxx_xxx0_1111_1111) begin $display("FAILED -- LHS>RHS LE -- array_1d2 = 'b%b", array_1d2); err=err+1; end
if (array_1d3 !== 17'bx_xxxx_xxx0_1111_1111) begin $display("FAILED -- LHS>RHS LE -- array_1d3 = 'b%b", array_1d3); err=err+1; end
if (array_1d4 !== 17'bx_xxxx_xxxx_xxx0_1111) begin $display("FAILED -- LHS>RHS LE -- array_1d4 = 'b%b", array_1d4); err=err+1; end
if (array_1d5 !== 17'bx_xxxx_xxxx_xxx0_1111) begin $display("FAILED -- LHS>RHS LE -- array_1d5 = 'b%b", array_1d5); err=err+1; end
if (array_1d6 !== 17'bx_xxxx_xxxx_xxxx_x011) begin $display("FAILED -- LHS>RHS LE -- array_1d6 = 'b%b", array_1d6); err=err+1; end
if (array_1d7 !== 17'bx_xxxx_xxxx_xxxx_x011) begin $display("FAILED -- LHS>RHS LE -- array_1d7 = 'b%b", array_1d7); err=err+1; end
if (array_1d8 !== 17'bx_xxxx_xxxx_xxxx_xx01) begin $display("FAILED -- LHS>RHS LE -- array_1d8 = 'b%b", array_1d8); err=err+1; end
if (array_1d9 !== 17'bx_xxxx_xxxx_xxxx_xx01) begin $display("FAILED -- LHS>RHS LE -- array_1d9 = 'b%b", array_1d9); err=err+1; end
// test read from array LHS<RHS
array_1d1 = {WA*WB+1{1'bx}}; array_1d1[WA *WB -1-1:0] = array_lt1 ;
array_1d2 = {WA*WB+1{1'bx}}; array_1d2[WA/2*WB -1-1:0] = array_lt2 [0 :WA/2-1] ;
array_1d3 = {WA*WB+1{1'bx}}; array_1d3[WA/2*WB -1-1:0] = array_lt3 [WA/2:WA -1] ;
array_1d4 = {WA*WB+1{1'bx}}; array_1d4[1 *WB -1-1:0] = array_lt4 [0 ] ;
array_1d5 = {WA*WB+1{1'bx}}; array_1d5[1 *WB -1-1:0] = array_lt5 [ WA -1] ;
array_1d6 = {WA*WB+1{1'bx}}; array_1d6[1 *WB/2-1-1:0] = array_lt6 [0 ][0 :WB/2-1];
array_1d7 = {WA*WB+1{1'bx}}; array_1d7[1 *WB/2-1-1:0] = array_lt7 [ WA -1][WB/2:WB -1];
//array_1d8 = {WA*WB+1{1'bx}}; array_1d8[1 *1 -1-1:0] = array_lt8 [0 ][0 ];
//array_1d9 = {WA*WB+1{1'bx}}; array_1d9[1 *1 -1-1:0] = array_lt9 [ WA -1][ WB -1];
// check
if (array_1d1 !== 17'bx_x111_1111_1111_1111) begin $display("FAILED -- LHS<RHS LE -- array_1d1 = 'b%b", array_1d1); err=err+1; end
if (array_1d2 !== 17'bx_xxxx_xxxx_x111_1111) begin $display("FAILED -- LHS<RHS LE -- array_1d2 = 'b%b", array_1d2); err=err+1; end
if (array_1d3 !== 17'bx_xxxx_xxxx_x111_1111) begin $display("FAILED -- LHS<RHS LE -- array_1d3 = 'b%b", array_1d3); err=err+1; end
if (array_1d4 !== 17'bx_xxxx_xxxx_xxxx_x111) begin $display("FAILED -- LHS<RHS LE -- array_1d4 = 'b%b", array_1d4); err=err+1; end
if (array_1d5 !== 17'bx_xxxx_xxxx_xxxx_x111) begin $display("FAILED -- LHS<RHS LE -- array_1d5 = 'b%b", array_1d5); err=err+1; end
if (array_1d6 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS<RHS LE -- array_1d6 = 'b%b", array_1d6); err=err+1; end
if (array_1d7 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS<RHS LE -- array_1d7 = 'b%b", array_1d7); err=err+1; end
//if (array_1d8 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS<RHS LE -- array_1d8 = 'b%b", array_1d8); err=err+1; end
//if (array_1d9 !== 17'bx_xxxx_xxxx_xxxx_xxx1) begin $display("FAILED -- LHS<RHS LE -- array_1d9 = 'b%b", array_1d9); err=err+1; end
if (err) $finish();
else $display("PASSED");
end
endmodule // test
|
// Ethernet_v6.v -
// Contains
// i) block-level-wrapper
// ii) EMAC wrapper
// iii) GMII code
//-----------------------------------------------------------------------------
// Title : Block-level Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : v6_emac_v1_5_block.v
// Version : 1.5
//-----------------------------------------------------------------------------
// Description: This is the block-level wrapper for the Virtex-6 Embedded
// Tri-Mode Ethernet MAC. It is intended that this example design
// can be quickly adapted and downloaded onto an FPGA to provide
// a hardware test environment.
//
// The block-level wrapper:
//
// * instantiates appropriate PHY interface modules (GMII, MII,
// RGMII, SGMII or 1000BASE-X) as required per the user
// configuration;
//
// * instantiates some clocking and reset resources to operate
// the EMAC and its example design.
//
// Please refer to the Datasheet, Getting Started Guide, and
// the Virtex-6 Embedded Tri-Mode Ethernet MAC User Gude for
// further information.
//-----------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Module declaration for the block-level wrapper
//-----------------------------------------------------------------------------
module v6_emac_v1_5_block
(
// TX clock output
TX_CLK_OUT,
// TX clock input from BUFG
TX_CLK,
// Client receiver interface
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
// Client transmitter interface
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
// MAC control interface
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
// Receive-side PHY clock on regional buffer, to EMAC
PHY_RX_CLK,
// Clock signal
GTX_CLK,
// GMII interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
// Asynchronous reset
RESET
);
//-----------------------------------------------------------------------------
// Port declarations
//-----------------------------------------------------------------------------
// TX clock output
output TX_CLK_OUT;
// TX clock input from BUFG
input TX_CLK;
// Client receiver interface
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
// Client transmitter interface
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
// MAC control interface
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
// Receive-side PHY clock on regional buffer, to EMAC
input PHY_RX_CLK;
// Clock signal
input GTX_CLK;
// GMII interface
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
// Asynchronous reset
input RESET;
//-----------------------------------------------------------------------------
// Wire and register declarations
//-----------------------------------------------------------------------------
// Asynchronous reset signals
wire reset_ibuf_i;
wire reset_i;
// Client clocking signals
wire rx_client_clk_out_i;
wire rx_client_clk_in_i;
wire tx_client_clk_out_i;
wire tx_client_clk_in_i;
wire tx_gmii_mii_clk_out_i;
wire tx_gmii_mii_clk_in_i;
// Physical interface signals
wire gmii_tx_en_i;
wire gmii_tx_er_i;
wire [7:0] gmii_txd_i;
wire gmii_rx_dv_r;
wire gmii_rx_er_r;
wire [7:0] gmii_rxd_r;
wire gmii_rx_clk_i;
// 125MHz reference clock
wire gtx_clk_ibufg_i;
//-----------------------------------------------------------------------------
// Main body of code
//-----------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Main reset circuitry
//-------------------------------------------------------------------------
assign reset_ibuf_i = RESET;
assign reset_i = reset_ibuf_i;
//-------------------------------------------------------------------------
// GMII circuitry for the physical interface
//-------------------------------------------------------------------------
gmii_if gmii (
.RESET (reset_i),
.GMII_TXD (GMII_TXD),
.GMII_TX_EN (GMII_TX_EN),
.GMII_TX_ER (GMII_TX_ER),
.GMII_TX_CLK (GMII_TX_CLK),
.GMII_RXD (GMII_RXD),
.GMII_RX_DV (GMII_RX_DV),
.GMII_RX_ER (GMII_RX_ER),
.TXD_FROM_MAC (gmii_txd_i),
.TX_EN_FROM_MAC (gmii_tx_en_i),
.TX_ER_FROM_MAC (gmii_tx_er_i),
.TX_CLK (tx_gmii_mii_clk_in_i),
.RXD_TO_MAC (gmii_rxd_r),
.RX_DV_TO_MAC (gmii_rx_dv_r),
.RX_ER_TO_MAC (gmii_rx_er_r),
.RX_CLK (GMII_RX_CLK)
);
// GTX reference clock
assign gtx_clk_ibufg_i = GTX_CLK;
// GMII PHY-side transmit clock
assign tx_gmii_mii_clk_in_i = TX_CLK;
// GMII PHY-side receive clock, regionally-buffered
assign gmii_rx_clk_i = PHY_RX_CLK;
// GMII client-side transmit clock
assign tx_client_clk_in_i = TX_CLK;
// GMII client-side receive clock
assign rx_client_clk_in_i = gmii_rx_clk_i;
// TX clock output
assign TX_CLK_OUT = tx_gmii_mii_clk_out_i;
//------------------------------------------------------------------------
// Instantiate the primitive-level EMAC wrapper (v6_emac_v1_5.v)
//------------------------------------------------------------------------
v6_emac_v1_5 v6_emac_v1_5_inst
(
// Client receiver interface
.EMACCLIENTRXCLIENTCLKOUT (rx_client_clk_out_i),
.CLIENTEMACRXCLIENTCLKIN (rx_client_clk_in_i),
.EMACCLIENTRXD (EMACCLIENTRXD),
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXDVLDMSW (),
.EMACCLIENTRXGOODFRAME (EMACCLIENTRXGOODFRAME),
.EMACCLIENTRXBADFRAME (EMACCLIENTRXBADFRAME),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
// Client transmitter interface
.EMACCLIENTTXCLIENTCLKOUT (tx_client_clk_out_i),
.CLIENTEMACTXCLIENTCLKIN (tx_client_clk_in_i),
.CLIENTEMACTXD (CLIENTEMACTXD),
.CLIENTEMACTXDVLD (CLIENTEMACTXDVLD),
.CLIENTEMACTXDVLDMSW (1'b0),
.EMACCLIENTTXACK (EMACCLIENTTXACK),
.CLIENTEMACTXFIRSTBYTE (CLIENTEMACTXFIRSTBYTE),
.CLIENTEMACTXUNDERRUN (CLIENTEMACTXUNDERRUN),
.EMACCLIENTTXCOLLISION (EMACCLIENTTXCOLLISION),
.EMACCLIENTTXRETRANSMIT (EMACCLIENTTXRETRANSMIT),
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
// MAC control interface
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
// Clock signals
.GTX_CLK (gtx_clk_ibufg_i),
.EMACPHYTXGMIIMIICLKOUT (tx_gmii_mii_clk_out_i),
.PHYEMACTXGMIIMIICLKIN (tx_gmii_mii_clk_in_i),
// GMII interface
.GMII_TXD (gmii_txd_i),
.GMII_TX_EN (gmii_tx_en_i),
.GMII_TX_ER (gmii_tx_er_i),
.GMII_RXD (gmii_rxd_r),
.GMII_RX_DV (gmii_rx_dv_r),
.GMII_RX_ER (gmii_rx_er_r),
.GMII_RX_CLK (gmii_rx_clk_i),
// MMCM lock indicator
.MMCM_LOCKED (1'b1),
// Asynchronous reset
.RESET (reset_i)
);
endmodule
//-----------------------------------------------------------------------------
// Title : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : v6_emac_v1_5.v
// Version : 1.5
//-----------------------------------------------------------------------------
// Description: This wrapper file instantiates the full Virtex-6 Embedded
// Tri-Mode Ethernet MAC (EMAC) primitive, where:
//
// * all unused input ports on the primitive are tied to the
// appropriate logic level;
//
// * all unused output ports on the primitive are left
// unconnected;
//
// * the attributes are set based on the options selected
// from CORE Generator;
//
// * only used ports are connected to the ports of this
// wrapper file.
//
// This simplified wrapper should therefore be used as the
// instantiation template for the EMAC primitive in customer
// designs.
//------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//------------------------------------------------------------------------------
// Module declaration for the primitive-level wrapper
//------------------------------------------------------------------------------
(* X_CORE_INFO = "v6_emac_v1_5, Coregen 11.3" *)
(* CORE_GENERATION_INFO = "v6_emac_v1_5,v6_emac_v1_5,{c_has_mii=false,c_has_gmii=true,c_has_rgmii_v1_5=false,c_has_rgmii_v2_0=false,c_has_sgmii=false,c_has_gpcs=false,c_tri_speed=false,c_speed_10=false,c_speed_100=false,c_speed_1000=true,c_has_host=false,c_has_dcr=false,c_has_mdio=false,c_client_16=false,c_add_filter=false,c_has_clock_enable=false,c_serial_mode_switch_en=false,c_overclocking_rate_2000mbps=false,c_overclocking_rate_2500mbps=false,}" *)
module v6_emac_v1_5
(
// Client Receiver Interface
EMACCLIENTRXCLIENTCLKOUT,
CLIENTEMACRXCLIENTCLKIN,
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXDVLDMSW,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
// Client Transmitter Interface
EMACCLIENTTXCLIENTCLKOUT,
CLIENTEMACTXCLIENTCLKIN,
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
CLIENTEMACTXDVLDMSW,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
// MAC Control Interface
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
// Clock Signals
GTX_CLK,
PHYEMACTXGMIIMIICLKIN,
EMACPHYTXGMIIMIICLKOUT,
// GMII Interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
// MMCM Lock Indicator
MMCM_LOCKED,
// Asynchronous Reset
RESET
);
//--------------------------------------------------------------------------
// Port declarations
//--------------------------------------------------------------------------
// Client Receiver Interface
output EMACCLIENTRXCLIENTCLKOUT;
input CLIENTEMACRXCLIENTCLKIN;
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXDVLDMSW;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
// Client Transmitter Interface
output EMACCLIENTTXCLIENTCLKOUT;
input CLIENTEMACTXCLIENTCLKIN;
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
input CLIENTEMACTXDVLDMSW;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
// MAC Control Interface
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
// Clock Signals
input GTX_CLK;
output EMACPHYTXGMIIMIICLKOUT;
input PHYEMACTXGMIIMIICLKIN;
// GMII Interface
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
// MMCM Lock Indicator
input MMCM_LOCKED;
// Asynchronous Reset
input RESET;
//--------------------------------------------------------------------------
// Wire declarations
//--------------------------------------------------------------------------
wire [15:0] client_rx_data_i;
wire [15:0] client_tx_data_i;
//--------------------------------------------------------------------------
// Main body of code
//--------------------------------------------------------------------------
// Use the 8-bit client data interface
assign EMACCLIENTRXD = client_rx_data_i[7:0];
assign #4000 client_tx_data_i = {8'b00000000, CLIENTEMACTXD};
// Instantiate the Virtex-6 Embedded Tri-Mode Ethernet MAC
TEMAC_SINGLE #(
// PCS/PMA logic is not in use
.EMAC_PHYINITAUTONEG_ENABLE ("FALSE"),
.EMAC_PHYISOLATE ("FALSE"),
.EMAC_PHYLOOPBACKMSB ("FALSE"),
.EMAC_PHYPOWERDOWN ("FALSE"),
.EMAC_PHYRESET ("TRUE"),
.EMAC_GTLOOPBACK ("FALSE"),
.EMAC_UNIDIRECTION_ENABLE ("FALSE"),
.EMAC_LINKTIMERVAL (9'h000),
.EMAC_MDIO_IGNORE_PHYADZERO ("FALSE"),
// Configure the EMAC operating mode
// MDIO is not enabled
.EMAC_MDIO_ENABLE ("FALSE"),
// Speed is defaulted to 1000 Mb/s
.EMAC_SPEED_LSB ("FALSE"),
.EMAC_SPEED_MSB ("TRUE"),
// Clock Enable advanced clocking is not in use
.EMAC_USECLKEN ("FALSE"),
// Byte PHY advanced clocking is not supported. Do not modify.
.EMAC_BYTEPHY ("FALSE"),
// RGMII physical interface is not in use
.EMAC_RGMII_ENABLE ("FALSE"),
// SGMII physical interface is not in use
.EMAC_SGMII_ENABLE ("FALSE"),
.EMAC_1000BASEX_ENABLE ("FALSE"),
// The host interface is not enabled
.EMAC_HOST_ENABLE ("FALSE"),
// The Tx-side 8-bit client data interface is used
.EMAC_TX16BITCLIENT_ENABLE ("FALSE"),
// The Rx-side 8-bit client data interface is used
.EMAC_RX16BITCLIENT_ENABLE ("FALSE"),
// The address filter is not enabled
.EMAC_ADDRFILTER_ENABLE ("FALSE"),
// EMAC configuration defaults
// Rx Length/Type checking is enabled
.EMAC_LTCHECK_DISABLE ("FALSE"),
// Rx control frame length checking is enabled
.EMAC_CTRLLENCHECK_DISABLE ("FALSE"),
// Rx flow control is not enabled
.EMAC_RXFLOWCTRL_ENABLE ("FALSE"),
// Tx flow control is not enabled
.EMAC_TXFLOWCTRL_ENABLE ("FALSE"),
// Transmitter is not held in reset
.EMAC_TXRESET ("FALSE"),
// Transmitter Jumbo frames are not enabled
.EMAC_TXJUMBOFRAME_ENABLE ("FALSE"),
// Transmitter in-band FCS is not enabled
.EMAC_TXINBANDFCS_ENABLE ("FALSE"),
// Transmitter is enabled
.EMAC_TX_ENABLE ("TRUE"),
// Transmitter VLAN frames are not enabled
.EMAC_TXVLAN_ENABLE ("FALSE"),
// Transmitter full-duplex mode is enabled
.EMAC_TXHALFDUPLEX ("FALSE"),
// Transmitter IFG Adjust is not enabled
.EMAC_TXIFGADJUST_ENABLE ("FALSE"),
// Receiver is not held in reset
.EMAC_RXRESET ("FALSE"),
// Receiver Jumbo frames are not enabled
.EMAC_RXJUMBOFRAME_ENABLE ("FALSE"),
// Receiver in-band FCS is not enabled
.EMAC_RXINBANDFCS_ENABLE ("FALSE"),
// Receiver is enabled
.EMAC_RX_ENABLE ("TRUE"),
// Receiver VLAN frames are not enabled
.EMAC_RXVLAN_ENABLE ("FALSE"),
// Receiver full-duplex mode is enabled
.EMAC_RXHALFDUPLEX ("FALSE"),
// Configure the EMAC addressing
// Set the PAUSE address default
.EMAC_PAUSEADDR (48'hFFEEDDCCBBAA),
// Do not set the unicast address (address filter is unused)
.EMAC_UNICASTADDR (48'h000000000000),
// Do not set the DCR base address (DCR is unused)
.EMAC_DCRBASEADDR (8'h00)
)
v6_emac
(
.RESET (RESET),
.EMACCLIENTRXCLIENTCLKOUT (EMACCLIENTRXCLIENTCLKOUT),
.CLIENTEMACRXCLIENTCLKIN (CLIENTEMACRXCLIENTCLKIN),
.EMACCLIENTRXD (client_rx_data_i),
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXDVLDMSW (EMACCLIENTRXDVLDMSW),
.EMACCLIENTRXGOODFRAME (EMACCLIENTRXGOODFRAME),
.EMACCLIENTRXBADFRAME (EMACCLIENTRXBADFRAME),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
.EMACCLIENTTXCLIENTCLKOUT (EMACCLIENTTXCLIENTCLKOUT),
.CLIENTEMACTXCLIENTCLKIN (CLIENTEMACTXCLIENTCLKIN),
.CLIENTEMACTXD (client_tx_data_i),
.CLIENTEMACTXDVLD (CLIENTEMACTXDVLD),
.CLIENTEMACTXDVLDMSW (CLIENTEMACTXDVLDMSW),
.EMACCLIENTTXACK (EMACCLIENTTXACK),
.CLIENTEMACTXFIRSTBYTE (CLIENTEMACTXFIRSTBYTE),
.CLIENTEMACTXUNDERRUN (CLIENTEMACTXUNDERRUN),
.EMACCLIENTTXCOLLISION (EMACCLIENTTXCOLLISION),
.EMACCLIENTTXRETRANSMIT (EMACCLIENTTXRETRANSMIT),
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
.PHYEMACGTXCLK (GTX_CLK),
.EMACPHYTXGMIIMIICLKOUT (EMACPHYTXGMIIMIICLKOUT),
.PHYEMACTXGMIIMIICLKIN (PHYEMACTXGMIIMIICLKIN),
.PHYEMACRXCLK (GMII_RX_CLK),
.PHYEMACRXD (GMII_RXD),
.PHYEMACRXDV (GMII_RX_DV),
.PHYEMACRXER (GMII_RX_ER),
.EMACPHYTXCLK (),
.EMACPHYTXD (GMII_TXD),
.EMACPHYTXEN (GMII_TX_EN),
.EMACPHYTXER (GMII_TX_ER),
.PHYEMACMIITXCLK (1'b0),
.PHYEMACCOL (1'b0),
.PHYEMACCRS (1'b0),
.CLIENTEMACDCMLOCKED (MMCM_LOCKED),
.EMACCLIENTANINTERRUPT (),
.PHYEMACSIGNALDET (1'b0),
.PHYEMACPHYAD (5'b00000),
.EMACPHYENCOMMAALIGN (),
.EMACPHYLOOPBACKMSB (),
.EMACPHYMGTRXRESET (),
.EMACPHYMGTTXRESET (),
.EMACPHYPOWERDOWN (),
.EMACPHYSYNCACQSTATUS (),
.PHYEMACRXCLKCORCNT (3'b000),
.PHYEMACRXBUFSTATUS (2'b00),
.PHYEMACRXCHARISCOMMA (1'b0),
.PHYEMACRXCHARISK (1'b0),
.PHYEMACRXDISPERR (1'b0),
.PHYEMACRXNOTINTABLE (1'b0),
.PHYEMACRXRUNDISP (1'b0),
.PHYEMACTXBUFERR (1'b0),
.EMACPHYTXCHARDISPMODE (),
.EMACPHYTXCHARDISPVAL (),
.EMACPHYTXCHARISK (),
.EMACPHYMCLKOUT (),
.PHYEMACMCLKIN (1'b0),
.PHYEMACMDIN (1'b1),
.EMACPHYMDOUT (),
.EMACPHYMDTRI (),
.EMACSPEEDIS10100 (),
.HOSTCLK (1'b0),
.HOSTOPCODE (2'b00),
.HOSTREQ (1'b0),
.HOSTMIIMSEL (1'b0),
.HOSTADDR (10'b0000000000),
.HOSTWRDATA (32'h00000000),
.HOSTMIIMRDY (),
.HOSTRDDATA (),
.DCREMACCLK (1'b0),
.DCREMACABUS (10'h000),
.DCREMACREAD (1'b0),
.DCREMACWRITE (1'b0),
.DCREMACDBUS (32'h00000000),
.EMACDCRACK (),
.EMACDCRDBUS (),
.DCREMACENABLE (1'b0),
.DCRHOSTDONEIR ()
);
endmodule
//----------------------------------------------------------------------
// Title : Gigabit Media Independent Interface (GMII) Physical I/F
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : gmii_if.v
// Version : 1.5
//-----------------------------------------------------------------------------
// Description: This module creates a Gigabit Media Independent
// Interface (GMII) by instantiating Input/Output buffers
// and Input/Output flip-flops as required.
//
// This interface is used to connect the Ethernet MAC to
// an external 1000Mb/s (or Tri-speed) Ethernet PHY.
//----------------------------------------------------------------------
`timescale 1 ps / 1 ps
module gmii_if (
RESET,
// GMII Interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
// MAC Interface
TXD_FROM_MAC,
TX_EN_FROM_MAC,
TX_ER_FROM_MAC,
TX_CLK,
RXD_TO_MAC,
RX_DV_TO_MAC,
RX_ER_TO_MAC,
RX_CLK
);
input RESET;
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input [7:0] TXD_FROM_MAC;
input TX_EN_FROM_MAC;
input TX_ER_FROM_MAC;
input TX_CLK;
output [7:0] RXD_TO_MAC;
output RX_DV_TO_MAC;
output RX_ER_TO_MAC;
input RX_CLK;
reg [7:0] RXD_TO_MAC;
reg RX_DV_TO_MAC;
reg RX_ER_TO_MAC;
reg [7:0] GMII_TXD;
reg GMII_TX_EN;
reg GMII_TX_ER;
wire [7:0] GMII_RXD_DLY;
wire GMII_RX_DV_DLY;
wire GMII_RX_ER_DLY;
//------------------------------------------------------------------------
// GMII Transmitter Clock Management
//------------------------------------------------------------------------
// Instantiate a DDR output register. This is a good way to drive
// GMII_TX_CLK since the clock-to-pad delay will be the same as that for
// data driven from IOB Ouput flip-flops, eg. GMII_TXD[7:0].
ODDR gmii_tx_clk_oddr (
.Q (GMII_TX_CLK),
.C (TX_CLK),
.CE (1'b1),
.D1 (1'b0),
.D2 (1'b1),
.R (RESET),
.S (1'b0)
);
//------------------------------------------------------------------------
// GMII Transmitter Logic : Drive TX signals through IOBs onto the
// GMII interface
//------------------------------------------------------------------------
// Infer IOB Output flip-flops
always @(posedge TX_CLK, posedge RESET)
begin
if (RESET == 1'b1)
begin
GMII_TX_EN <= 1'b0;
GMII_TX_ER <= 1'b0;
GMII_TXD <= 8'h00;
end
else
begin
GMII_TX_EN <= TX_EN_FROM_MAC;
GMII_TX_ER <= TX_ER_FROM_MAC;
GMII_TXD <= TXD_FROM_MAC;
end
end
//------------------------------------------------------------------------
// Route GMII inputs through IODELAY blocks, using IDELAY function
//------------------------------------------------------------------------
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld0 (
.IDATAIN(GMII_RXD[0]),
.DATAOUT(GMII_RXD_DLY[0]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld1 (
.IDATAIN(GMII_RXD[1]),
.DATAOUT(GMII_RXD_DLY[1]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld2 (
.IDATAIN(GMII_RXD[2]),
.DATAOUT(GMII_RXD_DLY[2]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld3 (
.IDATAIN(GMII_RXD[3]),
.DATAOUT(GMII_RXD_DLY[3]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld4 (
.IDATAIN(GMII_RXD[4]),
.DATAOUT(GMII_RXD_DLY[4]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld5 (
.IDATAIN(GMII_RXD[5]),
.DATAOUT(GMII_RXD_DLY[5]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld6 (
.IDATAIN(GMII_RXD[6]),
.DATAOUT(GMII_RXD_DLY[6]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideld7 (
.IDATAIN(GMII_RXD[7]),
.DATAOUT(GMII_RXD_DLY[7]),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideldv(
.IDATAIN(GMII_RX_DV),
.DATAOUT(GMII_RX_DV_DLY),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
IODELAY #(
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.HIGH_PERFORMANCE_MODE ("TRUE")
)
ideler(
.IDATAIN(GMII_RX_ER),
.DATAOUT(GMII_RX_ER_DLY),
.DATAIN(1'b0),
.ODATAIN(1'b0),
.C(1'b0),
.CE(1'b0),
.INC(1'b0),
.T(1'b0),
.RST(1'b0)
);
//------------------------------------------------------------------------
// GMII Receiver Logic : Receive RX signals through IOBs from the
// GMII interface
//------------------------------------------------------------------------
// Infer IOB Input flip-flops
always @(posedge RX_CLK, posedge RESET)
begin
if (RESET == 1'b1)
begin
RX_DV_TO_MAC <= 1'b0;
RX_ER_TO_MAC <= 1'b0;
RXD_TO_MAC <= 8'h00;
end
else
begin
RX_DV_TO_MAC <= GMII_RX_DV_DLY;
RX_ER_TO_MAC <= GMII_RX_ER_DLY;
RXD_TO_MAC <= GMII_RXD_DLY;
end
end
endmodule
|
module map_reducer #(
NUM_MAPPERS = 64
)
(
input i_clk,
input i_rst,
input [63:0] i_strm_data,
input i_strm_data_valid,
output o_strm_data_rdy,
output [31:0] o_data_count
);
wire [NUM_MAPPERS-1:0] mapper_rdy;
wire [NUM_MAPPERS-1:0] data_valid;
wire [(32*NUM_MAPPERS)-1:0] data_count;
wire [31:0] reduced_data_count;
mapper_controller
#(
.NUM_MAPPERS(NUM_MAPPERS)
)
mc(
.i_clk(i_clk),
.i_rst(i_rst),
.i_mapper_rdy(mapper_rdy),
.i_pcie_strm_valid(i_strm_data_valid),
.o_pcie_strm_valid(data_valid),
.o_pcie_strm_rdy(o_strm_data_rdy)
);
reducer #(
.NUM_MAPPERS(NUM_MAPPERS)
)
reducer(
.i_clk(i_clk),
.i_rst(i_rst),
.i_data_count(data_count),
.o_data_count(o_data_count)
);
generate
genvar i;
for (i=0; i < NUM_MAPPERS; i=i+1) begin : Mapper
mapper map(
.i_clk(i_clk),
.i_rst(i_rst),
.i_data_valid(data_valid[i]),
.o_data_rdy(mapper_rdy[i]),
.i_data(i_strm_data),
.o_count(data_count[(i*32)+31:i*32])
);
end
endgenerate
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2013 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
typedef struct packed {
logic [3:2] a;
logic [5:4][3:2] b;
} ab_t;
typedef ab_t [7:6] c_t; // array of structs
typedef struct packed {
c_t [17:16] d;
} e_t;
`define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
initial begin
e_t e;
`checkh($bits(ab_t),6);
`checkh($bits(c_t),12);
`checkh($bits(e_t),24);
`checkh($bits(e), 24);
`checkh($bits(e.d[17]),12);
`checkh($bits(e.d[16][6]),6);
`checkh($bits(e.d[16][6].b[5]),2);
`checkh($bits(e.d[16][6].b[5][2]), 1);
//
e = 24'b101101010111010110101010;
`checkb(e, 24'b101101010111010110101010);
e.d[17] = 12'b111110011011;
`checkb(e, 24'b111110011011010110101010);
e.d[16][6] = 6'b010101;
`checkb(e, 24'b111110011011010110010101);
e.d[16][6].b[5] = 2'b10;
`checkb(e, 24'b111110011011010110011001);
e.d[16][6].b[5][2] = 1'b1;
//
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// $Id: c_err_rpt.v 1570 2009-09-24 02:29:36Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// error reporting module
module c_err_rpt
(clk, reset, errors_in, errors_out);
`include "c_constants.v"
// number of error inputs
parameter num_errors = 1;
// select mode of operation
parameter capture_mode = `ERROR_CAPTURE_MODE_NO_HOLD;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// raw error inputs
input [0:num_errors-1] errors_in;
// registered and potentially held error outputs
output [0:num_errors-1] errors_out;
wire [0:num_errors-1] errors_out;
generate
if(capture_mode != `ERROR_CAPTURE_MODE_NONE)
begin
wire [0:num_errors-1] errors_s, errors_q;
case(capture_mode)
`ERROR_CAPTURE_MODE_NO_HOLD:
begin
assign errors_s = errors_in;
end
`ERROR_CAPTURE_MODE_HOLD_FIRST:
begin
assign errors_s = ~|errors_q ? errors_in : errors_q;
end
`ERROR_CAPTURE_MODE_HOLD_ALL:
begin
assign errors_s = errors_q | errors_in;
end
endcase
c_dff
#(.width(num_errors),
.reset_type(reset_type))
errorsq
(.clk(clk),
.reset(reset),
.d(errors_s),
.q(errors_q));
assign errors_out = errors_q;
end
else
assign errors_out = {num_errors{1'b0}};
endgenerate
endmodule
|
module timer(
input CLK,
input switch_up,
input switch_dn,
input switch_cancel,
input switch_start_stop,
output [7:0] SEG,
output [3:0] DIGIT,
output BUZZER
);
wire s_up, s_dn, s_cancel, s_start_stop;
debouncer d1(.CLK (CLK), .switch_input (switch_up), .trans_dn (s_up));
debouncer d2(.CLK (CLK), .switch_input (switch_dn), .trans_dn (s_dn));
debouncer d3(.CLK (CLK), .switch_input (switch_cancel), .trans_dn (s_cancel));
debouncer d4(.CLK (CLK), .switch_input (switch_start_stop), .trans_dn (s_start_stop));
reg alarm_on = 0;
alarm a(.CLK (CLK), .BUZZER (BUZZER), .enable (alarm_on));
reg [3:0] secs = 0;
reg [3:0] ten_secs = 0;
reg [3:0] mins = 1;
reg [3:0] mins_stored;
reg [3:0] unused_digit = 4'd10; // digits above 9 not displayed
reg [25:0] prescaler = 0;
display_7_seg display(.CLK (CLK),
.units (secs), .tens (ten_secs), .hundreds (mins), .thousands (unused_digit),
.SEG (SEG), .DIGIT (DIGIT));
// States
localparam SETTING = 0, RUNNING = 1, BEEPING = 2;
reg [1:0] state = SETTING;
always @(posedge CLK)
begin
case (state)
SETTING : begin
handle_settings();
if (s_start_stop)
begin
mins_stored <= mins;
state <= RUNNING;
end
end
RUNNING : begin
decrement_time();
if (s_start_stop)
begin
state <= SETTING;
end
if (s_cancel)
begin
reset_time();
state <= SETTING;
end
if ((secs == 0) & (ten_secs == 0) & (mins == 0))
begin
alarm_on <= 1;
state <= BEEPING;
end
end
BEEPING : begin
if (s_cancel)
begin
alarm_on <= 0;
state <= SETTING;
reset_time();
end
end
endcase
end
task handle_settings;
begin
if (s_up)
begin
mins <= mins + 1;
if (mins == 9)
begin
mins <= 1;
end
end
if (s_dn)
begin
mins <= mins - 1;
if (mins == 1)
begin
mins <= 9;
end
end
end
endtask
task decrement_time;
begin
prescaler <= prescaler + 1;
if (prescaler == 26'd49999999) // 50 MHz to 1Hz
begin
prescaler <= 0;
secs <= secs - 1;
if (secs < 1)
begin
secs <= 9;
ten_secs <= ten_secs - 1;
if (ten_secs < 1)
begin
ten_secs <= 5;
mins <= mins - 1;
end
end
end
end
endtask
task reset_time;
begin
secs <= 0;
ten_secs <= 0;
mins <= mins_stored;
end
endtask
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_queue.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Bank machine queue controller.
//
// Bank machines are always associated with a queue. When the system is
// idle, all bank machines are in the idle queue. As requests are
// received, the bank machine at the head of the idle queue accepts
// the request, removes itself from the idle queue and places itself
// in a queue associated with the rank-bank of the new request.
//
// If the new request is to an idle rank-bank, a new queue is created
// for that rank-bank. If the rank-bank is not idle, then the new
// request is added to the end of the existing rank-bank queue.
//
// When the head of the idle queue accepts a new request, all other
// bank machines move down one in the idle queue. When the idle queue
// is empty, the memory interface deasserts its accept signal.
//
// When new requests are received, the first step is to classify them
// as to whether the request targets an already open rank-bank, and if
// so, does the new request also hit on the already open page? As mentioned
// above, a new request places itself in the existing queue for a
// rank-bank hit. If it is also detected that the last entry in the
// existing rank-bank queue has the same page, then the current tail
// sets a bit telling itself to pass the open row when the column
// command is issued. The "passee" knows its in the head minus one
// position and hence takes control of the rank-bank.
//
// Requests are retired out of order to optimize DRAM array resources.
// However it is required that the user cannot "observe" this out of
// order processing as a data corruption. An ordering queue is
// used to enforce some ordering rules. As controlled by a paramter,
// there can be no ordering (RELAXED), ordering of writes only (NORM), and
// strict (STRICT) ordering whereby input request ordering is
// strictly adhered to.
//
// Note that ordering applies only to column commands. Row commands
// such as activate and precharge are allowed to proceed in any order
// with the proviso that within a rank-bank row commands are processed in
// the request order.
//
// When a bank machine accepts a new request, it looks at the ordering
// mode. If no ordering, nothing is done. If strict ordering, then
// it always places itself at the end of the ordering queue. If "normal"
// or write ordering, the row machine places itself in the ordering
// queue only if the new request is a write. The bank state machine
// looks at the ordering queue, and will only issue a column
// command when it sees itself at the head of the ordering queue.
//
// When a bank machine has completed its request, it must re-enter the
// idle queue. This is done by setting the idle_r bit, and setting q_entry_r
// to the idle count.
//
// There are several situations where more than one bank machine
// will enter the idle queue simultaneously. If two or more
// simply use the idle count to place themselves in the idle queue, multiple
// bank machines will end up at the same location in the idle queue, which
// is illegal.
//
// Based on the bank machine instance numbers, a count is made of
// the number of bank machines entering idle "below" this instance. This
// number is added to the idle count to compute the location in
// idle queue.
//
// There is also a single bit computed that says there were bank machines
// entering the idle queue "above" this instance. This is used to
// compute the tail bit.
//
// The word "queue" is used frequently to describe the behavior of the
// bank_queue block. In reality, there are no queues in the ordinary sense.
// As instantiated in this block, each bank machine has a q_entry_r number.
// This number represents the position of the bank machine in its current
// queue. At any given time, a bank machine may be in the idle queue,
// one of the dynamic rank-bank queues, or a single entry manitenance queue.
// A complete description of which queue a bank machine is currently in is
// given by idle_r, its rank-bank, mainteance status and its q_entry_r number.
//
// DRAM refresh and ZQ have a private single entry queue/channel. However,
// when a refresh request is made, it must be injected into the main queue
// properly. At the time of injection, the refresh rank is compared against
// all entryies in the queue. For those that match, if timing allows, and
// they are the tail of the rank-bank queue, then the auto_pre bit is set.
// Otherwise precharge is in progress. This results in a fully precharged
// rank.
//
// At the time of injection, the refresh channel builds a bit
// vector of queue entries that hit on the refresh rank. Once all
// of these entries finish, the refresh is forced in at the row arbiter.
//
// New requests that come after the refresh request will notice that
// a refresh is in progress for their rank and wait for the refresh
// to finish before attempting to arbitrate to send an activate.
//
// Injection of a refresh sets the q_has_rd bit for all queues hitting
// on the refresh rank. This insures a starved write request will not
// indefinitely hold off a refresh.
//
// Periodic reads are required to compare themselves against requests
// that are in progress. Adding a unique compare channel for this
// is not worthwhile. Periodic read requests inhibit the accept
// signal and override any new request that might be trying to
// enter the queue.
//
// Once a periodic read has entered the queue it is nearly indistinguishable
// from a normal read request. The req_periodic_rd_r bit is set for
// queue entry. This signal is used to inhibit the rd_data_en signal.
`timescale 1ps/1ps
`define BM_SHARED_BV (ID+nBANK_MACHS-1):(ID+1)
module mig_7series_v1_8_bank_queue #
(
parameter TCQ = 100,
parameter BM_CNT_WIDTH = 2,
parameter nBANK_MACHS = 4,
parameter ORDERING = "NORM",
parameter ID = 0
)
(/*AUTOARG*/
// Outputs
head_r, tail_r, idle_ns, idle_r, pass_open_bank_ns,
pass_open_bank_r, auto_pre_r, bm_end, passing_open_bank,
ordered_issued, ordered_r, order_q_zero, rcv_open_bank,
rb_hit_busies_r, q_has_rd, q_has_priority, wait_for_maint_r,
// Inputs
clk, rst, accept_internal_r, use_addr, periodic_rd_ack_r, bm_end_in,
idle_cnt, rb_hit_busy_cnt, accept_req, rb_hit_busy_r, maint_idle,
maint_hit, row_hit_r, pre_wait_r, allow_auto_pre, sending_col,
bank_wait_in_progress, precharge_bm_end, req_wr_r, rd_wr_r,
adv_order_q, order_cnt, rb_hit_busy_ns_in, passing_open_bank_in,
was_wr, maint_req_r, was_priority
);
localparam ZERO = 0;
localparam ONE = 1;
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ZERO = ZERO[0+:BM_CNT_WIDTH];
localparam [BM_CNT_WIDTH-1:0] BM_CNT_ONE = ONE[0+:BM_CNT_WIDTH];
input clk;
input rst;
// Decide if this bank machine should accept a new request.
reg idle_r_lcl;
reg head_r_lcl;
input accept_internal_r;
wire bm_ready = idle_r_lcl && head_r_lcl && accept_internal_r;
// Accept request in this bank machine. Could be maintenance or
// regular request.
input use_addr;
input periodic_rd_ack_r;
wire accept_this_bm = bm_ready && (use_addr || periodic_rd_ack_r);
// Multiple machines may enter the idle queue in a single state.
// Based on bank machine instance number, compute how many
// bank machines with lower instance numbers are entering
// the idle queue.
input [(nBANK_MACHS*2)-1:0] bm_end_in;
reg [BM_CNT_WIDTH-1:0] idlers_below;
integer i;
always @(/*AS*/bm_end_in) begin
idlers_below = BM_CNT_ZERO;
for (i=0; i<ID; i=i+1)
idlers_below = idlers_below + bm_end_in[i];
end
reg idlers_above;
always @(/*AS*/bm_end_in) begin
idlers_above = 1'b0;
for (i=ID+1; i<ID+nBANK_MACHS; i=i+1)
idlers_above = idlers_above || bm_end_in[i];
end
`ifdef MC_SVA
bm_end_and_idlers_above: cover property (@(posedge clk)
(~rst && bm_end && idlers_above));
bm_end_and_idlers_below: cover property (@(posedge clk)
(~rst && bm_end && |idlers_below));
`endif
// Compute the q_entry number.
input [BM_CNT_WIDTH-1:0] idle_cnt;
input [BM_CNT_WIDTH-1:0] rb_hit_busy_cnt;
input accept_req;
wire bm_end_lcl;
reg adv_queue = 1'b0;
reg [BM_CNT_WIDTH-1:0] q_entry_r;
reg [BM_CNT_WIDTH-1:0] q_entry_ns;
wire [BM_CNT_WIDTH-1:0] temp;
// always @(/*AS*/accept_req or accept_this_bm or adv_queue
// or bm_end_lcl or idle_cnt or idle_r_lcl or idlers_below
// or q_entry_r or rb_hit_busy_cnt /*or rst*/) begin
//// if (rst) q_entry_ns = ID[BM_CNT_WIDTH-1:0];
//// else begin
// q_entry_ns = q_entry_r;
// if ((~idle_r_lcl && adv_queue) ||
// (idle_r_lcl && accept_req && ~accept_this_bm))
// q_entry_ns = q_entry_r - BM_CNT_ONE;
// if (accept_this_bm)
//// q_entry_ns = rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO);
// q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
// if (bm_end_lcl) begin
// q_entry_ns = idle_cnt + idlers_below;
// if (accept_req) q_entry_ns = q_entry_ns - BM_CNT_ONE;
//// end
// end
// end
assign temp = idle_cnt + idlers_below;
always @ (*)
begin
if (accept_req & bm_end_lcl)
q_entry_ns = temp - BM_CNT_ONE;
else if (bm_end_lcl)
q_entry_ns = temp;
else if (accept_this_bm)
q_entry_ns = adv_queue ? (rb_hit_busy_cnt - BM_CNT_ONE) : (rb_hit_busy_cnt -BM_CNT_ZERO);
else if ((!idle_r_lcl & adv_queue) |
(idle_r_lcl & accept_req & !accept_this_bm))
q_entry_ns = q_entry_r - BM_CNT_ONE;
else
q_entry_ns = q_entry_r;
end
always @(posedge clk)
if (rst)
q_entry_r <= #TCQ ID[BM_CNT_WIDTH-1:0];
else
q_entry_r <= #TCQ q_entry_ns;
// Determine if this entry is the head of its queue.
reg head_ns;
always @(/*AS*/accept_req or accept_this_bm or adv_queue
or bm_end_lcl or head_r_lcl or idle_cnt or idle_r_lcl
or idlers_below or q_entry_r or rb_hit_busy_cnt or rst) begin
if (rst) head_ns = ~|ID[BM_CNT_WIDTH-1:0];
else begin
head_ns = head_r_lcl;
if (accept_this_bm)
head_ns = ~|(rb_hit_busy_cnt - (adv_queue ? BM_CNT_ONE : BM_CNT_ZERO));
if ((~idle_r_lcl && adv_queue) ||
(idle_r_lcl && accept_req && ~accept_this_bm))
head_ns = ~|(q_entry_r - BM_CNT_ONE);
if (bm_end_lcl) begin
head_ns = ~|(idle_cnt - (accept_req ? BM_CNT_ONE : BM_CNT_ZERO)) &&
~|idlers_below;
end
end
end
always @(posedge clk) head_r_lcl <= #TCQ head_ns;
output wire head_r;
assign head_r = head_r_lcl;
// Determine if this entry is the tail of its queue. Note that
// an entry can be both head and tail.
input rb_hit_busy_r;
reg tail_r_lcl = 1'b1;
generate
if (nBANK_MACHS > 1) begin : compute_tail
reg tail_ns;
always @(accept_req or accept_this_bm
or bm_end_in or bm_end_lcl or idle_r_lcl
or idlers_above or rb_hit_busy_r or rst or tail_r_lcl) begin
if (rst) tail_ns = (ID == nBANK_MACHS);
// The order of the statements below is important in the case where
// another bank machine is retiring and this bank machine is accepting.
else begin
tail_ns = tail_r_lcl;
if ((accept_req && rb_hit_busy_r) ||
(|bm_end_in[`BM_SHARED_BV] && idle_r_lcl))
tail_ns = 1'b0;
if (accept_this_bm || (bm_end_lcl && ~idlers_above)) tail_ns = 1'b1;
end
end
always @(posedge clk) tail_r_lcl <= #TCQ tail_ns;
end // if (nBANK_MACHS > 1)
endgenerate
output wire tail_r;
assign tail_r = tail_r_lcl;
wire clear_req = bm_end_lcl || rst;
// Is this entry in the idle queue?
reg idle_ns_lcl;
always @(/*AS*/accept_this_bm or clear_req or idle_r_lcl) begin
idle_ns_lcl = idle_r_lcl;
if (accept_this_bm) idle_ns_lcl = 1'b0;
if (clear_req) idle_ns_lcl = 1'b1;
end
always @(posedge clk) idle_r_lcl <= #TCQ idle_ns_lcl;
output wire idle_ns;
assign idle_ns = idle_ns_lcl;
output wire idle_r;
assign idle_r = idle_r_lcl;
// Maintenance hitting on this active bank machine is in progress.
input maint_idle;
input maint_hit;
wire maint_hit_this_bm = ~maint_idle && maint_hit;
// Does new request hit on this bank machine while it is able to pass the
// open bank?
input row_hit_r;
input pre_wait_r;
wire pass_open_bank_eligible =
tail_r_lcl && rb_hit_busy_r && row_hit_r && ~pre_wait_r;
// Set pass open bank bit, but not if request preceded active maintenance.
reg wait_for_maint_r_lcl;
reg pass_open_bank_r_lcl;
wire pass_open_bank_ns_lcl = ~clear_req &&
(pass_open_bank_r_lcl ||
(accept_req && pass_open_bank_eligible &&
(~maint_hit_this_bm || wait_for_maint_r_lcl)));
always @(posedge clk) pass_open_bank_r_lcl <= #TCQ pass_open_bank_ns_lcl;
output wire pass_open_bank_ns;
assign pass_open_bank_ns = pass_open_bank_ns_lcl;
output wire pass_open_bank_r;
assign pass_open_bank_r = pass_open_bank_r_lcl;
`ifdef MC_SVA
pass_open_bank: cover property (@(posedge clk) (~rst && pass_open_bank_ns));
pass_open_bank_killed_by_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && ~wait_for_maint_r_lcl));
pass_open_bank_following_maint: cover property (@(posedge clk)
(~rst && accept_req && pass_open_bank_eligible &&
maint_hit_this_bm && wait_for_maint_r_lcl));
`endif
// Should the column command be sent with the auto precharge bit set? This
// will happen when it is detected that next request is to a different row,
// or the next reqest is the next request is refresh to this rank.
reg auto_pre_r_lcl;
reg auto_pre_ns;
input allow_auto_pre;
always @(/*AS*/accept_req or allow_auto_pre or auto_pre_r_lcl
or clear_req or maint_hit_this_bm or rb_hit_busy_r
or row_hit_r or tail_r_lcl or wait_for_maint_r_lcl) begin
auto_pre_ns = auto_pre_r_lcl;
if (clear_req) auto_pre_ns = 1'b0;
else
if (accept_req && tail_r_lcl && allow_auto_pre && rb_hit_busy_r &&
(~row_hit_r || (maint_hit_this_bm && ~wait_for_maint_r_lcl)))
auto_pre_ns = 1'b1;
end
always @(posedge clk) auto_pre_r_lcl <= #TCQ auto_pre_ns;
output wire auto_pre_r;
assign auto_pre_r = auto_pre_r_lcl;
`ifdef MC_SVA
auto_precharge: cover property (@(posedge clk) (~rst && auto_pre_ns));
maint_triggers_auto_precharge: cover property (@(posedge clk)
(~rst && auto_pre_ns && ~auto_pre_r && row_hit_r));
`endif
// Determine when the current request is finished.
input sending_col;
input req_wr_r;
input rd_wr_r;
wire sending_col_not_rmw_rd = sending_col && !(req_wr_r && rd_wr_r);
input bank_wait_in_progress;
input precharge_bm_end;
reg pre_bm_end_r;
wire pre_bm_end_ns = precharge_bm_end ||
(bank_wait_in_progress && pass_open_bank_ns_lcl);
always @(posedge clk) pre_bm_end_r <= #TCQ pre_bm_end_ns;
assign bm_end_lcl =
pre_bm_end_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
output wire bm_end;
assign bm_end = bm_end_lcl;
// Determine that the open bank should be passed to the successor bank machine.
reg pre_passing_open_bank_r;
wire pre_passing_open_bank_ns =
bank_wait_in_progress && pass_open_bank_ns_lcl;
always @(posedge clk) pre_passing_open_bank_r <= #TCQ
pre_passing_open_bank_ns;
output wire passing_open_bank;
assign passing_open_bank =
pre_passing_open_bank_r || (sending_col_not_rmw_rd && pass_open_bank_r_lcl);
reg ordered_ns;
wire set_order_q = ((ORDERING == "STRICT") || ((ORDERING == "NORM") &&
req_wr_r)) && accept_this_bm;
wire ordered_issued_lcl =
sending_col_not_rmw_rd && !(req_wr_r && rd_wr_r) &&
((ORDERING == "STRICT") || ((ORDERING == "NORM") && req_wr_r));
output wire ordered_issued;
assign ordered_issued = ordered_issued_lcl;
reg ordered_r_lcl;
always @(/*AS*/ordered_issued_lcl or ordered_r_lcl or rst
or set_order_q) begin
if (rst) ordered_ns = 1'b0;
else begin
ordered_ns = ordered_r_lcl;
// Should never see accept_this_bm and adv_order_q at the same time.
if (set_order_q) ordered_ns = 1'b1;
if (ordered_issued_lcl) ordered_ns = 1'b0;
end
end
always @(posedge clk) ordered_r_lcl <= #TCQ ordered_ns;
output wire ordered_r;
assign ordered_r = ordered_r_lcl;
// Figure out when to advance the ordering queue.
input adv_order_q;
input [BM_CNT_WIDTH-1:0] order_cnt;
reg [BM_CNT_WIDTH-1:0] order_q_r;
reg [BM_CNT_WIDTH-1:0] order_q_ns;
always @(/*AS*/adv_order_q or order_cnt or order_q_r or rst
or set_order_q) begin
order_q_ns = order_q_r;
if (rst) order_q_ns = BM_CNT_ZERO;
if (set_order_q)
if (adv_order_q) order_q_ns = order_cnt - BM_CNT_ONE;
else order_q_ns = order_cnt;
if (adv_order_q && |order_q_r) order_q_ns = order_q_r - BM_CNT_ONE;
end
always @(posedge clk) order_q_r <= #TCQ order_q_ns;
output wire order_q_zero;
assign order_q_zero = ~|order_q_r ||
(adv_order_q && (order_q_r == BM_CNT_ONE)) ||
((ORDERING == "NORM") && rd_wr_r);
// Keep track of which other bank machine are ahead of this one in a
// rank-bank queue. This is necessary to know when to advance this bank
// machine in the queue, and when to update bank state machine counter upon
// passing a bank.
input [(nBANK_MACHS*2)-1:0] rb_hit_busy_ns_in;
reg [(nBANK_MACHS*2)-1:0] rb_hit_busies_r_lcl = {nBANK_MACHS*2{1'b0}};
input [(nBANK_MACHS*2)-1:0] passing_open_bank_in;
output reg rcv_open_bank = 1'b0;
generate
if (nBANK_MACHS > 1) begin : rb_hit_busies
// The clear_vector resets bits in the rb_hit_busies vector as bank machines
// completes requests. rst also resets all the bits.
wire [nBANK_MACHS-2:0] clear_vector =
({nBANK_MACHS-1{rst}} | bm_end_in[`BM_SHARED_BV]);
// As this bank machine takes on a new request, capture the vector of
// which other bank machines are in the same queue.
wire [`BM_SHARED_BV] rb_hit_busies_ns =
~clear_vector &
(idle_ns_lcl
? rb_hit_busy_ns_in[`BM_SHARED_BV]
: rb_hit_busies_r_lcl[`BM_SHARED_BV]);
always @(posedge clk) rb_hit_busies_r_lcl[`BM_SHARED_BV] <=
#TCQ rb_hit_busies_ns;
// Compute when to advance this queue entry based on seeing other bank machines
// in the same queue finish.
always @(bm_end_in or rb_hit_busies_r_lcl)
adv_queue =
|(bm_end_in[`BM_SHARED_BV] & rb_hit_busies_r_lcl[`BM_SHARED_BV]);
// Decide when to receive an open bank based on knowing this bank machine is
// one entry from the head, and a passing_open_bank hits on the
// rb_hit_busies vector.
always @(idle_r_lcl
or passing_open_bank_in or q_entry_r
or rb_hit_busies_r_lcl) rcv_open_bank =
|(rb_hit_busies_r_lcl[`BM_SHARED_BV] & passing_open_bank_in[`BM_SHARED_BV])
&& (q_entry_r == BM_CNT_ONE) && ~idle_r_lcl;
end
endgenerate
output wire [nBANK_MACHS*2-1:0] rb_hit_busies_r;
assign rb_hit_busies_r = rb_hit_busies_r_lcl;
// Keep track if the queue this entry is in has priority content.
input was_wr;
input maint_req_r;
reg q_has_rd_r;
wire q_has_rd_ns = ~clear_req &&
(q_has_rd_r || (accept_req && rb_hit_busy_r && ~was_wr) ||
(maint_req_r && maint_hit && ~idle_r_lcl));
always @(posedge clk) q_has_rd_r <= #TCQ q_has_rd_ns;
output wire q_has_rd;
assign q_has_rd = q_has_rd_r;
input was_priority;
reg q_has_priority_r;
wire q_has_priority_ns = ~clear_req &&
(q_has_priority_r || (accept_req && rb_hit_busy_r && was_priority));
always @(posedge clk) q_has_priority_r <= #TCQ q_has_priority_ns;
output wire q_has_priority;
assign q_has_priority = q_has_priority_r;
// Figure out if this entry should wait for maintenance to end.
wire wait_for_maint_ns = ~rst && ~maint_idle &&
(wait_for_maint_r_lcl || (maint_hit && accept_this_bm));
always @(posedge clk) wait_for_maint_r_lcl <= #TCQ wait_for_maint_ns;
output wire wait_for_maint_r;
assign wait_for_maint_r = wait_for_maint_r_lcl;
endmodule // bank_queue
|
/*------------------------------------------------------------------------------
* This code was generated by Spiral Multiplier Block Generator, www.spiral.net
* Copyright (c) 2006, Carnegie Mellon University
* All rights reserved.
* The code is distributed under a BSD style license
* (see http://www.opensource.org/licenses/bsd-license.php)
*------------------------------------------------------------------------------ */
/* ./multBlockGen.pl 21608 -fractionalBits 0*/
module multiplier_block (
i_data0,
o_data0
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0]
o_data0;
//Multipliers:
wire [31:0]
w1,
w128,
w129,
w2064,
w2193,
w516,
w2709,
w8,
w2701,
w21608;
assign w1 = i_data0;
assign w128 = w1 << 7;
assign w129 = w1 + w128;
assign w2064 = w129 << 4;
assign w21608 = w2701 << 3;
assign w2193 = w129 + w2064;
assign w2701 = w2709 - w8;
assign w2709 = w2193 + w516;
assign w516 = w129 << 2;
assign w8 = w1 << 3;
assign o_data0 = w21608;
//multiplier_block area estimate = 6719.32805906029;
endmodule //multiplier_block
module surround_with_regs(
i_data0,
o_data0,
clk
);
// Port mode declarations:
input [31:0] i_data0;
output [31:0] o_data0;
reg [31:0] o_data0;
input clk;
reg [31:0] i_data0_reg;
wire [30:0] o_data0_from_mult;
always @(posedge clk) begin
i_data0_reg <= i_data0;
o_data0 <= o_data0_from_mult;
end
multiplier_block mult_blk(
.i_data0(i_data0_reg),
.o_data0(o_data0_from_mult)
);
endmodule
|
`timescale 1ps/1ps
module srio_gen2_0_srio_clk
(// Clock in ports
input sys_clkp,
input sys_clkn,
// Status and control signals
input sys_rst,
input mode_1x,
// Clock out ports
output log_clk,
output phy_clk,
output gt_pcs_clk,
output gt_clk,
output refclk,
output drpclk,
// Status and control signals
output clk_lock
);
//------------------------------------
// wire declarations
//------------------------------------
wire refclk_bufg;
wire clkout0;
wire clkout1;
wire clkout2;
wire clkout3;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire to_feedback_in;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
// End wire declarations
//------------------------------------
// // input buffering
//------------------------------------
IBUFDS_GTE2 u_refclk_ibufds(
.O (refclk),
.I (sys_clkp),
.IB (sys_clkn),
.CEB (1'b0),
.ODIV2 ()
);
BUFG refclk_bufg_inst
(.O (refclk_bufg),
.I (refclk));
// End input buffering
// MMCME2_ADV instantiation
//------------------------------------
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (6.500),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (6.500),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (26),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (13),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (6.400),
.REF_JITTER1 (0.010))
srio_mmcm_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (refclk_bufg),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (clk_lock),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (1'b0)
);
// End 7 series MMCM instantiation
//______________________________________________________________________________
// output buffering
//-----------------------------------
BUFG drpclk_bufr_inst
(.O (drpclk),
.I (clkout1));
BUFG gt_clk_bufg_inst
(.O (gt_clk),
.I (clkout0));
BUFG gt_pcs_clk_bufg_inst
(.O (gt_pcs_clk),
.I (clkout2));
BUFGMUX phy_clk_bufg_inst
(.O (phy_clk),
.I0(clkout2),
.I1(clkout1),
.S (mode_1x));
// Note that this bufg is a duplicate of the gt_pcs_clk bufg, and is not necessary if BUFG resources are limited.
BUFG log_clk_bufg_inst
(.O (log_clk),
.I (clkout2));
// End output buffering
//______________________________________________________________________________
endmodule
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